1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). These are set to -1
208 if they have not been initialized. Changed by `.set <asename>', by
209 command line options, and based on the default architecture. */
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
222 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
223 1 if we are, and -1 if the value has not been initialized. Changed
224 by `.set micromips' and `.set nomicromips', and the -mmicromips
225 and -mno-micromips command line options, and the default CPU. */
227 /* Non-zero if we should not reorder instructions. Changed by `.set
228 reorder' and `.set noreorder'. */
230 /* Non-zero if we should not permit the register designated "assembler
231 temporary" to be used in instructions. The value is the register
232 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
233 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
235 /* Non-zero if we should warn when a macro instruction expands into
236 more than one machine instruction. Changed by `.set nomacro' and
238 int warn_about_macros
;
239 /* Non-zero if we should not move instructions. Changed by `.set
240 move', `.set volatile', `.set nomove', and `.set novolatile'. */
242 /* Non-zero if we should not optimize branches by moving the target
243 of the branch into the delay slot. Actually, we don't perform
244 this optimization anyhow. Changed by `.set bopt' and `.set
247 /* Non-zero if we should not autoextend mips16 instructions.
248 Changed by `.set autoextend' and `.set noautoextend'. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bfd_boolean soft_float
;
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bfd_boolean single_float
;
271 /* This is the struct we use to hold the current set of options. Note
272 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
273 -1 to indicate that they have not been initialized. */
275 /* True if -mgp32 was passed. */
276 static int file_mips_gp32
= -1;
278 /* True if -mfp32 was passed. */
279 static int file_mips_fp32
= -1;
281 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
282 static int file_mips_soft_float
= 0;
284 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
285 static int file_mips_single_float
= 0;
287 static struct mips_set_options mips_opts
=
289 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
290 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
291 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
292 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
293 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
294 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* True if -mips3d was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_mips3d
;
333 /* True if -mdmx was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mdmx
;
337 /* True if -msmartmips was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_smartmips
;
341 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2)
344 /* True if -mdsp was passed or implied by arguments passed on the
345 command line (e.g., by -march). */
346 static int file_ase_dsp
;
348 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
349 || mips_opts.isa == ISA_MIPS64R2 \
350 || mips_opts.micromips)
352 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mdspr2 was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_dspr2
;
358 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2 \
360 || mips_opts.micromips)
362 /* True if -mmt was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_mt
;
366 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2)
369 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2 \
371 || mips_opts.micromips)
373 /* The argument of the -march= flag. The architecture we are assembling. */
374 static int file_mips_arch
= CPU_UNKNOWN
;
375 static const char *mips_arch_string
;
377 /* The argument of the -mtune= flag. The architecture for which we
379 static int mips_tune
= CPU_UNKNOWN
;
380 static const char *mips_tune_string
;
382 /* True when generating 32-bit code for a 64-bit processor. */
383 static int mips_32bitmode
= 0;
385 /* True if the given ABI requires 32-bit registers. */
386 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
388 /* Likewise 64-bit registers. */
389 #define ABI_NEEDS_64BIT_REGS(ABI) \
391 || (ABI) == N64_ABI \
394 /* Return true if ISA supports 64 bit wide gp registers. */
395 #define ISA_HAS_64BIT_REGS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS64 \
400 || (ISA) == ISA_MIPS64R2)
402 /* Return true if ISA supports 64 bit wide float registers. */
403 #define ISA_HAS_64BIT_FPRS(ISA) \
404 ((ISA) == ISA_MIPS3 \
405 || (ISA) == ISA_MIPS4 \
406 || (ISA) == ISA_MIPS5 \
407 || (ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64 \
409 || (ISA) == ISA_MIPS64R2)
411 /* Return true if ISA supports 64-bit right rotate (dror et al.)
413 #define ISA_HAS_DROR(ISA) \
414 ((ISA) == ISA_MIPS64R2 \
415 || (mips_opts.micromips \
416 && ISA_HAS_64BIT_REGS (ISA)) \
419 /* Return true if ISA supports 32-bit right rotate (ror et al.)
421 #define ISA_HAS_ROR(ISA) \
422 ((ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64R2 \
424 || mips_opts.ase_smartmips \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
430 ((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS64 \
433 || (ISA) == ISA_MIPS64R2)
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS64R2)
441 #define HAVE_32BIT_GPRS \
442 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
444 #define HAVE_32BIT_FPRS \
445 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
447 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
448 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
450 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
452 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
454 /* True if relocations are stored in-place. */
455 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
457 /* The ABI-derived address size. */
458 #define HAVE_64BIT_ADDRESSES \
459 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
460 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
462 /* The size of symbolic constants (i.e., expressions of the form
463 "SYMBOL" or "SYMBOL + OFFSET"). */
464 #define HAVE_32BIT_SYMBOLS \
465 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
466 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
468 /* Addresses are loaded in different ways, depending on the address size
469 in use. The n32 ABI Documentation also mandates the use of additions
470 with overflow checking, but existing implementations don't follow it. */
471 #define ADDRESS_ADD_INSN \
472 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
474 #define ADDRESS_ADDI_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
477 #define ADDRESS_LOAD_INSN \
478 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
480 #define ADDRESS_STORE_INSN \
481 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
483 /* Return true if the given CPU supports the MIPS16 ASE. */
484 #define CPU_HAS_MIPS16(cpu) \
485 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
486 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
488 /* Return true if the given CPU supports the microMIPS ASE. */
489 #define CPU_HAS_MICROMIPS(cpu) 0
491 /* True if CPU has a dror instruction. */
492 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
494 /* True if CPU has a ror instruction. */
495 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
497 /* True if CPU is in the Octeon family */
498 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
500 /* True if CPU has seq/sne and seqi/snei instructions. */
501 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
574 has been selected. This implies, in particular, that addresses of text
575 labels have their LSB set. */
576 #define HAVE_CODE_COMPRESSION \
577 ((mips_opts.mips16 | mips_opts.micromips) != 0)
579 /* MIPS PIC level. */
581 enum mips_pic_level mips_pic
;
583 /* 1 if we should generate 32 bit offsets from the $gp register in
584 SVR4_PIC mode. Currently has no meaning in other modes. */
585 static int mips_big_got
= 0;
587 /* 1 if trap instructions should used for overflow rather than break
589 static int mips_trap
= 0;
591 /* 1 if double width floating point constants should not be constructed
592 by assembling two single width halves into two single width floating
593 point registers which just happen to alias the double width destination
594 register. On some architectures this aliasing can be disabled by a bit
595 in the status register, and the setting of this bit cannot be determined
596 automatically at assemble time. */
597 static int mips_disable_float_construction
;
599 /* Non-zero if any .set noreorder directives were used. */
601 static int mips_any_noreorder
;
603 /* Non-zero if nops should be inserted when the register referenced in
604 an mfhi/mflo instruction is read in the next two instructions. */
605 static int mips_7000_hilo_fix
;
607 /* The size of objects in the small data section. */
608 static unsigned int g_switch_value
= 8;
609 /* Whether the -G option was used. */
610 static int g_switch_seen
= 0;
615 /* If we can determine in advance that GP optimization won't be
616 possible, we can skip the relaxation stuff that tries to produce
617 GP-relative references. This makes delay slot optimization work
620 This function can only provide a guess, but it seems to work for
621 gcc output. It needs to guess right for gcc, otherwise gcc
622 will put what it thinks is a GP-relative instruction in a branch
625 I don't know if a fix is needed for the SVR4_PIC mode. I've only
626 fixed it for the non-PIC mode. KR 95/04/07 */
627 static int nopic_need_relax (symbolS
*, int);
629 /* handle of the OPCODE hash table */
630 static struct hash_control
*op_hash
= NULL
;
632 /* The opcode hash table we use for the mips16. */
633 static struct hash_control
*mips16_op_hash
= NULL
;
635 /* The opcode hash table we use for the microMIPS ASE. */
636 static struct hash_control
*micromips_op_hash
= NULL
;
638 /* This array holds the chars that always start a comment. If the
639 pre-processor is disabled, these aren't very useful */
640 const char comment_chars
[] = "#";
642 /* This array holds the chars that only start a comment at the beginning of
643 a line. If the line seems to have the form '# 123 filename'
644 .line and .file directives will appear in the pre-processed output */
645 /* Note that input_file.c hand checks for '#' at the beginning of the
646 first line of the input file. This is because the compiler outputs
647 #NO_APP at the beginning of its output. */
648 /* Also note that C style comments are always supported. */
649 const char line_comment_chars
[] = "#";
651 /* This array holds machine specific line separator characters. */
652 const char line_separator_chars
[] = ";";
654 /* Chars that can be used to separate mant from exp in floating point nums */
655 const char EXP_CHARS
[] = "eE";
657 /* Chars that mean this number is a floating point constant */
660 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
662 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
663 changed in read.c . Ideally it shouldn't have to know about it at all,
664 but nothing is ideal around here.
667 static char *insn_error
;
669 static int auto_align
= 1;
671 /* When outputting SVR4 PIC code, the assembler needs to know the
672 offset in the stack frame from which to restore the $gp register.
673 This is set by the .cprestore pseudo-op, and saved in this
675 static offsetT mips_cprestore_offset
= -1;
677 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
678 more optimizations, it can use a register value instead of a memory-saved
679 offset and even an other register than $gp as global pointer. */
680 static offsetT mips_cpreturn_offset
= -1;
681 static int mips_cpreturn_register
= -1;
682 static int mips_gp_register
= GP
;
683 static int mips_gprel_offset
= 0;
685 /* Whether mips_cprestore_offset has been set in the current function
686 (or whether it has already been warned about, if not). */
687 static int mips_cprestore_valid
= 0;
689 /* This is the register which holds the stack frame, as set by the
690 .frame pseudo-op. This is needed to implement .cprestore. */
691 static int mips_frame_reg
= SP
;
693 /* Whether mips_frame_reg has been set in the current function
694 (or whether it has already been warned about, if not). */
695 static int mips_frame_reg_valid
= 0;
697 /* To output NOP instructions correctly, we need to keep information
698 about the previous two instructions. */
700 /* Whether we are optimizing. The default value of 2 means to remove
701 unneeded NOPs and swap branch instructions when possible. A value
702 of 1 means to not swap branches. A value of 0 means to always
704 static int mips_optimize
= 2;
706 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
707 equivalent to seeing no -g option at all. */
708 static int mips_debug
= 0;
710 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
711 #define MAX_VR4130_NOPS 4
713 /* The maximum number of NOPs needed to fill delay slots. */
714 #define MAX_DELAY_NOPS 2
716 /* The maximum number of NOPs needed for any purpose. */
719 /* A list of previous instructions, with index 0 being the most recent.
720 We need to look back MAX_NOPS instructions when filling delay slots
721 or working around processor errata. We need to look back one
722 instruction further if we're thinking about using history[0] to
723 fill a branch delay slot. */
724 static struct mips_cl_insn history
[1 + MAX_NOPS
];
726 /* Nop instructions used by emit_nop. */
727 static struct mips_cl_insn nop_insn
;
728 static struct mips_cl_insn mips16_nop_insn
;
729 static struct mips_cl_insn micromips_nop16_insn
;
730 static struct mips_cl_insn micromips_nop32_insn
;
732 /* The appropriate nop for the current mode. */
733 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
734 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
736 /* The size of NOP_INSN in bytes. */
737 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
739 /* If this is set, it points to a frag holding nop instructions which
740 were inserted before the start of a noreorder section. If those
741 nops turn out to be unnecessary, the size of the frag can be
743 static fragS
*prev_nop_frag
;
745 /* The number of nop instructions we created in prev_nop_frag. */
746 static int prev_nop_frag_holds
;
748 /* The number of nop instructions that we know we need in
750 static int prev_nop_frag_required
;
752 /* The number of instructions we've seen since prev_nop_frag. */
753 static int prev_nop_frag_since
;
755 /* For ECOFF and ELF, relocations against symbols are done in two
756 parts, with a HI relocation and a LO relocation. Each relocation
757 has only 16 bits of space to store an addend. This means that in
758 order for the linker to handle carries correctly, it must be able
759 to locate both the HI and the LO relocation. This means that the
760 relocations must appear in order in the relocation table.
762 In order to implement this, we keep track of each unmatched HI
763 relocation. We then sort them so that they immediately precede the
764 corresponding LO relocation. */
769 struct mips_hi_fixup
*next
;
772 /* The section this fixup is in. */
776 /* The list of unmatched HI relocs. */
778 static struct mips_hi_fixup
*mips_hi_fixup_list
;
780 /* The frag containing the last explicit relocation operator.
781 Null if explicit relocations have not been used. */
783 static fragS
*prev_reloc_op_frag
;
785 /* Map normal MIPS register numbers to mips16 register numbers. */
787 #define X ILLEGAL_REG
788 static const int mips32_to_16_reg_map
[] =
790 X
, X
, 2, 3, 4, 5, 6, 7,
791 X
, X
, X
, X
, X
, X
, X
, X
,
792 0, 1, X
, X
, X
, X
, X
, X
,
793 X
, X
, X
, X
, X
, X
, X
, X
797 /* Map mips16 register numbers to normal MIPS register numbers. */
799 static const unsigned int mips16_to_32_reg_map
[] =
801 16, 17, 2, 3, 4, 5, 6, 7
804 /* Map normal MIPS register numbers to microMIPS register numbers. */
806 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
811 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
814 #define X ILLEGAL_REG
815 /* reg type h: 4, 5, 6. */
816 static const int mips32_to_micromips_reg_h_map
[] =
818 X
, X
, X
, X
, 4, 5, 6, X
,
819 X
, X
, X
, X
, X
, X
, X
, X
,
820 X
, X
, X
, X
, X
, X
, X
, X
,
821 X
, X
, X
, X
, X
, X
, X
, X
824 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
825 static const int mips32_to_micromips_reg_m_map
[] =
827 0, X
, 2, 3, X
, X
, X
, X
,
828 X
, X
, X
, X
, X
, X
, X
, X
,
829 4, 1, 5, 6, 7, X
, X
, X
,
830 X
, X
, X
, X
, X
, X
, X
, X
833 /* reg type q: 0, 2-7. 17. */
834 static const int mips32_to_micromips_reg_q_map
[] =
836 0, X
, 2, 3, 4, 5, 6, 7,
837 X
, X
, X
, X
, X
, X
, X
, X
,
838 X
, 1, X
, X
, X
, X
, X
, X
,
839 X
, X
, X
, X
, X
, X
, X
, X
842 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
845 /* Map microMIPS register numbers to normal MIPS register numbers. */
847 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
851 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
852 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
854 /* The microMIPS registers with type h. */
855 static const unsigned int micromips_to_32_reg_h_map
[] =
857 5, 5, 6, 4, 4, 4, 4, 4
860 /* The microMIPS registers with type i. */
861 static const unsigned int micromips_to_32_reg_i_map
[] =
863 6, 7, 7, 21, 22, 5, 6, 7
866 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
868 /* The microMIPS registers with type m. */
869 static const unsigned int micromips_to_32_reg_m_map
[] =
871 0, 17, 2, 3, 16, 18, 19, 20
874 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
876 /* The microMIPS registers with type q. */
877 static const unsigned int micromips_to_32_reg_q_map
[] =
879 0, 17, 2, 3, 4, 5, 6, 7
882 /* microMIPS imm type B. */
883 static const int micromips_imm_b_map
[] =
885 1, 4, 8, 12, 16, 20, 24, -1
888 /* microMIPS imm type C. */
889 static const int micromips_imm_c_map
[] =
891 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
894 /* Classifies the kind of instructions we're interested in when
895 implementing -mfix-vr4120. */
896 enum fix_vr4120_class
904 NUM_FIX_VR4120_CLASSES
907 /* ...likewise -mfix-loongson2f-jump. */
908 static bfd_boolean mips_fix_loongson2f_jump
;
910 /* ...likewise -mfix-loongson2f-nop. */
911 static bfd_boolean mips_fix_loongson2f_nop
;
913 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
914 static bfd_boolean mips_fix_loongson2f
;
916 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
917 there must be at least one other instruction between an instruction
918 of type X and an instruction of type Y. */
919 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
921 /* True if -mfix-vr4120 is in force. */
922 static int mips_fix_vr4120
;
924 /* ...likewise -mfix-vr4130. */
925 static int mips_fix_vr4130
;
927 /* ...likewise -mfix-24k. */
928 static int mips_fix_24k
;
930 /* ...likewise -mfix-cn63xxp1 */
931 static bfd_boolean mips_fix_cn63xxp1
;
933 /* We don't relax branches by default, since this causes us to expand
934 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
935 fail to compute the offset before expanding the macro to the most
936 efficient expansion. */
938 static int mips_relax_branch
;
940 /* The expansion of many macros depends on the type of symbol that
941 they refer to. For example, when generating position-dependent code,
942 a macro that refers to a symbol may have two different expansions,
943 one which uses GP-relative addresses and one which uses absolute
944 addresses. When generating SVR4-style PIC, a macro may have
945 different expansions for local and global symbols.
947 We handle these situations by generating both sequences and putting
948 them in variant frags. In position-dependent code, the first sequence
949 will be the GP-relative one and the second sequence will be the
950 absolute one. In SVR4 PIC, the first sequence will be for global
951 symbols and the second will be for local symbols.
953 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
954 SECOND are the lengths of the two sequences in bytes. These fields
955 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
956 the subtype has the following flags:
959 Set if it has been decided that we should use the second
960 sequence instead of the first.
963 Set in the first variant frag if the macro's second implementation
964 is longer than its first. This refers to the macro as a whole,
965 not an individual relaxation.
968 Set in the first variant frag if the macro appeared in a .set nomacro
969 block and if one alternative requires a warning but the other does not.
972 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
975 RELAX_DELAY_SLOT_16BIT
976 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
979 RELAX_DELAY_SLOT_SIZE_FIRST
980 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
981 the macro is of the wrong size for the branch delay slot.
983 RELAX_DELAY_SLOT_SIZE_SECOND
984 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
985 the macro is of the wrong size for the branch delay slot.
987 The frag's "opcode" points to the first fixup for relaxable code.
989 Relaxable macros are generated using a sequence such as:
991 relax_start (SYMBOL);
992 ... generate first expansion ...
994 ... generate second expansion ...
997 The code and fixups for the unwanted alternative are discarded
998 by md_convert_frag. */
999 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1001 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1002 #define RELAX_SECOND(X) ((X) & 0xff)
1003 #define RELAX_USE_SECOND 0x10000
1004 #define RELAX_SECOND_LONGER 0x20000
1005 #define RELAX_NOMACRO 0x40000
1006 #define RELAX_DELAY_SLOT 0x80000
1007 #define RELAX_DELAY_SLOT_16BIT 0x100000
1008 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1009 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1011 /* Branch without likely bit. If label is out of range, we turn:
1013 beq reg1, reg2, label
1023 with the following opcode replacements:
1030 bltzal <-> bgezal (with jal label instead of j label)
1032 Even though keeping the delay slot instruction in the delay slot of
1033 the branch would be more efficient, it would be very tricky to do
1034 correctly, because we'd have to introduce a variable frag *after*
1035 the delay slot instruction, and expand that instead. Let's do it
1036 the easy way for now, even if the branch-not-taken case now costs
1037 one additional instruction. Out-of-range branches are not supposed
1038 to be common, anyway.
1040 Branch likely. If label is out of range, we turn:
1042 beql reg1, reg2, label
1043 delay slot (annulled if branch not taken)
1052 delay slot (executed only if branch taken)
1055 It would be possible to generate a shorter sequence by losing the
1056 likely bit, generating something like:
1061 delay slot (executed only if branch taken)
1073 bltzall -> bgezal (with jal label instead of j label)
1074 bgezall -> bltzal (ditto)
1077 but it's not clear that it would actually improve performance. */
1078 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1079 ((relax_substateT) \
1082 | ((toofar) ? 0x20 : 0) \
1083 | ((link) ? 0x40 : 0) \
1084 | ((likely) ? 0x80 : 0) \
1085 | ((uncond) ? 0x100 : 0)))
1086 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1087 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1088 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1089 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1090 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1091 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1093 /* For mips16 code, we use an entirely different form of relaxation.
1094 mips16 supports two versions of most instructions which take
1095 immediate values: a small one which takes some small value, and a
1096 larger one which takes a 16 bit value. Since branches also follow
1097 this pattern, relaxing these values is required.
1099 We can assemble both mips16 and normal MIPS code in a single
1100 object. Therefore, we need to support this type of relaxation at
1101 the same time that we support the relaxation described above. We
1102 use the high bit of the subtype field to distinguish these cases.
1104 The information we store for this type of relaxation is the
1105 argument code found in the opcode file for this relocation, whether
1106 the user explicitly requested a small or extended form, and whether
1107 the relocation is in a jump or jal delay slot. That tells us the
1108 size of the value, and how it should be stored. We also store
1109 whether the fragment is considered to be extended or not. We also
1110 store whether this is known to be a branch to a different section,
1111 whether we have tried to relax this frag yet, and whether we have
1112 ever extended a PC relative fragment because of a shift count. */
1113 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1116 | ((small) ? 0x100 : 0) \
1117 | ((ext) ? 0x200 : 0) \
1118 | ((dslot) ? 0x400 : 0) \
1119 | ((jal_dslot) ? 0x800 : 0))
1120 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1121 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1123 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1124 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1125 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1126 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1127 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1128 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1129 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1130 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1131 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1133 /* For microMIPS code, we use relaxation similar to one we use for
1134 MIPS16 code. Some instructions that take immediate values support
1135 two encodings: a small one which takes some small value, and a
1136 larger one which takes a 16 bit value. As some branches also follow
1137 this pattern, relaxing these values is required.
1139 We can assemble both microMIPS and normal MIPS code in a single
1140 object. Therefore, we need to support this type of relaxation at
1141 the same time that we support the relaxation described above. We
1142 use one of the high bits of the subtype field to distinguish these
1145 The information we store for this type of relaxation is the argument
1146 code found in the opcode file for this relocation, the register
1147 selected as the assembler temporary, whether the branch is
1148 unconditional, whether it is compact, whether it stores the link
1149 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1150 branches to a sequence of instructions is enabled, and whether the
1151 displacement of a branch is too large to fit as an immediate argument
1152 of a 16-bit and a 32-bit branch, respectively. */
1153 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1154 relax32, toofar16, toofar32) \
1157 | (((at) & 0x1f) << 8) \
1158 | ((uncond) ? 0x2000 : 0) \
1159 | ((compact) ? 0x4000 : 0) \
1160 | ((link) ? 0x8000 : 0) \
1161 | ((relax32) ? 0x10000 : 0) \
1162 | ((toofar16) ? 0x20000 : 0) \
1163 | ((toofar32) ? 0x40000 : 0))
1164 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1165 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1166 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1167 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1168 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1169 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1170 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1172 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1173 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1174 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1175 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1176 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1177 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1179 /* Is the given value a sign-extended 32-bit value? */
1180 #define IS_SEXT_32BIT_NUM(x) \
1181 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1182 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1184 /* Is the given value a sign-extended 16-bit value? */
1185 #define IS_SEXT_16BIT_NUM(x) \
1186 (((x) &~ (offsetT) 0x7fff) == 0 \
1187 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1189 /* Is the given value a sign-extended 12-bit value? */
1190 #define IS_SEXT_12BIT_NUM(x) \
1191 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1193 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1194 #define IS_ZEXT_32BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0xffffffff) == 0 \
1196 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1198 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1199 VALUE << SHIFT. VALUE is evaluated exactly once. */
1200 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1201 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1202 | (((VALUE) & (MASK)) << (SHIFT)))
1204 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1206 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1207 (((STRUCT) >> (SHIFT)) & (MASK))
1209 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1210 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1212 include/opcode/mips.h specifies operand fields using the macros
1213 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1214 with "MIPS16OP" instead of "OP". */
1215 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1218 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1219 OP_MASK_##FIELD, OP_SH_##FIELD); \
1221 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1222 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1224 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1225 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1226 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1228 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1229 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1231 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1232 : EXTRACT_BITS ((INSN).insn_opcode, \
1233 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1234 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1235 EXTRACT_BITS ((INSN).insn_opcode, \
1236 MIPS16OP_MASK_##FIELD, \
1237 MIPS16OP_SH_##FIELD)
1239 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1240 #define MIPS16_EXTEND (0xf000U << 16)
1242 /* Whether or not we are emitting a branch-likely macro. */
1243 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1245 /* Global variables used when generating relaxable macros. See the
1246 comment above RELAX_ENCODE for more details about how relaxation
1249 /* 0 if we're not emitting a relaxable macro.
1250 1 if we're emitting the first of the two relaxation alternatives.
1251 2 if we're emitting the second alternative. */
1254 /* The first relaxable fixup in the current frag. (In other words,
1255 the first fixup that refers to relaxable code.) */
1258 /* sizes[0] says how many bytes of the first alternative are stored in
1259 the current frag. Likewise sizes[1] for the second alternative. */
1260 unsigned int sizes
[2];
1262 /* The symbol on which the choice of sequence depends. */
1266 /* Global variables used to decide whether a macro needs a warning. */
1268 /* True if the macro is in a branch delay slot. */
1269 bfd_boolean delay_slot_p
;
1271 /* Set to the length in bytes required if the macro is in a delay slot
1272 that requires a specific length of instruction, otherwise zero. */
1273 unsigned int delay_slot_length
;
1275 /* For relaxable macros, sizes[0] is the length of the first alternative
1276 in bytes and sizes[1] is the length of the second alternative.
1277 For non-relaxable macros, both elements give the length of the
1279 unsigned int sizes
[2];
1281 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1282 instruction of the first alternative in bytes and first_insn_sizes[1]
1283 is the length of the first instruction of the second alternative.
1284 For non-relaxable macros, both elements give the length of the first
1285 instruction in bytes.
1287 Set to zero if we haven't yet seen the first instruction. */
1288 unsigned int first_insn_sizes
[2];
1290 /* For relaxable macros, insns[0] is the number of instructions for the
1291 first alternative and insns[1] is the number of instructions for the
1294 For non-relaxable macros, both elements give the number of
1295 instructions for the macro. */
1296 unsigned int insns
[2];
1298 /* The first variant frag for this macro. */
1300 } mips_macro_warning
;
1302 /* Prototypes for static functions. */
1304 #define internalError() \
1305 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1307 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1309 static void append_insn
1310 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1311 bfd_boolean expansionp
);
1312 static void mips_no_prev_insn (void);
1313 static void macro_build (expressionS
*, const char *, const char *, ...);
1314 static void mips16_macro_build
1315 (expressionS
*, const char *, const char *, va_list *);
1316 static void load_register (int, expressionS
*, int);
1317 static void macro_start (void);
1318 static void macro_end (void);
1319 static void macro (struct mips_cl_insn
* ip
);
1320 static void mips16_macro (struct mips_cl_insn
* ip
);
1321 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1322 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1323 static void mips16_immed
1324 (char *, unsigned int, int, offsetT
, unsigned int, unsigned long *);
1325 static size_t my_getSmallExpression
1326 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1327 static void my_getExpression (expressionS
*, char *);
1328 static void s_align (int);
1329 static void s_change_sec (int);
1330 static void s_change_section (int);
1331 static void s_cons (int);
1332 static void s_float_cons (int);
1333 static void s_mips_globl (int);
1334 static void s_option (int);
1335 static void s_mipsset (int);
1336 static void s_abicalls (int);
1337 static void s_cpload (int);
1338 static void s_cpsetup (int);
1339 static void s_cplocal (int);
1340 static void s_cprestore (int);
1341 static void s_cpreturn (int);
1342 static void s_dtprelword (int);
1343 static void s_dtpreldword (int);
1344 static void s_tprelword (int);
1345 static void s_tpreldword (int);
1346 static void s_gpvalue (int);
1347 static void s_gpword (int);
1348 static void s_gpdword (int);
1349 static void s_cpadd (int);
1350 static void s_insn (int);
1351 static void md_obj_begin (void);
1352 static void md_obj_end (void);
1353 static void s_mips_ent (int);
1354 static void s_mips_end (int);
1355 static void s_mips_frame (int);
1356 static void s_mips_mask (int reg_type
);
1357 static void s_mips_stab (int);
1358 static void s_mips_weakext (int);
1359 static void s_mips_file (int);
1360 static void s_mips_loc (int);
1361 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1362 static int relaxed_branch_length (fragS
*, asection
*, int);
1363 static int validate_mips_insn (const struct mips_opcode
*);
1364 static int validate_micromips_insn (const struct mips_opcode
*);
1365 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1366 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1368 /* Table and functions used to map between CPU/ISA names, and
1369 ISA levels, and CPU numbers. */
1371 struct mips_cpu_info
1373 const char *name
; /* CPU or ISA name. */
1374 int flags
; /* ASEs available, or ISA flag. */
1375 int isa
; /* ISA level. */
1376 int cpu
; /* CPU number (default CPU if ISA). */
1379 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1380 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1381 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1382 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1383 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1384 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1385 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1386 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1388 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1389 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1390 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1394 The following pseudo-ops from the Kane and Heinrich MIPS book
1395 should be defined here, but are currently unsupported: .alias,
1396 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1398 The following pseudo-ops from the Kane and Heinrich MIPS book are
1399 specific to the type of debugging information being generated, and
1400 should be defined by the object format: .aent, .begin, .bend,
1401 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1404 The following pseudo-ops from the Kane and Heinrich MIPS book are
1405 not MIPS CPU specific, but are also not specific to the object file
1406 format. This file is probably the best place to define them, but
1407 they are not currently supported: .asm0, .endr, .lab, .struct. */
1409 static const pseudo_typeS mips_pseudo_table
[] =
1411 /* MIPS specific pseudo-ops. */
1412 {"option", s_option
, 0},
1413 {"set", s_mipsset
, 0},
1414 {"rdata", s_change_sec
, 'r'},
1415 {"sdata", s_change_sec
, 's'},
1416 {"livereg", s_ignore
, 0},
1417 {"abicalls", s_abicalls
, 0},
1418 {"cpload", s_cpload
, 0},
1419 {"cpsetup", s_cpsetup
, 0},
1420 {"cplocal", s_cplocal
, 0},
1421 {"cprestore", s_cprestore
, 0},
1422 {"cpreturn", s_cpreturn
, 0},
1423 {"dtprelword", s_dtprelword
, 0},
1424 {"dtpreldword", s_dtpreldword
, 0},
1425 {"tprelword", s_tprelword
, 0},
1426 {"tpreldword", s_tpreldword
, 0},
1427 {"gpvalue", s_gpvalue
, 0},
1428 {"gpword", s_gpword
, 0},
1429 {"gpdword", s_gpdword
, 0},
1430 {"cpadd", s_cpadd
, 0},
1431 {"insn", s_insn
, 0},
1433 /* Relatively generic pseudo-ops that happen to be used on MIPS
1435 {"asciiz", stringer
, 8 + 1},
1436 {"bss", s_change_sec
, 'b'},
1438 {"half", s_cons
, 1},
1439 {"dword", s_cons
, 3},
1440 {"weakext", s_mips_weakext
, 0},
1441 {"origin", s_org
, 0},
1442 {"repeat", s_rept
, 0},
1444 /* For MIPS this is non-standard, but we define it for consistency. */
1445 {"sbss", s_change_sec
, 'B'},
1447 /* These pseudo-ops are defined in read.c, but must be overridden
1448 here for one reason or another. */
1449 {"align", s_align
, 0},
1450 {"byte", s_cons
, 0},
1451 {"data", s_change_sec
, 'd'},
1452 {"double", s_float_cons
, 'd'},
1453 {"float", s_float_cons
, 'f'},
1454 {"globl", s_mips_globl
, 0},
1455 {"global", s_mips_globl
, 0},
1456 {"hword", s_cons
, 1},
1458 {"long", s_cons
, 2},
1459 {"octa", s_cons
, 4},
1460 {"quad", s_cons
, 3},
1461 {"section", s_change_section
, 0},
1462 {"short", s_cons
, 1},
1463 {"single", s_float_cons
, 'f'},
1464 {"stabn", s_mips_stab
, 'n'},
1465 {"text", s_change_sec
, 't'},
1466 {"word", s_cons
, 2},
1468 { "extern", ecoff_directive_extern
, 0},
1473 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1475 /* These pseudo-ops should be defined by the object file format.
1476 However, a.out doesn't support them, so we have versions here. */
1477 {"aent", s_mips_ent
, 1},
1478 {"bgnb", s_ignore
, 0},
1479 {"end", s_mips_end
, 0},
1480 {"endb", s_ignore
, 0},
1481 {"ent", s_mips_ent
, 0},
1482 {"file", s_mips_file
, 0},
1483 {"fmask", s_mips_mask
, 'F'},
1484 {"frame", s_mips_frame
, 0},
1485 {"loc", s_mips_loc
, 0},
1486 {"mask", s_mips_mask
, 'R'},
1487 {"verstamp", s_ignore
, 0},
1491 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1492 purpose of the `.dc.a' internal pseudo-op. */
1495 mips_address_bytes (void)
1497 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1500 extern void pop_insert (const pseudo_typeS
*);
1503 mips_pop_insert (void)
1505 pop_insert (mips_pseudo_table
);
1506 if (! ECOFF_DEBUGGING
)
1507 pop_insert (mips_nonecoff_pseudo_table
);
1510 /* Symbols labelling the current insn. */
1512 struct insn_label_list
1514 struct insn_label_list
*next
;
1518 static struct insn_label_list
*free_insn_labels
;
1519 #define label_list tc_segment_info_data.labels
1521 static void mips_clear_insn_labels (void);
1522 static void mips_mark_labels (void);
1523 static void mips_compressed_mark_labels (void);
1526 mips_clear_insn_labels (void)
1528 register struct insn_label_list
**pl
;
1529 segment_info_type
*si
;
1533 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1536 si
= seg_info (now_seg
);
1537 *pl
= si
->label_list
;
1538 si
->label_list
= NULL
;
1542 /* Mark instruction labels in MIPS16/microMIPS mode. */
1545 mips_mark_labels (void)
1547 if (HAVE_CODE_COMPRESSION
)
1548 mips_compressed_mark_labels ();
1551 static char *expr_end
;
1553 /* Expressions which appear in instructions. These are set by
1556 static expressionS imm_expr
;
1557 static expressionS imm2_expr
;
1558 static expressionS offset_expr
;
1560 /* Relocs associated with imm_expr and offset_expr. */
1562 static bfd_reloc_code_real_type imm_reloc
[3]
1563 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1564 static bfd_reloc_code_real_type offset_reloc
[3]
1565 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1567 /* This is set to the resulting size of the instruction to be produced
1568 by mips16_ip if an explicit extension is used or by mips_ip if an
1569 explicit size is supplied. */
1571 static unsigned int forced_insn_length
;
1574 /* The pdr segment for per procedure frame/regmask info. Not used for
1577 static segT pdr_seg
;
1580 /* The default target format to use. */
1582 #if defined (TE_FreeBSD)
1583 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1584 #elif defined (TE_TMIPS)
1585 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1587 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1591 mips_target_format (void)
1593 switch (OUTPUT_FLAVOR
)
1595 case bfd_target_ecoff_flavour
:
1596 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1597 case bfd_target_coff_flavour
:
1599 case bfd_target_elf_flavour
:
1601 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1602 return (target_big_endian
1603 ? "elf32-bigmips-vxworks"
1604 : "elf32-littlemips-vxworks");
1606 return (target_big_endian
1607 ? (HAVE_64BIT_OBJECTS
1608 ? ELF_TARGET ("elf64-", "big")
1610 ? ELF_TARGET ("elf32-n", "big")
1611 : ELF_TARGET ("elf32-", "big")))
1612 : (HAVE_64BIT_OBJECTS
1613 ? ELF_TARGET ("elf64-", "little")
1615 ? ELF_TARGET ("elf32-n", "little")
1616 : ELF_TARGET ("elf32-", "little"))));
1623 /* Return the length of a microMIPS instruction in bytes. If bits of
1624 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1625 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1626 major opcode) will require further modifications to the opcode
1629 static inline unsigned int
1630 micromips_insn_length (const struct mips_opcode
*mo
)
1632 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1635 /* Return the length of MIPS16 instruction OPCODE. */
1637 static inline unsigned int
1638 mips16_opcode_length (unsigned long opcode
)
1640 return (opcode
>> 16) == 0 ? 2 : 4;
1643 /* Return the length of instruction INSN. */
1645 static inline unsigned int
1646 insn_length (const struct mips_cl_insn
*insn
)
1648 if (mips_opts
.micromips
)
1649 return micromips_insn_length (insn
->insn_mo
);
1650 else if (mips_opts
.mips16
)
1651 return mips16_opcode_length (insn
->insn_opcode
);
1656 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1659 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1664 insn
->insn_opcode
= mo
->match
;
1667 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1668 insn
->fixp
[i
] = NULL
;
1669 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1670 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1671 insn
->mips16_absolute_jump_p
= 0;
1672 insn
->complete_p
= 0;
1675 /* Record the current MIPS16/microMIPS mode in now_seg. */
1678 mips_record_compressed_mode (void)
1680 segment_info_type
*si
;
1682 si
= seg_info (now_seg
);
1683 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1684 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1685 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1686 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1689 /* Read a standard MIPS instruction from BUF. */
1691 static unsigned long
1692 read_insn (char *buf
)
1694 if (target_big_endian
)
1695 return bfd_getb32 ((bfd_byte
*) buf
);
1697 return bfd_getl32 ((bfd_byte
*) buf
);
1700 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1704 write_insn (char *buf
, unsigned int insn
)
1706 md_number_to_chars (buf
, insn
, 4);
1710 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1711 has length LENGTH. */
1713 static unsigned long
1714 read_compressed_insn (char *buf
, unsigned int length
)
1720 for (i
= 0; i
< length
; i
+= 2)
1723 if (target_big_endian
)
1724 insn
|= bfd_getb16 ((char *) buf
);
1726 insn
|= bfd_getl16 ((char *) buf
);
1732 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1733 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1736 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1740 for (i
= 0; i
< length
; i
+= 2)
1741 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1742 return buf
+ length
;
1745 /* Install INSN at the location specified by its "frag" and "where" fields. */
1748 install_insn (const struct mips_cl_insn
*insn
)
1750 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1751 if (HAVE_CODE_COMPRESSION
)
1752 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1754 write_insn (f
, insn
->insn_opcode
);
1755 mips_record_compressed_mode ();
1758 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1759 and install the opcode in the new location. */
1762 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1767 insn
->where
= where
;
1768 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1769 if (insn
->fixp
[i
] != NULL
)
1771 insn
->fixp
[i
]->fx_frag
= frag
;
1772 insn
->fixp
[i
]->fx_where
= where
;
1774 install_insn (insn
);
1777 /* Add INSN to the end of the output. */
1780 add_fixed_insn (struct mips_cl_insn
*insn
)
1782 char *f
= frag_more (insn_length (insn
));
1783 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1786 /* Start a variant frag and move INSN to the start of the variant part,
1787 marking it as fixed. The other arguments are as for frag_var. */
1790 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1791 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1793 frag_grow (max_chars
);
1794 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1796 frag_var (rs_machine_dependent
, max_chars
, var
,
1797 subtype
, symbol
, offset
, NULL
);
1800 /* Insert N copies of INSN into the history buffer, starting at
1801 position FIRST. Neither FIRST nor N need to be clipped. */
1804 insert_into_history (unsigned int first
, unsigned int n
,
1805 const struct mips_cl_insn
*insn
)
1807 if (mips_relax
.sequence
!= 2)
1811 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1813 history
[i
] = history
[i
- n
];
1819 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1820 the idea is to make it obvious at a glance that each errata is
1824 init_vr4120_conflicts (void)
1826 #define CONFLICT(FIRST, SECOND) \
1827 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1829 /* Errata 21 - [D]DIV[U] after [D]MACC */
1830 CONFLICT (MACC
, DIV
);
1831 CONFLICT (DMACC
, DIV
);
1833 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1834 CONFLICT (DMULT
, DMULT
);
1835 CONFLICT (DMULT
, DMACC
);
1836 CONFLICT (DMACC
, DMULT
);
1837 CONFLICT (DMACC
, DMACC
);
1839 /* Errata 24 - MT{LO,HI} after [D]MACC */
1840 CONFLICT (MACC
, MTHILO
);
1841 CONFLICT (DMACC
, MTHILO
);
1843 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1844 instruction is executed immediately after a MACC or DMACC
1845 instruction, the result of [either instruction] is incorrect." */
1846 CONFLICT (MACC
, MULT
);
1847 CONFLICT (MACC
, DMULT
);
1848 CONFLICT (DMACC
, MULT
);
1849 CONFLICT (DMACC
, DMULT
);
1851 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1852 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1853 DDIV or DDIVU instruction, the result of the MACC or
1854 DMACC instruction is incorrect.". */
1855 CONFLICT (DMULT
, MACC
);
1856 CONFLICT (DMULT
, DMACC
);
1857 CONFLICT (DIV
, MACC
);
1858 CONFLICT (DIV
, DMACC
);
1868 #define RTYPE_MASK 0x1ff00
1869 #define RTYPE_NUM 0x00100
1870 #define RTYPE_FPU 0x00200
1871 #define RTYPE_FCC 0x00400
1872 #define RTYPE_VEC 0x00800
1873 #define RTYPE_GP 0x01000
1874 #define RTYPE_CP0 0x02000
1875 #define RTYPE_PC 0x04000
1876 #define RTYPE_ACC 0x08000
1877 #define RTYPE_CCC 0x10000
1878 #define RNUM_MASK 0x000ff
1879 #define RWARN 0x80000
1881 #define GENERIC_REGISTER_NUMBERS \
1882 {"$0", RTYPE_NUM | 0}, \
1883 {"$1", RTYPE_NUM | 1}, \
1884 {"$2", RTYPE_NUM | 2}, \
1885 {"$3", RTYPE_NUM | 3}, \
1886 {"$4", RTYPE_NUM | 4}, \
1887 {"$5", RTYPE_NUM | 5}, \
1888 {"$6", RTYPE_NUM | 6}, \
1889 {"$7", RTYPE_NUM | 7}, \
1890 {"$8", RTYPE_NUM | 8}, \
1891 {"$9", RTYPE_NUM | 9}, \
1892 {"$10", RTYPE_NUM | 10}, \
1893 {"$11", RTYPE_NUM | 11}, \
1894 {"$12", RTYPE_NUM | 12}, \
1895 {"$13", RTYPE_NUM | 13}, \
1896 {"$14", RTYPE_NUM | 14}, \
1897 {"$15", RTYPE_NUM | 15}, \
1898 {"$16", RTYPE_NUM | 16}, \
1899 {"$17", RTYPE_NUM | 17}, \
1900 {"$18", RTYPE_NUM | 18}, \
1901 {"$19", RTYPE_NUM | 19}, \
1902 {"$20", RTYPE_NUM | 20}, \
1903 {"$21", RTYPE_NUM | 21}, \
1904 {"$22", RTYPE_NUM | 22}, \
1905 {"$23", RTYPE_NUM | 23}, \
1906 {"$24", RTYPE_NUM | 24}, \
1907 {"$25", RTYPE_NUM | 25}, \
1908 {"$26", RTYPE_NUM | 26}, \
1909 {"$27", RTYPE_NUM | 27}, \
1910 {"$28", RTYPE_NUM | 28}, \
1911 {"$29", RTYPE_NUM | 29}, \
1912 {"$30", RTYPE_NUM | 30}, \
1913 {"$31", RTYPE_NUM | 31}
1915 #define FPU_REGISTER_NAMES \
1916 {"$f0", RTYPE_FPU | 0}, \
1917 {"$f1", RTYPE_FPU | 1}, \
1918 {"$f2", RTYPE_FPU | 2}, \
1919 {"$f3", RTYPE_FPU | 3}, \
1920 {"$f4", RTYPE_FPU | 4}, \
1921 {"$f5", RTYPE_FPU | 5}, \
1922 {"$f6", RTYPE_FPU | 6}, \
1923 {"$f7", RTYPE_FPU | 7}, \
1924 {"$f8", RTYPE_FPU | 8}, \
1925 {"$f9", RTYPE_FPU | 9}, \
1926 {"$f10", RTYPE_FPU | 10}, \
1927 {"$f11", RTYPE_FPU | 11}, \
1928 {"$f12", RTYPE_FPU | 12}, \
1929 {"$f13", RTYPE_FPU | 13}, \
1930 {"$f14", RTYPE_FPU | 14}, \
1931 {"$f15", RTYPE_FPU | 15}, \
1932 {"$f16", RTYPE_FPU | 16}, \
1933 {"$f17", RTYPE_FPU | 17}, \
1934 {"$f18", RTYPE_FPU | 18}, \
1935 {"$f19", RTYPE_FPU | 19}, \
1936 {"$f20", RTYPE_FPU | 20}, \
1937 {"$f21", RTYPE_FPU | 21}, \
1938 {"$f22", RTYPE_FPU | 22}, \
1939 {"$f23", RTYPE_FPU | 23}, \
1940 {"$f24", RTYPE_FPU | 24}, \
1941 {"$f25", RTYPE_FPU | 25}, \
1942 {"$f26", RTYPE_FPU | 26}, \
1943 {"$f27", RTYPE_FPU | 27}, \
1944 {"$f28", RTYPE_FPU | 28}, \
1945 {"$f29", RTYPE_FPU | 29}, \
1946 {"$f30", RTYPE_FPU | 30}, \
1947 {"$f31", RTYPE_FPU | 31}
1949 #define FPU_CONDITION_CODE_NAMES \
1950 {"$fcc0", RTYPE_FCC | 0}, \
1951 {"$fcc1", RTYPE_FCC | 1}, \
1952 {"$fcc2", RTYPE_FCC | 2}, \
1953 {"$fcc3", RTYPE_FCC | 3}, \
1954 {"$fcc4", RTYPE_FCC | 4}, \
1955 {"$fcc5", RTYPE_FCC | 5}, \
1956 {"$fcc6", RTYPE_FCC | 6}, \
1957 {"$fcc7", RTYPE_FCC | 7}
1959 #define COPROC_CONDITION_CODE_NAMES \
1960 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1961 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1962 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1963 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1964 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1965 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1966 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1967 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1969 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1970 {"$a4", RTYPE_GP | 8}, \
1971 {"$a5", RTYPE_GP | 9}, \
1972 {"$a6", RTYPE_GP | 10}, \
1973 {"$a7", RTYPE_GP | 11}, \
1974 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1975 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1976 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1977 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1978 {"$t0", RTYPE_GP | 12}, \
1979 {"$t1", RTYPE_GP | 13}, \
1980 {"$t2", RTYPE_GP | 14}, \
1981 {"$t3", RTYPE_GP | 15}
1983 #define O32_SYMBOLIC_REGISTER_NAMES \
1984 {"$t0", RTYPE_GP | 8}, \
1985 {"$t1", RTYPE_GP | 9}, \
1986 {"$t2", RTYPE_GP | 10}, \
1987 {"$t3", RTYPE_GP | 11}, \
1988 {"$t4", RTYPE_GP | 12}, \
1989 {"$t5", RTYPE_GP | 13}, \
1990 {"$t6", RTYPE_GP | 14}, \
1991 {"$t7", RTYPE_GP | 15}, \
1992 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1993 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1994 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1995 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1997 /* Remaining symbolic register names */
1998 #define SYMBOLIC_REGISTER_NAMES \
1999 {"$zero", RTYPE_GP | 0}, \
2000 {"$at", RTYPE_GP | 1}, \
2001 {"$AT", RTYPE_GP | 1}, \
2002 {"$v0", RTYPE_GP | 2}, \
2003 {"$v1", RTYPE_GP | 3}, \
2004 {"$a0", RTYPE_GP | 4}, \
2005 {"$a1", RTYPE_GP | 5}, \
2006 {"$a2", RTYPE_GP | 6}, \
2007 {"$a3", RTYPE_GP | 7}, \
2008 {"$s0", RTYPE_GP | 16}, \
2009 {"$s1", RTYPE_GP | 17}, \
2010 {"$s2", RTYPE_GP | 18}, \
2011 {"$s3", RTYPE_GP | 19}, \
2012 {"$s4", RTYPE_GP | 20}, \
2013 {"$s5", RTYPE_GP | 21}, \
2014 {"$s6", RTYPE_GP | 22}, \
2015 {"$s7", RTYPE_GP | 23}, \
2016 {"$t8", RTYPE_GP | 24}, \
2017 {"$t9", RTYPE_GP | 25}, \
2018 {"$k0", RTYPE_GP | 26}, \
2019 {"$kt0", RTYPE_GP | 26}, \
2020 {"$k1", RTYPE_GP | 27}, \
2021 {"$kt1", RTYPE_GP | 27}, \
2022 {"$gp", RTYPE_GP | 28}, \
2023 {"$sp", RTYPE_GP | 29}, \
2024 {"$s8", RTYPE_GP | 30}, \
2025 {"$fp", RTYPE_GP | 30}, \
2026 {"$ra", RTYPE_GP | 31}
2028 #define MIPS16_SPECIAL_REGISTER_NAMES \
2029 {"$pc", RTYPE_PC | 0}
2031 #define MDMX_VECTOR_REGISTER_NAMES \
2032 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2033 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2034 {"$v2", RTYPE_VEC | 2}, \
2035 {"$v3", RTYPE_VEC | 3}, \
2036 {"$v4", RTYPE_VEC | 4}, \
2037 {"$v5", RTYPE_VEC | 5}, \
2038 {"$v6", RTYPE_VEC | 6}, \
2039 {"$v7", RTYPE_VEC | 7}, \
2040 {"$v8", RTYPE_VEC | 8}, \
2041 {"$v9", RTYPE_VEC | 9}, \
2042 {"$v10", RTYPE_VEC | 10}, \
2043 {"$v11", RTYPE_VEC | 11}, \
2044 {"$v12", RTYPE_VEC | 12}, \
2045 {"$v13", RTYPE_VEC | 13}, \
2046 {"$v14", RTYPE_VEC | 14}, \
2047 {"$v15", RTYPE_VEC | 15}, \
2048 {"$v16", RTYPE_VEC | 16}, \
2049 {"$v17", RTYPE_VEC | 17}, \
2050 {"$v18", RTYPE_VEC | 18}, \
2051 {"$v19", RTYPE_VEC | 19}, \
2052 {"$v20", RTYPE_VEC | 20}, \
2053 {"$v21", RTYPE_VEC | 21}, \
2054 {"$v22", RTYPE_VEC | 22}, \
2055 {"$v23", RTYPE_VEC | 23}, \
2056 {"$v24", RTYPE_VEC | 24}, \
2057 {"$v25", RTYPE_VEC | 25}, \
2058 {"$v26", RTYPE_VEC | 26}, \
2059 {"$v27", RTYPE_VEC | 27}, \
2060 {"$v28", RTYPE_VEC | 28}, \
2061 {"$v29", RTYPE_VEC | 29}, \
2062 {"$v30", RTYPE_VEC | 30}, \
2063 {"$v31", RTYPE_VEC | 31}
2065 #define MIPS_DSP_ACCUMULATOR_NAMES \
2066 {"$ac0", RTYPE_ACC | 0}, \
2067 {"$ac1", RTYPE_ACC | 1}, \
2068 {"$ac2", RTYPE_ACC | 2}, \
2069 {"$ac3", RTYPE_ACC | 3}
2071 static const struct regname reg_names
[] = {
2072 GENERIC_REGISTER_NUMBERS
,
2074 FPU_CONDITION_CODE_NAMES
,
2075 COPROC_CONDITION_CODE_NAMES
,
2077 /* The $txx registers depends on the abi,
2078 these will be added later into the symbol table from
2079 one of the tables below once mips_abi is set after
2080 parsing of arguments from the command line. */
2081 SYMBOLIC_REGISTER_NAMES
,
2083 MIPS16_SPECIAL_REGISTER_NAMES
,
2084 MDMX_VECTOR_REGISTER_NAMES
,
2085 MIPS_DSP_ACCUMULATOR_NAMES
,
2089 static const struct regname reg_names_o32
[] = {
2090 O32_SYMBOLIC_REGISTER_NAMES
,
2094 static const struct regname reg_names_n32n64
[] = {
2095 N32N64_SYMBOLIC_REGISTER_NAMES
,
2099 /* Check if S points at a valid register specifier according to TYPES.
2100 If so, then return 1, advance S to consume the specifier and store
2101 the register's number in REGNOP, otherwise return 0. */
2104 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2111 /* Find end of name. */
2113 if (is_name_beginner (*e
))
2115 while (is_part_of_name (*e
))
2118 /* Terminate name. */
2122 /* Look for a register symbol. */
2123 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2125 int r
= S_GET_VALUE (symbolP
);
2127 reg
= r
& RNUM_MASK
;
2128 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2129 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2130 reg
= (r
& RNUM_MASK
) - 2;
2132 /* Else see if this is a register defined in an itbl entry. */
2133 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2140 if (itbl_get_reg_val (n
, &r
))
2141 reg
= r
& RNUM_MASK
;
2144 /* Advance to next token if a register was recognised. */
2147 else if (types
& RWARN
)
2148 as_warn (_("Unrecognized register name `%s'"), *s
);
2156 /* Check if S points at a valid register list according to TYPES.
2157 If so, then return 1, advance S to consume the list and store
2158 the registers present on the list as a bitmask of ones in REGLISTP,
2159 otherwise return 0. A valid list comprises a comma-separated
2160 enumeration of valid single registers and/or dash-separated
2161 contiguous register ranges as determined by their numbers.
2163 As a special exception if one of s0-s7 registers is specified as
2164 the range's lower delimiter and s8 (fp) is its upper one, then no
2165 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2166 are selected; they have to be listed separately if needed. */
2169 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2171 unsigned int reglist
= 0;
2172 unsigned int lastregno
;
2173 bfd_boolean ok
= TRUE
;
2174 unsigned int regmask
;
2175 char *s_endlist
= *s
;
2179 while (reg_lookup (s
, types
, ®no
))
2185 ok
= reg_lookup (s
, types
, &lastregno
);
2186 if (ok
&& lastregno
< regno
)
2192 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2197 regmask
= 1 << lastregno
;
2198 regmask
= (regmask
<< 1) - 1;
2199 regmask
^= (1 << regno
) - 1;
2213 *reglistp
= reglist
;
2214 return ok
&& reglist
!= 0;
2217 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2218 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2221 is_opcode_valid (const struct mips_opcode
*mo
)
2223 int isa
= mips_opts
.isa
;
2226 if (mips_opts
.ase_mdmx
)
2228 if (mips_opts
.ase_dsp
)
2230 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2232 if (mips_opts
.ase_dspr2
)
2234 if (mips_opts
.ase_mt
)
2236 if (mips_opts
.ase_mips3d
)
2238 if (mips_opts
.ase_smartmips
)
2239 isa
|= INSN_SMARTMIPS
;
2240 if (mips_opts
.ase_mcu
)
2243 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2246 /* Check whether the instruction or macro requires single-precision or
2247 double-precision floating-point support. Note that this information is
2248 stored differently in the opcode table for insns and macros. */
2249 if (mo
->pinfo
== INSN_MACRO
)
2251 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2252 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2256 fp_s
= mo
->pinfo
& FP_S
;
2257 fp_d
= mo
->pinfo
& FP_D
;
2260 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2263 if (fp_s
&& mips_opts
.soft_float
)
2269 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2270 selected ISA and architecture. */
2273 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2275 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2278 /* Return TRUE if the size of the microMIPS opcode MO matches one
2279 explicitly requested. Always TRUE in the standard MIPS mode. */
2282 is_size_valid (const struct mips_opcode
*mo
)
2284 if (!mips_opts
.micromips
)
2287 if (!forced_insn_length
)
2289 if (mo
->pinfo
== INSN_MACRO
)
2291 return forced_insn_length
== micromips_insn_length (mo
);
2294 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2295 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2298 is_delay_slot_valid (const struct mips_opcode
*mo
)
2300 if (!mips_opts
.micromips
)
2303 if (mo
->pinfo
== INSN_MACRO
)
2305 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2306 && micromips_insn_length (mo
) != 4)
2308 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2309 && micromips_insn_length (mo
) != 2)
2315 /* This function is called once, at assembler startup time. It should set up
2316 all the tables, etc. that the MD part of the assembler will need. */
2321 const char *retval
= NULL
;
2325 if (mips_pic
!= NO_PIC
)
2327 if (g_switch_seen
&& g_switch_value
!= 0)
2328 as_bad (_("-G may not be used in position-independent code"));
2332 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2333 as_warn (_("Could not set architecture and machine"));
2335 op_hash
= hash_new ();
2337 for (i
= 0; i
< NUMOPCODES
;)
2339 const char *name
= mips_opcodes
[i
].name
;
2341 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2344 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2345 mips_opcodes
[i
].name
, retval
);
2346 /* Probably a memory allocation problem? Give up now. */
2347 as_fatal (_("Broken assembler. No assembly attempted."));
2351 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2353 if (!validate_mips_insn (&mips_opcodes
[i
]))
2355 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2357 create_insn (&nop_insn
, mips_opcodes
+ i
);
2358 if (mips_fix_loongson2f_nop
)
2359 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2360 nop_insn
.fixed_p
= 1;
2365 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2368 mips16_op_hash
= hash_new ();
2371 while (i
< bfd_mips16_num_opcodes
)
2373 const char *name
= mips16_opcodes
[i
].name
;
2375 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2377 as_fatal (_("internal: can't hash `%s': %s"),
2378 mips16_opcodes
[i
].name
, retval
);
2381 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2382 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2383 != mips16_opcodes
[i
].match
))
2385 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2386 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2389 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2391 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2392 mips16_nop_insn
.fixed_p
= 1;
2396 while (i
< bfd_mips16_num_opcodes
2397 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2400 micromips_op_hash
= hash_new ();
2403 while (i
< bfd_micromips_num_opcodes
)
2405 const char *name
= micromips_opcodes
[i
].name
;
2407 retval
= hash_insert (micromips_op_hash
, name
,
2408 (void *) µmips_opcodes
[i
]);
2410 as_fatal (_("internal: can't hash `%s': %s"),
2411 micromips_opcodes
[i
].name
, retval
);
2413 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2415 struct mips_cl_insn
*micromips_nop_insn
;
2417 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2420 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2421 micromips_nop_insn
= µmips_nop16_insn
;
2422 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2423 micromips_nop_insn
= µmips_nop32_insn
;
2427 if (micromips_nop_insn
->insn_mo
== NULL
2428 && strcmp (name
, "nop") == 0)
2430 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2431 micromips_nop_insn
->fixed_p
= 1;
2434 while (++i
< bfd_micromips_num_opcodes
2435 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2439 as_fatal (_("Broken assembler. No assembly attempted."));
2441 /* We add all the general register names to the symbol table. This
2442 helps us detect invalid uses of them. */
2443 for (i
= 0; reg_names
[i
].name
; i
++)
2444 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2445 reg_names
[i
].num
, /* & RNUM_MASK, */
2446 &zero_address_frag
));
2448 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2449 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2450 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2451 &zero_address_frag
));
2453 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2454 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2455 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2456 &zero_address_frag
));
2458 mips_no_prev_insn ();
2461 mips_cprmask
[0] = 0;
2462 mips_cprmask
[1] = 0;
2463 mips_cprmask
[2] = 0;
2464 mips_cprmask
[3] = 0;
2466 /* set the default alignment for the text section (2**2) */
2467 record_alignment (text_section
, 2);
2469 bfd_set_gp_size (stdoutput
, g_switch_value
);
2474 /* On a native system other than VxWorks, sections must be aligned
2475 to 16 byte boundaries. When configured for an embedded ELF
2476 target, we don't bother. */
2477 if (strncmp (TARGET_OS
, "elf", 3) != 0
2478 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2480 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2481 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2482 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2485 /* Create a .reginfo section for register masks and a .mdebug
2486 section for debugging information. */
2494 subseg
= now_subseg
;
2496 /* The ABI says this section should be loaded so that the
2497 running program can access it. However, we don't load it
2498 if we are configured for an embedded target */
2499 flags
= SEC_READONLY
| SEC_DATA
;
2500 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2501 flags
|= SEC_ALLOC
| SEC_LOAD
;
2503 if (mips_abi
!= N64_ABI
)
2505 sec
= subseg_new (".reginfo", (subsegT
) 0);
2507 bfd_set_section_flags (stdoutput
, sec
, flags
);
2508 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2510 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2514 /* The 64-bit ABI uses a .MIPS.options section rather than
2515 .reginfo section. */
2516 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2517 bfd_set_section_flags (stdoutput
, sec
, flags
);
2518 bfd_set_section_alignment (stdoutput
, sec
, 3);
2520 /* Set up the option header. */
2522 Elf_Internal_Options opthdr
;
2525 opthdr
.kind
= ODK_REGINFO
;
2526 opthdr
.size
= (sizeof (Elf_External_Options
)
2527 + sizeof (Elf64_External_RegInfo
));
2530 f
= frag_more (sizeof (Elf_External_Options
));
2531 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2532 (Elf_External_Options
*) f
);
2534 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2538 if (ECOFF_DEBUGGING
)
2540 sec
= subseg_new (".mdebug", (subsegT
) 0);
2541 (void) bfd_set_section_flags (stdoutput
, sec
,
2542 SEC_HAS_CONTENTS
| SEC_READONLY
);
2543 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2545 else if (mips_flag_pdr
)
2547 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2548 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2549 SEC_READONLY
| SEC_RELOC
2551 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2554 subseg_set (seg
, subseg
);
2557 #endif /* OBJ_ELF */
2559 if (! ECOFF_DEBUGGING
)
2562 if (mips_fix_vr4120
)
2563 init_vr4120_conflicts ();
2569 mips_emit_delays ();
2570 if (! ECOFF_DEBUGGING
)
2575 md_assemble (char *str
)
2577 struct mips_cl_insn insn
;
2578 bfd_reloc_code_real_type unused_reloc
[3]
2579 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2581 imm_expr
.X_op
= O_absent
;
2582 imm2_expr
.X_op
= O_absent
;
2583 offset_expr
.X_op
= O_absent
;
2584 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2585 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2586 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2587 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2588 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2589 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2591 if (mips_opts
.mips16
)
2592 mips16_ip (str
, &insn
);
2595 mips_ip (str
, &insn
);
2596 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2597 str
, insn
.insn_opcode
));
2602 as_bad ("%s `%s'", insn_error
, str
);
2606 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2609 if (mips_opts
.mips16
)
2610 mips16_macro (&insn
);
2617 if (imm_expr
.X_op
!= O_absent
)
2618 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2619 else if (offset_expr
.X_op
!= O_absent
)
2620 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2622 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2626 /* Convenience functions for abstracting away the differences between
2627 MIPS16 and non-MIPS16 relocations. */
2629 static inline bfd_boolean
2630 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2634 case BFD_RELOC_MIPS16_JMP
:
2635 case BFD_RELOC_MIPS16_GPREL
:
2636 case BFD_RELOC_MIPS16_GOT16
:
2637 case BFD_RELOC_MIPS16_CALL16
:
2638 case BFD_RELOC_MIPS16_HI16_S
:
2639 case BFD_RELOC_MIPS16_HI16
:
2640 case BFD_RELOC_MIPS16_LO16
:
2648 static inline bfd_boolean
2649 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2653 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2654 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2655 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2656 case BFD_RELOC_MICROMIPS_GPREL16
:
2657 case BFD_RELOC_MICROMIPS_JMP
:
2658 case BFD_RELOC_MICROMIPS_HI16
:
2659 case BFD_RELOC_MICROMIPS_HI16_S
:
2660 case BFD_RELOC_MICROMIPS_LO16
:
2661 case BFD_RELOC_MICROMIPS_LITERAL
:
2662 case BFD_RELOC_MICROMIPS_GOT16
:
2663 case BFD_RELOC_MICROMIPS_CALL16
:
2664 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2665 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2666 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2667 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2668 case BFD_RELOC_MICROMIPS_SUB
:
2669 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2670 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2671 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2672 case BFD_RELOC_MICROMIPS_HIGHEST
:
2673 case BFD_RELOC_MICROMIPS_HIGHER
:
2674 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2675 case BFD_RELOC_MICROMIPS_JALR
:
2683 static inline bfd_boolean
2684 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2686 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2689 static inline bfd_boolean
2690 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2692 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2693 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2696 static inline bfd_boolean
2697 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2699 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2700 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2703 static inline bfd_boolean
2704 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2706 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2707 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2710 static inline bfd_boolean
2711 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2713 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2716 /* Return true if the given relocation might need a matching %lo().
2717 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2718 need a matching %lo() when applied to local symbols. */
2720 static inline bfd_boolean
2721 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2723 return (HAVE_IN_PLACE_ADDENDS
2724 && (hi16_reloc_p (reloc
)
2725 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2726 all GOT16 relocations evaluate to "G". */
2727 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2730 /* Return the type of %lo() reloc needed by RELOC, given that
2731 reloc_needs_lo_p. */
2733 static inline bfd_reloc_code_real_type
2734 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2736 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2737 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2741 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2744 static inline bfd_boolean
2745 fixup_has_matching_lo_p (fixS
*fixp
)
2747 return (fixp
->fx_next
!= NULL
2748 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2749 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2750 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2753 /* This function returns true if modifying a register requires a
2757 reg_needs_delay (unsigned int reg
)
2759 unsigned long prev_pinfo
;
2761 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2762 if (! mips_opts
.noreorder
2763 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2764 && ! gpr_interlocks
)
2765 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2766 && ! cop_interlocks
)))
2768 /* A load from a coprocessor or from memory. All load delays
2769 delay the use of general register rt for one instruction. */
2770 /* Itbl support may require additional care here. */
2771 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2772 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2779 /* Move all labels in LABELS to the current insertion point. TEXT_P
2780 says whether the labels refer to text or data. */
2783 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2785 struct insn_label_list
*l
;
2788 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2790 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2791 symbol_set_frag (l
->label
, frag_now
);
2792 val
= (valueT
) frag_now_fix ();
2793 /* MIPS16/microMIPS text labels are stored as odd. */
2794 if (text_p
&& HAVE_CODE_COMPRESSION
)
2796 S_SET_VALUE (l
->label
, val
);
2800 /* Move all labels in insn_labels to the current insertion point
2801 and treat them as text labels. */
2804 mips_move_text_labels (void)
2806 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2810 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2812 bfd_boolean linkonce
= FALSE
;
2813 segT symseg
= S_GET_SEGMENT (sym
);
2815 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2817 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2820 /* The GNU toolchain uses an extension for ELF: a section
2821 beginning with the magic string .gnu.linkonce is a
2822 linkonce section. */
2823 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2824 sizeof ".gnu.linkonce" - 1) == 0)
2831 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2832 linker to handle them specially, such as generating jalx instructions
2833 when needed. We also make them odd for the duration of the assembly,
2834 in order to generate the right sort of code. We will make them even
2835 in the adjust_symtab routine, while leaving them marked. This is
2836 convenient for the debugger and the disassembler. The linker knows
2837 to make them odd again. */
2840 mips_compressed_mark_labels (void)
2842 segment_info_type
*si
= seg_info (now_seg
);
2843 struct insn_label_list
*l
;
2845 gas_assert (HAVE_CODE_COMPRESSION
);
2847 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2849 symbolS
*label
= l
->label
;
2851 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2854 if (mips_opts
.mips16
)
2855 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2857 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2860 if ((S_GET_VALUE (label
) & 1) == 0
2861 /* Don't adjust the address if the label is global or weak, or
2862 in a link-once section, since we'll be emitting symbol reloc
2863 references to it which will be patched up by the linker, and
2864 the final value of the symbol may or may not be MIPS16/microMIPS. */
2865 && ! S_IS_WEAK (label
)
2866 && ! S_IS_EXTERNAL (label
)
2867 && ! s_is_linkonce (label
, now_seg
))
2868 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2872 /* End the current frag. Make it a variant frag and record the
2876 relax_close_frag (void)
2878 mips_macro_warning
.first_frag
= frag_now
;
2879 frag_var (rs_machine_dependent
, 0, 0,
2880 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2881 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2883 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2884 mips_relax
.first_fixup
= 0;
2887 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2888 See the comment above RELAX_ENCODE for more details. */
2891 relax_start (symbolS
*symbol
)
2893 gas_assert (mips_relax
.sequence
== 0);
2894 mips_relax
.sequence
= 1;
2895 mips_relax
.symbol
= symbol
;
2898 /* Start generating the second version of a relaxable sequence.
2899 See the comment above RELAX_ENCODE for more details. */
2904 gas_assert (mips_relax
.sequence
== 1);
2905 mips_relax
.sequence
= 2;
2908 /* End the current relaxable sequence. */
2913 gas_assert (mips_relax
.sequence
== 2);
2914 relax_close_frag ();
2915 mips_relax
.sequence
= 0;
2918 /* Return true if IP is a delayed branch or jump. */
2920 static inline bfd_boolean
2921 delayed_branch_p (const struct mips_cl_insn
*ip
)
2923 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2924 | INSN_COND_BRANCH_DELAY
2925 | INSN_COND_BRANCH_LIKELY
)) != 0;
2928 /* Return true if IP is a compact branch or jump. */
2930 static inline bfd_boolean
2931 compact_branch_p (const struct mips_cl_insn
*ip
)
2933 if (mips_opts
.mips16
)
2934 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2935 | MIPS16_INSN_COND_BRANCH
)) != 0;
2937 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2938 | INSN2_COND_BRANCH
)) != 0;
2941 /* Return true if IP is an unconditional branch or jump. */
2943 static inline bfd_boolean
2944 uncond_branch_p (const struct mips_cl_insn
*ip
)
2946 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2947 || (mips_opts
.mips16
2948 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
2949 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
2952 /* Return true if IP is a branch-likely instruction. */
2954 static inline bfd_boolean
2955 branch_likely_p (const struct mips_cl_insn
*ip
)
2957 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
2960 /* Return the type of nop that should be used to fill the delay slot
2961 of delayed branch IP. */
2963 static struct mips_cl_insn
*
2964 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
2966 if (mips_opts
.micromips
2967 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
2968 return µmips_nop32_insn
;
2972 /* Return the mask of core registers that IP reads or writes. */
2975 gpr_mod_mask (const struct mips_cl_insn
*ip
)
2977 unsigned long pinfo2
;
2981 pinfo2
= ip
->insn_mo
->pinfo2
;
2982 if (mips_opts
.micromips
)
2984 if (pinfo2
& INSN2_MOD_GPR_MD
)
2985 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
2986 if (pinfo2
& INSN2_MOD_GPR_MF
)
2987 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
2988 if (pinfo2
& INSN2_MOD_SP
)
2994 /* Return the mask of core registers that IP reads. */
2997 gpr_read_mask (const struct mips_cl_insn
*ip
)
2999 unsigned long pinfo
, pinfo2
;
3002 mask
= gpr_mod_mask (ip
);
3003 pinfo
= ip
->insn_mo
->pinfo
;
3004 pinfo2
= ip
->insn_mo
->pinfo2
;
3005 if (mips_opts
.mips16
)
3007 if (pinfo
& MIPS16_INSN_READ_X
)
3008 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3009 if (pinfo
& MIPS16_INSN_READ_Y
)
3010 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3011 if (pinfo
& MIPS16_INSN_READ_T
)
3013 if (pinfo
& MIPS16_INSN_READ_SP
)
3015 if (pinfo
& MIPS16_INSN_READ_31
)
3017 if (pinfo
& MIPS16_INSN_READ_Z
)
3018 mask
|= 1 << (mips16_to_32_reg_map
3019 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3020 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3021 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3025 if (pinfo2
& INSN2_READ_GPR_D
)
3026 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3027 if (pinfo
& INSN_READ_GPR_T
)
3028 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3029 if (pinfo
& INSN_READ_GPR_S
)
3030 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3031 if (pinfo2
& INSN2_READ_GP
)
3033 if (pinfo2
& INSN2_READ_GPR_31
)
3035 if (pinfo2
& INSN2_READ_GPR_Z
)
3036 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3038 if (mips_opts
.micromips
)
3040 if (pinfo2
& INSN2_READ_GPR_MC
)
3041 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3042 if (pinfo2
& INSN2_READ_GPR_ME
)
3043 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3044 if (pinfo2
& INSN2_READ_GPR_MG
)
3045 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3046 if (pinfo2
& INSN2_READ_GPR_MJ
)
3047 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3048 if (pinfo2
& INSN2_READ_GPR_MMN
)
3050 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3051 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3053 if (pinfo2
& INSN2_READ_GPR_MP
)
3054 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3055 if (pinfo2
& INSN2_READ_GPR_MQ
)
3056 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3058 /* Don't include register 0. */
3062 /* Return the mask of core registers that IP writes. */
3065 gpr_write_mask (const struct mips_cl_insn
*ip
)
3067 unsigned long pinfo
, pinfo2
;
3070 mask
= gpr_mod_mask (ip
);
3071 pinfo
= ip
->insn_mo
->pinfo
;
3072 pinfo2
= ip
->insn_mo
->pinfo2
;
3073 if (mips_opts
.mips16
)
3075 if (pinfo
& MIPS16_INSN_WRITE_X
)
3076 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3077 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3078 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3079 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3080 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3081 if (pinfo
& MIPS16_INSN_WRITE_T
)
3083 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3085 if (pinfo
& MIPS16_INSN_WRITE_31
)
3087 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3088 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3092 if (pinfo
& INSN_WRITE_GPR_D
)
3093 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3094 if (pinfo
& INSN_WRITE_GPR_T
)
3095 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3096 if (pinfo
& INSN_WRITE_GPR_S
)
3097 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3098 if (pinfo
& INSN_WRITE_GPR_31
)
3100 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3101 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3103 if (mips_opts
.micromips
)
3105 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3106 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3107 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3109 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3110 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3112 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3113 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3114 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3115 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3117 /* Don't include register 0. */
3121 /* Return the mask of floating-point registers that IP reads. */
3124 fpr_read_mask (const struct mips_cl_insn
*ip
)
3126 unsigned long pinfo
, pinfo2
;
3130 pinfo
= ip
->insn_mo
->pinfo
;
3131 pinfo2
= ip
->insn_mo
->pinfo2
;
3132 if (!mips_opts
.mips16
)
3134 if (pinfo2
& INSN2_READ_FPR_D
)
3135 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3136 if (pinfo
& INSN_READ_FPR_S
)
3137 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3138 if (pinfo
& INSN_READ_FPR_T
)
3139 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3140 if (pinfo
& INSN_READ_FPR_R
)
3141 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3142 if (pinfo2
& INSN2_READ_FPR_Z
)
3143 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3145 /* Conservatively treat all operands to an FP_D instruction are doubles.
3146 (This is overly pessimistic for things like cvt.d.s.) */
3147 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3152 /* Return the mask of floating-point registers that IP writes. */
3155 fpr_write_mask (const struct mips_cl_insn
*ip
)
3157 unsigned long pinfo
, pinfo2
;
3161 pinfo
= ip
->insn_mo
->pinfo
;
3162 pinfo2
= ip
->insn_mo
->pinfo2
;
3163 if (!mips_opts
.mips16
)
3165 if (pinfo
& INSN_WRITE_FPR_D
)
3166 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3167 if (pinfo
& INSN_WRITE_FPR_S
)
3168 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3169 if (pinfo
& INSN_WRITE_FPR_T
)
3170 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3171 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3172 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3174 /* Conservatively treat all operands to an FP_D instruction are doubles.
3175 (This is overly pessimistic for things like cvt.s.d.) */
3176 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3181 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3182 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3183 by VR4120 errata. */
3186 classify_vr4120_insn (const char *name
)
3188 if (strncmp (name
, "macc", 4) == 0)
3189 return FIX_VR4120_MACC
;
3190 if (strncmp (name
, "dmacc", 5) == 0)
3191 return FIX_VR4120_DMACC
;
3192 if (strncmp (name
, "mult", 4) == 0)
3193 return FIX_VR4120_MULT
;
3194 if (strncmp (name
, "dmult", 5) == 0)
3195 return FIX_VR4120_DMULT
;
3196 if (strstr (name
, "div"))
3197 return FIX_VR4120_DIV
;
3198 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3199 return FIX_VR4120_MTHILO
;
3200 return NUM_FIX_VR4120_CLASSES
;
3203 #define INSN_ERET 0x42000018
3204 #define INSN_DERET 0x4200001f
3206 /* Return the number of instructions that must separate INSN1 and INSN2,
3207 where INSN1 is the earlier instruction. Return the worst-case value
3208 for any INSN2 if INSN2 is null. */
3211 insns_between (const struct mips_cl_insn
*insn1
,
3212 const struct mips_cl_insn
*insn2
)
3214 unsigned long pinfo1
, pinfo2
;
3217 /* This function needs to know which pinfo flags are set for INSN2
3218 and which registers INSN2 uses. The former is stored in PINFO2 and
3219 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3220 will have every flag set and INSN2_USES_GPR will always return true. */
3221 pinfo1
= insn1
->insn_mo
->pinfo
;
3222 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3224 #define INSN2_USES_GPR(REG) \
3225 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3227 /* For most targets, write-after-read dependencies on the HI and LO
3228 registers must be separated by at least two instructions. */
3229 if (!hilo_interlocks
)
3231 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3233 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3237 /* If we're working around r7000 errata, there must be two instructions
3238 between an mfhi or mflo and any instruction that uses the result. */
3239 if (mips_7000_hilo_fix
3240 && !mips_opts
.micromips
3241 && MF_HILO_INSN (pinfo1
)
3242 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3245 /* If we're working around 24K errata, one instruction is required
3246 if an ERET or DERET is followed by a branch instruction. */
3247 if (mips_fix_24k
&& !mips_opts
.micromips
)
3249 if (insn1
->insn_opcode
== INSN_ERET
3250 || insn1
->insn_opcode
== INSN_DERET
)
3253 || insn2
->insn_opcode
== INSN_ERET
3254 || insn2
->insn_opcode
== INSN_DERET
3255 || delayed_branch_p (insn2
))
3260 /* If working around VR4120 errata, check for combinations that need
3261 a single intervening instruction. */
3262 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3264 unsigned int class1
, class2
;
3266 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3267 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3271 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3272 if (vr4120_conflicts
[class1
] & (1 << class2
))
3277 if (!HAVE_CODE_COMPRESSION
)
3279 /* Check for GPR or coprocessor load delays. All such delays
3280 are on the RT register. */
3281 /* Itbl support may require additional care here. */
3282 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3283 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3285 know (pinfo1
& INSN_WRITE_GPR_T
);
3286 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3290 /* Check for generic coprocessor hazards.
3292 This case is not handled very well. There is no special
3293 knowledge of CP0 handling, and the coprocessors other than
3294 the floating point unit are not distinguished at all. */
3295 /* Itbl support may require additional care here. FIXME!
3296 Need to modify this to include knowledge about
3297 user specified delays! */
3298 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3299 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3301 /* Handle cases where INSN1 writes to a known general coprocessor
3302 register. There must be a one instruction delay before INSN2
3303 if INSN2 reads that register, otherwise no delay is needed. */
3304 mask
= fpr_write_mask (insn1
);
3307 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3312 /* Read-after-write dependencies on the control registers
3313 require a two-instruction gap. */
3314 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3315 && (pinfo2
& INSN_READ_COND_CODE
))
3318 /* We don't know exactly what INSN1 does. If INSN2 is
3319 also a coprocessor instruction, assume there must be
3320 a one instruction gap. */
3321 if (pinfo2
& INSN_COP
)
3326 /* Check for read-after-write dependencies on the coprocessor
3327 control registers in cases where INSN1 does not need a general
3328 coprocessor delay. This means that INSN1 is a floating point
3329 comparison instruction. */
3330 /* Itbl support may require additional care here. */
3331 else if (!cop_interlocks
3332 && (pinfo1
& INSN_WRITE_COND_CODE
)
3333 && (pinfo2
& INSN_READ_COND_CODE
))
3337 #undef INSN2_USES_GPR
3342 /* Return the number of nops that would be needed to work around the
3343 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3344 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3345 that are contained within the first IGNORE instructions of HIST. */
3348 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3349 const struct mips_cl_insn
*insn
)
3354 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3355 are not affected by the errata. */
3357 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3358 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3359 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3362 /* Search for the first MFLO or MFHI. */
3363 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3364 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3366 /* Extract the destination register. */
3367 mask
= gpr_write_mask (&hist
[i
]);
3369 /* No nops are needed if INSN reads that register. */
3370 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3373 /* ...or if any of the intervening instructions do. */
3374 for (j
= 0; j
< i
; j
++)
3375 if (gpr_read_mask (&hist
[j
]) & mask
)
3379 return MAX_VR4130_NOPS
- i
;
3384 #define BASE_REG_EQ(INSN1, INSN2) \
3385 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3386 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3388 /* Return the minimum alignment for this store instruction. */
3391 fix_24k_align_to (const struct mips_opcode
*mo
)
3393 if (strcmp (mo
->name
, "sh") == 0)
3396 if (strcmp (mo
->name
, "swc1") == 0
3397 || strcmp (mo
->name
, "swc2") == 0
3398 || strcmp (mo
->name
, "sw") == 0
3399 || strcmp (mo
->name
, "sc") == 0
3400 || strcmp (mo
->name
, "s.s") == 0)
3403 if (strcmp (mo
->name
, "sdc1") == 0
3404 || strcmp (mo
->name
, "sdc2") == 0
3405 || strcmp (mo
->name
, "s.d") == 0)
3412 struct fix_24k_store_info
3414 /* Immediate offset, if any, for this store instruction. */
3416 /* Alignment required by this store instruction. */
3418 /* True for register offsets. */
3419 int register_offset
;
3422 /* Comparison function used by qsort. */
3425 fix_24k_sort (const void *a
, const void *b
)
3427 const struct fix_24k_store_info
*pos1
= a
;
3428 const struct fix_24k_store_info
*pos2
= b
;
3430 return (pos1
->off
- pos2
->off
);
3433 /* INSN is a store instruction. Try to record the store information
3434 in STINFO. Return false if the information isn't known. */
3437 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3438 const struct mips_cl_insn
*insn
)
3440 /* The instruction must have a known offset. */
3441 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3444 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3445 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3449 /* Return the number of nops that would be needed to work around the 24k
3450 "lost data on stores during refill" errata if instruction INSN
3451 immediately followed the 2 instructions described by HIST.
3452 Ignore hazards that are contained within the first IGNORE
3453 instructions of HIST.
3455 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3456 for the data cache refills and store data. The following describes
3457 the scenario where the store data could be lost.
3459 * A data cache miss, due to either a load or a store, causing fill
3460 data to be supplied by the memory subsystem
3461 * The first three doublewords of fill data are returned and written
3463 * A sequence of four stores occurs in consecutive cycles around the
3464 final doubleword of the fill:
3468 * Zero, One or more instructions
3471 The four stores A-D must be to different doublewords of the line that
3472 is being filled. The fourth instruction in the sequence above permits
3473 the fill of the final doubleword to be transferred from the FSB into
3474 the cache. In the sequence above, the stores may be either integer
3475 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3476 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3477 different doublewords on the line. If the floating point unit is
3478 running in 1:2 mode, it is not possible to create the sequence above
3479 using only floating point store instructions.
3481 In this case, the cache line being filled is incorrectly marked
3482 invalid, thereby losing the data from any store to the line that
3483 occurs between the original miss and the completion of the five
3484 cycle sequence shown above.
3486 The workarounds are:
3488 * Run the data cache in write-through mode.
3489 * Insert a non-store instruction between
3490 Store A and Store B or Store B and Store C. */
3493 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3494 const struct mips_cl_insn
*insn
)
3496 struct fix_24k_store_info pos
[3];
3497 int align
, i
, base_offset
;
3502 /* If the previous instruction wasn't a store, there's nothing to
3504 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3507 /* If the instructions after the previous one are unknown, we have
3508 to assume the worst. */
3512 /* Check whether we are dealing with three consecutive stores. */
3513 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3514 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3517 /* If we don't know the relationship between the store addresses,
3518 assume the worst. */
3519 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3520 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3523 if (!fix_24k_record_store_info (&pos
[0], insn
)
3524 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3525 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3528 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3530 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3531 X bytes and such that the base register + X is known to be aligned
3534 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3538 align
= pos
[0].align_to
;
3539 base_offset
= pos
[0].off
;
3540 for (i
= 1; i
< 3; i
++)
3541 if (align
< pos
[i
].align_to
)
3543 align
= pos
[i
].align_to
;
3544 base_offset
= pos
[i
].off
;
3546 for (i
= 0; i
< 3; i
++)
3547 pos
[i
].off
-= base_offset
;
3550 pos
[0].off
&= ~align
+ 1;
3551 pos
[1].off
&= ~align
+ 1;
3552 pos
[2].off
&= ~align
+ 1;
3554 /* If any two stores write to the same chunk, they also write to the
3555 same doubleword. The offsets are still sorted at this point. */
3556 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3559 /* A range of at least 9 bytes is needed for the stores to be in
3560 non-overlapping doublewords. */
3561 if (pos
[2].off
- pos
[0].off
<= 8)
3564 if (pos
[2].off
- pos
[1].off
>= 24
3565 || pos
[1].off
- pos
[0].off
>= 24
3566 || pos
[2].off
- pos
[0].off
>= 32)
3572 /* Return the number of nops that would be needed if instruction INSN
3573 immediately followed the MAX_NOPS instructions given by HIST,
3574 where HIST[0] is the most recent instruction. Ignore hazards
3575 between INSN and the first IGNORE instructions in HIST.
3577 If INSN is null, return the worse-case number of nops for any
3581 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3582 const struct mips_cl_insn
*insn
)
3584 int i
, nops
, tmp_nops
;
3587 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3589 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3590 if (tmp_nops
> nops
)
3594 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3596 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3597 if (tmp_nops
> nops
)
3601 if (mips_fix_24k
&& !mips_opts
.micromips
)
3603 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3604 if (tmp_nops
> nops
)
3611 /* The variable arguments provide NUM_INSNS extra instructions that
3612 might be added to HIST. Return the largest number of nops that
3613 would be needed after the extended sequence, ignoring hazards
3614 in the first IGNORE instructions. */
3617 nops_for_sequence (int num_insns
, int ignore
,
3618 const struct mips_cl_insn
*hist
, ...)
3621 struct mips_cl_insn buffer
[MAX_NOPS
];
3622 struct mips_cl_insn
*cursor
;
3625 va_start (args
, hist
);
3626 cursor
= buffer
+ num_insns
;
3627 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3628 while (cursor
> buffer
)
3629 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3631 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3636 /* Like nops_for_insn, but if INSN is a branch, take into account the
3637 worst-case delay for the branch target. */
3640 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3641 const struct mips_cl_insn
*insn
)
3645 nops
= nops_for_insn (ignore
, hist
, insn
);
3646 if (delayed_branch_p (insn
))
3648 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3649 hist
, insn
, get_delay_slot_nop (insn
));
3650 if (tmp_nops
> nops
)
3653 else if (compact_branch_p (insn
))
3655 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3656 if (tmp_nops
> nops
)
3662 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3665 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3667 gas_assert (!HAVE_CODE_COMPRESSION
);
3668 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3669 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3672 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3673 jr target pc &= 'hffff_ffff_cfff_ffff. */
3676 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3678 gas_assert (!HAVE_CODE_COMPRESSION
);
3679 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3680 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3681 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3689 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3690 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3693 ep
.X_op
= O_constant
;
3694 ep
.X_add_number
= 0xcfff0000;
3695 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3696 ep
.X_add_number
= 0xffff;
3697 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3698 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3703 fix_loongson2f (struct mips_cl_insn
* ip
)
3705 if (mips_fix_loongson2f_nop
)
3706 fix_loongson2f_nop (ip
);
3708 if (mips_fix_loongson2f_jump
)
3709 fix_loongson2f_jump (ip
);
3712 /* IP is a branch that has a delay slot, and we need to fill it
3713 automatically. Return true if we can do that by swapping IP
3714 with the previous instruction. */
3717 can_swap_branch_p (struct mips_cl_insn
*ip
)
3719 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3720 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3722 /* -O2 and above is required for this optimization. */
3723 if (mips_optimize
< 2)
3726 /* If we have seen .set volatile or .set nomove, don't optimize. */
3727 if (mips_opts
.nomove
)
3730 /* We can't swap if the previous instruction's position is fixed. */
3731 if (history
[0].fixed_p
)
3734 /* If the previous previous insn was in a .set noreorder, we can't
3735 swap. Actually, the MIPS assembler will swap in this situation.
3736 However, gcc configured -with-gnu-as will generate code like
3744 in which we can not swap the bne and INSN. If gcc is not configured
3745 -with-gnu-as, it does not output the .set pseudo-ops. */
3746 if (history
[1].noreorder_p
)
3749 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3750 This means that the previous instruction was a 4-byte one anyhow. */
3751 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3754 /* If the branch is itself the target of a branch, we can not swap.
3755 We cheat on this; all we check for is whether there is a label on
3756 this instruction. If there are any branches to anything other than
3757 a label, users must use .set noreorder. */
3758 if (seg_info (now_seg
)->label_list
)
3761 /* If the previous instruction is in a variant frag other than this
3762 branch's one, we cannot do the swap. This does not apply to
3763 MIPS16 code, which uses variant frags for different purposes. */
3764 if (!mips_opts
.mips16
3766 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3769 /* We do not swap with instructions that cannot architecturally
3770 be placed in a branch delay slot, such as SYNC or ERET. We
3771 also refrain from swapping with a trap instruction, since it
3772 complicates trap handlers to have the trap instruction be in
3774 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3775 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3778 /* Check for conflicts between the branch and the instructions
3779 before the candidate delay slot. */
3780 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3783 /* Check for conflicts between the swapped sequence and the
3784 target of the branch. */
3785 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3788 /* If the branch reads a register that the previous
3789 instruction sets, we can not swap. */
3790 gpr_read
= gpr_read_mask (ip
);
3791 prev_gpr_write
= gpr_write_mask (&history
[0]);
3792 if (gpr_read
& prev_gpr_write
)
3795 /* If the branch writes a register that the previous
3796 instruction sets, we can not swap. */
3797 gpr_write
= gpr_write_mask (ip
);
3798 if (gpr_write
& prev_gpr_write
)
3801 /* If the branch writes a register that the previous
3802 instruction reads, we can not swap. */
3803 prev_gpr_read
= gpr_read_mask (&history
[0]);
3804 if (gpr_write
& prev_gpr_read
)
3807 /* If one instruction sets a condition code and the
3808 other one uses a condition code, we can not swap. */
3809 pinfo
= ip
->insn_mo
->pinfo
;
3810 if ((pinfo
& INSN_READ_COND_CODE
)
3811 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3813 if ((pinfo
& INSN_WRITE_COND_CODE
)
3814 && (prev_pinfo
& INSN_READ_COND_CODE
))
3817 /* If the previous instruction uses the PC, we can not swap. */
3818 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3819 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3821 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3824 /* If the previous instruction has an incorrect size for a fixed
3825 branch delay slot in microMIPS mode, we cannot swap. */
3826 pinfo2
= ip
->insn_mo
->pinfo2
;
3827 if (mips_opts
.micromips
3828 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3829 && insn_length (history
) != 2)
3831 if (mips_opts
.micromips
3832 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3833 && insn_length (history
) != 4)
3839 /* Decide how we should add IP to the instruction stream. */
3841 static enum append_method
3842 get_append_method (struct mips_cl_insn
*ip
)
3844 unsigned long pinfo
;
3846 /* The relaxed version of a macro sequence must be inherently
3848 if (mips_relax
.sequence
== 2)
3851 /* We must not dabble with instructions in a ".set norerorder" block. */
3852 if (mips_opts
.noreorder
)
3855 /* Otherwise, it's our responsibility to fill branch delay slots. */
3856 if (delayed_branch_p (ip
))
3858 if (!branch_likely_p (ip
) && can_swap_branch_p (ip
))
3861 pinfo
= ip
->insn_mo
->pinfo
;
3862 if (mips_opts
.mips16
3863 && ISA_SUPPORTS_MIPS16E
3864 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3865 return APPEND_ADD_COMPACT
;
3867 return APPEND_ADD_WITH_NOP
;
3873 /* IP is a MIPS16 instruction whose opcode we have just changed.
3874 Point IP->insn_mo to the new opcode's definition. */
3877 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3879 const struct mips_opcode
*mo
, *end
;
3881 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3882 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3883 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3891 /* For microMIPS macros, we need to generate a local number label
3892 as the target of branches. */
3893 #define MICROMIPS_LABEL_CHAR '\037'
3894 static unsigned long micromips_target_label
;
3895 static char micromips_target_name
[32];
3898 micromips_label_name (void)
3900 char *p
= micromips_target_name
;
3901 char symbol_name_temporary
[24];
3909 l
= micromips_target_label
;
3910 #ifdef LOCAL_LABEL_PREFIX
3911 *p
++ = LOCAL_LABEL_PREFIX
;
3914 *p
++ = MICROMIPS_LABEL_CHAR
;
3917 symbol_name_temporary
[i
++] = l
% 10 + '0';
3922 *p
++ = symbol_name_temporary
[--i
];
3925 return micromips_target_name
;
3929 micromips_label_expr (expressionS
*label_expr
)
3931 label_expr
->X_op
= O_symbol
;
3932 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
3933 label_expr
->X_add_number
= 0;
3937 micromips_label_inc (void)
3939 micromips_target_label
++;
3940 *micromips_target_name
= '\0';
3944 micromips_add_label (void)
3948 s
= colon (micromips_label_name ());
3949 micromips_label_inc ();
3950 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3952 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
3958 /* If assembling microMIPS code, then return the microMIPS reloc
3959 corresponding to the requested one if any. Otherwise return
3960 the reloc unchanged. */
3962 static bfd_reloc_code_real_type
3963 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
3965 static const bfd_reloc_code_real_type relocs
[][2] =
3967 /* Keep sorted incrementally by the left-hand key. */
3968 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
3969 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
3970 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
3971 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
3972 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
3973 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
3974 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
3975 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
3976 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
3977 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
3978 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
3979 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
3980 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
3981 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
3982 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
3983 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
3984 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
3985 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
3986 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
3987 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
3988 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
3989 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
3990 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
3991 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
3992 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
3993 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
3994 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
3996 bfd_reloc_code_real_type r
;
3999 if (!mips_opts
.micromips
)
4001 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4007 return relocs
[i
][1];
4012 /* Output an instruction. IP is the instruction information.
4013 ADDRESS_EXPR is an operand of the instruction to be used with
4014 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4015 a macro expansion. */
4018 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4019 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4021 unsigned long prev_pinfo2
, pinfo
;
4022 bfd_boolean relaxed_branch
= FALSE
;
4023 enum append_method method
;
4024 bfd_boolean relax32
;
4027 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4028 fix_loongson2f (ip
);
4030 mips_mark_labels ();
4032 file_ase_mips16
|= mips_opts
.mips16
;
4033 file_ase_micromips
|= mips_opts
.micromips
;
4035 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4036 pinfo
= ip
->insn_mo
->pinfo
;
4038 if (mips_opts
.micromips
4040 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4041 && micromips_insn_length (ip
->insn_mo
) != 2)
4042 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4043 && micromips_insn_length (ip
->insn_mo
) != 4)))
4044 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4045 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4047 if (address_expr
== NULL
)
4049 else if (*reloc_type
<= BFD_RELOC_UNUSED
4050 && address_expr
->X_op
== O_constant
)
4055 switch (*reloc_type
)
4058 ip
->insn_opcode
|= address_expr
->X_add_number
;
4061 case BFD_RELOC_MIPS_HIGHEST
:
4062 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
4063 ip
->insn_opcode
|= tmp
& 0xffff;
4066 case BFD_RELOC_MIPS_HIGHER
:
4067 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
4068 ip
->insn_opcode
|= tmp
& 0xffff;
4071 case BFD_RELOC_HI16_S
:
4072 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
4073 ip
->insn_opcode
|= tmp
& 0xffff;
4076 case BFD_RELOC_HI16
:
4077 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
4080 case BFD_RELOC_UNUSED
:
4081 case BFD_RELOC_LO16
:
4082 case BFD_RELOC_MIPS_GOT_DISP
:
4083 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
4086 case BFD_RELOC_MIPS_JMP
:
4090 shift
= mips_opts
.micromips
? 1 : 2;
4091 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4092 as_bad (_("jump to misaligned address (0x%lx)"),
4093 (unsigned long) address_expr
->X_add_number
);
4094 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4100 case BFD_RELOC_MIPS16_JMP
:
4101 if ((address_expr
->X_add_number
& 3) != 0)
4102 as_bad (_("jump to misaligned address (0x%lx)"),
4103 (unsigned long) address_expr
->X_add_number
);
4105 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4106 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4107 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4111 case BFD_RELOC_16_PCREL_S2
:
4115 shift
= mips_opts
.micromips
? 1 : 2;
4116 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4117 as_bad (_("branch to misaligned address (0x%lx)"),
4118 (unsigned long) address_expr
->X_add_number
);
4119 if (!mips_relax_branch
)
4121 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4122 & ~((1 << (shift
+ 16)) - 1))
4123 as_bad (_("branch address range overflow (0x%lx)"),
4124 (unsigned long) address_expr
->X_add_number
);
4125 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4137 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4139 /* There are a lot of optimizations we could do that we don't.
4140 In particular, we do not, in general, reorder instructions.
4141 If you use gcc with optimization, it will reorder
4142 instructions and generally do much more optimization then we
4143 do here; repeating all that work in the assembler would only
4144 benefit hand written assembly code, and does not seem worth
4146 int nops
= (mips_optimize
== 0
4147 ? nops_for_insn (0, history
, NULL
)
4148 : nops_for_insn_or_target (0, history
, ip
));
4152 unsigned long old_frag_offset
;
4155 old_frag
= frag_now
;
4156 old_frag_offset
= frag_now_fix ();
4158 for (i
= 0; i
< nops
; i
++)
4159 add_fixed_insn (NOP_INSN
);
4160 insert_into_history (0, nops
, NOP_INSN
);
4164 listing_prev_line ();
4165 /* We may be at the start of a variant frag. In case we
4166 are, make sure there is enough space for the frag
4167 after the frags created by listing_prev_line. The
4168 argument to frag_grow here must be at least as large
4169 as the argument to all other calls to frag_grow in
4170 this file. We don't have to worry about being in the
4171 middle of a variant frag, because the variants insert
4172 all needed nop instructions themselves. */
4176 mips_move_text_labels ();
4178 #ifndef NO_ECOFF_DEBUGGING
4179 if (ECOFF_DEBUGGING
)
4180 ecoff_fix_loc (old_frag
, old_frag_offset
);
4184 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4188 /* Work out how many nops in prev_nop_frag are needed by IP,
4189 ignoring hazards generated by the first prev_nop_frag_since
4191 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4192 gas_assert (nops
<= prev_nop_frag_holds
);
4194 /* Enforce NOPS as a minimum. */
4195 if (nops
> prev_nop_frag_required
)
4196 prev_nop_frag_required
= nops
;
4198 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4200 /* Settle for the current number of nops. Update the history
4201 accordingly (for the benefit of any future .set reorder code). */
4202 prev_nop_frag
= NULL
;
4203 insert_into_history (prev_nop_frag_since
,
4204 prev_nop_frag_holds
, NOP_INSN
);
4208 /* Allow this instruction to replace one of the nops that was
4209 tentatively added to prev_nop_frag. */
4210 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4211 prev_nop_frag_holds
--;
4212 prev_nop_frag_since
++;
4216 method
= get_append_method (ip
);
4217 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4220 /* The value passed to dwarf2_emit_insn is the distance between
4221 the beginning of the current instruction and the address that
4222 should be recorded in the debug tables. This is normally the
4225 For MIPS16/microMIPS debug info we want to use ISA-encoded
4226 addresses, so we use -1 for an address higher by one than the
4229 If the instruction produced is a branch that we will swap with
4230 the preceding instruction, then we add the displacement by which
4231 the branch will be moved backwards. This is more appropriate
4232 and for MIPS16/microMIPS code also prevents a debugger from
4233 placing a breakpoint in the middle of the branch (and corrupting
4234 code if software breakpoints are used). */
4235 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4238 relax32
= (mips_relax_branch
4239 /* Don't try branch relaxation within .set nomacro, or within
4240 .set noat if we use $at for PIC computations. If it turns
4241 out that the branch was out-of-range, we'll get an error. */
4242 && !mips_opts
.warn_about_macros
4243 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4244 /* Don't relax BPOSGE32/64 as they have no complementing
4246 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4248 if (!HAVE_CODE_COMPRESSION
4251 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4252 && delayed_branch_p (ip
))
4254 relaxed_branch
= TRUE
;
4255 add_relaxed_insn (ip
, (relaxed_branch_length
4257 uncond_branch_p (ip
) ? -1
4258 : branch_likely_p (ip
) ? 1
4262 uncond_branch_p (ip
),
4263 branch_likely_p (ip
),
4264 pinfo
& INSN_WRITE_GPR_31
,
4266 address_expr
->X_add_symbol
,
4267 address_expr
->X_add_number
);
4268 *reloc_type
= BFD_RELOC_UNUSED
;
4270 else if (mips_opts
.micromips
4272 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4273 || *reloc_type
> BFD_RELOC_UNUSED
)
4274 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4275 /* Don't try branch relaxation when users specify
4276 16-bit/32-bit instructions. */
4277 && !forced_insn_length
)
4279 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4280 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4281 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4282 int compact
= compact_branch_p (ip
);
4283 int al
= pinfo
& INSN_WRITE_GPR_31
;
4286 gas_assert (address_expr
!= NULL
);
4287 gas_assert (!mips_relax
.sequence
);
4289 relaxed_branch
= TRUE
;
4290 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4291 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4292 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4294 address_expr
->X_add_symbol
,
4295 address_expr
->X_add_number
);
4296 *reloc_type
= BFD_RELOC_UNUSED
;
4298 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4300 /* We need to set up a variant frag. */
4301 gas_assert (address_expr
!= NULL
);
4302 add_relaxed_insn (ip
, 4, 0,
4304 (*reloc_type
- BFD_RELOC_UNUSED
,
4305 forced_insn_length
== 2, forced_insn_length
== 4,
4306 delayed_branch_p (&history
[0]),
4307 history
[0].mips16_absolute_jump_p
),
4308 make_expr_symbol (address_expr
), 0);
4310 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4312 if (!delayed_branch_p (ip
))
4313 /* Make sure there is enough room to swap this instruction with
4314 a following jump instruction. */
4316 add_fixed_insn (ip
);
4320 if (mips_opts
.mips16
4321 && mips_opts
.noreorder
4322 && delayed_branch_p (&history
[0]))
4323 as_warn (_("extended instruction in delay slot"));
4325 if (mips_relax
.sequence
)
4327 /* If we've reached the end of this frag, turn it into a variant
4328 frag and record the information for the instructions we've
4330 if (frag_room () < 4)
4331 relax_close_frag ();
4332 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4335 if (mips_relax
.sequence
!= 2)
4337 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4338 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4339 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4340 mips_macro_warning
.insns
[0]++;
4342 if (mips_relax
.sequence
!= 1)
4344 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4345 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4346 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4347 mips_macro_warning
.insns
[1]++;
4350 if (mips_opts
.mips16
)
4353 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4355 add_fixed_insn (ip
);
4358 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4360 bfd_reloc_code_real_type final_type
[3];
4361 reloc_howto_type
*howto0
;
4362 reloc_howto_type
*howto
;
4365 /* Perform any necessary conversion to microMIPS relocations
4366 and find out how many relocations there actually are. */
4367 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4368 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4370 /* In a compound relocation, it is the final (outermost)
4371 operator that determines the relocated field. */
4372 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4376 /* To reproduce this failure try assembling gas/testsuites/
4377 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4379 as_bad (_("Unsupported MIPS relocation number %d"),
4381 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4385 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4386 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4387 bfd_get_reloc_size (howto
),
4389 howto0
&& howto0
->pc_relative
,
4392 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4393 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4394 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4396 /* These relocations can have an addend that won't fit in
4397 4 octets for 64bit assembly. */
4399 && ! howto
->partial_inplace
4400 && (reloc_type
[0] == BFD_RELOC_16
4401 || reloc_type
[0] == BFD_RELOC_32
4402 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4403 || reloc_type
[0] == BFD_RELOC_GPREL16
4404 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4405 || reloc_type
[0] == BFD_RELOC_GPREL32
4406 || reloc_type
[0] == BFD_RELOC_64
4407 || reloc_type
[0] == BFD_RELOC_CTOR
4408 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4409 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4410 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4411 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4412 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4413 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4414 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4415 || hi16_reloc_p (reloc_type
[0])
4416 || lo16_reloc_p (reloc_type
[0])))
4417 ip
->fixp
[0]->fx_no_overflow
= 1;
4419 if (mips_relax
.sequence
)
4421 if (mips_relax
.first_fixup
== 0)
4422 mips_relax
.first_fixup
= ip
->fixp
[0];
4424 else if (reloc_needs_lo_p (*reloc_type
))
4426 struct mips_hi_fixup
*hi_fixup
;
4428 /* Reuse the last entry if it already has a matching %lo. */
4429 hi_fixup
= mips_hi_fixup_list
;
4431 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4433 hi_fixup
= ((struct mips_hi_fixup
*)
4434 xmalloc (sizeof (struct mips_hi_fixup
)));
4435 hi_fixup
->next
= mips_hi_fixup_list
;
4436 mips_hi_fixup_list
= hi_fixup
;
4438 hi_fixup
->fixp
= ip
->fixp
[0];
4439 hi_fixup
->seg
= now_seg
;
4442 /* Add fixups for the second and third relocations, if given.
4443 Note that the ABI allows the second relocation to be
4444 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4445 moment we only use RSS_UNDEF, but we could add support
4446 for the others if it ever becomes necessary. */
4447 for (i
= 1; i
< 3; i
++)
4448 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4450 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4451 ip
->fixp
[0]->fx_size
, NULL
, 0,
4452 FALSE
, final_type
[i
]);
4454 /* Use fx_tcbit to mark compound relocs. */
4455 ip
->fixp
[0]->fx_tcbit
= 1;
4456 ip
->fixp
[i
]->fx_tcbit
= 1;
4461 /* Update the register mask information. */
4462 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4463 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4468 insert_into_history (0, 1, ip
);
4471 case APPEND_ADD_WITH_NOP
:
4473 struct mips_cl_insn
*nop
;
4475 insert_into_history (0, 1, ip
);
4476 nop
= get_delay_slot_nop (ip
);
4477 add_fixed_insn (nop
);
4478 insert_into_history (0, 1, nop
);
4479 if (mips_relax
.sequence
)
4480 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4484 case APPEND_ADD_COMPACT
:
4485 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4486 gas_assert (mips_opts
.mips16
);
4487 ip
->insn_opcode
|= 0x0080;
4488 find_altered_mips16_opcode (ip
);
4490 insert_into_history (0, 1, ip
);
4495 struct mips_cl_insn delay
= history
[0];
4496 if (mips_opts
.mips16
)
4498 know (delay
.frag
== ip
->frag
);
4499 move_insn (ip
, delay
.frag
, delay
.where
);
4500 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4502 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4504 /* Add the delay slot instruction to the end of the
4505 current frag and shrink the fixed part of the
4506 original frag. If the branch occupies the tail of
4507 the latter, move it backwards to cover the gap. */
4508 delay
.frag
->fr_fix
-= branch_disp
;
4509 if (delay
.frag
== ip
->frag
)
4510 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4511 add_fixed_insn (&delay
);
4515 move_insn (&delay
, ip
->frag
,
4516 ip
->where
- branch_disp
+ insn_length (ip
));
4517 move_insn (ip
, history
[0].frag
, history
[0].where
);
4521 insert_into_history (0, 1, &delay
);
4526 /* If we have just completed an unconditional branch, clear the history. */
4527 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4528 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4529 mips_no_prev_insn ();
4531 /* We need to emit a label at the end of branch-likely macros. */
4532 if (emit_branch_likely_macro
)
4534 emit_branch_likely_macro
= FALSE
;
4535 micromips_add_label ();
4538 /* We just output an insn, so the next one doesn't have a label. */
4539 mips_clear_insn_labels ();
4542 /* Forget that there was any previous instruction or label. */
4545 mips_no_prev_insn (void)
4547 prev_nop_frag
= NULL
;
4548 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4549 mips_clear_insn_labels ();
4552 /* This function must be called before we emit something other than
4553 instructions. It is like mips_no_prev_insn except that it inserts
4554 any NOPS that might be needed by previous instructions. */
4557 mips_emit_delays (void)
4559 if (! mips_opts
.noreorder
)
4561 int nops
= nops_for_insn (0, history
, NULL
);
4565 add_fixed_insn (NOP_INSN
);
4566 mips_move_text_labels ();
4569 mips_no_prev_insn ();
4572 /* Start a (possibly nested) noreorder block. */
4575 start_noreorder (void)
4577 if (mips_opts
.noreorder
== 0)
4582 /* None of the instructions before the .set noreorder can be moved. */
4583 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4584 history
[i
].fixed_p
= 1;
4586 /* Insert any nops that might be needed between the .set noreorder
4587 block and the previous instructions. We will later remove any
4588 nops that turn out not to be needed. */
4589 nops
= nops_for_insn (0, history
, NULL
);
4592 if (mips_optimize
!= 0)
4594 /* Record the frag which holds the nop instructions, so
4595 that we can remove them if we don't need them. */
4596 frag_grow (nops
* NOP_INSN_SIZE
);
4597 prev_nop_frag
= frag_now
;
4598 prev_nop_frag_holds
= nops
;
4599 prev_nop_frag_required
= 0;
4600 prev_nop_frag_since
= 0;
4603 for (; nops
> 0; --nops
)
4604 add_fixed_insn (NOP_INSN
);
4606 /* Move on to a new frag, so that it is safe to simply
4607 decrease the size of prev_nop_frag. */
4608 frag_wane (frag_now
);
4610 mips_move_text_labels ();
4612 mips_mark_labels ();
4613 mips_clear_insn_labels ();
4615 mips_opts
.noreorder
++;
4616 mips_any_noreorder
= 1;
4619 /* End a nested noreorder block. */
4622 end_noreorder (void)
4624 mips_opts
.noreorder
--;
4625 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4627 /* Commit to inserting prev_nop_frag_required nops and go back to
4628 handling nop insertion the .set reorder way. */
4629 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4631 insert_into_history (prev_nop_frag_since
,
4632 prev_nop_frag_required
, NOP_INSN
);
4633 prev_nop_frag
= NULL
;
4637 /* Set up global variables for the start of a new macro. */
4642 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4643 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4644 sizeof (mips_macro_warning
.first_insn_sizes
));
4645 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4646 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4647 && delayed_branch_p (&history
[0]));
4648 switch (history
[0].insn_mo
->pinfo2
4649 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4651 case INSN2_BRANCH_DELAY_32BIT
:
4652 mips_macro_warning
.delay_slot_length
= 4;
4654 case INSN2_BRANCH_DELAY_16BIT
:
4655 mips_macro_warning
.delay_slot_length
= 2;
4658 mips_macro_warning
.delay_slot_length
= 0;
4661 mips_macro_warning
.first_frag
= NULL
;
4664 /* Given that a macro is longer than one instruction or of the wrong size,
4665 return the appropriate warning for it. Return null if no warning is
4666 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4667 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4668 and RELAX_NOMACRO. */
4671 macro_warning (relax_substateT subtype
)
4673 if (subtype
& RELAX_DELAY_SLOT
)
4674 return _("Macro instruction expanded into multiple instructions"
4675 " in a branch delay slot");
4676 else if (subtype
& RELAX_NOMACRO
)
4677 return _("Macro instruction expanded into multiple instructions");
4678 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4679 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4680 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4681 ? _("Macro instruction expanded into a wrong size instruction"
4682 " in a 16-bit branch delay slot")
4683 : _("Macro instruction expanded into a wrong size instruction"
4684 " in a 32-bit branch delay slot"));
4689 /* Finish up a macro. Emit warnings as appropriate. */
4694 /* Relaxation warning flags. */
4695 relax_substateT subtype
= 0;
4697 /* Check delay slot size requirements. */
4698 if (mips_macro_warning
.delay_slot_length
== 2)
4699 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4700 if (mips_macro_warning
.delay_slot_length
!= 0)
4702 if (mips_macro_warning
.delay_slot_length
4703 != mips_macro_warning
.first_insn_sizes
[0])
4704 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4705 if (mips_macro_warning
.delay_slot_length
4706 != mips_macro_warning
.first_insn_sizes
[1])
4707 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4710 /* Check instruction count requirements. */
4711 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4713 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4714 subtype
|= RELAX_SECOND_LONGER
;
4715 if (mips_opts
.warn_about_macros
)
4716 subtype
|= RELAX_NOMACRO
;
4717 if (mips_macro_warning
.delay_slot_p
)
4718 subtype
|= RELAX_DELAY_SLOT
;
4721 /* If both alternatives fail to fill a delay slot correctly,
4722 emit the warning now. */
4723 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4724 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4729 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4730 | RELAX_DELAY_SLOT_SIZE_FIRST
4731 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4732 msg
= macro_warning (s
);
4734 as_warn ("%s", msg
);
4738 /* If both implementations are longer than 1 instruction, then emit the
4740 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4745 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4746 msg
= macro_warning (s
);
4748 as_warn ("%s", msg
);
4752 /* If any flags still set, then one implementation might need a warning
4753 and the other either will need one of a different kind or none at all.
4754 Pass any remaining flags over to relaxation. */
4755 if (mips_macro_warning
.first_frag
!= NULL
)
4756 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4759 /* Instruction operand formats used in macros that vary between
4760 standard MIPS and microMIPS code. */
4762 static const char * const brk_fmt
[2] = { "c", "mF" };
4763 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4764 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4765 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4766 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4767 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4768 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4769 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4771 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4772 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4773 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4774 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4775 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4776 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4777 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4778 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4780 /* Read a macro's relocation codes from *ARGS and store them in *R.
4781 The first argument in *ARGS will be either the code for a single
4782 relocation or -1 followed by the three codes that make up a
4783 composite relocation. */
4786 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4790 next
= va_arg (*args
, int);
4792 r
[0] = (bfd_reloc_code_real_type
) next
;
4794 for (i
= 0; i
< 3; i
++)
4795 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4798 /* Build an instruction created by a macro expansion. This is passed
4799 a pointer to the count of instructions created so far, an
4800 expression, the name of the instruction to build, an operand format
4801 string, and corresponding arguments. */
4804 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4806 const struct mips_opcode
*mo
= NULL
;
4807 bfd_reloc_code_real_type r
[3];
4808 const struct mips_opcode
*amo
;
4809 struct hash_control
*hash
;
4810 struct mips_cl_insn insn
;
4813 va_start (args
, fmt
);
4815 if (mips_opts
.mips16
)
4817 mips16_macro_build (ep
, name
, fmt
, &args
);
4822 r
[0] = BFD_RELOC_UNUSED
;
4823 r
[1] = BFD_RELOC_UNUSED
;
4824 r
[2] = BFD_RELOC_UNUSED
;
4825 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4826 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4828 gas_assert (strcmp (name
, amo
->name
) == 0);
4832 /* Search until we get a match for NAME. It is assumed here that
4833 macros will never generate MDMX, MIPS-3D, or MT instructions.
4834 We try to match an instruction that fulfils the branch delay
4835 slot instruction length requirement (if any) of the previous
4836 instruction. While doing this we record the first instruction
4837 seen that matches all the other conditions and use it anyway
4838 if the requirement cannot be met; we will issue an appropriate
4839 warning later on. */
4840 if (strcmp (fmt
, amo
->args
) == 0
4841 && amo
->pinfo
!= INSN_MACRO
4842 && is_opcode_valid (amo
)
4843 && is_size_valid (amo
))
4845 if (is_delay_slot_valid (amo
))
4855 gas_assert (amo
->name
);
4857 while (strcmp (name
, amo
->name
) == 0);
4860 create_insn (&insn
, mo
);
4878 INSERT_OPERAND (mips_opts
.micromips
,
4879 EXTLSB
, insn
, va_arg (args
, int));
4884 /* Note that in the macro case, these arguments are already
4885 in MSB form. (When handling the instruction in the
4886 non-macro case, these arguments are sizes from which
4887 MSB values must be calculated.) */
4888 INSERT_OPERAND (mips_opts
.micromips
,
4889 INSMSB
, insn
, va_arg (args
, int));
4895 /* Note that in the macro case, these arguments are already
4896 in MSBD form. (When handling the instruction in the
4897 non-macro case, these arguments are sizes from which
4898 MSBD values must be calculated.) */
4899 INSERT_OPERAND (mips_opts
.micromips
,
4900 EXTMSBD
, insn
, va_arg (args
, int));
4904 gas_assert (!mips_opts
.micromips
);
4905 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
4914 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
4918 gas_assert (mips_opts
.micromips
);
4922 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
4926 gas_assert (!mips_opts
.micromips
);
4927 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
4931 gas_assert (!mips_opts
.micromips
);
4933 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
4937 if (mips_opts
.micromips
)
4938 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
4940 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
4944 gas_assert (!mips_opts
.micromips
);
4946 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
4950 gas_assert (!mips_opts
.micromips
);
4952 int tmp
= va_arg (args
, int);
4954 INSERT_OPERAND (0, RT
, insn
, tmp
);
4955 INSERT_OPERAND (0, RD
, insn
, tmp
);
4961 gas_assert (!mips_opts
.micromips
);
4962 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
4969 INSERT_OPERAND (mips_opts
.micromips
,
4970 SHAMT
, insn
, va_arg (args
, int));
4974 gas_assert (!mips_opts
.micromips
);
4975 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
4979 gas_assert (!mips_opts
.micromips
);
4980 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
4984 gas_assert (!mips_opts
.micromips
);
4985 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
4989 gas_assert (!mips_opts
.micromips
);
4990 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
4997 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5002 macro_read_relocs (&args
, r
);
5003 gas_assert (*r
== BFD_RELOC_GPREL16
5004 || *r
== BFD_RELOC_MIPS_HIGHER
5005 || *r
== BFD_RELOC_HI16_S
5006 || *r
== BFD_RELOC_LO16
5007 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5011 macro_read_relocs (&args
, r
);
5015 macro_read_relocs (&args
, r
);
5016 gas_assert (ep
!= NULL
5017 && (ep
->X_op
== O_constant
5018 || (ep
->X_op
== O_symbol
5019 && (*r
== BFD_RELOC_MIPS_HIGHEST
5020 || *r
== BFD_RELOC_HI16_S
5021 || *r
== BFD_RELOC_HI16
5022 || *r
== BFD_RELOC_GPREL16
5023 || *r
== BFD_RELOC_MIPS_GOT_HI16
5024 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5028 gas_assert (ep
!= NULL
);
5031 * This allows macro() to pass an immediate expression for
5032 * creating short branches without creating a symbol.
5034 * We don't allow branch relaxation for these branches, as
5035 * they should only appear in ".set nomacro" anyway.
5037 if (ep
->X_op
== O_constant
)
5039 /* For microMIPS we always use relocations for branches.
5040 So we should not resolve immediate values. */
5041 gas_assert (!mips_opts
.micromips
);
5043 if ((ep
->X_add_number
& 3) != 0)
5044 as_bad (_("branch to misaligned address (0x%lx)"),
5045 (unsigned long) ep
->X_add_number
);
5046 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5047 as_bad (_("branch address range overflow (0x%lx)"),
5048 (unsigned long) ep
->X_add_number
);
5049 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5053 *r
= BFD_RELOC_16_PCREL_S2
;
5057 gas_assert (ep
!= NULL
);
5058 *r
= BFD_RELOC_MIPS_JMP
;
5062 gas_assert (!mips_opts
.micromips
);
5063 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5067 INSERT_OPERAND (mips_opts
.micromips
,
5068 CACHE
, insn
, va_arg (args
, unsigned long));
5072 gas_assert (mips_opts
.micromips
);
5073 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5077 gas_assert (mips_opts
.micromips
);
5078 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5082 INSERT_OPERAND (mips_opts
.micromips
,
5083 3BITPOS
, insn
, va_arg (args
, unsigned int));
5087 INSERT_OPERAND (mips_opts
.micromips
,
5088 OFFSET12
, insn
, va_arg (args
, unsigned long));
5092 gas_assert (mips_opts
.micromips
);
5093 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5096 case 'm': /* Opcode extension character. */
5097 gas_assert (mips_opts
.micromips
);
5101 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5105 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5109 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5123 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5125 append_insn (&insn
, ep
, r
, TRUE
);
5129 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5132 struct mips_opcode
*mo
;
5133 struct mips_cl_insn insn
;
5134 bfd_reloc_code_real_type r
[3]
5135 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5137 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5139 gas_assert (strcmp (name
, mo
->name
) == 0);
5141 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5144 gas_assert (mo
->name
);
5145 gas_assert (strcmp (name
, mo
->name
) == 0);
5148 create_insn (&insn
, mo
);
5166 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5171 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5175 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5179 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5189 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5196 regno
= va_arg (*args
, int);
5197 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5198 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5219 gas_assert (ep
!= NULL
);
5221 if (ep
->X_op
!= O_constant
)
5222 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5225 mips16_immed (NULL
, 0, c
, ep
->X_add_number
,
5226 0, &insn
.insn_opcode
);
5228 *r
= BFD_RELOC_UNUSED
;
5234 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5241 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5243 append_insn (&insn
, ep
, r
, TRUE
);
5247 * Sign-extend 32-bit mode constants that have bit 31 set and all
5248 * higher bits unset.
5251 normalize_constant_expr (expressionS
*ex
)
5253 if (ex
->X_op
== O_constant
5254 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5255 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5260 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5261 * all higher bits unset.
5264 normalize_address_expr (expressionS
*ex
)
5266 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5267 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5268 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5269 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5274 * Generate a "jalr" instruction with a relocation hint to the called
5275 * function. This occurs in NewABI PIC code.
5278 macro_build_jalr (expressionS
*ep
, int cprestore
)
5280 static const bfd_reloc_code_real_type jalr_relocs
[2]
5281 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5282 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5286 if (MIPS_JALR_HINT_P (ep
))
5291 if (mips_opts
.micromips
)
5293 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5294 if (MIPS_JALR_HINT_P (ep
))
5295 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5297 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5300 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5301 if (MIPS_JALR_HINT_P (ep
))
5302 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5306 * Generate a "lui" instruction.
5309 macro_build_lui (expressionS
*ep
, int regnum
)
5311 gas_assert (! mips_opts
.mips16
);
5313 if (ep
->X_op
!= O_constant
)
5315 gas_assert (ep
->X_op
== O_symbol
);
5316 /* _gp_disp is a special case, used from s_cpload.
5317 __gnu_local_gp is used if mips_no_shared. */
5318 gas_assert (mips_pic
== NO_PIC
5320 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5321 || (! mips_in_shared
5322 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5323 "__gnu_local_gp") == 0));
5326 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5329 /* Generate a sequence of instructions to do a load or store from a constant
5330 offset off of a base register (breg) into/from a target register (treg),
5331 using AT if necessary. */
5333 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5334 int treg
, int breg
, int dbl
)
5336 gas_assert (ep
->X_op
== O_constant
);
5338 /* Sign-extending 32-bit constants makes their handling easier. */
5340 normalize_constant_expr (ep
);
5342 /* Right now, this routine can only handle signed 32-bit constants. */
5343 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5344 as_warn (_("operand overflow"));
5346 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5348 /* Signed 16-bit offset will fit in the op. Easy! */
5349 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5353 /* 32-bit offset, need multiple instructions and AT, like:
5354 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5355 addu $tempreg,$tempreg,$breg
5356 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5357 to handle the complete offset. */
5358 macro_build_lui (ep
, AT
);
5359 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5360 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5363 as_bad (_("Macro used $at after \".set noat\""));
5368 * Generates code to set the $at register to true (one)
5369 * if reg is less than the immediate expression.
5372 set_at (int reg
, int unsignedp
)
5374 if (imm_expr
.X_op
== O_constant
5375 && imm_expr
.X_add_number
>= -0x8000
5376 && imm_expr
.X_add_number
< 0x8000)
5377 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5378 AT
, reg
, BFD_RELOC_LO16
);
5381 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5382 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5386 /* Warn if an expression is not a constant. */
5389 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5391 if (ex
->X_op
== O_big
)
5392 as_bad (_("unsupported large constant"));
5393 else if (ex
->X_op
!= O_constant
)
5394 as_bad (_("Instruction %s requires absolute expression"),
5397 if (HAVE_32BIT_GPRS
)
5398 normalize_constant_expr (ex
);
5401 /* Count the leading zeroes by performing a binary chop. This is a
5402 bulky bit of source, but performance is a LOT better for the
5403 majority of values than a simple loop to count the bits:
5404 for (lcnt = 0; (lcnt < 32); lcnt++)
5405 if ((v) & (1 << (31 - lcnt)))
5407 However it is not code size friendly, and the gain will drop a bit
5408 on certain cached systems.
5410 #define COUNT_TOP_ZEROES(v) \
5411 (((v) & ~0xffff) == 0 \
5412 ? ((v) & ~0xff) == 0 \
5413 ? ((v) & ~0xf) == 0 \
5414 ? ((v) & ~0x3) == 0 \
5415 ? ((v) & ~0x1) == 0 \
5420 : ((v) & ~0x7) == 0 \
5423 : ((v) & ~0x3f) == 0 \
5424 ? ((v) & ~0x1f) == 0 \
5427 : ((v) & ~0x7f) == 0 \
5430 : ((v) & ~0xfff) == 0 \
5431 ? ((v) & ~0x3ff) == 0 \
5432 ? ((v) & ~0x1ff) == 0 \
5435 : ((v) & ~0x7ff) == 0 \
5438 : ((v) & ~0x3fff) == 0 \
5439 ? ((v) & ~0x1fff) == 0 \
5442 : ((v) & ~0x7fff) == 0 \
5445 : ((v) & ~0xffffff) == 0 \
5446 ? ((v) & ~0xfffff) == 0 \
5447 ? ((v) & ~0x3ffff) == 0 \
5448 ? ((v) & ~0x1ffff) == 0 \
5451 : ((v) & ~0x7ffff) == 0 \
5454 : ((v) & ~0x3fffff) == 0 \
5455 ? ((v) & ~0x1fffff) == 0 \
5458 : ((v) & ~0x7fffff) == 0 \
5461 : ((v) & ~0xfffffff) == 0 \
5462 ? ((v) & ~0x3ffffff) == 0 \
5463 ? ((v) & ~0x1ffffff) == 0 \
5466 : ((v) & ~0x7ffffff) == 0 \
5469 : ((v) & ~0x3fffffff) == 0 \
5470 ? ((v) & ~0x1fffffff) == 0 \
5473 : ((v) & ~0x7fffffff) == 0 \
5478 * This routine generates the least number of instructions necessary to load
5479 * an absolute expression value into a register.
5482 load_register (int reg
, expressionS
*ep
, int dbl
)
5485 expressionS hi32
, lo32
;
5487 if (ep
->X_op
!= O_big
)
5489 gas_assert (ep
->X_op
== O_constant
);
5491 /* Sign-extending 32-bit constants makes their handling easier. */
5493 normalize_constant_expr (ep
);
5495 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5497 /* We can handle 16 bit signed values with an addiu to
5498 $zero. No need to ever use daddiu here, since $zero and
5499 the result are always correct in 32 bit mode. */
5500 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5503 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5505 /* We can handle 16 bit unsigned values with an ori to
5507 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5510 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5512 /* 32 bit values require an lui. */
5513 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5514 if ((ep
->X_add_number
& 0xffff) != 0)
5515 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5520 /* The value is larger than 32 bits. */
5522 if (!dbl
|| HAVE_32BIT_GPRS
)
5526 sprintf_vma (value
, ep
->X_add_number
);
5527 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5528 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5532 if (ep
->X_op
!= O_big
)
5535 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5536 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5537 hi32
.X_add_number
&= 0xffffffff;
5539 lo32
.X_add_number
&= 0xffffffff;
5543 gas_assert (ep
->X_add_number
> 2);
5544 if (ep
->X_add_number
== 3)
5545 generic_bignum
[3] = 0;
5546 else if (ep
->X_add_number
> 4)
5547 as_bad (_("Number larger than 64 bits"));
5548 lo32
.X_op
= O_constant
;
5549 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5550 hi32
.X_op
= O_constant
;
5551 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5554 if (hi32
.X_add_number
== 0)
5559 unsigned long hi
, lo
;
5561 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5563 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5565 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5568 if (lo32
.X_add_number
& 0x80000000)
5570 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5571 if (lo32
.X_add_number
& 0xffff)
5572 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5577 /* Check for 16bit shifted constant. We know that hi32 is
5578 non-zero, so start the mask on the first bit of the hi32
5583 unsigned long himask
, lomask
;
5587 himask
= 0xffff >> (32 - shift
);
5588 lomask
= (0xffff << shift
) & 0xffffffff;
5592 himask
= 0xffff << (shift
- 32);
5595 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5596 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5600 tmp
.X_op
= O_constant
;
5602 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5603 | (lo32
.X_add_number
>> shift
));
5605 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5606 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5607 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5608 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5613 while (shift
<= (64 - 16));
5615 /* Find the bit number of the lowest one bit, and store the
5616 shifted value in hi/lo. */
5617 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5618 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5622 while ((lo
& 1) == 0)
5627 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5633 while ((hi
& 1) == 0)
5642 /* Optimize if the shifted value is a (power of 2) - 1. */
5643 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5644 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5646 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5651 /* This instruction will set the register to be all
5653 tmp
.X_op
= O_constant
;
5654 tmp
.X_add_number
= (offsetT
) -1;
5655 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5659 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5660 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5662 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5663 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5668 /* Sign extend hi32 before calling load_register, because we can
5669 generally get better code when we load a sign extended value. */
5670 if ((hi32
.X_add_number
& 0x80000000) != 0)
5671 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5672 load_register (reg
, &hi32
, 0);
5675 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5679 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5687 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5689 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5690 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5696 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5700 mid16
.X_add_number
>>= 16;
5701 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5702 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5705 if ((lo32
.X_add_number
& 0xffff) != 0)
5706 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5710 load_delay_nop (void)
5712 if (!gpr_interlocks
)
5713 macro_build (NULL
, "nop", "");
5716 /* Load an address into a register. */
5719 load_address (int reg
, expressionS
*ep
, int *used_at
)
5721 if (ep
->X_op
!= O_constant
5722 && ep
->X_op
!= O_symbol
)
5724 as_bad (_("expression too complex"));
5725 ep
->X_op
= O_constant
;
5728 if (ep
->X_op
== O_constant
)
5730 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5734 if (mips_pic
== NO_PIC
)
5736 /* If this is a reference to a GP relative symbol, we want
5737 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5739 lui $reg,<sym> (BFD_RELOC_HI16_S)
5740 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5741 If we have an addend, we always use the latter form.
5743 With 64bit address space and a usable $at we want
5744 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5745 lui $at,<sym> (BFD_RELOC_HI16_S)
5746 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5747 daddiu $at,<sym> (BFD_RELOC_LO16)
5751 If $at is already in use, we use a path which is suboptimal
5752 on superscalar processors.
5753 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5754 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5756 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5758 daddiu $reg,<sym> (BFD_RELOC_LO16)
5760 For GP relative symbols in 64bit address space we can use
5761 the same sequence as in 32bit address space. */
5762 if (HAVE_64BIT_SYMBOLS
)
5764 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5765 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5767 relax_start (ep
->X_add_symbol
);
5768 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5769 mips_gp_register
, BFD_RELOC_GPREL16
);
5773 if (*used_at
== 0 && mips_opts
.at
)
5775 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5776 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5777 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5778 BFD_RELOC_MIPS_HIGHER
);
5779 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5780 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5781 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5786 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5787 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5788 BFD_RELOC_MIPS_HIGHER
);
5789 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5790 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5791 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5792 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5795 if (mips_relax
.sequence
)
5800 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5801 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5803 relax_start (ep
->X_add_symbol
);
5804 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5805 mips_gp_register
, BFD_RELOC_GPREL16
);
5808 macro_build_lui (ep
, reg
);
5809 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5810 reg
, reg
, BFD_RELOC_LO16
);
5811 if (mips_relax
.sequence
)
5815 else if (!mips_big_got
)
5819 /* If this is a reference to an external symbol, we want
5820 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5822 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5824 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5825 If there is a constant, it must be added in after.
5827 If we have NewABI, we want
5828 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5829 unless we're referencing a global symbol with a non-zero
5830 offset, in which case cst must be added separately. */
5833 if (ep
->X_add_number
)
5835 ex
.X_add_number
= ep
->X_add_number
;
5836 ep
->X_add_number
= 0;
5837 relax_start (ep
->X_add_symbol
);
5838 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5839 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5840 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5841 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5842 ex
.X_op
= O_constant
;
5843 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5844 reg
, reg
, BFD_RELOC_LO16
);
5845 ep
->X_add_number
= ex
.X_add_number
;
5848 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5849 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5850 if (mips_relax
.sequence
)
5855 ex
.X_add_number
= ep
->X_add_number
;
5856 ep
->X_add_number
= 0;
5857 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5858 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5860 relax_start (ep
->X_add_symbol
);
5862 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5866 if (ex
.X_add_number
!= 0)
5868 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5869 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5870 ex
.X_op
= O_constant
;
5871 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5872 reg
, reg
, BFD_RELOC_LO16
);
5876 else if (mips_big_got
)
5880 /* This is the large GOT case. If this is a reference to an
5881 external symbol, we want
5882 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5884 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5886 Otherwise, for a reference to a local symbol in old ABI, we want
5887 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5889 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5890 If there is a constant, it must be added in after.
5892 In the NewABI, for local symbols, with or without offsets, we want:
5893 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5894 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5898 ex
.X_add_number
= ep
->X_add_number
;
5899 ep
->X_add_number
= 0;
5900 relax_start (ep
->X_add_symbol
);
5901 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5902 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5903 reg
, reg
, mips_gp_register
);
5904 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5905 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5906 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5907 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5908 else if (ex
.X_add_number
)
5910 ex
.X_op
= O_constant
;
5911 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5915 ep
->X_add_number
= ex
.X_add_number
;
5917 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5918 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5919 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5920 BFD_RELOC_MIPS_GOT_OFST
);
5925 ex
.X_add_number
= ep
->X_add_number
;
5926 ep
->X_add_number
= 0;
5927 relax_start (ep
->X_add_symbol
);
5928 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
5929 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5930 reg
, reg
, mips_gp_register
);
5931 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
5932 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
5934 if (reg_needs_delay (mips_gp_register
))
5936 /* We need a nop before loading from $gp. This special
5937 check is required because the lui which starts the main
5938 instruction stream does not refer to $gp, and so will not
5939 insert the nop which may be required. */
5940 macro_build (NULL
, "nop", "");
5942 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5943 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5945 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5949 if (ex
.X_add_number
!= 0)
5951 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5952 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5953 ex
.X_op
= O_constant
;
5954 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
5962 if (!mips_opts
.at
&& *used_at
== 1)
5963 as_bad (_("Macro used $at after \".set noat\""));
5966 /* Move the contents of register SOURCE into register DEST. */
5969 move_register (int dest
, int source
)
5971 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5972 instruction specifically requires a 32-bit one. */
5973 if (mips_opts
.micromips
5974 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5975 macro_build (NULL
, "move", "mp,mj", dest
, source
);
5977 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
5981 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5982 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5983 The two alternatives are:
5985 Global symbol Local sybmol
5986 ------------- ------------
5987 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5989 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5991 load_got_offset emits the first instruction and add_got_offset
5992 emits the second for a 16-bit offset or add_got_offset_hilo emits
5993 a sequence to add a 32-bit offset using a scratch register. */
5996 load_got_offset (int dest
, expressionS
*local
)
6001 global
.X_add_number
= 0;
6003 relax_start (local
->X_add_symbol
);
6004 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6005 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6007 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6008 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6013 add_got_offset (int dest
, expressionS
*local
)
6017 global
.X_op
= O_constant
;
6018 global
.X_op_symbol
= NULL
;
6019 global
.X_add_symbol
= NULL
;
6020 global
.X_add_number
= local
->X_add_number
;
6022 relax_start (local
->X_add_symbol
);
6023 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6024 dest
, dest
, BFD_RELOC_LO16
);
6026 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6031 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6034 int hold_mips_optimize
;
6036 global
.X_op
= O_constant
;
6037 global
.X_op_symbol
= NULL
;
6038 global
.X_add_symbol
= NULL
;
6039 global
.X_add_number
= local
->X_add_number
;
6041 relax_start (local
->X_add_symbol
);
6042 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6044 /* Set mips_optimize around the lui instruction to avoid
6045 inserting an unnecessary nop after the lw. */
6046 hold_mips_optimize
= mips_optimize
;
6048 macro_build_lui (&global
, tmp
);
6049 mips_optimize
= hold_mips_optimize
;
6050 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6053 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6056 /* Emit a sequence of instructions to emulate a branch likely operation.
6057 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6058 is its complementing branch with the original condition negated.
6059 CALL is set if the original branch specified the link operation.
6060 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6062 Code like this is produced in the noreorder mode:
6067 delay slot (executed only if branch taken)
6075 delay slot (executed only if branch taken)
6078 In the reorder mode the delay slot would be filled with a nop anyway,
6079 so code produced is simply:
6084 This function is used when producing code for the microMIPS ASE that
6085 does not implement branch likely instructions in hardware. */
6088 macro_build_branch_likely (const char *br
, const char *brneg
,
6089 int call
, expressionS
*ep
, const char *fmt
,
6090 unsigned int sreg
, unsigned int treg
)
6092 int noreorder
= mips_opts
.noreorder
;
6095 gas_assert (mips_opts
.micromips
);
6099 micromips_label_expr (&expr1
);
6100 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6101 macro_build (NULL
, "nop", "");
6102 macro_build (ep
, call
? "bal" : "b", "p");
6104 /* Set to true so that append_insn adds a label. */
6105 emit_branch_likely_macro
= TRUE
;
6109 macro_build (ep
, br
, fmt
, sreg
, treg
);
6110 macro_build (NULL
, "nop", "");
6115 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6116 the condition code tested. EP specifies the branch target. */
6119 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6146 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6149 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6150 the register tested. EP specifies the branch target. */
6153 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6155 const char *brneg
= NULL
;
6165 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6169 gas_assert (mips_opts
.micromips
);
6178 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6185 br
= mips_opts
.micromips
? "blez" : "blezl";
6192 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6196 gas_assert (mips_opts
.micromips
);
6204 if (mips_opts
.micromips
&& brneg
)
6205 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6207 macro_build (ep
, br
, "s,p", sreg
);
6210 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6211 TREG as the registers tested. EP specifies the branch target. */
6214 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6215 unsigned int sreg
, unsigned int treg
)
6217 const char *brneg
= NULL
;
6229 br
= mips_opts
.micromips
? "beq" : "beql";
6238 br
= mips_opts
.micromips
? "bne" : "bnel";
6244 if (mips_opts
.micromips
&& brneg
)
6245 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6247 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6252 * This routine implements the seemingly endless macro or synthesized
6253 * instructions and addressing modes in the mips assembly language. Many
6254 * of these macros are simple and are similar to each other. These could
6255 * probably be handled by some kind of table or grammar approach instead of
6256 * this verbose method. Others are not simple macros but are more like
6257 * optimizing code generation.
6258 * One interesting optimization is when several store macros appear
6259 * consecutively that would load AT with the upper half of the same address.
6260 * The ensuing load upper instructions are ommited. This implies some kind
6261 * of global optimization. We currently only optimize within a single macro.
6262 * For many of the load and store macros if the address is specified as a
6263 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6264 * first load register 'at' with zero and use it as the base register. The
6265 * mips assembler simply uses register $zero. Just one tiny optimization
6269 macro (struct mips_cl_insn
*ip
)
6271 unsigned int treg
, sreg
, dreg
, breg
;
6272 unsigned int tempreg
;
6275 expressionS label_expr
;
6294 bfd_reloc_code_real_type r
;
6295 int hold_mips_optimize
;
6297 gas_assert (! mips_opts
.mips16
);
6299 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6300 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6301 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6302 mask
= ip
->insn_mo
->mask
;
6304 label_expr
.X_op
= O_constant
;
6305 label_expr
.X_op_symbol
= NULL
;
6306 label_expr
.X_add_symbol
= NULL
;
6307 label_expr
.X_add_number
= 0;
6309 expr1
.X_op
= O_constant
;
6310 expr1
.X_op_symbol
= NULL
;
6311 expr1
.X_add_symbol
= NULL
;
6312 expr1
.X_add_number
= 1;
6327 if (mips_opts
.micromips
)
6328 micromips_label_expr (&label_expr
);
6330 label_expr
.X_add_number
= 8;
6331 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6333 macro_build (NULL
, "nop", "");
6335 move_register (dreg
, sreg
);
6336 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6337 if (mips_opts
.micromips
)
6338 micromips_add_label ();
6355 if (!mips_opts
.micromips
)
6357 if (imm_expr
.X_op
== O_constant
6358 && imm_expr
.X_add_number
>= -0x200
6359 && imm_expr
.X_add_number
< 0x200)
6361 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6370 if (imm_expr
.X_op
== O_constant
6371 && imm_expr
.X_add_number
>= -0x8000
6372 && imm_expr
.X_add_number
< 0x8000)
6374 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6379 load_register (AT
, &imm_expr
, dbl
);
6380 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6399 if (imm_expr
.X_op
== O_constant
6400 && imm_expr
.X_add_number
>= 0
6401 && imm_expr
.X_add_number
< 0x10000)
6403 if (mask
!= M_NOR_I
)
6404 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6407 macro_build (&imm_expr
, "ori", "t,r,i",
6408 treg
, sreg
, BFD_RELOC_LO16
);
6409 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6415 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6416 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6420 switch (imm_expr
.X_add_number
)
6423 macro_build (NULL
, "nop", "");
6426 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6430 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6431 (int) imm_expr
.X_add_number
);
6434 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6435 (unsigned long) imm_expr
.X_add_number
);
6444 gas_assert (mips_opts
.micromips
);
6445 macro_build_branch_ccl (mask
, &offset_expr
,
6446 EXTRACT_OPERAND (1, BCC
, *ip
));
6453 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6459 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6464 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6471 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6473 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6477 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6478 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6479 &offset_expr
, AT
, ZERO
);
6489 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6495 /* Check for > max integer. */
6496 maxnum
= 0x7fffffff;
6497 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6504 if (imm_expr
.X_op
== O_constant
6505 && imm_expr
.X_add_number
>= maxnum
6506 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6509 /* Result is always false. */
6511 macro_build (NULL
, "nop", "");
6513 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6516 if (imm_expr
.X_op
!= O_constant
)
6517 as_bad (_("Unsupported large constant"));
6518 ++imm_expr
.X_add_number
;
6522 if (mask
== M_BGEL_I
)
6524 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6526 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6527 &offset_expr
, sreg
);
6530 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6532 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6533 &offset_expr
, sreg
);
6536 maxnum
= 0x7fffffff;
6537 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6544 maxnum
= - maxnum
- 1;
6545 if (imm_expr
.X_op
== O_constant
6546 && imm_expr
.X_add_number
<= maxnum
6547 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6550 /* result is always true */
6551 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6552 macro_build (&offset_expr
, "b", "p");
6557 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6558 &offset_expr
, AT
, ZERO
);
6567 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6568 &offset_expr
, ZERO
, treg
);
6572 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6573 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6574 &offset_expr
, AT
, ZERO
);
6583 && imm_expr
.X_op
== O_constant
6584 && imm_expr
.X_add_number
== -1))
6586 if (imm_expr
.X_op
!= O_constant
)
6587 as_bad (_("Unsupported large constant"));
6588 ++imm_expr
.X_add_number
;
6592 if (mask
== M_BGEUL_I
)
6594 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6596 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6597 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6598 &offset_expr
, sreg
, ZERO
);
6603 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6604 &offset_expr
, AT
, ZERO
);
6612 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6614 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6618 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6619 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6620 &offset_expr
, AT
, ZERO
);
6628 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6629 &offset_expr
, sreg
, ZERO
);
6635 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6636 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6637 &offset_expr
, AT
, ZERO
);
6645 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6647 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6651 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6652 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6653 &offset_expr
, AT
, ZERO
);
6660 maxnum
= 0x7fffffff;
6661 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6668 if (imm_expr
.X_op
== O_constant
6669 && imm_expr
.X_add_number
>= maxnum
6670 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6672 if (imm_expr
.X_op
!= O_constant
)
6673 as_bad (_("Unsupported large constant"));
6674 ++imm_expr
.X_add_number
;
6678 if (mask
== M_BLTL_I
)
6680 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6681 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6682 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6683 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6688 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6689 &offset_expr
, AT
, ZERO
);
6697 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6698 &offset_expr
, sreg
, ZERO
);
6704 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6705 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6706 &offset_expr
, AT
, ZERO
);
6715 && imm_expr
.X_op
== O_constant
6716 && imm_expr
.X_add_number
== -1))
6718 if (imm_expr
.X_op
!= O_constant
)
6719 as_bad (_("Unsupported large constant"));
6720 ++imm_expr
.X_add_number
;
6724 if (mask
== M_BLTUL_I
)
6726 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6728 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6729 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6730 &offset_expr
, sreg
, ZERO
);
6735 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6736 &offset_expr
, AT
, ZERO
);
6744 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6746 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6750 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6751 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6752 &offset_expr
, AT
, ZERO
);
6762 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6763 &offset_expr
, ZERO
, treg
);
6767 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6768 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6769 &offset_expr
, AT
, ZERO
);
6775 /* Use unsigned arithmetic. */
6779 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6781 as_bad (_("Unsupported large constant"));
6786 pos
= imm_expr
.X_add_number
;
6787 size
= imm2_expr
.X_add_number
;
6792 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6795 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6797 as_bad (_("Improper extract size (%lu, position %lu)"),
6798 (unsigned long) size
, (unsigned long) pos
);
6802 if (size
<= 32 && pos
< 32)
6807 else if (size
<= 32)
6817 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6824 /* Use unsigned arithmetic. */
6828 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6830 as_bad (_("Unsupported large constant"));
6835 pos
= imm_expr
.X_add_number
;
6836 size
= imm2_expr
.X_add_number
;
6841 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6844 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6846 as_bad (_("Improper insert size (%lu, position %lu)"),
6847 (unsigned long) size
, (unsigned long) pos
);
6851 if (pos
< 32 && (pos
+ size
- 1) < 32)
6866 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6867 (int) (pos
+ size
- 1));
6883 as_warn (_("Divide by zero."));
6885 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6887 macro_build (NULL
, "break", BRK_FMT
, 7);
6894 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
6895 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6899 if (mips_opts
.micromips
)
6900 micromips_label_expr (&label_expr
);
6902 label_expr
.X_add_number
= 8;
6903 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
6904 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
6905 macro_build (NULL
, "break", BRK_FMT
, 7);
6906 if (mips_opts
.micromips
)
6907 micromips_add_label ();
6909 expr1
.X_add_number
= -1;
6911 load_register (AT
, &expr1
, dbl
);
6912 if (mips_opts
.micromips
)
6913 micromips_label_expr (&label_expr
);
6915 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
6916 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
6919 expr1
.X_add_number
= 1;
6920 load_register (AT
, &expr1
, dbl
);
6921 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
6925 expr1
.X_add_number
= 0x80000000;
6926 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
6930 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
6931 /* We want to close the noreorder block as soon as possible, so
6932 that later insns are available for delay slot filling. */
6937 if (mips_opts
.micromips
)
6938 micromips_label_expr (&label_expr
);
6940 label_expr
.X_add_number
= 8;
6941 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
6942 macro_build (NULL
, "nop", "");
6944 /* We want to close the noreorder block as soon as possible, so
6945 that later insns are available for delay slot filling. */
6948 macro_build (NULL
, "break", BRK_FMT
, 6);
6950 if (mips_opts
.micromips
)
6951 micromips_add_label ();
6952 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
6991 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6993 as_warn (_("Divide by zero."));
6995 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
6997 macro_build (NULL
, "break", BRK_FMT
, 7);
7000 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7002 if (strcmp (s2
, "mflo") == 0)
7003 move_register (dreg
, sreg
);
7005 move_register (dreg
, ZERO
);
7008 if (imm_expr
.X_op
== O_constant
7009 && imm_expr
.X_add_number
== -1
7010 && s
[strlen (s
) - 1] != 'u')
7012 if (strcmp (s2
, "mflo") == 0)
7014 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7017 move_register (dreg
, ZERO
);
7022 load_register (AT
, &imm_expr
, dbl
);
7023 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7024 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7046 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7047 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7048 /* We want to close the noreorder block as soon as possible, so
7049 that later insns are available for delay slot filling. */
7054 if (mips_opts
.micromips
)
7055 micromips_label_expr (&label_expr
);
7057 label_expr
.X_add_number
= 8;
7058 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7059 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7061 /* We want to close the noreorder block as soon as possible, so
7062 that later insns are available for delay slot filling. */
7064 macro_build (NULL
, "break", BRK_FMT
, 7);
7065 if (mips_opts
.micromips
)
7066 micromips_add_label ();
7068 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7080 /* Load the address of a symbol into a register. If breg is not
7081 zero, we then add a base register to it. */
7083 if (dbl
&& HAVE_32BIT_GPRS
)
7084 as_warn (_("dla used to load 32-bit register"));
7086 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7087 as_warn (_("la used to load 64-bit address"));
7089 if (offset_expr
.X_op
== O_constant
7090 && offset_expr
.X_add_number
>= -0x8000
7091 && offset_expr
.X_add_number
< 0x8000)
7093 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7094 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7098 if (mips_opts
.at
&& (treg
== breg
))
7108 if (offset_expr
.X_op
!= O_symbol
7109 && offset_expr
.X_op
!= O_constant
)
7111 as_bad (_("Expression too complex"));
7112 offset_expr
.X_op
= O_constant
;
7115 if (offset_expr
.X_op
== O_constant
)
7116 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7117 else if (mips_pic
== NO_PIC
)
7119 /* If this is a reference to a GP relative symbol, we want
7120 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7122 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7123 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7124 If we have a constant, we need two instructions anyhow,
7125 so we may as well always use the latter form.
7127 With 64bit address space and a usable $at we want
7128 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7129 lui $at,<sym> (BFD_RELOC_HI16_S)
7130 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7131 daddiu $at,<sym> (BFD_RELOC_LO16)
7133 daddu $tempreg,$tempreg,$at
7135 If $at is already in use, we use a path which is suboptimal
7136 on superscalar processors.
7137 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7138 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7140 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7142 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7144 For GP relative symbols in 64bit address space we can use
7145 the same sequence as in 32bit address space. */
7146 if (HAVE_64BIT_SYMBOLS
)
7148 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7149 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7151 relax_start (offset_expr
.X_add_symbol
);
7152 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7153 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7157 if (used_at
== 0 && mips_opts
.at
)
7159 macro_build (&offset_expr
, "lui", LUI_FMT
,
7160 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7161 macro_build (&offset_expr
, "lui", LUI_FMT
,
7162 AT
, BFD_RELOC_HI16_S
);
7163 macro_build (&offset_expr
, "daddiu", "t,r,j",
7164 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7165 macro_build (&offset_expr
, "daddiu", "t,r,j",
7166 AT
, AT
, BFD_RELOC_LO16
);
7167 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7168 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7173 macro_build (&offset_expr
, "lui", LUI_FMT
,
7174 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7175 macro_build (&offset_expr
, "daddiu", "t,r,j",
7176 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7177 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7178 macro_build (&offset_expr
, "daddiu", "t,r,j",
7179 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7180 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7181 macro_build (&offset_expr
, "daddiu", "t,r,j",
7182 tempreg
, tempreg
, BFD_RELOC_LO16
);
7185 if (mips_relax
.sequence
)
7190 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7191 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7193 relax_start (offset_expr
.X_add_symbol
);
7194 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7195 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7198 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7199 as_bad (_("Offset too large"));
7200 macro_build_lui (&offset_expr
, tempreg
);
7201 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7202 tempreg
, tempreg
, BFD_RELOC_LO16
);
7203 if (mips_relax
.sequence
)
7207 else if (!mips_big_got
&& !HAVE_NEWABI
)
7209 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7211 /* If this is a reference to an external symbol, and there
7212 is no constant, we want
7213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7214 or for lca or if tempreg is PIC_CALL_REG
7215 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7216 For a local symbol, we want
7217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7219 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7221 If we have a small constant, and this is a reference to
7222 an external symbol, we want
7223 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7225 addiu $tempreg,$tempreg,<constant>
7226 For a local symbol, we want the same instruction
7227 sequence, but we output a BFD_RELOC_LO16 reloc on the
7230 If we have a large constant, and this is a reference to
7231 an external symbol, we want
7232 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7233 lui $at,<hiconstant>
7234 addiu $at,$at,<loconstant>
7235 addu $tempreg,$tempreg,$at
7236 For a local symbol, we want the same instruction
7237 sequence, but we output a BFD_RELOC_LO16 reloc on the
7241 if (offset_expr
.X_add_number
== 0)
7243 if (mips_pic
== SVR4_PIC
7245 && (call
|| tempreg
== PIC_CALL_REG
))
7246 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7248 relax_start (offset_expr
.X_add_symbol
);
7249 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7250 lw_reloc_type
, mips_gp_register
);
7253 /* We're going to put in an addu instruction using
7254 tempreg, so we may as well insert the nop right
7259 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7260 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7262 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7263 tempreg
, tempreg
, BFD_RELOC_LO16
);
7265 /* FIXME: If breg == 0, and the next instruction uses
7266 $tempreg, then if this variant case is used an extra
7267 nop will be generated. */
7269 else if (offset_expr
.X_add_number
>= -0x8000
7270 && offset_expr
.X_add_number
< 0x8000)
7272 load_got_offset (tempreg
, &offset_expr
);
7274 add_got_offset (tempreg
, &offset_expr
);
7278 expr1
.X_add_number
= offset_expr
.X_add_number
;
7279 offset_expr
.X_add_number
=
7280 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7281 load_got_offset (tempreg
, &offset_expr
);
7282 offset_expr
.X_add_number
= expr1
.X_add_number
;
7283 /* If we are going to add in a base register, and the
7284 target register and the base register are the same,
7285 then we are using AT as a temporary register. Since
7286 we want to load the constant into AT, we add our
7287 current AT (from the global offset table) and the
7288 register into the register now, and pretend we were
7289 not using a base register. */
7293 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7298 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7302 else if (!mips_big_got
&& HAVE_NEWABI
)
7304 int add_breg_early
= 0;
7306 /* If this is a reference to an external, and there is no
7307 constant, or local symbol (*), with or without a
7309 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7310 or for lca or if tempreg is PIC_CALL_REG
7311 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7313 If we have a small constant, and this is a reference to
7314 an external symbol, we want
7315 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7316 addiu $tempreg,$tempreg,<constant>
7318 If we have a large constant, and this is a reference to
7319 an external symbol, we want
7320 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7321 lui $at,<hiconstant>
7322 addiu $at,$at,<loconstant>
7323 addu $tempreg,$tempreg,$at
7325 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7326 local symbols, even though it introduces an additional
7329 if (offset_expr
.X_add_number
)
7331 expr1
.X_add_number
= offset_expr
.X_add_number
;
7332 offset_expr
.X_add_number
= 0;
7334 relax_start (offset_expr
.X_add_symbol
);
7335 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7336 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7338 if (expr1
.X_add_number
>= -0x8000
7339 && expr1
.X_add_number
< 0x8000)
7341 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7342 tempreg
, tempreg
, BFD_RELOC_LO16
);
7344 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7346 /* If we are going to add in a base register, and the
7347 target register and the base register are the same,
7348 then we are using AT as a temporary register. Since
7349 we want to load the constant into AT, we add our
7350 current AT (from the global offset table) and the
7351 register into the register now, and pretend we were
7352 not using a base register. */
7357 gas_assert (tempreg
== AT
);
7358 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7364 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7365 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7371 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7374 offset_expr
.X_add_number
= expr1
.X_add_number
;
7376 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7377 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7380 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7381 treg
, tempreg
, breg
);
7387 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7389 relax_start (offset_expr
.X_add_symbol
);
7390 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7391 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7393 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7394 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7399 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7400 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7403 else if (mips_big_got
&& !HAVE_NEWABI
)
7406 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7407 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7408 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7410 /* This is the large GOT case. If this is a reference to an
7411 external symbol, and there is no constant, we want
7412 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7413 addu $tempreg,$tempreg,$gp
7414 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7415 or for lca or if tempreg is PIC_CALL_REG
7416 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7417 addu $tempreg,$tempreg,$gp
7418 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7419 For a local symbol, we want
7420 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7422 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7424 If we have a small constant, and this is a reference to
7425 an external symbol, we want
7426 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7427 addu $tempreg,$tempreg,$gp
7428 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7430 addiu $tempreg,$tempreg,<constant>
7431 For a local symbol, we want
7432 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7434 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7436 If we have a large constant, and this is a reference to
7437 an external symbol, we want
7438 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7439 addu $tempreg,$tempreg,$gp
7440 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7441 lui $at,<hiconstant>
7442 addiu $at,$at,<loconstant>
7443 addu $tempreg,$tempreg,$at
7444 For a local symbol, we want
7445 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7446 lui $at,<hiconstant>
7447 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7448 addu $tempreg,$tempreg,$at
7451 expr1
.X_add_number
= offset_expr
.X_add_number
;
7452 offset_expr
.X_add_number
= 0;
7453 relax_start (offset_expr
.X_add_symbol
);
7454 gpdelay
= reg_needs_delay (mips_gp_register
);
7455 if (expr1
.X_add_number
== 0 && breg
== 0
7456 && (call
|| tempreg
== PIC_CALL_REG
))
7458 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7459 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7461 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7462 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7463 tempreg
, tempreg
, mips_gp_register
);
7464 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7465 tempreg
, lw_reloc_type
, tempreg
);
7466 if (expr1
.X_add_number
== 0)
7470 /* We're going to put in an addu instruction using
7471 tempreg, so we may as well insert the nop right
7476 else if (expr1
.X_add_number
>= -0x8000
7477 && expr1
.X_add_number
< 0x8000)
7480 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7481 tempreg
, tempreg
, BFD_RELOC_LO16
);
7485 /* If we are going to add in a base register, and the
7486 target register and the base register are the same,
7487 then we are using AT as a temporary register. Since
7488 we want to load the constant into AT, we add our
7489 current AT (from the global offset table) and the
7490 register into the register now, and pretend we were
7491 not using a base register. */
7496 gas_assert (tempreg
== AT
);
7498 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7503 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7504 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7508 offset_expr
.X_add_number
=
7509 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
7514 /* This is needed because this instruction uses $gp, but
7515 the first instruction on the main stream does not. */
7516 macro_build (NULL
, "nop", "");
7519 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7520 local_reloc_type
, mips_gp_register
);
7521 if (expr1
.X_add_number
>= -0x8000
7522 && expr1
.X_add_number
< 0x8000)
7525 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7526 tempreg
, tempreg
, BFD_RELOC_LO16
);
7527 /* FIXME: If add_number is 0, and there was no base
7528 register, the external symbol case ended with a load,
7529 so if the symbol turns out to not be external, and
7530 the next instruction uses tempreg, an unnecessary nop
7531 will be inserted. */
7537 /* We must add in the base register now, as in the
7538 external symbol case. */
7539 gas_assert (tempreg
== AT
);
7541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7544 /* We set breg to 0 because we have arranged to add
7545 it in in both cases. */
7549 macro_build_lui (&expr1
, AT
);
7550 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7551 AT
, AT
, BFD_RELOC_LO16
);
7552 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7553 tempreg
, tempreg
, AT
);
7558 else if (mips_big_got
&& HAVE_NEWABI
)
7560 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7561 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7562 int add_breg_early
= 0;
7564 /* This is the large GOT case. If this is a reference to an
7565 external symbol, and there is no constant, we want
7566 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7567 add $tempreg,$tempreg,$gp
7568 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7569 or for lca or if tempreg is PIC_CALL_REG
7570 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7571 add $tempreg,$tempreg,$gp
7572 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7574 If we have a small constant, and this is a reference to
7575 an external symbol, we want
7576 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7577 add $tempreg,$tempreg,$gp
7578 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7579 addi $tempreg,$tempreg,<constant>
7581 If we have a large constant, and this is a reference to
7582 an external symbol, we want
7583 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7584 addu $tempreg,$tempreg,$gp
7585 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7586 lui $at,<hiconstant>
7587 addi $at,$at,<loconstant>
7588 add $tempreg,$tempreg,$at
7590 If we have NewABI, and we know it's a local symbol, we want
7591 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7592 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7593 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7595 relax_start (offset_expr
.X_add_symbol
);
7597 expr1
.X_add_number
= offset_expr
.X_add_number
;
7598 offset_expr
.X_add_number
= 0;
7600 if (expr1
.X_add_number
== 0 && breg
== 0
7601 && (call
|| tempreg
== PIC_CALL_REG
))
7603 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7604 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7606 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7607 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7608 tempreg
, tempreg
, mips_gp_register
);
7609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7610 tempreg
, lw_reloc_type
, tempreg
);
7612 if (expr1
.X_add_number
== 0)
7614 else if (expr1
.X_add_number
>= -0x8000
7615 && expr1
.X_add_number
< 0x8000)
7617 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7618 tempreg
, tempreg
, BFD_RELOC_LO16
);
7620 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7622 /* If we are going to add in a base register, and the
7623 target register and the base register are the same,
7624 then we are using AT as a temporary register. Since
7625 we want to load the constant into AT, we add our
7626 current AT (from the global offset table) and the
7627 register into the register now, and pretend we were
7628 not using a base register. */
7633 gas_assert (tempreg
== AT
);
7634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7640 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7641 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7646 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7649 offset_expr
.X_add_number
= expr1
.X_add_number
;
7650 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7651 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7652 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7653 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7656 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7657 treg
, tempreg
, breg
);
7667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7671 gas_assert (!mips_opts
.micromips
);
7673 unsigned long temp
= (treg
<< 16) | (0x01);
7674 macro_build (NULL
, "c2", "C", temp
);
7679 gas_assert (!mips_opts
.micromips
);
7681 unsigned long temp
= (0x02);
7682 macro_build (NULL
, "c2", "C", temp
);
7687 gas_assert (!mips_opts
.micromips
);
7689 unsigned long temp
= (treg
<< 16) | (0x02);
7690 macro_build (NULL
, "c2", "C", temp
);
7695 gas_assert (!mips_opts
.micromips
);
7696 macro_build (NULL
, "c2", "C", 3);
7700 gas_assert (!mips_opts
.micromips
);
7702 unsigned long temp
= (treg
<< 16) | 0x03;
7703 macro_build (NULL
, "c2", "C", temp
);
7708 /* The j instruction may not be used in PIC code, since it
7709 requires an absolute address. We convert it to a b
7711 if (mips_pic
== NO_PIC
)
7712 macro_build (&offset_expr
, "j", "a");
7714 macro_build (&offset_expr
, "b", "p");
7717 /* The jal instructions must be handled as macros because when
7718 generating PIC code they expand to multi-instruction
7719 sequences. Normally they are simple instructions. */
7724 gas_assert (mips_opts
.micromips
);
7732 if (mips_pic
== NO_PIC
)
7734 s
= jals
? "jalrs" : "jalr";
7735 if (mips_opts
.micromips
&& dreg
== RA
)
7736 macro_build (NULL
, s
, "mj", sreg
);
7738 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7742 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7743 && mips_cprestore_offset
>= 0);
7745 if (sreg
!= PIC_CALL_REG
)
7746 as_warn (_("MIPS PIC call to register other than $25"));
7748 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7749 ? "jalrs" : "jalr");
7750 if (mips_opts
.micromips
&& dreg
== RA
)
7751 macro_build (NULL
, s
, "mj", sreg
);
7753 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7754 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7756 if (mips_cprestore_offset
< 0)
7757 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7760 if (!mips_frame_reg_valid
)
7762 as_warn (_("No .frame pseudo-op used in PIC code"));
7763 /* Quiet this warning. */
7764 mips_frame_reg_valid
= 1;
7766 if (!mips_cprestore_valid
)
7768 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7769 /* Quiet this warning. */
7770 mips_cprestore_valid
= 1;
7772 if (mips_opts
.noreorder
)
7773 macro_build (NULL
, "nop", "");
7774 expr1
.X_add_number
= mips_cprestore_offset
;
7775 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7778 HAVE_64BIT_ADDRESSES
);
7786 gas_assert (mips_opts
.micromips
);
7790 if (mips_pic
== NO_PIC
)
7791 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7792 else if (mips_pic
== SVR4_PIC
)
7794 /* If this is a reference to an external symbol, and we are
7795 using a small GOT, we want
7796 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7800 lw $gp,cprestore($sp)
7801 The cprestore value is set using the .cprestore
7802 pseudo-op. If we are using a big GOT, we want
7803 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7805 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7809 lw $gp,cprestore($sp)
7810 If the symbol is not external, we want
7811 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7813 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7816 lw $gp,cprestore($sp)
7818 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7819 sequences above, minus nops, unless the symbol is local,
7820 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7826 relax_start (offset_expr
.X_add_symbol
);
7827 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7828 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7831 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7832 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7838 relax_start (offset_expr
.X_add_symbol
);
7839 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7840 BFD_RELOC_MIPS_CALL_HI16
);
7841 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7842 PIC_CALL_REG
, mips_gp_register
);
7843 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7844 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7847 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7848 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7850 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7851 PIC_CALL_REG
, PIC_CALL_REG
,
7852 BFD_RELOC_MIPS_GOT_OFST
);
7856 macro_build_jalr (&offset_expr
, 0);
7860 relax_start (offset_expr
.X_add_symbol
);
7863 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7864 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7873 gpdelay
= reg_needs_delay (mips_gp_register
);
7874 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7875 BFD_RELOC_MIPS_CALL_HI16
);
7876 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7877 PIC_CALL_REG
, mips_gp_register
);
7878 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7879 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7884 macro_build (NULL
, "nop", "");
7886 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7887 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
7890 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7891 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
7893 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
7895 if (mips_cprestore_offset
< 0)
7896 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7899 if (!mips_frame_reg_valid
)
7901 as_warn (_("No .frame pseudo-op used in PIC code"));
7902 /* Quiet this warning. */
7903 mips_frame_reg_valid
= 1;
7905 if (!mips_cprestore_valid
)
7907 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7908 /* Quiet this warning. */
7909 mips_cprestore_valid
= 1;
7911 if (mips_opts
.noreorder
)
7912 macro_build (NULL
, "nop", "");
7913 expr1
.X_add_number
= mips_cprestore_offset
;
7914 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7917 HAVE_64BIT_ADDRESSES
);
7921 else if (mips_pic
== VXWORKS_PIC
)
7922 as_bad (_("Non-PIC jump used in PIC library"));
7932 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7940 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
7971 gas_assert (!mips_opts
.micromips
);
7974 /* Itbl support may require additional care here. */
7981 /* Itbl support may require additional care here. */
7989 off12
= mips_opts
.micromips
;
7990 /* Itbl support may require additional care here. */
7995 gas_assert (!mips_opts
.micromips
);
7998 /* Itbl support may require additional care here. */
8006 off12
= mips_opts
.micromips
;
8013 off12
= mips_opts
.micromips
;
8019 /* Itbl support may require additional care here. */
8027 off12
= mips_opts
.micromips
;
8028 /* Itbl support may require additional care here. */
8035 /* Itbl support may require additional care here. */
8043 off12
= mips_opts
.micromips
;
8050 off12
= mips_opts
.micromips
;
8057 off12
= mips_opts
.micromips
;
8064 off12
= mips_opts
.micromips
;
8071 off12
= mips_opts
.micromips
;
8076 gas_assert (mips_opts
.micromips
);
8085 gas_assert (mips_opts
.micromips
);
8094 gas_assert (mips_opts
.micromips
);
8102 gas_assert (mips_opts
.micromips
);
8109 if (breg
== treg
+ lp
)
8112 tempreg
= treg
+ lp
;
8132 gas_assert (!mips_opts
.micromips
);
8135 /* Itbl support may require additional care here. */
8142 /* Itbl support may require additional care here. */
8150 off12
= mips_opts
.micromips
;
8151 /* Itbl support may require additional care here. */
8156 gas_assert (!mips_opts
.micromips
);
8159 /* Itbl support may require additional care here. */
8167 off12
= mips_opts
.micromips
;
8174 off12
= mips_opts
.micromips
;
8181 off12
= mips_opts
.micromips
;
8188 off12
= mips_opts
.micromips
;
8194 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8195 off12
= mips_opts
.micromips
;
8201 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8202 off12
= mips_opts
.micromips
;
8209 /* Itbl support may require additional care here. */
8216 off12
= mips_opts
.micromips
;
8217 /* Itbl support may require additional care here. */
8222 gas_assert (!mips_opts
.micromips
);
8225 /* Itbl support may require additional care here. */
8233 off12
= mips_opts
.micromips
;
8240 off12
= mips_opts
.micromips
;
8245 gas_assert (mips_opts
.micromips
);
8253 gas_assert (mips_opts
.micromips
);
8261 gas_assert (mips_opts
.micromips
);
8269 gas_assert (mips_opts
.micromips
);
8278 if (offset_expr
.X_op
!= O_constant
8279 && offset_expr
.X_op
!= O_symbol
)
8281 as_bad (_("Expression too complex"));
8282 offset_expr
.X_op
= O_constant
;
8285 if (HAVE_32BIT_ADDRESSES
8286 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8290 sprintf_vma (value
, offset_expr
.X_add_number
);
8291 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8294 /* A constant expression in PIC code can be handled just as it
8295 is in non PIC code. */
8296 if (offset_expr
.X_op
== O_constant
)
8300 expr1
.X_add_number
= offset_expr
.X_add_number
;
8301 normalize_address_expr (&expr1
);
8302 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8304 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8305 & ~(bfd_vma
) 0xffff);
8308 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8310 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8311 & ~(bfd_vma
) 0xfff);
8316 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8318 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8319 tempreg
, tempreg
, breg
);
8324 if (offset_expr
.X_add_number
== 0)
8327 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8328 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8329 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8332 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8334 macro_build (NULL
, s
, fmt
,
8335 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8337 else if (off12
|| off0
)
8339 /* A 12-bit or 0-bit offset field is too narrow to be used
8340 for a low-part relocation, so load the whole address into
8341 the auxillary register. In the case of "A(b)" addresses,
8342 we first load absolute address "A" into the register and
8343 then add base register "b". In the case of "o(b)" addresses,
8344 we simply need to add 16-bit offset "o" to base register "b", and
8345 offset_reloc already contains the relocations associated
8349 load_address (tempreg
, &offset_expr
, &used_at
);
8351 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8352 tempreg
, tempreg
, breg
);
8355 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8357 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8358 expr1
.X_add_number
= 0;
8360 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8362 macro_build (NULL
, s
, fmt
,
8363 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8365 else if (mips_pic
== NO_PIC
)
8367 /* If this is a reference to a GP relative symbol, and there
8368 is no base register, we want
8369 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8370 Otherwise, if there is no base register, we want
8371 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8372 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8373 If we have a constant, we need two instructions anyhow,
8374 so we always use the latter form.
8376 If we have a base register, and this is a reference to a
8377 GP relative symbol, we want
8378 addu $tempreg,$breg,$gp
8379 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8381 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8382 addu $tempreg,$tempreg,$breg
8383 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8384 With a constant we always use the latter case.
8386 With 64bit address space and no base register and $at usable,
8388 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8389 lui $at,<sym> (BFD_RELOC_HI16_S)
8390 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8393 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8394 If we have a base register, we want
8395 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8396 lui $at,<sym> (BFD_RELOC_HI16_S)
8397 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8401 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8403 Without $at we can't generate the optimal path for superscalar
8404 processors here since this would require two temporary registers.
8405 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8406 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8408 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8410 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8411 If we have a base register, we want
8412 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8413 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8415 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8417 daddu $tempreg,$tempreg,$breg
8418 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8420 For GP relative symbols in 64bit address space we can use
8421 the same sequence as in 32bit address space. */
8422 if (HAVE_64BIT_SYMBOLS
)
8424 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8425 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8427 relax_start (offset_expr
.X_add_symbol
);
8430 macro_build (&offset_expr
, s
, fmt
, treg
,
8431 BFD_RELOC_GPREL16
, mips_gp_register
);
8435 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8436 tempreg
, breg
, mips_gp_register
);
8437 macro_build (&offset_expr
, s
, fmt
, treg
,
8438 BFD_RELOC_GPREL16
, tempreg
);
8443 if (used_at
== 0 && mips_opts
.at
)
8445 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8446 BFD_RELOC_MIPS_HIGHEST
);
8447 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8449 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8450 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8452 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8453 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8454 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8455 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8461 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8462 BFD_RELOC_MIPS_HIGHEST
);
8463 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8464 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8465 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8466 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8467 tempreg
, BFD_RELOC_HI16_S
);
8468 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8470 macro_build (NULL
, "daddu", "d,v,t",
8471 tempreg
, tempreg
, breg
);
8472 macro_build (&offset_expr
, s
, fmt
, treg
,
8473 BFD_RELOC_LO16
, tempreg
);
8476 if (mips_relax
.sequence
)
8483 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8484 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8486 relax_start (offset_expr
.X_add_symbol
);
8487 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8491 macro_build_lui (&offset_expr
, tempreg
);
8492 macro_build (&offset_expr
, s
, fmt
, treg
,
8493 BFD_RELOC_LO16
, tempreg
);
8494 if (mips_relax
.sequence
)
8499 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8500 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8502 relax_start (offset_expr
.X_add_symbol
);
8503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8504 tempreg
, breg
, mips_gp_register
);
8505 macro_build (&offset_expr
, s
, fmt
, treg
,
8506 BFD_RELOC_GPREL16
, tempreg
);
8509 macro_build_lui (&offset_expr
, tempreg
);
8510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8511 tempreg
, tempreg
, breg
);
8512 macro_build (&offset_expr
, s
, fmt
, treg
,
8513 BFD_RELOC_LO16
, tempreg
);
8514 if (mips_relax
.sequence
)
8518 else if (!mips_big_got
)
8520 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8522 /* If this is a reference to an external symbol, we want
8523 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8525 <op> $treg,0($tempreg)
8527 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8529 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8530 <op> $treg,0($tempreg)
8533 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8534 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8536 If there is a base register, we add it to $tempreg before
8537 the <op>. If there is a constant, we stick it in the
8538 <op> instruction. We don't handle constants larger than
8539 16 bits, because we have no way to load the upper 16 bits
8540 (actually, we could handle them for the subset of cases
8541 in which we are not using $at). */
8542 gas_assert (offset_expr
.X_op
== O_symbol
);
8545 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8546 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8548 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8549 tempreg
, tempreg
, breg
);
8550 macro_build (&offset_expr
, s
, fmt
, treg
,
8551 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8554 expr1
.X_add_number
= offset_expr
.X_add_number
;
8555 offset_expr
.X_add_number
= 0;
8556 if (expr1
.X_add_number
< -0x8000
8557 || expr1
.X_add_number
>= 0x8000)
8558 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8559 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8560 lw_reloc_type
, mips_gp_register
);
8562 relax_start (offset_expr
.X_add_symbol
);
8564 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8565 tempreg
, BFD_RELOC_LO16
);
8568 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8569 tempreg
, tempreg
, breg
);
8570 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8572 else if (mips_big_got
&& !HAVE_NEWABI
)
8576 /* If this is a reference to an external symbol, we want
8577 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8578 addu $tempreg,$tempreg,$gp
8579 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8580 <op> $treg,0($tempreg)
8582 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8584 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8585 <op> $treg,0($tempreg)
8586 If there is a base register, we add it to $tempreg before
8587 the <op>. If there is a constant, we stick it in the
8588 <op> instruction. We don't handle constants larger than
8589 16 bits, because we have no way to load the upper 16 bits
8590 (actually, we could handle them for the subset of cases
8591 in which we are not using $at). */
8592 gas_assert (offset_expr
.X_op
== O_symbol
);
8593 expr1
.X_add_number
= offset_expr
.X_add_number
;
8594 offset_expr
.X_add_number
= 0;
8595 if (expr1
.X_add_number
< -0x8000
8596 || expr1
.X_add_number
>= 0x8000)
8597 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8598 gpdelay
= reg_needs_delay (mips_gp_register
);
8599 relax_start (offset_expr
.X_add_symbol
);
8600 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8601 BFD_RELOC_MIPS_GOT_HI16
);
8602 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8604 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8605 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8608 macro_build (NULL
, "nop", "");
8609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8610 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8612 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8613 tempreg
, BFD_RELOC_LO16
);
8617 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8618 tempreg
, tempreg
, breg
);
8619 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8621 else if (mips_big_got
&& HAVE_NEWABI
)
8623 /* If this is a reference to an external symbol, we want
8624 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8625 add $tempreg,$tempreg,$gp
8626 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8627 <op> $treg,<ofst>($tempreg)
8628 Otherwise, for local symbols, we want:
8629 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8630 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8631 gas_assert (offset_expr
.X_op
== O_symbol
);
8632 expr1
.X_add_number
= offset_expr
.X_add_number
;
8633 offset_expr
.X_add_number
= 0;
8634 if (expr1
.X_add_number
< -0x8000
8635 || expr1
.X_add_number
>= 0x8000)
8636 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8637 relax_start (offset_expr
.X_add_symbol
);
8638 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8639 BFD_RELOC_MIPS_GOT_HI16
);
8640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8642 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8643 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8645 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8646 tempreg
, tempreg
, breg
);
8647 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8650 offset_expr
.X_add_number
= expr1
.X_add_number
;
8651 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8652 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8654 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8655 tempreg
, tempreg
, breg
);
8656 macro_build (&offset_expr
, s
, fmt
, treg
,
8657 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8667 load_register (treg
, &imm_expr
, 0);
8671 load_register (treg
, &imm_expr
, 1);
8675 if (imm_expr
.X_op
== O_constant
)
8678 load_register (AT
, &imm_expr
, 0);
8679 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8684 gas_assert (offset_expr
.X_op
== O_symbol
8685 && strcmp (segment_name (S_GET_SEGMENT
8686 (offset_expr
.X_add_symbol
)),
8688 && offset_expr
.X_add_number
== 0);
8689 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8690 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8695 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8696 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8697 order 32 bits of the value and the low order 32 bits are either
8698 zero or in OFFSET_EXPR. */
8699 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8701 if (HAVE_64BIT_GPRS
)
8702 load_register (treg
, &imm_expr
, 1);
8707 if (target_big_endian
)
8719 load_register (hreg
, &imm_expr
, 0);
8722 if (offset_expr
.X_op
== O_absent
)
8723 move_register (lreg
, 0);
8726 gas_assert (offset_expr
.X_op
== O_constant
);
8727 load_register (lreg
, &offset_expr
, 0);
8734 /* We know that sym is in the .rdata section. First we get the
8735 upper 16 bits of the address. */
8736 if (mips_pic
== NO_PIC
)
8738 macro_build_lui (&offset_expr
, AT
);
8743 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8744 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8748 /* Now we load the register(s). */
8749 if (HAVE_64BIT_GPRS
)
8752 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8757 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8760 /* FIXME: How in the world do we deal with the possible
8762 offset_expr
.X_add_number
+= 4;
8763 macro_build (&offset_expr
, "lw", "t,o(b)",
8764 treg
+ 1, BFD_RELOC_LO16
, AT
);
8770 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8771 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8772 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8773 the value and the low order 32 bits are either zero or in
8775 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8778 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8779 if (HAVE_64BIT_FPRS
)
8781 gas_assert (HAVE_64BIT_GPRS
);
8782 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8786 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8787 if (offset_expr
.X_op
== O_absent
)
8788 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8791 gas_assert (offset_expr
.X_op
== O_constant
);
8792 load_register (AT
, &offset_expr
, 0);
8793 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8799 gas_assert (offset_expr
.X_op
== O_symbol
8800 && offset_expr
.X_add_number
== 0);
8801 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8802 if (strcmp (s
, ".lit8") == 0)
8804 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8806 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8807 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8810 breg
= mips_gp_register
;
8811 r
= BFD_RELOC_MIPS_LITERAL
;
8816 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8818 if (mips_pic
!= NO_PIC
)
8819 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8820 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8823 /* FIXME: This won't work for a 64 bit address. */
8824 macro_build_lui (&offset_expr
, AT
);
8827 if (mips_opts
.isa
!= ISA_MIPS1
|| mips_opts
.micromips
)
8829 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8830 treg
, BFD_RELOC_LO16
, AT
);
8839 /* Even on a big endian machine $fn comes before $fn+1. We have
8840 to adjust when loading from memory. */
8843 gas_assert (!mips_opts
.micromips
);
8844 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8845 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8846 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8847 /* FIXME: A possible overflow which I don't know how to deal
8849 offset_expr
.X_add_number
+= 4;
8850 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8851 target_big_endian
? treg
: treg
+ 1, r
, breg
);
8855 gas_assert (!mips_opts
.micromips
);
8856 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
8857 /* Even on a big endian machine $fn comes before $fn+1. We have
8858 to adjust when storing to memory. */
8859 macro_build (&offset_expr
, "swc1", "T,o(b)",
8860 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
8861 offset_expr
.X_add_number
+= 4;
8862 macro_build (&offset_expr
, "swc1", "T,o(b)",
8863 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
8867 gas_assert (!mips_opts
.micromips
);
8869 * The MIPS assembler seems to check for X_add_number not
8870 * being double aligned and generating:
8873 * addiu at,at,%lo(foo+1)
8876 * But, the resulting address is the same after relocation so why
8877 * generate the extra instruction?
8879 /* Itbl support may require additional care here. */
8882 if (mips_opts
.isa
!= ISA_MIPS1
)
8891 gas_assert (!mips_opts
.micromips
);
8892 /* Itbl support may require additional care here. */
8895 if (mips_opts
.isa
!= ISA_MIPS1
)
8905 if (HAVE_64BIT_GPRS
)
8915 if (HAVE_64BIT_GPRS
)
8923 if (offset_expr
.X_op
!= O_symbol
8924 && offset_expr
.X_op
!= O_constant
)
8926 as_bad (_("Expression too complex"));
8927 offset_expr
.X_op
= O_constant
;
8930 if (HAVE_32BIT_ADDRESSES
8931 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8935 sprintf_vma (value
, offset_expr
.X_add_number
);
8936 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8939 /* Even on a big endian machine $fn comes before $fn+1. We have
8940 to adjust when loading from memory. We set coproc if we must
8941 load $fn+1 first. */
8942 /* Itbl support may require additional care here. */
8943 if (!target_big_endian
)
8946 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
8948 /* If this is a reference to a GP relative symbol, we want
8949 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8950 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8951 If we have a base register, we use this
8953 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8954 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8955 If this is not a GP relative symbol, we want
8956 lui $at,<sym> (BFD_RELOC_HI16_S)
8957 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8958 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8959 If there is a base register, we add it to $at after the
8960 lui instruction. If there is a constant, we always use
8962 if (offset_expr
.X_op
== O_symbol
8963 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8964 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8966 relax_start (offset_expr
.X_add_symbol
);
8969 tempreg
= mips_gp_register
;
8973 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8974 AT
, breg
, mips_gp_register
);
8979 /* Itbl support may require additional care here. */
8980 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
8981 BFD_RELOC_GPREL16
, tempreg
);
8982 offset_expr
.X_add_number
+= 4;
8984 /* Set mips_optimize to 2 to avoid inserting an
8986 hold_mips_optimize
= mips_optimize
;
8988 /* Itbl support may require additional care here. */
8989 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
8990 BFD_RELOC_GPREL16
, tempreg
);
8991 mips_optimize
= hold_mips_optimize
;
8995 offset_expr
.X_add_number
-= 4;
8998 macro_build_lui (&offset_expr
, AT
);
9000 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9001 /* Itbl support may require additional care here. */
9002 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9003 BFD_RELOC_LO16
, AT
);
9004 /* FIXME: How do we handle overflow here? */
9005 offset_expr
.X_add_number
+= 4;
9006 /* Itbl support may require additional care here. */
9007 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9008 BFD_RELOC_LO16
, AT
);
9009 if (mips_relax
.sequence
)
9012 else if (!mips_big_got
)
9014 /* If this is a reference to an external symbol, we want
9015 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9020 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9022 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9023 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9024 If there is a base register we add it to $at before the
9025 lwc1 instructions. If there is a constant we include it
9026 in the lwc1 instructions. */
9028 expr1
.X_add_number
= offset_expr
.X_add_number
;
9029 if (expr1
.X_add_number
< -0x8000
9030 || expr1
.X_add_number
>= 0x8000 - 4)
9031 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9032 load_got_offset (AT
, &offset_expr
);
9035 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9037 /* Set mips_optimize to 2 to avoid inserting an undesired
9039 hold_mips_optimize
= mips_optimize
;
9042 /* Itbl support may require additional care here. */
9043 relax_start (offset_expr
.X_add_symbol
);
9044 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9045 BFD_RELOC_LO16
, AT
);
9046 expr1
.X_add_number
+= 4;
9047 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9048 BFD_RELOC_LO16
, AT
);
9050 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9051 BFD_RELOC_LO16
, AT
);
9052 offset_expr
.X_add_number
+= 4;
9053 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9054 BFD_RELOC_LO16
, AT
);
9057 mips_optimize
= hold_mips_optimize
;
9059 else if (mips_big_got
)
9063 /* If this is a reference to an external symbol, we want
9064 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9066 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9071 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9073 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9074 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9075 If there is a base register we add it to $at before the
9076 lwc1 instructions. If there is a constant we include it
9077 in the lwc1 instructions. */
9079 expr1
.X_add_number
= offset_expr
.X_add_number
;
9080 offset_expr
.X_add_number
= 0;
9081 if (expr1
.X_add_number
< -0x8000
9082 || expr1
.X_add_number
>= 0x8000 - 4)
9083 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9084 gpdelay
= reg_needs_delay (mips_gp_register
);
9085 relax_start (offset_expr
.X_add_symbol
);
9086 macro_build (&offset_expr
, "lui", LUI_FMT
,
9087 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9088 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9089 AT
, AT
, mips_gp_register
);
9090 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9091 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9095 /* Itbl support may require additional care here. */
9096 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9097 BFD_RELOC_LO16
, AT
);
9098 expr1
.X_add_number
+= 4;
9100 /* Set mips_optimize to 2 to avoid inserting an undesired
9102 hold_mips_optimize
= mips_optimize
;
9104 /* Itbl support may require additional care here. */
9105 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9106 BFD_RELOC_LO16
, AT
);
9107 mips_optimize
= hold_mips_optimize
;
9108 expr1
.X_add_number
-= 4;
9111 offset_expr
.X_add_number
= expr1
.X_add_number
;
9113 macro_build (NULL
, "nop", "");
9114 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9115 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9118 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9119 /* Itbl support may require additional care here. */
9120 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9121 BFD_RELOC_LO16
, AT
);
9122 offset_expr
.X_add_number
+= 4;
9124 /* Set mips_optimize to 2 to avoid inserting an undesired
9126 hold_mips_optimize
= mips_optimize
;
9128 /* Itbl support may require additional care here. */
9129 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9130 BFD_RELOC_LO16
, AT
);
9131 mips_optimize
= hold_mips_optimize
;
9140 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9143 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9145 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9146 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9148 if (!HAVE_64BIT_GPRS
)
9150 offset_expr
.X_add_number
+= 4;
9151 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9152 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9173 /* New code added to support COPZ instructions.
9174 This code builds table entries out of the macros in mip_opcodes.
9175 R4000 uses interlocks to handle coproc delays.
9176 Other chips (like the R3000) require nops to be inserted for delays.
9178 FIXME: Currently, we require that the user handle delays.
9179 In order to fill delay slots for non-interlocked chips,
9180 we must have a way to specify delays based on the coprocessor.
9181 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9182 What are the side-effects of the cop instruction?
9183 What cache support might we have and what are its effects?
9184 Both coprocessor & memory require delays. how long???
9185 What registers are read/set/modified?
9187 If an itbl is provided to interpret cop instructions,
9188 this knowledge can be encoded in the itbl spec. */
9202 gas_assert (!mips_opts
.micromips
);
9203 /* For now we just do C (same as Cz). The parameter will be
9204 stored in insn_opcode by mips_ip. */
9205 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9209 move_register (dreg
, sreg
);
9215 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9216 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9222 /* The MIPS assembler some times generates shifts and adds. I'm
9223 not trying to be that fancy. GCC should do this for us
9226 load_register (AT
, &imm_expr
, dbl
);
9227 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9228 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9244 load_register (AT
, &imm_expr
, dbl
);
9245 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9246 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9247 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9248 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9250 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9253 if (mips_opts
.micromips
)
9254 micromips_label_expr (&label_expr
);
9256 label_expr
.X_add_number
= 8;
9257 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9258 macro_build (NULL
, "nop", "");
9259 macro_build (NULL
, "break", BRK_FMT
, 6);
9260 if (mips_opts
.micromips
)
9261 micromips_add_label ();
9264 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9280 load_register (AT
, &imm_expr
, dbl
);
9281 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9282 sreg
, imm
? AT
: treg
);
9283 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9284 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9286 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9289 if (mips_opts
.micromips
)
9290 micromips_label_expr (&label_expr
);
9292 label_expr
.X_add_number
= 8;
9293 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9294 macro_build (NULL
, "nop", "");
9295 macro_build (NULL
, "break", BRK_FMT
, 6);
9296 if (mips_opts
.micromips
)
9297 micromips_add_label ();
9303 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9314 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9315 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9319 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9320 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9321 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9322 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9326 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9337 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9338 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9342 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9343 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9344 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9345 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9354 if (imm_expr
.X_op
!= O_constant
)
9355 as_bad (_("Improper rotate count"));
9356 rot
= imm_expr
.X_add_number
& 0x3f;
9357 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9359 rot
= (64 - rot
) & 0x3f;
9361 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9363 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9368 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9371 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9372 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9375 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9376 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9377 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9385 if (imm_expr
.X_op
!= O_constant
)
9386 as_bad (_("Improper rotate count"));
9387 rot
= imm_expr
.X_add_number
& 0x1f;
9388 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9390 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9395 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9399 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9400 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9401 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9406 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9408 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9412 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9413 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9414 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9415 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9419 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9421 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9425 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9426 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9427 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9428 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9437 if (imm_expr
.X_op
!= O_constant
)
9438 as_bad (_("Improper rotate count"));
9439 rot
= imm_expr
.X_add_number
& 0x3f;
9440 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9443 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9445 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9450 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9453 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9454 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9457 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9458 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9459 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9467 if (imm_expr
.X_op
!= O_constant
)
9468 as_bad (_("Improper rotate count"));
9469 rot
= imm_expr
.X_add_number
& 0x1f;
9470 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9472 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9477 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9481 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9482 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9483 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9489 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9491 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9494 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9495 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9500 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9502 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9507 as_warn (_("Instruction %s: result is always false"),
9509 move_register (dreg
, 0);
9512 if (CPU_HAS_SEQ (mips_opts
.arch
)
9513 && -512 <= imm_expr
.X_add_number
9514 && imm_expr
.X_add_number
< 512)
9516 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9517 (int) imm_expr
.X_add_number
);
9520 if (imm_expr
.X_op
== O_constant
9521 && imm_expr
.X_add_number
>= 0
9522 && imm_expr
.X_add_number
< 0x10000)
9524 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9526 else if (imm_expr
.X_op
== O_constant
9527 && imm_expr
.X_add_number
> -0x8000
9528 && imm_expr
.X_add_number
< 0)
9530 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9531 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9532 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9534 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9537 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9538 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9543 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9544 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9547 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9550 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9556 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9557 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9560 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9562 if (imm_expr
.X_op
== O_constant
9563 && imm_expr
.X_add_number
>= -0x8000
9564 && imm_expr
.X_add_number
< 0x8000)
9566 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9567 dreg
, sreg
, BFD_RELOC_LO16
);
9571 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9572 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9576 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9579 case M_SGT
: /* sreg > treg <==> treg < sreg */
9585 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9588 case M_SGT_I
: /* sreg > I <==> I < sreg */
9595 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9596 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9599 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9605 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9606 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9609 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9616 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9617 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9618 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9622 if (imm_expr
.X_op
== O_constant
9623 && imm_expr
.X_add_number
>= -0x8000
9624 && imm_expr
.X_add_number
< 0x8000)
9626 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9630 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9631 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9635 if (imm_expr
.X_op
== O_constant
9636 && imm_expr
.X_add_number
>= -0x8000
9637 && imm_expr
.X_add_number
< 0x8000)
9639 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9644 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9645 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9650 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9652 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9655 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9656 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9661 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9663 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9668 as_warn (_("Instruction %s: result is always true"),
9670 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9671 dreg
, 0, BFD_RELOC_LO16
);
9674 if (CPU_HAS_SEQ (mips_opts
.arch
)
9675 && -512 <= imm_expr
.X_add_number
9676 && imm_expr
.X_add_number
< 512)
9678 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9679 (int) imm_expr
.X_add_number
);
9682 if (imm_expr
.X_op
== O_constant
9683 && imm_expr
.X_add_number
>= 0
9684 && imm_expr
.X_add_number
< 0x10000)
9686 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9688 else if (imm_expr
.X_op
== O_constant
9689 && imm_expr
.X_add_number
> -0x8000
9690 && imm_expr
.X_add_number
< 0)
9692 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9693 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9694 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9696 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9699 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9700 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9705 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9706 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9709 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9724 if (!mips_opts
.micromips
)
9726 if (imm_expr
.X_op
== O_constant
9727 && imm_expr
.X_add_number
> -0x200
9728 && imm_expr
.X_add_number
<= 0x200)
9730 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9739 if (imm_expr
.X_op
== O_constant
9740 && imm_expr
.X_add_number
> -0x8000
9741 && imm_expr
.X_add_number
<= 0x8000)
9743 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9744 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9749 load_register (AT
, &imm_expr
, dbl
);
9750 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9772 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9773 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9778 gas_assert (!mips_opts
.micromips
);
9779 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9781 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9782 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9785 * Is the double cfc1 instruction a bug in the mips assembler;
9786 * or is there a reason for it?
9789 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9790 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9791 macro_build (NULL
, "nop", "");
9792 expr1
.X_add_number
= 3;
9793 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9794 expr1
.X_add_number
= 2;
9795 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9796 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9797 macro_build (NULL
, "nop", "");
9798 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9800 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9801 macro_build (NULL
, "nop", "");
9824 off12
= mips_opts
.micromips
;
9832 off12
= mips_opts
.micromips
;
9848 off12
= mips_opts
.micromips
;
9857 off12
= mips_opts
.micromips
;
9862 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
9863 as_bad (_("Operand overflow"));
9866 expr1
.X_add_number
= 0;
9871 load_address (tempreg
, ep
, &used_at
);
9873 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9874 tempreg
, tempreg
, breg
);
9880 && (offset_expr
.X_op
!= O_constant
9881 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
9882 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
9886 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
9887 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9892 else if (!ust
&& treg
== breg
)
9903 if (!target_big_endian
)
9904 ep
->X_add_number
+= off
;
9906 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9908 macro_build (NULL
, s
, "t,~(b)",
9909 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9911 if (!target_big_endian
)
9912 ep
->X_add_number
-= off
;
9914 ep
->X_add_number
+= off
;
9916 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9918 macro_build (NULL
, s2
, "t,~(b)",
9919 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
9921 /* If necessary, move the result in tempreg to the final destination. */
9922 if (!ust
&& treg
!= tempreg
)
9924 /* Protect second load's delay slot. */
9926 move_register (treg
, tempreg
);
9932 if (target_big_endian
== ust
)
9933 ep
->X_add_number
+= off
;
9934 tempreg
= ust
|| ab
? treg
: AT
;
9935 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9937 /* For halfword transfers we need a temporary register to shuffle
9938 bytes. Unfortunately for M_USH_A we have none available before
9939 the next store as AT holds the base address. We deal with this
9940 case by clobbering TREG and then restoring it as with ULH. */
9941 tempreg
= ust
== ab
? treg
: AT
;
9943 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
9945 if (target_big_endian
== ust
)
9946 ep
->X_add_number
-= off
;
9948 ep
->X_add_number
+= off
;
9949 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
9951 /* For M_USH_A re-retrieve the LSB. */
9954 if (target_big_endian
)
9955 ep
->X_add_number
+= off
;
9957 ep
->X_add_number
-= off
;
9958 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
9960 /* For ULH and M_USH_A OR the LSB in. */
9963 tempreg
= !ab
? AT
: treg
;
9964 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
9965 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
9970 /* FIXME: Check if this is one of the itbl macros, since they
9971 are added dynamically. */
9972 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
9975 if (!mips_opts
.at
&& used_at
)
9976 as_bad (_("Macro used $at after \".set noat\""));
9979 /* Implement macros in mips16 mode. */
9982 mips16_macro (struct mips_cl_insn
*ip
)
9985 int xreg
, yreg
, zreg
, tmp
;
9988 const char *s
, *s2
, *s3
;
9990 mask
= ip
->insn_mo
->mask
;
9992 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
9993 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
9994 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
9996 expr1
.X_op
= O_constant
;
9997 expr1
.X_op_symbol
= NULL
;
9998 expr1
.X_add_symbol
= NULL
;
9999 expr1
.X_add_number
= 1;
10018 start_noreorder ();
10019 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10020 expr1
.X_add_number
= 2;
10021 macro_build (&expr1
, "bnez", "x,p", yreg
);
10022 macro_build (NULL
, "break", "6", 7);
10024 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10025 since that causes an overflow. We should do that as well,
10026 but I don't see how to do the comparisons without a temporary
10029 macro_build (NULL
, s
, "x", zreg
);
10048 start_noreorder ();
10049 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10050 expr1
.X_add_number
= 2;
10051 macro_build (&expr1
, "bnez", "x,p", yreg
);
10052 macro_build (NULL
, "break", "6", 7);
10054 macro_build (NULL
, s2
, "x", zreg
);
10060 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10061 macro_build (NULL
, "mflo", "x", zreg
);
10069 if (imm_expr
.X_op
!= O_constant
)
10070 as_bad (_("Unsupported large constant"));
10071 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10072 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10076 if (imm_expr
.X_op
!= O_constant
)
10077 as_bad (_("Unsupported large constant"));
10078 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10079 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10083 if (imm_expr
.X_op
!= O_constant
)
10084 as_bad (_("Unsupported large constant"));
10085 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10086 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10108 goto do_reverse_branch
;
10112 goto do_reverse_branch
;
10124 goto do_reverse_branch
;
10135 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10136 macro_build (&offset_expr
, s2
, "p");
10163 goto do_addone_branch_i
;
10168 goto do_addone_branch_i
;
10183 goto do_addone_branch_i
;
10189 do_addone_branch_i
:
10190 if (imm_expr
.X_op
!= O_constant
)
10191 as_bad (_("Unsupported large constant"));
10192 ++imm_expr
.X_add_number
;
10195 macro_build (&imm_expr
, s
, s3
, xreg
);
10196 macro_build (&offset_expr
, s2
, "p");
10200 expr1
.X_add_number
= 0;
10201 macro_build (&expr1
, "slti", "x,8", yreg
);
10203 move_register (xreg
, yreg
);
10204 expr1
.X_add_number
= 2;
10205 macro_build (&expr1
, "bteqz", "p");
10206 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10210 /* For consistency checking, verify that all bits are specified either
10211 by the match/mask part of the instruction definition, or by the
10214 validate_mips_insn (const struct mips_opcode
*opc
)
10216 const char *p
= opc
->args
;
10218 unsigned long used_bits
= opc
->mask
;
10220 if ((used_bits
& opc
->match
) != opc
->match
)
10222 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10223 opc
->name
, opc
->args
);
10226 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10236 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10237 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10238 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10239 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10240 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10241 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10242 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10243 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10244 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10245 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10246 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10247 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10248 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10250 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10251 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10252 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10253 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10254 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10255 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10256 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10257 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10258 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10259 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10260 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10261 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10262 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10263 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10264 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10267 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10268 c
, opc
->name
, opc
->args
);
10272 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10273 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10275 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10276 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10277 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10278 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10280 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10281 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10283 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10284 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10286 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10287 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10288 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10289 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10290 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10291 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10292 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10293 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10294 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10295 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10296 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10297 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10298 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10299 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10300 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10301 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10302 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10304 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10305 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10306 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10307 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10309 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10310 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10311 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10312 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10313 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10314 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10315 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10316 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10317 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10320 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10321 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10322 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10323 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10324 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10327 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10328 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10329 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10330 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10331 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10332 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10333 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10334 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10335 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10336 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10337 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10338 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10339 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10340 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10341 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10342 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10343 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10344 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10345 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10346 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10348 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10349 c
, opc
->name
, opc
->args
);
10353 if (used_bits
!= 0xffffffff)
10355 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10356 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10362 /* For consistency checking, verify that the length implied matches the
10363 major opcode and that all bits are specified either by the match/mask
10364 part of the instruction definition, or by the operand list. */
10367 validate_micromips_insn (const struct mips_opcode
*opc
)
10369 unsigned long match
= opc
->match
;
10370 unsigned long mask
= opc
->mask
;
10371 const char *p
= opc
->args
;
10372 unsigned long insn_bits
;
10373 unsigned long used_bits
;
10374 unsigned long major
;
10375 unsigned int length
;
10379 if ((mask
& match
) != match
)
10381 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10382 opc
->name
, opc
->args
);
10385 length
= micromips_insn_length (opc
);
10386 if (length
!= 2 && length
!= 4)
10388 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10389 "%s %s"), length
, opc
->name
, opc
->args
);
10392 major
= match
>> (10 + 8 * (length
- 2));
10393 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10394 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10396 as_bad (_("Internal error: bad microMIPS opcode "
10397 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10401 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10402 insn_bits
= 1 << 4 * length
;
10403 insn_bits
<<= 4 * length
;
10406 #define USE_BITS(field) \
10407 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10418 case 'A': USE_BITS (EXTLSB
); break;
10419 case 'B': USE_BITS (INSMSB
); break;
10420 case 'C': USE_BITS (EXTMSBD
); break;
10421 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10422 case 'E': USE_BITS (EXTLSB
); break;
10423 case 'F': USE_BITS (INSMSB
); break;
10424 case 'G': USE_BITS (EXTMSBD
); break;
10425 case 'H': USE_BITS (EXTMSBD
); break;
10427 as_bad (_("Internal error: bad mips opcode "
10428 "(unknown extension operand type `%c%c'): %s %s"),
10429 e
, c
, opc
->name
, opc
->args
);
10437 case 'A': USE_BITS (IMMA
); break;
10438 case 'B': USE_BITS (IMMB
); break;
10439 case 'C': USE_BITS (IMMC
); break;
10440 case 'D': USE_BITS (IMMD
); break;
10441 case 'E': USE_BITS (IMME
); break;
10442 case 'F': USE_BITS (IMMF
); break;
10443 case 'G': USE_BITS (IMMG
); break;
10444 case 'H': USE_BITS (IMMH
); break;
10445 case 'I': USE_BITS (IMMI
); break;
10446 case 'J': USE_BITS (IMMJ
); break;
10447 case 'L': USE_BITS (IMML
); break;
10448 case 'M': USE_BITS (IMMM
); break;
10449 case 'N': USE_BITS (IMMN
); break;
10450 case 'O': USE_BITS (IMMO
); break;
10451 case 'P': USE_BITS (IMMP
); break;
10452 case 'Q': USE_BITS (IMMQ
); break;
10453 case 'U': USE_BITS (IMMU
); break;
10454 case 'W': USE_BITS (IMMW
); break;
10455 case 'X': USE_BITS (IMMX
); break;
10456 case 'Y': USE_BITS (IMMY
); break;
10459 case 'b': USE_BITS (MB
); break;
10460 case 'c': USE_BITS (MC
); break;
10461 case 'd': USE_BITS (MD
); break;
10462 case 'e': USE_BITS (ME
); break;
10463 case 'f': USE_BITS (MF
); break;
10464 case 'g': USE_BITS (MG
); break;
10465 case 'h': USE_BITS (MH
); break;
10466 case 'i': USE_BITS (MI
); break;
10467 case 'j': USE_BITS (MJ
); break;
10468 case 'l': USE_BITS (ML
); break;
10469 case 'm': USE_BITS (MM
); break;
10470 case 'n': USE_BITS (MN
); break;
10471 case 'p': USE_BITS (MP
); break;
10472 case 'q': USE_BITS (MQ
); break;
10480 as_bad (_("Internal error: bad mips opcode "
10481 "(unknown extension operand type `%c%c'): %s %s"),
10482 e
, c
, opc
->name
, opc
->args
);
10486 case '.': USE_BITS (OFFSET10
); break;
10487 case '1': USE_BITS (STYPE
); break;
10488 case '2': USE_BITS (BP
); break;
10489 case '3': USE_BITS (SA3
); break;
10490 case '4': USE_BITS (SA4
); break;
10491 case '5': USE_BITS (IMM8
); break;
10492 case '6': USE_BITS (RS
); break;
10493 case '7': USE_BITS (DSPACC
); break;
10494 case '8': USE_BITS (WRDSP
); break;
10495 case '0': USE_BITS (DSPSFT
); break;
10496 case '<': USE_BITS (SHAMT
); break;
10497 case '>': USE_BITS (SHAMT
); break;
10498 case '@': USE_BITS (IMM10
); break;
10499 case 'B': USE_BITS (CODE10
); break;
10500 case 'C': USE_BITS (COPZ
); break;
10501 case 'D': USE_BITS (FD
); break;
10502 case 'E': USE_BITS (RT
); break;
10503 case 'G': USE_BITS (RS
); break;
10504 case 'H': USE_BITS (SEL
); break;
10505 case 'K': USE_BITS (RS
); break;
10506 case 'M': USE_BITS (CCC
); break;
10507 case 'N': USE_BITS (BCC
); break;
10508 case 'R': USE_BITS (FR
); break;
10509 case 'S': USE_BITS (FS
); break;
10510 case 'T': USE_BITS (FT
); break;
10511 case 'V': USE_BITS (FS
); break;
10512 case '\\': USE_BITS (3BITPOS
); break;
10513 case '^': USE_BITS (RD
); break;
10514 case 'a': USE_BITS (TARGET
); break;
10515 case 'b': USE_BITS (RS
); break;
10516 case 'c': USE_BITS (CODE
); break;
10517 case 'd': USE_BITS (RD
); break;
10518 case 'h': USE_BITS (PREFX
); break;
10519 case 'i': USE_BITS (IMMEDIATE
); break;
10520 case 'j': USE_BITS (DELTA
); break;
10521 case 'k': USE_BITS (CACHE
); break;
10522 case 'n': USE_BITS (RT
); break;
10523 case 'o': USE_BITS (DELTA
); break;
10524 case 'p': USE_BITS (DELTA
); break;
10525 case 'q': USE_BITS (CODE2
); break;
10526 case 'r': USE_BITS (RS
); break;
10527 case 's': USE_BITS (RS
); break;
10528 case 't': USE_BITS (RT
); break;
10529 case 'u': USE_BITS (IMMEDIATE
); break;
10530 case 'v': USE_BITS (RS
); break;
10531 case 'w': USE_BITS (RT
); break;
10532 case 'y': USE_BITS (RS3
); break;
10534 case '|': USE_BITS (TRAP
); break;
10535 case '~': USE_BITS (OFFSET12
); break;
10537 as_bad (_("Internal error: bad microMIPS opcode "
10538 "(unknown operand type `%c'): %s %s"),
10539 c
, opc
->name
, opc
->args
);
10543 if (used_bits
!= insn_bits
)
10545 if (~used_bits
& insn_bits
)
10546 as_bad (_("Internal error: bad microMIPS opcode "
10547 "(bits 0x%lx undefined): %s %s"),
10548 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10549 if (used_bits
& ~insn_bits
)
10550 as_bad (_("Internal error: bad microMIPS opcode "
10551 "(bits 0x%lx defined): %s %s"),
10552 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10558 /* UDI immediates. */
10559 struct mips_immed
{
10561 unsigned int shift
;
10562 unsigned long mask
;
10566 static const struct mips_immed mips_immed
[] = {
10567 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10568 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10569 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10570 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10574 /* Check whether an odd floating-point register is allowed. */
10576 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10578 const char *s
= insn
->name
;
10580 if (insn
->pinfo
== INSN_MACRO
)
10581 /* Let a macro pass, we'll catch it later when it is expanded. */
10584 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
10586 /* Allow odd registers for single-precision ops. */
10587 switch (insn
->pinfo
& (FP_S
| FP_D
))
10591 return 1; /* both single precision - ok */
10593 return 0; /* both double precision - fail */
10598 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10599 s
= strchr (insn
->name
, '.');
10601 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10602 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10605 /* Single-precision coprocessor loads and moves are OK too. */
10606 if ((insn
->pinfo
& FP_S
)
10607 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10608 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10614 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10615 taking bits from BIT up. */
10617 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10619 return (ep
->X_op
== O_constant
10620 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10621 && ep
->X_add_number
>= min
<< bit
10622 && ep
->X_add_number
< max
<< bit
);
10625 /* This routine assembles an instruction into its binary format. As a
10626 side effect, it sets one of the global variables imm_reloc or
10627 offset_reloc to the type of relocation to do if one of the operands
10628 is an address expression. */
10631 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10633 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10634 bfd_boolean need_delay_slot_ok
= TRUE
;
10635 struct mips_opcode
*firstinsn
= NULL
;
10636 const struct mips_opcode
*past
;
10637 struct hash_control
*hash
;
10641 struct mips_opcode
*insn
;
10643 unsigned int regno
;
10644 unsigned int lastregno
;
10645 unsigned int destregno
= 0;
10646 unsigned int lastpos
= 0;
10647 unsigned int limlo
, limhi
;
10649 offsetT min_range
, max_range
;
10653 unsigned int rtype
;
10659 if (mips_opts
.micromips
)
10661 hash
= micromips_op_hash
;
10662 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10667 past
= &mips_opcodes
[NUMOPCODES
];
10669 forced_insn_length
= 0;
10672 /* We first try to match an instruction up to a space or to the end. */
10673 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10676 /* Make a copy of the instruction so that we can fiddle with it. */
10677 name
= alloca (end
+ 1);
10678 memcpy (name
, str
, end
);
10683 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10685 if (insn
!= NULL
|| !mips_opts
.micromips
)
10687 if (forced_insn_length
)
10690 /* See if there's an instruction size override suffix,
10691 either `16' or `32', at the end of the mnemonic proper,
10692 that defines the operation, i.e. before the first `.'
10693 character if any. Strip it and retry. */
10694 dot
= strchr (name
, '.');
10695 opend
= dot
!= NULL
? dot
- name
: end
;
10698 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10699 forced_insn_length
= 2;
10700 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10701 forced_insn_length
= 4;
10704 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10708 insn_error
= _("Unrecognized opcode");
10712 /* For microMIPS instructions placed in a fixed-length branch delay slot
10713 we make up to two passes over the relevant fragment of the opcode
10714 table. First we try instructions that meet the delay slot's length
10715 requirement. If none matched, then we retry with the remaining ones
10716 and if one matches, then we use it and then issue an appropriate
10717 warning later on. */
10718 argsStart
= s
= str
+ end
;
10721 bfd_boolean delay_slot_ok
;
10722 bfd_boolean size_ok
;
10725 gas_assert (strcmp (insn
->name
, name
) == 0);
10727 ok
= is_opcode_valid (insn
);
10728 size_ok
= is_size_valid (insn
);
10729 delay_slot_ok
= is_delay_slot_valid (insn
);
10730 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10733 wrong_delay_slot_insns
= TRUE
;
10735 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10737 static char buf
[256];
10739 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10744 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10746 gas_assert (firstinsn
);
10747 need_delay_slot_ok
= FALSE
;
10757 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10758 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10759 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10761 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10762 8 * forced_insn_length
);
10768 create_insn (ip
, insn
);
10771 lastregno
= 0xffffffff;
10772 for (args
= insn
->args
;; ++args
)
10776 s
+= strspn (s
, " \t");
10780 case '\0': /* end of args */
10786 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10787 code) or 14 (for microMIPS code). */
10788 my_getExpression (&imm_expr
, s
);
10789 check_absolute_expr (ip
, &imm_expr
);
10790 if ((unsigned long) imm_expr
.X_add_number
!= 1
10791 && (unsigned long) imm_expr
.X_add_number
!= 3)
10793 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10794 (unsigned long) imm_expr
.X_add_number
);
10796 INSERT_OPERAND (mips_opts
.micromips
,
10797 BP
, *ip
, imm_expr
.X_add_number
);
10798 imm_expr
.X_op
= O_absent
;
10803 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10804 code) or 21 (for microMIPS code). */
10806 unsigned long mask
= (mips_opts
.micromips
10807 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10809 my_getExpression (&imm_expr
, s
);
10810 check_absolute_expr (ip
, &imm_expr
);
10811 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10812 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10813 mask
, (unsigned long) imm_expr
.X_add_number
);
10814 INSERT_OPERAND (mips_opts
.micromips
,
10815 SA3
, *ip
, imm_expr
.X_add_number
);
10816 imm_expr
.X_op
= O_absent
;
10822 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10823 code) or 21 (for microMIPS code). */
10825 unsigned long mask
= (mips_opts
.micromips
10826 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10828 my_getExpression (&imm_expr
, s
);
10829 check_absolute_expr (ip
, &imm_expr
);
10830 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10831 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10832 mask
, (unsigned long) imm_expr
.X_add_number
);
10833 INSERT_OPERAND (mips_opts
.micromips
,
10834 SA4
, *ip
, imm_expr
.X_add_number
);
10835 imm_expr
.X_op
= O_absent
;
10841 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10842 code) or 16 (for microMIPS code). */
10844 unsigned long mask
= (mips_opts
.micromips
10845 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
10847 my_getExpression (&imm_expr
, s
);
10848 check_absolute_expr (ip
, &imm_expr
);
10849 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10850 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10851 mask
, (unsigned long) imm_expr
.X_add_number
);
10852 INSERT_OPERAND (mips_opts
.micromips
,
10853 IMM8
, *ip
, imm_expr
.X_add_number
);
10854 imm_expr
.X_op
= O_absent
;
10860 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10861 code) or 21 (for microMIPS code). */
10863 unsigned long mask
= (mips_opts
.micromips
10864 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
10866 my_getExpression (&imm_expr
, s
);
10867 check_absolute_expr (ip
, &imm_expr
);
10868 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10869 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10870 mask
, (unsigned long) imm_expr
.X_add_number
);
10871 INSERT_OPERAND (mips_opts
.micromips
,
10872 RS
, *ip
, imm_expr
.X_add_number
);
10873 imm_expr
.X_op
= O_absent
;
10878 case '7': /* Four DSP accumulators in bits 11,12. */
10879 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10880 && s
[3] >= '0' && s
[3] <= '3')
10882 regno
= s
[3] - '0';
10884 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
10888 as_bad (_("Invalid dsp acc register"));
10892 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10893 code) or 14 (for microMIPS code). */
10895 unsigned long mask
= (mips_opts
.micromips
10896 ? MICROMIPSOP_MASK_WRDSP
10899 my_getExpression (&imm_expr
, s
);
10900 check_absolute_expr (ip
, &imm_expr
);
10901 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10902 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10903 mask
, (unsigned long) imm_expr
.X_add_number
);
10904 INSERT_OPERAND (mips_opts
.micromips
,
10905 WRDSP
, *ip
, imm_expr
.X_add_number
);
10906 imm_expr
.X_op
= O_absent
;
10911 case '9': /* Four DSP accumulators in bits 21,22. */
10912 gas_assert (!mips_opts
.micromips
);
10913 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
10914 && s
[3] >= '0' && s
[3] <= '3')
10916 regno
= s
[3] - '0';
10918 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
10922 as_bad (_("Invalid dsp acc register"));
10926 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10927 code) or 20 (for microMIPS code). */
10929 long mask
= (mips_opts
.micromips
10930 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
10932 my_getExpression (&imm_expr
, s
);
10933 check_absolute_expr (ip
, &imm_expr
);
10934 min_range
= -((mask
+ 1) >> 1);
10935 max_range
= ((mask
+ 1) >> 1) - 1;
10936 if (imm_expr
.X_add_number
< min_range
10937 || imm_expr
.X_add_number
> max_range
)
10938 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10939 (long) min_range
, (long) max_range
,
10940 (long) imm_expr
.X_add_number
);
10941 INSERT_OPERAND (mips_opts
.micromips
,
10942 DSPSFT
, *ip
, imm_expr
.X_add_number
);
10943 imm_expr
.X_op
= O_absent
;
10948 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10949 gas_assert (!mips_opts
.micromips
);
10950 my_getExpression (&imm_expr
, s
);
10951 check_absolute_expr (ip
, &imm_expr
);
10952 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
10954 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10956 (unsigned long) imm_expr
.X_add_number
);
10958 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
10959 imm_expr
.X_op
= O_absent
;
10963 case ':': /* DSP 7-bit signed immediate in bit 19. */
10964 gas_assert (!mips_opts
.micromips
);
10965 my_getExpression (&imm_expr
, s
);
10966 check_absolute_expr (ip
, &imm_expr
);
10967 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
10968 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
10969 if (imm_expr
.X_add_number
< min_range
||
10970 imm_expr
.X_add_number
> max_range
)
10972 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10973 (long) min_range
, (long) max_range
,
10974 (long) imm_expr
.X_add_number
);
10976 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
10977 imm_expr
.X_op
= O_absent
;
10981 case '@': /* DSP 10-bit signed immediate in bit 16. */
10983 long mask
= (mips_opts
.micromips
10984 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
10986 my_getExpression (&imm_expr
, s
);
10987 check_absolute_expr (ip
, &imm_expr
);
10988 min_range
= -((mask
+ 1) >> 1);
10989 max_range
= ((mask
+ 1) >> 1) - 1;
10990 if (imm_expr
.X_add_number
< min_range
10991 || imm_expr
.X_add_number
> max_range
)
10992 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10993 (long) min_range
, (long) max_range
,
10994 (long) imm_expr
.X_add_number
);
10995 INSERT_OPERAND (mips_opts
.micromips
,
10996 IMM10
, *ip
, imm_expr
.X_add_number
);
10997 imm_expr
.X_op
= O_absent
;
11002 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11003 gas_assert (mips_opts
.micromips
);
11004 my_getExpression (&imm_expr
, s
);
11005 check_absolute_expr (ip
, &imm_expr
);
11006 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11007 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11008 MICROMIPSOP_MASK_RD
,
11009 (unsigned long) imm_expr
.X_add_number
);
11010 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11011 imm_expr
.X_op
= O_absent
;
11015 case '!': /* MT usermode flag bit. */
11016 gas_assert (!mips_opts
.micromips
);
11017 my_getExpression (&imm_expr
, s
);
11018 check_absolute_expr (ip
, &imm_expr
);
11019 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11020 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11021 (unsigned long) imm_expr
.X_add_number
);
11022 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11023 imm_expr
.X_op
= O_absent
;
11027 case '$': /* MT load high flag bit. */
11028 gas_assert (!mips_opts
.micromips
);
11029 my_getExpression (&imm_expr
, s
);
11030 check_absolute_expr (ip
, &imm_expr
);
11031 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11032 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11033 (unsigned long) imm_expr
.X_add_number
);
11034 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11035 imm_expr
.X_op
= O_absent
;
11039 case '*': /* Four DSP accumulators in bits 18,19. */
11040 gas_assert (!mips_opts
.micromips
);
11041 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11042 s
[3] >= '0' && s
[3] <= '3')
11044 regno
= s
[3] - '0';
11046 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11050 as_bad (_("Invalid dsp/smartmips acc register"));
11053 case '&': /* Four DSP accumulators in bits 13,14. */
11054 gas_assert (!mips_opts
.micromips
);
11055 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11056 s
[3] >= '0' && s
[3] <= '3')
11058 regno
= s
[3] - '0';
11060 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11064 as_bad (_("Invalid dsp/smartmips acc register"));
11067 case '\\': /* 3-bit bit position. */
11069 unsigned long mask
= (mips_opts
.micromips
11070 ? MICROMIPSOP_MASK_3BITPOS
11071 : OP_MASK_3BITPOS
);
11073 my_getExpression (&imm_expr
, s
);
11074 check_absolute_expr (ip
, &imm_expr
);
11075 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11076 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11078 mask
, (unsigned long) imm_expr
.X_add_number
);
11079 INSERT_OPERAND (mips_opts
.micromips
,
11080 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11081 imm_expr
.X_op
= O_absent
;
11095 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11099 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11103 gas_assert (!mips_opts
.micromips
);
11104 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11108 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11114 /* Handle optional base register.
11115 Either the base register is omitted or
11116 we must have a left paren. */
11117 /* This is dependent on the next operand specifier
11118 is a base register specification. */
11119 gas_assert (args
[1] == 'b'
11120 || (mips_opts
.micromips
11122 && (args
[2] == 'l' || args
[2] == 'n'
11123 || args
[2] == 's' || args
[2] == 'a')));
11124 if (*s
== '\0' && args
[1] == 'b')
11126 /* Fall through. */
11128 case ')': /* These must match exactly. */
11133 case '[': /* These must match exactly. */
11135 gas_assert (!mips_opts
.micromips
);
11140 case '+': /* Opcode extension character. */
11143 case '1': /* UDI immediates. */
11147 gas_assert (!mips_opts
.micromips
);
11149 const struct mips_immed
*imm
= mips_immed
;
11151 while (imm
->type
&& imm
->type
!= *args
)
11155 my_getExpression (&imm_expr
, s
);
11156 check_absolute_expr (ip
, &imm_expr
);
11157 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11159 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11160 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11161 (unsigned long) imm_expr
.X_add_number
,
11162 (unsigned long) imm_expr
.X_add_number
);
11163 imm_expr
.X_add_number
&= imm
->mask
;
11165 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11167 imm_expr
.X_op
= O_absent
;
11172 case 'A': /* ins/ext position, becomes LSB. */
11181 my_getExpression (&imm_expr
, s
);
11182 check_absolute_expr (ip
, &imm_expr
);
11183 if ((unsigned long) imm_expr
.X_add_number
< limlo
11184 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11186 as_bad (_("Improper position (%lu)"),
11187 (unsigned long) imm_expr
.X_add_number
);
11188 imm_expr
.X_add_number
= limlo
;
11190 lastpos
= imm_expr
.X_add_number
;
11191 INSERT_OPERAND (mips_opts
.micromips
,
11192 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11193 imm_expr
.X_op
= O_absent
;
11197 case 'B': /* ins size, becomes MSB. */
11206 my_getExpression (&imm_expr
, s
);
11207 check_absolute_expr (ip
, &imm_expr
);
11208 /* Check for negative input so that small negative numbers
11209 will not succeed incorrectly. The checks against
11210 (pos+size) transitively check "size" itself,
11211 assuming that "pos" is reasonable. */
11212 if ((long) imm_expr
.X_add_number
< 0
11213 || ((unsigned long) imm_expr
.X_add_number
11215 || ((unsigned long) imm_expr
.X_add_number
11216 + lastpos
) > limhi
)
11218 as_bad (_("Improper insert size (%lu, position %lu)"),
11219 (unsigned long) imm_expr
.X_add_number
,
11220 (unsigned long) lastpos
);
11221 imm_expr
.X_add_number
= limlo
- lastpos
;
11223 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11224 lastpos
+ imm_expr
.X_add_number
- 1);
11225 imm_expr
.X_op
= O_absent
;
11229 case 'C': /* ext size, becomes MSBD. */
11242 my_getExpression (&imm_expr
, s
);
11243 check_absolute_expr (ip
, &imm_expr
);
11244 /* Check for negative input so that small negative numbers
11245 will not succeed incorrectly. The checks against
11246 (pos+size) transitively check "size" itself,
11247 assuming that "pos" is reasonable. */
11248 if ((long) imm_expr
.X_add_number
< 0
11249 || ((unsigned long) imm_expr
.X_add_number
11251 || ((unsigned long) imm_expr
.X_add_number
11252 + lastpos
) > limhi
)
11254 as_bad (_("Improper extract size (%lu, position %lu)"),
11255 (unsigned long) imm_expr
.X_add_number
,
11256 (unsigned long) lastpos
);
11257 imm_expr
.X_add_number
= limlo
- lastpos
;
11259 INSERT_OPERAND (mips_opts
.micromips
,
11260 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11261 imm_expr
.X_op
= O_absent
;
11266 /* +D is for disassembly only; never match. */
11270 /* "+I" is like "I", except that imm2_expr is used. */
11271 my_getExpression (&imm2_expr
, s
);
11272 if (imm2_expr
.X_op
!= O_big
11273 && imm2_expr
.X_op
!= O_constant
)
11274 insn_error
= _("absolute expression required");
11275 if (HAVE_32BIT_GPRS
)
11276 normalize_constant_expr (&imm2_expr
);
11280 case 'T': /* Coprocessor register. */
11281 gas_assert (!mips_opts
.micromips
);
11282 /* +T is for disassembly only; never match. */
11285 case 't': /* Coprocessor register number. */
11286 gas_assert (!mips_opts
.micromips
);
11287 if (s
[0] == '$' && ISDIGIT (s
[1]))
11297 while (ISDIGIT (*s
));
11299 as_bad (_("Invalid register number (%d)"), regno
);
11302 INSERT_OPERAND (0, RT
, *ip
, regno
);
11307 as_bad (_("Invalid coprocessor 0 register number"));
11311 /* bbit[01] and bbit[01]32 bit index. Give error if index
11312 is not in the valid range. */
11313 gas_assert (!mips_opts
.micromips
);
11314 my_getExpression (&imm_expr
, s
);
11315 check_absolute_expr (ip
, &imm_expr
);
11316 if ((unsigned) imm_expr
.X_add_number
> 31)
11318 as_bad (_("Improper bit index (%lu)"),
11319 (unsigned long) imm_expr
.X_add_number
);
11320 imm_expr
.X_add_number
= 0;
11322 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11323 imm_expr
.X_op
= O_absent
;
11328 /* bbit[01] bit index when bbit is used but we generate
11329 bbit[01]32 because the index is over 32. Move to the
11330 next candidate if index is not in the valid range. */
11331 gas_assert (!mips_opts
.micromips
);
11332 my_getExpression (&imm_expr
, s
);
11333 check_absolute_expr (ip
, &imm_expr
);
11334 if ((unsigned) imm_expr
.X_add_number
< 32
11335 || (unsigned) imm_expr
.X_add_number
> 63)
11337 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11338 imm_expr
.X_op
= O_absent
;
11343 /* cins, cins32, exts and exts32 position field. Give error
11344 if it's not in the valid range. */
11345 gas_assert (!mips_opts
.micromips
);
11346 my_getExpression (&imm_expr
, s
);
11347 check_absolute_expr (ip
, &imm_expr
);
11348 if ((unsigned) imm_expr
.X_add_number
> 31)
11350 as_bad (_("Improper position (%lu)"),
11351 (unsigned long) imm_expr
.X_add_number
);
11352 imm_expr
.X_add_number
= 0;
11354 /* Make the pos explicit to simplify +S. */
11355 lastpos
= imm_expr
.X_add_number
+ 32;
11356 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11357 imm_expr
.X_op
= O_absent
;
11362 /* cins, cins32, exts and exts32 position field. Move to
11363 the next candidate if it's not in the valid range. */
11364 gas_assert (!mips_opts
.micromips
);
11365 my_getExpression (&imm_expr
, s
);
11366 check_absolute_expr (ip
, &imm_expr
);
11367 if ((unsigned) imm_expr
.X_add_number
< 32
11368 || (unsigned) imm_expr
.X_add_number
> 63)
11370 lastpos
= imm_expr
.X_add_number
;
11371 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11372 imm_expr
.X_op
= O_absent
;
11377 /* cins and exts length-minus-one field. */
11378 gas_assert (!mips_opts
.micromips
);
11379 my_getExpression (&imm_expr
, s
);
11380 check_absolute_expr (ip
, &imm_expr
);
11381 if ((unsigned long) imm_expr
.X_add_number
> 31)
11383 as_bad (_("Improper size (%lu)"),
11384 (unsigned long) imm_expr
.X_add_number
);
11385 imm_expr
.X_add_number
= 0;
11387 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11388 imm_expr
.X_op
= O_absent
;
11393 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11394 length-minus-one field. */
11395 gas_assert (!mips_opts
.micromips
);
11396 my_getExpression (&imm_expr
, s
);
11397 check_absolute_expr (ip
, &imm_expr
);
11398 if ((long) imm_expr
.X_add_number
< 0
11399 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11401 as_bad (_("Improper size (%lu)"),
11402 (unsigned long) imm_expr
.X_add_number
);
11403 imm_expr
.X_add_number
= 0;
11405 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11406 imm_expr
.X_op
= O_absent
;
11411 /* seqi/snei immediate field. */
11412 gas_assert (!mips_opts
.micromips
);
11413 my_getExpression (&imm_expr
, s
);
11414 check_absolute_expr (ip
, &imm_expr
);
11415 if ((long) imm_expr
.X_add_number
< -512
11416 || (long) imm_expr
.X_add_number
>= 512)
11418 as_bad (_("Improper immediate (%ld)"),
11419 (long) imm_expr
.X_add_number
);
11420 imm_expr
.X_add_number
= 0;
11422 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11423 imm_expr
.X_op
= O_absent
;
11427 case 'a': /* 8-bit signed offset in bit 6 */
11428 gas_assert (!mips_opts
.micromips
);
11429 my_getExpression (&imm_expr
, s
);
11430 check_absolute_expr (ip
, &imm_expr
);
11431 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11432 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11433 if (imm_expr
.X_add_number
< min_range
11434 || imm_expr
.X_add_number
> max_range
)
11436 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11437 (long) min_range
, (long) max_range
,
11438 (long) imm_expr
.X_add_number
);
11440 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11441 imm_expr
.X_op
= O_absent
;
11445 case 'b': /* 8-bit signed offset in bit 3 */
11446 gas_assert (!mips_opts
.micromips
);
11447 my_getExpression (&imm_expr
, s
);
11448 check_absolute_expr (ip
, &imm_expr
);
11449 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11450 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11451 if (imm_expr
.X_add_number
< min_range
11452 || imm_expr
.X_add_number
> max_range
)
11454 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11455 (long) min_range
, (long) max_range
,
11456 (long) imm_expr
.X_add_number
);
11458 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11459 imm_expr
.X_op
= O_absent
;
11463 case 'c': /* 9-bit signed offset in bit 6 */
11464 gas_assert (!mips_opts
.micromips
);
11465 my_getExpression (&imm_expr
, s
);
11466 check_absolute_expr (ip
, &imm_expr
);
11467 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11468 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11469 /* We check the offset range before adjusted. */
11472 if (imm_expr
.X_add_number
< min_range
11473 || imm_expr
.X_add_number
> max_range
)
11475 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11476 (long) min_range
, (long) max_range
,
11477 (long) imm_expr
.X_add_number
);
11479 if (imm_expr
.X_add_number
& 0xf)
11481 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11482 (long) imm_expr
.X_add_number
);
11484 /* Right shift 4 bits to adjust the offset operand. */
11485 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11486 imm_expr
.X_add_number
>> 4);
11487 imm_expr
.X_op
= O_absent
;
11492 gas_assert (!mips_opts
.micromips
);
11493 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11495 if (regno
== AT
&& mips_opts
.at
)
11497 if (mips_opts
.at
== ATREG
)
11498 as_warn (_("used $at without \".set noat\""));
11500 as_warn (_("used $%u with \".set at=$%u\""),
11501 regno
, mips_opts
.at
);
11503 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11507 gas_assert (!mips_opts
.micromips
);
11508 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11510 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11514 as_bad (_("Internal error: bad %s opcode "
11515 "(unknown extension operand type `+%c'): %s %s"),
11516 mips_opts
.micromips
? "microMIPS" : "MIPS",
11517 *args
, insn
->name
, insn
->args
);
11518 /* Further processing is fruitless. */
11523 case '.': /* 10-bit offset. */
11524 gas_assert (mips_opts
.micromips
);
11525 case '~': /* 12-bit offset. */
11527 int shift
= *args
== '.' ? 9 : 11;
11530 /* Check whether there is only a single bracketed expression
11531 left. If so, it must be the base register and the
11532 constant must be zero. */
11533 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11536 /* If this value won't fit into the offset, then go find
11537 a macro that will generate a 16- or 32-bit offset code
11539 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11540 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11541 || imm_expr
.X_add_number
>= 1 << shift
11542 || imm_expr
.X_add_number
< -1 << shift
))
11545 imm_expr
.X_op
= O_absent
;
11549 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11551 INSERT_OPERAND (mips_opts
.micromips
,
11552 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11553 imm_expr
.X_op
= O_absent
;
11558 case '<': /* must be at least one digit */
11560 * According to the manual, if the shift amount is greater
11561 * than 31 or less than 0, then the shift amount should be
11562 * mod 32. In reality the mips assembler issues an error.
11563 * We issue a warning and mask out all but the low 5 bits.
11565 my_getExpression (&imm_expr
, s
);
11566 check_absolute_expr (ip
, &imm_expr
);
11567 if ((unsigned long) imm_expr
.X_add_number
> 31)
11568 as_warn (_("Improper shift amount (%lu)"),
11569 (unsigned long) imm_expr
.X_add_number
);
11570 INSERT_OPERAND (mips_opts
.micromips
,
11571 SHAMT
, *ip
, imm_expr
.X_add_number
);
11572 imm_expr
.X_op
= O_absent
;
11576 case '>': /* shift amount minus 32 */
11577 my_getExpression (&imm_expr
, s
);
11578 check_absolute_expr (ip
, &imm_expr
);
11579 if ((unsigned long) imm_expr
.X_add_number
< 32
11580 || (unsigned long) imm_expr
.X_add_number
> 63)
11582 INSERT_OPERAND (mips_opts
.micromips
,
11583 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11584 imm_expr
.X_op
= O_absent
;
11588 case 'k': /* CACHE code. */
11589 case 'h': /* PREFX code. */
11590 case '1': /* SYNC type. */
11591 my_getExpression (&imm_expr
, s
);
11592 check_absolute_expr (ip
, &imm_expr
);
11593 if ((unsigned long) imm_expr
.X_add_number
> 31)
11594 as_warn (_("Invalid value for `%s' (%lu)"),
11596 (unsigned long) imm_expr
.X_add_number
);
11600 if (mips_fix_cn63xxp1
11601 && !mips_opts
.micromips
11602 && strcmp ("pref", insn
->name
) == 0)
11603 switch (imm_expr
.X_add_number
)
11612 case 31: /* These are ok. */
11615 default: /* The rest must be changed to 28. */
11616 imm_expr
.X_add_number
= 28;
11619 INSERT_OPERAND (mips_opts
.micromips
,
11620 CACHE
, *ip
, imm_expr
.X_add_number
);
11623 INSERT_OPERAND (mips_opts
.micromips
,
11624 PREFX
, *ip
, imm_expr
.X_add_number
);
11627 INSERT_OPERAND (mips_opts
.micromips
,
11628 STYPE
, *ip
, imm_expr
.X_add_number
);
11631 imm_expr
.X_op
= O_absent
;
11635 case 'c': /* BREAK code. */
11637 unsigned long mask
= (mips_opts
.micromips
11638 ? MICROMIPSOP_MASK_CODE
11641 my_getExpression (&imm_expr
, s
);
11642 check_absolute_expr (ip
, &imm_expr
);
11643 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11644 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11646 mask
, (unsigned long) imm_expr
.X_add_number
);
11647 INSERT_OPERAND (mips_opts
.micromips
,
11648 CODE
, *ip
, imm_expr
.X_add_number
);
11649 imm_expr
.X_op
= O_absent
;
11654 case 'q': /* Lower BREAK code. */
11656 unsigned long mask
= (mips_opts
.micromips
11657 ? MICROMIPSOP_MASK_CODE2
11660 my_getExpression (&imm_expr
, s
);
11661 check_absolute_expr (ip
, &imm_expr
);
11662 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11663 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11665 mask
, (unsigned long) imm_expr
.X_add_number
);
11666 INSERT_OPERAND (mips_opts
.micromips
,
11667 CODE2
, *ip
, imm_expr
.X_add_number
);
11668 imm_expr
.X_op
= O_absent
;
11673 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11675 unsigned long mask
= (mips_opts
.micromips
11676 ? MICROMIPSOP_MASK_CODE10
11679 my_getExpression (&imm_expr
, s
);
11680 check_absolute_expr (ip
, &imm_expr
);
11681 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11682 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11684 mask
, (unsigned long) imm_expr
.X_add_number
);
11685 if (mips_opts
.micromips
)
11686 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11688 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11689 imm_expr
.X_op
= O_absent
;
11694 case 'C': /* 25- or 23-bit coprocessor code. */
11696 unsigned long mask
= (mips_opts
.micromips
11697 ? MICROMIPSOP_MASK_COPZ
11700 my_getExpression (&imm_expr
, s
);
11701 check_absolute_expr (ip
, &imm_expr
);
11702 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11703 as_warn (_("Coproccesor code > %u bits (%lu)"),
11704 mips_opts
.micromips
? 23U : 25U,
11705 (unsigned long) imm_expr
.X_add_number
);
11706 INSERT_OPERAND (mips_opts
.micromips
,
11707 COPZ
, *ip
, imm_expr
.X_add_number
);
11708 imm_expr
.X_op
= O_absent
;
11713 case 'J': /* 19-bit WAIT code. */
11714 gas_assert (!mips_opts
.micromips
);
11715 my_getExpression (&imm_expr
, s
);
11716 check_absolute_expr (ip
, &imm_expr
);
11717 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11719 as_warn (_("Illegal 19-bit code (%lu)"),
11720 (unsigned long) imm_expr
.X_add_number
);
11721 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11723 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11724 imm_expr
.X_op
= O_absent
;
11728 case 'P': /* Performance register. */
11729 gas_assert (!mips_opts
.micromips
);
11730 my_getExpression (&imm_expr
, s
);
11731 check_absolute_expr (ip
, &imm_expr
);
11732 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11733 as_warn (_("Invalid performance register (%lu)"),
11734 (unsigned long) imm_expr
.X_add_number
);
11735 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11736 imm_expr
.X_op
= O_absent
;
11740 case 'G': /* Coprocessor destination register. */
11742 unsigned long opcode
= ip
->insn_opcode
;
11743 unsigned long mask
;
11744 unsigned int types
;
11747 if (mips_opts
.micromips
)
11749 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11750 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11751 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11755 case 0x000000fc: /* mfc0 */
11756 case 0x000002fc: /* mtc0 */
11757 case 0x580000fc: /* dmfc0 */
11758 case 0x580002fc: /* dmtc0 */
11768 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11769 cop0
= opcode
== OP_OP_COP0
;
11771 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11772 ok
= reg_lookup (&s
, types
, ®no
);
11773 if (mips_opts
.micromips
)
11774 INSERT_OPERAND (1, RS
, *ip
, regno
);
11776 INSERT_OPERAND (0, RD
, *ip
, regno
);
11785 case 'y': /* ALNV.PS source register. */
11786 gas_assert (mips_opts
.micromips
);
11788 case 'x': /* Ignore register name. */
11789 case 'U': /* Destination register (CLO/CLZ). */
11790 case 'g': /* Coprocessor destination register. */
11791 gas_assert (!mips_opts
.micromips
);
11792 case 'b': /* Base register. */
11793 case 'd': /* Destination register. */
11794 case 's': /* Source register. */
11795 case 't': /* Target register. */
11796 case 'r': /* Both target and source. */
11797 case 'v': /* Both dest and source. */
11798 case 'w': /* Both dest and target. */
11799 case 'E': /* Coprocessor target register. */
11800 case 'K': /* RDHWR destination register. */
11801 case 'z': /* Must be zero register. */
11804 if (*args
== 'E' || *args
== 'K')
11805 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11808 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11809 if (regno
== AT
&& mips_opts
.at
)
11811 if (mips_opts
.at
== ATREG
)
11812 as_warn (_("Used $at without \".set noat\""));
11814 as_warn (_("Used $%u with \".set at=$%u\""),
11815 regno
, mips_opts
.at
);
11825 if (c
== 'r' || c
== 'v' || c
== 'w')
11832 /* 'z' only matches $0. */
11833 if (c
== 'z' && regno
!= 0)
11836 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
11838 if (regno
== lastregno
)
11841 = _("Source and destination must be different");
11844 if (regno
== 31 && lastregno
== 0xffffffff)
11847 = _("A destination register must be supplied");
11851 /* Now that we have assembled one operand, we use the args
11852 string to figure out where it goes in the instruction. */
11859 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
11863 if (mips_opts
.micromips
)
11864 INSERT_OPERAND (1, RS
, *ip
, regno
);
11866 INSERT_OPERAND (0, RD
, *ip
, regno
);
11871 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
11875 gas_assert (!mips_opts
.micromips
);
11876 INSERT_OPERAND (0, RD
, *ip
, regno
);
11877 INSERT_OPERAND (0, RT
, *ip
, regno
);
11883 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
11887 gas_assert (mips_opts
.micromips
);
11888 INSERT_OPERAND (1, RS3
, *ip
, regno
);
11892 /* This case exists because on the r3000 trunc
11893 expands into a macro which requires a gp
11894 register. On the r6000 or r4000 it is
11895 assembled into a single instruction which
11896 ignores the register. Thus the insn version
11897 is MIPS_ISA2 and uses 'x', and the macro
11898 version is MIPS_ISA1 and uses 't'. */
11902 /* This case is for the div instruction, which
11903 acts differently if the destination argument
11904 is $0. This only matches $0, and is checked
11905 outside the switch. */
11915 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11919 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11924 case 'O': /* MDMX alignment immediate constant. */
11925 gas_assert (!mips_opts
.micromips
);
11926 my_getExpression (&imm_expr
, s
);
11927 check_absolute_expr (ip
, &imm_expr
);
11928 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
11929 as_warn (_("Improper align amount (%ld), using low bits"),
11930 (long) imm_expr
.X_add_number
);
11931 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
11932 imm_expr
.X_op
= O_absent
;
11936 case 'Q': /* MDMX vector, element sel, or const. */
11939 /* MDMX Immediate. */
11940 gas_assert (!mips_opts
.micromips
);
11941 my_getExpression (&imm_expr
, s
);
11942 check_absolute_expr (ip
, &imm_expr
);
11943 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
11944 as_warn (_("Invalid MDMX Immediate (%ld)"),
11945 (long) imm_expr
.X_add_number
);
11946 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
11947 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
11948 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
11950 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
11951 imm_expr
.X_op
= O_absent
;
11955 /* Not MDMX Immediate. Fall through. */
11956 case 'X': /* MDMX destination register. */
11957 case 'Y': /* MDMX source register. */
11958 case 'Z': /* MDMX target register. */
11961 gas_assert (!mips_opts
.micromips
);
11962 case 'D': /* Floating point destination register. */
11963 case 'S': /* Floating point source register. */
11964 case 'T': /* Floating point target register. */
11965 case 'R': /* Floating point source register. */
11969 || (mips_opts
.ase_mdmx
11970 && (ip
->insn_mo
->pinfo
& FP_D
)
11971 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
11972 | INSN_COPROC_MEMORY_DELAY
11973 | INSN_LOAD_COPROC_DELAY
11974 | INSN_LOAD_MEMORY_DELAY
11975 | INSN_STORE_MEMORY
))))
11976 rtype
|= RTYPE_VEC
;
11978 if (reg_lookup (&s
, rtype
, ®no
))
11980 if ((regno
& 1) != 0
11982 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
11983 as_warn (_("Float register should be even, was %d"),
11991 if (c
== 'V' || c
== 'W')
12002 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12008 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12012 /* This is like 'Z', but also needs to fix the MDMX
12013 vector/scalar select bits. Note that the
12014 scalar immediate case is handled above. */
12017 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12018 int max_el
= (is_qh
? 3 : 7);
12020 my_getExpression(&imm_expr
, s
);
12021 check_absolute_expr (ip
, &imm_expr
);
12023 if (imm_expr
.X_add_number
> max_el
)
12024 as_bad (_("Bad element selector %ld"),
12025 (long) imm_expr
.X_add_number
);
12026 imm_expr
.X_add_number
&= max_el
;
12027 ip
->insn_opcode
|= (imm_expr
.X_add_number
12030 imm_expr
.X_op
= O_absent
;
12032 as_warn (_("Expecting ']' found '%s'"), s
);
12038 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12039 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12042 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12045 /* Fall through. */
12049 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12053 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12063 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12067 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12073 my_getExpression (&imm_expr
, s
);
12074 if (imm_expr
.X_op
!= O_big
12075 && imm_expr
.X_op
!= O_constant
)
12076 insn_error
= _("absolute expression required");
12077 if (HAVE_32BIT_GPRS
)
12078 normalize_constant_expr (&imm_expr
);
12083 my_getExpression (&offset_expr
, s
);
12084 normalize_address_expr (&offset_expr
);
12085 *imm_reloc
= BFD_RELOC_32
;
12098 unsigned char temp
[8];
12100 unsigned int length
;
12105 /* These only appear as the last operand in an
12106 instruction, and every instruction that accepts
12107 them in any variant accepts them in all variants.
12108 This means we don't have to worry about backing out
12109 any changes if the instruction does not match.
12111 The difference between them is the size of the
12112 floating point constant and where it goes. For 'F'
12113 and 'L' the constant is 64 bits; for 'f' and 'l' it
12114 is 32 bits. Where the constant is placed is based
12115 on how the MIPS assembler does things:
12118 f -- immediate value
12121 The .lit4 and .lit8 sections are only used if
12122 permitted by the -G argument.
12124 The code below needs to know whether the target register
12125 is 32 or 64 bits wide. It relies on the fact 'f' and
12126 'F' are used with GPR-based instructions and 'l' and
12127 'L' are used with FPR-based instructions. */
12129 f64
= *args
== 'F' || *args
== 'L';
12130 using_gprs
= *args
== 'F' || *args
== 'f';
12132 save_in
= input_line_pointer
;
12133 input_line_pointer
= s
;
12134 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12136 s
= input_line_pointer
;
12137 input_line_pointer
= save_in
;
12138 if (err
!= NULL
&& *err
!= '\0')
12140 as_bad (_("Bad floating point constant: %s"), err
);
12141 memset (temp
, '\0', sizeof temp
);
12142 length
= f64
? 8 : 4;
12145 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12149 && (g_switch_value
< 4
12150 || (temp
[0] == 0 && temp
[1] == 0)
12151 || (temp
[2] == 0 && temp
[3] == 0))))
12153 imm_expr
.X_op
= O_constant
;
12154 if (!target_big_endian
)
12155 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12157 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12159 else if (length
> 4
12160 && !mips_disable_float_construction
12161 /* Constants can only be constructed in GPRs and
12162 copied to FPRs if the GPRs are at least as wide
12163 as the FPRs. Force the constant into memory if
12164 we are using 64-bit FPRs but the GPRs are only
12167 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12168 && ((temp
[0] == 0 && temp
[1] == 0)
12169 || (temp
[2] == 0 && temp
[3] == 0))
12170 && ((temp
[4] == 0 && temp
[5] == 0)
12171 || (temp
[6] == 0 && temp
[7] == 0)))
12173 /* The value is simple enough to load with a couple of
12174 instructions. If using 32-bit registers, set
12175 imm_expr to the high order 32 bits and offset_expr to
12176 the low order 32 bits. Otherwise, set imm_expr to
12177 the entire 64 bit constant. */
12178 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12180 imm_expr
.X_op
= O_constant
;
12181 offset_expr
.X_op
= O_constant
;
12182 if (!target_big_endian
)
12184 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12185 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12189 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12190 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12192 if (offset_expr
.X_add_number
== 0)
12193 offset_expr
.X_op
= O_absent
;
12195 else if (sizeof (imm_expr
.X_add_number
) > 4)
12197 imm_expr
.X_op
= O_constant
;
12198 if (!target_big_endian
)
12199 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12201 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12205 imm_expr
.X_op
= O_big
;
12206 imm_expr
.X_add_number
= 4;
12207 if (!target_big_endian
)
12209 generic_bignum
[0] = bfd_getl16 (temp
);
12210 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12211 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12212 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12216 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12217 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12218 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12219 generic_bignum
[3] = bfd_getb16 (temp
);
12225 const char *newname
;
12228 /* Switch to the right section. */
12230 subseg
= now_subseg
;
12233 default: /* unused default case avoids warnings. */
12235 newname
= RDATA_SECTION_NAME
;
12236 if (g_switch_value
>= 8)
12240 newname
= RDATA_SECTION_NAME
;
12243 gas_assert (g_switch_value
>= 4);
12247 new_seg
= subseg_new (newname
, (subsegT
) 0);
12249 bfd_set_section_flags (stdoutput
, new_seg
,
12254 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12255 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12256 record_alignment (new_seg
, 4);
12258 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12259 if (seg
== now_seg
)
12260 as_bad (_("Can't use floating point insn in this section"));
12262 /* Set the argument to the current address in the
12264 offset_expr
.X_op
= O_symbol
;
12265 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12266 offset_expr
.X_add_number
= 0;
12268 /* Put the floating point number into the section. */
12269 p
= frag_more ((int) length
);
12270 memcpy (p
, temp
, length
);
12272 /* Switch back to the original section. */
12273 subseg_set (seg
, subseg
);
12278 case 'i': /* 16-bit unsigned immediate. */
12279 case 'j': /* 16-bit signed immediate. */
12280 *imm_reloc
= BFD_RELOC_LO16
;
12281 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12284 offsetT minval
, maxval
;
12286 more
= (insn
+ 1 < past
12287 && strcmp (insn
->name
, insn
[1].name
) == 0);
12289 /* If the expression was written as an unsigned number,
12290 only treat it as signed if there are no more
12294 && sizeof (imm_expr
.X_add_number
) <= 4
12295 && imm_expr
.X_op
== O_constant
12296 && imm_expr
.X_add_number
< 0
12297 && imm_expr
.X_unsigned
12298 && HAVE_64BIT_GPRS
)
12301 /* For compatibility with older assemblers, we accept
12302 0x8000-0xffff as signed 16-bit numbers when only
12303 signed numbers are allowed. */
12305 minval
= 0, maxval
= 0xffff;
12307 minval
= -0x8000, maxval
= 0x7fff;
12309 minval
= -0x8000, maxval
= 0xffff;
12311 if (imm_expr
.X_op
!= O_constant
12312 || imm_expr
.X_add_number
< minval
12313 || imm_expr
.X_add_number
> maxval
)
12317 if (imm_expr
.X_op
== O_constant
12318 || imm_expr
.X_op
== O_big
)
12319 as_bad (_("Expression out of range"));
12325 case 'o': /* 16-bit offset. */
12326 offset_reloc
[0] = BFD_RELOC_LO16
;
12327 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12328 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12330 /* Check whether there is only a single bracketed expression
12331 left. If so, it must be the base register and the
12332 constant must be zero. */
12333 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12335 offset_expr
.X_op
= O_constant
;
12336 offset_expr
.X_add_number
= 0;
12340 /* If this value won't fit into a 16 bit offset, then go
12341 find a macro that will generate the 32 bit offset
12343 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12344 && (offset_expr
.X_op
!= O_constant
12345 || offset_expr
.X_add_number
>= 0x8000
12346 || offset_expr
.X_add_number
< -0x8000))
12352 case 'p': /* PC-relative offset. */
12353 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12354 my_getExpression (&offset_expr
, s
);
12358 case 'u': /* Upper 16 bits. */
12359 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12360 && imm_expr
.X_op
== O_constant
12361 && (imm_expr
.X_add_number
< 0
12362 || imm_expr
.X_add_number
>= 0x10000))
12363 as_bad (_("lui expression (%lu) not in range 0..65535"),
12364 (unsigned long) imm_expr
.X_add_number
);
12368 case 'a': /* 26-bit address. */
12369 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12370 my_getExpression (&offset_expr
, s
);
12374 case 'N': /* 3-bit branch condition code. */
12375 case 'M': /* 3-bit compare condition code. */
12377 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12378 rtype
|= RTYPE_FCC
;
12379 if (!reg_lookup (&s
, rtype
, ®no
))
12381 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12382 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12383 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12384 && (regno
& 1) != 0)
12385 as_warn (_("Condition code register should be even for %s, "
12388 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12389 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12390 && (regno
& 3) != 0)
12391 as_warn (_("Condition code register should be 0 or 4 for %s, "
12395 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12397 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12401 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12412 while (ISDIGIT (*s
));
12415 c
= 8; /* Invalid sel value. */
12418 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12419 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12423 gas_assert (!mips_opts
.micromips
);
12424 /* Must be at least one digit. */
12425 my_getExpression (&imm_expr
, s
);
12426 check_absolute_expr (ip
, &imm_expr
);
12428 if ((unsigned long) imm_expr
.X_add_number
12429 > (unsigned long) OP_MASK_VECBYTE
)
12431 as_bad (_("bad byte vector index (%ld)"),
12432 (long) imm_expr
.X_add_number
);
12433 imm_expr
.X_add_number
= 0;
12436 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12437 imm_expr
.X_op
= O_absent
;
12442 gas_assert (!mips_opts
.micromips
);
12443 my_getExpression (&imm_expr
, s
);
12444 check_absolute_expr (ip
, &imm_expr
);
12446 if ((unsigned long) imm_expr
.X_add_number
12447 > (unsigned long) OP_MASK_VECALIGN
)
12449 as_bad (_("bad byte vector index (%ld)"),
12450 (long) imm_expr
.X_add_number
);
12451 imm_expr
.X_add_number
= 0;
12454 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12455 imm_expr
.X_op
= O_absent
;
12459 case 'm': /* Opcode extension character. */
12460 gas_assert (mips_opts
.micromips
);
12465 if (strncmp (s
, "$pc", 3) == 0)
12493 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12494 if (regno
== AT
&& mips_opts
.at
)
12496 if (mips_opts
.at
== ATREG
)
12497 as_warn (_("Used $at without \".set noat\""));
12499 as_warn (_("Used $%u with \".set at=$%u\""),
12500 regno
, mips_opts
.at
);
12506 gas_assert (args
[1] == ',');
12512 gas_assert (args
[1] == ',');
12514 continue; /* Nothing to do. */
12520 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12522 if (regno
== lastregno
)
12525 = _("Source and destination must be different");
12528 if (regno
== 31 && lastregno
== 0xffffffff)
12531 = _("A destination register must be supplied");
12542 gas_assert (args
[1] == ',');
12549 gas_assert (args
[1] == ',');
12552 continue; /* Nothing to do. */
12556 /* Make sure regno is the same as lastregno. */
12557 if (c
== 't' && regno
!= lastregno
)
12560 /* Make sure regno is the same as destregno. */
12561 if (c
== 'x' && regno
!= destregno
)
12564 /* We need to save regno, before regno maps to the
12565 microMIPS register encoding. */
12575 regno
= ILLEGAL_REG
;
12579 regno
= mips32_to_micromips_reg_b_map
[regno
];
12583 regno
= mips32_to_micromips_reg_c_map
[regno
];
12587 regno
= mips32_to_micromips_reg_d_map
[regno
];
12591 regno
= mips32_to_micromips_reg_e_map
[regno
];
12595 regno
= mips32_to_micromips_reg_f_map
[regno
];
12599 regno
= mips32_to_micromips_reg_g_map
[regno
];
12603 regno
= mips32_to_micromips_reg_h_map
[regno
];
12607 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12612 else if (regno
== 22)
12614 else if (regno
== 5)
12616 else if (regno
== 6)
12618 else if (regno
== 7)
12621 regno
= ILLEGAL_REG
;
12627 else if (regno
== 7)
12630 regno
= ILLEGAL_REG
;
12637 regno
= ILLEGAL_REG
;
12641 regno
= ILLEGAL_REG
;
12647 regno
= mips32_to_micromips_reg_l_map
[regno
];
12651 regno
= mips32_to_micromips_reg_m_map
[regno
];
12655 regno
= mips32_to_micromips_reg_n_map
[regno
];
12659 regno
= mips32_to_micromips_reg_q_map
[regno
];
12664 regno
= ILLEGAL_REG
;
12669 regno
= ILLEGAL_REG
;
12674 regno
= ILLEGAL_REG
;
12677 case 'j': /* Do nothing. */
12687 if (regno
== ILLEGAL_REG
)
12693 INSERT_OPERAND (1, MB
, *ip
, regno
);
12697 INSERT_OPERAND (1, MC
, *ip
, regno
);
12701 INSERT_OPERAND (1, MD
, *ip
, regno
);
12705 INSERT_OPERAND (1, ME
, *ip
, regno
);
12709 INSERT_OPERAND (1, MF
, *ip
, regno
);
12713 INSERT_OPERAND (1, MG
, *ip
, regno
);
12717 INSERT_OPERAND (1, MH
, *ip
, regno
);
12721 INSERT_OPERAND (1, MI
, *ip
, regno
);
12725 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12729 INSERT_OPERAND (1, ML
, *ip
, regno
);
12733 INSERT_OPERAND (1, MM
, *ip
, regno
);
12737 INSERT_OPERAND (1, MN
, *ip
, regno
);
12741 INSERT_OPERAND (1, MP
, *ip
, regno
);
12745 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12748 case 'a': /* Do nothing. */
12749 case 's': /* Do nothing. */
12750 case 't': /* Do nothing. */
12751 case 'x': /* Do nothing. */
12752 case 'y': /* Do nothing. */
12753 case 'z': /* Do nothing. */
12763 bfd_reloc_code_real_type r
[3];
12767 /* Check whether there is only a single bracketed
12768 expression left. If so, it must be the base register
12769 and the constant must be zero. */
12770 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12772 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12776 if (my_getSmallExpression (&ep
, r
, s
) > 0
12777 || !expr_const_in_range (&ep
, -64, 64, 2))
12780 imm
= ep
.X_add_number
>> 2;
12781 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12788 bfd_reloc_code_real_type r
[3];
12792 if (my_getSmallExpression (&ep
, r
, s
) > 0
12793 || ep
.X_op
!= O_constant
)
12796 for (imm
= 0; imm
< 8; imm
++)
12797 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12802 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12809 bfd_reloc_code_real_type r
[3];
12813 if (my_getSmallExpression (&ep
, r
, s
) > 0
12814 || ep
.X_op
!= O_constant
)
12817 for (imm
= 0; imm
< 16; imm
++)
12818 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12823 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
12828 case 'D': /* pc relative offset */
12829 case 'E': /* pc relative offset */
12830 my_getExpression (&offset_expr
, s
);
12831 if (offset_expr
.X_op
== O_register
)
12834 if (!forced_insn_length
)
12835 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12837 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12839 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12845 bfd_reloc_code_real_type r
[3];
12849 if (my_getSmallExpression (&ep
, r
, s
) > 0
12850 || !expr_const_in_range (&ep
, 0, 16, 0))
12853 imm
= ep
.X_add_number
;
12854 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
12861 bfd_reloc_code_real_type r
[3];
12865 /* Check whether there is only a single bracketed
12866 expression left. If so, it must be the base register
12867 and the constant must be zero. */
12868 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12870 INSERT_OPERAND (1, IMMG
, *ip
, 0);
12874 if (my_getSmallExpression (&ep
, r
, s
) > 0
12875 || !expr_const_in_range (&ep
, -1, 15, 0))
12878 imm
= ep
.X_add_number
& 15;
12879 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
12886 bfd_reloc_code_real_type r
[3];
12890 /* Check whether there is only a single bracketed
12891 expression left. If so, it must be the base register
12892 and the constant must be zero. */
12893 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12895 INSERT_OPERAND (1, IMMH
, *ip
, 0);
12899 if (my_getSmallExpression (&ep
, r
, s
) > 0
12900 || !expr_const_in_range (&ep
, 0, 16, 1))
12903 imm
= ep
.X_add_number
>> 1;
12904 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
12911 bfd_reloc_code_real_type r
[3];
12915 if (my_getSmallExpression (&ep
, r
, s
) > 0
12916 || !expr_const_in_range (&ep
, -1, 127, 0))
12919 imm
= ep
.X_add_number
& 127;
12920 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
12927 bfd_reloc_code_real_type r
[3];
12931 /* Check whether there is only a single bracketed
12932 expression left. If so, it must be the base register
12933 and the constant must be zero. */
12934 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12936 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
12940 if (my_getSmallExpression (&ep
, r
, s
) > 0
12941 || !expr_const_in_range (&ep
, 0, 16, 2))
12944 imm
= ep
.X_add_number
>> 2;
12945 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
12952 bfd_reloc_code_real_type r
[3];
12956 /* Check whether there is only a single bracketed
12957 expression left. If so, it must be the base register
12958 and the constant must be zero. */
12959 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12961 INSERT_OPERAND (1, IMML
, *ip
, 0);
12965 if (my_getSmallExpression (&ep
, r
, s
) > 0
12966 || !expr_const_in_range (&ep
, 0, 16, 0))
12969 imm
= ep
.X_add_number
;
12970 INSERT_OPERAND (1, IMML
, *ip
, imm
);
12977 bfd_reloc_code_real_type r
[3];
12981 if (my_getSmallExpression (&ep
, r
, s
) > 0
12982 || !expr_const_in_range (&ep
, 1, 9, 0))
12985 imm
= ep
.X_add_number
& 7;
12986 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
12991 case 'N': /* Register list for lwm and swm. */
12993 /* A comma-separated list of registers and/or
12994 dash-separated contiguous ranges including
12995 both ra and a set of one or more registers
12996 starting at s0 up to s3 which have to be
13003 and any permutations of these. */
13004 unsigned int reglist
;
13007 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13010 if ((reglist
& 0xfff1ffff) != 0x80010000)
13013 reglist
= (reglist
>> 17) & 7;
13015 if ((reglist
& -reglist
) != reglist
)
13018 imm
= ffs (reglist
) - 1;
13019 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13023 case 'O': /* sdbbp 4-bit code. */
13025 bfd_reloc_code_real_type r
[3];
13029 if (my_getSmallExpression (&ep
, r
, s
) > 0
13030 || !expr_const_in_range (&ep
, 0, 16, 0))
13033 imm
= ep
.X_add_number
;
13034 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13041 bfd_reloc_code_real_type r
[3];
13045 if (my_getSmallExpression (&ep
, r
, s
) > 0
13046 || !expr_const_in_range (&ep
, 0, 32, 2))
13049 imm
= ep
.X_add_number
>> 2;
13050 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13057 bfd_reloc_code_real_type r
[3];
13061 if (my_getSmallExpression (&ep
, r
, s
) > 0
13062 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13065 imm
= ep
.X_add_number
>> 2;
13066 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13073 bfd_reloc_code_real_type r
[3];
13077 /* Check whether there is only a single bracketed
13078 expression left. If so, it must be the base register
13079 and the constant must be zero. */
13080 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13082 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13086 if (my_getSmallExpression (&ep
, r
, s
) > 0
13087 || !expr_const_in_range (&ep
, 0, 32, 2))
13090 imm
= ep
.X_add_number
>> 2;
13091 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13098 bfd_reloc_code_real_type r
[3];
13102 if (my_getSmallExpression (&ep
, r
, s
) > 0
13103 || !expr_const_in_range (&ep
, 0, 64, 2))
13106 imm
= ep
.X_add_number
>> 2;
13107 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13114 bfd_reloc_code_real_type r
[3];
13118 if (my_getSmallExpression (&ep
, r
, s
) > 0
13119 || !expr_const_in_range (&ep
, -8, 8, 0))
13122 imm
= ep
.X_add_number
;
13123 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13130 bfd_reloc_code_real_type r
[3];
13134 if (my_getSmallExpression (&ep
, r
, s
) > 0
13135 || expr_const_in_range (&ep
, -2, 2, 2)
13136 || !expr_const_in_range (&ep
, -258, 258, 2))
13139 imm
= ep
.X_add_number
>> 2;
13140 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13141 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13148 bfd_reloc_code_real_type r
[3];
13151 if (my_getSmallExpression (&ep
, r
, s
) > 0
13152 || !expr_const_in_range (&ep
, 0, 1, 0))
13159 as_bad (_("Internal error: bad microMIPS opcode "
13160 "(unknown extension operand type `m%c'): %s %s"),
13161 *args
, insn
->name
, insn
->args
);
13162 /* Further processing is fruitless. */
13167 case 'n': /* Register list for 32-bit lwm and swm. */
13168 gas_assert (mips_opts
.micromips
);
13170 /* A comma-separated list of registers and/or
13171 dash-separated contiguous ranges including
13172 at least one of ra and a set of one or more
13173 registers starting at s0 up to s7 and then
13174 s8 which have to be consecutive, e.g.:
13182 and any permutations of these. */
13183 unsigned int reglist
;
13187 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13190 if ((reglist
& 0x3f00ffff) != 0)
13193 ra
= (reglist
>> 27) & 0x10;
13194 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13196 if ((reglist
& -reglist
) != reglist
)
13199 imm
= (ffs (reglist
) - 1) | ra
;
13200 INSERT_OPERAND (1, RT
, *ip
, imm
);
13201 imm_expr
.X_op
= O_absent
;
13205 case '|': /* 4-bit trap code. */
13206 gas_assert (mips_opts
.micromips
);
13207 my_getExpression (&imm_expr
, s
);
13208 check_absolute_expr (ip
, &imm_expr
);
13209 if ((unsigned long) imm_expr
.X_add_number
13210 > MICROMIPSOP_MASK_TRAP
)
13211 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13212 (unsigned long) imm_expr
.X_add_number
,
13213 ip
->insn_mo
->name
);
13214 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13215 imm_expr
.X_op
= O_absent
;
13220 as_bad (_("Bad char = '%c'\n"), *args
);
13225 /* Args don't match. */
13227 insn_error
= _("Illegal operands");
13228 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13233 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13235 gas_assert (firstinsn
);
13236 need_delay_slot_ok
= FALSE
;
13245 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13247 /* This routine assembles an instruction into its binary format when
13248 assembling for the mips16. As a side effect, it sets one of the
13249 global variables imm_reloc or offset_reloc to the type of relocation
13250 to do if one of the operands is an address expression. It also sets
13251 forced_insn_length to the resulting instruction size in bytes if the
13252 user explicitly requested a small or extended instruction. */
13255 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13259 struct mips_opcode
*insn
;
13261 unsigned int regno
;
13262 unsigned int lastregno
= 0;
13268 forced_insn_length
= 0;
13270 for (s
= str
; ISLOWER (*s
); ++s
)
13282 if (s
[1] == 't' && s
[2] == ' ')
13285 forced_insn_length
= 2;
13289 else if (s
[1] == 'e' && s
[2] == ' ')
13292 forced_insn_length
= 4;
13296 /* Fall through. */
13298 insn_error
= _("unknown opcode");
13302 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13303 forced_insn_length
= 2;
13305 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13307 insn_error
= _("unrecognized opcode");
13316 gas_assert (strcmp (insn
->name
, str
) == 0);
13318 ok
= is_opcode_valid_16 (insn
);
13321 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13322 && strcmp (insn
->name
, insn
[1].name
) == 0)
13331 static char buf
[100];
13333 _("Opcode not supported on this processor: %s (%s)"),
13334 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13335 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13342 create_insn (ip
, insn
);
13343 imm_expr
.X_op
= O_absent
;
13344 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13345 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13346 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13347 imm2_expr
.X_op
= O_absent
;
13348 offset_expr
.X_op
= O_absent
;
13349 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13350 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13351 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13352 for (args
= insn
->args
; 1; ++args
)
13359 /* In this switch statement we call break if we did not find
13360 a match, continue if we did find a match, or return if we
13369 /* Stuff the immediate value in now, if we can. */
13370 if (imm_expr
.X_op
== O_constant
13371 && *imm_reloc
> BFD_RELOC_UNUSED
13372 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
13373 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
13374 && insn
->pinfo
!= INSN_MACRO
)
13378 switch (*offset_reloc
)
13380 case BFD_RELOC_MIPS16_HI16_S
:
13381 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
13384 case BFD_RELOC_MIPS16_HI16
:
13385 tmp
= imm_expr
.X_add_number
>> 16;
13388 case BFD_RELOC_MIPS16_LO16
:
13389 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
13393 case BFD_RELOC_UNUSED
:
13394 tmp
= imm_expr
.X_add_number
;
13400 *offset_reloc
= BFD_RELOC_UNUSED
;
13402 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13403 tmp
, forced_insn_length
, &ip
->insn_opcode
);
13404 imm_expr
.X_op
= O_absent
;
13405 *imm_reloc
= BFD_RELOC_UNUSED
;
13419 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13422 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13438 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13440 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13444 /* Fall through. */
13455 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13457 if (c
== 'v' || c
== 'w')
13460 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13462 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13473 if (c
== 'v' || c
== 'w')
13475 regno
= mips16_to_32_reg_map
[lastregno
];
13489 regno
= mips32_to_16_reg_map
[regno
];
13494 regno
= ILLEGAL_REG
;
13499 regno
= ILLEGAL_REG
;
13504 regno
= ILLEGAL_REG
;
13509 if (regno
== AT
&& mips_opts
.at
)
13511 if (mips_opts
.at
== ATREG
)
13512 as_warn (_("used $at without \".set noat\""));
13514 as_warn (_("used $%u with \".set at=$%u\""),
13515 regno
, mips_opts
.at
);
13523 if (regno
== ILLEGAL_REG
)
13530 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13534 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13537 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13540 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13546 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13549 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13550 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13560 if (strncmp (s
, "$pc", 3) == 0)
13577 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13580 if (imm_expr
.X_op
!= O_constant
)
13582 forced_insn_length
= 4;
13583 ip
->insn_opcode
|= MIPS16_EXTEND
;
13587 /* We need to relax this instruction. */
13588 *offset_reloc
= *imm_reloc
;
13589 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13594 *imm_reloc
= BFD_RELOC_UNUSED
;
13595 /* Fall through. */
13602 my_getExpression (&imm_expr
, s
);
13603 if (imm_expr
.X_op
== O_register
)
13605 /* What we thought was an expression turned out to
13608 if (s
[0] == '(' && args
[1] == '(')
13610 /* It looks like the expression was omitted
13611 before a register indirection, which means
13612 that the expression is implicitly zero. We
13613 still set up imm_expr, so that we handle
13614 explicit extensions correctly. */
13615 imm_expr
.X_op
= O_constant
;
13616 imm_expr
.X_add_number
= 0;
13617 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13624 /* We need to relax this instruction. */
13625 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13634 /* We use offset_reloc rather than imm_reloc for the PC
13635 relative operands. This lets macros with both
13636 immediate and address operands work correctly. */
13637 my_getExpression (&offset_expr
, s
);
13639 if (offset_expr
.X_op
== O_register
)
13642 /* We need to relax this instruction. */
13643 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13647 case '6': /* break code */
13648 my_getExpression (&imm_expr
, s
);
13649 check_absolute_expr (ip
, &imm_expr
);
13650 if ((unsigned long) imm_expr
.X_add_number
> 63)
13651 as_warn (_("Invalid value for `%s' (%lu)"),
13653 (unsigned long) imm_expr
.X_add_number
);
13654 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13655 imm_expr
.X_op
= O_absent
;
13659 case 'a': /* 26 bit address */
13660 my_getExpression (&offset_expr
, s
);
13662 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13663 ip
->insn_opcode
<<= 16;
13666 case 'l': /* register list for entry macro */
13667 case 'L': /* register list for exit macro */
13677 unsigned int freg
, reg1
, reg2
;
13679 while (*s
== ' ' || *s
== ',')
13681 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13683 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13687 as_bad (_("can't parse register list"));
13697 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13698 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13700 as_bad (_("invalid register list"));
13704 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13706 mask
&= ~ (7 << 3);
13709 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13711 mask
&= ~ (7 << 3);
13714 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13715 mask
|= (reg2
- 3) << 3;
13716 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13717 mask
|= (reg2
- 15) << 1;
13718 else if (reg1
== RA
&& reg2
== RA
)
13722 as_bad (_("invalid register list"));
13726 /* The mask is filled in in the opcode table for the
13727 benefit of the disassembler. We remove it before
13728 applying the actual mask. */
13729 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13730 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13734 case 'm': /* Register list for save insn. */
13735 case 'M': /* Register list for restore insn. */
13737 int opcode
= ip
->insn_opcode
;
13738 int framesz
= 0, seen_framesz
= 0;
13739 int nargs
= 0, statics
= 0, sregs
= 0;
13743 unsigned int reg1
, reg2
;
13745 SKIP_SPACE_TABS (s
);
13748 SKIP_SPACE_TABS (s
);
13750 my_getExpression (&imm_expr
, s
);
13751 if (imm_expr
.X_op
== O_constant
)
13753 /* Handle the frame size. */
13756 as_bad (_("more than one frame size in list"));
13760 framesz
= imm_expr
.X_add_number
;
13761 imm_expr
.X_op
= O_absent
;
13766 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13768 as_bad (_("can't parse register list"));
13780 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13783 as_bad (_("can't parse register list"));
13788 while (reg1
<= reg2
)
13790 if (reg1
>= 4 && reg1
<= 7)
13794 nargs
|= 1 << (reg1
- 4);
13796 /* statics $a0-$a3 */
13797 statics
|= 1 << (reg1
- 4);
13799 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13802 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13804 else if (reg1
== 31)
13806 /* Add $ra to insn. */
13811 as_bad (_("unexpected register in list"));
13819 /* Encode args/statics combination. */
13820 if (nargs
& statics
)
13821 as_bad (_("arg/static registers overlap"));
13822 else if (nargs
== 0xf)
13823 /* All $a0-$a3 are args. */
13824 opcode
|= MIPS16_ALL_ARGS
<< 16;
13825 else if (statics
== 0xf)
13826 /* All $a0-$a3 are statics. */
13827 opcode
|= MIPS16_ALL_STATICS
<< 16;
13830 int narg
= 0, nstat
= 0;
13832 /* Count arg registers. */
13833 while (nargs
& 0x1)
13839 as_bad (_("invalid arg register list"));
13841 /* Count static registers. */
13842 while (statics
& 0x8)
13844 statics
= (statics
<< 1) & 0xf;
13848 as_bad (_("invalid static register list"));
13850 /* Encode args/statics. */
13851 opcode
|= ((narg
<< 2) | nstat
) << 16;
13854 /* Encode $s0/$s1. */
13855 if (sregs
& (1 << 0)) /* $s0 */
13857 if (sregs
& (1 << 1)) /* $s1 */
13863 /* Count regs $s2-$s8. */
13871 as_bad (_("invalid static register list"));
13872 /* Encode $s2-$s8. */
13873 opcode
|= nsreg
<< 24;
13876 /* Encode frame size. */
13878 as_bad (_("missing frame size"));
13879 else if ((framesz
& 7) != 0 || framesz
< 0
13880 || framesz
> 0xff * 8)
13881 as_bad (_("invalid frame size"));
13882 else if (framesz
!= 128 || (opcode
>> 16) != 0)
13885 opcode
|= (((framesz
& 0xf0) << 16)
13886 | (framesz
& 0x0f));
13889 /* Finally build the instruction. */
13890 if ((opcode
>> 16) != 0 || framesz
== 0)
13891 opcode
|= MIPS16_EXTEND
;
13892 ip
->insn_opcode
= opcode
;
13896 case 'e': /* extend code */
13897 my_getExpression (&imm_expr
, s
);
13898 check_absolute_expr (ip
, &imm_expr
);
13899 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
13901 as_warn (_("Invalid value for `%s' (%lu)"),
13903 (unsigned long) imm_expr
.X_add_number
);
13904 imm_expr
.X_add_number
&= 0x7ff;
13906 ip
->insn_opcode
|= imm_expr
.X_add_number
;
13907 imm_expr
.X_op
= O_absent
;
13917 /* Args don't match. */
13918 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
13919 strcmp (insn
->name
, insn
[1].name
) == 0)
13926 insn_error
= _("illegal operands");
13932 /* This structure holds information we know about a mips16 immediate
13935 struct mips16_immed_operand
13937 /* The type code used in the argument string in the opcode table. */
13939 /* The number of bits in the short form of the opcode. */
13941 /* The number of bits in the extended form of the opcode. */
13943 /* The amount by which the short form is shifted when it is used;
13944 for example, the sw instruction has a shift count of 2. */
13946 /* The amount by which the short form is shifted when it is stored
13947 into the instruction code. */
13949 /* Non-zero if the short form is unsigned. */
13951 /* Non-zero if the extended form is unsigned. */
13953 /* Non-zero if the value is PC relative. */
13957 /* The mips16 immediate operand types. */
13959 static const struct mips16_immed_operand mips16_immed_operands
[] =
13961 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13962 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13963 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
13964 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
13965 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
13966 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13967 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13968 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13969 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
13970 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
13971 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13972 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13973 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
13974 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
13975 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13976 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
13977 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13978 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
13979 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
13980 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
13981 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
13984 #define MIPS16_NUM_IMMED \
13985 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13987 /* Install immediate value VAL into MIPS16 instruction *INSN,
13988 extending it if necessary. The instruction in *INSN may
13989 already be extended.
13991 TYPE is the type of the immediate field. USER_INSN_LENGTH is the
13992 length that the user requested, or 0 if none. */
13995 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
13996 unsigned int user_insn_length
, unsigned long *insn
)
13998 const struct mips16_immed_operand
*op
;
13999 int mintiny
, maxtiny
;
14001 op
= mips16_immed_operands
;
14002 while (op
->type
!= type
)
14005 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14010 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14013 maxtiny
= 1 << op
->nbits
;
14018 maxtiny
= (1 << op
->nbits
) - 1;
14023 mintiny
= - (1 << (op
->nbits
- 1));
14024 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14027 /* Branch offsets have an implicit 0 in the lowest bit. */
14028 if (type
== 'p' || type
== 'q')
14031 if ((val
& ((1 << op
->shift
) - 1)) != 0
14032 || val
< (mintiny
<< op
->shift
)
14033 || val
> (maxtiny
<< op
->shift
))
14035 /* We need an extended instruction. */
14036 if (user_insn_length
== 2)
14037 as_bad_where (file
, line
, _("invalid unextended operand value"));
14039 *insn
|= MIPS16_EXTEND
;
14041 else if (user_insn_length
== 4)
14043 /* The operand doesn't force an unextended instruction to be extended.
14044 Warn if the user wanted an extended instruction anyway. */
14045 *insn
|= MIPS16_EXTEND
;
14046 as_warn_where (file
, line
,
14047 _("extended operand requested but not required"));
14050 if (mips16_opcode_length (*insn
) == 2)
14054 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14055 insnval
<<= op
->op_shift
;
14060 long minext
, maxext
;
14066 maxext
= (1 << op
->extbits
) - 1;
14070 minext
= - (1 << (op
->extbits
- 1));
14071 maxext
= (1 << (op
->extbits
- 1)) - 1;
14073 if (val
< minext
|| val
> maxext
)
14074 as_bad_where (file
, line
,
14075 _("operand value out of range for instruction"));
14077 if (op
->extbits
== 16)
14079 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14082 else if (op
->extbits
== 15)
14084 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14089 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14093 *insn
|= (extval
<< 16) | val
;
14097 struct percent_op_match
14100 bfd_reloc_code_real_type reloc
;
14103 static const struct percent_op_match mips_percent_op
[] =
14105 {"%lo", BFD_RELOC_LO16
},
14107 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14108 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14109 {"%call16", BFD_RELOC_MIPS_CALL16
},
14110 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14111 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14112 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14113 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14114 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14115 {"%got", BFD_RELOC_MIPS_GOT16
},
14116 {"%gp_rel", BFD_RELOC_GPREL16
},
14117 {"%half", BFD_RELOC_16
},
14118 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14119 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14120 {"%neg", BFD_RELOC_MIPS_SUB
},
14121 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14122 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14123 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14124 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14125 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14126 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14127 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14129 {"%hi", BFD_RELOC_HI16_S
}
14132 static const struct percent_op_match mips16_percent_op
[] =
14134 {"%lo", BFD_RELOC_MIPS16_LO16
},
14135 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14136 {"%got", BFD_RELOC_MIPS16_GOT16
},
14137 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14138 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14139 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14140 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14141 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14142 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14143 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14144 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14145 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14149 /* Return true if *STR points to a relocation operator. When returning true,
14150 move *STR over the operator and store its relocation code in *RELOC.
14151 Leave both *STR and *RELOC alone when returning false. */
14154 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14156 const struct percent_op_match
*percent_op
;
14159 if (mips_opts
.mips16
)
14161 percent_op
= mips16_percent_op
;
14162 limit
= ARRAY_SIZE (mips16_percent_op
);
14166 percent_op
= mips_percent_op
;
14167 limit
= ARRAY_SIZE (mips_percent_op
);
14170 for (i
= 0; i
< limit
; i
++)
14171 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14173 int len
= strlen (percent_op
[i
].str
);
14175 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14178 *str
+= strlen (percent_op
[i
].str
);
14179 *reloc
= percent_op
[i
].reloc
;
14181 /* Check whether the output BFD supports this relocation.
14182 If not, issue an error and fall back on something safe. */
14183 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14185 as_bad (_("relocation %s isn't supported by the current ABI"),
14186 percent_op
[i
].str
);
14187 *reloc
= BFD_RELOC_UNUSED
;
14195 /* Parse string STR as a 16-bit relocatable operand. Store the
14196 expression in *EP and the relocations in the array starting
14197 at RELOC. Return the number of relocation operators used.
14199 On exit, EXPR_END points to the first character after the expression. */
14202 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14205 bfd_reloc_code_real_type reversed_reloc
[3];
14206 size_t reloc_index
, i
;
14207 int crux_depth
, str_depth
;
14210 /* Search for the start of the main expression, recoding relocations
14211 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14212 of the main expression and with CRUX_DEPTH containing the number
14213 of open brackets at that point. */
14220 crux_depth
= str_depth
;
14222 /* Skip over whitespace and brackets, keeping count of the number
14224 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14229 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14230 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14232 my_getExpression (ep
, crux
);
14235 /* Match every open bracket. */
14236 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14240 if (crux_depth
> 0)
14241 as_bad (_("unclosed '('"));
14245 if (reloc_index
!= 0)
14247 prev_reloc_op_frag
= frag_now
;
14248 for (i
= 0; i
< reloc_index
; i
++)
14249 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14252 return reloc_index
;
14256 my_getExpression (expressionS
*ep
, char *str
)
14260 save_in
= input_line_pointer
;
14261 input_line_pointer
= str
;
14263 expr_end
= input_line_pointer
;
14264 input_line_pointer
= save_in
;
14268 md_atof (int type
, char *litP
, int *sizeP
)
14270 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14274 md_number_to_chars (char *buf
, valueT val
, int n
)
14276 if (target_big_endian
)
14277 number_to_chars_bigendian (buf
, val
, n
);
14279 number_to_chars_littleendian (buf
, val
, n
);
14283 static int support_64bit_objects(void)
14285 const char **list
, **l
;
14288 list
= bfd_target_list ();
14289 for (l
= list
; *l
!= NULL
; l
++)
14290 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14291 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14293 yes
= (*l
!= NULL
);
14297 #endif /* OBJ_ELF */
14299 const char *md_shortopts
= "O::g::G:";
14303 OPTION_MARCH
= OPTION_MD_BASE
,
14325 OPTION_NO_SMARTMIPS
,
14329 OPTION_NO_MICROMIPS
,
14332 OPTION_COMPAT_ARCH_BASE
,
14341 OPTION_M7000_HILO_FIX
,
14342 OPTION_MNO_7000_HILO_FIX
,
14345 OPTION_FIX_LOONGSON2F_JUMP
,
14346 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14347 OPTION_FIX_LOONGSON2F_NOP
,
14348 OPTION_NO_FIX_LOONGSON2F_NOP
,
14350 OPTION_NO_FIX_VR4120
,
14352 OPTION_NO_FIX_VR4130
,
14353 OPTION_FIX_CN63XXP1
,
14354 OPTION_NO_FIX_CN63XXP1
,
14361 OPTION_CONSTRUCT_FLOATS
,
14362 OPTION_NO_CONSTRUCT_FLOATS
,
14365 OPTION_RELAX_BRANCH
,
14366 OPTION_NO_RELAX_BRANCH
,
14373 OPTION_SINGLE_FLOAT
,
14374 OPTION_DOUBLE_FLOAT
,
14377 OPTION_CALL_SHARED
,
14378 OPTION_CALL_NONPIC
,
14388 OPTION_MVXWORKS_PIC
,
14389 #endif /* OBJ_ELF */
14393 struct option md_longopts
[] =
14395 /* Options which specify architecture. */
14396 {"march", required_argument
, NULL
, OPTION_MARCH
},
14397 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14398 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14399 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14400 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14401 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14402 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14403 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14404 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14405 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14406 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14407 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14409 /* Options which specify Application Specific Extensions (ASEs). */
14410 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14411 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14412 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14413 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14414 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14415 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14416 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14417 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14418 {"mmt", no_argument
, NULL
, OPTION_MT
},
14419 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14420 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14421 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14422 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14423 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14424 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14425 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14426 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14427 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14429 /* Old-style architecture options. Don't add more of these. */
14430 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14431 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14432 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14433 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14434 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14435 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14436 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14437 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14439 /* Options which enable bug fixes. */
14440 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14441 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14442 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14443 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14444 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14445 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14446 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14447 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14448 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14449 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14450 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14451 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14452 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14453 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14454 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14456 /* Miscellaneous options. */
14457 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14458 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14459 {"break", no_argument
, NULL
, OPTION_BREAK
},
14460 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14461 {"EB", no_argument
, NULL
, OPTION_EB
},
14462 {"EL", no_argument
, NULL
, OPTION_EL
},
14463 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14464 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14465 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14466 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14467 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14468 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14469 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14470 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14471 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14472 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14473 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14474 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14475 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14476 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14477 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14478 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14480 /* Strictly speaking this next option is ELF specific,
14481 but we allow it for other ports as well in order to
14482 make testing easier. */
14483 {"32", no_argument
, NULL
, OPTION_32
},
14485 /* ELF-specific options. */
14487 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14488 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14489 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14490 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14491 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14492 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14493 {"n32", no_argument
, NULL
, OPTION_N32
},
14494 {"64", no_argument
, NULL
, OPTION_64
},
14495 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14496 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14497 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14498 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14499 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14500 #endif /* OBJ_ELF */
14502 {NULL
, no_argument
, NULL
, 0}
14504 size_t md_longopts_size
= sizeof (md_longopts
);
14506 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14507 NEW_VALUE. Warn if another value was already specified. Note:
14508 we have to defer parsing the -march and -mtune arguments in order
14509 to handle 'from-abi' correctly, since the ABI might be specified
14510 in a later argument. */
14513 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14515 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14516 as_warn (_("A different %s was already specified, is now %s"),
14517 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14520 *string_ptr
= new_value
;
14524 md_parse_option (int c
, char *arg
)
14528 case OPTION_CONSTRUCT_FLOATS
:
14529 mips_disable_float_construction
= 0;
14532 case OPTION_NO_CONSTRUCT_FLOATS
:
14533 mips_disable_float_construction
= 1;
14545 target_big_endian
= 1;
14549 target_big_endian
= 0;
14555 else if (arg
[0] == '0')
14557 else if (arg
[0] == '1')
14567 mips_debug
= atoi (arg
);
14571 file_mips_isa
= ISA_MIPS1
;
14575 file_mips_isa
= ISA_MIPS2
;
14579 file_mips_isa
= ISA_MIPS3
;
14583 file_mips_isa
= ISA_MIPS4
;
14587 file_mips_isa
= ISA_MIPS5
;
14590 case OPTION_MIPS32
:
14591 file_mips_isa
= ISA_MIPS32
;
14594 case OPTION_MIPS32R2
:
14595 file_mips_isa
= ISA_MIPS32R2
;
14598 case OPTION_MIPS64R2
:
14599 file_mips_isa
= ISA_MIPS64R2
;
14602 case OPTION_MIPS64
:
14603 file_mips_isa
= ISA_MIPS64
;
14607 mips_set_option_string (&mips_tune_string
, arg
);
14611 mips_set_option_string (&mips_arch_string
, arg
);
14615 mips_set_option_string (&mips_arch_string
, "4650");
14616 mips_set_option_string (&mips_tune_string
, "4650");
14619 case OPTION_NO_M4650
:
14623 mips_set_option_string (&mips_arch_string
, "4010");
14624 mips_set_option_string (&mips_tune_string
, "4010");
14627 case OPTION_NO_M4010
:
14631 mips_set_option_string (&mips_arch_string
, "4100");
14632 mips_set_option_string (&mips_tune_string
, "4100");
14635 case OPTION_NO_M4100
:
14639 mips_set_option_string (&mips_arch_string
, "3900");
14640 mips_set_option_string (&mips_tune_string
, "3900");
14643 case OPTION_NO_M3900
:
14647 mips_opts
.ase_mdmx
= 1;
14650 case OPTION_NO_MDMX
:
14651 mips_opts
.ase_mdmx
= 0;
14655 mips_opts
.ase_dsp
= 1;
14656 mips_opts
.ase_dspr2
= 0;
14659 case OPTION_NO_DSP
:
14660 mips_opts
.ase_dsp
= 0;
14661 mips_opts
.ase_dspr2
= 0;
14665 mips_opts
.ase_dspr2
= 1;
14666 mips_opts
.ase_dsp
= 1;
14669 case OPTION_NO_DSPR2
:
14670 mips_opts
.ase_dspr2
= 0;
14671 mips_opts
.ase_dsp
= 0;
14675 mips_opts
.ase_mt
= 1;
14679 mips_opts
.ase_mt
= 0;
14683 mips_opts
.ase_mcu
= 1;
14686 case OPTION_NO_MCU
:
14687 mips_opts
.ase_mcu
= 0;
14690 case OPTION_MICROMIPS
:
14691 if (mips_opts
.mips16
== 1)
14693 as_bad (_("-mmicromips cannot be used with -mips16"));
14696 mips_opts
.micromips
= 1;
14697 mips_no_prev_insn ();
14700 case OPTION_NO_MICROMIPS
:
14701 mips_opts
.micromips
= 0;
14702 mips_no_prev_insn ();
14705 case OPTION_MIPS16
:
14706 if (mips_opts
.micromips
== 1)
14708 as_bad (_("-mips16 cannot be used with -micromips"));
14711 mips_opts
.mips16
= 1;
14712 mips_no_prev_insn ();
14715 case OPTION_NO_MIPS16
:
14716 mips_opts
.mips16
= 0;
14717 mips_no_prev_insn ();
14720 case OPTION_MIPS3D
:
14721 mips_opts
.ase_mips3d
= 1;
14724 case OPTION_NO_MIPS3D
:
14725 mips_opts
.ase_mips3d
= 0;
14728 case OPTION_SMARTMIPS
:
14729 mips_opts
.ase_smartmips
= 1;
14732 case OPTION_NO_SMARTMIPS
:
14733 mips_opts
.ase_smartmips
= 0;
14736 case OPTION_FIX_24K
:
14740 case OPTION_NO_FIX_24K
:
14744 case OPTION_FIX_LOONGSON2F_JUMP
:
14745 mips_fix_loongson2f_jump
= TRUE
;
14748 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14749 mips_fix_loongson2f_jump
= FALSE
;
14752 case OPTION_FIX_LOONGSON2F_NOP
:
14753 mips_fix_loongson2f_nop
= TRUE
;
14756 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14757 mips_fix_loongson2f_nop
= FALSE
;
14760 case OPTION_FIX_VR4120
:
14761 mips_fix_vr4120
= 1;
14764 case OPTION_NO_FIX_VR4120
:
14765 mips_fix_vr4120
= 0;
14768 case OPTION_FIX_VR4130
:
14769 mips_fix_vr4130
= 1;
14772 case OPTION_NO_FIX_VR4130
:
14773 mips_fix_vr4130
= 0;
14776 case OPTION_FIX_CN63XXP1
:
14777 mips_fix_cn63xxp1
= TRUE
;
14780 case OPTION_NO_FIX_CN63XXP1
:
14781 mips_fix_cn63xxp1
= FALSE
;
14784 case OPTION_RELAX_BRANCH
:
14785 mips_relax_branch
= 1;
14788 case OPTION_NO_RELAX_BRANCH
:
14789 mips_relax_branch
= 0;
14792 case OPTION_MSHARED
:
14793 mips_in_shared
= TRUE
;
14796 case OPTION_MNO_SHARED
:
14797 mips_in_shared
= FALSE
;
14800 case OPTION_MSYM32
:
14801 mips_opts
.sym32
= TRUE
;
14804 case OPTION_MNO_SYM32
:
14805 mips_opts
.sym32
= FALSE
;
14809 /* When generating ELF code, we permit -KPIC and -call_shared to
14810 select SVR4_PIC, and -non_shared to select no PIC. This is
14811 intended to be compatible with Irix 5. */
14812 case OPTION_CALL_SHARED
:
14815 as_bad (_("-call_shared is supported only for ELF format"));
14818 mips_pic
= SVR4_PIC
;
14819 mips_abicalls
= TRUE
;
14822 case OPTION_CALL_NONPIC
:
14825 as_bad (_("-call_nonpic is supported only for ELF format"));
14829 mips_abicalls
= TRUE
;
14832 case OPTION_NON_SHARED
:
14835 as_bad (_("-non_shared is supported only for ELF format"));
14839 mips_abicalls
= FALSE
;
14842 /* The -xgot option tells the assembler to use 32 bit offsets
14843 when accessing the got in SVR4_PIC mode. It is for Irix
14848 #endif /* OBJ_ELF */
14851 g_switch_value
= atoi (arg
);
14855 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14859 mips_abi
= O32_ABI
;
14860 /* We silently ignore -32 for non-ELF targets. This greatly
14861 simplifies the construction of the MIPS GAS test cases. */
14868 as_bad (_("-n32 is supported for ELF format only"));
14871 mips_abi
= N32_ABI
;
14877 as_bad (_("-64 is supported for ELF format only"));
14880 mips_abi
= N64_ABI
;
14881 if (!support_64bit_objects())
14882 as_fatal (_("No compiled in support for 64 bit object file format"));
14884 #endif /* OBJ_ELF */
14887 file_mips_gp32
= 1;
14891 file_mips_gp32
= 0;
14895 file_mips_fp32
= 1;
14899 file_mips_fp32
= 0;
14902 case OPTION_SINGLE_FLOAT
:
14903 file_mips_single_float
= 1;
14906 case OPTION_DOUBLE_FLOAT
:
14907 file_mips_single_float
= 0;
14910 case OPTION_SOFT_FLOAT
:
14911 file_mips_soft_float
= 1;
14914 case OPTION_HARD_FLOAT
:
14915 file_mips_soft_float
= 0;
14922 as_bad (_("-mabi is supported for ELF format only"));
14925 if (strcmp (arg
, "32") == 0)
14926 mips_abi
= O32_ABI
;
14927 else if (strcmp (arg
, "o64") == 0)
14928 mips_abi
= O64_ABI
;
14929 else if (strcmp (arg
, "n32") == 0)
14930 mips_abi
= N32_ABI
;
14931 else if (strcmp (arg
, "64") == 0)
14933 mips_abi
= N64_ABI
;
14934 if (! support_64bit_objects())
14935 as_fatal (_("No compiled in support for 64 bit object file "
14938 else if (strcmp (arg
, "eabi") == 0)
14939 mips_abi
= EABI_ABI
;
14942 as_fatal (_("invalid abi -mabi=%s"), arg
);
14946 #endif /* OBJ_ELF */
14948 case OPTION_M7000_HILO_FIX
:
14949 mips_7000_hilo_fix
= TRUE
;
14952 case OPTION_MNO_7000_HILO_FIX
:
14953 mips_7000_hilo_fix
= FALSE
;
14957 case OPTION_MDEBUG
:
14958 mips_flag_mdebug
= TRUE
;
14961 case OPTION_NO_MDEBUG
:
14962 mips_flag_mdebug
= FALSE
;
14966 mips_flag_pdr
= TRUE
;
14969 case OPTION_NO_PDR
:
14970 mips_flag_pdr
= FALSE
;
14973 case OPTION_MVXWORKS_PIC
:
14974 mips_pic
= VXWORKS_PIC
;
14976 #endif /* OBJ_ELF */
14982 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14987 /* Set up globals to generate code for the ISA or processor
14988 described by INFO. */
14991 mips_set_architecture (const struct mips_cpu_info
*info
)
14995 file_mips_arch
= info
->cpu
;
14996 mips_opts
.arch
= info
->cpu
;
14997 mips_opts
.isa
= info
->isa
;
15002 /* Likewise for tuning. */
15005 mips_set_tune (const struct mips_cpu_info
*info
)
15008 mips_tune
= info
->cpu
;
15013 mips_after_parse_args (void)
15015 const struct mips_cpu_info
*arch_info
= 0;
15016 const struct mips_cpu_info
*tune_info
= 0;
15018 /* GP relative stuff not working for PE */
15019 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15021 if (g_switch_seen
&& g_switch_value
!= 0)
15022 as_bad (_("-G not supported in this configuration."));
15023 g_switch_value
= 0;
15026 if (mips_abi
== NO_ABI
)
15027 mips_abi
= MIPS_DEFAULT_ABI
;
15029 /* The following code determines the architecture and register size.
15030 Similar code was added to GCC 3.3 (see override_options() in
15031 config/mips/mips.c). The GAS and GCC code should be kept in sync
15032 as much as possible. */
15034 if (mips_arch_string
!= 0)
15035 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15037 if (file_mips_isa
!= ISA_UNKNOWN
)
15039 /* Handle -mipsN. At this point, file_mips_isa contains the
15040 ISA level specified by -mipsN, while arch_info->isa contains
15041 the -march selection (if any). */
15042 if (arch_info
!= 0)
15044 /* -march takes precedence over -mipsN, since it is more descriptive.
15045 There's no harm in specifying both as long as the ISA levels
15047 if (file_mips_isa
!= arch_info
->isa
)
15048 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15049 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15050 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15053 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15056 if (arch_info
== 0)
15058 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15059 gas_assert (arch_info
);
15062 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15063 as_bad (_("-march=%s is not compatible with the selected ABI"),
15066 mips_set_architecture (arch_info
);
15068 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15069 if (mips_tune_string
!= 0)
15070 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15072 if (tune_info
== 0)
15073 mips_set_tune (arch_info
);
15075 mips_set_tune (tune_info
);
15077 if (file_mips_gp32
>= 0)
15079 /* The user specified the size of the integer registers. Make sure
15080 it agrees with the ABI and ISA. */
15081 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15082 as_bad (_("-mgp64 used with a 32-bit processor"));
15083 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15084 as_bad (_("-mgp32 used with a 64-bit ABI"));
15085 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15086 as_bad (_("-mgp64 used with a 32-bit ABI"));
15090 /* Infer the integer register size from the ABI and processor.
15091 Restrict ourselves to 32-bit registers if that's all the
15092 processor has, or if the ABI cannot handle 64-bit registers. */
15093 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15094 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15097 switch (file_mips_fp32
)
15101 /* No user specified float register size.
15102 ??? GAS treats single-float processors as though they had 64-bit
15103 float registers (although it complains when double-precision
15104 instructions are used). As things stand, saying they have 32-bit
15105 registers would lead to spurious "register must be even" messages.
15106 So here we assume float registers are never smaller than the
15108 if (file_mips_gp32
== 0)
15109 /* 64-bit integer registers implies 64-bit float registers. */
15110 file_mips_fp32
= 0;
15111 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15112 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15113 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15114 file_mips_fp32
= 0;
15116 /* 32-bit float registers. */
15117 file_mips_fp32
= 1;
15120 /* The user specified the size of the float registers. Check if it
15121 agrees with the ABI and ISA. */
15123 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15124 as_bad (_("-mfp64 used with a 32-bit fpu"));
15125 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15126 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15127 as_warn (_("-mfp64 used with a 32-bit ABI"));
15130 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15131 as_warn (_("-mfp32 used with a 64-bit ABI"));
15135 /* End of GCC-shared inference code. */
15137 /* This flag is set when we have a 64-bit capable CPU but use only
15138 32-bit wide registers. Note that EABI does not use it. */
15139 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15140 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15141 || mips_abi
== O32_ABI
))
15142 mips_32bitmode
= 1;
15144 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15145 as_bad (_("trap exception not supported at ISA 1"));
15147 /* If the selected architecture includes support for ASEs, enable
15148 generation of code for them. */
15149 if (mips_opts
.mips16
== -1)
15150 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15151 if (mips_opts
.micromips
== -1)
15152 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15153 if (mips_opts
.ase_mips3d
== -1)
15154 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15155 && file_mips_fp32
== 0) ? 1 : 0;
15156 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15157 as_bad (_("-mfp32 used with -mips3d"));
15159 if (mips_opts
.ase_mdmx
== -1)
15160 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15161 && file_mips_fp32
== 0) ? 1 : 0;
15162 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15163 as_bad (_("-mfp32 used with -mdmx"));
15165 if (mips_opts
.ase_smartmips
== -1)
15166 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15167 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15168 as_warn (_("%s ISA does not support SmartMIPS"),
15169 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15171 if (mips_opts
.ase_dsp
== -1)
15172 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15173 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15174 as_warn (_("%s ISA does not support DSP ASE"),
15175 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15177 if (mips_opts
.ase_dspr2
== -1)
15179 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15180 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15182 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15183 as_warn (_("%s ISA does not support DSP R2 ASE"),
15184 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15186 if (mips_opts
.ase_mt
== -1)
15187 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15188 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15189 as_warn (_("%s ISA does not support MT ASE"),
15190 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15192 if (mips_opts
.ase_mcu
== -1)
15193 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15194 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15195 as_warn (_("%s ISA does not support MCU ASE"),
15196 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15198 file_mips_isa
= mips_opts
.isa
;
15199 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15200 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15201 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15202 file_ase_dsp
= mips_opts
.ase_dsp
;
15203 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15204 file_ase_mt
= mips_opts
.ase_mt
;
15205 mips_opts
.gp32
= file_mips_gp32
;
15206 mips_opts
.fp32
= file_mips_fp32
;
15207 mips_opts
.soft_float
= file_mips_soft_float
;
15208 mips_opts
.single_float
= file_mips_single_float
;
15210 if (mips_flag_mdebug
< 0)
15212 #ifdef OBJ_MAYBE_ECOFF
15213 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15214 mips_flag_mdebug
= 1;
15216 #endif /* OBJ_MAYBE_ECOFF */
15217 mips_flag_mdebug
= 0;
15222 mips_init_after_args (void)
15224 /* initialize opcodes */
15225 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15226 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15230 md_pcrel_from (fixS
*fixP
)
15232 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15233 switch (fixP
->fx_r_type
)
15235 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15236 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15237 /* Return the address of the delay slot. */
15240 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15241 case BFD_RELOC_MICROMIPS_JMP
:
15242 case BFD_RELOC_16_PCREL_S2
:
15243 case BFD_RELOC_MIPS_JMP
:
15244 /* Return the address of the delay slot. */
15248 /* We have no relocation type for PC relative MIPS16 instructions. */
15249 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15251 _("PC relative MIPS16 instruction references a different section"));
15256 /* This is called before the symbol table is processed. In order to
15257 work with gcc when using mips-tfile, we must keep all local labels.
15258 However, in other cases, we want to discard them. If we were
15259 called with -g, but we didn't see any debugging information, it may
15260 mean that gcc is smuggling debugging information through to
15261 mips-tfile, in which case we must generate all local labels. */
15264 mips_frob_file_before_adjust (void)
15266 #ifndef NO_ECOFF_DEBUGGING
15267 if (ECOFF_DEBUGGING
15269 && ! ecoff_debugging_seen
)
15270 flag_keep_locals
= 1;
15274 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15275 the corresponding LO16 reloc. This is called before md_apply_fix and
15276 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15277 relocation operators.
15279 For our purposes, a %lo() expression matches a %got() or %hi()
15282 (a) it refers to the same symbol; and
15283 (b) the offset applied in the %lo() expression is no lower than
15284 the offset applied in the %got() or %hi().
15286 (b) allows us to cope with code like:
15289 lh $4,%lo(foo+2)($4)
15291 ...which is legal on RELA targets, and has a well-defined behaviour
15292 if the user knows that adding 2 to "foo" will not induce a carry to
15295 When several %lo()s match a particular %got() or %hi(), we use the
15296 following rules to distinguish them:
15298 (1) %lo()s with smaller offsets are a better match than %lo()s with
15301 (2) %lo()s with no matching %got() or %hi() are better than those
15302 that already have a matching %got() or %hi().
15304 (3) later %lo()s are better than earlier %lo()s.
15306 These rules are applied in order.
15308 (1) means, among other things, that %lo()s with identical offsets are
15309 chosen if they exist.
15311 (2) means that we won't associate several high-part relocations with
15312 the same low-part relocation unless there's no alternative. Having
15313 several high parts for the same low part is a GNU extension; this rule
15314 allows careful users to avoid it.
15316 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15317 with the last high-part relocation being at the front of the list.
15318 It therefore makes sense to choose the last matching low-part
15319 relocation, all other things being equal. It's also easier
15320 to code that way. */
15323 mips_frob_file (void)
15325 struct mips_hi_fixup
*l
;
15326 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15328 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15330 segment_info_type
*seginfo
;
15331 bfd_boolean matched_lo_p
;
15332 fixS
**hi_pos
, **lo_pos
, **pos
;
15334 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15336 /* If a GOT16 relocation turns out to be against a global symbol,
15337 there isn't supposed to be a matching LO. */
15338 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15339 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
15342 /* Check quickly whether the next fixup happens to be a matching %lo. */
15343 if (fixup_has_matching_lo_p (l
->fixp
))
15346 seginfo
= seg_info (l
->seg
);
15348 /* Set HI_POS to the position of this relocation in the chain.
15349 Set LO_POS to the position of the chosen low-part relocation.
15350 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15351 relocation that matches an immediately-preceding high-part
15355 matched_lo_p
= FALSE
;
15356 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15358 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15360 if (*pos
== l
->fixp
)
15363 if ((*pos
)->fx_r_type
== looking_for_rtype
15364 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15365 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15367 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15369 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15372 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15373 && fixup_has_matching_lo_p (*pos
));
15376 /* If we found a match, remove the high-part relocation from its
15377 current position and insert it before the low-part relocation.
15378 Make the offsets match so that fixup_has_matching_lo_p()
15381 We don't warn about unmatched high-part relocations since some
15382 versions of gcc have been known to emit dead "lui ...%hi(...)"
15384 if (lo_pos
!= NULL
)
15386 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15387 if (l
->fixp
->fx_next
!= *lo_pos
)
15389 *hi_pos
= l
->fixp
->fx_next
;
15390 l
->fixp
->fx_next
= *lo_pos
;
15397 /* We may have combined relocations without symbols in the N32/N64 ABI.
15398 We have to prevent gas from dropping them. */
15401 mips_force_relocation (fixS
*fixp
)
15403 if (generic_force_reloc (fixp
))
15406 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15407 so that the linker relaxation can update targets. */
15408 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15409 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15410 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15414 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
15415 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
15416 || hi16_reloc_p (fixp
->fx_r_type
)
15417 || lo16_reloc_p (fixp
->fx_r_type
)))
15423 /* Apply a fixup to the object file. */
15426 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15430 reloc_howto_type
*howto
;
15432 /* We ignore generic BFD relocations we don't know about. */
15433 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15437 gas_assert (fixP
->fx_size
== 2
15438 || fixP
->fx_size
== 4
15439 || fixP
->fx_r_type
== BFD_RELOC_16
15440 || fixP
->fx_r_type
== BFD_RELOC_64
15441 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15442 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15443 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15444 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15445 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15446 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15448 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15450 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15451 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15452 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15453 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15455 /* Don't treat parts of a composite relocation as done. There are two
15458 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15459 should nevertheless be emitted if the first part is.
15461 (2) In normal usage, composite relocations are never assembly-time
15462 constants. The easiest way of dealing with the pathological
15463 exceptions is to generate a relocation against STN_UNDEF and
15464 leave everything up to the linker. */
15465 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15468 switch (fixP
->fx_r_type
)
15470 case BFD_RELOC_MIPS_TLS_GD
:
15471 case BFD_RELOC_MIPS_TLS_LDM
:
15472 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15473 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15474 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15475 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15476 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15477 case BFD_RELOC_MIPS_TLS_TPREL32
:
15478 case BFD_RELOC_MIPS_TLS_TPREL64
:
15479 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15480 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15481 case BFD_RELOC_MICROMIPS_TLS_GD
:
15482 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15483 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15484 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15485 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15486 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15487 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15488 case BFD_RELOC_MIPS16_TLS_GD
:
15489 case BFD_RELOC_MIPS16_TLS_LDM
:
15490 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15491 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15492 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15493 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15494 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15495 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15498 case BFD_RELOC_MIPS_JMP
:
15499 case BFD_RELOC_MIPS_SHIFT5
:
15500 case BFD_RELOC_MIPS_SHIFT6
:
15501 case BFD_RELOC_MIPS_GOT_DISP
:
15502 case BFD_RELOC_MIPS_GOT_PAGE
:
15503 case BFD_RELOC_MIPS_GOT_OFST
:
15504 case BFD_RELOC_MIPS_SUB
:
15505 case BFD_RELOC_MIPS_INSERT_A
:
15506 case BFD_RELOC_MIPS_INSERT_B
:
15507 case BFD_RELOC_MIPS_DELETE
:
15508 case BFD_RELOC_MIPS_HIGHEST
:
15509 case BFD_RELOC_MIPS_HIGHER
:
15510 case BFD_RELOC_MIPS_SCN_DISP
:
15511 case BFD_RELOC_MIPS_REL16
:
15512 case BFD_RELOC_MIPS_RELGOT
:
15513 case BFD_RELOC_MIPS_JALR
:
15514 case BFD_RELOC_HI16
:
15515 case BFD_RELOC_HI16_S
:
15516 case BFD_RELOC_GPREL16
:
15517 case BFD_RELOC_MIPS_LITERAL
:
15518 case BFD_RELOC_MIPS_CALL16
:
15519 case BFD_RELOC_MIPS_GOT16
:
15520 case BFD_RELOC_GPREL32
:
15521 case BFD_RELOC_MIPS_GOT_HI16
:
15522 case BFD_RELOC_MIPS_GOT_LO16
:
15523 case BFD_RELOC_MIPS_CALL_HI16
:
15524 case BFD_RELOC_MIPS_CALL_LO16
:
15525 case BFD_RELOC_MIPS16_GPREL
:
15526 case BFD_RELOC_MIPS16_GOT16
:
15527 case BFD_RELOC_MIPS16_CALL16
:
15528 case BFD_RELOC_MIPS16_HI16
:
15529 case BFD_RELOC_MIPS16_HI16_S
:
15530 case BFD_RELOC_MIPS16_JMP
:
15531 case BFD_RELOC_MICROMIPS_JMP
:
15532 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15533 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15534 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15535 case BFD_RELOC_MICROMIPS_SUB
:
15536 case BFD_RELOC_MICROMIPS_HIGHEST
:
15537 case BFD_RELOC_MICROMIPS_HIGHER
:
15538 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15539 case BFD_RELOC_MICROMIPS_JALR
:
15540 case BFD_RELOC_MICROMIPS_HI16
:
15541 case BFD_RELOC_MICROMIPS_HI16_S
:
15542 case BFD_RELOC_MICROMIPS_GPREL16
:
15543 case BFD_RELOC_MICROMIPS_LITERAL
:
15544 case BFD_RELOC_MICROMIPS_CALL16
:
15545 case BFD_RELOC_MICROMIPS_GOT16
:
15546 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15547 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15548 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15549 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15550 /* Nothing needed to do. The value comes from the reloc entry. */
15554 /* This is handled like BFD_RELOC_32, but we output a sign
15555 extended value if we are only 32 bits. */
15558 if (8 <= sizeof (valueT
))
15559 md_number_to_chars (buf
, *valP
, 8);
15564 if ((*valP
& 0x80000000) != 0)
15568 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15569 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15574 case BFD_RELOC_RVA
:
15577 /* If we are deleting this reloc entry, we must fill in the
15578 value now. This can happen if we have a .word which is not
15579 resolved when it appears but is later defined. */
15581 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15584 case BFD_RELOC_LO16
:
15585 case BFD_RELOC_MIPS16_LO16
:
15586 case BFD_RELOC_MICROMIPS_LO16
:
15587 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15588 may be safe to remove, but if so it's not obvious. */
15589 /* When handling an embedded PIC switch statement, we can wind
15590 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15593 if (*valP
+ 0x8000 > 0xffff)
15594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15595 _("relocation overflow"));
15596 /* 32-bit microMIPS instructions are divided into two halfwords.
15597 Relocations always refer to the second halfword, regardless
15599 if (target_big_endian
|| fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_LO16
)
15601 md_number_to_chars (buf
, *valP
, 2);
15605 case BFD_RELOC_16_PCREL_S2
:
15606 if ((*valP
& 0x3) != 0)
15607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15608 _("Branch to misaligned address (%lx)"), (long) *valP
);
15610 /* We need to save the bits in the instruction since fixup_segment()
15611 might be deleting the relocation entry (i.e., a branch within
15612 the current segment). */
15613 if (! fixP
->fx_done
)
15616 /* Update old instruction data. */
15617 insn
= read_insn (buf
);
15619 if (*valP
+ 0x20000 <= 0x3ffff)
15621 insn
|= (*valP
>> 2) & 0xffff;
15622 write_insn (buf
, insn
);
15624 else if (mips_pic
== NO_PIC
15626 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15627 && (fixP
->fx_frag
->fr_address
15628 < text_section
->vma
+ bfd_get_section_size (text_section
))
15629 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15630 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15631 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15633 /* The branch offset is too large. If this is an
15634 unconditional branch, and we are not generating PIC code,
15635 we can convert it to an absolute jump instruction. */
15636 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15637 insn
= 0x0c000000; /* jal */
15639 insn
= 0x08000000; /* j */
15640 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15642 fixP
->fx_addsy
= section_symbol (text_section
);
15643 *valP
+= md_pcrel_from (fixP
);
15644 write_insn (buf
, insn
);
15648 /* If we got here, we have branch-relaxation disabled,
15649 and there's nothing we can do to fix this instruction
15650 without turning it into a longer sequence. */
15651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15652 _("Branch out of range"));
15656 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15657 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15658 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15659 /* We adjust the offset back to even. */
15660 if ((*valP
& 0x1) != 0)
15663 if (! fixP
->fx_done
)
15666 /* Should never visit here, because we keep the relocation. */
15670 case BFD_RELOC_VTABLE_INHERIT
:
15673 && !S_IS_DEFINED (fixP
->fx_addsy
)
15674 && !S_IS_WEAK (fixP
->fx_addsy
))
15675 S_SET_WEAK (fixP
->fx_addsy
);
15678 case BFD_RELOC_VTABLE_ENTRY
:
15686 /* Remember value for tc_gen_reloc. */
15687 fixP
->fx_addnumber
= *valP
;
15697 name
= input_line_pointer
;
15698 c
= get_symbol_end ();
15699 p
= (symbolS
*) symbol_find_or_make (name
);
15700 *input_line_pointer
= c
;
15704 /* Align the current frag to a given power of two. If a particular
15705 fill byte should be used, FILL points to an integer that contains
15706 that byte, otherwise FILL is null.
15708 This function used to have the comment:
15710 The MIPS assembler also automatically adjusts any preceding label.
15712 The implementation therefore applied the adjustment to a maximum of
15713 one label. However, other label adjustments are applied to batches
15714 of labels, and adjusting just one caused problems when new labels
15715 were added for the sake of debugging or unwind information.
15716 We therefore adjust all preceding labels (given as LABELS) instead. */
15719 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15721 mips_emit_delays ();
15722 mips_record_compressed_mode ();
15723 if (fill
== NULL
&& subseg_text_p (now_seg
))
15724 frag_align_code (to
, 0);
15726 frag_align (to
, fill
? *fill
: 0, 0);
15727 record_alignment (now_seg
, to
);
15728 mips_move_labels (labels
, FALSE
);
15731 /* Align to a given power of two. .align 0 turns off the automatic
15732 alignment used by the data creating pseudo-ops. */
15735 s_align (int x ATTRIBUTE_UNUSED
)
15737 int temp
, fill_value
, *fill_ptr
;
15738 long max_alignment
= 28;
15740 /* o Note that the assembler pulls down any immediately preceding label
15741 to the aligned address.
15742 o It's not documented but auto alignment is reinstated by
15743 a .align pseudo instruction.
15744 o Note also that after auto alignment is turned off the mips assembler
15745 issues an error on attempt to assemble an improperly aligned data item.
15748 temp
= get_absolute_expression ();
15749 if (temp
> max_alignment
)
15750 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15753 as_warn (_("Alignment negative: 0 assumed."));
15756 if (*input_line_pointer
== ',')
15758 ++input_line_pointer
;
15759 fill_value
= get_absolute_expression ();
15760 fill_ptr
= &fill_value
;
15766 segment_info_type
*si
= seg_info (now_seg
);
15767 struct insn_label_list
*l
= si
->label_list
;
15768 /* Auto alignment should be switched on by next section change. */
15770 mips_align (temp
, fill_ptr
, l
);
15777 demand_empty_rest_of_line ();
15781 s_change_sec (int sec
)
15786 /* The ELF backend needs to know that we are changing sections, so
15787 that .previous works correctly. We could do something like check
15788 for an obj_section_change_hook macro, but that might be confusing
15789 as it would not be appropriate to use it in the section changing
15790 functions in read.c, since obj-elf.c intercepts those. FIXME:
15791 This should be cleaner, somehow. */
15793 obj_elf_section_change_hook ();
15796 mips_emit_delays ();
15807 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15808 demand_empty_rest_of_line ();
15812 seg
= subseg_new (RDATA_SECTION_NAME
,
15813 (subsegT
) get_absolute_expression ());
15816 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15817 | SEC_READONLY
| SEC_RELOC
15819 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15820 record_alignment (seg
, 4);
15822 demand_empty_rest_of_line ();
15826 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15829 bfd_set_section_flags (stdoutput
, seg
,
15830 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15831 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15832 record_alignment (seg
, 4);
15834 demand_empty_rest_of_line ();
15838 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15841 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15842 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15843 record_alignment (seg
, 4);
15845 demand_empty_rest_of_line ();
15853 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15856 char *section_name
;
15861 int section_entry_size
;
15862 int section_alignment
;
15867 section_name
= input_line_pointer
;
15868 c
= get_symbol_end ();
15870 next_c
= *(input_line_pointer
+ 1);
15872 /* Do we have .section Name<,"flags">? */
15873 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15875 /* just after name is now '\0'. */
15876 *input_line_pointer
= c
;
15877 input_line_pointer
= section_name
;
15878 obj_elf_section (ignore
);
15881 input_line_pointer
++;
15883 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15885 section_type
= get_absolute_expression ();
15888 if (*input_line_pointer
++ == ',')
15889 section_flag
= get_absolute_expression ();
15892 if (*input_line_pointer
++ == ',')
15893 section_entry_size
= get_absolute_expression ();
15895 section_entry_size
= 0;
15896 if (*input_line_pointer
++ == ',')
15897 section_alignment
= get_absolute_expression ();
15899 section_alignment
= 0;
15900 /* FIXME: really ignore? */
15901 (void) section_alignment
;
15903 section_name
= xstrdup (section_name
);
15905 /* When using the generic form of .section (as implemented by obj-elf.c),
15906 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15907 traditionally had to fall back on the more common @progbits instead.
15909 There's nothing really harmful in this, since bfd will correct
15910 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15911 means that, for backwards compatibility, the special_section entries
15912 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15914 Even so, we shouldn't force users of the MIPS .section syntax to
15915 incorrectly label the sections as SHT_PROGBITS. The best compromise
15916 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15917 generic type-checking code. */
15918 if (section_type
== SHT_MIPS_DWARF
)
15919 section_type
= SHT_PROGBITS
;
15921 obj_elf_change_section (section_name
, section_type
, section_flag
,
15922 section_entry_size
, 0, 0, 0);
15924 if (now_seg
->name
!= section_name
)
15925 free (section_name
);
15926 #endif /* OBJ_ELF */
15930 mips_enable_auto_align (void)
15936 s_cons (int log_size
)
15938 segment_info_type
*si
= seg_info (now_seg
);
15939 struct insn_label_list
*l
= si
->label_list
;
15941 mips_emit_delays ();
15942 if (log_size
> 0 && auto_align
)
15943 mips_align (log_size
, 0, l
);
15944 cons (1 << log_size
);
15945 mips_clear_insn_labels ();
15949 s_float_cons (int type
)
15951 segment_info_type
*si
= seg_info (now_seg
);
15952 struct insn_label_list
*l
= si
->label_list
;
15954 mips_emit_delays ();
15959 mips_align (3, 0, l
);
15961 mips_align (2, 0, l
);
15965 mips_clear_insn_labels ();
15968 /* Handle .globl. We need to override it because on Irix 5 you are
15971 where foo is an undefined symbol, to mean that foo should be
15972 considered to be the address of a function. */
15975 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15984 name
= input_line_pointer
;
15985 c
= get_symbol_end ();
15986 symbolP
= symbol_find_or_make (name
);
15987 S_SET_EXTERNAL (symbolP
);
15989 *input_line_pointer
= c
;
15990 SKIP_WHITESPACE ();
15992 /* On Irix 5, every global symbol that is not explicitly labelled as
15993 being a function is apparently labelled as being an object. */
15996 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15997 && (*input_line_pointer
!= ','))
16002 secname
= input_line_pointer
;
16003 c
= get_symbol_end ();
16004 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16006 as_bad (_("%s: no such section"), secname
);
16007 *input_line_pointer
= c
;
16009 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16010 flag
= BSF_FUNCTION
;
16013 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16015 c
= *input_line_pointer
;
16018 input_line_pointer
++;
16019 SKIP_WHITESPACE ();
16020 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16026 demand_empty_rest_of_line ();
16030 s_option (int x ATTRIBUTE_UNUSED
)
16035 opt
= input_line_pointer
;
16036 c
= get_symbol_end ();
16040 /* FIXME: What does this mean? */
16042 else if (strncmp (opt
, "pic", 3) == 0)
16046 i
= atoi (opt
+ 3);
16051 mips_pic
= SVR4_PIC
;
16052 mips_abicalls
= TRUE
;
16055 as_bad (_(".option pic%d not supported"), i
);
16057 if (mips_pic
== SVR4_PIC
)
16059 if (g_switch_seen
&& g_switch_value
!= 0)
16060 as_warn (_("-G may not be used with SVR4 PIC code"));
16061 g_switch_value
= 0;
16062 bfd_set_gp_size (stdoutput
, 0);
16066 as_warn (_("Unrecognized option \"%s\""), opt
);
16068 *input_line_pointer
= c
;
16069 demand_empty_rest_of_line ();
16072 /* This structure is used to hold a stack of .set values. */
16074 struct mips_option_stack
16076 struct mips_option_stack
*next
;
16077 struct mips_set_options options
;
16080 static struct mips_option_stack
*mips_opts_stack
;
16082 /* Handle the .set pseudo-op. */
16085 s_mipsset (int x ATTRIBUTE_UNUSED
)
16087 char *name
= input_line_pointer
, ch
;
16089 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16090 ++input_line_pointer
;
16091 ch
= *input_line_pointer
;
16092 *input_line_pointer
= '\0';
16094 if (strcmp (name
, "reorder") == 0)
16096 if (mips_opts
.noreorder
)
16099 else if (strcmp (name
, "noreorder") == 0)
16101 if (!mips_opts
.noreorder
)
16102 start_noreorder ();
16104 else if (strncmp (name
, "at=", 3) == 0)
16106 char *s
= name
+ 3;
16108 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16109 as_bad (_("Unrecognized register name `%s'"), s
);
16111 else if (strcmp (name
, "at") == 0)
16113 mips_opts
.at
= ATREG
;
16115 else if (strcmp (name
, "noat") == 0)
16117 mips_opts
.at
= ZERO
;
16119 else if (strcmp (name
, "macro") == 0)
16121 mips_opts
.warn_about_macros
= 0;
16123 else if (strcmp (name
, "nomacro") == 0)
16125 if (mips_opts
.noreorder
== 0)
16126 as_bad (_("`noreorder' must be set before `nomacro'"));
16127 mips_opts
.warn_about_macros
= 1;
16129 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16131 mips_opts
.nomove
= 0;
16133 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16135 mips_opts
.nomove
= 1;
16137 else if (strcmp (name
, "bopt") == 0)
16139 mips_opts
.nobopt
= 0;
16141 else if (strcmp (name
, "nobopt") == 0)
16143 mips_opts
.nobopt
= 1;
16145 else if (strcmp (name
, "gp=default") == 0)
16146 mips_opts
.gp32
= file_mips_gp32
;
16147 else if (strcmp (name
, "gp=32") == 0)
16148 mips_opts
.gp32
= 1;
16149 else if (strcmp (name
, "gp=64") == 0)
16151 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16152 as_warn (_("%s isa does not support 64-bit registers"),
16153 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16154 mips_opts
.gp32
= 0;
16156 else if (strcmp (name
, "fp=default") == 0)
16157 mips_opts
.fp32
= file_mips_fp32
;
16158 else if (strcmp (name
, "fp=32") == 0)
16159 mips_opts
.fp32
= 1;
16160 else if (strcmp (name
, "fp=64") == 0)
16162 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16163 as_warn (_("%s isa does not support 64-bit floating point registers"),
16164 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16165 mips_opts
.fp32
= 0;
16167 else if (strcmp (name
, "softfloat") == 0)
16168 mips_opts
.soft_float
= 1;
16169 else if (strcmp (name
, "hardfloat") == 0)
16170 mips_opts
.soft_float
= 0;
16171 else if (strcmp (name
, "singlefloat") == 0)
16172 mips_opts
.single_float
= 1;
16173 else if (strcmp (name
, "doublefloat") == 0)
16174 mips_opts
.single_float
= 0;
16175 else if (strcmp (name
, "mips16") == 0
16176 || strcmp (name
, "MIPS-16") == 0)
16178 if (mips_opts
.micromips
== 1)
16179 as_fatal (_("`mips16' cannot be used with `micromips'"));
16180 mips_opts
.mips16
= 1;
16182 else if (strcmp (name
, "nomips16") == 0
16183 || strcmp (name
, "noMIPS-16") == 0)
16184 mips_opts
.mips16
= 0;
16185 else if (strcmp (name
, "micromips") == 0)
16187 if (mips_opts
.mips16
== 1)
16188 as_fatal (_("`micromips' cannot be used with `mips16'"));
16189 mips_opts
.micromips
= 1;
16191 else if (strcmp (name
, "nomicromips") == 0)
16192 mips_opts
.micromips
= 0;
16193 else if (strcmp (name
, "smartmips") == 0)
16195 if (!ISA_SUPPORTS_SMARTMIPS
)
16196 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16197 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16198 mips_opts
.ase_smartmips
= 1;
16200 else if (strcmp (name
, "nosmartmips") == 0)
16201 mips_opts
.ase_smartmips
= 0;
16202 else if (strcmp (name
, "mips3d") == 0)
16203 mips_opts
.ase_mips3d
= 1;
16204 else if (strcmp (name
, "nomips3d") == 0)
16205 mips_opts
.ase_mips3d
= 0;
16206 else if (strcmp (name
, "mdmx") == 0)
16207 mips_opts
.ase_mdmx
= 1;
16208 else if (strcmp (name
, "nomdmx") == 0)
16209 mips_opts
.ase_mdmx
= 0;
16210 else if (strcmp (name
, "dsp") == 0)
16212 if (!ISA_SUPPORTS_DSP_ASE
)
16213 as_warn (_("%s ISA does not support DSP ASE"),
16214 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16215 mips_opts
.ase_dsp
= 1;
16216 mips_opts
.ase_dspr2
= 0;
16218 else if (strcmp (name
, "nodsp") == 0)
16220 mips_opts
.ase_dsp
= 0;
16221 mips_opts
.ase_dspr2
= 0;
16223 else if (strcmp (name
, "dspr2") == 0)
16225 if (!ISA_SUPPORTS_DSPR2_ASE
)
16226 as_warn (_("%s ISA does not support DSP R2 ASE"),
16227 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16228 mips_opts
.ase_dspr2
= 1;
16229 mips_opts
.ase_dsp
= 1;
16231 else if (strcmp (name
, "nodspr2") == 0)
16233 mips_opts
.ase_dspr2
= 0;
16234 mips_opts
.ase_dsp
= 0;
16236 else if (strcmp (name
, "mt") == 0)
16238 if (!ISA_SUPPORTS_MT_ASE
)
16239 as_warn (_("%s ISA does not support MT ASE"),
16240 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16241 mips_opts
.ase_mt
= 1;
16243 else if (strcmp (name
, "nomt") == 0)
16244 mips_opts
.ase_mt
= 0;
16245 else if (strcmp (name
, "mcu") == 0)
16246 mips_opts
.ase_mcu
= 1;
16247 else if (strcmp (name
, "nomcu") == 0)
16248 mips_opts
.ase_mcu
= 0;
16249 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16253 /* Permit the user to change the ISA and architecture on the fly.
16254 Needless to say, misuse can cause serious problems. */
16255 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16258 mips_opts
.isa
= file_mips_isa
;
16259 mips_opts
.arch
= file_mips_arch
;
16261 else if (strncmp (name
, "arch=", 5) == 0)
16263 const struct mips_cpu_info
*p
;
16265 p
= mips_parse_cpu("internal use", name
+ 5);
16267 as_bad (_("unknown architecture %s"), name
+ 5);
16270 mips_opts
.arch
= p
->cpu
;
16271 mips_opts
.isa
= p
->isa
;
16274 else if (strncmp (name
, "mips", 4) == 0)
16276 const struct mips_cpu_info
*p
;
16278 p
= mips_parse_cpu("internal use", name
);
16280 as_bad (_("unknown ISA level %s"), name
+ 4);
16283 mips_opts
.arch
= p
->cpu
;
16284 mips_opts
.isa
= p
->isa
;
16288 as_bad (_("unknown ISA or architecture %s"), name
);
16290 switch (mips_opts
.isa
)
16298 mips_opts
.gp32
= 1;
16299 mips_opts
.fp32
= 1;
16306 mips_opts
.gp32
= 0;
16307 mips_opts
.fp32
= 0;
16310 as_bad (_("unknown ISA level %s"), name
+ 4);
16315 mips_opts
.gp32
= file_mips_gp32
;
16316 mips_opts
.fp32
= file_mips_fp32
;
16319 else if (strcmp (name
, "autoextend") == 0)
16320 mips_opts
.noautoextend
= 0;
16321 else if (strcmp (name
, "noautoextend") == 0)
16322 mips_opts
.noautoextend
= 1;
16323 else if (strcmp (name
, "push") == 0)
16325 struct mips_option_stack
*s
;
16327 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16328 s
->next
= mips_opts_stack
;
16329 s
->options
= mips_opts
;
16330 mips_opts_stack
= s
;
16332 else if (strcmp (name
, "pop") == 0)
16334 struct mips_option_stack
*s
;
16336 s
= mips_opts_stack
;
16338 as_bad (_(".set pop with no .set push"));
16341 /* If we're changing the reorder mode we need to handle
16342 delay slots correctly. */
16343 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16344 start_noreorder ();
16345 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16348 mips_opts
= s
->options
;
16349 mips_opts_stack
= s
->next
;
16353 else if (strcmp (name
, "sym32") == 0)
16354 mips_opts
.sym32
= TRUE
;
16355 else if (strcmp (name
, "nosym32") == 0)
16356 mips_opts
.sym32
= FALSE
;
16357 else if (strchr (name
, ','))
16359 /* Generic ".set" directive; use the generic handler. */
16360 *input_line_pointer
= ch
;
16361 input_line_pointer
= name
;
16367 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16369 *input_line_pointer
= ch
;
16370 demand_empty_rest_of_line ();
16373 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16374 .option pic2. It means to generate SVR4 PIC calls. */
16377 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16379 mips_pic
= SVR4_PIC
;
16380 mips_abicalls
= TRUE
;
16382 if (g_switch_seen
&& g_switch_value
!= 0)
16383 as_warn (_("-G may not be used with SVR4 PIC code"));
16384 g_switch_value
= 0;
16386 bfd_set_gp_size (stdoutput
, 0);
16387 demand_empty_rest_of_line ();
16390 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16391 PIC code. It sets the $gp register for the function based on the
16392 function address, which is in the register named in the argument.
16393 This uses a relocation against _gp_disp, which is handled specially
16394 by the linker. The result is:
16395 lui $gp,%hi(_gp_disp)
16396 addiu $gp,$gp,%lo(_gp_disp)
16397 addu $gp,$gp,.cpload argument
16398 The .cpload argument is normally $25 == $t9.
16400 The -mno-shared option changes this to:
16401 lui $gp,%hi(__gnu_local_gp)
16402 addiu $gp,$gp,%lo(__gnu_local_gp)
16403 and the argument is ignored. This saves an instruction, but the
16404 resulting code is not position independent; it uses an absolute
16405 address for __gnu_local_gp. Thus code assembled with -mno-shared
16406 can go into an ordinary executable, but not into a shared library. */
16409 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16415 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16416 .cpload is ignored. */
16417 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16423 if (mips_opts
.mips16
)
16425 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16426 ignore_rest_of_line ();
16430 /* .cpload should be in a .set noreorder section. */
16431 if (mips_opts
.noreorder
== 0)
16432 as_warn (_(".cpload not in noreorder section"));
16434 reg
= tc_get_register (0);
16436 /* If we need to produce a 64-bit address, we are better off using
16437 the default instruction sequence. */
16438 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16440 ex
.X_op
= O_symbol
;
16441 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16443 ex
.X_op_symbol
= NULL
;
16444 ex
.X_add_number
= 0;
16446 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16447 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16450 macro_build_lui (&ex
, mips_gp_register
);
16451 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16452 mips_gp_register
, BFD_RELOC_LO16
);
16454 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16455 mips_gp_register
, reg
);
16458 demand_empty_rest_of_line ();
16461 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16462 .cpsetup $reg1, offset|$reg2, label
16464 If offset is given, this results in:
16465 sd $gp, offset($sp)
16466 lui $gp, %hi(%neg(%gp_rel(label)))
16467 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16468 daddu $gp, $gp, $reg1
16470 If $reg2 is given, this results in:
16471 daddu $reg2, $gp, $0
16472 lui $gp, %hi(%neg(%gp_rel(label)))
16473 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16474 daddu $gp, $gp, $reg1
16475 $reg1 is normally $25 == $t9.
16477 The -mno-shared option replaces the last three instructions with
16479 addiu $gp,$gp,%lo(_gp) */
16482 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16484 expressionS ex_off
;
16485 expressionS ex_sym
;
16488 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16489 We also need NewABI support. */
16490 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16496 if (mips_opts
.mips16
)
16498 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16499 ignore_rest_of_line ();
16503 reg1
= tc_get_register (0);
16504 SKIP_WHITESPACE ();
16505 if (*input_line_pointer
!= ',')
16507 as_bad (_("missing argument separator ',' for .cpsetup"));
16511 ++input_line_pointer
;
16512 SKIP_WHITESPACE ();
16513 if (*input_line_pointer
== '$')
16515 mips_cpreturn_register
= tc_get_register (0);
16516 mips_cpreturn_offset
= -1;
16520 mips_cpreturn_offset
= get_absolute_expression ();
16521 mips_cpreturn_register
= -1;
16523 SKIP_WHITESPACE ();
16524 if (*input_line_pointer
!= ',')
16526 as_bad (_("missing argument separator ',' for .cpsetup"));
16530 ++input_line_pointer
;
16531 SKIP_WHITESPACE ();
16532 expression (&ex_sym
);
16535 if (mips_cpreturn_register
== -1)
16537 ex_off
.X_op
= O_constant
;
16538 ex_off
.X_add_symbol
= NULL
;
16539 ex_off
.X_op_symbol
= NULL
;
16540 ex_off
.X_add_number
= mips_cpreturn_offset
;
16542 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16543 BFD_RELOC_LO16
, SP
);
16546 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16547 mips_gp_register
, 0);
16549 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16551 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16552 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16555 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16556 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16557 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16559 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16560 mips_gp_register
, reg1
);
16566 ex
.X_op
= O_symbol
;
16567 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16568 ex
.X_op_symbol
= NULL
;
16569 ex
.X_add_number
= 0;
16571 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16572 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16574 macro_build_lui (&ex
, mips_gp_register
);
16575 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16576 mips_gp_register
, BFD_RELOC_LO16
);
16581 demand_empty_rest_of_line ();
16585 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16587 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16588 .cplocal is ignored. */
16589 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16595 if (mips_opts
.mips16
)
16597 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16598 ignore_rest_of_line ();
16602 mips_gp_register
= tc_get_register (0);
16603 demand_empty_rest_of_line ();
16606 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16607 offset from $sp. The offset is remembered, and after making a PIC
16608 call $gp is restored from that location. */
16611 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16615 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16616 .cprestore is ignored. */
16617 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16623 if (mips_opts
.mips16
)
16625 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16626 ignore_rest_of_line ();
16630 mips_cprestore_offset
= get_absolute_expression ();
16631 mips_cprestore_valid
= 1;
16633 ex
.X_op
= O_constant
;
16634 ex
.X_add_symbol
= NULL
;
16635 ex
.X_op_symbol
= NULL
;
16636 ex
.X_add_number
= mips_cprestore_offset
;
16639 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16640 SP
, HAVE_64BIT_ADDRESSES
);
16643 demand_empty_rest_of_line ();
16646 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16647 was given in the preceding .cpsetup, it results in:
16648 ld $gp, offset($sp)
16650 If a register $reg2 was given there, it results in:
16651 daddu $gp, $reg2, $0 */
16654 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16658 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16659 We also need NewABI support. */
16660 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16666 if (mips_opts
.mips16
)
16668 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16669 ignore_rest_of_line ();
16674 if (mips_cpreturn_register
== -1)
16676 ex
.X_op
= O_constant
;
16677 ex
.X_add_symbol
= NULL
;
16678 ex
.X_op_symbol
= NULL
;
16679 ex
.X_add_number
= mips_cpreturn_offset
;
16681 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16684 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16685 mips_cpreturn_register
, 0);
16688 demand_empty_rest_of_line ();
16691 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16692 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16693 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16694 debug information or MIPS16 TLS. */
16697 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16698 bfd_reloc_code_real_type rtype
)
16705 if (ex
.X_op
!= O_symbol
)
16707 as_bad (_("Unsupported use of %s"), dirstr
);
16708 ignore_rest_of_line ();
16711 p
= frag_more (bytes
);
16712 md_number_to_chars (p
, 0, bytes
);
16713 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16714 demand_empty_rest_of_line ();
16715 mips_clear_insn_labels ();
16718 /* Handle .dtprelword. */
16721 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16723 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16726 /* Handle .dtpreldword. */
16729 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16731 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16734 /* Handle .tprelword. */
16737 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16739 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16742 /* Handle .tpreldword. */
16745 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16747 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16750 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16751 code. It sets the offset to use in gp_rel relocations. */
16754 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16756 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16757 We also need NewABI support. */
16758 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16764 mips_gprel_offset
= get_absolute_expression ();
16766 demand_empty_rest_of_line ();
16769 /* Handle the .gpword pseudo-op. This is used when generating PIC
16770 code. It generates a 32 bit GP relative reloc. */
16773 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16775 segment_info_type
*si
;
16776 struct insn_label_list
*l
;
16780 /* When not generating PIC code, this is treated as .word. */
16781 if (mips_pic
!= SVR4_PIC
)
16787 si
= seg_info (now_seg
);
16788 l
= si
->label_list
;
16789 mips_emit_delays ();
16791 mips_align (2, 0, l
);
16794 mips_clear_insn_labels ();
16796 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16798 as_bad (_("Unsupported use of .gpword"));
16799 ignore_rest_of_line ();
16803 md_number_to_chars (p
, 0, 4);
16804 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16805 BFD_RELOC_GPREL32
);
16807 demand_empty_rest_of_line ();
16811 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16813 segment_info_type
*si
;
16814 struct insn_label_list
*l
;
16818 /* When not generating PIC code, this is treated as .dword. */
16819 if (mips_pic
!= SVR4_PIC
)
16825 si
= seg_info (now_seg
);
16826 l
= si
->label_list
;
16827 mips_emit_delays ();
16829 mips_align (3, 0, l
);
16832 mips_clear_insn_labels ();
16834 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16836 as_bad (_("Unsupported use of .gpdword"));
16837 ignore_rest_of_line ();
16841 md_number_to_chars (p
, 0, 8);
16842 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16843 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16845 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16846 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16847 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16849 demand_empty_rest_of_line ();
16852 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16853 tables in SVR4 PIC code. */
16856 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16860 /* This is ignored when not generating SVR4 PIC code. */
16861 if (mips_pic
!= SVR4_PIC
)
16867 /* Add $gp to the register named as an argument. */
16869 reg
= tc_get_register (0);
16870 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16873 demand_empty_rest_of_line ();
16876 /* Handle the .insn pseudo-op. This marks instruction labels in
16877 mips16/micromips mode. This permits the linker to handle them specially,
16878 such as generating jalx instructions when needed. We also make
16879 them odd for the duration of the assembly, in order to generate the
16880 right sort of code. We will make them even in the adjust_symtab
16881 routine, while leaving them marked. This is convenient for the
16882 debugger and the disassembler. The linker knows to make them odd
16886 s_insn (int ignore ATTRIBUTE_UNUSED
)
16888 mips_mark_labels ();
16890 demand_empty_rest_of_line ();
16893 /* Handle a .stabn directive. We need these in order to mark a label
16894 as being a mips16 text label correctly. Sometimes the compiler
16895 will emit a label, followed by a .stabn, and then switch sections.
16896 If the label and .stabn are in mips16 mode, then the label is
16897 really a mips16 text label. */
16900 s_mips_stab (int type
)
16903 mips_mark_labels ();
16908 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16911 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
16918 name
= input_line_pointer
;
16919 c
= get_symbol_end ();
16920 symbolP
= symbol_find_or_make (name
);
16921 S_SET_WEAK (symbolP
);
16922 *input_line_pointer
= c
;
16924 SKIP_WHITESPACE ();
16926 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
16928 if (S_IS_DEFINED (symbolP
))
16930 as_bad (_("ignoring attempt to redefine symbol %s"),
16931 S_GET_NAME (symbolP
));
16932 ignore_rest_of_line ();
16936 if (*input_line_pointer
== ',')
16938 ++input_line_pointer
;
16939 SKIP_WHITESPACE ();
16943 if (exp
.X_op
!= O_symbol
)
16945 as_bad (_("bad .weakext directive"));
16946 ignore_rest_of_line ();
16949 symbol_set_value_expression (symbolP
, &exp
);
16952 demand_empty_rest_of_line ();
16955 /* Parse a register string into a number. Called from the ECOFF code
16956 to parse .frame. The argument is non-zero if this is the frame
16957 register, so that we can record it in mips_frame_reg. */
16960 tc_get_register (int frame
)
16964 SKIP_WHITESPACE ();
16965 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
16969 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
16970 mips_frame_reg_valid
= 1;
16971 mips_cprestore_valid
= 0;
16977 md_section_align (asection
*seg
, valueT addr
)
16979 int align
= bfd_get_section_alignment (stdoutput
, seg
);
16983 /* We don't need to align ELF sections to the full alignment.
16984 However, Irix 5 may prefer that we align them at least to a 16
16985 byte boundary. We don't bother to align the sections if we
16986 are targeted for an embedded system. */
16987 if (strncmp (TARGET_OS
, "elf", 3) == 0)
16993 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
16996 /* Utility routine, called from above as well. If called while the
16997 input file is still being read, it's only an approximation. (For
16998 example, a symbol may later become defined which appeared to be
16999 undefined earlier.) */
17002 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17007 if (g_switch_value
> 0)
17009 const char *symname
;
17012 /* Find out whether this symbol can be referenced off the $gp
17013 register. It can be if it is smaller than the -G size or if
17014 it is in the .sdata or .sbss section. Certain symbols can
17015 not be referenced off the $gp, although it appears as though
17017 symname
= S_GET_NAME (sym
);
17018 if (symname
!= (const char *) NULL
17019 && (strcmp (symname
, "eprol") == 0
17020 || strcmp (symname
, "etext") == 0
17021 || strcmp (symname
, "_gp") == 0
17022 || strcmp (symname
, "edata") == 0
17023 || strcmp (symname
, "_fbss") == 0
17024 || strcmp (symname
, "_fdata") == 0
17025 || strcmp (symname
, "_ftext") == 0
17026 || strcmp (symname
, "end") == 0
17027 || strcmp (symname
, "_gp_disp") == 0))
17029 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17031 #ifndef NO_ECOFF_DEBUGGING
17032 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17033 && (symbol_get_obj (sym
)->ecoff_extern_size
17034 <= g_switch_value
))
17036 /* We must defer this decision until after the whole
17037 file has been read, since there might be a .extern
17038 after the first use of this symbol. */
17039 || (before_relaxing
17040 #ifndef NO_ECOFF_DEBUGGING
17041 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17043 && S_GET_VALUE (sym
) == 0)
17044 || (S_GET_VALUE (sym
) != 0
17045 && S_GET_VALUE (sym
) <= g_switch_value
)))
17049 const char *segname
;
17051 segname
= segment_name (S_GET_SEGMENT (sym
));
17052 gas_assert (strcmp (segname
, ".lit8") != 0
17053 && strcmp (segname
, ".lit4") != 0);
17054 change
= (strcmp (segname
, ".sdata") != 0
17055 && strcmp (segname
, ".sbss") != 0
17056 && strncmp (segname
, ".sdata.", 7) != 0
17057 && strncmp (segname
, ".sbss.", 6) != 0
17058 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17059 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17064 /* We are not optimizing for the $gp register. */
17069 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17072 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17076 /* Handle the case of a symbol equated to another symbol. */
17077 while (symbol_equated_reloc_p (sym
))
17081 /* It's possible to get a loop here in a badly written program. */
17082 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17088 if (symbol_section_p (sym
))
17091 symsec
= S_GET_SEGMENT (sym
);
17093 /* This must duplicate the test in adjust_reloc_syms. */
17094 return (!bfd_is_und_section (symsec
)
17095 && !bfd_is_abs_section (symsec
)
17096 && !bfd_is_com_section (symsec
)
17097 && !s_is_linkonce (sym
, segtype
)
17099 /* A global or weak symbol is treated as external. */
17100 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17106 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17107 extended opcode. SEC is the section the frag is in. */
17110 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17113 const struct mips16_immed_operand
*op
;
17115 int mintiny
, maxtiny
;
17119 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17121 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17124 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17125 op
= mips16_immed_operands
;
17126 while (op
->type
!= type
)
17129 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17134 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17137 maxtiny
= 1 << op
->nbits
;
17142 maxtiny
= (1 << op
->nbits
) - 1;
17147 mintiny
= - (1 << (op
->nbits
- 1));
17148 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17151 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17152 val
= S_GET_VALUE (fragp
->fr_symbol
);
17153 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17159 /* We won't have the section when we are called from
17160 mips_relax_frag. However, we will always have been called
17161 from md_estimate_size_before_relax first. If this is a
17162 branch to a different section, we mark it as such. If SEC is
17163 NULL, and the frag is not marked, then it must be a branch to
17164 the same section. */
17167 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17172 /* Must have been called from md_estimate_size_before_relax. */
17175 fragp
->fr_subtype
=
17176 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17178 /* FIXME: We should support this, and let the linker
17179 catch branches and loads that are out of range. */
17180 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17181 _("unsupported PC relative reference to different section"));
17185 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17186 /* Assume non-extended on the first relaxation pass.
17187 The address we have calculated will be bogus if this is
17188 a forward branch to another frag, as the forward frag
17189 will have fr_address == 0. */
17193 /* In this case, we know for sure that the symbol fragment is in
17194 the same section. If the relax_marker of the symbol fragment
17195 differs from the relax_marker of this fragment, we have not
17196 yet adjusted the symbol fragment fr_address. We want to add
17197 in STRETCH in order to get a better estimate of the address.
17198 This particularly matters because of the shift bits. */
17200 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17204 /* Adjust stretch for any alignment frag. Note that if have
17205 been expanding the earlier code, the symbol may be
17206 defined in what appears to be an earlier frag. FIXME:
17207 This doesn't handle the fr_subtype field, which specifies
17208 a maximum number of bytes to skip when doing an
17210 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17212 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17215 stretch
= - ((- stretch
)
17216 & ~ ((1 << (int) f
->fr_offset
) - 1));
17218 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17227 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17229 /* The base address rules are complicated. The base address of
17230 a branch is the following instruction. The base address of a
17231 PC relative load or add is the instruction itself, but if it
17232 is in a delay slot (in which case it can not be extended) use
17233 the address of the instruction whose delay slot it is in. */
17234 if (type
== 'p' || type
== 'q')
17238 /* If we are currently assuming that this frag should be
17239 extended, then, the current address is two bytes
17241 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17244 /* Ignore the low bit in the target, since it will be set
17245 for a text label. */
17246 if ((val
& 1) != 0)
17249 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17251 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17254 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17256 /* Branch offsets have an implicit 0 in the lowest bit. */
17257 if (type
== 'p' || type
== 'q')
17260 /* If any of the shifted bits are set, we must use an extended
17261 opcode. If the address depends on the size of this
17262 instruction, this can lead to a loop, so we arrange to always
17263 use an extended opcode. We only check this when we are in
17264 the main relaxation loop, when SEC is NULL. */
17265 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17267 fragp
->fr_subtype
=
17268 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17272 /* If we are about to mark a frag as extended because the value
17273 is precisely maxtiny + 1, then there is a chance of an
17274 infinite loop as in the following code:
17279 In this case when the la is extended, foo is 0x3fc bytes
17280 away, so the la can be shrunk, but then foo is 0x400 away, so
17281 the la must be extended. To avoid this loop, we mark the
17282 frag as extended if it was small, and is about to become
17283 extended with a value of maxtiny + 1. */
17284 if (val
== ((maxtiny
+ 1) << op
->shift
)
17285 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17288 fragp
->fr_subtype
=
17289 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17293 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17294 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17296 if ((val
& ((1 << op
->shift
) - 1)) != 0
17297 || val
< (mintiny
<< op
->shift
)
17298 || val
> (maxtiny
<< op
->shift
))
17304 /* Compute the length of a branch sequence, and adjust the
17305 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17306 worst-case length is computed, with UPDATE being used to indicate
17307 whether an unconditional (-1), branch-likely (+1) or regular (0)
17308 branch is to be computed. */
17310 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17312 bfd_boolean toofar
;
17316 && S_IS_DEFINED (fragp
->fr_symbol
)
17317 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17322 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17324 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17328 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17331 /* If the symbol is not defined or it's in a different segment,
17332 assume the user knows what's going on and emit a short
17338 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17340 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17341 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17342 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17343 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17349 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17352 if (mips_pic
!= NO_PIC
)
17354 /* Additional space for PIC loading of target address. */
17356 if (mips_opts
.isa
== ISA_MIPS1
)
17357 /* Additional space for $at-stabilizing nop. */
17361 /* If branch is conditional. */
17362 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17369 /* Compute the length of a branch sequence, and adjust the
17370 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17371 worst-case length is computed, with UPDATE being used to indicate
17372 whether an unconditional (-1), or regular (0) branch is to be
17376 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17378 bfd_boolean toofar
;
17382 && S_IS_DEFINED (fragp
->fr_symbol
)
17383 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17388 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17389 /* Ignore the low bit in the target, since it will be set
17390 for a text label. */
17391 if ((val
& 1) != 0)
17394 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17398 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17401 /* If the symbol is not defined or it's in a different segment,
17402 assume the user knows what's going on and emit a short
17408 if (fragp
&& update
17409 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17410 fragp
->fr_subtype
= (toofar
17411 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17412 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17417 bfd_boolean compact_known
= fragp
!= NULL
;
17418 bfd_boolean compact
= FALSE
;
17419 bfd_boolean uncond
;
17422 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17424 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17426 uncond
= update
< 0;
17428 /* If label is out of range, we turn branch <br>:
17430 <br> label # 4 bytes
17436 nop # 2 bytes if compact && !PIC
17439 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17442 /* If assembling PIC code, we further turn:
17448 lw/ld at, %got(label)(gp) # 4 bytes
17449 d/addiu at, %lo(label) # 4 bytes
17452 if (mips_pic
!= NO_PIC
)
17455 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17457 <brneg> 0f # 4 bytes
17458 nop # 2 bytes if !compact
17461 length
+= (compact_known
&& compact
) ? 4 : 6;
17467 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17468 bit accordingly. */
17471 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17473 bfd_boolean toofar
;
17476 && S_IS_DEFINED (fragp
->fr_symbol
)
17477 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17483 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17484 /* Ignore the low bit in the target, since it will be set
17485 for a text label. */
17486 if ((val
& 1) != 0)
17489 /* Assume this is a 2-byte branch. */
17490 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17492 /* We try to avoid the infinite loop by not adding 2 more bytes for
17497 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17499 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17500 else if (type
== 'E')
17501 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17506 /* If the symbol is not defined or it's in a different segment,
17507 we emit a normal 32-bit branch. */
17510 if (fragp
&& update
17511 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17513 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17514 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17522 /* Estimate the size of a frag before relaxing. Unless this is the
17523 mips16, we are not really relaxing here, and the final size is
17524 encoded in the subtype information. For the mips16, we have to
17525 decide whether we are using an extended opcode or not. */
17528 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17532 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17535 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17537 return fragp
->fr_var
;
17540 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17541 /* We don't want to modify the EXTENDED bit here; it might get us
17542 into infinite loops. We change it only in mips_relax_frag(). */
17543 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17545 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17549 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17550 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17551 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17552 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17553 fragp
->fr_var
= length
;
17558 if (mips_pic
== NO_PIC
)
17559 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17560 else if (mips_pic
== SVR4_PIC
)
17561 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17562 else if (mips_pic
== VXWORKS_PIC
)
17563 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17570 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17571 return -RELAX_FIRST (fragp
->fr_subtype
);
17574 return -RELAX_SECOND (fragp
->fr_subtype
);
17577 /* This is called to see whether a reloc against a defined symbol
17578 should be converted into a reloc against a section. */
17581 mips_fix_adjustable (fixS
*fixp
)
17583 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17584 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17587 if (fixp
->fx_addsy
== NULL
)
17590 /* If symbol SYM is in a mergeable section, relocations of the form
17591 SYM + 0 can usually be made section-relative. The mergeable data
17592 is then identified by the section offset rather than by the symbol.
17594 However, if we're generating REL LO16 relocations, the offset is split
17595 between the LO16 and parterning high part relocation. The linker will
17596 need to recalculate the complete offset in order to correctly identify
17599 The linker has traditionally not looked for the parterning high part
17600 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17601 placed anywhere. Rather than break backwards compatibility by changing
17602 this, it seems better not to force the issue, and instead keep the
17603 original symbol. This will work with either linker behavior. */
17604 if ((lo16_reloc_p (fixp
->fx_r_type
)
17605 || reloc_needs_lo_p (fixp
->fx_r_type
))
17606 && HAVE_IN_PLACE_ADDENDS
17607 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17610 /* There is no place to store an in-place offset for JALR relocations.
17611 Likewise an in-range offset of PC-relative relocations may overflow
17612 the in-place relocatable field if recalculated against the start
17613 address of the symbol's containing section. */
17614 if (HAVE_IN_PLACE_ADDENDS
17615 && (fixp
->fx_pcrel
|| jalr_reloc_p (fixp
->fx_r_type
)))
17619 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17620 to a floating-point stub. The same is true for non-R_MIPS16_26
17621 relocations against MIPS16 functions; in this case, the stub becomes
17622 the function's canonical address.
17624 Floating-point stubs are stored in unique .mips16.call.* or
17625 .mips16.fn.* sections. If a stub T for function F is in section S,
17626 the first relocation in section S must be against F; this is how the
17627 linker determines the target function. All relocations that might
17628 resolve to T must also be against F. We therefore have the following
17629 restrictions, which are given in an intentionally-redundant way:
17631 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17634 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17635 if that stub might be used.
17637 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17640 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17641 that stub might be used.
17643 There is a further restriction:
17645 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17646 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17647 targets with in-place addends; the relocation field cannot
17648 encode the low bit.
17650 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17651 against a MIPS16 symbol. We deal with (5) by by not reducing any
17652 such relocations on REL targets.
17654 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17655 relocation against some symbol R, no relocation against R may be
17656 reduced. (Note that this deals with (2) as well as (1) because
17657 relocations against global symbols will never be reduced on ELF
17658 targets.) This approach is a little simpler than trying to detect
17659 stub sections, and gives the "all or nothing" per-symbol consistency
17660 that we have for MIPS16 symbols. */
17662 && fixp
->fx_subsy
== NULL
17663 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17664 || *symbol_get_tc (fixp
->fx_addsy
)
17665 || (HAVE_IN_PLACE_ADDENDS
17666 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17667 && jmp_reloc_p (fixp
->fx_r_type
))))
17674 /* Translate internal representation of relocation info to BFD target
17678 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17680 static arelent
*retval
[4];
17682 bfd_reloc_code_real_type code
;
17684 memset (retval
, 0, sizeof(retval
));
17685 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17686 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17687 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17688 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17690 if (fixp
->fx_pcrel
)
17692 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17693 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17694 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17695 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17697 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17698 Relocations want only the symbol offset. */
17699 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17702 /* A gruesome hack which is a result of the gruesome gas
17703 reloc handling. What's worse, for COFF (as opposed to
17704 ECOFF), we might need yet another copy of reloc->address.
17705 See bfd_install_relocation. */
17706 reloc
->addend
+= reloc
->address
;
17710 reloc
->addend
= fixp
->fx_addnumber
;
17712 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17713 entry to be used in the relocation's section offset. */
17714 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17716 reloc
->address
= reloc
->addend
;
17720 code
= fixp
->fx_r_type
;
17722 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17723 if (reloc
->howto
== NULL
)
17725 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17726 _("Can not represent %s relocation in this object file format"),
17727 bfd_get_reloc_code_name (code
));
17734 /* Relax a machine dependent frag. This returns the amount by which
17735 the current size of the frag should change. */
17738 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17740 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17742 offsetT old_var
= fragp
->fr_var
;
17744 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17746 return fragp
->fr_var
- old_var
;
17749 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17751 offsetT old_var
= fragp
->fr_var
;
17752 offsetT new_var
= 4;
17754 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17755 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17756 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17757 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17758 fragp
->fr_var
= new_var
;
17760 return new_var
- old_var
;
17763 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17766 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17768 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17770 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17775 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17777 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17784 /* Convert a machine dependent frag. */
17787 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17789 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17792 unsigned long insn
;
17796 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17797 insn
= read_insn (buf
);
17799 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17801 /* We generate a fixup instead of applying it right now
17802 because, if there are linker relaxations, we're going to
17803 need the relocations. */
17804 exp
.X_op
= O_symbol
;
17805 exp
.X_add_symbol
= fragp
->fr_symbol
;
17806 exp
.X_add_number
= fragp
->fr_offset
;
17808 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17809 BFD_RELOC_16_PCREL_S2
);
17810 fixp
->fx_file
= fragp
->fr_file
;
17811 fixp
->fx_line
= fragp
->fr_line
;
17813 buf
= write_insn (buf
, insn
);
17819 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17820 _("Relaxed out-of-range branch into a jump"));
17822 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17825 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17827 /* Reverse the branch. */
17828 switch ((insn
>> 28) & 0xf)
17831 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17832 have the condition reversed by tweaking a single
17833 bit, and their opcodes all have 0x4???????. */
17834 gas_assert ((insn
& 0xf1000000) == 0x41000000);
17835 insn
^= 0x00010000;
17839 /* bltz 0x04000000 bgez 0x04010000
17840 bltzal 0x04100000 bgezal 0x04110000 */
17841 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17842 insn
^= 0x00010000;
17846 /* beq 0x10000000 bne 0x14000000
17847 blez 0x18000000 bgtz 0x1c000000 */
17848 insn
^= 0x04000000;
17856 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17858 /* Clear the and-link bit. */
17859 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17861 /* bltzal 0x04100000 bgezal 0x04110000
17862 bltzall 0x04120000 bgezall 0x04130000 */
17863 insn
&= ~0x00100000;
17866 /* Branch over the branch (if the branch was likely) or the
17867 full jump (not likely case). Compute the offset from the
17868 current instruction to branch to. */
17869 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17873 /* How many bytes in instructions we've already emitted? */
17874 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17875 /* How many bytes in instructions from here to the end? */
17876 i
= fragp
->fr_var
- i
;
17878 /* Convert to instruction count. */
17880 /* Branch counts from the next instruction. */
17883 /* Branch over the jump. */
17884 buf
= write_insn (buf
, insn
);
17887 buf
= write_insn (buf
, 0);
17889 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17891 /* beql $0, $0, 2f */
17893 /* Compute the PC offset from the current instruction to
17894 the end of the variable frag. */
17895 /* How many bytes in instructions we've already emitted? */
17896 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17897 /* How many bytes in instructions from here to the end? */
17898 i
= fragp
->fr_var
- i
;
17899 /* Convert to instruction count. */
17901 /* Don't decrement i, because we want to branch over the
17905 buf
= write_insn (buf
, insn
);
17906 buf
= write_insn (buf
, 0);
17910 if (mips_pic
== NO_PIC
)
17913 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
17914 ? 0x0c000000 : 0x08000000);
17915 exp
.X_op
= O_symbol
;
17916 exp
.X_add_symbol
= fragp
->fr_symbol
;
17917 exp
.X_add_number
= fragp
->fr_offset
;
17919 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17920 FALSE
, BFD_RELOC_MIPS_JMP
);
17921 fixp
->fx_file
= fragp
->fr_file
;
17922 fixp
->fx_line
= fragp
->fr_line
;
17924 buf
= write_insn (buf
, insn
);
17928 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
17930 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17931 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
17932 insn
|= at
<< OP_SH_RT
;
17933 exp
.X_op
= O_symbol
;
17934 exp
.X_add_symbol
= fragp
->fr_symbol
;
17935 exp
.X_add_number
= fragp
->fr_offset
;
17937 if (fragp
->fr_offset
)
17939 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17940 exp
.X_add_number
= 0;
17943 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17944 FALSE
, BFD_RELOC_MIPS_GOT16
);
17945 fixp
->fx_file
= fragp
->fr_file
;
17946 fixp
->fx_line
= fragp
->fr_line
;
17948 buf
= write_insn (buf
, insn
);
17950 if (mips_opts
.isa
== ISA_MIPS1
)
17952 buf
= write_insn (buf
, 0);
17954 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17955 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
17956 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
17958 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
17959 FALSE
, BFD_RELOC_LO16
);
17960 fixp
->fx_file
= fragp
->fr_file
;
17961 fixp
->fx_line
= fragp
->fr_line
;
17963 buf
= write_insn (buf
, insn
);
17966 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17970 insn
|= at
<< OP_SH_RS
;
17972 buf
= write_insn (buf
, insn
);
17976 fragp
->fr_fix
+= fragp
->fr_var
;
17977 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17981 /* Relax microMIPS branches. */
17982 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17984 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17985 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17986 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17987 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17988 bfd_boolean short_ds
;
17989 unsigned long insn
;
17993 exp
.X_op
= O_symbol
;
17994 exp
.X_add_symbol
= fragp
->fr_symbol
;
17995 exp
.X_add_number
= fragp
->fr_offset
;
17997 fragp
->fr_fix
+= fragp
->fr_var
;
17999 /* Handle 16-bit branches that fit or are forced to fit. */
18000 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18002 /* We generate a fixup instead of applying it right now,
18003 because if there is linker relaxation, we're going to
18004 need the relocations. */
18006 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18007 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18008 else if (type
== 'E')
18009 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18010 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18014 fixp
->fx_file
= fragp
->fr_file
;
18015 fixp
->fx_line
= fragp
->fr_line
;
18017 /* These relocations can have an addend that won't fit in
18019 fixp
->fx_no_overflow
= 1;
18024 /* Handle 32-bit branches that fit or are forced to fit. */
18025 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18026 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18028 /* We generate a fixup instead of applying it right now,
18029 because if there is linker relaxation, we're going to
18030 need the relocations. */
18031 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18032 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18033 fixp
->fx_file
= fragp
->fr_file
;
18034 fixp
->fx_line
= fragp
->fr_line
;
18040 /* Relax 16-bit branches to 32-bit branches. */
18043 insn
= read_compressed_insn (buf
, 2);
18045 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18046 insn
= 0x94000000; /* beq */
18047 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18049 unsigned long regno
;
18051 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18052 regno
= micromips_to_32_reg_d_map
[regno
];
18053 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18054 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18059 /* Nothing else to do, just write it out. */
18060 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18061 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18063 buf
= write_compressed_insn (buf
, insn
, 4);
18064 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18069 insn
= read_compressed_insn (buf
, 4);
18071 /* Relax 32-bit branches to a sequence of instructions. */
18072 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18073 _("Relaxed out-of-range branch into a jump"));
18075 /* Set the short-delay-slot bit. */
18076 short_ds
= al
&& (insn
& 0x02000000) != 0;
18078 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18082 /* Reverse the branch. */
18083 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18084 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18085 insn
^= 0x20000000;
18086 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18087 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18088 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18089 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18090 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18091 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18092 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18093 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18094 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18095 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18096 insn
^= 0x00400000;
18097 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18098 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18099 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18100 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18101 insn
^= 0x00200000;
18107 /* Clear the and-link and short-delay-slot bits. */
18108 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18110 /* bltzal 0x40200000 bgezal 0x40600000 */
18111 /* bltzals 0x42200000 bgezals 0x42600000 */
18112 insn
&= ~0x02200000;
18115 /* Make a label at the end for use with the branch. */
18116 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18117 micromips_label_inc ();
18118 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18120 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18124 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18125 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18126 fixp
->fx_file
= fragp
->fr_file
;
18127 fixp
->fx_line
= fragp
->fr_line
;
18129 /* Branch over the jump. */
18130 buf
= write_compressed_insn (buf
, insn
, 4);
18133 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18136 if (mips_pic
== NO_PIC
)
18138 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18140 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18141 insn
= al
? jal
: 0xd4000000;
18143 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18144 BFD_RELOC_MICROMIPS_JMP
);
18145 fixp
->fx_file
= fragp
->fr_file
;
18146 fixp
->fx_line
= fragp
->fr_line
;
18148 buf
= write_compressed_insn (buf
, insn
, 4);
18151 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18155 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18156 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18157 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18159 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18160 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18161 insn
|= at
<< MICROMIPSOP_SH_RT
;
18163 if (exp
.X_add_number
)
18165 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18166 exp
.X_add_number
= 0;
18169 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18170 BFD_RELOC_MICROMIPS_GOT16
);
18171 fixp
->fx_file
= fragp
->fr_file
;
18172 fixp
->fx_line
= fragp
->fr_line
;
18174 buf
= write_compressed_insn (buf
, insn
, 4);
18176 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18177 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18178 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18180 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18181 BFD_RELOC_MICROMIPS_LO16
);
18182 fixp
->fx_file
= fragp
->fr_file
;
18183 fixp
->fx_line
= fragp
->fr_line
;
18185 buf
= write_compressed_insn (buf
, insn
, 4);
18187 /* jr/jrc/jalr/jalrs $at */
18188 insn
= al
? jalr
: jr
;
18189 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18191 buf
= write_compressed_insn (buf
, insn
, 2);
18194 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18198 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18201 const struct mips16_immed_operand
*op
;
18204 unsigned int user_length
, length
;
18205 unsigned long insn
;
18208 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18209 op
= mips16_immed_operands
;
18210 while (op
->type
!= type
)
18213 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18214 val
= resolve_symbol_value (fragp
->fr_symbol
);
18219 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18221 /* The rules for the base address of a PC relative reloc are
18222 complicated; see mips16_extended_frag. */
18223 if (type
== 'p' || type
== 'q')
18228 /* Ignore the low bit in the target, since it will be
18229 set for a text label. */
18230 if ((val
& 1) != 0)
18233 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18235 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18238 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18241 /* Make sure the section winds up with the alignment we have
18244 record_alignment (asec
, op
->shift
);
18248 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18249 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18250 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18251 _("extended instruction in delay slot"));
18253 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18255 insn
= read_compressed_insn (buf
, 2);
18257 insn
|= MIPS16_EXTEND
;
18259 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18261 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18266 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
18267 user_length
, &insn
);
18269 length
= (ext
? 4 : 2);
18270 gas_assert (mips16_opcode_length (insn
) == length
);
18271 write_compressed_insn (buf
, insn
, length
);
18272 fragp
->fr_fix
+= length
;
18276 relax_substateT subtype
= fragp
->fr_subtype
;
18277 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18278 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18282 first
= RELAX_FIRST (subtype
);
18283 second
= RELAX_SECOND (subtype
);
18284 fixp
= (fixS
*) fragp
->fr_opcode
;
18286 /* If the delay slot chosen does not match the size of the instruction,
18287 then emit a warning. */
18288 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18289 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18294 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18295 | RELAX_DELAY_SLOT_SIZE_FIRST
18296 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18297 msg
= macro_warning (s
);
18299 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18303 /* Possibly emit a warning if we've chosen the longer option. */
18304 if (use_second
== second_longer
)
18310 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18311 msg
= macro_warning (s
);
18313 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18317 /* Go through all the fixups for the first sequence. Disable them
18318 (by marking them as done) if we're going to use the second
18319 sequence instead. */
18321 && fixp
->fx_frag
== fragp
18322 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18324 if (subtype
& RELAX_USE_SECOND
)
18326 fixp
= fixp
->fx_next
;
18329 /* Go through the fixups for the second sequence. Disable them if
18330 we're going to use the first sequence, otherwise adjust their
18331 addresses to account for the relaxation. */
18332 while (fixp
&& fixp
->fx_frag
== fragp
)
18334 if (subtype
& RELAX_USE_SECOND
)
18335 fixp
->fx_where
-= first
;
18338 fixp
= fixp
->fx_next
;
18341 /* Now modify the frag contents. */
18342 if (subtype
& RELAX_USE_SECOND
)
18346 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18347 memmove (start
, start
+ first
, second
);
18348 fragp
->fr_fix
-= first
;
18351 fragp
->fr_fix
-= second
;
18357 /* This function is called after the relocs have been generated.
18358 We've been storing mips16 text labels as odd. Here we convert them
18359 back to even for the convenience of the debugger. */
18362 mips_frob_file_after_relocs (void)
18365 unsigned int count
, i
;
18370 syms
= bfd_get_outsymbols (stdoutput
);
18371 count
= bfd_get_symcount (stdoutput
);
18372 for (i
= 0; i
< count
; i
++, syms
++)
18373 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18374 && ((*syms
)->value
& 1) != 0)
18376 (*syms
)->value
&= ~1;
18377 /* If the symbol has an odd size, it was probably computed
18378 incorrectly, so adjust that as well. */
18379 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18380 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18386 /* This function is called whenever a label is defined, including fake
18387 labels instantiated off the dot special symbol. It is used when
18388 handling branch delays; if a branch has a label, we assume we cannot
18389 move it. This also bumps the value of the symbol by 1 in compressed
18393 mips_record_label (symbolS
*sym
)
18395 segment_info_type
*si
= seg_info (now_seg
);
18396 struct insn_label_list
*l
;
18398 if (free_insn_labels
== NULL
)
18399 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18402 l
= free_insn_labels
;
18403 free_insn_labels
= l
->next
;
18407 l
->next
= si
->label_list
;
18408 si
->label_list
= l
;
18411 /* This function is called as tc_frob_label() whenever a label is defined
18412 and adds a DWARF-2 record we only want for true labels. */
18415 mips_define_label (symbolS
*sym
)
18417 mips_record_label (sym
);
18419 dwarf2_emit_label (sym
);
18423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18425 /* Some special processing for a MIPS ELF file. */
18428 mips_elf_final_processing (void)
18430 /* Write out the register information. */
18431 if (mips_abi
!= N64_ABI
)
18435 s
.ri_gprmask
= mips_gprmask
;
18436 s
.ri_cprmask
[0] = mips_cprmask
[0];
18437 s
.ri_cprmask
[1] = mips_cprmask
[1];
18438 s
.ri_cprmask
[2] = mips_cprmask
[2];
18439 s
.ri_cprmask
[3] = mips_cprmask
[3];
18440 /* The gp_value field is set by the MIPS ELF backend. */
18442 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18443 ((Elf32_External_RegInfo
*)
18444 mips_regmask_frag
));
18448 Elf64_Internal_RegInfo s
;
18450 s
.ri_gprmask
= mips_gprmask
;
18452 s
.ri_cprmask
[0] = mips_cprmask
[0];
18453 s
.ri_cprmask
[1] = mips_cprmask
[1];
18454 s
.ri_cprmask
[2] = mips_cprmask
[2];
18455 s
.ri_cprmask
[3] = mips_cprmask
[3];
18456 /* The gp_value field is set by the MIPS ELF backend. */
18458 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18459 ((Elf64_External_RegInfo
*)
18460 mips_regmask_frag
));
18463 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18464 sort of BFD interface for this. */
18465 if (mips_any_noreorder
)
18466 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18467 if (mips_pic
!= NO_PIC
)
18469 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18470 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18473 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18475 /* Set MIPS ELF flags for ASEs. */
18476 /* We may need to define a new flag for DSP ASE, and set this flag when
18477 file_ase_dsp is true. */
18478 /* Same for DSP R2. */
18479 /* We may need to define a new flag for MT ASE, and set this flag when
18480 file_ase_mt is true. */
18481 if (file_ase_mips16
)
18482 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18483 if (file_ase_micromips
)
18484 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18485 #if 0 /* XXX FIXME */
18486 if (file_ase_mips3d
)
18487 elf_elfheader (stdoutput
)->e_flags
|= ???;
18490 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18492 /* Set the MIPS ELF ABI flags. */
18493 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18494 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18495 else if (mips_abi
== O64_ABI
)
18496 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18497 else if (mips_abi
== EABI_ABI
)
18499 if (!file_mips_gp32
)
18500 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18502 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18504 else if (mips_abi
== N32_ABI
)
18505 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18507 /* Nothing to do for N64_ABI. */
18509 if (mips_32bitmode
)
18510 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18512 #if 0 /* XXX FIXME */
18513 /* 32 bit code with 64 bit FP registers. */
18514 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18515 elf_elfheader (stdoutput
)->e_flags
|= ???;
18519 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18521 typedef struct proc
{
18523 symbolS
*func_end_sym
;
18524 unsigned long reg_mask
;
18525 unsigned long reg_offset
;
18526 unsigned long fpreg_mask
;
18527 unsigned long fpreg_offset
;
18528 unsigned long frame_offset
;
18529 unsigned long frame_reg
;
18530 unsigned long pc_reg
;
18533 static procS cur_proc
;
18534 static procS
*cur_proc_ptr
;
18535 static int numprocs
;
18537 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18538 as "2", and a normal nop as "0". */
18540 #define NOP_OPCODE_MIPS 0
18541 #define NOP_OPCODE_MIPS16 1
18542 #define NOP_OPCODE_MICROMIPS 2
18545 mips_nop_opcode (void)
18547 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18548 return NOP_OPCODE_MICROMIPS
;
18549 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18550 return NOP_OPCODE_MIPS16
;
18552 return NOP_OPCODE_MIPS
;
18555 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18556 32-bit microMIPS NOPs here (if applicable). */
18559 mips_handle_align (fragS
*fragp
)
18563 int bytes
, size
, excess
;
18566 if (fragp
->fr_type
!= rs_align_code
)
18569 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18571 switch (nop_opcode
)
18573 case NOP_OPCODE_MICROMIPS
:
18574 opcode
= micromips_nop32_insn
.insn_opcode
;
18577 case NOP_OPCODE_MIPS16
:
18578 opcode
= mips16_nop_insn
.insn_opcode
;
18581 case NOP_OPCODE_MIPS
:
18583 opcode
= nop_insn
.insn_opcode
;
18588 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18589 excess
= bytes
% size
;
18591 /* Handle the leading part if we're not inserting a whole number of
18592 instructions, and make it the end of the fixed part of the frag.
18593 Try to fit in a short microMIPS NOP if applicable and possible,
18594 and use zeroes otherwise. */
18595 gas_assert (excess
< 4);
18596 fragp
->fr_fix
+= excess
;
18601 /* Fall through. */
18603 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18605 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18609 /* Fall through. */
18612 /* Fall through. */
18617 md_number_to_chars (p
, opcode
, size
);
18618 fragp
->fr_var
= size
;
18622 md_obj_begin (void)
18629 /* Check for premature end, nesting errors, etc. */
18631 as_warn (_("missing .end at end of assembly"));
18640 if (*input_line_pointer
== '-')
18642 ++input_line_pointer
;
18645 if (!ISDIGIT (*input_line_pointer
))
18646 as_bad (_("expected simple number"));
18647 if (input_line_pointer
[0] == '0')
18649 if (input_line_pointer
[1] == 'x')
18651 input_line_pointer
+= 2;
18652 while (ISXDIGIT (*input_line_pointer
))
18655 val
|= hex_value (*input_line_pointer
++);
18657 return negative
? -val
: val
;
18661 ++input_line_pointer
;
18662 while (ISDIGIT (*input_line_pointer
))
18665 val
|= *input_line_pointer
++ - '0';
18667 return negative
? -val
: val
;
18670 if (!ISDIGIT (*input_line_pointer
))
18672 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18673 *input_line_pointer
, *input_line_pointer
);
18674 as_warn (_("invalid number"));
18677 while (ISDIGIT (*input_line_pointer
))
18680 val
+= *input_line_pointer
++ - '0';
18682 return negative
? -val
: val
;
18685 /* The .file directive; just like the usual .file directive, but there
18686 is an initial number which is the ECOFF file index. In the non-ECOFF
18687 case .file implies DWARF-2. */
18690 s_mips_file (int x ATTRIBUTE_UNUSED
)
18692 static int first_file_directive
= 0;
18694 if (ECOFF_DEBUGGING
)
18703 filename
= dwarf2_directive_file (0);
18705 /* Versions of GCC up to 3.1 start files with a ".file"
18706 directive even for stabs output. Make sure that this
18707 ".file" is handled. Note that you need a version of GCC
18708 after 3.1 in order to support DWARF-2 on MIPS. */
18709 if (filename
!= NULL
&& ! first_file_directive
)
18711 (void) new_logical_line (filename
, -1);
18712 s_app_file_string (filename
, 0);
18714 first_file_directive
= 1;
18718 /* The .loc directive, implying DWARF-2. */
18721 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18723 if (!ECOFF_DEBUGGING
)
18724 dwarf2_directive_loc (0);
18727 /* The .end directive. */
18730 s_mips_end (int x ATTRIBUTE_UNUSED
)
18734 /* Following functions need their own .frame and .cprestore directives. */
18735 mips_frame_reg_valid
= 0;
18736 mips_cprestore_valid
= 0;
18738 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18741 demand_empty_rest_of_line ();
18746 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18747 as_warn (_(".end not in text section"));
18751 as_warn (_(".end directive without a preceding .ent directive."));
18752 demand_empty_rest_of_line ();
18758 gas_assert (S_GET_NAME (p
));
18759 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18760 as_warn (_(".end symbol does not match .ent symbol."));
18762 if (debug_type
== DEBUG_STABS
)
18763 stabs_generate_asm_endfunc (S_GET_NAME (p
),
18767 as_warn (_(".end directive missing or unknown symbol"));
18770 /* Create an expression to calculate the size of the function. */
18771 if (p
&& cur_proc_ptr
)
18773 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
18774 expressionS
*exp
= xmalloc (sizeof (expressionS
));
18777 exp
->X_op
= O_subtract
;
18778 exp
->X_add_symbol
= symbol_temp_new_now ();
18779 exp
->X_op_symbol
= p
;
18780 exp
->X_add_number
= 0;
18782 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
18785 /* Generate a .pdr section. */
18786 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
18788 segT saved_seg
= now_seg
;
18789 subsegT saved_subseg
= now_subseg
;
18793 #ifdef md_flush_pending_output
18794 md_flush_pending_output ();
18797 gas_assert (pdr_seg
);
18798 subseg_set (pdr_seg
, 0);
18800 /* Write the symbol. */
18801 exp
.X_op
= O_symbol
;
18802 exp
.X_add_symbol
= p
;
18803 exp
.X_add_number
= 0;
18804 emit_expr (&exp
, 4);
18806 fragp
= frag_more (7 * 4);
18808 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
18809 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
18810 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
18811 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
18812 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
18813 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
18814 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
18816 subseg_set (saved_seg
, saved_subseg
);
18818 #endif /* OBJ_ELF */
18820 cur_proc_ptr
= NULL
;
18823 /* The .aent and .ent directives. */
18826 s_mips_ent (int aent
)
18830 symbolP
= get_symbol ();
18831 if (*input_line_pointer
== ',')
18832 ++input_line_pointer
;
18833 SKIP_WHITESPACE ();
18834 if (ISDIGIT (*input_line_pointer
)
18835 || *input_line_pointer
== '-')
18838 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18839 as_warn (_(".ent or .aent not in text section."));
18841 if (!aent
&& cur_proc_ptr
)
18842 as_warn (_("missing .end"));
18846 /* This function needs its own .frame and .cprestore directives. */
18847 mips_frame_reg_valid
= 0;
18848 mips_cprestore_valid
= 0;
18850 cur_proc_ptr
= &cur_proc
;
18851 memset (cur_proc_ptr
, '\0', sizeof (procS
));
18853 cur_proc_ptr
->func_sym
= symbolP
;
18857 if (debug_type
== DEBUG_STABS
)
18858 stabs_generate_asm_func (S_GET_NAME (symbolP
),
18859 S_GET_NAME (symbolP
));
18862 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
18864 demand_empty_rest_of_line ();
18867 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18868 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18869 s_mips_frame is used so that we can set the PDR information correctly.
18870 We can't use the ecoff routines because they make reference to the ecoff
18871 symbol table (in the mdebug section). */
18874 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
18877 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18881 if (cur_proc_ptr
== (procS
*) NULL
)
18883 as_warn (_(".frame outside of .ent"));
18884 demand_empty_rest_of_line ();
18888 cur_proc_ptr
->frame_reg
= tc_get_register (1);
18890 SKIP_WHITESPACE ();
18891 if (*input_line_pointer
++ != ','
18892 || get_absolute_expression_and_terminator (&val
) != ',')
18894 as_warn (_("Bad .frame directive"));
18895 --input_line_pointer
;
18896 demand_empty_rest_of_line ();
18900 cur_proc_ptr
->frame_offset
= val
;
18901 cur_proc_ptr
->pc_reg
= tc_get_register (0);
18903 demand_empty_rest_of_line ();
18906 #endif /* OBJ_ELF */
18910 /* The .fmask and .mask directives. If the mdebug section is present
18911 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18912 embedded targets, s_mips_mask is used so that we can set the PDR
18913 information correctly. We can't use the ecoff routines because they
18914 make reference to the ecoff symbol table (in the mdebug section). */
18917 s_mips_mask (int reg_type
)
18920 if (IS_ELF
&& !ECOFF_DEBUGGING
)
18924 if (cur_proc_ptr
== (procS
*) NULL
)
18926 as_warn (_(".mask/.fmask outside of .ent"));
18927 demand_empty_rest_of_line ();
18931 if (get_absolute_expression_and_terminator (&mask
) != ',')
18933 as_warn (_("Bad .mask/.fmask directive"));
18934 --input_line_pointer
;
18935 demand_empty_rest_of_line ();
18939 off
= get_absolute_expression ();
18941 if (reg_type
== 'F')
18943 cur_proc_ptr
->fpreg_mask
= mask
;
18944 cur_proc_ptr
->fpreg_offset
= off
;
18948 cur_proc_ptr
->reg_mask
= mask
;
18949 cur_proc_ptr
->reg_offset
= off
;
18952 demand_empty_rest_of_line ();
18955 #endif /* OBJ_ELF */
18956 s_ignore (reg_type
);
18959 /* A table describing all the processors gas knows about. Names are
18960 matched in the order listed.
18962 To ease comparison, please keep this table in the same order as
18963 gcc's mips_cpu_info_table[]. */
18964 static const struct mips_cpu_info mips_cpu_info_table
[] =
18966 /* Entries for generic ISAs */
18967 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
18968 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
18969 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
18970 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
18971 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
18972 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
18973 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
18974 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
18975 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
18978 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
18979 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
18980 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
18983 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
18986 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
18987 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
18988 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
18989 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
18990 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
18991 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
18992 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
18993 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
18994 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
18995 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
18996 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
18997 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
18998 /* ST Microelectronics Loongson 2E and 2F cores */
18999 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19000 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19003 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19004 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19005 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19006 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19007 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19008 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19009 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19010 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19011 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19012 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19013 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19014 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19015 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19016 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19017 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19020 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19021 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19022 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19023 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19025 /* MIPS 32 Release 2 */
19026 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19027 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19028 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19029 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19030 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19031 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19032 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19033 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19034 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19035 ISA_MIPS32R2
, CPU_MIPS32R2
},
19036 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19037 ISA_MIPS32R2
, CPU_MIPS32R2
},
19038 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19039 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19040 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19041 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19042 /* Deprecated forms of the above. */
19043 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19044 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19045 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19046 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19047 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19048 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19049 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19050 /* Deprecated forms of the above. */
19051 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19052 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19053 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19054 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19055 ISA_MIPS32R2
, CPU_MIPS32R2
},
19056 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19057 ISA_MIPS32R2
, CPU_MIPS32R2
},
19058 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19059 ISA_MIPS32R2
, CPU_MIPS32R2
},
19060 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19061 ISA_MIPS32R2
, CPU_MIPS32R2
},
19062 /* Deprecated forms of the above. */
19063 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19064 ISA_MIPS32R2
, CPU_MIPS32R2
},
19065 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19066 ISA_MIPS32R2
, CPU_MIPS32R2
},
19067 /* 34Kn is a 34kc without DSP. */
19068 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19069 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19070 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19071 ISA_MIPS32R2
, CPU_MIPS32R2
},
19072 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19073 ISA_MIPS32R2
, CPU_MIPS32R2
},
19074 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19075 ISA_MIPS32R2
, CPU_MIPS32R2
},
19076 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19077 ISA_MIPS32R2
, CPU_MIPS32R2
},
19078 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19079 ISA_MIPS32R2
, CPU_MIPS32R2
},
19080 /* Deprecated forms of the above. */
19081 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19082 ISA_MIPS32R2
, CPU_MIPS32R2
},
19083 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19084 ISA_MIPS32R2
, CPU_MIPS32R2
},
19085 /* 1004K cores are multiprocessor versions of the 34K. */
19086 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19087 ISA_MIPS32R2
, CPU_MIPS32R2
},
19088 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19089 ISA_MIPS32R2
, CPU_MIPS32R2
},
19090 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19091 ISA_MIPS32R2
, CPU_MIPS32R2
},
19092 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19093 ISA_MIPS32R2
, CPU_MIPS32R2
},
19096 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19097 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19098 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19099 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19101 /* Broadcom SB-1 CPU core */
19102 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19103 ISA_MIPS64
, CPU_SB1
},
19104 /* Broadcom SB-1A CPU core */
19105 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19106 ISA_MIPS64
, CPU_SB1
},
19108 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19110 /* MIPS 64 Release 2 */
19112 /* Cavium Networks Octeon CPU core */
19113 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19114 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19115 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19118 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19121 XLP is mostly like XLR, with the prominent exception that it is
19122 MIPS64R2 rather than MIPS64. */
19123 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19130 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19131 with a final "000" replaced by "k". Ignore case.
19133 Note: this function is shared between GCC and GAS. */
19136 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19138 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19139 given
++, canonical
++;
19141 return ((*given
== 0 && *canonical
== 0)
19142 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19146 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19147 CPU name. We've traditionally allowed a lot of variation here.
19149 Note: this function is shared between GCC and GAS. */
19152 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19154 /* First see if the name matches exactly, or with a final "000"
19155 turned into "k". */
19156 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19159 /* If not, try comparing based on numerical designation alone.
19160 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19161 if (TOLOWER (*given
) == 'r')
19163 if (!ISDIGIT (*given
))
19166 /* Skip over some well-known prefixes in the canonical name,
19167 hoping to find a number there too. */
19168 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19170 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19172 else if (TOLOWER (canonical
[0]) == 'r')
19175 return mips_strict_matching_cpu_name_p (canonical
, given
);
19179 /* Parse an option that takes the name of a processor as its argument.
19180 OPTION is the name of the option and CPU_STRING is the argument.
19181 Return the corresponding processor enumeration if the CPU_STRING is
19182 recognized, otherwise report an error and return null.
19184 A similar function exists in GCC. */
19186 static const struct mips_cpu_info
*
19187 mips_parse_cpu (const char *option
, const char *cpu_string
)
19189 const struct mips_cpu_info
*p
;
19191 /* 'from-abi' selects the most compatible architecture for the given
19192 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19193 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19194 version. Look first at the -mgp options, if given, otherwise base
19195 the choice on MIPS_DEFAULT_64BIT.
19197 Treat NO_ABI like the EABIs. One reason to do this is that the
19198 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19199 architecture. This code picks MIPS I for 'mips' and MIPS III for
19200 'mips64', just as we did in the days before 'from-abi'. */
19201 if (strcasecmp (cpu_string
, "from-abi") == 0)
19203 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19204 return mips_cpu_info_from_isa (ISA_MIPS1
);
19206 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19207 return mips_cpu_info_from_isa (ISA_MIPS3
);
19209 if (file_mips_gp32
>= 0)
19210 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19212 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19217 /* 'default' has traditionally been a no-op. Probably not very useful. */
19218 if (strcasecmp (cpu_string
, "default") == 0)
19221 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19222 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19225 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19229 /* Return the canonical processor information for ISA (a member of the
19230 ISA_MIPS* enumeration). */
19232 static const struct mips_cpu_info
*
19233 mips_cpu_info_from_isa (int isa
)
19237 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19238 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19239 && isa
== mips_cpu_info_table
[i
].isa
)
19240 return (&mips_cpu_info_table
[i
]);
19245 static const struct mips_cpu_info
*
19246 mips_cpu_info_from_arch (int arch
)
19250 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19251 if (arch
== mips_cpu_info_table
[i
].cpu
)
19252 return (&mips_cpu_info_table
[i
]);
19258 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19262 fprintf (stream
, "%24s", "");
19267 fprintf (stream
, ", ");
19271 if (*col_p
+ strlen (string
) > 72)
19273 fprintf (stream
, "\n%24s", "");
19277 fprintf (stream
, "%s", string
);
19278 *col_p
+= strlen (string
);
19284 md_show_usage (FILE *stream
)
19289 fprintf (stream
, _("\
19291 -EB generate big endian output\n\
19292 -EL generate little endian output\n\
19293 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19294 -G NUM allow referencing objects up to NUM bytes\n\
19295 implicitly with the gp register [default 8]\n"));
19296 fprintf (stream
, _("\
19297 -mips1 generate MIPS ISA I instructions\n\
19298 -mips2 generate MIPS ISA II instructions\n\
19299 -mips3 generate MIPS ISA III instructions\n\
19300 -mips4 generate MIPS ISA IV instructions\n\
19301 -mips5 generate MIPS ISA V instructions\n\
19302 -mips32 generate MIPS32 ISA instructions\n\
19303 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19304 -mips64 generate MIPS64 ISA instructions\n\
19305 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19306 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19310 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19311 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19312 show (stream
, "from-abi", &column
, &first
);
19313 fputc ('\n', stream
);
19315 fprintf (stream
, _("\
19316 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19317 -no-mCPU don't generate code specific to CPU.\n\
19318 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19322 show (stream
, "3900", &column
, &first
);
19323 show (stream
, "4010", &column
, &first
);
19324 show (stream
, "4100", &column
, &first
);
19325 show (stream
, "4650", &column
, &first
);
19326 fputc ('\n', stream
);
19328 fprintf (stream
, _("\
19329 -mips16 generate mips16 instructions\n\
19330 -no-mips16 do not generate mips16 instructions\n"));
19331 fprintf (stream
, _("\
19332 -mmicromips generate microMIPS instructions\n\
19333 -mno-micromips do not generate microMIPS instructions\n"));
19334 fprintf (stream
, _("\
19335 -msmartmips generate smartmips instructions\n\
19336 -mno-smartmips do not generate smartmips instructions\n"));
19337 fprintf (stream
, _("\
19338 -mdsp generate DSP instructions\n\
19339 -mno-dsp do not generate DSP instructions\n"));
19340 fprintf (stream
, _("\
19341 -mdspr2 generate DSP R2 instructions\n\
19342 -mno-dspr2 do not generate DSP R2 instructions\n"));
19343 fprintf (stream
, _("\
19344 -mmt generate MT instructions\n\
19345 -mno-mt do not generate MT instructions\n"));
19346 fprintf (stream
, _("\
19347 -mmcu generate MCU instructions\n\
19348 -mno-mcu do not generate MCU instructions\n"));
19349 fprintf (stream
, _("\
19350 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19351 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19352 -mfix-vr4120 work around certain VR4120 errata\n\
19353 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19354 -mfix-24k insert a nop after ERET and DERET instructions\n\
19355 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19356 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19357 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19358 -msym32 assume all symbols have 32-bit values\n\
19359 -O0 remove unneeded NOPs, do not swap branches\n\
19360 -O remove unneeded NOPs and swap branches\n\
19361 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19362 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19363 fprintf (stream
, _("\
19364 -mhard-float allow floating-point instructions\n\
19365 -msoft-float do not allow floating-point instructions\n\
19366 -msingle-float only allow 32-bit floating-point operations\n\
19367 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19368 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19371 fprintf (stream
, _("\
19372 -KPIC, -call_shared generate SVR4 position independent code\n\
19373 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19374 -mvxworks-pic generate VxWorks position independent code\n\
19375 -non_shared do not generate code that can operate with DSOs\n\
19376 -xgot assume a 32 bit GOT\n\
19377 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19378 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19379 position dependent (non shared) code\n\
19380 -mabi=ABI create ABI conformant object file for:\n"));
19384 show (stream
, "32", &column
, &first
);
19385 show (stream
, "o64", &column
, &first
);
19386 show (stream
, "n32", &column
, &first
);
19387 show (stream
, "64", &column
, &first
);
19388 show (stream
, "eabi", &column
, &first
);
19390 fputc ('\n', stream
);
19392 fprintf (stream
, _("\
19393 -32 create o32 ABI object file (default)\n\
19394 -n32 create n32 ABI object file\n\
19395 -64 create 64 ABI object file\n"));
19401 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19403 if (HAVE_64BIT_SYMBOLS
)
19404 return dwarf2_format_64bit_irix
;
19406 return dwarf2_format_32bit
;
19411 mips_dwarf2_addr_size (void)
19413 if (HAVE_64BIT_OBJECTS
)
19419 /* Standard calling conventions leave the CFA at SP on entry. */
19421 mips_cfi_frame_initial_instructions (void)
19423 cfi_add_CFA_def_cfa_register (SP
);
19427 tc_mips_regname_to_dw2regnum (char *regname
)
19429 unsigned int regnum
= -1;
19432 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))