1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF. */
109 /* The default target format to use. */
111 mips_target_format ()
113 switch (OUTPUT_FLAVOR
)
115 case bfd_target_aout_flavour
:
116 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
117 case bfd_target_ecoff_flavour
:
118 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
119 case bfd_target_elf_flavour
:
120 return (target_big_endian
121 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
122 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
128 /* The name of the readonly data section. */
129 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
131 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
133 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
137 /* This is the set of options which may be modified by the .set
138 pseudo-op. We use a struct so that .set push and .set pop are more
141 struct mips_set_options
143 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
144 if it has not been initialized. Changed by `.set mipsN', and the
145 -mipsN command line option, and the default CPU. */
147 /* Whether we are assembling for the mips16 processor. 0 if we are
148 not, 1 if we are, and -1 if the value has not been initialized.
149 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
150 -nomips16 command line options, and the default CPU. */
152 /* Non-zero if we should not reorder instructions. Changed by `.set
153 reorder' and `.set noreorder'. */
155 /* Non-zero if we should not permit the $at ($1) register to be used
156 in instructions. Changed by `.set at' and `.set noat'. */
158 /* Non-zero if we should warn when a macro instruction expands into
159 more than one machine instruction. Changed by `.set nomacro' and
161 int warn_about_macros
;
162 /* Non-zero if we should not move instructions. Changed by `.set
163 move', `.set volatile', `.set nomove', and `.set novolatile'. */
165 /* Non-zero if we should not optimize branches by moving the target
166 of the branch into the delay slot. Actually, we don't perform
167 this optimization anyhow. Changed by `.set bopt' and `.set
170 /* Non-zero if we should not autoextend mips16 instructions.
171 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* This is the struct we use to hold the current set of options. Note
176 that we must set the isa and mips16 fields to -1 to indicate that
177 they have not been initialized. */
179 static struct mips_set_options mips_opts
= { -1, -1 };
181 /* These variables are filled in with the masks of registers used.
182 The object format code reads them and puts them in the appropriate
184 unsigned long mips_gprmask
;
185 unsigned long mips_cprmask
[4];
187 /* MIPS ISA we are using for this output file. */
188 static int file_mips_isa
;
190 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
191 static int mips_cpu
= -1;
193 /* Whether the 4650 instructions (mad/madu) are permitted. */
194 static int mips_4650
= -1;
196 /* Whether the 4010 instructions are permitted. */
197 static int mips_4010
= -1;
199 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
200 static int mips_4100
= -1;
202 /* start-sanitize-r5900 */
203 /* Whether Toshiba r5900 instructions are permitted. */
204 static int mips_5900
= -1;
205 /* end-sanitize-r5900 */
207 /* Whether Toshiba r3900 instructions are permitted. */
208 static int mips_3900
= -1;
210 /* Whether the processor uses hardware interlocks to protect
211 reads from the HI and LO registers, and thus does not
212 require nops to be inserted. */
213 static int hilo_interlocks
= -1;
215 /* Whether the processor uses hardware interlocks to protect
216 reads from the GPRs, and thus does not
217 require nops to be inserted. */
218 static int gpr_interlocks
= -1;
220 /* As with other "interlocks" this is used by hardware that has FP
221 (co-processor) interlocks. */
222 /* Itbl support may require additional care here. */
223 static int cop_interlocks
= -1;
225 /* MIPS PIC level. */
229 /* Do not generate PIC code. */
232 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
233 not sure what it is supposed to do. */
236 /* Generate PIC code as in the SVR4 MIPS ABI. */
239 /* Generate PIC code without using a global offset table: the data
240 segment has a maximum size of 64K, all data references are off
241 the $gp register, and all text references are PC relative. This
242 is used on some embedded systems. */
246 static enum mips_pic_level mips_pic
;
248 /* 1 if we should generate 32 bit offsets from the GP register in
249 SVR4_PIC mode. Currently has no meaning in other modes. */
250 static int mips_big_got
;
252 /* 1 if trap instructions should used for overflow rather than break
254 static int mips_trap
;
256 /* Non-zero if any .set noreorder directives were used. */
258 static int mips_any_noreorder
;
260 /* The size of the small data section. */
261 static int g_switch_value
= 8;
262 /* Whether the -G option was used. */
263 static int g_switch_seen
= 0;
268 /* If we can determine in advance that GP optimization won't be
269 possible, we can skip the relaxation stuff that tries to produce
270 GP-relative references. This makes delay slot optimization work
273 This function can only provide a guess, but it seems to work for
274 gcc output. If it guesses wrong, the only loss should be in
275 efficiency; it shouldn't introduce any bugs.
277 I don't know if a fix is needed for the SVR4_PIC mode. I've only
278 fixed it for the non-PIC mode. KR 95/04/07 */
279 static int nopic_need_relax
PARAMS ((symbolS
*, int));
281 /* handle of the OPCODE hash table */
282 static struct hash_control
*op_hash
= NULL
;
284 /* The opcode hash table we use for the mips16. */
285 static struct hash_control
*mips16_op_hash
= NULL
;
287 /* This array holds the chars that always start a comment. If the
288 pre-processor is disabled, these aren't very useful */
289 const char comment_chars
[] = "#";
291 /* This array holds the chars that only start a comment at the beginning of
292 a line. If the line seems to have the form '# 123 filename'
293 .line and .file directives will appear in the pre-processed output */
294 /* Note that input_file.c hand checks for '#' at the beginning of the
295 first line of the input file. This is because the compiler outputs
296 #NO_APP at the beginning of its output. */
297 /* Also note that C style comments are always supported. */
298 const char line_comment_chars
[] = "#";
300 /* This array holds machine specific line separator characters. */
301 const char line_separator_chars
[] = "";
303 /* Chars that can be used to separate mant from exp in floating point nums */
304 const char EXP_CHARS
[] = "eE";
306 /* Chars that mean this number is a floating point constant */
309 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
311 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
312 changed in read.c . Ideally it shouldn't have to know about it at all,
313 but nothing is ideal around here.
316 static char *insn_error
;
318 static int auto_align
= 1;
320 /* When outputting SVR4 PIC code, the assembler needs to know the
321 offset in the stack frame from which to restore the $gp register.
322 This is set by the .cprestore pseudo-op, and saved in this
324 static offsetT mips_cprestore_offset
= -1;
326 /* This is the register which holds the stack frame, as set by the
327 .frame pseudo-op. This is needed to implement .cprestore. */
328 static int mips_frame_reg
= SP
;
330 /* To output NOP instructions correctly, we need to keep information
331 about the previous two instructions. */
333 /* Whether we are optimizing. The default value of 2 means to remove
334 unneeded NOPs and swap branch instructions when possible. A value
335 of 1 means to not swap branches. A value of 0 means to always
337 static int mips_optimize
= 2;
339 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
340 equivalent to seeing no -g option at all. */
341 static int mips_debug
= 0;
343 /* The previous instruction. */
344 static struct mips_cl_insn prev_insn
;
346 /* The instruction before prev_insn. */
347 static struct mips_cl_insn prev_prev_insn
;
349 /* If we don't want information for prev_insn or prev_prev_insn, we
350 point the insn_mo field at this dummy integer. */
351 static const struct mips_opcode dummy_opcode
= { 0 };
353 /* Non-zero if prev_insn is valid. */
354 static int prev_insn_valid
;
356 /* The frag for the previous instruction. */
357 static struct frag
*prev_insn_frag
;
359 /* The offset into prev_insn_frag for the previous instruction. */
360 static long prev_insn_where
;
362 /* The reloc type for the previous instruction, if any. */
363 static bfd_reloc_code_real_type prev_insn_reloc_type
;
365 /* The reloc for the previous instruction, if any. */
366 static fixS
*prev_insn_fixp
;
368 /* Non-zero if the previous instruction was in a delay slot. */
369 static int prev_insn_is_delay_slot
;
371 /* Non-zero if the previous instruction was in a .set noreorder. */
372 static int prev_insn_unreordered
;
374 /* Non-zero if the previous instruction uses an extend opcode (if
376 static int prev_insn_extended
;
378 /* Non-zero if the previous previous instruction was in a .set
380 static int prev_prev_insn_unreordered
;
382 /* If this is set, it points to a frag holding nop instructions which
383 were inserted before the start of a noreorder section. If those
384 nops turn out to be unnecessary, the size of the frag can be
386 static fragS
*prev_nop_frag
;
388 /* The number of nop instructions we created in prev_nop_frag. */
389 static int prev_nop_frag_holds
;
391 /* The number of nop instructions that we know we need in
393 static int prev_nop_frag_required
;
395 /* The number of instructions we've seen since prev_nop_frag. */
396 static int prev_nop_frag_since
;
398 /* For ECOFF and ELF, relocations against symbols are done in two
399 parts, with a HI relocation and a LO relocation. Each relocation
400 has only 16 bits of space to store an addend. This means that in
401 order for the linker to handle carries correctly, it must be able
402 to locate both the HI and the LO relocation. This means that the
403 relocations must appear in order in the relocation table.
405 In order to implement this, we keep track of each unmatched HI
406 relocation. We then sort them so that they immediately precede the
407 corresponding LO relocation. */
412 struct mips_hi_fixup
*next
;
415 /* The section this fixup is in. */
419 /* The list of unmatched HI relocs. */
421 static struct mips_hi_fixup
*mips_hi_fixup_list
;
423 /* Map normal MIPS register numbers to mips16 register numbers. */
425 #define X ILLEGAL_REG
426 static const int mips32_to_16_reg_map
[] =
428 X
, X
, 2, 3, 4, 5, 6, 7,
429 X
, X
, X
, X
, X
, X
, X
, X
,
430 0, 1, X
, X
, X
, X
, X
, X
,
431 X
, X
, X
, X
, X
, X
, X
, X
435 /* Map mips16 register numbers to normal MIPS register numbers. */
437 static const int mips16_to_32_reg_map
[] =
439 16, 17, 2, 3, 4, 5, 6, 7
442 /* Since the MIPS does not have multiple forms of PC relative
443 instructions, we do not have to do relaxing as is done on other
444 platforms. However, we do have to handle GP relative addressing
445 correctly, which turns out to be a similar problem.
447 Every macro that refers to a symbol can occur in (at least) two
448 forms, one with GP relative addressing and one without. For
449 example, loading a global variable into a register generally uses
450 a macro instruction like this:
452 If i can be addressed off the GP register (this is true if it is in
453 the .sbss or .sdata section, or if it is known to be smaller than
454 the -G argument) this will generate the following instruction:
456 This instruction will use a GPREL reloc. If i can not be addressed
457 off the GP register, the following instruction sequence will be used:
460 In this case the first instruction will have a HI16 reloc, and the
461 second reloc will have a LO16 reloc. Both relocs will be against
464 The issue here is that we may not know whether i is GP addressable
465 until after we see the instruction that uses it. Therefore, we
466 want to be able to choose the final instruction sequence only at
467 the end of the assembly. This is similar to the way other
468 platforms choose the size of a PC relative instruction only at the
471 When generating position independent code we do not use GP
472 addressing in quite the same way, but the issue still arises as
473 external symbols and local symbols must be handled differently.
475 We handle these issues by actually generating both possible
476 instruction sequences. The longer one is put in a frag_var with
477 type rs_machine_dependent. We encode what to do with the frag in
478 the subtype field. We encode (1) the number of existing bytes to
479 replace, (2) the number of new bytes to use, (3) the offset from
480 the start of the existing bytes to the first reloc we must generate
481 (that is, the offset is applied from the start of the existing
482 bytes after they are replaced by the new bytes, if any), (4) the
483 offset from the start of the existing bytes to the second reloc,
484 (5) whether a third reloc is needed (the third reloc is always four
485 bytes after the second reloc), and (6) whether to warn if this
486 variant is used (this is sometimes needed if .set nomacro or .set
487 noat is in effect). All these numbers are reasonably small.
489 Generating two instruction sequences must be handled carefully to
490 ensure that delay slots are handled correctly. Fortunately, there
491 are a limited number of cases. When the second instruction
492 sequence is generated, append_insn is directed to maintain the
493 existing delay slot information, so it continues to apply to any
494 code after the second instruction sequence. This means that the
495 second instruction sequence must not impose any requirements not
496 required by the first instruction sequence.
498 These variant frags are then handled in functions called by the
499 machine independent code. md_estimate_size_before_relax returns
500 the final size of the frag. md_convert_frag sets up the final form
501 of the frag. tc_gen_reloc adjust the first reloc and adds a second
503 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
507 | (((reloc1) + 64) << 9) \
508 | (((reloc2) + 64) << 2) \
509 | ((reloc3) ? (1 << 1) : 0) \
511 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
512 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
513 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
514 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
515 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
516 #define RELAX_WARN(i) ((i) & 1)
518 /* For mips16 code, we use an entirely different form of relaxation.
519 mips16 supports two versions of most instructions which take
520 immediate values: a small one which takes some small value, and a
521 larger one which takes a 16 bit value. Since branches also follow
522 this pattern, relaxing these values is required.
524 We can assemble both mips16 and normal MIPS code in a single
525 object. Therefore, we need to support this type of relaxation at
526 the same time that we support the relaxation described above. We
527 use the high bit of the subtype field to distinguish these cases.
529 The information we store for this type of relaxation is the
530 argument code found in the opcode file for this relocation, whether
531 the user explicitly requested a small or extended form, and whether
532 the relocation is in a jump or jal delay slot. That tells us the
533 size of the value, and how it should be stored. We also store
534 whether the fragment is considered to be extended or not. We also
535 store whether this is known to be a branch to a different section,
536 whether we have tried to relax this frag yet, and whether we have
537 ever extended a PC relative fragment because of a shift count. */
538 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
541 | ((small) ? 0x100 : 0) \
542 | ((ext) ? 0x200 : 0) \
543 | ((dslot) ? 0x400 : 0) \
544 | ((jal_dslot) ? 0x800 : 0))
545 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
546 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
547 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
548 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
549 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
550 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
551 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
552 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
553 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
554 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
555 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
556 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
558 /* Prototypes for static functions. */
561 #define internalError() \
562 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
564 #define internalError() as_fatal ("MIPS internal Error");
567 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
569 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
570 unsigned int reg
, enum mips_regclass
class));
571 static int reg_needs_delay
PARAMS ((int));
572 static void mips16_mark_labels
PARAMS ((void));
573 static void append_insn
PARAMS ((char *place
,
574 struct mips_cl_insn
* ip
,
576 bfd_reloc_code_real_type r
,
578 static void mips_no_prev_insn
PARAMS ((int));
579 static void mips_emit_delays
PARAMS ((boolean
));
581 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
582 const char *name
, const char *fmt
,
585 static void macro_build ();
587 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
588 const char *, const char *,
590 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
591 expressionS
* ep
, int regnum
));
592 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
593 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
595 static void load_register
PARAMS ((int *, int, expressionS
*, int));
596 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
597 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
598 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
599 #ifdef LOSING_COMPILER
600 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
602 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
603 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
604 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
605 boolean
, boolean
, unsigned long *,
606 boolean
*, unsigned short *));
607 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
608 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
609 static symbolS
*get_symbol
PARAMS ((void));
610 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
611 static void s_align
PARAMS ((int));
612 static void s_change_sec
PARAMS ((int));
613 static void s_cons
PARAMS ((int));
614 static void s_float_cons
PARAMS ((int));
615 static void s_mips_globl
PARAMS ((int));
616 static void s_option
PARAMS ((int));
617 static void s_mipsset
PARAMS ((int));
618 static void s_abicalls
PARAMS ((int));
619 static void s_cpload
PARAMS ((int));
620 static void s_cprestore
PARAMS ((int));
621 static void s_gpword
PARAMS ((int));
622 static void s_cpadd
PARAMS ((int));
623 static void s_insn
PARAMS ((int));
624 static void md_obj_begin
PARAMS ((void));
625 static void md_obj_end
PARAMS ((void));
626 static long get_number
PARAMS ((void));
627 static void s_ent
PARAMS ((int));
628 static void s_mipsend
PARAMS ((int));
629 static void s_file
PARAMS ((int));
630 static void s_mips_stab
PARAMS ((int));
631 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
635 The following pseudo-ops from the Kane and Heinrich MIPS book
636 should be defined here, but are currently unsupported: .alias,
637 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
639 The following pseudo-ops from the Kane and Heinrich MIPS book are
640 specific to the type of debugging information being generated, and
641 should be defined by the object format: .aent, .begin, .bend,
642 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
645 The following pseudo-ops from the Kane and Heinrich MIPS book are
646 not MIPS CPU specific, but are also not specific to the object file
647 format. This file is probably the best place to define them, but
648 they are not currently supported: .asm0, .endr, .lab, .repeat,
649 .struct, .weakext. */
651 static const pseudo_typeS mips_pseudo_table
[] =
653 /* MIPS specific pseudo-ops. */
654 {"option", s_option
, 0},
655 {"set", s_mipsset
, 0},
656 {"rdata", s_change_sec
, 'r'},
657 {"sdata", s_change_sec
, 's'},
658 {"livereg", s_ignore
, 0},
659 {"abicalls", s_abicalls
, 0},
660 {"cpload", s_cpload
, 0},
661 {"cprestore", s_cprestore
, 0},
662 {"gpword", s_gpword
, 0},
663 {"cpadd", s_cpadd
, 0},
666 /* Relatively generic pseudo-ops that happen to be used on MIPS
668 {"asciiz", stringer
, 1},
669 {"bss", s_change_sec
, 'b'},
672 {"dword", s_cons
, 3},
674 /* These pseudo-ops are defined in read.c, but must be overridden
675 here for one reason or another. */
676 {"align", s_align
, 0},
678 {"data", s_change_sec
, 'd'},
679 {"double", s_float_cons
, 'd'},
680 {"float", s_float_cons
, 'f'},
681 {"globl", s_mips_globl
, 0},
682 {"global", s_mips_globl
, 0},
683 {"hword", s_cons
, 1},
688 {"short", s_cons
, 1},
689 {"single", s_float_cons
, 'f'},
690 {"stabn", s_mips_stab
, 'n'},
691 {"text", s_change_sec
, 't'},
696 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
697 /* These pseudo-ops should be defined by the object file format.
698 However, a.out doesn't support them, so we have versions here. */
700 {"bgnb", s_ignore
, 0},
701 {"end", s_mipsend
, 0},
702 {"endb", s_ignore
, 0},
705 {"fmask", s_ignore
, 'F'},
706 {"frame", s_ignore
, 0},
707 {"loc", s_ignore
, 0},
708 {"mask", s_ignore
, 'R'},
709 {"verstamp", s_ignore
, 0},
713 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
718 pop_insert (mips_pseudo_table
);
719 if (! ECOFF_DEBUGGING
)
720 pop_insert (mips_nonecoff_pseudo_table
);
723 /* Symbols labelling the current insn. */
725 struct insn_label_list
727 struct insn_label_list
*next
;
731 static struct insn_label_list
*insn_labels
;
732 static struct insn_label_list
*free_insn_labels
;
734 static void mips_clear_insn_labels
PARAMS ((void));
737 mips_clear_insn_labels ()
739 register struct insn_label_list
**pl
;
741 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
747 static char *expr_end
;
749 /* Expressions which appear in instructions. These are set by
752 static expressionS imm_expr
;
753 static expressionS offset_expr
;
755 /* Relocs associated with imm_expr and offset_expr. */
757 static bfd_reloc_code_real_type imm_reloc
;
758 static bfd_reloc_code_real_type offset_reloc
;
760 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
762 static boolean imm_unmatched_hi
;
764 /* These are set by mips16_ip if an explicit extension is used. */
766 static boolean mips16_small
, mips16_ext
;
769 * This function is called once, at assembler startup time. It should
770 * set up all the tables, etc. that the MD part of the assembler will need.
776 register const char *retval
= NULL
;
777 register unsigned int i
= 0;
779 if (mips_opts
.isa
== -1)
785 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
787 a
= xmalloc (sizeof TARGET_CPU
);
788 strcpy (a
, TARGET_CPU
);
789 a
[(sizeof TARGET_CPU
) - 3] = '\0';
793 if (strcmp (cpu
, "mips") == 0)
799 else if (strcmp (cpu
, "r3900") == 0
800 || strcmp (cpu
, "mipsr3900") == 0)
808 else if (strcmp (cpu
, "r6000") == 0
809 || strcmp (cpu
, "mips2") == 0)
815 else if (strcmp (cpu
, "mips64") == 0
816 || strcmp (cpu
, "r4000") == 0
817 || strcmp (cpu
, "mips3") == 0)
823 else if (strcmp (cpu
, "r4400") == 0)
829 else if (strcmp (cpu
, "mips64orion") == 0
830 || strcmp (cpu
, "r4600") == 0)
836 else if (strcmp (cpu
, "r4650") == 0)
844 else if (strcmp (cpu
, "mips64vr4300") == 0)
850 else if (strcmp (cpu
, "mips64vr4100") == 0)
858 else if (strcmp (cpu
, "r4010") == 0)
866 else if (strcmp (cpu
, "r5000") == 0
867 || strcmp (cpu
, "mips64vr5000") == 0)
873 /* start-sanitize-r5900 */
874 else if (strcmp (cpu
, "r5900") == 0
875 || strcmp (cpu
, "mips64vr5900") == 0
876 || strcmp (cpu
, "mips64vr5900el") == 0)
884 /* end-sanitize-r5900 */
885 else if (strcmp (cpu
, "r8000") == 0
886 || strcmp (cpu
, "mips4") == 0)
892 else if (strcmp (cpu
, "r10000") == 0)
898 else if (strcmp (cpu
, "mips16") == 0)
902 mips_cpu
= 0; /* FIXME */
915 if (mips_opts
.mips16
< 0)
917 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
918 mips_opts
.mips16
= 1;
920 mips_opts
.mips16
= 0;
932 /* start-sanitize-r5900 */
935 /* end-sanitize-r5900 */
948 if (mips_opts
.isa
>= 2
955 /* Itbl support may require additional care here. */
956 if (mips_cpu
== 4300)
961 if (mips_opts
.isa
< 2 && mips_trap
)
962 as_bad ("trap exception not supported at ISA 1");
964 switch (mips_opts
.isa
)
967 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
970 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
973 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
976 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
980 as_warn ("Could not set architecture and machine");
982 file_mips_isa
= mips_opts
.isa
;
984 op_hash
= hash_new ();
986 for (i
= 0; i
< NUMOPCODES
;)
988 const char *name
= mips_opcodes
[i
].name
;
990 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
993 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
994 mips_opcodes
[i
].name
, retval
);
995 as_fatal ("Broken assembler. No assembly attempted.");
999 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1000 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
1001 != mips_opcodes
[i
].match
))
1003 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
1004 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
1005 as_fatal ("Broken assembler. No assembly attempted.");
1009 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1012 mips16_op_hash
= hash_new ();
1015 while (i
< bfd_mips16_num_opcodes
)
1017 const char *name
= mips16_opcodes
[i
].name
;
1019 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1021 as_fatal ("internal error: can't hash `%s': %s\n",
1022 mips16_opcodes
[i
].name
, retval
);
1025 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1026 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1027 != mips16_opcodes
[i
].match
))
1028 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
1029 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1032 while (i
< bfd_mips16_num_opcodes
1033 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1036 /* We add all the general register names to the symbol table. This
1037 helps us detect invalid uses of them. */
1038 for (i
= 0; i
< 32; i
++)
1042 sprintf (buf
, "$%d", i
);
1043 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1044 &zero_address_frag
));
1046 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1047 &zero_address_frag
));
1048 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1049 &zero_address_frag
));
1050 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1051 &zero_address_frag
));
1052 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1053 &zero_address_frag
));
1054 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1055 &zero_address_frag
));
1056 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1057 &zero_address_frag
));
1058 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1059 &zero_address_frag
));
1061 mips_no_prev_insn (false);
1064 mips_cprmask
[0] = 0;
1065 mips_cprmask
[1] = 0;
1066 mips_cprmask
[2] = 0;
1067 mips_cprmask
[3] = 0;
1069 /* set the default alignment for the text section (2**2) */
1070 record_alignment (text_section
, 2);
1072 if (USE_GLOBAL_POINTER_OPT
)
1073 bfd_set_gp_size (stdoutput
, g_switch_value
);
1075 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1077 /* On a native system, sections must be aligned to 16 byte
1078 boundaries. When configured for an embedded ELF target, we
1080 if (strcmp (TARGET_OS
, "elf") != 0)
1082 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1083 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1084 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1087 /* Create a .reginfo section for register masks and a .mdebug
1088 section for debugging information. */
1096 subseg
= now_subseg
;
1098 /* The ABI says this section should be loaded so that the
1099 running program can access it. However, we don't load it
1100 if we are configured for an embedded target */
1101 flags
= SEC_READONLY
| SEC_DATA
;
1102 if (strcmp (TARGET_OS
, "elf") != 0)
1103 flags
|= SEC_ALLOC
| SEC_LOAD
;
1107 sec
= subseg_new (".reginfo", (subsegT
) 0);
1110 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1111 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1114 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1119 /* The 64-bit ABI uses a .MIPS.options section rather than
1120 .reginfo section. */
1121 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1122 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1123 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1126 /* Set up the option header. */
1128 Elf_Internal_Options opthdr
;
1131 opthdr
.kind
= ODK_REGINFO
;
1132 opthdr
.size
= (sizeof (Elf_External_Options
)
1133 + sizeof (Elf64_External_RegInfo
));
1136 f
= frag_more (sizeof (Elf_External_Options
));
1137 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1138 (Elf_External_Options
*) f
);
1140 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1145 if (ECOFF_DEBUGGING
)
1147 sec
= subseg_new (".mdebug", (subsegT
) 0);
1148 (void) bfd_set_section_flags (stdoutput
, sec
,
1149 SEC_HAS_CONTENTS
| SEC_READONLY
);
1150 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1153 subseg_set (seg
, subseg
);
1157 if (! ECOFF_DEBUGGING
)
1164 if (! ECOFF_DEBUGGING
)
1172 struct mips_cl_insn insn
;
1174 imm_expr
.X_op
= O_absent
;
1175 imm_reloc
= BFD_RELOC_UNUSED
;
1176 imm_unmatched_hi
= false;
1177 offset_expr
.X_op
= O_absent
;
1178 offset_reloc
= BFD_RELOC_UNUSED
;
1180 if (mips_opts
.mips16
)
1181 mips16_ip (str
, &insn
);
1184 mips_ip (str
, &insn
);
1185 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1186 str
, insn
.insn_opcode
));
1191 as_bad ("%s `%s'", insn_error
, str
);
1195 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1197 if (mips_opts
.mips16
)
1198 mips16_macro (&insn
);
1204 if (imm_expr
.X_op
!= O_absent
)
1205 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1207 else if (offset_expr
.X_op
!= O_absent
)
1208 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1210 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1214 /* See whether instruction IP reads register REG. CLASS is the type
1218 insn_uses_reg (ip
, reg
, class)
1219 struct mips_cl_insn
*ip
;
1221 enum mips_regclass
class;
1223 if (class == MIPS16_REG
)
1225 assert (mips_opts
.mips16
);
1226 reg
= mips16_to_32_reg_map
[reg
];
1227 class = MIPS_GR_REG
;
1230 /* Don't report on general register 0, since it never changes. */
1231 if (class == MIPS_GR_REG
&& reg
== 0)
1234 if (class == MIPS_FP_REG
)
1236 assert (! mips_opts
.mips16
);
1237 /* If we are called with either $f0 or $f1, we must check $f0.
1238 This is not optimal, because it will introduce an unnecessary
1239 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1240 need to distinguish reading both $f0 and $f1 or just one of
1241 them. Note that we don't have to check the other way,
1242 because there is no instruction that sets both $f0 and $f1
1243 and requires a delay. */
1244 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1245 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1246 == (reg
&~ (unsigned) 1)))
1248 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1249 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1250 == (reg
&~ (unsigned) 1)))
1253 else if (! mips_opts
.mips16
)
1255 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1256 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1258 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1259 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1264 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1265 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1266 & MIPS16OP_MASK_RX
)]
1269 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1270 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1271 & MIPS16OP_MASK_RY
)]
1274 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1275 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1276 & MIPS16OP_MASK_MOVE32Z
)]
1279 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1281 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1283 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1285 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1286 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1287 & MIPS16OP_MASK_REGR32
) == reg
)
1294 /* This function returns true if modifying a register requires a
1298 reg_needs_delay (reg
)
1301 unsigned long prev_pinfo
;
1303 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1304 if (! mips_opts
.noreorder
1305 && mips_opts
.isa
< 4
1306 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1307 || (! gpr_interlocks
1308 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1310 /* A load from a coprocessor or from memory. All load
1311 delays delay the use of general register rt for one
1312 instruction on the r3000. The r6000 and r4000 use
1314 /* Itbl support may require additional care here. */
1315 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1316 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1323 /* Mark instruction labels in mips16 mode. This permits the linker to
1324 handle them specially, such as generating jalx instructions when
1325 needed. We also make them odd for the duration of the assembly, in
1326 order to generate the right sort of code. We will make them even
1327 in the adjust_symtab routine, while leaving them marked. This is
1328 convenient for the debugger and the disassembler. The linker knows
1329 to make them odd again. */
1332 mips16_mark_labels ()
1334 if (mips_opts
.mips16
)
1336 struct insn_label_list
*l
;
1338 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1341 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1342 S_SET_OTHER (l
->label
, STO_MIPS16
);
1344 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1345 ++l
->label
->sy_value
.X_add_number
;
1350 /* Output an instruction. PLACE is where to put the instruction; if
1351 it is NULL, this uses frag_more to get room. IP is the instruction
1352 information. ADDRESS_EXPR is an operand of the instruction to be
1353 used with RELOC_TYPE. */
1356 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1358 struct mips_cl_insn
*ip
;
1359 expressionS
*address_expr
;
1360 bfd_reloc_code_real_type reloc_type
;
1361 boolean unmatched_hi
;
1363 register unsigned long prev_pinfo
, pinfo
;
1368 /* Mark instruction labels in mips16 mode. */
1369 if (mips_opts
.mips16
)
1370 mips16_mark_labels ();
1372 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1373 pinfo
= ip
->insn_mo
->pinfo
;
1375 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1379 /* If the previous insn required any delay slots, see if we need
1380 to insert a NOP or two. There are eight kinds of possible
1381 hazards, of which an instruction can have at most one type.
1382 (1) a load from memory delay
1383 (2) a load from a coprocessor delay
1384 (3) an unconditional branch delay
1385 (4) a conditional branch delay
1386 (5) a move to coprocessor register delay
1387 (6) a load coprocessor register from memory delay
1388 (7) a coprocessor condition code delay
1389 (8) a HI/LO special register delay
1391 There are a lot of optimizations we could do that we don't.
1392 In particular, we do not, in general, reorder instructions.
1393 If you use gcc with optimization, it will reorder
1394 instructions and generally do much more optimization then we
1395 do here; repeating all that work in the assembler would only
1396 benefit hand written assembly code, and does not seem worth
1399 /* This is how a NOP is emitted. */
1400 #define emit_nop() \
1402 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1403 : md_number_to_chars (frag_more (4), 0, 4))
1405 /* The previous insn might require a delay slot, depending upon
1406 the contents of the current insn. */
1407 if (! mips_opts
.mips16
1408 && mips_opts
.isa
< 4
1409 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1410 && ! cop_interlocks
)
1411 || (! gpr_interlocks
1412 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1414 /* A load from a coprocessor or from memory. All load
1415 delays delay the use of general register rt for one
1416 instruction on the r3000. The r6000 and r4000 use
1418 /* Itbl support may require additional care here. */
1419 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1420 if (mips_optimize
== 0
1421 || insn_uses_reg (ip
,
1422 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1427 else if (! mips_opts
.mips16
1428 && mips_opts
.isa
< 4
1429 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1430 && ! cop_interlocks
)
1431 || (mips_opts
.isa
< 2
1432 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1434 /* A generic coprocessor delay. The previous instruction
1435 modified a coprocessor general or control register. If
1436 it modified a control register, we need to avoid any
1437 coprocessor instruction (this is probably not always
1438 required, but it sometimes is). If it modified a general
1439 register, we avoid using that register.
1441 On the r6000 and r4000 loading a coprocessor register
1442 from memory is interlocked, and does not require a delay.
1444 This case is not handled very well. There is no special
1445 knowledge of CP0 handling, and the coprocessors other
1446 than the floating point unit are not distinguished at
1448 /* Itbl support may require additional care here. FIXME!
1449 Need to modify this to include knowledge about
1450 user specified delays! */
1451 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1453 if (mips_optimize
== 0
1454 || insn_uses_reg (ip
,
1455 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1460 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1462 if (mips_optimize
== 0
1463 || insn_uses_reg (ip
,
1464 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1471 /* We don't know exactly what the previous instruction
1472 does. If the current instruction uses a coprocessor
1473 register, we must insert a NOP. If previous
1474 instruction may set the condition codes, and the
1475 current instruction uses them, we must insert two
1477 /* Itbl support may require additional care here. */
1478 if (mips_optimize
== 0
1479 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1480 && (pinfo
& INSN_READ_COND_CODE
)))
1482 else if (pinfo
& INSN_COP
)
1486 else if (! mips_opts
.mips16
1487 && mips_opts
.isa
< 4
1488 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1489 && ! cop_interlocks
)
1491 /* The previous instruction sets the coprocessor condition
1492 codes, but does not require a general coprocessor delay
1493 (this means it is a floating point comparison
1494 instruction). If this instruction uses the condition
1495 codes, we need to insert a single NOP. */
1496 /* Itbl support may require additional care here. */
1497 if (mips_optimize
== 0
1498 || (pinfo
& INSN_READ_COND_CODE
))
1501 else if (prev_pinfo
& INSN_READ_LO
)
1503 /* The previous instruction reads the LO register; if the
1504 current instruction writes to the LO register, we must
1505 insert two NOPS. Some newer processors have interlocks. */
1506 if (! hilo_interlocks
1507 && (mips_optimize
== 0
1508 || (pinfo
& INSN_WRITE_LO
)))
1511 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1513 /* The previous instruction reads the HI register; if the
1514 current instruction writes to the HI register, we must
1515 insert a NOP. Some newer processors have interlocks. */
1516 if (! hilo_interlocks
1517 && (mips_optimize
== 0
1518 || (pinfo
& INSN_WRITE_HI
)))
1522 /* If the previous instruction was in a noreorder section, then
1523 we don't want to insert the nop after all. */
1524 /* Itbl support may require additional care here. */
1525 if (prev_insn_unreordered
)
1528 /* There are two cases which require two intervening
1529 instructions: 1) setting the condition codes using a move to
1530 coprocessor instruction which requires a general coprocessor
1531 delay and then reading the condition codes 2) reading the HI
1532 or LO register and then writing to it (except on processors
1533 which have interlocks). If we are not already emitting a NOP
1534 instruction, we must check for these cases compared to the
1535 instruction previous to the previous instruction. */
1536 if ((! mips_opts
.mips16
1537 && mips_opts
.isa
< 4
1538 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1539 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1540 && (pinfo
& INSN_READ_COND_CODE
)
1541 && ! cop_interlocks
)
1542 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1543 && (pinfo
& INSN_WRITE_LO
)
1544 && ! hilo_interlocks
)
1545 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1546 && (pinfo
& INSN_WRITE_HI
)
1547 && ! hilo_interlocks
))
1552 if (prev_prev_insn_unreordered
)
1555 if (prev_prev_nop
&& nops
== 0)
1558 /* If we are being given a nop instruction, don't bother with
1559 one of the nops we would otherwise output. This will only
1560 happen when a nop instruction is used with mips_optimize set
1563 && ! mips_opts
.noreorder
1564 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1567 /* Now emit the right number of NOP instructions. */
1568 if (nops
> 0 && ! mips_opts
.noreorder
)
1571 unsigned long old_frag_offset
;
1573 struct insn_label_list
*l
;
1575 old_frag
= frag_now
;
1576 old_frag_offset
= frag_now_fix ();
1578 for (i
= 0; i
< nops
; i
++)
1583 listing_prev_line ();
1584 /* We may be at the start of a variant frag. In case we
1585 are, make sure there is enough space for the frag
1586 after the frags created by listing_prev_line. The
1587 argument to frag_grow here must be at least as large
1588 as the argument to all other calls to frag_grow in
1589 this file. We don't have to worry about being in the
1590 middle of a variant frag, because the variants insert
1591 all needed nop instructions themselves. */
1595 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1597 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1598 l
->label
->sy_frag
= frag_now
;
1599 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1600 /* mips16 text labels are stored as odd. */
1601 if (mips_opts
.mips16
)
1602 ++l
->label
->sy_value
.X_add_number
;
1605 #ifndef NO_ECOFF_DEBUGGING
1606 if (ECOFF_DEBUGGING
)
1607 ecoff_fix_loc (old_frag
, old_frag_offset
);
1610 else if (prev_nop_frag
!= NULL
)
1612 /* We have a frag holding nops we may be able to remove. If
1613 we don't need any nops, we can decrease the size of
1614 prev_nop_frag by the size of one instruction. If we do
1615 need some nops, we count them in prev_nops_required. */
1616 if (prev_nop_frag_since
== 0)
1620 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1621 --prev_nop_frag_holds
;
1624 prev_nop_frag_required
+= nops
;
1628 if (prev_prev_nop
== 0)
1630 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1631 --prev_nop_frag_holds
;
1634 ++prev_nop_frag_required
;
1637 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1638 prev_nop_frag
= NULL
;
1640 ++prev_nop_frag_since
;
1642 /* Sanity check: by the time we reach the second instruction
1643 after prev_nop_frag, we should have used up all the nops
1644 one way or another. */
1645 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1649 if (reloc_type
> BFD_RELOC_UNUSED
)
1651 /* We need to set up a variant frag. */
1652 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1653 f
= frag_var (rs_machine_dependent
, 4, 0,
1654 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1655 mips16_small
, mips16_ext
,
1657 & INSN_UNCOND_BRANCH_DELAY
),
1658 (prev_insn_reloc_type
1659 == BFD_RELOC_MIPS16_JMP
)),
1660 make_expr_symbol (address_expr
), (offsetT
) 0,
1663 else if (place
!= NULL
)
1665 else if (mips_opts
.mips16
1667 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1669 /* Make sure there is enough room to swap this instruction with
1670 a following jump instruction. */
1676 if (mips_opts
.mips16
1677 && mips_opts
.noreorder
1678 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1679 as_warn ("extended instruction in delay slot");
1685 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1687 if (address_expr
->X_op
== O_constant
)
1692 ip
->insn_opcode
|= address_expr
->X_add_number
;
1695 case BFD_RELOC_LO16
:
1696 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1699 case BFD_RELOC_MIPS_JMP
:
1700 if ((address_expr
->X_add_number
& 3) != 0)
1701 as_bad ("jump to misaligned address (0x%lx)",
1702 (unsigned long) address_expr
->X_add_number
);
1703 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1706 case BFD_RELOC_MIPS16_JMP
:
1707 if ((address_expr
->X_add_number
& 3) != 0)
1708 as_bad ("jump to misaligned address (0x%lx)",
1709 (unsigned long) address_expr
->X_add_number
);
1711 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1712 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1713 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1716 case BFD_RELOC_16_PCREL_S2
:
1726 /* Don't generate a reloc if we are writing into a variant
1730 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1732 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1736 struct mips_hi_fixup
*hi_fixup
;
1738 assert (reloc_type
== BFD_RELOC_HI16_S
);
1739 hi_fixup
= ((struct mips_hi_fixup
*)
1740 xmalloc (sizeof (struct mips_hi_fixup
)));
1741 hi_fixup
->fixp
= fixp
;
1742 hi_fixup
->seg
= now_seg
;
1743 hi_fixup
->next
= mips_hi_fixup_list
;
1744 mips_hi_fixup_list
= hi_fixup
;
1750 if (! mips_opts
.mips16
)
1751 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1752 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1754 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1755 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1761 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1764 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1767 /* Update the register mask information. */
1768 if (! mips_opts
.mips16
)
1770 if (pinfo
& INSN_WRITE_GPR_D
)
1771 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1772 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1773 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1774 if (pinfo
& INSN_READ_GPR_S
)
1775 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1776 if (pinfo
& INSN_WRITE_GPR_31
)
1777 mips_gprmask
|= 1 << 31;
1778 if (pinfo
& INSN_WRITE_FPR_D
)
1779 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1780 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1781 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1782 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1783 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1784 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1785 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1786 if (pinfo
& INSN_COP
)
1788 /* We don't keep enough information to sort these cases out.
1789 The itbl support does keep this information however, although
1790 we currently don't support itbl fprmats as part of the cop
1791 instruction. May want to add this support in the future. */
1793 /* Never set the bit for $0, which is always zero. */
1794 mips_gprmask
&=~ 1 << 0;
1798 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1799 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1800 & MIPS16OP_MASK_RX
);
1801 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1802 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1803 & MIPS16OP_MASK_RY
);
1804 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1805 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1806 & MIPS16OP_MASK_RZ
);
1807 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1808 mips_gprmask
|= 1 << TREG
;
1809 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1810 mips_gprmask
|= 1 << SP
;
1811 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1812 mips_gprmask
|= 1 << RA
;
1813 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1814 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1815 if (pinfo
& MIPS16_INSN_READ_Z
)
1816 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1817 & MIPS16OP_MASK_MOVE32Z
);
1818 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1819 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1820 & MIPS16OP_MASK_REGR32
);
1823 if (place
== NULL
&& ! mips_opts
.noreorder
)
1825 /* Filling the branch delay slot is more complex. We try to
1826 switch the branch with the previous instruction, which we can
1827 do if the previous instruction does not set up a condition
1828 that the branch tests and if the branch is not itself the
1829 target of any branch. */
1830 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1831 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1833 if (mips_optimize
< 2
1834 /* If we have seen .set volatile or .set nomove, don't
1836 || mips_opts
.nomove
!= 0
1837 /* If we had to emit any NOP instructions, then we
1838 already know we can not swap. */
1840 /* If we don't even know the previous insn, we can not
1842 || ! prev_insn_valid
1843 /* If the previous insn is already in a branch delay
1844 slot, then we can not swap. */
1845 || prev_insn_is_delay_slot
1846 /* If the previous previous insn was in a .set
1847 noreorder, we can't swap. Actually, the MIPS
1848 assembler will swap in this situation. However, gcc
1849 configured -with-gnu-as will generate code like
1855 in which we can not swap the bne and INSN. If gcc is
1856 not configured -with-gnu-as, it does not output the
1857 .set pseudo-ops. We don't have to check
1858 prev_insn_unreordered, because prev_insn_valid will
1859 be 0 in that case. We don't want to use
1860 prev_prev_insn_valid, because we do want to be able
1861 to swap at the start of a function. */
1862 || prev_prev_insn_unreordered
1863 /* If the branch is itself the target of a branch, we
1864 can not swap. We cheat on this; all we check for is
1865 whether there is a label on this instruction. If
1866 there are any branches to anything other than a
1867 label, users must use .set noreorder. */
1868 || insn_labels
!= NULL
1869 /* If the previous instruction is in a variant frag, we
1870 can not do the swap. This does not apply to the
1871 mips16, which uses variant frags for different
1873 || (! mips_opts
.mips16
1874 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1875 /* If the branch reads the condition codes, we don't
1876 even try to swap, because in the sequence
1881 we can not swap, and I don't feel like handling that
1883 || (! mips_opts
.mips16
1884 && mips_opts
.isa
< 4
1885 && (pinfo
& INSN_READ_COND_CODE
))
1886 /* We can not swap with an instruction that requires a
1887 delay slot, becase the target of the branch might
1888 interfere with that instruction. */
1889 || (! mips_opts
.mips16
1890 && mips_opts
.isa
< 4
1892 /* Itbl support may require additional care here. */
1893 & (INSN_LOAD_COPROC_DELAY
1894 | INSN_COPROC_MOVE_DELAY
1895 | INSN_WRITE_COND_CODE
)))
1896 || (! hilo_interlocks
1900 || (! mips_opts
.mips16
1902 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1903 || (! mips_opts
.mips16
1904 && mips_opts
.isa
< 2
1905 /* Itbl support may require additional care here. */
1906 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1907 /* We can not swap with a branch instruction. */
1909 & (INSN_UNCOND_BRANCH_DELAY
1910 | INSN_COND_BRANCH_DELAY
1911 | INSN_COND_BRANCH_LIKELY
))
1912 /* We do not swap with a trap instruction, since it
1913 complicates trap handlers to have the trap
1914 instruction be in a delay slot. */
1915 || (prev_pinfo
& INSN_TRAP
)
1916 /* If the branch reads a register that the previous
1917 instruction sets, we can not swap. */
1918 || (! mips_opts
.mips16
1919 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1920 && insn_uses_reg (ip
,
1921 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1924 || (! mips_opts
.mips16
1925 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1926 && insn_uses_reg (ip
,
1927 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1930 || (mips_opts
.mips16
1931 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1932 && insn_uses_reg (ip
,
1933 ((prev_insn
.insn_opcode
1935 & MIPS16OP_MASK_RX
),
1937 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1938 && insn_uses_reg (ip
,
1939 ((prev_insn
.insn_opcode
1941 & MIPS16OP_MASK_RY
),
1943 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1944 && insn_uses_reg (ip
,
1945 ((prev_insn
.insn_opcode
1947 & MIPS16OP_MASK_RZ
),
1949 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1950 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1951 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1952 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1953 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1954 && insn_uses_reg (ip
,
1955 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1958 /* If the branch writes a register that the previous
1959 instruction sets, we can not swap (we know that
1960 branches write only to RD or to $31). */
1961 || (! mips_opts
.mips16
1962 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1963 && (((pinfo
& INSN_WRITE_GPR_D
)
1964 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1965 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1966 || ((pinfo
& INSN_WRITE_GPR_31
)
1967 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1970 || (! mips_opts
.mips16
1971 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1972 && (((pinfo
& INSN_WRITE_GPR_D
)
1973 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1974 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1975 || ((pinfo
& INSN_WRITE_GPR_31
)
1976 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1979 || (mips_opts
.mips16
1980 && (pinfo
& MIPS16_INSN_WRITE_31
)
1981 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1982 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1983 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1985 /* If the branch writes a register that the previous
1986 instruction reads, we can not swap (we know that
1987 branches only write to RD or to $31). */
1988 || (! mips_opts
.mips16
1989 && (pinfo
& INSN_WRITE_GPR_D
)
1990 && insn_uses_reg (&prev_insn
,
1991 ((ip
->insn_opcode
>> OP_SH_RD
)
1994 || (! mips_opts
.mips16
1995 && (pinfo
& INSN_WRITE_GPR_31
)
1996 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1997 || (mips_opts
.mips16
1998 && (pinfo
& MIPS16_INSN_WRITE_31
)
1999 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2000 /* If we are generating embedded PIC code, the branch
2001 might be expanded into a sequence which uses $at, so
2002 we can't swap with an instruction which reads it. */
2003 || (mips_pic
== EMBEDDED_PIC
2004 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2005 /* If the previous previous instruction has a load
2006 delay, and sets a register that the branch reads, we
2008 || (! mips_opts
.mips16
2009 && mips_opts
.isa
< 4
2010 /* Itbl support may require additional care here. */
2011 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2012 || (! gpr_interlocks
2013 && (prev_prev_insn
.insn_mo
->pinfo
2014 & INSN_LOAD_MEMORY_DELAY
)))
2015 && insn_uses_reg (ip
,
2016 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2019 /* If one instruction sets a condition code and the
2020 other one uses a condition code, we can not swap. */
2021 || ((pinfo
& INSN_READ_COND_CODE
)
2022 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2023 || ((pinfo
& INSN_WRITE_COND_CODE
)
2024 && (prev_pinfo
& INSN_READ_COND_CODE
))
2025 /* If the previous instruction uses the PC, we can not
2027 || (mips_opts
.mips16
2028 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2029 /* If the previous instruction was extended, we can not
2031 || (mips_opts
.mips16
&& prev_insn_extended
)
2032 /* If the previous instruction had a fixup in mips16
2033 mode, we can not swap. This normally means that the
2034 previous instruction was a 4 byte branch anyhow. */
2035 || (mips_opts
.mips16
&& prev_insn_fixp
))
2037 /* We could do even better for unconditional branches to
2038 portions of this object file; we could pick up the
2039 instruction at the destination, put it in the delay
2040 slot, and bump the destination address. */
2042 /* Update the previous insn information. */
2043 prev_prev_insn
= *ip
;
2044 prev_insn
.insn_mo
= &dummy_opcode
;
2048 /* It looks like we can actually do the swap. */
2049 if (! mips_opts
.mips16
)
2054 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2055 memcpy (temp
, prev_f
, 4);
2056 memcpy (prev_f
, f
, 4);
2057 memcpy (f
, temp
, 4);
2060 prev_insn_fixp
->fx_frag
= frag_now
;
2061 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2065 fixp
->fx_frag
= prev_insn_frag
;
2066 fixp
->fx_where
= prev_insn_where
;
2074 assert (prev_insn_fixp
== NULL
);
2075 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2076 memcpy (temp
, prev_f
, 2);
2077 memcpy (prev_f
, f
, 2);
2078 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2080 assert (reloc_type
== BFD_RELOC_UNUSED
);
2081 memcpy (f
, temp
, 2);
2085 memcpy (f
, f
+ 2, 2);
2086 memcpy (f
+ 2, temp
, 2);
2090 fixp
->fx_frag
= prev_insn_frag
;
2091 fixp
->fx_where
= prev_insn_where
;
2095 /* Update the previous insn information; leave prev_insn
2097 prev_prev_insn
= *ip
;
2099 prev_insn_is_delay_slot
= 1;
2101 /* If that was an unconditional branch, forget the previous
2102 insn information. */
2103 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2105 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2106 prev_insn
.insn_mo
= &dummy_opcode
;
2109 prev_insn_fixp
= NULL
;
2110 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2111 prev_insn_extended
= 0;
2113 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2115 /* We don't yet optimize a branch likely. What we should do
2116 is look at the target, copy the instruction found there
2117 into the delay slot, and increment the branch to jump to
2118 the next instruction. */
2120 /* Update the previous insn information. */
2121 prev_prev_insn
= *ip
;
2122 prev_insn
.insn_mo
= &dummy_opcode
;
2123 prev_insn_fixp
= NULL
;
2124 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2125 prev_insn_extended
= 0;
2129 /* Update the previous insn information. */
2131 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2133 prev_prev_insn
= prev_insn
;
2136 /* Any time we see a branch, we always fill the delay slot
2137 immediately; since this insn is not a branch, we know it
2138 is not in a delay slot. */
2139 prev_insn_is_delay_slot
= 0;
2141 prev_insn_fixp
= fixp
;
2142 prev_insn_reloc_type
= reloc_type
;
2143 if (mips_opts
.mips16
)
2144 prev_insn_extended
= (ip
->use_extend
2145 || reloc_type
> BFD_RELOC_UNUSED
);
2148 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2149 prev_insn_unreordered
= 0;
2150 prev_insn_frag
= frag_now
;
2151 prev_insn_where
= f
- frag_now
->fr_literal
;
2152 prev_insn_valid
= 1;
2154 else if (place
== NULL
)
2156 /* We need to record a bit of information even when we are not
2157 reordering, in order to determine the base address for mips16
2158 PC relative relocs. */
2159 prev_prev_insn
= prev_insn
;
2161 prev_insn_reloc_type
= reloc_type
;
2162 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2163 prev_insn_unreordered
= 1;
2166 /* We just output an insn, so the next one doesn't have a label. */
2167 mips_clear_insn_labels ();
2170 /* This function forgets that there was any previous instruction or
2171 label. If PRESERVE is non-zero, it remembers enough information to
2172 know whether nops are needed before a noreorder section. */
2175 mips_no_prev_insn (preserve
)
2180 prev_insn
.insn_mo
= &dummy_opcode
;
2181 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2182 prev_nop_frag
= NULL
;
2183 prev_nop_frag_holds
= 0;
2184 prev_nop_frag_required
= 0;
2185 prev_nop_frag_since
= 0;
2187 prev_insn_valid
= 0;
2188 prev_insn_is_delay_slot
= 0;
2189 prev_insn_unreordered
= 0;
2190 prev_insn_extended
= 0;
2191 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2192 prev_prev_insn_unreordered
= 0;
2193 mips_clear_insn_labels ();
2196 /* This function must be called whenever we turn on noreorder or emit
2197 something other than instructions. It inserts any NOPS which might
2198 be needed by the previous instruction, and clears the information
2199 kept for the previous instructions. The INSNS parameter is true if
2200 instructions are to follow. */
2203 mips_emit_delays (insns
)
2206 if (! mips_opts
.noreorder
)
2211 if ((! mips_opts
.mips16
2212 && mips_opts
.isa
< 4
2213 && (! cop_interlocks
2214 && (prev_insn
.insn_mo
->pinfo
2215 & (INSN_LOAD_COPROC_DELAY
2216 | INSN_COPROC_MOVE_DELAY
2217 | INSN_WRITE_COND_CODE
))))
2218 || (! hilo_interlocks
2219 && (prev_insn
.insn_mo
->pinfo
2222 || (! mips_opts
.mips16
2224 && (prev_insn
.insn_mo
->pinfo
2225 & INSN_LOAD_MEMORY_DELAY
))
2226 || (! mips_opts
.mips16
2227 && mips_opts
.isa
< 2
2228 && (prev_insn
.insn_mo
->pinfo
2229 & INSN_COPROC_MEMORY_DELAY
)))
2231 /* Itbl support may require additional care here. */
2233 if ((! mips_opts
.mips16
2234 && mips_opts
.isa
< 4
2235 && (! cop_interlocks
2236 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2237 || (! hilo_interlocks
2238 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2239 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2242 if (prev_insn_unreordered
)
2245 else if ((! mips_opts
.mips16
2246 && mips_opts
.isa
< 4
2247 && (! cop_interlocks
2248 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2249 || (! hilo_interlocks
2250 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2251 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2253 /* Itbl support may require additional care here. */
2254 if (! prev_prev_insn_unreordered
)
2260 struct insn_label_list
*l
;
2264 /* Record the frag which holds the nop instructions, so
2265 that we can remove them if we don't need them. */
2266 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2267 prev_nop_frag
= frag_now
;
2268 prev_nop_frag_holds
= nops
;
2269 prev_nop_frag_required
= 0;
2270 prev_nop_frag_since
= 0;
2273 for (; nops
> 0; --nops
)
2278 /* Move on to a new frag, so that it is safe to simply
2279 decrease the size of prev_nop_frag. */
2280 frag_wane (frag_now
);
2284 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2286 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2287 l
->label
->sy_frag
= frag_now
;
2288 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2289 /* mips16 text labels are stored as odd. */
2290 if (mips_opts
.mips16
)
2291 ++l
->label
->sy_value
.X_add_number
;
2296 /* Mark instruction labels in mips16 mode. */
2297 if (mips_opts
.mips16
&& insns
)
2298 mips16_mark_labels ();
2300 mips_no_prev_insn (insns
);
2303 /* Build an instruction created by a macro expansion. This is passed
2304 a pointer to the count of instructions created so far, an
2305 expression, the name of the instruction to build, an operand format
2306 string, and corresponding arguments. */
2310 macro_build (char *place
,
2318 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2327 struct mips_cl_insn insn
;
2328 bfd_reloc_code_real_type r
;
2333 va_start (args
, fmt
);
2339 * If the macro is about to expand into a second instruction,
2340 * print a warning if needed. We need to pass ip as a parameter
2341 * to generate a better warning message here...
2343 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2344 as_warn ("Macro instruction expanded into multiple instructions");
2347 *counter
+= 1; /* bump instruction counter */
2349 if (mips_opts
.mips16
)
2351 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2356 r
= BFD_RELOC_UNUSED
;
2357 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2358 assert (insn
.insn_mo
);
2359 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2362 /* Search until we get a match for NAME. */
2365 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2366 insn_isa
= insn
.insn_mo
->match
;
2367 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2369 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2371 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2373 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2378 if (insn_isa
> mips_opts
.isa
2379 && (insn
.insn_mo
->pinfo
!= INSN_MACRO
2381 && (insn
.insn_mo
->membership
& INSN_4650
) != INSN_4650
)
2382 || (mips_4650
&& (insn
.insn_mo
->pinfo
& FP_D
))
2384 && (insn
.insn_mo
->membership
& INSN_4010
) != INSN_4010
)
2386 && (insn
.insn_mo
->membership
& INSN_4100
) != INSN_4100
)
2387 /* start-sanitize-r5900 */
2389 && (insn
.insn_mo
->membership
& INSN_5900
) != INSN_5900
)
2390 || (mips_5900
&& (insn
.insn_mo
->pinfo
& FP_D
))
2391 /* end-sanitize-r5900 */
2393 && (insn
.insn_mo
->membership
& INSN_3900
) != INSN_3900
))))
2396 assert (insn
.insn_mo
->name
);
2397 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2401 /* We got a successful match. */
2405 insn
.insn_opcode
= insn
.insn_mo
->match
;
2421 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2427 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2432 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2437 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2444 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2448 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2452 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2459 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2465 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2466 assert (r
== BFD_RELOC_MIPS_GPREL
2467 || r
== BFD_RELOC_MIPS_LITERAL
2468 || r
== BFD_RELOC_LO16
2469 || r
== BFD_RELOC_MIPS_GOT16
2470 || r
== BFD_RELOC_MIPS_CALL16
2471 || r
== BFD_RELOC_MIPS_GOT_LO16
2472 || r
== BFD_RELOC_MIPS_CALL_LO16
2473 || (ep
->X_op
== O_subtract
2474 && now_seg
== text_section
2475 && r
== BFD_RELOC_PCREL_LO16
));
2479 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2481 && (ep
->X_op
== O_constant
2482 || (ep
->X_op
== O_symbol
2483 && (r
== BFD_RELOC_HI16_S
2484 || r
== BFD_RELOC_HI16
2485 || r
== BFD_RELOC_MIPS_GOT_HI16
2486 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2487 || (ep
->X_op
== O_subtract
2488 && now_seg
== text_section
2489 && r
== BFD_RELOC_PCREL_HI16_S
)));
2490 if (ep
->X_op
== O_constant
)
2492 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2494 r
= BFD_RELOC_UNUSED
;
2499 assert (ep
!= NULL
);
2501 * This allows macro() to pass an immediate expression for
2502 * creating short branches without creating a symbol.
2503 * Note that the expression still might come from the assembly
2504 * input, in which case the value is not checked for range nor
2505 * is a relocation entry generated (yuck).
2507 if (ep
->X_op
== O_constant
)
2509 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2513 r
= BFD_RELOC_16_PCREL_S2
;
2517 assert (ep
!= NULL
);
2518 r
= BFD_RELOC_MIPS_JMP
;
2527 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2529 append_insn (place
, &insn
, ep
, r
, false);
2533 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2541 struct mips_cl_insn insn
;
2542 bfd_reloc_code_real_type r
;
2544 r
= BFD_RELOC_UNUSED
;
2545 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2546 assert (insn
.insn_mo
);
2547 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2549 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2550 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2553 assert (insn
.insn_mo
->name
);
2554 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2557 insn
.insn_opcode
= insn
.insn_mo
->match
;
2558 insn
.use_extend
= false;
2577 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2582 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2586 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2590 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2600 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2607 regno
= va_arg (args
, int);
2608 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2609 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2630 assert (ep
!= NULL
);
2632 if (ep
->X_op
!= O_constant
)
2633 r
= BFD_RELOC_UNUSED
+ c
;
2636 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2637 false, false, &insn
.insn_opcode
,
2638 &insn
.use_extend
, &insn
.extend
);
2640 r
= BFD_RELOC_UNUSED
;
2646 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2653 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2655 append_insn (place
, &insn
, ep
, r
, false);
2659 * Generate a "lui" instruction.
2662 macro_build_lui (place
, counter
, ep
, regnum
)
2668 expressionS high_expr
;
2669 struct mips_cl_insn insn
;
2670 bfd_reloc_code_real_type r
;
2671 CONST
char *name
= "lui";
2672 CONST
char *fmt
= "t,u";
2674 assert (! mips_opts
.mips16
);
2680 high_expr
.X_op
= O_constant
;
2681 high_expr
.X_add_number
= ep
->X_add_number
;
2684 if (high_expr
.X_op
== O_constant
)
2686 /* we can compute the instruction now without a relocation entry */
2687 if (high_expr
.X_add_number
& 0x8000)
2688 high_expr
.X_add_number
+= 0x10000;
2689 high_expr
.X_add_number
=
2690 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2691 r
= BFD_RELOC_UNUSED
;
2695 assert (ep
->X_op
== O_symbol
);
2696 /* _gp_disp is a special case, used from s_cpload. */
2697 assert (mips_pic
== NO_PIC
2698 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2699 r
= BFD_RELOC_HI16_S
;
2703 * If the macro is about to expand into a second instruction,
2704 * print a warning if needed. We need to pass ip as a parameter
2705 * to generate a better warning message here...
2707 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2708 as_warn ("Macro instruction expanded into multiple instructions");
2711 *counter
+= 1; /* bump instruction counter */
2713 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2714 assert (insn
.insn_mo
);
2715 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2716 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2718 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2719 if (r
== BFD_RELOC_UNUSED
)
2721 insn
.insn_opcode
|= high_expr
.X_add_number
;
2722 append_insn (place
, &insn
, NULL
, r
, false);
2725 append_insn (place
, &insn
, &high_expr
, r
, false);
2729 * Generates code to set the $at register to true (one)
2730 * if reg is less than the immediate expression.
2733 set_at (counter
, reg
, unsignedp
)
2738 if (imm_expr
.X_op
== O_constant
2739 && imm_expr
.X_add_number
>= -0x8000
2740 && imm_expr
.X_add_number
< 0x8000)
2741 macro_build ((char *) NULL
, counter
, &imm_expr
,
2742 unsignedp
? "sltiu" : "slti",
2743 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2746 load_register (counter
, AT
, &imm_expr
, 0);
2747 macro_build ((char *) NULL
, counter
, NULL
,
2748 unsignedp
? "sltu" : "slt",
2749 "d,v,t", AT
, reg
, AT
);
2753 /* Warn if an expression is not a constant. */
2756 check_absolute_expr (ip
, ex
)
2757 struct mips_cl_insn
*ip
;
2760 if (ex
->X_op
== O_big
)
2761 as_bad ("unsupported large constant");
2762 else if (ex
->X_op
!= O_constant
)
2763 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2766 /* Count the leading zeroes by performing a binary chop. This is a
2767 bulky bit of source, but performance is a LOT better for the
2768 majority of values than a simple loop to count the bits:
2769 for (lcnt = 0; (lcnt < 32); lcnt++)
2770 if ((v) & (1 << (31 - lcnt)))
2772 However it is not code size friendly, and the gain will drop a bit
2773 on certain cached systems.
2775 #define COUNT_TOP_ZEROES(v) \
2776 (((v) & ~0xffff) == 0 \
2777 ? ((v) & ~0xff) == 0 \
2778 ? ((v) & ~0xf) == 0 \
2779 ? ((v) & ~0x3) == 0 \
2780 ? ((v) & ~0x1) == 0 \
2785 : ((v) & ~0x7) == 0 \
2788 : ((v) & ~0x3f) == 0 \
2789 ? ((v) & ~0x1f) == 0 \
2792 : ((v) & ~0x7f) == 0 \
2795 : ((v) & ~0xfff) == 0 \
2796 ? ((v) & ~0x3ff) == 0 \
2797 ? ((v) & ~0x1ff) == 0 \
2800 : ((v) & ~0x7ff) == 0 \
2803 : ((v) & ~0x3fff) == 0 \
2804 ? ((v) & ~0x1fff) == 0 \
2807 : ((v) & ~0x7fff) == 0 \
2810 : ((v) & ~0xffffff) == 0 \
2811 ? ((v) & ~0xfffff) == 0 \
2812 ? ((v) & ~0x3ffff) == 0 \
2813 ? ((v) & ~0x1ffff) == 0 \
2816 : ((v) & ~0x7ffff) == 0 \
2819 : ((v) & ~0x3fffff) == 0 \
2820 ? ((v) & ~0x1fffff) == 0 \
2823 : ((v) & ~0x7fffff) == 0 \
2826 : ((v) & ~0xfffffff) == 0 \
2827 ? ((v) & ~0x3ffffff) == 0 \
2828 ? ((v) & ~0x1ffffff) == 0 \
2831 : ((v) & ~0x7ffffff) == 0 \
2834 : ((v) & ~0x3fffffff) == 0 \
2835 ? ((v) & ~0x1fffffff) == 0 \
2838 : ((v) & ~0x7fffffff) == 0 \
2843 * This routine generates the least number of instructions neccessary to load
2844 * an absolute expression value into a register.
2847 load_register (counter
, reg
, ep
, dbl
)
2854 expressionS hi32
, lo32
;
2856 if (ep
->X_op
!= O_big
)
2858 assert (ep
->X_op
== O_constant
);
2859 if (ep
->X_add_number
< 0x8000
2860 && (ep
->X_add_number
>= 0
2861 || (ep
->X_add_number
>= -0x8000
2864 || sizeof (ep
->X_add_number
) > 4))))
2866 /* We can handle 16 bit signed values with an addiu to
2867 $zero. No need to ever use daddiu here, since $zero and
2868 the result are always correct in 32 bit mode. */
2869 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2870 (int) BFD_RELOC_LO16
);
2873 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2875 /* We can handle 16 bit unsigned values with an ori to
2877 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2878 (int) BFD_RELOC_LO16
);
2881 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2882 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2883 == ~ (offsetT
) 0x7fffffff))
2886 || sizeof (ep
->X_add_number
) > 4
2887 || (ep
->X_add_number
& 0x80000000) == 0))
2888 || ((mips_opts
.isa
< 3 || ! dbl
)
2889 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2890 || (mips_opts
.isa
< 3
2892 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2893 == ~ (offsetT
) 0xffffffff)))
2895 /* 32 bit values require an lui. */
2896 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2897 (int) BFD_RELOC_HI16
);
2898 if ((ep
->X_add_number
& 0xffff) != 0)
2899 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2900 (int) BFD_RELOC_LO16
);
2905 /* The value is larger than 32 bits. */
2907 if (mips_opts
.isa
< 3)
2909 as_bad ("Number larger than 32 bits");
2910 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2911 (int) BFD_RELOC_LO16
);
2915 if (ep
->X_op
!= O_big
)
2918 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2919 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2920 hi32
.X_add_number
&= 0xffffffff;
2922 lo32
.X_add_number
&= 0xffffffff;
2926 assert (ep
->X_add_number
> 2);
2927 if (ep
->X_add_number
== 3)
2928 generic_bignum
[3] = 0;
2929 else if (ep
->X_add_number
> 4)
2930 as_bad ("Number larger than 64 bits");
2931 lo32
.X_op
= O_constant
;
2932 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2933 hi32
.X_op
= O_constant
;
2934 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2937 if (hi32
.X_add_number
== 0)
2942 unsigned long hi
, lo
;
2944 if (hi32
.X_add_number
== 0xffffffff)
2946 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2948 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2949 reg
, 0, (int) BFD_RELOC_LO16
);
2952 if (lo32
.X_add_number
& 0x80000000)
2954 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2955 (int) BFD_RELOC_HI16
);
2956 if (lo32
.X_add_number
& 0xffff)
2957 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2958 reg
, reg
, (int) BFD_RELOC_LO16
);
2963 /* Check for 16bit shifted constant. We know that hi32 is
2964 non-zero, so start the mask on the first bit of the hi32
2969 unsigned long himask
, lomask
;
2973 himask
= 0xffff >> (32 - shift
);
2974 lomask
= (0xffff << shift
) & 0xffffffff;
2978 himask
= 0xffff << (shift
- 32);
2981 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2982 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2986 tmp
.X_op
= O_constant
;
2988 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2989 | (lo32
.X_add_number
>> shift
));
2991 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2992 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2993 (int) BFD_RELOC_LO16
);
2994 macro_build ((char *) NULL
, counter
, NULL
,
2995 (shift
>= 32) ? "dsll32" : "dsll",
2997 (shift
>= 32) ? shift
- 32 : shift
);
3001 } while (shift
<= (64 - 16));
3003 /* Find the bit number of the lowest one bit, and store the
3004 shifted value in hi/lo. */
3005 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3006 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3010 while ((lo
& 1) == 0)
3015 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3021 while ((hi
& 1) == 0)
3030 /* Optimize if the shifted value is a (power of 2) - 1. */
3031 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3032 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3034 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3039 /* This instruction will set the register to be all
3041 tmp
.X_op
= O_constant
;
3042 tmp
.X_add_number
= (offsetT
) -1;
3043 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3044 reg
, 0, (int) BFD_RELOC_LO16
);
3048 macro_build ((char *) NULL
, counter
, NULL
,
3049 (bit
>= 32) ? "dsll32" : "dsll",
3051 (bit
>= 32) ? bit
- 32 : bit
);
3053 macro_build ((char *) NULL
, counter
, NULL
,
3054 (shift
>= 32) ? "dsrl32" : "dsrl",
3056 (shift
>= 32) ? shift
- 32 : shift
);
3061 /* Sign extend hi32 before calling load_register, because we can
3062 generally get better code when we load a sign extended value. */
3063 if ((hi32
.X_add_number
& 0x80000000) != 0)
3064 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3065 load_register (counter
, reg
, &hi32
, 0);
3068 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3072 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3081 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3083 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3084 (int) BFD_RELOC_HI16
);
3085 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3092 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3097 mid16
.X_add_number
>>= 16;
3098 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3099 freg
, (int) BFD_RELOC_LO16
);
3100 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3104 if ((lo32
.X_add_number
& 0xffff) != 0)
3105 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3106 (int) BFD_RELOC_LO16
);
3109 /* Load an address into a register. */
3112 load_address (counter
, reg
, ep
)
3119 if (ep
->X_op
!= O_constant
3120 && ep
->X_op
!= O_symbol
)
3122 as_bad ("expression too complex");
3123 ep
->X_op
= O_constant
;
3126 if (ep
->X_op
== O_constant
)
3128 load_register (counter
, reg
, ep
, 0);
3132 if (mips_pic
== NO_PIC
)
3134 /* If this is a reference to a GP relative symbol, we want
3135 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3137 lui $reg,<sym> (BFD_RELOC_HI16_S)
3138 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3139 If we have an addend, we always use the latter form. */
3140 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3141 || nopic_need_relax (ep
->X_add_symbol
, 1))
3146 macro_build ((char *) NULL
, counter
, ep
,
3147 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3148 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3149 p
= frag_var (rs_machine_dependent
, 8, 0,
3150 RELAX_ENCODE (4, 8, 0, 4, 0,
3151 mips_opts
.warn_about_macros
),
3152 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3154 macro_build_lui (p
, counter
, ep
, reg
);
3157 macro_build (p
, counter
, ep
,
3158 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3159 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3161 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3165 /* If this is a reference to an external symbol, we want
3166 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3168 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3170 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3171 If there is a constant, it must be added in after. */
3172 ex
.X_add_number
= ep
->X_add_number
;
3173 ep
->X_add_number
= 0;
3175 macro_build ((char *) NULL
, counter
, ep
,
3176 mips_opts
.isa
< 3 ? "lw" : "ld",
3177 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3178 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3179 p
= frag_var (rs_machine_dependent
, 4, 0,
3180 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3181 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3182 macro_build (p
, counter
, ep
,
3183 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3184 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3185 if (ex
.X_add_number
!= 0)
3187 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3188 as_bad ("PIC code offset overflow (max 16 signed bits)");
3189 ex
.X_op
= O_constant
;
3190 macro_build ((char *) NULL
, counter
, &ex
,
3191 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3192 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3195 else if (mips_pic
== SVR4_PIC
)
3200 /* This is the large GOT case. If this is a reference to an
3201 external symbol, we want
3202 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3204 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3205 Otherwise, for a reference to a local symbol, we want
3206 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3208 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3209 If there is a constant, it must be added in after. */
3210 ex
.X_add_number
= ep
->X_add_number
;
3211 ep
->X_add_number
= 0;
3212 if (reg_needs_delay (GP
))
3217 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3218 (int) BFD_RELOC_MIPS_GOT_HI16
);
3219 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3220 mips_opts
.isa
< 3 ? "addu" : "daddu",
3221 "d,v,t", reg
, reg
, GP
);
3222 macro_build ((char *) NULL
, counter
, ep
,
3223 mips_opts
.isa
< 3 ? "lw" : "ld",
3224 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3225 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3226 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3227 mips_opts
.warn_about_macros
),
3228 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3231 /* We need a nop before loading from $gp. This special
3232 check is required because the lui which starts the main
3233 instruction stream does not refer to $gp, and so will not
3234 insert the nop which may be required. */
3235 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3238 macro_build (p
, counter
, ep
,
3239 mips_opts
.isa
< 3 ? "lw" : "ld",
3240 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3242 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3244 macro_build (p
, counter
, ep
,
3245 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3246 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3247 if (ex
.X_add_number
!= 0)
3249 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3250 as_bad ("PIC code offset overflow (max 16 signed bits)");
3251 ex
.X_op
= O_constant
;
3252 macro_build ((char *) NULL
, counter
, &ex
,
3253 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3254 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3257 else if (mips_pic
== EMBEDDED_PIC
)
3260 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3262 macro_build ((char *) NULL
, counter
, ep
,
3263 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3264 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3272 * This routine implements the seemingly endless macro or synthesized
3273 * instructions and addressing modes in the mips assembly language. Many
3274 * of these macros are simple and are similar to each other. These could
3275 * probably be handled by some kind of table or grammer aproach instead of
3276 * this verbose method. Others are not simple macros but are more like
3277 * optimizing code generation.
3278 * One interesting optimization is when several store macros appear
3279 * consecutivly that would load AT with the upper half of the same address.
3280 * The ensuing load upper instructions are ommited. This implies some kind
3281 * of global optimization. We currently only optimize within a single macro.
3282 * For many of the load and store macros if the address is specified as a
3283 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3284 * first load register 'at' with zero and use it as the base register. The
3285 * mips assembler simply uses register $zero. Just one tiny optimization
3290 struct mips_cl_insn
*ip
;
3292 register int treg
, sreg
, dreg
, breg
;
3307 bfd_reloc_code_real_type r
;
3309 int hold_mips_optimize
;
3311 assert (! mips_opts
.mips16
);
3313 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3314 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3315 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3316 mask
= ip
->insn_mo
->mask
;
3318 expr1
.X_op
= O_constant
;
3319 expr1
.X_op_symbol
= NULL
;
3320 expr1
.X_add_symbol
= NULL
;
3321 expr1
.X_add_number
= 1;
3333 mips_emit_delays (true);
3334 ++mips_opts
.noreorder
;
3335 mips_any_noreorder
= 1;
3337 expr1
.X_add_number
= 8;
3338 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3340 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3342 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3343 macro_build ((char *) NULL
, &icnt
, NULL
,
3344 dbl
? "dsub" : "sub",
3345 "d,v,t", dreg
, 0, sreg
);
3347 --mips_opts
.noreorder
;
3368 if (imm_expr
.X_op
== O_constant
3369 && imm_expr
.X_add_number
>= -0x8000
3370 && imm_expr
.X_add_number
< 0x8000)
3372 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3373 (int) BFD_RELOC_LO16
);
3376 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3377 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3396 if (imm_expr
.X_op
== O_constant
3397 && imm_expr
.X_add_number
>= 0
3398 && imm_expr
.X_add_number
< 0x10000)
3400 if (mask
!= M_NOR_I
)
3401 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3402 sreg
, (int) BFD_RELOC_LO16
);
3405 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3406 treg
, sreg
, (int) BFD_RELOC_LO16
);
3407 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3413 load_register (&icnt
, AT
, &imm_expr
, 0);
3414 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3431 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3433 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3437 load_register (&icnt
, AT
, &imm_expr
, 0);
3438 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3446 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3447 likely
? "bgezl" : "bgez",
3453 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3454 likely
? "blezl" : "blez",
3458 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3459 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3460 likely
? "beql" : "beq",
3467 /* check for > max integer */
3468 maxnum
= 0x7fffffff;
3469 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3476 if (imm_expr
.X_op
== O_constant
3477 && imm_expr
.X_add_number
>= maxnum
3478 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3481 /* result is always false */
3484 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3485 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3489 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3495 if (imm_expr
.X_op
!= O_constant
)
3496 as_bad ("Unsupported large constant");
3497 imm_expr
.X_add_number
++;
3501 if (mask
== M_BGEL_I
)
3503 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3506 likely
? "bgezl" : "bgez",
3510 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3512 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3513 likely
? "bgtzl" : "bgtz",
3517 maxnum
= 0x7fffffff;
3518 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3525 maxnum
= - maxnum
- 1;
3526 if (imm_expr
.X_op
== O_constant
3527 && imm_expr
.X_add_number
<= maxnum
3528 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3531 /* result is always true */
3532 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3533 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3536 set_at (&icnt
, sreg
, 0);
3537 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3538 likely
? "beql" : "beq",
3549 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3550 likely
? "beql" : "beq",
3554 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3556 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3557 likely
? "beql" : "beq",
3565 || (mips_opts
.isa
< 3
3566 && imm_expr
.X_op
== O_constant
3567 && imm_expr
.X_add_number
== 0xffffffff))
3569 if (imm_expr
.X_op
!= O_constant
)
3570 as_bad ("Unsupported large constant");
3571 imm_expr
.X_add_number
++;
3575 if (mask
== M_BGEUL_I
)
3577 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3579 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3581 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3582 likely
? "bnel" : "bne",
3586 set_at (&icnt
, sreg
, 1);
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3588 likely
? "beql" : "beq",
3597 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3598 likely
? "bgtzl" : "bgtz",
3604 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3605 likely
? "bltzl" : "bltz",
3609 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3610 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3611 likely
? "bnel" : "bne",
3620 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3621 likely
? "bnel" : "bne",
3627 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3630 likely
? "bnel" : "bne",
3639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3640 likely
? "blezl" : "blez",
3646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3647 likely
? "bgezl" : "bgez",
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3653 likely
? "beql" : "beq",
3660 maxnum
= 0x7fffffff;
3661 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3668 if (imm_expr
.X_op
== O_constant
3669 && imm_expr
.X_add_number
>= maxnum
3670 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3672 if (imm_expr
.X_op
!= O_constant
)
3673 as_bad ("Unsupported large constant");
3674 imm_expr
.X_add_number
++;
3678 if (mask
== M_BLTL_I
)
3680 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3682 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3683 likely
? "bltzl" : "bltz",
3687 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3689 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3690 likely
? "blezl" : "blez",
3694 set_at (&icnt
, sreg
, 0);
3695 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3696 likely
? "bnel" : "bne",
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3706 likely
? "beql" : "beq",
3712 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3715 likely
? "beql" : "beq",
3723 || (mips_opts
.isa
< 3
3724 && imm_expr
.X_op
== O_constant
3725 && imm_expr
.X_add_number
== 0xffffffff))
3727 if (imm_expr
.X_op
!= O_constant
)
3728 as_bad ("Unsupported large constant");
3729 imm_expr
.X_add_number
++;
3733 if (mask
== M_BLTUL_I
)
3735 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3737 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3739 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3740 likely
? "beql" : "beq",
3744 set_at (&icnt
, sreg
, 1);
3745 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3746 likely
? "bnel" : "bne",
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 likely
? "bltzl" : "bltz",
3762 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3763 likely
? "bgtzl" : "bgtz",
3767 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3768 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3769 likely
? "bnel" : "bne",
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "bnel" : "bne",
3785 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3787 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3788 likely
? "bnel" : "bne",
3804 as_warn ("Divide by zero.");
3806 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3808 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3812 mips_emit_delays (true);
3813 ++mips_opts
.noreorder
;
3814 mips_any_noreorder
= 1;
3815 macro_build ((char *) NULL
, &icnt
, NULL
,
3816 dbl
? "ddiv" : "div",
3817 "z,s,t", sreg
, treg
);
3819 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3822 expr1
.X_add_number
= 8;
3823 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3824 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3825 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3827 expr1
.X_add_number
= -1;
3828 macro_build ((char *) NULL
, &icnt
, &expr1
,
3829 dbl
? "daddiu" : "addiu",
3830 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3831 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3832 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3835 expr1
.X_add_number
= 1;
3836 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3837 (int) BFD_RELOC_LO16
);
3838 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3843 expr1
.X_add_number
= 0x80000000;
3844 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3845 (int) BFD_RELOC_HI16
);
3848 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3851 expr1
.X_add_number
= 8;
3852 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3853 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3854 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3856 --mips_opts
.noreorder
;
3857 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3896 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3898 as_warn ("Divide by zero.");
3900 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3902 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3905 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3907 if (strcmp (s2
, "mflo") == 0)
3908 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3911 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3914 if (imm_expr
.X_op
== O_constant
3915 && imm_expr
.X_add_number
== -1
3916 && s
[strlen (s
) - 1] != 'u')
3918 if (strcmp (s2
, "mflo") == 0)
3921 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3924 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3928 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3932 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3933 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3934 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3953 mips_emit_delays (true);
3954 ++mips_opts
.noreorder
;
3955 mips_any_noreorder
= 1;
3956 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3958 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3961 expr1
.X_add_number
= 8;
3962 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3963 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3964 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3966 --mips_opts
.noreorder
;
3967 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3973 /* Load the address of a symbol into a register. If breg is not
3974 zero, we then add a base register to it. */
3976 /* When generating embedded PIC code, we permit expressions of
3979 where bar is an address in the .text section. These are used
3980 when getting the addresses of functions. We don't permit
3981 X_add_number to be non-zero, because if the symbol is
3982 external the relaxing code needs to know that any addend is
3983 purely the offset to X_op_symbol. */
3984 if (mips_pic
== EMBEDDED_PIC
3985 && offset_expr
.X_op
== O_subtract
3986 && now_seg
== text_section
3987 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3988 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3989 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3990 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3991 ->sy_value
.X_add_symbol
)
3994 && offset_expr
.X_add_number
== 0)
3996 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3997 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3999 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4000 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4004 if (offset_expr
.X_op
!= O_symbol
4005 && offset_expr
.X_op
!= O_constant
)
4007 as_bad ("expression too complex");
4008 offset_expr
.X_op
= O_constant
;
4022 if (offset_expr
.X_op
== O_constant
)
4023 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4024 else if (mips_pic
== NO_PIC
)
4026 /* If this is a reference to an GP relative symbol, we want
4027 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4029 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4030 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4031 If we have a constant, we need two instructions anyhow,
4032 so we may as well always use the latter form. */
4033 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4034 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4039 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4040 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4041 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4042 p
= frag_var (rs_machine_dependent
, 8, 0,
4043 RELAX_ENCODE (4, 8, 0, 4, 0,
4044 mips_opts
.warn_about_macros
),
4045 offset_expr
.X_add_symbol
, (offsetT
) 0,
4048 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4051 macro_build (p
, &icnt
, &offset_expr
,
4052 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4053 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4055 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4057 /* If this is a reference to an external symbol, and there
4058 is no constant, we want
4059 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4060 For a local symbol, we want
4061 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4063 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4065 If we have a small constant, and this is a reference to
4066 an external symbol, we want
4067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4069 addiu $tempreg,$tempreg,<constant>
4070 For a local symbol, we want the same instruction
4071 sequence, but we output a BFD_RELOC_LO16 reloc on the
4074 If we have a large constant, and this is a reference to
4075 an external symbol, we want
4076 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4077 lui $at,<hiconstant>
4078 addiu $at,$at,<loconstant>
4079 addu $tempreg,$tempreg,$at
4080 For a local symbol, we want the same instruction
4081 sequence, but we output a BFD_RELOC_LO16 reloc on the
4082 addiu instruction. */
4083 expr1
.X_add_number
= offset_expr
.X_add_number
;
4084 offset_expr
.X_add_number
= 0;
4086 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4088 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4089 if (expr1
.X_add_number
== 0)
4097 /* We're going to put in an addu instruction using
4098 tempreg, so we may as well insert the nop right
4100 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4104 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4105 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4107 ? mips_opts
.warn_about_macros
4109 offset_expr
.X_add_symbol
, (offsetT
) 0,
4113 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4116 macro_build (p
, &icnt
, &expr1
,
4117 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4118 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4119 /* FIXME: If breg == 0, and the next instruction uses
4120 $tempreg, then if this variant case is used an extra
4121 nop will be generated. */
4123 else if (expr1
.X_add_number
>= -0x8000
4124 && expr1
.X_add_number
< 0x8000)
4126 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4128 macro_build ((char *) NULL
, &icnt
, &expr1
,
4129 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4130 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4131 (void) frag_var (rs_machine_dependent
, 0, 0,
4132 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4133 offset_expr
.X_add_symbol
, (offsetT
) 0,
4140 /* If we are going to add in a base register, and the
4141 target register and the base register are the same,
4142 then we are using AT as a temporary register. Since
4143 we want to load the constant into AT, we add our
4144 current AT (from the global offset table) and the
4145 register into the register now, and pretend we were
4146 not using a base register. */
4151 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4153 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4154 mips_opts
.isa
< 3 ? "addu" : "daddu",
4155 "d,v,t", treg
, AT
, breg
);
4161 /* Set mips_optimize around the lui instruction to avoid
4162 inserting an unnecessary nop after the lw. */
4163 hold_mips_optimize
= mips_optimize
;
4165 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4166 mips_optimize
= hold_mips_optimize
;
4168 macro_build ((char *) NULL
, &icnt
, &expr1
,
4169 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4170 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4172 mips_opts
.isa
< 3 ? "addu" : "daddu",
4173 "d,v,t", tempreg
, tempreg
, AT
);
4174 (void) frag_var (rs_machine_dependent
, 0, 0,
4175 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4176 offset_expr
.X_add_symbol
, (offsetT
) 0,
4181 else if (mips_pic
== SVR4_PIC
)
4185 /* This is the large GOT case. If this is a reference to an
4186 external symbol, and there is no constant, we want
4187 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4188 addu $tempreg,$tempreg,$gp
4189 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4190 For a local symbol, we want
4191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4193 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4195 If we have a small constant, and this is a reference to
4196 an external symbol, we want
4197 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4198 addu $tempreg,$tempreg,$gp
4199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4201 addiu $tempreg,$tempreg,<constant>
4202 For a local symbol, we want
4203 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4205 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4207 If we have a large constant, and this is a reference to
4208 an external symbol, we want
4209 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4210 addu $tempreg,$tempreg,$gp
4211 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4212 lui $at,<hiconstant>
4213 addiu $at,$at,<loconstant>
4214 addu $tempreg,$tempreg,$at
4215 For a local symbol, we want
4216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4217 lui $at,<hiconstant>
4218 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4219 addu $tempreg,$tempreg,$at
4221 expr1
.X_add_number
= offset_expr
.X_add_number
;
4222 offset_expr
.X_add_number
= 0;
4224 if (reg_needs_delay (GP
))
4228 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4229 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4230 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4231 mips_opts
.isa
< 3 ? "addu" : "daddu",
4232 "d,v,t", tempreg
, tempreg
, GP
);
4233 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4235 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4237 if (expr1
.X_add_number
== 0)
4245 /* We're going to put in an addu instruction using
4246 tempreg, so we may as well insert the nop right
4248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4253 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4254 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4257 ? mips_opts
.warn_about_macros
4259 offset_expr
.X_add_symbol
, (offsetT
) 0,
4262 else if (expr1
.X_add_number
>= -0x8000
4263 && expr1
.X_add_number
< 0x8000)
4265 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4267 macro_build ((char *) NULL
, &icnt
, &expr1
,
4268 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4269 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4271 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4272 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4274 ? mips_opts
.warn_about_macros
4276 offset_expr
.X_add_symbol
, (offsetT
) 0,
4283 /* If we are going to add in a base register, and the
4284 target register and the base register are the same,
4285 then we are using AT as a temporary register. Since
4286 we want to load the constant into AT, we add our
4287 current AT (from the global offset table) and the
4288 register into the register now, and pretend we were
4289 not using a base register. */
4297 assert (tempreg
== AT
);
4298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4301 mips_opts
.isa
< 3 ? "addu" : "daddu",
4302 "d,v,t", treg
, AT
, breg
);
4307 /* Set mips_optimize around the lui instruction to avoid
4308 inserting an unnecessary nop after the lw. */
4309 hold_mips_optimize
= mips_optimize
;
4311 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4312 mips_optimize
= hold_mips_optimize
;
4314 macro_build ((char *) NULL
, &icnt
, &expr1
,
4315 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4316 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4318 mips_opts
.isa
< 3 ? "addu" : "daddu",
4319 "d,v,t", dreg
, dreg
, AT
);
4321 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4322 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4325 ? mips_opts
.warn_about_macros
4327 offset_expr
.X_add_symbol
, (offsetT
) 0,
4335 /* This is needed because this instruction uses $gp, but
4336 the first instruction on the main stream does not. */
4337 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4340 macro_build (p
, &icnt
, &offset_expr
,
4342 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4344 if (expr1
.X_add_number
>= -0x8000
4345 && expr1
.X_add_number
< 0x8000)
4347 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4349 macro_build (p
, &icnt
, &expr1
,
4350 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4351 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4352 /* FIXME: If add_number is 0, and there was no base
4353 register, the external symbol case ended with a load,
4354 so if the symbol turns out to not be external, and
4355 the next instruction uses tempreg, an unnecessary nop
4356 will be inserted. */
4362 /* We must add in the base register now, as in the
4363 external symbol case. */
4364 assert (tempreg
== AT
);
4365 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4367 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4368 mips_opts
.isa
< 3 ? "addu" : "daddu",
4369 "d,v,t", treg
, AT
, breg
);
4372 /* We set breg to 0 because we have arranged to add
4373 it in in both cases. */
4377 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4379 macro_build (p
, &icnt
, &expr1
,
4380 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4381 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4383 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4384 mips_opts
.isa
< 3 ? "addu" : "daddu",
4385 "d,v,t", tempreg
, tempreg
, AT
);
4389 else if (mips_pic
== EMBEDDED_PIC
)
4392 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4394 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4395 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4396 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4403 mips_opts
.isa
< 3 ? "addu" : "daddu",
4404 "d,v,t", treg
, tempreg
, breg
);
4412 /* The j instruction may not be used in PIC code, since it
4413 requires an absolute address. We convert it to a b
4415 if (mips_pic
== NO_PIC
)
4416 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4418 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4421 /* The jal instructions must be handled as macros because when
4422 generating PIC code they expand to multi-instruction
4423 sequences. Normally they are simple instructions. */
4428 if (mips_pic
== NO_PIC
4429 || mips_pic
== EMBEDDED_PIC
)
4430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4432 else if (mips_pic
== SVR4_PIC
)
4434 if (sreg
!= PIC_CALL_REG
)
4435 as_warn ("MIPS PIC call to register other than $25");
4437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4439 if (mips_cprestore_offset
< 0)
4440 as_warn ("No .cprestore pseudo-op used in PIC code");
4443 expr1
.X_add_number
= mips_cprestore_offset
;
4444 macro_build ((char *) NULL
, &icnt
, &expr1
,
4445 mips_opts
.isa
< 3 ? "lw" : "ld",
4446 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4455 if (mips_pic
== NO_PIC
)
4456 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4457 else if (mips_pic
== SVR4_PIC
)
4459 /* If this is a reference to an external symbol, and we are
4460 using a small GOT, we want
4461 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4465 lw $gp,cprestore($sp)
4466 The cprestore value is set using the .cprestore
4467 pseudo-op. If we are using a big GOT, we want
4468 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4470 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4474 lw $gp,cprestore($sp)
4475 If the symbol is not external, we want
4476 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4478 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4481 lw $gp,cprestore($sp) */
4485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4486 mips_opts
.isa
< 3 ? "lw" : "ld",
4487 "t,o(b)", PIC_CALL_REG
,
4488 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4489 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4491 p
= frag_var (rs_machine_dependent
, 4, 0,
4492 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4493 offset_expr
.X_add_symbol
, (offsetT
) 0,
4500 if (reg_needs_delay (GP
))
4504 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4505 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4507 mips_opts
.isa
< 3 ? "addu" : "daddu",
4508 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4509 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4510 mips_opts
.isa
< 3 ? "lw" : "ld",
4511 "t,o(b)", PIC_CALL_REG
,
4512 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4513 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4515 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4516 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4518 offset_expr
.X_add_symbol
, (offsetT
) 0,
4522 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4525 macro_build (p
, &icnt
, &offset_expr
,
4526 mips_opts
.isa
< 3 ? "lw" : "ld",
4527 "t,o(b)", PIC_CALL_REG
,
4528 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4530 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4533 macro_build (p
, &icnt
, &offset_expr
,
4534 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4535 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4536 (int) BFD_RELOC_LO16
);
4537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4538 "jalr", "s", PIC_CALL_REG
);
4539 if (mips_cprestore_offset
< 0)
4540 as_warn ("No .cprestore pseudo-op used in PIC code");
4543 if (mips_opts
.noreorder
)
4544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4546 expr1
.X_add_number
= mips_cprestore_offset
;
4547 macro_build ((char *) NULL
, &icnt
, &expr1
,
4548 mips_opts
.isa
< 3 ? "lw" : "ld",
4549 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4553 else if (mips_pic
== EMBEDDED_PIC
)
4555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4556 /* The linker may expand the call to a longer sequence which
4557 uses $at, so we must break rather than return. */
4582 /* Itbl support may require additional care here. */
4587 /* Itbl support may require additional care here. */
4592 /* Itbl support may require additional care here. */
4597 /* Itbl support may require additional care here. */
4610 /* Itbl support may require additional care here. */
4615 /* Itbl support may require additional care here. */
4620 /* Itbl support may require additional care here. */
4640 if (breg
== treg
|| coproc
|| lr
)
4662 /* Itbl support may require additional care here. */
4667 /* Itbl support may require additional care here. */
4672 /* Itbl support may require additional care here. */
4677 /* Itbl support may require additional care here. */
4695 /* Itbl support may require additional care here. */
4699 /* Itbl support may require additional care here. */
4704 /* Itbl support may require additional care here. */
4716 /* Itbl support may require additional care here. */
4717 if (mask
== M_LWC1_AB
4718 || mask
== M_SWC1_AB
4719 || mask
== M_LDC1_AB
4720 || mask
== M_SDC1_AB
4729 if (offset_expr
.X_op
!= O_constant
4730 && offset_expr
.X_op
!= O_symbol
)
4732 as_bad ("expression too complex");
4733 offset_expr
.X_op
= O_constant
;
4736 /* A constant expression in PIC code can be handled just as it
4737 is in non PIC code. */
4738 if (mips_pic
== NO_PIC
4739 || offset_expr
.X_op
== O_constant
)
4741 /* If this is a reference to a GP relative symbol, and there
4742 is no base register, we want
4743 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4744 Otherwise, if there is no base register, we want
4745 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4746 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4747 If we have a constant, we need two instructions anyhow,
4748 so we always use the latter form.
4750 If we have a base register, and this is a reference to a
4751 GP relative symbol, we want
4752 addu $tempreg,$breg,$gp
4753 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4755 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4756 addu $tempreg,$tempreg,$breg
4757 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4758 With a constant we always use the latter case. */
4761 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4762 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4767 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4768 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4769 p
= frag_var (rs_machine_dependent
, 8, 0,
4770 RELAX_ENCODE (4, 8, 0, 4, 0,
4771 (mips_opts
.warn_about_macros
4773 && mips_opts
.noat
))),
4774 offset_expr
.X_add_symbol
, (offsetT
) 0,
4778 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4781 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4782 (int) BFD_RELOC_LO16
, tempreg
);
4786 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4787 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4792 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4793 mips_opts
.isa
< 3 ? "addu" : "daddu",
4794 "d,v,t", tempreg
, breg
, GP
);
4795 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4796 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4797 p
= frag_var (rs_machine_dependent
, 12, 0,
4798 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4799 offset_expr
.X_add_symbol
, (offsetT
) 0,
4802 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4805 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4806 mips_opts
.isa
< 3 ? "addu" : "daddu",
4807 "d,v,t", tempreg
, tempreg
, breg
);
4810 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4811 (int) BFD_RELOC_LO16
, tempreg
);
4814 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4816 /* If this is a reference to an external symbol, we want
4817 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4819 <op> $treg,0($tempreg)
4821 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4823 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4824 <op> $treg,0($tempreg)
4825 If there is a base register, we add it to $tempreg before
4826 the <op>. If there is a constant, we stick it in the
4827 <op> instruction. We don't handle constants larger than
4828 16 bits, because we have no way to load the upper 16 bits
4829 (actually, we could handle them for the subset of cases
4830 in which we are not using $at). */
4831 assert (offset_expr
.X_op
== O_symbol
);
4832 expr1
.X_add_number
= offset_expr
.X_add_number
;
4833 offset_expr
.X_add_number
= 0;
4834 if (expr1
.X_add_number
< -0x8000
4835 || expr1
.X_add_number
>= 0x8000)
4836 as_bad ("PIC code offset overflow (max 16 signed bits)");
4838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4839 mips_opts
.isa
< 3 ? "lw" : "ld",
4840 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4842 p
= frag_var (rs_machine_dependent
, 4, 0,
4843 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4844 offset_expr
.X_add_symbol
, (offsetT
) 0,
4846 macro_build (p
, &icnt
, &offset_expr
,
4847 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4848 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4851 mips_opts
.isa
< 3 ? "addu" : "daddu",
4852 "d,v,t", tempreg
, tempreg
, breg
);
4853 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4854 (int) BFD_RELOC_LO16
, tempreg
);
4856 else if (mips_pic
== SVR4_PIC
)
4860 /* If this is a reference to an external symbol, we want
4861 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4862 addu $tempreg,$tempreg,$gp
4863 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4864 <op> $treg,0($tempreg)
4866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4869 <op> $treg,0($tempreg)
4870 If there is a base register, we add it to $tempreg before
4871 the <op>. If there is a constant, we stick it in the
4872 <op> instruction. We don't handle constants larger than
4873 16 bits, because we have no way to load the upper 16 bits
4874 (actually, we could handle them for the subset of cases
4875 in which we are not using $at). */
4876 assert (offset_expr
.X_op
== O_symbol
);
4877 expr1
.X_add_number
= offset_expr
.X_add_number
;
4878 offset_expr
.X_add_number
= 0;
4879 if (expr1
.X_add_number
< -0x8000
4880 || expr1
.X_add_number
>= 0x8000)
4881 as_bad ("PIC code offset overflow (max 16 signed bits)");
4882 if (reg_needs_delay (GP
))
4887 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4888 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4890 mips_opts
.isa
< 3 ? "addu" : "daddu",
4891 "d,v,t", tempreg
, tempreg
, GP
);
4892 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4893 mips_opts
.isa
< 3 ? "lw" : "ld",
4894 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4896 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4897 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4898 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4901 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4904 macro_build (p
, &icnt
, &offset_expr
,
4905 mips_opts
.isa
< 3 ? "lw" : "ld",
4906 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4908 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4910 macro_build (p
, &icnt
, &offset_expr
,
4911 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4912 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4914 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4915 mips_opts
.isa
< 3 ? "addu" : "daddu",
4916 "d,v,t", tempreg
, tempreg
, breg
);
4917 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4918 (int) BFD_RELOC_LO16
, tempreg
);
4920 else if (mips_pic
== EMBEDDED_PIC
)
4922 /* If there is no base register, we want
4923 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4924 If there is a base register, we want
4925 addu $tempreg,$breg,$gp
4926 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4928 assert (offset_expr
.X_op
== O_symbol
);
4931 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4932 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4937 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4938 mips_opts
.isa
< 3 ? "addu" : "daddu",
4939 "d,v,t", tempreg
, breg
, GP
);
4940 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4941 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4954 load_register (&icnt
, treg
, &imm_expr
, 0);
4958 load_register (&icnt
, treg
, &imm_expr
, 1);
4962 if (imm_expr
.X_op
== O_constant
)
4964 load_register (&icnt
, AT
, &imm_expr
, 0);
4965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4966 "mtc1", "t,G", AT
, treg
);
4971 assert (offset_expr
.X_op
== O_symbol
4972 && strcmp (segment_name (S_GET_SEGMENT
4973 (offset_expr
.X_add_symbol
)),
4975 && offset_expr
.X_add_number
== 0);
4976 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4977 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4982 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
4983 the entire value, and in mips1 mode it is the high order 32
4984 bits of the value and the low order 32 bits are either zero
4985 or in offset_expr. */
4986 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
4988 load_register (&icnt
, treg
, &imm_expr
, mips_opts
.isa
>= 3);
4989 if (mips_opts
.isa
< 3 && treg
!= 31)
4991 if (offset_expr
.X_op
== O_absent
)
4992 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
4996 assert (offset_expr
.X_op
== O_constant
);
4997 load_register (&icnt
, treg
+ 1, &offset_expr
, 0);
5003 /* We know that sym is in the .rdata section. First we get the
5004 upper 16 bits of the address. */
5005 if (mips_pic
== NO_PIC
)
5007 /* FIXME: This won't work for a 64 bit address. */
5008 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5010 else if (mips_pic
== SVR4_PIC
)
5012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5013 mips_opts
.isa
< 3 ? "lw" : "ld",
5014 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5016 else if (mips_pic
== EMBEDDED_PIC
)
5018 /* For embedded PIC we pick up the entire address off $gp in
5019 a single instruction. */
5020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5021 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5022 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5023 offset_expr
.X_op
= O_constant
;
5024 offset_expr
.X_add_number
= 0;
5029 /* Now we load the register(s). */
5030 if (mips_opts
.isa
>= 3)
5031 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5032 treg
, (int) BFD_RELOC_LO16
, AT
);
5035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5036 treg
, (int) BFD_RELOC_LO16
, AT
);
5039 /* FIXME: How in the world do we deal with the possible
5041 offset_expr
.X_add_number
+= 4;
5042 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5043 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5047 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5048 does not become a variant frag. */
5049 frag_wane (frag_now
);
5055 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5056 the entire value, and in mips1 mode it is the high order 32
5057 bits of the value and the low order 32 bits are either zero
5058 or in offset_expr. */
5059 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5061 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5062 if (mips_opts
.isa
>= 3)
5063 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5064 "dmtc1", "t,S", AT
, treg
);
5067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5068 "mtc1", "t,G", AT
, treg
+ 1);
5069 if (offset_expr
.X_op
== O_absent
)
5070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5071 "mtc1", "t,G", 0, treg
);
5074 assert (offset_expr
.X_op
== O_constant
);
5075 load_register (&icnt
, AT
, &offset_expr
, 0);
5076 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5077 "mtc1", "t,G", AT
, treg
);
5083 assert (offset_expr
.X_op
== O_symbol
5084 && offset_expr
.X_add_number
== 0);
5085 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5086 if (strcmp (s
, ".lit8") == 0)
5088 if (mips_opts
.isa
>= 2)
5090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5091 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5095 r
= BFD_RELOC_MIPS_LITERAL
;
5100 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5101 if (mips_pic
== SVR4_PIC
)
5102 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5103 mips_opts
.isa
< 3 ? "lw" : "ld",
5104 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5107 /* FIXME: This won't work for a 64 bit address. */
5108 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5111 if (mips_opts
.isa
>= 2)
5113 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5114 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5116 /* To avoid confusion in tc_gen_reloc, we must ensure
5117 that this does not become a variant frag. */
5118 frag_wane (frag_now
);
5129 /* Even on a big endian machine $fn comes before $fn+1. We have
5130 to adjust when loading from memory. */
5133 assert (mips_opts
.isa
< 2);
5134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5135 target_big_endian
? treg
+ 1 : treg
,
5137 /* FIXME: A possible overflow which I don't know how to deal
5139 offset_expr
.X_add_number
+= 4;
5140 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5141 target_big_endian
? treg
: treg
+ 1,
5144 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5145 does not become a variant frag. */
5146 frag_wane (frag_now
);
5155 * The MIPS assembler seems to check for X_add_number not
5156 * being double aligned and generating:
5159 * addiu at,at,%lo(foo+1)
5162 * But, the resulting address is the same after relocation so why
5163 * generate the extra instruction?
5165 /* Itbl support may require additional care here. */
5167 if (mips_opts
.isa
>= 2)
5178 if (mips_opts
.isa
>= 2)
5186 /* Itbl support may require additional care here. */
5191 if (mips_opts
.isa
>= 3)
5202 if (mips_opts
.isa
>= 3)
5212 if (offset_expr
.X_op
!= O_symbol
5213 && offset_expr
.X_op
!= O_constant
)
5215 as_bad ("expression too complex");
5216 offset_expr
.X_op
= O_constant
;
5219 /* Even on a big endian machine $fn comes before $fn+1. We have
5220 to adjust when loading from memory. We set coproc if we must
5221 load $fn+1 first. */
5222 /* Itbl support may require additional care here. */
5223 if (! target_big_endian
)
5226 if (mips_pic
== NO_PIC
5227 || offset_expr
.X_op
== O_constant
)
5229 /* If this is a reference to a GP relative symbol, we want
5230 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5231 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5232 If we have a base register, we use this
5234 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5235 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5236 If this is not a GP relative symbol, we want
5237 lui $at,<sym> (BFD_RELOC_HI16_S)
5238 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5239 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5240 If there is a base register, we add it to $at after the
5241 lui instruction. If there is a constant, we always use
5243 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5244 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5264 mips_opts
.isa
< 3 ? "addu" : "daddu",
5265 "d,v,t", AT
, breg
, GP
);
5271 /* Itbl support may require additional care here. */
5272 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5273 coproc
? treg
+ 1 : treg
,
5274 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5275 offset_expr
.X_add_number
+= 4;
5277 /* Set mips_optimize to 2 to avoid inserting an
5279 hold_mips_optimize
= mips_optimize
;
5281 /* Itbl support may require additional care here. */
5282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5283 coproc
? treg
: treg
+ 1,
5284 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5285 mips_optimize
= hold_mips_optimize
;
5287 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5288 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5289 used_at
&& mips_opts
.noat
),
5290 offset_expr
.X_add_symbol
, (offsetT
) 0,
5293 /* We just generated two relocs. When tc_gen_reloc
5294 handles this case, it will skip the first reloc and
5295 handle the second. The second reloc already has an
5296 extra addend of 4, which we added above. We must
5297 subtract it out, and then subtract another 4 to make
5298 the first reloc come out right. The second reloc
5299 will come out right because we are going to add 4 to
5300 offset_expr when we build its instruction below. */
5301 offset_expr
.X_add_number
-= 8;
5302 offset_expr
.X_op
= O_constant
;
5304 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5309 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5310 mips_opts
.isa
< 3 ? "addu" : "daddu",
5311 "d,v,t", AT
, breg
, AT
);
5315 /* Itbl support may require additional care here. */
5316 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5317 coproc
? treg
+ 1 : treg
,
5318 (int) BFD_RELOC_LO16
, AT
);
5321 /* FIXME: How do we handle overflow here? */
5322 offset_expr
.X_add_number
+= 4;
5323 /* Itbl support may require additional care here. */
5324 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5325 coproc
? treg
: treg
+ 1,
5326 (int) BFD_RELOC_LO16
, AT
);
5328 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5332 /* If this is a reference to an external symbol, we want
5333 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5338 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5340 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5341 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5342 If there is a base register we add it to $at before the
5343 lwc1 instructions. If there is a constant we include it
5344 in the lwc1 instructions. */
5346 expr1
.X_add_number
= offset_expr
.X_add_number
;
5347 offset_expr
.X_add_number
= 0;
5348 if (expr1
.X_add_number
< -0x8000
5349 || expr1
.X_add_number
>= 0x8000 - 4)
5350 as_bad ("PIC code offset overflow (max 16 signed bits)");
5355 frag_grow (24 + off
);
5356 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5357 mips_opts
.isa
< 3 ? "lw" : "ld",
5358 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5359 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5361 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5362 mips_opts
.isa
< 3 ? "addu" : "daddu",
5363 "d,v,t", AT
, breg
, AT
);
5364 /* Itbl support may require additional care here. */
5365 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5366 coproc
? treg
+ 1 : treg
,
5367 (int) BFD_RELOC_LO16
, AT
);
5368 expr1
.X_add_number
+= 4;
5370 /* Set mips_optimize to 2 to avoid inserting an undesired
5372 hold_mips_optimize
= mips_optimize
;
5374 /* Itbl support may require additional care here. */
5375 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5376 coproc
? treg
: treg
+ 1,
5377 (int) BFD_RELOC_LO16
, AT
);
5378 mips_optimize
= hold_mips_optimize
;
5380 (void) frag_var (rs_machine_dependent
, 0, 0,
5381 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5382 offset_expr
.X_add_symbol
, (offsetT
) 0,
5385 else if (mips_pic
== SVR4_PIC
)
5389 /* If this is a reference to an external symbol, we want
5390 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5392 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5397 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5399 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5400 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5401 If there is a base register we add it to $at before the
5402 lwc1 instructions. If there is a constant we include it
5403 in the lwc1 instructions. */
5405 expr1
.X_add_number
= offset_expr
.X_add_number
;
5406 offset_expr
.X_add_number
= 0;
5407 if (expr1
.X_add_number
< -0x8000
5408 || expr1
.X_add_number
>= 0x8000 - 4)
5409 as_bad ("PIC code offset overflow (max 16 signed bits)");
5410 if (reg_needs_delay (GP
))
5419 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5420 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5422 mips_opts
.isa
< 3 ? "addu" : "daddu",
5423 "d,v,t", AT
, AT
, GP
);
5424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5425 mips_opts
.isa
< 3 ? "lw" : "ld",
5426 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5427 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5429 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5430 mips_opts
.isa
< 3 ? "addu" : "daddu",
5431 "d,v,t", AT
, breg
, AT
);
5432 /* Itbl support may require additional care here. */
5433 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5434 coproc
? treg
+ 1 : treg
,
5435 (int) BFD_RELOC_LO16
, AT
);
5436 expr1
.X_add_number
+= 4;
5438 /* Set mips_optimize to 2 to avoid inserting an undesired
5440 hold_mips_optimize
= mips_optimize
;
5442 /* Itbl support may require additional care here. */
5443 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5444 coproc
? treg
: treg
+ 1,
5445 (int) BFD_RELOC_LO16
, AT
);
5446 mips_optimize
= hold_mips_optimize
;
5447 expr1
.X_add_number
-= 4;
5449 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5450 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5451 8 + gpdel
+ off
, 1, 0),
5452 offset_expr
.X_add_symbol
, (offsetT
) 0,
5456 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5459 macro_build (p
, &icnt
, &offset_expr
,
5460 mips_opts
.isa
< 3 ? "lw" : "ld",
5461 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5463 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5467 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5468 mips_opts
.isa
< 3 ? "addu" : "daddu",
5469 "d,v,t", AT
, breg
, AT
);
5472 /* Itbl support may require additional care here. */
5473 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5474 coproc
? treg
+ 1 : treg
,
5475 (int) BFD_RELOC_LO16
, AT
);
5477 expr1
.X_add_number
+= 4;
5479 /* Set mips_optimize to 2 to avoid inserting an undesired
5481 hold_mips_optimize
= mips_optimize
;
5483 /* Itbl support may require additional care here. */
5484 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5485 coproc
? treg
: treg
+ 1,
5486 (int) BFD_RELOC_LO16
, AT
);
5487 mips_optimize
= hold_mips_optimize
;
5489 else if (mips_pic
== EMBEDDED_PIC
)
5491 /* If there is no base register, we use
5492 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5493 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5494 If we have a base register, we use
5496 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5497 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5507 mips_opts
.isa
< 3 ? "addu" : "daddu",
5508 "d,v,t", AT
, breg
, GP
);
5513 /* Itbl support may require additional care here. */
5514 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5515 coproc
? treg
+ 1 : treg
,
5516 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5517 offset_expr
.X_add_number
+= 4;
5518 /* Itbl support may require additional care here. */
5519 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5520 coproc
? treg
: treg
+ 1,
5521 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5537 assert (mips_opts
.isa
< 3);
5538 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5539 (int) BFD_RELOC_LO16
, breg
);
5540 offset_expr
.X_add_number
+= 4;
5541 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5542 (int) BFD_RELOC_LO16
, breg
);
5545 /* New code added to support COPZ instructions.
5546 This code builds table entries out of the macros in mip_opcodes.
5547 R4000 uses interlocks to handle coproc delays.
5548 Other chips (like the R3000) require nops to be inserted for delays.
5550 FIXME: Currently, we require that the user handle delays.
5551 In order to fill delay slots for non-interlocked chips,
5552 we must have a way to specify delays based on the coprocessor.
5553 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5554 What are the side-effects of the cop instruction?
5555 What cache support might we have and what are its effects?
5556 Both coprocessor & memory require delays. how long???
5557 What registers are read/set/modified?
5559 If an itbl is provided to interpret cop instructions,
5560 this knowledge can be encoded in the itbl spec. */
5574 /* For now we just do C (same as Cz). */
5575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5578 #ifdef LOSING_COMPILER
5580 /* Try and see if this is a new itbl instruction.
5581 This code builds table entries out of the macros in mip_opcodes.
5582 FIXME: For now we just assemble the expression and pass it's
5583 value along as a 32-bit immediate.
5584 We may want to have the assembler assemble this value,
5585 so that we gain the assembler's knowledge of delay slots,
5587 Would it be more efficient to use mask (id) here? */
5588 if (itbl_have_entries
5589 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5591 s
= ip
->insn_mo
->name
;
5593 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5594 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5601 as_warn ("Macro used $at after \".set noat\"");
5606 struct mips_cl_insn
*ip
;
5608 register int treg
, sreg
, dreg
, breg
;
5623 bfd_reloc_code_real_type r
;
5626 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5627 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5628 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5629 mask
= ip
->insn_mo
->mask
;
5631 expr1
.X_op
= O_constant
;
5632 expr1
.X_op_symbol
= NULL
;
5633 expr1
.X_add_symbol
= NULL
;
5634 expr1
.X_add_number
= 1;
5638 #endif /* LOSING_COMPILER */
5643 macro_build ((char *) NULL
, &icnt
, NULL
,
5644 dbl
? "dmultu" : "multu",
5646 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5652 /* The MIPS assembler some times generates shifts and adds. I'm
5653 not trying to be that fancy. GCC should do this for us
5655 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5656 macro_build ((char *) NULL
, &icnt
, NULL
,
5657 dbl
? "dmult" : "mult",
5659 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5665 mips_emit_delays (true);
5666 ++mips_opts
.noreorder
;
5667 mips_any_noreorder
= 1;
5668 macro_build ((char *) NULL
, &icnt
, NULL
,
5669 dbl
? "dmult" : "mult",
5671 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5672 macro_build ((char *) NULL
, &icnt
, NULL
,
5673 dbl
? "dsra32" : "sra",
5674 "d,w,<", dreg
, dreg
, 31);
5675 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5677 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5680 expr1
.X_add_number
= 8;
5681 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5682 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5683 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5685 --mips_opts
.noreorder
;
5686 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5692 mips_emit_delays (true);
5693 ++mips_opts
.noreorder
;
5694 mips_any_noreorder
= 1;
5695 macro_build ((char *) NULL
, &icnt
, NULL
,
5696 dbl
? "dmultu" : "multu",
5698 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5699 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5701 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5704 expr1
.X_add_number
= 8;
5705 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5706 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5707 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5709 --mips_opts
.noreorder
;
5713 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5714 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5715 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5717 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5721 if (imm_expr
.X_op
!= O_constant
)
5722 as_bad ("rotate count too large");
5723 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5724 (int) (imm_expr
.X_add_number
& 0x1f));
5725 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5726 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5727 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5731 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5732 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5733 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5735 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5739 if (imm_expr
.X_op
!= O_constant
)
5740 as_bad ("rotate count too large");
5741 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5742 (int) (imm_expr
.X_add_number
& 0x1f));
5743 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5744 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5745 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5749 assert (mips_opts
.isa
< 2);
5750 /* Even on a big endian machine $fn comes before $fn+1. We have
5751 to adjust when storing to memory. */
5752 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5753 target_big_endian
? treg
+ 1 : treg
,
5754 (int) BFD_RELOC_LO16
, breg
);
5755 offset_expr
.X_add_number
+= 4;
5756 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5757 target_big_endian
? treg
: treg
+ 1,
5758 (int) BFD_RELOC_LO16
, breg
);
5763 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5764 treg
, (int) BFD_RELOC_LO16
);
5766 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5767 sreg
, (int) BFD_RELOC_LO16
);
5770 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5772 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5773 dreg
, (int) BFD_RELOC_LO16
);
5778 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5780 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5781 sreg
, (int) BFD_RELOC_LO16
);
5786 as_warn ("Instruction %s: result is always false",
5788 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5791 if (imm_expr
.X_op
== O_constant
5792 && imm_expr
.X_add_number
>= 0
5793 && imm_expr
.X_add_number
< 0x10000)
5795 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5796 sreg
, (int) BFD_RELOC_LO16
);
5799 else if (imm_expr
.X_op
== O_constant
5800 && imm_expr
.X_add_number
> -0x8000
5801 && imm_expr
.X_add_number
< 0)
5803 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5804 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5805 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5806 "t,r,j", dreg
, sreg
,
5807 (int) BFD_RELOC_LO16
);
5812 load_register (&icnt
, AT
, &imm_expr
, 0);
5813 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5817 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5818 (int) BFD_RELOC_LO16
);
5823 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5829 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5830 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5831 (int) BFD_RELOC_LO16
);
5834 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5836 if (imm_expr
.X_op
== O_constant
5837 && imm_expr
.X_add_number
>= -0x8000
5838 && imm_expr
.X_add_number
< 0x8000)
5840 macro_build ((char *) NULL
, &icnt
, &expr1
,
5841 mask
== M_SGE_I
? "slti" : "sltiu",
5842 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5847 load_register (&icnt
, AT
, &imm_expr
, 0);
5848 macro_build ((char *) NULL
, &icnt
, NULL
,
5849 mask
== M_SGE_I
? "slt" : "sltu",
5850 "d,v,t", dreg
, sreg
, AT
);
5853 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5854 (int) BFD_RELOC_LO16
);
5859 case M_SGT
: /* sreg > treg <==> treg < sreg */
5865 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5868 case M_SGT_I
: /* sreg > I <==> I < sreg */
5874 load_register (&icnt
, AT
, &imm_expr
, 0);
5875 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5878 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5884 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5885 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5886 (int) BFD_RELOC_LO16
);
5889 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5895 load_register (&icnt
, AT
, &imm_expr
, 0);
5896 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5897 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5898 (int) BFD_RELOC_LO16
);
5902 if (imm_expr
.X_op
== O_constant
5903 && imm_expr
.X_add_number
>= -0x8000
5904 && imm_expr
.X_add_number
< 0x8000)
5906 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5907 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5910 load_register (&icnt
, AT
, &imm_expr
, 0);
5911 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5915 if (imm_expr
.X_op
== O_constant
5916 && imm_expr
.X_add_number
>= -0x8000
5917 && imm_expr
.X_add_number
< 0x8000)
5919 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5920 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5923 load_register (&icnt
, AT
, &imm_expr
, 0);
5924 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5930 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5933 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5937 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5939 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5945 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5947 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5953 as_warn ("Instruction %s: result is always true",
5955 macro_build ((char *) NULL
, &icnt
, &expr1
,
5956 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5957 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5960 if (imm_expr
.X_op
== O_constant
5961 && imm_expr
.X_add_number
>= 0
5962 && imm_expr
.X_add_number
< 0x10000)
5964 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5965 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5968 else if (imm_expr
.X_op
== O_constant
5969 && imm_expr
.X_add_number
> -0x8000
5970 && imm_expr
.X_add_number
< 0)
5972 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5973 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5974 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5975 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5980 load_register (&icnt
, AT
, &imm_expr
, 0);
5981 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5985 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5993 if (imm_expr
.X_op
== O_constant
5994 && imm_expr
.X_add_number
> -0x8000
5995 && imm_expr
.X_add_number
<= 0x8000)
5997 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5998 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5999 dbl
? "daddi" : "addi",
6000 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6003 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6004 macro_build ((char *) NULL
, &icnt
, NULL
,
6005 dbl
? "dsub" : "sub",
6006 "d,v,t", dreg
, sreg
, AT
);
6012 if (imm_expr
.X_op
== O_constant
6013 && imm_expr
.X_add_number
> -0x8000
6014 && imm_expr
.X_add_number
<= 0x8000)
6016 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6017 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6018 dbl
? "daddiu" : "addiu",
6019 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6022 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6023 macro_build ((char *) NULL
, &icnt
, NULL
,
6024 dbl
? "dsubu" : "subu",
6025 "d,v,t", dreg
, sreg
, AT
);
6046 load_register (&icnt
, AT
, &imm_expr
, 0);
6047 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6052 assert (mips_opts
.isa
< 2);
6053 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6054 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6057 * Is the double cfc1 instruction a bug in the mips assembler;
6058 * or is there a reason for it?
6060 mips_emit_delays (true);
6061 ++mips_opts
.noreorder
;
6062 mips_any_noreorder
= 1;
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6064 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6066 expr1
.X_add_number
= 3;
6067 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6068 (int) BFD_RELOC_LO16
);
6069 expr1
.X_add_number
= 2;
6070 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6071 (int) BFD_RELOC_LO16
);
6072 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6073 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6074 macro_build ((char *) NULL
, &icnt
, NULL
,
6075 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6076 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6078 --mips_opts
.noreorder
;
6087 if (offset_expr
.X_add_number
>= 0x7fff)
6088 as_bad ("operand overflow");
6089 /* avoid load delay */
6090 if (! target_big_endian
)
6091 offset_expr
.X_add_number
+= 1;
6092 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6093 (int) BFD_RELOC_LO16
, breg
);
6094 if (! target_big_endian
)
6095 offset_expr
.X_add_number
-= 1;
6097 offset_expr
.X_add_number
+= 1;
6098 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6099 (int) BFD_RELOC_LO16
, breg
);
6100 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6101 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6114 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6115 as_bad ("operand overflow");
6116 if (! target_big_endian
)
6117 offset_expr
.X_add_number
+= off
;
6118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6119 (int) BFD_RELOC_LO16
, breg
);
6120 if (! target_big_endian
)
6121 offset_expr
.X_add_number
-= off
;
6123 offset_expr
.X_add_number
+= off
;
6124 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6125 (int) BFD_RELOC_LO16
, breg
);
6138 load_address (&icnt
, AT
, &offset_expr
);
6140 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6141 mips_opts
.isa
< 3 ? "addu" : "daddu",
6142 "d,v,t", AT
, AT
, breg
);
6143 if (! target_big_endian
)
6144 expr1
.X_add_number
= off
;
6146 expr1
.X_add_number
= 0;
6147 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6148 (int) BFD_RELOC_LO16
, AT
);
6149 if (! target_big_endian
)
6150 expr1
.X_add_number
= 0;
6152 expr1
.X_add_number
= off
;
6153 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6154 (int) BFD_RELOC_LO16
, AT
);
6159 load_address (&icnt
, AT
, &offset_expr
);
6161 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6162 mips_opts
.isa
< 3 ? "addu" : "daddu",
6163 "d,v,t", AT
, AT
, breg
);
6164 if (target_big_endian
)
6165 expr1
.X_add_number
= 0;
6166 macro_build ((char *) NULL
, &icnt
, &expr1
,
6167 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6168 (int) BFD_RELOC_LO16
, AT
);
6169 if (target_big_endian
)
6170 expr1
.X_add_number
= 1;
6172 expr1
.X_add_number
= 0;
6173 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6174 (int) BFD_RELOC_LO16
, AT
);
6175 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6177 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6182 if (offset_expr
.X_add_number
>= 0x7fff)
6183 as_bad ("operand overflow");
6184 if (target_big_endian
)
6185 offset_expr
.X_add_number
+= 1;
6186 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6187 (int) BFD_RELOC_LO16
, breg
);
6188 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6189 if (target_big_endian
)
6190 offset_expr
.X_add_number
-= 1;
6192 offset_expr
.X_add_number
+= 1;
6193 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6194 (int) BFD_RELOC_LO16
, breg
);
6207 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6208 as_bad ("operand overflow");
6209 if (! target_big_endian
)
6210 offset_expr
.X_add_number
+= off
;
6211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6212 (int) BFD_RELOC_LO16
, breg
);
6213 if (! target_big_endian
)
6214 offset_expr
.X_add_number
-= off
;
6216 offset_expr
.X_add_number
+= off
;
6217 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6218 (int) BFD_RELOC_LO16
, breg
);
6231 load_address (&icnt
, AT
, &offset_expr
);
6233 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6234 mips_opts
.isa
< 3 ? "addu" : "daddu",
6235 "d,v,t", AT
, AT
, breg
);
6236 if (! target_big_endian
)
6237 expr1
.X_add_number
= off
;
6239 expr1
.X_add_number
= 0;
6240 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6241 (int) BFD_RELOC_LO16
, AT
);
6242 if (! target_big_endian
)
6243 expr1
.X_add_number
= 0;
6245 expr1
.X_add_number
= off
;
6246 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6247 (int) BFD_RELOC_LO16
, AT
);
6251 load_address (&icnt
, AT
, &offset_expr
);
6253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6254 mips_opts
.isa
< 3 ? "addu" : "daddu",
6255 "d,v,t", AT
, AT
, breg
);
6256 if (! target_big_endian
)
6257 expr1
.X_add_number
= 0;
6258 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6259 (int) BFD_RELOC_LO16
, AT
);
6260 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6262 if (! target_big_endian
)
6263 expr1
.X_add_number
= 1;
6265 expr1
.X_add_number
= 0;
6266 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6267 (int) BFD_RELOC_LO16
, AT
);
6268 if (! target_big_endian
)
6269 expr1
.X_add_number
= 0;
6271 expr1
.X_add_number
= 1;
6272 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6273 (int) BFD_RELOC_LO16
, AT
);
6274 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6276 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6281 /* FIXME: Check if this is one of the itbl macros, since they
6282 are added dynamically. */
6283 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6287 as_warn ("Macro used $at after \".set noat\"");
6290 /* Implement macros in mips16 mode. */
6294 struct mips_cl_insn
*ip
;
6297 int xreg
, yreg
, zreg
, tmp
;
6301 const char *s
, *s2
, *s3
;
6303 mask
= ip
->insn_mo
->mask
;
6305 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6306 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6307 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6311 expr1
.X_op
= O_constant
;
6312 expr1
.X_op_symbol
= NULL
;
6313 expr1
.X_add_symbol
= NULL
;
6314 expr1
.X_add_number
= 1;
6333 mips_emit_delays (true);
6334 ++mips_opts
.noreorder
;
6335 mips_any_noreorder
= 1;
6336 macro_build ((char *) NULL
, &icnt
, NULL
,
6337 dbl
? "ddiv" : "div",
6338 "0,x,y", xreg
, yreg
);
6339 expr1
.X_add_number
= 2;
6340 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6341 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6342 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6343 since that causes an overflow. We should do that as well,
6344 but I don't see how to do the comparisons without a temporary
6346 --mips_opts
.noreorder
;
6347 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6366 mips_emit_delays (true);
6367 ++mips_opts
.noreorder
;
6368 mips_any_noreorder
= 1;
6369 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6370 expr1
.X_add_number
= 2;
6371 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6372 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6373 --mips_opts
.noreorder
;
6374 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6380 macro_build ((char *) NULL
, &icnt
, NULL
,
6381 dbl
? "dmultu" : "multu",
6383 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6391 if (imm_expr
.X_op
!= O_constant
)
6392 as_bad ("Unsupported large constant");
6393 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6394 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6395 dbl
? "daddiu" : "addiu",
6396 "y,x,4", yreg
, xreg
);
6400 if (imm_expr
.X_op
!= O_constant
)
6401 as_bad ("Unsupported large constant");
6402 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6403 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6408 if (imm_expr
.X_op
!= O_constant
)
6409 as_bad ("Unsupported large constant");
6410 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6411 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6434 goto do_reverse_branch
;
6438 goto do_reverse_branch
;
6450 goto do_reverse_branch
;
6461 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6463 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6490 goto do_addone_branch_i
;
6495 goto do_addone_branch_i
;
6510 goto do_addone_branch_i
;
6517 if (imm_expr
.X_op
!= O_constant
)
6518 as_bad ("Unsupported large constant");
6519 ++imm_expr
.X_add_number
;
6522 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6523 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6527 expr1
.X_add_number
= 0;
6528 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6530 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6531 "move", "y,X", xreg
, yreg
);
6532 expr1
.X_add_number
= 2;
6533 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6535 "neg", "x,w", xreg
, xreg
);
6539 /* This routine assembles an instruction into its binary format. As a
6540 side effect, it sets one of the global variables imm_reloc or
6541 offset_reloc to the type of relocation to do if one of the operands
6542 is an address expression. */
6547 struct mips_cl_insn
*ip
;
6552 struct mips_opcode
*insn
;
6555 unsigned int lastregno
= 0;
6560 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6565 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6567 insn_error
= "unrecognized opcode";
6575 assert (strcmp (insn
->name
, str
) == 0);
6577 if (insn
->pinfo
== INSN_MACRO
)
6578 insn_isa
= insn
->match
;
6579 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6581 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6583 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6585 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
6590 if (insn_isa
> mips_opts
.isa
6591 && (insn
->pinfo
!= INSN_MACRO
6593 && (insn
->membership
& INSN_4650
) != INSN_4650
)
6594 || (mips_4650
&& (insn
->pinfo
& FP_D
))
6596 && (insn
->membership
& INSN_4010
) != INSN_4010
)
6598 && (insn
->membership
& INSN_4100
) != INSN_4100
)
6599 /* start-sanitize-r5900 */
6601 && (insn
->membership
& INSN_5900
) != INSN_5900
)
6602 || (mips_5900
&& (insn
->pinfo
& FP_D
))
6603 /* end-sanitize-r5900 */
6605 && (insn
->membership
& INSN_3900
) != INSN_3900
))))
6607 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6608 && strcmp (insn
->name
, insn
[1].name
) == 0)
6613 if (insn_isa
<= mips_opts
.isa
)
6614 insn_error
= "opcode not supported on this processor";
6617 static char buf
[100];
6619 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6626 ip
->insn_opcode
= insn
->match
;
6627 for (args
= insn
->args
;; ++args
)
6633 case '\0': /* end of args */
6646 ip
->insn_opcode
|= lastregno
<< 21;
6651 ip
->insn_opcode
|= lastregno
<< 16;
6655 ip
->insn_opcode
|= lastregno
<< 11;
6661 /* handle optional base register.
6662 Either the base register is omitted or
6663 we must have a left paren. */
6664 /* this is dependent on the next operand specifier
6665 is a 'b' for base register */
6666 assert (args
[1] == 'b');
6670 case ')': /* these must match exactly */
6675 case '<': /* must be at least one digit */
6677 * According to the manual, if the shift amount is greater
6678 * than 31 or less than 0 the the shift amount should be
6679 * mod 32. In reality the mips assembler issues an error.
6680 * We issue a warning and mask out all but the low 5 bits.
6682 my_getExpression (&imm_expr
, s
);
6683 check_absolute_expr (ip
, &imm_expr
);
6684 if ((unsigned long) imm_expr
.X_add_number
> 31)
6686 as_warn ("Improper shift amount (%ld)",
6687 (long) imm_expr
.X_add_number
);
6688 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6690 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6691 imm_expr
.X_op
= O_absent
;
6695 case '>': /* shift amount minus 32 */
6696 my_getExpression (&imm_expr
, s
);
6697 check_absolute_expr (ip
, &imm_expr
);
6698 if ((unsigned long) imm_expr
.X_add_number
< 32
6699 || (unsigned long) imm_expr
.X_add_number
> 63)
6701 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6702 imm_expr
.X_op
= O_absent
;
6706 case 'k': /* cache code */
6707 case 'h': /* prefx code */
6708 my_getExpression (&imm_expr
, s
);
6709 check_absolute_expr (ip
, &imm_expr
);
6710 if ((unsigned long) imm_expr
.X_add_number
> 31)
6712 as_warn ("Invalid value for `%s' (%lu)",
6714 (unsigned long) imm_expr
.X_add_number
);
6715 imm_expr
.X_add_number
&= 0x1f;
6718 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6720 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6721 imm_expr
.X_op
= O_absent
;
6725 case 'c': /* break code */
6726 my_getExpression (&imm_expr
, s
);
6727 check_absolute_expr (ip
, &imm_expr
);
6728 if ((unsigned) imm_expr
.X_add_number
> 1023)
6729 as_warn ("Illegal break code (%ld)",
6730 (long) imm_expr
.X_add_number
);
6731 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6732 imm_expr
.X_op
= O_absent
;
6736 case 'B': /* syscall code */
6737 my_getExpression (&imm_expr
, s
);
6738 check_absolute_expr (ip
, &imm_expr
);
6739 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6740 as_warn ("Illegal syscall code (%ld)",
6741 (long) imm_expr
.X_add_number
);
6742 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6743 imm_expr
.X_op
= O_absent
;
6747 case 'C': /* Coprocessor code */
6748 my_getExpression (&imm_expr
, s
);
6749 check_absolute_expr (ip
, &imm_expr
);
6750 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6752 as_warn ("Coproccesor code > 25 bits (%ld)",
6753 (long) imm_expr
.X_add_number
);
6754 imm_expr
.X_add_number
&= ((1<<25) - 1);
6756 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6757 imm_expr
.X_op
= O_absent
;
6761 case 'b': /* base register */
6762 case 'd': /* destination register */
6763 case 's': /* source register */
6764 case 't': /* target register */
6765 case 'r': /* both target and source */
6766 case 'v': /* both dest and source */
6767 case 'w': /* both dest and target */
6768 case 'E': /* coprocessor target register */
6769 case 'G': /* coprocessor destination register */
6770 case 'x': /* ignore register name */
6771 case 'z': /* must be zero register */
6785 while (isdigit (*s
));
6787 as_bad ("Invalid register number (%d)", regno
);
6789 else if (*args
== 'E' || *args
== 'G')
6793 if (s
[1] == 'f' && s
[2] == 'p')
6798 else if (s
[1] == 's' && s
[2] == 'p')
6803 else if (s
[1] == 'g' && s
[2] == 'p')
6808 else if (s
[1] == 'a' && s
[2] == 't')
6813 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6818 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6823 else if (itbl_have_entries
)
6828 p
= s
+1; /* advance past '$' */
6829 n
= itbl_get_field (&p
); /* n is name */
6831 /* See if this is a register defined in an
6833 r
= itbl_get_reg_val (n
);
6836 /* Get_field advances to the start of
6837 the next field, so we need to back
6838 rack to the end of the last field. */
6842 s
= strchr (s
,'\0');
6855 as_warn ("Used $at without \".set noat\"");
6861 if (c
== 'r' || c
== 'v' || c
== 'w')
6868 /* 'z' only matches $0. */
6869 if (c
== 'z' && regno
!= 0)
6872 /* Now that we have assembled one operand, we use the args string
6873 * to figure out where it goes in the instruction. */
6880 ip
->insn_opcode
|= regno
<< 21;
6884 ip
->insn_opcode
|= regno
<< 11;
6889 ip
->insn_opcode
|= regno
<< 16;
6892 /* This case exists because on the r3000 trunc
6893 expands into a macro which requires a gp
6894 register. On the r6000 or r4000 it is
6895 assembled into a single instruction which
6896 ignores the register. Thus the insn version
6897 is MIPS_ISA2 and uses 'x', and the macro
6898 version is MIPS_ISA1 and uses 't'. */
6901 /* This case is for the div instruction, which
6902 acts differently if the destination argument
6903 is $0. This only matches $0, and is checked
6904 outside the switch. */
6907 /* Itbl operand; not yet implemented. FIXME ?? */
6909 /* What about all other operands like 'i', which
6910 can be specified in the opcode table? */
6920 ip
->insn_opcode
|= lastregno
<< 21;
6923 ip
->insn_opcode
|= lastregno
<< 16;
6928 case 'D': /* floating point destination register */
6929 case 'S': /* floating point source register */
6930 case 'T': /* floating point target register */
6931 case 'R': /* floating point source register */
6935 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6945 while (isdigit (*s
));
6948 as_bad ("Invalid float register number (%d)", regno
);
6950 if ((regno
& 1) != 0
6951 && mips_opts
.isa
< 3
6952 && ! (strcmp (str
, "mtc1") == 0
6953 || strcmp (str
, "mfc1") == 0
6954 || strcmp (str
, "lwc1") == 0
6955 || strcmp (str
, "swc1") == 0
6956 || strcmp (str
, "l.s") == 0
6957 || strcmp (str
, "s.s") == 0))
6958 as_warn ("Float register should be even, was %d",
6966 if (c
== 'V' || c
== 'W')
6976 ip
->insn_opcode
|= regno
<< 6;
6980 ip
->insn_opcode
|= regno
<< 11;
6984 ip
->insn_opcode
|= regno
<< 16;
6987 ip
->insn_opcode
|= regno
<< 21;
6996 ip
->insn_opcode
|= lastregno
<< 11;
6999 ip
->insn_opcode
|= lastregno
<< 16;
7005 my_getExpression (&imm_expr
, s
);
7006 if (imm_expr
.X_op
!= O_big
7007 && imm_expr
.X_op
!= O_constant
)
7008 insn_error
= "absolute expression required";
7013 my_getExpression (&offset_expr
, s
);
7014 imm_reloc
= BFD_RELOC_32
;
7026 unsigned char temp
[8];
7028 unsigned int length
;
7033 /* These only appear as the last operand in an
7034 instruction, and every instruction that accepts
7035 them in any variant accepts them in all variants.
7036 This means we don't have to worry about backing out
7037 any changes if the instruction does not match.
7039 The difference between them is the size of the
7040 floating point constant and where it goes. For 'F'
7041 and 'L' the constant is 64 bits; for 'f' and 'l' it
7042 is 32 bits. Where the constant is placed is based
7043 on how the MIPS assembler does things:
7046 f -- immediate value
7049 The .lit4 and .lit8 sections are only used if
7050 permitted by the -G argument.
7052 When generating embedded PIC code, we use the
7053 .lit8 section but not the .lit4 section (we can do
7054 .lit4 inline easily; we need to put .lit8
7055 somewhere in the data segment, and using .lit8
7056 permits the linker to eventually combine identical
7059 f64
= *args
== 'F' || *args
== 'L';
7061 save_in
= input_line_pointer
;
7062 input_line_pointer
= s
;
7063 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7065 s
= input_line_pointer
;
7066 input_line_pointer
= save_in
;
7067 if (err
!= NULL
&& *err
!= '\0')
7069 as_bad ("Bad floating point constant: %s", err
);
7070 memset (temp
, '\0', sizeof temp
);
7071 length
= f64
? 8 : 4;
7074 assert (length
== (f64
? 8 : 4));
7078 && (! USE_GLOBAL_POINTER_OPT
7079 || mips_pic
== EMBEDDED_PIC
7080 || g_switch_value
< 4
7081 || (temp
[0] == 0 && temp
[1] == 0)
7082 || (temp
[2] == 0 && temp
[3] == 0))))
7084 imm_expr
.X_op
= O_constant
;
7085 if (! target_big_endian
)
7086 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7088 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7091 && ((temp
[0] == 0 && temp
[1] == 0)
7092 || (temp
[2] == 0 && temp
[3] == 0))
7093 && ((temp
[4] == 0 && temp
[5] == 0)
7094 || (temp
[6] == 0 && temp
[7] == 0)))
7096 /* The value is simple enough to load with a
7097 couple of instructions. In mips1 mode, set
7098 imm_expr to the high order 32 bits and
7099 offset_expr to the low order 32 bits.
7100 Otherwise, set imm_expr to the entire 64 bit
7102 if (mips_opts
.isa
< 3)
7104 imm_expr
.X_op
= O_constant
;
7105 offset_expr
.X_op
= O_constant
;
7106 if (! target_big_endian
)
7108 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7109 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7113 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7114 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7116 if (offset_expr
.X_add_number
== 0)
7117 offset_expr
.X_op
= O_absent
;
7119 else if (sizeof (imm_expr
.X_add_number
) > 4)
7121 imm_expr
.X_op
= O_constant
;
7122 if (! target_big_endian
)
7123 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7125 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7129 imm_expr
.X_op
= O_big
;
7130 imm_expr
.X_add_number
= 4;
7131 if (! target_big_endian
)
7133 generic_bignum
[0] = bfd_getl16 (temp
);
7134 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7135 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7136 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7140 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7141 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7142 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7143 generic_bignum
[3] = bfd_getb16 (temp
);
7149 const char *newname
;
7152 /* Switch to the right section. */
7154 subseg
= now_subseg
;
7157 default: /* unused default case avoids warnings. */
7159 newname
= RDATA_SECTION_NAME
;
7160 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7164 newname
= RDATA_SECTION_NAME
;
7167 assert (!USE_GLOBAL_POINTER_OPT
7168 || g_switch_value
>= 4);
7172 new_seg
= subseg_new (newname
, (subsegT
) 0);
7173 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7174 bfd_set_section_flags (stdoutput
, new_seg
,
7179 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7180 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7181 && strcmp (TARGET_OS
, "elf") != 0)
7182 record_alignment (new_seg
, 4);
7184 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7186 as_bad ("Can't use floating point insn in this section");
7188 /* Set the argument to the current address in the
7190 offset_expr
.X_op
= O_symbol
;
7191 offset_expr
.X_add_symbol
=
7192 symbol_new ("L0\001", now_seg
,
7193 (valueT
) frag_now_fix (), frag_now
);
7194 offset_expr
.X_add_number
= 0;
7196 /* Put the floating point number into the section. */
7197 p
= frag_more ((int) length
);
7198 memcpy (p
, temp
, length
);
7200 /* Switch back to the original section. */
7201 subseg_set (seg
, subseg
);
7206 case 'i': /* 16 bit unsigned immediate */
7207 case 'j': /* 16 bit signed immediate */
7208 imm_reloc
= BFD_RELOC_LO16
;
7209 c
= my_getSmallExpression (&imm_expr
, s
);
7214 if (imm_expr
.X_op
== O_constant
)
7215 imm_expr
.X_add_number
=
7216 (imm_expr
.X_add_number
>> 16) & 0xffff;
7219 imm_reloc
= BFD_RELOC_HI16_S
;
7220 imm_unmatched_hi
= true;
7223 imm_reloc
= BFD_RELOC_HI16
;
7228 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7229 || ((imm_expr
.X_add_number
< 0
7230 || imm_expr
.X_add_number
>= 0x10000)
7231 && imm_expr
.X_op
== O_constant
))
7233 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7234 !strcmp (insn
->name
, insn
[1].name
))
7236 if (imm_expr
.X_op
!= O_constant
7237 && imm_expr
.X_op
!= O_big
)
7238 insn_error
= "absolute expression required";
7240 as_bad ("16 bit expression not in range 0..65535");
7248 /* The upper bound should be 0x8000, but
7249 unfortunately the MIPS assembler accepts numbers
7250 from 0x8000 to 0xffff and sign extends them, and
7251 we want to be compatible. We only permit this
7252 extended range for an instruction which does not
7253 provide any further alternates, since those
7254 alternates may handle other cases. People should
7255 use the numbers they mean, rather than relying on
7256 a mysterious sign extension. */
7257 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7258 strcmp (insn
->name
, insn
[1].name
) == 0);
7263 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7264 || ((imm_expr
.X_add_number
< -0x8000
7265 || imm_expr
.X_add_number
>= max
)
7266 && imm_expr
.X_op
== O_constant
)
7268 && imm_expr
.X_add_number
< 0
7269 && mips_opts
.isa
>= 3
7270 && imm_expr
.X_unsigned
7271 && sizeof (imm_expr
.X_add_number
) <= 4))
7275 if (imm_expr
.X_op
!= O_constant
7276 && imm_expr
.X_op
!= O_big
)
7277 insn_error
= "absolute expression required";
7279 as_bad ("16 bit expression not in range -32768..32767");
7285 case 'o': /* 16 bit offset */
7286 c
= my_getSmallExpression (&offset_expr
, s
);
7288 /* If this value won't fit into a 16 bit offset, then go
7289 find a macro that will generate the 32 bit offset
7290 code pattern. As a special hack, we accept the
7291 difference of two local symbols as a constant. This
7292 is required to suppose embedded PIC switches, which
7293 use an instruction which looks like
7294 lw $4,$L12-$LS12($4)
7295 The problem with handling this in a more general
7296 fashion is that the macro function doesn't expect to
7297 see anything which can be handled in a single
7298 constant instruction. */
7300 && (offset_expr
.X_op
!= O_constant
7301 || offset_expr
.X_add_number
>= 0x8000
7302 || offset_expr
.X_add_number
< -0x8000)
7303 && (mips_pic
!= EMBEDDED_PIC
7304 || offset_expr
.X_op
!= O_subtract
7305 || now_seg
!= text_section
7306 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7310 offset_reloc
= BFD_RELOC_LO16
;
7311 if (c
== 'h' || c
== 'H')
7313 assert (offset_expr
.X_op
== O_constant
);
7314 offset_expr
.X_add_number
=
7315 (offset_expr
.X_add_number
>> 16) & 0xffff;
7320 case 'p': /* pc relative offset */
7321 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7322 my_getExpression (&offset_expr
, s
);
7326 case 'u': /* upper 16 bits */
7327 c
= my_getSmallExpression (&imm_expr
, s
);
7328 if (imm_expr
.X_op
== O_constant
7329 && (imm_expr
.X_add_number
< 0
7330 || imm_expr
.X_add_number
>= 0x10000))
7331 as_bad ("lui expression not in range 0..65535");
7332 imm_reloc
= BFD_RELOC_LO16
;
7337 if (imm_expr
.X_op
== O_constant
)
7338 imm_expr
.X_add_number
=
7339 (imm_expr
.X_add_number
>> 16) & 0xffff;
7342 imm_reloc
= BFD_RELOC_HI16_S
;
7343 imm_unmatched_hi
= true;
7346 imm_reloc
= BFD_RELOC_HI16
;
7352 case 'a': /* 26 bit address */
7353 my_getExpression (&offset_expr
, s
);
7355 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7358 case 'N': /* 3 bit branch condition code */
7359 case 'M': /* 3 bit compare condition code */
7360 if (strncmp (s
, "$fcc", 4) != 0)
7370 while (isdigit (*s
));
7372 as_bad ("invalid condition code register $fcc%d", regno
);
7374 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7376 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7380 fprintf (stderr
, "bad char = '%c'\n", *args
);
7385 /* Args don't match. */
7386 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7387 !strcmp (insn
->name
, insn
[1].name
))
7393 insn_error
= "illegal operands";
7398 /* This routine assembles an instruction into its binary format when
7399 assembling for the mips16. As a side effect, it sets one of the
7400 global variables imm_reloc or offset_reloc to the type of
7401 relocation to do if one of the operands is an address expression.
7402 It also sets mips16_small and mips16_ext if the user explicitly
7403 requested a small or extended instruction. */
7408 struct mips_cl_insn
*ip
;
7412 struct mips_opcode
*insn
;
7415 unsigned int lastregno
= 0;
7420 mips16_small
= false;
7423 for (s
= str
; islower (*s
); ++s
)
7435 if (s
[1] == 't' && s
[2] == ' ')
7438 mips16_small
= true;
7442 else if (s
[1] == 'e' && s
[2] == ' ')
7451 insn_error
= "unknown opcode";
7455 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7456 mips16_small
= true;
7458 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7460 insn_error
= "unrecognized opcode";
7467 assert (strcmp (insn
->name
, str
) == 0);
7470 ip
->insn_opcode
= insn
->match
;
7471 ip
->use_extend
= false;
7472 imm_expr
.X_op
= O_absent
;
7473 imm_reloc
= BFD_RELOC_UNUSED
;
7474 offset_expr
.X_op
= O_absent
;
7475 offset_reloc
= BFD_RELOC_UNUSED
;
7476 for (args
= insn
->args
; 1; ++args
)
7483 /* In this switch statement we call break if we did not find
7484 a match, continue if we did find a match, or return if we
7493 /* Stuff the immediate value in now, if we can. */
7494 if (imm_expr
.X_op
== O_constant
7495 && imm_reloc
> BFD_RELOC_UNUSED
7496 && insn
->pinfo
!= INSN_MACRO
)
7498 mips16_immed ((char *) NULL
, 0,
7499 imm_reloc
- BFD_RELOC_UNUSED
,
7500 imm_expr
.X_add_number
, true, mips16_small
,
7501 mips16_ext
, &ip
->insn_opcode
,
7502 &ip
->use_extend
, &ip
->extend
);
7503 imm_expr
.X_op
= O_absent
;
7504 imm_reloc
= BFD_RELOC_UNUSED
;
7518 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7521 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7537 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7539 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7566 while (isdigit (*s
));
7569 as_bad ("invalid register number (%d)", regno
);
7575 if (s
[1] == 'f' && s
[2] == 'p')
7580 else if (s
[1] == 's' && s
[2] == 'p')
7585 else if (s
[1] == 'g' && s
[2] == 'p')
7590 else if (s
[1] == 'a' && s
[2] == 't')
7595 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7600 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7613 if (c
== 'v' || c
== 'w')
7615 regno
= mips16_to_32_reg_map
[lastregno
];
7629 regno
= mips32_to_16_reg_map
[regno
];
7634 regno
= ILLEGAL_REG
;
7639 regno
= ILLEGAL_REG
;
7644 regno
= ILLEGAL_REG
;
7649 if (regno
== AT
&& ! mips_opts
.noat
)
7650 as_warn ("used $at without \".set noat\"");
7657 if (regno
== ILLEGAL_REG
)
7664 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7668 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7671 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7674 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7680 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7683 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7684 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7694 if (strncmp (s
, "$pc", 3) == 0)
7718 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7720 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7721 and generate the appropriate reloc. If the text
7722 inside %gprel is not a symbol name with an
7723 optional offset, then we generate a normal reloc
7724 and will probably fail later. */
7725 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7726 if (imm_expr
.X_op
== O_symbol
)
7729 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7731 ip
->use_extend
= true;
7738 /* Just pick up a normal expression. */
7739 my_getExpression (&imm_expr
, s
);
7742 if (imm_expr
.X_op
== O_register
)
7744 /* What we thought was an expression turned out to
7747 if (s
[0] == '(' && args
[1] == '(')
7749 /* It looks like the expression was omitted
7750 before a register indirection, which means
7751 that the expression is implicitly zero. We
7752 still set up imm_expr, so that we handle
7753 explicit extensions correctly. */
7754 imm_expr
.X_op
= O_constant
;
7755 imm_expr
.X_add_number
= 0;
7756 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7763 /* We need to relax this instruction. */
7764 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7773 /* We use offset_reloc rather than imm_reloc for the PC
7774 relative operands. This lets macros with both
7775 immediate and address operands work correctly. */
7776 my_getExpression (&offset_expr
, s
);
7778 if (offset_expr
.X_op
== O_register
)
7781 /* We need to relax this instruction. */
7782 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7786 case '6': /* break code */
7787 my_getExpression (&imm_expr
, s
);
7788 check_absolute_expr (ip
, &imm_expr
);
7789 if ((unsigned long) imm_expr
.X_add_number
> 63)
7791 as_warn ("Invalid value for `%s' (%lu)",
7793 (unsigned long) imm_expr
.X_add_number
);
7794 imm_expr
.X_add_number
&= 0x3f;
7796 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7797 imm_expr
.X_op
= O_absent
;
7801 case 'a': /* 26 bit address */
7802 my_getExpression (&offset_expr
, s
);
7804 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7805 ip
->insn_opcode
<<= 16;
7808 case 'l': /* register list for entry macro */
7809 case 'L': /* register list for exit macro */
7819 int freg
, reg1
, reg2
;
7821 while (*s
== ' ' || *s
== ',')
7825 as_bad ("can't parse register list");
7837 while (isdigit (*s
))
7859 as_bad ("invalid register list");
7864 while (isdigit (*s
))
7871 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7876 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7881 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7882 mask
|= (reg2
- 3) << 3;
7883 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7884 mask
|= (reg2
- 15) << 1;
7885 else if (reg1
== 31 && reg2
== 31)
7889 as_bad ("invalid register list");
7893 /* The mask is filled in in the opcode table for the
7894 benefit of the disassembler. We remove it before
7895 applying the actual mask. */
7896 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7897 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7901 case 'e': /* extend code */
7902 my_getExpression (&imm_expr
, s
);
7903 check_absolute_expr (ip
, &imm_expr
);
7904 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7906 as_warn ("Invalid value for `%s' (%lu)",
7908 (unsigned long) imm_expr
.X_add_number
);
7909 imm_expr
.X_add_number
&= 0x7ff;
7911 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7912 imm_expr
.X_op
= O_absent
;
7922 /* Args don't match. */
7923 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7924 strcmp (insn
->name
, insn
[1].name
) == 0)
7931 insn_error
= "illegal operands";
7937 /* This structure holds information we know about a mips16 immediate
7940 struct mips16_immed_operand
7942 /* The type code used in the argument string in the opcode table. */
7944 /* The number of bits in the short form of the opcode. */
7946 /* The number of bits in the extended form of the opcode. */
7948 /* The amount by which the short form is shifted when it is used;
7949 for example, the sw instruction has a shift count of 2. */
7951 /* The amount by which the short form is shifted when it is stored
7952 into the instruction code. */
7954 /* Non-zero if the short form is unsigned. */
7956 /* Non-zero if the extended form is unsigned. */
7958 /* Non-zero if the value is PC relative. */
7962 /* The mips16 immediate operand types. */
7964 static const struct mips16_immed_operand mips16_immed_operands
[] =
7966 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7967 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7968 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7969 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7970 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7971 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7972 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7973 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7974 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7975 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7976 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7977 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7978 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7979 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7980 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7981 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7982 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7983 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7984 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7985 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7986 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7989 #define MIPS16_NUM_IMMED \
7990 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7992 /* Handle a mips16 instruction with an immediate value. This or's the
7993 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7994 whether an extended value is needed; if one is needed, it sets
7995 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7996 If SMALL is true, an unextended opcode was explicitly requested.
7997 If EXT is true, an extended opcode was explicitly requested. If
7998 WARN is true, warn if EXT does not match reality. */
8001 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8010 unsigned long *insn
;
8011 boolean
*use_extend
;
8012 unsigned short *extend
;
8014 register const struct mips16_immed_operand
*op
;
8015 int mintiny
, maxtiny
;
8018 op
= mips16_immed_operands
;
8019 while (op
->type
!= type
)
8022 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8027 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8030 maxtiny
= 1 << op
->nbits
;
8035 maxtiny
= (1 << op
->nbits
) - 1;
8040 mintiny
= - (1 << (op
->nbits
- 1));
8041 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8044 /* Branch offsets have an implicit 0 in the lowest bit. */
8045 if (type
== 'p' || type
== 'q')
8048 if ((val
& ((1 << op
->shift
) - 1)) != 0
8049 || val
< (mintiny
<< op
->shift
)
8050 || val
> (maxtiny
<< op
->shift
))
8055 if (warn
&& ext
&& ! needext
)
8056 as_warn_where (file
, line
, "extended operand requested but not required");
8057 if (small
&& needext
)
8058 as_bad_where (file
, line
, "invalid unextended operand value");
8060 if (small
|| (! ext
&& ! needext
))
8064 *use_extend
= false;
8065 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8066 insnval
<<= op
->op_shift
;
8071 long minext
, maxext
;
8077 maxext
= (1 << op
->extbits
) - 1;
8081 minext
= - (1 << (op
->extbits
- 1));
8082 maxext
= (1 << (op
->extbits
- 1)) - 1;
8084 if (val
< minext
|| val
> maxext
)
8085 as_bad_where (file
, line
,
8086 "operand value out of range for instruction");
8089 if (op
->extbits
== 16)
8091 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8094 else if (op
->extbits
== 15)
8096 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8101 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8105 *extend
= (unsigned short) extval
;
8114 my_getSmallExpression (ep
, str
)
8125 ((str
[1] == 'h' && str
[2] == 'i')
8126 || (str
[1] == 'H' && str
[2] == 'I')
8127 || (str
[1] == 'l' && str
[2] == 'o'))
8139 * A small expression may be followed by a base register.
8140 * Scan to the end of this operand, and then back over a possible
8141 * base register. Then scan the small expression up to that
8142 * point. (Based on code in sparc.c...)
8144 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8146 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8148 if (isdigit (sp
[-2]))
8150 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8152 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8158 else if (sp
- 5 >= str
8161 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8162 || (sp
[-3] == 's' && sp
[-2] == 'p')
8163 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8164 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8170 /* no expression means zero offset */
8173 /* %xx(reg) is an error */
8174 ep
->X_op
= O_absent
;
8179 ep
->X_op
= O_constant
;
8182 ep
->X_add_symbol
= NULL
;
8183 ep
->X_op_symbol
= NULL
;
8184 ep
->X_add_number
= 0;
8189 my_getExpression (ep
, str
);
8196 my_getExpression (ep
, str
);
8197 return c
; /* => %hi or %lo encountered */
8201 my_getExpression (ep
, str
)
8207 save_in
= input_line_pointer
;
8208 input_line_pointer
= str
;
8210 expr_end
= input_line_pointer
;
8211 input_line_pointer
= save_in
;
8213 /* If we are in mips16 mode, and this is an expression based on `.',
8214 then we bump the value of the symbol by 1 since that is how other
8215 text symbols are handled. We don't bother to handle complex
8216 expressions, just `.' plus or minus a constant. */
8217 if (mips_opts
.mips16
8218 && ep
->X_op
== O_symbol
8219 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8220 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8221 && ep
->X_add_symbol
->sy_frag
== frag_now
8222 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8223 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8224 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8227 /* Turn a string in input_line_pointer into a floating point constant
8228 of type type, and store the appropriate bytes in *litP. The number
8229 of LITTLENUMS emitted is stored in *sizeP . An error message is
8230 returned, or NULL on OK. */
8233 md_atof (type
, litP
, sizeP
)
8239 LITTLENUM_TYPE words
[4];
8255 return "bad call to md_atof";
8258 t
= atof_ieee (input_line_pointer
, type
, words
);
8260 input_line_pointer
= t
;
8264 if (! target_big_endian
)
8266 for (i
= prec
- 1; i
>= 0; i
--)
8268 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8274 for (i
= 0; i
< prec
; i
++)
8276 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8285 md_number_to_chars (buf
, val
, n
)
8290 if (target_big_endian
)
8291 number_to_chars_bigendian (buf
, val
, n
);
8293 number_to_chars_littleendian (buf
, val
, n
);
8296 CONST
char *md_shortopts
= "O::g::G:";
8298 struct option md_longopts
[] = {
8299 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8300 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8301 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8302 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8303 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8304 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8305 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8306 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8307 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8308 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8309 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8310 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8311 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8312 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8313 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8314 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8315 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8316 {"break", no_argument
, NULL
, OPTION_BREAK
},
8317 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8318 #define OPTION_EB (OPTION_MD_BASE + 11)
8319 {"EB", no_argument
, NULL
, OPTION_EB
},
8320 #define OPTION_EL (OPTION_MD_BASE + 12)
8321 {"EL", no_argument
, NULL
, OPTION_EL
},
8322 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8323 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8324 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8325 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8326 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8327 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8328 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8329 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8330 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8331 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8332 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8333 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8334 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8335 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8336 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8337 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8338 /* start-sanitize-r5900 */
8339 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8340 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8341 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8342 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8343 /* end-sanitize-r5900 */
8344 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8345 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8346 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8347 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8350 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8351 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8352 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8353 #define OPTION_32 (OPTION_MD_BASE + 20)
8354 #define OPTION_64 (OPTION_MD_BASE + 21)
8356 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8357 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8358 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8359 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8360 {"32", no_argument
, NULL
, OPTION_32
},
8361 {"64", no_argument
, NULL
, OPTION_64
},
8364 {NULL
, no_argument
, NULL
, 0}
8366 size_t md_longopts_size
= sizeof(md_longopts
);
8369 md_parse_option (c
, arg
)
8384 target_big_endian
= 1;
8388 target_big_endian
= 0;
8392 if (arg
&& arg
[1] == '0')
8402 mips_debug
= atoi (arg
);
8403 /* When the MIPS assembler sees -g or -g2, it does not do
8404 optimizations which limit full symbolic debugging. We take
8405 that to be equivalent to -O0. */
8406 if (mips_debug
== 2)
8438 /* Identify the processor type */
8440 if (strcmp (p
, "default") == 0
8441 || strcmp (p
, "DEFAULT") == 0)
8447 /* We need to cope with the various "vr" prefixes for the 4300
8449 if (*p
== 'v' || *p
== 'V')
8455 if (*p
== 'r' || *p
== 'R')
8462 if (strcmp (p
, "10000") == 0
8463 || strcmp (p
, "10k") == 0
8464 || strcmp (p
, "10K") == 0)
8469 if (strcmp (p
, "2000") == 0
8470 || strcmp (p
, "2k") == 0
8471 || strcmp (p
, "2K") == 0)
8476 if (strcmp (p
, "3000") == 0
8477 || strcmp (p
, "3k") == 0
8478 || strcmp (p
, "3K") == 0)
8480 else if (strcmp (p
, "3900") == 0)
8485 if (strcmp (p
, "4000") == 0
8486 || strcmp (p
, "4k") == 0
8487 || strcmp (p
, "4K") == 0)
8489 else if (strcmp (p
, "4100") == 0)
8495 else if (strcmp (p
, "4300") == 0)
8497 else if (strcmp (p
, "4400") == 0)
8499 else if (strcmp (p
, "4600") == 0)
8501 else if (strcmp (p
, "4650") == 0)
8507 else if (strcmp (p
, "4010") == 0)
8516 if (strcmp (p
, "5000") == 0
8517 || strcmp (p
, "5k") == 0
8518 || strcmp (p
, "5K") == 0)
8520 /* start-sanitize-r5900 */
8521 else if (strcmp (p
, "5900") == 0)
8523 /* end-sanitize-r5900 */
8527 if (strcmp (p
, "6000") == 0
8528 || strcmp (p
, "6k") == 0
8529 || strcmp (p
, "6K") == 0)
8534 if (strcmp (p
, "8000") == 0
8535 || strcmp (p
, "8k") == 0
8536 || strcmp (p
, "8K") == 0)
8541 if (strcmp (p
, "orion") == 0)
8546 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8548 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8554 as_bad ("invalid architecture -mcpu=%s", arg
);
8565 case OPTION_NO_M4650
:
8573 case OPTION_NO_M4010
:
8581 case OPTION_NO_M4100
:
8585 /* start-sanitize-r5900 */
8590 case OPTION_NO_M5900
:
8593 /* end-sanitize-r5900 */
8599 case OPTION_NO_M3900
:
8604 mips_opts
.mips16
= 1;
8605 mips_no_prev_insn (false);
8608 case OPTION_NO_MIPS16
:
8609 mips_opts
.mips16
= 0;
8610 mips_no_prev_insn (false);
8613 case OPTION_MEMBEDDED_PIC
:
8614 mips_pic
= EMBEDDED_PIC
;
8615 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8617 as_bad ("-G may not be used with embedded PIC code");
8620 g_switch_value
= 0x7fffffff;
8623 /* When generating ELF code, we permit -KPIC and -call_shared to
8624 select SVR4_PIC, and -non_shared to select no PIC. This is
8625 intended to be compatible with Irix 5. */
8626 case OPTION_CALL_SHARED
:
8627 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8629 as_bad ("-call_shared is supported only for ELF format");
8632 mips_pic
= SVR4_PIC
;
8633 if (g_switch_seen
&& g_switch_value
!= 0)
8635 as_bad ("-G may not be used with SVR4 PIC code");
8641 case OPTION_NON_SHARED
:
8642 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8644 as_bad ("-non_shared is supported only for ELF format");
8650 /* The -xgot option tells the assembler to use 32 offsets when
8651 accessing the got in SVR4_PIC mode. It is for Irix
8658 if (! USE_GLOBAL_POINTER_OPT
)
8660 as_bad ("-G is not supported for this configuration");
8663 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8665 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8669 g_switch_value
= atoi (arg
);
8673 /* The -32 and -64 options tell the assembler to output the 32
8674 bit or the 64 bit MIPS ELF format. */
8681 const char **list
, **l
;
8683 list
= bfd_target_list ();
8684 for (l
= list
; *l
!= NULL
; l
++)
8685 if (strcmp (*l
, "elf64-bigmips") == 0
8686 || strcmp (*l
, "elf64-littlemips") == 0)
8689 as_fatal ("No compiled in support for 64 bit object file format");
8703 md_show_usage (stream
)
8708 -membedded-pic generate embedded position independent code\n\
8709 -EB generate big endian output\n\
8710 -EL generate little endian output\n\
8711 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8712 -G NUM allow referencing objects up to NUM bytes\n\
8713 implicitly with the gp register [default 8]\n");
8715 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8716 -mips2, -mcpu=r6000 generate code for r6000\n\
8717 -mips3, -mcpu=r4000 generate code for r4000\n\
8718 -mips4, -mcpu=r8000 generate code for r8000\n\
8719 -mcpu=vr4300 generate code for vr4300\n\
8720 -mcpu=vr4100 generate code for vr4100\n\
8721 -m4650 permit R4650 instructions\n\
8722 -no-m4650 do not permit R4650 instructions\n\
8723 -m4010 permit R4010 instructions\n\
8724 -no-m4010 do not permit R4010 instructions\n\
8725 -m4100 permit VR4100 instructions\n\
8726 -no-m4100 do not permit VR4100 instructions\n");
8728 -mips16 generate mips16 instructions\n\
8729 -no-mips16 do not generate mips16 instructions\n");
8731 -O0 remove unneeded NOPs, do not swap branches\n\
8732 -O remove unneeded NOPs and swap branches\n\
8733 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8734 --break, --no-trap break exception on div by 0 and mult overflow\n");
8737 -KPIC, -call_shared generate SVR4 position independent code\n\
8738 -non_shared do not generate position independent code\n\
8739 -xgot assume a 32 bit GOT\n\
8740 -32 create 32 bit object file (default)\n\
8741 -64 create 64 bit object file\n");
8746 mips_init_after_args ()
8748 /* initialize opcodes */
8749 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8750 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8754 md_pcrel_from (fixP
)
8757 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8758 && fixP
->fx_addsy
!= (symbolS
*) NULL
8759 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8761 /* This makes a branch to an undefined symbol be a branch to the
8762 current location. */
8766 /* return the address of the delay slot */
8767 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8770 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8771 reloc for a cons. We could use the definition there, except that
8772 we want to handle 64 bit relocs specially. */
8775 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8778 unsigned int nbytes
;
8782 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8784 if (nbytes
== 8 && ! mips_64
)
8786 if (target_big_endian
)
8792 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8793 as_bad ("Unsupported reloc size %d", nbytes
);
8795 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8798 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8801 /* This is called before the symbol table is processed. In order to
8802 work with gcc when using mips-tfile, we must keep all local labels.
8803 However, in other cases, we want to discard them. If we were
8804 called with -g, but we didn't see any debugging information, it may
8805 mean that gcc is smuggling debugging information through to
8806 mips-tfile, in which case we must generate all local labels. */
8809 mips_frob_file_before_adjust ()
8811 #ifndef NO_ECOFF_DEBUGGING
8814 && ! ecoff_debugging_seen
)
8815 flag_keep_locals
= 1;
8819 /* Sort any unmatched HI16_S relocs so that they immediately precede
8820 the corresponding LO reloc. This is called before md_apply_fix and
8821 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8822 explicit use of the %hi modifier. */
8827 struct mips_hi_fixup
*l
;
8829 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8831 segment_info_type
*seginfo
;
8834 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8836 /* Check quickly whether the next fixup happens to be a matching
8838 if (l
->fixp
->fx_next
!= NULL
8839 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8840 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8841 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8844 /* Look through the fixups for this segment for a matching %lo.
8845 When we find one, move the %hi just in front of it. We do
8846 this in two passes. In the first pass, we try to find a
8847 unique %lo. In the second pass, we permit multiple %hi
8848 relocs for a single %lo (this is a GNU extension). */
8849 seginfo
= seg_info (l
->seg
);
8850 for (pass
= 0; pass
< 2; pass
++)
8855 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8857 /* Check whether this is a %lo fixup which matches l->fixp. */
8858 if (f
->fx_r_type
== BFD_RELOC_LO16
8859 && f
->fx_addsy
== l
->fixp
->fx_addsy
8860 && f
->fx_offset
== l
->fixp
->fx_offset
8863 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8864 || prev
->fx_addsy
!= f
->fx_addsy
8865 || prev
->fx_offset
!= f
->fx_offset
))
8869 /* Move l->fixp before f. */
8870 for (pf
= &seginfo
->fix_root
;
8872 pf
= &(*pf
)->fx_next
)
8873 assert (*pf
!= NULL
);
8875 *pf
= l
->fixp
->fx_next
;
8877 l
->fixp
->fx_next
= f
;
8879 seginfo
->fix_root
= l
->fixp
;
8881 prev
->fx_next
= l
->fixp
;
8893 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8894 "Unmatched %%hi reloc");
8899 /* When generating embedded PIC code we need to use a special
8900 relocation to represent the difference of two symbols in the .text
8901 section (switch tables use a difference of this sort). See
8902 include/coff/mips.h for details. This macro checks whether this
8903 fixup requires the special reloc. */
8904 #define SWITCH_TABLE(fixp) \
8905 ((fixp)->fx_r_type == BFD_RELOC_32 \
8906 && (fixp)->fx_addsy != NULL \
8907 && (fixp)->fx_subsy != NULL \
8908 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8909 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8911 /* When generating embedded PIC code we must keep all PC relative
8912 relocations, in case the linker has to relax a call. We also need
8913 to keep relocations for switch table entries. */
8917 mips_force_relocation (fixp
)
8920 return (mips_pic
== EMBEDDED_PIC
8922 || SWITCH_TABLE (fixp
)
8923 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8924 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8927 /* Apply a fixup to the object file. */
8930 md_apply_fix (fixP
, valueP
)
8937 assert (fixP
->fx_size
== 4
8938 || fixP
->fx_r_type
== BFD_RELOC_16
8939 || fixP
->fx_r_type
== BFD_RELOC_64
);
8943 /* If we aren't adjusting this fixup to be against the section
8944 symbol, we need to adjust the value. */
8946 if (fixP
->fx_addsy
!= NULL
8947 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8948 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8950 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8951 if (value
!= 0 && ! fixP
->fx_pcrel
)
8953 /* In this case, the bfd_install_relocation routine will
8954 incorrectly add the symbol value back in. We just want
8955 the addend to appear in the object file. */
8956 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8961 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8963 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8966 switch (fixP
->fx_r_type
)
8968 case BFD_RELOC_MIPS_JMP
:
8969 case BFD_RELOC_HI16
:
8970 case BFD_RELOC_HI16_S
:
8971 case BFD_RELOC_MIPS_GPREL
:
8972 case BFD_RELOC_MIPS_LITERAL
:
8973 case BFD_RELOC_MIPS_CALL16
:
8974 case BFD_RELOC_MIPS_GOT16
:
8975 case BFD_RELOC_MIPS_GPREL32
:
8976 case BFD_RELOC_MIPS_GOT_HI16
:
8977 case BFD_RELOC_MIPS_GOT_LO16
:
8978 case BFD_RELOC_MIPS_CALL_HI16
:
8979 case BFD_RELOC_MIPS_CALL_LO16
:
8980 case BFD_RELOC_MIPS16_GPREL
:
8982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8983 "Invalid PC relative reloc");
8984 /* Nothing needed to do. The value comes from the reloc entry */
8987 case BFD_RELOC_MIPS16_JMP
:
8988 /* We currently always generate a reloc against a symbol, which
8989 means that we don't want an addend even if the symbol is
8991 fixP
->fx_addnumber
= 0;
8994 case BFD_RELOC_PCREL_HI16_S
:
8995 /* The addend for this is tricky if it is internal, so we just
8996 do everything here rather than in bfd_install_relocation. */
8997 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8999 /* For an external symbol adjust by the address to make it
9000 pcrel_offset. We use the address of the RELLO reloc
9001 which follows this one. */
9002 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9003 + fixP
->fx_next
->fx_where
);
9008 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9009 if (target_big_endian
)
9011 md_number_to_chars (buf
, value
, 2);
9014 case BFD_RELOC_PCREL_LO16
:
9015 /* The addend for this is tricky if it is internal, so we just
9016 do everything here rather than in bfd_install_relocation. */
9017 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9018 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9019 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9020 if (target_big_endian
)
9022 md_number_to_chars (buf
, value
, 2);
9026 /* This is handled like BFD_RELOC_32, but we output a sign
9027 extended value if we are only 32 bits. */
9029 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9031 if (8 <= sizeof (valueT
))
9032 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9039 w1
= w2
= fixP
->fx_where
;
9040 if (target_big_endian
)
9044 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9045 if ((value
& 0x80000000) != 0)
9049 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9055 /* If we are deleting this reloc entry, we must fill in the
9056 value now. This can happen if we have a .word which is not
9057 resolved when it appears but is later defined. We also need
9058 to fill in the value if this is an embedded PIC switch table
9061 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9062 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9067 /* If we are deleting this reloc entry, we must fill in the
9069 assert (fixP
->fx_size
== 2);
9071 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9075 case BFD_RELOC_LO16
:
9076 /* When handling an embedded PIC switch statement, we can wind
9077 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9080 if (value
< -0x8000 || value
> 0x7fff)
9081 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9082 "relocation overflow");
9083 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9084 if (target_big_endian
)
9086 md_number_to_chars (buf
, value
, 2);
9090 case BFD_RELOC_16_PCREL_S2
:
9092 * We need to save the bits in the instruction since fixup_segment()
9093 * might be deleting the relocation entry (i.e., a branch within
9094 * the current segment).
9096 if ((value
& 0x3) != 0)
9097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9098 "Branch to odd address (%lx)", value
);
9101 /* update old instruction data */
9102 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9103 if (target_big_endian
)
9104 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9106 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9108 if (value
>= -0x8000 && value
< 0x8000)
9109 insn
|= value
& 0xffff;
9112 /* The branch offset is too large. If this is an
9113 unconditional branch, and we are not generating PIC code,
9114 we can convert it to an absolute jump instruction. */
9115 if (mips_pic
== NO_PIC
9117 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9118 && (fixP
->fx_frag
->fr_address
9119 < text_section
->vma
+ text_section
->_raw_size
)
9120 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9121 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9122 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9124 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9125 insn
= 0x0c000000; /* jal */
9127 insn
= 0x08000000; /* j */
9128 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9130 fixP
->fx_addsy
= section_symbol (text_section
);
9131 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9135 /* FIXME. It would be possible in principle to handle
9136 conditional branches which overflow. They could be
9137 transformed into a branch around a jump. This would
9138 require setting up variant frags for each different
9139 branch type. The native MIPS assembler attempts to
9140 handle these cases, but it appears to do it
9142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9143 "Branch out of range");
9147 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9162 const struct mips_opcode
*p
;
9163 int treg
, sreg
, dreg
, shamt
;
9168 for (i
= 0; i
< NUMOPCODES
; ++i
)
9170 p
= &mips_opcodes
[i
];
9171 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9173 printf ("%08lx %s\t", oc
, p
->name
);
9174 treg
= (oc
>> 16) & 0x1f;
9175 sreg
= (oc
>> 21) & 0x1f;
9176 dreg
= (oc
>> 11) & 0x1f;
9177 shamt
= (oc
>> 6) & 0x1f;
9179 for (args
= p
->args
;; ++args
)
9190 printf ("%c", *args
);
9194 assert (treg
== sreg
);
9195 printf ("$%d,$%d", treg
, sreg
);
9200 printf ("$%d", dreg
);
9205 printf ("$%d", treg
);
9209 printf ("0x%x", treg
);
9214 printf ("$%d", sreg
);
9218 printf ("0x%08lx", oc
& 0x1ffffff);
9230 printf ("$%d", shamt
);
9241 printf ("%08lx UNDEFINED\n", oc
);
9252 name
= input_line_pointer
;
9253 c
= get_symbol_end ();
9254 p
= (symbolS
*) symbol_find_or_make (name
);
9255 *input_line_pointer
= c
;
9259 /* Align the current frag to a given power of two. The MIPS assembler
9260 also automatically adjusts any preceding label. */
9263 mips_align (to
, fill
, label
)
9268 mips_emit_delays (false);
9269 frag_align (to
, fill
, 0);
9270 record_alignment (now_seg
, to
);
9273 assert (S_GET_SEGMENT (label
) == now_seg
);
9274 label
->sy_frag
= frag_now
;
9275 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9279 /* Align to a given power of two. .align 0 turns off the automatic
9280 alignment used by the data creating pseudo-ops. */
9287 register long temp_fill
;
9288 long max_alignment
= 15;
9292 o Note that the assembler pulls down any immediately preceeding label
9293 to the aligned address.
9294 o It's not documented but auto alignment is reinstated by
9295 a .align pseudo instruction.
9296 o Note also that after auto alignment is turned off the mips assembler
9297 issues an error on attempt to assemble an improperly aligned data item.
9302 temp
= get_absolute_expression ();
9303 if (temp
> max_alignment
)
9304 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9307 as_warn ("Alignment negative: 0 assumed.");
9310 if (*input_line_pointer
== ',')
9312 input_line_pointer
++;
9313 temp_fill
= get_absolute_expression ();
9320 mips_align (temp
, (int) temp_fill
,
9321 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9328 demand_empty_rest_of_line ();
9332 mips_flush_pending_output ()
9334 mips_emit_delays (false);
9335 mips_clear_insn_labels ();
9344 /* When generating embedded PIC code, we only use the .text, .lit8,
9345 .sdata and .sbss sections. We change the .data and .rdata
9346 pseudo-ops to use .sdata. */
9347 if (mips_pic
== EMBEDDED_PIC
9348 && (sec
== 'd' || sec
== 'r'))
9352 /* The ELF backend needs to know that we are changing sections, so
9353 that .previous works correctly. We could do something like check
9354 for a obj_section_change_hook macro, but that might be confusing
9355 as it would not be appropriate to use it in the section changing
9356 functions in read.c, since obj-elf.c intercepts those. FIXME:
9357 This should be cleaner, somehow. */
9358 obj_elf_section_change_hook ();
9361 mips_emit_delays (false);
9371 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9372 demand_empty_rest_of_line ();
9376 if (USE_GLOBAL_POINTER_OPT
)
9378 seg
= subseg_new (RDATA_SECTION_NAME
,
9379 (subsegT
) get_absolute_expression ());
9380 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9382 bfd_set_section_flags (stdoutput
, seg
,
9388 if (strcmp (TARGET_OS
, "elf") != 0)
9389 bfd_set_section_alignment (stdoutput
, seg
, 4);
9391 demand_empty_rest_of_line ();
9395 as_bad ("No read only data section in this object file format");
9396 demand_empty_rest_of_line ();
9402 if (USE_GLOBAL_POINTER_OPT
)
9404 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9405 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9407 bfd_set_section_flags (stdoutput
, seg
,
9408 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9410 if (strcmp (TARGET_OS
, "elf") != 0)
9411 bfd_set_section_alignment (stdoutput
, seg
, 4);
9413 demand_empty_rest_of_line ();
9418 as_bad ("Global pointers not supported; recompile -G 0");
9419 demand_empty_rest_of_line ();
9428 mips_enable_auto_align ()
9439 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9440 mips_emit_delays (false);
9441 if (log_size
> 0 && auto_align
)
9442 mips_align (log_size
, 0, label
);
9443 mips_clear_insn_labels ();
9444 cons (1 << log_size
);
9453 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9455 mips_emit_delays (false);
9459 mips_align (3, 0, label
);
9461 mips_align (2, 0, label
);
9463 mips_clear_insn_labels ();
9468 /* Handle .globl. We need to override it because on Irix 5 you are
9471 where foo is an undefined symbol, to mean that foo should be
9472 considered to be the address of a function. */
9483 name
= input_line_pointer
;
9484 c
= get_symbol_end ();
9485 symbolP
= symbol_find_or_make (name
);
9486 *input_line_pointer
= c
;
9489 /* On Irix 5, every global symbol that is not explicitly labelled as
9490 being a function is apparently labelled as being an object. */
9493 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9498 secname
= input_line_pointer
;
9499 c
= get_symbol_end ();
9500 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9502 as_bad ("%s: no such section", secname
);
9503 *input_line_pointer
= c
;
9505 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9506 flag
= BSF_FUNCTION
;
9509 symbolP
->bsym
->flags
|= flag
;
9511 S_SET_EXTERNAL (symbolP
);
9512 demand_empty_rest_of_line ();
9522 opt
= input_line_pointer
;
9523 c
= get_symbol_end ();
9527 /* FIXME: What does this mean? */
9529 else if (strncmp (opt
, "pic", 3) == 0)
9537 mips_pic
= SVR4_PIC
;
9539 as_bad (".option pic%d not supported", i
);
9541 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9543 if (g_switch_seen
&& g_switch_value
!= 0)
9544 as_warn ("-G may not be used with SVR4 PIC code");
9546 bfd_set_gp_size (stdoutput
, 0);
9550 as_warn ("Unrecognized option \"%s\"", opt
);
9552 *input_line_pointer
= c
;
9553 demand_empty_rest_of_line ();
9556 /* This structure is used to hold a stack of .set values. */
9558 struct mips_option_stack
9560 struct mips_option_stack
*next
;
9561 struct mips_set_options options
;
9564 static struct mips_option_stack
*mips_opts_stack
;
9566 /* Handle the .set pseudo-op. */
9572 char *name
= input_line_pointer
, ch
;
9574 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9575 input_line_pointer
++;
9576 ch
= *input_line_pointer
;
9577 *input_line_pointer
= '\0';
9579 if (strcmp (name
, "reorder") == 0)
9581 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9583 /* If we still have pending nops, we can discard them. The
9584 usual nop handling will insert any that are still
9586 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9587 * (mips_opts
.mips16
? 2 : 4));
9588 prev_nop_frag
= NULL
;
9590 mips_opts
.noreorder
= 0;
9592 else if (strcmp (name
, "noreorder") == 0)
9594 mips_emit_delays (true);
9595 mips_opts
.noreorder
= 1;
9596 mips_any_noreorder
= 1;
9598 else if (strcmp (name
, "at") == 0)
9602 else if (strcmp (name
, "noat") == 0)
9606 else if (strcmp (name
, "macro") == 0)
9608 mips_opts
.warn_about_macros
= 0;
9610 else if (strcmp (name
, "nomacro") == 0)
9612 if (mips_opts
.noreorder
== 0)
9613 as_bad ("`noreorder' must be set before `nomacro'");
9614 mips_opts
.warn_about_macros
= 1;
9616 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9618 mips_opts
.nomove
= 0;
9620 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9622 mips_opts
.nomove
= 1;
9624 else if (strcmp (name
, "bopt") == 0)
9626 mips_opts
.nobopt
= 0;
9628 else if (strcmp (name
, "nobopt") == 0)
9630 mips_opts
.nobopt
= 1;
9632 else if (strcmp (name
, "mips16") == 0
9633 || strcmp (name
, "MIPS-16") == 0)
9634 mips_opts
.mips16
= 1;
9635 else if (strcmp (name
, "nomips16") == 0
9636 || strcmp (name
, "noMIPS-16") == 0)
9637 mips_opts
.mips16
= 0;
9638 else if (strncmp (name
, "mips", 4) == 0)
9642 /* Permit the user to change the ISA on the fly. Needless to
9643 say, misuse can cause serious problems. */
9644 isa
= atoi (name
+ 4);
9646 mips_opts
.isa
= file_mips_isa
;
9647 else if (isa
< 1 || isa
> 4)
9648 as_bad ("unknown ISA level");
9650 mips_opts
.isa
= isa
;
9652 else if (strcmp (name
, "autoextend") == 0)
9653 mips_opts
.noautoextend
= 0;
9654 else if (strcmp (name
, "noautoextend") == 0)
9655 mips_opts
.noautoextend
= 1;
9656 else if (strcmp (name
, "push") == 0)
9658 struct mips_option_stack
*s
;
9660 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9661 s
->next
= mips_opts_stack
;
9662 s
->options
= mips_opts
;
9663 mips_opts_stack
= s
;
9665 else if (strcmp (name
, "pop") == 0)
9667 struct mips_option_stack
*s
;
9669 s
= mips_opts_stack
;
9671 as_bad (".set pop with no .set push");
9674 /* If we're changing the reorder mode we need to handle
9675 delay slots correctly. */
9676 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9677 mips_emit_delays (true);
9678 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9680 if (prev_nop_frag
!= NULL
)
9682 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9683 * (mips_opts
.mips16
? 2 : 4));
9684 prev_nop_frag
= NULL
;
9688 mips_opts
= s
->options
;
9689 mips_opts_stack
= s
->next
;
9695 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9697 *input_line_pointer
= ch
;
9698 demand_empty_rest_of_line ();
9701 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9702 .option pic2. It means to generate SVR4 PIC calls. */
9708 mips_pic
= SVR4_PIC
;
9709 if (USE_GLOBAL_POINTER_OPT
)
9711 if (g_switch_seen
&& g_switch_value
!= 0)
9712 as_warn ("-G may not be used with SVR4 PIC code");
9715 bfd_set_gp_size (stdoutput
, 0);
9716 demand_empty_rest_of_line ();
9719 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9720 PIC code. It sets the $gp register for the function based on the
9721 function address, which is in the register named in the argument.
9722 This uses a relocation against _gp_disp, which is handled specially
9723 by the linker. The result is:
9724 lui $gp,%hi(_gp_disp)
9725 addiu $gp,$gp,%lo(_gp_disp)
9726 addu $gp,$gp,.cpload argument
9727 The .cpload argument is normally $25 == $t9. */
9736 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9737 if (mips_pic
!= SVR4_PIC
)
9743 /* .cpload should be a in .set noreorder section. */
9744 if (mips_opts
.noreorder
== 0)
9745 as_warn (".cpload not in noreorder section");
9748 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9749 ex
.X_op_symbol
= NULL
;
9750 ex
.X_add_number
= 0;
9752 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9753 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9755 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9756 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9757 (int) BFD_RELOC_LO16
);
9759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9760 GP
, GP
, tc_get_register (0));
9762 demand_empty_rest_of_line ();
9765 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9766 offset from $sp. The offset is remembered, and after making a PIC
9767 call $gp is restored from that location. */
9770 s_cprestore (ignore
)
9776 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9777 if (mips_pic
!= SVR4_PIC
)
9783 mips_cprestore_offset
= get_absolute_expression ();
9785 ex
.X_op
= O_constant
;
9786 ex
.X_add_symbol
= NULL
;
9787 ex
.X_op_symbol
= NULL
;
9788 ex
.X_add_number
= mips_cprestore_offset
;
9790 macro_build ((char *) NULL
, &icnt
, &ex
,
9791 mips_opts
.isa
< 3 ? "sw" : "sd",
9792 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9794 demand_empty_rest_of_line ();
9797 /* Handle the .gpword pseudo-op. This is used when generating PIC
9798 code. It generates a 32 bit GP relative reloc. */
9808 /* When not generating PIC code, this is treated as .word. */
9809 if (mips_pic
!= SVR4_PIC
)
9815 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9816 mips_emit_delays (true);
9818 mips_align (2, 0, label
);
9819 mips_clear_insn_labels ();
9823 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9825 as_bad ("Unsupported use of .gpword");
9826 ignore_rest_of_line ();
9830 md_number_to_chars (p
, (valueT
) 0, 4);
9831 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9832 BFD_RELOC_MIPS_GPREL32
);
9834 demand_empty_rest_of_line ();
9837 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9838 tables in SVR4 PIC code. */
9847 /* This is ignored when not generating SVR4 PIC code. */
9848 if (mips_pic
!= SVR4_PIC
)
9854 /* Add $gp to the register named as an argument. */
9855 reg
= tc_get_register (0);
9856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9857 mips_opts
.isa
< 3 ? "addu" : "daddu",
9858 "d,v,t", reg
, reg
, GP
);
9860 demand_empty_rest_of_line ();
9863 /* Handle the .insn pseudo-op. This marks instruction labels in
9864 mips16 mode. This permits the linker to handle them specially,
9865 such as generating jalx instructions when needed. We also make
9866 them odd for the duration of the assembly, in order to generate the
9867 right sort of code. We will make them even in the adjust_symtab
9868 routine, while leaving them marked. This is convenient for the
9869 debugger and the disassembler. The linker knows to make them odd
9876 if (mips_opts
.mips16
)
9877 mips16_mark_labels ();
9879 demand_empty_rest_of_line ();
9882 /* Handle a .stabn directive. We need these in order to mark a label
9883 as being a mips16 text label correctly. Sometimes the compiler
9884 will emit a label, followed by a .stabn, and then switch sections.
9885 If the label and .stabn are in mips16 mode, then the label is
9886 really a mips16 text label. */
9892 if (type
== 'n' && mips_opts
.mips16
)
9893 mips16_mark_labels ();
9898 /* Parse a register string into a number. Called from the ECOFF code
9899 to parse .frame. The argument is non-zero if this is the frame
9900 register, so that we can record it in mips_frame_reg. */
9903 tc_get_register (frame
)
9909 if (*input_line_pointer
++ != '$')
9911 as_warn ("expected `$'");
9914 else if (isdigit ((unsigned char) *input_line_pointer
))
9916 reg
= get_absolute_expression ();
9917 if (reg
< 0 || reg
>= 32)
9919 as_warn ("Bad register number");
9925 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9927 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9929 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9931 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9935 as_warn ("Unrecognized register name");
9938 input_line_pointer
+= 2;
9941 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9946 md_section_align (seg
, addr
)
9950 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9953 /* We don't need to align ELF sections to the full alignment.
9954 However, Irix 5 may prefer that we align them at least to a 16
9955 byte boundary. We don't bother to align the sections if we are
9956 targeted for an embedded system. */
9957 if (strcmp (TARGET_OS
, "elf") == 0)
9963 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9966 /* Utility routine, called from above as well. If called while the
9967 input file is still being read, it's only an approximation. (For
9968 example, a symbol may later become defined which appeared to be
9969 undefined earlier.) */
9972 nopic_need_relax (sym
, before_relaxing
)
9974 int before_relaxing
;
9979 if (USE_GLOBAL_POINTER_OPT
)
9981 const char *symname
;
9984 /* Find out whether this symbol can be referenced off the GP
9985 register. It can be if it is smaller than the -G size or if
9986 it is in the .sdata or .sbss section. Certain symbols can
9987 not be referenced off the GP, although it appears as though
9989 symname
= S_GET_NAME (sym
);
9990 if (symname
!= (const char *) NULL
9991 && (strcmp (symname
, "eprol") == 0
9992 || strcmp (symname
, "etext") == 0
9993 || strcmp (symname
, "_gp") == 0
9994 || strcmp (symname
, "edata") == 0
9995 || strcmp (symname
, "_fbss") == 0
9996 || strcmp (symname
, "_fdata") == 0
9997 || strcmp (symname
, "_ftext") == 0
9998 || strcmp (symname
, "end") == 0
9999 || strcmp (symname
, "_gp_disp") == 0))
10001 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10003 #ifndef NO_ECOFF_DEBUGGING
10004 || (sym
->ecoff_extern_size
!= 0
10005 && sym
->ecoff_extern_size
<= g_switch_value
)
10007 /* We must defer this decision until after the whole
10008 file has been read, since there might be a .extern
10009 after the first use of this symbol. */
10010 || (before_relaxing
10011 #ifndef NO_ECOFF_DEBUGGING
10012 && sym
->ecoff_extern_size
== 0
10014 && S_GET_VALUE (sym
) == 0)
10015 || (S_GET_VALUE (sym
) != 0
10016 && S_GET_VALUE (sym
) <= g_switch_value
)))
10020 const char *segname
;
10022 segname
= segment_name (S_GET_SEGMENT (sym
));
10023 assert (strcmp (segname
, ".lit8") != 0
10024 && strcmp (segname
, ".lit4") != 0);
10025 change
= (strcmp (segname
, ".sdata") != 0
10026 && strcmp (segname
, ".sbss") != 0);
10031 /* We are not optimizing for the GP register. */
10035 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10036 extended opcode. SEC is the section the frag is in. */
10039 mips16_extended_frag (fragp
, sec
, stretch
)
10045 register const struct mips16_immed_operand
*op
;
10047 int mintiny
, maxtiny
;
10050 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10052 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10055 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10056 op
= mips16_immed_operands
;
10057 while (op
->type
!= type
)
10060 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10065 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10068 maxtiny
= 1 << op
->nbits
;
10073 maxtiny
= (1 << op
->nbits
) - 1;
10078 mintiny
= - (1 << (op
->nbits
- 1));
10079 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10082 /* We can't call S_GET_VALUE here, because we don't want to lock in
10083 a particular frag address. */
10084 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10086 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10087 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10088 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10090 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10091 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10094 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10095 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10096 + fragp
->fr_symbol
->sy_value
.X_add_number
10097 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10098 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10107 /* We won't have the section when we are called from
10108 mips_relax_frag. However, we will always have been called
10109 from md_estimate_size_before_relax first. If this is a
10110 branch to a different section, we mark it as such. If SEC is
10111 NULL, and the frag is not marked, then it must be a branch to
10112 the same section. */
10115 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10122 fragp
->fr_subtype
=
10123 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10125 /* FIXME: We should support this, and let the linker
10126 catch branches and loads that are out of range. */
10127 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10128 "unsupported PC relative reference to different section");
10134 /* In this case, we know for sure that the symbol fragment is in
10135 the same section. If the fr_address of the symbol fragment
10136 is greater then the address of this fragment we want to add
10137 in STRETCH in order to get a better estimate of the address.
10138 This particularly matters because of the shift bits. */
10140 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10144 /* Adjust stretch for any alignment frag. Note that if have
10145 been expanding the earlier code, the symbol may be
10146 defined in what appears to be an earlier frag. FIXME:
10147 This doesn't handle the fr_subtype field, which specifies
10148 a maximum number of bytes to skip when doing an
10151 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10154 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10157 stretch
= - ((- stretch
)
10158 & ~ ((1 << (int) f
->fr_offset
) - 1));
10160 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10169 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10171 /* The base address rules are complicated. The base address of
10172 a branch is the following instruction. The base address of a
10173 PC relative load or add is the instruction itself, but if it
10174 is in a delay slot (in which case it can not be extended) use
10175 the address of the instruction whose delay slot it is in. */
10176 if (type
== 'p' || type
== 'q')
10180 /* If we are currently assuming that this frag should be
10181 extended, then, the current address is two bytes
10183 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10186 /* Ignore the low bit in the target, since it will be set
10187 for a text label. */
10188 if ((val
& 1) != 0)
10191 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10193 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10196 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10198 /* Branch offsets have an implicit 0 in the lowest bit. */
10199 if (type
== 'p' || type
== 'q')
10202 /* If any of the shifted bits are set, we must use an extended
10203 opcode. If the address depends on the size of this
10204 instruction, this can lead to a loop, so we arrange to always
10205 use an extended opcode. We only check this when we are in
10206 the main relaxation loop, when SEC is NULL. */
10207 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10209 fragp
->fr_subtype
=
10210 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10214 /* If we are about to mark a frag as extended because the value
10215 is precisely maxtiny + 1, then there is a chance of an
10216 infinite loop as in the following code:
10221 In this case when the la is extended, foo is 0x3fc bytes
10222 away, so the la can be shrunk, but then foo is 0x400 away, so
10223 the la must be extended. To avoid this loop, we mark the
10224 frag as extended if it was small, and is about to become
10225 extended with a value of maxtiny + 1. */
10226 if (val
== ((maxtiny
+ 1) << op
->shift
)
10227 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10230 fragp
->fr_subtype
=
10231 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10235 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10236 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10238 if ((val
& ((1 << op
->shift
) - 1)) != 0
10239 || val
< (mintiny
<< op
->shift
)
10240 || val
> (maxtiny
<< op
->shift
))
10246 /* Estimate the size of a frag before relaxing. Unless this is the
10247 mips16, we are not really relaxing here, and the final size is
10248 encoded in the subtype information. For the mips16, we have to
10249 decide whether we are using an extended opcode or not. */
10253 md_estimate_size_before_relax (fragp
, segtype
)
10259 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10261 if (mips16_extended_frag (fragp
, segtype
, 0))
10263 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10268 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10273 if (mips_pic
== NO_PIC
)
10275 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10277 else if (mips_pic
== SVR4_PIC
)
10282 sym
= fragp
->fr_symbol
;
10284 /* Handle the case of a symbol equated to another symbol. */
10285 while (sym
->sy_value
.X_op
== O_symbol
10286 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10290 /* It's possible to get a loop here in a badly written
10292 n
= sym
->sy_value
.X_add_symbol
;
10298 symsec
= S_GET_SEGMENT (sym
);
10300 /* This must duplicate the test in adjust_reloc_syms. */
10301 change
= (symsec
!= &bfd_und_section
10302 && symsec
!= &bfd_abs_section
10303 && ! bfd_is_com_section (symsec
));
10310 /* Record the offset to the first reloc in the fr_opcode field.
10311 This lets md_convert_frag and tc_gen_reloc know that the code
10312 must be expanded. */
10313 fragp
->fr_opcode
= (fragp
->fr_literal
10315 - RELAX_OLD (fragp
->fr_subtype
)
10316 + RELAX_RELOC1 (fragp
->fr_subtype
));
10317 /* FIXME: This really needs as_warn_where. */
10318 if (RELAX_WARN (fragp
->fr_subtype
))
10319 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10325 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10328 /* This is called to see whether a reloc against a defined symbol
10329 should be converted into a reloc against a section. Don't adjust
10330 MIPS16 jump relocations, so we don't have to worry about the format
10331 of the offset in the .o file. Don't adjust relocations against
10332 mips16 symbols, so that the linker can find them if it needs to set
10336 mips_fix_adjustable (fixp
)
10339 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10341 if (fixp
->fx_addsy
== NULL
)
10344 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10345 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10346 && fixp
->fx_subsy
== NULL
)
10352 /* Translate internal representation of relocation info to BFD target
10356 tc_gen_reloc (section
, fixp
)
10360 static arelent
*retval
[4];
10362 bfd_reloc_code_real_type code
;
10364 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10367 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10368 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10370 if (mips_pic
== EMBEDDED_PIC
10371 && SWITCH_TABLE (fixp
))
10373 /* For a switch table entry we use a special reloc. The addend
10374 is actually the difference between the reloc address and the
10376 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10377 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10378 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10379 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10381 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10383 /* We use a special addend for an internal RELLO reloc. */
10384 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10385 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10387 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10389 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10391 assert (fixp
->fx_next
!= NULL
10392 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10393 /* We use a special addend for an internal RELHI reloc. The
10394 reloc is relative to the RELLO; adjust the addend
10396 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10397 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10398 + fixp
->fx_next
->fx_where
10399 - S_GET_VALUE (fixp
->fx_subsy
));
10401 reloc
->addend
= (fixp
->fx_addnumber
10402 + fixp
->fx_next
->fx_frag
->fr_address
10403 + fixp
->fx_next
->fx_where
);
10405 else if (fixp
->fx_pcrel
== 0)
10406 reloc
->addend
= fixp
->fx_addnumber
;
10409 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10410 /* A gruesome hack which is a result of the gruesome gas reloc
10412 reloc
->addend
= reloc
->address
;
10414 reloc
->addend
= -reloc
->address
;
10417 /* If this is a variant frag, we may need to adjust the existing
10418 reloc and generate a new one. */
10419 if (fixp
->fx_frag
->fr_opcode
!= NULL
10420 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10421 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10422 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10423 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10424 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10425 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10426 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10430 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10432 /* If this is not the last reloc in this frag, then we have two
10433 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10434 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10435 the second one handle all of them. */
10436 if (fixp
->fx_next
!= NULL
10437 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10439 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10440 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10441 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10442 && (fixp
->fx_next
->fx_r_type
10443 == BFD_RELOC_MIPS_GOT_LO16
))
10444 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10445 && (fixp
->fx_next
->fx_r_type
10446 == BFD_RELOC_MIPS_CALL_LO16
)));
10451 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10452 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10453 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10455 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10456 reloc2
->address
= (reloc
->address
10457 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10458 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10459 reloc2
->addend
= fixp
->fx_addnumber
;
10460 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10461 assert (reloc2
->howto
!= NULL
);
10463 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10467 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10470 reloc3
->address
+= 4;
10473 if (mips_pic
== NO_PIC
)
10475 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10476 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10478 else if (mips_pic
== SVR4_PIC
)
10480 switch (fixp
->fx_r_type
)
10484 case BFD_RELOC_MIPS_GOT16
:
10486 case BFD_RELOC_MIPS_CALL16
:
10487 case BFD_RELOC_MIPS_GOT_LO16
:
10488 case BFD_RELOC_MIPS_CALL_LO16
:
10489 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10497 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10498 fixup_segment converted a non-PC relative reloc into a PC
10499 relative reloc. In such a case, we need to convert the reloc
10501 code
= fixp
->fx_r_type
;
10502 if (fixp
->fx_pcrel
)
10507 code
= BFD_RELOC_8_PCREL
;
10510 code
= BFD_RELOC_16_PCREL
;
10513 code
= BFD_RELOC_32_PCREL
;
10516 code
= BFD_RELOC_64_PCREL
;
10518 case BFD_RELOC_8_PCREL
:
10519 case BFD_RELOC_16_PCREL
:
10520 case BFD_RELOC_32_PCREL
:
10521 case BFD_RELOC_64_PCREL
:
10522 case BFD_RELOC_16_PCREL_S2
:
10523 case BFD_RELOC_PCREL_HI16_S
:
10524 case BFD_RELOC_PCREL_LO16
:
10527 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10528 "Cannot make %s relocation PC relative",
10529 bfd_get_reloc_code_name (code
));
10533 /* To support a PC relative reloc when generating embedded PIC code
10534 for ECOFF, we use a Cygnus extension. We check for that here to
10535 make sure that we don't let such a reloc escape normally. */
10536 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10537 && code
== BFD_RELOC_16_PCREL_S2
10538 && mips_pic
!= EMBEDDED_PIC
)
10539 reloc
->howto
= NULL
;
10541 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10543 if (reloc
->howto
== NULL
)
10545 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10546 "Can not represent %s relocation in this object file format",
10547 bfd_get_reloc_code_name (code
));
10554 /* Relax a machine dependent frag. This returns the amount by which
10555 the current size of the frag should change. */
10558 mips_relax_frag (fragp
, stretch
)
10562 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10565 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10567 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10569 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10574 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10576 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10583 /* Convert a machine dependent frag. */
10586 md_convert_frag (abfd
, asec
, fragp
)
10594 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10597 register const struct mips16_immed_operand
*op
;
10598 boolean small
, ext
;
10601 unsigned long insn
;
10602 boolean use_extend
;
10603 unsigned short extend
;
10605 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10606 op
= mips16_immed_operands
;
10607 while (op
->type
!= type
)
10610 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10621 resolve_symbol_value (fragp
->fr_symbol
);
10622 val
= S_GET_VALUE (fragp
->fr_symbol
);
10627 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10629 /* The rules for the base address of a PC relative reloc are
10630 complicated; see mips16_extended_frag. */
10631 if (type
== 'p' || type
== 'q')
10636 /* Ignore the low bit in the target, since it will be
10637 set for a text label. */
10638 if ((val
& 1) != 0)
10641 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10643 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10646 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10649 /* Make sure the section winds up with the alignment we have
10652 record_alignment (asec
, op
->shift
);
10656 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10657 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10658 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10659 "extended instruction in delay slot");
10661 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10663 if (target_big_endian
)
10664 insn
= bfd_getb16 (buf
);
10666 insn
= bfd_getl16 (buf
);
10668 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10669 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10670 small
, ext
, &insn
, &use_extend
, &extend
);
10674 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10675 fragp
->fr_fix
+= 2;
10679 md_number_to_chars (buf
, insn
, 2);
10680 fragp
->fr_fix
+= 2;
10685 if (fragp
->fr_opcode
== NULL
)
10688 old
= RELAX_OLD (fragp
->fr_subtype
);
10689 new = RELAX_NEW (fragp
->fr_subtype
);
10690 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10693 memcpy (fixptr
- old
, fixptr
, new);
10695 fragp
->fr_fix
+= new - old
;
10701 /* This function is called after the relocs have been generated.
10702 We've been storing mips16 text labels as odd. Here we convert them
10703 back to even for the convenience of the debugger. */
10706 mips_frob_file_after_relocs ()
10709 unsigned int count
, i
;
10711 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10714 syms
= bfd_get_outsymbols (stdoutput
);
10715 count
= bfd_get_symcount (stdoutput
);
10716 for (i
= 0; i
< count
; i
++, syms
++)
10718 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10719 && ((*syms
)->value
& 1) != 0)
10721 (*syms
)->value
&= ~1;
10722 /* If the symbol has an odd size, it was probably computed
10723 incorrectly, so adjust that as well. */
10724 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10725 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10732 /* This function is called whenever a label is defined. It is used
10733 when handling branch delays; if a branch has a label, we assume we
10734 can not move it. */
10737 mips_define_label (sym
)
10740 struct insn_label_list
*l
;
10742 if (free_insn_labels
== NULL
)
10743 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10746 l
= free_insn_labels
;
10747 free_insn_labels
= l
->next
;
10751 l
->next
= insn_labels
;
10755 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10757 /* Some special processing for a MIPS ELF file. */
10760 mips_elf_final_processing ()
10762 /* Write out the register information. */
10767 s
.ri_gprmask
= mips_gprmask
;
10768 s
.ri_cprmask
[0] = mips_cprmask
[0];
10769 s
.ri_cprmask
[1] = mips_cprmask
[1];
10770 s
.ri_cprmask
[2] = mips_cprmask
[2];
10771 s
.ri_cprmask
[3] = mips_cprmask
[3];
10772 /* The gp_value field is set by the MIPS ELF backend. */
10774 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10775 ((Elf32_External_RegInfo
*)
10776 mips_regmask_frag
));
10780 Elf64_Internal_RegInfo s
;
10782 s
.ri_gprmask
= mips_gprmask
;
10784 s
.ri_cprmask
[0] = mips_cprmask
[0];
10785 s
.ri_cprmask
[1] = mips_cprmask
[1];
10786 s
.ri_cprmask
[2] = mips_cprmask
[2];
10787 s
.ri_cprmask
[3] = mips_cprmask
[3];
10788 /* The gp_value field is set by the MIPS ELF backend. */
10790 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10791 ((Elf64_External_RegInfo
*)
10792 mips_regmask_frag
));
10795 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10796 sort of BFD interface for this. */
10797 if (mips_any_noreorder
)
10798 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10799 if (mips_pic
!= NO_PIC
)
10800 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10803 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10805 /* These functions should really be defined by the object file format,
10806 since they are related to debugging information. However, this
10807 code has to work for the a.out format, which does not define them,
10808 so we provide simple versions here. These don't actually generate
10809 any debugging information, but they do simple checking and someday
10810 somebody may make them useful. */
10814 struct loc
*loc_next
;
10815 unsigned long loc_fileno
;
10816 unsigned long loc_lineno
;
10817 unsigned long loc_offset
;
10818 unsigned short loc_delta
;
10819 unsigned short loc_count
;
10826 typedef struct proc
10828 struct proc
*proc_next
;
10829 struct symbol
*proc_isym
;
10830 struct symbol
*proc_end
;
10831 unsigned long proc_reg_mask
;
10832 unsigned long proc_reg_offset
;
10833 unsigned long proc_fpreg_mask
;
10834 unsigned long proc_fpreg_offset
;
10835 unsigned long proc_frameoffset
;
10836 unsigned long proc_framereg
;
10837 unsigned long proc_pcreg
;
10839 struct file
*proc_file
;
10844 typedef struct file
10846 struct file
*file_next
;
10847 unsigned long file_fileno
;
10848 struct symbol
*file_symbol
;
10849 struct symbol
*file_end
;
10850 struct proc
*file_proc
;
10855 static struct obstack proc_frags
;
10856 static procS
*proc_lastP
;
10857 static procS
*proc_rootP
;
10858 static int numprocs
;
10863 obstack_begin (&proc_frags
, 0x2000);
10869 /* check for premature end, nesting errors, etc */
10870 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10871 as_warn ("missing `.end' at end of assembly");
10880 if (*input_line_pointer
== '-')
10882 ++input_line_pointer
;
10885 if (!isdigit (*input_line_pointer
))
10886 as_bad ("Expected simple number.");
10887 if (input_line_pointer
[0] == '0')
10889 if (input_line_pointer
[1] == 'x')
10891 input_line_pointer
+= 2;
10892 while (isxdigit (*input_line_pointer
))
10895 val
|= hex_value (*input_line_pointer
++);
10897 return negative
? -val
: val
;
10901 ++input_line_pointer
;
10902 while (isdigit (*input_line_pointer
))
10905 val
|= *input_line_pointer
++ - '0';
10907 return negative
? -val
: val
;
10910 if (!isdigit (*input_line_pointer
))
10912 printf (" *input_line_pointer == '%c' 0x%02x\n",
10913 *input_line_pointer
, *input_line_pointer
);
10914 as_warn ("Invalid number");
10917 while (isdigit (*input_line_pointer
))
10920 val
+= *input_line_pointer
++ - '0';
10922 return negative
? -val
: val
;
10925 /* The .file directive; just like the usual .file directive, but there
10926 is an initial number which is the ECOFF file index. */
10934 line
= get_number ();
10939 /* The .end directive. */
10947 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10950 demand_empty_rest_of_line ();
10954 if (now_seg
!= text_section
)
10955 as_warn (".end not in text section");
10958 as_warn (".end and no .ent seen yet.");
10964 assert (S_GET_NAME (p
));
10965 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10966 as_warn (".end symbol does not match .ent symbol.");
10969 proc_lastP
->proc_end
= (symbolS
*) 1;
10972 /* The .aent and .ent directives. */
10982 symbolP
= get_symbol ();
10983 if (*input_line_pointer
== ',')
10984 input_line_pointer
++;
10985 SKIP_WHITESPACE ();
10986 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10987 number
= get_number ();
10988 if (now_seg
!= text_section
)
10989 as_warn (".ent or .aent not in text section.");
10991 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10992 as_warn ("missing `.end'");
10996 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10997 procP
->proc_isym
= symbolP
;
10998 procP
->proc_reg_mask
= 0;
10999 procP
->proc_reg_offset
= 0;
11000 procP
->proc_fpreg_mask
= 0;
11001 procP
->proc_fpreg_offset
= 0;
11002 procP
->proc_frameoffset
= 0;
11003 procP
->proc_framereg
= 0;
11004 procP
->proc_pcreg
= 0;
11005 procP
->proc_end
= NULL
;
11006 procP
->proc_next
= NULL
;
11008 proc_lastP
->proc_next
= procP
;
11010 proc_rootP
= procP
;
11011 proc_lastP
= procP
;
11014 demand_empty_rest_of_line ();
11017 /* The .frame directive. */
11030 frame_reg
= tc_get_register (1);
11031 if (*input_line_pointer
== ',')
11032 input_line_pointer
++;
11033 frame_off
= get_absolute_expression ();
11034 if (*input_line_pointer
== ',')
11035 input_line_pointer
++;
11036 pcreg
= tc_get_register (0);
11038 /* bob third eye */
11039 assert (proc_rootP
);
11040 proc_rootP
->proc_framereg
= frame_reg
;
11041 proc_rootP
->proc_frameoffset
= frame_off
;
11042 proc_rootP
->proc_pcreg
= pcreg
;
11043 /* bob macho .frame */
11045 /* We don't have to write out a frame stab for unoptimized code. */
11046 if (!(frame_reg
== FP
&& frame_off
== 0))
11049 as_warn ("No .ent for .frame to use.");
11050 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11051 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11052 S_SET_TYPE (symP
, N_RMASK
);
11053 S_SET_OTHER (symP
, 0);
11054 S_SET_DESC (symP
, 0);
11055 symP
->sy_forward
= proc_lastP
->proc_isym
;
11056 /* bob perhaps I should have used pseudo set */
11058 demand_empty_rest_of_line ();
11062 /* The .fmask and .mask directives. */
11069 char str
[100], *strP
;
11075 mask
= get_number ();
11076 if (*input_line_pointer
== ',')
11077 input_line_pointer
++;
11078 off
= get_absolute_expression ();
11080 /* bob only for coff */
11081 assert (proc_rootP
);
11082 if (reg_type
== 'F')
11084 proc_rootP
->proc_fpreg_mask
= mask
;
11085 proc_rootP
->proc_fpreg_offset
= off
;
11089 proc_rootP
->proc_reg_mask
= mask
;
11090 proc_rootP
->proc_reg_offset
= off
;
11093 /* bob macho .mask + .fmask */
11095 /* We don't have to write out a mask stab if no saved regs. */
11099 as_warn ("No .ent for .mask to use.");
11101 for (i
= 0; i
< 32; i
++)
11105 sprintf (strP
, "%c%d,", reg_type
, i
);
11106 strP
+= strlen (strP
);
11110 sprintf (strP
, ";%d,", off
);
11111 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11112 S_SET_TYPE (symP
, N_RMASK
);
11113 S_SET_OTHER (symP
, 0);
11114 S_SET_DESC (symP
, 0);
11115 symP
->sy_forward
= proc_lastP
->proc_isym
;
11116 /* bob perhaps I should have used pseudo set */
11121 /* The .loc directive. */
11132 assert (now_seg
== text_section
);
11134 lineno
= get_number ();
11135 addroff
= frag_now_fix ();
11137 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11138 S_SET_TYPE (symbolP
, N_SLINE
);
11139 S_SET_OTHER (symbolP
, 0);
11140 S_SET_DESC (symbolP
, lineno
);
11141 symbolP
->sy_segment
= now_seg
;