1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian
;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode
*insn_mo
;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode
;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p
: 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p
: 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p
: 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p
: 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p
: 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi
= NO_ABI
;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls
= FALSE
;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared
= TRUE
;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros
;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float
;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float
;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32
= -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32
= -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float
= 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float
= 0;
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
296 /* at */ ATREG
, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
298 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask
;
305 unsigned long mips_cprmask
[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa
= ISA_UNKNOWN
;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16
;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips
;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d
;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx
;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips
;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp
;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2 \
354 || mips_opts.micromips)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2
;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2 \
364 || mips_opts.micromips)
366 /* True if -mmt was passed or implied by arguments passed on the
367 command line (e.g., by -march). */
368 static int file_ase_mt
;
370 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
371 || mips_opts.isa == ISA_MIPS64R2)
373 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
374 || mips_opts.isa == ISA_MIPS64R2 \
375 || mips_opts.micromips)
377 /* The argument of the -march= flag. The architecture we are assembling. */
378 static int file_mips_arch
= CPU_UNKNOWN
;
379 static const char *mips_arch_string
;
381 /* The argument of the -mtune= flag. The architecture for which we
383 static int mips_tune
= CPU_UNKNOWN
;
384 static const char *mips_tune_string
;
386 /* True when generating 32-bit code for a 64-bit processor. */
387 static int mips_32bitmode
= 0;
389 /* True if the given ABI requires 32-bit registers. */
390 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
392 /* Likewise 64-bit registers. */
393 #define ABI_NEEDS_64BIT_REGS(ABI) \
395 || (ABI) == N64_ABI \
398 /* Return true if ISA supports 64 bit wide gp registers. */
399 #define ISA_HAS_64BIT_REGS(ISA) \
400 ((ISA) == ISA_MIPS3 \
401 || (ISA) == ISA_MIPS4 \
402 || (ISA) == ISA_MIPS5 \
403 || (ISA) == ISA_MIPS64 \
404 || (ISA) == ISA_MIPS64R2)
406 /* Return true if ISA supports 64 bit wide float registers. */
407 #define ISA_HAS_64BIT_FPRS(ISA) \
408 ((ISA) == ISA_MIPS3 \
409 || (ISA) == ISA_MIPS4 \
410 || (ISA) == ISA_MIPS5 \
411 || (ISA) == ISA_MIPS32R2 \
412 || (ISA) == ISA_MIPS64 \
413 || (ISA) == ISA_MIPS64R2)
415 /* Return true if ISA supports 64-bit right rotate (dror et al.)
417 #define ISA_HAS_DROR(ISA) \
418 ((ISA) == ISA_MIPS64R2 \
419 || (mips_opts.micromips \
420 && ISA_HAS_64BIT_REGS (ISA)) \
423 /* Return true if ISA supports 32-bit right rotate (ror et al.)
425 #define ISA_HAS_ROR(ISA) \
426 ((ISA) == ISA_MIPS32R2 \
427 || (ISA) == ISA_MIPS64R2 \
428 || mips_opts.ase_smartmips \
429 || mips_opts.micromips \
432 /* Return true if ISA supports single-precision floats in odd registers. */
433 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
434 ((ISA) == ISA_MIPS32 \
435 || (ISA) == ISA_MIPS32R2 \
436 || (ISA) == ISA_MIPS64 \
437 || (ISA) == ISA_MIPS64R2)
439 /* Return true if ISA supports move to/from high part of a 64-bit
440 floating-point register. */
441 #define ISA_HAS_MXHC1(ISA) \
442 ((ISA) == ISA_MIPS32R2 \
443 || (ISA) == ISA_MIPS64R2)
445 #define HAVE_32BIT_GPRS \
446 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
448 #define HAVE_32BIT_FPRS \
449 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
451 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
452 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
454 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
456 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
458 /* True if relocations are stored in-place. */
459 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
461 /* The ABI-derived address size. */
462 #define HAVE_64BIT_ADDRESSES \
463 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
464 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
466 /* The size of symbolic constants (i.e., expressions of the form
467 "SYMBOL" or "SYMBOL + OFFSET"). */
468 #define HAVE_32BIT_SYMBOLS \
469 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
470 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
472 /* Addresses are loaded in different ways, depending on the address size
473 in use. The n32 ABI Documentation also mandates the use of additions
474 with overflow checking, but existing implementations don't follow it. */
475 #define ADDRESS_ADD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
478 #define ADDRESS_ADDI_INSN \
479 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
481 #define ADDRESS_LOAD_INSN \
482 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
484 #define ADDRESS_STORE_INSN \
485 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
487 /* Return true if the given CPU supports the MIPS16 ASE. */
488 #define CPU_HAS_MIPS16(cpu) \
489 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
490 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
492 /* Return true if the given CPU supports the microMIPS ASE. */
493 #define CPU_HAS_MICROMIPS(cpu) 0
495 /* True if CPU has a dror instruction. */
496 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
498 /* True if CPU has a ror instruction. */
499 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
501 /* True if CPU is in the Octeon family */
502 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
504 /* True if CPU has seq/sne and seqi/snei instructions. */
505 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
507 /* True, if CPU has support for ldc1 and sdc1. */
508 #define CPU_HAS_LDC1_SDC1(CPU) \
509 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
511 /* True if mflo and mfhi can be immediately followed by instructions
512 which write to the HI and LO registers.
514 According to MIPS specifications, MIPS ISAs I, II, and III need
515 (at least) two instructions between the reads of HI/LO and
516 instructions which write them, and later ISAs do not. Contradicting
517 the MIPS specifications, some MIPS IV processor user manuals (e.g.
518 the UM for the NEC Vr5000) document needing the instructions between
519 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
520 MIPS64 and later ISAs to have the interlocks, plus any specific
521 earlier-ISA CPUs for which CPU documentation declares that the
522 instructions are really interlocked. */
523 #define hilo_interlocks \
524 (mips_opts.isa == ISA_MIPS32 \
525 || mips_opts.isa == ISA_MIPS32R2 \
526 || mips_opts.isa == ISA_MIPS64 \
527 || mips_opts.isa == ISA_MIPS64R2 \
528 || mips_opts.arch == CPU_R4010 \
529 || mips_opts.arch == CPU_R5900 \
530 || mips_opts.arch == CPU_R10000 \
531 || mips_opts.arch == CPU_R12000 \
532 || mips_opts.arch == CPU_R14000 \
533 || mips_opts.arch == CPU_R16000 \
534 || mips_opts.arch == CPU_RM7000 \
535 || mips_opts.arch == CPU_VR5500 \
536 || mips_opts.micromips \
539 /* Whether the processor uses hardware interlocks to protect reads
540 from the GPRs after they are loaded from memory, and thus does not
541 require nops to be inserted. This applies to instructions marked
542 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
543 level I and microMIPS mode instructions are always interlocked. */
544 #define gpr_interlocks \
545 (mips_opts.isa != ISA_MIPS1 \
546 || mips_opts.arch == CPU_R3900 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.micromips \
551 /* Whether the processor uses hardware interlocks to avoid delays
552 required by coprocessor instructions, and thus does not require
553 nops to be inserted. This applies to instructions marked
554 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
555 between instructions marked INSN_WRITE_COND_CODE and ones marked
556 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
557 levels I, II, and III and microMIPS mode instructions are always
559 /* Itbl support may require additional care here. */
560 #define cop_interlocks \
561 ((mips_opts.isa != ISA_MIPS1 \
562 && mips_opts.isa != ISA_MIPS2 \
563 && mips_opts.isa != ISA_MIPS3) \
564 || mips_opts.arch == CPU_R4300 \
565 || mips_opts.micromips \
568 /* Whether the processor uses hardware interlocks to protect reads
569 from coprocessor registers after they are loaded from memory, and
570 thus does not require nops to be inserted. This applies to
571 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
572 requires at MIPS ISA level I and microMIPS mode instructions are
573 always interlocked. */
574 #define cop_mem_interlocks \
575 (mips_opts.isa != ISA_MIPS1 \
576 || mips_opts.micromips \
579 /* Is this a mfhi or mflo instruction? */
580 #define MF_HILO_INSN(PINFO) \
581 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
583 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
584 has been selected. This implies, in particular, that addresses of text
585 labels have their LSB set. */
586 #define HAVE_CODE_COMPRESSION \
587 ((mips_opts.mips16 | mips_opts.micromips) != 0)
589 /* MIPS PIC level. */
591 enum mips_pic_level mips_pic
;
593 /* 1 if we should generate 32 bit offsets from the $gp register in
594 SVR4_PIC mode. Currently has no meaning in other modes. */
595 static int mips_big_got
= 0;
597 /* 1 if trap instructions should used for overflow rather than break
599 static int mips_trap
= 0;
601 /* 1 if double width floating point constants should not be constructed
602 by assembling two single width halves into two single width floating
603 point registers which just happen to alias the double width destination
604 register. On some architectures this aliasing can be disabled by a bit
605 in the status register, and the setting of this bit cannot be determined
606 automatically at assemble time. */
607 static int mips_disable_float_construction
;
609 /* Non-zero if any .set noreorder directives were used. */
611 static int mips_any_noreorder
;
613 /* Non-zero if nops should be inserted when the register referenced in
614 an mfhi/mflo instruction is read in the next two instructions. */
615 static int mips_7000_hilo_fix
;
617 /* The size of objects in the small data section. */
618 static unsigned int g_switch_value
= 8;
619 /* Whether the -G option was used. */
620 static int g_switch_seen
= 0;
625 /* If we can determine in advance that GP optimization won't be
626 possible, we can skip the relaxation stuff that tries to produce
627 GP-relative references. This makes delay slot optimization work
630 This function can only provide a guess, but it seems to work for
631 gcc output. It needs to guess right for gcc, otherwise gcc
632 will put what it thinks is a GP-relative instruction in a branch
635 I don't know if a fix is needed for the SVR4_PIC mode. I've only
636 fixed it for the non-PIC mode. KR 95/04/07 */
637 static int nopic_need_relax (symbolS
*, int);
639 /* handle of the OPCODE hash table */
640 static struct hash_control
*op_hash
= NULL
;
642 /* The opcode hash table we use for the mips16. */
643 static struct hash_control
*mips16_op_hash
= NULL
;
645 /* The opcode hash table we use for the microMIPS ASE. */
646 static struct hash_control
*micromips_op_hash
= NULL
;
648 /* This array holds the chars that always start a comment. If the
649 pre-processor is disabled, these aren't very useful */
650 const char comment_chars
[] = "#";
652 /* This array holds the chars that only start a comment at the beginning of
653 a line. If the line seems to have the form '# 123 filename'
654 .line and .file directives will appear in the pre-processed output */
655 /* Note that input_file.c hand checks for '#' at the beginning of the
656 first line of the input file. This is because the compiler outputs
657 #NO_APP at the beginning of its output. */
658 /* Also note that C style comments are always supported. */
659 const char line_comment_chars
[] = "#";
661 /* This array holds machine specific line separator characters. */
662 const char line_separator_chars
[] = ";";
664 /* Chars that can be used to separate mant from exp in floating point nums */
665 const char EXP_CHARS
[] = "eE";
667 /* Chars that mean this number is a floating point constant */
670 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
672 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
673 changed in read.c . Ideally it shouldn't have to know about it at all,
674 but nothing is ideal around here.
677 static char *insn_error
;
679 static int auto_align
= 1;
681 /* When outputting SVR4 PIC code, the assembler needs to know the
682 offset in the stack frame from which to restore the $gp register.
683 This is set by the .cprestore pseudo-op, and saved in this
685 static offsetT mips_cprestore_offset
= -1;
687 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
688 more optimizations, it can use a register value instead of a memory-saved
689 offset and even an other register than $gp as global pointer. */
690 static offsetT mips_cpreturn_offset
= -1;
691 static int mips_cpreturn_register
= -1;
692 static int mips_gp_register
= GP
;
693 static int mips_gprel_offset
= 0;
695 /* Whether mips_cprestore_offset has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_cprestore_valid
= 0;
699 /* This is the register which holds the stack frame, as set by the
700 .frame pseudo-op. This is needed to implement .cprestore. */
701 static int mips_frame_reg
= SP
;
703 /* Whether mips_frame_reg has been set in the current function
704 (or whether it has already been warned about, if not). */
705 static int mips_frame_reg_valid
= 0;
707 /* To output NOP instructions correctly, we need to keep information
708 about the previous two instructions. */
710 /* Whether we are optimizing. The default value of 2 means to remove
711 unneeded NOPs and swap branch instructions when possible. A value
712 of 1 means to not swap branches. A value of 0 means to always
714 static int mips_optimize
= 2;
716 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
717 equivalent to seeing no -g option at all. */
718 static int mips_debug
= 0;
720 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
721 #define MAX_VR4130_NOPS 4
723 /* The maximum number of NOPs needed to fill delay slots. */
724 #define MAX_DELAY_NOPS 2
726 /* The maximum number of NOPs needed for any purpose. */
729 /* A list of previous instructions, with index 0 being the most recent.
730 We need to look back MAX_NOPS instructions when filling delay slots
731 or working around processor errata. We need to look back one
732 instruction further if we're thinking about using history[0] to
733 fill a branch delay slot. */
734 static struct mips_cl_insn history
[1 + MAX_NOPS
];
736 /* Nop instructions used by emit_nop. */
737 static struct mips_cl_insn nop_insn
;
738 static struct mips_cl_insn mips16_nop_insn
;
739 static struct mips_cl_insn micromips_nop16_insn
;
740 static struct mips_cl_insn micromips_nop32_insn
;
742 /* The appropriate nop for the current mode. */
743 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
744 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
746 /* The size of NOP_INSN in bytes. */
747 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
749 /* If this is set, it points to a frag holding nop instructions which
750 were inserted before the start of a noreorder section. If those
751 nops turn out to be unnecessary, the size of the frag can be
753 static fragS
*prev_nop_frag
;
755 /* The number of nop instructions we created in prev_nop_frag. */
756 static int prev_nop_frag_holds
;
758 /* The number of nop instructions that we know we need in
760 static int prev_nop_frag_required
;
762 /* The number of instructions we've seen since prev_nop_frag. */
763 static int prev_nop_frag_since
;
765 /* For ECOFF and ELF, relocations against symbols are done in two
766 parts, with a HI relocation and a LO relocation. Each relocation
767 has only 16 bits of space to store an addend. This means that in
768 order for the linker to handle carries correctly, it must be able
769 to locate both the HI and the LO relocation. This means that the
770 relocations must appear in order in the relocation table.
772 In order to implement this, we keep track of each unmatched HI
773 relocation. We then sort them so that they immediately precede the
774 corresponding LO relocation. */
779 struct mips_hi_fixup
*next
;
782 /* The section this fixup is in. */
786 /* The list of unmatched HI relocs. */
788 static struct mips_hi_fixup
*mips_hi_fixup_list
;
790 /* The frag containing the last explicit relocation operator.
791 Null if explicit relocations have not been used. */
793 static fragS
*prev_reloc_op_frag
;
795 /* Map normal MIPS register numbers to mips16 register numbers. */
797 #define X ILLEGAL_REG
798 static const int mips32_to_16_reg_map
[] =
800 X
, X
, 2, 3, 4, 5, 6, 7,
801 X
, X
, X
, X
, X
, X
, X
, X
,
802 0, 1, X
, X
, X
, X
, X
, X
,
803 X
, X
, X
, X
, X
, X
, X
, X
807 /* Map mips16 register numbers to normal MIPS register numbers. */
809 static const unsigned int mips16_to_32_reg_map
[] =
811 16, 17, 2, 3, 4, 5, 6, 7
814 /* Map normal MIPS register numbers to microMIPS register numbers. */
816 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
819 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
822 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
824 #define X ILLEGAL_REG
825 /* reg type h: 4, 5, 6. */
826 static const int mips32_to_micromips_reg_h_map
[] =
828 X
, X
, X
, X
, 4, 5, 6, X
,
829 X
, X
, X
, X
, X
, X
, X
, X
,
830 X
, X
, X
, X
, X
, X
, X
, X
,
831 X
, X
, X
, X
, X
, X
, X
, X
834 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
835 static const int mips32_to_micromips_reg_m_map
[] =
837 0, X
, 2, 3, X
, X
, X
, X
,
838 X
, X
, X
, X
, X
, X
, X
, X
,
839 4, 1, 5, 6, 7, X
, X
, X
,
840 X
, X
, X
, X
, X
, X
, X
, X
843 /* reg type q: 0, 2-7. 17. */
844 static const int mips32_to_micromips_reg_q_map
[] =
846 0, X
, 2, 3, 4, 5, 6, 7,
847 X
, X
, X
, X
, X
, X
, X
, X
,
848 X
, 1, X
, X
, X
, X
, X
, X
,
849 X
, X
, X
, X
, X
, X
, X
, X
852 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
855 /* Map microMIPS register numbers to normal MIPS register numbers. */
857 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
859 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
860 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
862 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
864 /* The microMIPS registers with type h. */
865 static const unsigned int micromips_to_32_reg_h_map
[] =
867 5, 5, 6, 4, 4, 4, 4, 4
870 /* The microMIPS registers with type i. */
871 static const unsigned int micromips_to_32_reg_i_map
[] =
873 6, 7, 7, 21, 22, 5, 6, 7
876 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
878 /* The microMIPS registers with type m. */
879 static const unsigned int micromips_to_32_reg_m_map
[] =
881 0, 17, 2, 3, 16, 18, 19, 20
884 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
886 /* The microMIPS registers with type q. */
887 static const unsigned int micromips_to_32_reg_q_map
[] =
889 0, 17, 2, 3, 4, 5, 6, 7
892 /* microMIPS imm type B. */
893 static const int micromips_imm_b_map
[] =
895 1, 4, 8, 12, 16, 20, 24, -1
898 /* microMIPS imm type C. */
899 static const int micromips_imm_c_map
[] =
901 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
904 /* Classifies the kind of instructions we're interested in when
905 implementing -mfix-vr4120. */
906 enum fix_vr4120_class
914 NUM_FIX_VR4120_CLASSES
917 /* ...likewise -mfix-loongson2f-jump. */
918 static bfd_boolean mips_fix_loongson2f_jump
;
920 /* ...likewise -mfix-loongson2f-nop. */
921 static bfd_boolean mips_fix_loongson2f_nop
;
923 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
924 static bfd_boolean mips_fix_loongson2f
;
926 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
927 there must be at least one other instruction between an instruction
928 of type X and an instruction of type Y. */
929 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
931 /* True if -mfix-vr4120 is in force. */
932 static int mips_fix_vr4120
;
934 /* ...likewise -mfix-vr4130. */
935 static int mips_fix_vr4130
;
937 /* ...likewise -mfix-24k. */
938 static int mips_fix_24k
;
940 /* ...likewise -mfix-cn63xxp1 */
941 static bfd_boolean mips_fix_cn63xxp1
;
943 /* We don't relax branches by default, since this causes us to expand
944 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
945 fail to compute the offset before expanding the macro to the most
946 efficient expansion. */
948 static int mips_relax_branch
;
950 /* The expansion of many macros depends on the type of symbol that
951 they refer to. For example, when generating position-dependent code,
952 a macro that refers to a symbol may have two different expansions,
953 one which uses GP-relative addresses and one which uses absolute
954 addresses. When generating SVR4-style PIC, a macro may have
955 different expansions for local and global symbols.
957 We handle these situations by generating both sequences and putting
958 them in variant frags. In position-dependent code, the first sequence
959 will be the GP-relative one and the second sequence will be the
960 absolute one. In SVR4 PIC, the first sequence will be for global
961 symbols and the second will be for local symbols.
963 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
964 SECOND are the lengths of the two sequences in bytes. These fields
965 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
966 the subtype has the following flags:
969 Set if it has been decided that we should use the second
970 sequence instead of the first.
973 Set in the first variant frag if the macro's second implementation
974 is longer than its first. This refers to the macro as a whole,
975 not an individual relaxation.
978 Set in the first variant frag if the macro appeared in a .set nomacro
979 block and if one alternative requires a warning but the other does not.
982 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
985 RELAX_DELAY_SLOT_16BIT
986 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
989 RELAX_DELAY_SLOT_SIZE_FIRST
990 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
991 the macro is of the wrong size for the branch delay slot.
993 RELAX_DELAY_SLOT_SIZE_SECOND
994 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
995 the macro is of the wrong size for the branch delay slot.
997 The frag's "opcode" points to the first fixup for relaxable code.
999 Relaxable macros are generated using a sequence such as:
1001 relax_start (SYMBOL);
1002 ... generate first expansion ...
1004 ... generate second expansion ...
1007 The code and fixups for the unwanted alternative are discarded
1008 by md_convert_frag. */
1009 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1011 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1012 #define RELAX_SECOND(X) ((X) & 0xff)
1013 #define RELAX_USE_SECOND 0x10000
1014 #define RELAX_SECOND_LONGER 0x20000
1015 #define RELAX_NOMACRO 0x40000
1016 #define RELAX_DELAY_SLOT 0x80000
1017 #define RELAX_DELAY_SLOT_16BIT 0x100000
1018 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1019 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1021 /* Branch without likely bit. If label is out of range, we turn:
1023 beq reg1, reg2, label
1033 with the following opcode replacements:
1040 bltzal <-> bgezal (with jal label instead of j label)
1042 Even though keeping the delay slot instruction in the delay slot of
1043 the branch would be more efficient, it would be very tricky to do
1044 correctly, because we'd have to introduce a variable frag *after*
1045 the delay slot instruction, and expand that instead. Let's do it
1046 the easy way for now, even if the branch-not-taken case now costs
1047 one additional instruction. Out-of-range branches are not supposed
1048 to be common, anyway.
1050 Branch likely. If label is out of range, we turn:
1052 beql reg1, reg2, label
1053 delay slot (annulled if branch not taken)
1062 delay slot (executed only if branch taken)
1065 It would be possible to generate a shorter sequence by losing the
1066 likely bit, generating something like:
1071 delay slot (executed only if branch taken)
1083 bltzall -> bgezal (with jal label instead of j label)
1084 bgezall -> bltzal (ditto)
1087 but it's not clear that it would actually improve performance. */
1088 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1089 ((relax_substateT) \
1092 | ((toofar) ? 0x20 : 0) \
1093 | ((link) ? 0x40 : 0) \
1094 | ((likely) ? 0x80 : 0) \
1095 | ((uncond) ? 0x100 : 0)))
1096 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1097 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1098 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1099 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1100 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1101 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1103 /* For mips16 code, we use an entirely different form of relaxation.
1104 mips16 supports two versions of most instructions which take
1105 immediate values: a small one which takes some small value, and a
1106 larger one which takes a 16 bit value. Since branches also follow
1107 this pattern, relaxing these values is required.
1109 We can assemble both mips16 and normal MIPS code in a single
1110 object. Therefore, we need to support this type of relaxation at
1111 the same time that we support the relaxation described above. We
1112 use the high bit of the subtype field to distinguish these cases.
1114 The information we store for this type of relaxation is the
1115 argument code found in the opcode file for this relocation, whether
1116 the user explicitly requested a small or extended form, and whether
1117 the relocation is in a jump or jal delay slot. That tells us the
1118 size of the value, and how it should be stored. We also store
1119 whether the fragment is considered to be extended or not. We also
1120 store whether this is known to be a branch to a different section,
1121 whether we have tried to relax this frag yet, and whether we have
1122 ever extended a PC relative fragment because of a shift count. */
1123 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1126 | ((small) ? 0x100 : 0) \
1127 | ((ext) ? 0x200 : 0) \
1128 | ((dslot) ? 0x400 : 0) \
1129 | ((jal_dslot) ? 0x800 : 0))
1130 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1131 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1132 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1133 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1134 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1135 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1136 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1137 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1138 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1139 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1140 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1141 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1143 /* For microMIPS code, we use relaxation similar to one we use for
1144 MIPS16 code. Some instructions that take immediate values support
1145 two encodings: a small one which takes some small value, and a
1146 larger one which takes a 16 bit value. As some branches also follow
1147 this pattern, relaxing these values is required.
1149 We can assemble both microMIPS and normal MIPS code in a single
1150 object. Therefore, we need to support this type of relaxation at
1151 the same time that we support the relaxation described above. We
1152 use one of the high bits of the subtype field to distinguish these
1155 The information we store for this type of relaxation is the argument
1156 code found in the opcode file for this relocation, the register
1157 selected as the assembler temporary, whether the branch is
1158 unconditional, whether it is compact, whether it stores the link
1159 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1160 branches to a sequence of instructions is enabled, and whether the
1161 displacement of a branch is too large to fit as an immediate argument
1162 of a 16-bit and a 32-bit branch, respectively. */
1163 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1164 relax32, toofar16, toofar32) \
1167 | (((at) & 0x1f) << 8) \
1168 | ((uncond) ? 0x2000 : 0) \
1169 | ((compact) ? 0x4000 : 0) \
1170 | ((link) ? 0x8000 : 0) \
1171 | ((relax32) ? 0x10000 : 0) \
1172 | ((toofar16) ? 0x20000 : 0) \
1173 | ((toofar32) ? 0x40000 : 0))
1174 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1175 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1176 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1177 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1178 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1179 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1180 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1182 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1183 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1184 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1185 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1186 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1187 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1189 /* Sign-extend 16-bit value X. */
1190 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1192 /* Is the given value a sign-extended 32-bit value? */
1193 #define IS_SEXT_32BIT_NUM(x) \
1194 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1195 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1197 /* Is the given value a sign-extended 16-bit value? */
1198 #define IS_SEXT_16BIT_NUM(x) \
1199 (((x) &~ (offsetT) 0x7fff) == 0 \
1200 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1202 /* Is the given value a sign-extended 12-bit value? */
1203 #define IS_SEXT_12BIT_NUM(x) \
1204 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1212 VALUE << SHIFT. VALUE is evaluated exactly once. */
1213 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1214 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1215 | (((VALUE) & (MASK)) << (SHIFT)))
1217 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1219 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1220 (((STRUCT) >> (SHIFT)) & (MASK))
1222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1223 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1225 include/opcode/mips.h specifies operand fields using the macros
1226 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1227 with "MIPS16OP" instead of "OP". */
1228 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1231 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1232 OP_MASK_##FIELD, OP_SH_##FIELD); \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1237 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1241 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1242 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1244 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1245 : EXTRACT_BITS ((INSN).insn_opcode, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1247 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1248 EXTRACT_BITS ((INSN).insn_opcode, \
1249 MIPS16OP_MASK_##FIELD, \
1250 MIPS16OP_SH_##FIELD)
1252 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1253 #define MIPS16_EXTEND (0xf000U << 16)
1255 /* Whether or not we are emitting a branch-likely macro. */
1256 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1258 /* Global variables used when generating relaxable macros. See the
1259 comment above RELAX_ENCODE for more details about how relaxation
1262 /* 0 if we're not emitting a relaxable macro.
1263 1 if we're emitting the first of the two relaxation alternatives.
1264 2 if we're emitting the second alternative. */
1267 /* The first relaxable fixup in the current frag. (In other words,
1268 the first fixup that refers to relaxable code.) */
1271 /* sizes[0] says how many bytes of the first alternative are stored in
1272 the current frag. Likewise sizes[1] for the second alternative. */
1273 unsigned int sizes
[2];
1275 /* The symbol on which the choice of sequence depends. */
1279 /* Global variables used to decide whether a macro needs a warning. */
1281 /* True if the macro is in a branch delay slot. */
1282 bfd_boolean delay_slot_p
;
1284 /* Set to the length in bytes required if the macro is in a delay slot
1285 that requires a specific length of instruction, otherwise zero. */
1286 unsigned int delay_slot_length
;
1288 /* For relaxable macros, sizes[0] is the length of the first alternative
1289 in bytes and sizes[1] is the length of the second alternative.
1290 For non-relaxable macros, both elements give the length of the
1292 unsigned int sizes
[2];
1294 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1295 instruction of the first alternative in bytes and first_insn_sizes[1]
1296 is the length of the first instruction of the second alternative.
1297 For non-relaxable macros, both elements give the length of the first
1298 instruction in bytes.
1300 Set to zero if we haven't yet seen the first instruction. */
1301 unsigned int first_insn_sizes
[2];
1303 /* For relaxable macros, insns[0] is the number of instructions for the
1304 first alternative and insns[1] is the number of instructions for the
1307 For non-relaxable macros, both elements give the number of
1308 instructions for the macro. */
1309 unsigned int insns
[2];
1311 /* The first variant frag for this macro. */
1313 } mips_macro_warning
;
1315 /* Prototypes for static functions. */
1317 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1319 static void append_insn
1320 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1321 bfd_boolean expansionp
);
1322 static void mips_no_prev_insn (void);
1323 static void macro_build (expressionS
*, const char *, const char *, ...);
1324 static void mips16_macro_build
1325 (expressionS
*, const char *, const char *, va_list *);
1326 static void load_register (int, expressionS
*, int);
1327 static void macro_start (void);
1328 static void macro_end (void);
1329 static void macro (struct mips_cl_insn
* ip
);
1330 static void mips16_macro (struct mips_cl_insn
* ip
);
1331 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1332 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1333 static void mips16_immed
1334 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1335 unsigned int, unsigned long *);
1336 static size_t my_getSmallExpression
1337 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1338 static void my_getExpression (expressionS
*, char *);
1339 static void s_align (int);
1340 static void s_change_sec (int);
1341 static void s_change_section (int);
1342 static void s_cons (int);
1343 static void s_float_cons (int);
1344 static void s_mips_globl (int);
1345 static void s_option (int);
1346 static void s_mipsset (int);
1347 static void s_abicalls (int);
1348 static void s_cpload (int);
1349 static void s_cpsetup (int);
1350 static void s_cplocal (int);
1351 static void s_cprestore (int);
1352 static void s_cpreturn (int);
1353 static void s_dtprelword (int);
1354 static void s_dtpreldword (int);
1355 static void s_tprelword (int);
1356 static void s_tpreldword (int);
1357 static void s_gpvalue (int);
1358 static void s_gpword (int);
1359 static void s_gpdword (int);
1360 static void s_cpadd (int);
1361 static void s_insn (int);
1362 static void md_obj_begin (void);
1363 static void md_obj_end (void);
1364 static void s_mips_ent (int);
1365 static void s_mips_end (int);
1366 static void s_mips_frame (int);
1367 static void s_mips_mask (int reg_type
);
1368 static void s_mips_stab (int);
1369 static void s_mips_weakext (int);
1370 static void s_mips_file (int);
1371 static void s_mips_loc (int);
1372 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1373 static int relaxed_branch_length (fragS
*, asection
*, int);
1374 static int validate_mips_insn (const struct mips_opcode
*);
1375 static int validate_micromips_insn (const struct mips_opcode
*);
1376 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1377 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1379 /* Table and functions used to map between CPU/ISA names, and
1380 ISA levels, and CPU numbers. */
1382 struct mips_cpu_info
1384 const char *name
; /* CPU or ISA name. */
1385 int flags
; /* ASEs available, or ISA flag. */
1386 int isa
; /* ISA level. */
1387 int cpu
; /* CPU number (default CPU if ISA). */
1390 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1391 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1392 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1393 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1394 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1395 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1396 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1397 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1399 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1400 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1401 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1405 The following pseudo-ops from the Kane and Heinrich MIPS book
1406 should be defined here, but are currently unsupported: .alias,
1407 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1409 The following pseudo-ops from the Kane and Heinrich MIPS book are
1410 specific to the type of debugging information being generated, and
1411 should be defined by the object format: .aent, .begin, .bend,
1412 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1415 The following pseudo-ops from the Kane and Heinrich MIPS book are
1416 not MIPS CPU specific, but are also not specific to the object file
1417 format. This file is probably the best place to define them, but
1418 they are not currently supported: .asm0, .endr, .lab, .struct. */
1420 static const pseudo_typeS mips_pseudo_table
[] =
1422 /* MIPS specific pseudo-ops. */
1423 {"option", s_option
, 0},
1424 {"set", s_mipsset
, 0},
1425 {"rdata", s_change_sec
, 'r'},
1426 {"sdata", s_change_sec
, 's'},
1427 {"livereg", s_ignore
, 0},
1428 {"abicalls", s_abicalls
, 0},
1429 {"cpload", s_cpload
, 0},
1430 {"cpsetup", s_cpsetup
, 0},
1431 {"cplocal", s_cplocal
, 0},
1432 {"cprestore", s_cprestore
, 0},
1433 {"cpreturn", s_cpreturn
, 0},
1434 {"dtprelword", s_dtprelword
, 0},
1435 {"dtpreldword", s_dtpreldword
, 0},
1436 {"tprelword", s_tprelword
, 0},
1437 {"tpreldword", s_tpreldword
, 0},
1438 {"gpvalue", s_gpvalue
, 0},
1439 {"gpword", s_gpword
, 0},
1440 {"gpdword", s_gpdword
, 0},
1441 {"cpadd", s_cpadd
, 0},
1442 {"insn", s_insn
, 0},
1444 /* Relatively generic pseudo-ops that happen to be used on MIPS
1446 {"asciiz", stringer
, 8 + 1},
1447 {"bss", s_change_sec
, 'b'},
1449 {"half", s_cons
, 1},
1450 {"dword", s_cons
, 3},
1451 {"weakext", s_mips_weakext
, 0},
1452 {"origin", s_org
, 0},
1453 {"repeat", s_rept
, 0},
1455 /* For MIPS this is non-standard, but we define it for consistency. */
1456 {"sbss", s_change_sec
, 'B'},
1458 /* These pseudo-ops are defined in read.c, but must be overridden
1459 here for one reason or another. */
1460 {"align", s_align
, 0},
1461 {"byte", s_cons
, 0},
1462 {"data", s_change_sec
, 'd'},
1463 {"double", s_float_cons
, 'd'},
1464 {"float", s_float_cons
, 'f'},
1465 {"globl", s_mips_globl
, 0},
1466 {"global", s_mips_globl
, 0},
1467 {"hword", s_cons
, 1},
1469 {"long", s_cons
, 2},
1470 {"octa", s_cons
, 4},
1471 {"quad", s_cons
, 3},
1472 {"section", s_change_section
, 0},
1473 {"short", s_cons
, 1},
1474 {"single", s_float_cons
, 'f'},
1475 {"stabd", s_mips_stab
, 'd'},
1476 {"stabn", s_mips_stab
, 'n'},
1477 {"stabs", s_mips_stab
, 's'},
1478 {"text", s_change_sec
, 't'},
1479 {"word", s_cons
, 2},
1481 { "extern", ecoff_directive_extern
, 0},
1486 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1488 /* These pseudo-ops should be defined by the object file format.
1489 However, a.out doesn't support them, so we have versions here. */
1490 {"aent", s_mips_ent
, 1},
1491 {"bgnb", s_ignore
, 0},
1492 {"end", s_mips_end
, 0},
1493 {"endb", s_ignore
, 0},
1494 {"ent", s_mips_ent
, 0},
1495 {"file", s_mips_file
, 0},
1496 {"fmask", s_mips_mask
, 'F'},
1497 {"frame", s_mips_frame
, 0},
1498 {"loc", s_mips_loc
, 0},
1499 {"mask", s_mips_mask
, 'R'},
1500 {"verstamp", s_ignore
, 0},
1504 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1505 purpose of the `.dc.a' internal pseudo-op. */
1508 mips_address_bytes (void)
1510 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1513 extern void pop_insert (const pseudo_typeS
*);
1516 mips_pop_insert (void)
1518 pop_insert (mips_pseudo_table
);
1519 if (! ECOFF_DEBUGGING
)
1520 pop_insert (mips_nonecoff_pseudo_table
);
1523 /* Symbols labelling the current insn. */
1525 struct insn_label_list
1527 struct insn_label_list
*next
;
1531 static struct insn_label_list
*free_insn_labels
;
1532 #define label_list tc_segment_info_data.labels
1534 static void mips_clear_insn_labels (void);
1535 static void mips_mark_labels (void);
1536 static void mips_compressed_mark_labels (void);
1539 mips_clear_insn_labels (void)
1541 register struct insn_label_list
**pl
;
1542 segment_info_type
*si
;
1546 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1549 si
= seg_info (now_seg
);
1550 *pl
= si
->label_list
;
1551 si
->label_list
= NULL
;
1555 /* Mark instruction labels in MIPS16/microMIPS mode. */
1558 mips_mark_labels (void)
1560 if (HAVE_CODE_COMPRESSION
)
1561 mips_compressed_mark_labels ();
1564 static char *expr_end
;
1566 /* Expressions which appear in instructions. These are set by
1569 static expressionS imm_expr
;
1570 static expressionS imm2_expr
;
1571 static expressionS offset_expr
;
1573 /* Relocs associated with imm_expr and offset_expr. */
1575 static bfd_reloc_code_real_type imm_reloc
[3]
1576 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1577 static bfd_reloc_code_real_type offset_reloc
[3]
1578 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1580 /* This is set to the resulting size of the instruction to be produced
1581 by mips16_ip if an explicit extension is used or by mips_ip if an
1582 explicit size is supplied. */
1584 static unsigned int forced_insn_length
;
1586 /* True if we are assembling an instruction. All dot symbols defined during
1587 this time should be treated as code labels. */
1589 static bfd_boolean mips_assembling_insn
;
1592 /* The pdr segment for per procedure frame/regmask info. Not used for
1595 static segT pdr_seg
;
1598 /* The default target format to use. */
1600 #if defined (TE_FreeBSD)
1601 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1602 #elif defined (TE_TMIPS)
1603 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1605 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1609 mips_target_format (void)
1611 switch (OUTPUT_FLAVOR
)
1613 case bfd_target_ecoff_flavour
:
1614 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1615 case bfd_target_coff_flavour
:
1617 case bfd_target_elf_flavour
:
1619 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1620 return (target_big_endian
1621 ? "elf32-bigmips-vxworks"
1622 : "elf32-littlemips-vxworks");
1624 return (target_big_endian
1625 ? (HAVE_64BIT_OBJECTS
1626 ? ELF_TARGET ("elf64-", "big")
1628 ? ELF_TARGET ("elf32-n", "big")
1629 : ELF_TARGET ("elf32-", "big")))
1630 : (HAVE_64BIT_OBJECTS
1631 ? ELF_TARGET ("elf64-", "little")
1633 ? ELF_TARGET ("elf32-n", "little")
1634 : ELF_TARGET ("elf32-", "little"))));
1641 /* Return the length of a microMIPS instruction in bytes. If bits of
1642 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1643 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1644 major opcode) will require further modifications to the opcode
1647 static inline unsigned int
1648 micromips_insn_length (const struct mips_opcode
*mo
)
1650 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1653 /* Return the length of MIPS16 instruction OPCODE. */
1655 static inline unsigned int
1656 mips16_opcode_length (unsigned long opcode
)
1658 return (opcode
>> 16) == 0 ? 2 : 4;
1661 /* Return the length of instruction INSN. */
1663 static inline unsigned int
1664 insn_length (const struct mips_cl_insn
*insn
)
1666 if (mips_opts
.micromips
)
1667 return micromips_insn_length (insn
->insn_mo
);
1668 else if (mips_opts
.mips16
)
1669 return mips16_opcode_length (insn
->insn_opcode
);
1674 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1677 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1682 insn
->insn_opcode
= mo
->match
;
1685 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1686 insn
->fixp
[i
] = NULL
;
1687 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1688 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1689 insn
->mips16_absolute_jump_p
= 0;
1690 insn
->complete_p
= 0;
1691 insn
->cleared_p
= 0;
1694 /* Record the current MIPS16/microMIPS mode in now_seg. */
1697 mips_record_compressed_mode (void)
1699 segment_info_type
*si
;
1701 si
= seg_info (now_seg
);
1702 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1703 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1704 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
1705 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
1708 /* Read a standard MIPS instruction from BUF. */
1710 static unsigned long
1711 read_insn (char *buf
)
1713 if (target_big_endian
)
1714 return bfd_getb32 ((bfd_byte
*) buf
);
1716 return bfd_getl32 ((bfd_byte
*) buf
);
1719 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1723 write_insn (char *buf
, unsigned int insn
)
1725 md_number_to_chars (buf
, insn
, 4);
1729 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1730 has length LENGTH. */
1732 static unsigned long
1733 read_compressed_insn (char *buf
, unsigned int length
)
1739 for (i
= 0; i
< length
; i
+= 2)
1742 if (target_big_endian
)
1743 insn
|= bfd_getb16 ((char *) buf
);
1745 insn
|= bfd_getl16 ((char *) buf
);
1751 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1752 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1755 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
1759 for (i
= 0; i
< length
; i
+= 2)
1760 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
1761 return buf
+ length
;
1764 /* Install INSN at the location specified by its "frag" and "where" fields. */
1767 install_insn (const struct mips_cl_insn
*insn
)
1769 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1770 if (HAVE_CODE_COMPRESSION
)
1771 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
1773 write_insn (f
, insn
->insn_opcode
);
1774 mips_record_compressed_mode ();
1777 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1778 and install the opcode in the new location. */
1781 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1786 insn
->where
= where
;
1787 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1788 if (insn
->fixp
[i
] != NULL
)
1790 insn
->fixp
[i
]->fx_frag
= frag
;
1791 insn
->fixp
[i
]->fx_where
= where
;
1793 install_insn (insn
);
1796 /* Add INSN to the end of the output. */
1799 add_fixed_insn (struct mips_cl_insn
*insn
)
1801 char *f
= frag_more (insn_length (insn
));
1802 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1805 /* Start a variant frag and move INSN to the start of the variant part,
1806 marking it as fixed. The other arguments are as for frag_var. */
1809 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1810 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1812 frag_grow (max_chars
);
1813 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1815 frag_var (rs_machine_dependent
, max_chars
, var
,
1816 subtype
, symbol
, offset
, NULL
);
1819 /* Insert N copies of INSN into the history buffer, starting at
1820 position FIRST. Neither FIRST nor N need to be clipped. */
1823 insert_into_history (unsigned int first
, unsigned int n
,
1824 const struct mips_cl_insn
*insn
)
1826 if (mips_relax
.sequence
!= 2)
1830 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1832 history
[i
] = history
[i
- n
];
1838 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1839 the idea is to make it obvious at a glance that each errata is
1843 init_vr4120_conflicts (void)
1845 #define CONFLICT(FIRST, SECOND) \
1846 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1848 /* Errata 21 - [D]DIV[U] after [D]MACC */
1849 CONFLICT (MACC
, DIV
);
1850 CONFLICT (DMACC
, DIV
);
1852 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1853 CONFLICT (DMULT
, DMULT
);
1854 CONFLICT (DMULT
, DMACC
);
1855 CONFLICT (DMACC
, DMULT
);
1856 CONFLICT (DMACC
, DMACC
);
1858 /* Errata 24 - MT{LO,HI} after [D]MACC */
1859 CONFLICT (MACC
, MTHILO
);
1860 CONFLICT (DMACC
, MTHILO
);
1862 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1863 instruction is executed immediately after a MACC or DMACC
1864 instruction, the result of [either instruction] is incorrect." */
1865 CONFLICT (MACC
, MULT
);
1866 CONFLICT (MACC
, DMULT
);
1867 CONFLICT (DMACC
, MULT
);
1868 CONFLICT (DMACC
, DMULT
);
1870 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1871 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1872 DDIV or DDIVU instruction, the result of the MACC or
1873 DMACC instruction is incorrect.". */
1874 CONFLICT (DMULT
, MACC
);
1875 CONFLICT (DMULT
, DMACC
);
1876 CONFLICT (DIV
, MACC
);
1877 CONFLICT (DIV
, DMACC
);
1887 #define RTYPE_MASK 0x1ff00
1888 #define RTYPE_NUM 0x00100
1889 #define RTYPE_FPU 0x00200
1890 #define RTYPE_FCC 0x00400
1891 #define RTYPE_VEC 0x00800
1892 #define RTYPE_GP 0x01000
1893 #define RTYPE_CP0 0x02000
1894 #define RTYPE_PC 0x04000
1895 #define RTYPE_ACC 0x08000
1896 #define RTYPE_CCC 0x10000
1897 #define RNUM_MASK 0x000ff
1898 #define RWARN 0x80000
1900 #define GENERIC_REGISTER_NUMBERS \
1901 {"$0", RTYPE_NUM | 0}, \
1902 {"$1", RTYPE_NUM | 1}, \
1903 {"$2", RTYPE_NUM | 2}, \
1904 {"$3", RTYPE_NUM | 3}, \
1905 {"$4", RTYPE_NUM | 4}, \
1906 {"$5", RTYPE_NUM | 5}, \
1907 {"$6", RTYPE_NUM | 6}, \
1908 {"$7", RTYPE_NUM | 7}, \
1909 {"$8", RTYPE_NUM | 8}, \
1910 {"$9", RTYPE_NUM | 9}, \
1911 {"$10", RTYPE_NUM | 10}, \
1912 {"$11", RTYPE_NUM | 11}, \
1913 {"$12", RTYPE_NUM | 12}, \
1914 {"$13", RTYPE_NUM | 13}, \
1915 {"$14", RTYPE_NUM | 14}, \
1916 {"$15", RTYPE_NUM | 15}, \
1917 {"$16", RTYPE_NUM | 16}, \
1918 {"$17", RTYPE_NUM | 17}, \
1919 {"$18", RTYPE_NUM | 18}, \
1920 {"$19", RTYPE_NUM | 19}, \
1921 {"$20", RTYPE_NUM | 20}, \
1922 {"$21", RTYPE_NUM | 21}, \
1923 {"$22", RTYPE_NUM | 22}, \
1924 {"$23", RTYPE_NUM | 23}, \
1925 {"$24", RTYPE_NUM | 24}, \
1926 {"$25", RTYPE_NUM | 25}, \
1927 {"$26", RTYPE_NUM | 26}, \
1928 {"$27", RTYPE_NUM | 27}, \
1929 {"$28", RTYPE_NUM | 28}, \
1930 {"$29", RTYPE_NUM | 29}, \
1931 {"$30", RTYPE_NUM | 30}, \
1932 {"$31", RTYPE_NUM | 31}
1934 #define FPU_REGISTER_NAMES \
1935 {"$f0", RTYPE_FPU | 0}, \
1936 {"$f1", RTYPE_FPU | 1}, \
1937 {"$f2", RTYPE_FPU | 2}, \
1938 {"$f3", RTYPE_FPU | 3}, \
1939 {"$f4", RTYPE_FPU | 4}, \
1940 {"$f5", RTYPE_FPU | 5}, \
1941 {"$f6", RTYPE_FPU | 6}, \
1942 {"$f7", RTYPE_FPU | 7}, \
1943 {"$f8", RTYPE_FPU | 8}, \
1944 {"$f9", RTYPE_FPU | 9}, \
1945 {"$f10", RTYPE_FPU | 10}, \
1946 {"$f11", RTYPE_FPU | 11}, \
1947 {"$f12", RTYPE_FPU | 12}, \
1948 {"$f13", RTYPE_FPU | 13}, \
1949 {"$f14", RTYPE_FPU | 14}, \
1950 {"$f15", RTYPE_FPU | 15}, \
1951 {"$f16", RTYPE_FPU | 16}, \
1952 {"$f17", RTYPE_FPU | 17}, \
1953 {"$f18", RTYPE_FPU | 18}, \
1954 {"$f19", RTYPE_FPU | 19}, \
1955 {"$f20", RTYPE_FPU | 20}, \
1956 {"$f21", RTYPE_FPU | 21}, \
1957 {"$f22", RTYPE_FPU | 22}, \
1958 {"$f23", RTYPE_FPU | 23}, \
1959 {"$f24", RTYPE_FPU | 24}, \
1960 {"$f25", RTYPE_FPU | 25}, \
1961 {"$f26", RTYPE_FPU | 26}, \
1962 {"$f27", RTYPE_FPU | 27}, \
1963 {"$f28", RTYPE_FPU | 28}, \
1964 {"$f29", RTYPE_FPU | 29}, \
1965 {"$f30", RTYPE_FPU | 30}, \
1966 {"$f31", RTYPE_FPU | 31}
1968 #define FPU_CONDITION_CODE_NAMES \
1969 {"$fcc0", RTYPE_FCC | 0}, \
1970 {"$fcc1", RTYPE_FCC | 1}, \
1971 {"$fcc2", RTYPE_FCC | 2}, \
1972 {"$fcc3", RTYPE_FCC | 3}, \
1973 {"$fcc4", RTYPE_FCC | 4}, \
1974 {"$fcc5", RTYPE_FCC | 5}, \
1975 {"$fcc6", RTYPE_FCC | 6}, \
1976 {"$fcc7", RTYPE_FCC | 7}
1978 #define COPROC_CONDITION_CODE_NAMES \
1979 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1980 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1981 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1982 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1983 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1984 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1985 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1986 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1988 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1989 {"$a4", RTYPE_GP | 8}, \
1990 {"$a5", RTYPE_GP | 9}, \
1991 {"$a6", RTYPE_GP | 10}, \
1992 {"$a7", RTYPE_GP | 11}, \
1993 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1994 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1995 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1996 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1997 {"$t0", RTYPE_GP | 12}, \
1998 {"$t1", RTYPE_GP | 13}, \
1999 {"$t2", RTYPE_GP | 14}, \
2000 {"$t3", RTYPE_GP | 15}
2002 #define O32_SYMBOLIC_REGISTER_NAMES \
2003 {"$t0", RTYPE_GP | 8}, \
2004 {"$t1", RTYPE_GP | 9}, \
2005 {"$t2", RTYPE_GP | 10}, \
2006 {"$t3", RTYPE_GP | 11}, \
2007 {"$t4", RTYPE_GP | 12}, \
2008 {"$t5", RTYPE_GP | 13}, \
2009 {"$t6", RTYPE_GP | 14}, \
2010 {"$t7", RTYPE_GP | 15}, \
2011 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2012 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2013 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2014 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2016 /* Remaining symbolic register names */
2017 #define SYMBOLIC_REGISTER_NAMES \
2018 {"$zero", RTYPE_GP | 0}, \
2019 {"$at", RTYPE_GP | 1}, \
2020 {"$AT", RTYPE_GP | 1}, \
2021 {"$v0", RTYPE_GP | 2}, \
2022 {"$v1", RTYPE_GP | 3}, \
2023 {"$a0", RTYPE_GP | 4}, \
2024 {"$a1", RTYPE_GP | 5}, \
2025 {"$a2", RTYPE_GP | 6}, \
2026 {"$a3", RTYPE_GP | 7}, \
2027 {"$s0", RTYPE_GP | 16}, \
2028 {"$s1", RTYPE_GP | 17}, \
2029 {"$s2", RTYPE_GP | 18}, \
2030 {"$s3", RTYPE_GP | 19}, \
2031 {"$s4", RTYPE_GP | 20}, \
2032 {"$s5", RTYPE_GP | 21}, \
2033 {"$s6", RTYPE_GP | 22}, \
2034 {"$s7", RTYPE_GP | 23}, \
2035 {"$t8", RTYPE_GP | 24}, \
2036 {"$t9", RTYPE_GP | 25}, \
2037 {"$k0", RTYPE_GP | 26}, \
2038 {"$kt0", RTYPE_GP | 26}, \
2039 {"$k1", RTYPE_GP | 27}, \
2040 {"$kt1", RTYPE_GP | 27}, \
2041 {"$gp", RTYPE_GP | 28}, \
2042 {"$sp", RTYPE_GP | 29}, \
2043 {"$s8", RTYPE_GP | 30}, \
2044 {"$fp", RTYPE_GP | 30}, \
2045 {"$ra", RTYPE_GP | 31}
2047 #define MIPS16_SPECIAL_REGISTER_NAMES \
2048 {"$pc", RTYPE_PC | 0}
2050 #define MDMX_VECTOR_REGISTER_NAMES \
2051 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2052 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2053 {"$v2", RTYPE_VEC | 2}, \
2054 {"$v3", RTYPE_VEC | 3}, \
2055 {"$v4", RTYPE_VEC | 4}, \
2056 {"$v5", RTYPE_VEC | 5}, \
2057 {"$v6", RTYPE_VEC | 6}, \
2058 {"$v7", RTYPE_VEC | 7}, \
2059 {"$v8", RTYPE_VEC | 8}, \
2060 {"$v9", RTYPE_VEC | 9}, \
2061 {"$v10", RTYPE_VEC | 10}, \
2062 {"$v11", RTYPE_VEC | 11}, \
2063 {"$v12", RTYPE_VEC | 12}, \
2064 {"$v13", RTYPE_VEC | 13}, \
2065 {"$v14", RTYPE_VEC | 14}, \
2066 {"$v15", RTYPE_VEC | 15}, \
2067 {"$v16", RTYPE_VEC | 16}, \
2068 {"$v17", RTYPE_VEC | 17}, \
2069 {"$v18", RTYPE_VEC | 18}, \
2070 {"$v19", RTYPE_VEC | 19}, \
2071 {"$v20", RTYPE_VEC | 20}, \
2072 {"$v21", RTYPE_VEC | 21}, \
2073 {"$v22", RTYPE_VEC | 22}, \
2074 {"$v23", RTYPE_VEC | 23}, \
2075 {"$v24", RTYPE_VEC | 24}, \
2076 {"$v25", RTYPE_VEC | 25}, \
2077 {"$v26", RTYPE_VEC | 26}, \
2078 {"$v27", RTYPE_VEC | 27}, \
2079 {"$v28", RTYPE_VEC | 28}, \
2080 {"$v29", RTYPE_VEC | 29}, \
2081 {"$v30", RTYPE_VEC | 30}, \
2082 {"$v31", RTYPE_VEC | 31}
2084 #define MIPS_DSP_ACCUMULATOR_NAMES \
2085 {"$ac0", RTYPE_ACC | 0}, \
2086 {"$ac1", RTYPE_ACC | 1}, \
2087 {"$ac2", RTYPE_ACC | 2}, \
2088 {"$ac3", RTYPE_ACC | 3}
2090 static const struct regname reg_names
[] = {
2091 GENERIC_REGISTER_NUMBERS
,
2093 FPU_CONDITION_CODE_NAMES
,
2094 COPROC_CONDITION_CODE_NAMES
,
2096 /* The $txx registers depends on the abi,
2097 these will be added later into the symbol table from
2098 one of the tables below once mips_abi is set after
2099 parsing of arguments from the command line. */
2100 SYMBOLIC_REGISTER_NAMES
,
2102 MIPS16_SPECIAL_REGISTER_NAMES
,
2103 MDMX_VECTOR_REGISTER_NAMES
,
2104 MIPS_DSP_ACCUMULATOR_NAMES
,
2108 static const struct regname reg_names_o32
[] = {
2109 O32_SYMBOLIC_REGISTER_NAMES
,
2113 static const struct regname reg_names_n32n64
[] = {
2114 N32N64_SYMBOLIC_REGISTER_NAMES
,
2118 /* Check if S points at a valid register specifier according to TYPES.
2119 If so, then return 1, advance S to consume the specifier and store
2120 the register's number in REGNOP, otherwise return 0. */
2123 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2130 /* Find end of name. */
2132 if (is_name_beginner (*e
))
2134 while (is_part_of_name (*e
))
2137 /* Terminate name. */
2141 /* Look for a register symbol. */
2142 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2144 int r
= S_GET_VALUE (symbolP
);
2146 reg
= r
& RNUM_MASK
;
2147 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2148 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2149 reg
= (r
& RNUM_MASK
) - 2;
2151 /* Else see if this is a register defined in an itbl entry. */
2152 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2159 if (itbl_get_reg_val (n
, &r
))
2160 reg
= r
& RNUM_MASK
;
2163 /* Advance to next token if a register was recognised. */
2166 else if (types
& RWARN
)
2167 as_warn (_("Unrecognized register name `%s'"), *s
);
2175 /* Check if S points at a valid register list according to TYPES.
2176 If so, then return 1, advance S to consume the list and store
2177 the registers present on the list as a bitmask of ones in REGLISTP,
2178 otherwise return 0. A valid list comprises a comma-separated
2179 enumeration of valid single registers and/or dash-separated
2180 contiguous register ranges as determined by their numbers.
2182 As a special exception if one of s0-s7 registers is specified as
2183 the range's lower delimiter and s8 (fp) is its upper one, then no
2184 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2185 are selected; they have to be listed separately if needed. */
2188 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2190 unsigned int reglist
= 0;
2191 unsigned int lastregno
;
2192 bfd_boolean ok
= TRUE
;
2193 unsigned int regmask
;
2194 char *s_endlist
= *s
;
2198 while (reg_lookup (s
, types
, ®no
))
2204 ok
= reg_lookup (s
, types
, &lastregno
);
2205 if (ok
&& lastregno
< regno
)
2211 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2216 regmask
= 1 << lastregno
;
2217 regmask
= (regmask
<< 1) - 1;
2218 regmask
^= (1 << regno
) - 1;
2232 *reglistp
= reglist
;
2233 return ok
&& reglist
!= 0;
2236 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2237 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2240 is_opcode_valid (const struct mips_opcode
*mo
)
2242 int isa
= mips_opts
.isa
;
2245 if (mips_opts
.ase_mdmx
)
2247 if (mips_opts
.ase_dsp
)
2249 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
2251 if (mips_opts
.ase_dspr2
)
2253 if (mips_opts
.ase_mt
)
2255 if (mips_opts
.ase_mips3d
)
2257 if (mips_opts
.ase_smartmips
)
2258 isa
|= INSN_SMARTMIPS
;
2259 if (mips_opts
.ase_mcu
)
2262 if (!opcode_is_member (mo
, isa
, mips_opts
.arch
))
2265 /* Check whether the instruction or macro requires single-precision or
2266 double-precision floating-point support. Note that this information is
2267 stored differently in the opcode table for insns and macros. */
2268 if (mo
->pinfo
== INSN_MACRO
)
2270 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2271 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2275 fp_s
= mo
->pinfo
& FP_S
;
2276 fp_d
= mo
->pinfo
& FP_D
;
2279 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2282 if (fp_s
&& mips_opts
.soft_float
)
2288 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2289 selected ISA and architecture. */
2292 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2294 return opcode_is_member (mo
, mips_opts
.isa
, mips_opts
.arch
);
2297 /* Return TRUE if the size of the microMIPS opcode MO matches one
2298 explicitly requested. Always TRUE in the standard MIPS mode. */
2301 is_size_valid (const struct mips_opcode
*mo
)
2303 if (!mips_opts
.micromips
)
2306 if (!forced_insn_length
)
2308 if (mo
->pinfo
== INSN_MACRO
)
2310 return forced_insn_length
== micromips_insn_length (mo
);
2313 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2314 of the preceding instruction. Always TRUE in the standard MIPS mode.
2316 We don't accept macros in 16-bit delay slots to avoid a case where
2317 a macro expansion fails because it relies on a preceding 32-bit real
2318 instruction to have matched and does not handle the operands correctly.
2319 The only macros that may expand to 16-bit instructions are JAL that
2320 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2321 and BGT (that likewise cannot be placed in a delay slot) that decay to
2322 a NOP. In all these cases the macros precede any corresponding real
2323 instruction definitions in the opcode table, so they will match in the
2324 second pass where the size of the delay slot is ignored and therefore
2325 produce correct code. */
2328 is_delay_slot_valid (const struct mips_opcode
*mo
)
2330 if (!mips_opts
.micromips
)
2333 if (mo
->pinfo
== INSN_MACRO
)
2334 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2335 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2336 && micromips_insn_length (mo
) != 4)
2338 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2339 && micromips_insn_length (mo
) != 2)
2345 /* This function is called once, at assembler startup time. It should set up
2346 all the tables, etc. that the MD part of the assembler will need. */
2351 const char *retval
= NULL
;
2355 if (mips_pic
!= NO_PIC
)
2357 if (g_switch_seen
&& g_switch_value
!= 0)
2358 as_bad (_("-G may not be used in position-independent code"));
2362 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2363 as_warn (_("Could not set architecture and machine"));
2365 op_hash
= hash_new ();
2367 for (i
= 0; i
< NUMOPCODES
;)
2369 const char *name
= mips_opcodes
[i
].name
;
2371 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2374 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2375 mips_opcodes
[i
].name
, retval
);
2376 /* Probably a memory allocation problem? Give up now. */
2377 as_fatal (_("Broken assembler. No assembly attempted."));
2381 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2383 if (!validate_mips_insn (&mips_opcodes
[i
]))
2385 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2387 create_insn (&nop_insn
, mips_opcodes
+ i
);
2388 if (mips_fix_loongson2f_nop
)
2389 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2390 nop_insn
.fixed_p
= 1;
2395 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2398 mips16_op_hash
= hash_new ();
2401 while (i
< bfd_mips16_num_opcodes
)
2403 const char *name
= mips16_opcodes
[i
].name
;
2405 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2407 as_fatal (_("internal: can't hash `%s': %s"),
2408 mips16_opcodes
[i
].name
, retval
);
2411 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2412 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2413 != mips16_opcodes
[i
].match
))
2415 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2416 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2419 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2421 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2422 mips16_nop_insn
.fixed_p
= 1;
2426 while (i
< bfd_mips16_num_opcodes
2427 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2430 micromips_op_hash
= hash_new ();
2433 while (i
< bfd_micromips_num_opcodes
)
2435 const char *name
= micromips_opcodes
[i
].name
;
2437 retval
= hash_insert (micromips_op_hash
, name
,
2438 (void *) µmips_opcodes
[i
]);
2440 as_fatal (_("internal: can't hash `%s': %s"),
2441 micromips_opcodes
[i
].name
, retval
);
2443 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2445 struct mips_cl_insn
*micromips_nop_insn
;
2447 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2450 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2451 micromips_nop_insn
= µmips_nop16_insn
;
2452 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2453 micromips_nop_insn
= µmips_nop32_insn
;
2457 if (micromips_nop_insn
->insn_mo
== NULL
2458 && strcmp (name
, "nop") == 0)
2460 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2461 micromips_nop_insn
->fixed_p
= 1;
2464 while (++i
< bfd_micromips_num_opcodes
2465 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2469 as_fatal (_("Broken assembler. No assembly attempted."));
2471 /* We add all the general register names to the symbol table. This
2472 helps us detect invalid uses of them. */
2473 for (i
= 0; reg_names
[i
].name
; i
++)
2474 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2475 reg_names
[i
].num
, /* & RNUM_MASK, */
2476 &zero_address_frag
));
2478 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2479 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2480 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2481 &zero_address_frag
));
2483 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2484 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2485 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2486 &zero_address_frag
));
2488 mips_no_prev_insn ();
2491 mips_cprmask
[0] = 0;
2492 mips_cprmask
[1] = 0;
2493 mips_cprmask
[2] = 0;
2494 mips_cprmask
[3] = 0;
2496 /* set the default alignment for the text section (2**2) */
2497 record_alignment (text_section
, 2);
2499 bfd_set_gp_size (stdoutput
, g_switch_value
);
2504 /* On a native system other than VxWorks, sections must be aligned
2505 to 16 byte boundaries. When configured for an embedded ELF
2506 target, we don't bother. */
2507 if (strncmp (TARGET_OS
, "elf", 3) != 0
2508 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2510 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2511 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2512 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2515 /* Create a .reginfo section for register masks and a .mdebug
2516 section for debugging information. */
2524 subseg
= now_subseg
;
2526 /* The ABI says this section should be loaded so that the
2527 running program can access it. However, we don't load it
2528 if we are configured for an embedded target */
2529 flags
= SEC_READONLY
| SEC_DATA
;
2530 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2531 flags
|= SEC_ALLOC
| SEC_LOAD
;
2533 if (mips_abi
!= N64_ABI
)
2535 sec
= subseg_new (".reginfo", (subsegT
) 0);
2537 bfd_set_section_flags (stdoutput
, sec
, flags
);
2538 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2540 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2544 /* The 64-bit ABI uses a .MIPS.options section rather than
2545 .reginfo section. */
2546 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2547 bfd_set_section_flags (stdoutput
, sec
, flags
);
2548 bfd_set_section_alignment (stdoutput
, sec
, 3);
2550 /* Set up the option header. */
2552 Elf_Internal_Options opthdr
;
2555 opthdr
.kind
= ODK_REGINFO
;
2556 opthdr
.size
= (sizeof (Elf_External_Options
)
2557 + sizeof (Elf64_External_RegInfo
));
2560 f
= frag_more (sizeof (Elf_External_Options
));
2561 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2562 (Elf_External_Options
*) f
);
2564 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2568 if (ECOFF_DEBUGGING
)
2570 sec
= subseg_new (".mdebug", (subsegT
) 0);
2571 (void) bfd_set_section_flags (stdoutput
, sec
,
2572 SEC_HAS_CONTENTS
| SEC_READONLY
);
2573 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2575 else if (mips_flag_pdr
)
2577 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2578 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2579 SEC_READONLY
| SEC_RELOC
2581 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2584 subseg_set (seg
, subseg
);
2587 #endif /* OBJ_ELF */
2589 if (! ECOFF_DEBUGGING
)
2592 if (mips_fix_vr4120
)
2593 init_vr4120_conflicts ();
2599 mips_emit_delays ();
2600 if (! ECOFF_DEBUGGING
)
2605 md_assemble (char *str
)
2607 struct mips_cl_insn insn
;
2608 bfd_reloc_code_real_type unused_reloc
[3]
2609 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2611 imm_expr
.X_op
= O_absent
;
2612 imm2_expr
.X_op
= O_absent
;
2613 offset_expr
.X_op
= O_absent
;
2614 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2615 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2616 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2617 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2618 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2619 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2621 mips_mark_labels ();
2622 mips_assembling_insn
= TRUE
;
2624 if (mips_opts
.mips16
)
2625 mips16_ip (str
, &insn
);
2628 mips_ip (str
, &insn
);
2629 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2630 str
, insn
.insn_opcode
));
2634 as_bad ("%s `%s'", insn_error
, str
);
2635 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2638 if (mips_opts
.mips16
)
2639 mips16_macro (&insn
);
2646 if (imm_expr
.X_op
!= O_absent
)
2647 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2648 else if (offset_expr
.X_op
!= O_absent
)
2649 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2651 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2654 mips_assembling_insn
= FALSE
;
2657 /* Convenience functions for abstracting away the differences between
2658 MIPS16 and non-MIPS16 relocations. */
2660 static inline bfd_boolean
2661 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2665 case BFD_RELOC_MIPS16_JMP
:
2666 case BFD_RELOC_MIPS16_GPREL
:
2667 case BFD_RELOC_MIPS16_GOT16
:
2668 case BFD_RELOC_MIPS16_CALL16
:
2669 case BFD_RELOC_MIPS16_HI16_S
:
2670 case BFD_RELOC_MIPS16_HI16
:
2671 case BFD_RELOC_MIPS16_LO16
:
2679 static inline bfd_boolean
2680 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
2684 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2685 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2686 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2687 case BFD_RELOC_MICROMIPS_GPREL16
:
2688 case BFD_RELOC_MICROMIPS_JMP
:
2689 case BFD_RELOC_MICROMIPS_HI16
:
2690 case BFD_RELOC_MICROMIPS_HI16_S
:
2691 case BFD_RELOC_MICROMIPS_LO16
:
2692 case BFD_RELOC_MICROMIPS_LITERAL
:
2693 case BFD_RELOC_MICROMIPS_GOT16
:
2694 case BFD_RELOC_MICROMIPS_CALL16
:
2695 case BFD_RELOC_MICROMIPS_GOT_HI16
:
2696 case BFD_RELOC_MICROMIPS_GOT_LO16
:
2697 case BFD_RELOC_MICROMIPS_CALL_HI16
:
2698 case BFD_RELOC_MICROMIPS_CALL_LO16
:
2699 case BFD_RELOC_MICROMIPS_SUB
:
2700 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
2701 case BFD_RELOC_MICROMIPS_GOT_OFST
:
2702 case BFD_RELOC_MICROMIPS_GOT_DISP
:
2703 case BFD_RELOC_MICROMIPS_HIGHEST
:
2704 case BFD_RELOC_MICROMIPS_HIGHER
:
2705 case BFD_RELOC_MICROMIPS_SCN_DISP
:
2706 case BFD_RELOC_MICROMIPS_JALR
:
2714 static inline bfd_boolean
2715 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
2717 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
2720 static inline bfd_boolean
2721 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2723 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
2724 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
2727 static inline bfd_boolean
2728 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2730 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
2731 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
2734 static inline bfd_boolean
2735 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2737 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
2738 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
2741 static inline bfd_boolean
2742 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
2744 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
2747 /* Return true if RELOC is a PC-relative relocation that does not have
2748 full address range. */
2750 static inline bfd_boolean
2751 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
2755 case BFD_RELOC_16_PCREL_S2
:
2756 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
2757 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
2758 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
2765 /* Return true if the given relocation might need a matching %lo().
2766 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2767 need a matching %lo() when applied to local symbols. */
2769 static inline bfd_boolean
2770 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2772 return (HAVE_IN_PLACE_ADDENDS
2773 && (hi16_reloc_p (reloc
)
2774 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2775 all GOT16 relocations evaluate to "G". */
2776 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2779 /* Return the type of %lo() reloc needed by RELOC, given that
2780 reloc_needs_lo_p. */
2782 static inline bfd_reloc_code_real_type
2783 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2785 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
2786 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
2790 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2793 static inline bfd_boolean
2794 fixup_has_matching_lo_p (fixS
*fixp
)
2796 return (fixp
->fx_next
!= NULL
2797 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2798 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2799 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2802 /* This function returns true if modifying a register requires a
2806 reg_needs_delay (unsigned int reg
)
2808 unsigned long prev_pinfo
;
2810 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2811 if (! mips_opts
.noreorder
2812 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2813 && ! gpr_interlocks
)
2814 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2815 && ! cop_interlocks
)))
2817 /* A load from a coprocessor or from memory. All load delays
2818 delay the use of general register rt for one instruction. */
2819 /* Itbl support may require additional care here. */
2820 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2821 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
2828 /* Move all labels in LABELS to the current insertion point. TEXT_P
2829 says whether the labels refer to text or data. */
2832 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
2834 struct insn_label_list
*l
;
2837 for (l
= labels
; l
!= NULL
; l
= l
->next
)
2839 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2840 symbol_set_frag (l
->label
, frag_now
);
2841 val
= (valueT
) frag_now_fix ();
2842 /* MIPS16/microMIPS text labels are stored as odd. */
2843 if (text_p
&& HAVE_CODE_COMPRESSION
)
2845 S_SET_VALUE (l
->label
, val
);
2849 /* Move all labels in insn_labels to the current insertion point
2850 and treat them as text labels. */
2853 mips_move_text_labels (void)
2855 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
2859 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2861 bfd_boolean linkonce
= FALSE
;
2862 segT symseg
= S_GET_SEGMENT (sym
);
2864 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2866 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2869 /* The GNU toolchain uses an extension for ELF: a section
2870 beginning with the magic string .gnu.linkonce is a
2871 linkonce section. */
2872 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2873 sizeof ".gnu.linkonce" - 1) == 0)
2880 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2881 linker to handle them specially, such as generating jalx instructions
2882 when needed. We also make them odd for the duration of the assembly,
2883 in order to generate the right sort of code. We will make them even
2884 in the adjust_symtab routine, while leaving them marked. This is
2885 convenient for the debugger and the disassembler. The linker knows
2886 to make them odd again. */
2889 mips_compressed_mark_label (symbolS
*label
)
2891 gas_assert (HAVE_CODE_COMPRESSION
);
2893 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2896 if (mips_opts
.mips16
)
2897 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2899 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
2902 if ((S_GET_VALUE (label
) & 1) == 0
2903 /* Don't adjust the address if the label is global or weak, or
2904 in a link-once section, since we'll be emitting symbol reloc
2905 references to it which will be patched up by the linker, and
2906 the final value of the symbol may or may not be MIPS16/microMIPS. */
2907 && !S_IS_WEAK (label
)
2908 && !S_IS_EXTERNAL (label
)
2909 && !s_is_linkonce (label
, now_seg
))
2910 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2913 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2916 mips_compressed_mark_labels (void)
2918 struct insn_label_list
*l
;
2920 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
2921 mips_compressed_mark_label (l
->label
);
2924 /* End the current frag. Make it a variant frag and record the
2928 relax_close_frag (void)
2930 mips_macro_warning
.first_frag
= frag_now
;
2931 frag_var (rs_machine_dependent
, 0, 0,
2932 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2933 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2935 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2936 mips_relax
.first_fixup
= 0;
2939 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2940 See the comment above RELAX_ENCODE for more details. */
2943 relax_start (symbolS
*symbol
)
2945 gas_assert (mips_relax
.sequence
== 0);
2946 mips_relax
.sequence
= 1;
2947 mips_relax
.symbol
= symbol
;
2950 /* Start generating the second version of a relaxable sequence.
2951 See the comment above RELAX_ENCODE for more details. */
2956 gas_assert (mips_relax
.sequence
== 1);
2957 mips_relax
.sequence
= 2;
2960 /* End the current relaxable sequence. */
2965 gas_assert (mips_relax
.sequence
== 2);
2966 relax_close_frag ();
2967 mips_relax
.sequence
= 0;
2970 /* Return true if IP is a delayed branch or jump. */
2972 static inline bfd_boolean
2973 delayed_branch_p (const struct mips_cl_insn
*ip
)
2975 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2976 | INSN_COND_BRANCH_DELAY
2977 | INSN_COND_BRANCH_LIKELY
)) != 0;
2980 /* Return true if IP is a compact branch or jump. */
2982 static inline bfd_boolean
2983 compact_branch_p (const struct mips_cl_insn
*ip
)
2985 if (mips_opts
.mips16
)
2986 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2987 | MIPS16_INSN_COND_BRANCH
)) != 0;
2989 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
2990 | INSN2_COND_BRANCH
)) != 0;
2993 /* Return true if IP is an unconditional branch or jump. */
2995 static inline bfd_boolean
2996 uncond_branch_p (const struct mips_cl_insn
*ip
)
2998 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
2999 || (mips_opts
.mips16
3000 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3001 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3004 /* Return true if IP is a branch-likely instruction. */
3006 static inline bfd_boolean
3007 branch_likely_p (const struct mips_cl_insn
*ip
)
3009 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3012 /* Return the type of nop that should be used to fill the delay slot
3013 of delayed branch IP. */
3015 static struct mips_cl_insn
*
3016 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3018 if (mips_opts
.micromips
3019 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3020 return µmips_nop32_insn
;
3024 /* Return the mask of core registers that IP reads or writes. */
3027 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3029 unsigned long pinfo2
;
3033 pinfo2
= ip
->insn_mo
->pinfo2
;
3034 if (mips_opts
.micromips
)
3036 if (pinfo2
& INSN2_MOD_GPR_MD
)
3037 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3038 if (pinfo2
& INSN2_MOD_GPR_MF
)
3039 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3040 if (pinfo2
& INSN2_MOD_SP
)
3046 /* Return the mask of core registers that IP reads. */
3049 gpr_read_mask (const struct mips_cl_insn
*ip
)
3051 unsigned long pinfo
, pinfo2
;
3054 mask
= gpr_mod_mask (ip
);
3055 pinfo
= ip
->insn_mo
->pinfo
;
3056 pinfo2
= ip
->insn_mo
->pinfo2
;
3057 if (mips_opts
.mips16
)
3059 if (pinfo
& MIPS16_INSN_READ_X
)
3060 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3061 if (pinfo
& MIPS16_INSN_READ_Y
)
3062 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3063 if (pinfo
& MIPS16_INSN_READ_T
)
3065 if (pinfo
& MIPS16_INSN_READ_SP
)
3067 if (pinfo
& MIPS16_INSN_READ_31
)
3069 if (pinfo
& MIPS16_INSN_READ_Z
)
3070 mask
|= 1 << (mips16_to_32_reg_map
3071 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3072 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3073 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3077 if (pinfo2
& INSN2_READ_GPR_D
)
3078 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3079 if (pinfo
& INSN_READ_GPR_T
)
3080 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3081 if (pinfo
& INSN_READ_GPR_S
)
3082 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3083 if (pinfo2
& INSN2_READ_GP
)
3085 if (pinfo2
& INSN2_READ_GPR_31
)
3087 if (pinfo2
& INSN2_READ_GPR_Z
)
3088 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3090 if (mips_opts
.micromips
)
3092 if (pinfo2
& INSN2_READ_GPR_MC
)
3093 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3094 if (pinfo2
& INSN2_READ_GPR_ME
)
3095 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3096 if (pinfo2
& INSN2_READ_GPR_MG
)
3097 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3098 if (pinfo2
& INSN2_READ_GPR_MJ
)
3099 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3100 if (pinfo2
& INSN2_READ_GPR_MMN
)
3102 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3103 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3105 if (pinfo2
& INSN2_READ_GPR_MP
)
3106 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3107 if (pinfo2
& INSN2_READ_GPR_MQ
)
3108 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3110 /* Don't include register 0. */
3114 /* Return the mask of core registers that IP writes. */
3117 gpr_write_mask (const struct mips_cl_insn
*ip
)
3119 unsigned long pinfo
, pinfo2
;
3122 mask
= gpr_mod_mask (ip
);
3123 pinfo
= ip
->insn_mo
->pinfo
;
3124 pinfo2
= ip
->insn_mo
->pinfo2
;
3125 if (mips_opts
.mips16
)
3127 if (pinfo
& MIPS16_INSN_WRITE_X
)
3128 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3129 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3130 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3131 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3132 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3133 if (pinfo
& MIPS16_INSN_WRITE_T
)
3135 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3137 if (pinfo
& MIPS16_INSN_WRITE_31
)
3139 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3140 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3144 if (pinfo
& INSN_WRITE_GPR_D
)
3145 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3146 if (pinfo
& INSN_WRITE_GPR_T
)
3147 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3148 if (pinfo
& INSN_WRITE_GPR_S
)
3149 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3150 if (pinfo
& INSN_WRITE_GPR_31
)
3152 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3153 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3155 if (mips_opts
.micromips
)
3157 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3158 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3159 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3161 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3162 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3164 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3165 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3166 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3167 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3169 /* Don't include register 0. */
3173 /* Return the mask of floating-point registers that IP reads. */
3176 fpr_read_mask (const struct mips_cl_insn
*ip
)
3178 unsigned long pinfo
, pinfo2
;
3182 pinfo
= ip
->insn_mo
->pinfo
;
3183 pinfo2
= ip
->insn_mo
->pinfo2
;
3184 if (!mips_opts
.mips16
)
3186 if (pinfo2
& INSN2_READ_FPR_D
)
3187 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3188 if (pinfo
& INSN_READ_FPR_S
)
3189 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3190 if (pinfo
& INSN_READ_FPR_T
)
3191 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3192 if (pinfo
& INSN_READ_FPR_R
)
3193 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3194 if (pinfo2
& INSN2_READ_FPR_Z
)
3195 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3197 /* Conservatively treat all operands to an FP_D instruction are doubles.
3198 (This is overly pessimistic for things like cvt.d.s.) */
3199 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3204 /* Return the mask of floating-point registers that IP writes. */
3207 fpr_write_mask (const struct mips_cl_insn
*ip
)
3209 unsigned long pinfo
, pinfo2
;
3213 pinfo
= ip
->insn_mo
->pinfo
;
3214 pinfo2
= ip
->insn_mo
->pinfo2
;
3215 if (!mips_opts
.mips16
)
3217 if (pinfo
& INSN_WRITE_FPR_D
)
3218 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3219 if (pinfo
& INSN_WRITE_FPR_S
)
3220 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3221 if (pinfo
& INSN_WRITE_FPR_T
)
3222 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3223 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3224 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3226 /* Conservatively treat all operands to an FP_D instruction are doubles.
3227 (This is overly pessimistic for things like cvt.s.d.) */
3228 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3233 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3234 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3235 by VR4120 errata. */
3238 classify_vr4120_insn (const char *name
)
3240 if (strncmp (name
, "macc", 4) == 0)
3241 return FIX_VR4120_MACC
;
3242 if (strncmp (name
, "dmacc", 5) == 0)
3243 return FIX_VR4120_DMACC
;
3244 if (strncmp (name
, "mult", 4) == 0)
3245 return FIX_VR4120_MULT
;
3246 if (strncmp (name
, "dmult", 5) == 0)
3247 return FIX_VR4120_DMULT
;
3248 if (strstr (name
, "div"))
3249 return FIX_VR4120_DIV
;
3250 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3251 return FIX_VR4120_MTHILO
;
3252 return NUM_FIX_VR4120_CLASSES
;
3255 #define INSN_ERET 0x42000018
3256 #define INSN_DERET 0x4200001f
3258 /* Return the number of instructions that must separate INSN1 and INSN2,
3259 where INSN1 is the earlier instruction. Return the worst-case value
3260 for any INSN2 if INSN2 is null. */
3263 insns_between (const struct mips_cl_insn
*insn1
,
3264 const struct mips_cl_insn
*insn2
)
3266 unsigned long pinfo1
, pinfo2
;
3269 /* This function needs to know which pinfo flags are set for INSN2
3270 and which registers INSN2 uses. The former is stored in PINFO2 and
3271 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3272 will have every flag set and INSN2_USES_GPR will always return true. */
3273 pinfo1
= insn1
->insn_mo
->pinfo
;
3274 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3276 #define INSN2_USES_GPR(REG) \
3277 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3279 /* For most targets, write-after-read dependencies on the HI and LO
3280 registers must be separated by at least two instructions. */
3281 if (!hilo_interlocks
)
3283 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3285 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3289 /* If we're working around r7000 errata, there must be two instructions
3290 between an mfhi or mflo and any instruction that uses the result. */
3291 if (mips_7000_hilo_fix
3292 && !mips_opts
.micromips
3293 && MF_HILO_INSN (pinfo1
)
3294 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3297 /* If we're working around 24K errata, one instruction is required
3298 if an ERET or DERET is followed by a branch instruction. */
3299 if (mips_fix_24k
&& !mips_opts
.micromips
)
3301 if (insn1
->insn_opcode
== INSN_ERET
3302 || insn1
->insn_opcode
== INSN_DERET
)
3305 || insn2
->insn_opcode
== INSN_ERET
3306 || insn2
->insn_opcode
== INSN_DERET
3307 || delayed_branch_p (insn2
))
3312 /* If working around VR4120 errata, check for combinations that need
3313 a single intervening instruction. */
3314 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3316 unsigned int class1
, class2
;
3318 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3319 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3323 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3324 if (vr4120_conflicts
[class1
] & (1 << class2
))
3329 if (!HAVE_CODE_COMPRESSION
)
3331 /* Check for GPR or coprocessor load delays. All such delays
3332 are on the RT register. */
3333 /* Itbl support may require additional care here. */
3334 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3335 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3337 know (pinfo1
& INSN_WRITE_GPR_T
);
3338 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3342 /* Check for generic coprocessor hazards.
3344 This case is not handled very well. There is no special
3345 knowledge of CP0 handling, and the coprocessors other than
3346 the floating point unit are not distinguished at all. */
3347 /* Itbl support may require additional care here. FIXME!
3348 Need to modify this to include knowledge about
3349 user specified delays! */
3350 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3351 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3353 /* Handle cases where INSN1 writes to a known general coprocessor
3354 register. There must be a one instruction delay before INSN2
3355 if INSN2 reads that register, otherwise no delay is needed. */
3356 mask
= fpr_write_mask (insn1
);
3359 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3364 /* Read-after-write dependencies on the control registers
3365 require a two-instruction gap. */
3366 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3367 && (pinfo2
& INSN_READ_COND_CODE
))
3370 /* We don't know exactly what INSN1 does. If INSN2 is
3371 also a coprocessor instruction, assume there must be
3372 a one instruction gap. */
3373 if (pinfo2
& INSN_COP
)
3378 /* Check for read-after-write dependencies on the coprocessor
3379 control registers in cases where INSN1 does not need a general
3380 coprocessor delay. This means that INSN1 is a floating point
3381 comparison instruction. */
3382 /* Itbl support may require additional care here. */
3383 else if (!cop_interlocks
3384 && (pinfo1
& INSN_WRITE_COND_CODE
)
3385 && (pinfo2
& INSN_READ_COND_CODE
))
3389 #undef INSN2_USES_GPR
3394 /* Return the number of nops that would be needed to work around the
3395 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3396 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3397 that are contained within the first IGNORE instructions of HIST. */
3400 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3401 const struct mips_cl_insn
*insn
)
3406 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3407 are not affected by the errata. */
3409 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3410 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3411 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3414 /* Search for the first MFLO or MFHI. */
3415 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3416 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3418 /* Extract the destination register. */
3419 mask
= gpr_write_mask (&hist
[i
]);
3421 /* No nops are needed if INSN reads that register. */
3422 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3425 /* ...or if any of the intervening instructions do. */
3426 for (j
= 0; j
< i
; j
++)
3427 if (gpr_read_mask (&hist
[j
]) & mask
)
3431 return MAX_VR4130_NOPS
- i
;
3436 #define BASE_REG_EQ(INSN1, INSN2) \
3437 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3438 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3440 /* Return the minimum alignment for this store instruction. */
3443 fix_24k_align_to (const struct mips_opcode
*mo
)
3445 if (strcmp (mo
->name
, "sh") == 0)
3448 if (strcmp (mo
->name
, "swc1") == 0
3449 || strcmp (mo
->name
, "swc2") == 0
3450 || strcmp (mo
->name
, "sw") == 0
3451 || strcmp (mo
->name
, "sc") == 0
3452 || strcmp (mo
->name
, "s.s") == 0)
3455 if (strcmp (mo
->name
, "sdc1") == 0
3456 || strcmp (mo
->name
, "sdc2") == 0
3457 || strcmp (mo
->name
, "s.d") == 0)
3464 struct fix_24k_store_info
3466 /* Immediate offset, if any, for this store instruction. */
3468 /* Alignment required by this store instruction. */
3470 /* True for register offsets. */
3471 int register_offset
;
3474 /* Comparison function used by qsort. */
3477 fix_24k_sort (const void *a
, const void *b
)
3479 const struct fix_24k_store_info
*pos1
= a
;
3480 const struct fix_24k_store_info
*pos2
= b
;
3482 return (pos1
->off
- pos2
->off
);
3485 /* INSN is a store instruction. Try to record the store information
3486 in STINFO. Return false if the information isn't known. */
3489 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3490 const struct mips_cl_insn
*insn
)
3492 /* The instruction must have a known offset. */
3493 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3496 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3497 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3501 /* Return the number of nops that would be needed to work around the 24k
3502 "lost data on stores during refill" errata if instruction INSN
3503 immediately followed the 2 instructions described by HIST.
3504 Ignore hazards that are contained within the first IGNORE
3505 instructions of HIST.
3507 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3508 for the data cache refills and store data. The following describes
3509 the scenario where the store data could be lost.
3511 * A data cache miss, due to either a load or a store, causing fill
3512 data to be supplied by the memory subsystem
3513 * The first three doublewords of fill data are returned and written
3515 * A sequence of four stores occurs in consecutive cycles around the
3516 final doubleword of the fill:
3520 * Zero, One or more instructions
3523 The four stores A-D must be to different doublewords of the line that
3524 is being filled. The fourth instruction in the sequence above permits
3525 the fill of the final doubleword to be transferred from the FSB into
3526 the cache. In the sequence above, the stores may be either integer
3527 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3528 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3529 different doublewords on the line. If the floating point unit is
3530 running in 1:2 mode, it is not possible to create the sequence above
3531 using only floating point store instructions.
3533 In this case, the cache line being filled is incorrectly marked
3534 invalid, thereby losing the data from any store to the line that
3535 occurs between the original miss and the completion of the five
3536 cycle sequence shown above.
3538 The workarounds are:
3540 * Run the data cache in write-through mode.
3541 * Insert a non-store instruction between
3542 Store A and Store B or Store B and Store C. */
3545 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3546 const struct mips_cl_insn
*insn
)
3548 struct fix_24k_store_info pos
[3];
3549 int align
, i
, base_offset
;
3554 /* If the previous instruction wasn't a store, there's nothing to
3556 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3559 /* If the instructions after the previous one are unknown, we have
3560 to assume the worst. */
3564 /* Check whether we are dealing with three consecutive stores. */
3565 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3566 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3569 /* If we don't know the relationship between the store addresses,
3570 assume the worst. */
3571 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3572 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3575 if (!fix_24k_record_store_info (&pos
[0], insn
)
3576 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3577 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3580 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3582 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3583 X bytes and such that the base register + X is known to be aligned
3586 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3590 align
= pos
[0].align_to
;
3591 base_offset
= pos
[0].off
;
3592 for (i
= 1; i
< 3; i
++)
3593 if (align
< pos
[i
].align_to
)
3595 align
= pos
[i
].align_to
;
3596 base_offset
= pos
[i
].off
;
3598 for (i
= 0; i
< 3; i
++)
3599 pos
[i
].off
-= base_offset
;
3602 pos
[0].off
&= ~align
+ 1;
3603 pos
[1].off
&= ~align
+ 1;
3604 pos
[2].off
&= ~align
+ 1;
3606 /* If any two stores write to the same chunk, they also write to the
3607 same doubleword. The offsets are still sorted at this point. */
3608 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3611 /* A range of at least 9 bytes is needed for the stores to be in
3612 non-overlapping doublewords. */
3613 if (pos
[2].off
- pos
[0].off
<= 8)
3616 if (pos
[2].off
- pos
[1].off
>= 24
3617 || pos
[1].off
- pos
[0].off
>= 24
3618 || pos
[2].off
- pos
[0].off
>= 32)
3624 /* Return the number of nops that would be needed if instruction INSN
3625 immediately followed the MAX_NOPS instructions given by HIST,
3626 where HIST[0] is the most recent instruction. Ignore hazards
3627 between INSN and the first IGNORE instructions in HIST.
3629 If INSN is null, return the worse-case number of nops for any
3633 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3634 const struct mips_cl_insn
*insn
)
3636 int i
, nops
, tmp_nops
;
3639 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3641 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3642 if (tmp_nops
> nops
)
3646 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3648 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3649 if (tmp_nops
> nops
)
3653 if (mips_fix_24k
&& !mips_opts
.micromips
)
3655 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3656 if (tmp_nops
> nops
)
3663 /* The variable arguments provide NUM_INSNS extra instructions that
3664 might be added to HIST. Return the largest number of nops that
3665 would be needed after the extended sequence, ignoring hazards
3666 in the first IGNORE instructions. */
3669 nops_for_sequence (int num_insns
, int ignore
,
3670 const struct mips_cl_insn
*hist
, ...)
3673 struct mips_cl_insn buffer
[MAX_NOPS
];
3674 struct mips_cl_insn
*cursor
;
3677 va_start (args
, hist
);
3678 cursor
= buffer
+ num_insns
;
3679 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
3680 while (cursor
> buffer
)
3681 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
3683 nops
= nops_for_insn (ignore
, buffer
, NULL
);
3688 /* Like nops_for_insn, but if INSN is a branch, take into account the
3689 worst-case delay for the branch target. */
3692 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
3693 const struct mips_cl_insn
*insn
)
3697 nops
= nops_for_insn (ignore
, hist
, insn
);
3698 if (delayed_branch_p (insn
))
3700 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
3701 hist
, insn
, get_delay_slot_nop (insn
));
3702 if (tmp_nops
> nops
)
3705 else if (compact_branch_p (insn
))
3707 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
3708 if (tmp_nops
> nops
)
3714 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3717 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
3719 gas_assert (!HAVE_CODE_COMPRESSION
);
3720 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
3721 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
3724 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3725 jr target pc &= 'hffff_ffff_cfff_ffff. */
3728 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
3730 gas_assert (!HAVE_CODE_COMPRESSION
);
3731 if (strcmp (ip
->insn_mo
->name
, "j") == 0
3732 || strcmp (ip
->insn_mo
->name
, "jr") == 0
3733 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
3741 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
3742 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
3745 ep
.X_op
= O_constant
;
3746 ep
.X_add_number
= 0xcfff0000;
3747 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
3748 ep
.X_add_number
= 0xffff;
3749 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
3750 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
3755 fix_loongson2f (struct mips_cl_insn
* ip
)
3757 if (mips_fix_loongson2f_nop
)
3758 fix_loongson2f_nop (ip
);
3760 if (mips_fix_loongson2f_jump
)
3761 fix_loongson2f_jump (ip
);
3764 /* IP is a branch that has a delay slot, and we need to fill it
3765 automatically. Return true if we can do that by swapping IP
3766 with the previous instruction.
3767 ADDRESS_EXPR is an operand of the instruction to be used with
3771 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3772 bfd_reloc_code_real_type
*reloc_type
)
3774 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
3775 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
3777 /* -O2 and above is required for this optimization. */
3778 if (mips_optimize
< 2)
3781 /* If we have seen .set volatile or .set nomove, don't optimize. */
3782 if (mips_opts
.nomove
)
3785 /* We can't swap if the previous instruction's position is fixed. */
3786 if (history
[0].fixed_p
)
3789 /* If the previous previous insn was in a .set noreorder, we can't
3790 swap. Actually, the MIPS assembler will swap in this situation.
3791 However, gcc configured -with-gnu-as will generate code like
3799 in which we can not swap the bne and INSN. If gcc is not configured
3800 -with-gnu-as, it does not output the .set pseudo-ops. */
3801 if (history
[1].noreorder_p
)
3804 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3805 This means that the previous instruction was a 4-byte one anyhow. */
3806 if (mips_opts
.mips16
&& history
[0].fixp
[0])
3809 /* If the branch is itself the target of a branch, we can not swap.
3810 We cheat on this; all we check for is whether there is a label on
3811 this instruction. If there are any branches to anything other than
3812 a label, users must use .set noreorder. */
3813 if (seg_info (now_seg
)->label_list
)
3816 /* If the previous instruction is in a variant frag other than this
3817 branch's one, we cannot do the swap. This does not apply to
3818 MIPS16 code, which uses variant frags for different purposes. */
3819 if (!mips_opts
.mips16
3821 && history
[0].frag
->fr_type
== rs_machine_dependent
)
3824 /* We do not swap with instructions that cannot architecturally
3825 be placed in a branch delay slot, such as SYNC or ERET. We
3826 also refrain from swapping with a trap instruction, since it
3827 complicates trap handlers to have the trap instruction be in
3829 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3830 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
3833 /* Check for conflicts between the branch and the instructions
3834 before the candidate delay slot. */
3835 if (nops_for_insn (0, history
+ 1, ip
) > 0)
3838 /* Check for conflicts between the swapped sequence and the
3839 target of the branch. */
3840 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
3843 /* If the branch reads a register that the previous
3844 instruction sets, we can not swap. */
3845 gpr_read
= gpr_read_mask (ip
);
3846 prev_gpr_write
= gpr_write_mask (&history
[0]);
3847 if (gpr_read
& prev_gpr_write
)
3850 /* If the branch writes a register that the previous
3851 instruction sets, we can not swap. */
3852 gpr_write
= gpr_write_mask (ip
);
3853 if (gpr_write
& prev_gpr_write
)
3856 /* If the branch writes a register that the previous
3857 instruction reads, we can not swap. */
3858 prev_gpr_read
= gpr_read_mask (&history
[0]);
3859 if (gpr_write
& prev_gpr_read
)
3862 /* If one instruction sets a condition code and the
3863 other one uses a condition code, we can not swap. */
3864 pinfo
= ip
->insn_mo
->pinfo
;
3865 if ((pinfo
& INSN_READ_COND_CODE
)
3866 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3868 if ((pinfo
& INSN_WRITE_COND_CODE
)
3869 && (prev_pinfo
& INSN_READ_COND_CODE
))
3872 /* If the previous instruction uses the PC, we can not swap. */
3873 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
3874 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
3876 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
3879 /* If the previous instruction has an incorrect size for a fixed
3880 branch delay slot in microMIPS mode, we cannot swap. */
3881 pinfo2
= ip
->insn_mo
->pinfo2
;
3882 if (mips_opts
.micromips
3883 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
3884 && insn_length (history
) != 2)
3886 if (mips_opts
.micromips
3887 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
3888 && insn_length (history
) != 4)
3891 /* On R5900 short loops need to be fixed by inserting a nop in
3892 the branch delay slots.
3893 A short loop can be terminated too early. */
3894 if (mips_opts
.arch
== CPU_R5900
3895 /* Check if instruction has a parameter, ignore "j $31". */
3896 && (address_expr
!= NULL
)
3897 /* Parameter must be 16 bit. */
3898 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
3899 /* Branch to same segment. */
3900 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
3901 /* Branch to same code fragment. */
3902 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
3903 /* Can only calculate branch offset if value is known. */
3904 && symbol_constant_p(address_expr
->X_add_symbol
)
3905 /* Check if branch is really conditional. */
3906 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
3907 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
3908 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
3911 /* Check if loop is shorter than 6 instructions including
3912 branch and delay slot. */
3913 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
3920 /* When the loop includes branches or jumps,
3921 it is not a short loop. */
3922 for (i
= 0; i
< (distance
/ 4); i
++)
3924 if ((history
[i
].cleared_p
)
3925 || delayed_branch_p(&history
[i
]))
3933 /* Insert nop after branch to fix short loop. */
3942 /* Decide how we should add IP to the instruction stream.
3943 ADDRESS_EXPR is an operand of the instruction to be used with
3946 static enum append_method
3947 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
3948 bfd_reloc_code_real_type
*reloc_type
)
3950 unsigned long pinfo
;
3952 /* The relaxed version of a macro sequence must be inherently
3954 if (mips_relax
.sequence
== 2)
3957 /* We must not dabble with instructions in a ".set norerorder" block. */
3958 if (mips_opts
.noreorder
)
3961 /* Otherwise, it's our responsibility to fill branch delay slots. */
3962 if (delayed_branch_p (ip
))
3964 if (!branch_likely_p (ip
)
3965 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
3968 pinfo
= ip
->insn_mo
->pinfo
;
3969 if (mips_opts
.mips16
3970 && ISA_SUPPORTS_MIPS16E
3971 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
3972 return APPEND_ADD_COMPACT
;
3974 return APPEND_ADD_WITH_NOP
;
3980 /* IP is a MIPS16 instruction whose opcode we have just changed.
3981 Point IP->insn_mo to the new opcode's definition. */
3984 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
3986 const struct mips_opcode
*mo
, *end
;
3988 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
3989 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
3990 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
3998 /* For microMIPS macros, we need to generate a local number label
3999 as the target of branches. */
4000 #define MICROMIPS_LABEL_CHAR '\037'
4001 static unsigned long micromips_target_label
;
4002 static char micromips_target_name
[32];
4005 micromips_label_name (void)
4007 char *p
= micromips_target_name
;
4008 char symbol_name_temporary
[24];
4016 l
= micromips_target_label
;
4017 #ifdef LOCAL_LABEL_PREFIX
4018 *p
++ = LOCAL_LABEL_PREFIX
;
4021 *p
++ = MICROMIPS_LABEL_CHAR
;
4024 symbol_name_temporary
[i
++] = l
% 10 + '0';
4029 *p
++ = symbol_name_temporary
[--i
];
4032 return micromips_target_name
;
4036 micromips_label_expr (expressionS
*label_expr
)
4038 label_expr
->X_op
= O_symbol
;
4039 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4040 label_expr
->X_add_number
= 0;
4044 micromips_label_inc (void)
4046 micromips_target_label
++;
4047 *micromips_target_name
= '\0';
4051 micromips_add_label (void)
4055 s
= colon (micromips_label_name ());
4056 micromips_label_inc ();
4057 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4059 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4065 /* If assembling microMIPS code, then return the microMIPS reloc
4066 corresponding to the requested one if any. Otherwise return
4067 the reloc unchanged. */
4069 static bfd_reloc_code_real_type
4070 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4072 static const bfd_reloc_code_real_type relocs
[][2] =
4074 /* Keep sorted incrementally by the left-hand key. */
4075 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4076 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4077 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4078 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4079 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4080 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4081 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4082 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4083 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4084 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4085 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4086 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4087 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4088 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4089 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4090 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4091 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4092 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4093 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4094 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4095 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4096 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4097 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4098 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4099 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4100 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4101 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4103 bfd_reloc_code_real_type r
;
4106 if (!mips_opts
.micromips
)
4108 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4114 return relocs
[i
][1];
4119 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4120 Return true on success, storing the resolved value in RESULT. */
4123 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4128 case BFD_RELOC_MIPS_HIGHEST
:
4129 case BFD_RELOC_MICROMIPS_HIGHEST
:
4130 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4133 case BFD_RELOC_MIPS_HIGHER
:
4134 case BFD_RELOC_MICROMIPS_HIGHER
:
4135 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4138 case BFD_RELOC_HI16_S
:
4139 case BFD_RELOC_MICROMIPS_HI16_S
:
4140 case BFD_RELOC_MIPS16_HI16_S
:
4141 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4144 case BFD_RELOC_HI16
:
4145 case BFD_RELOC_MICROMIPS_HI16
:
4146 case BFD_RELOC_MIPS16_HI16
:
4147 *result
= (operand
>> 16) & 0xffff;
4150 case BFD_RELOC_LO16
:
4151 case BFD_RELOC_MICROMIPS_LO16
:
4152 case BFD_RELOC_MIPS16_LO16
:
4153 *result
= operand
& 0xffff;
4156 case BFD_RELOC_UNUSED
:
4165 /* Output an instruction. IP is the instruction information.
4166 ADDRESS_EXPR is an operand of the instruction to be used with
4167 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4168 a macro expansion. */
4171 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4172 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4174 unsigned long prev_pinfo2
, pinfo
;
4175 bfd_boolean relaxed_branch
= FALSE
;
4176 enum append_method method
;
4177 bfd_boolean relax32
;
4180 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4181 fix_loongson2f (ip
);
4183 file_ase_mips16
|= mips_opts
.mips16
;
4184 file_ase_micromips
|= mips_opts
.micromips
;
4186 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4187 pinfo
= ip
->insn_mo
->pinfo
;
4189 if (mips_opts
.micromips
4191 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4192 && micromips_insn_length (ip
->insn_mo
) != 2)
4193 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4194 && micromips_insn_length (ip
->insn_mo
) != 4)))
4195 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4196 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4198 if (address_expr
== NULL
)
4200 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4201 && reloc_type
[1] == BFD_RELOC_UNUSED
4202 && reloc_type
[2] == BFD_RELOC_UNUSED
4203 && address_expr
->X_op
== O_constant
)
4205 switch (*reloc_type
)
4207 case BFD_RELOC_MIPS_JMP
:
4211 shift
= mips_opts
.micromips
? 1 : 2;
4212 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4213 as_bad (_("jump to misaligned address (0x%lx)"),
4214 (unsigned long) address_expr
->X_add_number
);
4215 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4221 case BFD_RELOC_MIPS16_JMP
:
4222 if ((address_expr
->X_add_number
& 3) != 0)
4223 as_bad (_("jump to misaligned address (0x%lx)"),
4224 (unsigned long) address_expr
->X_add_number
);
4226 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4227 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4228 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4232 case BFD_RELOC_16_PCREL_S2
:
4236 shift
= mips_opts
.micromips
? 1 : 2;
4237 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4238 as_bad (_("branch to misaligned address (0x%lx)"),
4239 (unsigned long) address_expr
->X_add_number
);
4240 if (!mips_relax_branch
)
4242 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4243 & ~((1 << (shift
+ 16)) - 1))
4244 as_bad (_("branch address range overflow (0x%lx)"),
4245 (unsigned long) address_expr
->X_add_number
);
4246 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4256 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4259 ip
->insn_opcode
|= value
& 0xffff;
4267 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4269 /* There are a lot of optimizations we could do that we don't.
4270 In particular, we do not, in general, reorder instructions.
4271 If you use gcc with optimization, it will reorder
4272 instructions and generally do much more optimization then we
4273 do here; repeating all that work in the assembler would only
4274 benefit hand written assembly code, and does not seem worth
4276 int nops
= (mips_optimize
== 0
4277 ? nops_for_insn (0, history
, NULL
)
4278 : nops_for_insn_or_target (0, history
, ip
));
4282 unsigned long old_frag_offset
;
4285 old_frag
= frag_now
;
4286 old_frag_offset
= frag_now_fix ();
4288 for (i
= 0; i
< nops
; i
++)
4289 add_fixed_insn (NOP_INSN
);
4290 insert_into_history (0, nops
, NOP_INSN
);
4294 listing_prev_line ();
4295 /* We may be at the start of a variant frag. In case we
4296 are, make sure there is enough space for the frag
4297 after the frags created by listing_prev_line. The
4298 argument to frag_grow here must be at least as large
4299 as the argument to all other calls to frag_grow in
4300 this file. We don't have to worry about being in the
4301 middle of a variant frag, because the variants insert
4302 all needed nop instructions themselves. */
4306 mips_move_text_labels ();
4308 #ifndef NO_ECOFF_DEBUGGING
4309 if (ECOFF_DEBUGGING
)
4310 ecoff_fix_loc (old_frag
, old_frag_offset
);
4314 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4318 /* Work out how many nops in prev_nop_frag are needed by IP,
4319 ignoring hazards generated by the first prev_nop_frag_since
4321 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4322 gas_assert (nops
<= prev_nop_frag_holds
);
4324 /* Enforce NOPS as a minimum. */
4325 if (nops
> prev_nop_frag_required
)
4326 prev_nop_frag_required
= nops
;
4328 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4330 /* Settle for the current number of nops. Update the history
4331 accordingly (for the benefit of any future .set reorder code). */
4332 prev_nop_frag
= NULL
;
4333 insert_into_history (prev_nop_frag_since
,
4334 prev_nop_frag_holds
, NOP_INSN
);
4338 /* Allow this instruction to replace one of the nops that was
4339 tentatively added to prev_nop_frag. */
4340 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4341 prev_nop_frag_holds
--;
4342 prev_nop_frag_since
++;
4346 method
= get_append_method (ip
, address_expr
, reloc_type
);
4347 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4350 /* The value passed to dwarf2_emit_insn is the distance between
4351 the beginning of the current instruction and the address that
4352 should be recorded in the debug tables. This is normally the
4355 For MIPS16/microMIPS debug info we want to use ISA-encoded
4356 addresses, so we use -1 for an address higher by one than the
4359 If the instruction produced is a branch that we will swap with
4360 the preceding instruction, then we add the displacement by which
4361 the branch will be moved backwards. This is more appropriate
4362 and for MIPS16/microMIPS code also prevents a debugger from
4363 placing a breakpoint in the middle of the branch (and corrupting
4364 code if software breakpoints are used). */
4365 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION
? -1 : 0) + branch_disp
);
4368 relax32
= (mips_relax_branch
4369 /* Don't try branch relaxation within .set nomacro, or within
4370 .set noat if we use $at for PIC computations. If it turns
4371 out that the branch was out-of-range, we'll get an error. */
4372 && !mips_opts
.warn_about_macros
4373 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4374 /* Don't relax BPOSGE32/64 as they have no complementing
4376 && !(ip
->insn_mo
->membership
& (INSN_DSP64
| INSN_DSP
)));
4378 if (!HAVE_CODE_COMPRESSION
4381 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4382 && delayed_branch_p (ip
))
4384 relaxed_branch
= TRUE
;
4385 add_relaxed_insn (ip
, (relaxed_branch_length
4387 uncond_branch_p (ip
) ? -1
4388 : branch_likely_p (ip
) ? 1
4392 uncond_branch_p (ip
),
4393 branch_likely_p (ip
),
4394 pinfo
& INSN_WRITE_GPR_31
,
4396 address_expr
->X_add_symbol
,
4397 address_expr
->X_add_number
);
4398 *reloc_type
= BFD_RELOC_UNUSED
;
4400 else if (mips_opts
.micromips
4402 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4403 || *reloc_type
> BFD_RELOC_UNUSED
)
4404 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4405 /* Don't try branch relaxation when users specify
4406 16-bit/32-bit instructions. */
4407 && !forced_insn_length
)
4409 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4410 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4411 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4412 int compact
= compact_branch_p (ip
);
4413 int al
= pinfo
& INSN_WRITE_GPR_31
;
4416 gas_assert (address_expr
!= NULL
);
4417 gas_assert (!mips_relax
.sequence
);
4419 relaxed_branch
= TRUE
;
4420 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4421 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4422 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4424 address_expr
->X_add_symbol
,
4425 address_expr
->X_add_number
);
4426 *reloc_type
= BFD_RELOC_UNUSED
;
4428 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4430 /* We need to set up a variant frag. */
4431 gas_assert (address_expr
!= NULL
);
4432 add_relaxed_insn (ip
, 4, 0,
4434 (*reloc_type
- BFD_RELOC_UNUSED
,
4435 forced_insn_length
== 2, forced_insn_length
== 4,
4436 delayed_branch_p (&history
[0]),
4437 history
[0].mips16_absolute_jump_p
),
4438 make_expr_symbol (address_expr
), 0);
4440 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4442 if (!delayed_branch_p (ip
))
4443 /* Make sure there is enough room to swap this instruction with
4444 a following jump instruction. */
4446 add_fixed_insn (ip
);
4450 if (mips_opts
.mips16
4451 && mips_opts
.noreorder
4452 && delayed_branch_p (&history
[0]))
4453 as_warn (_("extended instruction in delay slot"));
4455 if (mips_relax
.sequence
)
4457 /* If we've reached the end of this frag, turn it into a variant
4458 frag and record the information for the instructions we've
4460 if (frag_room () < 4)
4461 relax_close_frag ();
4462 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4465 if (mips_relax
.sequence
!= 2)
4467 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4468 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4469 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4470 mips_macro_warning
.insns
[0]++;
4472 if (mips_relax
.sequence
!= 1)
4474 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4475 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4476 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4477 mips_macro_warning
.insns
[1]++;
4480 if (mips_opts
.mips16
)
4483 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4485 add_fixed_insn (ip
);
4488 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4490 bfd_reloc_code_real_type final_type
[3];
4491 reloc_howto_type
*howto0
;
4492 reloc_howto_type
*howto
;
4495 /* Perform any necessary conversion to microMIPS relocations
4496 and find out how many relocations there actually are. */
4497 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4498 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4500 /* In a compound relocation, it is the final (outermost)
4501 operator that determines the relocated field. */
4502 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4506 /* To reproduce this failure try assembling gas/testsuites/
4507 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4509 as_bad (_("Unsupported MIPS relocation number %d"),
4511 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
4515 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4516 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4517 bfd_get_reloc_size (howto
),
4519 howto0
&& howto0
->pc_relative
,
4522 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4523 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4524 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4526 /* These relocations can have an addend that won't fit in
4527 4 octets for 64bit assembly. */
4529 && ! howto
->partial_inplace
4530 && (reloc_type
[0] == BFD_RELOC_16
4531 || reloc_type
[0] == BFD_RELOC_32
4532 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4533 || reloc_type
[0] == BFD_RELOC_GPREL16
4534 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4535 || reloc_type
[0] == BFD_RELOC_GPREL32
4536 || reloc_type
[0] == BFD_RELOC_64
4537 || reloc_type
[0] == BFD_RELOC_CTOR
4538 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4539 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4540 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4541 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4542 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4543 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4544 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4545 || hi16_reloc_p (reloc_type
[0])
4546 || lo16_reloc_p (reloc_type
[0])))
4547 ip
->fixp
[0]->fx_no_overflow
= 1;
4549 /* These relocations can have an addend that won't fit in 2 octets. */
4550 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4551 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4552 ip
->fixp
[0]->fx_no_overflow
= 1;
4554 if (mips_relax
.sequence
)
4556 if (mips_relax
.first_fixup
== 0)
4557 mips_relax
.first_fixup
= ip
->fixp
[0];
4559 else if (reloc_needs_lo_p (*reloc_type
))
4561 struct mips_hi_fixup
*hi_fixup
;
4563 /* Reuse the last entry if it already has a matching %lo. */
4564 hi_fixup
= mips_hi_fixup_list
;
4566 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4568 hi_fixup
= ((struct mips_hi_fixup
*)
4569 xmalloc (sizeof (struct mips_hi_fixup
)));
4570 hi_fixup
->next
= mips_hi_fixup_list
;
4571 mips_hi_fixup_list
= hi_fixup
;
4573 hi_fixup
->fixp
= ip
->fixp
[0];
4574 hi_fixup
->seg
= now_seg
;
4577 /* Add fixups for the second and third relocations, if given.
4578 Note that the ABI allows the second relocation to be
4579 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4580 moment we only use RSS_UNDEF, but we could add support
4581 for the others if it ever becomes necessary. */
4582 for (i
= 1; i
< 3; i
++)
4583 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4585 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4586 ip
->fixp
[0]->fx_size
, NULL
, 0,
4587 FALSE
, final_type
[i
]);
4589 /* Use fx_tcbit to mark compound relocs. */
4590 ip
->fixp
[0]->fx_tcbit
= 1;
4591 ip
->fixp
[i
]->fx_tcbit
= 1;
4596 /* Update the register mask information. */
4597 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4598 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4603 insert_into_history (0, 1, ip
);
4606 case APPEND_ADD_WITH_NOP
:
4608 struct mips_cl_insn
*nop
;
4610 insert_into_history (0, 1, ip
);
4611 nop
= get_delay_slot_nop (ip
);
4612 add_fixed_insn (nop
);
4613 insert_into_history (0, 1, nop
);
4614 if (mips_relax
.sequence
)
4615 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4619 case APPEND_ADD_COMPACT
:
4620 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4621 gas_assert (mips_opts
.mips16
);
4622 ip
->insn_opcode
|= 0x0080;
4623 find_altered_mips16_opcode (ip
);
4625 insert_into_history (0, 1, ip
);
4630 struct mips_cl_insn delay
= history
[0];
4631 if (mips_opts
.mips16
)
4633 know (delay
.frag
== ip
->frag
);
4634 move_insn (ip
, delay
.frag
, delay
.where
);
4635 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4637 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4639 /* Add the delay slot instruction to the end of the
4640 current frag and shrink the fixed part of the
4641 original frag. If the branch occupies the tail of
4642 the latter, move it backwards to cover the gap. */
4643 delay
.frag
->fr_fix
-= branch_disp
;
4644 if (delay
.frag
== ip
->frag
)
4645 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4646 add_fixed_insn (&delay
);
4650 move_insn (&delay
, ip
->frag
,
4651 ip
->where
- branch_disp
+ insn_length (ip
));
4652 move_insn (ip
, history
[0].frag
, history
[0].where
);
4656 insert_into_history (0, 1, &delay
);
4661 /* If we have just completed an unconditional branch, clear the history. */
4662 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4663 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4667 mips_no_prev_insn ();
4669 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4670 history
[i
].cleared_p
= 1;
4673 /* We need to emit a label at the end of branch-likely macros. */
4674 if (emit_branch_likely_macro
)
4676 emit_branch_likely_macro
= FALSE
;
4677 micromips_add_label ();
4680 /* We just output an insn, so the next one doesn't have a label. */
4681 mips_clear_insn_labels ();
4684 /* Forget that there was any previous instruction or label.
4685 When BRANCH is true, the branch history is also flushed. */
4688 mips_no_prev_insn (void)
4690 prev_nop_frag
= NULL
;
4691 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
4692 mips_clear_insn_labels ();
4695 /* This function must be called before we emit something other than
4696 instructions. It is like mips_no_prev_insn except that it inserts
4697 any NOPS that might be needed by previous instructions. */
4700 mips_emit_delays (void)
4702 if (! mips_opts
.noreorder
)
4704 int nops
= nops_for_insn (0, history
, NULL
);
4708 add_fixed_insn (NOP_INSN
);
4709 mips_move_text_labels ();
4712 mips_no_prev_insn ();
4715 /* Start a (possibly nested) noreorder block. */
4718 start_noreorder (void)
4720 if (mips_opts
.noreorder
== 0)
4725 /* None of the instructions before the .set noreorder can be moved. */
4726 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4727 history
[i
].fixed_p
= 1;
4729 /* Insert any nops that might be needed between the .set noreorder
4730 block and the previous instructions. We will later remove any
4731 nops that turn out not to be needed. */
4732 nops
= nops_for_insn (0, history
, NULL
);
4735 if (mips_optimize
!= 0)
4737 /* Record the frag which holds the nop instructions, so
4738 that we can remove them if we don't need them. */
4739 frag_grow (nops
* NOP_INSN_SIZE
);
4740 prev_nop_frag
= frag_now
;
4741 prev_nop_frag_holds
= nops
;
4742 prev_nop_frag_required
= 0;
4743 prev_nop_frag_since
= 0;
4746 for (; nops
> 0; --nops
)
4747 add_fixed_insn (NOP_INSN
);
4749 /* Move on to a new frag, so that it is safe to simply
4750 decrease the size of prev_nop_frag. */
4751 frag_wane (frag_now
);
4753 mips_move_text_labels ();
4755 mips_mark_labels ();
4756 mips_clear_insn_labels ();
4758 mips_opts
.noreorder
++;
4759 mips_any_noreorder
= 1;
4762 /* End a nested noreorder block. */
4765 end_noreorder (void)
4767 mips_opts
.noreorder
--;
4768 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
4770 /* Commit to inserting prev_nop_frag_required nops and go back to
4771 handling nop insertion the .set reorder way. */
4772 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
4774 insert_into_history (prev_nop_frag_since
,
4775 prev_nop_frag_required
, NOP_INSN
);
4776 prev_nop_frag
= NULL
;
4780 /* Set up global variables for the start of a new macro. */
4785 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
4786 memset (&mips_macro_warning
.first_insn_sizes
, 0,
4787 sizeof (mips_macro_warning
.first_insn_sizes
));
4788 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
4789 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
4790 && delayed_branch_p (&history
[0]));
4791 switch (history
[0].insn_mo
->pinfo2
4792 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
4794 case INSN2_BRANCH_DELAY_32BIT
:
4795 mips_macro_warning
.delay_slot_length
= 4;
4797 case INSN2_BRANCH_DELAY_16BIT
:
4798 mips_macro_warning
.delay_slot_length
= 2;
4801 mips_macro_warning
.delay_slot_length
= 0;
4804 mips_macro_warning
.first_frag
= NULL
;
4807 /* Given that a macro is longer than one instruction or of the wrong size,
4808 return the appropriate warning for it. Return null if no warning is
4809 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4810 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4811 and RELAX_NOMACRO. */
4814 macro_warning (relax_substateT subtype
)
4816 if (subtype
& RELAX_DELAY_SLOT
)
4817 return _("Macro instruction expanded into multiple instructions"
4818 " in a branch delay slot");
4819 else if (subtype
& RELAX_NOMACRO
)
4820 return _("Macro instruction expanded into multiple instructions");
4821 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
4822 | RELAX_DELAY_SLOT_SIZE_SECOND
))
4823 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
4824 ? _("Macro instruction expanded into a wrong size instruction"
4825 " in a 16-bit branch delay slot")
4826 : _("Macro instruction expanded into a wrong size instruction"
4827 " in a 32-bit branch delay slot"));
4832 /* Finish up a macro. Emit warnings as appropriate. */
4837 /* Relaxation warning flags. */
4838 relax_substateT subtype
= 0;
4840 /* Check delay slot size requirements. */
4841 if (mips_macro_warning
.delay_slot_length
== 2)
4842 subtype
|= RELAX_DELAY_SLOT_16BIT
;
4843 if (mips_macro_warning
.delay_slot_length
!= 0)
4845 if (mips_macro_warning
.delay_slot_length
4846 != mips_macro_warning
.first_insn_sizes
[0])
4847 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
4848 if (mips_macro_warning
.delay_slot_length
4849 != mips_macro_warning
.first_insn_sizes
[1])
4850 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
4853 /* Check instruction count requirements. */
4854 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
4856 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
4857 subtype
|= RELAX_SECOND_LONGER
;
4858 if (mips_opts
.warn_about_macros
)
4859 subtype
|= RELAX_NOMACRO
;
4860 if (mips_macro_warning
.delay_slot_p
)
4861 subtype
|= RELAX_DELAY_SLOT
;
4864 /* If both alternatives fail to fill a delay slot correctly,
4865 emit the warning now. */
4866 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
4867 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
4872 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
4873 | RELAX_DELAY_SLOT_SIZE_FIRST
4874 | RELAX_DELAY_SLOT_SIZE_SECOND
);
4875 msg
= macro_warning (s
);
4877 as_warn ("%s", msg
);
4881 /* If both implementations are longer than 1 instruction, then emit the
4883 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
4888 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
4889 msg
= macro_warning (s
);
4891 as_warn ("%s", msg
);
4895 /* If any flags still set, then one implementation might need a warning
4896 and the other either will need one of a different kind or none at all.
4897 Pass any remaining flags over to relaxation. */
4898 if (mips_macro_warning
.first_frag
!= NULL
)
4899 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
4902 /* Instruction operand formats used in macros that vary between
4903 standard MIPS and microMIPS code. */
4905 static const char * const brk_fmt
[2] = { "c", "mF" };
4906 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
4907 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
4908 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
4909 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
4910 static const char * const mfhl_fmt
[2] = { "d", "mj" };
4911 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
4912 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
4914 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4915 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4916 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4917 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4918 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4919 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4920 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4921 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4923 /* Read a macro's relocation codes from *ARGS and store them in *R.
4924 The first argument in *ARGS will be either the code for a single
4925 relocation or -1 followed by the three codes that make up a
4926 composite relocation. */
4929 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
4933 next
= va_arg (*args
, int);
4935 r
[0] = (bfd_reloc_code_real_type
) next
;
4937 for (i
= 0; i
< 3; i
++)
4938 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
4941 /* Build an instruction created by a macro expansion. This is passed
4942 a pointer to the count of instructions created so far, an
4943 expression, the name of the instruction to build, an operand format
4944 string, and corresponding arguments. */
4947 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
4949 const struct mips_opcode
*mo
= NULL
;
4950 bfd_reloc_code_real_type r
[3];
4951 const struct mips_opcode
*amo
;
4952 struct hash_control
*hash
;
4953 struct mips_cl_insn insn
;
4956 va_start (args
, fmt
);
4958 if (mips_opts
.mips16
)
4960 mips16_macro_build (ep
, name
, fmt
, &args
);
4965 r
[0] = BFD_RELOC_UNUSED
;
4966 r
[1] = BFD_RELOC_UNUSED
;
4967 r
[2] = BFD_RELOC_UNUSED
;
4968 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
4969 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
4971 gas_assert (strcmp (name
, amo
->name
) == 0);
4975 /* Search until we get a match for NAME. It is assumed here that
4976 macros will never generate MDMX, MIPS-3D, or MT instructions.
4977 We try to match an instruction that fulfils the branch delay
4978 slot instruction length requirement (if any) of the previous
4979 instruction. While doing this we record the first instruction
4980 seen that matches all the other conditions and use it anyway
4981 if the requirement cannot be met; we will issue an appropriate
4982 warning later on. */
4983 if (strcmp (fmt
, amo
->args
) == 0
4984 && amo
->pinfo
!= INSN_MACRO
4985 && is_opcode_valid (amo
)
4986 && is_size_valid (amo
))
4988 if (is_delay_slot_valid (amo
))
4998 gas_assert (amo
->name
);
5000 while (strcmp (name
, amo
->name
) == 0);
5003 create_insn (&insn
, mo
);
5021 INSERT_OPERAND (mips_opts
.micromips
,
5022 EXTLSB
, insn
, va_arg (args
, int));
5027 /* Note that in the macro case, these arguments are already
5028 in MSB form. (When handling the instruction in the
5029 non-macro case, these arguments are sizes from which
5030 MSB values must be calculated.) */
5031 INSERT_OPERAND (mips_opts
.micromips
,
5032 INSMSB
, insn
, va_arg (args
, int));
5038 /* Note that in the macro case, these arguments are already
5039 in MSBD form. (When handling the instruction in the
5040 non-macro case, these arguments are sizes from which
5041 MSBD values must be calculated.) */
5042 INSERT_OPERAND (mips_opts
.micromips
,
5043 EXTMSBD
, insn
, va_arg (args
, int));
5047 gas_assert (!mips_opts
.micromips
);
5048 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5057 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5061 gas_assert (mips_opts
.micromips
);
5065 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5069 gas_assert (!mips_opts
.micromips
);
5070 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
5074 gas_assert (!mips_opts
.micromips
);
5076 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5080 if (mips_opts
.micromips
)
5081 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5083 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5087 gas_assert (!mips_opts
.micromips
);
5089 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5093 gas_assert (!mips_opts
.micromips
);
5095 int tmp
= va_arg (args
, int);
5097 INSERT_OPERAND (0, RT
, insn
, tmp
);
5098 INSERT_OPERAND (0, RD
, insn
, tmp
);
5104 gas_assert (!mips_opts
.micromips
);
5105 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5112 INSERT_OPERAND (mips_opts
.micromips
,
5113 SHAMT
, insn
, va_arg (args
, int));
5117 gas_assert (!mips_opts
.micromips
);
5118 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5122 gas_assert (!mips_opts
.micromips
);
5123 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5127 gas_assert (!mips_opts
.micromips
);
5128 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5132 gas_assert (!mips_opts
.micromips
);
5133 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5140 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5145 macro_read_relocs (&args
, r
);
5146 gas_assert (*r
== BFD_RELOC_GPREL16
5147 || *r
== BFD_RELOC_MIPS_HIGHER
5148 || *r
== BFD_RELOC_HI16_S
5149 || *r
== BFD_RELOC_LO16
5150 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5154 macro_read_relocs (&args
, r
);
5158 macro_read_relocs (&args
, r
);
5159 gas_assert (ep
!= NULL
5160 && (ep
->X_op
== O_constant
5161 || (ep
->X_op
== O_symbol
5162 && (*r
== BFD_RELOC_MIPS_HIGHEST
5163 || *r
== BFD_RELOC_HI16_S
5164 || *r
== BFD_RELOC_HI16
5165 || *r
== BFD_RELOC_GPREL16
5166 || *r
== BFD_RELOC_MIPS_GOT_HI16
5167 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5171 gas_assert (ep
!= NULL
);
5174 * This allows macro() to pass an immediate expression for
5175 * creating short branches without creating a symbol.
5177 * We don't allow branch relaxation for these branches, as
5178 * they should only appear in ".set nomacro" anyway.
5180 if (ep
->X_op
== O_constant
)
5182 /* For microMIPS we always use relocations for branches.
5183 So we should not resolve immediate values. */
5184 gas_assert (!mips_opts
.micromips
);
5186 if ((ep
->X_add_number
& 3) != 0)
5187 as_bad (_("branch to misaligned address (0x%lx)"),
5188 (unsigned long) ep
->X_add_number
);
5189 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5190 as_bad (_("branch address range overflow (0x%lx)"),
5191 (unsigned long) ep
->X_add_number
);
5192 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5196 *r
= BFD_RELOC_16_PCREL_S2
;
5200 gas_assert (ep
!= NULL
);
5201 *r
= BFD_RELOC_MIPS_JMP
;
5205 gas_assert (!mips_opts
.micromips
);
5206 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5210 INSERT_OPERAND (mips_opts
.micromips
,
5211 CACHE
, insn
, va_arg (args
, unsigned long));
5215 gas_assert (mips_opts
.micromips
);
5216 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5220 gas_assert (mips_opts
.micromips
);
5221 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5225 INSERT_OPERAND (mips_opts
.micromips
,
5226 3BITPOS
, insn
, va_arg (args
, unsigned int));
5230 INSERT_OPERAND (mips_opts
.micromips
,
5231 OFFSET12
, insn
, va_arg (args
, unsigned long));
5235 gas_assert (mips_opts
.micromips
);
5236 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5239 case 'm': /* Opcode extension character. */
5240 gas_assert (mips_opts
.micromips
);
5244 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5248 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5252 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5266 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5268 append_insn (&insn
, ep
, r
, TRUE
);
5272 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5275 struct mips_opcode
*mo
;
5276 struct mips_cl_insn insn
;
5277 bfd_reloc_code_real_type r
[3]
5278 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5280 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5282 gas_assert (strcmp (name
, mo
->name
) == 0);
5284 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5287 gas_assert (mo
->name
);
5288 gas_assert (strcmp (name
, mo
->name
) == 0);
5291 create_insn (&insn
, mo
);
5309 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5314 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5318 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5322 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5332 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5339 regno
= va_arg (*args
, int);
5340 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5341 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5364 gas_assert (ep
!= NULL
);
5366 if (ep
->X_op
!= O_constant
)
5367 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5368 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5370 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5372 *r
= BFD_RELOC_UNUSED
;
5378 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5385 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5387 append_insn (&insn
, ep
, r
, TRUE
);
5391 * Sign-extend 32-bit mode constants that have bit 31 set and all
5392 * higher bits unset.
5395 normalize_constant_expr (expressionS
*ex
)
5397 if (ex
->X_op
== O_constant
5398 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5399 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5404 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5405 * all higher bits unset.
5408 normalize_address_expr (expressionS
*ex
)
5410 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5411 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5412 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5413 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5418 * Generate a "jalr" instruction with a relocation hint to the called
5419 * function. This occurs in NewABI PIC code.
5422 macro_build_jalr (expressionS
*ep
, int cprestore
)
5424 static const bfd_reloc_code_real_type jalr_relocs
[2]
5425 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5426 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5430 if (MIPS_JALR_HINT_P (ep
))
5435 if (mips_opts
.micromips
)
5437 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5438 if (MIPS_JALR_HINT_P (ep
)
5439 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5440 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5442 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5445 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5446 if (MIPS_JALR_HINT_P (ep
))
5447 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5451 * Generate a "lui" instruction.
5454 macro_build_lui (expressionS
*ep
, int regnum
)
5456 gas_assert (! mips_opts
.mips16
);
5458 if (ep
->X_op
!= O_constant
)
5460 gas_assert (ep
->X_op
== O_symbol
);
5461 /* _gp_disp is a special case, used from s_cpload.
5462 __gnu_local_gp is used if mips_no_shared. */
5463 gas_assert (mips_pic
== NO_PIC
5465 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5466 || (! mips_in_shared
5467 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5468 "__gnu_local_gp") == 0));
5471 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5474 /* Generate a sequence of instructions to do a load or store from a constant
5475 offset off of a base register (breg) into/from a target register (treg),
5476 using AT if necessary. */
5478 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5479 int treg
, int breg
, int dbl
)
5481 gas_assert (ep
->X_op
== O_constant
);
5483 /* Sign-extending 32-bit constants makes their handling easier. */
5485 normalize_constant_expr (ep
);
5487 /* Right now, this routine can only handle signed 32-bit constants. */
5488 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5489 as_warn (_("operand overflow"));
5491 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5493 /* Signed 16-bit offset will fit in the op. Easy! */
5494 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5498 /* 32-bit offset, need multiple instructions and AT, like:
5499 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5500 addu $tempreg,$tempreg,$breg
5501 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5502 to handle the complete offset. */
5503 macro_build_lui (ep
, AT
);
5504 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5505 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5508 as_bad (_("Macro used $at after \".set noat\""));
5513 * Generates code to set the $at register to true (one)
5514 * if reg is less than the immediate expression.
5517 set_at (int reg
, int unsignedp
)
5519 if (imm_expr
.X_op
== O_constant
5520 && imm_expr
.X_add_number
>= -0x8000
5521 && imm_expr
.X_add_number
< 0x8000)
5522 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5523 AT
, reg
, BFD_RELOC_LO16
);
5526 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5527 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5531 /* Warn if an expression is not a constant. */
5534 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5536 if (ex
->X_op
== O_big
)
5537 as_bad (_("unsupported large constant"));
5538 else if (ex
->X_op
!= O_constant
)
5539 as_bad (_("Instruction %s requires absolute expression"),
5542 if (HAVE_32BIT_GPRS
)
5543 normalize_constant_expr (ex
);
5546 /* Count the leading zeroes by performing a binary chop. This is a
5547 bulky bit of source, but performance is a LOT better for the
5548 majority of values than a simple loop to count the bits:
5549 for (lcnt = 0; (lcnt < 32); lcnt++)
5550 if ((v) & (1 << (31 - lcnt)))
5552 However it is not code size friendly, and the gain will drop a bit
5553 on certain cached systems.
5555 #define COUNT_TOP_ZEROES(v) \
5556 (((v) & ~0xffff) == 0 \
5557 ? ((v) & ~0xff) == 0 \
5558 ? ((v) & ~0xf) == 0 \
5559 ? ((v) & ~0x3) == 0 \
5560 ? ((v) & ~0x1) == 0 \
5565 : ((v) & ~0x7) == 0 \
5568 : ((v) & ~0x3f) == 0 \
5569 ? ((v) & ~0x1f) == 0 \
5572 : ((v) & ~0x7f) == 0 \
5575 : ((v) & ~0xfff) == 0 \
5576 ? ((v) & ~0x3ff) == 0 \
5577 ? ((v) & ~0x1ff) == 0 \
5580 : ((v) & ~0x7ff) == 0 \
5583 : ((v) & ~0x3fff) == 0 \
5584 ? ((v) & ~0x1fff) == 0 \
5587 : ((v) & ~0x7fff) == 0 \
5590 : ((v) & ~0xffffff) == 0 \
5591 ? ((v) & ~0xfffff) == 0 \
5592 ? ((v) & ~0x3ffff) == 0 \
5593 ? ((v) & ~0x1ffff) == 0 \
5596 : ((v) & ~0x7ffff) == 0 \
5599 : ((v) & ~0x3fffff) == 0 \
5600 ? ((v) & ~0x1fffff) == 0 \
5603 : ((v) & ~0x7fffff) == 0 \
5606 : ((v) & ~0xfffffff) == 0 \
5607 ? ((v) & ~0x3ffffff) == 0 \
5608 ? ((v) & ~0x1ffffff) == 0 \
5611 : ((v) & ~0x7ffffff) == 0 \
5614 : ((v) & ~0x3fffffff) == 0 \
5615 ? ((v) & ~0x1fffffff) == 0 \
5618 : ((v) & ~0x7fffffff) == 0 \
5623 * This routine generates the least number of instructions necessary to load
5624 * an absolute expression value into a register.
5627 load_register (int reg
, expressionS
*ep
, int dbl
)
5630 expressionS hi32
, lo32
;
5632 if (ep
->X_op
!= O_big
)
5634 gas_assert (ep
->X_op
== O_constant
);
5636 /* Sign-extending 32-bit constants makes their handling easier. */
5638 normalize_constant_expr (ep
);
5640 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5642 /* We can handle 16 bit signed values with an addiu to
5643 $zero. No need to ever use daddiu here, since $zero and
5644 the result are always correct in 32 bit mode. */
5645 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5648 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5650 /* We can handle 16 bit unsigned values with an ori to
5652 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5655 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5657 /* 32 bit values require an lui. */
5658 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5659 if ((ep
->X_add_number
& 0xffff) != 0)
5660 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5665 /* The value is larger than 32 bits. */
5667 if (!dbl
|| HAVE_32BIT_GPRS
)
5671 sprintf_vma (value
, ep
->X_add_number
);
5672 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5673 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5677 if (ep
->X_op
!= O_big
)
5680 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5681 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
5682 hi32
.X_add_number
&= 0xffffffff;
5684 lo32
.X_add_number
&= 0xffffffff;
5688 gas_assert (ep
->X_add_number
> 2);
5689 if (ep
->X_add_number
== 3)
5690 generic_bignum
[3] = 0;
5691 else if (ep
->X_add_number
> 4)
5692 as_bad (_("Number larger than 64 bits"));
5693 lo32
.X_op
= O_constant
;
5694 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
5695 hi32
.X_op
= O_constant
;
5696 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
5699 if (hi32
.X_add_number
== 0)
5704 unsigned long hi
, lo
;
5706 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
5708 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
5710 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5713 if (lo32
.X_add_number
& 0x80000000)
5715 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5716 if (lo32
.X_add_number
& 0xffff)
5717 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
5722 /* Check for 16bit shifted constant. We know that hi32 is
5723 non-zero, so start the mask on the first bit of the hi32
5728 unsigned long himask
, lomask
;
5732 himask
= 0xffff >> (32 - shift
);
5733 lomask
= (0xffff << shift
) & 0xffffffff;
5737 himask
= 0xffff << (shift
- 32);
5740 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
5741 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
5745 tmp
.X_op
= O_constant
;
5747 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
5748 | (lo32
.X_add_number
>> shift
));
5750 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
5751 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5752 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5753 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5758 while (shift
<= (64 - 16));
5760 /* Find the bit number of the lowest one bit, and store the
5761 shifted value in hi/lo. */
5762 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
5763 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
5767 while ((lo
& 1) == 0)
5772 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
5778 while ((hi
& 1) == 0)
5787 /* Optimize if the shifted value is a (power of 2) - 1. */
5788 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
5789 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
5791 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
5796 /* This instruction will set the register to be all
5798 tmp
.X_op
= O_constant
;
5799 tmp
.X_add_number
= (offsetT
) -1;
5800 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5804 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
5805 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
5807 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
5808 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
5813 /* Sign extend hi32 before calling load_register, because we can
5814 generally get better code when we load a sign extended value. */
5815 if ((hi32
.X_add_number
& 0x80000000) != 0)
5816 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
5817 load_register (reg
, &hi32
, 0);
5820 if ((lo32
.X_add_number
& 0xffff0000) == 0)
5824 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
5832 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
5834 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5835 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
5841 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
5845 mid16
.X_add_number
>>= 16;
5846 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5847 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5850 if ((lo32
.X_add_number
& 0xffff) != 0)
5851 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
5855 load_delay_nop (void)
5857 if (!gpr_interlocks
)
5858 macro_build (NULL
, "nop", "");
5861 /* Load an address into a register. */
5864 load_address (int reg
, expressionS
*ep
, int *used_at
)
5866 if (ep
->X_op
!= O_constant
5867 && ep
->X_op
!= O_symbol
)
5869 as_bad (_("expression too complex"));
5870 ep
->X_op
= O_constant
;
5873 if (ep
->X_op
== O_constant
)
5875 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
5879 if (mips_pic
== NO_PIC
)
5881 /* If this is a reference to a GP relative symbol, we want
5882 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5884 lui $reg,<sym> (BFD_RELOC_HI16_S)
5885 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5886 If we have an addend, we always use the latter form.
5888 With 64bit address space and a usable $at we want
5889 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5890 lui $at,<sym> (BFD_RELOC_HI16_S)
5891 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5892 daddiu $at,<sym> (BFD_RELOC_LO16)
5896 If $at is already in use, we use a path which is suboptimal
5897 on superscalar processors.
5898 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5899 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5901 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5903 daddiu $reg,<sym> (BFD_RELOC_LO16)
5905 For GP relative symbols in 64bit address space we can use
5906 the same sequence as in 32bit address space. */
5907 if (HAVE_64BIT_SYMBOLS
)
5909 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5910 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5912 relax_start (ep
->X_add_symbol
);
5913 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5914 mips_gp_register
, BFD_RELOC_GPREL16
);
5918 if (*used_at
== 0 && mips_opts
.at
)
5920 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5921 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
5922 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5923 BFD_RELOC_MIPS_HIGHER
);
5924 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
5925 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
5926 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
5931 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
5932 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
5933 BFD_RELOC_MIPS_HIGHER
);
5934 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5935 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
5936 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
5937 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
5940 if (mips_relax
.sequence
)
5945 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
5946 && !nopic_need_relax (ep
->X_add_symbol
, 1))
5948 relax_start (ep
->X_add_symbol
);
5949 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
5950 mips_gp_register
, BFD_RELOC_GPREL16
);
5953 macro_build_lui (ep
, reg
);
5954 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
5955 reg
, reg
, BFD_RELOC_LO16
);
5956 if (mips_relax
.sequence
)
5960 else if (!mips_big_got
)
5964 /* If this is a reference to an external symbol, we want
5965 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5967 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5969 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5970 If there is a constant, it must be added in after.
5972 If we have NewABI, we want
5973 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5974 unless we're referencing a global symbol with a non-zero
5975 offset, in which case cst must be added separately. */
5978 if (ep
->X_add_number
)
5980 ex
.X_add_number
= ep
->X_add_number
;
5981 ep
->X_add_number
= 0;
5982 relax_start (ep
->X_add_symbol
);
5983 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5984 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5985 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
5986 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5987 ex
.X_op
= O_constant
;
5988 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
5989 reg
, reg
, BFD_RELOC_LO16
);
5990 ep
->X_add_number
= ex
.X_add_number
;
5993 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
5994 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5995 if (mips_relax
.sequence
)
6000 ex
.X_add_number
= ep
->X_add_number
;
6001 ep
->X_add_number
= 0;
6002 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6003 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6005 relax_start (ep
->X_add_symbol
);
6007 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6011 if (ex
.X_add_number
!= 0)
6013 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6014 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6015 ex
.X_op
= O_constant
;
6016 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6017 reg
, reg
, BFD_RELOC_LO16
);
6021 else if (mips_big_got
)
6025 /* This is the large GOT case. If this is a reference to an
6026 external symbol, we want
6027 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6029 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6031 Otherwise, for a reference to a local symbol in old ABI, we want
6032 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6034 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6035 If there is a constant, it must be added in after.
6037 In the NewABI, for local symbols, with or without offsets, we want:
6038 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6039 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6043 ex
.X_add_number
= ep
->X_add_number
;
6044 ep
->X_add_number
= 0;
6045 relax_start (ep
->X_add_symbol
);
6046 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6047 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6048 reg
, reg
, mips_gp_register
);
6049 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6050 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6051 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6052 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6053 else if (ex
.X_add_number
)
6055 ex
.X_op
= O_constant
;
6056 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6060 ep
->X_add_number
= ex
.X_add_number
;
6062 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6063 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6064 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6065 BFD_RELOC_MIPS_GOT_OFST
);
6070 ex
.X_add_number
= ep
->X_add_number
;
6071 ep
->X_add_number
= 0;
6072 relax_start (ep
->X_add_symbol
);
6073 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6074 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6075 reg
, reg
, mips_gp_register
);
6076 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6077 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6079 if (reg_needs_delay (mips_gp_register
))
6081 /* We need a nop before loading from $gp. This special
6082 check is required because the lui which starts the main
6083 instruction stream does not refer to $gp, and so will not
6084 insert the nop which may be required. */
6085 macro_build (NULL
, "nop", "");
6087 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6088 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6090 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6094 if (ex
.X_add_number
!= 0)
6096 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6097 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6098 ex
.X_op
= O_constant
;
6099 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6107 if (!mips_opts
.at
&& *used_at
== 1)
6108 as_bad (_("Macro used $at after \".set noat\""));
6111 /* Move the contents of register SOURCE into register DEST. */
6114 move_register (int dest
, int source
)
6116 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6117 instruction specifically requires a 32-bit one. */
6118 if (mips_opts
.micromips
6119 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6120 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6122 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6126 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6127 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6128 The two alternatives are:
6130 Global symbol Local sybmol
6131 ------------- ------------
6132 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6134 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6136 load_got_offset emits the first instruction and add_got_offset
6137 emits the second for a 16-bit offset or add_got_offset_hilo emits
6138 a sequence to add a 32-bit offset using a scratch register. */
6141 load_got_offset (int dest
, expressionS
*local
)
6146 global
.X_add_number
= 0;
6148 relax_start (local
->X_add_symbol
);
6149 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6150 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6152 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6153 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6158 add_got_offset (int dest
, expressionS
*local
)
6162 global
.X_op
= O_constant
;
6163 global
.X_op_symbol
= NULL
;
6164 global
.X_add_symbol
= NULL
;
6165 global
.X_add_number
= local
->X_add_number
;
6167 relax_start (local
->X_add_symbol
);
6168 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6169 dest
, dest
, BFD_RELOC_LO16
);
6171 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6176 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6179 int hold_mips_optimize
;
6181 global
.X_op
= O_constant
;
6182 global
.X_op_symbol
= NULL
;
6183 global
.X_add_symbol
= NULL
;
6184 global
.X_add_number
= local
->X_add_number
;
6186 relax_start (local
->X_add_symbol
);
6187 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6189 /* Set mips_optimize around the lui instruction to avoid
6190 inserting an unnecessary nop after the lw. */
6191 hold_mips_optimize
= mips_optimize
;
6193 macro_build_lui (&global
, tmp
);
6194 mips_optimize
= hold_mips_optimize
;
6195 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6198 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6201 /* Emit a sequence of instructions to emulate a branch likely operation.
6202 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6203 is its complementing branch with the original condition negated.
6204 CALL is set if the original branch specified the link operation.
6205 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6207 Code like this is produced in the noreorder mode:
6212 delay slot (executed only if branch taken)
6220 delay slot (executed only if branch taken)
6223 In the reorder mode the delay slot would be filled with a nop anyway,
6224 so code produced is simply:
6229 This function is used when producing code for the microMIPS ASE that
6230 does not implement branch likely instructions in hardware. */
6233 macro_build_branch_likely (const char *br
, const char *brneg
,
6234 int call
, expressionS
*ep
, const char *fmt
,
6235 unsigned int sreg
, unsigned int treg
)
6237 int noreorder
= mips_opts
.noreorder
;
6240 gas_assert (mips_opts
.micromips
);
6244 micromips_label_expr (&expr1
);
6245 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6246 macro_build (NULL
, "nop", "");
6247 macro_build (ep
, call
? "bal" : "b", "p");
6249 /* Set to true so that append_insn adds a label. */
6250 emit_branch_likely_macro
= TRUE
;
6254 macro_build (ep
, br
, fmt
, sreg
, treg
);
6255 macro_build (NULL
, "nop", "");
6260 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6261 the condition code tested. EP specifies the branch target. */
6264 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6291 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6294 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6295 the register tested. EP specifies the branch target. */
6298 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6300 const char *brneg
= NULL
;
6310 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6314 gas_assert (mips_opts
.micromips
);
6323 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6330 br
= mips_opts
.micromips
? "blez" : "blezl";
6337 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6341 gas_assert (mips_opts
.micromips
);
6349 if (mips_opts
.micromips
&& brneg
)
6350 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6352 macro_build (ep
, br
, "s,p", sreg
);
6355 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6356 TREG as the registers tested. EP specifies the branch target. */
6359 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6360 unsigned int sreg
, unsigned int treg
)
6362 const char *brneg
= NULL
;
6374 br
= mips_opts
.micromips
? "beq" : "beql";
6383 br
= mips_opts
.micromips
? "bne" : "bnel";
6389 if (mips_opts
.micromips
&& brneg
)
6390 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6392 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6397 * This routine implements the seemingly endless macro or synthesized
6398 * instructions and addressing modes in the mips assembly language. Many
6399 * of these macros are simple and are similar to each other. These could
6400 * probably be handled by some kind of table or grammar approach instead of
6401 * this verbose method. Others are not simple macros but are more like
6402 * optimizing code generation.
6403 * One interesting optimization is when several store macros appear
6404 * consecutively that would load AT with the upper half of the same address.
6405 * The ensuing load upper instructions are ommited. This implies some kind
6406 * of global optimization. We currently only optimize within a single macro.
6407 * For many of the load and store macros if the address is specified as a
6408 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6409 * first load register 'at' with zero and use it as the base register. The
6410 * mips assembler simply uses register $zero. Just one tiny optimization
6414 macro (struct mips_cl_insn
*ip
)
6416 unsigned int treg
, sreg
, dreg
, breg
;
6417 unsigned int tempreg
;
6420 expressionS label_expr
;
6439 bfd_reloc_code_real_type r
;
6440 int hold_mips_optimize
;
6442 gas_assert (! mips_opts
.mips16
);
6444 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6445 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6446 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6447 mask
= ip
->insn_mo
->mask
;
6449 label_expr
.X_op
= O_constant
;
6450 label_expr
.X_op_symbol
= NULL
;
6451 label_expr
.X_add_symbol
= NULL
;
6452 label_expr
.X_add_number
= 0;
6454 expr1
.X_op
= O_constant
;
6455 expr1
.X_op_symbol
= NULL
;
6456 expr1
.X_add_symbol
= NULL
;
6457 expr1
.X_add_number
= 1;
6472 if (mips_opts
.micromips
)
6473 micromips_label_expr (&label_expr
);
6475 label_expr
.X_add_number
= 8;
6476 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6478 macro_build (NULL
, "nop", "");
6480 move_register (dreg
, sreg
);
6481 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6482 if (mips_opts
.micromips
)
6483 micromips_add_label ();
6500 if (!mips_opts
.micromips
)
6502 if (imm_expr
.X_op
== O_constant
6503 && imm_expr
.X_add_number
>= -0x200
6504 && imm_expr
.X_add_number
< 0x200)
6506 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6515 if (imm_expr
.X_op
== O_constant
6516 && imm_expr
.X_add_number
>= -0x8000
6517 && imm_expr
.X_add_number
< 0x8000)
6519 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6524 load_register (AT
, &imm_expr
, dbl
);
6525 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6544 if (imm_expr
.X_op
== O_constant
6545 && imm_expr
.X_add_number
>= 0
6546 && imm_expr
.X_add_number
< 0x10000)
6548 if (mask
!= M_NOR_I
)
6549 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6552 macro_build (&imm_expr
, "ori", "t,r,i",
6553 treg
, sreg
, BFD_RELOC_LO16
);
6554 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6560 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6561 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6565 switch (imm_expr
.X_add_number
)
6568 macro_build (NULL
, "nop", "");
6571 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6575 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6576 (int) imm_expr
.X_add_number
);
6579 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6580 (unsigned long) imm_expr
.X_add_number
);
6589 gas_assert (mips_opts
.micromips
);
6590 macro_build_branch_ccl (mask
, &offset_expr
,
6591 EXTRACT_OPERAND (1, BCC
, *ip
));
6598 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6604 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6609 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6616 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6618 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6622 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6623 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6624 &offset_expr
, AT
, ZERO
);
6634 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6640 /* Check for > max integer. */
6641 maxnum
= 0x7fffffff;
6642 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6649 if (imm_expr
.X_op
== O_constant
6650 && imm_expr
.X_add_number
>= maxnum
6651 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6654 /* Result is always false. */
6656 macro_build (NULL
, "nop", "");
6658 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6661 if (imm_expr
.X_op
!= O_constant
)
6662 as_bad (_("Unsupported large constant"));
6663 ++imm_expr
.X_add_number
;
6667 if (mask
== M_BGEL_I
)
6669 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6671 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
6672 &offset_expr
, sreg
);
6675 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6677 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
6678 &offset_expr
, sreg
);
6681 maxnum
= 0x7fffffff;
6682 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6689 maxnum
= - maxnum
- 1;
6690 if (imm_expr
.X_op
== O_constant
6691 && imm_expr
.X_add_number
<= maxnum
6692 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6695 /* result is always true */
6696 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
6697 macro_build (&offset_expr
, "b", "p");
6702 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6703 &offset_expr
, AT
, ZERO
);
6712 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6713 &offset_expr
, ZERO
, treg
);
6717 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6718 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6719 &offset_expr
, AT
, ZERO
);
6728 && imm_expr
.X_op
== O_constant
6729 && imm_expr
.X_add_number
== -1))
6731 if (imm_expr
.X_op
!= O_constant
)
6732 as_bad (_("Unsupported large constant"));
6733 ++imm_expr
.X_add_number
;
6737 if (mask
== M_BGEUL_I
)
6739 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6741 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6742 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6743 &offset_expr
, sreg
, ZERO
);
6748 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6749 &offset_expr
, AT
, ZERO
);
6757 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
6759 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
6763 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6764 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6765 &offset_expr
, AT
, ZERO
);
6773 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6774 &offset_expr
, sreg
, ZERO
);
6780 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6781 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6782 &offset_expr
, AT
, ZERO
);
6790 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6792 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
6796 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
6797 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6798 &offset_expr
, AT
, ZERO
);
6805 maxnum
= 0x7fffffff;
6806 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6813 if (imm_expr
.X_op
== O_constant
6814 && imm_expr
.X_add_number
>= maxnum
6815 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6817 if (imm_expr
.X_op
!= O_constant
)
6818 as_bad (_("Unsupported large constant"));
6819 ++imm_expr
.X_add_number
;
6823 if (mask
== M_BLTL_I
)
6825 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6826 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6827 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6828 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
6833 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6834 &offset_expr
, AT
, ZERO
);
6842 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6843 &offset_expr
, sreg
, ZERO
);
6849 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
6850 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6851 &offset_expr
, AT
, ZERO
);
6860 && imm_expr
.X_op
== O_constant
6861 && imm_expr
.X_add_number
== -1))
6863 if (imm_expr
.X_op
!= O_constant
)
6864 as_bad (_("Unsupported large constant"));
6865 ++imm_expr
.X_add_number
;
6869 if (mask
== M_BLTUL_I
)
6871 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6873 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
6874 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6875 &offset_expr
, sreg
, ZERO
);
6880 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6881 &offset_expr
, AT
, ZERO
);
6889 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
6891 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
6895 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6896 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6897 &offset_expr
, AT
, ZERO
);
6907 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6908 &offset_expr
, ZERO
, treg
);
6912 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
6913 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
6914 &offset_expr
, AT
, ZERO
);
6920 /* Use unsigned arithmetic. */
6924 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6926 as_bad (_("Unsupported large constant"));
6931 pos
= imm_expr
.X_add_number
;
6932 size
= imm2_expr
.X_add_number
;
6937 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6940 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6942 as_bad (_("Improper extract size (%lu, position %lu)"),
6943 (unsigned long) size
, (unsigned long) pos
);
6947 if (size
<= 32 && pos
< 32)
6952 else if (size
<= 32)
6962 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
6969 /* Use unsigned arithmetic. */
6973 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
6975 as_bad (_("Unsupported large constant"));
6980 pos
= imm_expr
.X_add_number
;
6981 size
= imm2_expr
.X_add_number
;
6986 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
6989 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
6991 as_bad (_("Improper insert size (%lu, position %lu)"),
6992 (unsigned long) size
, (unsigned long) pos
);
6996 if (pos
< 32 && (pos
+ size
- 1) < 32)
7011 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7012 (int) (pos
+ size
- 1));
7028 as_warn (_("Divide by zero."));
7030 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7032 macro_build (NULL
, "break", BRK_FMT
, 7);
7039 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7040 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7044 if (mips_opts
.micromips
)
7045 micromips_label_expr (&label_expr
);
7047 label_expr
.X_add_number
= 8;
7048 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7049 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7050 macro_build (NULL
, "break", BRK_FMT
, 7);
7051 if (mips_opts
.micromips
)
7052 micromips_add_label ();
7054 expr1
.X_add_number
= -1;
7056 load_register (AT
, &expr1
, dbl
);
7057 if (mips_opts
.micromips
)
7058 micromips_label_expr (&label_expr
);
7060 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7061 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7064 expr1
.X_add_number
= 1;
7065 load_register (AT
, &expr1
, dbl
);
7066 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7070 expr1
.X_add_number
= 0x80000000;
7071 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7075 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7076 /* We want to close the noreorder block as soon as possible, so
7077 that later insns are available for delay slot filling. */
7082 if (mips_opts
.micromips
)
7083 micromips_label_expr (&label_expr
);
7085 label_expr
.X_add_number
= 8;
7086 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7087 macro_build (NULL
, "nop", "");
7089 /* We want to close the noreorder block as soon as possible, so
7090 that later insns are available for delay slot filling. */
7093 macro_build (NULL
, "break", BRK_FMT
, 6);
7095 if (mips_opts
.micromips
)
7096 micromips_add_label ();
7097 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7136 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7138 as_warn (_("Divide by zero."));
7140 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7142 macro_build (NULL
, "break", BRK_FMT
, 7);
7145 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7147 if (strcmp (s2
, "mflo") == 0)
7148 move_register (dreg
, sreg
);
7150 move_register (dreg
, ZERO
);
7153 if (imm_expr
.X_op
== O_constant
7154 && imm_expr
.X_add_number
== -1
7155 && s
[strlen (s
) - 1] != 'u')
7157 if (strcmp (s2
, "mflo") == 0)
7159 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7162 move_register (dreg
, ZERO
);
7167 load_register (AT
, &imm_expr
, dbl
);
7168 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7169 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7191 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7192 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7193 /* We want to close the noreorder block as soon as possible, so
7194 that later insns are available for delay slot filling. */
7199 if (mips_opts
.micromips
)
7200 micromips_label_expr (&label_expr
);
7202 label_expr
.X_add_number
= 8;
7203 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7204 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7206 /* We want to close the noreorder block as soon as possible, so
7207 that later insns are available for delay slot filling. */
7209 macro_build (NULL
, "break", BRK_FMT
, 7);
7210 if (mips_opts
.micromips
)
7211 micromips_add_label ();
7213 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7225 /* Load the address of a symbol into a register. If breg is not
7226 zero, we then add a base register to it. */
7228 if (dbl
&& HAVE_32BIT_GPRS
)
7229 as_warn (_("dla used to load 32-bit register"));
7231 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7232 as_warn (_("la used to load 64-bit address"));
7234 if (offset_expr
.X_op
== O_constant
7235 && offset_expr
.X_add_number
>= -0x8000
7236 && offset_expr
.X_add_number
< 0x8000)
7238 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7239 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7243 if (mips_opts
.at
&& (treg
== breg
))
7253 if (offset_expr
.X_op
!= O_symbol
7254 && offset_expr
.X_op
!= O_constant
)
7256 as_bad (_("Expression too complex"));
7257 offset_expr
.X_op
= O_constant
;
7260 if (offset_expr
.X_op
== O_constant
)
7261 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7262 else if (mips_pic
== NO_PIC
)
7264 /* If this is a reference to a GP relative symbol, we want
7265 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7267 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7268 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7269 If we have a constant, we need two instructions anyhow,
7270 so we may as well always use the latter form.
7272 With 64bit address space and a usable $at we want
7273 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7274 lui $at,<sym> (BFD_RELOC_HI16_S)
7275 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7276 daddiu $at,<sym> (BFD_RELOC_LO16)
7278 daddu $tempreg,$tempreg,$at
7280 If $at is already in use, we use a path which is suboptimal
7281 on superscalar processors.
7282 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7283 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7285 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7287 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7289 For GP relative symbols in 64bit address space we can use
7290 the same sequence as in 32bit address space. */
7291 if (HAVE_64BIT_SYMBOLS
)
7293 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7294 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7296 relax_start (offset_expr
.X_add_symbol
);
7297 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7298 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7302 if (used_at
== 0 && mips_opts
.at
)
7304 macro_build (&offset_expr
, "lui", LUI_FMT
,
7305 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7306 macro_build (&offset_expr
, "lui", LUI_FMT
,
7307 AT
, BFD_RELOC_HI16_S
);
7308 macro_build (&offset_expr
, "daddiu", "t,r,j",
7309 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7310 macro_build (&offset_expr
, "daddiu", "t,r,j",
7311 AT
, AT
, BFD_RELOC_LO16
);
7312 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7313 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7318 macro_build (&offset_expr
, "lui", LUI_FMT
,
7319 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7320 macro_build (&offset_expr
, "daddiu", "t,r,j",
7321 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7322 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7323 macro_build (&offset_expr
, "daddiu", "t,r,j",
7324 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7325 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7326 macro_build (&offset_expr
, "daddiu", "t,r,j",
7327 tempreg
, tempreg
, BFD_RELOC_LO16
);
7330 if (mips_relax
.sequence
)
7335 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7336 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7338 relax_start (offset_expr
.X_add_symbol
);
7339 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7340 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7343 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7344 as_bad (_("Offset too large"));
7345 macro_build_lui (&offset_expr
, tempreg
);
7346 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7347 tempreg
, tempreg
, BFD_RELOC_LO16
);
7348 if (mips_relax
.sequence
)
7352 else if (!mips_big_got
&& !HAVE_NEWABI
)
7354 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7356 /* If this is a reference to an external symbol, and there
7357 is no constant, we want
7358 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7359 or for lca or if tempreg is PIC_CALL_REG
7360 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7361 For a local symbol, we want
7362 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7364 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7366 If we have a small constant, and this is a reference to
7367 an external symbol, we want
7368 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7370 addiu $tempreg,$tempreg,<constant>
7371 For a local symbol, we want the same instruction
7372 sequence, but we output a BFD_RELOC_LO16 reloc on the
7375 If we have a large constant, and this is a reference to
7376 an external symbol, we want
7377 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7378 lui $at,<hiconstant>
7379 addiu $at,$at,<loconstant>
7380 addu $tempreg,$tempreg,$at
7381 For a local symbol, we want the same instruction
7382 sequence, but we output a BFD_RELOC_LO16 reloc on the
7386 if (offset_expr
.X_add_number
== 0)
7388 if (mips_pic
== SVR4_PIC
7390 && (call
|| tempreg
== PIC_CALL_REG
))
7391 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7393 relax_start (offset_expr
.X_add_symbol
);
7394 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7395 lw_reloc_type
, mips_gp_register
);
7398 /* We're going to put in an addu instruction using
7399 tempreg, so we may as well insert the nop right
7404 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7405 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7407 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7408 tempreg
, tempreg
, BFD_RELOC_LO16
);
7410 /* FIXME: If breg == 0, and the next instruction uses
7411 $tempreg, then if this variant case is used an extra
7412 nop will be generated. */
7414 else if (offset_expr
.X_add_number
>= -0x8000
7415 && offset_expr
.X_add_number
< 0x8000)
7417 load_got_offset (tempreg
, &offset_expr
);
7419 add_got_offset (tempreg
, &offset_expr
);
7423 expr1
.X_add_number
= offset_expr
.X_add_number
;
7424 offset_expr
.X_add_number
=
7425 SEXT_16BIT (offset_expr
.X_add_number
);
7426 load_got_offset (tempreg
, &offset_expr
);
7427 offset_expr
.X_add_number
= expr1
.X_add_number
;
7428 /* If we are going to add in a base register, and the
7429 target register and the base register are the same,
7430 then we are using AT as a temporary register. Since
7431 we want to load the constant into AT, we add our
7432 current AT (from the global offset table) and the
7433 register into the register now, and pretend we were
7434 not using a base register. */
7438 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7443 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7447 else if (!mips_big_got
&& HAVE_NEWABI
)
7449 int add_breg_early
= 0;
7451 /* If this is a reference to an external, and there is no
7452 constant, or local symbol (*), with or without a
7454 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7455 or for lca or if tempreg is PIC_CALL_REG
7456 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7458 If we have a small constant, and this is a reference to
7459 an external symbol, we want
7460 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7461 addiu $tempreg,$tempreg,<constant>
7463 If we have a large constant, and this is a reference to
7464 an external symbol, we want
7465 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7466 lui $at,<hiconstant>
7467 addiu $at,$at,<loconstant>
7468 addu $tempreg,$tempreg,$at
7470 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7471 local symbols, even though it introduces an additional
7474 if (offset_expr
.X_add_number
)
7476 expr1
.X_add_number
= offset_expr
.X_add_number
;
7477 offset_expr
.X_add_number
= 0;
7479 relax_start (offset_expr
.X_add_symbol
);
7480 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7481 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7483 if (expr1
.X_add_number
>= -0x8000
7484 && expr1
.X_add_number
< 0x8000)
7486 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7487 tempreg
, tempreg
, BFD_RELOC_LO16
);
7489 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7491 /* If we are going to add in a base register, and the
7492 target register and the base register are the same,
7493 then we are using AT as a temporary register. Since
7494 we want to load the constant into AT, we add our
7495 current AT (from the global offset table) and the
7496 register into the register now, and pretend we were
7497 not using a base register. */
7502 gas_assert (tempreg
== AT
);
7503 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7509 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7516 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7519 offset_expr
.X_add_number
= expr1
.X_add_number
;
7521 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7522 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7526 treg
, tempreg
, breg
);
7532 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7534 relax_start (offset_expr
.X_add_symbol
);
7535 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7536 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7538 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7539 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7544 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7545 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7548 else if (mips_big_got
&& !HAVE_NEWABI
)
7551 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7552 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7553 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7555 /* This is the large GOT case. If this is a reference to an
7556 external symbol, and there is no constant, we want
7557 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7558 addu $tempreg,$tempreg,$gp
7559 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7560 or for lca or if tempreg is PIC_CALL_REG
7561 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7562 addu $tempreg,$tempreg,$gp
7563 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7564 For a local symbol, we want
7565 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7567 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7569 If we have a small constant, and this is a reference to
7570 an external symbol, we want
7571 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7572 addu $tempreg,$tempreg,$gp
7573 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7575 addiu $tempreg,$tempreg,<constant>
7576 For a local symbol, we want
7577 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7579 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7581 If we have a large constant, and this is a reference to
7582 an external symbol, we want
7583 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7584 addu $tempreg,$tempreg,$gp
7585 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7586 lui $at,<hiconstant>
7587 addiu $at,$at,<loconstant>
7588 addu $tempreg,$tempreg,$at
7589 For a local symbol, we want
7590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7591 lui $at,<hiconstant>
7592 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7593 addu $tempreg,$tempreg,$at
7596 expr1
.X_add_number
= offset_expr
.X_add_number
;
7597 offset_expr
.X_add_number
= 0;
7598 relax_start (offset_expr
.X_add_symbol
);
7599 gpdelay
= reg_needs_delay (mips_gp_register
);
7600 if (expr1
.X_add_number
== 0 && breg
== 0
7601 && (call
|| tempreg
== PIC_CALL_REG
))
7603 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7604 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7606 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7607 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7608 tempreg
, tempreg
, mips_gp_register
);
7609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7610 tempreg
, lw_reloc_type
, tempreg
);
7611 if (expr1
.X_add_number
== 0)
7615 /* We're going to put in an addu instruction using
7616 tempreg, so we may as well insert the nop right
7621 else if (expr1
.X_add_number
>= -0x8000
7622 && expr1
.X_add_number
< 0x8000)
7625 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7626 tempreg
, tempreg
, BFD_RELOC_LO16
);
7630 /* If we are going to add in a base register, and the
7631 target register and the base register are the same,
7632 then we are using AT as a temporary register. Since
7633 we want to load the constant into AT, we add our
7634 current AT (from the global offset table) and the
7635 register into the register now, and pretend we were
7636 not using a base register. */
7641 gas_assert (tempreg
== AT
);
7643 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7648 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7649 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7653 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7658 /* This is needed because this instruction uses $gp, but
7659 the first instruction on the main stream does not. */
7660 macro_build (NULL
, "nop", "");
7663 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7664 local_reloc_type
, mips_gp_register
);
7665 if (expr1
.X_add_number
>= -0x8000
7666 && expr1
.X_add_number
< 0x8000)
7669 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7670 tempreg
, tempreg
, BFD_RELOC_LO16
);
7671 /* FIXME: If add_number is 0, and there was no base
7672 register, the external symbol case ended with a load,
7673 so if the symbol turns out to not be external, and
7674 the next instruction uses tempreg, an unnecessary nop
7675 will be inserted. */
7681 /* We must add in the base register now, as in the
7682 external symbol case. */
7683 gas_assert (tempreg
== AT
);
7685 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7688 /* We set breg to 0 because we have arranged to add
7689 it in in both cases. */
7693 macro_build_lui (&expr1
, AT
);
7694 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7695 AT
, AT
, BFD_RELOC_LO16
);
7696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7697 tempreg
, tempreg
, AT
);
7702 else if (mips_big_got
&& HAVE_NEWABI
)
7704 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7705 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7706 int add_breg_early
= 0;
7708 /* This is the large GOT case. If this is a reference to an
7709 external symbol, and there is no constant, we want
7710 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7711 add $tempreg,$tempreg,$gp
7712 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7713 or for lca or if tempreg is PIC_CALL_REG
7714 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7715 add $tempreg,$tempreg,$gp
7716 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7718 If we have a small constant, and this is a reference to
7719 an external symbol, we want
7720 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7721 add $tempreg,$tempreg,$gp
7722 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7723 addi $tempreg,$tempreg,<constant>
7725 If we have a large constant, and this is a reference to
7726 an external symbol, we want
7727 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7728 addu $tempreg,$tempreg,$gp
7729 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7730 lui $at,<hiconstant>
7731 addi $at,$at,<loconstant>
7732 add $tempreg,$tempreg,$at
7734 If we have NewABI, and we know it's a local symbol, we want
7735 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7736 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7737 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7739 relax_start (offset_expr
.X_add_symbol
);
7741 expr1
.X_add_number
= offset_expr
.X_add_number
;
7742 offset_expr
.X_add_number
= 0;
7744 if (expr1
.X_add_number
== 0 && breg
== 0
7745 && (call
|| tempreg
== PIC_CALL_REG
))
7747 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7748 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7750 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7751 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7752 tempreg
, tempreg
, mips_gp_register
);
7753 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7754 tempreg
, lw_reloc_type
, tempreg
);
7756 if (expr1
.X_add_number
== 0)
7758 else if (expr1
.X_add_number
>= -0x8000
7759 && expr1
.X_add_number
< 0x8000)
7761 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7762 tempreg
, tempreg
, BFD_RELOC_LO16
);
7764 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7766 /* If we are going to add in a base register, and the
7767 target register and the base register are the same,
7768 then we are using AT as a temporary register. Since
7769 we want to load the constant into AT, we add our
7770 current AT (from the global offset table) and the
7771 register into the register now, and pretend we were
7772 not using a base register. */
7777 gas_assert (tempreg
== AT
);
7778 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7784 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7785 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7790 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7793 offset_expr
.X_add_number
= expr1
.X_add_number
;
7794 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7795 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7796 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
7797 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
7800 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7801 treg
, tempreg
, breg
);
7811 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
7815 gas_assert (!mips_opts
.micromips
);
7817 unsigned long temp
= (treg
<< 16) | (0x01);
7818 macro_build (NULL
, "c2", "C", temp
);
7823 gas_assert (!mips_opts
.micromips
);
7825 unsigned long temp
= (0x02);
7826 macro_build (NULL
, "c2", "C", temp
);
7831 gas_assert (!mips_opts
.micromips
);
7833 unsigned long temp
= (treg
<< 16) | (0x02);
7834 macro_build (NULL
, "c2", "C", temp
);
7839 gas_assert (!mips_opts
.micromips
);
7840 macro_build (NULL
, "c2", "C", 3);
7844 gas_assert (!mips_opts
.micromips
);
7846 unsigned long temp
= (treg
<< 16) | 0x03;
7847 macro_build (NULL
, "c2", "C", temp
);
7852 /* The j instruction may not be used in PIC code, since it
7853 requires an absolute address. We convert it to a b
7855 if (mips_pic
== NO_PIC
)
7856 macro_build (&offset_expr
, "j", "a");
7858 macro_build (&offset_expr
, "b", "p");
7861 /* The jal instructions must be handled as macros because when
7862 generating PIC code they expand to multi-instruction
7863 sequences. Normally they are simple instructions. */
7868 gas_assert (mips_opts
.micromips
);
7876 if (mips_pic
== NO_PIC
)
7878 s
= jals
? "jalrs" : "jalr";
7879 if (mips_opts
.micromips
7881 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7882 macro_build (NULL
, s
, "mj", sreg
);
7884 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7888 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
7889 && mips_cprestore_offset
>= 0);
7891 if (sreg
!= PIC_CALL_REG
)
7892 as_warn (_("MIPS PIC call to register other than $25"));
7894 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
7895 ? "jalrs" : "jalr");
7896 if (mips_opts
.micromips
7898 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7899 macro_build (NULL
, s
, "mj", sreg
);
7901 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
7902 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
7904 if (mips_cprestore_offset
< 0)
7905 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7908 if (!mips_frame_reg_valid
)
7910 as_warn (_("No .frame pseudo-op used in PIC code"));
7911 /* Quiet this warning. */
7912 mips_frame_reg_valid
= 1;
7914 if (!mips_cprestore_valid
)
7916 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7917 /* Quiet this warning. */
7918 mips_cprestore_valid
= 1;
7920 if (mips_opts
.noreorder
)
7921 macro_build (NULL
, "nop", "");
7922 expr1
.X_add_number
= mips_cprestore_offset
;
7923 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
7926 HAVE_64BIT_ADDRESSES
);
7934 gas_assert (mips_opts
.micromips
);
7938 if (mips_pic
== NO_PIC
)
7939 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
7940 else if (mips_pic
== SVR4_PIC
)
7942 /* If this is a reference to an external symbol, and we are
7943 using a small GOT, we want
7944 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7948 lw $gp,cprestore($sp)
7949 The cprestore value is set using the .cprestore
7950 pseudo-op. If we are using a big GOT, we want
7951 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7953 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7957 lw $gp,cprestore($sp)
7958 If the symbol is not external, we want
7959 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7961 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7964 lw $gp,cprestore($sp)
7966 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7967 sequences above, minus nops, unless the symbol is local,
7968 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7974 relax_start (offset_expr
.X_add_symbol
);
7975 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7976 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
7979 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7980 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
7986 relax_start (offset_expr
.X_add_symbol
);
7987 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
7988 BFD_RELOC_MIPS_CALL_HI16
);
7989 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
7990 PIC_CALL_REG
, mips_gp_register
);
7991 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7992 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
7995 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7996 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
7998 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7999 PIC_CALL_REG
, PIC_CALL_REG
,
8000 BFD_RELOC_MIPS_GOT_OFST
);
8004 macro_build_jalr (&offset_expr
, 0);
8008 relax_start (offset_expr
.X_add_symbol
);
8011 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8012 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8021 gpdelay
= reg_needs_delay (mips_gp_register
);
8022 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8023 BFD_RELOC_MIPS_CALL_HI16
);
8024 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8025 PIC_CALL_REG
, mips_gp_register
);
8026 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8027 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8032 macro_build (NULL
, "nop", "");
8034 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8035 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8038 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8039 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8041 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8043 if (mips_cprestore_offset
< 0)
8044 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8047 if (!mips_frame_reg_valid
)
8049 as_warn (_("No .frame pseudo-op used in PIC code"));
8050 /* Quiet this warning. */
8051 mips_frame_reg_valid
= 1;
8053 if (!mips_cprestore_valid
)
8055 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8056 /* Quiet this warning. */
8057 mips_cprestore_valid
= 1;
8059 if (mips_opts
.noreorder
)
8060 macro_build (NULL
, "nop", "");
8061 expr1
.X_add_number
= mips_cprestore_offset
;
8062 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8065 HAVE_64BIT_ADDRESSES
);
8069 else if (mips_pic
== VXWORKS_PIC
)
8070 as_bad (_("Non-PIC jump used in PIC library"));
8080 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8088 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8119 gas_assert (!mips_opts
.micromips
);
8122 /* Itbl support may require additional care here. */
8129 /* Itbl support may require additional care here. */
8137 off12
= mips_opts
.micromips
;
8138 /* Itbl support may require additional care here. */
8143 gas_assert (!mips_opts
.micromips
);
8146 /* Itbl support may require additional care here. */
8154 off12
= mips_opts
.micromips
;
8161 off12
= mips_opts
.micromips
;
8167 /* Itbl support may require additional care here. */
8175 off12
= mips_opts
.micromips
;
8176 /* Itbl support may require additional care here. */
8183 /* Itbl support may require additional care here. */
8191 off12
= mips_opts
.micromips
;
8198 off12
= mips_opts
.micromips
;
8205 off12
= mips_opts
.micromips
;
8212 off12
= mips_opts
.micromips
;
8219 off12
= mips_opts
.micromips
;
8224 gas_assert (mips_opts
.micromips
);
8233 gas_assert (mips_opts
.micromips
);
8242 gas_assert (mips_opts
.micromips
);
8250 gas_assert (mips_opts
.micromips
);
8257 if (breg
== treg
+ lp
)
8260 tempreg
= treg
+ lp
;
8280 gas_assert (!mips_opts
.micromips
);
8283 /* Itbl support may require additional care here. */
8290 /* Itbl support may require additional care here. */
8298 off12
= mips_opts
.micromips
;
8299 /* Itbl support may require additional care here. */
8304 gas_assert (!mips_opts
.micromips
);
8307 /* Itbl support may require additional care here. */
8315 off12
= mips_opts
.micromips
;
8322 off12
= mips_opts
.micromips
;
8329 off12
= mips_opts
.micromips
;
8336 off12
= mips_opts
.micromips
;
8342 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8343 off12
= mips_opts
.micromips
;
8349 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8350 off12
= mips_opts
.micromips
;
8357 /* Itbl support may require additional care here. */
8364 off12
= mips_opts
.micromips
;
8365 /* Itbl support may require additional care here. */
8370 gas_assert (!mips_opts
.micromips
);
8373 /* Itbl support may require additional care here. */
8381 off12
= mips_opts
.micromips
;
8388 off12
= mips_opts
.micromips
;
8393 gas_assert (mips_opts
.micromips
);
8401 gas_assert (mips_opts
.micromips
);
8409 gas_assert (mips_opts
.micromips
);
8417 gas_assert (mips_opts
.micromips
);
8426 if (offset_expr
.X_op
!= O_constant
8427 && offset_expr
.X_op
!= O_symbol
)
8429 as_bad (_("Expression too complex"));
8430 offset_expr
.X_op
= O_constant
;
8433 if (HAVE_32BIT_ADDRESSES
8434 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8438 sprintf_vma (value
, offset_expr
.X_add_number
);
8439 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8442 /* A constant expression in PIC code can be handled just as it
8443 is in non PIC code. */
8444 if (offset_expr
.X_op
== O_constant
)
8448 expr1
.X_add_number
= offset_expr
.X_add_number
;
8449 normalize_address_expr (&expr1
);
8450 if (!off12
&& !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8452 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8453 & ~(bfd_vma
) 0xffff);
8456 else if (off12
&& !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8458 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8459 & ~(bfd_vma
) 0xfff);
8464 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8466 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8467 tempreg
, tempreg
, breg
);
8472 if (offset_expr
.X_add_number
== 0)
8475 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8476 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8477 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8480 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8482 macro_build (NULL
, s
, fmt
,
8483 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8485 else if (off12
|| off0
)
8487 /* A 12-bit or 0-bit offset field is too narrow to be used
8488 for a low-part relocation, so load the whole address into
8489 the auxillary register. In the case of "A(b)" addresses,
8490 we first load absolute address "A" into the register and
8491 then add base register "b". In the case of "o(b)" addresses,
8492 we simply need to add 16-bit offset "o" to base register "b", and
8493 offset_reloc already contains the relocations associated
8497 load_address (tempreg
, &offset_expr
, &used_at
);
8499 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8500 tempreg
, tempreg
, breg
);
8503 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8505 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8506 expr1
.X_add_number
= 0;
8508 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8510 macro_build (NULL
, s
, fmt
,
8511 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8513 else if (mips_pic
== NO_PIC
)
8515 /* If this is a reference to a GP relative symbol, and there
8516 is no base register, we want
8517 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8518 Otherwise, if there is no base register, we want
8519 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8520 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8521 If we have a constant, we need two instructions anyhow,
8522 so we always use the latter form.
8524 If we have a base register, and this is a reference to a
8525 GP relative symbol, we want
8526 addu $tempreg,$breg,$gp
8527 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8529 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8530 addu $tempreg,$tempreg,$breg
8531 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8532 With a constant we always use the latter case.
8534 With 64bit address space and no base register and $at usable,
8536 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8537 lui $at,<sym> (BFD_RELOC_HI16_S)
8538 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8541 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8542 If we have a base register, we want
8543 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8544 lui $at,<sym> (BFD_RELOC_HI16_S)
8545 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8549 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8551 Without $at we can't generate the optimal path for superscalar
8552 processors here since this would require two temporary registers.
8553 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8554 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8556 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8558 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8559 If we have a base register, we want
8560 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8561 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8563 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8565 daddu $tempreg,$tempreg,$breg
8566 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8568 For GP relative symbols in 64bit address space we can use
8569 the same sequence as in 32bit address space. */
8570 if (HAVE_64BIT_SYMBOLS
)
8572 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8573 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8575 relax_start (offset_expr
.X_add_symbol
);
8578 macro_build (&offset_expr
, s
, fmt
, treg
,
8579 BFD_RELOC_GPREL16
, mips_gp_register
);
8583 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8584 tempreg
, breg
, mips_gp_register
);
8585 macro_build (&offset_expr
, s
, fmt
, treg
,
8586 BFD_RELOC_GPREL16
, tempreg
);
8591 if (used_at
== 0 && mips_opts
.at
)
8593 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8594 BFD_RELOC_MIPS_HIGHEST
);
8595 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
8597 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8598 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8600 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
8601 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
8602 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
8603 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
8609 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8610 BFD_RELOC_MIPS_HIGHEST
);
8611 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8612 tempreg
, BFD_RELOC_MIPS_HIGHER
);
8613 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8614 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
8615 tempreg
, BFD_RELOC_HI16_S
);
8616 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
8618 macro_build (NULL
, "daddu", "d,v,t",
8619 tempreg
, tempreg
, breg
);
8620 macro_build (&offset_expr
, s
, fmt
, treg
,
8621 BFD_RELOC_LO16
, tempreg
);
8624 if (mips_relax
.sequence
)
8631 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8632 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8634 relax_start (offset_expr
.X_add_symbol
);
8635 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
8639 macro_build_lui (&offset_expr
, tempreg
);
8640 macro_build (&offset_expr
, s
, fmt
, treg
,
8641 BFD_RELOC_LO16
, tempreg
);
8642 if (mips_relax
.sequence
)
8647 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
8648 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
8650 relax_start (offset_expr
.X_add_symbol
);
8651 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8652 tempreg
, breg
, mips_gp_register
);
8653 macro_build (&offset_expr
, s
, fmt
, treg
,
8654 BFD_RELOC_GPREL16
, tempreg
);
8657 macro_build_lui (&offset_expr
, tempreg
);
8658 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8659 tempreg
, tempreg
, breg
);
8660 macro_build (&offset_expr
, s
, fmt
, treg
,
8661 BFD_RELOC_LO16
, tempreg
);
8662 if (mips_relax
.sequence
)
8666 else if (!mips_big_got
)
8668 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
8670 /* If this is a reference to an external symbol, we want
8671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8673 <op> $treg,0($tempreg)
8675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8677 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8678 <op> $treg,0($tempreg)
8681 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8682 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8684 If there is a base register, we add it to $tempreg before
8685 the <op>. If there is a constant, we stick it in the
8686 <op> instruction. We don't handle constants larger than
8687 16 bits, because we have no way to load the upper 16 bits
8688 (actually, we could handle them for the subset of cases
8689 in which we are not using $at). */
8690 gas_assert (offset_expr
.X_op
== O_symbol
);
8693 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8694 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8697 tempreg
, tempreg
, breg
);
8698 macro_build (&offset_expr
, s
, fmt
, treg
,
8699 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8702 expr1
.X_add_number
= offset_expr
.X_add_number
;
8703 offset_expr
.X_add_number
= 0;
8704 if (expr1
.X_add_number
< -0x8000
8705 || expr1
.X_add_number
>= 0x8000)
8706 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8707 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8708 lw_reloc_type
, mips_gp_register
);
8710 relax_start (offset_expr
.X_add_symbol
);
8712 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8713 tempreg
, BFD_RELOC_LO16
);
8716 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8717 tempreg
, tempreg
, breg
);
8718 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8720 else if (mips_big_got
&& !HAVE_NEWABI
)
8724 /* If this is a reference to an external symbol, we want
8725 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8726 addu $tempreg,$tempreg,$gp
8727 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8728 <op> $treg,0($tempreg)
8730 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8732 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8733 <op> $treg,0($tempreg)
8734 If there is a base register, we add it to $tempreg before
8735 the <op>. If there is a constant, we stick it in the
8736 <op> instruction. We don't handle constants larger than
8737 16 bits, because we have no way to load the upper 16 bits
8738 (actually, we could handle them for the subset of cases
8739 in which we are not using $at). */
8740 gas_assert (offset_expr
.X_op
== O_symbol
);
8741 expr1
.X_add_number
= offset_expr
.X_add_number
;
8742 offset_expr
.X_add_number
= 0;
8743 if (expr1
.X_add_number
< -0x8000
8744 || expr1
.X_add_number
>= 0x8000)
8745 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8746 gpdelay
= reg_needs_delay (mips_gp_register
);
8747 relax_start (offset_expr
.X_add_symbol
);
8748 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8749 BFD_RELOC_MIPS_GOT_HI16
);
8750 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8752 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8753 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8756 macro_build (NULL
, "nop", "");
8757 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8758 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8760 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8761 tempreg
, BFD_RELOC_LO16
);
8765 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8766 tempreg
, tempreg
, breg
);
8767 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8769 else if (mips_big_got
&& HAVE_NEWABI
)
8771 /* If this is a reference to an external symbol, we want
8772 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8773 add $tempreg,$tempreg,$gp
8774 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8775 <op> $treg,<ofst>($tempreg)
8776 Otherwise, for local symbols, we want:
8777 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8778 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8779 gas_assert (offset_expr
.X_op
== O_symbol
);
8780 expr1
.X_add_number
= offset_expr
.X_add_number
;
8781 offset_expr
.X_add_number
= 0;
8782 if (expr1
.X_add_number
< -0x8000
8783 || expr1
.X_add_number
>= 0x8000)
8784 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8785 relax_start (offset_expr
.X_add_symbol
);
8786 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
8787 BFD_RELOC_MIPS_GOT_HI16
);
8788 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
8790 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8791 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
8793 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8794 tempreg
, tempreg
, breg
);
8795 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
8798 offset_expr
.X_add_number
= expr1
.X_add_number
;
8799 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8800 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8802 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8803 tempreg
, tempreg
, breg
);
8804 macro_build (&offset_expr
, s
, fmt
, treg
,
8805 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
8815 load_register (treg
, &imm_expr
, 0);
8819 load_register (treg
, &imm_expr
, 1);
8823 if (imm_expr
.X_op
== O_constant
)
8826 load_register (AT
, &imm_expr
, 0);
8827 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8832 gas_assert (offset_expr
.X_op
== O_symbol
8833 && strcmp (segment_name (S_GET_SEGMENT
8834 (offset_expr
.X_add_symbol
)),
8836 && offset_expr
.X_add_number
== 0);
8837 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
8838 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8843 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8844 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8845 order 32 bits of the value and the low order 32 bits are either
8846 zero or in OFFSET_EXPR. */
8847 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8849 if (HAVE_64BIT_GPRS
)
8850 load_register (treg
, &imm_expr
, 1);
8855 if (target_big_endian
)
8867 load_register (hreg
, &imm_expr
, 0);
8870 if (offset_expr
.X_op
== O_absent
)
8871 move_register (lreg
, 0);
8874 gas_assert (offset_expr
.X_op
== O_constant
);
8875 load_register (lreg
, &offset_expr
, 0);
8882 /* We know that sym is in the .rdata section. First we get the
8883 upper 16 bits of the address. */
8884 if (mips_pic
== NO_PIC
)
8886 macro_build_lui (&offset_expr
, AT
);
8891 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8892 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8896 /* Now we load the register(s). */
8897 if (HAVE_64BIT_GPRS
)
8900 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8905 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8908 /* FIXME: How in the world do we deal with the possible
8910 offset_expr
.X_add_number
+= 4;
8911 macro_build (&offset_expr
, "lw", "t,o(b)",
8912 treg
+ 1, BFD_RELOC_LO16
, AT
);
8918 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8919 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8920 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8921 the value and the low order 32 bits are either zero or in
8923 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
8926 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
8927 if (HAVE_64BIT_FPRS
)
8929 gas_assert (HAVE_64BIT_GPRS
);
8930 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
8934 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
8935 if (offset_expr
.X_op
== O_absent
)
8936 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
8939 gas_assert (offset_expr
.X_op
== O_constant
);
8940 load_register (AT
, &offset_expr
, 0);
8941 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
8947 gas_assert (offset_expr
.X_op
== O_symbol
8948 && offset_expr
.X_add_number
== 0);
8949 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
8950 if (strcmp (s
, ".lit8") == 0)
8952 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
8954 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
8955 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
8958 breg
= mips_gp_register
;
8959 r
= BFD_RELOC_MIPS_LITERAL
;
8964 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
8966 if (mips_pic
!= NO_PIC
)
8967 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
8968 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8971 /* FIXME: This won't work for a 64 bit address. */
8972 macro_build_lui (&offset_expr
, AT
);
8975 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
8977 macro_build (&offset_expr
, "ldc1", "T,o(b)",
8978 treg
, BFD_RELOC_LO16
, AT
);
8987 /* Even on a big endian machine $fn comes before $fn+1. We have
8988 to adjust when loading from memory. */
8991 gas_assert (!mips_opts
.micromips
);
8992 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
8993 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8994 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
8995 /* FIXME: A possible overflow which I don't know how to deal
8997 offset_expr
.X_add_number
+= 4;
8998 macro_build (&offset_expr
, "lwc1", "T,o(b)",
8999 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9003 gas_assert (!mips_opts
.micromips
);
9004 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9005 /* Even on a big endian machine $fn comes before $fn+1. We have
9006 to adjust when storing to memory. */
9007 macro_build (&offset_expr
, "swc1", "T,o(b)",
9008 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9009 offset_expr
.X_add_number
+= 4;
9010 macro_build (&offset_expr
, "swc1", "T,o(b)",
9011 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9015 gas_assert (!mips_opts
.micromips
);
9017 * The MIPS assembler seems to check for X_add_number not
9018 * being double aligned and generating:
9021 * addiu at,at,%lo(foo+1)
9024 * But, the resulting address is the same after relocation so why
9025 * generate the extra instruction?
9027 /* Itbl support may require additional care here. */
9030 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9039 gas_assert (!mips_opts
.micromips
);
9040 /* Itbl support may require additional care here. */
9043 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9063 if (HAVE_64BIT_GPRS
)
9073 if (HAVE_64BIT_GPRS
)
9081 if (offset_expr
.X_op
!= O_symbol
9082 && offset_expr
.X_op
!= O_constant
)
9084 as_bad (_("Expression too complex"));
9085 offset_expr
.X_op
= O_constant
;
9088 if (HAVE_32BIT_ADDRESSES
9089 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9093 sprintf_vma (value
, offset_expr
.X_add_number
);
9094 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9097 /* Even on a big endian machine $fn comes before $fn+1. We have
9098 to adjust when loading from memory. We set coproc if we must
9099 load $fn+1 first. */
9100 /* Itbl support may require additional care here. */
9101 if (!target_big_endian
)
9104 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9106 /* If this is a reference to a GP relative symbol, we want
9107 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9108 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9109 If we have a base register, we use this
9111 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9112 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9113 If this is not a GP relative symbol, we want
9114 lui $at,<sym> (BFD_RELOC_HI16_S)
9115 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9116 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9117 If there is a base register, we add it to $at after the
9118 lui instruction. If there is a constant, we always use
9120 if (offset_expr
.X_op
== O_symbol
9121 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9122 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9124 relax_start (offset_expr
.X_add_symbol
);
9127 tempreg
= mips_gp_register
;
9131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9132 AT
, breg
, mips_gp_register
);
9137 /* Itbl support may require additional care here. */
9138 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9139 BFD_RELOC_GPREL16
, tempreg
);
9140 offset_expr
.X_add_number
+= 4;
9142 /* Set mips_optimize to 2 to avoid inserting an
9144 hold_mips_optimize
= mips_optimize
;
9146 /* Itbl support may require additional care here. */
9147 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9148 BFD_RELOC_GPREL16
, tempreg
);
9149 mips_optimize
= hold_mips_optimize
;
9153 offset_expr
.X_add_number
-= 4;
9156 macro_build_lui (&offset_expr
, AT
);
9158 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9159 /* Itbl support may require additional care here. */
9160 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9161 BFD_RELOC_LO16
, AT
);
9162 /* FIXME: How do we handle overflow here? */
9163 offset_expr
.X_add_number
+= 4;
9164 /* Itbl support may require additional care here. */
9165 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9166 BFD_RELOC_LO16
, AT
);
9167 if (mips_relax
.sequence
)
9170 else if (!mips_big_got
)
9172 /* If this is a reference to an external symbol, we want
9173 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9178 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9180 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9181 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9182 If there is a base register we add it to $at before the
9183 lwc1 instructions. If there is a constant we include it
9184 in the lwc1 instructions. */
9186 expr1
.X_add_number
= offset_expr
.X_add_number
;
9187 if (expr1
.X_add_number
< -0x8000
9188 || expr1
.X_add_number
>= 0x8000 - 4)
9189 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9190 load_got_offset (AT
, &offset_expr
);
9193 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9195 /* Set mips_optimize to 2 to avoid inserting an undesired
9197 hold_mips_optimize
= mips_optimize
;
9200 /* Itbl support may require additional care here. */
9201 relax_start (offset_expr
.X_add_symbol
);
9202 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9203 BFD_RELOC_LO16
, AT
);
9204 expr1
.X_add_number
+= 4;
9205 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9206 BFD_RELOC_LO16
, AT
);
9208 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9209 BFD_RELOC_LO16
, AT
);
9210 offset_expr
.X_add_number
+= 4;
9211 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9212 BFD_RELOC_LO16
, AT
);
9215 mips_optimize
= hold_mips_optimize
;
9217 else if (mips_big_got
)
9221 /* If this is a reference to an external symbol, we want
9222 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9224 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9229 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9231 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9232 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9233 If there is a base register we add it to $at before the
9234 lwc1 instructions. If there is a constant we include it
9235 in the lwc1 instructions. */
9237 expr1
.X_add_number
= offset_expr
.X_add_number
;
9238 offset_expr
.X_add_number
= 0;
9239 if (expr1
.X_add_number
< -0x8000
9240 || expr1
.X_add_number
>= 0x8000 - 4)
9241 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9242 gpdelay
= reg_needs_delay (mips_gp_register
);
9243 relax_start (offset_expr
.X_add_symbol
);
9244 macro_build (&offset_expr
, "lui", LUI_FMT
,
9245 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9247 AT
, AT
, mips_gp_register
);
9248 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9249 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9252 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9253 /* Itbl support may require additional care here. */
9254 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9255 BFD_RELOC_LO16
, AT
);
9256 expr1
.X_add_number
+= 4;
9258 /* Set mips_optimize to 2 to avoid inserting an undesired
9260 hold_mips_optimize
= mips_optimize
;
9262 /* Itbl support may require additional care here. */
9263 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9264 BFD_RELOC_LO16
, AT
);
9265 mips_optimize
= hold_mips_optimize
;
9266 expr1
.X_add_number
-= 4;
9269 offset_expr
.X_add_number
= expr1
.X_add_number
;
9271 macro_build (NULL
, "nop", "");
9272 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9273 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9276 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9277 /* Itbl support may require additional care here. */
9278 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9279 BFD_RELOC_LO16
, AT
);
9280 offset_expr
.X_add_number
+= 4;
9282 /* Set mips_optimize to 2 to avoid inserting an undesired
9284 hold_mips_optimize
= mips_optimize
;
9286 /* Itbl support may require additional care here. */
9287 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9288 BFD_RELOC_LO16
, AT
);
9289 mips_optimize
= hold_mips_optimize
;
9298 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9301 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9303 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9304 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9306 if (!HAVE_64BIT_GPRS
)
9308 offset_expr
.X_add_number
+= 4;
9309 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9310 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9331 /* New code added to support COPZ instructions.
9332 This code builds table entries out of the macros in mip_opcodes.
9333 R4000 uses interlocks to handle coproc delays.
9334 Other chips (like the R3000) require nops to be inserted for delays.
9336 FIXME: Currently, we require that the user handle delays.
9337 In order to fill delay slots for non-interlocked chips,
9338 we must have a way to specify delays based on the coprocessor.
9339 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9340 What are the side-effects of the cop instruction?
9341 What cache support might we have and what are its effects?
9342 Both coprocessor & memory require delays. how long???
9343 What registers are read/set/modified?
9345 If an itbl is provided to interpret cop instructions,
9346 this knowledge can be encoded in the itbl spec. */
9360 gas_assert (!mips_opts
.micromips
);
9361 /* For now we just do C (same as Cz). The parameter will be
9362 stored in insn_opcode by mips_ip. */
9363 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9367 move_register (dreg
, sreg
);
9373 if (mips_opts
.arch
== CPU_R5900
)
9375 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9379 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9380 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9387 /* The MIPS assembler some times generates shifts and adds. I'm
9388 not trying to be that fancy. GCC should do this for us
9391 load_register (AT
, &imm_expr
, dbl
);
9392 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9393 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9409 load_register (AT
, &imm_expr
, dbl
);
9410 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9411 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9412 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9413 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9415 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9418 if (mips_opts
.micromips
)
9419 micromips_label_expr (&label_expr
);
9421 label_expr
.X_add_number
= 8;
9422 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9423 macro_build (NULL
, "nop", "");
9424 macro_build (NULL
, "break", BRK_FMT
, 6);
9425 if (mips_opts
.micromips
)
9426 micromips_add_label ();
9429 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9445 load_register (AT
, &imm_expr
, dbl
);
9446 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9447 sreg
, imm
? AT
: treg
);
9448 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9449 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9451 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9454 if (mips_opts
.micromips
)
9455 micromips_label_expr (&label_expr
);
9457 label_expr
.X_add_number
= 8;
9458 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9459 macro_build (NULL
, "nop", "");
9460 macro_build (NULL
, "break", BRK_FMT
, 6);
9461 if (mips_opts
.micromips
)
9462 micromips_add_label ();
9468 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9479 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9480 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9484 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9485 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9486 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9487 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9491 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9502 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9503 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9507 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9508 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9509 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9510 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9519 if (imm_expr
.X_op
!= O_constant
)
9520 as_bad (_("Improper rotate count"));
9521 rot
= imm_expr
.X_add_number
& 0x3f;
9522 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9524 rot
= (64 - rot
) & 0x3f;
9526 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9528 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9533 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9536 l
= (rot
< 0x20) ? "dsll" : "dsll32";
9537 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
9540 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
9541 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9542 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9550 if (imm_expr
.X_op
!= O_constant
)
9551 as_bad (_("Improper rotate count"));
9552 rot
= imm_expr
.X_add_number
& 0x1f;
9553 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9555 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
9560 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9564 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
9565 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9566 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9571 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9573 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
9577 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9578 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
9579 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
9580 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9584 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9586 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
9590 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9591 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
9592 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
9593 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9602 if (imm_expr
.X_op
!= O_constant
)
9603 as_bad (_("Improper rotate count"));
9604 rot
= imm_expr
.X_add_number
& 0x3f;
9605 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9608 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
9610 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
9615 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
9618 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
9619 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
9622 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
9623 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9624 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9632 if (imm_expr
.X_op
!= O_constant
)
9633 as_bad (_("Improper rotate count"));
9634 rot
= imm_expr
.X_add_number
& 0x1f;
9635 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9637 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
9642 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
9646 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
9647 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
9648 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9654 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
9656 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9659 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9660 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9665 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9667 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9672 as_warn (_("Instruction %s: result is always false"),
9674 move_register (dreg
, 0);
9677 if (CPU_HAS_SEQ (mips_opts
.arch
)
9678 && -512 <= imm_expr
.X_add_number
9679 && imm_expr
.X_add_number
< 512)
9681 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
9682 (int) imm_expr
.X_add_number
);
9685 if (imm_expr
.X_op
== O_constant
9686 && imm_expr
.X_add_number
>= 0
9687 && imm_expr
.X_add_number
< 0x10000)
9689 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9691 else if (imm_expr
.X_op
== O_constant
9692 && imm_expr
.X_add_number
> -0x8000
9693 && imm_expr
.X_add_number
< 0)
9695 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9696 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9697 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9699 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9702 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9703 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
9708 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9709 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9712 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
9715 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
9721 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
9722 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9725 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
9727 if (imm_expr
.X_op
== O_constant
9728 && imm_expr
.X_add_number
>= -0x8000
9729 && imm_expr
.X_add_number
< 0x8000)
9731 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
9732 dreg
, sreg
, BFD_RELOC_LO16
);
9736 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9737 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
9741 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9744 case M_SGT
: /* sreg > treg <==> treg < sreg */
9750 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9753 case M_SGT_I
: /* sreg > I <==> I < sreg */
9760 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9761 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9764 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9770 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
9771 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9774 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9781 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9782 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
9783 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
9787 if (imm_expr
.X_op
== O_constant
9788 && imm_expr
.X_add_number
>= -0x8000
9789 && imm_expr
.X_add_number
< 0x8000)
9791 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9795 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9796 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
9800 if (imm_expr
.X_op
== O_constant
9801 && imm_expr
.X_add_number
>= -0x8000
9802 && imm_expr
.X_add_number
< 0x8000)
9804 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
9809 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9810 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
9815 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
9817 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9820 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
9821 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9826 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9828 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
9833 as_warn (_("Instruction %s: result is always true"),
9835 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
9836 dreg
, 0, BFD_RELOC_LO16
);
9839 if (CPU_HAS_SEQ (mips_opts
.arch
)
9840 && -512 <= imm_expr
.X_add_number
9841 && imm_expr
.X_add_number
< 512)
9843 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
9844 (int) imm_expr
.X_add_number
);
9847 if (imm_expr
.X_op
== O_constant
9848 && imm_expr
.X_add_number
>= 0
9849 && imm_expr
.X_add_number
< 0x10000)
9851 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
9853 else if (imm_expr
.X_op
== O_constant
9854 && imm_expr
.X_add_number
> -0x8000
9855 && imm_expr
.X_add_number
< 0)
9857 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9858 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
9859 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9861 else if (CPU_HAS_SEQ (mips_opts
.arch
))
9864 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9865 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
9870 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9871 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
9874 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
9889 if (!mips_opts
.micromips
)
9891 if (imm_expr
.X_op
== O_constant
9892 && imm_expr
.X_add_number
> -0x200
9893 && imm_expr
.X_add_number
<= 0x200)
9895 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
9904 if (imm_expr
.X_op
== O_constant
9905 && imm_expr
.X_add_number
> -0x8000
9906 && imm_expr
.X_add_number
<= 0x8000)
9908 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
9909 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
9914 load_register (AT
, &imm_expr
, dbl
);
9915 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
9937 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9938 macro_build (NULL
, s
, "s,t", sreg
, AT
);
9943 gas_assert (!mips_opts
.micromips
);
9944 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
9946 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
9947 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
9950 * Is the double cfc1 instruction a bug in the mips assembler;
9951 * or is there a reason for it?
9954 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9955 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
9956 macro_build (NULL
, "nop", "");
9957 expr1
.X_add_number
= 3;
9958 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
9959 expr1
.X_add_number
= 2;
9960 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
9961 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
9962 macro_build (NULL
, "nop", "");
9963 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
9965 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
9966 macro_build (NULL
, "nop", "");
9989 off12
= mips_opts
.micromips
;
9997 off12
= mips_opts
.micromips
;
10013 off12
= mips_opts
.micromips
;
10022 off12
= mips_opts
.micromips
;
10027 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10028 as_bad (_("Operand overflow"));
10031 expr1
.X_add_number
= 0;
10036 load_address (tempreg
, ep
, &used_at
);
10038 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10039 tempreg
, tempreg
, breg
);
10045 && (offset_expr
.X_op
!= O_constant
10046 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10047 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10051 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10052 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10057 else if (!ust
&& treg
== breg
)
10068 if (!target_big_endian
)
10069 ep
->X_add_number
+= off
;
10071 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10073 macro_build (NULL
, s
, "t,~(b)",
10074 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10076 if (!target_big_endian
)
10077 ep
->X_add_number
-= off
;
10079 ep
->X_add_number
+= off
;
10081 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10083 macro_build (NULL
, s2
, "t,~(b)",
10084 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10086 /* If necessary, move the result in tempreg to the final destination. */
10087 if (!ust
&& treg
!= tempreg
)
10089 /* Protect second load's delay slot. */
10091 move_register (treg
, tempreg
);
10097 if (target_big_endian
== ust
)
10098 ep
->X_add_number
+= off
;
10099 tempreg
= ust
|| ab
? treg
: AT
;
10100 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10102 /* For halfword transfers we need a temporary register to shuffle
10103 bytes. Unfortunately for M_USH_A we have none available before
10104 the next store as AT holds the base address. We deal with this
10105 case by clobbering TREG and then restoring it as with ULH. */
10106 tempreg
= ust
== ab
? treg
: AT
;
10108 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10110 if (target_big_endian
== ust
)
10111 ep
->X_add_number
-= off
;
10113 ep
->X_add_number
+= off
;
10114 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10116 /* For M_USH_A re-retrieve the LSB. */
10119 if (target_big_endian
)
10120 ep
->X_add_number
+= off
;
10122 ep
->X_add_number
-= off
;
10123 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10125 /* For ULH and M_USH_A OR the LSB in. */
10128 tempreg
= !ab
? AT
: treg
;
10129 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10130 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10135 /* FIXME: Check if this is one of the itbl macros, since they
10136 are added dynamically. */
10137 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10140 if (!mips_opts
.at
&& used_at
)
10141 as_bad (_("Macro used $at after \".set noat\""));
10144 /* Implement macros in mips16 mode. */
10147 mips16_macro (struct mips_cl_insn
*ip
)
10150 int xreg
, yreg
, zreg
, tmp
;
10153 const char *s
, *s2
, *s3
;
10155 mask
= ip
->insn_mo
->mask
;
10157 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10158 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10159 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10161 expr1
.X_op
= O_constant
;
10162 expr1
.X_op_symbol
= NULL
;
10163 expr1
.X_add_symbol
= NULL
;
10164 expr1
.X_add_number
= 1;
10183 start_noreorder ();
10184 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10185 expr1
.X_add_number
= 2;
10186 macro_build (&expr1
, "bnez", "x,p", yreg
);
10187 macro_build (NULL
, "break", "6", 7);
10189 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10190 since that causes an overflow. We should do that as well,
10191 but I don't see how to do the comparisons without a temporary
10194 macro_build (NULL
, s
, "x", zreg
);
10213 start_noreorder ();
10214 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10215 expr1
.X_add_number
= 2;
10216 macro_build (&expr1
, "bnez", "x,p", yreg
);
10217 macro_build (NULL
, "break", "6", 7);
10219 macro_build (NULL
, s2
, "x", zreg
);
10225 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10226 macro_build (NULL
, "mflo", "x", zreg
);
10234 if (imm_expr
.X_op
!= O_constant
)
10235 as_bad (_("Unsupported large constant"));
10236 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10237 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10241 if (imm_expr
.X_op
!= O_constant
)
10242 as_bad (_("Unsupported large constant"));
10243 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10244 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10248 if (imm_expr
.X_op
!= O_constant
)
10249 as_bad (_("Unsupported large constant"));
10250 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10251 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10273 goto do_reverse_branch
;
10277 goto do_reverse_branch
;
10289 goto do_reverse_branch
;
10300 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10301 macro_build (&offset_expr
, s2
, "p");
10328 goto do_addone_branch_i
;
10333 goto do_addone_branch_i
;
10348 goto do_addone_branch_i
;
10354 do_addone_branch_i
:
10355 if (imm_expr
.X_op
!= O_constant
)
10356 as_bad (_("Unsupported large constant"));
10357 ++imm_expr
.X_add_number
;
10360 macro_build (&imm_expr
, s
, s3
, xreg
);
10361 macro_build (&offset_expr
, s2
, "p");
10365 expr1
.X_add_number
= 0;
10366 macro_build (&expr1
, "slti", "x,8", yreg
);
10368 move_register (xreg
, yreg
);
10369 expr1
.X_add_number
= 2;
10370 macro_build (&expr1
, "bteqz", "p");
10371 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10375 /* For consistency checking, verify that all bits are specified either
10376 by the match/mask part of the instruction definition, or by the
10379 validate_mips_insn (const struct mips_opcode
*opc
)
10381 const char *p
= opc
->args
;
10383 unsigned long used_bits
= opc
->mask
;
10385 if ((used_bits
& opc
->match
) != opc
->match
)
10387 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10388 opc
->name
, opc
->args
);
10391 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10401 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10402 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10403 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10404 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10405 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10406 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10407 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10408 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10409 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10410 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10411 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10412 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10413 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10415 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10416 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10417 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10418 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10419 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10420 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10421 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10422 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10423 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10424 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10425 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10426 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10427 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10428 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10429 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10432 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10433 c
, opc
->name
, opc
->args
);
10437 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10438 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10440 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10441 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10442 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10443 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10445 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10446 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10448 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10449 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10451 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10452 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10453 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10454 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10455 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10456 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10457 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10458 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10459 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10460 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10461 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10462 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10463 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10464 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10465 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10466 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10467 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10469 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10470 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10471 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10472 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10474 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10475 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10476 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10477 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10478 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10479 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10480 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10481 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10482 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10485 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10486 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10487 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10488 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10489 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10492 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10493 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10494 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10495 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10496 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10497 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10498 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10499 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10500 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10501 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10502 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10503 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10504 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10505 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10506 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10507 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10508 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10509 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10510 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10511 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10513 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10514 c
, opc
->name
, opc
->args
);
10518 if (used_bits
!= 0xffffffff)
10520 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10521 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
10527 /* For consistency checking, verify that the length implied matches the
10528 major opcode and that all bits are specified either by the match/mask
10529 part of the instruction definition, or by the operand list. */
10532 validate_micromips_insn (const struct mips_opcode
*opc
)
10534 unsigned long match
= opc
->match
;
10535 unsigned long mask
= opc
->mask
;
10536 const char *p
= opc
->args
;
10537 unsigned long insn_bits
;
10538 unsigned long used_bits
;
10539 unsigned long major
;
10540 unsigned int length
;
10544 if ((mask
& match
) != match
)
10546 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10547 opc
->name
, opc
->args
);
10550 length
= micromips_insn_length (opc
);
10551 if (length
!= 2 && length
!= 4)
10553 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10554 "%s %s"), length
, opc
->name
, opc
->args
);
10557 major
= match
>> (10 + 8 * (length
- 2));
10558 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
10559 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
10561 as_bad (_("Internal error: bad microMIPS opcode "
10562 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
10566 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10567 insn_bits
= 1 << 4 * length
;
10568 insn_bits
<<= 4 * length
;
10571 #define USE_BITS(field) \
10572 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10583 case 'A': USE_BITS (EXTLSB
); break;
10584 case 'B': USE_BITS (INSMSB
); break;
10585 case 'C': USE_BITS (EXTMSBD
); break;
10586 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
10587 case 'E': USE_BITS (EXTLSB
); break;
10588 case 'F': USE_BITS (INSMSB
); break;
10589 case 'G': USE_BITS (EXTMSBD
); break;
10590 case 'H': USE_BITS (EXTMSBD
); break;
10592 as_bad (_("Internal error: bad mips opcode "
10593 "(unknown extension operand type `%c%c'): %s %s"),
10594 e
, c
, opc
->name
, opc
->args
);
10602 case 'A': USE_BITS (IMMA
); break;
10603 case 'B': USE_BITS (IMMB
); break;
10604 case 'C': USE_BITS (IMMC
); break;
10605 case 'D': USE_BITS (IMMD
); break;
10606 case 'E': USE_BITS (IMME
); break;
10607 case 'F': USE_BITS (IMMF
); break;
10608 case 'G': USE_BITS (IMMG
); break;
10609 case 'H': USE_BITS (IMMH
); break;
10610 case 'I': USE_BITS (IMMI
); break;
10611 case 'J': USE_BITS (IMMJ
); break;
10612 case 'L': USE_BITS (IMML
); break;
10613 case 'M': USE_BITS (IMMM
); break;
10614 case 'N': USE_BITS (IMMN
); break;
10615 case 'O': USE_BITS (IMMO
); break;
10616 case 'P': USE_BITS (IMMP
); break;
10617 case 'Q': USE_BITS (IMMQ
); break;
10618 case 'U': USE_BITS (IMMU
); break;
10619 case 'W': USE_BITS (IMMW
); break;
10620 case 'X': USE_BITS (IMMX
); break;
10621 case 'Y': USE_BITS (IMMY
); break;
10624 case 'b': USE_BITS (MB
); break;
10625 case 'c': USE_BITS (MC
); break;
10626 case 'd': USE_BITS (MD
); break;
10627 case 'e': USE_BITS (ME
); break;
10628 case 'f': USE_BITS (MF
); break;
10629 case 'g': USE_BITS (MG
); break;
10630 case 'h': USE_BITS (MH
); break;
10631 case 'i': USE_BITS (MI
); break;
10632 case 'j': USE_BITS (MJ
); break;
10633 case 'l': USE_BITS (ML
); break;
10634 case 'm': USE_BITS (MM
); break;
10635 case 'n': USE_BITS (MN
); break;
10636 case 'p': USE_BITS (MP
); break;
10637 case 'q': USE_BITS (MQ
); break;
10645 as_bad (_("Internal error: bad mips opcode "
10646 "(unknown extension operand type `%c%c'): %s %s"),
10647 e
, c
, opc
->name
, opc
->args
);
10651 case '.': USE_BITS (OFFSET10
); break;
10652 case '1': USE_BITS (STYPE
); break;
10653 case '2': USE_BITS (BP
); break;
10654 case '3': USE_BITS (SA3
); break;
10655 case '4': USE_BITS (SA4
); break;
10656 case '5': USE_BITS (IMM8
); break;
10657 case '6': USE_BITS (RS
); break;
10658 case '7': USE_BITS (DSPACC
); break;
10659 case '8': USE_BITS (WRDSP
); break;
10660 case '0': USE_BITS (DSPSFT
); break;
10661 case '<': USE_BITS (SHAMT
); break;
10662 case '>': USE_BITS (SHAMT
); break;
10663 case '@': USE_BITS (IMM10
); break;
10664 case 'B': USE_BITS (CODE10
); break;
10665 case 'C': USE_BITS (COPZ
); break;
10666 case 'D': USE_BITS (FD
); break;
10667 case 'E': USE_BITS (RT
); break;
10668 case 'G': USE_BITS (RS
); break;
10669 case 'H': USE_BITS (SEL
); break;
10670 case 'K': USE_BITS (RS
); break;
10671 case 'M': USE_BITS (CCC
); break;
10672 case 'N': USE_BITS (BCC
); break;
10673 case 'R': USE_BITS (FR
); break;
10674 case 'S': USE_BITS (FS
); break;
10675 case 'T': USE_BITS (FT
); break;
10676 case 'V': USE_BITS (FS
); break;
10677 case '\\': USE_BITS (3BITPOS
); break;
10678 case '^': USE_BITS (RD
); break;
10679 case 'a': USE_BITS (TARGET
); break;
10680 case 'b': USE_BITS (RS
); break;
10681 case 'c': USE_BITS (CODE
); break;
10682 case 'd': USE_BITS (RD
); break;
10683 case 'h': USE_BITS (PREFX
); break;
10684 case 'i': USE_BITS (IMMEDIATE
); break;
10685 case 'j': USE_BITS (DELTA
); break;
10686 case 'k': USE_BITS (CACHE
); break;
10687 case 'n': USE_BITS (RT
); break;
10688 case 'o': USE_BITS (DELTA
); break;
10689 case 'p': USE_BITS (DELTA
); break;
10690 case 'q': USE_BITS (CODE2
); break;
10691 case 'r': USE_BITS (RS
); break;
10692 case 's': USE_BITS (RS
); break;
10693 case 't': USE_BITS (RT
); break;
10694 case 'u': USE_BITS (IMMEDIATE
); break;
10695 case 'v': USE_BITS (RS
); break;
10696 case 'w': USE_BITS (RT
); break;
10697 case 'y': USE_BITS (RS3
); break;
10699 case '|': USE_BITS (TRAP
); break;
10700 case '~': USE_BITS (OFFSET12
); break;
10702 as_bad (_("Internal error: bad microMIPS opcode "
10703 "(unknown operand type `%c'): %s %s"),
10704 c
, opc
->name
, opc
->args
);
10708 if (used_bits
!= insn_bits
)
10710 if (~used_bits
& insn_bits
)
10711 as_bad (_("Internal error: bad microMIPS opcode "
10712 "(bits 0x%lx undefined): %s %s"),
10713 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
10714 if (used_bits
& ~insn_bits
)
10715 as_bad (_("Internal error: bad microMIPS opcode "
10716 "(bits 0x%lx defined): %s %s"),
10717 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
10723 /* UDI immediates. */
10724 struct mips_immed
{
10726 unsigned int shift
;
10727 unsigned long mask
;
10731 static const struct mips_immed mips_immed
[] = {
10732 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
10733 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
10734 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
10735 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
10739 /* Check whether an odd floating-point register is allowed. */
10741 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
10743 const char *s
= insn
->name
;
10745 if (insn
->pinfo
== INSN_MACRO
)
10746 /* Let a macro pass, we'll catch it later when it is expanded. */
10749 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
10751 /* Allow odd registers for single-precision ops. */
10752 switch (insn
->pinfo
& (FP_S
| FP_D
))
10756 return 1; /* both single precision - ok */
10758 return 0; /* both double precision - fail */
10763 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10764 s
= strchr (insn
->name
, '.');
10766 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
10767 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
10770 /* Single-precision coprocessor loads and moves are OK too. */
10771 if ((insn
->pinfo
& FP_S
)
10772 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
10773 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
10779 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10780 taking bits from BIT up. */
10782 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
10784 return (ep
->X_op
== O_constant
10785 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
10786 && ep
->X_add_number
>= min
<< bit
10787 && ep
->X_add_number
< max
<< bit
);
10790 /* This routine assembles an instruction into its binary format. As a
10791 side effect, it sets one of the global variables imm_reloc or
10792 offset_reloc to the type of relocation to do if one of the operands
10793 is an address expression. */
10796 mips_ip (char *str
, struct mips_cl_insn
*ip
)
10798 bfd_boolean wrong_delay_slot_insns
= FALSE
;
10799 bfd_boolean need_delay_slot_ok
= TRUE
;
10800 struct mips_opcode
*firstinsn
= NULL
;
10801 const struct mips_opcode
*past
;
10802 struct hash_control
*hash
;
10806 struct mips_opcode
*insn
;
10808 unsigned int regno
;
10809 unsigned int lastregno
;
10810 unsigned int destregno
= 0;
10811 unsigned int lastpos
= 0;
10812 unsigned int limlo
, limhi
;
10815 offsetT min_range
, max_range
;
10819 unsigned int rtype
;
10825 if (mips_opts
.micromips
)
10827 hash
= micromips_op_hash
;
10828 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
10833 past
= &mips_opcodes
[NUMOPCODES
];
10835 forced_insn_length
= 0;
10838 /* We first try to match an instruction up to a space or to the end. */
10839 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
10842 /* Make a copy of the instruction so that we can fiddle with it. */
10843 name
= alloca (end
+ 1);
10844 memcpy (name
, str
, end
);
10849 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
10851 if (insn
!= NULL
|| !mips_opts
.micromips
)
10853 if (forced_insn_length
)
10856 /* See if there's an instruction size override suffix,
10857 either `16' or `32', at the end of the mnemonic proper,
10858 that defines the operation, i.e. before the first `.'
10859 character if any. Strip it and retry. */
10860 dot
= strchr (name
, '.');
10861 opend
= dot
!= NULL
? dot
- name
: end
;
10864 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
10865 forced_insn_length
= 2;
10866 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
10867 forced_insn_length
= 4;
10870 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
10874 insn_error
= _("Unrecognized opcode");
10878 /* For microMIPS instructions placed in a fixed-length branch delay slot
10879 we make up to two passes over the relevant fragment of the opcode
10880 table. First we try instructions that meet the delay slot's length
10881 requirement. If none matched, then we retry with the remaining ones
10882 and if one matches, then we use it and then issue an appropriate
10883 warning later on. */
10884 argsStart
= s
= str
+ end
;
10887 bfd_boolean delay_slot_ok
;
10888 bfd_boolean size_ok
;
10891 gas_assert (strcmp (insn
->name
, name
) == 0);
10893 ok
= is_opcode_valid (insn
);
10894 size_ok
= is_size_valid (insn
);
10895 delay_slot_ok
= is_delay_slot_valid (insn
);
10896 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
10899 wrong_delay_slot_insns
= TRUE
;
10901 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
10903 static char buf
[256];
10905 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
10910 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
10912 gas_assert (firstinsn
);
10913 need_delay_slot_ok
= FALSE
;
10923 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
10924 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10925 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10927 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
10928 8 * forced_insn_length
);
10934 create_insn (ip
, insn
);
10937 lastregno
= 0xffffffff;
10938 for (args
= insn
->args
;; ++args
)
10942 s
+= strspn (s
, " \t");
10946 case '\0': /* end of args */
10952 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10953 code) or 14 (for microMIPS code). */
10954 my_getExpression (&imm_expr
, s
);
10955 check_absolute_expr (ip
, &imm_expr
);
10956 if ((unsigned long) imm_expr
.X_add_number
!= 1
10957 && (unsigned long) imm_expr
.X_add_number
!= 3)
10959 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10960 (unsigned long) imm_expr
.X_add_number
);
10962 INSERT_OPERAND (mips_opts
.micromips
,
10963 BP
, *ip
, imm_expr
.X_add_number
);
10964 imm_expr
.X_op
= O_absent
;
10969 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10970 code) or 21 (for microMIPS code). */
10972 unsigned long mask
= (mips_opts
.micromips
10973 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
10975 my_getExpression (&imm_expr
, s
);
10976 check_absolute_expr (ip
, &imm_expr
);
10977 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10978 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10979 mask
, (unsigned long) imm_expr
.X_add_number
);
10980 INSERT_OPERAND (mips_opts
.micromips
,
10981 SA3
, *ip
, imm_expr
.X_add_number
);
10982 imm_expr
.X_op
= O_absent
;
10988 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10989 code) or 21 (for microMIPS code). */
10991 unsigned long mask
= (mips_opts
.micromips
10992 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
10994 my_getExpression (&imm_expr
, s
);
10995 check_absolute_expr (ip
, &imm_expr
);
10996 if ((unsigned long) imm_expr
.X_add_number
> mask
)
10997 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10998 mask
, (unsigned long) imm_expr
.X_add_number
);
10999 INSERT_OPERAND (mips_opts
.micromips
,
11000 SA4
, *ip
, imm_expr
.X_add_number
);
11001 imm_expr
.X_op
= O_absent
;
11007 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11008 code) or 16 (for microMIPS code). */
11010 unsigned long mask
= (mips_opts
.micromips
11011 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11013 my_getExpression (&imm_expr
, s
);
11014 check_absolute_expr (ip
, &imm_expr
);
11015 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11016 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11017 mask
, (unsigned long) imm_expr
.X_add_number
);
11018 INSERT_OPERAND (mips_opts
.micromips
,
11019 IMM8
, *ip
, imm_expr
.X_add_number
);
11020 imm_expr
.X_op
= O_absent
;
11026 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11027 code) or 21 (for microMIPS code). */
11029 unsigned long mask
= (mips_opts
.micromips
11030 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11032 my_getExpression (&imm_expr
, s
);
11033 check_absolute_expr (ip
, &imm_expr
);
11034 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11035 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11036 mask
, (unsigned long) imm_expr
.X_add_number
);
11037 INSERT_OPERAND (mips_opts
.micromips
,
11038 RS
, *ip
, imm_expr
.X_add_number
);
11039 imm_expr
.X_op
= O_absent
;
11044 case '7': /* Four DSP accumulators in bits 11,12. */
11045 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11046 && s
[3] >= '0' && s
[3] <= '3')
11048 regno
= s
[3] - '0';
11050 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11054 as_bad (_("Invalid dsp acc register"));
11058 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11059 code) or 14 (for microMIPS code). */
11061 unsigned long mask
= (mips_opts
.micromips
11062 ? MICROMIPSOP_MASK_WRDSP
11065 my_getExpression (&imm_expr
, s
);
11066 check_absolute_expr (ip
, &imm_expr
);
11067 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11068 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11069 mask
, (unsigned long) imm_expr
.X_add_number
);
11070 INSERT_OPERAND (mips_opts
.micromips
,
11071 WRDSP
, *ip
, imm_expr
.X_add_number
);
11072 imm_expr
.X_op
= O_absent
;
11077 case '9': /* Four DSP accumulators in bits 21,22. */
11078 gas_assert (!mips_opts
.micromips
);
11079 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11080 && s
[3] >= '0' && s
[3] <= '3')
11082 regno
= s
[3] - '0';
11084 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11088 as_bad (_("Invalid dsp acc register"));
11092 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11093 code) or 20 (for microMIPS code). */
11095 long mask
= (mips_opts
.micromips
11096 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11098 my_getExpression (&imm_expr
, s
);
11099 check_absolute_expr (ip
, &imm_expr
);
11100 min_range
= -((mask
+ 1) >> 1);
11101 max_range
= ((mask
+ 1) >> 1) - 1;
11102 if (imm_expr
.X_add_number
< min_range
11103 || imm_expr
.X_add_number
> max_range
)
11104 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11105 (long) min_range
, (long) max_range
,
11106 (long) imm_expr
.X_add_number
);
11107 INSERT_OPERAND (mips_opts
.micromips
,
11108 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11109 imm_expr
.X_op
= O_absent
;
11114 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11115 gas_assert (!mips_opts
.micromips
);
11116 my_getExpression (&imm_expr
, s
);
11117 check_absolute_expr (ip
, &imm_expr
);
11118 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11120 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11122 (unsigned long) imm_expr
.X_add_number
);
11124 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11125 imm_expr
.X_op
= O_absent
;
11129 case ':': /* DSP 7-bit signed immediate in bit 19. */
11130 gas_assert (!mips_opts
.micromips
);
11131 my_getExpression (&imm_expr
, s
);
11132 check_absolute_expr (ip
, &imm_expr
);
11133 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11134 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11135 if (imm_expr
.X_add_number
< min_range
||
11136 imm_expr
.X_add_number
> max_range
)
11138 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11139 (long) min_range
, (long) max_range
,
11140 (long) imm_expr
.X_add_number
);
11142 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11143 imm_expr
.X_op
= O_absent
;
11147 case '@': /* DSP 10-bit signed immediate in bit 16. */
11149 long mask
= (mips_opts
.micromips
11150 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11152 my_getExpression (&imm_expr
, s
);
11153 check_absolute_expr (ip
, &imm_expr
);
11154 min_range
= -((mask
+ 1) >> 1);
11155 max_range
= ((mask
+ 1) >> 1) - 1;
11156 if (imm_expr
.X_add_number
< min_range
11157 || imm_expr
.X_add_number
> max_range
)
11158 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11159 (long) min_range
, (long) max_range
,
11160 (long) imm_expr
.X_add_number
);
11161 INSERT_OPERAND (mips_opts
.micromips
,
11162 IMM10
, *ip
, imm_expr
.X_add_number
);
11163 imm_expr
.X_op
= O_absent
;
11168 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11169 gas_assert (mips_opts
.micromips
);
11170 my_getExpression (&imm_expr
, s
);
11171 check_absolute_expr (ip
, &imm_expr
);
11172 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11173 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11174 MICROMIPSOP_MASK_RD
,
11175 (unsigned long) imm_expr
.X_add_number
);
11176 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11177 imm_expr
.X_op
= O_absent
;
11181 case '!': /* MT usermode flag bit. */
11182 gas_assert (!mips_opts
.micromips
);
11183 my_getExpression (&imm_expr
, s
);
11184 check_absolute_expr (ip
, &imm_expr
);
11185 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11186 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11187 (unsigned long) imm_expr
.X_add_number
);
11188 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11189 imm_expr
.X_op
= O_absent
;
11193 case '$': /* MT load high flag bit. */
11194 gas_assert (!mips_opts
.micromips
);
11195 my_getExpression (&imm_expr
, s
);
11196 check_absolute_expr (ip
, &imm_expr
);
11197 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11198 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11199 (unsigned long) imm_expr
.X_add_number
);
11200 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11201 imm_expr
.X_op
= O_absent
;
11205 case '*': /* Four DSP accumulators in bits 18,19. */
11206 gas_assert (!mips_opts
.micromips
);
11207 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11208 s
[3] >= '0' && s
[3] <= '3')
11210 regno
= s
[3] - '0';
11212 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11216 as_bad (_("Invalid dsp/smartmips acc register"));
11219 case '&': /* Four DSP accumulators in bits 13,14. */
11220 gas_assert (!mips_opts
.micromips
);
11221 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11222 s
[3] >= '0' && s
[3] <= '3')
11224 regno
= s
[3] - '0';
11226 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11230 as_bad (_("Invalid dsp/smartmips acc register"));
11233 case '\\': /* 3-bit bit position. */
11235 unsigned long mask
= (mips_opts
.micromips
11236 ? MICROMIPSOP_MASK_3BITPOS
11237 : OP_MASK_3BITPOS
);
11239 my_getExpression (&imm_expr
, s
);
11240 check_absolute_expr (ip
, &imm_expr
);
11241 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11242 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11244 mask
, (unsigned long) imm_expr
.X_add_number
);
11245 INSERT_OPERAND (mips_opts
.micromips
,
11246 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11247 imm_expr
.X_op
= O_absent
;
11261 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11265 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11269 gas_assert (!mips_opts
.micromips
);
11270 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11274 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11280 /* Handle optional base register.
11281 Either the base register is omitted or
11282 we must have a left paren. */
11283 /* This is dependent on the next operand specifier
11284 is a base register specification. */
11285 gas_assert (args
[1] == 'b'
11286 || (mips_opts
.micromips
11288 && (args
[2] == 'l' || args
[2] == 'n'
11289 || args
[2] == 's' || args
[2] == 'a')));
11290 if (*s
== '\0' && args
[1] == 'b')
11292 /* Fall through. */
11294 case ')': /* These must match exactly. */
11299 case '[': /* These must match exactly. */
11301 gas_assert (!mips_opts
.micromips
);
11306 case '+': /* Opcode extension character. */
11309 case '1': /* UDI immediates. */
11313 gas_assert (!mips_opts
.micromips
);
11315 const struct mips_immed
*imm
= mips_immed
;
11317 while (imm
->type
&& imm
->type
!= *args
)
11321 my_getExpression (&imm_expr
, s
);
11322 check_absolute_expr (ip
, &imm_expr
);
11323 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11325 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11326 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11327 (unsigned long) imm_expr
.X_add_number
,
11328 (unsigned long) imm_expr
.X_add_number
);
11329 imm_expr
.X_add_number
&= imm
->mask
;
11331 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11333 imm_expr
.X_op
= O_absent
;
11338 case 'A': /* ins/ext position, becomes LSB. */
11347 my_getExpression (&imm_expr
, s
);
11348 check_absolute_expr (ip
, &imm_expr
);
11349 if ((unsigned long) imm_expr
.X_add_number
< limlo
11350 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11352 as_bad (_("Improper position (%lu)"),
11353 (unsigned long) imm_expr
.X_add_number
);
11354 imm_expr
.X_add_number
= limlo
;
11356 lastpos
= imm_expr
.X_add_number
;
11357 INSERT_OPERAND (mips_opts
.micromips
,
11358 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11359 imm_expr
.X_op
= O_absent
;
11363 case 'B': /* ins size, becomes MSB. */
11372 my_getExpression (&imm_expr
, s
);
11373 check_absolute_expr (ip
, &imm_expr
);
11374 /* Check for negative input so that small negative numbers
11375 will not succeed incorrectly. The checks against
11376 (pos+size) transitively check "size" itself,
11377 assuming that "pos" is reasonable. */
11378 if ((long) imm_expr
.X_add_number
< 0
11379 || ((unsigned long) imm_expr
.X_add_number
11381 || ((unsigned long) imm_expr
.X_add_number
11382 + lastpos
) > limhi
)
11384 as_bad (_("Improper insert size (%lu, position %lu)"),
11385 (unsigned long) imm_expr
.X_add_number
,
11386 (unsigned long) lastpos
);
11387 imm_expr
.X_add_number
= limlo
- lastpos
;
11389 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11390 lastpos
+ imm_expr
.X_add_number
- 1);
11391 imm_expr
.X_op
= O_absent
;
11395 case 'C': /* ext size, becomes MSBD. */
11411 my_getExpression (&imm_expr
, s
);
11412 check_absolute_expr (ip
, &imm_expr
);
11413 /* The checks against (pos+size) don't transitively check
11414 "size" itself, assuming that "pos" is reasonable.
11415 We also need to check the lower bound of "size". */
11416 if ((long) imm_expr
.X_add_number
< sizelo
11417 || ((unsigned long) imm_expr
.X_add_number
11419 || ((unsigned long) imm_expr
.X_add_number
11420 + lastpos
) > limhi
)
11422 as_bad (_("Improper extract size (%lu, position %lu)"),
11423 (unsigned long) imm_expr
.X_add_number
,
11424 (unsigned long) lastpos
);
11425 imm_expr
.X_add_number
= limlo
- lastpos
;
11427 INSERT_OPERAND (mips_opts
.micromips
,
11428 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11429 imm_expr
.X_op
= O_absent
;
11434 /* +D is for disassembly only; never match. */
11438 /* "+I" is like "I", except that imm2_expr is used. */
11439 my_getExpression (&imm2_expr
, s
);
11440 if (imm2_expr
.X_op
!= O_big
11441 && imm2_expr
.X_op
!= O_constant
)
11442 insn_error
= _("absolute expression required");
11443 if (HAVE_32BIT_GPRS
)
11444 normalize_constant_expr (&imm2_expr
);
11448 case 'T': /* Coprocessor register. */
11449 gas_assert (!mips_opts
.micromips
);
11450 /* +T is for disassembly only; never match. */
11453 case 't': /* Coprocessor register number. */
11454 gas_assert (!mips_opts
.micromips
);
11455 if (s
[0] == '$' && ISDIGIT (s
[1]))
11465 while (ISDIGIT (*s
));
11467 as_bad (_("Invalid register number (%d)"), regno
);
11470 INSERT_OPERAND (0, RT
, *ip
, regno
);
11475 as_bad (_("Invalid coprocessor 0 register number"));
11479 /* bbit[01] and bbit[01]32 bit index. Give error if index
11480 is not in the valid range. */
11481 gas_assert (!mips_opts
.micromips
);
11482 my_getExpression (&imm_expr
, s
);
11483 check_absolute_expr (ip
, &imm_expr
);
11484 if ((unsigned) imm_expr
.X_add_number
> 31)
11486 as_bad (_("Improper bit index (%lu)"),
11487 (unsigned long) imm_expr
.X_add_number
);
11488 imm_expr
.X_add_number
= 0;
11490 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11491 imm_expr
.X_op
= O_absent
;
11496 /* bbit[01] bit index when bbit is used but we generate
11497 bbit[01]32 because the index is over 32. Move to the
11498 next candidate if index is not in the valid range. */
11499 gas_assert (!mips_opts
.micromips
);
11500 my_getExpression (&imm_expr
, s
);
11501 check_absolute_expr (ip
, &imm_expr
);
11502 if ((unsigned) imm_expr
.X_add_number
< 32
11503 || (unsigned) imm_expr
.X_add_number
> 63)
11505 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11506 imm_expr
.X_op
= O_absent
;
11511 /* cins, cins32, exts and exts32 position field. Give error
11512 if it's not in the valid range. */
11513 gas_assert (!mips_opts
.micromips
);
11514 my_getExpression (&imm_expr
, s
);
11515 check_absolute_expr (ip
, &imm_expr
);
11516 if ((unsigned) imm_expr
.X_add_number
> 31)
11518 as_bad (_("Improper position (%lu)"),
11519 (unsigned long) imm_expr
.X_add_number
);
11520 imm_expr
.X_add_number
= 0;
11522 /* Make the pos explicit to simplify +S. */
11523 lastpos
= imm_expr
.X_add_number
+ 32;
11524 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
11525 imm_expr
.X_op
= O_absent
;
11530 /* cins, cins32, exts and exts32 position field. Move to
11531 the next candidate if it's not in the valid range. */
11532 gas_assert (!mips_opts
.micromips
);
11533 my_getExpression (&imm_expr
, s
);
11534 check_absolute_expr (ip
, &imm_expr
);
11535 if ((unsigned) imm_expr
.X_add_number
< 32
11536 || (unsigned) imm_expr
.X_add_number
> 63)
11538 lastpos
= imm_expr
.X_add_number
;
11539 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
11540 imm_expr
.X_op
= O_absent
;
11545 /* cins and exts length-minus-one field. */
11546 gas_assert (!mips_opts
.micromips
);
11547 my_getExpression (&imm_expr
, s
);
11548 check_absolute_expr (ip
, &imm_expr
);
11549 if ((unsigned long) imm_expr
.X_add_number
> 31)
11551 as_bad (_("Improper size (%lu)"),
11552 (unsigned long) imm_expr
.X_add_number
);
11553 imm_expr
.X_add_number
= 0;
11555 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11556 imm_expr
.X_op
= O_absent
;
11561 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11562 length-minus-one field. */
11563 gas_assert (!mips_opts
.micromips
);
11564 my_getExpression (&imm_expr
, s
);
11565 check_absolute_expr (ip
, &imm_expr
);
11566 if ((long) imm_expr
.X_add_number
< 0
11567 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
11569 as_bad (_("Improper size (%lu)"),
11570 (unsigned long) imm_expr
.X_add_number
);
11571 imm_expr
.X_add_number
= 0;
11573 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
11574 imm_expr
.X_op
= O_absent
;
11579 /* seqi/snei immediate field. */
11580 gas_assert (!mips_opts
.micromips
);
11581 my_getExpression (&imm_expr
, s
);
11582 check_absolute_expr (ip
, &imm_expr
);
11583 if ((long) imm_expr
.X_add_number
< -512
11584 || (long) imm_expr
.X_add_number
>= 512)
11586 as_bad (_("Improper immediate (%ld)"),
11587 (long) imm_expr
.X_add_number
);
11588 imm_expr
.X_add_number
= 0;
11590 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
11591 imm_expr
.X_op
= O_absent
;
11595 case 'a': /* 8-bit signed offset in bit 6 */
11596 gas_assert (!mips_opts
.micromips
);
11597 my_getExpression (&imm_expr
, s
);
11598 check_absolute_expr (ip
, &imm_expr
);
11599 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
11600 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
11601 if (imm_expr
.X_add_number
< min_range
11602 || imm_expr
.X_add_number
> max_range
)
11604 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11605 (long) min_range
, (long) max_range
,
11606 (long) imm_expr
.X_add_number
);
11608 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
11609 imm_expr
.X_op
= O_absent
;
11613 case 'b': /* 8-bit signed offset in bit 3 */
11614 gas_assert (!mips_opts
.micromips
);
11615 my_getExpression (&imm_expr
, s
);
11616 check_absolute_expr (ip
, &imm_expr
);
11617 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
11618 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
11619 if (imm_expr
.X_add_number
< min_range
11620 || imm_expr
.X_add_number
> max_range
)
11622 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11623 (long) min_range
, (long) max_range
,
11624 (long) imm_expr
.X_add_number
);
11626 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
11627 imm_expr
.X_op
= O_absent
;
11631 case 'c': /* 9-bit signed offset in bit 6 */
11632 gas_assert (!mips_opts
.micromips
);
11633 my_getExpression (&imm_expr
, s
);
11634 check_absolute_expr (ip
, &imm_expr
);
11635 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
11636 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
11637 /* We check the offset range before adjusted. */
11640 if (imm_expr
.X_add_number
< min_range
11641 || imm_expr
.X_add_number
> max_range
)
11643 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11644 (long) min_range
, (long) max_range
,
11645 (long) imm_expr
.X_add_number
);
11647 if (imm_expr
.X_add_number
& 0xf)
11649 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11650 (long) imm_expr
.X_add_number
);
11652 /* Right shift 4 bits to adjust the offset operand. */
11653 INSERT_OPERAND (0, OFFSET_C
, *ip
,
11654 imm_expr
.X_add_number
>> 4);
11655 imm_expr
.X_op
= O_absent
;
11660 gas_assert (!mips_opts
.micromips
);
11661 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
11663 if (regno
== AT
&& mips_opts
.at
)
11665 if (mips_opts
.at
== ATREG
)
11666 as_warn (_("used $at without \".set noat\""));
11668 as_warn (_("used $%u with \".set at=$%u\""),
11669 regno
, mips_opts
.at
);
11671 INSERT_OPERAND (0, RZ
, *ip
, regno
);
11675 gas_assert (!mips_opts
.micromips
);
11676 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
11678 INSERT_OPERAND (0, FZ
, *ip
, regno
);
11682 as_bad (_("Internal error: bad %s opcode "
11683 "(unknown extension operand type `+%c'): %s %s"),
11684 mips_opts
.micromips
? "microMIPS" : "MIPS",
11685 *args
, insn
->name
, insn
->args
);
11686 /* Further processing is fruitless. */
11691 case '.': /* 10-bit offset. */
11692 gas_assert (mips_opts
.micromips
);
11693 case '~': /* 12-bit offset. */
11695 int shift
= *args
== '.' ? 9 : 11;
11698 /* Check whether there is only a single bracketed expression
11699 left. If so, it must be the base register and the
11700 constant must be zero. */
11701 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
11704 /* If this value won't fit into the offset, then go find
11705 a macro that will generate a 16- or 32-bit offset code
11707 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
11708 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
11709 || imm_expr
.X_add_number
>= 1 << shift
11710 || imm_expr
.X_add_number
< -1 << shift
))
11713 imm_expr
.X_op
= O_absent
;
11717 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
11719 INSERT_OPERAND (mips_opts
.micromips
,
11720 OFFSET12
, *ip
, imm_expr
.X_add_number
);
11721 imm_expr
.X_op
= O_absent
;
11726 case '<': /* must be at least one digit */
11728 * According to the manual, if the shift amount is greater
11729 * than 31 or less than 0, then the shift amount should be
11730 * mod 32. In reality the mips assembler issues an error.
11731 * We issue a warning and mask out all but the low 5 bits.
11733 my_getExpression (&imm_expr
, s
);
11734 check_absolute_expr (ip
, &imm_expr
);
11735 if ((unsigned long) imm_expr
.X_add_number
> 31)
11736 as_warn (_("Improper shift amount (%lu)"),
11737 (unsigned long) imm_expr
.X_add_number
);
11738 INSERT_OPERAND (mips_opts
.micromips
,
11739 SHAMT
, *ip
, imm_expr
.X_add_number
);
11740 imm_expr
.X_op
= O_absent
;
11744 case '>': /* shift amount minus 32 */
11745 my_getExpression (&imm_expr
, s
);
11746 check_absolute_expr (ip
, &imm_expr
);
11747 if ((unsigned long) imm_expr
.X_add_number
< 32
11748 || (unsigned long) imm_expr
.X_add_number
> 63)
11750 INSERT_OPERAND (mips_opts
.micromips
,
11751 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
11752 imm_expr
.X_op
= O_absent
;
11756 case 'k': /* CACHE code. */
11757 case 'h': /* PREFX code. */
11758 case '1': /* SYNC type. */
11759 my_getExpression (&imm_expr
, s
);
11760 check_absolute_expr (ip
, &imm_expr
);
11761 if ((unsigned long) imm_expr
.X_add_number
> 31)
11762 as_warn (_("Invalid value for `%s' (%lu)"),
11764 (unsigned long) imm_expr
.X_add_number
);
11768 if (mips_fix_cn63xxp1
11769 && !mips_opts
.micromips
11770 && strcmp ("pref", insn
->name
) == 0)
11771 switch (imm_expr
.X_add_number
)
11780 case 31: /* These are ok. */
11783 default: /* The rest must be changed to 28. */
11784 imm_expr
.X_add_number
= 28;
11787 INSERT_OPERAND (mips_opts
.micromips
,
11788 CACHE
, *ip
, imm_expr
.X_add_number
);
11791 INSERT_OPERAND (mips_opts
.micromips
,
11792 PREFX
, *ip
, imm_expr
.X_add_number
);
11795 INSERT_OPERAND (mips_opts
.micromips
,
11796 STYPE
, *ip
, imm_expr
.X_add_number
);
11799 imm_expr
.X_op
= O_absent
;
11803 case 'c': /* BREAK code. */
11805 unsigned long mask
= (mips_opts
.micromips
11806 ? MICROMIPSOP_MASK_CODE
11809 my_getExpression (&imm_expr
, s
);
11810 check_absolute_expr (ip
, &imm_expr
);
11811 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11812 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11814 mask
, (unsigned long) imm_expr
.X_add_number
);
11815 INSERT_OPERAND (mips_opts
.micromips
,
11816 CODE
, *ip
, imm_expr
.X_add_number
);
11817 imm_expr
.X_op
= O_absent
;
11822 case 'q': /* Lower BREAK code. */
11824 unsigned long mask
= (mips_opts
.micromips
11825 ? MICROMIPSOP_MASK_CODE2
11828 my_getExpression (&imm_expr
, s
);
11829 check_absolute_expr (ip
, &imm_expr
);
11830 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11831 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11833 mask
, (unsigned long) imm_expr
.X_add_number
);
11834 INSERT_OPERAND (mips_opts
.micromips
,
11835 CODE2
, *ip
, imm_expr
.X_add_number
);
11836 imm_expr
.X_op
= O_absent
;
11841 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11843 unsigned long mask
= (mips_opts
.micromips
11844 ? MICROMIPSOP_MASK_CODE10
11847 my_getExpression (&imm_expr
, s
);
11848 check_absolute_expr (ip
, &imm_expr
);
11849 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11850 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11852 mask
, (unsigned long) imm_expr
.X_add_number
);
11853 if (mips_opts
.micromips
)
11854 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
11856 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
11857 imm_expr
.X_op
= O_absent
;
11862 case 'C': /* 25- or 23-bit coprocessor code. */
11864 unsigned long mask
= (mips_opts
.micromips
11865 ? MICROMIPSOP_MASK_COPZ
11868 my_getExpression (&imm_expr
, s
);
11869 check_absolute_expr (ip
, &imm_expr
);
11870 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11871 as_warn (_("Coproccesor code > %u bits (%lu)"),
11872 mips_opts
.micromips
? 23U : 25U,
11873 (unsigned long) imm_expr
.X_add_number
);
11874 INSERT_OPERAND (mips_opts
.micromips
,
11875 COPZ
, *ip
, imm_expr
.X_add_number
);
11876 imm_expr
.X_op
= O_absent
;
11881 case 'J': /* 19-bit WAIT code. */
11882 gas_assert (!mips_opts
.micromips
);
11883 my_getExpression (&imm_expr
, s
);
11884 check_absolute_expr (ip
, &imm_expr
);
11885 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
11887 as_warn (_("Illegal 19-bit code (%lu)"),
11888 (unsigned long) imm_expr
.X_add_number
);
11889 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
11891 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
11892 imm_expr
.X_op
= O_absent
;
11896 case 'P': /* Performance register. */
11897 gas_assert (!mips_opts
.micromips
);
11898 my_getExpression (&imm_expr
, s
);
11899 check_absolute_expr (ip
, &imm_expr
);
11900 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
11901 as_warn (_("Invalid performance register (%lu)"),
11902 (unsigned long) imm_expr
.X_add_number
);
11903 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
11904 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
11905 as_warn (_("Invalid performance register (%lu)"),
11906 (unsigned long) imm_expr
.X_add_number
);
11907 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
11908 imm_expr
.X_op
= O_absent
;
11912 case 'G': /* Coprocessor destination register. */
11914 unsigned long opcode
= ip
->insn_opcode
;
11915 unsigned long mask
;
11916 unsigned int types
;
11919 if (mips_opts
.micromips
)
11921 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
11922 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
11923 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
11927 case 0x000000fc: /* mfc0 */
11928 case 0x000002fc: /* mtc0 */
11929 case 0x580000fc: /* dmfc0 */
11930 case 0x580002fc: /* dmtc0 */
11940 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
11941 cop0
= opcode
== OP_OP_COP0
;
11943 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
11944 ok
= reg_lookup (&s
, types
, ®no
);
11945 if (mips_opts
.micromips
)
11946 INSERT_OPERAND (1, RS
, *ip
, regno
);
11948 INSERT_OPERAND (0, RD
, *ip
, regno
);
11957 case 'y': /* ALNV.PS source register. */
11958 gas_assert (mips_opts
.micromips
);
11960 case 'x': /* Ignore register name. */
11961 case 'U': /* Destination register (CLO/CLZ). */
11962 case 'g': /* Coprocessor destination register. */
11963 gas_assert (!mips_opts
.micromips
);
11964 case 'b': /* Base register. */
11965 case 'd': /* Destination register. */
11966 case 's': /* Source register. */
11967 case 't': /* Target register. */
11968 case 'r': /* Both target and source. */
11969 case 'v': /* Both dest and source. */
11970 case 'w': /* Both dest and target. */
11971 case 'E': /* Coprocessor target register. */
11972 case 'K': /* RDHWR destination register. */
11973 case 'z': /* Must be zero register. */
11976 if (*args
== 'E' || *args
== 'K')
11977 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
11980 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
11981 if (regno
== AT
&& mips_opts
.at
)
11983 if (mips_opts
.at
== ATREG
)
11984 as_warn (_("Used $at without \".set noat\""));
11986 as_warn (_("Used $%u with \".set at=$%u\""),
11987 regno
, mips_opts
.at
);
11997 if (c
== 'r' || c
== 'v' || c
== 'w')
12004 /* 'z' only matches $0. */
12005 if (c
== 'z' && regno
!= 0)
12008 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12010 if (regno
== lastregno
)
12013 = _("Source and destination must be different");
12016 if (regno
== 31 && lastregno
== 0xffffffff)
12019 = _("A destination register must be supplied");
12023 /* Now that we have assembled one operand, we use the args
12024 string to figure out where it goes in the instruction. */
12031 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12035 if (mips_opts
.micromips
)
12036 INSERT_OPERAND (1, RS
, *ip
, regno
);
12038 INSERT_OPERAND (0, RD
, *ip
, regno
);
12043 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12047 gas_assert (!mips_opts
.micromips
);
12048 INSERT_OPERAND (0, RD
, *ip
, regno
);
12049 INSERT_OPERAND (0, RT
, *ip
, regno
);
12055 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12059 gas_assert (mips_opts
.micromips
);
12060 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12064 /* This case exists because on the r3000 trunc
12065 expands into a macro which requires a gp
12066 register. On the r6000 or r4000 it is
12067 assembled into a single instruction which
12068 ignores the register. Thus the insn version
12069 is MIPS_ISA2 and uses 'x', and the macro
12070 version is MIPS_ISA1 and uses 't'. */
12074 /* This case is for the div instruction, which
12075 acts differently if the destination argument
12076 is $0. This only matches $0, and is checked
12077 outside the switch. */
12087 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12091 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12096 case 'O': /* MDMX alignment immediate constant. */
12097 gas_assert (!mips_opts
.micromips
);
12098 my_getExpression (&imm_expr
, s
);
12099 check_absolute_expr (ip
, &imm_expr
);
12100 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12101 as_warn (_("Improper align amount (%ld), using low bits"),
12102 (long) imm_expr
.X_add_number
);
12103 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12104 imm_expr
.X_op
= O_absent
;
12108 case 'Q': /* MDMX vector, element sel, or const. */
12111 /* MDMX Immediate. */
12112 gas_assert (!mips_opts
.micromips
);
12113 my_getExpression (&imm_expr
, s
);
12114 check_absolute_expr (ip
, &imm_expr
);
12115 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12116 as_warn (_("Invalid MDMX Immediate (%ld)"),
12117 (long) imm_expr
.X_add_number
);
12118 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12119 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12120 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12122 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12123 imm_expr
.X_op
= O_absent
;
12127 /* Not MDMX Immediate. Fall through. */
12128 case 'X': /* MDMX destination register. */
12129 case 'Y': /* MDMX source register. */
12130 case 'Z': /* MDMX target register. */
12133 gas_assert (!mips_opts
.micromips
);
12134 case 'D': /* Floating point destination register. */
12135 case 'S': /* Floating point source register. */
12136 case 'T': /* Floating point target register. */
12137 case 'R': /* Floating point source register. */
12141 || (mips_opts
.ase_mdmx
12142 && (ip
->insn_mo
->pinfo
& FP_D
)
12143 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12144 | INSN_COPROC_MEMORY_DELAY
12145 | INSN_LOAD_COPROC_DELAY
12146 | INSN_LOAD_MEMORY_DELAY
12147 | INSN_STORE_MEMORY
))))
12148 rtype
|= RTYPE_VEC
;
12150 if (reg_lookup (&s
, rtype
, ®no
))
12152 if ((regno
& 1) != 0
12154 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12155 as_warn (_("Float register should be even, was %d"),
12163 if (c
== 'V' || c
== 'W')
12174 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12180 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12184 /* This is like 'Z', but also needs to fix the MDMX
12185 vector/scalar select bits. Note that the
12186 scalar immediate case is handled above. */
12189 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12190 int max_el
= (is_qh
? 3 : 7);
12192 my_getExpression(&imm_expr
, s
);
12193 check_absolute_expr (ip
, &imm_expr
);
12195 if (imm_expr
.X_add_number
> max_el
)
12196 as_bad (_("Bad element selector %ld"),
12197 (long) imm_expr
.X_add_number
);
12198 imm_expr
.X_add_number
&= max_el
;
12199 ip
->insn_opcode
|= (imm_expr
.X_add_number
12202 imm_expr
.X_op
= O_absent
;
12204 as_warn (_("Expecting ']' found '%s'"), s
);
12210 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12211 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12214 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12217 /* Fall through. */
12221 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12225 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12235 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12239 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12245 my_getExpression (&imm_expr
, s
);
12246 if (imm_expr
.X_op
!= O_big
12247 && imm_expr
.X_op
!= O_constant
)
12248 insn_error
= _("absolute expression required");
12249 if (HAVE_32BIT_GPRS
)
12250 normalize_constant_expr (&imm_expr
);
12255 my_getExpression (&offset_expr
, s
);
12256 normalize_address_expr (&offset_expr
);
12257 *imm_reloc
= BFD_RELOC_32
;
12270 unsigned char temp
[8];
12272 unsigned int length
;
12277 /* These only appear as the last operand in an
12278 instruction, and every instruction that accepts
12279 them in any variant accepts them in all variants.
12280 This means we don't have to worry about backing out
12281 any changes if the instruction does not match.
12283 The difference between them is the size of the
12284 floating point constant and where it goes. For 'F'
12285 and 'L' the constant is 64 bits; for 'f' and 'l' it
12286 is 32 bits. Where the constant is placed is based
12287 on how the MIPS assembler does things:
12290 f -- immediate value
12293 The .lit4 and .lit8 sections are only used if
12294 permitted by the -G argument.
12296 The code below needs to know whether the target register
12297 is 32 or 64 bits wide. It relies on the fact 'f' and
12298 'F' are used with GPR-based instructions and 'l' and
12299 'L' are used with FPR-based instructions. */
12301 f64
= *args
== 'F' || *args
== 'L';
12302 using_gprs
= *args
== 'F' || *args
== 'f';
12304 save_in
= input_line_pointer
;
12305 input_line_pointer
= s
;
12306 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12308 s
= input_line_pointer
;
12309 input_line_pointer
= save_in
;
12310 if (err
!= NULL
&& *err
!= '\0')
12312 as_bad (_("Bad floating point constant: %s"), err
);
12313 memset (temp
, '\0', sizeof temp
);
12314 length
= f64
? 8 : 4;
12317 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12321 && (g_switch_value
< 4
12322 || (temp
[0] == 0 && temp
[1] == 0)
12323 || (temp
[2] == 0 && temp
[3] == 0))))
12325 imm_expr
.X_op
= O_constant
;
12326 if (!target_big_endian
)
12327 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12329 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12331 else if (length
> 4
12332 && !mips_disable_float_construction
12333 /* Constants can only be constructed in GPRs and
12334 copied to FPRs if the GPRs are at least as wide
12335 as the FPRs. Force the constant into memory if
12336 we are using 64-bit FPRs but the GPRs are only
12339 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12340 && ((temp
[0] == 0 && temp
[1] == 0)
12341 || (temp
[2] == 0 && temp
[3] == 0))
12342 && ((temp
[4] == 0 && temp
[5] == 0)
12343 || (temp
[6] == 0 && temp
[7] == 0)))
12345 /* The value is simple enough to load with a couple of
12346 instructions. If using 32-bit registers, set
12347 imm_expr to the high order 32 bits and offset_expr to
12348 the low order 32 bits. Otherwise, set imm_expr to
12349 the entire 64 bit constant. */
12350 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12352 imm_expr
.X_op
= O_constant
;
12353 offset_expr
.X_op
= O_constant
;
12354 if (!target_big_endian
)
12356 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12357 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12361 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12362 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12364 if (offset_expr
.X_add_number
== 0)
12365 offset_expr
.X_op
= O_absent
;
12367 else if (sizeof (imm_expr
.X_add_number
) > 4)
12369 imm_expr
.X_op
= O_constant
;
12370 if (!target_big_endian
)
12371 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12373 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12377 imm_expr
.X_op
= O_big
;
12378 imm_expr
.X_add_number
= 4;
12379 if (!target_big_endian
)
12381 generic_bignum
[0] = bfd_getl16 (temp
);
12382 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12383 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12384 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12388 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12389 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12390 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12391 generic_bignum
[3] = bfd_getb16 (temp
);
12397 const char *newname
;
12400 /* Switch to the right section. */
12402 subseg
= now_subseg
;
12405 default: /* unused default case avoids warnings. */
12407 newname
= RDATA_SECTION_NAME
;
12408 if (g_switch_value
>= 8)
12412 newname
= RDATA_SECTION_NAME
;
12415 gas_assert (g_switch_value
>= 4);
12419 new_seg
= subseg_new (newname
, (subsegT
) 0);
12421 bfd_set_section_flags (stdoutput
, new_seg
,
12426 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12427 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12428 record_alignment (new_seg
, 4);
12430 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12431 if (seg
== now_seg
)
12432 as_bad (_("Can't use floating point insn in this section"));
12434 /* Set the argument to the current address in the
12436 offset_expr
.X_op
= O_symbol
;
12437 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12438 offset_expr
.X_add_number
= 0;
12440 /* Put the floating point number into the section. */
12441 p
= frag_more ((int) length
);
12442 memcpy (p
, temp
, length
);
12444 /* Switch back to the original section. */
12445 subseg_set (seg
, subseg
);
12450 case 'i': /* 16-bit unsigned immediate. */
12451 case 'j': /* 16-bit signed immediate. */
12452 *imm_reloc
= BFD_RELOC_LO16
;
12453 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12456 offsetT minval
, maxval
;
12458 more
= (insn
+ 1 < past
12459 && strcmp (insn
->name
, insn
[1].name
) == 0);
12461 /* If the expression was written as an unsigned number,
12462 only treat it as signed if there are no more
12466 && sizeof (imm_expr
.X_add_number
) <= 4
12467 && imm_expr
.X_op
== O_constant
12468 && imm_expr
.X_add_number
< 0
12469 && imm_expr
.X_unsigned
12470 && HAVE_64BIT_GPRS
)
12473 /* For compatibility with older assemblers, we accept
12474 0x8000-0xffff as signed 16-bit numbers when only
12475 signed numbers are allowed. */
12477 minval
= 0, maxval
= 0xffff;
12479 minval
= -0x8000, maxval
= 0x7fff;
12481 minval
= -0x8000, maxval
= 0xffff;
12483 if (imm_expr
.X_op
!= O_constant
12484 || imm_expr
.X_add_number
< minval
12485 || imm_expr
.X_add_number
> maxval
)
12489 if (imm_expr
.X_op
== O_constant
12490 || imm_expr
.X_op
== O_big
)
12491 as_bad (_("Expression out of range"));
12497 case 'o': /* 16-bit offset. */
12498 offset_reloc
[0] = BFD_RELOC_LO16
;
12499 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12500 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12502 /* Check whether there is only a single bracketed expression
12503 left. If so, it must be the base register and the
12504 constant must be zero. */
12505 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12507 offset_expr
.X_op
= O_constant
;
12508 offset_expr
.X_add_number
= 0;
12512 /* If this value won't fit into a 16 bit offset, then go
12513 find a macro that will generate the 32 bit offset
12515 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
12516 && (offset_expr
.X_op
!= O_constant
12517 || offset_expr
.X_add_number
>= 0x8000
12518 || offset_expr
.X_add_number
< -0x8000))
12524 case 'p': /* PC-relative offset. */
12525 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12526 my_getExpression (&offset_expr
, s
);
12530 case 'u': /* Upper 16 bits. */
12531 *imm_reloc
= BFD_RELOC_LO16
;
12532 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
12533 && imm_expr
.X_op
== O_constant
12534 && (imm_expr
.X_add_number
< 0
12535 || imm_expr
.X_add_number
>= 0x10000))
12536 as_bad (_("lui expression (%lu) not in range 0..65535"),
12537 (unsigned long) imm_expr
.X_add_number
);
12541 case 'a': /* 26-bit address. */
12542 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12543 my_getExpression (&offset_expr
, s
);
12547 case 'N': /* 3-bit branch condition code. */
12548 case 'M': /* 3-bit compare condition code. */
12550 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
12551 rtype
|= RTYPE_FCC
;
12552 if (!reg_lookup (&s
, rtype
, ®no
))
12554 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
12555 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
12556 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
12557 && (regno
& 1) != 0)
12558 as_warn (_("Condition code register should be even for %s, "
12561 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
12562 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
12563 && (regno
& 3) != 0)
12564 as_warn (_("Condition code register should be 0 or 4 for %s, "
12568 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
12570 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
12574 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
12585 while (ISDIGIT (*s
));
12588 c
= 8; /* Invalid sel value. */
12591 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12592 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
12596 gas_assert (!mips_opts
.micromips
);
12597 /* Must be at least one digit. */
12598 my_getExpression (&imm_expr
, s
);
12599 check_absolute_expr (ip
, &imm_expr
);
12601 if ((unsigned long) imm_expr
.X_add_number
12602 > (unsigned long) OP_MASK_VECBYTE
)
12604 as_bad (_("bad byte vector index (%ld)"),
12605 (long) imm_expr
.X_add_number
);
12606 imm_expr
.X_add_number
= 0;
12609 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
12610 imm_expr
.X_op
= O_absent
;
12615 gas_assert (!mips_opts
.micromips
);
12616 my_getExpression (&imm_expr
, s
);
12617 check_absolute_expr (ip
, &imm_expr
);
12619 if ((unsigned long) imm_expr
.X_add_number
12620 > (unsigned long) OP_MASK_VECALIGN
)
12622 as_bad (_("bad byte vector index (%ld)"),
12623 (long) imm_expr
.X_add_number
);
12624 imm_expr
.X_add_number
= 0;
12627 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
12628 imm_expr
.X_op
= O_absent
;
12632 case 'm': /* Opcode extension character. */
12633 gas_assert (mips_opts
.micromips
);
12638 if (strncmp (s
, "$pc", 3) == 0)
12666 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12667 if (regno
== AT
&& mips_opts
.at
)
12669 if (mips_opts
.at
== ATREG
)
12670 as_warn (_("Used $at without \".set noat\""));
12672 as_warn (_("Used $%u with \".set at=$%u\""),
12673 regno
, mips_opts
.at
);
12679 gas_assert (args
[1] == ',');
12685 gas_assert (args
[1] == ',');
12687 continue; /* Nothing to do. */
12693 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12695 if (regno
== lastregno
)
12698 = _("Source and destination must be different");
12701 if (regno
== 31 && lastregno
== 0xffffffff)
12704 = _("A destination register must be supplied");
12715 gas_assert (args
[1] == ',');
12722 gas_assert (args
[1] == ',');
12725 continue; /* Nothing to do. */
12729 /* Make sure regno is the same as lastregno. */
12730 if (c
== 't' && regno
!= lastregno
)
12733 /* Make sure regno is the same as destregno. */
12734 if (c
== 'x' && regno
!= destregno
)
12737 /* We need to save regno, before regno maps to the
12738 microMIPS register encoding. */
12748 regno
= ILLEGAL_REG
;
12752 regno
= mips32_to_micromips_reg_b_map
[regno
];
12756 regno
= mips32_to_micromips_reg_c_map
[regno
];
12760 regno
= mips32_to_micromips_reg_d_map
[regno
];
12764 regno
= mips32_to_micromips_reg_e_map
[regno
];
12768 regno
= mips32_to_micromips_reg_f_map
[regno
];
12772 regno
= mips32_to_micromips_reg_g_map
[regno
];
12776 regno
= mips32_to_micromips_reg_h_map
[regno
];
12780 switch (EXTRACT_OPERAND (1, MI
, *ip
))
12785 else if (regno
== 22)
12787 else if (regno
== 5)
12789 else if (regno
== 6)
12791 else if (regno
== 7)
12794 regno
= ILLEGAL_REG
;
12800 else if (regno
== 7)
12803 regno
= ILLEGAL_REG
;
12810 regno
= ILLEGAL_REG
;
12814 regno
= ILLEGAL_REG
;
12820 regno
= mips32_to_micromips_reg_l_map
[regno
];
12824 regno
= mips32_to_micromips_reg_m_map
[regno
];
12828 regno
= mips32_to_micromips_reg_n_map
[regno
];
12832 regno
= mips32_to_micromips_reg_q_map
[regno
];
12837 regno
= ILLEGAL_REG
;
12842 regno
= ILLEGAL_REG
;
12847 regno
= ILLEGAL_REG
;
12850 case 'j': /* Do nothing. */
12860 if (regno
== ILLEGAL_REG
)
12866 INSERT_OPERAND (1, MB
, *ip
, regno
);
12870 INSERT_OPERAND (1, MC
, *ip
, regno
);
12874 INSERT_OPERAND (1, MD
, *ip
, regno
);
12878 INSERT_OPERAND (1, ME
, *ip
, regno
);
12882 INSERT_OPERAND (1, MF
, *ip
, regno
);
12886 INSERT_OPERAND (1, MG
, *ip
, regno
);
12890 INSERT_OPERAND (1, MH
, *ip
, regno
);
12894 INSERT_OPERAND (1, MI
, *ip
, regno
);
12898 INSERT_OPERAND (1, MJ
, *ip
, regno
);
12902 INSERT_OPERAND (1, ML
, *ip
, regno
);
12906 INSERT_OPERAND (1, MM
, *ip
, regno
);
12910 INSERT_OPERAND (1, MN
, *ip
, regno
);
12914 INSERT_OPERAND (1, MP
, *ip
, regno
);
12918 INSERT_OPERAND (1, MQ
, *ip
, regno
);
12921 case 'a': /* Do nothing. */
12922 case 's': /* Do nothing. */
12923 case 't': /* Do nothing. */
12924 case 'x': /* Do nothing. */
12925 case 'y': /* Do nothing. */
12926 case 'z': /* Do nothing. */
12936 bfd_reloc_code_real_type r
[3];
12940 /* Check whether there is only a single bracketed
12941 expression left. If so, it must be the base register
12942 and the constant must be zero. */
12943 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12945 INSERT_OPERAND (1, IMMA
, *ip
, 0);
12949 if (my_getSmallExpression (&ep
, r
, s
) > 0
12950 || !expr_const_in_range (&ep
, -64, 64, 2))
12953 imm
= ep
.X_add_number
>> 2;
12954 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
12961 bfd_reloc_code_real_type r
[3];
12965 if (my_getSmallExpression (&ep
, r
, s
) > 0
12966 || ep
.X_op
!= O_constant
)
12969 for (imm
= 0; imm
< 8; imm
++)
12970 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
12975 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
12982 bfd_reloc_code_real_type r
[3];
12986 if (my_getSmallExpression (&ep
, r
, s
) > 0
12987 || ep
.X_op
!= O_constant
)
12990 for (imm
= 0; imm
< 16; imm
++)
12991 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
12996 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13001 case 'D': /* pc relative offset */
13002 case 'E': /* pc relative offset */
13003 my_getExpression (&offset_expr
, s
);
13004 if (offset_expr
.X_op
== O_register
)
13007 if (!forced_insn_length
)
13008 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13010 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13012 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13018 bfd_reloc_code_real_type r
[3];
13022 if (my_getSmallExpression (&ep
, r
, s
) > 0
13023 || !expr_const_in_range (&ep
, 0, 16, 0))
13026 imm
= ep
.X_add_number
;
13027 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13034 bfd_reloc_code_real_type r
[3];
13038 /* Check whether there is only a single bracketed
13039 expression left. If so, it must be the base register
13040 and the constant must be zero. */
13041 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13043 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13047 if (my_getSmallExpression (&ep
, r
, s
) > 0
13048 || !expr_const_in_range (&ep
, -1, 15, 0))
13051 imm
= ep
.X_add_number
& 15;
13052 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13059 bfd_reloc_code_real_type r
[3];
13063 /* Check whether there is only a single bracketed
13064 expression left. If so, it must be the base register
13065 and the constant must be zero. */
13066 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13068 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13072 if (my_getSmallExpression (&ep
, r
, s
) > 0
13073 || !expr_const_in_range (&ep
, 0, 16, 1))
13076 imm
= ep
.X_add_number
>> 1;
13077 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13084 bfd_reloc_code_real_type r
[3];
13088 if (my_getSmallExpression (&ep
, r
, s
) > 0
13089 || !expr_const_in_range (&ep
, -1, 127, 0))
13092 imm
= ep
.X_add_number
& 127;
13093 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13100 bfd_reloc_code_real_type r
[3];
13104 /* Check whether there is only a single bracketed
13105 expression left. If so, it must be the base register
13106 and the constant must be zero. */
13107 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13109 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13113 if (my_getSmallExpression (&ep
, r
, s
) > 0
13114 || !expr_const_in_range (&ep
, 0, 16, 2))
13117 imm
= ep
.X_add_number
>> 2;
13118 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13125 bfd_reloc_code_real_type r
[3];
13129 /* Check whether there is only a single bracketed
13130 expression left. If so, it must be the base register
13131 and the constant must be zero. */
13132 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13134 INSERT_OPERAND (1, IMML
, *ip
, 0);
13138 if (my_getSmallExpression (&ep
, r
, s
) > 0
13139 || !expr_const_in_range (&ep
, 0, 16, 0))
13142 imm
= ep
.X_add_number
;
13143 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13150 bfd_reloc_code_real_type r
[3];
13154 if (my_getSmallExpression (&ep
, r
, s
) > 0
13155 || !expr_const_in_range (&ep
, 1, 9, 0))
13158 imm
= ep
.X_add_number
& 7;
13159 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13164 case 'N': /* Register list for lwm and swm. */
13166 /* A comma-separated list of registers and/or
13167 dash-separated contiguous ranges including
13168 both ra and a set of one or more registers
13169 starting at s0 up to s3 which have to be
13176 and any permutations of these. */
13177 unsigned int reglist
;
13180 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13183 if ((reglist
& 0xfff1ffff) != 0x80010000)
13186 reglist
= (reglist
>> 17) & 7;
13188 if ((reglist
& -reglist
) != reglist
)
13191 imm
= ffs (reglist
) - 1;
13192 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13196 case 'O': /* sdbbp 4-bit code. */
13198 bfd_reloc_code_real_type r
[3];
13202 if (my_getSmallExpression (&ep
, r
, s
) > 0
13203 || !expr_const_in_range (&ep
, 0, 16, 0))
13206 imm
= ep
.X_add_number
;
13207 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13214 bfd_reloc_code_real_type r
[3];
13218 if (my_getSmallExpression (&ep
, r
, s
) > 0
13219 || !expr_const_in_range (&ep
, 0, 32, 2))
13222 imm
= ep
.X_add_number
>> 2;
13223 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13230 bfd_reloc_code_real_type r
[3];
13234 if (my_getSmallExpression (&ep
, r
, s
) > 0
13235 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13238 imm
= ep
.X_add_number
>> 2;
13239 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13246 bfd_reloc_code_real_type r
[3];
13250 /* Check whether there is only a single bracketed
13251 expression left. If so, it must be the base register
13252 and the constant must be zero. */
13253 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13255 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13259 if (my_getSmallExpression (&ep
, r
, s
) > 0
13260 || !expr_const_in_range (&ep
, 0, 32, 2))
13263 imm
= ep
.X_add_number
>> 2;
13264 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13271 bfd_reloc_code_real_type r
[3];
13275 if (my_getSmallExpression (&ep
, r
, s
) > 0
13276 || !expr_const_in_range (&ep
, 0, 64, 2))
13279 imm
= ep
.X_add_number
>> 2;
13280 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13287 bfd_reloc_code_real_type r
[3];
13291 if (my_getSmallExpression (&ep
, r
, s
) > 0
13292 || !expr_const_in_range (&ep
, -8, 8, 0))
13295 imm
= ep
.X_add_number
;
13296 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13303 bfd_reloc_code_real_type r
[3];
13307 if (my_getSmallExpression (&ep
, r
, s
) > 0
13308 || expr_const_in_range (&ep
, -2, 2, 2)
13309 || !expr_const_in_range (&ep
, -258, 258, 2))
13312 imm
= ep
.X_add_number
>> 2;
13313 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13314 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13321 bfd_reloc_code_real_type r
[3];
13324 if (my_getSmallExpression (&ep
, r
, s
) > 0
13325 || !expr_const_in_range (&ep
, 0, 1, 0))
13332 as_bad (_("Internal error: bad microMIPS opcode "
13333 "(unknown extension operand type `m%c'): %s %s"),
13334 *args
, insn
->name
, insn
->args
);
13335 /* Further processing is fruitless. */
13340 case 'n': /* Register list for 32-bit lwm and swm. */
13341 gas_assert (mips_opts
.micromips
);
13343 /* A comma-separated list of registers and/or
13344 dash-separated contiguous ranges including
13345 at least one of ra and a set of one or more
13346 registers starting at s0 up to s7 and then
13347 s8 which have to be consecutive, e.g.:
13355 and any permutations of these. */
13356 unsigned int reglist
;
13360 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13363 if ((reglist
& 0x3f00ffff) != 0)
13366 ra
= (reglist
>> 27) & 0x10;
13367 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13369 if ((reglist
& -reglist
) != reglist
)
13372 imm
= (ffs (reglist
) - 1) | ra
;
13373 INSERT_OPERAND (1, RT
, *ip
, imm
);
13374 imm_expr
.X_op
= O_absent
;
13378 case '|': /* 4-bit trap code. */
13379 gas_assert (mips_opts
.micromips
);
13380 my_getExpression (&imm_expr
, s
);
13381 check_absolute_expr (ip
, &imm_expr
);
13382 if ((unsigned long) imm_expr
.X_add_number
13383 > MICROMIPSOP_MASK_TRAP
)
13384 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13385 (unsigned long) imm_expr
.X_add_number
,
13386 ip
->insn_mo
->name
);
13387 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13388 imm_expr
.X_op
= O_absent
;
13393 as_bad (_("Bad char = '%c'\n"), *args
);
13398 /* Args don't match. */
13400 insn_error
= _("Illegal operands");
13401 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13406 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13408 gas_assert (firstinsn
);
13409 need_delay_slot_ok
= FALSE
;
13418 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13420 /* This routine assembles an instruction into its binary format when
13421 assembling for the mips16. As a side effect, it sets one of the
13422 global variables imm_reloc or offset_reloc to the type of relocation
13423 to do if one of the operands is an address expression. It also sets
13424 forced_insn_length to the resulting instruction size in bytes if the
13425 user explicitly requested a small or extended instruction. */
13428 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13432 struct mips_opcode
*insn
;
13434 unsigned int regno
;
13435 unsigned int lastregno
= 0;
13441 forced_insn_length
= 0;
13443 for (s
= str
; ISLOWER (*s
); ++s
)
13455 if (s
[1] == 't' && s
[2] == ' ')
13458 forced_insn_length
= 2;
13462 else if (s
[1] == 'e' && s
[2] == ' ')
13465 forced_insn_length
= 4;
13469 /* Fall through. */
13471 insn_error
= _("unknown opcode");
13475 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13476 forced_insn_length
= 2;
13478 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13480 insn_error
= _("unrecognized opcode");
13489 gas_assert (strcmp (insn
->name
, str
) == 0);
13491 ok
= is_opcode_valid_16 (insn
);
13494 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
13495 && strcmp (insn
->name
, insn
[1].name
) == 0)
13504 static char buf
[100];
13506 _("Opcode not supported on this processor: %s (%s)"),
13507 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
13508 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13515 create_insn (ip
, insn
);
13516 imm_expr
.X_op
= O_absent
;
13517 imm_reloc
[0] = BFD_RELOC_UNUSED
;
13518 imm_reloc
[1] = BFD_RELOC_UNUSED
;
13519 imm_reloc
[2] = BFD_RELOC_UNUSED
;
13520 imm2_expr
.X_op
= O_absent
;
13521 offset_expr
.X_op
= O_absent
;
13522 offset_reloc
[0] = BFD_RELOC_UNUSED
;
13523 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13524 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13525 for (args
= insn
->args
; 1; ++args
)
13532 /* In this switch statement we call break if we did not find
13533 a match, continue if we did find a match, or return if we
13544 /* Stuff the immediate value in now, if we can. */
13545 if (imm_expr
.X_op
== O_constant
13546 && *imm_reloc
> BFD_RELOC_UNUSED
13547 && insn
->pinfo
!= INSN_MACRO
13548 && calculate_reloc (*offset_reloc
,
13549 imm_expr
.X_add_number
, &value
))
13551 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
13552 *offset_reloc
, value
, forced_insn_length
,
13554 imm_expr
.X_op
= O_absent
;
13555 *imm_reloc
= BFD_RELOC_UNUSED
;
13556 *offset_reloc
= BFD_RELOC_UNUSED
;
13570 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13573 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13589 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13591 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13595 /* Fall through. */
13606 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
13608 if (c
== 'v' || c
== 'w')
13611 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
13613 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
13624 if (c
== 'v' || c
== 'w')
13626 regno
= mips16_to_32_reg_map
[lastregno
];
13640 regno
= mips32_to_16_reg_map
[regno
];
13645 regno
= ILLEGAL_REG
;
13650 regno
= ILLEGAL_REG
;
13655 regno
= ILLEGAL_REG
;
13660 if (regno
== AT
&& mips_opts
.at
)
13662 if (mips_opts
.at
== ATREG
)
13663 as_warn (_("used $at without \".set noat\""));
13665 as_warn (_("used $%u with \".set at=$%u\""),
13666 regno
, mips_opts
.at
);
13674 if (regno
== ILLEGAL_REG
)
13681 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
13685 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
13688 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
13691 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
13697 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
13700 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
13701 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
13711 if (strncmp (s
, "$pc", 3) == 0)
13728 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
13731 if (imm_expr
.X_op
!= O_constant
)
13733 forced_insn_length
= 4;
13734 ip
->insn_opcode
|= MIPS16_EXTEND
;
13738 /* We need to relax this instruction. */
13739 *offset_reloc
= *imm_reloc
;
13740 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13745 *imm_reloc
= BFD_RELOC_UNUSED
;
13746 /* Fall through. */
13753 my_getExpression (&imm_expr
, s
);
13754 if (imm_expr
.X_op
== O_register
)
13756 /* What we thought was an expression turned out to
13759 if (s
[0] == '(' && args
[1] == '(')
13761 /* It looks like the expression was omitted
13762 before a register indirection, which means
13763 that the expression is implicitly zero. We
13764 still set up imm_expr, so that we handle
13765 explicit extensions correctly. */
13766 imm_expr
.X_op
= O_constant
;
13767 imm_expr
.X_add_number
= 0;
13768 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13775 /* We need to relax this instruction. */
13776 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13785 /* We use offset_reloc rather than imm_reloc for the PC
13786 relative operands. This lets macros with both
13787 immediate and address operands work correctly. */
13788 my_getExpression (&offset_expr
, s
);
13790 if (offset_expr
.X_op
== O_register
)
13793 /* We need to relax this instruction. */
13794 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13798 case '6': /* break code */
13799 my_getExpression (&imm_expr
, s
);
13800 check_absolute_expr (ip
, &imm_expr
);
13801 if ((unsigned long) imm_expr
.X_add_number
> 63)
13802 as_warn (_("Invalid value for `%s' (%lu)"),
13804 (unsigned long) imm_expr
.X_add_number
);
13805 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
13806 imm_expr
.X_op
= O_absent
;
13810 case 'a': /* 26 bit address */
13811 my_getExpression (&offset_expr
, s
);
13813 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13814 ip
->insn_opcode
<<= 16;
13817 case 'l': /* register list for entry macro */
13818 case 'L': /* register list for exit macro */
13828 unsigned int freg
, reg1
, reg2
;
13830 while (*s
== ' ' || *s
== ',')
13832 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13834 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
13838 as_bad (_("can't parse register list"));
13848 if (!reg_lookup (&s
, freg
? RTYPE_FPU
13849 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
13851 as_bad (_("invalid register list"));
13855 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
13857 mask
&= ~ (7 << 3);
13860 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
13862 mask
&= ~ (7 << 3);
13865 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
13866 mask
|= (reg2
- 3) << 3;
13867 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
13868 mask
|= (reg2
- 15) << 1;
13869 else if (reg1
== RA
&& reg2
== RA
)
13873 as_bad (_("invalid register list"));
13877 /* The mask is filled in in the opcode table for the
13878 benefit of the disassembler. We remove it before
13879 applying the actual mask. */
13880 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
13881 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
13885 case 'm': /* Register list for save insn. */
13886 case 'M': /* Register list for restore insn. */
13888 int opcode
= ip
->insn_opcode
;
13889 int framesz
= 0, seen_framesz
= 0;
13890 int nargs
= 0, statics
= 0, sregs
= 0;
13894 unsigned int reg1
, reg2
;
13896 SKIP_SPACE_TABS (s
);
13899 SKIP_SPACE_TABS (s
);
13901 my_getExpression (&imm_expr
, s
);
13902 if (imm_expr
.X_op
== O_constant
)
13904 /* Handle the frame size. */
13907 as_bad (_("more than one frame size in list"));
13911 framesz
= imm_expr
.X_add_number
;
13912 imm_expr
.X_op
= O_absent
;
13917 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
13919 as_bad (_("can't parse register list"));
13931 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
13934 as_bad (_("can't parse register list"));
13939 while (reg1
<= reg2
)
13941 if (reg1
>= 4 && reg1
<= 7)
13945 nargs
|= 1 << (reg1
- 4);
13947 /* statics $a0-$a3 */
13948 statics
|= 1 << (reg1
- 4);
13950 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
13953 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
13955 else if (reg1
== 31)
13957 /* Add $ra to insn. */
13962 as_bad (_("unexpected register in list"));
13970 /* Encode args/statics combination. */
13971 if (nargs
& statics
)
13972 as_bad (_("arg/static registers overlap"));
13973 else if (nargs
== 0xf)
13974 /* All $a0-$a3 are args. */
13975 opcode
|= MIPS16_ALL_ARGS
<< 16;
13976 else if (statics
== 0xf)
13977 /* All $a0-$a3 are statics. */
13978 opcode
|= MIPS16_ALL_STATICS
<< 16;
13981 int narg
= 0, nstat
= 0;
13983 /* Count arg registers. */
13984 while (nargs
& 0x1)
13990 as_bad (_("invalid arg register list"));
13992 /* Count static registers. */
13993 while (statics
& 0x8)
13995 statics
= (statics
<< 1) & 0xf;
13999 as_bad (_("invalid static register list"));
14001 /* Encode args/statics. */
14002 opcode
|= ((narg
<< 2) | nstat
) << 16;
14005 /* Encode $s0/$s1. */
14006 if (sregs
& (1 << 0)) /* $s0 */
14008 if (sregs
& (1 << 1)) /* $s1 */
14014 /* Count regs $s2-$s8. */
14022 as_bad (_("invalid static register list"));
14023 /* Encode $s2-$s8. */
14024 opcode
|= nsreg
<< 24;
14027 /* Encode frame size. */
14029 as_bad (_("missing frame size"));
14030 else if ((framesz
& 7) != 0 || framesz
< 0
14031 || framesz
> 0xff * 8)
14032 as_bad (_("invalid frame size"));
14033 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14036 opcode
|= (((framesz
& 0xf0) << 16)
14037 | (framesz
& 0x0f));
14040 /* Finally build the instruction. */
14041 if ((opcode
>> 16) != 0 || framesz
== 0)
14042 opcode
|= MIPS16_EXTEND
;
14043 ip
->insn_opcode
= opcode
;
14047 case 'e': /* extend code */
14048 my_getExpression (&imm_expr
, s
);
14049 check_absolute_expr (ip
, &imm_expr
);
14050 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14052 as_warn (_("Invalid value for `%s' (%lu)"),
14054 (unsigned long) imm_expr
.X_add_number
);
14055 imm_expr
.X_add_number
&= 0x7ff;
14057 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14058 imm_expr
.X_op
= O_absent
;
14068 /* Args don't match. */
14069 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14070 strcmp (insn
->name
, insn
[1].name
) == 0)
14077 insn_error
= _("illegal operands");
14083 /* This structure holds information we know about a mips16 immediate
14086 struct mips16_immed_operand
14088 /* The type code used in the argument string in the opcode table. */
14090 /* The number of bits in the short form of the opcode. */
14092 /* The number of bits in the extended form of the opcode. */
14094 /* The amount by which the short form is shifted when it is used;
14095 for example, the sw instruction has a shift count of 2. */
14097 /* The amount by which the short form is shifted when it is stored
14098 into the instruction code. */
14100 /* Non-zero if the short form is unsigned. */
14102 /* Non-zero if the extended form is unsigned. */
14104 /* Non-zero if the value is PC relative. */
14108 /* The mips16 immediate operand types. */
14110 static const struct mips16_immed_operand mips16_immed_operands
[] =
14112 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14113 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14114 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14115 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14116 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14117 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14118 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14119 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14120 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14121 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14122 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14123 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14124 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14125 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14126 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14127 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14128 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14129 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14130 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14131 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14132 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14135 #define MIPS16_NUM_IMMED \
14136 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14138 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14139 NBITS is the number of significant bits in VAL. */
14141 static unsigned long
14142 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14147 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14150 else if (nbits
== 15)
14152 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14157 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14160 return (extval
<< 16) | val
;
14163 /* Install immediate value VAL into MIPS16 instruction *INSN,
14164 extending it if necessary. The instruction in *INSN may
14165 already be extended.
14167 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14168 if none. In the former case, VAL is a 16-bit number with no
14169 defined signedness.
14171 TYPE is the type of the immediate field. USER_INSN_LENGTH
14172 is the length that the user requested, or 0 if none. */
14175 mips16_immed (char *file
, unsigned int line
, int type
,
14176 bfd_reloc_code_real_type reloc
, offsetT val
,
14177 unsigned int user_insn_length
, unsigned long *insn
)
14179 const struct mips16_immed_operand
*op
;
14180 int mintiny
, maxtiny
;
14182 op
= mips16_immed_operands
;
14183 while (op
->type
!= type
)
14186 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14191 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14194 maxtiny
= 1 << op
->nbits
;
14199 maxtiny
= (1 << op
->nbits
) - 1;
14201 if (reloc
!= BFD_RELOC_UNUSED
)
14206 mintiny
= - (1 << (op
->nbits
- 1));
14207 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14208 if (reloc
!= BFD_RELOC_UNUSED
)
14209 val
= SEXT_16BIT (val
);
14212 /* Branch offsets have an implicit 0 in the lowest bit. */
14213 if (type
== 'p' || type
== 'q')
14216 if ((val
& ((1 << op
->shift
) - 1)) != 0
14217 || val
< (mintiny
<< op
->shift
)
14218 || val
> (maxtiny
<< op
->shift
))
14220 /* We need an extended instruction. */
14221 if (user_insn_length
== 2)
14222 as_bad_where (file
, line
, _("invalid unextended operand value"));
14224 *insn
|= MIPS16_EXTEND
;
14226 else if (user_insn_length
== 4)
14228 /* The operand doesn't force an unextended instruction to be extended.
14229 Warn if the user wanted an extended instruction anyway. */
14230 *insn
|= MIPS16_EXTEND
;
14231 as_warn_where (file
, line
,
14232 _("extended operand requested but not required"));
14235 if (mips16_opcode_length (*insn
) == 2)
14239 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14240 insnval
<<= op
->op_shift
;
14245 long minext
, maxext
;
14247 if (reloc
== BFD_RELOC_UNUSED
)
14252 maxext
= (1 << op
->extbits
) - 1;
14256 minext
= - (1 << (op
->extbits
- 1));
14257 maxext
= (1 << (op
->extbits
- 1)) - 1;
14259 if (val
< minext
|| val
> maxext
)
14260 as_bad_where (file
, line
,
14261 _("operand value out of range for instruction"));
14264 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14268 struct percent_op_match
14271 bfd_reloc_code_real_type reloc
;
14274 static const struct percent_op_match mips_percent_op
[] =
14276 {"%lo", BFD_RELOC_LO16
},
14278 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14279 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14280 {"%call16", BFD_RELOC_MIPS_CALL16
},
14281 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14282 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14283 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14284 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14285 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14286 {"%got", BFD_RELOC_MIPS_GOT16
},
14287 {"%gp_rel", BFD_RELOC_GPREL16
},
14288 {"%half", BFD_RELOC_16
},
14289 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14290 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14291 {"%neg", BFD_RELOC_MIPS_SUB
},
14292 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14293 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14294 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14295 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14296 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14297 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14298 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14300 {"%hi", BFD_RELOC_HI16_S
}
14303 static const struct percent_op_match mips16_percent_op
[] =
14305 {"%lo", BFD_RELOC_MIPS16_LO16
},
14306 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14307 {"%got", BFD_RELOC_MIPS16_GOT16
},
14308 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14309 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14310 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14311 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14312 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14313 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14314 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14315 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14316 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14320 /* Return true if *STR points to a relocation operator. When returning true,
14321 move *STR over the operator and store its relocation code in *RELOC.
14322 Leave both *STR and *RELOC alone when returning false. */
14325 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14327 const struct percent_op_match
*percent_op
;
14330 if (mips_opts
.mips16
)
14332 percent_op
= mips16_percent_op
;
14333 limit
= ARRAY_SIZE (mips16_percent_op
);
14337 percent_op
= mips_percent_op
;
14338 limit
= ARRAY_SIZE (mips_percent_op
);
14341 for (i
= 0; i
< limit
; i
++)
14342 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14344 int len
= strlen (percent_op
[i
].str
);
14346 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14349 *str
+= strlen (percent_op
[i
].str
);
14350 *reloc
= percent_op
[i
].reloc
;
14352 /* Check whether the output BFD supports this relocation.
14353 If not, issue an error and fall back on something safe. */
14354 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14356 as_bad (_("relocation %s isn't supported by the current ABI"),
14357 percent_op
[i
].str
);
14358 *reloc
= BFD_RELOC_UNUSED
;
14366 /* Parse string STR as a 16-bit relocatable operand. Store the
14367 expression in *EP and the relocations in the array starting
14368 at RELOC. Return the number of relocation operators used.
14370 On exit, EXPR_END points to the first character after the expression. */
14373 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14376 bfd_reloc_code_real_type reversed_reloc
[3];
14377 size_t reloc_index
, i
;
14378 int crux_depth
, str_depth
;
14381 /* Search for the start of the main expression, recoding relocations
14382 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14383 of the main expression and with CRUX_DEPTH containing the number
14384 of open brackets at that point. */
14391 crux_depth
= str_depth
;
14393 /* Skip over whitespace and brackets, keeping count of the number
14395 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14400 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14401 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14403 my_getExpression (ep
, crux
);
14406 /* Match every open bracket. */
14407 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14411 if (crux_depth
> 0)
14412 as_bad (_("unclosed '('"));
14416 if (reloc_index
!= 0)
14418 prev_reloc_op_frag
= frag_now
;
14419 for (i
= 0; i
< reloc_index
; i
++)
14420 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14423 return reloc_index
;
14427 my_getExpression (expressionS
*ep
, char *str
)
14431 save_in
= input_line_pointer
;
14432 input_line_pointer
= str
;
14434 expr_end
= input_line_pointer
;
14435 input_line_pointer
= save_in
;
14439 md_atof (int type
, char *litP
, int *sizeP
)
14441 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14445 md_number_to_chars (char *buf
, valueT val
, int n
)
14447 if (target_big_endian
)
14448 number_to_chars_bigendian (buf
, val
, n
);
14450 number_to_chars_littleendian (buf
, val
, n
);
14454 static int support_64bit_objects(void)
14456 const char **list
, **l
;
14459 list
= bfd_target_list ();
14460 for (l
= list
; *l
!= NULL
; l
++)
14461 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14462 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14464 yes
= (*l
!= NULL
);
14468 #endif /* OBJ_ELF */
14470 const char *md_shortopts
= "O::g::G:";
14474 OPTION_MARCH
= OPTION_MD_BASE
,
14496 OPTION_NO_SMARTMIPS
,
14500 OPTION_NO_MICROMIPS
,
14503 OPTION_COMPAT_ARCH_BASE
,
14512 OPTION_M7000_HILO_FIX
,
14513 OPTION_MNO_7000_HILO_FIX
,
14516 OPTION_FIX_LOONGSON2F_JUMP
,
14517 OPTION_NO_FIX_LOONGSON2F_JUMP
,
14518 OPTION_FIX_LOONGSON2F_NOP
,
14519 OPTION_NO_FIX_LOONGSON2F_NOP
,
14521 OPTION_NO_FIX_VR4120
,
14523 OPTION_NO_FIX_VR4130
,
14524 OPTION_FIX_CN63XXP1
,
14525 OPTION_NO_FIX_CN63XXP1
,
14532 OPTION_CONSTRUCT_FLOATS
,
14533 OPTION_NO_CONSTRUCT_FLOATS
,
14536 OPTION_RELAX_BRANCH
,
14537 OPTION_NO_RELAX_BRANCH
,
14544 OPTION_SINGLE_FLOAT
,
14545 OPTION_DOUBLE_FLOAT
,
14548 OPTION_CALL_SHARED
,
14549 OPTION_CALL_NONPIC
,
14559 OPTION_MVXWORKS_PIC
,
14560 #endif /* OBJ_ELF */
14564 struct option md_longopts
[] =
14566 /* Options which specify architecture. */
14567 {"march", required_argument
, NULL
, OPTION_MARCH
},
14568 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14569 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
14570 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
14571 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
14572 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
14573 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
14574 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
14575 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
14576 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
14577 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
14578 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
14580 /* Options which specify Application Specific Extensions (ASEs). */
14581 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
14582 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
14583 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
14584 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
14585 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
14586 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
14587 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
14588 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
14589 {"mmt", no_argument
, NULL
, OPTION_MT
},
14590 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
14591 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
14592 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
14593 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
14594 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
14595 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
14596 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
14597 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
14598 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
14600 /* Old-style architecture options. Don't add more of these. */
14601 {"m4650", no_argument
, NULL
, OPTION_M4650
},
14602 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
14603 {"m4010", no_argument
, NULL
, OPTION_M4010
},
14604 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
14605 {"m4100", no_argument
, NULL
, OPTION_M4100
},
14606 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
14607 {"m3900", no_argument
, NULL
, OPTION_M3900
},
14608 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
14610 /* Options which enable bug fixes. */
14611 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
14612 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14613 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
14614 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
14615 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
14616 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
14617 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
14618 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
14619 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
14620 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
14621 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
14622 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
14623 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
14624 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
14625 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
14627 /* Miscellaneous options. */
14628 {"trap", no_argument
, NULL
, OPTION_TRAP
},
14629 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
14630 {"break", no_argument
, NULL
, OPTION_BREAK
},
14631 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
14632 {"EB", no_argument
, NULL
, OPTION_EB
},
14633 {"EL", no_argument
, NULL
, OPTION_EL
},
14634 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
14635 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
14636 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
14637 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
14638 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
14639 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
14640 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
14641 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
14642 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14643 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
14644 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
14645 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
14646 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
14647 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
14648 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
14649 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
14651 /* Strictly speaking this next option is ELF specific,
14652 but we allow it for other ports as well in order to
14653 make testing easier. */
14654 {"32", no_argument
, NULL
, OPTION_32
},
14656 /* ELF-specific options. */
14658 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
14659 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
14660 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
14661 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
14662 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
14663 {"mabi", required_argument
, NULL
, OPTION_MABI
},
14664 {"n32", no_argument
, NULL
, OPTION_N32
},
14665 {"64", no_argument
, NULL
, OPTION_64
},
14666 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
14667 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
14668 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
14669 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
14670 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
14671 #endif /* OBJ_ELF */
14673 {NULL
, no_argument
, NULL
, 0}
14675 size_t md_longopts_size
= sizeof (md_longopts
);
14677 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14678 NEW_VALUE. Warn if another value was already specified. Note:
14679 we have to defer parsing the -march and -mtune arguments in order
14680 to handle 'from-abi' correctly, since the ABI might be specified
14681 in a later argument. */
14684 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14686 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14687 as_warn (_("A different %s was already specified, is now %s"),
14688 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14691 *string_ptr
= new_value
;
14695 md_parse_option (int c
, char *arg
)
14699 case OPTION_CONSTRUCT_FLOATS
:
14700 mips_disable_float_construction
= 0;
14703 case OPTION_NO_CONSTRUCT_FLOATS
:
14704 mips_disable_float_construction
= 1;
14716 target_big_endian
= 1;
14720 target_big_endian
= 0;
14726 else if (arg
[0] == '0')
14728 else if (arg
[0] == '1')
14738 mips_debug
= atoi (arg
);
14742 file_mips_isa
= ISA_MIPS1
;
14746 file_mips_isa
= ISA_MIPS2
;
14750 file_mips_isa
= ISA_MIPS3
;
14754 file_mips_isa
= ISA_MIPS4
;
14758 file_mips_isa
= ISA_MIPS5
;
14761 case OPTION_MIPS32
:
14762 file_mips_isa
= ISA_MIPS32
;
14765 case OPTION_MIPS32R2
:
14766 file_mips_isa
= ISA_MIPS32R2
;
14769 case OPTION_MIPS64R2
:
14770 file_mips_isa
= ISA_MIPS64R2
;
14773 case OPTION_MIPS64
:
14774 file_mips_isa
= ISA_MIPS64
;
14778 mips_set_option_string (&mips_tune_string
, arg
);
14782 mips_set_option_string (&mips_arch_string
, arg
);
14786 mips_set_option_string (&mips_arch_string
, "4650");
14787 mips_set_option_string (&mips_tune_string
, "4650");
14790 case OPTION_NO_M4650
:
14794 mips_set_option_string (&mips_arch_string
, "4010");
14795 mips_set_option_string (&mips_tune_string
, "4010");
14798 case OPTION_NO_M4010
:
14802 mips_set_option_string (&mips_arch_string
, "4100");
14803 mips_set_option_string (&mips_tune_string
, "4100");
14806 case OPTION_NO_M4100
:
14810 mips_set_option_string (&mips_arch_string
, "3900");
14811 mips_set_option_string (&mips_tune_string
, "3900");
14814 case OPTION_NO_M3900
:
14818 mips_opts
.ase_mdmx
= 1;
14821 case OPTION_NO_MDMX
:
14822 mips_opts
.ase_mdmx
= 0;
14826 mips_opts
.ase_dsp
= 1;
14827 mips_opts
.ase_dspr2
= 0;
14830 case OPTION_NO_DSP
:
14831 mips_opts
.ase_dsp
= 0;
14832 mips_opts
.ase_dspr2
= 0;
14836 mips_opts
.ase_dspr2
= 1;
14837 mips_opts
.ase_dsp
= 1;
14840 case OPTION_NO_DSPR2
:
14841 mips_opts
.ase_dspr2
= 0;
14842 mips_opts
.ase_dsp
= 0;
14846 mips_opts
.ase_mt
= 1;
14850 mips_opts
.ase_mt
= 0;
14854 mips_opts
.ase_mcu
= 1;
14857 case OPTION_NO_MCU
:
14858 mips_opts
.ase_mcu
= 0;
14861 case OPTION_MICROMIPS
:
14862 if (mips_opts
.mips16
== 1)
14864 as_bad (_("-mmicromips cannot be used with -mips16"));
14867 mips_opts
.micromips
= 1;
14868 mips_no_prev_insn ();
14871 case OPTION_NO_MICROMIPS
:
14872 mips_opts
.micromips
= 0;
14873 mips_no_prev_insn ();
14876 case OPTION_MIPS16
:
14877 if (mips_opts
.micromips
== 1)
14879 as_bad (_("-mips16 cannot be used with -micromips"));
14882 mips_opts
.mips16
= 1;
14883 mips_no_prev_insn ();
14886 case OPTION_NO_MIPS16
:
14887 mips_opts
.mips16
= 0;
14888 mips_no_prev_insn ();
14891 case OPTION_MIPS3D
:
14892 mips_opts
.ase_mips3d
= 1;
14895 case OPTION_NO_MIPS3D
:
14896 mips_opts
.ase_mips3d
= 0;
14899 case OPTION_SMARTMIPS
:
14900 mips_opts
.ase_smartmips
= 1;
14903 case OPTION_NO_SMARTMIPS
:
14904 mips_opts
.ase_smartmips
= 0;
14907 case OPTION_FIX_24K
:
14911 case OPTION_NO_FIX_24K
:
14915 case OPTION_FIX_LOONGSON2F_JUMP
:
14916 mips_fix_loongson2f_jump
= TRUE
;
14919 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14920 mips_fix_loongson2f_jump
= FALSE
;
14923 case OPTION_FIX_LOONGSON2F_NOP
:
14924 mips_fix_loongson2f_nop
= TRUE
;
14927 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14928 mips_fix_loongson2f_nop
= FALSE
;
14931 case OPTION_FIX_VR4120
:
14932 mips_fix_vr4120
= 1;
14935 case OPTION_NO_FIX_VR4120
:
14936 mips_fix_vr4120
= 0;
14939 case OPTION_FIX_VR4130
:
14940 mips_fix_vr4130
= 1;
14943 case OPTION_NO_FIX_VR4130
:
14944 mips_fix_vr4130
= 0;
14947 case OPTION_FIX_CN63XXP1
:
14948 mips_fix_cn63xxp1
= TRUE
;
14951 case OPTION_NO_FIX_CN63XXP1
:
14952 mips_fix_cn63xxp1
= FALSE
;
14955 case OPTION_RELAX_BRANCH
:
14956 mips_relax_branch
= 1;
14959 case OPTION_NO_RELAX_BRANCH
:
14960 mips_relax_branch
= 0;
14963 case OPTION_MSHARED
:
14964 mips_in_shared
= TRUE
;
14967 case OPTION_MNO_SHARED
:
14968 mips_in_shared
= FALSE
;
14971 case OPTION_MSYM32
:
14972 mips_opts
.sym32
= TRUE
;
14975 case OPTION_MNO_SYM32
:
14976 mips_opts
.sym32
= FALSE
;
14980 /* When generating ELF code, we permit -KPIC and -call_shared to
14981 select SVR4_PIC, and -non_shared to select no PIC. This is
14982 intended to be compatible with Irix 5. */
14983 case OPTION_CALL_SHARED
:
14986 as_bad (_("-call_shared is supported only for ELF format"));
14989 mips_pic
= SVR4_PIC
;
14990 mips_abicalls
= TRUE
;
14993 case OPTION_CALL_NONPIC
:
14996 as_bad (_("-call_nonpic is supported only for ELF format"));
15000 mips_abicalls
= TRUE
;
15003 case OPTION_NON_SHARED
:
15006 as_bad (_("-non_shared is supported only for ELF format"));
15010 mips_abicalls
= FALSE
;
15013 /* The -xgot option tells the assembler to use 32 bit offsets
15014 when accessing the got in SVR4_PIC mode. It is for Irix
15019 #endif /* OBJ_ELF */
15022 g_switch_value
= atoi (arg
);
15026 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15030 mips_abi
= O32_ABI
;
15031 /* We silently ignore -32 for non-ELF targets. This greatly
15032 simplifies the construction of the MIPS GAS test cases. */
15039 as_bad (_("-n32 is supported for ELF format only"));
15042 mips_abi
= N32_ABI
;
15048 as_bad (_("-64 is supported for ELF format only"));
15051 mips_abi
= N64_ABI
;
15052 if (!support_64bit_objects())
15053 as_fatal (_("No compiled in support for 64 bit object file format"));
15055 #endif /* OBJ_ELF */
15058 file_mips_gp32
= 1;
15062 file_mips_gp32
= 0;
15066 file_mips_fp32
= 1;
15070 file_mips_fp32
= 0;
15073 case OPTION_SINGLE_FLOAT
:
15074 file_mips_single_float
= 1;
15077 case OPTION_DOUBLE_FLOAT
:
15078 file_mips_single_float
= 0;
15081 case OPTION_SOFT_FLOAT
:
15082 file_mips_soft_float
= 1;
15085 case OPTION_HARD_FLOAT
:
15086 file_mips_soft_float
= 0;
15093 as_bad (_("-mabi is supported for ELF format only"));
15096 if (strcmp (arg
, "32") == 0)
15097 mips_abi
= O32_ABI
;
15098 else if (strcmp (arg
, "o64") == 0)
15099 mips_abi
= O64_ABI
;
15100 else if (strcmp (arg
, "n32") == 0)
15101 mips_abi
= N32_ABI
;
15102 else if (strcmp (arg
, "64") == 0)
15104 mips_abi
= N64_ABI
;
15105 if (! support_64bit_objects())
15106 as_fatal (_("No compiled in support for 64 bit object file "
15109 else if (strcmp (arg
, "eabi") == 0)
15110 mips_abi
= EABI_ABI
;
15113 as_fatal (_("invalid abi -mabi=%s"), arg
);
15117 #endif /* OBJ_ELF */
15119 case OPTION_M7000_HILO_FIX
:
15120 mips_7000_hilo_fix
= TRUE
;
15123 case OPTION_MNO_7000_HILO_FIX
:
15124 mips_7000_hilo_fix
= FALSE
;
15128 case OPTION_MDEBUG
:
15129 mips_flag_mdebug
= TRUE
;
15132 case OPTION_NO_MDEBUG
:
15133 mips_flag_mdebug
= FALSE
;
15137 mips_flag_pdr
= TRUE
;
15140 case OPTION_NO_PDR
:
15141 mips_flag_pdr
= FALSE
;
15144 case OPTION_MVXWORKS_PIC
:
15145 mips_pic
= VXWORKS_PIC
;
15147 #endif /* OBJ_ELF */
15153 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15158 /* Set up globals to generate code for the ISA or processor
15159 described by INFO. */
15162 mips_set_architecture (const struct mips_cpu_info
*info
)
15166 file_mips_arch
= info
->cpu
;
15167 mips_opts
.arch
= info
->cpu
;
15168 mips_opts
.isa
= info
->isa
;
15173 /* Likewise for tuning. */
15176 mips_set_tune (const struct mips_cpu_info
*info
)
15179 mips_tune
= info
->cpu
;
15184 mips_after_parse_args (void)
15186 const struct mips_cpu_info
*arch_info
= 0;
15187 const struct mips_cpu_info
*tune_info
= 0;
15189 /* GP relative stuff not working for PE */
15190 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15192 if (g_switch_seen
&& g_switch_value
!= 0)
15193 as_bad (_("-G not supported in this configuration."));
15194 g_switch_value
= 0;
15197 if (mips_abi
== NO_ABI
)
15198 mips_abi
= MIPS_DEFAULT_ABI
;
15200 /* The following code determines the architecture and register size.
15201 Similar code was added to GCC 3.3 (see override_options() in
15202 config/mips/mips.c). The GAS and GCC code should be kept in sync
15203 as much as possible. */
15205 if (mips_arch_string
!= 0)
15206 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15208 if (file_mips_isa
!= ISA_UNKNOWN
)
15210 /* Handle -mipsN. At this point, file_mips_isa contains the
15211 ISA level specified by -mipsN, while arch_info->isa contains
15212 the -march selection (if any). */
15213 if (arch_info
!= 0)
15215 /* -march takes precedence over -mipsN, since it is more descriptive.
15216 There's no harm in specifying both as long as the ISA levels
15218 if (file_mips_isa
!= arch_info
->isa
)
15219 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15220 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15221 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15224 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15227 if (arch_info
== 0)
15229 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15230 gas_assert (arch_info
);
15233 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15234 as_bad (_("-march=%s is not compatible with the selected ABI"),
15237 mips_set_architecture (arch_info
);
15239 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15240 if (mips_tune_string
!= 0)
15241 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15243 if (tune_info
== 0)
15244 mips_set_tune (arch_info
);
15246 mips_set_tune (tune_info
);
15248 if (file_mips_gp32
>= 0)
15250 /* The user specified the size of the integer registers. Make sure
15251 it agrees with the ABI and ISA. */
15252 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15253 as_bad (_("-mgp64 used with a 32-bit processor"));
15254 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15255 as_bad (_("-mgp32 used with a 64-bit ABI"));
15256 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15257 as_bad (_("-mgp64 used with a 32-bit ABI"));
15261 /* Infer the integer register size from the ABI and processor.
15262 Restrict ourselves to 32-bit registers if that's all the
15263 processor has, or if the ABI cannot handle 64-bit registers. */
15264 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15265 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15268 switch (file_mips_fp32
)
15272 /* No user specified float register size.
15273 ??? GAS treats single-float processors as though they had 64-bit
15274 float registers (although it complains when double-precision
15275 instructions are used). As things stand, saying they have 32-bit
15276 registers would lead to spurious "register must be even" messages.
15277 So here we assume float registers are never smaller than the
15279 if (file_mips_gp32
== 0)
15280 /* 64-bit integer registers implies 64-bit float registers. */
15281 file_mips_fp32
= 0;
15282 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
15283 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15284 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15285 file_mips_fp32
= 0;
15287 /* 32-bit float registers. */
15288 file_mips_fp32
= 1;
15291 /* The user specified the size of the float registers. Check if it
15292 agrees with the ABI and ISA. */
15294 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15295 as_bad (_("-mfp64 used with a 32-bit fpu"));
15296 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15297 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15298 as_warn (_("-mfp64 used with a 32-bit ABI"));
15301 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15302 as_warn (_("-mfp32 used with a 64-bit ABI"));
15306 /* End of GCC-shared inference code. */
15308 /* This flag is set when we have a 64-bit capable CPU but use only
15309 32-bit wide registers. Note that EABI does not use it. */
15310 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15311 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15312 || mips_abi
== O32_ABI
))
15313 mips_32bitmode
= 1;
15315 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15316 as_bad (_("trap exception not supported at ISA 1"));
15318 /* If the selected architecture includes support for ASEs, enable
15319 generation of code for them. */
15320 if (mips_opts
.mips16
== -1)
15321 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15322 if (mips_opts
.micromips
== -1)
15323 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15324 if (mips_opts
.ase_mips3d
== -1)
15325 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
15326 && file_mips_fp32
== 0) ? 1 : 0;
15327 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
15328 as_bad (_("-mfp32 used with -mips3d"));
15330 if (mips_opts
.ase_mdmx
== -1)
15331 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
15332 && file_mips_fp32
== 0) ? 1 : 0;
15333 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
15334 as_bad (_("-mfp32 used with -mdmx"));
15336 if (mips_opts
.ase_smartmips
== -1)
15337 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
15338 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
15339 as_warn (_("%s ISA does not support SmartMIPS"),
15340 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15342 if (mips_opts
.ase_dsp
== -1)
15343 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15344 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
15345 as_warn (_("%s ISA does not support DSP ASE"),
15346 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15348 if (mips_opts
.ase_dspr2
== -1)
15350 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
15351 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
15353 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
15354 as_warn (_("%s ISA does not support DSP R2 ASE"),
15355 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15357 if (mips_opts
.ase_mt
== -1)
15358 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
15359 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
15360 as_warn (_("%s ISA does not support MT ASE"),
15361 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15363 if (mips_opts
.ase_mcu
== -1)
15364 mips_opts
.ase_mcu
= (arch_info
->flags
& MIPS_CPU_ASE_MCU
) ? 1 : 0;
15365 if (mips_opts
.ase_mcu
&& !ISA_SUPPORTS_MCU_ASE
)
15366 as_warn (_("%s ISA does not support MCU ASE"),
15367 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15369 file_mips_isa
= mips_opts
.isa
;
15370 file_ase_mips3d
= mips_opts
.ase_mips3d
;
15371 file_ase_mdmx
= mips_opts
.ase_mdmx
;
15372 file_ase_smartmips
= mips_opts
.ase_smartmips
;
15373 file_ase_dsp
= mips_opts
.ase_dsp
;
15374 file_ase_dspr2
= mips_opts
.ase_dspr2
;
15375 file_ase_mt
= mips_opts
.ase_mt
;
15376 mips_opts
.gp32
= file_mips_gp32
;
15377 mips_opts
.fp32
= file_mips_fp32
;
15378 mips_opts
.soft_float
= file_mips_soft_float
;
15379 mips_opts
.single_float
= file_mips_single_float
;
15381 if (mips_flag_mdebug
< 0)
15383 #ifdef OBJ_MAYBE_ECOFF
15384 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
15385 mips_flag_mdebug
= 1;
15387 #endif /* OBJ_MAYBE_ECOFF */
15388 mips_flag_mdebug
= 0;
15393 mips_init_after_args (void)
15395 /* initialize opcodes */
15396 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15397 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15401 md_pcrel_from (fixS
*fixP
)
15403 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15404 switch (fixP
->fx_r_type
)
15406 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15407 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15408 /* Return the address of the delay slot. */
15411 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15412 case BFD_RELOC_MICROMIPS_JMP
:
15413 case BFD_RELOC_16_PCREL_S2
:
15414 case BFD_RELOC_MIPS_JMP
:
15415 /* Return the address of the delay slot. */
15419 /* We have no relocation type for PC relative MIPS16 instructions. */
15420 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15422 _("PC relative MIPS16 instruction references a different section"));
15427 /* This is called before the symbol table is processed. In order to
15428 work with gcc when using mips-tfile, we must keep all local labels.
15429 However, in other cases, we want to discard them. If we were
15430 called with -g, but we didn't see any debugging information, it may
15431 mean that gcc is smuggling debugging information through to
15432 mips-tfile, in which case we must generate all local labels. */
15435 mips_frob_file_before_adjust (void)
15437 #ifndef NO_ECOFF_DEBUGGING
15438 if (ECOFF_DEBUGGING
15440 && ! ecoff_debugging_seen
)
15441 flag_keep_locals
= 1;
15445 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15446 the corresponding LO16 reloc. This is called before md_apply_fix and
15447 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15448 relocation operators.
15450 For our purposes, a %lo() expression matches a %got() or %hi()
15453 (a) it refers to the same symbol; and
15454 (b) the offset applied in the %lo() expression is no lower than
15455 the offset applied in the %got() or %hi().
15457 (b) allows us to cope with code like:
15460 lh $4,%lo(foo+2)($4)
15462 ...which is legal on RELA targets, and has a well-defined behaviour
15463 if the user knows that adding 2 to "foo" will not induce a carry to
15466 When several %lo()s match a particular %got() or %hi(), we use the
15467 following rules to distinguish them:
15469 (1) %lo()s with smaller offsets are a better match than %lo()s with
15472 (2) %lo()s with no matching %got() or %hi() are better than those
15473 that already have a matching %got() or %hi().
15475 (3) later %lo()s are better than earlier %lo()s.
15477 These rules are applied in order.
15479 (1) means, among other things, that %lo()s with identical offsets are
15480 chosen if they exist.
15482 (2) means that we won't associate several high-part relocations with
15483 the same low-part relocation unless there's no alternative. Having
15484 several high parts for the same low part is a GNU extension; this rule
15485 allows careful users to avoid it.
15487 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15488 with the last high-part relocation being at the front of the list.
15489 It therefore makes sense to choose the last matching low-part
15490 relocation, all other things being equal. It's also easier
15491 to code that way. */
15494 mips_frob_file (void)
15496 struct mips_hi_fixup
*l
;
15497 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15499 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15501 segment_info_type
*seginfo
;
15502 bfd_boolean matched_lo_p
;
15503 fixS
**hi_pos
, **lo_pos
, **pos
;
15505 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15507 /* If a GOT16 relocation turns out to be against a global symbol,
15508 there isn't supposed to be a matching LO. Ignore %gots against
15509 constants; we'll report an error for those later. */
15510 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15511 && !(l
->fixp
->fx_addsy
15512 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15515 /* Check quickly whether the next fixup happens to be a matching %lo. */
15516 if (fixup_has_matching_lo_p (l
->fixp
))
15519 seginfo
= seg_info (l
->seg
);
15521 /* Set HI_POS to the position of this relocation in the chain.
15522 Set LO_POS to the position of the chosen low-part relocation.
15523 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15524 relocation that matches an immediately-preceding high-part
15528 matched_lo_p
= FALSE
;
15529 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15531 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15533 if (*pos
== l
->fixp
)
15536 if ((*pos
)->fx_r_type
== looking_for_rtype
15537 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15538 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15540 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15542 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15545 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15546 && fixup_has_matching_lo_p (*pos
));
15549 /* If we found a match, remove the high-part relocation from its
15550 current position and insert it before the low-part relocation.
15551 Make the offsets match so that fixup_has_matching_lo_p()
15554 We don't warn about unmatched high-part relocations since some
15555 versions of gcc have been known to emit dead "lui ...%hi(...)"
15557 if (lo_pos
!= NULL
)
15559 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15560 if (l
->fixp
->fx_next
!= *lo_pos
)
15562 *hi_pos
= l
->fixp
->fx_next
;
15563 l
->fixp
->fx_next
= *lo_pos
;
15571 mips_force_relocation (fixS
*fixp
)
15573 if (generic_force_reloc (fixp
))
15576 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15577 so that the linker relaxation can update targets. */
15578 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15579 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15580 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15586 /* Read the instruction associated with RELOC from BUF. */
15588 static unsigned int
15589 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15591 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15592 return read_compressed_insn (buf
, 4);
15594 return read_insn (buf
);
15597 /* Write instruction INSN to BUF, given that it has been relocated
15601 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15602 unsigned long insn
)
15604 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15605 write_compressed_insn (buf
, insn
, 4);
15607 write_insn (buf
, insn
);
15610 /* Apply a fixup to the object file. */
15613 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15616 unsigned long insn
;
15617 reloc_howto_type
*howto
;
15619 /* We ignore generic BFD relocations we don't know about. */
15620 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15624 gas_assert (fixP
->fx_size
== 2
15625 || fixP
->fx_size
== 4
15626 || fixP
->fx_r_type
== BFD_RELOC_16
15627 || fixP
->fx_r_type
== BFD_RELOC_64
15628 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15629 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15630 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15631 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15632 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15633 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15635 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15637 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15638 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15639 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15640 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
15642 /* Don't treat parts of a composite relocation as done. There are two
15645 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15646 should nevertheless be emitted if the first part is.
15648 (2) In normal usage, composite relocations are never assembly-time
15649 constants. The easiest way of dealing with the pathological
15650 exceptions is to generate a relocation against STN_UNDEF and
15651 leave everything up to the linker. */
15652 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15655 switch (fixP
->fx_r_type
)
15657 case BFD_RELOC_MIPS_TLS_GD
:
15658 case BFD_RELOC_MIPS_TLS_LDM
:
15659 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15660 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15661 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15662 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15663 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15664 case BFD_RELOC_MIPS_TLS_TPREL32
:
15665 case BFD_RELOC_MIPS_TLS_TPREL64
:
15666 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15667 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15668 case BFD_RELOC_MICROMIPS_TLS_GD
:
15669 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15670 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15671 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15672 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15673 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15674 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15675 case BFD_RELOC_MIPS16_TLS_GD
:
15676 case BFD_RELOC_MIPS16_TLS_LDM
:
15677 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15678 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15679 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15680 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15681 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15682 if (!fixP
->fx_addsy
)
15684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15685 _("TLS relocation against a constant"));
15688 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15691 case BFD_RELOC_MIPS_JMP
:
15692 case BFD_RELOC_MIPS_SHIFT5
:
15693 case BFD_RELOC_MIPS_SHIFT6
:
15694 case BFD_RELOC_MIPS_GOT_DISP
:
15695 case BFD_RELOC_MIPS_GOT_PAGE
:
15696 case BFD_RELOC_MIPS_GOT_OFST
:
15697 case BFD_RELOC_MIPS_SUB
:
15698 case BFD_RELOC_MIPS_INSERT_A
:
15699 case BFD_RELOC_MIPS_INSERT_B
:
15700 case BFD_RELOC_MIPS_DELETE
:
15701 case BFD_RELOC_MIPS_HIGHEST
:
15702 case BFD_RELOC_MIPS_HIGHER
:
15703 case BFD_RELOC_MIPS_SCN_DISP
:
15704 case BFD_RELOC_MIPS_REL16
:
15705 case BFD_RELOC_MIPS_RELGOT
:
15706 case BFD_RELOC_MIPS_JALR
:
15707 case BFD_RELOC_HI16
:
15708 case BFD_RELOC_HI16_S
:
15709 case BFD_RELOC_LO16
:
15710 case BFD_RELOC_GPREL16
:
15711 case BFD_RELOC_MIPS_LITERAL
:
15712 case BFD_RELOC_MIPS_CALL16
:
15713 case BFD_RELOC_MIPS_GOT16
:
15714 case BFD_RELOC_GPREL32
:
15715 case BFD_RELOC_MIPS_GOT_HI16
:
15716 case BFD_RELOC_MIPS_GOT_LO16
:
15717 case BFD_RELOC_MIPS_CALL_HI16
:
15718 case BFD_RELOC_MIPS_CALL_LO16
:
15719 case BFD_RELOC_MIPS16_GPREL
:
15720 case BFD_RELOC_MIPS16_GOT16
:
15721 case BFD_RELOC_MIPS16_CALL16
:
15722 case BFD_RELOC_MIPS16_HI16
:
15723 case BFD_RELOC_MIPS16_HI16_S
:
15724 case BFD_RELOC_MIPS16_LO16
:
15725 case BFD_RELOC_MIPS16_JMP
:
15726 case BFD_RELOC_MICROMIPS_JMP
:
15727 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15728 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15729 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15730 case BFD_RELOC_MICROMIPS_SUB
:
15731 case BFD_RELOC_MICROMIPS_HIGHEST
:
15732 case BFD_RELOC_MICROMIPS_HIGHER
:
15733 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15734 case BFD_RELOC_MICROMIPS_JALR
:
15735 case BFD_RELOC_MICROMIPS_HI16
:
15736 case BFD_RELOC_MICROMIPS_HI16_S
:
15737 case BFD_RELOC_MICROMIPS_LO16
:
15738 case BFD_RELOC_MICROMIPS_GPREL16
:
15739 case BFD_RELOC_MICROMIPS_LITERAL
:
15740 case BFD_RELOC_MICROMIPS_CALL16
:
15741 case BFD_RELOC_MICROMIPS_GOT16
:
15742 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15743 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15744 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15745 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15750 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15752 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15753 if (mips16_reloc_p (fixP
->fx_r_type
))
15754 insn
|= mips16_immed_extend (value
, 16);
15756 insn
|= (value
& 0xffff);
15757 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15760 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15761 _("Unsupported constant in relocation"));
15766 /* This is handled like BFD_RELOC_32, but we output a sign
15767 extended value if we are only 32 bits. */
15770 if (8 <= sizeof (valueT
))
15771 md_number_to_chars (buf
, *valP
, 8);
15776 if ((*valP
& 0x80000000) != 0)
15780 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15781 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15786 case BFD_RELOC_RVA
:
15789 /* If we are deleting this reloc entry, we must fill in the
15790 value now. This can happen if we have a .word which is not
15791 resolved when it appears but is later defined. */
15793 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15796 case BFD_RELOC_16_PCREL_S2
:
15797 if ((*valP
& 0x3) != 0)
15798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15799 _("Branch to misaligned address (%lx)"), (long) *valP
);
15801 /* We need to save the bits in the instruction since fixup_segment()
15802 might be deleting the relocation entry (i.e., a branch within
15803 the current segment). */
15804 if (! fixP
->fx_done
)
15807 /* Update old instruction data. */
15808 insn
= read_insn (buf
);
15810 if (*valP
+ 0x20000 <= 0x3ffff)
15812 insn
|= (*valP
>> 2) & 0xffff;
15813 write_insn (buf
, insn
);
15815 else if (mips_pic
== NO_PIC
15817 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15818 && (fixP
->fx_frag
->fr_address
15819 < text_section
->vma
+ bfd_get_section_size (text_section
))
15820 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15821 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15822 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15824 /* The branch offset is too large. If this is an
15825 unconditional branch, and we are not generating PIC code,
15826 we can convert it to an absolute jump instruction. */
15827 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15828 insn
= 0x0c000000; /* jal */
15830 insn
= 0x08000000; /* j */
15831 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15833 fixP
->fx_addsy
= section_symbol (text_section
);
15834 *valP
+= md_pcrel_from (fixP
);
15835 write_insn (buf
, insn
);
15839 /* If we got here, we have branch-relaxation disabled,
15840 and there's nothing we can do to fix this instruction
15841 without turning it into a longer sequence. */
15842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15843 _("Branch out of range"));
15847 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15848 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15849 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15850 /* We adjust the offset back to even. */
15851 if ((*valP
& 0x1) != 0)
15854 if (! fixP
->fx_done
)
15857 /* Should never visit here, because we keep the relocation. */
15861 case BFD_RELOC_VTABLE_INHERIT
:
15864 && !S_IS_DEFINED (fixP
->fx_addsy
)
15865 && !S_IS_WEAK (fixP
->fx_addsy
))
15866 S_SET_WEAK (fixP
->fx_addsy
);
15869 case BFD_RELOC_VTABLE_ENTRY
:
15877 /* Remember value for tc_gen_reloc. */
15878 fixP
->fx_addnumber
= *valP
;
15888 name
= input_line_pointer
;
15889 c
= get_symbol_end ();
15890 p
= (symbolS
*) symbol_find_or_make (name
);
15891 *input_line_pointer
= c
;
15895 /* Align the current frag to a given power of two. If a particular
15896 fill byte should be used, FILL points to an integer that contains
15897 that byte, otherwise FILL is null.
15899 This function used to have the comment:
15901 The MIPS assembler also automatically adjusts any preceding label.
15903 The implementation therefore applied the adjustment to a maximum of
15904 one label. However, other label adjustments are applied to batches
15905 of labels, and adjusting just one caused problems when new labels
15906 were added for the sake of debugging or unwind information.
15907 We therefore adjust all preceding labels (given as LABELS) instead. */
15910 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15912 mips_emit_delays ();
15913 mips_record_compressed_mode ();
15914 if (fill
== NULL
&& subseg_text_p (now_seg
))
15915 frag_align_code (to
, 0);
15917 frag_align (to
, fill
? *fill
: 0, 0);
15918 record_alignment (now_seg
, to
);
15919 mips_move_labels (labels
, FALSE
);
15922 /* Align to a given power of two. .align 0 turns off the automatic
15923 alignment used by the data creating pseudo-ops. */
15926 s_align (int x ATTRIBUTE_UNUSED
)
15928 int temp
, fill_value
, *fill_ptr
;
15929 long max_alignment
= 28;
15931 /* o Note that the assembler pulls down any immediately preceding label
15932 to the aligned address.
15933 o It's not documented but auto alignment is reinstated by
15934 a .align pseudo instruction.
15935 o Note also that after auto alignment is turned off the mips assembler
15936 issues an error on attempt to assemble an improperly aligned data item.
15939 temp
= get_absolute_expression ();
15940 if (temp
> max_alignment
)
15941 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
15944 as_warn (_("Alignment negative: 0 assumed."));
15947 if (*input_line_pointer
== ',')
15949 ++input_line_pointer
;
15950 fill_value
= get_absolute_expression ();
15951 fill_ptr
= &fill_value
;
15957 segment_info_type
*si
= seg_info (now_seg
);
15958 struct insn_label_list
*l
= si
->label_list
;
15959 /* Auto alignment should be switched on by next section change. */
15961 mips_align (temp
, fill_ptr
, l
);
15968 demand_empty_rest_of_line ();
15972 s_change_sec (int sec
)
15977 /* The ELF backend needs to know that we are changing sections, so
15978 that .previous works correctly. We could do something like check
15979 for an obj_section_change_hook macro, but that might be confusing
15980 as it would not be appropriate to use it in the section changing
15981 functions in read.c, since obj-elf.c intercepts those. FIXME:
15982 This should be cleaner, somehow. */
15984 obj_elf_section_change_hook ();
15987 mips_emit_delays ();
15998 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15999 demand_empty_rest_of_line ();
16003 seg
= subseg_new (RDATA_SECTION_NAME
,
16004 (subsegT
) get_absolute_expression ());
16007 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16008 | SEC_READONLY
| SEC_RELOC
16010 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16011 record_alignment (seg
, 4);
16013 demand_empty_rest_of_line ();
16017 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16020 bfd_set_section_flags (stdoutput
, seg
,
16021 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16022 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16023 record_alignment (seg
, 4);
16025 demand_empty_rest_of_line ();
16029 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16032 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16033 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16034 record_alignment (seg
, 4);
16036 demand_empty_rest_of_line ();
16044 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16047 char *section_name
;
16052 int section_entry_size
;
16053 int section_alignment
;
16058 section_name
= input_line_pointer
;
16059 c
= get_symbol_end ();
16061 next_c
= *(input_line_pointer
+ 1);
16063 /* Do we have .section Name<,"flags">? */
16064 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16066 /* just after name is now '\0'. */
16067 *input_line_pointer
= c
;
16068 input_line_pointer
= section_name
;
16069 obj_elf_section (ignore
);
16072 input_line_pointer
++;
16074 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16076 section_type
= get_absolute_expression ();
16079 if (*input_line_pointer
++ == ',')
16080 section_flag
= get_absolute_expression ();
16083 if (*input_line_pointer
++ == ',')
16084 section_entry_size
= get_absolute_expression ();
16086 section_entry_size
= 0;
16087 if (*input_line_pointer
++ == ',')
16088 section_alignment
= get_absolute_expression ();
16090 section_alignment
= 0;
16091 /* FIXME: really ignore? */
16092 (void) section_alignment
;
16094 section_name
= xstrdup (section_name
);
16096 /* When using the generic form of .section (as implemented by obj-elf.c),
16097 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16098 traditionally had to fall back on the more common @progbits instead.
16100 There's nothing really harmful in this, since bfd will correct
16101 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16102 means that, for backwards compatibility, the special_section entries
16103 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16105 Even so, we shouldn't force users of the MIPS .section syntax to
16106 incorrectly label the sections as SHT_PROGBITS. The best compromise
16107 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16108 generic type-checking code. */
16109 if (section_type
== SHT_MIPS_DWARF
)
16110 section_type
= SHT_PROGBITS
;
16112 obj_elf_change_section (section_name
, section_type
, section_flag
,
16113 section_entry_size
, 0, 0, 0);
16115 if (now_seg
->name
!= section_name
)
16116 free (section_name
);
16117 #endif /* OBJ_ELF */
16121 mips_enable_auto_align (void)
16127 s_cons (int log_size
)
16129 segment_info_type
*si
= seg_info (now_seg
);
16130 struct insn_label_list
*l
= si
->label_list
;
16132 mips_emit_delays ();
16133 if (log_size
> 0 && auto_align
)
16134 mips_align (log_size
, 0, l
);
16135 cons (1 << log_size
);
16136 mips_clear_insn_labels ();
16140 s_float_cons (int type
)
16142 segment_info_type
*si
= seg_info (now_seg
);
16143 struct insn_label_list
*l
= si
->label_list
;
16145 mips_emit_delays ();
16150 mips_align (3, 0, l
);
16152 mips_align (2, 0, l
);
16156 mips_clear_insn_labels ();
16159 /* Handle .globl. We need to override it because on Irix 5 you are
16162 where foo is an undefined symbol, to mean that foo should be
16163 considered to be the address of a function. */
16166 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16175 name
= input_line_pointer
;
16176 c
= get_symbol_end ();
16177 symbolP
= symbol_find_or_make (name
);
16178 S_SET_EXTERNAL (symbolP
);
16180 *input_line_pointer
= c
;
16181 SKIP_WHITESPACE ();
16183 /* On Irix 5, every global symbol that is not explicitly labelled as
16184 being a function is apparently labelled as being an object. */
16187 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16188 && (*input_line_pointer
!= ','))
16193 secname
= input_line_pointer
;
16194 c
= get_symbol_end ();
16195 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16197 as_bad (_("%s: no such section"), secname
);
16198 *input_line_pointer
= c
;
16200 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16201 flag
= BSF_FUNCTION
;
16204 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16206 c
= *input_line_pointer
;
16209 input_line_pointer
++;
16210 SKIP_WHITESPACE ();
16211 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16217 demand_empty_rest_of_line ();
16221 s_option (int x ATTRIBUTE_UNUSED
)
16226 opt
= input_line_pointer
;
16227 c
= get_symbol_end ();
16231 /* FIXME: What does this mean? */
16233 else if (strncmp (opt
, "pic", 3) == 0)
16237 i
= atoi (opt
+ 3);
16242 mips_pic
= SVR4_PIC
;
16243 mips_abicalls
= TRUE
;
16246 as_bad (_(".option pic%d not supported"), i
);
16248 if (mips_pic
== SVR4_PIC
)
16250 if (g_switch_seen
&& g_switch_value
!= 0)
16251 as_warn (_("-G may not be used with SVR4 PIC code"));
16252 g_switch_value
= 0;
16253 bfd_set_gp_size (stdoutput
, 0);
16257 as_warn (_("Unrecognized option \"%s\""), opt
);
16259 *input_line_pointer
= c
;
16260 demand_empty_rest_of_line ();
16263 /* This structure is used to hold a stack of .set values. */
16265 struct mips_option_stack
16267 struct mips_option_stack
*next
;
16268 struct mips_set_options options
;
16271 static struct mips_option_stack
*mips_opts_stack
;
16273 /* Handle the .set pseudo-op. */
16276 s_mipsset (int x ATTRIBUTE_UNUSED
)
16278 char *name
= input_line_pointer
, ch
;
16280 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16281 ++input_line_pointer
;
16282 ch
= *input_line_pointer
;
16283 *input_line_pointer
= '\0';
16285 if (strcmp (name
, "reorder") == 0)
16287 if (mips_opts
.noreorder
)
16290 else if (strcmp (name
, "noreorder") == 0)
16292 if (!mips_opts
.noreorder
)
16293 start_noreorder ();
16295 else if (strncmp (name
, "at=", 3) == 0)
16297 char *s
= name
+ 3;
16299 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16300 as_bad (_("Unrecognized register name `%s'"), s
);
16302 else if (strcmp (name
, "at") == 0)
16304 mips_opts
.at
= ATREG
;
16306 else if (strcmp (name
, "noat") == 0)
16308 mips_opts
.at
= ZERO
;
16310 else if (strcmp (name
, "macro") == 0)
16312 mips_opts
.warn_about_macros
= 0;
16314 else if (strcmp (name
, "nomacro") == 0)
16316 if (mips_opts
.noreorder
== 0)
16317 as_bad (_("`noreorder' must be set before `nomacro'"));
16318 mips_opts
.warn_about_macros
= 1;
16320 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16322 mips_opts
.nomove
= 0;
16324 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16326 mips_opts
.nomove
= 1;
16328 else if (strcmp (name
, "bopt") == 0)
16330 mips_opts
.nobopt
= 0;
16332 else if (strcmp (name
, "nobopt") == 0)
16334 mips_opts
.nobopt
= 1;
16336 else if (strcmp (name
, "gp=default") == 0)
16337 mips_opts
.gp32
= file_mips_gp32
;
16338 else if (strcmp (name
, "gp=32") == 0)
16339 mips_opts
.gp32
= 1;
16340 else if (strcmp (name
, "gp=64") == 0)
16342 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16343 as_warn (_("%s isa does not support 64-bit registers"),
16344 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16345 mips_opts
.gp32
= 0;
16347 else if (strcmp (name
, "fp=default") == 0)
16348 mips_opts
.fp32
= file_mips_fp32
;
16349 else if (strcmp (name
, "fp=32") == 0)
16350 mips_opts
.fp32
= 1;
16351 else if (strcmp (name
, "fp=64") == 0)
16353 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16354 as_warn (_("%s isa does not support 64-bit floating point registers"),
16355 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16356 mips_opts
.fp32
= 0;
16358 else if (strcmp (name
, "softfloat") == 0)
16359 mips_opts
.soft_float
= 1;
16360 else if (strcmp (name
, "hardfloat") == 0)
16361 mips_opts
.soft_float
= 0;
16362 else if (strcmp (name
, "singlefloat") == 0)
16363 mips_opts
.single_float
= 1;
16364 else if (strcmp (name
, "doublefloat") == 0)
16365 mips_opts
.single_float
= 0;
16366 else if (strcmp (name
, "mips16") == 0
16367 || strcmp (name
, "MIPS-16") == 0)
16369 if (mips_opts
.micromips
== 1)
16370 as_fatal (_("`mips16' cannot be used with `micromips'"));
16371 mips_opts
.mips16
= 1;
16373 else if (strcmp (name
, "nomips16") == 0
16374 || strcmp (name
, "noMIPS-16") == 0)
16375 mips_opts
.mips16
= 0;
16376 else if (strcmp (name
, "micromips") == 0)
16378 if (mips_opts
.mips16
== 1)
16379 as_fatal (_("`micromips' cannot be used with `mips16'"));
16380 mips_opts
.micromips
= 1;
16382 else if (strcmp (name
, "nomicromips") == 0)
16383 mips_opts
.micromips
= 0;
16384 else if (strcmp (name
, "smartmips") == 0)
16386 if (!ISA_SUPPORTS_SMARTMIPS
)
16387 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16388 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16389 mips_opts
.ase_smartmips
= 1;
16391 else if (strcmp (name
, "nosmartmips") == 0)
16392 mips_opts
.ase_smartmips
= 0;
16393 else if (strcmp (name
, "mips3d") == 0)
16394 mips_opts
.ase_mips3d
= 1;
16395 else if (strcmp (name
, "nomips3d") == 0)
16396 mips_opts
.ase_mips3d
= 0;
16397 else if (strcmp (name
, "mdmx") == 0)
16398 mips_opts
.ase_mdmx
= 1;
16399 else if (strcmp (name
, "nomdmx") == 0)
16400 mips_opts
.ase_mdmx
= 0;
16401 else if (strcmp (name
, "dsp") == 0)
16403 if (!ISA_SUPPORTS_DSP_ASE
)
16404 as_warn (_("%s ISA does not support DSP ASE"),
16405 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16406 mips_opts
.ase_dsp
= 1;
16407 mips_opts
.ase_dspr2
= 0;
16409 else if (strcmp (name
, "nodsp") == 0)
16411 mips_opts
.ase_dsp
= 0;
16412 mips_opts
.ase_dspr2
= 0;
16414 else if (strcmp (name
, "dspr2") == 0)
16416 if (!ISA_SUPPORTS_DSPR2_ASE
)
16417 as_warn (_("%s ISA does not support DSP R2 ASE"),
16418 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16419 mips_opts
.ase_dspr2
= 1;
16420 mips_opts
.ase_dsp
= 1;
16422 else if (strcmp (name
, "nodspr2") == 0)
16424 mips_opts
.ase_dspr2
= 0;
16425 mips_opts
.ase_dsp
= 0;
16427 else if (strcmp (name
, "mt") == 0)
16429 if (!ISA_SUPPORTS_MT_ASE
)
16430 as_warn (_("%s ISA does not support MT ASE"),
16431 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16432 mips_opts
.ase_mt
= 1;
16434 else if (strcmp (name
, "nomt") == 0)
16435 mips_opts
.ase_mt
= 0;
16436 else if (strcmp (name
, "mcu") == 0)
16437 mips_opts
.ase_mcu
= 1;
16438 else if (strcmp (name
, "nomcu") == 0)
16439 mips_opts
.ase_mcu
= 0;
16440 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16444 /* Permit the user to change the ISA and architecture on the fly.
16445 Needless to say, misuse can cause serious problems. */
16446 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16449 mips_opts
.isa
= file_mips_isa
;
16450 mips_opts
.arch
= file_mips_arch
;
16452 else if (strncmp (name
, "arch=", 5) == 0)
16454 const struct mips_cpu_info
*p
;
16456 p
= mips_parse_cpu("internal use", name
+ 5);
16458 as_bad (_("unknown architecture %s"), name
+ 5);
16461 mips_opts
.arch
= p
->cpu
;
16462 mips_opts
.isa
= p
->isa
;
16465 else if (strncmp (name
, "mips", 4) == 0)
16467 const struct mips_cpu_info
*p
;
16469 p
= mips_parse_cpu("internal use", name
);
16471 as_bad (_("unknown ISA level %s"), name
+ 4);
16474 mips_opts
.arch
= p
->cpu
;
16475 mips_opts
.isa
= p
->isa
;
16479 as_bad (_("unknown ISA or architecture %s"), name
);
16481 switch (mips_opts
.isa
)
16489 mips_opts
.gp32
= 1;
16490 mips_opts
.fp32
= 1;
16497 mips_opts
.gp32
= 0;
16498 if (mips_opts
.arch
== CPU_R5900
)
16500 mips_opts
.fp32
= 1;
16504 mips_opts
.fp32
= 0;
16508 as_bad (_("unknown ISA level %s"), name
+ 4);
16513 mips_opts
.gp32
= file_mips_gp32
;
16514 mips_opts
.fp32
= file_mips_fp32
;
16517 else if (strcmp (name
, "autoextend") == 0)
16518 mips_opts
.noautoextend
= 0;
16519 else if (strcmp (name
, "noautoextend") == 0)
16520 mips_opts
.noautoextend
= 1;
16521 else if (strcmp (name
, "push") == 0)
16523 struct mips_option_stack
*s
;
16525 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16526 s
->next
= mips_opts_stack
;
16527 s
->options
= mips_opts
;
16528 mips_opts_stack
= s
;
16530 else if (strcmp (name
, "pop") == 0)
16532 struct mips_option_stack
*s
;
16534 s
= mips_opts_stack
;
16536 as_bad (_(".set pop with no .set push"));
16539 /* If we're changing the reorder mode we need to handle
16540 delay slots correctly. */
16541 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16542 start_noreorder ();
16543 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16546 mips_opts
= s
->options
;
16547 mips_opts_stack
= s
->next
;
16551 else if (strcmp (name
, "sym32") == 0)
16552 mips_opts
.sym32
= TRUE
;
16553 else if (strcmp (name
, "nosym32") == 0)
16554 mips_opts
.sym32
= FALSE
;
16555 else if (strchr (name
, ','))
16557 /* Generic ".set" directive; use the generic handler. */
16558 *input_line_pointer
= ch
;
16559 input_line_pointer
= name
;
16565 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16567 *input_line_pointer
= ch
;
16568 demand_empty_rest_of_line ();
16571 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16572 .option pic2. It means to generate SVR4 PIC calls. */
16575 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16577 mips_pic
= SVR4_PIC
;
16578 mips_abicalls
= TRUE
;
16580 if (g_switch_seen
&& g_switch_value
!= 0)
16581 as_warn (_("-G may not be used with SVR4 PIC code"));
16582 g_switch_value
= 0;
16584 bfd_set_gp_size (stdoutput
, 0);
16585 demand_empty_rest_of_line ();
16588 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16589 PIC code. It sets the $gp register for the function based on the
16590 function address, which is in the register named in the argument.
16591 This uses a relocation against _gp_disp, which is handled specially
16592 by the linker. The result is:
16593 lui $gp,%hi(_gp_disp)
16594 addiu $gp,$gp,%lo(_gp_disp)
16595 addu $gp,$gp,.cpload argument
16596 The .cpload argument is normally $25 == $t9.
16598 The -mno-shared option changes this to:
16599 lui $gp,%hi(__gnu_local_gp)
16600 addiu $gp,$gp,%lo(__gnu_local_gp)
16601 and the argument is ignored. This saves an instruction, but the
16602 resulting code is not position independent; it uses an absolute
16603 address for __gnu_local_gp. Thus code assembled with -mno-shared
16604 can go into an ordinary executable, but not into a shared library. */
16607 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16613 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16614 .cpload is ignored. */
16615 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16621 if (mips_opts
.mips16
)
16623 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16624 ignore_rest_of_line ();
16628 /* .cpload should be in a .set noreorder section. */
16629 if (mips_opts
.noreorder
== 0)
16630 as_warn (_(".cpload not in noreorder section"));
16632 reg
= tc_get_register (0);
16634 /* If we need to produce a 64-bit address, we are better off using
16635 the default instruction sequence. */
16636 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16638 ex
.X_op
= O_symbol
;
16639 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16641 ex
.X_op_symbol
= NULL
;
16642 ex
.X_add_number
= 0;
16644 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16645 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16647 mips_mark_labels ();
16648 mips_assembling_insn
= TRUE
;
16651 macro_build_lui (&ex
, mips_gp_register
);
16652 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16653 mips_gp_register
, BFD_RELOC_LO16
);
16655 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16656 mips_gp_register
, reg
);
16659 mips_assembling_insn
= FALSE
;
16660 demand_empty_rest_of_line ();
16663 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16664 .cpsetup $reg1, offset|$reg2, label
16666 If offset is given, this results in:
16667 sd $gp, offset($sp)
16668 lui $gp, %hi(%neg(%gp_rel(label)))
16669 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16670 daddu $gp, $gp, $reg1
16672 If $reg2 is given, this results in:
16673 daddu $reg2, $gp, $0
16674 lui $gp, %hi(%neg(%gp_rel(label)))
16675 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16676 daddu $gp, $gp, $reg1
16677 $reg1 is normally $25 == $t9.
16679 The -mno-shared option replaces the last three instructions with
16681 addiu $gp,$gp,%lo(_gp) */
16684 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16686 expressionS ex_off
;
16687 expressionS ex_sym
;
16690 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16691 We also need NewABI support. */
16692 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16698 if (mips_opts
.mips16
)
16700 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16701 ignore_rest_of_line ();
16705 reg1
= tc_get_register (0);
16706 SKIP_WHITESPACE ();
16707 if (*input_line_pointer
!= ',')
16709 as_bad (_("missing argument separator ',' for .cpsetup"));
16713 ++input_line_pointer
;
16714 SKIP_WHITESPACE ();
16715 if (*input_line_pointer
== '$')
16717 mips_cpreturn_register
= tc_get_register (0);
16718 mips_cpreturn_offset
= -1;
16722 mips_cpreturn_offset
= get_absolute_expression ();
16723 mips_cpreturn_register
= -1;
16725 SKIP_WHITESPACE ();
16726 if (*input_line_pointer
!= ',')
16728 as_bad (_("missing argument separator ',' for .cpsetup"));
16732 ++input_line_pointer
;
16733 SKIP_WHITESPACE ();
16734 expression (&ex_sym
);
16736 mips_mark_labels ();
16737 mips_assembling_insn
= TRUE
;
16740 if (mips_cpreturn_register
== -1)
16742 ex_off
.X_op
= O_constant
;
16743 ex_off
.X_add_symbol
= NULL
;
16744 ex_off
.X_op_symbol
= NULL
;
16745 ex_off
.X_add_number
= mips_cpreturn_offset
;
16747 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16748 BFD_RELOC_LO16
, SP
);
16751 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16752 mips_gp_register
, 0);
16754 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16756 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16757 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16760 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16761 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16762 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16764 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16765 mips_gp_register
, reg1
);
16771 ex
.X_op
= O_symbol
;
16772 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16773 ex
.X_op_symbol
= NULL
;
16774 ex
.X_add_number
= 0;
16776 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16777 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16779 macro_build_lui (&ex
, mips_gp_register
);
16780 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16781 mips_gp_register
, BFD_RELOC_LO16
);
16786 mips_assembling_insn
= FALSE
;
16787 demand_empty_rest_of_line ();
16791 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16793 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16794 .cplocal is ignored. */
16795 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16801 if (mips_opts
.mips16
)
16803 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16804 ignore_rest_of_line ();
16808 mips_gp_register
= tc_get_register (0);
16809 demand_empty_rest_of_line ();
16812 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16813 offset from $sp. The offset is remembered, and after making a PIC
16814 call $gp is restored from that location. */
16817 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16821 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16822 .cprestore is ignored. */
16823 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16829 if (mips_opts
.mips16
)
16831 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16832 ignore_rest_of_line ();
16836 mips_cprestore_offset
= get_absolute_expression ();
16837 mips_cprestore_valid
= 1;
16839 ex
.X_op
= O_constant
;
16840 ex
.X_add_symbol
= NULL
;
16841 ex
.X_op_symbol
= NULL
;
16842 ex
.X_add_number
= mips_cprestore_offset
;
16844 mips_mark_labels ();
16845 mips_assembling_insn
= TRUE
;
16848 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16849 SP
, HAVE_64BIT_ADDRESSES
);
16852 mips_assembling_insn
= FALSE
;
16853 demand_empty_rest_of_line ();
16856 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16857 was given in the preceding .cpsetup, it results in:
16858 ld $gp, offset($sp)
16860 If a register $reg2 was given there, it results in:
16861 daddu $gp, $reg2, $0 */
16864 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16868 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16869 We also need NewABI support. */
16870 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16876 if (mips_opts
.mips16
)
16878 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16879 ignore_rest_of_line ();
16883 mips_mark_labels ();
16884 mips_assembling_insn
= TRUE
;
16887 if (mips_cpreturn_register
== -1)
16889 ex
.X_op
= O_constant
;
16890 ex
.X_add_symbol
= NULL
;
16891 ex
.X_op_symbol
= NULL
;
16892 ex
.X_add_number
= mips_cpreturn_offset
;
16894 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16897 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
16898 mips_cpreturn_register
, 0);
16901 mips_assembling_insn
= FALSE
;
16902 demand_empty_rest_of_line ();
16905 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16906 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16907 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16908 debug information or MIPS16 TLS. */
16911 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16912 bfd_reloc_code_real_type rtype
)
16919 if (ex
.X_op
!= O_symbol
)
16921 as_bad (_("Unsupported use of %s"), dirstr
);
16922 ignore_rest_of_line ();
16925 p
= frag_more (bytes
);
16926 md_number_to_chars (p
, 0, bytes
);
16927 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16928 demand_empty_rest_of_line ();
16929 mips_clear_insn_labels ();
16932 /* Handle .dtprelword. */
16935 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16937 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16940 /* Handle .dtpreldword. */
16943 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16945 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16948 /* Handle .tprelword. */
16951 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16953 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16956 /* Handle .tpreldword. */
16959 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16961 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16964 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16965 code. It sets the offset to use in gp_rel relocations. */
16968 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16970 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16971 We also need NewABI support. */
16972 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16978 mips_gprel_offset
= get_absolute_expression ();
16980 demand_empty_rest_of_line ();
16983 /* Handle the .gpword pseudo-op. This is used when generating PIC
16984 code. It generates a 32 bit GP relative reloc. */
16987 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16989 segment_info_type
*si
;
16990 struct insn_label_list
*l
;
16994 /* When not generating PIC code, this is treated as .word. */
16995 if (mips_pic
!= SVR4_PIC
)
17001 si
= seg_info (now_seg
);
17002 l
= si
->label_list
;
17003 mips_emit_delays ();
17005 mips_align (2, 0, l
);
17008 mips_clear_insn_labels ();
17010 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17012 as_bad (_("Unsupported use of .gpword"));
17013 ignore_rest_of_line ();
17017 md_number_to_chars (p
, 0, 4);
17018 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17019 BFD_RELOC_GPREL32
);
17021 demand_empty_rest_of_line ();
17025 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17027 segment_info_type
*si
;
17028 struct insn_label_list
*l
;
17032 /* When not generating PIC code, this is treated as .dword. */
17033 if (mips_pic
!= SVR4_PIC
)
17039 si
= seg_info (now_seg
);
17040 l
= si
->label_list
;
17041 mips_emit_delays ();
17043 mips_align (3, 0, l
);
17046 mips_clear_insn_labels ();
17048 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17050 as_bad (_("Unsupported use of .gpdword"));
17051 ignore_rest_of_line ();
17055 md_number_to_chars (p
, 0, 8);
17056 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17057 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17059 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17060 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17061 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17063 demand_empty_rest_of_line ();
17066 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17067 tables in SVR4 PIC code. */
17070 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17074 /* This is ignored when not generating SVR4 PIC code. */
17075 if (mips_pic
!= SVR4_PIC
)
17081 mips_mark_labels ();
17082 mips_assembling_insn
= TRUE
;
17084 /* Add $gp to the register named as an argument. */
17086 reg
= tc_get_register (0);
17087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17090 mips_assembling_insn
= FALSE
;
17091 demand_empty_rest_of_line ();
17094 /* Handle the .insn pseudo-op. This marks instruction labels in
17095 mips16/micromips mode. This permits the linker to handle them specially,
17096 such as generating jalx instructions when needed. We also make
17097 them odd for the duration of the assembly, in order to generate the
17098 right sort of code. We will make them even in the adjust_symtab
17099 routine, while leaving them marked. This is convenient for the
17100 debugger and the disassembler. The linker knows to make them odd
17104 s_insn (int ignore ATTRIBUTE_UNUSED
)
17106 mips_mark_labels ();
17108 demand_empty_rest_of_line ();
17111 /* Handle a .stab[snd] directive. Ideally these directives would be
17112 implemented in a transparent way, so that removing them would not
17113 have any effect on the generated instructions. However, s_stab
17114 internally changes the section, so in practice we need to decide
17115 now whether the preceding label marks compressed code. We do not
17116 support changing the compression mode of a label after a .stab*
17117 directive, such as in:
17123 so the current mode wins. */
17126 s_mips_stab (int type
)
17128 mips_mark_labels ();
17132 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17135 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17142 name
= input_line_pointer
;
17143 c
= get_symbol_end ();
17144 symbolP
= symbol_find_or_make (name
);
17145 S_SET_WEAK (symbolP
);
17146 *input_line_pointer
= c
;
17148 SKIP_WHITESPACE ();
17150 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17152 if (S_IS_DEFINED (symbolP
))
17154 as_bad (_("ignoring attempt to redefine symbol %s"),
17155 S_GET_NAME (symbolP
));
17156 ignore_rest_of_line ();
17160 if (*input_line_pointer
== ',')
17162 ++input_line_pointer
;
17163 SKIP_WHITESPACE ();
17167 if (exp
.X_op
!= O_symbol
)
17169 as_bad (_("bad .weakext directive"));
17170 ignore_rest_of_line ();
17173 symbol_set_value_expression (symbolP
, &exp
);
17176 demand_empty_rest_of_line ();
17179 /* Parse a register string into a number. Called from the ECOFF code
17180 to parse .frame. The argument is non-zero if this is the frame
17181 register, so that we can record it in mips_frame_reg. */
17184 tc_get_register (int frame
)
17188 SKIP_WHITESPACE ();
17189 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17193 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17194 mips_frame_reg_valid
= 1;
17195 mips_cprestore_valid
= 0;
17201 md_section_align (asection
*seg
, valueT addr
)
17203 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17207 /* We don't need to align ELF sections to the full alignment.
17208 However, Irix 5 may prefer that we align them at least to a 16
17209 byte boundary. We don't bother to align the sections if we
17210 are targeted for an embedded system. */
17211 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17217 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17220 /* Utility routine, called from above as well. If called while the
17221 input file is still being read, it's only an approximation. (For
17222 example, a symbol may later become defined which appeared to be
17223 undefined earlier.) */
17226 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17231 if (g_switch_value
> 0)
17233 const char *symname
;
17236 /* Find out whether this symbol can be referenced off the $gp
17237 register. It can be if it is smaller than the -G size or if
17238 it is in the .sdata or .sbss section. Certain symbols can
17239 not be referenced off the $gp, although it appears as though
17241 symname
= S_GET_NAME (sym
);
17242 if (symname
!= (const char *) NULL
17243 && (strcmp (symname
, "eprol") == 0
17244 || strcmp (symname
, "etext") == 0
17245 || strcmp (symname
, "_gp") == 0
17246 || strcmp (symname
, "edata") == 0
17247 || strcmp (symname
, "_fbss") == 0
17248 || strcmp (symname
, "_fdata") == 0
17249 || strcmp (symname
, "_ftext") == 0
17250 || strcmp (symname
, "end") == 0
17251 || strcmp (symname
, "_gp_disp") == 0))
17253 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17255 #ifndef NO_ECOFF_DEBUGGING
17256 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17257 && (symbol_get_obj (sym
)->ecoff_extern_size
17258 <= g_switch_value
))
17260 /* We must defer this decision until after the whole
17261 file has been read, since there might be a .extern
17262 after the first use of this symbol. */
17263 || (before_relaxing
17264 #ifndef NO_ECOFF_DEBUGGING
17265 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17267 && S_GET_VALUE (sym
) == 0)
17268 || (S_GET_VALUE (sym
) != 0
17269 && S_GET_VALUE (sym
) <= g_switch_value
)))
17273 const char *segname
;
17275 segname
= segment_name (S_GET_SEGMENT (sym
));
17276 gas_assert (strcmp (segname
, ".lit8") != 0
17277 && strcmp (segname
, ".lit4") != 0);
17278 change
= (strcmp (segname
, ".sdata") != 0
17279 && strcmp (segname
, ".sbss") != 0
17280 && strncmp (segname
, ".sdata.", 7) != 0
17281 && strncmp (segname
, ".sbss.", 6) != 0
17282 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17283 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17288 /* We are not optimizing for the $gp register. */
17293 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17296 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17300 /* Handle the case of a symbol equated to another symbol. */
17301 while (symbol_equated_reloc_p (sym
))
17305 /* It's possible to get a loop here in a badly written program. */
17306 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17312 if (symbol_section_p (sym
))
17315 symsec
= S_GET_SEGMENT (sym
);
17317 /* This must duplicate the test in adjust_reloc_syms. */
17318 return (!bfd_is_und_section (symsec
)
17319 && !bfd_is_abs_section (symsec
)
17320 && !bfd_is_com_section (symsec
)
17321 && !s_is_linkonce (sym
, segtype
)
17323 /* A global or weak symbol is treated as external. */
17324 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17330 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17331 extended opcode. SEC is the section the frag is in. */
17334 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17337 const struct mips16_immed_operand
*op
;
17339 int mintiny
, maxtiny
;
17343 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17345 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17348 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17349 op
= mips16_immed_operands
;
17350 while (op
->type
!= type
)
17353 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17358 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17361 maxtiny
= 1 << op
->nbits
;
17366 maxtiny
= (1 << op
->nbits
) - 1;
17371 mintiny
= - (1 << (op
->nbits
- 1));
17372 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17375 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17376 val
= S_GET_VALUE (fragp
->fr_symbol
);
17377 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17383 /* We won't have the section when we are called from
17384 mips_relax_frag. However, we will always have been called
17385 from md_estimate_size_before_relax first. If this is a
17386 branch to a different section, we mark it as such. If SEC is
17387 NULL, and the frag is not marked, then it must be a branch to
17388 the same section. */
17391 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17396 /* Must have been called from md_estimate_size_before_relax. */
17399 fragp
->fr_subtype
=
17400 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17402 /* FIXME: We should support this, and let the linker
17403 catch branches and loads that are out of range. */
17404 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17405 _("unsupported PC relative reference to different section"));
17409 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17410 /* Assume non-extended on the first relaxation pass.
17411 The address we have calculated will be bogus if this is
17412 a forward branch to another frag, as the forward frag
17413 will have fr_address == 0. */
17417 /* In this case, we know for sure that the symbol fragment is in
17418 the same section. If the relax_marker of the symbol fragment
17419 differs from the relax_marker of this fragment, we have not
17420 yet adjusted the symbol fragment fr_address. We want to add
17421 in STRETCH in order to get a better estimate of the address.
17422 This particularly matters because of the shift bits. */
17424 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17428 /* Adjust stretch for any alignment frag. Note that if have
17429 been expanding the earlier code, the symbol may be
17430 defined in what appears to be an earlier frag. FIXME:
17431 This doesn't handle the fr_subtype field, which specifies
17432 a maximum number of bytes to skip when doing an
17434 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17436 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17439 stretch
= - ((- stretch
)
17440 & ~ ((1 << (int) f
->fr_offset
) - 1));
17442 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17451 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17453 /* The base address rules are complicated. The base address of
17454 a branch is the following instruction. The base address of a
17455 PC relative load or add is the instruction itself, but if it
17456 is in a delay slot (in which case it can not be extended) use
17457 the address of the instruction whose delay slot it is in. */
17458 if (type
== 'p' || type
== 'q')
17462 /* If we are currently assuming that this frag should be
17463 extended, then, the current address is two bytes
17465 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17468 /* Ignore the low bit in the target, since it will be set
17469 for a text label. */
17470 if ((val
& 1) != 0)
17473 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17475 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17478 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17480 /* Branch offsets have an implicit 0 in the lowest bit. */
17481 if (type
== 'p' || type
== 'q')
17484 /* If any of the shifted bits are set, we must use an extended
17485 opcode. If the address depends on the size of this
17486 instruction, this can lead to a loop, so we arrange to always
17487 use an extended opcode. We only check this when we are in
17488 the main relaxation loop, when SEC is NULL. */
17489 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17491 fragp
->fr_subtype
=
17492 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17496 /* If we are about to mark a frag as extended because the value
17497 is precisely maxtiny + 1, then there is a chance of an
17498 infinite loop as in the following code:
17503 In this case when the la is extended, foo is 0x3fc bytes
17504 away, so the la can be shrunk, but then foo is 0x400 away, so
17505 the la must be extended. To avoid this loop, we mark the
17506 frag as extended if it was small, and is about to become
17507 extended with a value of maxtiny + 1. */
17508 if (val
== ((maxtiny
+ 1) << op
->shift
)
17509 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17512 fragp
->fr_subtype
=
17513 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17517 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17518 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17520 if ((val
& ((1 << op
->shift
) - 1)) != 0
17521 || val
< (mintiny
<< op
->shift
)
17522 || val
> (maxtiny
<< op
->shift
))
17528 /* Compute the length of a branch sequence, and adjust the
17529 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17530 worst-case length is computed, with UPDATE being used to indicate
17531 whether an unconditional (-1), branch-likely (+1) or regular (0)
17532 branch is to be computed. */
17534 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17536 bfd_boolean toofar
;
17540 && S_IS_DEFINED (fragp
->fr_symbol
)
17541 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17546 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17548 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17552 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17555 /* If the symbol is not defined or it's in a different segment,
17556 assume the user knows what's going on and emit a short
17562 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17564 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17565 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17566 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17567 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17573 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17576 if (mips_pic
!= NO_PIC
)
17578 /* Additional space for PIC loading of target address. */
17580 if (mips_opts
.isa
== ISA_MIPS1
)
17581 /* Additional space for $at-stabilizing nop. */
17585 /* If branch is conditional. */
17586 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17593 /* Compute the length of a branch sequence, and adjust the
17594 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17595 worst-case length is computed, with UPDATE being used to indicate
17596 whether an unconditional (-1), or regular (0) branch is to be
17600 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17602 bfd_boolean toofar
;
17606 && S_IS_DEFINED (fragp
->fr_symbol
)
17607 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17612 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17613 /* Ignore the low bit in the target, since it will be set
17614 for a text label. */
17615 if ((val
& 1) != 0)
17618 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17622 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17625 /* If the symbol is not defined or it's in a different segment,
17626 assume the user knows what's going on and emit a short
17632 if (fragp
&& update
17633 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17634 fragp
->fr_subtype
= (toofar
17635 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17636 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17641 bfd_boolean compact_known
= fragp
!= NULL
;
17642 bfd_boolean compact
= FALSE
;
17643 bfd_boolean uncond
;
17646 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17648 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17650 uncond
= update
< 0;
17652 /* If label is out of range, we turn branch <br>:
17654 <br> label # 4 bytes
17660 nop # 2 bytes if compact && !PIC
17663 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17666 /* If assembling PIC code, we further turn:
17672 lw/ld at, %got(label)(gp) # 4 bytes
17673 d/addiu at, %lo(label) # 4 bytes
17676 if (mips_pic
!= NO_PIC
)
17679 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17681 <brneg> 0f # 4 bytes
17682 nop # 2 bytes if !compact
17685 length
+= (compact_known
&& compact
) ? 4 : 6;
17691 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17692 bit accordingly. */
17695 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17697 bfd_boolean toofar
;
17700 && S_IS_DEFINED (fragp
->fr_symbol
)
17701 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17707 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17708 /* Ignore the low bit in the target, since it will be set
17709 for a text label. */
17710 if ((val
& 1) != 0)
17713 /* Assume this is a 2-byte branch. */
17714 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17716 /* We try to avoid the infinite loop by not adding 2 more bytes for
17721 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17723 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17724 else if (type
== 'E')
17725 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17730 /* If the symbol is not defined or it's in a different segment,
17731 we emit a normal 32-bit branch. */
17734 if (fragp
&& update
17735 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17737 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17738 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17746 /* Estimate the size of a frag before relaxing. Unless this is the
17747 mips16, we are not really relaxing here, and the final size is
17748 encoded in the subtype information. For the mips16, we have to
17749 decide whether we are using an extended opcode or not. */
17752 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17756 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17759 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17761 return fragp
->fr_var
;
17764 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17765 /* We don't want to modify the EXTENDED bit here; it might get us
17766 into infinite loops. We change it only in mips_relax_frag(). */
17767 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17769 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17773 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17774 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17775 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17776 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17777 fragp
->fr_var
= length
;
17782 if (mips_pic
== NO_PIC
)
17783 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17784 else if (mips_pic
== SVR4_PIC
)
17785 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17786 else if (mips_pic
== VXWORKS_PIC
)
17787 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17794 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17795 return -RELAX_FIRST (fragp
->fr_subtype
);
17798 return -RELAX_SECOND (fragp
->fr_subtype
);
17801 /* This is called to see whether a reloc against a defined symbol
17802 should be converted into a reloc against a section. */
17805 mips_fix_adjustable (fixS
*fixp
)
17807 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17808 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17811 if (fixp
->fx_addsy
== NULL
)
17814 /* If symbol SYM is in a mergeable section, relocations of the form
17815 SYM + 0 can usually be made section-relative. The mergeable data
17816 is then identified by the section offset rather than by the symbol.
17818 However, if we're generating REL LO16 relocations, the offset is split
17819 between the LO16 and parterning high part relocation. The linker will
17820 need to recalculate the complete offset in order to correctly identify
17823 The linker has traditionally not looked for the parterning high part
17824 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17825 placed anywhere. Rather than break backwards compatibility by changing
17826 this, it seems better not to force the issue, and instead keep the
17827 original symbol. This will work with either linker behavior. */
17828 if ((lo16_reloc_p (fixp
->fx_r_type
)
17829 || reloc_needs_lo_p (fixp
->fx_r_type
))
17830 && HAVE_IN_PLACE_ADDENDS
17831 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17834 /* There is no place to store an in-place offset for JALR relocations.
17835 Likewise an in-range offset of limited PC-relative relocations may
17836 overflow the in-place relocatable field if recalculated against the
17837 start address of the symbol's containing section. */
17838 if (HAVE_IN_PLACE_ADDENDS
17839 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17840 || jalr_reloc_p (fixp
->fx_r_type
)))
17844 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17845 to a floating-point stub. The same is true for non-R_MIPS16_26
17846 relocations against MIPS16 functions; in this case, the stub becomes
17847 the function's canonical address.
17849 Floating-point stubs are stored in unique .mips16.call.* or
17850 .mips16.fn.* sections. If a stub T for function F is in section S,
17851 the first relocation in section S must be against F; this is how the
17852 linker determines the target function. All relocations that might
17853 resolve to T must also be against F. We therefore have the following
17854 restrictions, which are given in an intentionally-redundant way:
17856 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17859 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17860 if that stub might be used.
17862 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17865 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17866 that stub might be used.
17868 There is a further restriction:
17870 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17871 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17872 targets with in-place addends; the relocation field cannot
17873 encode the low bit.
17875 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17876 against a MIPS16 symbol. We deal with (5) by by not reducing any
17877 such relocations on REL targets.
17879 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17880 relocation against some symbol R, no relocation against R may be
17881 reduced. (Note that this deals with (2) as well as (1) because
17882 relocations against global symbols will never be reduced on ELF
17883 targets.) This approach is a little simpler than trying to detect
17884 stub sections, and gives the "all or nothing" per-symbol consistency
17885 that we have for MIPS16 symbols. */
17887 && fixp
->fx_subsy
== NULL
17888 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17889 || *symbol_get_tc (fixp
->fx_addsy
)
17890 || (HAVE_IN_PLACE_ADDENDS
17891 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17892 && jmp_reloc_p (fixp
->fx_r_type
))))
17899 /* Translate internal representation of relocation info to BFD target
17903 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17905 static arelent
*retval
[4];
17907 bfd_reloc_code_real_type code
;
17909 memset (retval
, 0, sizeof(retval
));
17910 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
17911 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
17912 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17913 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17915 if (fixp
->fx_pcrel
)
17917 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17918 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17919 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17920 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17922 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17923 Relocations want only the symbol offset. */
17924 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17927 /* A gruesome hack which is a result of the gruesome gas
17928 reloc handling. What's worse, for COFF (as opposed to
17929 ECOFF), we might need yet another copy of reloc->address.
17930 See bfd_install_relocation. */
17931 reloc
->addend
+= reloc
->address
;
17935 reloc
->addend
= fixp
->fx_addnumber
;
17937 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17938 entry to be used in the relocation's section offset. */
17939 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17941 reloc
->address
= reloc
->addend
;
17945 code
= fixp
->fx_r_type
;
17947 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17948 if (reloc
->howto
== NULL
)
17950 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17951 _("Can not represent %s relocation in this object file format"),
17952 bfd_get_reloc_code_name (code
));
17959 /* Relax a machine dependent frag. This returns the amount by which
17960 the current size of the frag should change. */
17963 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17965 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17967 offsetT old_var
= fragp
->fr_var
;
17969 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17971 return fragp
->fr_var
- old_var
;
17974 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17976 offsetT old_var
= fragp
->fr_var
;
17977 offsetT new_var
= 4;
17979 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17980 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17981 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17982 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17983 fragp
->fr_var
= new_var
;
17985 return new_var
- old_var
;
17988 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17991 if (mips16_extended_frag (fragp
, NULL
, stretch
))
17993 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17995 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18000 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18002 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18009 /* Convert a machine dependent frag. */
18012 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18014 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18017 unsigned long insn
;
18021 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18022 insn
= read_insn (buf
);
18024 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18026 /* We generate a fixup instead of applying it right now
18027 because, if there are linker relaxations, we're going to
18028 need the relocations. */
18029 exp
.X_op
= O_symbol
;
18030 exp
.X_add_symbol
= fragp
->fr_symbol
;
18031 exp
.X_add_number
= fragp
->fr_offset
;
18033 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18034 BFD_RELOC_16_PCREL_S2
);
18035 fixp
->fx_file
= fragp
->fr_file
;
18036 fixp
->fx_line
= fragp
->fr_line
;
18038 buf
= write_insn (buf
, insn
);
18044 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18045 _("Relaxed out-of-range branch into a jump"));
18047 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18050 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18052 /* Reverse the branch. */
18053 switch ((insn
>> 28) & 0xf)
18056 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18057 have the condition reversed by tweaking a single
18058 bit, and their opcodes all have 0x4???????. */
18059 gas_assert ((insn
& 0xf1000000) == 0x41000000);
18060 insn
^= 0x00010000;
18064 /* bltz 0x04000000 bgez 0x04010000
18065 bltzal 0x04100000 bgezal 0x04110000 */
18066 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18067 insn
^= 0x00010000;
18071 /* beq 0x10000000 bne 0x14000000
18072 blez 0x18000000 bgtz 0x1c000000 */
18073 insn
^= 0x04000000;
18081 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18083 /* Clear the and-link bit. */
18084 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18086 /* bltzal 0x04100000 bgezal 0x04110000
18087 bltzall 0x04120000 bgezall 0x04130000 */
18088 insn
&= ~0x00100000;
18091 /* Branch over the branch (if the branch was likely) or the
18092 full jump (not likely case). Compute the offset from the
18093 current instruction to branch to. */
18094 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18098 /* How many bytes in instructions we've already emitted? */
18099 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18100 /* How many bytes in instructions from here to the end? */
18101 i
= fragp
->fr_var
- i
;
18103 /* Convert to instruction count. */
18105 /* Branch counts from the next instruction. */
18108 /* Branch over the jump. */
18109 buf
= write_insn (buf
, insn
);
18112 buf
= write_insn (buf
, 0);
18114 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18116 /* beql $0, $0, 2f */
18118 /* Compute the PC offset from the current instruction to
18119 the end of the variable frag. */
18120 /* How many bytes in instructions we've already emitted? */
18121 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18122 /* How many bytes in instructions from here to the end? */
18123 i
= fragp
->fr_var
- i
;
18124 /* Convert to instruction count. */
18126 /* Don't decrement i, because we want to branch over the
18130 buf
= write_insn (buf
, insn
);
18131 buf
= write_insn (buf
, 0);
18135 if (mips_pic
== NO_PIC
)
18138 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18139 ? 0x0c000000 : 0x08000000);
18140 exp
.X_op
= O_symbol
;
18141 exp
.X_add_symbol
= fragp
->fr_symbol
;
18142 exp
.X_add_number
= fragp
->fr_offset
;
18144 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18145 FALSE
, BFD_RELOC_MIPS_JMP
);
18146 fixp
->fx_file
= fragp
->fr_file
;
18147 fixp
->fx_line
= fragp
->fr_line
;
18149 buf
= write_insn (buf
, insn
);
18153 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18155 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18156 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18157 insn
|= at
<< OP_SH_RT
;
18158 exp
.X_op
= O_symbol
;
18159 exp
.X_add_symbol
= fragp
->fr_symbol
;
18160 exp
.X_add_number
= fragp
->fr_offset
;
18162 if (fragp
->fr_offset
)
18164 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18165 exp
.X_add_number
= 0;
18168 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18169 FALSE
, BFD_RELOC_MIPS_GOT16
);
18170 fixp
->fx_file
= fragp
->fr_file
;
18171 fixp
->fx_line
= fragp
->fr_line
;
18173 buf
= write_insn (buf
, insn
);
18175 if (mips_opts
.isa
== ISA_MIPS1
)
18177 buf
= write_insn (buf
, 0);
18179 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18180 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18181 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18183 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18184 FALSE
, BFD_RELOC_LO16
);
18185 fixp
->fx_file
= fragp
->fr_file
;
18186 fixp
->fx_line
= fragp
->fr_line
;
18188 buf
= write_insn (buf
, insn
);
18191 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18195 insn
|= at
<< OP_SH_RS
;
18197 buf
= write_insn (buf
, insn
);
18201 fragp
->fr_fix
+= fragp
->fr_var
;
18202 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18206 /* Relax microMIPS branches. */
18207 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18209 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18210 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18211 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18212 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18213 bfd_boolean short_ds
;
18214 unsigned long insn
;
18218 exp
.X_op
= O_symbol
;
18219 exp
.X_add_symbol
= fragp
->fr_symbol
;
18220 exp
.X_add_number
= fragp
->fr_offset
;
18222 fragp
->fr_fix
+= fragp
->fr_var
;
18224 /* Handle 16-bit branches that fit or are forced to fit. */
18225 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18227 /* We generate a fixup instead of applying it right now,
18228 because if there is linker relaxation, we're going to
18229 need the relocations. */
18231 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18232 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18233 else if (type
== 'E')
18234 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18235 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18239 fixp
->fx_file
= fragp
->fr_file
;
18240 fixp
->fx_line
= fragp
->fr_line
;
18242 /* These relocations can have an addend that won't fit in
18244 fixp
->fx_no_overflow
= 1;
18249 /* Handle 32-bit branches that fit or are forced to fit. */
18250 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18251 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18253 /* We generate a fixup instead of applying it right now,
18254 because if there is linker relaxation, we're going to
18255 need the relocations. */
18256 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18257 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18258 fixp
->fx_file
= fragp
->fr_file
;
18259 fixp
->fx_line
= fragp
->fr_line
;
18265 /* Relax 16-bit branches to 32-bit branches. */
18268 insn
= read_compressed_insn (buf
, 2);
18270 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18271 insn
= 0x94000000; /* beq */
18272 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18274 unsigned long regno
;
18276 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18277 regno
= micromips_to_32_reg_d_map
[regno
];
18278 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18279 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18284 /* Nothing else to do, just write it out. */
18285 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18286 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18288 buf
= write_compressed_insn (buf
, insn
, 4);
18289 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18294 insn
= read_compressed_insn (buf
, 4);
18296 /* Relax 32-bit branches to a sequence of instructions. */
18297 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18298 _("Relaxed out-of-range branch into a jump"));
18300 /* Set the short-delay-slot bit. */
18301 short_ds
= al
&& (insn
& 0x02000000) != 0;
18303 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18307 /* Reverse the branch. */
18308 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18309 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18310 insn
^= 0x20000000;
18311 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18312 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18313 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18314 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18315 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18316 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18317 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18318 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18319 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18320 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18321 insn
^= 0x00400000;
18322 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18323 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18324 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18325 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18326 insn
^= 0x00200000;
18332 /* Clear the and-link and short-delay-slot bits. */
18333 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18335 /* bltzal 0x40200000 bgezal 0x40600000 */
18336 /* bltzals 0x42200000 bgezals 0x42600000 */
18337 insn
&= ~0x02200000;
18340 /* Make a label at the end for use with the branch. */
18341 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18342 micromips_label_inc ();
18343 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18345 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18349 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18350 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18351 fixp
->fx_file
= fragp
->fr_file
;
18352 fixp
->fx_line
= fragp
->fr_line
;
18354 /* Branch over the jump. */
18355 buf
= write_compressed_insn (buf
, insn
, 4);
18358 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18361 if (mips_pic
== NO_PIC
)
18363 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18365 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18366 insn
= al
? jal
: 0xd4000000;
18368 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18369 BFD_RELOC_MICROMIPS_JMP
);
18370 fixp
->fx_file
= fragp
->fr_file
;
18371 fixp
->fx_line
= fragp
->fr_line
;
18373 buf
= write_compressed_insn (buf
, insn
, 4);
18376 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18380 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18381 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18382 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18384 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18385 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18386 insn
|= at
<< MICROMIPSOP_SH_RT
;
18388 if (exp
.X_add_number
)
18390 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18391 exp
.X_add_number
= 0;
18394 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18395 BFD_RELOC_MICROMIPS_GOT16
);
18396 fixp
->fx_file
= fragp
->fr_file
;
18397 fixp
->fx_line
= fragp
->fr_line
;
18399 buf
= write_compressed_insn (buf
, insn
, 4);
18401 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18402 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18403 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18405 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18406 BFD_RELOC_MICROMIPS_LO16
);
18407 fixp
->fx_file
= fragp
->fr_file
;
18408 fixp
->fx_line
= fragp
->fr_line
;
18410 buf
= write_compressed_insn (buf
, insn
, 4);
18412 /* jr/jrc/jalr/jalrs $at */
18413 insn
= al
? jalr
: jr
;
18414 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18416 buf
= write_compressed_insn (buf
, insn
, 2);
18419 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18423 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18426 const struct mips16_immed_operand
*op
;
18429 unsigned int user_length
, length
;
18430 unsigned long insn
;
18433 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18434 op
= mips16_immed_operands
;
18435 while (op
->type
!= type
)
18438 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18439 val
= resolve_symbol_value (fragp
->fr_symbol
);
18444 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18446 /* The rules for the base address of a PC relative reloc are
18447 complicated; see mips16_extended_frag. */
18448 if (type
== 'p' || type
== 'q')
18453 /* Ignore the low bit in the target, since it will be
18454 set for a text label. */
18455 if ((val
& 1) != 0)
18458 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18460 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18463 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18466 /* Make sure the section winds up with the alignment we have
18469 record_alignment (asec
, op
->shift
);
18473 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18474 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18475 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18476 _("extended instruction in delay slot"));
18478 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18480 insn
= read_compressed_insn (buf
, 2);
18482 insn
|= MIPS16_EXTEND
;
18484 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18486 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18491 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18492 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18494 length
= (ext
? 4 : 2);
18495 gas_assert (mips16_opcode_length (insn
) == length
);
18496 write_compressed_insn (buf
, insn
, length
);
18497 fragp
->fr_fix
+= length
;
18501 relax_substateT subtype
= fragp
->fr_subtype
;
18502 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18503 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18507 first
= RELAX_FIRST (subtype
);
18508 second
= RELAX_SECOND (subtype
);
18509 fixp
= (fixS
*) fragp
->fr_opcode
;
18511 /* If the delay slot chosen does not match the size of the instruction,
18512 then emit a warning. */
18513 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18514 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18519 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18520 | RELAX_DELAY_SLOT_SIZE_FIRST
18521 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18522 msg
= macro_warning (s
);
18524 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18528 /* Possibly emit a warning if we've chosen the longer option. */
18529 if (use_second
== second_longer
)
18535 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18536 msg
= macro_warning (s
);
18538 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18542 /* Go through all the fixups for the first sequence. Disable them
18543 (by marking them as done) if we're going to use the second
18544 sequence instead. */
18546 && fixp
->fx_frag
== fragp
18547 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18549 if (subtype
& RELAX_USE_SECOND
)
18551 fixp
= fixp
->fx_next
;
18554 /* Go through the fixups for the second sequence. Disable them if
18555 we're going to use the first sequence, otherwise adjust their
18556 addresses to account for the relaxation. */
18557 while (fixp
&& fixp
->fx_frag
== fragp
)
18559 if (subtype
& RELAX_USE_SECOND
)
18560 fixp
->fx_where
-= first
;
18563 fixp
= fixp
->fx_next
;
18566 /* Now modify the frag contents. */
18567 if (subtype
& RELAX_USE_SECOND
)
18571 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18572 memmove (start
, start
+ first
, second
);
18573 fragp
->fr_fix
-= first
;
18576 fragp
->fr_fix
-= second
;
18582 /* This function is called after the relocs have been generated.
18583 We've been storing mips16 text labels as odd. Here we convert them
18584 back to even for the convenience of the debugger. */
18587 mips_frob_file_after_relocs (void)
18590 unsigned int count
, i
;
18595 syms
= bfd_get_outsymbols (stdoutput
);
18596 count
= bfd_get_symcount (stdoutput
);
18597 for (i
= 0; i
< count
; i
++, syms
++)
18598 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18599 && ((*syms
)->value
& 1) != 0)
18601 (*syms
)->value
&= ~1;
18602 /* If the symbol has an odd size, it was probably computed
18603 incorrectly, so adjust that as well. */
18604 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18605 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18611 /* This function is called whenever a label is defined, including fake
18612 labels instantiated off the dot special symbol. It is used when
18613 handling branch delays; if a branch has a label, we assume we cannot
18614 move it. This also bumps the value of the symbol by 1 in compressed
18618 mips_record_label (symbolS
*sym
)
18620 segment_info_type
*si
= seg_info (now_seg
);
18621 struct insn_label_list
*l
;
18623 if (free_insn_labels
== NULL
)
18624 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18627 l
= free_insn_labels
;
18628 free_insn_labels
= l
->next
;
18632 l
->next
= si
->label_list
;
18633 si
->label_list
= l
;
18636 /* This function is called as tc_frob_label() whenever a label is defined
18637 and adds a DWARF-2 record we only want for true labels. */
18640 mips_define_label (symbolS
*sym
)
18642 mips_record_label (sym
);
18644 dwarf2_emit_label (sym
);
18648 /* This function is called by tc_new_dot_label whenever a new dot symbol
18652 mips_add_dot_label (symbolS
*sym
)
18654 mips_record_label (sym
);
18655 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18656 mips_compressed_mark_label (sym
);
18659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18661 /* Some special processing for a MIPS ELF file. */
18664 mips_elf_final_processing (void)
18666 /* Write out the register information. */
18667 if (mips_abi
!= N64_ABI
)
18671 s
.ri_gprmask
= mips_gprmask
;
18672 s
.ri_cprmask
[0] = mips_cprmask
[0];
18673 s
.ri_cprmask
[1] = mips_cprmask
[1];
18674 s
.ri_cprmask
[2] = mips_cprmask
[2];
18675 s
.ri_cprmask
[3] = mips_cprmask
[3];
18676 /* The gp_value field is set by the MIPS ELF backend. */
18678 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18679 ((Elf32_External_RegInfo
*)
18680 mips_regmask_frag
));
18684 Elf64_Internal_RegInfo s
;
18686 s
.ri_gprmask
= mips_gprmask
;
18688 s
.ri_cprmask
[0] = mips_cprmask
[0];
18689 s
.ri_cprmask
[1] = mips_cprmask
[1];
18690 s
.ri_cprmask
[2] = mips_cprmask
[2];
18691 s
.ri_cprmask
[3] = mips_cprmask
[3];
18692 /* The gp_value field is set by the MIPS ELF backend. */
18694 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18695 ((Elf64_External_RegInfo
*)
18696 mips_regmask_frag
));
18699 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18700 sort of BFD interface for this. */
18701 if (mips_any_noreorder
)
18702 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18703 if (mips_pic
!= NO_PIC
)
18705 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18706 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18709 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18711 /* Set MIPS ELF flags for ASEs. */
18712 /* We may need to define a new flag for DSP ASE, and set this flag when
18713 file_ase_dsp is true. */
18714 /* Same for DSP R2. */
18715 /* We may need to define a new flag for MT ASE, and set this flag when
18716 file_ase_mt is true. */
18717 if (file_ase_mips16
)
18718 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18719 if (file_ase_micromips
)
18720 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18721 #if 0 /* XXX FIXME */
18722 if (file_ase_mips3d
)
18723 elf_elfheader (stdoutput
)->e_flags
|= ???;
18726 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18728 /* Set the MIPS ELF ABI flags. */
18729 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18730 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18731 else if (mips_abi
== O64_ABI
)
18732 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18733 else if (mips_abi
== EABI_ABI
)
18735 if (!file_mips_gp32
)
18736 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18738 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18740 else if (mips_abi
== N32_ABI
)
18741 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18743 /* Nothing to do for N64_ABI. */
18745 if (mips_32bitmode
)
18746 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18748 #if 0 /* XXX FIXME */
18749 /* 32 bit code with 64 bit FP registers. */
18750 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18751 elf_elfheader (stdoutput
)->e_flags
|= ???;
18755 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18757 typedef struct proc
{
18759 symbolS
*func_end_sym
;
18760 unsigned long reg_mask
;
18761 unsigned long reg_offset
;
18762 unsigned long fpreg_mask
;
18763 unsigned long fpreg_offset
;
18764 unsigned long frame_offset
;
18765 unsigned long frame_reg
;
18766 unsigned long pc_reg
;
18769 static procS cur_proc
;
18770 static procS
*cur_proc_ptr
;
18771 static int numprocs
;
18773 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18774 as "2", and a normal nop as "0". */
18776 #define NOP_OPCODE_MIPS 0
18777 #define NOP_OPCODE_MIPS16 1
18778 #define NOP_OPCODE_MICROMIPS 2
18781 mips_nop_opcode (void)
18783 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18784 return NOP_OPCODE_MICROMIPS
;
18785 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18786 return NOP_OPCODE_MIPS16
;
18788 return NOP_OPCODE_MIPS
;
18791 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18792 32-bit microMIPS NOPs here (if applicable). */
18795 mips_handle_align (fragS
*fragp
)
18799 int bytes
, size
, excess
;
18802 if (fragp
->fr_type
!= rs_align_code
)
18805 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18807 switch (nop_opcode
)
18809 case NOP_OPCODE_MICROMIPS
:
18810 opcode
= micromips_nop32_insn
.insn_opcode
;
18813 case NOP_OPCODE_MIPS16
:
18814 opcode
= mips16_nop_insn
.insn_opcode
;
18817 case NOP_OPCODE_MIPS
:
18819 opcode
= nop_insn
.insn_opcode
;
18824 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18825 excess
= bytes
% size
;
18827 /* Handle the leading part if we're not inserting a whole number of
18828 instructions, and make it the end of the fixed part of the frag.
18829 Try to fit in a short microMIPS NOP if applicable and possible,
18830 and use zeroes otherwise. */
18831 gas_assert (excess
< 4);
18832 fragp
->fr_fix
+= excess
;
18837 /* Fall through. */
18839 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
18841 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18845 /* Fall through. */
18848 /* Fall through. */
18853 md_number_to_chars (p
, opcode
, size
);
18854 fragp
->fr_var
= size
;
18858 md_obj_begin (void)
18865 /* Check for premature end, nesting errors, etc. */
18867 as_warn (_("missing .end at end of assembly"));
18876 if (*input_line_pointer
== '-')
18878 ++input_line_pointer
;
18881 if (!ISDIGIT (*input_line_pointer
))
18882 as_bad (_("expected simple number"));
18883 if (input_line_pointer
[0] == '0')
18885 if (input_line_pointer
[1] == 'x')
18887 input_line_pointer
+= 2;
18888 while (ISXDIGIT (*input_line_pointer
))
18891 val
|= hex_value (*input_line_pointer
++);
18893 return negative
? -val
: val
;
18897 ++input_line_pointer
;
18898 while (ISDIGIT (*input_line_pointer
))
18901 val
|= *input_line_pointer
++ - '0';
18903 return negative
? -val
: val
;
18906 if (!ISDIGIT (*input_line_pointer
))
18908 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18909 *input_line_pointer
, *input_line_pointer
);
18910 as_warn (_("invalid number"));
18913 while (ISDIGIT (*input_line_pointer
))
18916 val
+= *input_line_pointer
++ - '0';
18918 return negative
? -val
: val
;
18921 /* The .file directive; just like the usual .file directive, but there
18922 is an initial number which is the ECOFF file index. In the non-ECOFF
18923 case .file implies DWARF-2. */
18926 s_mips_file (int x ATTRIBUTE_UNUSED
)
18928 static int first_file_directive
= 0;
18930 if (ECOFF_DEBUGGING
)
18939 filename
= dwarf2_directive_file (0);
18941 /* Versions of GCC up to 3.1 start files with a ".file"
18942 directive even for stabs output. Make sure that this
18943 ".file" is handled. Note that you need a version of GCC
18944 after 3.1 in order to support DWARF-2 on MIPS. */
18945 if (filename
!= NULL
&& ! first_file_directive
)
18947 (void) new_logical_line (filename
, -1);
18948 s_app_file_string (filename
, 0);
18950 first_file_directive
= 1;
18954 /* The .loc directive, implying DWARF-2. */
18957 s_mips_loc (int x ATTRIBUTE_UNUSED
)
18959 if (!ECOFF_DEBUGGING
)
18960 dwarf2_directive_loc (0);
18963 /* The .end directive. */
18966 s_mips_end (int x ATTRIBUTE_UNUSED
)
18970 /* Following functions need their own .frame and .cprestore directives. */
18971 mips_frame_reg_valid
= 0;
18972 mips_cprestore_valid
= 0;
18974 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
18977 demand_empty_rest_of_line ();
18982 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
18983 as_warn (_(".end not in text section"));
18987 as_warn (_(".end directive without a preceding .ent directive."));
18988 demand_empty_rest_of_line ();
18994 gas_assert (S_GET_NAME (p
));
18995 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
18996 as_warn (_(".end symbol does not match .ent symbol."));
18998 if (debug_type
== DEBUG_STABS
)
18999 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19003 as_warn (_(".end directive missing or unknown symbol"));
19006 /* Create an expression to calculate the size of the function. */
19007 if (p
&& cur_proc_ptr
)
19009 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19010 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19013 exp
->X_op
= O_subtract
;
19014 exp
->X_add_symbol
= symbol_temp_new_now ();
19015 exp
->X_op_symbol
= p
;
19016 exp
->X_add_number
= 0;
19018 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19021 /* Generate a .pdr section. */
19022 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
19024 segT saved_seg
= now_seg
;
19025 subsegT saved_subseg
= now_subseg
;
19029 #ifdef md_flush_pending_output
19030 md_flush_pending_output ();
19033 gas_assert (pdr_seg
);
19034 subseg_set (pdr_seg
, 0);
19036 /* Write the symbol. */
19037 exp
.X_op
= O_symbol
;
19038 exp
.X_add_symbol
= p
;
19039 exp
.X_add_number
= 0;
19040 emit_expr (&exp
, 4);
19042 fragp
= frag_more (7 * 4);
19044 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19045 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19046 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19047 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19048 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19049 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19050 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19052 subseg_set (saved_seg
, saved_subseg
);
19054 #endif /* OBJ_ELF */
19056 cur_proc_ptr
= NULL
;
19059 /* The .aent and .ent directives. */
19062 s_mips_ent (int aent
)
19066 symbolP
= get_symbol ();
19067 if (*input_line_pointer
== ',')
19068 ++input_line_pointer
;
19069 SKIP_WHITESPACE ();
19070 if (ISDIGIT (*input_line_pointer
)
19071 || *input_line_pointer
== '-')
19074 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19075 as_warn (_(".ent or .aent not in text section."));
19077 if (!aent
&& cur_proc_ptr
)
19078 as_warn (_("missing .end"));
19082 /* This function needs its own .frame and .cprestore directives. */
19083 mips_frame_reg_valid
= 0;
19084 mips_cprestore_valid
= 0;
19086 cur_proc_ptr
= &cur_proc
;
19087 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19089 cur_proc_ptr
->func_sym
= symbolP
;
19093 if (debug_type
== DEBUG_STABS
)
19094 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19095 S_GET_NAME (symbolP
));
19098 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19100 demand_empty_rest_of_line ();
19103 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19104 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19105 s_mips_frame is used so that we can set the PDR information correctly.
19106 We can't use the ecoff routines because they make reference to the ecoff
19107 symbol table (in the mdebug section). */
19110 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19113 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19117 if (cur_proc_ptr
== (procS
*) NULL
)
19119 as_warn (_(".frame outside of .ent"));
19120 demand_empty_rest_of_line ();
19124 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19126 SKIP_WHITESPACE ();
19127 if (*input_line_pointer
++ != ','
19128 || get_absolute_expression_and_terminator (&val
) != ',')
19130 as_warn (_("Bad .frame directive"));
19131 --input_line_pointer
;
19132 demand_empty_rest_of_line ();
19136 cur_proc_ptr
->frame_offset
= val
;
19137 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19139 demand_empty_rest_of_line ();
19142 #endif /* OBJ_ELF */
19146 /* The .fmask and .mask directives. If the mdebug section is present
19147 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19148 embedded targets, s_mips_mask is used so that we can set the PDR
19149 information correctly. We can't use the ecoff routines because they
19150 make reference to the ecoff symbol table (in the mdebug section). */
19153 s_mips_mask (int reg_type
)
19156 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19160 if (cur_proc_ptr
== (procS
*) NULL
)
19162 as_warn (_(".mask/.fmask outside of .ent"));
19163 demand_empty_rest_of_line ();
19167 if (get_absolute_expression_and_terminator (&mask
) != ',')
19169 as_warn (_("Bad .mask/.fmask directive"));
19170 --input_line_pointer
;
19171 demand_empty_rest_of_line ();
19175 off
= get_absolute_expression ();
19177 if (reg_type
== 'F')
19179 cur_proc_ptr
->fpreg_mask
= mask
;
19180 cur_proc_ptr
->fpreg_offset
= off
;
19184 cur_proc_ptr
->reg_mask
= mask
;
19185 cur_proc_ptr
->reg_offset
= off
;
19188 demand_empty_rest_of_line ();
19191 #endif /* OBJ_ELF */
19192 s_ignore (reg_type
);
19195 /* A table describing all the processors gas knows about. Names are
19196 matched in the order listed.
19198 To ease comparison, please keep this table in the same order as
19199 gcc's mips_cpu_info_table[]. */
19200 static const struct mips_cpu_info mips_cpu_info_table
[] =
19202 /* Entries for generic ISAs */
19203 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
19204 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
19205 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
19206 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
19207 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
19208 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
19209 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19210 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
19211 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
19214 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
19215 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
19216 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
19219 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
19222 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
19223 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
19224 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
19225 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
19226 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
19227 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
19228 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
19229 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
19230 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
19231 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
19232 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
19233 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
19234 { "r5900", 0, ISA_MIPS3
, CPU_R5900
},
19235 /* ST Microelectronics Loongson 2E and 2F cores */
19236 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19237 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19240 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
19241 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
19242 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
19243 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
19244 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
19245 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
19246 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
19247 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
19248 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
19249 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
19250 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
19251 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
19252 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
19253 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
19254 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
19257 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
19258 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
19259 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
19260 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19262 /* MIPS 32 Release 2 */
19263 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19264 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19265 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19266 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19267 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19268 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19269 { "m14k", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19270 { "m14kc", MIPS_CPU_ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19271 { "m14ke", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19272 ISA_MIPS32R2
, CPU_MIPS32R2
},
19273 { "m14kec", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
| MIPS_CPU_ASE_MCU
,
19274 ISA_MIPS32R2
, CPU_MIPS32R2
},
19275 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19276 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19277 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19278 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19279 /* Deprecated forms of the above. */
19280 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19281 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19282 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19283 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19284 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19285 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19286 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19287 /* Deprecated forms of the above. */
19288 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19289 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19290 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19291 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19292 ISA_MIPS32R2
, CPU_MIPS32R2
},
19293 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19294 ISA_MIPS32R2
, CPU_MIPS32R2
},
19295 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19296 ISA_MIPS32R2
, CPU_MIPS32R2
},
19297 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19298 ISA_MIPS32R2
, CPU_MIPS32R2
},
19299 /* Deprecated forms of the above. */
19300 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19301 ISA_MIPS32R2
, CPU_MIPS32R2
},
19302 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19303 ISA_MIPS32R2
, CPU_MIPS32R2
},
19304 /* 34Kn is a 34kc without DSP. */
19305 { "34kn", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19306 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19307 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19308 ISA_MIPS32R2
, CPU_MIPS32R2
},
19309 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19310 ISA_MIPS32R2
, CPU_MIPS32R2
},
19311 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19312 ISA_MIPS32R2
, CPU_MIPS32R2
},
19313 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19314 ISA_MIPS32R2
, CPU_MIPS32R2
},
19315 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19316 ISA_MIPS32R2
, CPU_MIPS32R2
},
19317 /* Deprecated forms of the above. */
19318 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19319 ISA_MIPS32R2
, CPU_MIPS32R2
},
19320 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
19321 ISA_MIPS32R2
, CPU_MIPS32R2
},
19322 /* 1004K cores are multiprocessor versions of the 34K. */
19323 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19324 ISA_MIPS32R2
, CPU_MIPS32R2
},
19325 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19326 ISA_MIPS32R2
, CPU_MIPS32R2
},
19327 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19328 ISA_MIPS32R2
, CPU_MIPS32R2
},
19329 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
19330 ISA_MIPS32R2
, CPU_MIPS32R2
},
19333 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
19334 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
19335 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19336 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19338 /* Broadcom SB-1 CPU core */
19339 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19340 ISA_MIPS64
, CPU_SB1
},
19341 /* Broadcom SB-1A CPU core */
19342 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
19343 ISA_MIPS64
, CPU_SB1
},
19345 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19347 /* MIPS 64 Release 2 */
19349 /* Cavium Networks Octeon CPU core */
19350 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
19351 { "octeon+", 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19352 { "octeon2", 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19355 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
19358 XLP is mostly like XLR, with the prominent exception that it is
19359 MIPS64R2 rather than MIPS64. */
19360 { "xlp", 0, ISA_MIPS64R2
, CPU_XLR
},
19367 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19368 with a final "000" replaced by "k". Ignore case.
19370 Note: this function is shared between GCC and GAS. */
19373 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19375 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19376 given
++, canonical
++;
19378 return ((*given
== 0 && *canonical
== 0)
19379 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19383 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19384 CPU name. We've traditionally allowed a lot of variation here.
19386 Note: this function is shared between GCC and GAS. */
19389 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19391 /* First see if the name matches exactly, or with a final "000"
19392 turned into "k". */
19393 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19396 /* If not, try comparing based on numerical designation alone.
19397 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19398 if (TOLOWER (*given
) == 'r')
19400 if (!ISDIGIT (*given
))
19403 /* Skip over some well-known prefixes in the canonical name,
19404 hoping to find a number there too. */
19405 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19407 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19409 else if (TOLOWER (canonical
[0]) == 'r')
19412 return mips_strict_matching_cpu_name_p (canonical
, given
);
19416 /* Parse an option that takes the name of a processor as its argument.
19417 OPTION is the name of the option and CPU_STRING is the argument.
19418 Return the corresponding processor enumeration if the CPU_STRING is
19419 recognized, otherwise report an error and return null.
19421 A similar function exists in GCC. */
19423 static const struct mips_cpu_info
*
19424 mips_parse_cpu (const char *option
, const char *cpu_string
)
19426 const struct mips_cpu_info
*p
;
19428 /* 'from-abi' selects the most compatible architecture for the given
19429 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19430 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19431 version. Look first at the -mgp options, if given, otherwise base
19432 the choice on MIPS_DEFAULT_64BIT.
19434 Treat NO_ABI like the EABIs. One reason to do this is that the
19435 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19436 architecture. This code picks MIPS I for 'mips' and MIPS III for
19437 'mips64', just as we did in the days before 'from-abi'. */
19438 if (strcasecmp (cpu_string
, "from-abi") == 0)
19440 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19441 return mips_cpu_info_from_isa (ISA_MIPS1
);
19443 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19444 return mips_cpu_info_from_isa (ISA_MIPS3
);
19446 if (file_mips_gp32
>= 0)
19447 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19449 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19454 /* 'default' has traditionally been a no-op. Probably not very useful. */
19455 if (strcasecmp (cpu_string
, "default") == 0)
19458 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19459 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19462 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19466 /* Return the canonical processor information for ISA (a member of the
19467 ISA_MIPS* enumeration). */
19469 static const struct mips_cpu_info
*
19470 mips_cpu_info_from_isa (int isa
)
19474 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19475 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19476 && isa
== mips_cpu_info_table
[i
].isa
)
19477 return (&mips_cpu_info_table
[i
]);
19482 static const struct mips_cpu_info
*
19483 mips_cpu_info_from_arch (int arch
)
19487 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19488 if (arch
== mips_cpu_info_table
[i
].cpu
)
19489 return (&mips_cpu_info_table
[i
]);
19495 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19499 fprintf (stream
, "%24s", "");
19504 fprintf (stream
, ", ");
19508 if (*col_p
+ strlen (string
) > 72)
19510 fprintf (stream
, "\n%24s", "");
19514 fprintf (stream
, "%s", string
);
19515 *col_p
+= strlen (string
);
19521 md_show_usage (FILE *stream
)
19526 fprintf (stream
, _("\
19528 -EB generate big endian output\n\
19529 -EL generate little endian output\n\
19530 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19531 -G NUM allow referencing objects up to NUM bytes\n\
19532 implicitly with the gp register [default 8]\n"));
19533 fprintf (stream
, _("\
19534 -mips1 generate MIPS ISA I instructions\n\
19535 -mips2 generate MIPS ISA II instructions\n\
19536 -mips3 generate MIPS ISA III instructions\n\
19537 -mips4 generate MIPS ISA IV instructions\n\
19538 -mips5 generate MIPS ISA V instructions\n\
19539 -mips32 generate MIPS32 ISA instructions\n\
19540 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19541 -mips64 generate MIPS64 ISA instructions\n\
19542 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19543 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19547 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19548 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19549 show (stream
, "from-abi", &column
, &first
);
19550 fputc ('\n', stream
);
19552 fprintf (stream
, _("\
19553 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19554 -no-mCPU don't generate code specific to CPU.\n\
19555 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19559 show (stream
, "3900", &column
, &first
);
19560 show (stream
, "4010", &column
, &first
);
19561 show (stream
, "4100", &column
, &first
);
19562 show (stream
, "4650", &column
, &first
);
19563 fputc ('\n', stream
);
19565 fprintf (stream
, _("\
19566 -mips16 generate mips16 instructions\n\
19567 -no-mips16 do not generate mips16 instructions\n"));
19568 fprintf (stream
, _("\
19569 -mmicromips generate microMIPS instructions\n\
19570 -mno-micromips do not generate microMIPS instructions\n"));
19571 fprintf (stream
, _("\
19572 -msmartmips generate smartmips instructions\n\
19573 -mno-smartmips do not generate smartmips instructions\n"));
19574 fprintf (stream
, _("\
19575 -mdsp generate DSP instructions\n\
19576 -mno-dsp do not generate DSP instructions\n"));
19577 fprintf (stream
, _("\
19578 -mdspr2 generate DSP R2 instructions\n\
19579 -mno-dspr2 do not generate DSP R2 instructions\n"));
19580 fprintf (stream
, _("\
19581 -mmt generate MT instructions\n\
19582 -mno-mt do not generate MT instructions\n"));
19583 fprintf (stream
, _("\
19584 -mmcu generate MCU instructions\n\
19585 -mno-mcu do not generate MCU instructions\n"));
19586 fprintf (stream
, _("\
19587 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19588 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19589 -mfix-vr4120 work around certain VR4120 errata\n\
19590 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19591 -mfix-24k insert a nop after ERET and DERET instructions\n\
19592 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19593 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19594 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19595 -msym32 assume all symbols have 32-bit values\n\
19596 -O0 remove unneeded NOPs, do not swap branches\n\
19597 -O remove unneeded NOPs and swap branches\n\
19598 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19599 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19600 fprintf (stream
, _("\
19601 -mhard-float allow floating-point instructions\n\
19602 -msoft-float do not allow floating-point instructions\n\
19603 -msingle-float only allow 32-bit floating-point operations\n\
19604 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19605 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19608 fprintf (stream
, _("\
19609 -KPIC, -call_shared generate SVR4 position independent code\n\
19610 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19611 -mvxworks-pic generate VxWorks position independent code\n\
19612 -non_shared do not generate code that can operate with DSOs\n\
19613 -xgot assume a 32 bit GOT\n\
19614 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19615 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19616 position dependent (non shared) code\n\
19617 -mabi=ABI create ABI conformant object file for:\n"));
19621 show (stream
, "32", &column
, &first
);
19622 show (stream
, "o64", &column
, &first
);
19623 show (stream
, "n32", &column
, &first
);
19624 show (stream
, "64", &column
, &first
);
19625 show (stream
, "eabi", &column
, &first
);
19627 fputc ('\n', stream
);
19629 fprintf (stream
, _("\
19630 -32 create o32 ABI object file (default)\n\
19631 -n32 create n32 ABI object file\n\
19632 -64 create 64 ABI object file\n"));
19638 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19640 if (HAVE_64BIT_SYMBOLS
)
19641 return dwarf2_format_64bit_irix
;
19643 return dwarf2_format_32bit
;
19648 mips_dwarf2_addr_size (void)
19650 if (HAVE_64BIT_OBJECTS
)
19656 /* Standard calling conventions leave the CFA at SP on entry. */
19658 mips_cfi_frame_initial_instructions (void)
19660 cfi_add_CFA_def_cfa_register (SP
);
19664 tc_mips_regname_to_dw2regnum (char *regname
)
19666 unsigned int regnum
= -1;
19669 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))