1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
115 mips_target_format ()
117 switch (OUTPUT_FLAVOR
)
119 case bfd_target_aout_flavour
:
120 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
121 case bfd_target_ecoff_flavour
:
122 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
123 case bfd_target_coff_flavour
:
125 case bfd_target_elf_flavour
:
127 /* This is traditional mips */
128 return (target_big_endian
129 ? (mips_64
? "elf64-tradbigmips" : "elf32-tradbigmips")
130 : (mips_64
? "elf64-tradlittlemips" : "elf32-tradlittlemips"));
132 return (target_big_endian
133 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
134 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
142 /* The name of the readonly data section. */
143 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
145 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
147 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
149 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
153 /* This is the set of options which may be modified by the .set
154 pseudo-op. We use a struct so that .set push and .set pop are more
157 struct mips_set_options
159 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
160 if it has not been initialized. Changed by `.set mipsN', and the
161 -mipsN command line option, and the default CPU. */
163 /* Whether we are assembling for the mips16 processor. 0 if we are
164 not, 1 if we are, and -1 if the value has not been initialized.
165 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
166 -nomips16 command line options, and the default CPU. */
168 /* Non-zero if we should not reorder instructions. Changed by `.set
169 reorder' and `.set noreorder'. */
171 /* Non-zero if we should not permit the $at ($1) register to be used
172 in instructions. Changed by `.set at' and `.set noat'. */
174 /* Non-zero if we should warn when a macro instruction expands into
175 more than one machine instruction. Changed by `.set nomacro' and
177 int warn_about_macros
;
178 /* Non-zero if we should not move instructions. Changed by `.set
179 move', `.set volatile', `.set nomove', and `.set novolatile'. */
181 /* Non-zero if we should not optimize branches by moving the target
182 of the branch into the delay slot. Actually, we don't perform
183 this optimization anyhow. Changed by `.set bopt' and `.set
186 /* Non-zero if we should not autoextend mips16 instructions.
187 Changed by `.set autoextend' and `.set noautoextend'. */
191 /* This is the struct we use to hold the current set of options. Note
192 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
193 -1 to indicate that they have not been initialized. */
195 static struct mips_set_options mips_opts
=
197 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
200 /* These variables are filled in with the masks of registers used.
201 The object format code reads them and puts them in the appropriate
203 unsigned long mips_gprmask
;
204 unsigned long mips_cprmask
[4];
206 /* MIPS ISA we are using for this output file. */
207 static int file_mips_isa
= ISA_UNKNOWN
;
209 /* The argument of the -mcpu= flag. Historical for code generation. */
210 static int mips_cpu
= CPU_UNKNOWN
;
212 /* The argument of the -march= flag. The architecture we are assembling. */
213 static int mips_arch
= CPU_UNKNOWN
;
215 /* The argument of the -mtune= flag. The architecture for which we
217 static int mips_tune
= CPU_UNKNOWN
;
219 /* The argument of the -mabi= flag. */
220 static char * mips_abi_string
= NULL
;
222 /* Whether we should mark the file EABI64 or EABI32. */
223 static int mips_eabi64
= 0;
225 /* If they asked for mips1 or mips2 and a cpu that is
226 mips3 or greater, then mark the object file 32BITMODE. */
227 static int mips_32bitmode
= 0;
229 /* True if -mgp32 was passed. */
230 static int mips_gp32
= 0;
232 /* True if -mfp32 was passed. */
233 static int mips_fp32
= 0;
235 /* True if the selected ABI is defined for 32-bit registers only. */
236 static int mips_32bit_abi
= 0;
238 /* Some ISA's have delay slots for instructions which read or write
239 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
240 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
241 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
242 delay slot in this ISA. The uses of this macro assume that any
243 ISA that has delay slots for one of these, has them for all. They
244 also assume that ISAs which don't have delays for these insns, don't
245 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
246 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
248 || (ISA) == ISA_MIPS2 \
249 || (ISA) == ISA_MIPS3 \
252 /* Return true if ISA supports 64 bit gp register instructions. */
253 #define ISA_HAS_64BIT_REGS(ISA) ( \
255 || (ISA) == ISA_MIPS4 \
256 || (ISA) == ISA_MIPS5 \
257 || (ISA) == ISA_MIPS64 \
260 #define HAVE_32BIT_GPRS \
263 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
265 #define HAVE_32BIT_FPRS \
268 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
270 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
271 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
273 #define HAVE_32BIT_ADDRESSES \
275 || bfd_arch_bits_per_address (stdoutput) == 32)
277 /* Whether the processor uses hardware interlocks to protect
278 reads from the HI and LO registers, and thus does not
279 require nops to be inserted. */
281 #define hilo_interlocks (mips_arch == CPU_R4010 \
284 /* Whether the processor uses hardware interlocks to protect reads
285 from the GPRs, and thus does not require nops to be inserted. */
286 #define gpr_interlocks \
287 (mips_opts.isa != ISA_MIPS1 \
288 || mips_arch == CPU_R3900)
290 /* As with other "interlocks" this is used by hardware that has FP
291 (co-processor) interlocks. */
292 /* Itbl support may require additional care here. */
293 #define cop_interlocks (mips_arch == CPU_R4300 \
296 /* Is this a mfhi or mflo instruction? */
297 #define MF_HILO_INSN(PINFO) \
298 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
300 /* MIPS PIC level. */
304 /* Do not generate PIC code. */
307 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
308 not sure what it is supposed to do. */
311 /* Generate PIC code as in the SVR4 MIPS ABI. */
314 /* Generate PIC code without using a global offset table: the data
315 segment has a maximum size of 64K, all data references are off
316 the $gp register, and all text references are PC relative. This
317 is used on some embedded systems. */
321 static enum mips_pic_level mips_pic
;
323 /* Warn about all NOPS that the assembler generates. */
324 static int warn_nops
= 0;
326 /* 1 if we should generate 32 bit offsets from the GP register in
327 SVR4_PIC mode. Currently has no meaning in other modes. */
328 static int mips_big_got
;
330 /* 1 if trap instructions should used for overflow rather than break
332 static int mips_trap
;
334 /* 1 if double width floating point constants should not be constructed
335 by a assembling two single width halves into two single width floating
336 point registers which just happen to alias the double width destination
337 register. On some architectures this aliasing can be disabled by a bit
338 in the status register, and the setting of this bit cannot be determined
339 automatically at assemble time. */
340 static int mips_disable_float_construction
;
342 /* Non-zero if any .set noreorder directives were used. */
344 static int mips_any_noreorder
;
346 /* Non-zero if nops should be inserted when the register referenced in
347 an mfhi/mflo instruction is read in the next two instructions. */
348 static int mips_7000_hilo_fix
;
350 /* The size of the small data section. */
351 static unsigned int g_switch_value
= 8;
352 /* Whether the -G option was used. */
353 static int g_switch_seen
= 0;
358 /* If we can determine in advance that GP optimization won't be
359 possible, we can skip the relaxation stuff that tries to produce
360 GP-relative references. This makes delay slot optimization work
363 This function can only provide a guess, but it seems to work for
364 gcc output. It needs to guess right for gcc, otherwise gcc
365 will put what it thinks is a GP-relative instruction in a branch
368 I don't know if a fix is needed for the SVR4_PIC mode. I've only
369 fixed it for the non-PIC mode. KR 95/04/07 */
370 static int nopic_need_relax
PARAMS ((symbolS
*, int));
372 /* handle of the OPCODE hash table */
373 static struct hash_control
*op_hash
= NULL
;
375 /* The opcode hash table we use for the mips16. */
376 static struct hash_control
*mips16_op_hash
= NULL
;
378 /* This array holds the chars that always start a comment. If the
379 pre-processor is disabled, these aren't very useful */
380 const char comment_chars
[] = "#";
382 /* This array holds the chars that only start a comment at the beginning of
383 a line. If the line seems to have the form '# 123 filename'
384 .line and .file directives will appear in the pre-processed output */
385 /* Note that input_file.c hand checks for '#' at the beginning of the
386 first line of the input file. This is because the compiler outputs
387 #NO_APP at the beginning of its output. */
388 /* Also note that C style comments are always supported. */
389 const char line_comment_chars
[] = "#";
391 /* This array holds machine specific line separator characters. */
392 const char line_separator_chars
[] = ";";
394 /* Chars that can be used to separate mant from exp in floating point nums */
395 const char EXP_CHARS
[] = "eE";
397 /* Chars that mean this number is a floating point constant */
400 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
402 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
403 changed in read.c . Ideally it shouldn't have to know about it at all,
404 but nothing is ideal around here.
407 static char *insn_error
;
409 static int auto_align
= 1;
411 /* When outputting SVR4 PIC code, the assembler needs to know the
412 offset in the stack frame from which to restore the $gp register.
413 This is set by the .cprestore pseudo-op, and saved in this
415 static offsetT mips_cprestore_offset
= -1;
417 /* This is the register which holds the stack frame, as set by the
418 .frame pseudo-op. This is needed to implement .cprestore. */
419 static int mips_frame_reg
= SP
;
421 /* To output NOP instructions correctly, we need to keep information
422 about the previous two instructions. */
424 /* Whether we are optimizing. The default value of 2 means to remove
425 unneeded NOPs and swap branch instructions when possible. A value
426 of 1 means to not swap branches. A value of 0 means to always
428 static int mips_optimize
= 2;
430 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
431 equivalent to seeing no -g option at all. */
432 static int mips_debug
= 0;
434 /* The previous instruction. */
435 static struct mips_cl_insn prev_insn
;
437 /* The instruction before prev_insn. */
438 static struct mips_cl_insn prev_prev_insn
;
440 /* If we don't want information for prev_insn or prev_prev_insn, we
441 point the insn_mo field at this dummy integer. */
442 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
444 /* Non-zero if prev_insn is valid. */
445 static int prev_insn_valid
;
447 /* The frag for the previous instruction. */
448 static struct frag
*prev_insn_frag
;
450 /* The offset into prev_insn_frag for the previous instruction. */
451 static long prev_insn_where
;
453 /* The reloc type for the previous instruction, if any. */
454 static bfd_reloc_code_real_type prev_insn_reloc_type
;
456 /* The reloc for the previous instruction, if any. */
457 static fixS
*prev_insn_fixp
;
459 /* Non-zero if the previous instruction was in a delay slot. */
460 static int prev_insn_is_delay_slot
;
462 /* Non-zero if the previous instruction was in a .set noreorder. */
463 static int prev_insn_unreordered
;
465 /* Non-zero if the previous instruction uses an extend opcode (if
467 static int prev_insn_extended
;
469 /* Non-zero if the previous previous instruction was in a .set
471 static int prev_prev_insn_unreordered
;
473 /* If this is set, it points to a frag holding nop instructions which
474 were inserted before the start of a noreorder section. If those
475 nops turn out to be unnecessary, the size of the frag can be
477 static fragS
*prev_nop_frag
;
479 /* The number of nop instructions we created in prev_nop_frag. */
480 static int prev_nop_frag_holds
;
482 /* The number of nop instructions that we know we need in
484 static int prev_nop_frag_required
;
486 /* The number of instructions we've seen since prev_nop_frag. */
487 static int prev_nop_frag_since
;
489 /* For ECOFF and ELF, relocations against symbols are done in two
490 parts, with a HI relocation and a LO relocation. Each relocation
491 has only 16 bits of space to store an addend. This means that in
492 order for the linker to handle carries correctly, it must be able
493 to locate both the HI and the LO relocation. This means that the
494 relocations must appear in order in the relocation table.
496 In order to implement this, we keep track of each unmatched HI
497 relocation. We then sort them so that they immediately precede the
498 corresponding LO relocation. */
503 struct mips_hi_fixup
*next
;
506 /* The section this fixup is in. */
510 /* The list of unmatched HI relocs. */
512 static struct mips_hi_fixup
*mips_hi_fixup_list
;
514 /* Map normal MIPS register numbers to mips16 register numbers. */
516 #define X ILLEGAL_REG
517 static const int mips32_to_16_reg_map
[] =
519 X
, X
, 2, 3, 4, 5, 6, 7,
520 X
, X
, X
, X
, X
, X
, X
, X
,
521 0, 1, X
, X
, X
, X
, X
, X
,
522 X
, X
, X
, X
, X
, X
, X
, X
526 /* Map mips16 register numbers to normal MIPS register numbers. */
528 static const unsigned int mips16_to_32_reg_map
[] =
530 16, 17, 2, 3, 4, 5, 6, 7
533 /* Since the MIPS does not have multiple forms of PC relative
534 instructions, we do not have to do relaxing as is done on other
535 platforms. However, we do have to handle GP relative addressing
536 correctly, which turns out to be a similar problem.
538 Every macro that refers to a symbol can occur in (at least) two
539 forms, one with GP relative addressing and one without. For
540 example, loading a global variable into a register generally uses
541 a macro instruction like this:
543 If i can be addressed off the GP register (this is true if it is in
544 the .sbss or .sdata section, or if it is known to be smaller than
545 the -G argument) this will generate the following instruction:
547 This instruction will use a GPREL reloc. If i can not be addressed
548 off the GP register, the following instruction sequence will be used:
551 In this case the first instruction will have a HI16 reloc, and the
552 second reloc will have a LO16 reloc. Both relocs will be against
555 The issue here is that we may not know whether i is GP addressable
556 until after we see the instruction that uses it. Therefore, we
557 want to be able to choose the final instruction sequence only at
558 the end of the assembly. This is similar to the way other
559 platforms choose the size of a PC relative instruction only at the
562 When generating position independent code we do not use GP
563 addressing in quite the same way, but the issue still arises as
564 external symbols and local symbols must be handled differently.
566 We handle these issues by actually generating both possible
567 instruction sequences. The longer one is put in a frag_var with
568 type rs_machine_dependent. We encode what to do with the frag in
569 the subtype field. We encode (1) the number of existing bytes to
570 replace, (2) the number of new bytes to use, (3) the offset from
571 the start of the existing bytes to the first reloc we must generate
572 (that is, the offset is applied from the start of the existing
573 bytes after they are replaced by the new bytes, if any), (4) the
574 offset from the start of the existing bytes to the second reloc,
575 (5) whether a third reloc is needed (the third reloc is always four
576 bytes after the second reloc), and (6) whether to warn if this
577 variant is used (this is sometimes needed if .set nomacro or .set
578 noat is in effect). All these numbers are reasonably small.
580 Generating two instruction sequences must be handled carefully to
581 ensure that delay slots are handled correctly. Fortunately, there
582 are a limited number of cases. When the second instruction
583 sequence is generated, append_insn is directed to maintain the
584 existing delay slot information, so it continues to apply to any
585 code after the second instruction sequence. This means that the
586 second instruction sequence must not impose any requirements not
587 required by the first instruction sequence.
589 These variant frags are then handled in functions called by the
590 machine independent code. md_estimate_size_before_relax returns
591 the final size of the frag. md_convert_frag sets up the final form
592 of the frag. tc_gen_reloc adjust the first reloc and adds a second
594 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
598 | (((reloc1) + 64) << 9) \
599 | (((reloc2) + 64) << 2) \
600 | ((reloc3) ? (1 << 1) : 0) \
602 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
603 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
604 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
605 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
606 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
607 #define RELAX_WARN(i) ((i) & 1)
609 /* For mips16 code, we use an entirely different form of relaxation.
610 mips16 supports two versions of most instructions which take
611 immediate values: a small one which takes some small value, and a
612 larger one which takes a 16 bit value. Since branches also follow
613 this pattern, relaxing these values is required.
615 We can assemble both mips16 and normal MIPS code in a single
616 object. Therefore, we need to support this type of relaxation at
617 the same time that we support the relaxation described above. We
618 use the high bit of the subtype field to distinguish these cases.
620 The information we store for this type of relaxation is the
621 argument code found in the opcode file for this relocation, whether
622 the user explicitly requested a small or extended form, and whether
623 the relocation is in a jump or jal delay slot. That tells us the
624 size of the value, and how it should be stored. We also store
625 whether the fragment is considered to be extended or not. We also
626 store whether this is known to be a branch to a different section,
627 whether we have tried to relax this frag yet, and whether we have
628 ever extended a PC relative fragment because of a shift count. */
629 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
632 | ((small) ? 0x100 : 0) \
633 | ((ext) ? 0x200 : 0) \
634 | ((dslot) ? 0x400 : 0) \
635 | ((jal_dslot) ? 0x800 : 0))
636 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
637 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
638 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
639 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
640 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
641 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
642 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
643 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
644 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
645 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
646 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
647 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
649 /* Prototypes for static functions. */
652 #define internalError() \
653 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
655 #define internalError() as_fatal (_("MIPS internal Error"));
658 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
660 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
661 unsigned int reg
, enum mips_regclass
class));
662 static int reg_needs_delay
PARAMS ((unsigned int));
663 static void mips16_mark_labels
PARAMS ((void));
664 static void append_insn
PARAMS ((char *place
,
665 struct mips_cl_insn
* ip
,
667 bfd_reloc_code_real_type r
,
669 static void mips_no_prev_insn
PARAMS ((int));
670 static void mips_emit_delays
PARAMS ((boolean
));
672 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
673 const char *name
, const char *fmt
,
676 static void macro_build ();
678 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
679 const char *, const char *,
681 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
682 expressionS
* ep
, int regnum
));
683 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
684 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
686 static void load_register
PARAMS ((int *, int, expressionS
*, int));
687 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
688 static void move_register
PARAMS ((int *, int, int));
689 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
690 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
691 #ifdef LOSING_COMPILER
692 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
694 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
695 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
696 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
697 boolean
, boolean
, unsigned long *,
698 boolean
*, unsigned short *));
699 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
700 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
701 static symbolS
*get_symbol
PARAMS ((void));
702 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
703 static void s_align
PARAMS ((int));
704 static void s_change_sec
PARAMS ((int));
705 static void s_cons
PARAMS ((int));
706 static void s_float_cons
PARAMS ((int));
707 static void s_mips_globl
PARAMS ((int));
708 static void s_option
PARAMS ((int));
709 static void s_mipsset
PARAMS ((int));
710 static void s_abicalls
PARAMS ((int));
711 static void s_cpload
PARAMS ((int));
712 static void s_cprestore
PARAMS ((int));
713 static void s_gpword
PARAMS ((int));
714 static void s_cpadd
PARAMS ((int));
715 static void s_insn
PARAMS ((int));
716 static void md_obj_begin
PARAMS ((void));
717 static void md_obj_end
PARAMS ((void));
718 static long get_number
PARAMS ((void));
719 static void s_mips_ent
PARAMS ((int));
720 static void s_mips_end
PARAMS ((int));
721 static void s_mips_frame
PARAMS ((int));
722 static void s_mips_mask
PARAMS ((int));
723 static void s_mips_stab
PARAMS ((int));
724 static void s_mips_weakext
PARAMS ((int));
725 static void s_file
PARAMS ((int));
726 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
727 static const char *mips_isa_to_str
PARAMS ((int));
728 static const char *mips_cpu_to_str
PARAMS ((int));
729 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
730 static void show
PARAMS ((FILE *, char *, int *, int *));
732 /* Return values of my_getSmallExpression() */
745 /* Table and functions used to map between CPU/ISA names, and
746 ISA levels, and CPU numbers. */
750 const char *name
; /* CPU or ISA name. */
751 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
752 int isa
; /* ISA level. */
753 int cpu
; /* CPU number (default CPU if ISA). */
756 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
757 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
758 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
762 The following pseudo-ops from the Kane and Heinrich MIPS book
763 should be defined here, but are currently unsupported: .alias,
764 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
766 The following pseudo-ops from the Kane and Heinrich MIPS book are
767 specific to the type of debugging information being generated, and
768 should be defined by the object format: .aent, .begin, .bend,
769 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
772 The following pseudo-ops from the Kane and Heinrich MIPS book are
773 not MIPS CPU specific, but are also not specific to the object file
774 format. This file is probably the best place to define them, but
775 they are not currently supported: .asm0, .endr, .lab, .repeat,
778 static const pseudo_typeS mips_pseudo_table
[] =
780 /* MIPS specific pseudo-ops. */
781 {"option", s_option
, 0},
782 {"set", s_mipsset
, 0},
783 {"rdata", s_change_sec
, 'r'},
784 {"sdata", s_change_sec
, 's'},
785 {"livereg", s_ignore
, 0},
786 {"abicalls", s_abicalls
, 0},
787 {"cpload", s_cpload
, 0},
788 {"cprestore", s_cprestore
, 0},
789 {"gpword", s_gpword
, 0},
790 {"cpadd", s_cpadd
, 0},
793 /* Relatively generic pseudo-ops that happen to be used on MIPS
795 {"asciiz", stringer
, 1},
796 {"bss", s_change_sec
, 'b'},
799 {"dword", s_cons
, 3},
800 {"weakext", s_mips_weakext
, 0},
802 /* These pseudo-ops are defined in read.c, but must be overridden
803 here for one reason or another. */
804 {"align", s_align
, 0},
806 {"data", s_change_sec
, 'd'},
807 {"double", s_float_cons
, 'd'},
808 {"float", s_float_cons
, 'f'},
809 {"globl", s_mips_globl
, 0},
810 {"global", s_mips_globl
, 0},
811 {"hword", s_cons
, 1},
816 {"short", s_cons
, 1},
817 {"single", s_float_cons
, 'f'},
818 {"stabn", s_mips_stab
, 'n'},
819 {"text", s_change_sec
, 't'},
822 #ifdef MIPS_STABS_ELF
823 { "extern", ecoff_directive_extern
, 0},
829 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
831 /* These pseudo-ops should be defined by the object file format.
832 However, a.out doesn't support them, so we have versions here. */
833 {"aent", s_mips_ent
, 1},
834 {"bgnb", s_ignore
, 0},
835 {"end", s_mips_end
, 0},
836 {"endb", s_ignore
, 0},
837 {"ent", s_mips_ent
, 0},
839 {"fmask", s_mips_mask
, 'F'},
840 {"frame", s_mips_frame
, 0},
841 {"loc", s_ignore
, 0},
842 {"mask", s_mips_mask
, 'R'},
843 {"verstamp", s_ignore
, 0},
847 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
852 pop_insert (mips_pseudo_table
);
853 if (! ECOFF_DEBUGGING
)
854 pop_insert (mips_nonecoff_pseudo_table
);
857 /* Symbols labelling the current insn. */
859 struct insn_label_list
861 struct insn_label_list
*next
;
865 static struct insn_label_list
*insn_labels
;
866 static struct insn_label_list
*free_insn_labels
;
868 static void mips_clear_insn_labels
PARAMS ((void));
871 mips_clear_insn_labels ()
873 register struct insn_label_list
**pl
;
875 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
881 static char *expr_end
;
883 /* Expressions which appear in instructions. These are set by
886 static expressionS imm_expr
;
887 static expressionS offset_expr
;
889 /* Relocs associated with imm_expr and offset_expr. */
891 static bfd_reloc_code_real_type imm_reloc
;
892 static bfd_reloc_code_real_type offset_reloc
;
894 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
896 static boolean imm_unmatched_hi
;
898 /* These are set by mips16_ip if an explicit extension is used. */
900 static boolean mips16_small
, mips16_ext
;
902 #ifdef MIPS_STABS_ELF
903 /* The pdr segment for per procedure frame/regmask info */
909 mips_isa_to_str (isa
)
912 const struct mips_cpu_info
*ci
;
915 ci
= mips_cpu_info_from_isa (isa
);
919 sprintf (s
, "ISA#%d", isa
);
924 mips_cpu_to_str (cpu
)
927 const struct mips_cpu_info
*ci
;
930 ci
= mips_cpu_info_from_cpu (cpu
);
934 sprintf (s
, "CPU#%d", cpu
);
938 /* This function is called once, at assembler startup time. It should
939 set up all the tables, etc. that the MD part of the assembler will need. */
944 register const char *retval
= NULL
;
949 int mips_isa_from_cpu
;
950 int target_cpu_had_mips16
= 0;
951 const struct mips_cpu_info
*ci
;
953 /* GP relative stuff not working for PE */
954 if (strncmp (TARGET_OS
, "pe", 2) == 0
955 && g_switch_value
!= 0)
958 as_bad (_("-G not supported in this configuration."));
963 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
965 a
= xmalloc (sizeof TARGET_CPU
);
966 strcpy (a
, TARGET_CPU
);
967 a
[(sizeof TARGET_CPU
) - 3] = '\0';
971 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
973 target_cpu_had_mips16
= 1;
974 cpu
+= sizeof "mips16" - 1;
977 if (mips_opts
.mips16
< 0)
978 mips_opts
.mips16
= target_cpu_had_mips16
;
980 /* Backward compatibility for historic -mcpu= option. Check for
981 incompatible options, warn if -mcpu is used. */
982 if (mips_cpu
!= CPU_UNKNOWN
983 && mips_arch
!= CPU_UNKNOWN
984 && mips_cpu
!= mips_arch
)
986 as_fatal (_("The -mcpu option can't be used together with -march. "
987 "Use -mtune instead of -mcpu."));
990 if (mips_cpu
!= CPU_UNKNOWN
991 && mips_tune
!= CPU_UNKNOWN
992 && mips_cpu
!= mips_tune
)
994 as_fatal (_("The -mcpu option can't be used together with -mtune. "
995 "Use -march instead of -mcpu."));
998 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1000 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1001 assert (ci
!= NULL
);
1002 mips_arch
= ci
->cpu
;
1003 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1004 "-mtune instead."));
1007 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1008 specified on the command line, or some other value if one was.
1009 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1010 the command line, or will be set otherwise if one was. */
1011 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1013 /* We have to check if the isa is the default isa of arch. Otherwise
1014 we'll get invalid object file headers. */
1015 ci
= mips_cpu_info_from_cpu (mips_arch
);
1016 assert (ci
!= NULL
);
1017 if (mips_opts
.isa
!= ci
->isa
)
1019 /* This really should be an error instead of a warning, but old
1020 compilers only have -mcpu which sets both arch and tune. For
1021 now, we discard arch and preserve tune. */
1022 as_warn (_("The -march option is incompatible to -mipsN and "
1023 "therefore ignored."));
1024 if (mips_tune
== CPU_UNKNOWN
)
1025 mips_tune
= mips_arch
;
1026 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1027 assert (ci
!= NULL
);
1028 mips_arch
= ci
->cpu
;
1031 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1033 /* We have ARCH, we need ISA. */
1034 ci
= mips_cpu_info_from_cpu (mips_arch
);
1035 assert (ci
!= NULL
);
1036 mips_opts
.isa
= ci
->isa
;
1038 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1040 /* We have ISA, we need default ARCH. */
1041 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1042 assert (ci
!= NULL
);
1043 mips_arch
= ci
->cpu
;
1047 /* We need to set both ISA and ARCH from target cpu. */
1048 ci
= mips_cpu_info_from_name (cpu
);
1050 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1051 assert (ci
!= NULL
);
1052 mips_opts
.isa
= ci
->isa
;
1053 mips_arch
= ci
->cpu
;
1056 if (mips_tune
== CPU_UNKNOWN
)
1057 mips_tune
= mips_arch
;
1059 ci
= mips_cpu_info_from_cpu (mips_arch
);
1060 assert (ci
!= NULL
);
1061 mips_isa_from_cpu
= ci
->isa
;
1063 /* End of TARGET_CPU processing, get rid of malloced memory
1072 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1073 as_bad (_("trap exception not supported at ISA 1"));
1075 /* Set the EABI kind based on the ISA before the user gets
1076 to change the ISA with directives. This isn't really
1077 the best, but then neither is basing the abi on the isa. */
1078 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1080 && 0 == strcmp (mips_abi_string
, "eabi"))
1083 /* If they asked for mips1 or mips2 and a cpu that is
1084 mips3 or greater, then mark the object file 32BITMODE. */
1085 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1086 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1087 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1090 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1091 as_warn (_("Could not set architecture and machine"));
1093 file_mips_isa
= mips_opts
.isa
;
1095 op_hash
= hash_new ();
1097 for (i
= 0; i
< NUMOPCODES
;)
1099 const char *name
= mips_opcodes
[i
].name
;
1101 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1104 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1105 mips_opcodes
[i
].name
, retval
);
1106 /* Probably a memory allocation problem? Give up now. */
1107 as_fatal (_("Broken assembler. No assembly attempted."));
1111 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1113 if (!validate_mips_insn (&mips_opcodes
[i
]))
1118 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1121 mips16_op_hash
= hash_new ();
1124 while (i
< bfd_mips16_num_opcodes
)
1126 const char *name
= mips16_opcodes
[i
].name
;
1128 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1130 as_fatal (_("internal: can't hash `%s': %s"),
1131 mips16_opcodes
[i
].name
, retval
);
1134 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1135 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1136 != mips16_opcodes
[i
].match
))
1138 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1139 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1144 while (i
< bfd_mips16_num_opcodes
1145 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1149 as_fatal (_("Broken assembler. No assembly attempted."));
1151 /* We add all the general register names to the symbol table. This
1152 helps us detect invalid uses of them. */
1153 for (i
= 0; i
< 32; i
++)
1157 sprintf (buf
, "$%d", i
);
1158 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1159 &zero_address_frag
));
1161 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1162 &zero_address_frag
));
1163 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1164 &zero_address_frag
));
1165 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1166 &zero_address_frag
));
1167 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1168 &zero_address_frag
));
1169 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1170 &zero_address_frag
));
1171 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1172 &zero_address_frag
));
1173 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1174 &zero_address_frag
));
1176 mips_no_prev_insn (false);
1179 mips_cprmask
[0] = 0;
1180 mips_cprmask
[1] = 0;
1181 mips_cprmask
[2] = 0;
1182 mips_cprmask
[3] = 0;
1184 /* set the default alignment for the text section (2**2) */
1185 record_alignment (text_section
, 2);
1187 if (USE_GLOBAL_POINTER_OPT
)
1188 bfd_set_gp_size (stdoutput
, g_switch_value
);
1190 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1192 /* On a native system, sections must be aligned to 16 byte
1193 boundaries. When configured for an embedded ELF target, we
1195 if (strcmp (TARGET_OS
, "elf") != 0)
1197 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1198 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1199 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1202 /* Create a .reginfo section for register masks and a .mdebug
1203 section for debugging information. */
1211 subseg
= now_subseg
;
1213 /* The ABI says this section should be loaded so that the
1214 running program can access it. However, we don't load it
1215 if we are configured for an embedded target */
1216 flags
= SEC_READONLY
| SEC_DATA
;
1217 if (strcmp (TARGET_OS
, "elf") != 0)
1218 flags
|= SEC_ALLOC
| SEC_LOAD
;
1222 sec
= subseg_new (".reginfo", (subsegT
) 0);
1224 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1225 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1228 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1233 /* The 64-bit ABI uses a .MIPS.options section rather than
1234 .reginfo section. */
1235 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1236 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1237 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1240 /* Set up the option header. */
1242 Elf_Internal_Options opthdr
;
1245 opthdr
.kind
= ODK_REGINFO
;
1246 opthdr
.size
= (sizeof (Elf_External_Options
)
1247 + sizeof (Elf64_External_RegInfo
));
1250 f
= frag_more (sizeof (Elf_External_Options
));
1251 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1252 (Elf_External_Options
*) f
);
1254 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1259 if (ECOFF_DEBUGGING
)
1261 sec
= subseg_new (".mdebug", (subsegT
) 0);
1262 (void) bfd_set_section_flags (stdoutput
, sec
,
1263 SEC_HAS_CONTENTS
| SEC_READONLY
);
1264 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1267 #ifdef MIPS_STABS_ELF
1268 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1269 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1270 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1271 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1274 subseg_set (seg
, subseg
);
1278 if (! ECOFF_DEBUGGING
)
1285 if (! ECOFF_DEBUGGING
)
1293 struct mips_cl_insn insn
;
1295 imm_expr
.X_op
= O_absent
;
1296 imm_reloc
= BFD_RELOC_UNUSED
;
1297 imm_unmatched_hi
= false;
1298 offset_expr
.X_op
= O_absent
;
1299 offset_reloc
= BFD_RELOC_UNUSED
;
1301 if (mips_opts
.mips16
)
1302 mips16_ip (str
, &insn
);
1305 mips_ip (str
, &insn
);
1306 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1307 str
, insn
.insn_opcode
));
1312 as_bad ("%s `%s'", insn_error
, str
);
1316 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1318 if (mips_opts
.mips16
)
1319 mips16_macro (&insn
);
1325 if (imm_expr
.X_op
!= O_absent
)
1326 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1328 else if (offset_expr
.X_op
!= O_absent
)
1329 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1331 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1335 /* See whether instruction IP reads register REG. CLASS is the type
1339 insn_uses_reg (ip
, reg
, class)
1340 struct mips_cl_insn
*ip
;
1342 enum mips_regclass
class;
1344 if (class == MIPS16_REG
)
1346 assert (mips_opts
.mips16
);
1347 reg
= mips16_to_32_reg_map
[reg
];
1348 class = MIPS_GR_REG
;
1351 /* Don't report on general register 0, since it never changes. */
1352 if (class == MIPS_GR_REG
&& reg
== 0)
1355 if (class == MIPS_FP_REG
)
1357 assert (! mips_opts
.mips16
);
1358 /* If we are called with either $f0 or $f1, we must check $f0.
1359 This is not optimal, because it will introduce an unnecessary
1360 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1361 need to distinguish reading both $f0 and $f1 or just one of
1362 them. Note that we don't have to check the other way,
1363 because there is no instruction that sets both $f0 and $f1
1364 and requires a delay. */
1365 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1366 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1367 == (reg
&~ (unsigned) 1)))
1369 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1370 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1371 == (reg
&~ (unsigned) 1)))
1374 else if (! mips_opts
.mips16
)
1376 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1377 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1379 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1380 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1385 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1386 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1387 & MIPS16OP_MASK_RX
)]
1390 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1391 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1392 & MIPS16OP_MASK_RY
)]
1395 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1396 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1397 & MIPS16OP_MASK_MOVE32Z
)]
1400 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1402 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1404 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1406 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1407 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1408 & MIPS16OP_MASK_REGR32
) == reg
)
1415 /* This function returns true if modifying a register requires a
1419 reg_needs_delay (reg
)
1422 unsigned long prev_pinfo
;
1424 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1425 if (! mips_opts
.noreorder
1426 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1427 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1428 || (! gpr_interlocks
1429 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1431 /* A load from a coprocessor or from memory. All load
1432 delays delay the use of general register rt for one
1433 instruction on the r3000. The r6000 and r4000 use
1435 /* Itbl support may require additional care here. */
1436 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1437 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1444 /* Mark instruction labels in mips16 mode. This permits the linker to
1445 handle them specially, such as generating jalx instructions when
1446 needed. We also make them odd for the duration of the assembly, in
1447 order to generate the right sort of code. We will make them even
1448 in the adjust_symtab routine, while leaving them marked. This is
1449 convenient for the debugger and the disassembler. The linker knows
1450 to make them odd again. */
1453 mips16_mark_labels ()
1455 if (mips_opts
.mips16
)
1457 struct insn_label_list
*l
;
1460 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1463 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1464 S_SET_OTHER (l
->label
, STO_MIPS16
);
1466 val
= S_GET_VALUE (l
->label
);
1468 S_SET_VALUE (l
->label
, val
+ 1);
1473 /* Output an instruction. PLACE is where to put the instruction; if
1474 it is NULL, this uses frag_more to get room. IP is the instruction
1475 information. ADDRESS_EXPR is an operand of the instruction to be
1476 used with RELOC_TYPE. */
1479 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1481 struct mips_cl_insn
*ip
;
1482 expressionS
*address_expr
;
1483 bfd_reloc_code_real_type reloc_type
;
1484 boolean unmatched_hi
;
1486 register unsigned long prev_pinfo
, pinfo
;
1491 /* Mark instruction labels in mips16 mode. */
1492 if (mips_opts
.mips16
)
1493 mips16_mark_labels ();
1495 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1496 pinfo
= ip
->insn_mo
->pinfo
;
1498 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1502 /* If the previous insn required any delay slots, see if we need
1503 to insert a NOP or two. There are eight kinds of possible
1504 hazards, of which an instruction can have at most one type.
1505 (1) a load from memory delay
1506 (2) a load from a coprocessor delay
1507 (3) an unconditional branch delay
1508 (4) a conditional branch delay
1509 (5) a move to coprocessor register delay
1510 (6) a load coprocessor register from memory delay
1511 (7) a coprocessor condition code delay
1512 (8) a HI/LO special register delay
1514 There are a lot of optimizations we could do that we don't.
1515 In particular, we do not, in general, reorder instructions.
1516 If you use gcc with optimization, it will reorder
1517 instructions and generally do much more optimization then we
1518 do here; repeating all that work in the assembler would only
1519 benefit hand written assembly code, and does not seem worth
1522 /* This is how a NOP is emitted. */
1523 #define emit_nop() \
1525 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1526 : md_number_to_chars (frag_more (4), 0, 4))
1528 /* The previous insn might require a delay slot, depending upon
1529 the contents of the current insn. */
1530 if (! mips_opts
.mips16
1531 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1532 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1533 && ! cop_interlocks
)
1534 || (! gpr_interlocks
1535 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1537 /* A load from a coprocessor or from memory. All load
1538 delays delay the use of general register rt for one
1539 instruction on the r3000. The r6000 and r4000 use
1541 /* Itbl support may require additional care here. */
1542 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1543 if (mips_optimize
== 0
1544 || insn_uses_reg (ip
,
1545 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1550 else if (! mips_opts
.mips16
1551 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1552 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1553 && ! cop_interlocks
)
1554 || (mips_opts
.isa
== ISA_MIPS1
1555 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1557 /* A generic coprocessor delay. The previous instruction
1558 modified a coprocessor general or control register. If
1559 it modified a control register, we need to avoid any
1560 coprocessor instruction (this is probably not always
1561 required, but it sometimes is). If it modified a general
1562 register, we avoid using that register.
1564 On the r6000 and r4000 loading a coprocessor register
1565 from memory is interlocked, and does not require a delay.
1567 This case is not handled very well. There is no special
1568 knowledge of CP0 handling, and the coprocessors other
1569 than the floating point unit are not distinguished at
1571 /* Itbl support may require additional care here. FIXME!
1572 Need to modify this to include knowledge about
1573 user specified delays! */
1574 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1576 if (mips_optimize
== 0
1577 || insn_uses_reg (ip
,
1578 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1583 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1585 if (mips_optimize
== 0
1586 || insn_uses_reg (ip
,
1587 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1594 /* We don't know exactly what the previous instruction
1595 does. If the current instruction uses a coprocessor
1596 register, we must insert a NOP. If previous
1597 instruction may set the condition codes, and the
1598 current instruction uses them, we must insert two
1600 /* Itbl support may require additional care here. */
1601 if (mips_optimize
== 0
1602 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1603 && (pinfo
& INSN_READ_COND_CODE
)))
1605 else if (pinfo
& INSN_COP
)
1609 else if (! mips_opts
.mips16
1610 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1611 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1612 && ! cop_interlocks
)
1614 /* The previous instruction sets the coprocessor condition
1615 codes, but does not require a general coprocessor delay
1616 (this means it is a floating point comparison
1617 instruction). If this instruction uses the condition
1618 codes, we need to insert a single NOP. */
1619 /* Itbl support may require additional care here. */
1620 if (mips_optimize
== 0
1621 || (pinfo
& INSN_READ_COND_CODE
))
1625 /* If we're fixing up mfhi/mflo for the r7000 and the
1626 previous insn was an mfhi/mflo and the current insn
1627 reads the register that the mfhi/mflo wrote to, then
1630 else if (mips_7000_hilo_fix
1631 && MF_HILO_INSN (prev_pinfo
)
1632 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1639 /* If we're fixing up mfhi/mflo for the r7000 and the
1640 2nd previous insn was an mfhi/mflo and the current insn
1641 reads the register that the mfhi/mflo wrote to, then
1644 else if (mips_7000_hilo_fix
1645 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1646 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1654 else if (prev_pinfo
& INSN_READ_LO
)
1656 /* The previous instruction reads the LO register; if the
1657 current instruction writes to the LO register, we must
1658 insert two NOPS. Some newer processors have interlocks.
1659 Also the tx39's multiply instructions can be exectuted
1660 immediatly after a read from HI/LO (without the delay),
1661 though the tx39's divide insns still do require the
1663 if (! (hilo_interlocks
1664 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1665 && (mips_optimize
== 0
1666 || (pinfo
& INSN_WRITE_LO
)))
1668 /* Most mips16 branch insns don't have a delay slot.
1669 If a read from LO is immediately followed by a branch
1670 to a write to LO we have a read followed by a write
1671 less than 2 insns away. We assume the target of
1672 a branch might be a write to LO, and insert a nop
1673 between a read and an immediately following branch. */
1674 else if (mips_opts
.mips16
1675 && (mips_optimize
== 0
1676 || (pinfo
& MIPS16_INSN_BRANCH
)))
1679 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1681 /* The previous instruction reads the HI register; if the
1682 current instruction writes to the HI register, we must
1683 insert a NOP. Some newer processors have interlocks.
1684 Also the note tx39's multiply above. */
1685 if (! (hilo_interlocks
1686 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1687 && (mips_optimize
== 0
1688 || (pinfo
& INSN_WRITE_HI
)))
1690 /* Most mips16 branch insns don't have a delay slot.
1691 If a read from HI is immediately followed by a branch
1692 to a write to HI we have a read followed by a write
1693 less than 2 insns away. We assume the target of
1694 a branch might be a write to HI, and insert a nop
1695 between a read and an immediately following branch. */
1696 else if (mips_opts
.mips16
1697 && (mips_optimize
== 0
1698 || (pinfo
& MIPS16_INSN_BRANCH
)))
1702 /* If the previous instruction was in a noreorder section, then
1703 we don't want to insert the nop after all. */
1704 /* Itbl support may require additional care here. */
1705 if (prev_insn_unreordered
)
1708 /* There are two cases which require two intervening
1709 instructions: 1) setting the condition codes using a move to
1710 coprocessor instruction which requires a general coprocessor
1711 delay and then reading the condition codes 2) reading the HI
1712 or LO register and then writing to it (except on processors
1713 which have interlocks). If we are not already emitting a NOP
1714 instruction, we must check for these cases compared to the
1715 instruction previous to the previous instruction. */
1716 if ((! mips_opts
.mips16
1717 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1718 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1719 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1720 && (pinfo
& INSN_READ_COND_CODE
)
1721 && ! cop_interlocks
)
1722 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1723 && (pinfo
& INSN_WRITE_LO
)
1724 && ! (hilo_interlocks
1725 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1726 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1727 && (pinfo
& INSN_WRITE_HI
)
1728 && ! (hilo_interlocks
1729 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1734 if (prev_prev_insn_unreordered
)
1737 if (prev_prev_nop
&& nops
== 0)
1740 /* If we are being given a nop instruction, don't bother with
1741 one of the nops we would otherwise output. This will only
1742 happen when a nop instruction is used with mips_optimize set
1745 && ! mips_opts
.noreorder
1746 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1749 /* Now emit the right number of NOP instructions. */
1750 if (nops
> 0 && ! mips_opts
.noreorder
)
1753 unsigned long old_frag_offset
;
1755 struct insn_label_list
*l
;
1757 old_frag
= frag_now
;
1758 old_frag_offset
= frag_now_fix ();
1760 for (i
= 0; i
< nops
; i
++)
1765 listing_prev_line ();
1766 /* We may be at the start of a variant frag. In case we
1767 are, make sure there is enough space for the frag
1768 after the frags created by listing_prev_line. The
1769 argument to frag_grow here must be at least as large
1770 as the argument to all other calls to frag_grow in
1771 this file. We don't have to worry about being in the
1772 middle of a variant frag, because the variants insert
1773 all needed nop instructions themselves. */
1777 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1781 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1782 symbol_set_frag (l
->label
, frag_now
);
1783 val
= (valueT
) frag_now_fix ();
1784 /* mips16 text labels are stored as odd. */
1785 if (mips_opts
.mips16
)
1787 S_SET_VALUE (l
->label
, val
);
1790 #ifndef NO_ECOFF_DEBUGGING
1791 if (ECOFF_DEBUGGING
)
1792 ecoff_fix_loc (old_frag
, old_frag_offset
);
1795 else if (prev_nop_frag
!= NULL
)
1797 /* We have a frag holding nops we may be able to remove. If
1798 we don't need any nops, we can decrease the size of
1799 prev_nop_frag by the size of one instruction. If we do
1800 need some nops, we count them in prev_nops_required. */
1801 if (prev_nop_frag_since
== 0)
1805 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1806 --prev_nop_frag_holds
;
1809 prev_nop_frag_required
+= nops
;
1813 if (prev_prev_nop
== 0)
1815 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1816 --prev_nop_frag_holds
;
1819 ++prev_nop_frag_required
;
1822 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1823 prev_nop_frag
= NULL
;
1825 ++prev_nop_frag_since
;
1827 /* Sanity check: by the time we reach the second instruction
1828 after prev_nop_frag, we should have used up all the nops
1829 one way or another. */
1830 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1834 if (reloc_type
> BFD_RELOC_UNUSED
)
1836 /* We need to set up a variant frag. */
1837 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1838 f
= frag_var (rs_machine_dependent
, 4, 0,
1839 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1840 mips16_small
, mips16_ext
,
1842 & INSN_UNCOND_BRANCH_DELAY
),
1843 (prev_insn_reloc_type
1844 == BFD_RELOC_MIPS16_JMP
)),
1845 make_expr_symbol (address_expr
), (offsetT
) 0,
1848 else if (place
!= NULL
)
1850 else if (mips_opts
.mips16
1852 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1854 /* Make sure there is enough room to swap this instruction with
1855 a following jump instruction. */
1861 if (mips_opts
.mips16
1862 && mips_opts
.noreorder
1863 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1864 as_warn (_("extended instruction in delay slot"));
1870 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1872 if (address_expr
->X_op
== O_constant
)
1877 ip
->insn_opcode
|= address_expr
->X_add_number
;
1880 case BFD_RELOC_LO16
:
1881 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1884 case BFD_RELOC_MIPS_JMP
:
1885 if ((address_expr
->X_add_number
& 3) != 0)
1886 as_bad (_("jump to misaligned address (0x%lx)"),
1887 (unsigned long) address_expr
->X_add_number
);
1888 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1891 case BFD_RELOC_MIPS16_JMP
:
1892 if ((address_expr
->X_add_number
& 3) != 0)
1893 as_bad (_("jump to misaligned address (0x%lx)"),
1894 (unsigned long) address_expr
->X_add_number
);
1896 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1897 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1898 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1901 case BFD_RELOC_16_PCREL_S2
:
1911 /* Don't generate a reloc if we are writing into a variant
1915 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1917 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1921 struct mips_hi_fixup
*hi_fixup
;
1923 assert (reloc_type
== BFD_RELOC_HI16_S
);
1924 hi_fixup
= ((struct mips_hi_fixup
*)
1925 xmalloc (sizeof (struct mips_hi_fixup
)));
1926 hi_fixup
->fixp
= fixp
;
1927 hi_fixup
->seg
= now_seg
;
1928 hi_fixup
->next
= mips_hi_fixup_list
;
1929 mips_hi_fixup_list
= hi_fixup
;
1935 if (! mips_opts
.mips16
)
1936 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1937 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1939 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1940 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1946 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1949 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1952 /* Update the register mask information. */
1953 if (! mips_opts
.mips16
)
1955 if (pinfo
& INSN_WRITE_GPR_D
)
1956 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1957 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1958 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1959 if (pinfo
& INSN_READ_GPR_S
)
1960 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1961 if (pinfo
& INSN_WRITE_GPR_31
)
1962 mips_gprmask
|= 1 << 31;
1963 if (pinfo
& INSN_WRITE_FPR_D
)
1964 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1965 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1966 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1967 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1968 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1969 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1970 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1971 if (pinfo
& INSN_COP
)
1973 /* We don't keep enough information to sort these cases out.
1974 The itbl support does keep this information however, although
1975 we currently don't support itbl fprmats as part of the cop
1976 instruction. May want to add this support in the future. */
1978 /* Never set the bit for $0, which is always zero. */
1979 mips_gprmask
&= ~1 << 0;
1983 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1984 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1985 & MIPS16OP_MASK_RX
);
1986 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1987 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1988 & MIPS16OP_MASK_RY
);
1989 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1990 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1991 & MIPS16OP_MASK_RZ
);
1992 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1993 mips_gprmask
|= 1 << TREG
;
1994 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1995 mips_gprmask
|= 1 << SP
;
1996 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1997 mips_gprmask
|= 1 << RA
;
1998 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1999 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2000 if (pinfo
& MIPS16_INSN_READ_Z
)
2001 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2002 & MIPS16OP_MASK_MOVE32Z
);
2003 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2004 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2005 & MIPS16OP_MASK_REGR32
);
2008 if (place
== NULL
&& ! mips_opts
.noreorder
)
2010 /* Filling the branch delay slot is more complex. We try to
2011 switch the branch with the previous instruction, which we can
2012 do if the previous instruction does not set up a condition
2013 that the branch tests and if the branch is not itself the
2014 target of any branch. */
2015 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2016 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2018 if (mips_optimize
< 2
2019 /* If we have seen .set volatile or .set nomove, don't
2021 || mips_opts
.nomove
!= 0
2022 /* If we had to emit any NOP instructions, then we
2023 already know we can not swap. */
2025 /* If we don't even know the previous insn, we can not
2027 || ! prev_insn_valid
2028 /* If the previous insn is already in a branch delay
2029 slot, then we can not swap. */
2030 || prev_insn_is_delay_slot
2031 /* If the previous previous insn was in a .set
2032 noreorder, we can't swap. Actually, the MIPS
2033 assembler will swap in this situation. However, gcc
2034 configured -with-gnu-as will generate code like
2040 in which we can not swap the bne and INSN. If gcc is
2041 not configured -with-gnu-as, it does not output the
2042 .set pseudo-ops. We don't have to check
2043 prev_insn_unreordered, because prev_insn_valid will
2044 be 0 in that case. We don't want to use
2045 prev_prev_insn_valid, because we do want to be able
2046 to swap at the start of a function. */
2047 || prev_prev_insn_unreordered
2048 /* If the branch is itself the target of a branch, we
2049 can not swap. We cheat on this; all we check for is
2050 whether there is a label on this instruction. If
2051 there are any branches to anything other than a
2052 label, users must use .set noreorder. */
2053 || insn_labels
!= NULL
2054 /* If the previous instruction is in a variant frag, we
2055 can not do the swap. This does not apply to the
2056 mips16, which uses variant frags for different
2058 || (! mips_opts
.mips16
2059 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2060 /* If the branch reads the condition codes, we don't
2061 even try to swap, because in the sequence
2066 we can not swap, and I don't feel like handling that
2068 || (! mips_opts
.mips16
2069 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2070 && (pinfo
& INSN_READ_COND_CODE
))
2071 /* We can not swap with an instruction that requires a
2072 delay slot, becase the target of the branch might
2073 interfere with that instruction. */
2074 || (! mips_opts
.mips16
2075 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2077 /* Itbl support may require additional care here. */
2078 & (INSN_LOAD_COPROC_DELAY
2079 | INSN_COPROC_MOVE_DELAY
2080 | INSN_WRITE_COND_CODE
)))
2081 || (! (hilo_interlocks
2082 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2086 || (! mips_opts
.mips16
2088 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2089 || (! mips_opts
.mips16
2090 && mips_opts
.isa
== ISA_MIPS1
2091 /* Itbl support may require additional care here. */
2092 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2093 /* We can not swap with a branch instruction. */
2095 & (INSN_UNCOND_BRANCH_DELAY
2096 | INSN_COND_BRANCH_DELAY
2097 | INSN_COND_BRANCH_LIKELY
))
2098 /* We do not swap with a trap instruction, since it
2099 complicates trap handlers to have the trap
2100 instruction be in a delay slot. */
2101 || (prev_pinfo
& INSN_TRAP
)
2102 /* If the branch reads a register that the previous
2103 instruction sets, we can not swap. */
2104 || (! mips_opts
.mips16
2105 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2106 && insn_uses_reg (ip
,
2107 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2110 || (! mips_opts
.mips16
2111 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2112 && insn_uses_reg (ip
,
2113 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2116 || (mips_opts
.mips16
2117 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2118 && insn_uses_reg (ip
,
2119 ((prev_insn
.insn_opcode
2121 & MIPS16OP_MASK_RX
),
2123 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2124 && insn_uses_reg (ip
,
2125 ((prev_insn
.insn_opcode
2127 & MIPS16OP_MASK_RY
),
2129 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2130 && insn_uses_reg (ip
,
2131 ((prev_insn
.insn_opcode
2133 & MIPS16OP_MASK_RZ
),
2135 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2136 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2137 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2138 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2139 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2140 && insn_uses_reg (ip
,
2141 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2144 /* If the branch writes a register that the previous
2145 instruction sets, we can not swap (we know that
2146 branches write only to RD or to $31). */
2147 || (! mips_opts
.mips16
2148 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2149 && (((pinfo
& INSN_WRITE_GPR_D
)
2150 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2151 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2152 || ((pinfo
& INSN_WRITE_GPR_31
)
2153 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2156 || (! mips_opts
.mips16
2157 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2158 && (((pinfo
& INSN_WRITE_GPR_D
)
2159 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2160 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2161 || ((pinfo
& INSN_WRITE_GPR_31
)
2162 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2165 || (mips_opts
.mips16
2166 && (pinfo
& MIPS16_INSN_WRITE_31
)
2167 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2168 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2169 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2171 /* If the branch writes a register that the previous
2172 instruction reads, we can not swap (we know that
2173 branches only write to RD or to $31). */
2174 || (! mips_opts
.mips16
2175 && (pinfo
& INSN_WRITE_GPR_D
)
2176 && insn_uses_reg (&prev_insn
,
2177 ((ip
->insn_opcode
>> OP_SH_RD
)
2180 || (! mips_opts
.mips16
2181 && (pinfo
& INSN_WRITE_GPR_31
)
2182 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2183 || (mips_opts
.mips16
2184 && (pinfo
& MIPS16_INSN_WRITE_31
)
2185 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2186 /* If we are generating embedded PIC code, the branch
2187 might be expanded into a sequence which uses $at, so
2188 we can't swap with an instruction which reads it. */
2189 || (mips_pic
== EMBEDDED_PIC
2190 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2191 /* If the previous previous instruction has a load
2192 delay, and sets a register that the branch reads, we
2194 || (! mips_opts
.mips16
2195 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2196 /* Itbl support may require additional care here. */
2197 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2198 || (! gpr_interlocks
2199 && (prev_prev_insn
.insn_mo
->pinfo
2200 & INSN_LOAD_MEMORY_DELAY
)))
2201 && insn_uses_reg (ip
,
2202 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2205 /* If one instruction sets a condition code and the
2206 other one uses a condition code, we can not swap. */
2207 || ((pinfo
& INSN_READ_COND_CODE
)
2208 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2209 || ((pinfo
& INSN_WRITE_COND_CODE
)
2210 && (prev_pinfo
& INSN_READ_COND_CODE
))
2211 /* If the previous instruction uses the PC, we can not
2213 || (mips_opts
.mips16
2214 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2215 /* If the previous instruction was extended, we can not
2217 || (mips_opts
.mips16
&& prev_insn_extended
)
2218 /* If the previous instruction had a fixup in mips16
2219 mode, we can not swap. This normally means that the
2220 previous instruction was a 4 byte branch anyhow. */
2221 || (mips_opts
.mips16
&& prev_insn_fixp
)
2222 /* If the previous instruction is a sync, sync.l, or
2223 sync.p, we can not swap. */
2224 || (prev_pinfo
& INSN_SYNC
))
2226 /* We could do even better for unconditional branches to
2227 portions of this object file; we could pick up the
2228 instruction at the destination, put it in the delay
2229 slot, and bump the destination address. */
2231 /* Update the previous insn information. */
2232 prev_prev_insn
= *ip
;
2233 prev_insn
.insn_mo
= &dummy_opcode
;
2237 /* It looks like we can actually do the swap. */
2238 if (! mips_opts
.mips16
)
2243 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2244 memcpy (temp
, prev_f
, 4);
2245 memcpy (prev_f
, f
, 4);
2246 memcpy (f
, temp
, 4);
2249 prev_insn_fixp
->fx_frag
= frag_now
;
2250 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2254 fixp
->fx_frag
= prev_insn_frag
;
2255 fixp
->fx_where
= prev_insn_where
;
2263 assert (prev_insn_fixp
== NULL
);
2264 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2265 memcpy (temp
, prev_f
, 2);
2266 memcpy (prev_f
, f
, 2);
2267 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2269 assert (reloc_type
== BFD_RELOC_UNUSED
);
2270 memcpy (f
, temp
, 2);
2274 memcpy (f
, f
+ 2, 2);
2275 memcpy (f
+ 2, temp
, 2);
2279 fixp
->fx_frag
= prev_insn_frag
;
2280 fixp
->fx_where
= prev_insn_where
;
2284 /* Update the previous insn information; leave prev_insn
2286 prev_prev_insn
= *ip
;
2288 prev_insn_is_delay_slot
= 1;
2290 /* If that was an unconditional branch, forget the previous
2291 insn information. */
2292 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2294 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2295 prev_insn
.insn_mo
= &dummy_opcode
;
2298 prev_insn_fixp
= NULL
;
2299 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2300 prev_insn_extended
= 0;
2302 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2304 /* We don't yet optimize a branch likely. What we should do
2305 is look at the target, copy the instruction found there
2306 into the delay slot, and increment the branch to jump to
2307 the next instruction. */
2309 /* Update the previous insn information. */
2310 prev_prev_insn
= *ip
;
2311 prev_insn
.insn_mo
= &dummy_opcode
;
2312 prev_insn_fixp
= NULL
;
2313 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2314 prev_insn_extended
= 0;
2318 /* Update the previous insn information. */
2320 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2322 prev_prev_insn
= prev_insn
;
2325 /* Any time we see a branch, we always fill the delay slot
2326 immediately; since this insn is not a branch, we know it
2327 is not in a delay slot. */
2328 prev_insn_is_delay_slot
= 0;
2330 prev_insn_fixp
= fixp
;
2331 prev_insn_reloc_type
= reloc_type
;
2332 if (mips_opts
.mips16
)
2333 prev_insn_extended
= (ip
->use_extend
2334 || reloc_type
> BFD_RELOC_UNUSED
);
2337 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2338 prev_insn_unreordered
= 0;
2339 prev_insn_frag
= frag_now
;
2340 prev_insn_where
= f
- frag_now
->fr_literal
;
2341 prev_insn_valid
= 1;
2343 else if (place
== NULL
)
2345 /* We need to record a bit of information even when we are not
2346 reordering, in order to determine the base address for mips16
2347 PC relative relocs. */
2348 prev_prev_insn
= prev_insn
;
2350 prev_insn_reloc_type
= reloc_type
;
2351 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2352 prev_insn_unreordered
= 1;
2355 /* We just output an insn, so the next one doesn't have a label. */
2356 mips_clear_insn_labels ();
2358 /* We must ensure that a fixup associated with an unmatched %hi
2359 reloc does not become a variant frag. Otherwise, the
2360 rearrangement of %hi relocs in frob_file may confuse
2364 frag_wane (frag_now
);
2369 /* This function forgets that there was any previous instruction or
2370 label. If PRESERVE is non-zero, it remembers enough information to
2371 know whether nops are needed before a noreorder section. */
2374 mips_no_prev_insn (preserve
)
2379 prev_insn
.insn_mo
= &dummy_opcode
;
2380 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2381 prev_nop_frag
= NULL
;
2382 prev_nop_frag_holds
= 0;
2383 prev_nop_frag_required
= 0;
2384 prev_nop_frag_since
= 0;
2386 prev_insn_valid
= 0;
2387 prev_insn_is_delay_slot
= 0;
2388 prev_insn_unreordered
= 0;
2389 prev_insn_extended
= 0;
2390 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2391 prev_prev_insn_unreordered
= 0;
2392 mips_clear_insn_labels ();
2395 /* This function must be called whenever we turn on noreorder or emit
2396 something other than instructions. It inserts any NOPS which might
2397 be needed by the previous instruction, and clears the information
2398 kept for the previous instructions. The INSNS parameter is true if
2399 instructions are to follow. */
2402 mips_emit_delays (insns
)
2405 if (! mips_opts
.noreorder
)
2410 if ((! mips_opts
.mips16
2411 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2412 && (! cop_interlocks
2413 && (prev_insn
.insn_mo
->pinfo
2414 & (INSN_LOAD_COPROC_DELAY
2415 | INSN_COPROC_MOVE_DELAY
2416 | INSN_WRITE_COND_CODE
))))
2417 || (! hilo_interlocks
2418 && (prev_insn
.insn_mo
->pinfo
2421 || (! mips_opts
.mips16
2423 && (prev_insn
.insn_mo
->pinfo
2424 & INSN_LOAD_MEMORY_DELAY
))
2425 || (! mips_opts
.mips16
2426 && mips_opts
.isa
== ISA_MIPS1
2427 && (prev_insn
.insn_mo
->pinfo
2428 & INSN_COPROC_MEMORY_DELAY
)))
2430 /* Itbl support may require additional care here. */
2432 if ((! mips_opts
.mips16
2433 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2434 && (! cop_interlocks
2435 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2436 || (! hilo_interlocks
2437 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2438 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2441 if (prev_insn_unreordered
)
2444 else if ((! mips_opts
.mips16
2445 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2446 && (! cop_interlocks
2447 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2448 || (! hilo_interlocks
2449 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2450 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2452 /* Itbl support may require additional care here. */
2453 if (! prev_prev_insn_unreordered
)
2459 struct insn_label_list
*l
;
2463 /* Record the frag which holds the nop instructions, so
2464 that we can remove them if we don't need them. */
2465 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2466 prev_nop_frag
= frag_now
;
2467 prev_nop_frag_holds
= nops
;
2468 prev_nop_frag_required
= 0;
2469 prev_nop_frag_since
= 0;
2472 for (; nops
> 0; --nops
)
2477 /* Move on to a new frag, so that it is safe to simply
2478 decrease the size of prev_nop_frag. */
2479 frag_wane (frag_now
);
2483 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2487 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2488 symbol_set_frag (l
->label
, frag_now
);
2489 val
= (valueT
) frag_now_fix ();
2490 /* mips16 text labels are stored as odd. */
2491 if (mips_opts
.mips16
)
2493 S_SET_VALUE (l
->label
, val
);
2498 /* Mark instruction labels in mips16 mode. */
2499 if (mips_opts
.mips16
&& insns
)
2500 mips16_mark_labels ();
2502 mips_no_prev_insn (insns
);
2505 /* Build an instruction created by a macro expansion. This is passed
2506 a pointer to the count of instructions created so far, an
2507 expression, the name of the instruction to build, an operand format
2508 string, and corresponding arguments. */
2512 macro_build (char *place
,
2520 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2529 struct mips_cl_insn insn
;
2530 bfd_reloc_code_real_type r
;
2534 va_start (args
, fmt
);
2540 * If the macro is about to expand into a second instruction,
2541 * print a warning if needed. We need to pass ip as a parameter
2542 * to generate a better warning message here...
2544 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2545 as_warn (_("Macro instruction expanded into multiple instructions"));
2548 *counter
+= 1; /* bump instruction counter */
2550 if (mips_opts
.mips16
)
2552 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2557 r
= BFD_RELOC_UNUSED
;
2558 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2559 assert (insn
.insn_mo
);
2560 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2562 /* Search until we get a match for NAME. */
2565 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2566 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2567 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2568 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2572 assert (insn
.insn_mo
->name
);
2573 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2576 insn
.insn_opcode
= insn
.insn_mo
->match
;
2592 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2596 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2601 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2606 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2611 int tmp
= va_arg (args
, int);
2613 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2614 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2620 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2627 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2631 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2635 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2639 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2643 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2650 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2656 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2657 assert (r
== BFD_RELOC_MIPS_GPREL
2658 || r
== BFD_RELOC_MIPS_LITERAL
2659 || r
== BFD_RELOC_LO16
2660 || r
== BFD_RELOC_MIPS_GOT16
2661 || r
== BFD_RELOC_MIPS_CALL16
2662 || r
== BFD_RELOC_MIPS_GOT_LO16
2663 || r
== BFD_RELOC_MIPS_CALL_LO16
2664 || (ep
->X_op
== O_subtract
2665 && r
== BFD_RELOC_PCREL_LO16
));
2669 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2671 && (ep
->X_op
== O_constant
2672 || (ep
->X_op
== O_symbol
2673 && (r
== BFD_RELOC_HI16_S
2674 || r
== BFD_RELOC_HI16
2675 || r
== BFD_RELOC_MIPS_GOT_HI16
2676 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2677 || (ep
->X_op
== O_subtract
2678 && r
== BFD_RELOC_PCREL_HI16_S
)));
2679 if (ep
->X_op
== O_constant
)
2681 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2683 r
= BFD_RELOC_UNUSED
;
2688 assert (ep
!= NULL
);
2690 * This allows macro() to pass an immediate expression for
2691 * creating short branches without creating a symbol.
2692 * Note that the expression still might come from the assembly
2693 * input, in which case the value is not checked for range nor
2694 * is a relocation entry generated (yuck).
2696 if (ep
->X_op
== O_constant
)
2698 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2702 r
= BFD_RELOC_16_PCREL_S2
;
2706 assert (ep
!= NULL
);
2707 r
= BFD_RELOC_MIPS_JMP
;
2711 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2720 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2722 append_insn (place
, &insn
, ep
, r
, false);
2726 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2728 int *counter ATTRIBUTE_UNUSED
;
2734 struct mips_cl_insn insn
;
2735 bfd_reloc_code_real_type r
;
2737 r
= BFD_RELOC_UNUSED
;
2738 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2739 assert (insn
.insn_mo
);
2740 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2742 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2743 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2746 assert (insn
.insn_mo
->name
);
2747 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2750 insn
.insn_opcode
= insn
.insn_mo
->match
;
2751 insn
.use_extend
= false;
2770 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2775 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2779 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2783 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2793 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2800 regno
= va_arg (args
, int);
2801 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2802 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2823 assert (ep
!= NULL
);
2825 if (ep
->X_op
!= O_constant
)
2826 r
= BFD_RELOC_UNUSED
+ c
;
2829 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2830 false, false, &insn
.insn_opcode
,
2831 &insn
.use_extend
, &insn
.extend
);
2833 r
= BFD_RELOC_UNUSED
;
2839 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2846 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2848 append_insn (place
, &insn
, ep
, r
, false);
2852 * Generate a "lui" instruction.
2855 macro_build_lui (place
, counter
, ep
, regnum
)
2861 expressionS high_expr
;
2862 struct mips_cl_insn insn
;
2863 bfd_reloc_code_real_type r
;
2864 CONST
char *name
= "lui";
2865 CONST
char *fmt
= "t,u";
2867 assert (! mips_opts
.mips16
);
2873 high_expr
.X_op
= O_constant
;
2874 high_expr
.X_add_number
= ep
->X_add_number
;
2877 if (high_expr
.X_op
== O_constant
)
2879 /* we can compute the instruction now without a relocation entry */
2880 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
2882 r
= BFD_RELOC_UNUSED
;
2886 assert (ep
->X_op
== O_symbol
);
2887 /* _gp_disp is a special case, used from s_cpload. */
2888 assert (mips_pic
== NO_PIC
2889 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2890 r
= BFD_RELOC_HI16_S
;
2894 * If the macro is about to expand into a second instruction,
2895 * print a warning if needed. We need to pass ip as a parameter
2896 * to generate a better warning message here...
2898 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2899 as_warn (_("Macro instruction expanded into multiple instructions"));
2902 *counter
+= 1; /* bump instruction counter */
2904 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2905 assert (insn
.insn_mo
);
2906 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2907 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2909 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2910 if (r
== BFD_RELOC_UNUSED
)
2912 insn
.insn_opcode
|= high_expr
.X_add_number
;
2913 append_insn (place
, &insn
, NULL
, r
, false);
2916 append_insn (place
, &insn
, &high_expr
, r
, false);
2920 * Generates code to set the $at register to true (one)
2921 * if reg is less than the immediate expression.
2924 set_at (counter
, reg
, unsignedp
)
2929 if (imm_expr
.X_op
== O_constant
2930 && imm_expr
.X_add_number
>= -0x8000
2931 && imm_expr
.X_add_number
< 0x8000)
2932 macro_build ((char *) NULL
, counter
, &imm_expr
,
2933 unsignedp
? "sltiu" : "slti",
2934 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2937 load_register (counter
, AT
, &imm_expr
, 0);
2938 macro_build ((char *) NULL
, counter
, NULL
,
2939 unsignedp
? "sltu" : "slt",
2940 "d,v,t", AT
, reg
, AT
);
2944 /* Warn if an expression is not a constant. */
2947 check_absolute_expr (ip
, ex
)
2948 struct mips_cl_insn
*ip
;
2951 if (ex
->X_op
== O_big
)
2952 as_bad (_("unsupported large constant"));
2953 else if (ex
->X_op
!= O_constant
)
2954 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2957 /* Count the leading zeroes by performing a binary chop. This is a
2958 bulky bit of source, but performance is a LOT better for the
2959 majority of values than a simple loop to count the bits:
2960 for (lcnt = 0; (lcnt < 32); lcnt++)
2961 if ((v) & (1 << (31 - lcnt)))
2963 However it is not code size friendly, and the gain will drop a bit
2964 on certain cached systems.
2966 #define COUNT_TOP_ZEROES(v) \
2967 (((v) & ~0xffff) == 0 \
2968 ? ((v) & ~0xff) == 0 \
2969 ? ((v) & ~0xf) == 0 \
2970 ? ((v) & ~0x3) == 0 \
2971 ? ((v) & ~0x1) == 0 \
2976 : ((v) & ~0x7) == 0 \
2979 : ((v) & ~0x3f) == 0 \
2980 ? ((v) & ~0x1f) == 0 \
2983 : ((v) & ~0x7f) == 0 \
2986 : ((v) & ~0xfff) == 0 \
2987 ? ((v) & ~0x3ff) == 0 \
2988 ? ((v) & ~0x1ff) == 0 \
2991 : ((v) & ~0x7ff) == 0 \
2994 : ((v) & ~0x3fff) == 0 \
2995 ? ((v) & ~0x1fff) == 0 \
2998 : ((v) & ~0x7fff) == 0 \
3001 : ((v) & ~0xffffff) == 0 \
3002 ? ((v) & ~0xfffff) == 0 \
3003 ? ((v) & ~0x3ffff) == 0 \
3004 ? ((v) & ~0x1ffff) == 0 \
3007 : ((v) & ~0x7ffff) == 0 \
3010 : ((v) & ~0x3fffff) == 0 \
3011 ? ((v) & ~0x1fffff) == 0 \
3014 : ((v) & ~0x7fffff) == 0 \
3017 : ((v) & ~0xfffffff) == 0 \
3018 ? ((v) & ~0x3ffffff) == 0 \
3019 ? ((v) & ~0x1ffffff) == 0 \
3022 : ((v) & ~0x7ffffff) == 0 \
3025 : ((v) & ~0x3fffffff) == 0 \
3026 ? ((v) & ~0x1fffffff) == 0 \
3029 : ((v) & ~0x7fffffff) == 0 \
3034 * This routine generates the least number of instructions neccessary to load
3035 * an absolute expression value into a register.
3038 load_register (counter
, reg
, ep
, dbl
)
3045 expressionS hi32
, lo32
;
3047 if (ep
->X_op
!= O_big
)
3049 assert (ep
->X_op
== O_constant
);
3050 if (ep
->X_add_number
< 0x8000
3051 && (ep
->X_add_number
>= 0
3052 || (ep
->X_add_number
>= -0x8000
3055 || sizeof (ep
->X_add_number
) > 4))))
3057 /* We can handle 16 bit signed values with an addiu to
3058 $zero. No need to ever use daddiu here, since $zero and
3059 the result are always correct in 32 bit mode. */
3060 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3061 (int) BFD_RELOC_LO16
);
3064 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3066 /* We can handle 16 bit unsigned values with an ori to
3068 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3069 (int) BFD_RELOC_LO16
);
3072 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3073 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3074 == ~ (offsetT
) 0x7fffffff))
3077 || sizeof (ep
->X_add_number
) > 4
3078 || (ep
->X_add_number
& 0x80000000) == 0))
3079 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3080 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3083 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3084 == ~ (offsetT
) 0xffffffff)))
3086 /* 32 bit values require an lui. */
3087 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3088 (int) BFD_RELOC_HI16
);
3089 if ((ep
->X_add_number
& 0xffff) != 0)
3090 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3091 (int) BFD_RELOC_LO16
);
3096 /* The value is larger than 32 bits. */
3098 if (HAVE_32BIT_GPRS
)
3100 as_bad (_("Number larger than 32 bits"));
3101 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3102 (int) BFD_RELOC_LO16
);
3106 if (ep
->X_op
!= O_big
)
3109 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3110 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3111 hi32
.X_add_number
&= 0xffffffff;
3113 lo32
.X_add_number
&= 0xffffffff;
3117 assert (ep
->X_add_number
> 2);
3118 if (ep
->X_add_number
== 3)
3119 generic_bignum
[3] = 0;
3120 else if (ep
->X_add_number
> 4)
3121 as_bad (_("Number larger than 64 bits"));
3122 lo32
.X_op
= O_constant
;
3123 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3124 hi32
.X_op
= O_constant
;
3125 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3128 if (hi32
.X_add_number
== 0)
3133 unsigned long hi
, lo
;
3135 if (hi32
.X_add_number
== 0xffffffff)
3137 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3139 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3140 reg
, 0, (int) BFD_RELOC_LO16
);
3143 if (lo32
.X_add_number
& 0x80000000)
3145 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3146 (int) BFD_RELOC_HI16
);
3147 if (lo32
.X_add_number
& 0xffff)
3148 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3149 reg
, reg
, (int) BFD_RELOC_LO16
);
3154 /* Check for 16bit shifted constant. We know that hi32 is
3155 non-zero, so start the mask on the first bit of the hi32
3160 unsigned long himask
, lomask
;
3164 himask
= 0xffff >> (32 - shift
);
3165 lomask
= (0xffff << shift
) & 0xffffffff;
3169 himask
= 0xffff << (shift
- 32);
3172 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3173 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3177 tmp
.X_op
= O_constant
;
3179 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3180 | (lo32
.X_add_number
>> shift
));
3182 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3183 macro_build ((char *) NULL
, counter
, &tmp
,
3184 "ori", "t,r,i", reg
, 0,
3185 (int) BFD_RELOC_LO16
);
3186 macro_build ((char *) NULL
, counter
, NULL
,
3187 (shift
>= 32) ? "dsll32" : "dsll",
3189 (shift
>= 32) ? shift
- 32 : shift
);
3194 while (shift
<= (64 - 16));
3196 /* Find the bit number of the lowest one bit, and store the
3197 shifted value in hi/lo. */
3198 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3199 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3203 while ((lo
& 1) == 0)
3208 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3214 while ((hi
& 1) == 0)
3223 /* Optimize if the shifted value is a (power of 2) - 1. */
3224 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3225 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3227 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3232 /* This instruction will set the register to be all
3234 tmp
.X_op
= O_constant
;
3235 tmp
.X_add_number
= (offsetT
) -1;
3236 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3237 reg
, 0, (int) BFD_RELOC_LO16
);
3241 macro_build ((char *) NULL
, counter
, NULL
,
3242 (bit
>= 32) ? "dsll32" : "dsll",
3244 (bit
>= 32) ? bit
- 32 : bit
);
3246 macro_build ((char *) NULL
, counter
, NULL
,
3247 (shift
>= 32) ? "dsrl32" : "dsrl",
3249 (shift
>= 32) ? shift
- 32 : shift
);
3254 /* Sign extend hi32 before calling load_register, because we can
3255 generally get better code when we load a sign extended value. */
3256 if ((hi32
.X_add_number
& 0x80000000) != 0)
3257 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3258 load_register (counter
, reg
, &hi32
, 0);
3261 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3265 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3274 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3276 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3277 (int) BFD_RELOC_HI16
);
3278 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3285 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3290 mid16
.X_add_number
>>= 16;
3291 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3292 freg
, (int) BFD_RELOC_LO16
);
3293 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3297 if ((lo32
.X_add_number
& 0xffff) != 0)
3298 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3299 (int) BFD_RELOC_LO16
);
3302 /* Load an address into a register. */
3305 load_address (counter
, reg
, ep
)
3312 if (ep
->X_op
!= O_constant
3313 && ep
->X_op
!= O_symbol
)
3315 as_bad (_("expression too complex"));
3316 ep
->X_op
= O_constant
;
3319 if (ep
->X_op
== O_constant
)
3321 load_register (counter
, reg
, ep
, 0);
3325 if (mips_pic
== NO_PIC
)
3327 /* If this is a reference to a GP relative symbol, we want
3328 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3330 lui $reg,<sym> (BFD_RELOC_HI16_S)
3331 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3332 If we have an addend, we always use the latter form. */
3333 if ((valueT
) ep
->X_add_number
> MAX_GPREL_OFFSET
3334 || nopic_need_relax (ep
->X_add_symbol
, 1))
3339 macro_build ((char *) NULL
, counter
, ep
,
3340 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3341 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3342 p
= frag_var (rs_machine_dependent
, 8, 0,
3343 RELAX_ENCODE (4, 8, 0, 4, 0,
3344 mips_opts
.warn_about_macros
),
3345 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3347 macro_build_lui (p
, counter
, ep
, reg
);
3350 macro_build (p
, counter
, ep
,
3351 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3352 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3354 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3358 /* If this is a reference to an external symbol, we want
3359 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3361 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3363 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3364 If there is a constant, it must be added in after. */
3365 ex
.X_add_number
= ep
->X_add_number
;
3366 ep
->X_add_number
= 0;
3368 macro_build ((char *) NULL
, counter
, ep
,
3369 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3370 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3371 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3372 p
= frag_var (rs_machine_dependent
, 4, 0,
3373 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3374 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3375 macro_build (p
, counter
, ep
,
3376 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3377 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3378 if (ex
.X_add_number
!= 0)
3380 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3381 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3382 ex
.X_op
= O_constant
;
3383 macro_build ((char *) NULL
, counter
, &ex
,
3384 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3385 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3388 else if (mips_pic
== SVR4_PIC
)
3393 /* This is the large GOT case. If this is a reference to an
3394 external symbol, we want
3395 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3397 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3398 Otherwise, for a reference to a local symbol, we want
3399 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3401 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3402 If there is a constant, it must be added in after. */
3403 ex
.X_add_number
= ep
->X_add_number
;
3404 ep
->X_add_number
= 0;
3405 if (reg_needs_delay (GP
))
3410 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3411 (int) BFD_RELOC_MIPS_GOT_HI16
);
3412 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3413 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3414 "d,v,t", reg
, reg
, GP
);
3415 macro_build ((char *) NULL
, counter
, ep
,
3416 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3417 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3418 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3419 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3420 mips_opts
.warn_about_macros
),
3421 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3424 /* We need a nop before loading from $gp. This special
3425 check is required because the lui which starts the main
3426 instruction stream does not refer to $gp, and so will not
3427 insert the nop which may be required. */
3428 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3431 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3432 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3434 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3436 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3437 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3438 if (ex
.X_add_number
!= 0)
3440 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3441 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3442 ex
.X_op
= O_constant
;
3443 macro_build ((char *) NULL
, counter
, &ex
,
3444 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3445 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3448 else if (mips_pic
== EMBEDDED_PIC
)
3451 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3453 macro_build ((char *) NULL
, counter
, ep
,
3454 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3455 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3461 /* Move the contents of register SOURCE into register DEST. */
3464 move_register (counter
, dest
, source
)
3469 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3470 HAVE_32BIT_GPRS
? "addu" : "daddu",
3471 "d,v,t", dest
, source
, 0);
3476 * This routine implements the seemingly endless macro or synthesized
3477 * instructions and addressing modes in the mips assembly language. Many
3478 * of these macros are simple and are similar to each other. These could
3479 * probably be handled by some kind of table or grammer aproach instead of
3480 * this verbose method. Others are not simple macros but are more like
3481 * optimizing code generation.
3482 * One interesting optimization is when several store macros appear
3483 * consecutivly that would load AT with the upper half of the same address.
3484 * The ensuing load upper instructions are ommited. This implies some kind
3485 * of global optimization. We currently only optimize within a single macro.
3486 * For many of the load and store macros if the address is specified as a
3487 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3488 * first load register 'at' with zero and use it as the base register. The
3489 * mips assembler simply uses register $zero. Just one tiny optimization
3494 struct mips_cl_insn
*ip
;
3496 register int treg
, sreg
, dreg
, breg
;
3512 bfd_reloc_code_real_type r
;
3514 int hold_mips_optimize
;
3516 assert (! mips_opts
.mips16
);
3518 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3519 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3520 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3521 mask
= ip
->insn_mo
->mask
;
3523 expr1
.X_op
= O_constant
;
3524 expr1
.X_op_symbol
= NULL
;
3525 expr1
.X_add_symbol
= NULL
;
3526 expr1
.X_add_number
= 1;
3538 mips_emit_delays (true);
3539 ++mips_opts
.noreorder
;
3540 mips_any_noreorder
= 1;
3542 expr1
.X_add_number
= 8;
3543 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3545 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3547 move_register (&icnt
, dreg
, sreg
);
3548 macro_build ((char *) NULL
, &icnt
, NULL
,
3549 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3551 --mips_opts
.noreorder
;
3572 if (imm_expr
.X_op
== O_constant
3573 && imm_expr
.X_add_number
>= -0x8000
3574 && imm_expr
.X_add_number
< 0x8000)
3576 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3577 (int) BFD_RELOC_LO16
);
3580 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3581 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3600 if (imm_expr
.X_op
== O_constant
3601 && imm_expr
.X_add_number
>= 0
3602 && imm_expr
.X_add_number
< 0x10000)
3604 if (mask
!= M_NOR_I
)
3605 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3606 sreg
, (int) BFD_RELOC_LO16
);
3609 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3610 treg
, sreg
, (int) BFD_RELOC_LO16
);
3611 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3617 load_register (&icnt
, AT
, &imm_expr
, 0);
3618 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3635 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3641 load_register (&icnt
, AT
, &imm_expr
, 0);
3642 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3650 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3651 likely
? "bgezl" : "bgez",
3657 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3658 likely
? "blezl" : "blez",
3662 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3663 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3664 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3670 /* check for > max integer */
3671 maxnum
= 0x7fffffff;
3672 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3679 if (imm_expr
.X_op
== O_constant
3680 && imm_expr
.X_add_number
>= maxnum
3681 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3684 /* result is always false */
3688 as_warn (_("Branch %s is always false (nop)"),
3690 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3695 as_warn (_("Branch likely %s is always false"),
3697 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3702 if (imm_expr
.X_op
!= O_constant
)
3703 as_bad (_("Unsupported large constant"));
3704 imm_expr
.X_add_number
++;
3708 if (mask
== M_BGEL_I
)
3710 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3713 likely
? "bgezl" : "bgez", "s,p", sreg
);
3716 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3719 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3722 maxnum
= 0x7fffffff;
3723 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3730 maxnum
= - maxnum
- 1;
3731 if (imm_expr
.X_op
== O_constant
3732 && imm_expr
.X_add_number
<= maxnum
3733 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3736 /* result is always true */
3737 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3741 set_at (&icnt
, sreg
, 0);
3742 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3743 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3754 likely
? "beql" : "beq", "s,t,p", 0, treg
);
3757 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3759 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3760 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3768 && imm_expr
.X_op
== O_constant
3769 && imm_expr
.X_add_number
== 0xffffffff))
3771 if (imm_expr
.X_op
!= O_constant
)
3772 as_bad (_("Unsupported large constant"));
3773 imm_expr
.X_add_number
++;
3777 if (mask
== M_BGEUL_I
)
3779 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3781 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3783 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3784 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3787 set_at (&icnt
, sreg
, 1);
3788 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3789 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3798 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 likely
? "bltzl" : "bltz", "s,p", treg
);
3807 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3808 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3809 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3818 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3823 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3825 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3826 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3834 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3835 likely
? "blezl" : "blez", "s,p", sreg
);
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3841 likely
? "bgezl" : "bgez", "s,p", treg
);
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3846 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3852 maxnum
= 0x7fffffff;
3853 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3860 if (imm_expr
.X_op
== O_constant
3861 && imm_expr
.X_add_number
>= maxnum
3862 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3864 if (imm_expr
.X_op
!= O_constant
)
3865 as_bad (_("Unsupported large constant"));
3866 imm_expr
.X_add_number
++;
3870 if (mask
== M_BLTL_I
)
3872 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3875 likely
? "bltzl" : "bltz", "s,p", sreg
);
3878 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3880 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3881 likely
? "blezl" : "blez", "s,p", sreg
);
3884 set_at (&icnt
, sreg
, 0);
3885 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3886 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3894 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3895 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
3900 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3911 && imm_expr
.X_op
== O_constant
3912 && imm_expr
.X_add_number
== 0xffffffff))
3914 if (imm_expr
.X_op
!= O_constant
)
3915 as_bad (_("Unsupported large constant"));
3916 imm_expr
.X_add_number
++;
3920 if (mask
== M_BLTUL_I
)
3922 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3924 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3926 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3927 likely
? "beql" : "beq",
3931 set_at (&icnt
, sreg
, 1);
3932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3933 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3941 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3942 likely
? "bltzl" : "bltz", "s,p", sreg
);
3947 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3948 likely
? "bgtzl" : "bgtz", "s,p", treg
);
3951 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3952 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3953 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3963 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3964 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
3967 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3969 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3970 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
3985 as_warn (_("Divide by zero."));
3987 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3989 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3993 mips_emit_delays (true);
3994 ++mips_opts
.noreorder
;
3995 mips_any_noreorder
= 1;
3998 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3999 macro_build ((char *) NULL
, &icnt
, NULL
,
4000 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4004 expr1
.X_add_number
= 8;
4005 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4006 macro_build ((char *) NULL
, &icnt
, NULL
,
4007 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4008 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4010 expr1
.X_add_number
= -1;
4011 macro_build ((char *) NULL
, &icnt
, &expr1
,
4012 dbl
? "daddiu" : "addiu",
4013 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4014 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4015 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4018 expr1
.X_add_number
= 1;
4019 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4020 (int) BFD_RELOC_LO16
);
4021 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4026 expr1
.X_add_number
= 0x80000000;
4027 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4028 (int) BFD_RELOC_HI16
);
4032 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4033 /* We want to close the noreorder block as soon as possible, so
4034 that later insns are available for delay slot filling. */
4035 --mips_opts
.noreorder
;
4039 expr1
.X_add_number
= 8;
4040 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4041 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4043 /* We want to close the noreorder block as soon as possible, so
4044 that later insns are available for delay slot filling. */
4045 --mips_opts
.noreorder
;
4047 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4049 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4088 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4090 as_warn (_("Divide by zero."));
4092 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4094 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4097 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4099 if (strcmp (s2
, "mflo") == 0)
4100 move_register (&icnt
, dreg
, sreg
);
4102 move_register (&icnt
, dreg
, 0);
4105 if (imm_expr
.X_op
== O_constant
4106 && imm_expr
.X_add_number
== -1
4107 && s
[strlen (s
) - 1] != 'u')
4109 if (strcmp (s2
, "mflo") == 0)
4111 macro_build ((char *) NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg",
4115 move_register (&icnt
, dreg
, 0);
4119 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4120 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4121 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4140 mips_emit_delays (true);
4141 ++mips_opts
.noreorder
;
4142 mips_any_noreorder
= 1;
4145 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4146 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4147 /* We want to close the noreorder block as soon as possible, so
4148 that later insns are available for delay slot filling. */
4149 --mips_opts
.noreorder
;
4153 expr1
.X_add_number
= 8;
4154 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4155 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4157 /* We want to close the noreorder block as soon as possible, so
4158 that later insns are available for delay slot filling. */
4159 --mips_opts
.noreorder
;
4160 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4162 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4168 /* Load the address of a symbol into a register. If breg is not
4169 zero, we then add a base register to it. */
4171 /* When generating embedded PIC code, we permit expressions of
4174 where bar is an address in the current section. These are used
4175 when getting the addresses of functions. We don't permit
4176 X_add_number to be non-zero, because if the symbol is
4177 external the relaxing code needs to know that any addend is
4178 purely the offset to X_op_symbol. */
4179 if (mips_pic
== EMBEDDED_PIC
4180 && offset_expr
.X_op
== O_subtract
4181 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4182 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4183 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4185 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4189 && (offset_expr
.X_add_number
== 0
4190 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4192 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4193 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4194 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4195 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4196 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4200 if (offset_expr
.X_op
!= O_symbol
4201 && offset_expr
.X_op
!= O_constant
)
4203 as_bad (_("expression too complex"));
4204 offset_expr
.X_op
= O_constant
;
4218 if (offset_expr
.X_op
== O_constant
)
4219 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4220 else if (mips_pic
== NO_PIC
)
4222 /* If this is a reference to an GP relative symbol, we want
4223 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4225 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4226 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4227 If we have a constant, we need two instructions anyhow,
4228 so we may as well always use the latter form. */
4229 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
4230 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4235 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4236 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4237 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4238 p
= frag_var (rs_machine_dependent
, 8, 0,
4239 RELAX_ENCODE (4, 8, 0, 4, 0,
4240 mips_opts
.warn_about_macros
),
4241 offset_expr
.X_add_symbol
, (offsetT
) 0,
4244 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4247 macro_build (p
, &icnt
, &offset_expr
,
4248 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4249 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4251 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4253 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4255 /* If this is a reference to an external symbol, and there
4256 is no constant, we want
4257 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4258 or if tempreg is PIC_CALL_REG
4259 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4260 For a local symbol, we want
4261 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4263 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4265 If we have a small constant, and this is a reference to
4266 an external symbol, we want
4267 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4269 addiu $tempreg,$tempreg,<constant>
4270 For a local symbol, we want the same instruction
4271 sequence, but we output a BFD_RELOC_LO16 reloc on the
4274 If we have a large constant, and this is a reference to
4275 an external symbol, we want
4276 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4277 lui $at,<hiconstant>
4278 addiu $at,$at,<loconstant>
4279 addu $tempreg,$tempreg,$at
4280 For a local symbol, we want the same instruction
4281 sequence, but we output a BFD_RELOC_LO16 reloc on the
4282 addiu instruction. */
4283 expr1
.X_add_number
= offset_expr
.X_add_number
;
4284 offset_expr
.X_add_number
= 0;
4286 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4287 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4290 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4291 if (expr1
.X_add_number
== 0)
4299 /* We're going to put in an addu instruction using
4300 tempreg, so we may as well insert the nop right
4302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4306 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4307 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4309 ? mips_opts
.warn_about_macros
4311 offset_expr
.X_add_symbol
, (offsetT
) 0,
4315 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4318 macro_build (p
, &icnt
, &expr1
,
4319 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4320 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4321 /* FIXME: If breg == 0, and the next instruction uses
4322 $tempreg, then if this variant case is used an extra
4323 nop will be generated. */
4325 else if (expr1
.X_add_number
>= -0x8000
4326 && expr1
.X_add_number
< 0x8000)
4328 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4330 macro_build ((char *) NULL
, &icnt
, &expr1
,
4331 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4332 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4333 (void) frag_var (rs_machine_dependent
, 0, 0,
4334 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4335 offset_expr
.X_add_symbol
, (offsetT
) 0,
4342 /* If we are going to add in a base register, and the
4343 target register and the base register are the same,
4344 then we are using AT as a temporary register. Since
4345 we want to load the constant into AT, we add our
4346 current AT (from the global offset table) and the
4347 register into the register now, and pretend we were
4348 not using a base register. */
4353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4355 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4356 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4357 "d,v,t", treg
, AT
, breg
);
4363 /* Set mips_optimize around the lui instruction to avoid
4364 inserting an unnecessary nop after the lw. */
4365 hold_mips_optimize
= mips_optimize
;
4367 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4368 mips_optimize
= hold_mips_optimize
;
4370 macro_build ((char *) NULL
, &icnt
, &expr1
,
4371 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4372 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4374 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4375 "d,v,t", tempreg
, tempreg
, AT
);
4376 (void) frag_var (rs_machine_dependent
, 0, 0,
4377 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4378 offset_expr
.X_add_symbol
, (offsetT
) 0,
4383 else if (mips_pic
== SVR4_PIC
)
4386 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4387 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4389 /* This is the large GOT case. If this is a reference to an
4390 external symbol, and there is no constant, we want
4391 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4392 addu $tempreg,$tempreg,$gp
4393 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4394 or if tempreg is PIC_CALL_REG
4395 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4396 addu $tempreg,$tempreg,$gp
4397 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4398 For a local symbol, we want
4399 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4401 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4403 If we have a small constant, and this is a reference to
4404 an external symbol, we want
4405 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4406 addu $tempreg,$tempreg,$gp
4407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4409 addiu $tempreg,$tempreg,<constant>
4410 For a local symbol, we want
4411 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4413 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4415 If we have a large constant, and this is a reference to
4416 an external symbol, we want
4417 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4418 addu $tempreg,$tempreg,$gp
4419 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4420 lui $at,<hiconstant>
4421 addiu $at,$at,<loconstant>
4422 addu $tempreg,$tempreg,$at
4423 For a local symbol, we want
4424 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4425 lui $at,<hiconstant>
4426 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4427 addu $tempreg,$tempreg,$at
4429 expr1
.X_add_number
= offset_expr
.X_add_number
;
4430 offset_expr
.X_add_number
= 0;
4432 if (reg_needs_delay (GP
))
4436 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4438 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4439 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4441 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4442 tempreg
, lui_reloc_type
);
4443 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4444 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4445 "d,v,t", tempreg
, tempreg
, GP
);
4446 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4448 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4449 if (expr1
.X_add_number
== 0)
4457 /* We're going to put in an addu instruction using
4458 tempreg, so we may as well insert the nop right
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4465 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4466 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4469 ? mips_opts
.warn_about_macros
4471 offset_expr
.X_add_symbol
, (offsetT
) 0,
4474 else if (expr1
.X_add_number
>= -0x8000
4475 && expr1
.X_add_number
< 0x8000)
4477 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4479 macro_build ((char *) NULL
, &icnt
, &expr1
,
4480 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4481 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4483 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4484 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4486 ? mips_opts
.warn_about_macros
4488 offset_expr
.X_add_symbol
, (offsetT
) 0,
4495 /* If we are going to add in a base register, and the
4496 target register and the base register are the same,
4497 then we are using AT as a temporary register. Since
4498 we want to load the constant into AT, we add our
4499 current AT (from the global offset table) and the
4500 register into the register now, and pretend we were
4501 not using a base register. */
4509 assert (tempreg
== AT
);
4510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4512 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4513 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4514 "d,v,t", treg
, AT
, breg
);
4519 /* Set mips_optimize around the lui instruction to avoid
4520 inserting an unnecessary nop after the lw. */
4521 hold_mips_optimize
= mips_optimize
;
4523 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4524 mips_optimize
= hold_mips_optimize
;
4526 macro_build ((char *) NULL
, &icnt
, &expr1
,
4527 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4528 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4529 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4530 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4531 "d,v,t", dreg
, dreg
, AT
);
4533 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4534 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4537 ? mips_opts
.warn_about_macros
4539 offset_expr
.X_add_symbol
, (offsetT
) 0,
4547 /* This is needed because this instruction uses $gp, but
4548 the first instruction on the main stream does not. */
4549 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4552 macro_build (p
, &icnt
, &offset_expr
,
4554 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4556 if (expr1
.X_add_number
>= -0x8000
4557 && expr1
.X_add_number
< 0x8000)
4559 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4561 macro_build (p
, &icnt
, &expr1
,
4562 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4563 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4564 /* FIXME: If add_number is 0, and there was no base
4565 register, the external symbol case ended with a load,
4566 so if the symbol turns out to not be external, and
4567 the next instruction uses tempreg, an unnecessary nop
4568 will be inserted. */
4574 /* We must add in the base register now, as in the
4575 external symbol case. */
4576 assert (tempreg
== AT
);
4577 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4579 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4580 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4581 "d,v,t", treg
, AT
, breg
);
4584 /* We set breg to 0 because we have arranged to add
4585 it in in both cases. */
4589 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4591 macro_build (p
, &icnt
, &expr1
,
4592 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4593 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4595 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4596 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4597 "d,v,t", tempreg
, tempreg
, AT
);
4601 else if (mips_pic
== EMBEDDED_PIC
)
4604 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4606 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4607 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4608 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4615 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4616 "d,v,t", treg
, tempreg
, breg
);
4624 /* The j instruction may not be used in PIC code, since it
4625 requires an absolute address. We convert it to a b
4627 if (mips_pic
== NO_PIC
)
4628 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4633 /* The jal instructions must be handled as macros because when
4634 generating PIC code they expand to multi-instruction
4635 sequences. Normally they are simple instructions. */
4640 if (mips_pic
== NO_PIC
4641 || mips_pic
== EMBEDDED_PIC
)
4642 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4644 else if (mips_pic
== SVR4_PIC
)
4646 if (sreg
!= PIC_CALL_REG
)
4647 as_warn (_("MIPS PIC call to register other than $25"));
4649 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4651 if (mips_cprestore_offset
< 0)
4652 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4655 expr1
.X_add_number
= mips_cprestore_offset
;
4656 macro_build ((char *) NULL
, &icnt
, &expr1
,
4657 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4658 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4667 if (mips_pic
== NO_PIC
)
4668 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4669 else if (mips_pic
== SVR4_PIC
)
4671 /* If this is a reference to an external symbol, and we are
4672 using a small GOT, we want
4673 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4677 lw $gp,cprestore($sp)
4678 The cprestore value is set using the .cprestore
4679 pseudo-op. If we are using a big GOT, we want
4680 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4682 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4686 lw $gp,cprestore($sp)
4687 If the symbol is not external, we want
4688 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4690 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4693 lw $gp,cprestore($sp) */
4697 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4698 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4699 "t,o(b)", PIC_CALL_REG
,
4700 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4703 p
= frag_var (rs_machine_dependent
, 4, 0,
4704 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4705 offset_expr
.X_add_symbol
, (offsetT
) 0,
4712 if (reg_needs_delay (GP
))
4716 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4717 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4719 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4720 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4721 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4722 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4723 "t,o(b)", PIC_CALL_REG
,
4724 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4727 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4728 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4730 offset_expr
.X_add_symbol
, (offsetT
) 0,
4734 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4737 macro_build (p
, &icnt
, &offset_expr
,
4738 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4739 "t,o(b)", PIC_CALL_REG
,
4740 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4742 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4745 macro_build (p
, &icnt
, &offset_expr
,
4746 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4747 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4748 (int) BFD_RELOC_LO16
);
4749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4750 "jalr", "s", PIC_CALL_REG
);
4751 if (mips_cprestore_offset
< 0)
4752 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4755 if (mips_opts
.noreorder
)
4756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4758 expr1
.X_add_number
= mips_cprestore_offset
;
4759 macro_build ((char *) NULL
, &icnt
, &expr1
,
4760 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4761 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4765 else if (mips_pic
== EMBEDDED_PIC
)
4767 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4768 /* The linker may expand the call to a longer sequence which
4769 uses $at, so we must break rather than return. */
4794 /* Itbl support may require additional care here. */
4799 /* Itbl support may require additional care here. */
4804 /* Itbl support may require additional care here. */
4809 /* Itbl support may require additional care here. */
4821 if (mips_arch
== CPU_R4650
)
4823 as_bad (_("opcode not supported on this processor"));
4827 /* Itbl support may require additional care here. */
4832 /* Itbl support may require additional care here. */
4837 /* Itbl support may require additional care here. */
4857 if (breg
== treg
|| coproc
|| lr
)
4879 /* Itbl support may require additional care here. */
4884 /* Itbl support may require additional care here. */
4889 /* Itbl support may require additional care here. */
4894 /* Itbl support may require additional care here. */
4910 if (mips_arch
== CPU_R4650
)
4912 as_bad (_("opcode not supported on this processor"));
4917 /* Itbl support may require additional care here. */
4921 /* Itbl support may require additional care here. */
4926 /* Itbl support may require additional care here. */
4938 /* Itbl support may require additional care here. */
4939 if (mask
== M_LWC1_AB
4940 || mask
== M_SWC1_AB
4941 || mask
== M_LDC1_AB
4942 || mask
== M_SDC1_AB
4951 if (offset_expr
.X_op
!= O_constant
4952 && offset_expr
.X_op
!= O_symbol
)
4954 as_bad (_("expression too complex"));
4955 offset_expr
.X_op
= O_constant
;
4958 /* A constant expression in PIC code can be handled just as it
4959 is in non PIC code. */
4960 if (mips_pic
== NO_PIC
4961 || offset_expr
.X_op
== O_constant
)
4963 /* If this is a reference to a GP relative symbol, and there
4964 is no base register, we want
4965 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4966 Otherwise, if there is no base register, we want
4967 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4968 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4969 If we have a constant, we need two instructions anyhow,
4970 so we always use the latter form.
4972 If we have a base register, and this is a reference to a
4973 GP relative symbol, we want
4974 addu $tempreg,$breg,$gp
4975 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4977 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4978 addu $tempreg,$tempreg,$breg
4979 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4980 With a constant we always use the latter case. */
4983 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
4984 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4989 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4990 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4991 p
= frag_var (rs_machine_dependent
, 8, 0,
4992 RELAX_ENCODE (4, 8, 0, 4, 0,
4993 (mips_opts
.warn_about_macros
4995 && mips_opts
.noat
))),
4996 offset_expr
.X_add_symbol
, (offsetT
) 0,
5000 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5003 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5004 (int) BFD_RELOC_LO16
, tempreg
);
5008 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5009 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5015 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5016 "d,v,t", tempreg
, breg
, GP
);
5017 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5018 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5019 p
= frag_var (rs_machine_dependent
, 12, 0,
5020 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5021 offset_expr
.X_add_symbol
, (offsetT
) 0,
5024 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5027 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5028 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5029 "d,v,t", tempreg
, tempreg
, breg
);
5032 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5033 (int) BFD_RELOC_LO16
, tempreg
);
5036 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5038 /* If this is a reference to an external symbol, we want
5039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5041 <op> $treg,0($tempreg)
5043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5045 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5046 <op> $treg,0($tempreg)
5047 If there is a base register, we add it to $tempreg before
5048 the <op>. If there is a constant, we stick it in the
5049 <op> instruction. We don't handle constants larger than
5050 16 bits, because we have no way to load the upper 16 bits
5051 (actually, we could handle them for the subset of cases
5052 in which we are not using $at). */
5053 assert (offset_expr
.X_op
== O_symbol
);
5054 expr1
.X_add_number
= offset_expr
.X_add_number
;
5055 offset_expr
.X_add_number
= 0;
5056 if (expr1
.X_add_number
< -0x8000
5057 || expr1
.X_add_number
>= 0x8000)
5058 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5060 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5061 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5062 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5063 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5064 p
= frag_var (rs_machine_dependent
, 4, 0,
5065 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5066 offset_expr
.X_add_symbol
, (offsetT
) 0,
5068 macro_build (p
, &icnt
, &offset_expr
,
5069 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5070 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5072 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5073 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5074 "d,v,t", tempreg
, tempreg
, breg
);
5075 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5076 (int) BFD_RELOC_LO16
, tempreg
);
5078 else if (mips_pic
== SVR4_PIC
)
5082 /* If this is a reference to an external symbol, we want
5083 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5084 addu $tempreg,$tempreg,$gp
5085 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5086 <op> $treg,0($tempreg)
5088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5090 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5091 <op> $treg,0($tempreg)
5092 If there is a base register, we add it to $tempreg before
5093 the <op>. If there is a constant, we stick it in the
5094 <op> instruction. We don't handle constants larger than
5095 16 bits, because we have no way to load the upper 16 bits
5096 (actually, we could handle them for the subset of cases
5097 in which we are not using $at). */
5098 assert (offset_expr
.X_op
== O_symbol
);
5099 expr1
.X_add_number
= offset_expr
.X_add_number
;
5100 offset_expr
.X_add_number
= 0;
5101 if (expr1
.X_add_number
< -0x8000
5102 || expr1
.X_add_number
>= 0x8000)
5103 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5104 if (reg_needs_delay (GP
))
5109 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5110 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5111 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5112 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5113 "d,v,t", tempreg
, tempreg
, GP
);
5114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5115 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5116 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5118 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5119 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5120 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5123 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5126 macro_build (p
, &icnt
, &offset_expr
,
5127 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5128 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5130 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5132 macro_build (p
, &icnt
, &offset_expr
,
5133 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5134 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5136 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5137 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5138 "d,v,t", tempreg
, tempreg
, breg
);
5139 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5140 (int) BFD_RELOC_LO16
, tempreg
);
5142 else if (mips_pic
== EMBEDDED_PIC
)
5144 /* If there is no base register, we want
5145 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5146 If there is a base register, we want
5147 addu $tempreg,$breg,$gp
5148 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5150 assert (offset_expr
.X_op
== O_symbol
);
5153 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5154 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5159 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5160 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5161 "d,v,t", tempreg
, breg
, GP
);
5162 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5163 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5176 load_register (&icnt
, treg
, &imm_expr
, 0);
5180 load_register (&icnt
, treg
, &imm_expr
, 1);
5184 if (imm_expr
.X_op
== O_constant
)
5186 load_register (&icnt
, AT
, &imm_expr
, 0);
5187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5188 "mtc1", "t,G", AT
, treg
);
5193 assert (offset_expr
.X_op
== O_symbol
5194 && strcmp (segment_name (S_GET_SEGMENT
5195 (offset_expr
.X_add_symbol
)),
5197 && offset_expr
.X_add_number
== 0);
5198 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5199 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5204 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5205 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5206 order 32 bits of the value and the low order 32 bits are either
5207 zero or in OFFSET_EXPR. */
5208 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5210 if (HAVE_64BIT_GPRS
)
5211 load_register (&icnt
, treg
, &imm_expr
, 1);
5216 if (target_big_endian
)
5228 load_register (&icnt
, hreg
, &imm_expr
, 0);
5231 if (offset_expr
.X_op
== O_absent
)
5232 move_register (&icnt
, lreg
, 0);
5235 assert (offset_expr
.X_op
== O_constant
);
5236 load_register (&icnt
, lreg
, &offset_expr
, 0);
5243 /* We know that sym is in the .rdata section. First we get the
5244 upper 16 bits of the address. */
5245 if (mips_pic
== NO_PIC
)
5247 /* FIXME: This won't work for a 64 bit address. */
5248 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5250 else if (mips_pic
== SVR4_PIC
)
5252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5253 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5254 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5256 else if (mips_pic
== EMBEDDED_PIC
)
5258 /* For embedded PIC we pick up the entire address off $gp in
5259 a single instruction. */
5260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5261 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5262 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5263 offset_expr
.X_op
= O_constant
;
5264 offset_expr
.X_add_number
= 0;
5269 /* Now we load the register(s). */
5270 if (HAVE_64BIT_GPRS
)
5271 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5272 treg
, (int) BFD_RELOC_LO16
, AT
);
5275 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5276 treg
, (int) BFD_RELOC_LO16
, AT
);
5279 /* FIXME: How in the world do we deal with the possible
5281 offset_expr
.X_add_number
+= 4;
5282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5283 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5287 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5288 does not become a variant frag. */
5289 frag_wane (frag_now
);
5295 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5296 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5297 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5298 the value and the low order 32 bits are either zero or in
5300 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5302 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5303 if (HAVE_64BIT_FPRS
)
5305 assert (HAVE_64BIT_GPRS
);
5306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5307 "dmtc1", "t,S", AT
, treg
);
5311 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5312 "mtc1", "t,G", AT
, treg
+ 1);
5313 if (offset_expr
.X_op
== O_absent
)
5314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5315 "mtc1", "t,G", 0, treg
);
5318 assert (offset_expr
.X_op
== O_constant
);
5319 load_register (&icnt
, AT
, &offset_expr
, 0);
5320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5321 "mtc1", "t,G", AT
, treg
);
5327 assert (offset_expr
.X_op
== O_symbol
5328 && offset_expr
.X_add_number
== 0);
5329 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5330 if (strcmp (s
, ".lit8") == 0)
5332 if (mips_opts
.isa
!= ISA_MIPS1
)
5334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5335 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5339 r
= BFD_RELOC_MIPS_LITERAL
;
5344 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5345 if (mips_pic
== SVR4_PIC
)
5346 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5347 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5348 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5351 /* FIXME: This won't work for a 64 bit address. */
5352 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5355 if (mips_opts
.isa
!= ISA_MIPS1
)
5357 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5358 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5360 /* To avoid confusion in tc_gen_reloc, we must ensure
5361 that this does not become a variant frag. */
5362 frag_wane (frag_now
);
5373 if (mips_arch
== CPU_R4650
)
5375 as_bad (_("opcode not supported on this processor"));
5378 /* Even on a big endian machine $fn comes before $fn+1. We have
5379 to adjust when loading from memory. */
5382 assert (mips_opts
.isa
== ISA_MIPS1
);
5383 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5384 target_big_endian
? treg
+ 1 : treg
,
5386 /* FIXME: A possible overflow which I don't know how to deal
5388 offset_expr
.X_add_number
+= 4;
5389 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5390 target_big_endian
? treg
: treg
+ 1,
5393 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5394 does not become a variant frag. */
5395 frag_wane (frag_now
);
5404 * The MIPS assembler seems to check for X_add_number not
5405 * being double aligned and generating:
5408 * addiu at,at,%lo(foo+1)
5411 * But, the resulting address is the same after relocation so why
5412 * generate the extra instruction?
5414 if (mips_arch
== CPU_R4650
)
5416 as_bad (_("opcode not supported on this processor"));
5419 /* Itbl support may require additional care here. */
5421 if (mips_opts
.isa
!= ISA_MIPS1
)
5432 if (mips_arch
== CPU_R4650
)
5434 as_bad (_("opcode not supported on this processor"));
5438 if (mips_opts
.isa
!= ISA_MIPS1
)
5446 /* Itbl support may require additional care here. */
5451 if (HAVE_64BIT_GPRS
)
5462 if (HAVE_64BIT_GPRS
)
5472 if (offset_expr
.X_op
!= O_symbol
5473 && offset_expr
.X_op
!= O_constant
)
5475 as_bad (_("expression too complex"));
5476 offset_expr
.X_op
= O_constant
;
5479 /* Even on a big endian machine $fn comes before $fn+1. We have
5480 to adjust when loading from memory. We set coproc if we must
5481 load $fn+1 first. */
5482 /* Itbl support may require additional care here. */
5483 if (! target_big_endian
)
5486 if (mips_pic
== NO_PIC
5487 || offset_expr
.X_op
== O_constant
)
5489 /* If this is a reference to a GP relative symbol, we want
5490 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5491 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5492 If we have a base register, we use this
5494 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5495 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5496 If this is not a GP relative symbol, we want
5497 lui $at,<sym> (BFD_RELOC_HI16_S)
5498 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5499 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5500 If there is a base register, we add it to $at after the
5501 lui instruction. If there is a constant, we always use
5503 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5504 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5523 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5524 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5525 "d,v,t", AT
, breg
, GP
);
5531 /* Itbl support may require additional care here. */
5532 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5533 coproc
? treg
+ 1 : treg
,
5534 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5535 offset_expr
.X_add_number
+= 4;
5537 /* Set mips_optimize to 2 to avoid inserting an
5539 hold_mips_optimize
= mips_optimize
;
5541 /* Itbl support may require additional care here. */
5542 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5543 coproc
? treg
: treg
+ 1,
5544 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5545 mips_optimize
= hold_mips_optimize
;
5547 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5548 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5549 used_at
&& mips_opts
.noat
),
5550 offset_expr
.X_add_symbol
, (offsetT
) 0,
5553 /* We just generated two relocs. When tc_gen_reloc
5554 handles this case, it will skip the first reloc and
5555 handle the second. The second reloc already has an
5556 extra addend of 4, which we added above. We must
5557 subtract it out, and then subtract another 4 to make
5558 the first reloc come out right. The second reloc
5559 will come out right because we are going to add 4 to
5560 offset_expr when we build its instruction below.
5562 If we have a symbol, then we don't want to include
5563 the offset, because it will wind up being included
5564 when we generate the reloc. */
5566 if (offset_expr
.X_op
== O_constant
)
5567 offset_expr
.X_add_number
-= 8;
5570 offset_expr
.X_add_number
= -4;
5571 offset_expr
.X_op
= O_constant
;
5574 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5579 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5580 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5581 "d,v,t", AT
, breg
, AT
);
5585 /* Itbl support may require additional care here. */
5586 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5587 coproc
? treg
+ 1 : treg
,
5588 (int) BFD_RELOC_LO16
, AT
);
5591 /* FIXME: How do we handle overflow here? */
5592 offset_expr
.X_add_number
+= 4;
5593 /* Itbl support may require additional care here. */
5594 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5595 coproc
? treg
: treg
+ 1,
5596 (int) BFD_RELOC_LO16
, AT
);
5598 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5602 /* If this is a reference to an external symbol, we want
5603 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5608 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5610 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5611 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5612 If there is a base register we add it to $at before the
5613 lwc1 instructions. If there is a constant we include it
5614 in the lwc1 instructions. */
5616 expr1
.X_add_number
= offset_expr
.X_add_number
;
5617 offset_expr
.X_add_number
= 0;
5618 if (expr1
.X_add_number
< -0x8000
5619 || expr1
.X_add_number
>= 0x8000 - 4)
5620 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5625 frag_grow (24 + off
);
5626 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5627 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5628 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5629 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5632 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5633 "d,v,t", AT
, breg
, AT
);
5634 /* Itbl support may require additional care here. */
5635 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5636 coproc
? treg
+ 1 : treg
,
5637 (int) BFD_RELOC_LO16
, AT
);
5638 expr1
.X_add_number
+= 4;
5640 /* Set mips_optimize to 2 to avoid inserting an undesired
5642 hold_mips_optimize
= mips_optimize
;
5644 /* Itbl support may require additional care here. */
5645 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5646 coproc
? treg
: treg
+ 1,
5647 (int) BFD_RELOC_LO16
, AT
);
5648 mips_optimize
= hold_mips_optimize
;
5650 (void) frag_var (rs_machine_dependent
, 0, 0,
5651 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5652 offset_expr
.X_add_symbol
, (offsetT
) 0,
5655 else if (mips_pic
== SVR4_PIC
)
5659 /* If this is a reference to an external symbol, we want
5660 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5662 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5667 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5669 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5670 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5671 If there is a base register we add it to $at before the
5672 lwc1 instructions. If there is a constant we include it
5673 in the lwc1 instructions. */
5675 expr1
.X_add_number
= offset_expr
.X_add_number
;
5676 offset_expr
.X_add_number
= 0;
5677 if (expr1
.X_add_number
< -0x8000
5678 || expr1
.X_add_number
>= 0x8000 - 4)
5679 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5680 if (reg_needs_delay (GP
))
5689 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5690 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5692 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5693 "d,v,t", AT
, AT
, GP
);
5694 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5695 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5696 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5697 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5700 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5701 "d,v,t", AT
, breg
, AT
);
5702 /* Itbl support may require additional care here. */
5703 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5704 coproc
? treg
+ 1 : treg
,
5705 (int) BFD_RELOC_LO16
, AT
);
5706 expr1
.X_add_number
+= 4;
5708 /* Set mips_optimize to 2 to avoid inserting an undesired
5710 hold_mips_optimize
= mips_optimize
;
5712 /* Itbl support may require additional care here. */
5713 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5714 coproc
? treg
: treg
+ 1,
5715 (int) BFD_RELOC_LO16
, AT
);
5716 mips_optimize
= hold_mips_optimize
;
5717 expr1
.X_add_number
-= 4;
5719 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5720 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5721 8 + gpdel
+ off
, 1, 0),
5722 offset_expr
.X_add_symbol
, (offsetT
) 0,
5726 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5729 macro_build (p
, &icnt
, &offset_expr
,
5730 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5731 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5733 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5738 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5739 "d,v,t", AT
, breg
, AT
);
5742 /* Itbl support may require additional care here. */
5743 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5744 coproc
? treg
+ 1 : treg
,
5745 (int) BFD_RELOC_LO16
, AT
);
5747 expr1
.X_add_number
+= 4;
5749 /* Set mips_optimize to 2 to avoid inserting an undesired
5751 hold_mips_optimize
= mips_optimize
;
5753 /* Itbl support may require additional care here. */
5754 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5755 coproc
? treg
: treg
+ 1,
5756 (int) BFD_RELOC_LO16
, AT
);
5757 mips_optimize
= hold_mips_optimize
;
5759 else if (mips_pic
== EMBEDDED_PIC
)
5761 /* If there is no base register, we use
5762 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5763 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5764 If we have a base register, we use
5766 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5767 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5777 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5778 "d,v,t", AT
, breg
, GP
);
5783 /* Itbl support may require additional care here. */
5784 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5785 coproc
? treg
+ 1 : treg
,
5786 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5787 offset_expr
.X_add_number
+= 4;
5788 /* Itbl support may require additional care here. */
5789 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5790 coproc
? treg
: treg
+ 1,
5791 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5807 assert (HAVE_32BIT_ADDRESSES
);
5808 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5809 (int) BFD_RELOC_LO16
, breg
);
5810 offset_expr
.X_add_number
+= 4;
5811 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5812 (int) BFD_RELOC_LO16
, breg
);
5815 /* New code added to support COPZ instructions.
5816 This code builds table entries out of the macros in mip_opcodes.
5817 R4000 uses interlocks to handle coproc delays.
5818 Other chips (like the R3000) require nops to be inserted for delays.
5820 FIXME: Currently, we require that the user handle delays.
5821 In order to fill delay slots for non-interlocked chips,
5822 we must have a way to specify delays based on the coprocessor.
5823 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5824 What are the side-effects of the cop instruction?
5825 What cache support might we have and what are its effects?
5826 Both coprocessor & memory require delays. how long???
5827 What registers are read/set/modified?
5829 If an itbl is provided to interpret cop instructions,
5830 this knowledge can be encoded in the itbl spec. */
5844 /* For now we just do C (same as Cz). The parameter will be
5845 stored in insn_opcode by mips_ip. */
5846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5851 move_register (&icnt
, dreg
, sreg
);
5854 #ifdef LOSING_COMPILER
5856 /* Try and see if this is a new itbl instruction.
5857 This code builds table entries out of the macros in mip_opcodes.
5858 FIXME: For now we just assemble the expression and pass it's
5859 value along as a 32-bit immediate.
5860 We may want to have the assembler assemble this value,
5861 so that we gain the assembler's knowledge of delay slots,
5863 Would it be more efficient to use mask (id) here? */
5864 if (itbl_have_entries
5865 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5867 s
= ip
->insn_mo
->name
;
5869 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5870 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5877 as_warn (_("Macro used $at after \".set noat\""));
5882 struct mips_cl_insn
*ip
;
5884 register int treg
, sreg
, dreg
, breg
;
5900 bfd_reloc_code_real_type r
;
5903 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5904 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5905 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5906 mask
= ip
->insn_mo
->mask
;
5908 expr1
.X_op
= O_constant
;
5909 expr1
.X_op_symbol
= NULL
;
5910 expr1
.X_add_symbol
= NULL
;
5911 expr1
.X_add_number
= 1;
5915 #endif /* LOSING_COMPILER */
5920 macro_build ((char *) NULL
, &icnt
, NULL
,
5921 dbl
? "dmultu" : "multu",
5923 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5929 /* The MIPS assembler some times generates shifts and adds. I'm
5930 not trying to be that fancy. GCC should do this for us
5932 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5933 macro_build ((char *) NULL
, &icnt
, NULL
,
5934 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
5935 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5948 mips_emit_delays (true);
5949 ++mips_opts
.noreorder
;
5950 mips_any_noreorder
= 1;
5952 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5953 macro_build ((char *) NULL
, &icnt
, NULL
,
5954 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
5955 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5956 macro_build ((char *) NULL
, &icnt
, NULL
,
5957 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
5958 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5960 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5963 expr1
.X_add_number
= 8;
5964 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5965 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5966 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5968 --mips_opts
.noreorder
;
5969 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5982 mips_emit_delays (true);
5983 ++mips_opts
.noreorder
;
5984 mips_any_noreorder
= 1;
5986 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5987 macro_build ((char *) NULL
, &icnt
, NULL
,
5988 dbl
? "dmultu" : "multu",
5989 "s,t", sreg
, imm
? AT
: treg
);
5990 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5991 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5996 expr1
.X_add_number
= 8;
5997 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5998 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5999 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6001 --mips_opts
.noreorder
;
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6006 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6007 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6013 if (imm_expr
.X_op
!= O_constant
)
6014 as_bad (_("rotate count too large"));
6015 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6016 (int) (imm_expr
.X_add_number
& 0x1f));
6017 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6018 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6025 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6031 if (imm_expr
.X_op
!= O_constant
)
6032 as_bad (_("rotate count too large"));
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6034 (int) (imm_expr
.X_add_number
& 0x1f));
6035 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6036 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6037 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6041 if (mips_arch
== CPU_R4650
)
6043 as_bad (_("opcode not supported on this processor"));
6046 assert (mips_opts
.isa
== ISA_MIPS1
);
6047 /* Even on a big endian machine $fn comes before $fn+1. We have
6048 to adjust when storing to memory. */
6049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6050 target_big_endian
? treg
+ 1 : treg
,
6051 (int) BFD_RELOC_LO16
, breg
);
6052 offset_expr
.X_add_number
+= 4;
6053 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6054 target_big_endian
? treg
: treg
+ 1,
6055 (int) BFD_RELOC_LO16
, breg
);
6060 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6061 treg
, (int) BFD_RELOC_LO16
);
6063 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6064 sreg
, (int) BFD_RELOC_LO16
);
6067 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6069 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6070 dreg
, (int) BFD_RELOC_LO16
);
6075 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6077 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6078 sreg
, (int) BFD_RELOC_LO16
);
6083 as_warn (_("Instruction %s: result is always false"),
6085 move_register (&icnt
, dreg
, 0);
6088 if (imm_expr
.X_op
== O_constant
6089 && imm_expr
.X_add_number
>= 0
6090 && imm_expr
.X_add_number
< 0x10000)
6092 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6093 sreg
, (int) BFD_RELOC_LO16
);
6096 else if (imm_expr
.X_op
== O_constant
6097 && imm_expr
.X_add_number
> -0x8000
6098 && imm_expr
.X_add_number
< 0)
6100 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6101 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6102 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6103 "t,r,j", dreg
, sreg
,
6104 (int) BFD_RELOC_LO16
);
6109 load_register (&icnt
, AT
, &imm_expr
, 0);
6110 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6114 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6115 (int) BFD_RELOC_LO16
);
6120 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6126 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6127 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6128 (int) BFD_RELOC_LO16
);
6131 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6133 if (imm_expr
.X_op
== O_constant
6134 && imm_expr
.X_add_number
>= -0x8000
6135 && imm_expr
.X_add_number
< 0x8000)
6137 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6138 mask
== M_SGE_I
? "slti" : "sltiu",
6139 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6144 load_register (&icnt
, AT
, &imm_expr
, 0);
6145 macro_build ((char *) NULL
, &icnt
, NULL
,
6146 mask
== M_SGE_I
? "slt" : "sltu",
6147 "d,v,t", dreg
, sreg
, AT
);
6150 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6151 (int) BFD_RELOC_LO16
);
6156 case M_SGT
: /* sreg > treg <==> treg < sreg */
6162 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6165 case M_SGT_I
: /* sreg > I <==> I < sreg */
6171 load_register (&icnt
, AT
, &imm_expr
, 0);
6172 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6175 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6181 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6182 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6183 (int) BFD_RELOC_LO16
);
6186 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6192 load_register (&icnt
, AT
, &imm_expr
, 0);
6193 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6194 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6195 (int) BFD_RELOC_LO16
);
6199 if (imm_expr
.X_op
== O_constant
6200 && imm_expr
.X_add_number
>= -0x8000
6201 && imm_expr
.X_add_number
< 0x8000)
6203 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6204 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6207 load_register (&icnt
, AT
, &imm_expr
, 0);
6208 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6212 if (imm_expr
.X_op
== O_constant
6213 && imm_expr
.X_add_number
>= -0x8000
6214 && imm_expr
.X_add_number
< 0x8000)
6216 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6217 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6220 load_register (&icnt
, AT
, &imm_expr
, 0);
6221 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6227 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6230 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6234 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6236 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6242 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6244 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6250 as_warn (_("Instruction %s: result is always true"),
6252 macro_build ((char *) NULL
, &icnt
, &expr1
,
6253 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6254 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6257 if (imm_expr
.X_op
== O_constant
6258 && imm_expr
.X_add_number
>= 0
6259 && imm_expr
.X_add_number
< 0x10000)
6261 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6262 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6265 else if (imm_expr
.X_op
== O_constant
6266 && imm_expr
.X_add_number
> -0x8000
6267 && imm_expr
.X_add_number
< 0)
6269 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6270 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6271 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6272 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6277 load_register (&icnt
, AT
, &imm_expr
, 0);
6278 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6282 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6290 if (imm_expr
.X_op
== O_constant
6291 && imm_expr
.X_add_number
> -0x8000
6292 && imm_expr
.X_add_number
<= 0x8000)
6294 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6295 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6296 dbl
? "daddi" : "addi",
6297 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6300 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6301 macro_build ((char *) NULL
, &icnt
, NULL
,
6302 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6308 if (imm_expr
.X_op
== O_constant
6309 && imm_expr
.X_add_number
> -0x8000
6310 && imm_expr
.X_add_number
<= 0x8000)
6312 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6313 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6314 dbl
? "daddiu" : "addiu",
6315 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6318 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6319 macro_build ((char *) NULL
, &icnt
, NULL
,
6320 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6341 load_register (&icnt
, AT
, &imm_expr
, 0);
6342 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6347 assert (mips_opts
.isa
== ISA_MIPS1
);
6348 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6349 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6352 * Is the double cfc1 instruction a bug in the mips assembler;
6353 * or is there a reason for it?
6355 mips_emit_delays (true);
6356 ++mips_opts
.noreorder
;
6357 mips_any_noreorder
= 1;
6358 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6359 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6360 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6361 expr1
.X_add_number
= 3;
6362 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6363 (int) BFD_RELOC_LO16
);
6364 expr1
.X_add_number
= 2;
6365 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6366 (int) BFD_RELOC_LO16
);
6367 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6368 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6369 macro_build ((char *) NULL
, &icnt
, NULL
,
6370 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6371 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6372 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6373 --mips_opts
.noreorder
;
6382 if (offset_expr
.X_add_number
>= 0x7fff)
6383 as_bad (_("operand overflow"));
6384 /* avoid load delay */
6385 if (! target_big_endian
)
6386 offset_expr
.X_add_number
+= 1;
6387 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6388 (int) BFD_RELOC_LO16
, breg
);
6389 if (! target_big_endian
)
6390 offset_expr
.X_add_number
-= 1;
6392 offset_expr
.X_add_number
+= 1;
6393 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6394 (int) BFD_RELOC_LO16
, breg
);
6395 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6396 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6409 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6410 as_bad (_("operand overflow"));
6411 if (! target_big_endian
)
6412 offset_expr
.X_add_number
+= off
;
6413 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6414 (int) BFD_RELOC_LO16
, breg
);
6415 if (! target_big_endian
)
6416 offset_expr
.X_add_number
-= off
;
6418 offset_expr
.X_add_number
+= off
;
6419 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6420 (int) BFD_RELOC_LO16
, breg
);
6433 load_address (&icnt
, AT
, &offset_expr
);
6435 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6436 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6437 "d,v,t", AT
, AT
, breg
);
6438 if (! target_big_endian
)
6439 expr1
.X_add_number
= off
;
6441 expr1
.X_add_number
= 0;
6442 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6443 (int) BFD_RELOC_LO16
, AT
);
6444 if (! target_big_endian
)
6445 expr1
.X_add_number
= 0;
6447 expr1
.X_add_number
= off
;
6448 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6449 (int) BFD_RELOC_LO16
, AT
);
6454 load_address (&icnt
, AT
, &offset_expr
);
6456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6457 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6458 "d,v,t", AT
, AT
, breg
);
6459 if (target_big_endian
)
6460 expr1
.X_add_number
= 0;
6461 macro_build ((char *) NULL
, &icnt
, &expr1
,
6462 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6463 (int) BFD_RELOC_LO16
, AT
);
6464 if (target_big_endian
)
6465 expr1
.X_add_number
= 1;
6467 expr1
.X_add_number
= 0;
6468 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6469 (int) BFD_RELOC_LO16
, AT
);
6470 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6472 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6477 if (offset_expr
.X_add_number
>= 0x7fff)
6478 as_bad (_("operand overflow"));
6479 if (target_big_endian
)
6480 offset_expr
.X_add_number
+= 1;
6481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6482 (int) BFD_RELOC_LO16
, breg
);
6483 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6484 if (target_big_endian
)
6485 offset_expr
.X_add_number
-= 1;
6487 offset_expr
.X_add_number
+= 1;
6488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6489 (int) BFD_RELOC_LO16
, breg
);
6502 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6503 as_bad (_("operand overflow"));
6504 if (! target_big_endian
)
6505 offset_expr
.X_add_number
+= off
;
6506 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6507 (int) BFD_RELOC_LO16
, breg
);
6508 if (! target_big_endian
)
6509 offset_expr
.X_add_number
-= off
;
6511 offset_expr
.X_add_number
+= off
;
6512 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6513 (int) BFD_RELOC_LO16
, breg
);
6526 load_address (&icnt
, AT
, &offset_expr
);
6528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6529 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6530 "d,v,t", AT
, AT
, breg
);
6531 if (! target_big_endian
)
6532 expr1
.X_add_number
= off
;
6534 expr1
.X_add_number
= 0;
6535 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6536 (int) BFD_RELOC_LO16
, AT
);
6537 if (! target_big_endian
)
6538 expr1
.X_add_number
= 0;
6540 expr1
.X_add_number
= off
;
6541 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6542 (int) BFD_RELOC_LO16
, AT
);
6546 load_address (&icnt
, AT
, &offset_expr
);
6548 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6549 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6550 "d,v,t", AT
, AT
, breg
);
6551 if (! target_big_endian
)
6552 expr1
.X_add_number
= 0;
6553 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, AT
);
6555 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6557 if (! target_big_endian
)
6558 expr1
.X_add_number
= 1;
6560 expr1
.X_add_number
= 0;
6561 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6562 (int) BFD_RELOC_LO16
, AT
);
6563 if (! target_big_endian
)
6564 expr1
.X_add_number
= 0;
6566 expr1
.X_add_number
= 1;
6567 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6568 (int) BFD_RELOC_LO16
, AT
);
6569 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6571 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6576 /* FIXME: Check if this is one of the itbl macros, since they
6577 are added dynamically. */
6578 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6582 as_warn (_("Macro used $at after \".set noat\""));
6585 /* Implement macros in mips16 mode. */
6589 struct mips_cl_insn
*ip
;
6592 int xreg
, yreg
, zreg
, tmp
;
6596 const char *s
, *s2
, *s3
;
6598 mask
= ip
->insn_mo
->mask
;
6600 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6601 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6602 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6606 expr1
.X_op
= O_constant
;
6607 expr1
.X_op_symbol
= NULL
;
6608 expr1
.X_add_symbol
= NULL
;
6609 expr1
.X_add_number
= 1;
6628 mips_emit_delays (true);
6629 ++mips_opts
.noreorder
;
6630 mips_any_noreorder
= 1;
6631 macro_build ((char *) NULL
, &icnt
, NULL
,
6632 dbl
? "ddiv" : "div",
6633 "0,x,y", xreg
, yreg
);
6634 expr1
.X_add_number
= 2;
6635 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6636 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6638 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6639 since that causes an overflow. We should do that as well,
6640 but I don't see how to do the comparisons without a temporary
6642 --mips_opts
.noreorder
;
6643 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6662 mips_emit_delays (true);
6663 ++mips_opts
.noreorder
;
6664 mips_any_noreorder
= 1;
6665 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6666 expr1
.X_add_number
= 2;
6667 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6668 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6669 --mips_opts
.noreorder
;
6670 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6676 macro_build ((char *) NULL
, &icnt
, NULL
,
6677 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
6678 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6686 if (imm_expr
.X_op
!= O_constant
)
6687 as_bad (_("Unsupported large constant"));
6688 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6689 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6690 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
6694 if (imm_expr
.X_op
!= O_constant
)
6695 as_bad (_("Unsupported large constant"));
6696 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6697 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6702 if (imm_expr
.X_op
!= O_constant
)
6703 as_bad (_("Unsupported large constant"));
6704 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6705 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6728 goto do_reverse_branch
;
6732 goto do_reverse_branch
;
6744 goto do_reverse_branch
;
6755 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6784 goto do_addone_branch_i
;
6789 goto do_addone_branch_i
;
6804 goto do_addone_branch_i
;
6811 if (imm_expr
.X_op
!= O_constant
)
6812 as_bad (_("Unsupported large constant"));
6813 ++imm_expr
.X_add_number
;
6816 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6817 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6821 expr1
.X_add_number
= 0;
6822 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6824 move_register (&icnt
, xreg
, yreg
);
6825 expr1
.X_add_number
= 2;
6826 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6828 "neg", "x,w", xreg
, xreg
);
6832 /* For consistency checking, verify that all bits are specified either
6833 by the match/mask part of the instruction definition, or by the
6836 validate_mips_insn (opc
)
6837 const struct mips_opcode
*opc
;
6839 const char *p
= opc
->args
;
6841 unsigned long used_bits
= opc
->mask
;
6843 if ((used_bits
& opc
->match
) != opc
->match
)
6845 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6846 opc
->name
, opc
->args
);
6849 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6856 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6857 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6859 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6860 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6861 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6862 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6864 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6865 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6867 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6869 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6870 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6871 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6872 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6873 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6874 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6875 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6876 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6877 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6878 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6879 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6881 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6882 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6883 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6884 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6886 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6887 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6888 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6889 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6890 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6891 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6892 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6893 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6894 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6897 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6898 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6899 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6901 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6902 c
, opc
->name
, opc
->args
);
6906 if (used_bits
!= 0xffffffff)
6908 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6909 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6915 /* This routine assembles an instruction into its binary format. As a
6916 side effect, it sets one of the global variables imm_reloc or
6917 offset_reloc to the type of relocation to do if one of the operands
6918 is an address expression. */
6923 struct mips_cl_insn
*ip
;
6928 struct mips_opcode
*insn
;
6931 unsigned int lastregno
= 0;
6934 int full_opcode_match
= 1;
6938 /* If the instruction contains a '.', we first try to match an instruction
6939 including the '.'. Then we try again without the '.'. */
6941 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6944 /* If we stopped on whitespace, then replace the whitespace with null for
6945 the call to hash_find. Save the character we replaced just in case we
6946 have to re-parse the instruction. */
6947 if (isspace ((unsigned char) *s
))
6953 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6955 /* If we didn't find the instruction in the opcode table, try again, but
6956 this time with just the instruction up to, but not including the
6960 /* Restore the character we overwrite above (if any). */
6964 /* Scan up to the first '.' or whitespace. */
6965 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
6968 /* If we did not find a '.', then we can quit now. */
6971 insn_error
= "unrecognized opcode";
6975 /* Lookup the instruction in the hash table. */
6977 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6979 insn_error
= "unrecognized opcode";
6983 full_opcode_match
= 0;
6991 assert (strcmp (insn
->name
, str
) == 0);
6993 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
6998 if (insn
->pinfo
!= INSN_MACRO
)
7000 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7006 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7007 && strcmp (insn
->name
, insn
[1].name
) == 0)
7016 static char buf
[100];
7018 _("opcode not supported on this processor: %s (%s)"),
7019 mips_cpu_to_str (mips_arch
),
7020 mips_isa_to_str (mips_opts
.isa
));
7031 ip
->insn_opcode
= insn
->match
;
7033 for (args
= insn
->args
;; ++args
)
7039 case '\0': /* end of args */
7052 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7056 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7060 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7064 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7070 /* Handle optional base register.
7071 Either the base register is omitted or
7072 we must have a left paren. */
7073 /* This is dependent on the next operand specifier
7074 is a base register specification. */
7075 assert (args
[1] == 'b' || args
[1] == '5'
7076 || args
[1] == '-' || args
[1] == '4');
7080 case ')': /* these must match exactly */
7085 case '<': /* must be at least one digit */
7087 * According to the manual, if the shift amount is greater
7088 * than 31 or less than 0 the the shift amount should be
7089 * mod 32. In reality the mips assembler issues an error.
7090 * We issue a warning and mask out all but the low 5 bits.
7092 my_getExpression (&imm_expr
, s
);
7093 check_absolute_expr (ip
, &imm_expr
);
7094 if ((unsigned long) imm_expr
.X_add_number
> 31)
7096 as_warn (_("Improper shift amount (%ld)"),
7097 (long) imm_expr
.X_add_number
);
7098 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7100 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7101 imm_expr
.X_op
= O_absent
;
7105 case '>': /* shift amount minus 32 */
7106 my_getExpression (&imm_expr
, s
);
7107 check_absolute_expr (ip
, &imm_expr
);
7108 if ((unsigned long) imm_expr
.X_add_number
< 32
7109 || (unsigned long) imm_expr
.X_add_number
> 63)
7111 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7112 imm_expr
.X_op
= O_absent
;
7116 case 'k': /* cache code */
7117 case 'h': /* prefx code */
7118 my_getExpression (&imm_expr
, s
);
7119 check_absolute_expr (ip
, &imm_expr
);
7120 if ((unsigned long) imm_expr
.X_add_number
> 31)
7122 as_warn (_("Invalid value for `%s' (%lu)"),
7124 (unsigned long) imm_expr
.X_add_number
);
7125 imm_expr
.X_add_number
&= 0x1f;
7128 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7130 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7131 imm_expr
.X_op
= O_absent
;
7135 case 'c': /* break code */
7136 my_getExpression (&imm_expr
, s
);
7137 check_absolute_expr (ip
, &imm_expr
);
7138 if ((unsigned) imm_expr
.X_add_number
> 1023)
7140 as_warn (_("Illegal break code (%ld)"),
7141 (long) imm_expr
.X_add_number
);
7142 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7144 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7145 imm_expr
.X_op
= O_absent
;
7149 case 'q': /* lower break code */
7150 my_getExpression (&imm_expr
, s
);
7151 check_absolute_expr (ip
, &imm_expr
);
7152 if ((unsigned) imm_expr
.X_add_number
> 1023)
7154 as_warn (_("Illegal lower break code (%ld)"),
7155 (long) imm_expr
.X_add_number
);
7156 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7158 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7159 imm_expr
.X_op
= O_absent
;
7163 case 'B': /* 20-bit syscall/break code. */
7164 my_getExpression (&imm_expr
, s
);
7165 check_absolute_expr (ip
, &imm_expr
);
7166 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7167 as_warn (_("Illegal 20-bit code (%ld)"),
7168 (long) imm_expr
.X_add_number
);
7169 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7170 imm_expr
.X_op
= O_absent
;
7174 case 'C': /* Coprocessor code */
7175 my_getExpression (&imm_expr
, s
);
7176 check_absolute_expr (ip
, &imm_expr
);
7177 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7179 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7180 (long) imm_expr
.X_add_number
);
7181 imm_expr
.X_add_number
&= ((1<<25) - 1);
7183 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7184 imm_expr
.X_op
= O_absent
;
7188 case 'J': /* 19-bit wait code. */
7189 my_getExpression (&imm_expr
, s
);
7190 check_absolute_expr (ip
, &imm_expr
);
7191 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7192 as_warn (_("Illegal 19-bit code (%ld)"),
7193 (long) imm_expr
.X_add_number
);
7194 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7195 imm_expr
.X_op
= O_absent
;
7199 case 'P': /* Performance register */
7200 my_getExpression (&imm_expr
, s
);
7201 check_absolute_expr (ip
, &imm_expr
);
7202 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7204 as_warn (_("Invalid performance register (%ld)"),
7205 (long) imm_expr
.X_add_number
);
7206 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7208 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7209 imm_expr
.X_op
= O_absent
;
7213 case 'b': /* base register */
7214 case 'd': /* destination register */
7215 case 's': /* source register */
7216 case 't': /* target register */
7217 case 'r': /* both target and source */
7218 case 'v': /* both dest and source */
7219 case 'w': /* both dest and target */
7220 case 'E': /* coprocessor target register */
7221 case 'G': /* coprocessor destination register */
7222 case 'x': /* ignore register name */
7223 case 'z': /* must be zero register */
7224 case 'U': /* destination register (clo/clz). */
7229 if (isdigit ((unsigned char) s
[1]))
7239 while (isdigit ((unsigned char) *s
));
7241 as_bad (_("Invalid register number (%d)"), regno
);
7243 else if (*args
== 'E' || *args
== 'G')
7247 if (s
[1] == 'f' && s
[2] == 'p')
7252 else if (s
[1] == 's' && s
[2] == 'p')
7257 else if (s
[1] == 'g' && s
[2] == 'p')
7262 else if (s
[1] == 'a' && s
[2] == 't')
7267 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7272 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7277 else if (itbl_have_entries
)
7282 p
= s
+ 1; /* advance past '$' */
7283 n
= itbl_get_field (&p
); /* n is name */
7285 /* See if this is a register defined in an
7287 if (itbl_get_reg_val (n
, &r
))
7289 /* Get_field advances to the start of
7290 the next field, so we need to back
7291 rack to the end of the last field. */
7295 s
= strchr (s
, '\0');
7308 as_warn (_("Used $at without \".set noat\""));
7314 if (c
== 'r' || c
== 'v' || c
== 'w')
7321 /* 'z' only matches $0. */
7322 if (c
== 'z' && regno
!= 0)
7325 /* Now that we have assembled one operand, we use the args string
7326 * to figure out where it goes in the instruction. */
7333 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7337 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7340 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7341 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7346 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7349 /* This case exists because on the r3000 trunc
7350 expands into a macro which requires a gp
7351 register. On the r6000 or r4000 it is
7352 assembled into a single instruction which
7353 ignores the register. Thus the insn version
7354 is MIPS_ISA2 and uses 'x', and the macro
7355 version is MIPS_ISA1 and uses 't'. */
7358 /* This case is for the div instruction, which
7359 acts differently if the destination argument
7360 is $0. This only matches $0, and is checked
7361 outside the switch. */
7364 /* Itbl operand; not yet implemented. FIXME ?? */
7366 /* What about all other operands like 'i', which
7367 can be specified in the opcode table? */
7377 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7380 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7385 case 'D': /* floating point destination register */
7386 case 'S': /* floating point source register */
7387 case 'T': /* floating point target register */
7388 case 'R': /* floating point source register */
7392 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7402 while (isdigit ((unsigned char) *s
));
7405 as_bad (_("Invalid float register number (%d)"), regno
);
7407 if ((regno
& 1) != 0
7409 && ! (strcmp (str
, "mtc1") == 0
7410 || strcmp (str
, "mfc1") == 0
7411 || strcmp (str
, "lwc1") == 0
7412 || strcmp (str
, "swc1") == 0
7413 || strcmp (str
, "l.s") == 0
7414 || strcmp (str
, "s.s") == 0))
7415 as_warn (_("Float register should be even, was %d"),
7423 if (c
== 'V' || c
== 'W')
7433 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7437 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7441 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7444 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
7454 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7457 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7463 my_getExpression (&imm_expr
, s
);
7464 if (imm_expr
.X_op
!= O_big
7465 && imm_expr
.X_op
!= O_constant
)
7466 insn_error
= _("absolute expression required");
7471 my_getExpression (&offset_expr
, s
);
7472 imm_reloc
= BFD_RELOC_32
;
7485 unsigned char temp
[8];
7487 unsigned int length
;
7492 /* These only appear as the last operand in an
7493 instruction, and every instruction that accepts
7494 them in any variant accepts them in all variants.
7495 This means we don't have to worry about backing out
7496 any changes if the instruction does not match.
7498 The difference between them is the size of the
7499 floating point constant and where it goes. For 'F'
7500 and 'L' the constant is 64 bits; for 'f' and 'l' it
7501 is 32 bits. Where the constant is placed is based
7502 on how the MIPS assembler does things:
7505 f -- immediate value
7508 The .lit4 and .lit8 sections are only used if
7509 permitted by the -G argument.
7511 When generating embedded PIC code, we use the
7512 .lit8 section but not the .lit4 section (we can do
7513 .lit4 inline easily; we need to put .lit8
7514 somewhere in the data segment, and using .lit8
7515 permits the linker to eventually combine identical
7518 The code below needs to know whether the target register
7519 is 32 or 64 bits wide. It relies on the fact 'f' and
7520 'F' are used with GPR-based instructions and 'l' and
7521 'L' are used with FPR-based instructions. */
7523 f64
= *args
== 'F' || *args
== 'L';
7524 using_gprs
= *args
== 'F' || *args
== 'f';
7526 save_in
= input_line_pointer
;
7527 input_line_pointer
= s
;
7528 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7530 s
= input_line_pointer
;
7531 input_line_pointer
= save_in
;
7532 if (err
!= NULL
&& *err
!= '\0')
7534 as_bad (_("Bad floating point constant: %s"), err
);
7535 memset (temp
, '\0', sizeof temp
);
7536 length
= f64
? 8 : 4;
7539 assert (length
== (unsigned) (f64
? 8 : 4));
7543 && (! USE_GLOBAL_POINTER_OPT
7544 || mips_pic
== EMBEDDED_PIC
7545 || g_switch_value
< 4
7546 || (temp
[0] == 0 && temp
[1] == 0)
7547 || (temp
[2] == 0 && temp
[3] == 0))))
7549 imm_expr
.X_op
= O_constant
;
7550 if (! target_big_endian
)
7551 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7553 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7556 && ! mips_disable_float_construction
7557 /* Constants can only be constructed in GPRs and
7558 copied to FPRs if the GPRs are at least as wide
7559 as the FPRs. Force the constant into memory if
7560 we are using 64-bit FPRs but the GPRs are only
7563 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
7564 && ((temp
[0] == 0 && temp
[1] == 0)
7565 || (temp
[2] == 0 && temp
[3] == 0))
7566 && ((temp
[4] == 0 && temp
[5] == 0)
7567 || (temp
[6] == 0 && temp
[7] == 0)))
7569 /* The value is simple enough to load with a couple of
7570 instructions. If using 32-bit registers, set
7571 imm_expr to the high order 32 bits and offset_expr to
7572 the low order 32 bits. Otherwise, set imm_expr to
7573 the entire 64 bit constant. */
7574 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
7576 imm_expr
.X_op
= O_constant
;
7577 offset_expr
.X_op
= O_constant
;
7578 if (! target_big_endian
)
7580 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7581 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7585 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7586 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7588 if (offset_expr
.X_add_number
== 0)
7589 offset_expr
.X_op
= O_absent
;
7591 else if (sizeof (imm_expr
.X_add_number
) > 4)
7593 imm_expr
.X_op
= O_constant
;
7594 if (! target_big_endian
)
7595 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7597 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7601 imm_expr
.X_op
= O_big
;
7602 imm_expr
.X_add_number
= 4;
7603 if (! target_big_endian
)
7605 generic_bignum
[0] = bfd_getl16 (temp
);
7606 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7607 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7608 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7612 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7613 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7614 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7615 generic_bignum
[3] = bfd_getb16 (temp
);
7621 const char *newname
;
7624 /* Switch to the right section. */
7626 subseg
= now_subseg
;
7629 default: /* unused default case avoids warnings. */
7631 newname
= RDATA_SECTION_NAME
;
7632 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7633 || mips_pic
== EMBEDDED_PIC
)
7637 if (mips_pic
== EMBEDDED_PIC
)
7640 newname
= RDATA_SECTION_NAME
;
7643 assert (!USE_GLOBAL_POINTER_OPT
7644 || g_switch_value
>= 4);
7648 new_seg
= subseg_new (newname
, (subsegT
) 0);
7649 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7650 bfd_set_section_flags (stdoutput
, new_seg
,
7655 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7656 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7657 && strcmp (TARGET_OS
, "elf") != 0)
7658 record_alignment (new_seg
, 4);
7660 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7662 as_bad (_("Can't use floating point insn in this section"));
7664 /* Set the argument to the current address in the
7666 offset_expr
.X_op
= O_symbol
;
7667 offset_expr
.X_add_symbol
=
7668 symbol_new ("L0\001", now_seg
,
7669 (valueT
) frag_now_fix (), frag_now
);
7670 offset_expr
.X_add_number
= 0;
7672 /* Put the floating point number into the section. */
7673 p
= frag_more ((int) length
);
7674 memcpy (p
, temp
, length
);
7676 /* Switch back to the original section. */
7677 subseg_set (seg
, subseg
);
7682 case 'i': /* 16 bit unsigned immediate */
7683 case 'j': /* 16 bit signed immediate */
7684 imm_reloc
= BFD_RELOC_LO16
;
7685 c
= my_getSmallExpression (&imm_expr
, s
);
7690 if (imm_expr
.X_op
== O_constant
)
7691 imm_expr
.X_add_number
=
7692 (imm_expr
.X_add_number
>> 16) & 0xffff;
7693 else if (c
== S_EX_HIGHEST
)
7694 imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
7695 else if (c
== S_EX_HIGHER
)
7696 imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
7697 else if (c
== S_EX_HI
)
7699 imm_reloc
= BFD_RELOC_HI16_S
;
7700 imm_unmatched_hi
= true;
7703 imm_reloc
= BFD_RELOC_HI16
;
7705 else if (imm_expr
.X_op
== O_constant
)
7706 imm_expr
.X_add_number
&= 0xffff;
7710 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
7711 || ((imm_expr
.X_add_number
< 0
7712 || imm_expr
.X_add_number
>= 0x10000)
7713 && imm_expr
.X_op
== O_constant
))
7715 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7716 !strcmp (insn
->name
, insn
[1].name
))
7718 if (imm_expr
.X_op
== O_constant
7719 || imm_expr
.X_op
== O_big
)
7720 as_bad (_("16 bit expression not in range 0..65535"));
7728 /* The upper bound should be 0x8000, but
7729 unfortunately the MIPS assembler accepts numbers
7730 from 0x8000 to 0xffff and sign extends them, and
7731 we want to be compatible. We only permit this
7732 extended range for an instruction which does not
7733 provide any further alternates, since those
7734 alternates may handle other cases. People should
7735 use the numbers they mean, rather than relying on
7736 a mysterious sign extension. */
7737 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7738 strcmp (insn
->name
, insn
[1].name
) == 0);
7743 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
7744 || ((imm_expr
.X_add_number
< -0x8000
7745 || imm_expr
.X_add_number
>= max
)
7746 && imm_expr
.X_op
== O_constant
)
7748 && imm_expr
.X_add_number
< 0
7750 && imm_expr
.X_unsigned
7751 && sizeof (imm_expr
.X_add_number
) <= 4))
7755 if (imm_expr
.X_op
== O_constant
7756 || imm_expr
.X_op
== O_big
)
7757 as_bad (_("16 bit expression not in range -32768..32767"));
7763 case 'o': /* 16 bit offset */
7764 c
= my_getSmallExpression (&offset_expr
, s
);
7766 /* If this value won't fit into a 16 bit offset, then go
7767 find a macro that will generate the 32 bit offset
7768 code pattern. As a special hack, we accept the
7769 difference of two local symbols as a constant. This
7770 is required to suppose embedded PIC switches, which
7771 use an instruction which looks like
7772 lw $4,$L12-$LS12($4)
7773 The problem with handling this in a more general
7774 fashion is that the macro function doesn't expect to
7775 see anything which can be handled in a single
7776 constant instruction. */
7778 && (offset_expr
.X_op
!= O_constant
7779 || offset_expr
.X_add_number
>= 0x8000
7780 || offset_expr
.X_add_number
< -0x8000)
7781 && (mips_pic
!= EMBEDDED_PIC
7782 || offset_expr
.X_op
!= O_subtract
7783 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7784 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7789 if (offset_expr
.X_op
!= O_constant
)
7791 offset_expr
.X_add_number
=
7792 (offset_expr
.X_add_number
>> 16) & 0xffff;
7794 offset_reloc
= BFD_RELOC_LO16
;
7798 case 'p': /* pc relative offset */
7799 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7800 my_getExpression (&offset_expr
, s
);
7804 case 'u': /* upper 16 bits */
7805 c
= my_getSmallExpression (&imm_expr
, s
);
7806 imm_reloc
= BFD_RELOC_LO16
;
7811 if (imm_expr
.X_op
== O_constant
)
7812 imm_expr
.X_add_number
=
7813 (imm_expr
.X_add_number
>> 16) & 0xffff;
7814 else if (c
== S_EX_HIGHEST
)
7815 imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
7816 else if (c
== S_EX_HI
)
7818 imm_reloc
= BFD_RELOC_HI16_S
;
7819 imm_unmatched_hi
= true;
7822 imm_reloc
= BFD_RELOC_HI16
;
7824 else if (imm_expr
.X_op
== O_constant
)
7825 imm_expr
.X_add_number
&= 0xffff;
7827 if (imm_expr
.X_op
== O_constant
7828 && (imm_expr
.X_add_number
< 0
7829 || imm_expr
.X_add_number
>= 0x10000))
7830 as_bad (_("lui expression not in range 0..65535"));
7834 case 'a': /* 26 bit address */
7835 my_getExpression (&offset_expr
, s
);
7837 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7840 case 'N': /* 3 bit branch condition code */
7841 case 'M': /* 3 bit compare condition code */
7842 if (strncmp (s
, "$fcc", 4) != 0)
7852 while (isdigit ((unsigned char) *s
));
7854 as_bad (_("invalid condition code register $fcc%d"), regno
);
7856 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7858 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7862 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7864 if (isdigit ((unsigned char) *s
))
7873 while (isdigit ((unsigned char) *s
));
7876 c
= 8; /* Invalid sel value. */
7879 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7880 ip
->insn_opcode
|= c
;
7884 as_bad (_("bad char = '%c'\n"), *args
);
7889 /* Args don't match. */
7890 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7891 !strcmp (insn
->name
, insn
[1].name
))
7895 insn_error
= _("illegal operands");
7900 insn_error
= _("illegal operands");
7905 /* This routine assembles an instruction into its binary format when
7906 assembling for the mips16. As a side effect, it sets one of the
7907 global variables imm_reloc or offset_reloc to the type of
7908 relocation to do if one of the operands is an address expression.
7909 It also sets mips16_small and mips16_ext if the user explicitly
7910 requested a small or extended instruction. */
7915 struct mips_cl_insn
*ip
;
7919 struct mips_opcode
*insn
;
7922 unsigned int lastregno
= 0;
7927 mips16_small
= false;
7930 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7942 if (s
[1] == 't' && s
[2] == ' ')
7945 mips16_small
= true;
7949 else if (s
[1] == 'e' && s
[2] == ' ')
7958 insn_error
= _("unknown opcode");
7962 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7963 mips16_small
= true;
7965 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7967 insn_error
= _("unrecognized opcode");
7974 assert (strcmp (insn
->name
, str
) == 0);
7977 ip
->insn_opcode
= insn
->match
;
7978 ip
->use_extend
= false;
7979 imm_expr
.X_op
= O_absent
;
7980 imm_reloc
= BFD_RELOC_UNUSED
;
7981 offset_expr
.X_op
= O_absent
;
7982 offset_reloc
= BFD_RELOC_UNUSED
;
7983 for (args
= insn
->args
; 1; ++args
)
7990 /* In this switch statement we call break if we did not find
7991 a match, continue if we did find a match, or return if we
8000 /* Stuff the immediate value in now, if we can. */
8001 if (imm_expr
.X_op
== O_constant
8002 && imm_reloc
> BFD_RELOC_UNUSED
8003 && insn
->pinfo
!= INSN_MACRO
)
8005 mips16_immed ((char *) NULL
, 0,
8006 imm_reloc
- BFD_RELOC_UNUSED
,
8007 imm_expr
.X_add_number
, true, mips16_small
,
8008 mips16_ext
, &ip
->insn_opcode
,
8009 &ip
->use_extend
, &ip
->extend
);
8010 imm_expr
.X_op
= O_absent
;
8011 imm_reloc
= BFD_RELOC_UNUSED
;
8025 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8028 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8044 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8046 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8063 if (isdigit ((unsigned char) s
[1]))
8073 while (isdigit ((unsigned char) *s
));
8076 as_bad (_("invalid register number (%d)"), regno
);
8082 if (s
[1] == 'f' && s
[2] == 'p')
8087 else if (s
[1] == 's' && s
[2] == 'p')
8092 else if (s
[1] == 'g' && s
[2] == 'p')
8097 else if (s
[1] == 'a' && s
[2] == 't')
8102 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8107 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8120 if (c
== 'v' || c
== 'w')
8122 regno
= mips16_to_32_reg_map
[lastregno
];
8136 regno
= mips32_to_16_reg_map
[regno
];
8141 regno
= ILLEGAL_REG
;
8146 regno
= ILLEGAL_REG
;
8151 regno
= ILLEGAL_REG
;
8156 if (regno
== AT
&& ! mips_opts
.noat
)
8157 as_warn (_("used $at without \".set noat\""));
8164 if (regno
== ILLEGAL_REG
)
8171 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8175 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8178 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8181 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8187 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8190 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8191 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8201 if (strncmp (s
, "$pc", 3) == 0)
8225 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8227 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8228 and generate the appropriate reloc. If the text
8229 inside %gprel is not a symbol name with an
8230 optional offset, then we generate a normal reloc
8231 and will probably fail later. */
8232 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8233 if (imm_expr
.X_op
== O_symbol
)
8236 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8238 ip
->use_extend
= true;
8245 /* Just pick up a normal expression. */
8246 my_getExpression (&imm_expr
, s
);
8249 if (imm_expr
.X_op
== O_register
)
8251 /* What we thought was an expression turned out to
8254 if (s
[0] == '(' && args
[1] == '(')
8256 /* It looks like the expression was omitted
8257 before a register indirection, which means
8258 that the expression is implicitly zero. We
8259 still set up imm_expr, so that we handle
8260 explicit extensions correctly. */
8261 imm_expr
.X_op
= O_constant
;
8262 imm_expr
.X_add_number
= 0;
8263 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8270 /* We need to relax this instruction. */
8271 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8280 /* We use offset_reloc rather than imm_reloc for the PC
8281 relative operands. This lets macros with both
8282 immediate and address operands work correctly. */
8283 my_getExpression (&offset_expr
, s
);
8285 if (offset_expr
.X_op
== O_register
)
8288 /* We need to relax this instruction. */
8289 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8293 case '6': /* break code */
8294 my_getExpression (&imm_expr
, s
);
8295 check_absolute_expr (ip
, &imm_expr
);
8296 if ((unsigned long) imm_expr
.X_add_number
> 63)
8298 as_warn (_("Invalid value for `%s' (%lu)"),
8300 (unsigned long) imm_expr
.X_add_number
);
8301 imm_expr
.X_add_number
&= 0x3f;
8303 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8304 imm_expr
.X_op
= O_absent
;
8308 case 'a': /* 26 bit address */
8309 my_getExpression (&offset_expr
, s
);
8311 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8312 ip
->insn_opcode
<<= 16;
8315 case 'l': /* register list for entry macro */
8316 case 'L': /* register list for exit macro */
8326 int freg
, reg1
, reg2
;
8328 while (*s
== ' ' || *s
== ',')
8332 as_bad (_("can't parse register list"));
8344 while (isdigit ((unsigned char) *s
))
8366 as_bad (_("invalid register list"));
8371 while (isdigit ((unsigned char) *s
))
8378 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8383 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8388 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8389 mask
|= (reg2
- 3) << 3;
8390 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8391 mask
|= (reg2
- 15) << 1;
8392 else if (reg1
== 31 && reg2
== 31)
8396 as_bad (_("invalid register list"));
8400 /* The mask is filled in in the opcode table for the
8401 benefit of the disassembler. We remove it before
8402 applying the actual mask. */
8403 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8404 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8408 case 'e': /* extend code */
8409 my_getExpression (&imm_expr
, s
);
8410 check_absolute_expr (ip
, &imm_expr
);
8411 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8413 as_warn (_("Invalid value for `%s' (%lu)"),
8415 (unsigned long) imm_expr
.X_add_number
);
8416 imm_expr
.X_add_number
&= 0x7ff;
8418 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8419 imm_expr
.X_op
= O_absent
;
8429 /* Args don't match. */
8430 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8431 strcmp (insn
->name
, insn
[1].name
) == 0)
8438 insn_error
= _("illegal operands");
8444 /* This structure holds information we know about a mips16 immediate
8447 struct mips16_immed_operand
8449 /* The type code used in the argument string in the opcode table. */
8451 /* The number of bits in the short form of the opcode. */
8453 /* The number of bits in the extended form of the opcode. */
8455 /* The amount by which the short form is shifted when it is used;
8456 for example, the sw instruction has a shift count of 2. */
8458 /* The amount by which the short form is shifted when it is stored
8459 into the instruction code. */
8461 /* Non-zero if the short form is unsigned. */
8463 /* Non-zero if the extended form is unsigned. */
8465 /* Non-zero if the value is PC relative. */
8469 /* The mips16 immediate operand types. */
8471 static const struct mips16_immed_operand mips16_immed_operands
[] =
8473 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8474 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8475 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8476 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8477 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8478 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8479 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8480 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8481 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8482 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8483 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8484 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8485 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8486 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8487 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8488 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8489 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8490 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8491 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8492 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8493 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8496 #define MIPS16_NUM_IMMED \
8497 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8499 /* Handle a mips16 instruction with an immediate value. This or's the
8500 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8501 whether an extended value is needed; if one is needed, it sets
8502 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8503 If SMALL is true, an unextended opcode was explicitly requested.
8504 If EXT is true, an extended opcode was explicitly requested. If
8505 WARN is true, warn if EXT does not match reality. */
8508 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8517 unsigned long *insn
;
8518 boolean
*use_extend
;
8519 unsigned short *extend
;
8521 register const struct mips16_immed_operand
*op
;
8522 int mintiny
, maxtiny
;
8525 op
= mips16_immed_operands
;
8526 while (op
->type
!= type
)
8529 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8534 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8537 maxtiny
= 1 << op
->nbits
;
8542 maxtiny
= (1 << op
->nbits
) - 1;
8547 mintiny
= - (1 << (op
->nbits
- 1));
8548 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8551 /* Branch offsets have an implicit 0 in the lowest bit. */
8552 if (type
== 'p' || type
== 'q')
8555 if ((val
& ((1 << op
->shift
) - 1)) != 0
8556 || val
< (mintiny
<< op
->shift
)
8557 || val
> (maxtiny
<< op
->shift
))
8562 if (warn
&& ext
&& ! needext
)
8563 as_warn_where (file
, line
,
8564 _("extended operand requested but not required"));
8565 if (small
&& needext
)
8566 as_bad_where (file
, line
, _("invalid unextended operand value"));
8568 if (small
|| (! ext
&& ! needext
))
8572 *use_extend
= false;
8573 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8574 insnval
<<= op
->op_shift
;
8579 long minext
, maxext
;
8585 maxext
= (1 << op
->extbits
) - 1;
8589 minext
= - (1 << (op
->extbits
- 1));
8590 maxext
= (1 << (op
->extbits
- 1)) - 1;
8592 if (val
< minext
|| val
> maxext
)
8593 as_bad_where (file
, line
,
8594 _("operand value out of range for instruction"));
8597 if (op
->extbits
== 16)
8599 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8602 else if (op
->extbits
== 15)
8604 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8609 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8613 *extend
= (unsigned short) extval
;
8620 my_getSmallExpression (ep
, str
)
8632 else if (str
[0] == '%'
8633 && tolower(str
[1]) == 'l'
8634 && tolower(str
[2]) == 'o'
8638 str
+= sizeof ("%lo(") - 2;
8640 else if (str
[0] == '%'
8641 && tolower(str
[1]) == 'h'
8642 && tolower(str
[2]) == 'i'
8646 str
+= sizeof ("%hi(") - 2;
8648 else if (str
[0] == '%'
8649 && tolower(str
[1]) == 'h'
8650 && tolower(str
[2]) == 'i'
8651 && tolower(str
[3]) == 'g'
8652 && tolower(str
[4]) == 'h'
8653 && tolower(str
[5]) == 'e'
8654 && tolower(str
[6]) == 'r'
8658 str
+= sizeof ("%higher(") - 2;
8660 else if (str
[0] == '%'
8661 && tolower(str
[1]) == 'h'
8662 && tolower(str
[2]) == 'i'
8663 && tolower(str
[3]) == 'g'
8664 && tolower(str
[4]) == 'h'
8665 && tolower(str
[5]) == 'e'
8666 && tolower(str
[6]) == 's'
8667 && tolower(str
[7]) == 't'
8671 str
+= sizeof ("%highest(") - 2;
8673 /* currently unsupported */
8675 else if (str
[0] == '%'
8676 && tolower(str
[1]) == 'g'
8677 && tolower(str
[2]) == 'p'
8678 && tolower(str
[3]) == '_'
8679 && tolower(str
[4]) == 'r'
8680 && tolower(str
[5]) == 'e'
8681 && tolower(str
[6]) == 'l'
8685 str
+= sizeof ("%gp_rel(") - 2;
8687 else if (str
[0] == '%'
8688 && tolower(str
[1]) == 'n'
8689 && tolower(str
[2]) == 'e'
8690 && tolower(str
[3]) == 'g'
8694 str
+= sizeof ("%neg(") - 2;
8699 my_getExpression (ep
, str
);
8704 * A small expression may be followed by a base register.
8705 * Scan to the end of this operand, and then back over a possible
8706 * base register. Then scan the small expression up to that
8707 * point. (Based on code in sparc.c...)
8709 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8711 if (sp
- 4 >= str
&& sp
[-1] == ')')
8713 if (isdigit ((unsigned char) sp
[-2]))
8715 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8717 if (*sp
== '$' && sp
> str
&& sp
[-1] == '(')
8723 else if (sp
- 5 >= str
8726 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8727 || (sp
[-3] == 's' && sp
[-2] == 'p')
8728 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8729 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8735 /* no expression means zero offset */
8738 /* %xx(reg) is an error */
8739 ep
->X_op
= O_absent
;
8744 ep
->X_op
= O_constant
;
8747 ep
->X_add_symbol
= NULL
;
8748 ep
->X_op_symbol
= NULL
;
8749 ep
->X_add_number
= 0;
8754 my_getExpression (ep
, str
);
8760 my_getExpression (ep
, str
);
8762 /* => %highest, %higher, %hi, %lo, %gprel, %neg encountered */
8767 my_getExpression (ep
, str
)
8774 save_in
= input_line_pointer
;
8775 input_line_pointer
= str
;
8777 expr_end
= input_line_pointer
;
8778 input_line_pointer
= save_in
;
8780 /* If we are in mips16 mode, and this is an expression based on `.',
8781 then we bump the value of the symbol by 1 since that is how other
8782 text symbols are handled. We don't bother to handle complex
8783 expressions, just `.' plus or minus a constant. */
8784 if (mips_opts
.mips16
8785 && ep
->X_op
== O_symbol
8786 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8787 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8788 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8789 && symbol_constant_p (ep
->X_add_symbol
)
8790 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
8791 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
8794 /* Turn a string in input_line_pointer into a floating point constant
8795 of type TYPE, and store the appropriate bytes in *LITP. The number
8796 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8797 returned, or NULL on OK. */
8800 md_atof (type
, litP
, sizeP
)
8806 LITTLENUM_TYPE words
[4];
8822 return _("bad call to md_atof");
8825 t
= atof_ieee (input_line_pointer
, type
, words
);
8827 input_line_pointer
= t
;
8831 if (! target_big_endian
)
8833 for (i
= prec
- 1; i
>= 0; i
--)
8835 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8841 for (i
= 0; i
< prec
; i
++)
8843 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8852 md_number_to_chars (buf
, val
, n
)
8857 if (target_big_endian
)
8858 number_to_chars_bigendian (buf
, val
, n
);
8860 number_to_chars_littleendian (buf
, val
, n
);
8863 CONST
char *md_shortopts
= "nO::g::G:";
8865 struct option md_longopts
[] =
8867 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8868 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8869 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8870 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8871 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8872 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8873 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8874 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8875 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8876 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8877 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8878 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8879 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8880 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8881 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8882 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8883 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8884 {"break", no_argument
, NULL
, OPTION_BREAK
},
8885 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8886 #define OPTION_EB (OPTION_MD_BASE + 9)
8887 {"EB", no_argument
, NULL
, OPTION_EB
},
8888 #define OPTION_EL (OPTION_MD_BASE + 10)
8889 {"EL", no_argument
, NULL
, OPTION_EL
},
8890 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8891 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8892 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8893 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8894 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8895 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8896 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8897 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8898 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8899 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8900 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8901 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8902 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8903 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8904 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8905 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8906 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8907 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8908 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8909 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8910 #define OPTION_MABI (OPTION_MD_BASE + 21)
8911 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8912 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8913 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8914 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8915 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8916 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8917 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8918 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8919 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8920 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8921 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8922 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8923 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8924 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8925 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8926 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8927 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8928 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8929 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8930 #define OPTION_MARCH (OPTION_MD_BASE + 31)
8931 {"march", required_argument
, NULL
, OPTION_MARCH
},
8932 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
8933 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8934 #define OPTION_FP32 (OPTION_MD_BASE + 33)
8935 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
8937 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8938 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8939 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8940 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8941 #define OPTION_32 (OPTION_ELF_BASE + 3)
8942 #define OPTION_64 (OPTION_ELF_BASE + 4)
8943 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8944 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8945 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8946 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8947 {"32", no_argument
, NULL
, OPTION_32
},
8948 {"64", no_argument
, NULL
, OPTION_64
},
8951 {NULL
, no_argument
, NULL
, 0}
8953 size_t md_longopts_size
= sizeof (md_longopts
);
8956 md_parse_option (c
, arg
)
8962 case OPTION_CONSTRUCT_FLOATS
:
8963 mips_disable_float_construction
= 0;
8966 case OPTION_NO_CONSTRUCT_FLOATS
:
8967 mips_disable_float_construction
= 1;
8979 target_big_endian
= 1;
8983 target_big_endian
= 0;
8991 if (arg
&& arg
[1] == '0')
9001 mips_debug
= atoi (arg
);
9002 /* When the MIPS assembler sees -g or -g2, it does not do
9003 optimizations which limit full symbolic debugging. We take
9004 that to be equivalent to -O0. */
9005 if (mips_debug
== 2)
9010 mips_opts
.isa
= ISA_MIPS1
;
9014 mips_opts
.isa
= ISA_MIPS2
;
9018 mips_opts
.isa
= ISA_MIPS3
;
9022 mips_opts
.isa
= ISA_MIPS4
;
9026 mips_opts
.isa
= ISA_MIPS5
;
9030 mips_opts
.isa
= ISA_MIPS32
;
9034 mips_opts
.isa
= ISA_MIPS64
;
9041 int cpu
= CPU_UNKNOWN
;
9043 /* Identify the processor type. */
9044 if (strcasecmp (arg
, "default") != 0)
9046 const struct mips_cpu_info
*ci
;
9048 ci
= mips_cpu_info_from_name (arg
);
9049 if (ci
== NULL
|| ci
->is_isa
)
9054 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9057 as_fatal (_("invalid architecture -march=%s"), arg
);
9060 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9071 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9072 as_warn(_("A different -mtune= was already specified, is now "
9077 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9078 as_warn(_("A different -march= was already specified, is now "
9083 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9084 as_warn(_("A different -mcpu= was already specified, is now "
9092 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9093 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9094 as_warn(_("A different -march= or -mtune= was already specified, "
9096 mips_arch
= CPU_R4650
;
9097 mips_tune
= CPU_R4650
;
9100 case OPTION_NO_M4650
:
9104 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9105 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9106 as_warn(_("A different -march= or -mtune= was already specified, "
9108 mips_arch
= CPU_R4010
;
9109 mips_tune
= CPU_R4010
;
9112 case OPTION_NO_M4010
:
9116 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9117 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9118 as_warn(_("A different -march= or -mtune= was already specified, "
9120 mips_arch
= CPU_VR4100
;
9121 mips_tune
= CPU_VR4100
;
9124 case OPTION_NO_M4100
:
9128 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9129 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9130 as_warn(_("A different -march= or -mtune= was already specified, "
9132 mips_arch
= CPU_R3900
;
9133 mips_tune
= CPU_R3900
;
9136 case OPTION_NO_M3900
:
9140 mips_opts
.mips16
= 1;
9141 mips_no_prev_insn (false);
9144 case OPTION_NO_MIPS16
:
9145 mips_opts
.mips16
= 0;
9146 mips_no_prev_insn (false);
9149 case OPTION_MEMBEDDED_PIC
:
9150 mips_pic
= EMBEDDED_PIC
;
9151 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9153 as_bad (_("-G may not be used with embedded PIC code"));
9156 g_switch_value
= 0x7fffffff;
9160 /* When generating ELF code, we permit -KPIC and -call_shared to
9161 select SVR4_PIC, and -non_shared to select no PIC. This is
9162 intended to be compatible with Irix 5. */
9163 case OPTION_CALL_SHARED
:
9164 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9166 as_bad (_("-call_shared is supported only for ELF format"));
9169 mips_pic
= SVR4_PIC
;
9170 if (g_switch_seen
&& g_switch_value
!= 0)
9172 as_bad (_("-G may not be used with SVR4 PIC code"));
9178 case OPTION_NON_SHARED
:
9179 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9181 as_bad (_("-non_shared is supported only for ELF format"));
9187 /* The -xgot option tells the assembler to use 32 offsets when
9188 accessing the got in SVR4_PIC mode. It is for Irix
9193 #endif /* OBJ_ELF */
9196 if (! USE_GLOBAL_POINTER_OPT
)
9198 as_bad (_("-G is not supported for this configuration"));
9201 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9203 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9207 g_switch_value
= atoi (arg
);
9212 /* The -32 and -64 options tell the assembler to output the 32
9213 bit or the 64 bit MIPS ELF format. */
9220 const char **list
, **l
;
9222 list
= bfd_target_list ();
9223 for (l
= list
; *l
!= NULL
; l
++)
9225 /* This is traditional mips */
9226 if (strcmp (*l
, "elf64-tradbigmips") == 0
9227 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9229 if (strcmp (*l
, "elf64-bigmips") == 0
9230 || strcmp (*l
, "elf64-littlemips") == 0)
9234 as_fatal (_("No compiled in support for 64 bit object file format"));
9239 #endif /* OBJ_ELF */
9245 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9246 flag in object files because to do so would make it
9247 impossible to link with libraries compiled without "-gp32".
9248 This is unnecessarily restrictive.
9250 We could solve this problem by adding "-gp32" multilibs to
9251 gcc, but to set this flag before gcc is built with such
9252 multilibs will break too many systems. */
9272 if (strcmp (arg
, "32") == 0
9273 || strcmp (arg
, "n32") == 0
9274 || strcmp (arg
, "64") == 0
9275 || strcmp (arg
, "o64") == 0
9276 || strcmp (arg
, "eabi") == 0)
9278 mips_abi_string
= arg
;
9279 mips_32bit_abi
= (strcmp (arg
, "32") == 0);
9283 case OPTION_M7000_HILO_FIX
:
9284 mips_7000_hilo_fix
= true;
9287 case OPTION_NO_M7000_HILO_FIX
:
9288 mips_7000_hilo_fix
= false;
9299 show (stream
, string
, col_p
, first_p
)
9307 fprintf (stream
, "%24s", "");
9312 fprintf (stream
, ", ");
9316 if (*col_p
+ strlen (string
) > 72)
9318 fprintf (stream
, "\n%24s", "");
9322 fprintf (stream
, "%s", string
);
9323 *col_p
+= strlen (string
);
9329 md_show_usage (stream
)
9334 fprintf (stream
, _("\
9336 -membedded-pic generate embedded position independent code\n\
9337 -EB generate big endian output\n\
9338 -EL generate little endian output\n\
9339 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9340 -G NUM allow referencing objects up to NUM bytes\n\
9341 implicitly with the gp register [default 8]\n"));
9342 fprintf (stream
, _("\
9343 -mips1 generate MIPS ISA I instructions\n\
9344 -mips2 generate MIPS ISA II instructions\n\
9345 -mips3 generate MIPS ISA III instructions\n\
9346 -mips4 generate MIPS ISA IV instructions\n\
9347 -mips5 generate MIPS ISA V instructions\n\
9348 -mips32 generate MIPS32 ISA instructions\n\
9349 -mips64 generate MIPS64 ISA instructions\n\
9350 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9354 show (stream
, "2000", &column
, &first
);
9355 show (stream
, "3000", &column
, &first
);
9356 show (stream
, "3900", &column
, &first
);
9357 show (stream
, "4000", &column
, &first
);
9358 show (stream
, "4010", &column
, &first
);
9359 show (stream
, "4100", &column
, &first
);
9360 show (stream
, "4111", &column
, &first
);
9361 show (stream
, "4300", &column
, &first
);
9362 show (stream
, "4400", &column
, &first
);
9363 show (stream
, "4600", &column
, &first
);
9364 show (stream
, "4650", &column
, &first
);
9365 show (stream
, "5000", &column
, &first
);
9366 show (stream
, "5200", &column
, &first
);
9367 show (stream
, "5230", &column
, &first
);
9368 show (stream
, "5231", &column
, &first
);
9369 show (stream
, "5261", &column
, &first
);
9370 show (stream
, "5721", &column
, &first
);
9371 show (stream
, "6000", &column
, &first
);
9372 show (stream
, "8000", &column
, &first
);
9373 show (stream
, "10000", &column
, &first
);
9374 show (stream
, "12000", &column
, &first
);
9375 show (stream
, "mips32-4k", &column
, &first
);
9376 show (stream
, "sb-1", &column
, &first
);
9377 fputc ('\n', stream
);
9379 fprintf (stream
, _("\
9380 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9381 -no-mCPU don't generate code specific to CPU.\n\
9382 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9386 show (stream
, "3900", &column
, &first
);
9387 show (stream
, "4010", &column
, &first
);
9388 show (stream
, "4100", &column
, &first
);
9389 show (stream
, "4650", &column
, &first
);
9390 fputc ('\n', stream
);
9392 fprintf (stream
, _("\
9393 -mips16 generate mips16 instructions\n\
9394 -no-mips16 do not generate mips16 instructions\n"));
9395 fprintf (stream
, _("\
9396 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9397 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9398 -O0 remove unneeded NOPs, do not swap branches\n\
9399 -O remove unneeded NOPs and swap branches\n\
9400 -n warn about NOPs generated from macros\n\
9401 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9402 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9403 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9405 fprintf (stream
, _("\
9406 -KPIC, -call_shared generate SVR4 position independent code\n\
9407 -non_shared do not generate position independent code\n\
9408 -xgot assume a 32 bit GOT\n\
9409 -32 create 32 bit object file (default)\n\
9410 -64 create 64 bit object file\n"));
9415 mips_init_after_args ()
9417 /* initialize opcodes */
9418 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9419 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9423 md_pcrel_from (fixP
)
9426 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9427 && fixP
->fx_addsy
!= (symbolS
*) NULL
9428 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9430 /* This makes a branch to an undefined symbol be a branch to the
9431 current location. */
9435 /* return the address of the delay slot */
9436 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9439 /* This is called before the symbol table is processed. In order to
9440 work with gcc when using mips-tfile, we must keep all local labels.
9441 However, in other cases, we want to discard them. If we were
9442 called with -g, but we didn't see any debugging information, it may
9443 mean that gcc is smuggling debugging information through to
9444 mips-tfile, in which case we must generate all local labels. */
9447 mips_frob_file_before_adjust ()
9449 #ifndef NO_ECOFF_DEBUGGING
9452 && ! ecoff_debugging_seen
)
9453 flag_keep_locals
= 1;
9457 /* Sort any unmatched HI16_S relocs so that they immediately precede
9458 the corresponding LO reloc. This is called before md_apply_fix and
9459 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9460 explicit use of the %hi modifier. */
9465 struct mips_hi_fixup
*l
;
9467 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9469 segment_info_type
*seginfo
;
9472 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9474 /* Check quickly whether the next fixup happens to be a matching
9476 if (l
->fixp
->fx_next
!= NULL
9477 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9478 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9479 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9482 /* Look through the fixups for this segment for a matching %lo.
9483 When we find one, move the %hi just in front of it. We do
9484 this in two passes. In the first pass, we try to find a
9485 unique %lo. In the second pass, we permit multiple %hi
9486 relocs for a single %lo (this is a GNU extension). */
9487 seginfo
= seg_info (l
->seg
);
9488 for (pass
= 0; pass
< 2; pass
++)
9493 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9495 /* Check whether this is a %lo fixup which matches l->fixp. */
9496 if (f
->fx_r_type
== BFD_RELOC_LO16
9497 && f
->fx_addsy
== l
->fixp
->fx_addsy
9498 && f
->fx_offset
== l
->fixp
->fx_offset
9501 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9502 || prev
->fx_addsy
!= f
->fx_addsy
9503 || prev
->fx_offset
!= f
->fx_offset
))
9507 /* Move l->fixp before f. */
9508 for (pf
= &seginfo
->fix_root
;
9510 pf
= &(*pf
)->fx_next
)
9511 assert (*pf
!= NULL
);
9513 *pf
= l
->fixp
->fx_next
;
9515 l
->fixp
->fx_next
= f
;
9517 seginfo
->fix_root
= l
->fixp
;
9519 prev
->fx_next
= l
->fixp
;
9530 #if 0 /* GCC code motion plus incomplete dead code elimination
9531 can leave a %hi without a %lo. */
9533 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9534 _("Unmatched %%hi reloc"));
9540 /* When generating embedded PIC code we need to use a special
9541 relocation to represent the difference of two symbols in the .text
9542 section (switch tables use a difference of this sort). See
9543 include/coff/mips.h for details. This macro checks whether this
9544 fixup requires the special reloc. */
9545 #define SWITCH_TABLE(fixp) \
9546 ((fixp)->fx_r_type == BFD_RELOC_32 \
9547 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9548 && (fixp)->fx_addsy != NULL \
9549 && (fixp)->fx_subsy != NULL \
9550 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9551 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9553 /* When generating embedded PIC code we must keep all PC relative
9554 relocations, in case the linker has to relax a call. We also need
9555 to keep relocations for switch table entries. */
9558 mips_force_relocation (fixp
)
9561 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9562 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9565 return (mips_pic
== EMBEDDED_PIC
9567 || SWITCH_TABLE (fixp
)
9568 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9569 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9572 /* Apply a fixup to the object file. */
9575 md_apply_fix (fixP
, valueP
)
9583 assert (fixP
->fx_size
== 4
9584 || fixP
->fx_r_type
== BFD_RELOC_16
9585 || fixP
->fx_r_type
== BFD_RELOC_64
9586 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9587 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9591 /* If we aren't adjusting this fixup to be against the section
9592 symbol, we need to adjust the value. */
9594 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9596 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9597 || ((S_IS_WEAK (fixP
->fx_addsy
)
9598 || S_IS_EXTERN (fixP
->fx_addsy
))
9599 && !S_IS_COMMON (fixP
->fx_addsy
))
9600 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9601 && (((bfd_get_section_flags (stdoutput
,
9602 S_GET_SEGMENT (fixP
->fx_addsy
))
9603 & SEC_LINK_ONCE
) != 0)
9604 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9606 sizeof (".gnu.linkonce") - 1))))
9609 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
9613 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
9615 /* In this case, the bfd_install_relocation routine will
9616 incorrectly add the symbol value back in. We just want
9617 the addend to appear in the object file. */
9620 /* Make sure the addend is still non-zero. If it became zero
9621 after the last operation, set it to a spurious value and
9622 subtract the same value from the object file's contents. */
9627 /* The in-place addends for LO16 relocations are signed;
9628 leave the matching HI16 in-place addends as zero. */
9629 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
9631 reloc_howto_type
*howto
;
9632 bfd_vma contents
, mask
, field
;
9634 howto
= bfd_reloc_type_lookup (stdoutput
,
9637 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
9642 /* MASK has bits set where the relocation should go.
9643 FIELD is -value, shifted into the appropriate place
9644 for this relocation. */
9645 mask
= 1 << (howto
->bitsize
- 1);
9646 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
9647 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
9649 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
9650 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9658 /* This code was generated using trial and error and so is
9659 fragile and not trustworthy. If you change it, you should
9660 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9662 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9664 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9666 /* BFD's REL handling, for MIPS, is _very_ weird.
9667 This gives the right results, but it can't possibly
9668 be the way things are supposed to work. */
9669 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9670 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9671 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9676 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9678 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9681 switch (fixP
->fx_r_type
)
9683 case BFD_RELOC_MIPS_JMP
:
9684 case BFD_RELOC_HI16
:
9685 case BFD_RELOC_HI16_S
:
9686 case BFD_RELOC_MIPS_GPREL
:
9687 case BFD_RELOC_MIPS_LITERAL
:
9688 case BFD_RELOC_MIPS_CALL16
:
9689 case BFD_RELOC_MIPS_GOT16
:
9690 case BFD_RELOC_MIPS_GPREL32
:
9691 case BFD_RELOC_MIPS_GOT_HI16
:
9692 case BFD_RELOC_MIPS_GOT_LO16
:
9693 case BFD_RELOC_MIPS_CALL_HI16
:
9694 case BFD_RELOC_MIPS_CALL_LO16
:
9695 case BFD_RELOC_MIPS16_GPREL
:
9697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9698 _("Invalid PC relative reloc"));
9699 /* Nothing needed to do. The value comes from the reloc entry */
9702 case BFD_RELOC_MIPS16_JMP
:
9703 /* We currently always generate a reloc against a symbol, which
9704 means that we don't want an addend even if the symbol is
9706 fixP
->fx_addnumber
= 0;
9709 case BFD_RELOC_PCREL_HI16_S
:
9710 /* The addend for this is tricky if it is internal, so we just
9711 do everything here rather than in bfd_install_relocation. */
9712 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9717 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9719 /* For an external symbol adjust by the address to make it
9720 pcrel_offset. We use the address of the RELLO reloc
9721 which follows this one. */
9722 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9723 + fixP
->fx_next
->fx_where
);
9725 value
= ((value
+ 0x8000) >> 16) & 0xffff;
9726 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9727 if (target_big_endian
)
9729 md_number_to_chars (buf
, value
, 2);
9732 case BFD_RELOC_PCREL_LO16
:
9733 /* The addend for this is tricky if it is internal, so we just
9734 do everything here rather than in bfd_install_relocation. */
9735 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9740 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9741 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9742 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9743 if (target_big_endian
)
9745 md_number_to_chars (buf
, value
, 2);
9749 /* This is handled like BFD_RELOC_32, but we output a sign
9750 extended value if we are only 32 bits. */
9752 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9754 if (8 <= sizeof (valueT
))
9755 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9762 w1
= w2
= fixP
->fx_where
;
9763 if (target_big_endian
)
9767 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9768 if ((value
& 0x80000000) != 0)
9772 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9779 /* If we are deleting this reloc entry, we must fill in the
9780 value now. This can happen if we have a .word which is not
9781 resolved when it appears but is later defined. We also need
9782 to fill in the value if this is an embedded PIC switch table
9785 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9786 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9791 /* If we are deleting this reloc entry, we must fill in the
9793 assert (fixP
->fx_size
== 2);
9795 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9799 case BFD_RELOC_LO16
:
9800 /* When handling an embedded PIC switch statement, we can wind
9801 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9804 if (value
+ 0x8000 > 0xffff)
9805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9806 _("relocation overflow"));
9807 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9808 if (target_big_endian
)
9810 md_number_to_chars (buf
, value
, 2);
9814 case BFD_RELOC_16_PCREL_S2
:
9816 * We need to save the bits in the instruction since fixup_segment()
9817 * might be deleting the relocation entry (i.e., a branch within
9818 * the current segment).
9820 if ((value
& 0x3) != 0)
9821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9822 _("Branch to odd address (%lx)"), (long) value
);
9824 if (!fixP
->fx_done
&& value
!= 0)
9826 /* If 'value' is zero, the remaining reloc code won't actually
9827 do the store, so it must be done here. This is probably
9830 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9832 value
= (offsetT
) value
>> 2;
9834 /* update old instruction data */
9835 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9836 if (target_big_endian
)
9837 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9839 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9841 if (value
+ 0x8000 <= 0xffff)
9842 insn
|= value
& 0xffff;
9845 /* The branch offset is too large. If this is an
9846 unconditional branch, and we are not generating PIC code,
9847 we can convert it to an absolute jump instruction. */
9848 if (mips_pic
== NO_PIC
9850 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9851 && (fixP
->fx_frag
->fr_address
9852 < text_section
->vma
+ text_section
->_raw_size
)
9853 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9854 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9855 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9857 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9858 insn
= 0x0c000000; /* jal */
9860 insn
= 0x08000000; /* j */
9861 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9863 fixP
->fx_addsy
= section_symbol (text_section
);
9864 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9868 /* FIXME. It would be possible in principle to handle
9869 conditional branches which overflow. They could be
9870 transformed into a branch around a jump. This would
9871 require setting up variant frags for each different
9872 branch type. The native MIPS assembler attempts to
9873 handle these cases, but it appears to do it
9875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9876 _("Branch out of range"));
9880 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9883 case BFD_RELOC_VTABLE_INHERIT
:
9886 && !S_IS_DEFINED (fixP
->fx_addsy
)
9887 && !S_IS_WEAK (fixP
->fx_addsy
))
9888 S_SET_WEAK (fixP
->fx_addsy
);
9891 case BFD_RELOC_VTABLE_ENTRY
:
9907 const struct mips_opcode
*p
;
9908 int treg
, sreg
, dreg
, shamt
;
9913 for (i
= 0; i
< NUMOPCODES
; ++i
)
9915 p
= &mips_opcodes
[i
];
9916 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9918 printf ("%08lx %s\t", oc
, p
->name
);
9919 treg
= (oc
>> 16) & 0x1f;
9920 sreg
= (oc
>> 21) & 0x1f;
9921 dreg
= (oc
>> 11) & 0x1f;
9922 shamt
= (oc
>> 6) & 0x1f;
9924 for (args
= p
->args
;; ++args
)
9935 printf ("%c", *args
);
9939 assert (treg
== sreg
);
9940 printf ("$%d,$%d", treg
, sreg
);
9945 printf ("$%d", dreg
);
9950 printf ("$%d", treg
);
9954 printf ("0x%x", treg
);
9959 printf ("$%d", sreg
);
9963 printf ("0x%08lx", oc
& 0x1ffffff);
9975 printf ("$%d", shamt
);
9986 printf (_("%08lx UNDEFINED\n"), oc
);
9997 name
= input_line_pointer
;
9998 c
= get_symbol_end ();
9999 p
= (symbolS
*) symbol_find_or_make (name
);
10000 *input_line_pointer
= c
;
10004 /* Align the current frag to a given power of two. The MIPS assembler
10005 also automatically adjusts any preceding label. */
10008 mips_align (to
, fill
, label
)
10013 mips_emit_delays (false);
10014 frag_align (to
, fill
, 0);
10015 record_alignment (now_seg
, to
);
10018 assert (S_GET_SEGMENT (label
) == now_seg
);
10019 symbol_set_frag (label
, frag_now
);
10020 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10024 /* Align to a given power of two. .align 0 turns off the automatic
10025 alignment used by the data creating pseudo-ops. */
10029 int x ATTRIBUTE_UNUSED
;
10032 register long temp_fill
;
10033 long max_alignment
= 15;
10037 o Note that the assembler pulls down any immediately preceeding label
10038 to the aligned address.
10039 o It's not documented but auto alignment is reinstated by
10040 a .align pseudo instruction.
10041 o Note also that after auto alignment is turned off the mips assembler
10042 issues an error on attempt to assemble an improperly aligned data item.
10047 temp
= get_absolute_expression ();
10048 if (temp
> max_alignment
)
10049 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10052 as_warn (_("Alignment negative: 0 assumed."));
10055 if (*input_line_pointer
== ',')
10057 input_line_pointer
++;
10058 temp_fill
= get_absolute_expression ();
10065 mips_align (temp
, (int) temp_fill
,
10066 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10073 demand_empty_rest_of_line ();
10077 mips_flush_pending_output ()
10079 mips_emit_delays (false);
10080 mips_clear_insn_labels ();
10089 /* When generating embedded PIC code, we only use the .text, .lit8,
10090 .sdata and .sbss sections. We change the .data and .rdata
10091 pseudo-ops to use .sdata. */
10092 if (mips_pic
== EMBEDDED_PIC
10093 && (sec
== 'd' || sec
== 'r'))
10097 /* The ELF backend needs to know that we are changing sections, so
10098 that .previous works correctly. We could do something like check
10099 for a obj_section_change_hook macro, but that might be confusing
10100 as it would not be appropriate to use it in the section changing
10101 functions in read.c, since obj-elf.c intercepts those. FIXME:
10102 This should be cleaner, somehow. */
10103 obj_elf_section_change_hook ();
10106 mips_emit_delays (false);
10116 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10117 demand_empty_rest_of_line ();
10121 if (USE_GLOBAL_POINTER_OPT
)
10123 seg
= subseg_new (RDATA_SECTION_NAME
,
10124 (subsegT
) get_absolute_expression ());
10125 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10127 bfd_set_section_flags (stdoutput
, seg
,
10133 if (strcmp (TARGET_OS
, "elf") != 0)
10134 record_alignment (seg
, 4);
10136 demand_empty_rest_of_line ();
10140 as_bad (_("No read only data section in this object file format"));
10141 demand_empty_rest_of_line ();
10147 if (USE_GLOBAL_POINTER_OPT
)
10149 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10150 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10152 bfd_set_section_flags (stdoutput
, seg
,
10153 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10155 if (strcmp (TARGET_OS
, "elf") != 0)
10156 record_alignment (seg
, 4);
10158 demand_empty_rest_of_line ();
10163 as_bad (_("Global pointers not supported; recompile -G 0"));
10164 demand_empty_rest_of_line ();
10173 mips_enable_auto_align ()
10184 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10185 mips_emit_delays (false);
10186 if (log_size
> 0 && auto_align
)
10187 mips_align (log_size
, 0, label
);
10188 mips_clear_insn_labels ();
10189 cons (1 << log_size
);
10193 s_float_cons (type
)
10198 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10200 mips_emit_delays (false);
10205 mips_align (3, 0, label
);
10207 mips_align (2, 0, label
);
10210 mips_clear_insn_labels ();
10215 /* Handle .globl. We need to override it because on Irix 5 you are
10218 where foo is an undefined symbol, to mean that foo should be
10219 considered to be the address of a function. */
10223 int x ATTRIBUTE_UNUSED
;
10230 name
= input_line_pointer
;
10231 c
= get_symbol_end ();
10232 symbolP
= symbol_find_or_make (name
);
10233 *input_line_pointer
= c
;
10234 SKIP_WHITESPACE ();
10236 /* On Irix 5, every global symbol that is not explicitly labelled as
10237 being a function is apparently labelled as being an object. */
10240 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10245 secname
= input_line_pointer
;
10246 c
= get_symbol_end ();
10247 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10249 as_bad (_("%s: no such section"), secname
);
10250 *input_line_pointer
= c
;
10252 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10253 flag
= BSF_FUNCTION
;
10256 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10258 S_SET_EXTERNAL (symbolP
);
10259 demand_empty_rest_of_line ();
10264 int x ATTRIBUTE_UNUSED
;
10269 opt
= input_line_pointer
;
10270 c
= get_symbol_end ();
10274 /* FIXME: What does this mean? */
10276 else if (strncmp (opt
, "pic", 3) == 0)
10280 i
= atoi (opt
+ 3);
10284 mips_pic
= SVR4_PIC
;
10286 as_bad (_(".option pic%d not supported"), i
);
10288 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10290 if (g_switch_seen
&& g_switch_value
!= 0)
10291 as_warn (_("-G may not be used with SVR4 PIC code"));
10292 g_switch_value
= 0;
10293 bfd_set_gp_size (stdoutput
, 0);
10297 as_warn (_("Unrecognized option \"%s\""), opt
);
10299 *input_line_pointer
= c
;
10300 demand_empty_rest_of_line ();
10303 /* This structure is used to hold a stack of .set values. */
10305 struct mips_option_stack
10307 struct mips_option_stack
*next
;
10308 struct mips_set_options options
;
10311 static struct mips_option_stack
*mips_opts_stack
;
10313 /* Handle the .set pseudo-op. */
10317 int x ATTRIBUTE_UNUSED
;
10319 char *name
= input_line_pointer
, ch
;
10321 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10322 input_line_pointer
++;
10323 ch
= *input_line_pointer
;
10324 *input_line_pointer
= '\0';
10326 if (strcmp (name
, "reorder") == 0)
10328 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10330 /* If we still have pending nops, we can discard them. The
10331 usual nop handling will insert any that are still
10333 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10334 * (mips_opts
.mips16
? 2 : 4));
10335 prev_nop_frag
= NULL
;
10337 mips_opts
.noreorder
= 0;
10339 else if (strcmp (name
, "noreorder") == 0)
10341 mips_emit_delays (true);
10342 mips_opts
.noreorder
= 1;
10343 mips_any_noreorder
= 1;
10345 else if (strcmp (name
, "at") == 0)
10347 mips_opts
.noat
= 0;
10349 else if (strcmp (name
, "noat") == 0)
10351 mips_opts
.noat
= 1;
10353 else if (strcmp (name
, "macro") == 0)
10355 mips_opts
.warn_about_macros
= 0;
10357 else if (strcmp (name
, "nomacro") == 0)
10359 if (mips_opts
.noreorder
== 0)
10360 as_bad (_("`noreorder' must be set before `nomacro'"));
10361 mips_opts
.warn_about_macros
= 1;
10363 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10365 mips_opts
.nomove
= 0;
10367 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10369 mips_opts
.nomove
= 1;
10371 else if (strcmp (name
, "bopt") == 0)
10373 mips_opts
.nobopt
= 0;
10375 else if (strcmp (name
, "nobopt") == 0)
10377 mips_opts
.nobopt
= 1;
10379 else if (strcmp (name
, "mips16") == 0
10380 || strcmp (name
, "MIPS-16") == 0)
10381 mips_opts
.mips16
= 1;
10382 else if (strcmp (name
, "nomips16") == 0
10383 || strcmp (name
, "noMIPS-16") == 0)
10384 mips_opts
.mips16
= 0;
10385 else if (strncmp (name
, "mips", 4) == 0)
10389 /* Permit the user to change the ISA on the fly. Needless to
10390 say, misuse can cause serious problems. */
10391 isa
= atoi (name
+ 4);
10394 case 0: mips_opts
.isa
= file_mips_isa
; break;
10395 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10396 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10397 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10398 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10399 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10400 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10401 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10402 default: as_bad (_("unknown ISA level")); break;
10405 else if (strcmp (name
, "autoextend") == 0)
10406 mips_opts
.noautoextend
= 0;
10407 else if (strcmp (name
, "noautoextend") == 0)
10408 mips_opts
.noautoextend
= 1;
10409 else if (strcmp (name
, "push") == 0)
10411 struct mips_option_stack
*s
;
10413 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10414 s
->next
= mips_opts_stack
;
10415 s
->options
= mips_opts
;
10416 mips_opts_stack
= s
;
10418 else if (strcmp (name
, "pop") == 0)
10420 struct mips_option_stack
*s
;
10422 s
= mips_opts_stack
;
10424 as_bad (_(".set pop with no .set push"));
10427 /* If we're changing the reorder mode we need to handle
10428 delay slots correctly. */
10429 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10430 mips_emit_delays (true);
10431 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10433 if (prev_nop_frag
!= NULL
)
10435 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10436 * (mips_opts
.mips16
? 2 : 4));
10437 prev_nop_frag
= NULL
;
10441 mips_opts
= s
->options
;
10442 mips_opts_stack
= s
->next
;
10448 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10450 *input_line_pointer
= ch
;
10451 demand_empty_rest_of_line ();
10454 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10455 .option pic2. It means to generate SVR4 PIC calls. */
10458 s_abicalls (ignore
)
10459 int ignore ATTRIBUTE_UNUSED
;
10461 mips_pic
= SVR4_PIC
;
10462 if (USE_GLOBAL_POINTER_OPT
)
10464 if (g_switch_seen
&& g_switch_value
!= 0)
10465 as_warn (_("-G may not be used with SVR4 PIC code"));
10466 g_switch_value
= 0;
10468 bfd_set_gp_size (stdoutput
, 0);
10469 demand_empty_rest_of_line ();
10472 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10473 PIC code. It sets the $gp register for the function based on the
10474 function address, which is in the register named in the argument.
10475 This uses a relocation against _gp_disp, which is handled specially
10476 by the linker. The result is:
10477 lui $gp,%hi(_gp_disp)
10478 addiu $gp,$gp,%lo(_gp_disp)
10479 addu $gp,$gp,.cpload argument
10480 The .cpload argument is normally $25 == $t9. */
10484 int ignore ATTRIBUTE_UNUSED
;
10489 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10490 if (mips_pic
!= SVR4_PIC
)
10496 /* .cpload should be a in .set noreorder section. */
10497 if (mips_opts
.noreorder
== 0)
10498 as_warn (_(".cpload not in noreorder section"));
10500 ex
.X_op
= O_symbol
;
10501 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10502 ex
.X_op_symbol
= NULL
;
10503 ex
.X_add_number
= 0;
10505 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10506 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10508 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10509 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10510 (int) BFD_RELOC_LO16
);
10512 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10513 GP
, GP
, tc_get_register (0));
10515 demand_empty_rest_of_line ();
10518 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10519 offset from $sp. The offset is remembered, and after making a PIC
10520 call $gp is restored from that location. */
10523 s_cprestore (ignore
)
10524 int ignore ATTRIBUTE_UNUSED
;
10529 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10530 if (mips_pic
!= SVR4_PIC
)
10536 mips_cprestore_offset
= get_absolute_expression ();
10538 ex
.X_op
= O_constant
;
10539 ex
.X_add_symbol
= NULL
;
10540 ex
.X_op_symbol
= NULL
;
10541 ex
.X_add_number
= mips_cprestore_offset
;
10543 macro_build ((char *) NULL
, &icnt
, &ex
,
10544 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
10545 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10547 demand_empty_rest_of_line ();
10550 /* Handle the .gpword pseudo-op. This is used when generating PIC
10551 code. It generates a 32 bit GP relative reloc. */
10555 int ignore ATTRIBUTE_UNUSED
;
10561 /* When not generating PIC code, this is treated as .word. */
10562 if (mips_pic
!= SVR4_PIC
)
10568 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10569 mips_emit_delays (true);
10571 mips_align (2, 0, label
);
10572 mips_clear_insn_labels ();
10576 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10578 as_bad (_("Unsupported use of .gpword"));
10579 ignore_rest_of_line ();
10583 md_number_to_chars (p
, (valueT
) 0, 4);
10584 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10585 BFD_RELOC_MIPS_GPREL32
);
10587 demand_empty_rest_of_line ();
10590 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10591 tables in SVR4 PIC code. */
10595 int ignore ATTRIBUTE_UNUSED
;
10600 /* This is ignored when not generating SVR4 PIC code. */
10601 if (mips_pic
!= SVR4_PIC
)
10607 /* Add $gp to the register named as an argument. */
10608 reg
= tc_get_register (0);
10609 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10610 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
10611 "d,v,t", reg
, reg
, GP
);
10613 demand_empty_rest_of_line ();
10616 /* Handle the .insn pseudo-op. This marks instruction labels in
10617 mips16 mode. This permits the linker to handle them specially,
10618 such as generating jalx instructions when needed. We also make
10619 them odd for the duration of the assembly, in order to generate the
10620 right sort of code. We will make them even in the adjust_symtab
10621 routine, while leaving them marked. This is convenient for the
10622 debugger and the disassembler. The linker knows to make them odd
10627 int ignore ATTRIBUTE_UNUSED
;
10629 if (mips_opts
.mips16
)
10630 mips16_mark_labels ();
10632 demand_empty_rest_of_line ();
10635 /* Handle a .stabn directive. We need these in order to mark a label
10636 as being a mips16 text label correctly. Sometimes the compiler
10637 will emit a label, followed by a .stabn, and then switch sections.
10638 If the label and .stabn are in mips16 mode, then the label is
10639 really a mips16 text label. */
10645 if (type
== 'n' && mips_opts
.mips16
)
10646 mips16_mark_labels ();
10651 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10655 s_mips_weakext (ignore
)
10656 int ignore ATTRIBUTE_UNUSED
;
10663 name
= input_line_pointer
;
10664 c
= get_symbol_end ();
10665 symbolP
= symbol_find_or_make (name
);
10666 S_SET_WEAK (symbolP
);
10667 *input_line_pointer
= c
;
10669 SKIP_WHITESPACE ();
10671 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10673 if (S_IS_DEFINED (symbolP
))
10675 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10676 S_GET_NAME (symbolP
));
10677 ignore_rest_of_line ();
10681 if (*input_line_pointer
== ',')
10683 ++input_line_pointer
;
10684 SKIP_WHITESPACE ();
10688 if (exp
.X_op
!= O_symbol
)
10690 as_bad ("bad .weakext directive");
10691 ignore_rest_of_line();
10694 symbol_set_value_expression (symbolP
, &exp
);
10697 demand_empty_rest_of_line ();
10700 /* Parse a register string into a number. Called from the ECOFF code
10701 to parse .frame. The argument is non-zero if this is the frame
10702 register, so that we can record it in mips_frame_reg. */
10705 tc_get_register (frame
)
10710 SKIP_WHITESPACE ();
10711 if (*input_line_pointer
++ != '$')
10713 as_warn (_("expected `$'"));
10716 else if (isdigit ((unsigned char) *input_line_pointer
))
10718 reg
= get_absolute_expression ();
10719 if (reg
< 0 || reg
>= 32)
10721 as_warn (_("Bad register number"));
10727 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10729 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10731 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10733 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10737 as_warn (_("Unrecognized register name"));
10740 input_line_pointer
+= 2;
10743 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10748 md_section_align (seg
, addr
)
10752 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10755 /* We don't need to align ELF sections to the full alignment.
10756 However, Irix 5 may prefer that we align them at least to a 16
10757 byte boundary. We don't bother to align the sections if we are
10758 targeted for an embedded system. */
10759 if (strcmp (TARGET_OS
, "elf") == 0)
10765 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10768 /* Utility routine, called from above as well. If called while the
10769 input file is still being read, it's only an approximation. (For
10770 example, a symbol may later become defined which appeared to be
10771 undefined earlier.) */
10774 nopic_need_relax (sym
, before_relaxing
)
10776 int before_relaxing
;
10781 if (USE_GLOBAL_POINTER_OPT
)
10783 const char *symname
;
10786 /* Find out whether this symbol can be referenced off the GP
10787 register. It can be if it is smaller than the -G size or if
10788 it is in the .sdata or .sbss section. Certain symbols can
10789 not be referenced off the GP, although it appears as though
10791 symname
= S_GET_NAME (sym
);
10792 if (symname
!= (const char *) NULL
10793 && (strcmp (symname
, "eprol") == 0
10794 || strcmp (symname
, "etext") == 0
10795 || strcmp (symname
, "_gp") == 0
10796 || strcmp (symname
, "edata") == 0
10797 || strcmp (symname
, "_fbss") == 0
10798 || strcmp (symname
, "_fdata") == 0
10799 || strcmp (symname
, "_ftext") == 0
10800 || strcmp (symname
, "end") == 0
10801 || strcmp (symname
, "_gp_disp") == 0))
10803 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10805 #ifndef NO_ECOFF_DEBUGGING
10806 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10807 && (symbol_get_obj (sym
)->ecoff_extern_size
10808 <= g_switch_value
))
10810 /* We must defer this decision until after the whole
10811 file has been read, since there might be a .extern
10812 after the first use of this symbol. */
10813 || (before_relaxing
10814 #ifndef NO_ECOFF_DEBUGGING
10815 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10817 && S_GET_VALUE (sym
) == 0)
10818 || (S_GET_VALUE (sym
) != 0
10819 && S_GET_VALUE (sym
) <= g_switch_value
)))
10823 const char *segname
;
10825 segname
= segment_name (S_GET_SEGMENT (sym
));
10826 assert (strcmp (segname
, ".lit8") != 0
10827 && strcmp (segname
, ".lit4") != 0);
10828 change
= (strcmp (segname
, ".sdata") != 0
10829 && strcmp (segname
, ".sbss") != 0
10830 && strncmp (segname
, ".sdata.", 7) != 0
10831 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10836 /* We are not optimizing for the GP register. */
10840 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10841 extended opcode. SEC is the section the frag is in. */
10844 mips16_extended_frag (fragp
, sec
, stretch
)
10850 register const struct mips16_immed_operand
*op
;
10852 int mintiny
, maxtiny
;
10856 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10858 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10861 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10862 op
= mips16_immed_operands
;
10863 while (op
->type
!= type
)
10866 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10871 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10874 maxtiny
= 1 << op
->nbits
;
10879 maxtiny
= (1 << op
->nbits
) - 1;
10884 mintiny
= - (1 << (op
->nbits
- 1));
10885 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10888 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
10889 val
= S_GET_VALUE (fragp
->fr_symbol
);
10890 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10896 /* We won't have the section when we are called from
10897 mips_relax_frag. However, we will always have been called
10898 from md_estimate_size_before_relax first. If this is a
10899 branch to a different section, we mark it as such. If SEC is
10900 NULL, and the frag is not marked, then it must be a branch to
10901 the same section. */
10904 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10909 /* Must have been called from md_estimate_size_before_relax. */
10912 fragp
->fr_subtype
=
10913 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10915 /* FIXME: We should support this, and let the linker
10916 catch branches and loads that are out of range. */
10917 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10918 _("unsupported PC relative reference to different section"));
10922 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
10923 /* Assume non-extended on the first relaxation pass.
10924 The address we have calculated will be bogus if this is
10925 a forward branch to another frag, as the forward frag
10926 will have fr_address == 0. */
10930 /* In this case, we know for sure that the symbol fragment is in
10931 the same section. If the relax_marker of the symbol fragment
10932 differs from the relax_marker of this fragment, we have not
10933 yet adjusted the symbol fragment fr_address. We want to add
10934 in STRETCH in order to get a better estimate of the address.
10935 This particularly matters because of the shift bits. */
10937 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
10941 /* Adjust stretch for any alignment frag. Note that if have
10942 been expanding the earlier code, the symbol may be
10943 defined in what appears to be an earlier frag. FIXME:
10944 This doesn't handle the fr_subtype field, which specifies
10945 a maximum number of bytes to skip when doing an
10947 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
10949 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10952 stretch
= - ((- stretch
)
10953 & ~ ((1 << (int) f
->fr_offset
) - 1));
10955 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10964 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10966 /* The base address rules are complicated. The base address of
10967 a branch is the following instruction. The base address of a
10968 PC relative load or add is the instruction itself, but if it
10969 is in a delay slot (in which case it can not be extended) use
10970 the address of the instruction whose delay slot it is in. */
10971 if (type
== 'p' || type
== 'q')
10975 /* If we are currently assuming that this frag should be
10976 extended, then, the current address is two bytes
10978 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10981 /* Ignore the low bit in the target, since it will be set
10982 for a text label. */
10983 if ((val
& 1) != 0)
10986 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10988 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10991 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10993 /* Branch offsets have an implicit 0 in the lowest bit. */
10994 if (type
== 'p' || type
== 'q')
10997 /* If any of the shifted bits are set, we must use an extended
10998 opcode. If the address depends on the size of this
10999 instruction, this can lead to a loop, so we arrange to always
11000 use an extended opcode. We only check this when we are in
11001 the main relaxation loop, when SEC is NULL. */
11002 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11004 fragp
->fr_subtype
=
11005 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11009 /* If we are about to mark a frag as extended because the value
11010 is precisely maxtiny + 1, then there is a chance of an
11011 infinite loop as in the following code:
11016 In this case when the la is extended, foo is 0x3fc bytes
11017 away, so the la can be shrunk, but then foo is 0x400 away, so
11018 the la must be extended. To avoid this loop, we mark the
11019 frag as extended if it was small, and is about to become
11020 extended with a value of maxtiny + 1. */
11021 if (val
== ((maxtiny
+ 1) << op
->shift
)
11022 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11025 fragp
->fr_subtype
=
11026 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11030 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11031 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11033 if ((val
& ((1 << op
->shift
) - 1)) != 0
11034 || val
< (mintiny
<< op
->shift
)
11035 || val
> (maxtiny
<< op
->shift
))
11041 /* Estimate the size of a frag before relaxing. Unless this is the
11042 mips16, we are not really relaxing here, and the final size is
11043 encoded in the subtype information. For the mips16, we have to
11044 decide whether we are using an extended opcode or not. */
11047 md_estimate_size_before_relax (fragp
, segtype
)
11052 boolean linkonce
= false;
11054 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11056 if (mips16_extended_frag (fragp
, segtype
, 0))
11058 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11063 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11068 if (mips_pic
== NO_PIC
)
11070 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11072 else if (mips_pic
== SVR4_PIC
)
11077 sym
= fragp
->fr_symbol
;
11079 /* Handle the case of a symbol equated to another symbol. */
11080 while (symbol_equated_p (sym
)
11081 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11085 /* It's possible to get a loop here in a badly written
11087 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11093 symsec
= S_GET_SEGMENT (sym
);
11095 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11096 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11098 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11102 /* The GNU toolchain uses an extension for ELF: a section
11103 beginning with the magic string .gnu.linkonce is a linkonce
11105 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11106 sizeof ".gnu.linkonce" - 1) == 0)
11110 /* This must duplicate the test in adjust_reloc_syms. */
11111 change
= (symsec
!= &bfd_und_section
11112 && symsec
!= &bfd_abs_section
11113 && ! bfd_is_com_section (symsec
)
11116 /* A global or weak symbol is treated as external. */
11117 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11118 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
11127 /* Record the offset to the first reloc in the fr_opcode field.
11128 This lets md_convert_frag and tc_gen_reloc know that the code
11129 must be expanded. */
11130 fragp
->fr_opcode
= (fragp
->fr_literal
11132 - RELAX_OLD (fragp
->fr_subtype
)
11133 + RELAX_RELOC1 (fragp
->fr_subtype
));
11134 /* FIXME: This really needs as_warn_where. */
11135 if (RELAX_WARN (fragp
->fr_subtype
))
11136 as_warn (_("AT used after \".set noat\" or macro used after "
11137 "\".set nomacro\""));
11139 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11145 /* This is called to see whether a reloc against a defined symbol
11146 should be converted into a reloc against a section. Don't adjust
11147 MIPS16 jump relocations, so we don't have to worry about the format
11148 of the offset in the .o file. Don't adjust relocations against
11149 mips16 symbols, so that the linker can find them if it needs to set
11153 mips_fix_adjustable (fixp
)
11157 /* Prevent all adjustments to global symbols. */
11158 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11159 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
11162 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11164 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11165 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11167 if (fixp
->fx_addsy
== NULL
)
11170 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11171 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11172 && fixp
->fx_subsy
== NULL
)
11178 /* Translate internal representation of relocation info to BFD target
11182 tc_gen_reloc (section
, fixp
)
11183 asection
*section ATTRIBUTE_UNUSED
;
11186 static arelent
*retval
[4];
11188 bfd_reloc_code_real_type code
;
11190 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11193 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11194 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11195 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11197 if (mips_pic
== EMBEDDED_PIC
11198 && SWITCH_TABLE (fixp
))
11200 /* For a switch table entry we use a special reloc. The addend
11201 is actually the difference between the reloc address and the
11203 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11204 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11205 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11206 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11208 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11209 reloc
->addend
= fixp
->fx_addnumber
;
11210 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11212 /* We use a special addend for an internal RELLO reloc. */
11213 if (symbol_section_p (fixp
->fx_addsy
))
11214 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11216 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11218 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11220 assert (fixp
->fx_next
!= NULL
11221 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11222 /* We use a special addend for an internal RELHI reloc. The
11223 reloc is relative to the RELLO; adjust the addend
11225 if (symbol_section_p (fixp
->fx_addsy
))
11226 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11227 + fixp
->fx_next
->fx_where
11228 - S_GET_VALUE (fixp
->fx_subsy
));
11230 reloc
->addend
= (fixp
->fx_addnumber
11231 + fixp
->fx_next
->fx_frag
->fr_address
11232 + fixp
->fx_next
->fx_where
);
11236 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11237 /* A gruesome hack which is a result of the gruesome gas reloc
11239 reloc
->addend
= reloc
->address
;
11241 reloc
->addend
= -reloc
->address
;
11244 /* If this is a variant frag, we may need to adjust the existing
11245 reloc and generate a new one. */
11246 if (fixp
->fx_frag
->fr_opcode
!= NULL
11247 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11248 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11249 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11250 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11251 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11252 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11253 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11257 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11259 /* If this is not the last reloc in this frag, then we have two
11260 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11261 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11262 the second one handle all of them. */
11263 if (fixp
->fx_next
!= NULL
11264 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11266 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11267 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11268 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11269 && (fixp
->fx_next
->fx_r_type
11270 == BFD_RELOC_MIPS_GOT_LO16
))
11271 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11272 && (fixp
->fx_next
->fx_r_type
11273 == BFD_RELOC_MIPS_CALL_LO16
)));
11278 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11279 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11280 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11282 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11283 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11284 reloc2
->address
= (reloc
->address
11285 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11286 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11287 reloc2
->addend
= fixp
->fx_addnumber
;
11288 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11289 assert (reloc2
->howto
!= NULL
);
11291 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11295 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11298 reloc3
->address
+= 4;
11301 if (mips_pic
== NO_PIC
)
11303 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11304 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11306 else if (mips_pic
== SVR4_PIC
)
11308 switch (fixp
->fx_r_type
)
11312 case BFD_RELOC_MIPS_GOT16
:
11314 case BFD_RELOC_MIPS_CALL16
:
11315 case BFD_RELOC_MIPS_GOT_LO16
:
11316 case BFD_RELOC_MIPS_CALL_LO16
:
11317 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11325 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11326 to be used in the relocation's section offset. */
11327 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11329 reloc
->address
= reloc
->addend
;
11333 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11334 fixup_segment converted a non-PC relative reloc into a PC
11335 relative reloc. In such a case, we need to convert the reloc
11337 code
= fixp
->fx_r_type
;
11338 if (fixp
->fx_pcrel
)
11343 code
= BFD_RELOC_8_PCREL
;
11346 code
= BFD_RELOC_16_PCREL
;
11349 code
= BFD_RELOC_32_PCREL
;
11352 code
= BFD_RELOC_64_PCREL
;
11354 case BFD_RELOC_8_PCREL
:
11355 case BFD_RELOC_16_PCREL
:
11356 case BFD_RELOC_32_PCREL
:
11357 case BFD_RELOC_64_PCREL
:
11358 case BFD_RELOC_16_PCREL_S2
:
11359 case BFD_RELOC_PCREL_HI16_S
:
11360 case BFD_RELOC_PCREL_LO16
:
11363 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11364 _("Cannot make %s relocation PC relative"),
11365 bfd_get_reloc_code_name (code
));
11369 /* To support a PC relative reloc when generating embedded PIC code
11370 for ECOFF, we use a Cygnus extension. We check for that here to
11371 make sure that we don't let such a reloc escape normally. */
11372 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11373 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11374 && code
== BFD_RELOC_16_PCREL_S2
11375 && mips_pic
!= EMBEDDED_PIC
)
11376 reloc
->howto
= NULL
;
11378 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11380 if (reloc
->howto
== NULL
)
11382 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11383 _("Can not represent %s relocation in this object file format"),
11384 bfd_get_reloc_code_name (code
));
11391 /* Relax a machine dependent frag. This returns the amount by which
11392 the current size of the frag should change. */
11395 mips_relax_frag (fragp
, stretch
)
11399 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11402 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11404 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11406 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11411 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11413 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11420 /* Convert a machine dependent frag. */
11423 md_convert_frag (abfd
, asec
, fragp
)
11424 bfd
*abfd ATTRIBUTE_UNUSED
;
11431 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11434 register const struct mips16_immed_operand
*op
;
11435 boolean small
, ext
;
11438 unsigned long insn
;
11439 boolean use_extend
;
11440 unsigned short extend
;
11442 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11443 op
= mips16_immed_operands
;
11444 while (op
->type
!= type
)
11447 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11458 resolve_symbol_value (fragp
->fr_symbol
);
11459 val
= S_GET_VALUE (fragp
->fr_symbol
);
11464 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11466 /* The rules for the base address of a PC relative reloc are
11467 complicated; see mips16_extended_frag. */
11468 if (type
== 'p' || type
== 'q')
11473 /* Ignore the low bit in the target, since it will be
11474 set for a text label. */
11475 if ((val
& 1) != 0)
11478 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11480 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11483 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11486 /* Make sure the section winds up with the alignment we have
11489 record_alignment (asec
, op
->shift
);
11493 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11494 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11495 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11496 _("extended instruction in delay slot"));
11498 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11500 if (target_big_endian
)
11501 insn
= bfd_getb16 (buf
);
11503 insn
= bfd_getl16 (buf
);
11505 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11506 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11507 small
, ext
, &insn
, &use_extend
, &extend
);
11511 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11512 fragp
->fr_fix
+= 2;
11516 md_number_to_chars (buf
, insn
, 2);
11517 fragp
->fr_fix
+= 2;
11522 if (fragp
->fr_opcode
== NULL
)
11525 old
= RELAX_OLD (fragp
->fr_subtype
);
11526 new = RELAX_NEW (fragp
->fr_subtype
);
11527 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11530 memcpy (fixptr
- old
, fixptr
, new);
11532 fragp
->fr_fix
+= new - old
;
11538 /* This function is called after the relocs have been generated.
11539 We've been storing mips16 text labels as odd. Here we convert them
11540 back to even for the convenience of the debugger. */
11543 mips_frob_file_after_relocs ()
11546 unsigned int count
, i
;
11548 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11551 syms
= bfd_get_outsymbols (stdoutput
);
11552 count
= bfd_get_symcount (stdoutput
);
11553 for (i
= 0; i
< count
; i
++, syms
++)
11555 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11556 && ((*syms
)->value
& 1) != 0)
11558 (*syms
)->value
&= ~1;
11559 /* If the symbol has an odd size, it was probably computed
11560 incorrectly, so adjust that as well. */
11561 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11562 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11569 /* This function is called whenever a label is defined. It is used
11570 when handling branch delays; if a branch has a label, we assume we
11571 can not move it. */
11574 mips_define_label (sym
)
11577 struct insn_label_list
*l
;
11579 if (free_insn_labels
== NULL
)
11580 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11583 l
= free_insn_labels
;
11584 free_insn_labels
= l
->next
;
11588 l
->next
= insn_labels
;
11592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11594 /* Some special processing for a MIPS ELF file. */
11597 mips_elf_final_processing ()
11599 /* Write out the register information. */
11604 s
.ri_gprmask
= mips_gprmask
;
11605 s
.ri_cprmask
[0] = mips_cprmask
[0];
11606 s
.ri_cprmask
[1] = mips_cprmask
[1];
11607 s
.ri_cprmask
[2] = mips_cprmask
[2];
11608 s
.ri_cprmask
[3] = mips_cprmask
[3];
11609 /* The gp_value field is set by the MIPS ELF backend. */
11611 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11612 ((Elf32_External_RegInfo
*)
11613 mips_regmask_frag
));
11617 Elf64_Internal_RegInfo s
;
11619 s
.ri_gprmask
= mips_gprmask
;
11621 s
.ri_cprmask
[0] = mips_cprmask
[0];
11622 s
.ri_cprmask
[1] = mips_cprmask
[1];
11623 s
.ri_cprmask
[2] = mips_cprmask
[2];
11624 s
.ri_cprmask
[3] = mips_cprmask
[3];
11625 /* The gp_value field is set by the MIPS ELF backend. */
11627 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11628 ((Elf64_External_RegInfo
*)
11629 mips_regmask_frag
));
11632 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11633 sort of BFD interface for this. */
11634 if (mips_any_noreorder
)
11635 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11636 if (mips_pic
!= NO_PIC
)
11637 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11639 /* Set the MIPS ELF ABI flags. */
11640 if (mips_abi_string
== NULL
)
11642 else if (strcmp (mips_abi_string
, "32") == 0)
11643 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11644 else if (strcmp (mips_abi_string
, "o64") == 0)
11645 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11646 else if (strcmp (mips_abi_string
, "eabi") == 0)
11649 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11651 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11653 else if (strcmp (mips_abi_string
, "n32") == 0)
11654 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
11656 /* Nothing to do for "64". */
11658 if (mips_32bitmode
)
11659 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11662 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11664 typedef struct proc
{
11666 unsigned long reg_mask
;
11667 unsigned long reg_offset
;
11668 unsigned long fpreg_mask
;
11669 unsigned long fpreg_offset
;
11670 unsigned long frame_offset
;
11671 unsigned long frame_reg
;
11672 unsigned long pc_reg
;
11675 static procS cur_proc
;
11676 static procS
*cur_proc_ptr
;
11677 static int numprocs
;
11679 /* Fill in an rs_align_code fragment. */
11682 mips_handle_align (fragp
)
11685 if (fragp
->fr_type
!= rs_align_code
)
11688 if (mips_opts
.mips16
)
11690 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11691 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11696 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
11697 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
11702 fragp
->fr_fix
+= 1;
11705 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
11709 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
11720 /* check for premature end, nesting errors, etc */
11722 as_warn (_("missing .end at end of assembly"));
11731 if (*input_line_pointer
== '-')
11733 ++input_line_pointer
;
11736 if (!isdigit ((unsigned char) *input_line_pointer
))
11737 as_bad (_("Expected simple number."));
11738 if (input_line_pointer
[0] == '0')
11740 if (input_line_pointer
[1] == 'x')
11742 input_line_pointer
+= 2;
11743 while (isxdigit ((unsigned char) *input_line_pointer
))
11746 val
|= hex_value (*input_line_pointer
++);
11748 return negative
? -val
: val
;
11752 ++input_line_pointer
;
11753 while (isdigit ((unsigned char) *input_line_pointer
))
11756 val
|= *input_line_pointer
++ - '0';
11758 return negative
? -val
: val
;
11761 if (!isdigit ((unsigned char) *input_line_pointer
))
11763 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11764 *input_line_pointer
, *input_line_pointer
);
11765 as_warn (_("Invalid number"));
11768 while (isdigit ((unsigned char) *input_line_pointer
))
11771 val
+= *input_line_pointer
++ - '0';
11773 return negative
? -val
: val
;
11776 /* The .file directive; just like the usual .file directive, but there
11777 is an initial number which is the ECOFF file index. */
11781 int x ATTRIBUTE_UNUSED
;
11785 line
= get_number ();
11789 /* The .end directive. */
11793 int x ATTRIBUTE_UNUSED
;
11798 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11801 demand_empty_rest_of_line ();
11806 #ifdef BFD_ASSEMBLER
11807 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11812 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11819 as_warn (_(".end not in text section"));
11823 as_warn (_(".end directive without a preceding .ent directive."));
11824 demand_empty_rest_of_line ();
11830 assert (S_GET_NAME (p
));
11831 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11832 as_warn (_(".end symbol does not match .ent symbol."));
11835 as_warn (_(".end directive missing or unknown symbol"));
11837 #ifdef MIPS_STABS_ELF
11839 segT saved_seg
= now_seg
;
11840 subsegT saved_subseg
= now_subseg
;
11845 dot
= frag_now_fix ();
11847 #ifdef md_flush_pending_output
11848 md_flush_pending_output ();
11852 subseg_set (pdr_seg
, 0);
11854 /* Write the symbol. */
11855 exp
.X_op
= O_symbol
;
11856 exp
.X_add_symbol
= p
;
11857 exp
.X_add_number
= 0;
11858 emit_expr (&exp
, 4);
11860 fragp
= frag_more (7 * 4);
11862 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11863 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11864 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11865 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11866 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11867 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11868 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11870 subseg_set (saved_seg
, saved_subseg
);
11874 cur_proc_ptr
= NULL
;
11877 /* The .aent and .ent directives. */
11887 symbolP
= get_symbol ();
11888 if (*input_line_pointer
== ',')
11889 input_line_pointer
++;
11890 SKIP_WHITESPACE ();
11891 if (isdigit ((unsigned char) *input_line_pointer
)
11892 || *input_line_pointer
== '-')
11893 number
= get_number ();
11895 #ifdef BFD_ASSEMBLER
11896 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11901 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11908 as_warn (_(".ent or .aent not in text section."));
11910 if (!aent
&& cur_proc_ptr
)
11911 as_warn (_("missing .end"));
11915 cur_proc_ptr
= &cur_proc
;
11916 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11918 cur_proc_ptr
->isym
= symbolP
;
11920 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11925 demand_empty_rest_of_line ();
11928 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11929 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11930 s_mips_frame is used so that we can set the PDR information correctly.
11931 We can't use the ecoff routines because they make reference to the ecoff
11932 symbol table (in the mdebug section). */
11935 s_mips_frame (ignore
)
11936 int ignore ATTRIBUTE_UNUSED
;
11938 #ifdef MIPS_STABS_ELF
11942 if (cur_proc_ptr
== (procS
*) NULL
)
11944 as_warn (_(".frame outside of .ent"));
11945 demand_empty_rest_of_line ();
11949 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11951 SKIP_WHITESPACE ();
11952 if (*input_line_pointer
++ != ','
11953 || get_absolute_expression_and_terminator (&val
) != ',')
11955 as_warn (_("Bad .frame directive"));
11956 --input_line_pointer
;
11957 demand_empty_rest_of_line ();
11961 cur_proc_ptr
->frame_offset
= val
;
11962 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11964 demand_empty_rest_of_line ();
11967 #endif /* MIPS_STABS_ELF */
11970 /* The .fmask and .mask directives. If the mdebug section is present
11971 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11972 embedded targets, s_mips_mask is used so that we can set the PDR
11973 information correctly. We can't use the ecoff routines because they
11974 make reference to the ecoff symbol table (in the mdebug section). */
11977 s_mips_mask (reg_type
)
11980 #ifdef MIPS_STABS_ELF
11983 if (cur_proc_ptr
== (procS
*) NULL
)
11985 as_warn (_(".mask/.fmask outside of .ent"));
11986 demand_empty_rest_of_line ();
11990 if (get_absolute_expression_and_terminator (&mask
) != ',')
11992 as_warn (_("Bad .mask/.fmask directive"));
11993 --input_line_pointer
;
11994 demand_empty_rest_of_line ();
11998 off
= get_absolute_expression ();
12000 if (reg_type
== 'F')
12002 cur_proc_ptr
->fpreg_mask
= mask
;
12003 cur_proc_ptr
->fpreg_offset
= off
;
12007 cur_proc_ptr
->reg_mask
= mask
;
12008 cur_proc_ptr
->reg_offset
= off
;
12011 demand_empty_rest_of_line ();
12013 s_ignore (reg_type
);
12014 #endif /* MIPS_STABS_ELF */
12017 /* The .loc directive. */
12028 assert (now_seg
== text_section
);
12030 lineno
= get_number ();
12031 addroff
= frag_now_fix ();
12033 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12034 S_SET_TYPE (symbolP
, N_SLINE
);
12035 S_SET_OTHER (symbolP
, 0);
12036 S_SET_DESC (symbolP
, lineno
);
12037 symbolP
->sy_segment
= now_seg
;
12041 /* CPU name/ISA/number mapping table.
12043 Entries are grouped by type. The first matching CPU or ISA entry
12044 gets chosen by CPU or ISA, so it should be the 'canonical' name
12045 for that type. Entries after that within the type are sorted
12048 Case is ignored in comparison, so put the canonical entry in the
12049 appropriate case but everything else in lower case to ease eye pain. */
12050 static const struct mips_cpu_info mips_cpu_info_table
[] =
12053 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12054 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12057 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12060 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12063 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12066 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12067 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12070 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12071 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12074 /* XXX for now, MIPS64 -> MIPS3 because of history */
12075 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
}, /* XXX! */
12078 { "MIPS64", 1, ISA_MIPS64
, CPU_MIPS64
},
12080 { "mips64isa", 1, ISA_MIPS64
, CPU_MIPS64
},
12081 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12084 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12085 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12086 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12087 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12090 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
12091 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
12092 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
12093 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12096 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12097 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12098 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12101 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12102 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12103 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12104 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12107 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12108 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12111 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12112 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12115 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12116 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12117 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12118 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12121 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12122 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12125 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12126 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12127 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12128 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12131 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12132 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12133 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12134 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12137 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12138 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12139 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12140 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12143 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
12144 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
12145 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
12146 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
12149 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12150 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12151 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12152 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12155 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12156 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12157 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12158 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12161 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12162 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12163 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12164 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12167 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12168 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12169 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12170 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12171 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12172 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12173 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
12174 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12175 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
12176 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12177 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
12178 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12179 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
12180 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12181 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
12182 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12183 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12185 /* MIPS32 4K CPU */
12186 { "MIPS32-4K", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12187 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12188 { "4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12189 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12190 { "mips32-4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12191 { "mips32-4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12192 { "mips32-4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12194 /* SiByte SB-1 CPU */
12195 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12196 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12197 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12198 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12201 { NULL
, 0, 0, 0, },
12204 static const struct mips_cpu_info
*
12205 mips_cpu_info_from_name (name
)
12210 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12211 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12212 return (&mips_cpu_info_table
[i
]);
12217 static const struct mips_cpu_info
*
12218 mips_cpu_info_from_isa (isa
)
12223 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12224 if (mips_cpu_info_table
[i
].is_isa
12225 && isa
== mips_cpu_info_table
[i
].isa
)
12226 return (&mips_cpu_info_table
[i
]);
12231 static const struct mips_cpu_info
*
12232 mips_cpu_info_from_cpu (cpu
)
12237 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12238 if (!mips_cpu_info_table
[i
].is_isa
12239 && cpu
== mips_cpu_info_table
[i
].cpu
)
12240 return (&mips_cpu_info_table
[i
]);