1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 extern int target_big_endian
;
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME ".rodata"
114 /* Ways in which an instruction can be "appended" to the output. */
116 /* Just add it normally. */
119 /* Add it normally and then add a nop. */
122 /* Turn an instruction with a delay slot into a "compact" version. */
125 /* Insert the instruction before the last one. */
129 /* Information about an instruction, including its format, operands
133 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
134 const struct mips_opcode
*insn_mo
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. If we have
138 decided to use an extended MIPS16 instruction, this includes the
140 unsigned long insn_opcode
;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p
: 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p
: 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p
: 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p
: 1;
163 /* True if this instruction is cleared from history by unconditional
165 unsigned int cleared_p
: 1;
168 /* The ABI to use. */
179 /* MIPS ABI we are using for this output file. */
180 static enum mips_abi_level mips_abi
= NO_ABI
;
182 /* Whether or not we have code that can call pic code. */
183 int mips_abicalls
= FALSE
;
185 /* Whether or not we have code which can be put into a shared
187 static bfd_boolean mips_in_shared
= TRUE
;
189 /* This is the set of options which may be modified by the .set
190 pseudo-op. We use a struct so that .set push and .set pop are more
193 struct mips_set_options
195 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
196 if it has not been initialized. Changed by `.set mipsN', and the
197 -mipsN command line option, and the default CPU. */
199 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
200 <asename>', by command line options, and based on the default
203 /* Whether we are assembling for the mips16 processor. 0 if we are
204 not, 1 if we are, and -1 if the value has not been initialized.
205 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
206 -nomips16 command line options, and the default CPU. */
208 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
209 1 if we are, and -1 if the value has not been initialized. Changed
210 by `.set micromips' and `.set nomicromips', and the -mmicromips
211 and -mno-micromips command line options, and the default CPU. */
213 /* Non-zero if we should not reorder instructions. Changed by `.set
214 reorder' and `.set noreorder'. */
216 /* Non-zero if we should not permit the register designated "assembler
217 temporary" to be used in instructions. The value is the register
218 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
219 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
221 /* Non-zero if we should warn when a macro instruction expands into
222 more than one machine instruction. Changed by `.set nomacro' and
224 int warn_about_macros
;
225 /* Non-zero if we should not move instructions. Changed by `.set
226 move', `.set volatile', `.set nomove', and `.set novolatile'. */
228 /* Non-zero if we should not optimize branches by moving the target
229 of the branch into the delay slot. Actually, we don't perform
230 this optimization anyhow. Changed by `.set bopt' and `.set
233 /* Non-zero if we should not autoextend mips16 instructions.
234 Changed by `.set autoextend' and `.set noautoextend'. */
236 /* Restrict general purpose registers and floating point registers
237 to 32 bit. This is initially determined when -mgp32 or -mfp32
238 is passed but can changed if the assembler code uses .set mipsN. */
241 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
242 command line option, and the default CPU. */
244 /* True if ".set sym32" is in effect. */
246 /* True if floating-point operations are not allowed. Changed by .set
247 softfloat or .set hardfloat, by command line options -msoft-float or
248 -mhard-float. The default is false. */
249 bfd_boolean soft_float
;
251 /* True if only single-precision floating-point operations are allowed.
252 Changed by .set singlefloat or .set doublefloat, command-line options
253 -msingle-float or -mdouble-float. The default is false. */
254 bfd_boolean single_float
;
257 /* This is the struct we use to hold the current set of options. Note
258 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
259 -1 to indicate that they have not been initialized. */
261 /* True if -mgp32 was passed. */
262 static int file_mips_gp32
= -1;
264 /* True if -mfp32 was passed. */
265 static int file_mips_fp32
= -1;
267 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
268 static int file_mips_soft_float
= 0;
270 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
271 static int file_mips_single_float
= 0;
273 static struct mips_set_options mips_opts
=
275 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
276 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
277 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
278 /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
279 /* soft_float */ FALSE
, /* single_float */ FALSE
282 /* The set of ASEs that were selected on the command line, either
283 explicitly via ASE options or implicitly through things like -march. */
284 static unsigned int file_ase
;
286 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
287 static unsigned int file_ase_explicit
;
289 /* These variables are filled in with the masks of registers used.
290 The object format code reads them and puts them in the appropriate
292 unsigned long mips_gprmask
;
293 unsigned long mips_cprmask
[4];
295 /* MIPS ISA we are using for this output file. */
296 static int file_mips_isa
= ISA_UNKNOWN
;
298 /* True if any MIPS16 code was produced. */
299 static int file_ase_mips16
;
301 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
302 || mips_opts.isa == ISA_MIPS32R2 \
303 || mips_opts.isa == ISA_MIPS64 \
304 || mips_opts.isa == ISA_MIPS64R2)
306 /* True if any microMIPS code was produced. */
307 static int file_ase_micromips
;
309 /* True if we want to create R_MIPS_JALR for jalr $25. */
311 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
313 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
314 because there's no place for any addend, the only acceptable
315 expression is a bare symbol. */
316 #define MIPS_JALR_HINT_P(EXPR) \
317 (!HAVE_IN_PLACE_ADDENDS \
318 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
321 /* The argument of the -march= flag. The architecture we are assembling. */
322 static int file_mips_arch
= CPU_UNKNOWN
;
323 static const char *mips_arch_string
;
325 /* The argument of the -mtune= flag. The architecture for which we
327 static int mips_tune
= CPU_UNKNOWN
;
328 static const char *mips_tune_string
;
330 /* True when generating 32-bit code for a 64-bit processor. */
331 static int mips_32bitmode
= 0;
333 /* True if the given ABI requires 32-bit registers. */
334 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
336 /* Likewise 64-bit registers. */
337 #define ABI_NEEDS_64BIT_REGS(ABI) \
339 || (ABI) == N64_ABI \
342 /* Return true if ISA supports 64 bit wide gp registers. */
343 #define ISA_HAS_64BIT_REGS(ISA) \
344 ((ISA) == ISA_MIPS3 \
345 || (ISA) == ISA_MIPS4 \
346 || (ISA) == ISA_MIPS5 \
347 || (ISA) == ISA_MIPS64 \
348 || (ISA) == ISA_MIPS64R2)
350 /* Return true if ISA supports 64 bit wide float registers. */
351 #define ISA_HAS_64BIT_FPRS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS32R2 \
356 || (ISA) == ISA_MIPS64 \
357 || (ISA) == ISA_MIPS64R2)
359 /* Return true if ISA supports 64-bit right rotate (dror et al.)
361 #define ISA_HAS_DROR(ISA) \
362 ((ISA) == ISA_MIPS64R2 \
363 || (mips_opts.micromips \
364 && ISA_HAS_64BIT_REGS (ISA)) \
367 /* Return true if ISA supports 32-bit right rotate (ror et al.)
369 #define ISA_HAS_ROR(ISA) \
370 ((ISA) == ISA_MIPS32R2 \
371 || (ISA) == ISA_MIPS64R2 \
372 || (mips_opts.ase & ASE_SMARTMIPS) \
373 || mips_opts.micromips \
376 /* Return true if ISA supports single-precision floats in odd registers. */
377 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
378 ((ISA) == ISA_MIPS32 \
379 || (ISA) == ISA_MIPS32R2 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2)
383 /* Return true if ISA supports move to/from high part of a 64-bit
384 floating-point register. */
385 #define ISA_HAS_MXHC1(ISA) \
386 ((ISA) == ISA_MIPS32R2 \
387 || (ISA) == ISA_MIPS64R2)
389 #define HAVE_32BIT_GPRS \
390 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
392 #define HAVE_32BIT_FPRS \
393 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
395 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
396 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
398 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
400 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
402 /* True if relocations are stored in-place. */
403 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
405 /* The ABI-derived address size. */
406 #define HAVE_64BIT_ADDRESSES \
407 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
408 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
410 /* The size of symbolic constants (i.e., expressions of the form
411 "SYMBOL" or "SYMBOL + OFFSET"). */
412 #define HAVE_32BIT_SYMBOLS \
413 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
414 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
416 /* Addresses are loaded in different ways, depending on the address size
417 in use. The n32 ABI Documentation also mandates the use of additions
418 with overflow checking, but existing implementations don't follow it. */
419 #define ADDRESS_ADD_INSN \
420 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
422 #define ADDRESS_ADDI_INSN \
423 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
425 #define ADDRESS_LOAD_INSN \
426 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
428 #define ADDRESS_STORE_INSN \
429 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
431 /* Return true if the given CPU supports the MIPS16 ASE. */
432 #define CPU_HAS_MIPS16(cpu) \
433 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
434 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
436 /* Return true if the given CPU supports the microMIPS ASE. */
437 #define CPU_HAS_MICROMIPS(cpu) 0
439 /* True if CPU has a dror instruction. */
440 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
442 /* True if CPU has a ror instruction. */
443 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
445 /* True if CPU is in the Octeon family */
446 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
448 /* True if CPU has seq/sne and seqi/snei instructions. */
449 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
451 /* True, if CPU has support for ldc1 and sdc1. */
452 #define CPU_HAS_LDC1_SDC1(CPU) \
453 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R5900 \
474 || mips_opts.arch == CPU_R10000 \
475 || mips_opts.arch == CPU_R12000 \
476 || mips_opts.arch == CPU_R14000 \
477 || mips_opts.arch == CPU_R16000 \
478 || mips_opts.arch == CPU_RM7000 \
479 || mips_opts.arch == CPU_VR5500 \
480 || mips_opts.micromips \
483 /* Whether the processor uses hardware interlocks to protect reads
484 from the GPRs after they are loaded from memory, and thus does not
485 require nops to be inserted. This applies to instructions marked
486 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
487 level I and microMIPS mode instructions are always interlocked. */
488 #define gpr_interlocks \
489 (mips_opts.isa != ISA_MIPS1 \
490 || mips_opts.arch == CPU_R3900 \
491 || mips_opts.arch == CPU_R5900 \
492 || mips_opts.micromips \
495 /* Whether the processor uses hardware interlocks to avoid delays
496 required by coprocessor instructions, and thus does not require
497 nops to be inserted. This applies to instructions marked
498 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
499 between instructions marked INSN_WRITE_COND_CODE and ones marked
500 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
501 levels I, II, and III and microMIPS mode instructions are always
503 /* Itbl support may require additional care here. */
504 #define cop_interlocks \
505 ((mips_opts.isa != ISA_MIPS1 \
506 && mips_opts.isa != ISA_MIPS2 \
507 && mips_opts.isa != ISA_MIPS3) \
508 || mips_opts.arch == CPU_R4300 \
509 || mips_opts.micromips \
512 /* Whether the processor uses hardware interlocks to protect reads
513 from coprocessor registers after they are loaded from memory, and
514 thus does not require nops to be inserted. This applies to
515 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
516 requires at MIPS ISA level I and microMIPS mode instructions are
517 always interlocked. */
518 #define cop_mem_interlocks \
519 (mips_opts.isa != ISA_MIPS1 \
520 || mips_opts.micromips \
523 /* Is this a mfhi or mflo instruction? */
524 #define MF_HILO_INSN(PINFO) \
525 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
527 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
528 has been selected. This implies, in particular, that addresses of text
529 labels have their LSB set. */
530 #define HAVE_CODE_COMPRESSION \
531 ((mips_opts.mips16 | mips_opts.micromips) != 0)
533 /* MIPS PIC level. */
535 enum mips_pic_level mips_pic
;
537 /* 1 if we should generate 32 bit offsets from the $gp register in
538 SVR4_PIC mode. Currently has no meaning in other modes. */
539 static int mips_big_got
= 0;
541 /* 1 if trap instructions should used for overflow rather than break
543 static int mips_trap
= 0;
545 /* 1 if double width floating point constants should not be constructed
546 by assembling two single width halves into two single width floating
547 point registers which just happen to alias the double width destination
548 register. On some architectures this aliasing can be disabled by a bit
549 in the status register, and the setting of this bit cannot be determined
550 automatically at assemble time. */
551 static int mips_disable_float_construction
;
553 /* Non-zero if any .set noreorder directives were used. */
555 static int mips_any_noreorder
;
557 /* Non-zero if nops should be inserted when the register referenced in
558 an mfhi/mflo instruction is read in the next two instructions. */
559 static int mips_7000_hilo_fix
;
561 /* The size of objects in the small data section. */
562 static unsigned int g_switch_value
= 8;
563 /* Whether the -G option was used. */
564 static int g_switch_seen
= 0;
569 /* If we can determine in advance that GP optimization won't be
570 possible, we can skip the relaxation stuff that tries to produce
571 GP-relative references. This makes delay slot optimization work
574 This function can only provide a guess, but it seems to work for
575 gcc output. It needs to guess right for gcc, otherwise gcc
576 will put what it thinks is a GP-relative instruction in a branch
579 I don't know if a fix is needed for the SVR4_PIC mode. I've only
580 fixed it for the non-PIC mode. KR 95/04/07 */
581 static int nopic_need_relax (symbolS
*, int);
583 /* handle of the OPCODE hash table */
584 static struct hash_control
*op_hash
= NULL
;
586 /* The opcode hash table we use for the mips16. */
587 static struct hash_control
*mips16_op_hash
= NULL
;
589 /* The opcode hash table we use for the microMIPS ASE. */
590 static struct hash_control
*micromips_op_hash
= NULL
;
592 /* This array holds the chars that always start a comment. If the
593 pre-processor is disabled, these aren't very useful */
594 const char comment_chars
[] = "#";
596 /* This array holds the chars that only start a comment at the beginning of
597 a line. If the line seems to have the form '# 123 filename'
598 .line and .file directives will appear in the pre-processed output */
599 /* Note that input_file.c hand checks for '#' at the beginning of the
600 first line of the input file. This is because the compiler outputs
601 #NO_APP at the beginning of its output. */
602 /* Also note that C style comments are always supported. */
603 const char line_comment_chars
[] = "#";
605 /* This array holds machine specific line separator characters. */
606 const char line_separator_chars
[] = ";";
608 /* Chars that can be used to separate mant from exp in floating point nums */
609 const char EXP_CHARS
[] = "eE";
611 /* Chars that mean this number is a floating point constant */
614 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
616 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
617 changed in read.c . Ideally it shouldn't have to know about it at all,
618 but nothing is ideal around here.
621 static char *insn_error
;
623 static int auto_align
= 1;
625 /* When outputting SVR4 PIC code, the assembler needs to know the
626 offset in the stack frame from which to restore the $gp register.
627 This is set by the .cprestore pseudo-op, and saved in this
629 static offsetT mips_cprestore_offset
= -1;
631 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
632 more optimizations, it can use a register value instead of a memory-saved
633 offset and even an other register than $gp as global pointer. */
634 static offsetT mips_cpreturn_offset
= -1;
635 static int mips_cpreturn_register
= -1;
636 static int mips_gp_register
= GP
;
637 static int mips_gprel_offset
= 0;
639 /* Whether mips_cprestore_offset has been set in the current function
640 (or whether it has already been warned about, if not). */
641 static int mips_cprestore_valid
= 0;
643 /* This is the register which holds the stack frame, as set by the
644 .frame pseudo-op. This is needed to implement .cprestore. */
645 static int mips_frame_reg
= SP
;
647 /* Whether mips_frame_reg has been set in the current function
648 (or whether it has already been warned about, if not). */
649 static int mips_frame_reg_valid
= 0;
651 /* To output NOP instructions correctly, we need to keep information
652 about the previous two instructions. */
654 /* Whether we are optimizing. The default value of 2 means to remove
655 unneeded NOPs and swap branch instructions when possible. A value
656 of 1 means to not swap branches. A value of 0 means to always
658 static int mips_optimize
= 2;
660 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
661 equivalent to seeing no -g option at all. */
662 static int mips_debug
= 0;
664 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
665 #define MAX_VR4130_NOPS 4
667 /* The maximum number of NOPs needed to fill delay slots. */
668 #define MAX_DELAY_NOPS 2
670 /* The maximum number of NOPs needed for any purpose. */
673 /* A list of previous instructions, with index 0 being the most recent.
674 We need to look back MAX_NOPS instructions when filling delay slots
675 or working around processor errata. We need to look back one
676 instruction further if we're thinking about using history[0] to
677 fill a branch delay slot. */
678 static struct mips_cl_insn history
[1 + MAX_NOPS
];
680 /* Nop instructions used by emit_nop. */
681 static struct mips_cl_insn nop_insn
;
682 static struct mips_cl_insn mips16_nop_insn
;
683 static struct mips_cl_insn micromips_nop16_insn
;
684 static struct mips_cl_insn micromips_nop32_insn
;
686 /* The appropriate nop for the current mode. */
687 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
688 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
690 /* The size of NOP_INSN in bytes. */
691 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
693 /* If this is set, it points to a frag holding nop instructions which
694 were inserted before the start of a noreorder section. If those
695 nops turn out to be unnecessary, the size of the frag can be
697 static fragS
*prev_nop_frag
;
699 /* The number of nop instructions we created in prev_nop_frag. */
700 static int prev_nop_frag_holds
;
702 /* The number of nop instructions that we know we need in
704 static int prev_nop_frag_required
;
706 /* The number of instructions we've seen since prev_nop_frag. */
707 static int prev_nop_frag_since
;
709 /* Relocations against symbols are sometimes done in two parts, with a HI
710 relocation and a LO relocation. Each relocation has only 16 bits of
711 space to store an addend. This means that in order for the linker to
712 handle carries correctly, it must be able to locate both the HI and
713 the LO relocation. This means that the relocations must appear in
714 order in the relocation table.
716 In order to implement this, we keep track of each unmatched HI
717 relocation. We then sort them so that they immediately precede the
718 corresponding LO relocation. */
723 struct mips_hi_fixup
*next
;
726 /* The section this fixup is in. */
730 /* The list of unmatched HI relocs. */
732 static struct mips_hi_fixup
*mips_hi_fixup_list
;
734 /* The frag containing the last explicit relocation operator.
735 Null if explicit relocations have not been used. */
737 static fragS
*prev_reloc_op_frag
;
739 /* Map normal MIPS register numbers to mips16 register numbers. */
741 #define X ILLEGAL_REG
742 static const int mips32_to_16_reg_map
[] =
744 X
, X
, 2, 3, 4, 5, 6, 7,
745 X
, X
, X
, X
, X
, X
, X
, X
,
746 0, 1, X
, X
, X
, X
, X
, X
,
747 X
, X
, X
, X
, X
, X
, X
, X
751 /* Map mips16 register numbers to normal MIPS register numbers. */
753 static const unsigned int mips16_to_32_reg_map
[] =
755 16, 17, 2, 3, 4, 5, 6, 7
758 /* Map normal MIPS register numbers to microMIPS register numbers. */
760 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
761 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
762 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
763 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
764 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
765 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
766 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
768 #define X ILLEGAL_REG
769 /* reg type h: 4, 5, 6. */
770 static const int mips32_to_micromips_reg_h_map
[] =
772 X
, X
, X
, X
, 4, 5, 6, X
,
773 X
, X
, X
, X
, X
, X
, X
, X
,
774 X
, X
, X
, X
, X
, X
, X
, X
,
775 X
, X
, X
, X
, X
, X
, X
, X
778 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
779 static const int mips32_to_micromips_reg_m_map
[] =
781 0, X
, 2, 3, X
, X
, X
, X
,
782 X
, X
, X
, X
, X
, X
, X
, X
,
783 4, 1, 5, 6, 7, X
, X
, X
,
784 X
, X
, X
, X
, X
, X
, X
, X
787 /* reg type q: 0, 2-7. 17. */
788 static const int mips32_to_micromips_reg_q_map
[] =
790 0, X
, 2, 3, 4, 5, 6, 7,
791 X
, X
, X
, X
, X
, X
, X
, X
,
792 X
, 1, X
, X
, X
, X
, X
, X
,
793 X
, X
, X
, X
, X
, X
, X
, X
796 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
799 /* Map microMIPS register numbers to normal MIPS register numbers. */
801 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
802 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
803 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
804 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
805 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
806 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
808 /* The microMIPS registers with type h. */
809 static const unsigned int micromips_to_32_reg_h_map
[] =
811 5, 5, 6, 4, 4, 4, 4, 4
814 /* The microMIPS registers with type i. */
815 static const unsigned int micromips_to_32_reg_i_map
[] =
817 6, 7, 7, 21, 22, 5, 6, 7
820 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
822 /* The microMIPS registers with type m. */
823 static const unsigned int micromips_to_32_reg_m_map
[] =
825 0, 17, 2, 3, 16, 18, 19, 20
828 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
830 /* The microMIPS registers with type q. */
831 static const unsigned int micromips_to_32_reg_q_map
[] =
833 0, 17, 2, 3, 4, 5, 6, 7
836 /* microMIPS imm type B. */
837 static const int micromips_imm_b_map
[] =
839 1, 4, 8, 12, 16, 20, 24, -1
842 /* microMIPS imm type C. */
843 static const int micromips_imm_c_map
[] =
845 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
848 /* Classifies the kind of instructions we're interested in when
849 implementing -mfix-vr4120. */
850 enum fix_vr4120_class
858 NUM_FIX_VR4120_CLASSES
861 /* ...likewise -mfix-loongson2f-jump. */
862 static bfd_boolean mips_fix_loongson2f_jump
;
864 /* ...likewise -mfix-loongson2f-nop. */
865 static bfd_boolean mips_fix_loongson2f_nop
;
867 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
868 static bfd_boolean mips_fix_loongson2f
;
870 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
871 there must be at least one other instruction between an instruction
872 of type X and an instruction of type Y. */
873 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
875 /* True if -mfix-vr4120 is in force. */
876 static int mips_fix_vr4120
;
878 /* ...likewise -mfix-vr4130. */
879 static int mips_fix_vr4130
;
881 /* ...likewise -mfix-24k. */
882 static int mips_fix_24k
;
884 /* ...likewise -mfix-cn63xxp1 */
885 static bfd_boolean mips_fix_cn63xxp1
;
887 /* We don't relax branches by default, since this causes us to expand
888 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
889 fail to compute the offset before expanding the macro to the most
890 efficient expansion. */
892 static int mips_relax_branch
;
894 /* The expansion of many macros depends on the type of symbol that
895 they refer to. For example, when generating position-dependent code,
896 a macro that refers to a symbol may have two different expansions,
897 one which uses GP-relative addresses and one which uses absolute
898 addresses. When generating SVR4-style PIC, a macro may have
899 different expansions for local and global symbols.
901 We handle these situations by generating both sequences and putting
902 them in variant frags. In position-dependent code, the first sequence
903 will be the GP-relative one and the second sequence will be the
904 absolute one. In SVR4 PIC, the first sequence will be for global
905 symbols and the second will be for local symbols.
907 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
908 SECOND are the lengths of the two sequences in bytes. These fields
909 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
910 the subtype has the following flags:
913 Set if it has been decided that we should use the second
914 sequence instead of the first.
917 Set in the first variant frag if the macro's second implementation
918 is longer than its first. This refers to the macro as a whole,
919 not an individual relaxation.
922 Set in the first variant frag if the macro appeared in a .set nomacro
923 block and if one alternative requires a warning but the other does not.
926 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
929 RELAX_DELAY_SLOT_16BIT
930 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
933 RELAX_DELAY_SLOT_SIZE_FIRST
934 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
935 the macro is of the wrong size for the branch delay slot.
937 RELAX_DELAY_SLOT_SIZE_SECOND
938 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
939 the macro is of the wrong size for the branch delay slot.
941 The frag's "opcode" points to the first fixup for relaxable code.
943 Relaxable macros are generated using a sequence such as:
945 relax_start (SYMBOL);
946 ... generate first expansion ...
948 ... generate second expansion ...
951 The code and fixups for the unwanted alternative are discarded
952 by md_convert_frag. */
953 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
955 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
956 #define RELAX_SECOND(X) ((X) & 0xff)
957 #define RELAX_USE_SECOND 0x10000
958 #define RELAX_SECOND_LONGER 0x20000
959 #define RELAX_NOMACRO 0x40000
960 #define RELAX_DELAY_SLOT 0x80000
961 #define RELAX_DELAY_SLOT_16BIT 0x100000
962 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
963 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
965 /* Branch without likely bit. If label is out of range, we turn:
967 beq reg1, reg2, label
977 with the following opcode replacements:
984 bltzal <-> bgezal (with jal label instead of j label)
986 Even though keeping the delay slot instruction in the delay slot of
987 the branch would be more efficient, it would be very tricky to do
988 correctly, because we'd have to introduce a variable frag *after*
989 the delay slot instruction, and expand that instead. Let's do it
990 the easy way for now, even if the branch-not-taken case now costs
991 one additional instruction. Out-of-range branches are not supposed
992 to be common, anyway.
994 Branch likely. If label is out of range, we turn:
996 beql reg1, reg2, label
997 delay slot (annulled if branch not taken)
1006 delay slot (executed only if branch taken)
1009 It would be possible to generate a shorter sequence by losing the
1010 likely bit, generating something like:
1015 delay slot (executed only if branch taken)
1027 bltzall -> bgezal (with jal label instead of j label)
1028 bgezall -> bltzal (ditto)
1031 but it's not clear that it would actually improve performance. */
1032 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1033 ((relax_substateT) \
1036 | ((toofar) ? 0x20 : 0) \
1037 | ((link) ? 0x40 : 0) \
1038 | ((likely) ? 0x80 : 0) \
1039 | ((uncond) ? 0x100 : 0)))
1040 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1041 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1042 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1043 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1044 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1045 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1047 /* For mips16 code, we use an entirely different form of relaxation.
1048 mips16 supports two versions of most instructions which take
1049 immediate values: a small one which takes some small value, and a
1050 larger one which takes a 16 bit value. Since branches also follow
1051 this pattern, relaxing these values is required.
1053 We can assemble both mips16 and normal MIPS code in a single
1054 object. Therefore, we need to support this type of relaxation at
1055 the same time that we support the relaxation described above. We
1056 use the high bit of the subtype field to distinguish these cases.
1058 The information we store for this type of relaxation is the
1059 argument code found in the opcode file for this relocation, whether
1060 the user explicitly requested a small or extended form, and whether
1061 the relocation is in a jump or jal delay slot. That tells us the
1062 size of the value, and how it should be stored. We also store
1063 whether the fragment is considered to be extended or not. We also
1064 store whether this is known to be a branch to a different section,
1065 whether we have tried to relax this frag yet, and whether we have
1066 ever extended a PC relative fragment because of a shift count. */
1067 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1070 | ((small) ? 0x100 : 0) \
1071 | ((ext) ? 0x200 : 0) \
1072 | ((dslot) ? 0x400 : 0) \
1073 | ((jal_dslot) ? 0x800 : 0))
1074 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1075 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1076 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1077 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1078 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1079 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1080 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1081 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1082 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1083 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1084 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1085 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1087 /* For microMIPS code, we use relaxation similar to one we use for
1088 MIPS16 code. Some instructions that take immediate values support
1089 two encodings: a small one which takes some small value, and a
1090 larger one which takes a 16 bit value. As some branches also follow
1091 this pattern, relaxing these values is required.
1093 We can assemble both microMIPS and normal MIPS code in a single
1094 object. Therefore, we need to support this type of relaxation at
1095 the same time that we support the relaxation described above. We
1096 use one of the high bits of the subtype field to distinguish these
1099 The information we store for this type of relaxation is the argument
1100 code found in the opcode file for this relocation, the register
1101 selected as the assembler temporary, whether the branch is
1102 unconditional, whether it is compact, whether it stores the link
1103 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1104 branches to a sequence of instructions is enabled, and whether the
1105 displacement of a branch is too large to fit as an immediate argument
1106 of a 16-bit and a 32-bit branch, respectively. */
1107 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1108 relax32, toofar16, toofar32) \
1111 | (((at) & 0x1f) << 8) \
1112 | ((uncond) ? 0x2000 : 0) \
1113 | ((compact) ? 0x4000 : 0) \
1114 | ((link) ? 0x8000 : 0) \
1115 | ((relax32) ? 0x10000 : 0) \
1116 | ((toofar16) ? 0x20000 : 0) \
1117 | ((toofar32) ? 0x40000 : 0))
1118 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1119 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1120 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1121 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1122 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1123 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1124 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1126 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1127 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1128 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1129 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1130 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1131 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1133 /* Sign-extend 16-bit value X. */
1134 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1136 /* Is the given value a sign-extended 32-bit value? */
1137 #define IS_SEXT_32BIT_NUM(x) \
1138 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1139 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1141 /* Is the given value a sign-extended 16-bit value? */
1142 #define IS_SEXT_16BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1146 /* Is the given value a sign-extended 12-bit value? */
1147 #define IS_SEXT_12BIT_NUM(x) \
1148 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1150 /* Is the given value a sign-extended 9-bit value? */
1151 #define IS_SEXT_9BIT_NUM(x) \
1152 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1154 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1155 #define IS_ZEXT_32BIT_NUM(x) \
1156 (((x) &~ (offsetT) 0xffffffff) == 0 \
1157 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1159 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1160 VALUE << SHIFT. VALUE is evaluated exactly once. */
1161 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1162 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1163 | (((VALUE) & (MASK)) << (SHIFT)))
1165 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1167 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1168 (((STRUCT) >> (SHIFT)) & (MASK))
1170 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1171 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1173 include/opcode/mips.h specifies operand fields using the macros
1174 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1175 with "MIPS16OP" instead of "OP". */
1176 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1179 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1180 OP_MASK_##FIELD, OP_SH_##FIELD); \
1182 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1183 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1185 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1186 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1187 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1189 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1190 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1192 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1193 : EXTRACT_BITS ((INSN).insn_opcode, \
1194 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1195 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1196 EXTRACT_BITS ((INSN).insn_opcode, \
1197 MIPS16OP_MASK_##FIELD, \
1198 MIPS16OP_SH_##FIELD)
1200 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1201 #define MIPS16_EXTEND (0xf000U << 16)
1203 /* Whether or not we are emitting a branch-likely macro. */
1204 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1206 /* Global variables used when generating relaxable macros. See the
1207 comment above RELAX_ENCODE for more details about how relaxation
1210 /* 0 if we're not emitting a relaxable macro.
1211 1 if we're emitting the first of the two relaxation alternatives.
1212 2 if we're emitting the second alternative. */
1215 /* The first relaxable fixup in the current frag. (In other words,
1216 the first fixup that refers to relaxable code.) */
1219 /* sizes[0] says how many bytes of the first alternative are stored in
1220 the current frag. Likewise sizes[1] for the second alternative. */
1221 unsigned int sizes
[2];
1223 /* The symbol on which the choice of sequence depends. */
1227 /* Global variables used to decide whether a macro needs a warning. */
1229 /* True if the macro is in a branch delay slot. */
1230 bfd_boolean delay_slot_p
;
1232 /* Set to the length in bytes required if the macro is in a delay slot
1233 that requires a specific length of instruction, otherwise zero. */
1234 unsigned int delay_slot_length
;
1236 /* For relaxable macros, sizes[0] is the length of the first alternative
1237 in bytes and sizes[1] is the length of the second alternative.
1238 For non-relaxable macros, both elements give the length of the
1240 unsigned int sizes
[2];
1242 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1243 instruction of the first alternative in bytes and first_insn_sizes[1]
1244 is the length of the first instruction of the second alternative.
1245 For non-relaxable macros, both elements give the length of the first
1246 instruction in bytes.
1248 Set to zero if we haven't yet seen the first instruction. */
1249 unsigned int first_insn_sizes
[2];
1251 /* For relaxable macros, insns[0] is the number of instructions for the
1252 first alternative and insns[1] is the number of instructions for the
1255 For non-relaxable macros, both elements give the number of
1256 instructions for the macro. */
1257 unsigned int insns
[2];
1259 /* The first variant frag for this macro. */
1261 } mips_macro_warning
;
1263 /* Prototypes for static functions. */
1265 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1267 static void append_insn
1268 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1269 bfd_boolean expansionp
);
1270 static void mips_no_prev_insn (void);
1271 static void macro_build (expressionS
*, const char *, const char *, ...);
1272 static void mips16_macro_build
1273 (expressionS
*, const char *, const char *, va_list *);
1274 static void load_register (int, expressionS
*, int);
1275 static void macro_start (void);
1276 static void macro_end (void);
1277 static void macro (struct mips_cl_insn
* ip
);
1278 static void mips16_macro (struct mips_cl_insn
* ip
);
1279 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1280 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1281 static void mips16_immed
1282 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1283 unsigned int, unsigned long *);
1284 static size_t my_getSmallExpression
1285 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1286 static void my_getExpression (expressionS
*, char *);
1287 static void s_align (int);
1288 static void s_change_sec (int);
1289 static void s_change_section (int);
1290 static void s_cons (int);
1291 static void s_float_cons (int);
1292 static void s_mips_globl (int);
1293 static void s_option (int);
1294 static void s_mipsset (int);
1295 static void s_abicalls (int);
1296 static void s_cpload (int);
1297 static void s_cpsetup (int);
1298 static void s_cplocal (int);
1299 static void s_cprestore (int);
1300 static void s_cpreturn (int);
1301 static void s_dtprelword (int);
1302 static void s_dtpreldword (int);
1303 static void s_tprelword (int);
1304 static void s_tpreldword (int);
1305 static void s_gpvalue (int);
1306 static void s_gpword (int);
1307 static void s_gpdword (int);
1308 static void s_ehword (int);
1309 static void s_cpadd (int);
1310 static void s_insn (int);
1311 static void md_obj_begin (void);
1312 static void md_obj_end (void);
1313 static void s_mips_ent (int);
1314 static void s_mips_end (int);
1315 static void s_mips_frame (int);
1316 static void s_mips_mask (int reg_type
);
1317 static void s_mips_stab (int);
1318 static void s_mips_weakext (int);
1319 static void s_mips_file (int);
1320 static void s_mips_loc (int);
1321 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1322 static int relaxed_branch_length (fragS
*, asection
*, int);
1323 static int validate_mips_insn (const struct mips_opcode
*);
1324 static int validate_micromips_insn (const struct mips_opcode
*);
1325 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1326 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1328 /* Table and functions used to map between CPU/ISA names, and
1329 ISA levels, and CPU numbers. */
1331 struct mips_cpu_info
1333 const char *name
; /* CPU or ISA name. */
1334 int flags
; /* MIPS_CPU_* flags. */
1335 int ase
; /* Set of ASEs implemented by the CPU. */
1336 int isa
; /* ISA level. */
1337 int cpu
; /* CPU number (default CPU if ISA). */
1340 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1342 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1343 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1344 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1346 /* Command-line options. */
1347 const char *md_shortopts
= "O::g::G:";
1351 OPTION_MARCH
= OPTION_MD_BASE
,
1375 OPTION_NO_SMARTMIPS
,
1381 OPTION_NO_MICROMIPS
,
1384 OPTION_COMPAT_ARCH_BASE
,
1393 OPTION_M7000_HILO_FIX
,
1394 OPTION_MNO_7000_HILO_FIX
,
1397 OPTION_FIX_LOONGSON2F_JUMP
,
1398 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1399 OPTION_FIX_LOONGSON2F_NOP
,
1400 OPTION_NO_FIX_LOONGSON2F_NOP
,
1402 OPTION_NO_FIX_VR4120
,
1404 OPTION_NO_FIX_VR4130
,
1405 OPTION_FIX_CN63XXP1
,
1406 OPTION_NO_FIX_CN63XXP1
,
1413 OPTION_CONSTRUCT_FLOATS
,
1414 OPTION_NO_CONSTRUCT_FLOATS
,
1417 OPTION_RELAX_BRANCH
,
1418 OPTION_NO_RELAX_BRANCH
,
1425 OPTION_SINGLE_FLOAT
,
1426 OPTION_DOUBLE_FLOAT
,
1440 OPTION_MVXWORKS_PIC
,
1441 #endif /* OBJ_ELF */
1445 struct option md_longopts
[] =
1447 /* Options which specify architecture. */
1448 {"march", required_argument
, NULL
, OPTION_MARCH
},
1449 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1450 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1451 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1452 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1453 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1454 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1455 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1456 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1457 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1458 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1459 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1461 /* Options which specify Application Specific Extensions (ASEs). */
1462 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1463 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1464 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1465 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1466 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1467 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1468 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1469 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1470 {"mmt", no_argument
, NULL
, OPTION_MT
},
1471 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1472 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1473 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1474 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1475 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1476 {"meva", no_argument
, NULL
, OPTION_EVA
},
1477 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1478 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1479 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1480 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1481 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1482 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1483 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1485 /* Old-style architecture options. Don't add more of these. */
1486 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1487 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1488 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1489 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1490 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1491 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1492 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1493 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1495 /* Options which enable bug fixes. */
1496 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1497 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1498 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1499 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1500 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1501 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1502 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1503 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1504 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1505 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1506 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1507 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1508 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1509 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1510 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1512 /* Miscellaneous options. */
1513 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1514 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1515 {"break", no_argument
, NULL
, OPTION_BREAK
},
1516 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1517 {"EB", no_argument
, NULL
, OPTION_EB
},
1518 {"EL", no_argument
, NULL
, OPTION_EL
},
1519 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1520 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1521 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1522 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1523 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1524 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1525 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1526 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1527 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1528 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1529 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1530 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1531 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1532 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1533 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1534 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1536 /* Strictly speaking this next option is ELF specific,
1537 but we allow it for other ports as well in order to
1538 make testing easier. */
1539 {"32", no_argument
, NULL
, OPTION_32
},
1541 /* ELF-specific options. */
1543 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1544 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1545 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1546 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1547 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1548 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1549 {"n32", no_argument
, NULL
, OPTION_N32
},
1550 {"64", no_argument
, NULL
, OPTION_64
},
1551 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1552 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1553 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1554 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1555 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1556 #endif /* OBJ_ELF */
1558 {NULL
, no_argument
, NULL
, 0}
1560 size_t md_longopts_size
= sizeof (md_longopts
);
1562 /* Information about either an Application Specific Extension or an
1563 optional architecture feature that, for simplicity, we treat in the
1564 same way as an ASE. */
1567 /* The name of the ASE, used in both the command-line and .set options. */
1570 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1571 and 64-bit architectures, the flags here refer to the subset that
1572 is available on both. */
1575 /* The ASE_* flag used for instructions that are available on 64-bit
1576 architectures but that are not included in FLAGS. */
1577 unsigned int flags64
;
1579 /* The command-line options that turn the ASE on and off. */
1583 /* The minimum required architecture revisions for MIPS32, MIPS64,
1584 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1587 int micromips32_rev
;
1588 int micromips64_rev
;
1591 /* A table of all supported ASEs. */
1592 static const struct mips_ase mips_ases
[] = {
1593 { "dsp", ASE_DSP
, ASE_DSP64
,
1594 OPTION_DSP
, OPTION_NO_DSP
,
1597 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1598 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1601 { "eva", ASE_EVA
, 0,
1602 OPTION_EVA
, OPTION_NO_EVA
,
1605 { "mcu", ASE_MCU
, 0,
1606 OPTION_MCU
, OPTION_NO_MCU
,
1609 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1610 { "mdmx", ASE_MDMX
, 0,
1611 OPTION_MDMX
, OPTION_NO_MDMX
,
1614 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1615 { "mips3d", ASE_MIPS3D
, 0,
1616 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1620 OPTION_MT
, OPTION_NO_MT
,
1623 { "smartmips", ASE_SMARTMIPS
, 0,
1624 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1627 { "virt", ASE_VIRT
, ASE_VIRT64
,
1628 OPTION_VIRT
, OPTION_NO_VIRT
,
1632 /* The set of ASEs that require -mfp64. */
1633 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1635 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1636 static const unsigned int mips_ase_groups
[] = {
1642 The following pseudo-ops from the Kane and Heinrich MIPS book
1643 should be defined here, but are currently unsupported: .alias,
1644 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1646 The following pseudo-ops from the Kane and Heinrich MIPS book are
1647 specific to the type of debugging information being generated, and
1648 should be defined by the object format: .aent, .begin, .bend,
1649 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1652 The following pseudo-ops from the Kane and Heinrich MIPS book are
1653 not MIPS CPU specific, but are also not specific to the object file
1654 format. This file is probably the best place to define them, but
1655 they are not currently supported: .asm0, .endr, .lab, .struct. */
1657 static const pseudo_typeS mips_pseudo_table
[] =
1659 /* MIPS specific pseudo-ops. */
1660 {"option", s_option
, 0},
1661 {"set", s_mipsset
, 0},
1662 {"rdata", s_change_sec
, 'r'},
1663 {"sdata", s_change_sec
, 's'},
1664 {"livereg", s_ignore
, 0},
1665 {"abicalls", s_abicalls
, 0},
1666 {"cpload", s_cpload
, 0},
1667 {"cpsetup", s_cpsetup
, 0},
1668 {"cplocal", s_cplocal
, 0},
1669 {"cprestore", s_cprestore
, 0},
1670 {"cpreturn", s_cpreturn
, 0},
1671 {"dtprelword", s_dtprelword
, 0},
1672 {"dtpreldword", s_dtpreldword
, 0},
1673 {"tprelword", s_tprelword
, 0},
1674 {"tpreldword", s_tpreldword
, 0},
1675 {"gpvalue", s_gpvalue
, 0},
1676 {"gpword", s_gpword
, 0},
1677 {"gpdword", s_gpdword
, 0},
1678 {"ehword", s_ehword
, 0},
1679 {"cpadd", s_cpadd
, 0},
1680 {"insn", s_insn
, 0},
1682 /* Relatively generic pseudo-ops that happen to be used on MIPS
1684 {"asciiz", stringer
, 8 + 1},
1685 {"bss", s_change_sec
, 'b'},
1687 {"half", s_cons
, 1},
1688 {"dword", s_cons
, 3},
1689 {"weakext", s_mips_weakext
, 0},
1690 {"origin", s_org
, 0},
1691 {"repeat", s_rept
, 0},
1693 /* For MIPS this is non-standard, but we define it for consistency. */
1694 {"sbss", s_change_sec
, 'B'},
1696 /* These pseudo-ops are defined in read.c, but must be overridden
1697 here for one reason or another. */
1698 {"align", s_align
, 0},
1699 {"byte", s_cons
, 0},
1700 {"data", s_change_sec
, 'd'},
1701 {"double", s_float_cons
, 'd'},
1702 {"float", s_float_cons
, 'f'},
1703 {"globl", s_mips_globl
, 0},
1704 {"global", s_mips_globl
, 0},
1705 {"hword", s_cons
, 1},
1707 {"long", s_cons
, 2},
1708 {"octa", s_cons
, 4},
1709 {"quad", s_cons
, 3},
1710 {"section", s_change_section
, 0},
1711 {"short", s_cons
, 1},
1712 {"single", s_float_cons
, 'f'},
1713 {"stabd", s_mips_stab
, 'd'},
1714 {"stabn", s_mips_stab
, 'n'},
1715 {"stabs", s_mips_stab
, 's'},
1716 {"text", s_change_sec
, 't'},
1717 {"word", s_cons
, 2},
1719 { "extern", ecoff_directive_extern
, 0},
1724 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1726 /* These pseudo-ops should be defined by the object file format.
1727 However, a.out doesn't support them, so we have versions here. */
1728 {"aent", s_mips_ent
, 1},
1729 {"bgnb", s_ignore
, 0},
1730 {"end", s_mips_end
, 0},
1731 {"endb", s_ignore
, 0},
1732 {"ent", s_mips_ent
, 0},
1733 {"file", s_mips_file
, 0},
1734 {"fmask", s_mips_mask
, 'F'},
1735 {"frame", s_mips_frame
, 0},
1736 {"loc", s_mips_loc
, 0},
1737 {"mask", s_mips_mask
, 'R'},
1738 {"verstamp", s_ignore
, 0},
1742 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1743 purpose of the `.dc.a' internal pseudo-op. */
1746 mips_address_bytes (void)
1748 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1751 extern void pop_insert (const pseudo_typeS
*);
1754 mips_pop_insert (void)
1756 pop_insert (mips_pseudo_table
);
1757 if (! ECOFF_DEBUGGING
)
1758 pop_insert (mips_nonecoff_pseudo_table
);
1761 /* Symbols labelling the current insn. */
1763 struct insn_label_list
1765 struct insn_label_list
*next
;
1769 static struct insn_label_list
*free_insn_labels
;
1770 #define label_list tc_segment_info_data.labels
1772 static void mips_clear_insn_labels (void);
1773 static void mips_mark_labels (void);
1774 static void mips_compressed_mark_labels (void);
1777 mips_clear_insn_labels (void)
1779 register struct insn_label_list
**pl
;
1780 segment_info_type
*si
;
1784 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1787 si
= seg_info (now_seg
);
1788 *pl
= si
->label_list
;
1789 si
->label_list
= NULL
;
1793 /* Mark instruction labels in MIPS16/microMIPS mode. */
1796 mips_mark_labels (void)
1798 if (HAVE_CODE_COMPRESSION
)
1799 mips_compressed_mark_labels ();
1802 static char *expr_end
;
1804 /* Expressions which appear in instructions. These are set by
1807 static expressionS imm_expr
;
1808 static expressionS imm2_expr
;
1809 static expressionS offset_expr
;
1811 /* Relocs associated with imm_expr and offset_expr. */
1813 static bfd_reloc_code_real_type imm_reloc
[3]
1814 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1815 static bfd_reloc_code_real_type offset_reloc
[3]
1816 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1818 /* This is set to the resulting size of the instruction to be produced
1819 by mips16_ip if an explicit extension is used or by mips_ip if an
1820 explicit size is supplied. */
1822 static unsigned int forced_insn_length
;
1824 /* True if we are assembling an instruction. All dot symbols defined during
1825 this time should be treated as code labels. */
1827 static bfd_boolean mips_assembling_insn
;
1830 /* The pdr segment for per procedure frame/regmask info. Not used for
1833 static segT pdr_seg
;
1836 /* The default target format to use. */
1838 #if defined (TE_FreeBSD)
1839 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1840 #elif defined (TE_TMIPS)
1841 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1843 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1847 mips_target_format (void)
1849 switch (OUTPUT_FLAVOR
)
1851 case bfd_target_elf_flavour
:
1853 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1854 return (target_big_endian
1855 ? "elf32-bigmips-vxworks"
1856 : "elf32-littlemips-vxworks");
1858 return (target_big_endian
1859 ? (HAVE_64BIT_OBJECTS
1860 ? ELF_TARGET ("elf64-", "big")
1862 ? ELF_TARGET ("elf32-n", "big")
1863 : ELF_TARGET ("elf32-", "big")))
1864 : (HAVE_64BIT_OBJECTS
1865 ? ELF_TARGET ("elf64-", "little")
1867 ? ELF_TARGET ("elf32-n", "little")
1868 : ELF_TARGET ("elf32-", "little"))));
1875 /* Return the ISA revision that is currently in use, or 0 if we are
1876 generating code for MIPS V or below. */
1881 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1884 /* microMIPS implies revision 2 or above. */
1885 if (mips_opts
.micromips
)
1888 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1894 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1897 mips_ase_mask (unsigned int flags
)
1901 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1902 if (flags
& mips_ase_groups
[i
])
1903 flags
|= mips_ase_groups
[i
];
1907 /* Check whether the current ISA supports ASE. Issue a warning if
1911 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1915 static unsigned int warned_isa
;
1916 static unsigned int warned_fp32
;
1918 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1919 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1921 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1922 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1923 && (warned_isa
& ase
->flags
) != ase
->flags
)
1925 warned_isa
|= ase
->flags
;
1926 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1927 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1929 as_warn (_("The %d-bit %s architecture does not support the"
1930 " `%s' extension"), size
, base
, ase
->name
);
1932 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1933 ase
->name
, base
, size
, min_rev
);
1935 if ((ase
->flags
& FP64_ASES
)
1937 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1939 warned_fp32
|= ase
->flags
;
1940 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1944 /* Check all enabled ASEs to see whether they are supported by the
1945 chosen architecture. */
1948 mips_check_isa_supports_ases (void)
1950 unsigned int i
, mask
;
1952 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1954 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1955 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1956 mips_check_isa_supports_ase (&mips_ases
[i
]);
1960 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1961 that were affected. */
1964 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1968 mask
= mips_ase_mask (ase
->flags
);
1969 mips_opts
.ase
&= ~mask
;
1971 mips_opts
.ase
|= ase
->flags
;
1975 /* Return the ASE called NAME, or null if none. */
1977 static const struct mips_ase
*
1978 mips_lookup_ase (const char *name
)
1982 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1983 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1984 return &mips_ases
[i
];
1988 /* Return the length of a microMIPS instruction in bytes. If bits of
1989 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1990 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1991 major opcode) will require further modifications to the opcode
1994 static inline unsigned int
1995 micromips_insn_length (const struct mips_opcode
*mo
)
1997 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2000 /* Return the length of MIPS16 instruction OPCODE. */
2002 static inline unsigned int
2003 mips16_opcode_length (unsigned long opcode
)
2005 return (opcode
>> 16) == 0 ? 2 : 4;
2008 /* Return the length of instruction INSN. */
2010 static inline unsigned int
2011 insn_length (const struct mips_cl_insn
*insn
)
2013 if (mips_opts
.micromips
)
2014 return micromips_insn_length (insn
->insn_mo
);
2015 else if (mips_opts
.mips16
)
2016 return mips16_opcode_length (insn
->insn_opcode
);
2021 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2024 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2029 insn
->insn_opcode
= mo
->match
;
2032 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2033 insn
->fixp
[i
] = NULL
;
2034 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2035 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2036 insn
->mips16_absolute_jump_p
= 0;
2037 insn
->complete_p
= 0;
2038 insn
->cleared_p
= 0;
2041 /* Record the current MIPS16/microMIPS mode in now_seg. */
2044 mips_record_compressed_mode (void)
2046 segment_info_type
*si
;
2048 si
= seg_info (now_seg
);
2049 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2050 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2051 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2052 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2055 /* Read a standard MIPS instruction from BUF. */
2057 static unsigned long
2058 read_insn (char *buf
)
2060 if (target_big_endian
)
2061 return bfd_getb32 ((bfd_byte
*) buf
);
2063 return bfd_getl32 ((bfd_byte
*) buf
);
2066 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2070 write_insn (char *buf
, unsigned int insn
)
2072 md_number_to_chars (buf
, insn
, 4);
2076 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2077 has length LENGTH. */
2079 static unsigned long
2080 read_compressed_insn (char *buf
, unsigned int length
)
2086 for (i
= 0; i
< length
; i
+= 2)
2089 if (target_big_endian
)
2090 insn
|= bfd_getb16 ((char *) buf
);
2092 insn
|= bfd_getl16 ((char *) buf
);
2098 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2099 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2102 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2106 for (i
= 0; i
< length
; i
+= 2)
2107 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2108 return buf
+ length
;
2111 /* Install INSN at the location specified by its "frag" and "where" fields. */
2114 install_insn (const struct mips_cl_insn
*insn
)
2116 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2117 if (HAVE_CODE_COMPRESSION
)
2118 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2120 write_insn (f
, insn
->insn_opcode
);
2121 mips_record_compressed_mode ();
2124 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2125 and install the opcode in the new location. */
2128 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2133 insn
->where
= where
;
2134 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2135 if (insn
->fixp
[i
] != NULL
)
2137 insn
->fixp
[i
]->fx_frag
= frag
;
2138 insn
->fixp
[i
]->fx_where
= where
;
2140 install_insn (insn
);
2143 /* Add INSN to the end of the output. */
2146 add_fixed_insn (struct mips_cl_insn
*insn
)
2148 char *f
= frag_more (insn_length (insn
));
2149 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2152 /* Start a variant frag and move INSN to the start of the variant part,
2153 marking it as fixed. The other arguments are as for frag_var. */
2156 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2157 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2159 frag_grow (max_chars
);
2160 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2162 frag_var (rs_machine_dependent
, max_chars
, var
,
2163 subtype
, symbol
, offset
, NULL
);
2166 /* Insert N copies of INSN into the history buffer, starting at
2167 position FIRST. Neither FIRST nor N need to be clipped. */
2170 insert_into_history (unsigned int first
, unsigned int n
,
2171 const struct mips_cl_insn
*insn
)
2173 if (mips_relax
.sequence
!= 2)
2177 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2179 history
[i
] = history
[i
- n
];
2185 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2186 the idea is to make it obvious at a glance that each errata is
2190 init_vr4120_conflicts (void)
2192 #define CONFLICT(FIRST, SECOND) \
2193 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2195 /* Errata 21 - [D]DIV[U] after [D]MACC */
2196 CONFLICT (MACC
, DIV
);
2197 CONFLICT (DMACC
, DIV
);
2199 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2200 CONFLICT (DMULT
, DMULT
);
2201 CONFLICT (DMULT
, DMACC
);
2202 CONFLICT (DMACC
, DMULT
);
2203 CONFLICT (DMACC
, DMACC
);
2205 /* Errata 24 - MT{LO,HI} after [D]MACC */
2206 CONFLICT (MACC
, MTHILO
);
2207 CONFLICT (DMACC
, MTHILO
);
2209 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2210 instruction is executed immediately after a MACC or DMACC
2211 instruction, the result of [either instruction] is incorrect." */
2212 CONFLICT (MACC
, MULT
);
2213 CONFLICT (MACC
, DMULT
);
2214 CONFLICT (DMACC
, MULT
);
2215 CONFLICT (DMACC
, DMULT
);
2217 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2218 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2219 DDIV or DDIVU instruction, the result of the MACC or
2220 DMACC instruction is incorrect.". */
2221 CONFLICT (DMULT
, MACC
);
2222 CONFLICT (DMULT
, DMACC
);
2223 CONFLICT (DIV
, MACC
);
2224 CONFLICT (DIV
, DMACC
);
2234 #define RTYPE_MASK 0x1ff00
2235 #define RTYPE_NUM 0x00100
2236 #define RTYPE_FPU 0x00200
2237 #define RTYPE_FCC 0x00400
2238 #define RTYPE_VEC 0x00800
2239 #define RTYPE_GP 0x01000
2240 #define RTYPE_CP0 0x02000
2241 #define RTYPE_PC 0x04000
2242 #define RTYPE_ACC 0x08000
2243 #define RTYPE_CCC 0x10000
2244 #define RNUM_MASK 0x000ff
2245 #define RWARN 0x80000
2247 #define GENERIC_REGISTER_NUMBERS \
2248 {"$0", RTYPE_NUM | 0}, \
2249 {"$1", RTYPE_NUM | 1}, \
2250 {"$2", RTYPE_NUM | 2}, \
2251 {"$3", RTYPE_NUM | 3}, \
2252 {"$4", RTYPE_NUM | 4}, \
2253 {"$5", RTYPE_NUM | 5}, \
2254 {"$6", RTYPE_NUM | 6}, \
2255 {"$7", RTYPE_NUM | 7}, \
2256 {"$8", RTYPE_NUM | 8}, \
2257 {"$9", RTYPE_NUM | 9}, \
2258 {"$10", RTYPE_NUM | 10}, \
2259 {"$11", RTYPE_NUM | 11}, \
2260 {"$12", RTYPE_NUM | 12}, \
2261 {"$13", RTYPE_NUM | 13}, \
2262 {"$14", RTYPE_NUM | 14}, \
2263 {"$15", RTYPE_NUM | 15}, \
2264 {"$16", RTYPE_NUM | 16}, \
2265 {"$17", RTYPE_NUM | 17}, \
2266 {"$18", RTYPE_NUM | 18}, \
2267 {"$19", RTYPE_NUM | 19}, \
2268 {"$20", RTYPE_NUM | 20}, \
2269 {"$21", RTYPE_NUM | 21}, \
2270 {"$22", RTYPE_NUM | 22}, \
2271 {"$23", RTYPE_NUM | 23}, \
2272 {"$24", RTYPE_NUM | 24}, \
2273 {"$25", RTYPE_NUM | 25}, \
2274 {"$26", RTYPE_NUM | 26}, \
2275 {"$27", RTYPE_NUM | 27}, \
2276 {"$28", RTYPE_NUM | 28}, \
2277 {"$29", RTYPE_NUM | 29}, \
2278 {"$30", RTYPE_NUM | 30}, \
2279 {"$31", RTYPE_NUM | 31}
2281 #define FPU_REGISTER_NAMES \
2282 {"$f0", RTYPE_FPU | 0}, \
2283 {"$f1", RTYPE_FPU | 1}, \
2284 {"$f2", RTYPE_FPU | 2}, \
2285 {"$f3", RTYPE_FPU | 3}, \
2286 {"$f4", RTYPE_FPU | 4}, \
2287 {"$f5", RTYPE_FPU | 5}, \
2288 {"$f6", RTYPE_FPU | 6}, \
2289 {"$f7", RTYPE_FPU | 7}, \
2290 {"$f8", RTYPE_FPU | 8}, \
2291 {"$f9", RTYPE_FPU | 9}, \
2292 {"$f10", RTYPE_FPU | 10}, \
2293 {"$f11", RTYPE_FPU | 11}, \
2294 {"$f12", RTYPE_FPU | 12}, \
2295 {"$f13", RTYPE_FPU | 13}, \
2296 {"$f14", RTYPE_FPU | 14}, \
2297 {"$f15", RTYPE_FPU | 15}, \
2298 {"$f16", RTYPE_FPU | 16}, \
2299 {"$f17", RTYPE_FPU | 17}, \
2300 {"$f18", RTYPE_FPU | 18}, \
2301 {"$f19", RTYPE_FPU | 19}, \
2302 {"$f20", RTYPE_FPU | 20}, \
2303 {"$f21", RTYPE_FPU | 21}, \
2304 {"$f22", RTYPE_FPU | 22}, \
2305 {"$f23", RTYPE_FPU | 23}, \
2306 {"$f24", RTYPE_FPU | 24}, \
2307 {"$f25", RTYPE_FPU | 25}, \
2308 {"$f26", RTYPE_FPU | 26}, \
2309 {"$f27", RTYPE_FPU | 27}, \
2310 {"$f28", RTYPE_FPU | 28}, \
2311 {"$f29", RTYPE_FPU | 29}, \
2312 {"$f30", RTYPE_FPU | 30}, \
2313 {"$f31", RTYPE_FPU | 31}
2315 #define FPU_CONDITION_CODE_NAMES \
2316 {"$fcc0", RTYPE_FCC | 0}, \
2317 {"$fcc1", RTYPE_FCC | 1}, \
2318 {"$fcc2", RTYPE_FCC | 2}, \
2319 {"$fcc3", RTYPE_FCC | 3}, \
2320 {"$fcc4", RTYPE_FCC | 4}, \
2321 {"$fcc5", RTYPE_FCC | 5}, \
2322 {"$fcc6", RTYPE_FCC | 6}, \
2323 {"$fcc7", RTYPE_FCC | 7}
2325 #define COPROC_CONDITION_CODE_NAMES \
2326 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2327 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2328 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2329 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2330 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2331 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2332 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2333 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2335 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2336 {"$a4", RTYPE_GP | 8}, \
2337 {"$a5", RTYPE_GP | 9}, \
2338 {"$a6", RTYPE_GP | 10}, \
2339 {"$a7", RTYPE_GP | 11}, \
2340 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2341 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2342 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2343 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2344 {"$t0", RTYPE_GP | 12}, \
2345 {"$t1", RTYPE_GP | 13}, \
2346 {"$t2", RTYPE_GP | 14}, \
2347 {"$t3", RTYPE_GP | 15}
2349 #define O32_SYMBOLIC_REGISTER_NAMES \
2350 {"$t0", RTYPE_GP | 8}, \
2351 {"$t1", RTYPE_GP | 9}, \
2352 {"$t2", RTYPE_GP | 10}, \
2353 {"$t3", RTYPE_GP | 11}, \
2354 {"$t4", RTYPE_GP | 12}, \
2355 {"$t5", RTYPE_GP | 13}, \
2356 {"$t6", RTYPE_GP | 14}, \
2357 {"$t7", RTYPE_GP | 15}, \
2358 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2359 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2360 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2361 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2363 /* Remaining symbolic register names */
2364 #define SYMBOLIC_REGISTER_NAMES \
2365 {"$zero", RTYPE_GP | 0}, \
2366 {"$at", RTYPE_GP | 1}, \
2367 {"$AT", RTYPE_GP | 1}, \
2368 {"$v0", RTYPE_GP | 2}, \
2369 {"$v1", RTYPE_GP | 3}, \
2370 {"$a0", RTYPE_GP | 4}, \
2371 {"$a1", RTYPE_GP | 5}, \
2372 {"$a2", RTYPE_GP | 6}, \
2373 {"$a3", RTYPE_GP | 7}, \
2374 {"$s0", RTYPE_GP | 16}, \
2375 {"$s1", RTYPE_GP | 17}, \
2376 {"$s2", RTYPE_GP | 18}, \
2377 {"$s3", RTYPE_GP | 19}, \
2378 {"$s4", RTYPE_GP | 20}, \
2379 {"$s5", RTYPE_GP | 21}, \
2380 {"$s6", RTYPE_GP | 22}, \
2381 {"$s7", RTYPE_GP | 23}, \
2382 {"$t8", RTYPE_GP | 24}, \
2383 {"$t9", RTYPE_GP | 25}, \
2384 {"$k0", RTYPE_GP | 26}, \
2385 {"$kt0", RTYPE_GP | 26}, \
2386 {"$k1", RTYPE_GP | 27}, \
2387 {"$kt1", RTYPE_GP | 27}, \
2388 {"$gp", RTYPE_GP | 28}, \
2389 {"$sp", RTYPE_GP | 29}, \
2390 {"$s8", RTYPE_GP | 30}, \
2391 {"$fp", RTYPE_GP | 30}, \
2392 {"$ra", RTYPE_GP | 31}
2394 #define MIPS16_SPECIAL_REGISTER_NAMES \
2395 {"$pc", RTYPE_PC | 0}
2397 #define MDMX_VECTOR_REGISTER_NAMES \
2398 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2399 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2400 {"$v2", RTYPE_VEC | 2}, \
2401 {"$v3", RTYPE_VEC | 3}, \
2402 {"$v4", RTYPE_VEC | 4}, \
2403 {"$v5", RTYPE_VEC | 5}, \
2404 {"$v6", RTYPE_VEC | 6}, \
2405 {"$v7", RTYPE_VEC | 7}, \
2406 {"$v8", RTYPE_VEC | 8}, \
2407 {"$v9", RTYPE_VEC | 9}, \
2408 {"$v10", RTYPE_VEC | 10}, \
2409 {"$v11", RTYPE_VEC | 11}, \
2410 {"$v12", RTYPE_VEC | 12}, \
2411 {"$v13", RTYPE_VEC | 13}, \
2412 {"$v14", RTYPE_VEC | 14}, \
2413 {"$v15", RTYPE_VEC | 15}, \
2414 {"$v16", RTYPE_VEC | 16}, \
2415 {"$v17", RTYPE_VEC | 17}, \
2416 {"$v18", RTYPE_VEC | 18}, \
2417 {"$v19", RTYPE_VEC | 19}, \
2418 {"$v20", RTYPE_VEC | 20}, \
2419 {"$v21", RTYPE_VEC | 21}, \
2420 {"$v22", RTYPE_VEC | 22}, \
2421 {"$v23", RTYPE_VEC | 23}, \
2422 {"$v24", RTYPE_VEC | 24}, \
2423 {"$v25", RTYPE_VEC | 25}, \
2424 {"$v26", RTYPE_VEC | 26}, \
2425 {"$v27", RTYPE_VEC | 27}, \
2426 {"$v28", RTYPE_VEC | 28}, \
2427 {"$v29", RTYPE_VEC | 29}, \
2428 {"$v30", RTYPE_VEC | 30}, \
2429 {"$v31", RTYPE_VEC | 31}
2431 #define MIPS_DSP_ACCUMULATOR_NAMES \
2432 {"$ac0", RTYPE_ACC | 0}, \
2433 {"$ac1", RTYPE_ACC | 1}, \
2434 {"$ac2", RTYPE_ACC | 2}, \
2435 {"$ac3", RTYPE_ACC | 3}
2437 static const struct regname reg_names
[] = {
2438 GENERIC_REGISTER_NUMBERS
,
2440 FPU_CONDITION_CODE_NAMES
,
2441 COPROC_CONDITION_CODE_NAMES
,
2443 /* The $txx registers depends on the abi,
2444 these will be added later into the symbol table from
2445 one of the tables below once mips_abi is set after
2446 parsing of arguments from the command line. */
2447 SYMBOLIC_REGISTER_NAMES
,
2449 MIPS16_SPECIAL_REGISTER_NAMES
,
2450 MDMX_VECTOR_REGISTER_NAMES
,
2451 MIPS_DSP_ACCUMULATOR_NAMES
,
2455 static const struct regname reg_names_o32
[] = {
2456 O32_SYMBOLIC_REGISTER_NAMES
,
2460 static const struct regname reg_names_n32n64
[] = {
2461 N32N64_SYMBOLIC_REGISTER_NAMES
,
2465 /* Check if S points at a valid register specifier according to TYPES.
2466 If so, then return 1, advance S to consume the specifier and store
2467 the register's number in REGNOP, otherwise return 0. */
2470 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2477 /* Find end of name. */
2479 if (is_name_beginner (*e
))
2481 while (is_part_of_name (*e
))
2484 /* Terminate name. */
2488 /* Look for a register symbol. */
2489 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2491 int r
= S_GET_VALUE (symbolP
);
2493 reg
= r
& RNUM_MASK
;
2494 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2495 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2496 reg
= (r
& RNUM_MASK
) - 2;
2498 /* Else see if this is a register defined in an itbl entry. */
2499 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2506 if (itbl_get_reg_val (n
, &r
))
2507 reg
= r
& RNUM_MASK
;
2510 /* Advance to next token if a register was recognised. */
2513 else if (types
& RWARN
)
2514 as_warn (_("Unrecognized register name `%s'"), *s
);
2522 /* Check if S points at a valid register list according to TYPES.
2523 If so, then return 1, advance S to consume the list and store
2524 the registers present on the list as a bitmask of ones in REGLISTP,
2525 otherwise return 0. A valid list comprises a comma-separated
2526 enumeration of valid single registers and/or dash-separated
2527 contiguous register ranges as determined by their numbers.
2529 As a special exception if one of s0-s7 registers is specified as
2530 the range's lower delimiter and s8 (fp) is its upper one, then no
2531 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2532 are selected; they have to be listed separately if needed. */
2535 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2537 unsigned int reglist
= 0;
2538 unsigned int lastregno
;
2539 bfd_boolean ok
= TRUE
;
2540 unsigned int regmask
;
2541 char *s_endlist
= *s
;
2545 while (reg_lookup (s
, types
, ®no
))
2551 ok
= reg_lookup (s
, types
, &lastregno
);
2552 if (ok
&& lastregno
< regno
)
2558 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2563 regmask
= 1 << lastregno
;
2564 regmask
= (regmask
<< 1) - 1;
2565 regmask
^= (1 << regno
) - 1;
2579 *reglistp
= reglist
;
2580 return ok
&& reglist
!= 0;
2583 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2584 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2587 is_opcode_valid (const struct mips_opcode
*mo
)
2589 int isa
= mips_opts
.isa
;
2590 int ase
= mips_opts
.ase
;
2594 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2595 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2596 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2597 ase
|= mips_ases
[i
].flags64
;
2599 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2602 /* Check whether the instruction or macro requires single-precision or
2603 double-precision floating-point support. Note that this information is
2604 stored differently in the opcode table for insns and macros. */
2605 if (mo
->pinfo
== INSN_MACRO
)
2607 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2608 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2612 fp_s
= mo
->pinfo
& FP_S
;
2613 fp_d
= mo
->pinfo
& FP_D
;
2616 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2619 if (fp_s
&& mips_opts
.soft_float
)
2625 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2626 selected ISA and architecture. */
2629 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2631 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2634 /* Return TRUE if the size of the microMIPS opcode MO matches one
2635 explicitly requested. Always TRUE in the standard MIPS mode. */
2638 is_size_valid (const struct mips_opcode
*mo
)
2640 if (!mips_opts
.micromips
)
2643 if (!forced_insn_length
)
2645 if (mo
->pinfo
== INSN_MACRO
)
2647 return forced_insn_length
== micromips_insn_length (mo
);
2650 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2651 of the preceding instruction. Always TRUE in the standard MIPS mode.
2653 We don't accept macros in 16-bit delay slots to avoid a case where
2654 a macro expansion fails because it relies on a preceding 32-bit real
2655 instruction to have matched and does not handle the operands correctly.
2656 The only macros that may expand to 16-bit instructions are JAL that
2657 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2658 and BGT (that likewise cannot be placed in a delay slot) that decay to
2659 a NOP. In all these cases the macros precede any corresponding real
2660 instruction definitions in the opcode table, so they will match in the
2661 second pass where the size of the delay slot is ignored and therefore
2662 produce correct code. */
2665 is_delay_slot_valid (const struct mips_opcode
*mo
)
2667 if (!mips_opts
.micromips
)
2670 if (mo
->pinfo
== INSN_MACRO
)
2671 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2672 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2673 && micromips_insn_length (mo
) != 4)
2675 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2676 && micromips_insn_length (mo
) != 2)
2682 /* This function is called once, at assembler startup time. It should set up
2683 all the tables, etc. that the MD part of the assembler will need. */
2688 const char *retval
= NULL
;
2692 if (mips_pic
!= NO_PIC
)
2694 if (g_switch_seen
&& g_switch_value
!= 0)
2695 as_bad (_("-G may not be used in position-independent code"));
2699 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2700 as_warn (_("Could not set architecture and machine"));
2702 op_hash
= hash_new ();
2704 for (i
= 0; i
< NUMOPCODES
;)
2706 const char *name
= mips_opcodes
[i
].name
;
2708 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2711 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2712 mips_opcodes
[i
].name
, retval
);
2713 /* Probably a memory allocation problem? Give up now. */
2714 as_fatal (_("Broken assembler. No assembly attempted."));
2718 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2720 if (!validate_mips_insn (&mips_opcodes
[i
]))
2722 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2724 create_insn (&nop_insn
, mips_opcodes
+ i
);
2725 if (mips_fix_loongson2f_nop
)
2726 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2727 nop_insn
.fixed_p
= 1;
2732 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2735 mips16_op_hash
= hash_new ();
2738 while (i
< bfd_mips16_num_opcodes
)
2740 const char *name
= mips16_opcodes
[i
].name
;
2742 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2744 as_fatal (_("internal: can't hash `%s': %s"),
2745 mips16_opcodes
[i
].name
, retval
);
2748 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2749 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2750 != mips16_opcodes
[i
].match
))
2752 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2753 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2756 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2758 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2759 mips16_nop_insn
.fixed_p
= 1;
2763 while (i
< bfd_mips16_num_opcodes
2764 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2767 micromips_op_hash
= hash_new ();
2770 while (i
< bfd_micromips_num_opcodes
)
2772 const char *name
= micromips_opcodes
[i
].name
;
2774 retval
= hash_insert (micromips_op_hash
, name
,
2775 (void *) µmips_opcodes
[i
]);
2777 as_fatal (_("internal: can't hash `%s': %s"),
2778 micromips_opcodes
[i
].name
, retval
);
2780 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2782 struct mips_cl_insn
*micromips_nop_insn
;
2784 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2787 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2788 micromips_nop_insn
= µmips_nop16_insn
;
2789 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2790 micromips_nop_insn
= µmips_nop32_insn
;
2794 if (micromips_nop_insn
->insn_mo
== NULL
2795 && strcmp (name
, "nop") == 0)
2797 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2798 micromips_nop_insn
->fixed_p
= 1;
2801 while (++i
< bfd_micromips_num_opcodes
2802 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2806 as_fatal (_("Broken assembler. No assembly attempted."));
2808 /* We add all the general register names to the symbol table. This
2809 helps us detect invalid uses of them. */
2810 for (i
= 0; reg_names
[i
].name
; i
++)
2811 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2812 reg_names
[i
].num
, /* & RNUM_MASK, */
2813 &zero_address_frag
));
2815 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2816 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2817 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2818 &zero_address_frag
));
2820 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2821 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2822 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2823 &zero_address_frag
));
2825 mips_no_prev_insn ();
2828 mips_cprmask
[0] = 0;
2829 mips_cprmask
[1] = 0;
2830 mips_cprmask
[2] = 0;
2831 mips_cprmask
[3] = 0;
2833 /* set the default alignment for the text section (2**2) */
2834 record_alignment (text_section
, 2);
2836 bfd_set_gp_size (stdoutput
, g_switch_value
);
2841 /* On a native system other than VxWorks, sections must be aligned
2842 to 16 byte boundaries. When configured for an embedded ELF
2843 target, we don't bother. */
2844 if (strncmp (TARGET_OS
, "elf", 3) != 0
2845 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2847 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2848 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2849 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2852 /* Create a .reginfo section for register masks and a .mdebug
2853 section for debugging information. */
2861 subseg
= now_subseg
;
2863 /* The ABI says this section should be loaded so that the
2864 running program can access it. However, we don't load it
2865 if we are configured for an embedded target */
2866 flags
= SEC_READONLY
| SEC_DATA
;
2867 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2868 flags
|= SEC_ALLOC
| SEC_LOAD
;
2870 if (mips_abi
!= N64_ABI
)
2872 sec
= subseg_new (".reginfo", (subsegT
) 0);
2874 bfd_set_section_flags (stdoutput
, sec
, flags
);
2875 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2877 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2881 /* The 64-bit ABI uses a .MIPS.options section rather than
2882 .reginfo section. */
2883 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2884 bfd_set_section_flags (stdoutput
, sec
, flags
);
2885 bfd_set_section_alignment (stdoutput
, sec
, 3);
2887 /* Set up the option header. */
2889 Elf_Internal_Options opthdr
;
2892 opthdr
.kind
= ODK_REGINFO
;
2893 opthdr
.size
= (sizeof (Elf_External_Options
)
2894 + sizeof (Elf64_External_RegInfo
));
2897 f
= frag_more (sizeof (Elf_External_Options
));
2898 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2899 (Elf_External_Options
*) f
);
2901 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2905 if (ECOFF_DEBUGGING
)
2907 sec
= subseg_new (".mdebug", (subsegT
) 0);
2908 (void) bfd_set_section_flags (stdoutput
, sec
,
2909 SEC_HAS_CONTENTS
| SEC_READONLY
);
2910 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2912 else if (mips_flag_pdr
)
2914 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2915 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2916 SEC_READONLY
| SEC_RELOC
2918 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2921 subseg_set (seg
, subseg
);
2924 #endif /* OBJ_ELF */
2926 if (! ECOFF_DEBUGGING
)
2929 if (mips_fix_vr4120
)
2930 init_vr4120_conflicts ();
2936 mips_emit_delays ();
2937 if (! ECOFF_DEBUGGING
)
2942 md_assemble (char *str
)
2944 struct mips_cl_insn insn
;
2945 bfd_reloc_code_real_type unused_reloc
[3]
2946 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2948 imm_expr
.X_op
= O_absent
;
2949 imm2_expr
.X_op
= O_absent
;
2950 offset_expr
.X_op
= O_absent
;
2951 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2952 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2953 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2954 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2955 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2956 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2958 mips_mark_labels ();
2959 mips_assembling_insn
= TRUE
;
2961 if (mips_opts
.mips16
)
2962 mips16_ip (str
, &insn
);
2965 mips_ip (str
, &insn
);
2966 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2967 str
, insn
.insn_opcode
));
2971 as_bad ("%s `%s'", insn_error
, str
);
2972 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2975 if (mips_opts
.mips16
)
2976 mips16_macro (&insn
);
2983 if (imm_expr
.X_op
!= O_absent
)
2984 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2985 else if (offset_expr
.X_op
!= O_absent
)
2986 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
2988 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
2991 mips_assembling_insn
= FALSE
;
2994 /* Convenience functions for abstracting away the differences between
2995 MIPS16 and non-MIPS16 relocations. */
2997 static inline bfd_boolean
2998 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3002 case BFD_RELOC_MIPS16_JMP
:
3003 case BFD_RELOC_MIPS16_GPREL
:
3004 case BFD_RELOC_MIPS16_GOT16
:
3005 case BFD_RELOC_MIPS16_CALL16
:
3006 case BFD_RELOC_MIPS16_HI16_S
:
3007 case BFD_RELOC_MIPS16_HI16
:
3008 case BFD_RELOC_MIPS16_LO16
:
3016 static inline bfd_boolean
3017 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3021 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3022 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3023 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3024 case BFD_RELOC_MICROMIPS_GPREL16
:
3025 case BFD_RELOC_MICROMIPS_JMP
:
3026 case BFD_RELOC_MICROMIPS_HI16
:
3027 case BFD_RELOC_MICROMIPS_HI16_S
:
3028 case BFD_RELOC_MICROMIPS_LO16
:
3029 case BFD_RELOC_MICROMIPS_LITERAL
:
3030 case BFD_RELOC_MICROMIPS_GOT16
:
3031 case BFD_RELOC_MICROMIPS_CALL16
:
3032 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3033 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3034 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3035 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3036 case BFD_RELOC_MICROMIPS_SUB
:
3037 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3038 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3039 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3040 case BFD_RELOC_MICROMIPS_HIGHEST
:
3041 case BFD_RELOC_MICROMIPS_HIGHER
:
3042 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3043 case BFD_RELOC_MICROMIPS_JALR
:
3051 static inline bfd_boolean
3052 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3054 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3057 static inline bfd_boolean
3058 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3060 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3061 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3064 static inline bfd_boolean
3065 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3067 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3068 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3071 static inline bfd_boolean
3072 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3074 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3075 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3078 static inline bfd_boolean
3079 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3081 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3084 /* Return true if RELOC is a PC-relative relocation that does not have
3085 full address range. */
3087 static inline bfd_boolean
3088 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3092 case BFD_RELOC_16_PCREL_S2
:
3093 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3094 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3095 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3098 case BFD_RELOC_32_PCREL
:
3099 return HAVE_64BIT_ADDRESSES
;
3106 /* Return true if the given relocation might need a matching %lo().
3107 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3108 need a matching %lo() when applied to local symbols. */
3110 static inline bfd_boolean
3111 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3113 return (HAVE_IN_PLACE_ADDENDS
3114 && (hi16_reloc_p (reloc
)
3115 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3116 all GOT16 relocations evaluate to "G". */
3117 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3120 /* Return the type of %lo() reloc needed by RELOC, given that
3121 reloc_needs_lo_p. */
3123 static inline bfd_reloc_code_real_type
3124 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3126 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3127 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3131 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3134 static inline bfd_boolean
3135 fixup_has_matching_lo_p (fixS
*fixp
)
3137 return (fixp
->fx_next
!= NULL
3138 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3139 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3140 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3143 /* This function returns true if modifying a register requires a
3147 reg_needs_delay (unsigned int reg
)
3149 unsigned long prev_pinfo
;
3151 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3152 if (! mips_opts
.noreorder
3153 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
3154 && ! gpr_interlocks
)
3155 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
3156 && ! cop_interlocks
)))
3158 /* A load from a coprocessor or from memory. All load delays
3159 delay the use of general register rt for one instruction. */
3160 /* Itbl support may require additional care here. */
3161 know (prev_pinfo
& INSN_WRITE_GPR_T
);
3162 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
3169 /* Move all labels in LABELS to the current insertion point. TEXT_P
3170 says whether the labels refer to text or data. */
3173 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3175 struct insn_label_list
*l
;
3178 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3180 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3181 symbol_set_frag (l
->label
, frag_now
);
3182 val
= (valueT
) frag_now_fix ();
3183 /* MIPS16/microMIPS text labels are stored as odd. */
3184 if (text_p
&& HAVE_CODE_COMPRESSION
)
3186 S_SET_VALUE (l
->label
, val
);
3190 /* Move all labels in insn_labels to the current insertion point
3191 and treat them as text labels. */
3194 mips_move_text_labels (void)
3196 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3200 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3202 bfd_boolean linkonce
= FALSE
;
3203 segT symseg
= S_GET_SEGMENT (sym
);
3205 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3207 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3210 /* The GNU toolchain uses an extension for ELF: a section
3211 beginning with the magic string .gnu.linkonce is a
3212 linkonce section. */
3213 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3214 sizeof ".gnu.linkonce" - 1) == 0)
3221 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3222 linker to handle them specially, such as generating jalx instructions
3223 when needed. We also make them odd for the duration of the assembly,
3224 in order to generate the right sort of code. We will make them even
3225 in the adjust_symtab routine, while leaving them marked. This is
3226 convenient for the debugger and the disassembler. The linker knows
3227 to make them odd again. */
3230 mips_compressed_mark_label (symbolS
*label
)
3232 gas_assert (HAVE_CODE_COMPRESSION
);
3234 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3237 if (mips_opts
.mips16
)
3238 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3240 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3243 if ((S_GET_VALUE (label
) & 1) == 0
3244 /* Don't adjust the address if the label is global or weak, or
3245 in a link-once section, since we'll be emitting symbol reloc
3246 references to it which will be patched up by the linker, and
3247 the final value of the symbol may or may not be MIPS16/microMIPS. */
3248 && !S_IS_WEAK (label
)
3249 && !S_IS_EXTERNAL (label
)
3250 && !s_is_linkonce (label
, now_seg
))
3251 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3254 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3257 mips_compressed_mark_labels (void)
3259 struct insn_label_list
*l
;
3261 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3262 mips_compressed_mark_label (l
->label
);
3265 /* End the current frag. Make it a variant frag and record the
3269 relax_close_frag (void)
3271 mips_macro_warning
.first_frag
= frag_now
;
3272 frag_var (rs_machine_dependent
, 0, 0,
3273 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3274 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3276 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3277 mips_relax
.first_fixup
= 0;
3280 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3281 See the comment above RELAX_ENCODE for more details. */
3284 relax_start (symbolS
*symbol
)
3286 gas_assert (mips_relax
.sequence
== 0);
3287 mips_relax
.sequence
= 1;
3288 mips_relax
.symbol
= symbol
;
3291 /* Start generating the second version of a relaxable sequence.
3292 See the comment above RELAX_ENCODE for more details. */
3297 gas_assert (mips_relax
.sequence
== 1);
3298 mips_relax
.sequence
= 2;
3301 /* End the current relaxable sequence. */
3306 gas_assert (mips_relax
.sequence
== 2);
3307 relax_close_frag ();
3308 mips_relax
.sequence
= 0;
3311 /* Return true if IP is a delayed branch or jump. */
3313 static inline bfd_boolean
3314 delayed_branch_p (const struct mips_cl_insn
*ip
)
3316 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3317 | INSN_COND_BRANCH_DELAY
3318 | INSN_COND_BRANCH_LIKELY
)) != 0;
3321 /* Return true if IP is a compact branch or jump. */
3323 static inline bfd_boolean
3324 compact_branch_p (const struct mips_cl_insn
*ip
)
3326 if (mips_opts
.mips16
)
3327 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3328 | MIPS16_INSN_COND_BRANCH
)) != 0;
3330 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3331 | INSN2_COND_BRANCH
)) != 0;
3334 /* Return true if IP is an unconditional branch or jump. */
3336 static inline bfd_boolean
3337 uncond_branch_p (const struct mips_cl_insn
*ip
)
3339 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3340 || (mips_opts
.mips16
3341 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3342 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3345 /* Return true if IP is a branch-likely instruction. */
3347 static inline bfd_boolean
3348 branch_likely_p (const struct mips_cl_insn
*ip
)
3350 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3353 /* Return the type of nop that should be used to fill the delay slot
3354 of delayed branch IP. */
3356 static struct mips_cl_insn
*
3357 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3359 if (mips_opts
.micromips
3360 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3361 return µmips_nop32_insn
;
3365 /* Return the mask of core registers that IP reads or writes. */
3368 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3370 unsigned long pinfo2
;
3374 pinfo2
= ip
->insn_mo
->pinfo2
;
3375 if (mips_opts
.micromips
)
3377 if (pinfo2
& INSN2_MOD_GPR_MD
)
3378 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3379 if (pinfo2
& INSN2_MOD_GPR_MF
)
3380 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3381 if (pinfo2
& INSN2_MOD_SP
)
3387 /* Return the mask of core registers that IP reads. */
3390 gpr_read_mask (const struct mips_cl_insn
*ip
)
3392 unsigned long pinfo
, pinfo2
;
3395 mask
= gpr_mod_mask (ip
);
3396 pinfo
= ip
->insn_mo
->pinfo
;
3397 pinfo2
= ip
->insn_mo
->pinfo2
;
3398 if (mips_opts
.mips16
)
3400 if (pinfo
& MIPS16_INSN_READ_X
)
3401 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3402 if (pinfo
& MIPS16_INSN_READ_Y
)
3403 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3404 if (pinfo
& MIPS16_INSN_READ_T
)
3406 if (pinfo
& MIPS16_INSN_READ_SP
)
3408 if (pinfo
& MIPS16_INSN_READ_31
)
3410 if (pinfo
& MIPS16_INSN_READ_Z
)
3411 mask
|= 1 << (mips16_to_32_reg_map
3412 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3413 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3414 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3418 if (pinfo2
& INSN2_READ_GPR_D
)
3419 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3420 if (pinfo
& INSN_READ_GPR_T
)
3421 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3422 if (pinfo
& INSN_READ_GPR_S
)
3423 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3424 if (pinfo2
& INSN2_READ_GP
)
3426 if (pinfo2
& INSN2_READ_GPR_31
)
3428 if (pinfo2
& INSN2_READ_GPR_Z
)
3429 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3431 if (mips_opts
.micromips
)
3433 if (pinfo2
& INSN2_READ_GPR_MC
)
3434 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3435 if (pinfo2
& INSN2_READ_GPR_ME
)
3436 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3437 if (pinfo2
& INSN2_READ_GPR_MG
)
3438 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3439 if (pinfo2
& INSN2_READ_GPR_MJ
)
3440 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3441 if (pinfo2
& INSN2_READ_GPR_MMN
)
3443 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3444 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3446 if (pinfo2
& INSN2_READ_GPR_MP
)
3447 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3448 if (pinfo2
& INSN2_READ_GPR_MQ
)
3449 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3451 /* Don't include register 0. */
3455 /* Return the mask of core registers that IP writes. */
3458 gpr_write_mask (const struct mips_cl_insn
*ip
)
3460 unsigned long pinfo
, pinfo2
;
3463 mask
= gpr_mod_mask (ip
);
3464 pinfo
= ip
->insn_mo
->pinfo
;
3465 pinfo2
= ip
->insn_mo
->pinfo2
;
3466 if (mips_opts
.mips16
)
3468 if (pinfo
& MIPS16_INSN_WRITE_X
)
3469 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3470 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3471 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3472 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3473 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3474 if (pinfo
& MIPS16_INSN_WRITE_T
)
3476 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3478 if (pinfo
& MIPS16_INSN_WRITE_31
)
3480 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3481 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3485 if (pinfo
& INSN_WRITE_GPR_D
)
3486 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3487 if (pinfo
& INSN_WRITE_GPR_T
)
3488 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3489 if (pinfo
& INSN_WRITE_GPR_S
)
3490 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3491 if (pinfo
& INSN_WRITE_GPR_31
)
3493 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3494 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3496 if (mips_opts
.micromips
)
3498 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3499 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3500 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3502 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3503 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3505 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3506 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3507 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3508 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3510 /* Don't include register 0. */
3514 /* Return the mask of floating-point registers that IP reads. */
3517 fpr_read_mask (const struct mips_cl_insn
*ip
)
3519 unsigned long pinfo
, pinfo2
;
3523 pinfo
= ip
->insn_mo
->pinfo
;
3524 pinfo2
= ip
->insn_mo
->pinfo2
;
3525 if (!mips_opts
.mips16
)
3527 if (pinfo2
& INSN2_READ_FPR_D
)
3528 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3529 if (pinfo
& INSN_READ_FPR_S
)
3530 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3531 if (pinfo
& INSN_READ_FPR_T
)
3532 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3533 if (pinfo
& INSN_READ_FPR_R
)
3534 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3535 if (pinfo2
& INSN2_READ_FPR_Z
)
3536 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3538 /* Conservatively treat all operands to an FP_D instruction are doubles.
3539 (This is overly pessimistic for things like cvt.d.s.) */
3540 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3545 /* Return the mask of floating-point registers that IP writes. */
3548 fpr_write_mask (const struct mips_cl_insn
*ip
)
3550 unsigned long pinfo
, pinfo2
;
3554 pinfo
= ip
->insn_mo
->pinfo
;
3555 pinfo2
= ip
->insn_mo
->pinfo2
;
3556 if (!mips_opts
.mips16
)
3558 if (pinfo
& INSN_WRITE_FPR_D
)
3559 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3560 if (pinfo
& INSN_WRITE_FPR_S
)
3561 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3562 if (pinfo
& INSN_WRITE_FPR_T
)
3563 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3564 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3565 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3567 /* Conservatively treat all operands to an FP_D instruction are doubles.
3568 (This is overly pessimistic for things like cvt.s.d.) */
3569 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3574 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3575 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3576 by VR4120 errata. */
3579 classify_vr4120_insn (const char *name
)
3581 if (strncmp (name
, "macc", 4) == 0)
3582 return FIX_VR4120_MACC
;
3583 if (strncmp (name
, "dmacc", 5) == 0)
3584 return FIX_VR4120_DMACC
;
3585 if (strncmp (name
, "mult", 4) == 0)
3586 return FIX_VR4120_MULT
;
3587 if (strncmp (name
, "dmult", 5) == 0)
3588 return FIX_VR4120_DMULT
;
3589 if (strstr (name
, "div"))
3590 return FIX_VR4120_DIV
;
3591 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3592 return FIX_VR4120_MTHILO
;
3593 return NUM_FIX_VR4120_CLASSES
;
3596 #define INSN_ERET 0x42000018
3597 #define INSN_DERET 0x4200001f
3599 /* Return the number of instructions that must separate INSN1 and INSN2,
3600 where INSN1 is the earlier instruction. Return the worst-case value
3601 for any INSN2 if INSN2 is null. */
3604 insns_between (const struct mips_cl_insn
*insn1
,
3605 const struct mips_cl_insn
*insn2
)
3607 unsigned long pinfo1
, pinfo2
;
3610 /* This function needs to know which pinfo flags are set for INSN2
3611 and which registers INSN2 uses. The former is stored in PINFO2 and
3612 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3613 will have every flag set and INSN2_USES_GPR will always return true. */
3614 pinfo1
= insn1
->insn_mo
->pinfo
;
3615 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3617 #define INSN2_USES_GPR(REG) \
3618 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3620 /* For most targets, write-after-read dependencies on the HI and LO
3621 registers must be separated by at least two instructions. */
3622 if (!hilo_interlocks
)
3624 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3626 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3630 /* If we're working around r7000 errata, there must be two instructions
3631 between an mfhi or mflo and any instruction that uses the result. */
3632 if (mips_7000_hilo_fix
3633 && !mips_opts
.micromips
3634 && MF_HILO_INSN (pinfo1
)
3635 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3638 /* If we're working around 24K errata, one instruction is required
3639 if an ERET or DERET is followed by a branch instruction. */
3640 if (mips_fix_24k
&& !mips_opts
.micromips
)
3642 if (insn1
->insn_opcode
== INSN_ERET
3643 || insn1
->insn_opcode
== INSN_DERET
)
3646 || insn2
->insn_opcode
== INSN_ERET
3647 || insn2
->insn_opcode
== INSN_DERET
3648 || delayed_branch_p (insn2
))
3653 /* If working around VR4120 errata, check for combinations that need
3654 a single intervening instruction. */
3655 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3657 unsigned int class1
, class2
;
3659 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3660 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3664 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3665 if (vr4120_conflicts
[class1
] & (1 << class2
))
3670 if (!HAVE_CODE_COMPRESSION
)
3672 /* Check for GPR or coprocessor load delays. All such delays
3673 are on the RT register. */
3674 /* Itbl support may require additional care here. */
3675 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3676 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3678 know (pinfo1
& INSN_WRITE_GPR_T
);
3679 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3683 /* Check for generic coprocessor hazards.
3685 This case is not handled very well. There is no special
3686 knowledge of CP0 handling, and the coprocessors other than
3687 the floating point unit are not distinguished at all. */
3688 /* Itbl support may require additional care here. FIXME!
3689 Need to modify this to include knowledge about
3690 user specified delays! */
3691 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3692 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3694 /* Handle cases where INSN1 writes to a known general coprocessor
3695 register. There must be a one instruction delay before INSN2
3696 if INSN2 reads that register, otherwise no delay is needed. */
3697 mask
= fpr_write_mask (insn1
);
3700 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3705 /* Read-after-write dependencies on the control registers
3706 require a two-instruction gap. */
3707 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3708 && (pinfo2
& INSN_READ_COND_CODE
))
3711 /* We don't know exactly what INSN1 does. If INSN2 is
3712 also a coprocessor instruction, assume there must be
3713 a one instruction gap. */
3714 if (pinfo2
& INSN_COP
)
3719 /* Check for read-after-write dependencies on the coprocessor
3720 control registers in cases where INSN1 does not need a general
3721 coprocessor delay. This means that INSN1 is a floating point
3722 comparison instruction. */
3723 /* Itbl support may require additional care here. */
3724 else if (!cop_interlocks
3725 && (pinfo1
& INSN_WRITE_COND_CODE
)
3726 && (pinfo2
& INSN_READ_COND_CODE
))
3730 #undef INSN2_USES_GPR
3735 /* Return the number of nops that would be needed to work around the
3736 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3737 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3738 that are contained within the first IGNORE instructions of HIST. */
3741 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3742 const struct mips_cl_insn
*insn
)
3747 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3748 are not affected by the errata. */
3750 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3751 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3752 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3755 /* Search for the first MFLO or MFHI. */
3756 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3757 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3759 /* Extract the destination register. */
3760 mask
= gpr_write_mask (&hist
[i
]);
3762 /* No nops are needed if INSN reads that register. */
3763 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3766 /* ...or if any of the intervening instructions do. */
3767 for (j
= 0; j
< i
; j
++)
3768 if (gpr_read_mask (&hist
[j
]) & mask
)
3772 return MAX_VR4130_NOPS
- i
;
3777 #define BASE_REG_EQ(INSN1, INSN2) \
3778 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3779 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3781 /* Return the minimum alignment for this store instruction. */
3784 fix_24k_align_to (const struct mips_opcode
*mo
)
3786 if (strcmp (mo
->name
, "sh") == 0)
3789 if (strcmp (mo
->name
, "swc1") == 0
3790 || strcmp (mo
->name
, "swc2") == 0
3791 || strcmp (mo
->name
, "sw") == 0
3792 || strcmp (mo
->name
, "sc") == 0
3793 || strcmp (mo
->name
, "s.s") == 0)
3796 if (strcmp (mo
->name
, "sdc1") == 0
3797 || strcmp (mo
->name
, "sdc2") == 0
3798 || strcmp (mo
->name
, "s.d") == 0)
3805 struct fix_24k_store_info
3807 /* Immediate offset, if any, for this store instruction. */
3809 /* Alignment required by this store instruction. */
3811 /* True for register offsets. */
3812 int register_offset
;
3815 /* Comparison function used by qsort. */
3818 fix_24k_sort (const void *a
, const void *b
)
3820 const struct fix_24k_store_info
*pos1
= a
;
3821 const struct fix_24k_store_info
*pos2
= b
;
3823 return (pos1
->off
- pos2
->off
);
3826 /* INSN is a store instruction. Try to record the store information
3827 in STINFO. Return false if the information isn't known. */
3830 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3831 const struct mips_cl_insn
*insn
)
3833 /* The instruction must have a known offset. */
3834 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3837 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3838 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3842 /* Return the number of nops that would be needed to work around the 24k
3843 "lost data on stores during refill" errata if instruction INSN
3844 immediately followed the 2 instructions described by HIST.
3845 Ignore hazards that are contained within the first IGNORE
3846 instructions of HIST.
3848 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3849 for the data cache refills and store data. The following describes
3850 the scenario where the store data could be lost.
3852 * A data cache miss, due to either a load or a store, causing fill
3853 data to be supplied by the memory subsystem
3854 * The first three doublewords of fill data are returned and written
3856 * A sequence of four stores occurs in consecutive cycles around the
3857 final doubleword of the fill:
3861 * Zero, One or more instructions
3864 The four stores A-D must be to different doublewords of the line that
3865 is being filled. The fourth instruction in the sequence above permits
3866 the fill of the final doubleword to be transferred from the FSB into
3867 the cache. In the sequence above, the stores may be either integer
3868 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3869 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3870 different doublewords on the line. If the floating point unit is
3871 running in 1:2 mode, it is not possible to create the sequence above
3872 using only floating point store instructions.
3874 In this case, the cache line being filled is incorrectly marked
3875 invalid, thereby losing the data from any store to the line that
3876 occurs between the original miss and the completion of the five
3877 cycle sequence shown above.
3879 The workarounds are:
3881 * Run the data cache in write-through mode.
3882 * Insert a non-store instruction between
3883 Store A and Store B or Store B and Store C. */
3886 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3887 const struct mips_cl_insn
*insn
)
3889 struct fix_24k_store_info pos
[3];
3890 int align
, i
, base_offset
;
3895 /* If the previous instruction wasn't a store, there's nothing to
3897 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3900 /* If the instructions after the previous one are unknown, we have
3901 to assume the worst. */
3905 /* Check whether we are dealing with three consecutive stores. */
3906 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3907 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3910 /* If we don't know the relationship between the store addresses,
3911 assume the worst. */
3912 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3913 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3916 if (!fix_24k_record_store_info (&pos
[0], insn
)
3917 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3918 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3921 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3923 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3924 X bytes and such that the base register + X is known to be aligned
3927 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3931 align
= pos
[0].align_to
;
3932 base_offset
= pos
[0].off
;
3933 for (i
= 1; i
< 3; i
++)
3934 if (align
< pos
[i
].align_to
)
3936 align
= pos
[i
].align_to
;
3937 base_offset
= pos
[i
].off
;
3939 for (i
= 0; i
< 3; i
++)
3940 pos
[i
].off
-= base_offset
;
3943 pos
[0].off
&= ~align
+ 1;
3944 pos
[1].off
&= ~align
+ 1;
3945 pos
[2].off
&= ~align
+ 1;
3947 /* If any two stores write to the same chunk, they also write to the
3948 same doubleword. The offsets are still sorted at this point. */
3949 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3952 /* A range of at least 9 bytes is needed for the stores to be in
3953 non-overlapping doublewords. */
3954 if (pos
[2].off
- pos
[0].off
<= 8)
3957 if (pos
[2].off
- pos
[1].off
>= 24
3958 || pos
[1].off
- pos
[0].off
>= 24
3959 || pos
[2].off
- pos
[0].off
>= 32)
3965 /* Return the number of nops that would be needed if instruction INSN
3966 immediately followed the MAX_NOPS instructions given by HIST,
3967 where HIST[0] is the most recent instruction. Ignore hazards
3968 between INSN and the first IGNORE instructions in HIST.
3970 If INSN is null, return the worse-case number of nops for any
3974 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3975 const struct mips_cl_insn
*insn
)
3977 int i
, nops
, tmp_nops
;
3980 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3982 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3983 if (tmp_nops
> nops
)
3987 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3989 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3990 if (tmp_nops
> nops
)
3994 if (mips_fix_24k
&& !mips_opts
.micromips
)
3996 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
3997 if (tmp_nops
> nops
)
4004 /* The variable arguments provide NUM_INSNS extra instructions that
4005 might be added to HIST. Return the largest number of nops that
4006 would be needed after the extended sequence, ignoring hazards
4007 in the first IGNORE instructions. */
4010 nops_for_sequence (int num_insns
, int ignore
,
4011 const struct mips_cl_insn
*hist
, ...)
4014 struct mips_cl_insn buffer
[MAX_NOPS
];
4015 struct mips_cl_insn
*cursor
;
4018 va_start (args
, hist
);
4019 cursor
= buffer
+ num_insns
;
4020 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
4021 while (cursor
> buffer
)
4022 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
4024 nops
= nops_for_insn (ignore
, buffer
, NULL
);
4029 /* Like nops_for_insn, but if INSN is a branch, take into account the
4030 worst-case delay for the branch target. */
4033 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
4034 const struct mips_cl_insn
*insn
)
4038 nops
= nops_for_insn (ignore
, hist
, insn
);
4039 if (delayed_branch_p (insn
))
4041 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
4042 hist
, insn
, get_delay_slot_nop (insn
));
4043 if (tmp_nops
> nops
)
4046 else if (compact_branch_p (insn
))
4048 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
4049 if (tmp_nops
> nops
)
4055 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4058 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
4060 gas_assert (!HAVE_CODE_COMPRESSION
);
4061 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
4062 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
4065 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4066 jr target pc &= 'hffff_ffff_cfff_ffff. */
4069 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
4071 gas_assert (!HAVE_CODE_COMPRESSION
);
4072 if (strcmp (ip
->insn_mo
->name
, "j") == 0
4073 || strcmp (ip
->insn_mo
->name
, "jr") == 0
4074 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
4082 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
4083 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
4086 ep
.X_op
= O_constant
;
4087 ep
.X_add_number
= 0xcfff0000;
4088 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
4089 ep
.X_add_number
= 0xffff;
4090 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
4091 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
4096 fix_loongson2f (struct mips_cl_insn
* ip
)
4098 if (mips_fix_loongson2f_nop
)
4099 fix_loongson2f_nop (ip
);
4101 if (mips_fix_loongson2f_jump
)
4102 fix_loongson2f_jump (ip
);
4105 /* IP is a branch that has a delay slot, and we need to fill it
4106 automatically. Return true if we can do that by swapping IP
4107 with the previous instruction.
4108 ADDRESS_EXPR is an operand of the instruction to be used with
4112 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4113 bfd_reloc_code_real_type
*reloc_type
)
4115 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
4116 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
4118 /* -O2 and above is required for this optimization. */
4119 if (mips_optimize
< 2)
4122 /* If we have seen .set volatile or .set nomove, don't optimize. */
4123 if (mips_opts
.nomove
)
4126 /* We can't swap if the previous instruction's position is fixed. */
4127 if (history
[0].fixed_p
)
4130 /* If the previous previous insn was in a .set noreorder, we can't
4131 swap. Actually, the MIPS assembler will swap in this situation.
4132 However, gcc configured -with-gnu-as will generate code like
4140 in which we can not swap the bne and INSN. If gcc is not configured
4141 -with-gnu-as, it does not output the .set pseudo-ops. */
4142 if (history
[1].noreorder_p
)
4145 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4146 This means that the previous instruction was a 4-byte one anyhow. */
4147 if (mips_opts
.mips16
&& history
[0].fixp
[0])
4150 /* If the branch is itself the target of a branch, we can not swap.
4151 We cheat on this; all we check for is whether there is a label on
4152 this instruction. If there are any branches to anything other than
4153 a label, users must use .set noreorder. */
4154 if (seg_info (now_seg
)->label_list
)
4157 /* If the previous instruction is in a variant frag other than this
4158 branch's one, we cannot do the swap. This does not apply to
4159 MIPS16 code, which uses variant frags for different purposes. */
4160 if (!mips_opts
.mips16
4162 && history
[0].frag
->fr_type
== rs_machine_dependent
)
4165 /* We do not swap with instructions that cannot architecturally
4166 be placed in a branch delay slot, such as SYNC or ERET. We
4167 also refrain from swapping with a trap instruction, since it
4168 complicates trap handlers to have the trap instruction be in
4170 prev_pinfo
= history
[0].insn_mo
->pinfo
;
4171 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
4174 /* Check for conflicts between the branch and the instructions
4175 before the candidate delay slot. */
4176 if (nops_for_insn (0, history
+ 1, ip
) > 0)
4179 /* Check for conflicts between the swapped sequence and the
4180 target of the branch. */
4181 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
4184 /* If the branch reads a register that the previous
4185 instruction sets, we can not swap. */
4186 gpr_read
= gpr_read_mask (ip
);
4187 prev_gpr_write
= gpr_write_mask (&history
[0]);
4188 if (gpr_read
& prev_gpr_write
)
4191 /* If the branch writes a register that the previous
4192 instruction sets, we can not swap. */
4193 gpr_write
= gpr_write_mask (ip
);
4194 if (gpr_write
& prev_gpr_write
)
4197 /* If the branch writes a register that the previous
4198 instruction reads, we can not swap. */
4199 prev_gpr_read
= gpr_read_mask (&history
[0]);
4200 if (gpr_write
& prev_gpr_read
)
4203 /* If one instruction sets a condition code and the
4204 other one uses a condition code, we can not swap. */
4205 pinfo
= ip
->insn_mo
->pinfo
;
4206 if ((pinfo
& INSN_READ_COND_CODE
)
4207 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
4209 if ((pinfo
& INSN_WRITE_COND_CODE
)
4210 && (prev_pinfo
& INSN_READ_COND_CODE
))
4213 /* If the previous instruction uses the PC, we can not swap. */
4214 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4215 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
4217 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
4220 /* If the previous instruction has an incorrect size for a fixed
4221 branch delay slot in microMIPS mode, we cannot swap. */
4222 pinfo2
= ip
->insn_mo
->pinfo2
;
4223 if (mips_opts
.micromips
4224 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
4225 && insn_length (history
) != 2)
4227 if (mips_opts
.micromips
4228 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
4229 && insn_length (history
) != 4)
4232 /* On R5900 short loops need to be fixed by inserting a nop in
4233 the branch delay slots.
4234 A short loop can be terminated too early. */
4235 if (mips_opts
.arch
== CPU_R5900
4236 /* Check if instruction has a parameter, ignore "j $31". */
4237 && (address_expr
!= NULL
)
4238 /* Parameter must be 16 bit. */
4239 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
4240 /* Branch to same segment. */
4241 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
4242 /* Branch to same code fragment. */
4243 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
4244 /* Can only calculate branch offset if value is known. */
4245 && symbol_constant_p(address_expr
->X_add_symbol
)
4246 /* Check if branch is really conditional. */
4247 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
4248 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
4249 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
4252 /* Check if loop is shorter than 6 instructions including
4253 branch and delay slot. */
4254 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
4261 /* When the loop includes branches or jumps,
4262 it is not a short loop. */
4263 for (i
= 0; i
< (distance
/ 4); i
++)
4265 if ((history
[i
].cleared_p
)
4266 || delayed_branch_p(&history
[i
]))
4274 /* Insert nop after branch to fix short loop. */
4283 /* Decide how we should add IP to the instruction stream.
4284 ADDRESS_EXPR is an operand of the instruction to be used with
4287 static enum append_method
4288 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4289 bfd_reloc_code_real_type
*reloc_type
)
4291 unsigned long pinfo
;
4293 /* The relaxed version of a macro sequence must be inherently
4295 if (mips_relax
.sequence
== 2)
4298 /* We must not dabble with instructions in a ".set norerorder" block. */
4299 if (mips_opts
.noreorder
)
4302 /* Otherwise, it's our responsibility to fill branch delay slots. */
4303 if (delayed_branch_p (ip
))
4305 if (!branch_likely_p (ip
)
4306 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
4309 pinfo
= ip
->insn_mo
->pinfo
;
4310 if (mips_opts
.mips16
4311 && ISA_SUPPORTS_MIPS16E
4312 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
4313 return APPEND_ADD_COMPACT
;
4315 return APPEND_ADD_WITH_NOP
;
4321 /* IP is a MIPS16 instruction whose opcode we have just changed.
4322 Point IP->insn_mo to the new opcode's definition. */
4325 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
4327 const struct mips_opcode
*mo
, *end
;
4329 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
4330 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
4331 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4339 /* For microMIPS macros, we need to generate a local number label
4340 as the target of branches. */
4341 #define MICROMIPS_LABEL_CHAR '\037'
4342 static unsigned long micromips_target_label
;
4343 static char micromips_target_name
[32];
4346 micromips_label_name (void)
4348 char *p
= micromips_target_name
;
4349 char symbol_name_temporary
[24];
4357 l
= micromips_target_label
;
4358 #ifdef LOCAL_LABEL_PREFIX
4359 *p
++ = LOCAL_LABEL_PREFIX
;
4362 *p
++ = MICROMIPS_LABEL_CHAR
;
4365 symbol_name_temporary
[i
++] = l
% 10 + '0';
4370 *p
++ = symbol_name_temporary
[--i
];
4373 return micromips_target_name
;
4377 micromips_label_expr (expressionS
*label_expr
)
4379 label_expr
->X_op
= O_symbol
;
4380 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4381 label_expr
->X_add_number
= 0;
4385 micromips_label_inc (void)
4387 micromips_target_label
++;
4388 *micromips_target_name
= '\0';
4392 micromips_add_label (void)
4396 s
= colon (micromips_label_name ());
4397 micromips_label_inc ();
4398 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4400 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4406 /* If assembling microMIPS code, then return the microMIPS reloc
4407 corresponding to the requested one if any. Otherwise return
4408 the reloc unchanged. */
4410 static bfd_reloc_code_real_type
4411 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4413 static const bfd_reloc_code_real_type relocs
[][2] =
4415 /* Keep sorted incrementally by the left-hand key. */
4416 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4417 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4418 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4419 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4420 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4421 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4422 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4423 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4424 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4425 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4426 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4427 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4428 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4429 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4430 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4431 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4432 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4433 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4434 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4435 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4436 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4437 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4438 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4439 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4440 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4441 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4442 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4444 bfd_reloc_code_real_type r
;
4447 if (!mips_opts
.micromips
)
4449 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4455 return relocs
[i
][1];
4460 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4461 Return true on success, storing the resolved value in RESULT. */
4464 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4469 case BFD_RELOC_MIPS_HIGHEST
:
4470 case BFD_RELOC_MICROMIPS_HIGHEST
:
4471 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4474 case BFD_RELOC_MIPS_HIGHER
:
4475 case BFD_RELOC_MICROMIPS_HIGHER
:
4476 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4479 case BFD_RELOC_HI16_S
:
4480 case BFD_RELOC_MICROMIPS_HI16_S
:
4481 case BFD_RELOC_MIPS16_HI16_S
:
4482 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4485 case BFD_RELOC_HI16
:
4486 case BFD_RELOC_MICROMIPS_HI16
:
4487 case BFD_RELOC_MIPS16_HI16
:
4488 *result
= (operand
>> 16) & 0xffff;
4491 case BFD_RELOC_LO16
:
4492 case BFD_RELOC_MICROMIPS_LO16
:
4493 case BFD_RELOC_MIPS16_LO16
:
4494 *result
= operand
& 0xffff;
4497 case BFD_RELOC_UNUSED
:
4506 /* Output an instruction. IP is the instruction information.
4507 ADDRESS_EXPR is an operand of the instruction to be used with
4508 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4509 a macro expansion. */
4512 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4513 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4515 unsigned long prev_pinfo2
, pinfo
;
4516 bfd_boolean relaxed_branch
= FALSE
;
4517 enum append_method method
;
4518 bfd_boolean relax32
;
4521 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4522 fix_loongson2f (ip
);
4524 file_ase_mips16
|= mips_opts
.mips16
;
4525 file_ase_micromips
|= mips_opts
.micromips
;
4527 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4528 pinfo
= ip
->insn_mo
->pinfo
;
4530 if (mips_opts
.micromips
4532 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4533 && micromips_insn_length (ip
->insn_mo
) != 2)
4534 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4535 && micromips_insn_length (ip
->insn_mo
) != 4)))
4536 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4537 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4539 if (address_expr
== NULL
)
4541 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4542 && reloc_type
[1] == BFD_RELOC_UNUSED
4543 && reloc_type
[2] == BFD_RELOC_UNUSED
4544 && address_expr
->X_op
== O_constant
)
4546 switch (*reloc_type
)
4548 case BFD_RELOC_MIPS_JMP
:
4552 shift
= mips_opts
.micromips
? 1 : 2;
4553 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4554 as_bad (_("jump to misaligned address (0x%lx)"),
4555 (unsigned long) address_expr
->X_add_number
);
4556 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4562 case BFD_RELOC_MIPS16_JMP
:
4563 if ((address_expr
->X_add_number
& 3) != 0)
4564 as_bad (_("jump to misaligned address (0x%lx)"),
4565 (unsigned long) address_expr
->X_add_number
);
4567 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4568 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4569 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4573 case BFD_RELOC_16_PCREL_S2
:
4577 shift
= mips_opts
.micromips
? 1 : 2;
4578 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4579 as_bad (_("branch to misaligned address (0x%lx)"),
4580 (unsigned long) address_expr
->X_add_number
);
4581 if (!mips_relax_branch
)
4583 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4584 & ~((1 << (shift
+ 16)) - 1))
4585 as_bad (_("branch address range overflow (0x%lx)"),
4586 (unsigned long) address_expr
->X_add_number
);
4587 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4597 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4600 ip
->insn_opcode
|= value
& 0xffff;
4608 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4610 /* There are a lot of optimizations we could do that we don't.
4611 In particular, we do not, in general, reorder instructions.
4612 If you use gcc with optimization, it will reorder
4613 instructions and generally do much more optimization then we
4614 do here; repeating all that work in the assembler would only
4615 benefit hand written assembly code, and does not seem worth
4617 int nops
= (mips_optimize
== 0
4618 ? nops_for_insn (0, history
, NULL
)
4619 : nops_for_insn_or_target (0, history
, ip
));
4623 unsigned long old_frag_offset
;
4626 old_frag
= frag_now
;
4627 old_frag_offset
= frag_now_fix ();
4629 for (i
= 0; i
< nops
; i
++)
4630 add_fixed_insn (NOP_INSN
);
4631 insert_into_history (0, nops
, NOP_INSN
);
4635 listing_prev_line ();
4636 /* We may be at the start of a variant frag. In case we
4637 are, make sure there is enough space for the frag
4638 after the frags created by listing_prev_line. The
4639 argument to frag_grow here must be at least as large
4640 as the argument to all other calls to frag_grow in
4641 this file. We don't have to worry about being in the
4642 middle of a variant frag, because the variants insert
4643 all needed nop instructions themselves. */
4647 mips_move_text_labels ();
4649 #ifndef NO_ECOFF_DEBUGGING
4650 if (ECOFF_DEBUGGING
)
4651 ecoff_fix_loc (old_frag
, old_frag_offset
);
4655 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4659 /* Work out how many nops in prev_nop_frag are needed by IP,
4660 ignoring hazards generated by the first prev_nop_frag_since
4662 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4663 gas_assert (nops
<= prev_nop_frag_holds
);
4665 /* Enforce NOPS as a minimum. */
4666 if (nops
> prev_nop_frag_required
)
4667 prev_nop_frag_required
= nops
;
4669 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4671 /* Settle for the current number of nops. Update the history
4672 accordingly (for the benefit of any future .set reorder code). */
4673 prev_nop_frag
= NULL
;
4674 insert_into_history (prev_nop_frag_since
,
4675 prev_nop_frag_holds
, NOP_INSN
);
4679 /* Allow this instruction to replace one of the nops that was
4680 tentatively added to prev_nop_frag. */
4681 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4682 prev_nop_frag_holds
--;
4683 prev_nop_frag_since
++;
4687 method
= get_append_method (ip
, address_expr
, reloc_type
);
4688 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4691 dwarf2_emit_insn (0);
4692 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4693 so "move" the instruction address accordingly.
4695 Also, it doesn't seem appropriate for the assembler to reorder .loc
4696 entries. If this instruction is a branch that we are going to swap
4697 with the previous instruction, the two instructions should be
4698 treated as a unit, and the debug information for both instructions
4699 should refer to the start of the branch sequence. Using the
4700 current position is certainly wrong when swapping a 32-bit branch
4701 and a 16-bit delay slot, since the current position would then be
4702 in the middle of a branch. */
4703 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
4706 relax32
= (mips_relax_branch
4707 /* Don't try branch relaxation within .set nomacro, or within
4708 .set noat if we use $at for PIC computations. If it turns
4709 out that the branch was out-of-range, we'll get an error. */
4710 && !mips_opts
.warn_about_macros
4711 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4712 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4713 as they have no complementing branches. */
4714 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
4716 if (!HAVE_CODE_COMPRESSION
4719 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4720 && delayed_branch_p (ip
))
4722 relaxed_branch
= TRUE
;
4723 add_relaxed_insn (ip
, (relaxed_branch_length
4725 uncond_branch_p (ip
) ? -1
4726 : branch_likely_p (ip
) ? 1
4730 uncond_branch_p (ip
),
4731 branch_likely_p (ip
),
4732 pinfo
& INSN_WRITE_GPR_31
,
4734 address_expr
->X_add_symbol
,
4735 address_expr
->X_add_number
);
4736 *reloc_type
= BFD_RELOC_UNUSED
;
4738 else if (mips_opts
.micromips
4740 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4741 || *reloc_type
> BFD_RELOC_UNUSED
)
4742 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4743 /* Don't try branch relaxation when users specify
4744 16-bit/32-bit instructions. */
4745 && !forced_insn_length
)
4747 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4748 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4749 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4750 int compact
= compact_branch_p (ip
);
4751 int al
= pinfo
& INSN_WRITE_GPR_31
;
4754 gas_assert (address_expr
!= NULL
);
4755 gas_assert (!mips_relax
.sequence
);
4757 relaxed_branch
= TRUE
;
4758 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4759 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4760 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4762 address_expr
->X_add_symbol
,
4763 address_expr
->X_add_number
);
4764 *reloc_type
= BFD_RELOC_UNUSED
;
4766 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4768 /* We need to set up a variant frag. */
4769 gas_assert (address_expr
!= NULL
);
4770 add_relaxed_insn (ip
, 4, 0,
4772 (*reloc_type
- BFD_RELOC_UNUSED
,
4773 forced_insn_length
== 2, forced_insn_length
== 4,
4774 delayed_branch_p (&history
[0]),
4775 history
[0].mips16_absolute_jump_p
),
4776 make_expr_symbol (address_expr
), 0);
4778 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4780 if (!delayed_branch_p (ip
))
4781 /* Make sure there is enough room to swap this instruction with
4782 a following jump instruction. */
4784 add_fixed_insn (ip
);
4788 if (mips_opts
.mips16
4789 && mips_opts
.noreorder
4790 && delayed_branch_p (&history
[0]))
4791 as_warn (_("extended instruction in delay slot"));
4793 if (mips_relax
.sequence
)
4795 /* If we've reached the end of this frag, turn it into a variant
4796 frag and record the information for the instructions we've
4798 if (frag_room () < 4)
4799 relax_close_frag ();
4800 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4803 if (mips_relax
.sequence
!= 2)
4805 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4806 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4807 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4808 mips_macro_warning
.insns
[0]++;
4810 if (mips_relax
.sequence
!= 1)
4812 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4813 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4814 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4815 mips_macro_warning
.insns
[1]++;
4818 if (mips_opts
.mips16
)
4821 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4823 add_fixed_insn (ip
);
4826 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4828 bfd_reloc_code_real_type final_type
[3];
4829 reloc_howto_type
*howto0
;
4830 reloc_howto_type
*howto
;
4833 /* Perform any necessary conversion to microMIPS relocations
4834 and find out how many relocations there actually are. */
4835 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4836 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4838 /* In a compound relocation, it is the final (outermost)
4839 operator that determines the relocated field. */
4840 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4845 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4846 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4847 bfd_get_reloc_size (howto
),
4849 howto0
&& howto0
->pc_relative
,
4852 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4853 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4854 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4856 /* These relocations can have an addend that won't fit in
4857 4 octets for 64bit assembly. */
4859 && ! howto
->partial_inplace
4860 && (reloc_type
[0] == BFD_RELOC_16
4861 || reloc_type
[0] == BFD_RELOC_32
4862 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4863 || reloc_type
[0] == BFD_RELOC_GPREL16
4864 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4865 || reloc_type
[0] == BFD_RELOC_GPREL32
4866 || reloc_type
[0] == BFD_RELOC_64
4867 || reloc_type
[0] == BFD_RELOC_CTOR
4868 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4869 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4870 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4871 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4872 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4873 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4874 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4875 || hi16_reloc_p (reloc_type
[0])
4876 || lo16_reloc_p (reloc_type
[0])))
4877 ip
->fixp
[0]->fx_no_overflow
= 1;
4879 /* These relocations can have an addend that won't fit in 2 octets. */
4880 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4881 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4882 ip
->fixp
[0]->fx_no_overflow
= 1;
4884 if (mips_relax
.sequence
)
4886 if (mips_relax
.first_fixup
== 0)
4887 mips_relax
.first_fixup
= ip
->fixp
[0];
4889 else if (reloc_needs_lo_p (*reloc_type
))
4891 struct mips_hi_fixup
*hi_fixup
;
4893 /* Reuse the last entry if it already has a matching %lo. */
4894 hi_fixup
= mips_hi_fixup_list
;
4896 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4898 hi_fixup
= ((struct mips_hi_fixup
*)
4899 xmalloc (sizeof (struct mips_hi_fixup
)));
4900 hi_fixup
->next
= mips_hi_fixup_list
;
4901 mips_hi_fixup_list
= hi_fixup
;
4903 hi_fixup
->fixp
= ip
->fixp
[0];
4904 hi_fixup
->seg
= now_seg
;
4907 /* Add fixups for the second and third relocations, if given.
4908 Note that the ABI allows the second relocation to be
4909 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4910 moment we only use RSS_UNDEF, but we could add support
4911 for the others if it ever becomes necessary. */
4912 for (i
= 1; i
< 3; i
++)
4913 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4915 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4916 ip
->fixp
[0]->fx_size
, NULL
, 0,
4917 FALSE
, final_type
[i
]);
4919 /* Use fx_tcbit to mark compound relocs. */
4920 ip
->fixp
[0]->fx_tcbit
= 1;
4921 ip
->fixp
[i
]->fx_tcbit
= 1;
4926 /* Update the register mask information. */
4927 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4928 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4933 insert_into_history (0, 1, ip
);
4936 case APPEND_ADD_WITH_NOP
:
4938 struct mips_cl_insn
*nop
;
4940 insert_into_history (0, 1, ip
);
4941 nop
= get_delay_slot_nop (ip
);
4942 add_fixed_insn (nop
);
4943 insert_into_history (0, 1, nop
);
4944 if (mips_relax
.sequence
)
4945 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4949 case APPEND_ADD_COMPACT
:
4950 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4951 gas_assert (mips_opts
.mips16
);
4952 ip
->insn_opcode
|= 0x0080;
4953 find_altered_mips16_opcode (ip
);
4955 insert_into_history (0, 1, ip
);
4960 struct mips_cl_insn delay
= history
[0];
4961 if (mips_opts
.mips16
)
4963 know (delay
.frag
== ip
->frag
);
4964 move_insn (ip
, delay
.frag
, delay
.where
);
4965 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4967 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4969 /* Add the delay slot instruction to the end of the
4970 current frag and shrink the fixed part of the
4971 original frag. If the branch occupies the tail of
4972 the latter, move it backwards to cover the gap. */
4973 delay
.frag
->fr_fix
-= branch_disp
;
4974 if (delay
.frag
== ip
->frag
)
4975 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4976 add_fixed_insn (&delay
);
4980 move_insn (&delay
, ip
->frag
,
4981 ip
->where
- branch_disp
+ insn_length (ip
));
4982 move_insn (ip
, history
[0].frag
, history
[0].where
);
4986 insert_into_history (0, 1, &delay
);
4991 /* If we have just completed an unconditional branch, clear the history. */
4992 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4993 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4997 mips_no_prev_insn ();
4999 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5000 history
[i
].cleared_p
= 1;
5003 /* We need to emit a label at the end of branch-likely macros. */
5004 if (emit_branch_likely_macro
)
5006 emit_branch_likely_macro
= FALSE
;
5007 micromips_add_label ();
5010 /* We just output an insn, so the next one doesn't have a label. */
5011 mips_clear_insn_labels ();
5014 /* Forget that there was any previous instruction or label.
5015 When BRANCH is true, the branch history is also flushed. */
5018 mips_no_prev_insn (void)
5020 prev_nop_frag
= NULL
;
5021 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
5022 mips_clear_insn_labels ();
5025 /* This function must be called before we emit something other than
5026 instructions. It is like mips_no_prev_insn except that it inserts
5027 any NOPS that might be needed by previous instructions. */
5030 mips_emit_delays (void)
5032 if (! mips_opts
.noreorder
)
5034 int nops
= nops_for_insn (0, history
, NULL
);
5038 add_fixed_insn (NOP_INSN
);
5039 mips_move_text_labels ();
5042 mips_no_prev_insn ();
5045 /* Start a (possibly nested) noreorder block. */
5048 start_noreorder (void)
5050 if (mips_opts
.noreorder
== 0)
5055 /* None of the instructions before the .set noreorder can be moved. */
5056 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5057 history
[i
].fixed_p
= 1;
5059 /* Insert any nops that might be needed between the .set noreorder
5060 block and the previous instructions. We will later remove any
5061 nops that turn out not to be needed. */
5062 nops
= nops_for_insn (0, history
, NULL
);
5065 if (mips_optimize
!= 0)
5067 /* Record the frag which holds the nop instructions, so
5068 that we can remove them if we don't need them. */
5069 frag_grow (nops
* NOP_INSN_SIZE
);
5070 prev_nop_frag
= frag_now
;
5071 prev_nop_frag_holds
= nops
;
5072 prev_nop_frag_required
= 0;
5073 prev_nop_frag_since
= 0;
5076 for (; nops
> 0; --nops
)
5077 add_fixed_insn (NOP_INSN
);
5079 /* Move on to a new frag, so that it is safe to simply
5080 decrease the size of prev_nop_frag. */
5081 frag_wane (frag_now
);
5083 mips_move_text_labels ();
5085 mips_mark_labels ();
5086 mips_clear_insn_labels ();
5088 mips_opts
.noreorder
++;
5089 mips_any_noreorder
= 1;
5092 /* End a nested noreorder block. */
5095 end_noreorder (void)
5097 mips_opts
.noreorder
--;
5098 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
5100 /* Commit to inserting prev_nop_frag_required nops and go back to
5101 handling nop insertion the .set reorder way. */
5102 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
5104 insert_into_history (prev_nop_frag_since
,
5105 prev_nop_frag_required
, NOP_INSN
);
5106 prev_nop_frag
= NULL
;
5110 /* Set up global variables for the start of a new macro. */
5115 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
5116 memset (&mips_macro_warning
.first_insn_sizes
, 0,
5117 sizeof (mips_macro_warning
.first_insn_sizes
));
5118 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
5119 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
5120 && delayed_branch_p (&history
[0]));
5121 switch (history
[0].insn_mo
->pinfo2
5122 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
5124 case INSN2_BRANCH_DELAY_32BIT
:
5125 mips_macro_warning
.delay_slot_length
= 4;
5127 case INSN2_BRANCH_DELAY_16BIT
:
5128 mips_macro_warning
.delay_slot_length
= 2;
5131 mips_macro_warning
.delay_slot_length
= 0;
5134 mips_macro_warning
.first_frag
= NULL
;
5137 /* Given that a macro is longer than one instruction or of the wrong size,
5138 return the appropriate warning for it. Return null if no warning is
5139 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5140 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5141 and RELAX_NOMACRO. */
5144 macro_warning (relax_substateT subtype
)
5146 if (subtype
& RELAX_DELAY_SLOT
)
5147 return _("Macro instruction expanded into multiple instructions"
5148 " in a branch delay slot");
5149 else if (subtype
& RELAX_NOMACRO
)
5150 return _("Macro instruction expanded into multiple instructions");
5151 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
5152 | RELAX_DELAY_SLOT_SIZE_SECOND
))
5153 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
5154 ? _("Macro instruction expanded into a wrong size instruction"
5155 " in a 16-bit branch delay slot")
5156 : _("Macro instruction expanded into a wrong size instruction"
5157 " in a 32-bit branch delay slot"));
5162 /* Finish up a macro. Emit warnings as appropriate. */
5167 /* Relaxation warning flags. */
5168 relax_substateT subtype
= 0;
5170 /* Check delay slot size requirements. */
5171 if (mips_macro_warning
.delay_slot_length
== 2)
5172 subtype
|= RELAX_DELAY_SLOT_16BIT
;
5173 if (mips_macro_warning
.delay_slot_length
!= 0)
5175 if (mips_macro_warning
.delay_slot_length
5176 != mips_macro_warning
.first_insn_sizes
[0])
5177 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
5178 if (mips_macro_warning
.delay_slot_length
5179 != mips_macro_warning
.first_insn_sizes
[1])
5180 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
5183 /* Check instruction count requirements. */
5184 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
5186 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
5187 subtype
|= RELAX_SECOND_LONGER
;
5188 if (mips_opts
.warn_about_macros
)
5189 subtype
|= RELAX_NOMACRO
;
5190 if (mips_macro_warning
.delay_slot_p
)
5191 subtype
|= RELAX_DELAY_SLOT
;
5194 /* If both alternatives fail to fill a delay slot correctly,
5195 emit the warning now. */
5196 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
5197 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
5202 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
5203 | RELAX_DELAY_SLOT_SIZE_FIRST
5204 | RELAX_DELAY_SLOT_SIZE_SECOND
);
5205 msg
= macro_warning (s
);
5207 as_warn ("%s", msg
);
5211 /* If both implementations are longer than 1 instruction, then emit the
5213 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
5218 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
5219 msg
= macro_warning (s
);
5221 as_warn ("%s", msg
);
5225 /* If any flags still set, then one implementation might need a warning
5226 and the other either will need one of a different kind or none at all.
5227 Pass any remaining flags over to relaxation. */
5228 if (mips_macro_warning
.first_frag
!= NULL
)
5229 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
5232 /* Instruction operand formats used in macros that vary between
5233 standard MIPS and microMIPS code. */
5235 static const char * const brk_fmt
[2] = { "c", "mF" };
5236 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
5237 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
5238 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
5239 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
5240 static const char * const mfhl_fmt
[2] = { "d", "mj" };
5241 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
5242 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
5244 #define BRK_FMT (brk_fmt[mips_opts.micromips])
5245 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5246 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5247 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5248 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5249 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
5250 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5251 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5253 /* Read a macro's relocation codes from *ARGS and store them in *R.
5254 The first argument in *ARGS will be either the code for a single
5255 relocation or -1 followed by the three codes that make up a
5256 composite relocation. */
5259 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
5263 next
= va_arg (*args
, int);
5265 r
[0] = (bfd_reloc_code_real_type
) next
;
5267 for (i
= 0; i
< 3; i
++)
5268 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
5271 /* Build an instruction created by a macro expansion. This is passed
5272 a pointer to the count of instructions created so far, an
5273 expression, the name of the instruction to build, an operand format
5274 string, and corresponding arguments. */
5277 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
5279 const struct mips_opcode
*mo
= NULL
;
5280 bfd_reloc_code_real_type r
[3];
5281 const struct mips_opcode
*amo
;
5282 struct hash_control
*hash
;
5283 struct mips_cl_insn insn
;
5286 va_start (args
, fmt
);
5288 if (mips_opts
.mips16
)
5290 mips16_macro_build (ep
, name
, fmt
, &args
);
5295 r
[0] = BFD_RELOC_UNUSED
;
5296 r
[1] = BFD_RELOC_UNUSED
;
5297 r
[2] = BFD_RELOC_UNUSED
;
5298 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
5299 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
5301 gas_assert (strcmp (name
, amo
->name
) == 0);
5305 /* Search until we get a match for NAME. It is assumed here that
5306 macros will never generate MDMX, MIPS-3D, or MT instructions.
5307 We try to match an instruction that fulfils the branch delay
5308 slot instruction length requirement (if any) of the previous
5309 instruction. While doing this we record the first instruction
5310 seen that matches all the other conditions and use it anyway
5311 if the requirement cannot be met; we will issue an appropriate
5312 warning later on. */
5313 if (strcmp (fmt
, amo
->args
) == 0
5314 && amo
->pinfo
!= INSN_MACRO
5315 && is_opcode_valid (amo
)
5316 && is_size_valid (amo
))
5318 if (is_delay_slot_valid (amo
))
5328 gas_assert (amo
->name
);
5330 while (strcmp (name
, amo
->name
) == 0);
5333 create_insn (&insn
, mo
);
5351 INSERT_OPERAND (mips_opts
.micromips
,
5352 EXTLSB
, insn
, va_arg (args
, int));
5357 /* Note that in the macro case, these arguments are already
5358 in MSB form. (When handling the instruction in the
5359 non-macro case, these arguments are sizes from which
5360 MSB values must be calculated.) */
5361 INSERT_OPERAND (mips_opts
.micromips
,
5362 INSMSB
, insn
, va_arg (args
, int));
5366 gas_assert (!mips_opts
.micromips
);
5367 INSERT_OPERAND (0, CODE10
, insn
, va_arg (args
, int));
5373 /* Note that in the macro case, these arguments are already
5374 in MSBD form. (When handling the instruction in the
5375 non-macro case, these arguments are sizes from which
5376 MSBD values must be calculated.) */
5377 INSERT_OPERAND (mips_opts
.micromips
,
5378 EXTMSBD
, insn
, va_arg (args
, int));
5382 gas_assert (!mips_opts
.micromips
);
5383 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5387 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, insn
, va_arg (args
, int));
5396 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5400 gas_assert (mips_opts
.micromips
);
5404 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5408 gas_assert (!mips_opts
.micromips
);
5409 INSERT_OPERAND (0, CODE
, insn
, va_arg (args
, int));
5413 gas_assert (!mips_opts
.micromips
);
5415 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5419 if (mips_opts
.micromips
)
5420 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5422 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5426 gas_assert (!mips_opts
.micromips
);
5428 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5432 gas_assert (!mips_opts
.micromips
);
5434 int tmp
= va_arg (args
, int);
5436 INSERT_OPERAND (0, RT
, insn
, tmp
);
5437 INSERT_OPERAND (0, RD
, insn
, tmp
);
5443 gas_assert (!mips_opts
.micromips
);
5444 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5451 INSERT_OPERAND (mips_opts
.micromips
,
5452 SHAMT
, insn
, va_arg (args
, int));
5456 gas_assert (!mips_opts
.micromips
);
5457 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5461 gas_assert (!mips_opts
.micromips
);
5462 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5466 gas_assert (!mips_opts
.micromips
);
5467 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5471 gas_assert (!mips_opts
.micromips
);
5472 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5479 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5484 macro_read_relocs (&args
, r
);
5485 gas_assert (*r
== BFD_RELOC_GPREL16
5486 || *r
== BFD_RELOC_MIPS_HIGHER
5487 || *r
== BFD_RELOC_HI16_S
5488 || *r
== BFD_RELOC_LO16
5489 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5493 macro_read_relocs (&args
, r
);
5497 macro_read_relocs (&args
, r
);
5498 gas_assert (ep
!= NULL
5499 && (ep
->X_op
== O_constant
5500 || (ep
->X_op
== O_symbol
5501 && (*r
== BFD_RELOC_MIPS_HIGHEST
5502 || *r
== BFD_RELOC_HI16_S
5503 || *r
== BFD_RELOC_HI16
5504 || *r
== BFD_RELOC_GPREL16
5505 || *r
== BFD_RELOC_MIPS_GOT_HI16
5506 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5510 gas_assert (ep
!= NULL
);
5513 * This allows macro() to pass an immediate expression for
5514 * creating short branches without creating a symbol.
5516 * We don't allow branch relaxation for these branches, as
5517 * they should only appear in ".set nomacro" anyway.
5519 if (ep
->X_op
== O_constant
)
5521 /* For microMIPS we always use relocations for branches.
5522 So we should not resolve immediate values. */
5523 gas_assert (!mips_opts
.micromips
);
5525 if ((ep
->X_add_number
& 3) != 0)
5526 as_bad (_("branch to misaligned address (0x%lx)"),
5527 (unsigned long) ep
->X_add_number
);
5528 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5529 as_bad (_("branch address range overflow (0x%lx)"),
5530 (unsigned long) ep
->X_add_number
);
5531 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5535 *r
= BFD_RELOC_16_PCREL_S2
;
5539 gas_assert (ep
!= NULL
);
5540 *r
= BFD_RELOC_MIPS_JMP
;
5544 gas_assert (!mips_opts
.micromips
);
5545 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5549 INSERT_OPERAND (mips_opts
.micromips
,
5550 CACHE
, insn
, va_arg (args
, unsigned long));
5554 gas_assert (mips_opts
.micromips
);
5555 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5559 gas_assert (mips_opts
.micromips
);
5560 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5564 INSERT_OPERAND (mips_opts
.micromips
,
5565 3BITPOS
, insn
, va_arg (args
, unsigned int));
5569 INSERT_OPERAND (mips_opts
.micromips
,
5570 OFFSET12
, insn
, va_arg (args
, unsigned long));
5574 gas_assert (mips_opts
.micromips
);
5575 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5578 case 'm': /* Opcode extension character. */
5579 gas_assert (mips_opts
.micromips
);
5583 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5587 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5591 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5605 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5607 append_insn (&insn
, ep
, r
, TRUE
);
5611 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5614 struct mips_opcode
*mo
;
5615 struct mips_cl_insn insn
;
5616 bfd_reloc_code_real_type r
[3]
5617 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5619 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5621 gas_assert (strcmp (name
, mo
->name
) == 0);
5623 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5626 gas_assert (mo
->name
);
5627 gas_assert (strcmp (name
, mo
->name
) == 0);
5630 create_insn (&insn
, mo
);
5648 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5653 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5657 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5661 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5671 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5678 regno
= va_arg (*args
, int);
5679 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5680 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5703 gas_assert (ep
!= NULL
);
5705 if (ep
->X_op
!= O_constant
)
5706 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5707 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5709 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5711 *r
= BFD_RELOC_UNUSED
;
5717 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5724 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5726 append_insn (&insn
, ep
, r
, TRUE
);
5730 * Sign-extend 32-bit mode constants that have bit 31 set and all
5731 * higher bits unset.
5734 normalize_constant_expr (expressionS
*ex
)
5736 if (ex
->X_op
== O_constant
5737 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5738 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5743 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5744 * all higher bits unset.
5747 normalize_address_expr (expressionS
*ex
)
5749 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5750 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5751 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5752 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5757 * Generate a "jalr" instruction with a relocation hint to the called
5758 * function. This occurs in NewABI PIC code.
5761 macro_build_jalr (expressionS
*ep
, int cprestore
)
5763 static const bfd_reloc_code_real_type jalr_relocs
[2]
5764 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5765 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5769 if (MIPS_JALR_HINT_P (ep
))
5774 if (mips_opts
.micromips
)
5776 jalr
= mips_opts
.noreorder
&& !cprestore
? "jalr" : "jalrs";
5777 if (MIPS_JALR_HINT_P (ep
)
5778 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5779 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5781 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5784 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5785 if (MIPS_JALR_HINT_P (ep
))
5786 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5790 * Generate a "lui" instruction.
5793 macro_build_lui (expressionS
*ep
, int regnum
)
5795 gas_assert (! mips_opts
.mips16
);
5797 if (ep
->X_op
!= O_constant
)
5799 gas_assert (ep
->X_op
== O_symbol
);
5800 /* _gp_disp is a special case, used from s_cpload.
5801 __gnu_local_gp is used if mips_no_shared. */
5802 gas_assert (mips_pic
== NO_PIC
5804 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5805 || (! mips_in_shared
5806 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5807 "__gnu_local_gp") == 0));
5810 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5813 /* Generate a sequence of instructions to do a load or store from a constant
5814 offset off of a base register (breg) into/from a target register (treg),
5815 using AT if necessary. */
5817 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5818 int treg
, int breg
, int dbl
)
5820 gas_assert (ep
->X_op
== O_constant
);
5822 /* Sign-extending 32-bit constants makes their handling easier. */
5824 normalize_constant_expr (ep
);
5826 /* Right now, this routine can only handle signed 32-bit constants. */
5827 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5828 as_warn (_("operand overflow"));
5830 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5832 /* Signed 16-bit offset will fit in the op. Easy! */
5833 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5837 /* 32-bit offset, need multiple instructions and AT, like:
5838 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5839 addu $tempreg,$tempreg,$breg
5840 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5841 to handle the complete offset. */
5842 macro_build_lui (ep
, AT
);
5843 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5844 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5847 as_bad (_("Macro used $at after \".set noat\""));
5852 * Generates code to set the $at register to true (one)
5853 * if reg is less than the immediate expression.
5856 set_at (int reg
, int unsignedp
)
5858 if (imm_expr
.X_op
== O_constant
5859 && imm_expr
.X_add_number
>= -0x8000
5860 && imm_expr
.X_add_number
< 0x8000)
5861 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5862 AT
, reg
, BFD_RELOC_LO16
);
5865 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5866 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5870 /* Warn if an expression is not a constant. */
5873 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5875 if (ex
->X_op
== O_big
)
5876 as_bad (_("unsupported large constant"));
5877 else if (ex
->X_op
!= O_constant
)
5878 as_bad (_("Instruction %s requires absolute expression"),
5881 if (HAVE_32BIT_GPRS
)
5882 normalize_constant_expr (ex
);
5885 /* Count the leading zeroes by performing a binary chop. This is a
5886 bulky bit of source, but performance is a LOT better for the
5887 majority of values than a simple loop to count the bits:
5888 for (lcnt = 0; (lcnt < 32); lcnt++)
5889 if ((v) & (1 << (31 - lcnt)))
5891 However it is not code size friendly, and the gain will drop a bit
5892 on certain cached systems.
5894 #define COUNT_TOP_ZEROES(v) \
5895 (((v) & ~0xffff) == 0 \
5896 ? ((v) & ~0xff) == 0 \
5897 ? ((v) & ~0xf) == 0 \
5898 ? ((v) & ~0x3) == 0 \
5899 ? ((v) & ~0x1) == 0 \
5904 : ((v) & ~0x7) == 0 \
5907 : ((v) & ~0x3f) == 0 \
5908 ? ((v) & ~0x1f) == 0 \
5911 : ((v) & ~0x7f) == 0 \
5914 : ((v) & ~0xfff) == 0 \
5915 ? ((v) & ~0x3ff) == 0 \
5916 ? ((v) & ~0x1ff) == 0 \
5919 : ((v) & ~0x7ff) == 0 \
5922 : ((v) & ~0x3fff) == 0 \
5923 ? ((v) & ~0x1fff) == 0 \
5926 : ((v) & ~0x7fff) == 0 \
5929 : ((v) & ~0xffffff) == 0 \
5930 ? ((v) & ~0xfffff) == 0 \
5931 ? ((v) & ~0x3ffff) == 0 \
5932 ? ((v) & ~0x1ffff) == 0 \
5935 : ((v) & ~0x7ffff) == 0 \
5938 : ((v) & ~0x3fffff) == 0 \
5939 ? ((v) & ~0x1fffff) == 0 \
5942 : ((v) & ~0x7fffff) == 0 \
5945 : ((v) & ~0xfffffff) == 0 \
5946 ? ((v) & ~0x3ffffff) == 0 \
5947 ? ((v) & ~0x1ffffff) == 0 \
5950 : ((v) & ~0x7ffffff) == 0 \
5953 : ((v) & ~0x3fffffff) == 0 \
5954 ? ((v) & ~0x1fffffff) == 0 \
5957 : ((v) & ~0x7fffffff) == 0 \
5962 * This routine generates the least number of instructions necessary to load
5963 * an absolute expression value into a register.
5966 load_register (int reg
, expressionS
*ep
, int dbl
)
5969 expressionS hi32
, lo32
;
5971 if (ep
->X_op
!= O_big
)
5973 gas_assert (ep
->X_op
== O_constant
);
5975 /* Sign-extending 32-bit constants makes their handling easier. */
5977 normalize_constant_expr (ep
);
5979 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5981 /* We can handle 16 bit signed values with an addiu to
5982 $zero. No need to ever use daddiu here, since $zero and
5983 the result are always correct in 32 bit mode. */
5984 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5987 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5989 /* We can handle 16 bit unsigned values with an ori to
5991 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5994 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5996 /* 32 bit values require an lui. */
5997 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5998 if ((ep
->X_add_number
& 0xffff) != 0)
5999 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6004 /* The value is larger than 32 bits. */
6006 if (!dbl
|| HAVE_32BIT_GPRS
)
6010 sprintf_vma (value
, ep
->X_add_number
);
6011 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6012 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6016 if (ep
->X_op
!= O_big
)
6019 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6020 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6021 hi32
.X_add_number
&= 0xffffffff;
6023 lo32
.X_add_number
&= 0xffffffff;
6027 gas_assert (ep
->X_add_number
> 2);
6028 if (ep
->X_add_number
== 3)
6029 generic_bignum
[3] = 0;
6030 else if (ep
->X_add_number
> 4)
6031 as_bad (_("Number larger than 64 bits"));
6032 lo32
.X_op
= O_constant
;
6033 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
6034 hi32
.X_op
= O_constant
;
6035 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
6038 if (hi32
.X_add_number
== 0)
6043 unsigned long hi
, lo
;
6045 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
6047 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
6049 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6052 if (lo32
.X_add_number
& 0x80000000)
6054 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6055 if (lo32
.X_add_number
& 0xffff)
6056 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6061 /* Check for 16bit shifted constant. We know that hi32 is
6062 non-zero, so start the mask on the first bit of the hi32
6067 unsigned long himask
, lomask
;
6071 himask
= 0xffff >> (32 - shift
);
6072 lomask
= (0xffff << shift
) & 0xffffffff;
6076 himask
= 0xffff << (shift
- 32);
6079 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
6080 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
6084 tmp
.X_op
= O_constant
;
6086 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
6087 | (lo32
.X_add_number
>> shift
));
6089 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
6090 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6091 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6092 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6097 while (shift
<= (64 - 16));
6099 /* Find the bit number of the lowest one bit, and store the
6100 shifted value in hi/lo. */
6101 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
6102 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
6106 while ((lo
& 1) == 0)
6111 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
6117 while ((hi
& 1) == 0)
6126 /* Optimize if the shifted value is a (power of 2) - 1. */
6127 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
6128 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
6130 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
6135 /* This instruction will set the register to be all
6137 tmp
.X_op
= O_constant
;
6138 tmp
.X_add_number
= (offsetT
) -1;
6139 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6143 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6144 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
6146 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
6147 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6152 /* Sign extend hi32 before calling load_register, because we can
6153 generally get better code when we load a sign extended value. */
6154 if ((hi32
.X_add_number
& 0x80000000) != 0)
6155 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
6156 load_register (reg
, &hi32
, 0);
6159 if ((lo32
.X_add_number
& 0xffff0000) == 0)
6163 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
6171 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
6173 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6174 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
6180 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
6184 mid16
.X_add_number
>>= 16;
6185 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6186 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6189 if ((lo32
.X_add_number
& 0xffff) != 0)
6190 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6194 load_delay_nop (void)
6196 if (!gpr_interlocks
)
6197 macro_build (NULL
, "nop", "");
6200 /* Load an address into a register. */
6203 load_address (int reg
, expressionS
*ep
, int *used_at
)
6205 if (ep
->X_op
!= O_constant
6206 && ep
->X_op
!= O_symbol
)
6208 as_bad (_("expression too complex"));
6209 ep
->X_op
= O_constant
;
6212 if (ep
->X_op
== O_constant
)
6214 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
6218 if (mips_pic
== NO_PIC
)
6220 /* If this is a reference to a GP relative symbol, we want
6221 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6223 lui $reg,<sym> (BFD_RELOC_HI16_S)
6224 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6225 If we have an addend, we always use the latter form.
6227 With 64bit address space and a usable $at we want
6228 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6229 lui $at,<sym> (BFD_RELOC_HI16_S)
6230 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6231 daddiu $at,<sym> (BFD_RELOC_LO16)
6235 If $at is already in use, we use a path which is suboptimal
6236 on superscalar processors.
6237 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6238 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6240 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6242 daddiu $reg,<sym> (BFD_RELOC_LO16)
6244 For GP relative symbols in 64bit address space we can use
6245 the same sequence as in 32bit address space. */
6246 if (HAVE_64BIT_SYMBOLS
)
6248 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6249 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6251 relax_start (ep
->X_add_symbol
);
6252 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6253 mips_gp_register
, BFD_RELOC_GPREL16
);
6257 if (*used_at
== 0 && mips_opts
.at
)
6259 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6260 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
6261 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6262 BFD_RELOC_MIPS_HIGHER
);
6263 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
6264 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
6265 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
6270 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6271 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6272 BFD_RELOC_MIPS_HIGHER
);
6273 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6274 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
6275 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6276 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
6279 if (mips_relax
.sequence
)
6284 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6285 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6287 relax_start (ep
->X_add_symbol
);
6288 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6289 mips_gp_register
, BFD_RELOC_GPREL16
);
6292 macro_build_lui (ep
, reg
);
6293 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
6294 reg
, reg
, BFD_RELOC_LO16
);
6295 if (mips_relax
.sequence
)
6299 else if (!mips_big_got
)
6303 /* If this is a reference to an external symbol, we want
6304 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6306 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6308 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6309 If there is a constant, it must be added in after.
6311 If we have NewABI, we want
6312 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6313 unless we're referencing a global symbol with a non-zero
6314 offset, in which case cst must be added separately. */
6317 if (ep
->X_add_number
)
6319 ex
.X_add_number
= ep
->X_add_number
;
6320 ep
->X_add_number
= 0;
6321 relax_start (ep
->X_add_symbol
);
6322 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6323 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6324 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6325 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6326 ex
.X_op
= O_constant
;
6327 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6328 reg
, reg
, BFD_RELOC_LO16
);
6329 ep
->X_add_number
= ex
.X_add_number
;
6332 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6333 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6334 if (mips_relax
.sequence
)
6339 ex
.X_add_number
= ep
->X_add_number
;
6340 ep
->X_add_number
= 0;
6341 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6342 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6344 relax_start (ep
->X_add_symbol
);
6346 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6350 if (ex
.X_add_number
!= 0)
6352 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6353 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6354 ex
.X_op
= O_constant
;
6355 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6356 reg
, reg
, BFD_RELOC_LO16
);
6360 else if (mips_big_got
)
6364 /* This is the large GOT case. If this is a reference to an
6365 external symbol, we want
6366 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6368 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6370 Otherwise, for a reference to a local symbol in old ABI, we want
6371 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6373 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6374 If there is a constant, it must be added in after.
6376 In the NewABI, for local symbols, with or without offsets, we want:
6377 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6378 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6382 ex
.X_add_number
= ep
->X_add_number
;
6383 ep
->X_add_number
= 0;
6384 relax_start (ep
->X_add_symbol
);
6385 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6386 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6387 reg
, reg
, mips_gp_register
);
6388 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6389 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6390 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6391 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6392 else if (ex
.X_add_number
)
6394 ex
.X_op
= O_constant
;
6395 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6399 ep
->X_add_number
= ex
.X_add_number
;
6401 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6402 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6403 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6404 BFD_RELOC_MIPS_GOT_OFST
);
6409 ex
.X_add_number
= ep
->X_add_number
;
6410 ep
->X_add_number
= 0;
6411 relax_start (ep
->X_add_symbol
);
6412 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6414 reg
, reg
, mips_gp_register
);
6415 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6416 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6418 if (reg_needs_delay (mips_gp_register
))
6420 /* We need a nop before loading from $gp. This special
6421 check is required because the lui which starts the main
6422 instruction stream does not refer to $gp, and so will not
6423 insert the nop which may be required. */
6424 macro_build (NULL
, "nop", "");
6426 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6427 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6429 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6433 if (ex
.X_add_number
!= 0)
6435 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6436 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6437 ex
.X_op
= O_constant
;
6438 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6446 if (!mips_opts
.at
&& *used_at
== 1)
6447 as_bad (_("Macro used $at after \".set noat\""));
6450 /* Move the contents of register SOURCE into register DEST. */
6453 move_register (int dest
, int source
)
6455 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6456 instruction specifically requires a 32-bit one. */
6457 if (mips_opts
.micromips
6458 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6459 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6461 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6465 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6466 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6467 The two alternatives are:
6469 Global symbol Local sybmol
6470 ------------- ------------
6471 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6473 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6475 load_got_offset emits the first instruction and add_got_offset
6476 emits the second for a 16-bit offset or add_got_offset_hilo emits
6477 a sequence to add a 32-bit offset using a scratch register. */
6480 load_got_offset (int dest
, expressionS
*local
)
6485 global
.X_add_number
= 0;
6487 relax_start (local
->X_add_symbol
);
6488 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6489 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6491 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6492 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6497 add_got_offset (int dest
, expressionS
*local
)
6501 global
.X_op
= O_constant
;
6502 global
.X_op_symbol
= NULL
;
6503 global
.X_add_symbol
= NULL
;
6504 global
.X_add_number
= local
->X_add_number
;
6506 relax_start (local
->X_add_symbol
);
6507 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6508 dest
, dest
, BFD_RELOC_LO16
);
6510 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6515 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6518 int hold_mips_optimize
;
6520 global
.X_op
= O_constant
;
6521 global
.X_op_symbol
= NULL
;
6522 global
.X_add_symbol
= NULL
;
6523 global
.X_add_number
= local
->X_add_number
;
6525 relax_start (local
->X_add_symbol
);
6526 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6528 /* Set mips_optimize around the lui instruction to avoid
6529 inserting an unnecessary nop after the lw. */
6530 hold_mips_optimize
= mips_optimize
;
6532 macro_build_lui (&global
, tmp
);
6533 mips_optimize
= hold_mips_optimize
;
6534 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6537 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6540 /* Emit a sequence of instructions to emulate a branch likely operation.
6541 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6542 is its complementing branch with the original condition negated.
6543 CALL is set if the original branch specified the link operation.
6544 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6546 Code like this is produced in the noreorder mode:
6551 delay slot (executed only if branch taken)
6559 delay slot (executed only if branch taken)
6562 In the reorder mode the delay slot would be filled with a nop anyway,
6563 so code produced is simply:
6568 This function is used when producing code for the microMIPS ASE that
6569 does not implement branch likely instructions in hardware. */
6572 macro_build_branch_likely (const char *br
, const char *brneg
,
6573 int call
, expressionS
*ep
, const char *fmt
,
6574 unsigned int sreg
, unsigned int treg
)
6576 int noreorder
= mips_opts
.noreorder
;
6579 gas_assert (mips_opts
.micromips
);
6583 micromips_label_expr (&expr1
);
6584 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6585 macro_build (NULL
, "nop", "");
6586 macro_build (ep
, call
? "bal" : "b", "p");
6588 /* Set to true so that append_insn adds a label. */
6589 emit_branch_likely_macro
= TRUE
;
6593 macro_build (ep
, br
, fmt
, sreg
, treg
);
6594 macro_build (NULL
, "nop", "");
6599 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6600 the condition code tested. EP specifies the branch target. */
6603 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6630 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6633 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6634 the register tested. EP specifies the branch target. */
6637 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6639 const char *brneg
= NULL
;
6649 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6653 gas_assert (mips_opts
.micromips
);
6662 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6669 br
= mips_opts
.micromips
? "blez" : "blezl";
6676 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6680 gas_assert (mips_opts
.micromips
);
6688 if (mips_opts
.micromips
&& brneg
)
6689 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6691 macro_build (ep
, br
, "s,p", sreg
);
6694 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6695 TREG as the registers tested. EP specifies the branch target. */
6698 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6699 unsigned int sreg
, unsigned int treg
)
6701 const char *brneg
= NULL
;
6713 br
= mips_opts
.micromips
? "beq" : "beql";
6722 br
= mips_opts
.micromips
? "bne" : "bnel";
6728 if (mips_opts
.micromips
&& brneg
)
6729 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6731 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6736 * This routine implements the seemingly endless macro or synthesized
6737 * instructions and addressing modes in the mips assembly language. Many
6738 * of these macros are simple and are similar to each other. These could
6739 * probably be handled by some kind of table or grammar approach instead of
6740 * this verbose method. Others are not simple macros but are more like
6741 * optimizing code generation.
6742 * One interesting optimization is when several store macros appear
6743 * consecutively that would load AT with the upper half of the same address.
6744 * The ensuing load upper instructions are ommited. This implies some kind
6745 * of global optimization. We currently only optimize within a single macro.
6746 * For many of the load and store macros if the address is specified as a
6747 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6748 * first load register 'at' with zero and use it as the base register. The
6749 * mips assembler simply uses register $zero. Just one tiny optimization
6753 macro (struct mips_cl_insn
*ip
)
6755 unsigned int treg
, sreg
, dreg
, breg
;
6756 unsigned int tempreg
;
6759 expressionS label_expr
;
6777 bfd_reloc_code_real_type r
;
6778 int hold_mips_optimize
;
6780 gas_assert (! mips_opts
.mips16
);
6782 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6783 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6784 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6785 mask
= ip
->insn_mo
->mask
;
6787 label_expr
.X_op
= O_constant
;
6788 label_expr
.X_op_symbol
= NULL
;
6789 label_expr
.X_add_symbol
= NULL
;
6790 label_expr
.X_add_number
= 0;
6792 expr1
.X_op
= O_constant
;
6793 expr1
.X_op_symbol
= NULL
;
6794 expr1
.X_add_symbol
= NULL
;
6795 expr1
.X_add_number
= 1;
6810 if (mips_opts
.micromips
)
6811 micromips_label_expr (&label_expr
);
6813 label_expr
.X_add_number
= 8;
6814 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6816 macro_build (NULL
, "nop", "");
6818 move_register (dreg
, sreg
);
6819 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6820 if (mips_opts
.micromips
)
6821 micromips_add_label ();
6838 if (!mips_opts
.micromips
)
6840 if (imm_expr
.X_op
== O_constant
6841 && imm_expr
.X_add_number
>= -0x200
6842 && imm_expr
.X_add_number
< 0x200)
6844 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6853 if (imm_expr
.X_op
== O_constant
6854 && imm_expr
.X_add_number
>= -0x8000
6855 && imm_expr
.X_add_number
< 0x8000)
6857 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6862 load_register (AT
, &imm_expr
, dbl
);
6863 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6882 if (imm_expr
.X_op
== O_constant
6883 && imm_expr
.X_add_number
>= 0
6884 && imm_expr
.X_add_number
< 0x10000)
6886 if (mask
!= M_NOR_I
)
6887 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6890 macro_build (&imm_expr
, "ori", "t,r,i",
6891 treg
, sreg
, BFD_RELOC_LO16
);
6892 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6898 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6899 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6903 switch (imm_expr
.X_add_number
)
6906 macro_build (NULL
, "nop", "");
6909 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6913 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6914 (int) imm_expr
.X_add_number
);
6917 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6918 (unsigned long) imm_expr
.X_add_number
);
6927 gas_assert (mips_opts
.micromips
);
6928 macro_build_branch_ccl (mask
, &offset_expr
,
6929 EXTRACT_OPERAND (1, BCC
, *ip
));
6936 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6942 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6947 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6954 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6956 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6960 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6961 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6962 &offset_expr
, AT
, ZERO
);
6972 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6978 /* Check for > max integer. */
6979 maxnum
= 0x7fffffff;
6980 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
6987 if (imm_expr
.X_op
== O_constant
6988 && imm_expr
.X_add_number
>= maxnum
6989 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
6992 /* Result is always false. */
6994 macro_build (NULL
, "nop", "");
6996 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6999 if (imm_expr
.X_op
!= O_constant
)
7000 as_bad (_("Unsupported large constant"));
7001 ++imm_expr
.X_add_number
;
7005 if (mask
== M_BGEL_I
)
7007 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7009 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
7010 &offset_expr
, sreg
);
7013 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7015 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
7016 &offset_expr
, sreg
);
7019 maxnum
= 0x7fffffff;
7020 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
7027 maxnum
= - maxnum
- 1;
7028 if (imm_expr
.X_op
== O_constant
7029 && imm_expr
.X_add_number
<= maxnum
7030 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
7033 /* result is always true */
7034 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
7035 macro_build (&offset_expr
, "b", "p");
7040 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7041 &offset_expr
, AT
, ZERO
);
7050 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7051 &offset_expr
, ZERO
, treg
);
7055 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7056 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7057 &offset_expr
, AT
, ZERO
);
7066 && imm_expr
.X_op
== O_constant
7067 && imm_expr
.X_add_number
== -1))
7069 if (imm_expr
.X_op
!= O_constant
)
7070 as_bad (_("Unsupported large constant"));
7071 ++imm_expr
.X_add_number
;
7075 if (mask
== M_BGEUL_I
)
7077 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7079 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7080 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7081 &offset_expr
, sreg
, ZERO
);
7086 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7087 &offset_expr
, AT
, ZERO
);
7095 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
7097 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
7101 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7102 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7103 &offset_expr
, AT
, ZERO
);
7111 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7112 &offset_expr
, sreg
, ZERO
);
7118 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7119 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7120 &offset_expr
, AT
, ZERO
);
7128 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7130 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
7134 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7135 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7136 &offset_expr
, AT
, ZERO
);
7143 maxnum
= 0x7fffffff;
7144 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
7151 if (imm_expr
.X_op
== O_constant
7152 && imm_expr
.X_add_number
>= maxnum
7153 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
7155 if (imm_expr
.X_op
!= O_constant
)
7156 as_bad (_("Unsupported large constant"));
7157 ++imm_expr
.X_add_number
;
7161 if (mask
== M_BLTL_I
)
7163 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7164 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7165 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7166 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7171 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7172 &offset_expr
, AT
, ZERO
);
7180 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7181 &offset_expr
, sreg
, ZERO
);
7187 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7188 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7189 &offset_expr
, AT
, ZERO
);
7198 && imm_expr
.X_op
== O_constant
7199 && imm_expr
.X_add_number
== -1))
7201 if (imm_expr
.X_op
!= O_constant
)
7202 as_bad (_("Unsupported large constant"));
7203 ++imm_expr
.X_add_number
;
7207 if (mask
== M_BLTUL_I
)
7209 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7211 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7212 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7213 &offset_expr
, sreg
, ZERO
);
7218 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7219 &offset_expr
, AT
, ZERO
);
7227 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7229 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
7233 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7234 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7235 &offset_expr
, AT
, ZERO
);
7245 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7246 &offset_expr
, ZERO
, treg
);
7250 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7251 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7252 &offset_expr
, AT
, ZERO
);
7258 /* Use unsigned arithmetic. */
7262 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7264 as_bad (_("Unsupported large constant"));
7269 pos
= imm_expr
.X_add_number
;
7270 size
= imm2_expr
.X_add_number
;
7275 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7278 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7280 as_bad (_("Improper extract size (%lu, position %lu)"),
7281 (unsigned long) size
, (unsigned long) pos
);
7285 if (size
<= 32 && pos
< 32)
7290 else if (size
<= 32)
7300 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7307 /* Use unsigned arithmetic. */
7311 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7313 as_bad (_("Unsupported large constant"));
7318 pos
= imm_expr
.X_add_number
;
7319 size
= imm2_expr
.X_add_number
;
7324 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7327 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7329 as_bad (_("Improper insert size (%lu, position %lu)"),
7330 (unsigned long) size
, (unsigned long) pos
);
7334 if (pos
< 32 && (pos
+ size
- 1) < 32)
7349 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7350 (int) (pos
+ size
- 1));
7366 as_warn (_("Divide by zero."));
7368 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7370 macro_build (NULL
, "break", BRK_FMT
, 7);
7377 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7378 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7382 if (mips_opts
.micromips
)
7383 micromips_label_expr (&label_expr
);
7385 label_expr
.X_add_number
= 8;
7386 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7387 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7388 macro_build (NULL
, "break", BRK_FMT
, 7);
7389 if (mips_opts
.micromips
)
7390 micromips_add_label ();
7392 expr1
.X_add_number
= -1;
7394 load_register (AT
, &expr1
, dbl
);
7395 if (mips_opts
.micromips
)
7396 micromips_label_expr (&label_expr
);
7398 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7399 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7402 expr1
.X_add_number
= 1;
7403 load_register (AT
, &expr1
, dbl
);
7404 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7408 expr1
.X_add_number
= 0x80000000;
7409 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7413 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7414 /* We want to close the noreorder block as soon as possible, so
7415 that later insns are available for delay slot filling. */
7420 if (mips_opts
.micromips
)
7421 micromips_label_expr (&label_expr
);
7423 label_expr
.X_add_number
= 8;
7424 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7425 macro_build (NULL
, "nop", "");
7427 /* We want to close the noreorder block as soon as possible, so
7428 that later insns are available for delay slot filling. */
7431 macro_build (NULL
, "break", BRK_FMT
, 6);
7433 if (mips_opts
.micromips
)
7434 micromips_add_label ();
7435 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7474 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7476 as_warn (_("Divide by zero."));
7478 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7480 macro_build (NULL
, "break", BRK_FMT
, 7);
7483 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7485 if (strcmp (s2
, "mflo") == 0)
7486 move_register (dreg
, sreg
);
7488 move_register (dreg
, ZERO
);
7491 if (imm_expr
.X_op
== O_constant
7492 && imm_expr
.X_add_number
== -1
7493 && s
[strlen (s
) - 1] != 'u')
7495 if (strcmp (s2
, "mflo") == 0)
7497 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7500 move_register (dreg
, ZERO
);
7505 load_register (AT
, &imm_expr
, dbl
);
7506 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7507 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7529 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7530 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7531 /* We want to close the noreorder block as soon as possible, so
7532 that later insns are available for delay slot filling. */
7537 if (mips_opts
.micromips
)
7538 micromips_label_expr (&label_expr
);
7540 label_expr
.X_add_number
= 8;
7541 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7542 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7544 /* We want to close the noreorder block as soon as possible, so
7545 that later insns are available for delay slot filling. */
7547 macro_build (NULL
, "break", BRK_FMT
, 7);
7548 if (mips_opts
.micromips
)
7549 micromips_add_label ();
7551 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7563 /* Load the address of a symbol into a register. If breg is not
7564 zero, we then add a base register to it. */
7566 if (dbl
&& HAVE_32BIT_GPRS
)
7567 as_warn (_("dla used to load 32-bit register"));
7569 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7570 as_warn (_("la used to load 64-bit address"));
7572 if (offset_expr
.X_op
== O_constant
7573 && offset_expr
.X_add_number
>= -0x8000
7574 && offset_expr
.X_add_number
< 0x8000)
7576 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7577 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7581 if (mips_opts
.at
&& (treg
== breg
))
7591 if (offset_expr
.X_op
!= O_symbol
7592 && offset_expr
.X_op
!= O_constant
)
7594 as_bad (_("Expression too complex"));
7595 offset_expr
.X_op
= O_constant
;
7598 if (offset_expr
.X_op
== O_constant
)
7599 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7600 else if (mips_pic
== NO_PIC
)
7602 /* If this is a reference to a GP relative symbol, we want
7603 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7605 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7606 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7607 If we have a constant, we need two instructions anyhow,
7608 so we may as well always use the latter form.
7610 With 64bit address space and a usable $at we want
7611 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7612 lui $at,<sym> (BFD_RELOC_HI16_S)
7613 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7614 daddiu $at,<sym> (BFD_RELOC_LO16)
7616 daddu $tempreg,$tempreg,$at
7618 If $at is already in use, we use a path which is suboptimal
7619 on superscalar processors.
7620 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7621 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7623 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7625 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7627 For GP relative symbols in 64bit address space we can use
7628 the same sequence as in 32bit address space. */
7629 if (HAVE_64BIT_SYMBOLS
)
7631 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7632 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7634 relax_start (offset_expr
.X_add_symbol
);
7635 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7636 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7640 if (used_at
== 0 && mips_opts
.at
)
7642 macro_build (&offset_expr
, "lui", LUI_FMT
,
7643 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7644 macro_build (&offset_expr
, "lui", LUI_FMT
,
7645 AT
, BFD_RELOC_HI16_S
);
7646 macro_build (&offset_expr
, "daddiu", "t,r,j",
7647 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7648 macro_build (&offset_expr
, "daddiu", "t,r,j",
7649 AT
, AT
, BFD_RELOC_LO16
);
7650 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7651 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7656 macro_build (&offset_expr
, "lui", LUI_FMT
,
7657 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7658 macro_build (&offset_expr
, "daddiu", "t,r,j",
7659 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7660 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7661 macro_build (&offset_expr
, "daddiu", "t,r,j",
7662 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7663 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7664 macro_build (&offset_expr
, "daddiu", "t,r,j",
7665 tempreg
, tempreg
, BFD_RELOC_LO16
);
7668 if (mips_relax
.sequence
)
7673 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7674 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7676 relax_start (offset_expr
.X_add_symbol
);
7677 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7678 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7681 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7682 as_bad (_("Offset too large"));
7683 macro_build_lui (&offset_expr
, tempreg
);
7684 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7685 tempreg
, tempreg
, BFD_RELOC_LO16
);
7686 if (mips_relax
.sequence
)
7690 else if (!mips_big_got
&& !HAVE_NEWABI
)
7692 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7694 /* If this is a reference to an external symbol, and there
7695 is no constant, we want
7696 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7697 or for lca or if tempreg is PIC_CALL_REG
7698 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7699 For a local symbol, we want
7700 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7702 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7704 If we have a small constant, and this is a reference to
7705 an external symbol, we want
7706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7708 addiu $tempreg,$tempreg,<constant>
7709 For a local symbol, we want the same instruction
7710 sequence, but we output a BFD_RELOC_LO16 reloc on the
7713 If we have a large constant, and this is a reference to
7714 an external symbol, we want
7715 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7716 lui $at,<hiconstant>
7717 addiu $at,$at,<loconstant>
7718 addu $tempreg,$tempreg,$at
7719 For a local symbol, we want the same instruction
7720 sequence, but we output a BFD_RELOC_LO16 reloc on the
7724 if (offset_expr
.X_add_number
== 0)
7726 if (mips_pic
== SVR4_PIC
7728 && (call
|| tempreg
== PIC_CALL_REG
))
7729 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7731 relax_start (offset_expr
.X_add_symbol
);
7732 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7733 lw_reloc_type
, mips_gp_register
);
7736 /* We're going to put in an addu instruction using
7737 tempreg, so we may as well insert the nop right
7742 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7743 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7745 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7746 tempreg
, tempreg
, BFD_RELOC_LO16
);
7748 /* FIXME: If breg == 0, and the next instruction uses
7749 $tempreg, then if this variant case is used an extra
7750 nop will be generated. */
7752 else if (offset_expr
.X_add_number
>= -0x8000
7753 && offset_expr
.X_add_number
< 0x8000)
7755 load_got_offset (tempreg
, &offset_expr
);
7757 add_got_offset (tempreg
, &offset_expr
);
7761 expr1
.X_add_number
= offset_expr
.X_add_number
;
7762 offset_expr
.X_add_number
=
7763 SEXT_16BIT (offset_expr
.X_add_number
);
7764 load_got_offset (tempreg
, &offset_expr
);
7765 offset_expr
.X_add_number
= expr1
.X_add_number
;
7766 /* If we are going to add in a base register, and the
7767 target register and the base register are the same,
7768 then we are using AT as a temporary register. Since
7769 we want to load the constant into AT, we add our
7770 current AT (from the global offset table) and the
7771 register into the register now, and pretend we were
7772 not using a base register. */
7776 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7781 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7785 else if (!mips_big_got
&& HAVE_NEWABI
)
7787 int add_breg_early
= 0;
7789 /* If this is a reference to an external, and there is no
7790 constant, or local symbol (*), with or without a
7792 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7793 or for lca or if tempreg is PIC_CALL_REG
7794 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7796 If we have a small constant, and this is a reference to
7797 an external symbol, we want
7798 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7799 addiu $tempreg,$tempreg,<constant>
7801 If we have a large constant, and this is a reference to
7802 an external symbol, we want
7803 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7804 lui $at,<hiconstant>
7805 addiu $at,$at,<loconstant>
7806 addu $tempreg,$tempreg,$at
7808 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7809 local symbols, even though it introduces an additional
7812 if (offset_expr
.X_add_number
)
7814 expr1
.X_add_number
= offset_expr
.X_add_number
;
7815 offset_expr
.X_add_number
= 0;
7817 relax_start (offset_expr
.X_add_symbol
);
7818 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7819 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7821 if (expr1
.X_add_number
>= -0x8000
7822 && expr1
.X_add_number
< 0x8000)
7824 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7825 tempreg
, tempreg
, BFD_RELOC_LO16
);
7827 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7829 /* If we are going to add in a base register, and the
7830 target register and the base register are the same,
7831 then we are using AT as a temporary register. Since
7832 we want to load the constant into AT, we add our
7833 current AT (from the global offset table) and the
7834 register into the register now, and pretend we were
7835 not using a base register. */
7840 gas_assert (tempreg
== AT
);
7841 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7847 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7848 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7854 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7857 offset_expr
.X_add_number
= expr1
.X_add_number
;
7859 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7860 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7864 treg
, tempreg
, breg
);
7870 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7872 relax_start (offset_expr
.X_add_symbol
);
7873 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7874 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7876 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7877 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7882 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7883 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7886 else if (mips_big_got
&& !HAVE_NEWABI
)
7889 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7890 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7891 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7893 /* This is the large GOT case. If this is a reference to an
7894 external symbol, and there is no constant, we want
7895 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7896 addu $tempreg,$tempreg,$gp
7897 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7898 or for lca or if tempreg is PIC_CALL_REG
7899 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7900 addu $tempreg,$tempreg,$gp
7901 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7902 For a local symbol, we want
7903 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7905 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7907 If we have a small constant, and this is a reference to
7908 an external symbol, we want
7909 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7910 addu $tempreg,$tempreg,$gp
7911 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7913 addiu $tempreg,$tempreg,<constant>
7914 For a local symbol, we want
7915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7917 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7919 If we have a large constant, and this is a reference to
7920 an external symbol, we want
7921 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7922 addu $tempreg,$tempreg,$gp
7923 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7924 lui $at,<hiconstant>
7925 addiu $at,$at,<loconstant>
7926 addu $tempreg,$tempreg,$at
7927 For a local symbol, we want
7928 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7929 lui $at,<hiconstant>
7930 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7931 addu $tempreg,$tempreg,$at
7934 expr1
.X_add_number
= offset_expr
.X_add_number
;
7935 offset_expr
.X_add_number
= 0;
7936 relax_start (offset_expr
.X_add_symbol
);
7937 gpdelay
= reg_needs_delay (mips_gp_register
);
7938 if (expr1
.X_add_number
== 0 && breg
== 0
7939 && (call
|| tempreg
== PIC_CALL_REG
))
7941 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7942 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7944 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7945 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7946 tempreg
, tempreg
, mips_gp_register
);
7947 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7948 tempreg
, lw_reloc_type
, tempreg
);
7949 if (expr1
.X_add_number
== 0)
7953 /* We're going to put in an addu instruction using
7954 tempreg, so we may as well insert the nop right
7959 else if (expr1
.X_add_number
>= -0x8000
7960 && expr1
.X_add_number
< 0x8000)
7963 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7964 tempreg
, tempreg
, BFD_RELOC_LO16
);
7968 /* If we are going to add in a base register, and the
7969 target register and the base register are the same,
7970 then we are using AT as a temporary register. Since
7971 we want to load the constant into AT, we add our
7972 current AT (from the global offset table) and the
7973 register into the register now, and pretend we were
7974 not using a base register. */
7979 gas_assert (tempreg
== AT
);
7981 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7986 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7987 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7991 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7996 /* This is needed because this instruction uses $gp, but
7997 the first instruction on the main stream does not. */
7998 macro_build (NULL
, "nop", "");
8001 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8002 local_reloc_type
, mips_gp_register
);
8003 if (expr1
.X_add_number
>= -0x8000
8004 && expr1
.X_add_number
< 0x8000)
8007 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8008 tempreg
, tempreg
, BFD_RELOC_LO16
);
8009 /* FIXME: If add_number is 0, and there was no base
8010 register, the external symbol case ended with a load,
8011 so if the symbol turns out to not be external, and
8012 the next instruction uses tempreg, an unnecessary nop
8013 will be inserted. */
8019 /* We must add in the base register now, as in the
8020 external symbol case. */
8021 gas_assert (tempreg
== AT
);
8023 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8026 /* We set breg to 0 because we have arranged to add
8027 it in in both cases. */
8031 macro_build_lui (&expr1
, AT
);
8032 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8033 AT
, AT
, BFD_RELOC_LO16
);
8034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8035 tempreg
, tempreg
, AT
);
8040 else if (mips_big_got
&& HAVE_NEWABI
)
8042 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8043 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8044 int add_breg_early
= 0;
8046 /* This is the large GOT case. If this is a reference to an
8047 external symbol, and there is no constant, we want
8048 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8049 add $tempreg,$tempreg,$gp
8050 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8051 or for lca or if tempreg is PIC_CALL_REG
8052 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8053 add $tempreg,$tempreg,$gp
8054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8056 If we have a small constant, and this is a reference to
8057 an external symbol, we want
8058 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8059 add $tempreg,$tempreg,$gp
8060 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8061 addi $tempreg,$tempreg,<constant>
8063 If we have a large constant, and this is a reference to
8064 an external symbol, we want
8065 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8066 addu $tempreg,$tempreg,$gp
8067 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8068 lui $at,<hiconstant>
8069 addi $at,$at,<loconstant>
8070 add $tempreg,$tempreg,$at
8072 If we have NewABI, and we know it's a local symbol, we want
8073 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8074 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8075 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8077 relax_start (offset_expr
.X_add_symbol
);
8079 expr1
.X_add_number
= offset_expr
.X_add_number
;
8080 offset_expr
.X_add_number
= 0;
8082 if (expr1
.X_add_number
== 0 && breg
== 0
8083 && (call
|| tempreg
== PIC_CALL_REG
))
8085 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8086 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8088 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8089 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8090 tempreg
, tempreg
, mips_gp_register
);
8091 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8092 tempreg
, lw_reloc_type
, tempreg
);
8094 if (expr1
.X_add_number
== 0)
8096 else if (expr1
.X_add_number
>= -0x8000
8097 && expr1
.X_add_number
< 0x8000)
8099 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8100 tempreg
, tempreg
, BFD_RELOC_LO16
);
8102 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8104 /* If we are going to add in a base register, and the
8105 target register and the base register are the same,
8106 then we are using AT as a temporary register. Since
8107 we want to load the constant into AT, we add our
8108 current AT (from the global offset table) and the
8109 register into the register now, and pretend we were
8110 not using a base register. */
8115 gas_assert (tempreg
== AT
);
8116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8122 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8123 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8128 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8131 offset_expr
.X_add_number
= expr1
.X_add_number
;
8132 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8133 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8134 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8135 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
8138 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8139 treg
, tempreg
, breg
);
8149 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
8153 gas_assert (!mips_opts
.micromips
);
8155 unsigned long temp
= (treg
<< 16) | (0x01);
8156 macro_build (NULL
, "c2", "C", temp
);
8161 gas_assert (!mips_opts
.micromips
);
8163 unsigned long temp
= (0x02);
8164 macro_build (NULL
, "c2", "C", temp
);
8169 gas_assert (!mips_opts
.micromips
);
8171 unsigned long temp
= (treg
<< 16) | (0x02);
8172 macro_build (NULL
, "c2", "C", temp
);
8177 gas_assert (!mips_opts
.micromips
);
8178 macro_build (NULL
, "c2", "C", 3);
8182 gas_assert (!mips_opts
.micromips
);
8184 unsigned long temp
= (treg
<< 16) | 0x03;
8185 macro_build (NULL
, "c2", "C", temp
);
8190 /* The j instruction may not be used in PIC code, since it
8191 requires an absolute address. We convert it to a b
8193 if (mips_pic
== NO_PIC
)
8194 macro_build (&offset_expr
, "j", "a");
8196 macro_build (&offset_expr
, "b", "p");
8199 /* The jal instructions must be handled as macros because when
8200 generating PIC code they expand to multi-instruction
8201 sequences. Normally they are simple instructions. */
8206 gas_assert (mips_opts
.micromips
);
8214 if (mips_pic
== NO_PIC
)
8216 s
= jals
? "jalrs" : "jalr";
8217 if (mips_opts
.micromips
8219 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8220 macro_build (NULL
, s
, "mj", sreg
);
8222 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8226 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
8227 && mips_cprestore_offset
>= 0);
8229 if (sreg
!= PIC_CALL_REG
)
8230 as_warn (_("MIPS PIC call to register other than $25"));
8232 s
= (mips_opts
.micromips
&& (!mips_opts
.noreorder
|| cprestore
)
8233 ? "jalrs" : "jalr");
8234 if (mips_opts
.micromips
8236 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8237 macro_build (NULL
, s
, "mj", sreg
);
8239 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8240 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
8242 if (mips_cprestore_offset
< 0)
8243 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8246 if (!mips_frame_reg_valid
)
8248 as_warn (_("No .frame pseudo-op used in PIC code"));
8249 /* Quiet this warning. */
8250 mips_frame_reg_valid
= 1;
8252 if (!mips_cprestore_valid
)
8254 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8255 /* Quiet this warning. */
8256 mips_cprestore_valid
= 1;
8258 if (mips_opts
.noreorder
)
8259 macro_build (NULL
, "nop", "");
8260 expr1
.X_add_number
= mips_cprestore_offset
;
8261 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8264 HAVE_64BIT_ADDRESSES
);
8272 gas_assert (mips_opts
.micromips
);
8276 if (mips_pic
== NO_PIC
)
8277 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
8278 else if (mips_pic
== SVR4_PIC
)
8280 /* If this is a reference to an external symbol, and we are
8281 using a small GOT, we want
8282 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8286 lw $gp,cprestore($sp)
8287 The cprestore value is set using the .cprestore
8288 pseudo-op. If we are using a big GOT, we want
8289 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8291 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8295 lw $gp,cprestore($sp)
8296 If the symbol is not external, we want
8297 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8299 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8302 lw $gp,cprestore($sp)
8304 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8305 sequences above, minus nops, unless the symbol is local,
8306 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8312 relax_start (offset_expr
.X_add_symbol
);
8313 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8314 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8317 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8318 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
8324 relax_start (offset_expr
.X_add_symbol
);
8325 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8326 BFD_RELOC_MIPS_CALL_HI16
);
8327 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8328 PIC_CALL_REG
, mips_gp_register
);
8329 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8330 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8333 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8334 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8336 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8337 PIC_CALL_REG
, PIC_CALL_REG
,
8338 BFD_RELOC_MIPS_GOT_OFST
);
8342 macro_build_jalr (&offset_expr
, 0);
8346 relax_start (offset_expr
.X_add_symbol
);
8349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8350 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8359 gpdelay
= reg_needs_delay (mips_gp_register
);
8360 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8361 BFD_RELOC_MIPS_CALL_HI16
);
8362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8363 PIC_CALL_REG
, mips_gp_register
);
8364 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8365 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8370 macro_build (NULL
, "nop", "");
8372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8373 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8376 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8377 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8379 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8381 if (mips_cprestore_offset
< 0)
8382 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8385 if (!mips_frame_reg_valid
)
8387 as_warn (_("No .frame pseudo-op used in PIC code"));
8388 /* Quiet this warning. */
8389 mips_frame_reg_valid
= 1;
8391 if (!mips_cprestore_valid
)
8393 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8394 /* Quiet this warning. */
8395 mips_cprestore_valid
= 1;
8397 if (mips_opts
.noreorder
)
8398 macro_build (NULL
, "nop", "");
8399 expr1
.X_add_number
= mips_cprestore_offset
;
8400 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8403 HAVE_64BIT_ADDRESSES
);
8407 else if (mips_pic
== VXWORKS_PIC
)
8408 as_bad (_("Non-PIC jump used in PIC library"));
8516 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8524 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8555 gas_assert (!mips_opts
.micromips
);
8558 /* Itbl support may require additional care here. */
8565 /* Itbl support may require additional care here. */
8573 offbits
= (mips_opts
.micromips
? 12 : 16);
8574 /* Itbl support may require additional care here. */
8579 gas_assert (!mips_opts
.micromips
);
8582 /* Itbl support may require additional care here. */
8590 offbits
= (mips_opts
.micromips
? 12 : 16);
8597 offbits
= (mips_opts
.micromips
? 12 : 16);
8603 /* Itbl support may require additional care here. */
8611 offbits
= (mips_opts
.micromips
? 12 : 16);
8612 /* Itbl support may require additional care here. */
8619 /* Itbl support may require additional care here. */
8626 /* Itbl support may require additional care here. */
8634 offbits
= (mips_opts
.micromips
? 12 : 16);
8641 offbits
= (mips_opts
.micromips
? 12 : 16);
8648 offbits
= (mips_opts
.micromips
? 12 : 16);
8655 offbits
= (mips_opts
.micromips
? 12 : 16);
8662 offbits
= (mips_opts
.micromips
? 12 : 16);
8667 gas_assert (mips_opts
.micromips
);
8676 gas_assert (mips_opts
.micromips
);
8685 gas_assert (mips_opts
.micromips
);
8693 gas_assert (mips_opts
.micromips
);
8700 /* We don't want to use $0 as tempreg. */
8701 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
8704 tempreg
= treg
+ lp
;
8724 gas_assert (!mips_opts
.micromips
);
8727 /* Itbl support may require additional care here. */
8734 /* Itbl support may require additional care here. */
8742 offbits
= (mips_opts
.micromips
? 12 : 16);
8743 /* Itbl support may require additional care here. */
8748 gas_assert (!mips_opts
.micromips
);
8751 /* Itbl support may require additional care here. */
8759 offbits
= (mips_opts
.micromips
? 12 : 16);
8766 offbits
= (mips_opts
.micromips
? 12 : 16);
8773 offbits
= (mips_opts
.micromips
? 12 : 16);
8780 offbits
= (mips_opts
.micromips
? 12 : 16);
8786 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8787 offbits
= (mips_opts
.micromips
? 12 : 16);
8800 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8801 offbits
= (mips_opts
.micromips
? 12 : 16);
8815 /* Itbl support may require additional care here. */
8822 offbits
= (mips_opts
.micromips
? 12 : 16);
8823 /* Itbl support may require additional care here. */
8830 /* Itbl support may require additional care here. */
8835 gas_assert (!mips_opts
.micromips
);
8838 /* Itbl support may require additional care here. */
8846 offbits
= (mips_opts
.micromips
? 12 : 16);
8853 offbits
= (mips_opts
.micromips
? 12 : 16);
8858 gas_assert (mips_opts
.micromips
);
8866 gas_assert (mips_opts
.micromips
);
8874 gas_assert (mips_opts
.micromips
);
8882 gas_assert (mips_opts
.micromips
);
8891 if (offset_expr
.X_op
!= O_constant
8892 && offset_expr
.X_op
!= O_symbol
)
8894 as_bad (_("Expression too complex"));
8895 offset_expr
.X_op
= O_constant
;
8898 if (HAVE_32BIT_ADDRESSES
8899 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8903 sprintf_vma (value
, offset_expr
.X_add_number
);
8904 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8907 /* A constant expression in PIC code can be handled just as it
8908 is in non PIC code. */
8909 if (offset_expr
.X_op
== O_constant
)
8913 expr1
.X_add_number
= offset_expr
.X_add_number
;
8914 normalize_address_expr (&expr1
);
8915 if ((offbits
== 0 || offbits
== 16)
8916 && !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8918 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8919 & ~(bfd_vma
) 0xffff);
8922 else if (offbits
== 12 && !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8924 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8925 & ~(bfd_vma
) 0xfff);
8928 else if (offbits
== 9 && !IS_SEXT_9BIT_NUM (expr1
.X_add_number
))
8930 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x100)
8931 & ~(bfd_vma
) 0x1ff);
8936 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8938 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8939 tempreg
, tempreg
, breg
);
8944 if (offset_expr
.X_add_number
== 0)
8947 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8948 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8949 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8951 else if (offbits
== 16)
8952 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8954 macro_build (NULL
, s
, fmt
,
8955 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8957 else if (offbits
!= 16)
8959 /* The offset field is too narrow to be used for a low-part
8960 relocation, so load the whole address into the auxillary
8961 register. In the case of "A(b)" addresses, we first load
8962 absolute address "A" into the register and then add base
8963 register "b". In the case of "o(b)" addresses, we simply
8964 need to add 16-bit offset "o" to base register "b", and
8965 offset_reloc already contains the relocations associated
8969 load_address (tempreg
, &offset_expr
, &used_at
);
8971 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8972 tempreg
, tempreg
, breg
);
8975 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8977 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8978 expr1
.X_add_number
= 0;
8980 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8982 macro_build (NULL
, s
, fmt
,
8983 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8985 else if (mips_pic
== NO_PIC
)
8987 /* If this is a reference to a GP relative symbol, and there
8988 is no base register, we want
8989 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8990 Otherwise, if there is no base register, we want
8991 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8992 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8993 If we have a constant, we need two instructions anyhow,
8994 so we always use the latter form.
8996 If we have a base register, and this is a reference to a
8997 GP relative symbol, we want
8998 addu $tempreg,$breg,$gp
8999 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
9001 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9002 addu $tempreg,$tempreg,$breg
9003 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9004 With a constant we always use the latter case.
9006 With 64bit address space and no base register and $at usable,
9008 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9009 lui $at,<sym> (BFD_RELOC_HI16_S)
9010 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9013 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9014 If we have a base register, we want
9015 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9016 lui $at,<sym> (BFD_RELOC_HI16_S)
9017 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9021 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9023 Without $at we can't generate the optimal path for superscalar
9024 processors here since this would require two temporary registers.
9025 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9026 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9028 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9030 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9031 If we have a base register, we want
9032 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9033 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9035 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9037 daddu $tempreg,$tempreg,$breg
9038 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9040 For GP relative symbols in 64bit address space we can use
9041 the same sequence as in 32bit address space. */
9042 if (HAVE_64BIT_SYMBOLS
)
9044 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9045 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9047 relax_start (offset_expr
.X_add_symbol
);
9050 macro_build (&offset_expr
, s
, fmt
, treg
,
9051 BFD_RELOC_GPREL16
, mips_gp_register
);
9055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9056 tempreg
, breg
, mips_gp_register
);
9057 macro_build (&offset_expr
, s
, fmt
, treg
,
9058 BFD_RELOC_GPREL16
, tempreg
);
9063 if (used_at
== 0 && mips_opts
.at
)
9065 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9066 BFD_RELOC_MIPS_HIGHEST
);
9067 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
9069 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9070 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9072 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
9073 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9074 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9075 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
9081 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9082 BFD_RELOC_MIPS_HIGHEST
);
9083 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9084 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9085 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9086 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9087 tempreg
, BFD_RELOC_HI16_S
);
9088 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9090 macro_build (NULL
, "daddu", "d,v,t",
9091 tempreg
, tempreg
, breg
);
9092 macro_build (&offset_expr
, s
, fmt
, treg
,
9093 BFD_RELOC_LO16
, tempreg
);
9096 if (mips_relax
.sequence
)
9103 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9104 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9106 relax_start (offset_expr
.X_add_symbol
);
9107 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
9111 macro_build_lui (&offset_expr
, tempreg
);
9112 macro_build (&offset_expr
, s
, fmt
, treg
,
9113 BFD_RELOC_LO16
, tempreg
);
9114 if (mips_relax
.sequence
)
9119 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9120 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9122 relax_start (offset_expr
.X_add_symbol
);
9123 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9124 tempreg
, breg
, mips_gp_register
);
9125 macro_build (&offset_expr
, s
, fmt
, treg
,
9126 BFD_RELOC_GPREL16
, tempreg
);
9129 macro_build_lui (&offset_expr
, tempreg
);
9130 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9131 tempreg
, tempreg
, breg
);
9132 macro_build (&offset_expr
, s
, fmt
, treg
,
9133 BFD_RELOC_LO16
, tempreg
);
9134 if (mips_relax
.sequence
)
9138 else if (!mips_big_got
)
9140 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9142 /* If this is a reference to an external symbol, we want
9143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9145 <op> $treg,0($tempreg)
9147 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9149 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9150 <op> $treg,0($tempreg)
9153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9154 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9156 If there is a base register, we add it to $tempreg before
9157 the <op>. If there is a constant, we stick it in the
9158 <op> instruction. We don't handle constants larger than
9159 16 bits, because we have no way to load the upper 16 bits
9160 (actually, we could handle them for the subset of cases
9161 in which we are not using $at). */
9162 gas_assert (offset_expr
.X_op
== O_symbol
);
9165 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9166 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9168 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9169 tempreg
, tempreg
, breg
);
9170 macro_build (&offset_expr
, s
, fmt
, treg
,
9171 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9174 expr1
.X_add_number
= offset_expr
.X_add_number
;
9175 offset_expr
.X_add_number
= 0;
9176 if (expr1
.X_add_number
< -0x8000
9177 || expr1
.X_add_number
>= 0x8000)
9178 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9179 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9180 lw_reloc_type
, mips_gp_register
);
9182 relax_start (offset_expr
.X_add_symbol
);
9184 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9185 tempreg
, BFD_RELOC_LO16
);
9188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9189 tempreg
, tempreg
, breg
);
9190 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9192 else if (mips_big_got
&& !HAVE_NEWABI
)
9196 /* If this is a reference to an external symbol, we want
9197 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9198 addu $tempreg,$tempreg,$gp
9199 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9200 <op> $treg,0($tempreg)
9202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9204 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9205 <op> $treg,0($tempreg)
9206 If there is a base register, we add it to $tempreg before
9207 the <op>. If there is a constant, we stick it in the
9208 <op> instruction. We don't handle constants larger than
9209 16 bits, because we have no way to load the upper 16 bits
9210 (actually, we could handle them for the subset of cases
9211 in which we are not using $at). */
9212 gas_assert (offset_expr
.X_op
== O_symbol
);
9213 expr1
.X_add_number
= offset_expr
.X_add_number
;
9214 offset_expr
.X_add_number
= 0;
9215 if (expr1
.X_add_number
< -0x8000
9216 || expr1
.X_add_number
>= 0x8000)
9217 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9218 gpdelay
= reg_needs_delay (mips_gp_register
);
9219 relax_start (offset_expr
.X_add_symbol
);
9220 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9221 BFD_RELOC_MIPS_GOT_HI16
);
9222 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9224 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9225 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9228 macro_build (NULL
, "nop", "");
9229 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9230 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9232 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9233 tempreg
, BFD_RELOC_LO16
);
9237 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9238 tempreg
, tempreg
, breg
);
9239 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9241 else if (mips_big_got
&& HAVE_NEWABI
)
9243 /* If this is a reference to an external symbol, we want
9244 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9245 add $tempreg,$tempreg,$gp
9246 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9247 <op> $treg,<ofst>($tempreg)
9248 Otherwise, for local symbols, we want:
9249 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9250 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9251 gas_assert (offset_expr
.X_op
== O_symbol
);
9252 expr1
.X_add_number
= offset_expr
.X_add_number
;
9253 offset_expr
.X_add_number
= 0;
9254 if (expr1
.X_add_number
< -0x8000
9255 || expr1
.X_add_number
>= 0x8000)
9256 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9257 relax_start (offset_expr
.X_add_symbol
);
9258 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9259 BFD_RELOC_MIPS_GOT_HI16
);
9260 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9262 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9263 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9265 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9266 tempreg
, tempreg
, breg
);
9267 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9270 offset_expr
.X_add_number
= expr1
.X_add_number
;
9271 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9272 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9275 tempreg
, tempreg
, breg
);
9276 macro_build (&offset_expr
, s
, fmt
, treg
,
9277 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9287 load_register (treg
, &imm_expr
, 0);
9291 load_register (treg
, &imm_expr
, 1);
9295 if (imm_expr
.X_op
== O_constant
)
9298 load_register (AT
, &imm_expr
, 0);
9299 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9304 gas_assert (offset_expr
.X_op
== O_symbol
9305 && strcmp (segment_name (S_GET_SEGMENT
9306 (offset_expr
.X_add_symbol
)),
9308 && offset_expr
.X_add_number
== 0);
9309 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
9310 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9315 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9316 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9317 order 32 bits of the value and the low order 32 bits are either
9318 zero or in OFFSET_EXPR. */
9319 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9321 if (HAVE_64BIT_GPRS
)
9322 load_register (treg
, &imm_expr
, 1);
9327 if (target_big_endian
)
9339 load_register (hreg
, &imm_expr
, 0);
9342 if (offset_expr
.X_op
== O_absent
)
9343 move_register (lreg
, 0);
9346 gas_assert (offset_expr
.X_op
== O_constant
);
9347 load_register (lreg
, &offset_expr
, 0);
9354 /* We know that sym is in the .rdata section. First we get the
9355 upper 16 bits of the address. */
9356 if (mips_pic
== NO_PIC
)
9358 macro_build_lui (&offset_expr
, AT
);
9363 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9364 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9368 /* Now we load the register(s). */
9369 if (HAVE_64BIT_GPRS
)
9372 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9377 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9380 /* FIXME: How in the world do we deal with the possible
9382 offset_expr
.X_add_number
+= 4;
9383 macro_build (&offset_expr
, "lw", "t,o(b)",
9384 treg
+ 1, BFD_RELOC_LO16
, AT
);
9390 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9391 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9392 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9393 the value and the low order 32 bits are either zero or in
9395 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9398 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
9399 if (HAVE_64BIT_FPRS
)
9401 gas_assert (HAVE_64BIT_GPRS
);
9402 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
9406 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
9407 if (offset_expr
.X_op
== O_absent
)
9408 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
9411 gas_assert (offset_expr
.X_op
== O_constant
);
9412 load_register (AT
, &offset_expr
, 0);
9413 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9419 gas_assert (offset_expr
.X_op
== O_symbol
9420 && offset_expr
.X_add_number
== 0);
9421 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
9422 if (strcmp (s
, ".lit8") == 0)
9424 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9426 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
9427 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9430 breg
= mips_gp_register
;
9431 r
= BFD_RELOC_MIPS_LITERAL
;
9436 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
9438 if (mips_pic
!= NO_PIC
)
9439 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9440 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9443 /* FIXME: This won't work for a 64 bit address. */
9444 macro_build_lui (&offset_expr
, AT
);
9447 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9449 macro_build (&offset_expr
, "ldc1", "T,o(b)",
9450 treg
, BFD_RELOC_LO16
, AT
);
9459 /* Even on a big endian machine $fn comes before $fn+1. We have
9460 to adjust when loading from memory. */
9463 gas_assert (!mips_opts
.micromips
);
9464 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9465 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9466 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
9467 /* FIXME: A possible overflow which I don't know how to deal
9469 offset_expr
.X_add_number
+= 4;
9470 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9471 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9475 gas_assert (!mips_opts
.micromips
);
9476 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9477 /* Even on a big endian machine $fn comes before $fn+1. We have
9478 to adjust when storing to memory. */
9479 macro_build (&offset_expr
, "swc1", "T,o(b)",
9480 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9481 offset_expr
.X_add_number
+= 4;
9482 macro_build (&offset_expr
, "swc1", "T,o(b)",
9483 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9487 gas_assert (!mips_opts
.micromips
);
9489 * The MIPS assembler seems to check for X_add_number not
9490 * being double aligned and generating:
9493 * addiu at,at,%lo(foo+1)
9496 * But, the resulting address is the same after relocation so why
9497 * generate the extra instruction?
9499 /* Itbl support may require additional care here. */
9502 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9511 gas_assert (!mips_opts
.micromips
);
9512 /* Itbl support may require additional care here. */
9515 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9535 if (HAVE_64BIT_GPRS
)
9545 if (HAVE_64BIT_GPRS
)
9553 if (offset_expr
.X_op
!= O_symbol
9554 && offset_expr
.X_op
!= O_constant
)
9556 as_bad (_("Expression too complex"));
9557 offset_expr
.X_op
= O_constant
;
9560 if (HAVE_32BIT_ADDRESSES
9561 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9565 sprintf_vma (value
, offset_expr
.X_add_number
);
9566 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9569 /* Even on a big endian machine $fn comes before $fn+1. We have
9570 to adjust when loading from memory. We set coproc if we must
9571 load $fn+1 first. */
9572 /* Itbl support may require additional care here. */
9573 if (!target_big_endian
)
9576 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9578 /* If this is a reference to a GP relative symbol, we want
9579 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9580 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9581 If we have a base register, we use this
9583 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9584 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9585 If this is not a GP relative symbol, we want
9586 lui $at,<sym> (BFD_RELOC_HI16_S)
9587 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9588 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9589 If there is a base register, we add it to $at after the
9590 lui instruction. If there is a constant, we always use
9592 if (offset_expr
.X_op
== O_symbol
9593 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9594 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9596 relax_start (offset_expr
.X_add_symbol
);
9599 tempreg
= mips_gp_register
;
9603 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9604 AT
, breg
, mips_gp_register
);
9609 /* Itbl support may require additional care here. */
9610 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9611 BFD_RELOC_GPREL16
, tempreg
);
9612 offset_expr
.X_add_number
+= 4;
9614 /* Set mips_optimize to 2 to avoid inserting an
9616 hold_mips_optimize
= mips_optimize
;
9618 /* Itbl support may require additional care here. */
9619 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9620 BFD_RELOC_GPREL16
, tempreg
);
9621 mips_optimize
= hold_mips_optimize
;
9625 offset_expr
.X_add_number
-= 4;
9628 macro_build_lui (&offset_expr
, AT
);
9630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9631 /* Itbl support may require additional care here. */
9632 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9633 BFD_RELOC_LO16
, AT
);
9634 /* FIXME: How do we handle overflow here? */
9635 offset_expr
.X_add_number
+= 4;
9636 /* Itbl support may require additional care here. */
9637 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9638 BFD_RELOC_LO16
, AT
);
9639 if (mips_relax
.sequence
)
9642 else if (!mips_big_got
)
9644 /* If this is a reference to an external symbol, we want
9645 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9650 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9652 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9653 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9654 If there is a base register we add it to $at before the
9655 lwc1 instructions. If there is a constant we include it
9656 in the lwc1 instructions. */
9658 expr1
.X_add_number
= offset_expr
.X_add_number
;
9659 if (expr1
.X_add_number
< -0x8000
9660 || expr1
.X_add_number
>= 0x8000 - 4)
9661 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9662 load_got_offset (AT
, &offset_expr
);
9665 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9667 /* Set mips_optimize to 2 to avoid inserting an undesired
9669 hold_mips_optimize
= mips_optimize
;
9672 /* Itbl support may require additional care here. */
9673 relax_start (offset_expr
.X_add_symbol
);
9674 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9675 BFD_RELOC_LO16
, AT
);
9676 expr1
.X_add_number
+= 4;
9677 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9678 BFD_RELOC_LO16
, AT
);
9680 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9681 BFD_RELOC_LO16
, AT
);
9682 offset_expr
.X_add_number
+= 4;
9683 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9684 BFD_RELOC_LO16
, AT
);
9687 mips_optimize
= hold_mips_optimize
;
9689 else if (mips_big_got
)
9693 /* If this is a reference to an external symbol, we want
9694 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9696 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9701 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9703 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9704 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9705 If there is a base register we add it to $at before the
9706 lwc1 instructions. If there is a constant we include it
9707 in the lwc1 instructions. */
9709 expr1
.X_add_number
= offset_expr
.X_add_number
;
9710 offset_expr
.X_add_number
= 0;
9711 if (expr1
.X_add_number
< -0x8000
9712 || expr1
.X_add_number
>= 0x8000 - 4)
9713 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9714 gpdelay
= reg_needs_delay (mips_gp_register
);
9715 relax_start (offset_expr
.X_add_symbol
);
9716 macro_build (&offset_expr
, "lui", LUI_FMT
,
9717 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9718 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9719 AT
, AT
, mips_gp_register
);
9720 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9721 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9724 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9725 /* Itbl support may require additional care here. */
9726 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9727 BFD_RELOC_LO16
, AT
);
9728 expr1
.X_add_number
+= 4;
9730 /* Set mips_optimize to 2 to avoid inserting an undesired
9732 hold_mips_optimize
= mips_optimize
;
9734 /* Itbl support may require additional care here. */
9735 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9736 BFD_RELOC_LO16
, AT
);
9737 mips_optimize
= hold_mips_optimize
;
9738 expr1
.X_add_number
-= 4;
9741 offset_expr
.X_add_number
= expr1
.X_add_number
;
9743 macro_build (NULL
, "nop", "");
9744 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9745 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9748 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9749 /* Itbl support may require additional care here. */
9750 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9751 BFD_RELOC_LO16
, AT
);
9752 offset_expr
.X_add_number
+= 4;
9754 /* Set mips_optimize to 2 to avoid inserting an undesired
9756 hold_mips_optimize
= mips_optimize
;
9758 /* Itbl support may require additional care here. */
9759 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9760 BFD_RELOC_LO16
, AT
);
9761 mips_optimize
= hold_mips_optimize
;
9770 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9773 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9775 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9776 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9778 if (!HAVE_64BIT_GPRS
)
9780 offset_expr
.X_add_number
+= 4;
9781 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9782 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9803 /* New code added to support COPZ instructions.
9804 This code builds table entries out of the macros in mip_opcodes.
9805 R4000 uses interlocks to handle coproc delays.
9806 Other chips (like the R3000) require nops to be inserted for delays.
9808 FIXME: Currently, we require that the user handle delays.
9809 In order to fill delay slots for non-interlocked chips,
9810 we must have a way to specify delays based on the coprocessor.
9811 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9812 What are the side-effects of the cop instruction?
9813 What cache support might we have and what are its effects?
9814 Both coprocessor & memory require delays. how long???
9815 What registers are read/set/modified?
9817 If an itbl is provided to interpret cop instructions,
9818 this knowledge can be encoded in the itbl spec. */
9832 gas_assert (!mips_opts
.micromips
);
9833 /* For now we just do C (same as Cz). The parameter will be
9834 stored in insn_opcode by mips_ip. */
9835 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9839 move_register (dreg
, sreg
);
9845 if (mips_opts
.arch
== CPU_R5900
)
9847 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9851 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9852 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9859 /* The MIPS assembler some times generates shifts and adds. I'm
9860 not trying to be that fancy. GCC should do this for us
9863 load_register (AT
, &imm_expr
, dbl
);
9864 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9865 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9881 load_register (AT
, &imm_expr
, dbl
);
9882 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9883 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9884 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9885 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9887 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9890 if (mips_opts
.micromips
)
9891 micromips_label_expr (&label_expr
);
9893 label_expr
.X_add_number
= 8;
9894 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9895 macro_build (NULL
, "nop", "");
9896 macro_build (NULL
, "break", BRK_FMT
, 6);
9897 if (mips_opts
.micromips
)
9898 micromips_add_label ();
9901 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9917 load_register (AT
, &imm_expr
, dbl
);
9918 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9919 sreg
, imm
? AT
: treg
);
9920 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9921 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9923 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9926 if (mips_opts
.micromips
)
9927 micromips_label_expr (&label_expr
);
9929 label_expr
.X_add_number
= 8;
9930 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9931 macro_build (NULL
, "nop", "");
9932 macro_build (NULL
, "break", BRK_FMT
, 6);
9933 if (mips_opts
.micromips
)
9934 micromips_add_label ();
9940 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9951 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9952 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9956 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9957 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9958 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9959 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9963 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9974 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9975 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9979 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9980 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9981 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9982 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9991 if (imm_expr
.X_op
!= O_constant
)
9992 as_bad (_("Improper rotate count"));
9993 rot
= imm_expr
.X_add_number
& 0x3f;
9994 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9996 rot
= (64 - rot
) & 0x3f;
9998 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10000 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10005 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10008 l
= (rot
< 0x20) ? "dsll" : "dsll32";
10009 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
10012 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
10013 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10014 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10022 if (imm_expr
.X_op
!= O_constant
)
10023 as_bad (_("Improper rotate count"));
10024 rot
= imm_expr
.X_add_number
& 0x1f;
10025 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10027 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
10032 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10036 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
10037 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10038 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10043 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10045 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
10049 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10050 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
10051 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
10052 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10056 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10058 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
10062 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10063 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
10064 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
10065 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10074 if (imm_expr
.X_op
!= O_constant
)
10075 as_bad (_("Improper rotate count"));
10076 rot
= imm_expr
.X_add_number
& 0x3f;
10077 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10080 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10082 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10087 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10090 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
10091 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
10094 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
10095 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10096 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10104 if (imm_expr
.X_op
!= O_constant
)
10105 as_bad (_("Improper rotate count"));
10106 rot
= imm_expr
.X_add_number
& 0x1f;
10107 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10109 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
10114 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10118 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
10119 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10120 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10126 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
10127 else if (treg
== 0)
10128 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10131 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10132 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10137 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10139 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10144 as_warn (_("Instruction %s: result is always false"),
10145 ip
->insn_mo
->name
);
10146 move_register (dreg
, 0);
10149 if (CPU_HAS_SEQ (mips_opts
.arch
)
10150 && -512 <= imm_expr
.X_add_number
10151 && imm_expr
.X_add_number
< 512)
10153 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
10154 (int) imm_expr
.X_add_number
);
10157 if (imm_expr
.X_op
== O_constant
10158 && imm_expr
.X_add_number
>= 0
10159 && imm_expr
.X_add_number
< 0x10000)
10161 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10163 else if (imm_expr
.X_op
== O_constant
10164 && imm_expr
.X_add_number
> -0x8000
10165 && imm_expr
.X_add_number
< 0)
10167 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10168 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10169 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10171 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10174 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10175 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
10180 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10181 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10184 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10187 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
10193 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
10194 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10197 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
10199 if (imm_expr
.X_op
== O_constant
10200 && imm_expr
.X_add_number
>= -0x8000
10201 && imm_expr
.X_add_number
< 0x8000)
10203 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
10204 dreg
, sreg
, BFD_RELOC_LO16
);
10208 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10209 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
10213 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10216 case M_SGT
: /* sreg > treg <==> treg < sreg */
10222 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10225 case M_SGT_I
: /* sreg > I <==> I < sreg */
10232 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10233 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10236 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10242 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10243 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10246 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10253 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10254 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10255 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10259 if (imm_expr
.X_op
== O_constant
10260 && imm_expr
.X_add_number
>= -0x8000
10261 && imm_expr
.X_add_number
< 0x8000)
10263 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10267 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10268 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
10272 if (imm_expr
.X_op
== O_constant
10273 && imm_expr
.X_add_number
>= -0x8000
10274 && imm_expr
.X_add_number
< 0x8000)
10276 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
10281 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10282 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
10287 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
10288 else if (treg
== 0)
10289 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10292 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10293 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10298 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10300 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10305 as_warn (_("Instruction %s: result is always true"),
10306 ip
->insn_mo
->name
);
10307 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
10308 dreg
, 0, BFD_RELOC_LO16
);
10311 if (CPU_HAS_SEQ (mips_opts
.arch
)
10312 && -512 <= imm_expr
.X_add_number
10313 && imm_expr
.X_add_number
< 512)
10315 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
10316 (int) imm_expr
.X_add_number
);
10319 if (imm_expr
.X_op
== O_constant
10320 && imm_expr
.X_add_number
>= 0
10321 && imm_expr
.X_add_number
< 0x10000)
10323 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10325 else if (imm_expr
.X_op
== O_constant
10326 && imm_expr
.X_add_number
> -0x8000
10327 && imm_expr
.X_add_number
< 0)
10329 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10330 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10331 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10333 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10336 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10337 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
10342 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10343 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10346 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10361 if (!mips_opts
.micromips
)
10363 if (imm_expr
.X_op
== O_constant
10364 && imm_expr
.X_add_number
> -0x200
10365 && imm_expr
.X_add_number
<= 0x200)
10367 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
10376 if (imm_expr
.X_op
== O_constant
10377 && imm_expr
.X_add_number
> -0x8000
10378 && imm_expr
.X_add_number
<= 0x8000)
10380 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10381 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10386 load_register (AT
, &imm_expr
, dbl
);
10387 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
10409 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10410 macro_build (NULL
, s
, "s,t", sreg
, AT
);
10415 gas_assert (!mips_opts
.micromips
);
10416 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
10418 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
10419 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
10422 * Is the double cfc1 instruction a bug in the mips assembler;
10423 * or is there a reason for it?
10425 start_noreorder ();
10426 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10427 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10428 macro_build (NULL
, "nop", "");
10429 expr1
.X_add_number
= 3;
10430 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
10431 expr1
.X_add_number
= 2;
10432 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
10433 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
10434 macro_build (NULL
, "nop", "");
10435 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
10437 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
10438 macro_build (NULL
, "nop", "");
10461 offbits
= (mips_opts
.micromips
? 12 : 16);
10469 offbits
= (mips_opts
.micromips
? 12 : 16);
10485 offbits
= (mips_opts
.micromips
? 12 : 16);
10494 offbits
= (mips_opts
.micromips
? 12 : 16);
10499 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10500 as_bad (_("Operand overflow"));
10503 expr1
.X_add_number
= 0;
10508 load_address (tempreg
, ep
, &used_at
);
10510 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10511 tempreg
, tempreg
, breg
);
10516 else if (offbits
== 12
10517 && (offset_expr
.X_op
!= O_constant
10518 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10519 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10523 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10524 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10529 else if (!ust
&& treg
== breg
)
10540 if (!target_big_endian
)
10541 ep
->X_add_number
+= off
;
10543 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10545 macro_build (NULL
, s
, "t,~(b)",
10546 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10548 if (!target_big_endian
)
10549 ep
->X_add_number
-= off
;
10551 ep
->X_add_number
+= off
;
10553 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10555 macro_build (NULL
, s2
, "t,~(b)",
10556 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10558 /* If necessary, move the result in tempreg to the final destination. */
10559 if (!ust
&& treg
!= tempreg
)
10561 /* Protect second load's delay slot. */
10563 move_register (treg
, tempreg
);
10569 if (target_big_endian
== ust
)
10570 ep
->X_add_number
+= off
;
10571 tempreg
= ust
|| ab
? treg
: AT
;
10572 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10574 /* For halfword transfers we need a temporary register to shuffle
10575 bytes. Unfortunately for M_USH_A we have none available before
10576 the next store as AT holds the base address. We deal with this
10577 case by clobbering TREG and then restoring it as with ULH. */
10578 tempreg
= ust
== ab
? treg
: AT
;
10580 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10582 if (target_big_endian
== ust
)
10583 ep
->X_add_number
-= off
;
10585 ep
->X_add_number
+= off
;
10586 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10588 /* For M_USH_A re-retrieve the LSB. */
10591 if (target_big_endian
)
10592 ep
->X_add_number
+= off
;
10594 ep
->X_add_number
-= off
;
10595 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10597 /* For ULH and M_USH_A OR the LSB in. */
10600 tempreg
= !ab
? AT
: treg
;
10601 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10602 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10607 /* FIXME: Check if this is one of the itbl macros, since they
10608 are added dynamically. */
10609 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10612 if (!mips_opts
.at
&& used_at
)
10613 as_bad (_("Macro used $at after \".set noat\""));
10616 /* Implement macros in mips16 mode. */
10619 mips16_macro (struct mips_cl_insn
*ip
)
10622 int xreg
, yreg
, zreg
, tmp
;
10625 const char *s
, *s2
, *s3
;
10627 mask
= ip
->insn_mo
->mask
;
10629 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10630 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10631 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10633 expr1
.X_op
= O_constant
;
10634 expr1
.X_op_symbol
= NULL
;
10635 expr1
.X_add_symbol
= NULL
;
10636 expr1
.X_add_number
= 1;
10655 start_noreorder ();
10656 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10657 expr1
.X_add_number
= 2;
10658 macro_build (&expr1
, "bnez", "x,p", yreg
);
10659 macro_build (NULL
, "break", "6", 7);
10661 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10662 since that causes an overflow. We should do that as well,
10663 but I don't see how to do the comparisons without a temporary
10666 macro_build (NULL
, s
, "x", zreg
);
10685 start_noreorder ();
10686 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10687 expr1
.X_add_number
= 2;
10688 macro_build (&expr1
, "bnez", "x,p", yreg
);
10689 macro_build (NULL
, "break", "6", 7);
10691 macro_build (NULL
, s2
, "x", zreg
);
10697 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10698 macro_build (NULL
, "mflo", "x", zreg
);
10706 if (imm_expr
.X_op
!= O_constant
)
10707 as_bad (_("Unsupported large constant"));
10708 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10709 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10713 if (imm_expr
.X_op
!= O_constant
)
10714 as_bad (_("Unsupported large constant"));
10715 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10716 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10720 if (imm_expr
.X_op
!= O_constant
)
10721 as_bad (_("Unsupported large constant"));
10722 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10723 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10745 goto do_reverse_branch
;
10749 goto do_reverse_branch
;
10761 goto do_reverse_branch
;
10772 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10773 macro_build (&offset_expr
, s2
, "p");
10800 goto do_addone_branch_i
;
10805 goto do_addone_branch_i
;
10820 goto do_addone_branch_i
;
10826 do_addone_branch_i
:
10827 if (imm_expr
.X_op
!= O_constant
)
10828 as_bad (_("Unsupported large constant"));
10829 ++imm_expr
.X_add_number
;
10832 macro_build (&imm_expr
, s
, s3
, xreg
);
10833 macro_build (&offset_expr
, s2
, "p");
10837 expr1
.X_add_number
= 0;
10838 macro_build (&expr1
, "slti", "x,8", yreg
);
10840 move_register (xreg
, yreg
);
10841 expr1
.X_add_number
= 2;
10842 macro_build (&expr1
, "bteqz", "p");
10843 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10847 /* For consistency checking, verify that all bits are specified either
10848 by the match/mask part of the instruction definition, or by the
10851 validate_mips_insn (const struct mips_opcode
*opc
)
10853 const char *p
= opc
->args
;
10855 unsigned long used_bits
= opc
->mask
;
10857 if ((used_bits
& opc
->match
) != opc
->match
)
10859 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10860 opc
->name
, opc
->args
);
10863 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10873 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10874 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10875 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10876 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10877 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10878 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10879 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10880 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10881 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10882 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10883 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10884 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10885 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10887 case 'J': USE_BITS (OP_MASK_CODE10
, OP_SH_CODE10
); break;
10888 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10889 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10890 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10891 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10892 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10893 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10894 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10895 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10896 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10897 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10898 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10899 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10900 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10901 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10902 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10903 case 'j': USE_BITS (OP_MASK_EVAOFFSET
, OP_SH_EVAOFFSET
); break;
10906 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10907 c
, opc
->name
, opc
->args
);
10911 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10912 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10914 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10915 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10916 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10917 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10919 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10920 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10922 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10923 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10925 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10926 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10927 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10928 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10929 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10930 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10931 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10932 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10933 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10934 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10935 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10936 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10937 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10938 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10939 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10940 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10941 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10943 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10944 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10945 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10946 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10948 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10949 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10950 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10951 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10952 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10953 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10954 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10955 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10956 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10959 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10960 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10961 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10962 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10963 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10966 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10967 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10968 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10969 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10970 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10971 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10972 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10973 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10974 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10975 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10976 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10977 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10978 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10979 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10980 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10981 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10982 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10983 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10984 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10985 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10987 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10988 c
, opc
->name
, opc
->args
);
10992 if (used_bits
!= 0xffffffff)
10994 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10995 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
11001 /* For consistency checking, verify that the length implied matches the
11002 major opcode and that all bits are specified either by the match/mask
11003 part of the instruction definition, or by the operand list. */
11006 validate_micromips_insn (const struct mips_opcode
*opc
)
11008 unsigned long match
= opc
->match
;
11009 unsigned long mask
= opc
->mask
;
11010 const char *p
= opc
->args
;
11011 unsigned long insn_bits
;
11012 unsigned long used_bits
;
11013 unsigned long major
;
11014 unsigned int length
;
11018 if ((mask
& match
) != match
)
11020 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
11021 opc
->name
, opc
->args
);
11024 length
= micromips_insn_length (opc
);
11025 if (length
!= 2 && length
!= 4)
11027 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
11028 "%s %s"), length
, opc
->name
, opc
->args
);
11031 major
= match
>> (10 + 8 * (length
- 2));
11032 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
11033 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
11035 as_bad (_("Internal error: bad microMIPS opcode "
11036 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
11040 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
11041 insn_bits
= 1 << 4 * length
;
11042 insn_bits
<<= 4 * length
;
11045 #define USE_BITS(field) \
11046 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
11057 case 'A': USE_BITS (EXTLSB
); break;
11058 case 'B': USE_BITS (INSMSB
); break;
11059 case 'C': USE_BITS (EXTMSBD
); break;
11060 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
11061 case 'E': USE_BITS (EXTLSB
); break;
11062 case 'F': USE_BITS (INSMSB
); break;
11063 case 'G': USE_BITS (EXTMSBD
); break;
11064 case 'H': USE_BITS (EXTMSBD
); break;
11065 case 'j': USE_BITS (EVAOFFSET
); break;
11067 as_bad (_("Internal error: bad mips opcode "
11068 "(unknown extension operand type `%c%c'): %s %s"),
11069 e
, c
, opc
->name
, opc
->args
);
11077 case 'A': USE_BITS (IMMA
); break;
11078 case 'B': USE_BITS (IMMB
); break;
11079 case 'C': USE_BITS (IMMC
); break;
11080 case 'D': USE_BITS (IMMD
); break;
11081 case 'E': USE_BITS (IMME
); break;
11082 case 'F': USE_BITS (IMMF
); break;
11083 case 'G': USE_BITS (IMMG
); break;
11084 case 'H': USE_BITS (IMMH
); break;
11085 case 'I': USE_BITS (IMMI
); break;
11086 case 'J': USE_BITS (IMMJ
); break;
11087 case 'L': USE_BITS (IMML
); break;
11088 case 'M': USE_BITS (IMMM
); break;
11089 case 'N': USE_BITS (IMMN
); break;
11090 case 'O': USE_BITS (IMMO
); break;
11091 case 'P': USE_BITS (IMMP
); break;
11092 case 'Q': USE_BITS (IMMQ
); break;
11093 case 'U': USE_BITS (IMMU
); break;
11094 case 'W': USE_BITS (IMMW
); break;
11095 case 'X': USE_BITS (IMMX
); break;
11096 case 'Y': USE_BITS (IMMY
); break;
11099 case 'b': USE_BITS (MB
); break;
11100 case 'c': USE_BITS (MC
); break;
11101 case 'd': USE_BITS (MD
); break;
11102 case 'e': USE_BITS (ME
); break;
11103 case 'f': USE_BITS (MF
); break;
11104 case 'g': USE_BITS (MG
); break;
11105 case 'h': USE_BITS (MH
); break;
11106 case 'i': USE_BITS (MI
); break;
11107 case 'j': USE_BITS (MJ
); break;
11108 case 'l': USE_BITS (ML
); break;
11109 case 'm': USE_BITS (MM
); break;
11110 case 'n': USE_BITS (MN
); break;
11111 case 'p': USE_BITS (MP
); break;
11112 case 'q': USE_BITS (MQ
); break;
11120 as_bad (_("Internal error: bad mips opcode "
11121 "(unknown extension operand type `%c%c'): %s %s"),
11122 e
, c
, opc
->name
, opc
->args
);
11126 case '.': USE_BITS (OFFSET10
); break;
11127 case '1': USE_BITS (STYPE
); break;
11128 case '2': USE_BITS (BP
); break;
11129 case '3': USE_BITS (SA3
); break;
11130 case '4': USE_BITS (SA4
); break;
11131 case '5': USE_BITS (IMM8
); break;
11132 case '6': USE_BITS (RS
); break;
11133 case '7': USE_BITS (DSPACC
); break;
11134 case '8': USE_BITS (WRDSP
); break;
11135 case '0': USE_BITS (DSPSFT
); break;
11136 case '<': USE_BITS (SHAMT
); break;
11137 case '>': USE_BITS (SHAMT
); break;
11138 case '@': USE_BITS (IMM10
); break;
11139 case 'B': USE_BITS (CODE10
); break;
11140 case 'C': USE_BITS (COPZ
); break;
11141 case 'D': USE_BITS (FD
); break;
11142 case 'E': USE_BITS (RT
); break;
11143 case 'G': USE_BITS (RS
); break;
11144 case 'H': USE_BITS (SEL
); break;
11145 case 'K': USE_BITS (RS
); break;
11146 case 'M': USE_BITS (CCC
); break;
11147 case 'N': USE_BITS (BCC
); break;
11148 case 'R': USE_BITS (FR
); break;
11149 case 'S': USE_BITS (FS
); break;
11150 case 'T': USE_BITS (FT
); break;
11151 case 'V': USE_BITS (FS
); break;
11152 case '\\': USE_BITS (3BITPOS
); break;
11153 case '^': USE_BITS (RD
); break;
11154 case 'a': USE_BITS (TARGET
); break;
11155 case 'b': USE_BITS (RS
); break;
11156 case 'c': USE_BITS (CODE
); break;
11157 case 'd': USE_BITS (RD
); break;
11158 case 'h': USE_BITS (PREFX
); break;
11159 case 'i': USE_BITS (IMMEDIATE
); break;
11160 case 'j': USE_BITS (DELTA
); break;
11161 case 'k': USE_BITS (CACHE
); break;
11162 case 'n': USE_BITS (RT
); break;
11163 case 'o': USE_BITS (DELTA
); break;
11164 case 'p': USE_BITS (DELTA
); break;
11165 case 'q': USE_BITS (CODE2
); break;
11166 case 'r': USE_BITS (RS
); break;
11167 case 's': USE_BITS (RS
); break;
11168 case 't': USE_BITS (RT
); break;
11169 case 'u': USE_BITS (IMMEDIATE
); break;
11170 case 'v': USE_BITS (RS
); break;
11171 case 'w': USE_BITS (RT
); break;
11172 case 'y': USE_BITS (RS3
); break;
11174 case '|': USE_BITS (TRAP
); break;
11175 case '~': USE_BITS (OFFSET12
); break;
11177 as_bad (_("Internal error: bad microMIPS opcode "
11178 "(unknown operand type `%c'): %s %s"),
11179 c
, opc
->name
, opc
->args
);
11183 if (used_bits
!= insn_bits
)
11185 if (~used_bits
& insn_bits
)
11186 as_bad (_("Internal error: bad microMIPS opcode "
11187 "(bits 0x%lx undefined): %s %s"),
11188 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
11189 if (used_bits
& ~insn_bits
)
11190 as_bad (_("Internal error: bad microMIPS opcode "
11191 "(bits 0x%lx defined): %s %s"),
11192 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
11198 /* UDI immediates. */
11199 struct mips_immed
{
11201 unsigned int shift
;
11202 unsigned long mask
;
11206 static const struct mips_immed mips_immed
[] = {
11207 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
11208 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
11209 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
11210 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
11214 /* Check whether an odd floating-point register is allowed. */
11216 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
11218 const char *s
= insn
->name
;
11220 if (insn
->pinfo
== INSN_MACRO
)
11221 /* Let a macro pass, we'll catch it later when it is expanded. */
11224 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
11226 /* Allow odd registers for single-precision ops. */
11227 switch (insn
->pinfo
& (FP_S
| FP_D
))
11231 return 1; /* both single precision - ok */
11233 return 0; /* both double precision - fail */
11238 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11239 s
= strchr (insn
->name
, '.');
11241 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
11242 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
11245 /* Single-precision coprocessor loads and moves are OK too. */
11246 if ((insn
->pinfo
& FP_S
)
11247 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
11248 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
11254 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11255 taking bits from BIT up. */
11257 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
11259 return (ep
->X_op
== O_constant
11260 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
11261 && ep
->X_add_number
>= min
<< bit
11262 && ep
->X_add_number
< max
<< bit
);
11265 /* This routine assembles an instruction into its binary format. As a
11266 side effect, it sets one of the global variables imm_reloc or
11267 offset_reloc to the type of relocation to do if one of the operands
11268 is an address expression. */
11271 mips_ip (char *str
, struct mips_cl_insn
*ip
)
11273 bfd_boolean wrong_delay_slot_insns
= FALSE
;
11274 bfd_boolean need_delay_slot_ok
= TRUE
;
11275 struct mips_opcode
*firstinsn
= NULL
;
11276 const struct mips_opcode
*past
;
11277 struct hash_control
*hash
;
11281 struct mips_opcode
*insn
;
11283 unsigned int regno
;
11284 unsigned int lastregno
;
11285 unsigned int destregno
= 0;
11286 unsigned int lastpos
= 0;
11287 unsigned int limlo
, limhi
;
11290 offsetT min_range
, max_range
;
11294 unsigned int rtype
;
11300 if (mips_opts
.micromips
)
11302 hash
= micromips_op_hash
;
11303 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
11308 past
= &mips_opcodes
[NUMOPCODES
];
11310 forced_insn_length
= 0;
11313 /* We first try to match an instruction up to a space or to the end. */
11314 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
11317 /* Make a copy of the instruction so that we can fiddle with it. */
11318 name
= alloca (end
+ 1);
11319 memcpy (name
, str
, end
);
11324 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
11326 if (insn
!= NULL
|| !mips_opts
.micromips
)
11328 if (forced_insn_length
)
11331 /* See if there's an instruction size override suffix,
11332 either `16' or `32', at the end of the mnemonic proper,
11333 that defines the operation, i.e. before the first `.'
11334 character if any. Strip it and retry. */
11335 dot
= strchr (name
, '.');
11336 opend
= dot
!= NULL
? dot
- name
: end
;
11339 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
11340 forced_insn_length
= 2;
11341 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11342 forced_insn_length
= 4;
11345 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11349 insn_error
= _("Unrecognized opcode");
11353 /* For microMIPS instructions placed in a fixed-length branch delay slot
11354 we make up to two passes over the relevant fragment of the opcode
11355 table. First we try instructions that meet the delay slot's length
11356 requirement. If none matched, then we retry with the remaining ones
11357 and if one matches, then we use it and then issue an appropriate
11358 warning later on. */
11359 argsStart
= s
= str
+ end
;
11362 bfd_boolean delay_slot_ok
;
11363 bfd_boolean size_ok
;
11366 gas_assert (strcmp (insn
->name
, name
) == 0);
11368 ok
= is_opcode_valid (insn
);
11369 size_ok
= is_size_valid (insn
);
11370 delay_slot_ok
= is_delay_slot_valid (insn
);
11371 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11374 wrong_delay_slot_insns
= TRUE
;
11376 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11378 static char buf
[256];
11380 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
11385 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11387 gas_assert (firstinsn
);
11388 need_delay_slot_ok
= FALSE
;
11398 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11399 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11400 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11402 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11403 8 * forced_insn_length
);
11409 create_insn (ip
, insn
);
11412 lastregno
= 0xffffffff;
11413 for (args
= insn
->args
;; ++args
)
11417 s
+= strspn (s
, " \t");
11421 case '\0': /* end of args */
11427 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11428 code) or 14 (for microMIPS code). */
11429 my_getExpression (&imm_expr
, s
);
11430 check_absolute_expr (ip
, &imm_expr
);
11431 if ((unsigned long) imm_expr
.X_add_number
!= 1
11432 && (unsigned long) imm_expr
.X_add_number
!= 3)
11434 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11435 (unsigned long) imm_expr
.X_add_number
);
11437 INSERT_OPERAND (mips_opts
.micromips
,
11438 BP
, *ip
, imm_expr
.X_add_number
);
11439 imm_expr
.X_op
= O_absent
;
11444 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
11445 code) or 21 (for microMIPS code). */
11447 unsigned long mask
= (mips_opts
.micromips
11448 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11450 my_getExpression (&imm_expr
, s
);
11451 check_absolute_expr (ip
, &imm_expr
);
11452 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11453 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11454 mask
, (unsigned long) imm_expr
.X_add_number
);
11455 INSERT_OPERAND (mips_opts
.micromips
,
11456 SA3
, *ip
, imm_expr
.X_add_number
);
11457 imm_expr
.X_op
= O_absent
;
11463 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11464 code) or 21 (for microMIPS code). */
11466 unsigned long mask
= (mips_opts
.micromips
11467 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11469 my_getExpression (&imm_expr
, s
);
11470 check_absolute_expr (ip
, &imm_expr
);
11471 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11472 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11473 mask
, (unsigned long) imm_expr
.X_add_number
);
11474 INSERT_OPERAND (mips_opts
.micromips
,
11475 SA4
, *ip
, imm_expr
.X_add_number
);
11476 imm_expr
.X_op
= O_absent
;
11482 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11483 code) or 16 (for microMIPS code). */
11485 unsigned long mask
= (mips_opts
.micromips
11486 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11488 my_getExpression (&imm_expr
, s
);
11489 check_absolute_expr (ip
, &imm_expr
);
11490 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11491 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11492 mask
, (unsigned long) imm_expr
.X_add_number
);
11493 INSERT_OPERAND (mips_opts
.micromips
,
11494 IMM8
, *ip
, imm_expr
.X_add_number
);
11495 imm_expr
.X_op
= O_absent
;
11501 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11502 code) or 21 (for microMIPS code). */
11504 unsigned long mask
= (mips_opts
.micromips
11505 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11507 my_getExpression (&imm_expr
, s
);
11508 check_absolute_expr (ip
, &imm_expr
);
11509 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11510 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11511 mask
, (unsigned long) imm_expr
.X_add_number
);
11512 INSERT_OPERAND (mips_opts
.micromips
,
11513 RS
, *ip
, imm_expr
.X_add_number
);
11514 imm_expr
.X_op
= O_absent
;
11519 case '7': /* Four DSP accumulators in bits 11,12. */
11520 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11521 && s
[3] >= '0' && s
[3] <= '3')
11523 regno
= s
[3] - '0';
11525 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11529 as_bad (_("Invalid dsp acc register"));
11533 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11534 code) or 14 (for microMIPS code). */
11536 unsigned long mask
= (mips_opts
.micromips
11537 ? MICROMIPSOP_MASK_WRDSP
11540 my_getExpression (&imm_expr
, s
);
11541 check_absolute_expr (ip
, &imm_expr
);
11542 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11543 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11544 mask
, (unsigned long) imm_expr
.X_add_number
);
11545 INSERT_OPERAND (mips_opts
.micromips
,
11546 WRDSP
, *ip
, imm_expr
.X_add_number
);
11547 imm_expr
.X_op
= O_absent
;
11552 case '9': /* Four DSP accumulators in bits 21,22. */
11553 gas_assert (!mips_opts
.micromips
);
11554 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11555 && s
[3] >= '0' && s
[3] <= '3')
11557 regno
= s
[3] - '0';
11559 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11563 as_bad (_("Invalid dsp acc register"));
11567 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11568 code) or 20 (for microMIPS code). */
11570 long mask
= (mips_opts
.micromips
11571 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11573 my_getExpression (&imm_expr
, s
);
11574 check_absolute_expr (ip
, &imm_expr
);
11575 min_range
= -((mask
+ 1) >> 1);
11576 max_range
= ((mask
+ 1) >> 1) - 1;
11577 if (imm_expr
.X_add_number
< min_range
11578 || imm_expr
.X_add_number
> max_range
)
11579 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11580 (long) min_range
, (long) max_range
,
11581 (long) imm_expr
.X_add_number
);
11582 INSERT_OPERAND (mips_opts
.micromips
,
11583 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11584 imm_expr
.X_op
= O_absent
;
11589 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11590 gas_assert (!mips_opts
.micromips
);
11591 my_getExpression (&imm_expr
, s
);
11592 check_absolute_expr (ip
, &imm_expr
);
11593 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11595 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11597 (unsigned long) imm_expr
.X_add_number
);
11599 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11600 imm_expr
.X_op
= O_absent
;
11604 case ':': /* DSP 7-bit signed immediate in bit 19. */
11605 gas_assert (!mips_opts
.micromips
);
11606 my_getExpression (&imm_expr
, s
);
11607 check_absolute_expr (ip
, &imm_expr
);
11608 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11609 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11610 if (imm_expr
.X_add_number
< min_range
||
11611 imm_expr
.X_add_number
> max_range
)
11613 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11614 (long) min_range
, (long) max_range
,
11615 (long) imm_expr
.X_add_number
);
11617 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11618 imm_expr
.X_op
= O_absent
;
11622 case '@': /* DSP 10-bit signed immediate in bit 16. */
11624 long mask
= (mips_opts
.micromips
11625 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11627 my_getExpression (&imm_expr
, s
);
11628 check_absolute_expr (ip
, &imm_expr
);
11629 min_range
= -((mask
+ 1) >> 1);
11630 max_range
= ((mask
+ 1) >> 1) - 1;
11631 if (imm_expr
.X_add_number
< min_range
11632 || imm_expr
.X_add_number
> max_range
)
11633 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11634 (long) min_range
, (long) max_range
,
11635 (long) imm_expr
.X_add_number
);
11636 INSERT_OPERAND (mips_opts
.micromips
,
11637 IMM10
, *ip
, imm_expr
.X_add_number
);
11638 imm_expr
.X_op
= O_absent
;
11643 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11644 gas_assert (mips_opts
.micromips
);
11645 my_getExpression (&imm_expr
, s
);
11646 check_absolute_expr (ip
, &imm_expr
);
11647 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11648 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11649 MICROMIPSOP_MASK_RD
,
11650 (unsigned long) imm_expr
.X_add_number
);
11651 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11652 imm_expr
.X_op
= O_absent
;
11656 case '!': /* MT usermode flag bit. */
11657 gas_assert (!mips_opts
.micromips
);
11658 my_getExpression (&imm_expr
, s
);
11659 check_absolute_expr (ip
, &imm_expr
);
11660 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11661 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11662 (unsigned long) imm_expr
.X_add_number
);
11663 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11664 imm_expr
.X_op
= O_absent
;
11668 case '$': /* MT load high flag bit. */
11669 gas_assert (!mips_opts
.micromips
);
11670 my_getExpression (&imm_expr
, s
);
11671 check_absolute_expr (ip
, &imm_expr
);
11672 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11673 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11674 (unsigned long) imm_expr
.X_add_number
);
11675 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11676 imm_expr
.X_op
= O_absent
;
11680 case '*': /* Four DSP accumulators in bits 18,19. */
11681 gas_assert (!mips_opts
.micromips
);
11682 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11683 s
[3] >= '0' && s
[3] <= '3')
11685 regno
= s
[3] - '0';
11687 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11691 as_bad (_("Invalid dsp/smartmips acc register"));
11694 case '&': /* Four DSP accumulators in bits 13,14. */
11695 gas_assert (!mips_opts
.micromips
);
11696 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11697 s
[3] >= '0' && s
[3] <= '3')
11699 regno
= s
[3] - '0';
11701 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11705 as_bad (_("Invalid dsp/smartmips acc register"));
11708 case '\\': /* 3-bit bit position. */
11710 unsigned long mask
= (mips_opts
.micromips
11711 ? MICROMIPSOP_MASK_3BITPOS
11712 : OP_MASK_3BITPOS
);
11714 my_getExpression (&imm_expr
, s
);
11715 check_absolute_expr (ip
, &imm_expr
);
11716 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11717 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11719 mask
, (unsigned long) imm_expr
.X_add_number
);
11720 INSERT_OPERAND (mips_opts
.micromips
,
11721 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11722 imm_expr
.X_op
= O_absent
;
11736 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11740 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11744 gas_assert (!mips_opts
.micromips
);
11745 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11749 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11755 /* Handle optional base register.
11756 Either the base register is omitted or
11757 we must have a left paren. */
11758 /* This is dependent on the next operand specifier
11759 is a base register specification. */
11760 gas_assert (args
[1] == 'b'
11761 || (mips_opts
.micromips
11763 && (args
[2] == 'l' || args
[2] == 'n'
11764 || args
[2] == 's' || args
[2] == 'a')));
11765 if (*s
== '\0' && args
[1] == 'b')
11767 /* Fall through. */
11769 case ')': /* These must match exactly. */
11774 case '[': /* These must match exactly. */
11776 gas_assert (!mips_opts
.micromips
);
11781 case '+': /* Opcode extension character. */
11784 case '1': /* UDI immediates. */
11788 gas_assert (!mips_opts
.micromips
);
11790 const struct mips_immed
*imm
= mips_immed
;
11792 while (imm
->type
&& imm
->type
!= *args
)
11796 my_getExpression (&imm_expr
, s
);
11797 check_absolute_expr (ip
, &imm_expr
);
11798 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11800 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11801 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11802 (unsigned long) imm_expr
.X_add_number
,
11803 (unsigned long) imm_expr
.X_add_number
);
11804 imm_expr
.X_add_number
&= imm
->mask
;
11806 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11808 imm_expr
.X_op
= O_absent
;
11813 case 'J': /* 10-bit hypcall code. */
11814 gas_assert (!mips_opts
.micromips
);
11816 unsigned long mask
= OP_MASK_CODE10
;
11818 my_getExpression (&imm_expr
, s
);
11819 check_absolute_expr (ip
, &imm_expr
);
11820 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11821 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11823 mask
, (unsigned long) imm_expr
.X_add_number
);
11824 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
11825 imm_expr
.X_op
= O_absent
;
11830 case 'A': /* ins/ext position, becomes LSB. */
11839 my_getExpression (&imm_expr
, s
);
11840 check_absolute_expr (ip
, &imm_expr
);
11841 if ((unsigned long) imm_expr
.X_add_number
< limlo
11842 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11844 as_bad (_("Improper position (%lu)"),
11845 (unsigned long) imm_expr
.X_add_number
);
11846 imm_expr
.X_add_number
= limlo
;
11848 lastpos
= imm_expr
.X_add_number
;
11849 INSERT_OPERAND (mips_opts
.micromips
,
11850 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11851 imm_expr
.X_op
= O_absent
;
11855 case 'B': /* ins size, becomes MSB. */
11864 my_getExpression (&imm_expr
, s
);
11865 check_absolute_expr (ip
, &imm_expr
);
11866 /* Check for negative input so that small negative numbers
11867 will not succeed incorrectly. The checks against
11868 (pos+size) transitively check "size" itself,
11869 assuming that "pos" is reasonable. */
11870 if ((long) imm_expr
.X_add_number
< 0
11871 || ((unsigned long) imm_expr
.X_add_number
11873 || ((unsigned long) imm_expr
.X_add_number
11874 + lastpos
) > limhi
)
11876 as_bad (_("Improper insert size (%lu, position %lu)"),
11877 (unsigned long) imm_expr
.X_add_number
,
11878 (unsigned long) lastpos
);
11879 imm_expr
.X_add_number
= limlo
- lastpos
;
11881 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11882 lastpos
+ imm_expr
.X_add_number
- 1);
11883 imm_expr
.X_op
= O_absent
;
11887 case 'C': /* ext size, becomes MSBD. */
11903 my_getExpression (&imm_expr
, s
);
11904 check_absolute_expr (ip
, &imm_expr
);
11905 /* The checks against (pos+size) don't transitively check
11906 "size" itself, assuming that "pos" is reasonable.
11907 We also need to check the lower bound of "size". */
11908 if ((long) imm_expr
.X_add_number
< sizelo
11909 || ((unsigned long) imm_expr
.X_add_number
11911 || ((unsigned long) imm_expr
.X_add_number
11912 + lastpos
) > limhi
)
11914 as_bad (_("Improper extract size (%lu, position %lu)"),
11915 (unsigned long) imm_expr
.X_add_number
,
11916 (unsigned long) lastpos
);
11917 imm_expr
.X_add_number
= limlo
- lastpos
;
11919 INSERT_OPERAND (mips_opts
.micromips
,
11920 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11921 imm_expr
.X_op
= O_absent
;
11926 /* +D is for disassembly only; never match. */
11930 /* "+I" is like "I", except that imm2_expr is used. */
11931 my_getExpression (&imm2_expr
, s
);
11932 if (imm2_expr
.X_op
!= O_big
11933 && imm2_expr
.X_op
!= O_constant
)
11934 insn_error
= _("absolute expression required");
11935 if (HAVE_32BIT_GPRS
)
11936 normalize_constant_expr (&imm2_expr
);
11940 case 'T': /* Coprocessor register. */
11941 gas_assert (!mips_opts
.micromips
);
11942 /* +T is for disassembly only; never match. */
11945 case 't': /* Coprocessor register number. */
11946 gas_assert (!mips_opts
.micromips
);
11947 if (s
[0] == '$' && ISDIGIT (s
[1]))
11957 while (ISDIGIT (*s
));
11959 as_bad (_("Invalid register number (%d)"), regno
);
11962 INSERT_OPERAND (0, RT
, *ip
, regno
);
11967 as_bad (_("Invalid coprocessor 0 register number"));
11971 /* bbit[01] and bbit[01]32 bit index. Give error if index
11972 is not in the valid range. */
11973 gas_assert (!mips_opts
.micromips
);
11974 my_getExpression (&imm_expr
, s
);
11975 check_absolute_expr (ip
, &imm_expr
);
11976 if ((unsigned) imm_expr
.X_add_number
> 31)
11978 as_bad (_("Improper bit index (%lu)"),
11979 (unsigned long) imm_expr
.X_add_number
);
11980 imm_expr
.X_add_number
= 0;
11982 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11983 imm_expr
.X_op
= O_absent
;
11988 /* bbit[01] bit index when bbit is used but we generate
11989 bbit[01]32 because the index is over 32. Move to the
11990 next candidate if index is not in the valid range. */
11991 gas_assert (!mips_opts
.micromips
);
11992 my_getExpression (&imm_expr
, s
);
11993 check_absolute_expr (ip
, &imm_expr
);
11994 if ((unsigned) imm_expr
.X_add_number
< 32
11995 || (unsigned) imm_expr
.X_add_number
> 63)
11997 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
11998 imm_expr
.X_op
= O_absent
;
12003 /* cins, cins32, exts and exts32 position field. Give error
12004 if it's not in the valid range. */
12005 gas_assert (!mips_opts
.micromips
);
12006 my_getExpression (&imm_expr
, s
);
12007 check_absolute_expr (ip
, &imm_expr
);
12008 if ((unsigned) imm_expr
.X_add_number
> 31)
12010 as_bad (_("Improper position (%lu)"),
12011 (unsigned long) imm_expr
.X_add_number
);
12012 imm_expr
.X_add_number
= 0;
12014 /* Make the pos explicit to simplify +S. */
12015 lastpos
= imm_expr
.X_add_number
+ 32;
12016 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
12017 imm_expr
.X_op
= O_absent
;
12022 /* cins, cins32, exts and exts32 position field. Move to
12023 the next candidate if it's not in the valid range. */
12024 gas_assert (!mips_opts
.micromips
);
12025 my_getExpression (&imm_expr
, s
);
12026 check_absolute_expr (ip
, &imm_expr
);
12027 if ((unsigned) imm_expr
.X_add_number
< 32
12028 || (unsigned) imm_expr
.X_add_number
> 63)
12030 lastpos
= imm_expr
.X_add_number
;
12031 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
12032 imm_expr
.X_op
= O_absent
;
12037 /* cins and exts length-minus-one field. */
12038 gas_assert (!mips_opts
.micromips
);
12039 my_getExpression (&imm_expr
, s
);
12040 check_absolute_expr (ip
, &imm_expr
);
12041 if ((unsigned long) imm_expr
.X_add_number
> 31)
12043 as_bad (_("Improper size (%lu)"),
12044 (unsigned long) imm_expr
.X_add_number
);
12045 imm_expr
.X_add_number
= 0;
12047 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12048 imm_expr
.X_op
= O_absent
;
12053 /* cins32/exts32 and cins/exts aliasing cint32/exts32
12054 length-minus-one field. */
12055 gas_assert (!mips_opts
.micromips
);
12056 my_getExpression (&imm_expr
, s
);
12057 check_absolute_expr (ip
, &imm_expr
);
12058 if ((long) imm_expr
.X_add_number
< 0
12059 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
12061 as_bad (_("Improper size (%lu)"),
12062 (unsigned long) imm_expr
.X_add_number
);
12063 imm_expr
.X_add_number
= 0;
12065 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12066 imm_expr
.X_op
= O_absent
;
12071 /* seqi/snei immediate field. */
12072 gas_assert (!mips_opts
.micromips
);
12073 my_getExpression (&imm_expr
, s
);
12074 check_absolute_expr (ip
, &imm_expr
);
12075 if ((long) imm_expr
.X_add_number
< -512
12076 || (long) imm_expr
.X_add_number
>= 512)
12078 as_bad (_("Improper immediate (%ld)"),
12079 (long) imm_expr
.X_add_number
);
12080 imm_expr
.X_add_number
= 0;
12082 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
12083 imm_expr
.X_op
= O_absent
;
12087 case 'a': /* 8-bit signed offset in bit 6 */
12088 gas_assert (!mips_opts
.micromips
);
12089 my_getExpression (&imm_expr
, s
);
12090 check_absolute_expr (ip
, &imm_expr
);
12091 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
12092 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
12093 if (imm_expr
.X_add_number
< min_range
12094 || imm_expr
.X_add_number
> max_range
)
12096 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12097 (long) min_range
, (long) max_range
,
12098 (long) imm_expr
.X_add_number
);
12100 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
12101 imm_expr
.X_op
= O_absent
;
12105 case 'b': /* 8-bit signed offset in bit 3 */
12106 gas_assert (!mips_opts
.micromips
);
12107 my_getExpression (&imm_expr
, s
);
12108 check_absolute_expr (ip
, &imm_expr
);
12109 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
12110 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
12111 if (imm_expr
.X_add_number
< min_range
12112 || imm_expr
.X_add_number
> max_range
)
12114 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12115 (long) min_range
, (long) max_range
,
12116 (long) imm_expr
.X_add_number
);
12118 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
12119 imm_expr
.X_op
= O_absent
;
12123 case 'c': /* 9-bit signed offset in bit 6 */
12124 gas_assert (!mips_opts
.micromips
);
12125 my_getExpression (&imm_expr
, s
);
12126 check_absolute_expr (ip
, &imm_expr
);
12127 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
12128 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
12129 /* We check the offset range before adjusted. */
12132 if (imm_expr
.X_add_number
< min_range
12133 || imm_expr
.X_add_number
> max_range
)
12135 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12136 (long) min_range
, (long) max_range
,
12137 (long) imm_expr
.X_add_number
);
12139 if (imm_expr
.X_add_number
& 0xf)
12141 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12142 (long) imm_expr
.X_add_number
);
12144 /* Right shift 4 bits to adjust the offset operand. */
12145 INSERT_OPERAND (0, OFFSET_C
, *ip
,
12146 imm_expr
.X_add_number
>> 4);
12147 imm_expr
.X_op
= O_absent
;
12152 gas_assert (!mips_opts
.micromips
);
12153 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
12155 if (regno
== AT
&& mips_opts
.at
)
12157 if (mips_opts
.at
== ATREG
)
12158 as_warn (_("used $at without \".set noat\""));
12160 as_warn (_("used $%u with \".set at=$%u\""),
12161 regno
, mips_opts
.at
);
12163 INSERT_OPERAND (0, RZ
, *ip
, regno
);
12167 gas_assert (!mips_opts
.micromips
);
12168 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
12170 INSERT_OPERAND (0, FZ
, *ip
, regno
);
12177 /* Check whether there is only a single bracketed expression
12178 left. If so, it must be the base register and the
12179 constant must be zero. */
12180 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12183 /* If this value won't fit into the offset, then go find
12184 a macro that will generate a 16- or 32-bit offset code
12186 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
12187 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12188 || imm_expr
.X_add_number
>= 1 << shift
12189 || imm_expr
.X_add_number
< -1 << shift
))
12192 imm_expr
.X_op
= O_absent
;
12195 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, *ip
,
12196 imm_expr
.X_add_number
);
12197 imm_expr
.X_op
= O_absent
;
12203 as_bad (_("Internal error: bad %s opcode "
12204 "(unknown extension operand type `+%c'): %s %s"),
12205 mips_opts
.micromips
? "microMIPS" : "MIPS",
12206 *args
, insn
->name
, insn
->args
);
12207 /* Further processing is fruitless. */
12212 case '.': /* 10-bit offset. */
12213 gas_assert (mips_opts
.micromips
);
12214 case '~': /* 12-bit offset. */
12216 int shift
= *args
== '.' ? 9 : 11;
12219 /* Check whether there is only a single bracketed expression
12220 left. If so, it must be the base register and the
12221 constant must be zero. */
12222 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12225 /* If this value won't fit into the offset, then go find
12226 a macro that will generate a 16- or 32-bit offset code
12228 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
12229 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12230 || imm_expr
.X_add_number
>= 1 << shift
12231 || imm_expr
.X_add_number
< -1 << shift
))
12234 imm_expr
.X_op
= O_absent
;
12238 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
12240 INSERT_OPERAND (mips_opts
.micromips
,
12241 OFFSET12
, *ip
, imm_expr
.X_add_number
);
12242 imm_expr
.X_op
= O_absent
;
12247 case '<': /* must be at least one digit */
12249 * According to the manual, if the shift amount is greater
12250 * than 31 or less than 0, then the shift amount should be
12251 * mod 32. In reality the mips assembler issues an error.
12252 * We issue a warning and mask out all but the low 5 bits.
12254 my_getExpression (&imm_expr
, s
);
12255 check_absolute_expr (ip
, &imm_expr
);
12256 if ((unsigned long) imm_expr
.X_add_number
> 31)
12257 as_warn (_("Improper shift amount (%lu)"),
12258 (unsigned long) imm_expr
.X_add_number
);
12259 INSERT_OPERAND (mips_opts
.micromips
,
12260 SHAMT
, *ip
, imm_expr
.X_add_number
);
12261 imm_expr
.X_op
= O_absent
;
12265 case '>': /* shift amount minus 32 */
12266 my_getExpression (&imm_expr
, s
);
12267 check_absolute_expr (ip
, &imm_expr
);
12268 if ((unsigned long) imm_expr
.X_add_number
< 32
12269 || (unsigned long) imm_expr
.X_add_number
> 63)
12271 INSERT_OPERAND (mips_opts
.micromips
,
12272 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
12273 imm_expr
.X_op
= O_absent
;
12277 case 'k': /* CACHE code. */
12278 case 'h': /* PREFX code. */
12279 case '1': /* SYNC type. */
12280 my_getExpression (&imm_expr
, s
);
12281 check_absolute_expr (ip
, &imm_expr
);
12282 if ((unsigned long) imm_expr
.X_add_number
> 31)
12283 as_warn (_("Invalid value for `%s' (%lu)"),
12285 (unsigned long) imm_expr
.X_add_number
);
12289 if (mips_fix_cn63xxp1
12290 && !mips_opts
.micromips
12291 && strcmp ("pref", insn
->name
) == 0)
12292 switch (imm_expr
.X_add_number
)
12301 case 31: /* These are ok. */
12304 default: /* The rest must be changed to 28. */
12305 imm_expr
.X_add_number
= 28;
12308 INSERT_OPERAND (mips_opts
.micromips
,
12309 CACHE
, *ip
, imm_expr
.X_add_number
);
12312 INSERT_OPERAND (mips_opts
.micromips
,
12313 PREFX
, *ip
, imm_expr
.X_add_number
);
12316 INSERT_OPERAND (mips_opts
.micromips
,
12317 STYPE
, *ip
, imm_expr
.X_add_number
);
12320 imm_expr
.X_op
= O_absent
;
12324 case 'c': /* BREAK code. */
12326 unsigned long mask
= (mips_opts
.micromips
12327 ? MICROMIPSOP_MASK_CODE
12330 my_getExpression (&imm_expr
, s
);
12331 check_absolute_expr (ip
, &imm_expr
);
12332 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12333 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12335 mask
, (unsigned long) imm_expr
.X_add_number
);
12336 INSERT_OPERAND (mips_opts
.micromips
,
12337 CODE
, *ip
, imm_expr
.X_add_number
);
12338 imm_expr
.X_op
= O_absent
;
12343 case 'q': /* Lower BREAK code. */
12345 unsigned long mask
= (mips_opts
.micromips
12346 ? MICROMIPSOP_MASK_CODE2
12349 my_getExpression (&imm_expr
, s
);
12350 check_absolute_expr (ip
, &imm_expr
);
12351 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12352 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12354 mask
, (unsigned long) imm_expr
.X_add_number
);
12355 INSERT_OPERAND (mips_opts
.micromips
,
12356 CODE2
, *ip
, imm_expr
.X_add_number
);
12357 imm_expr
.X_op
= O_absent
;
12362 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12364 unsigned long mask
= (mips_opts
.micromips
12365 ? MICROMIPSOP_MASK_CODE10
12368 my_getExpression (&imm_expr
, s
);
12369 check_absolute_expr (ip
, &imm_expr
);
12370 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12371 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12373 mask
, (unsigned long) imm_expr
.X_add_number
);
12374 if (mips_opts
.micromips
)
12375 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
12377 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
12378 imm_expr
.X_op
= O_absent
;
12383 case 'C': /* 25- or 23-bit coprocessor code. */
12385 unsigned long mask
= (mips_opts
.micromips
12386 ? MICROMIPSOP_MASK_COPZ
12389 my_getExpression (&imm_expr
, s
);
12390 check_absolute_expr (ip
, &imm_expr
);
12391 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12392 as_warn (_("Coproccesor code > %u bits (%lu)"),
12393 mips_opts
.micromips
? 23U : 25U,
12394 (unsigned long) imm_expr
.X_add_number
);
12395 INSERT_OPERAND (mips_opts
.micromips
,
12396 COPZ
, *ip
, imm_expr
.X_add_number
);
12397 imm_expr
.X_op
= O_absent
;
12402 case 'J': /* 19-bit WAIT code. */
12403 gas_assert (!mips_opts
.micromips
);
12404 my_getExpression (&imm_expr
, s
);
12405 check_absolute_expr (ip
, &imm_expr
);
12406 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
12408 as_warn (_("Illegal 19-bit code (%lu)"),
12409 (unsigned long) imm_expr
.X_add_number
);
12410 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
12412 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
12413 imm_expr
.X_op
= O_absent
;
12417 case 'P': /* Performance register. */
12418 gas_assert (!mips_opts
.micromips
);
12419 my_getExpression (&imm_expr
, s
);
12420 check_absolute_expr (ip
, &imm_expr
);
12421 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
12422 as_warn (_("Invalid performance register (%lu)"),
12423 (unsigned long) imm_expr
.X_add_number
);
12424 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
12425 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
12426 as_warn (_("Invalid performance register (%lu)"),
12427 (unsigned long) imm_expr
.X_add_number
);
12428 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
12429 imm_expr
.X_op
= O_absent
;
12433 case 'G': /* Coprocessor destination register. */
12435 unsigned long opcode
= ip
->insn_opcode
;
12436 unsigned long mask
;
12437 unsigned int types
;
12440 if (mips_opts
.micromips
)
12442 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
12443 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
12444 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
12448 case 0x000000fc: /* mfc0 */
12449 case 0x000002fc: /* mtc0 */
12450 case 0x580000fc: /* dmfc0 */
12451 case 0x580002fc: /* dmtc0 */
12461 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
12462 cop0
= opcode
== OP_OP_COP0
;
12464 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
12465 ok
= reg_lookup (&s
, types
, ®no
);
12466 if (mips_opts
.micromips
)
12467 INSERT_OPERAND (1, RS
, *ip
, regno
);
12469 INSERT_OPERAND (0, RD
, *ip
, regno
);
12478 case 'y': /* ALNV.PS source register. */
12479 gas_assert (mips_opts
.micromips
);
12481 case 'x': /* Ignore register name. */
12482 case 'U': /* Destination register (CLO/CLZ). */
12483 case 'g': /* Coprocessor destination register. */
12484 gas_assert (!mips_opts
.micromips
);
12485 case 'b': /* Base register. */
12486 case 'd': /* Destination register. */
12487 case 's': /* Source register. */
12488 case 't': /* Target register. */
12489 case 'r': /* Both target and source. */
12490 case 'v': /* Both dest and source. */
12491 case 'w': /* Both dest and target. */
12492 case 'E': /* Coprocessor target register. */
12493 case 'K': /* RDHWR destination register. */
12494 case 'z': /* Must be zero register. */
12497 if (*args
== 'E' || *args
== 'K')
12498 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12501 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12502 if (regno
== AT
&& mips_opts
.at
)
12504 if (mips_opts
.at
== ATREG
)
12505 as_warn (_("Used $at without \".set noat\""));
12507 as_warn (_("Used $%u with \".set at=$%u\""),
12508 regno
, mips_opts
.at
);
12518 if (c
== 'r' || c
== 'v' || c
== 'w')
12525 /* 'z' only matches $0. */
12526 if (c
== 'z' && regno
!= 0)
12529 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12531 if (regno
== lastregno
)
12534 = _("Source and destination must be different");
12537 if (regno
== 31 && lastregno
== 0xffffffff)
12540 = _("A destination register must be supplied");
12544 /* Now that we have assembled one operand, we use the args
12545 string to figure out where it goes in the instruction. */
12552 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12556 if (mips_opts
.micromips
)
12557 INSERT_OPERAND (1, RS
, *ip
, regno
);
12559 INSERT_OPERAND (0, RD
, *ip
, regno
);
12564 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12568 gas_assert (!mips_opts
.micromips
);
12569 INSERT_OPERAND (0, RD
, *ip
, regno
);
12570 INSERT_OPERAND (0, RT
, *ip
, regno
);
12576 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12580 gas_assert (mips_opts
.micromips
);
12581 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12585 /* This case exists because on the r3000 trunc
12586 expands into a macro which requires a gp
12587 register. On the r6000 or r4000 it is
12588 assembled into a single instruction which
12589 ignores the register. Thus the insn version
12590 is MIPS_ISA2 and uses 'x', and the macro
12591 version is MIPS_ISA1 and uses 't'. */
12595 /* This case is for the div instruction, which
12596 acts differently if the destination argument
12597 is $0. This only matches $0, and is checked
12598 outside the switch. */
12608 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12612 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12617 case 'O': /* MDMX alignment immediate constant. */
12618 gas_assert (!mips_opts
.micromips
);
12619 my_getExpression (&imm_expr
, s
);
12620 check_absolute_expr (ip
, &imm_expr
);
12621 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12622 as_warn (_("Improper align amount (%ld), using low bits"),
12623 (long) imm_expr
.X_add_number
);
12624 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12625 imm_expr
.X_op
= O_absent
;
12629 case 'Q': /* MDMX vector, element sel, or const. */
12632 /* MDMX Immediate. */
12633 gas_assert (!mips_opts
.micromips
);
12634 my_getExpression (&imm_expr
, s
);
12635 check_absolute_expr (ip
, &imm_expr
);
12636 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12637 as_warn (_("Invalid MDMX Immediate (%ld)"),
12638 (long) imm_expr
.X_add_number
);
12639 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12640 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12641 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12643 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12644 imm_expr
.X_op
= O_absent
;
12648 /* Not MDMX Immediate. Fall through. */
12649 case 'X': /* MDMX destination register. */
12650 case 'Y': /* MDMX source register. */
12651 case 'Z': /* MDMX target register. */
12654 gas_assert (!mips_opts
.micromips
);
12655 case 'D': /* Floating point destination register. */
12656 case 'S': /* Floating point source register. */
12657 case 'T': /* Floating point target register. */
12658 case 'R': /* Floating point source register. */
12662 || ((mips_opts
.ase
& ASE_MDMX
)
12663 && (ip
->insn_mo
->pinfo
& FP_D
)
12664 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12665 | INSN_COPROC_MEMORY_DELAY
12666 | INSN_LOAD_COPROC_DELAY
12667 | INSN_LOAD_MEMORY_DELAY
12668 | INSN_STORE_MEMORY
))))
12669 rtype
|= RTYPE_VEC
;
12671 if (reg_lookup (&s
, rtype
, ®no
))
12673 if ((regno
& 1) != 0
12675 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12676 as_warn (_("Float register should be even, was %d"),
12684 if (c
== 'V' || c
== 'W')
12695 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12701 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12705 /* This is like 'Z', but also needs to fix the MDMX
12706 vector/scalar select bits. Note that the
12707 scalar immediate case is handled above. */
12710 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12711 int max_el
= (is_qh
? 3 : 7);
12713 my_getExpression(&imm_expr
, s
);
12714 check_absolute_expr (ip
, &imm_expr
);
12716 if (imm_expr
.X_add_number
> max_el
)
12717 as_bad (_("Bad element selector %ld"),
12718 (long) imm_expr
.X_add_number
);
12719 imm_expr
.X_add_number
&= max_el
;
12720 ip
->insn_opcode
|= (imm_expr
.X_add_number
12723 imm_expr
.X_op
= O_absent
;
12725 as_warn (_("Expecting ']' found '%s'"), s
);
12731 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12732 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12735 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12738 /* Fall through. */
12742 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12746 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12756 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12760 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12766 my_getExpression (&imm_expr
, s
);
12767 if (imm_expr
.X_op
!= O_big
12768 && imm_expr
.X_op
!= O_constant
)
12769 insn_error
= _("absolute expression required");
12770 if (HAVE_32BIT_GPRS
)
12771 normalize_constant_expr (&imm_expr
);
12776 my_getExpression (&offset_expr
, s
);
12777 normalize_address_expr (&offset_expr
);
12778 *imm_reloc
= BFD_RELOC_32
;
12791 unsigned char temp
[8];
12793 unsigned int length
;
12798 /* These only appear as the last operand in an
12799 instruction, and every instruction that accepts
12800 them in any variant accepts them in all variants.
12801 This means we don't have to worry about backing out
12802 any changes if the instruction does not match.
12804 The difference between them is the size of the
12805 floating point constant and where it goes. For 'F'
12806 and 'L' the constant is 64 bits; for 'f' and 'l' it
12807 is 32 bits. Where the constant is placed is based
12808 on how the MIPS assembler does things:
12811 f -- immediate value
12814 The .lit4 and .lit8 sections are only used if
12815 permitted by the -G argument.
12817 The code below needs to know whether the target register
12818 is 32 or 64 bits wide. It relies on the fact 'f' and
12819 'F' are used with GPR-based instructions and 'l' and
12820 'L' are used with FPR-based instructions. */
12822 f64
= *args
== 'F' || *args
== 'L';
12823 using_gprs
= *args
== 'F' || *args
== 'f';
12825 save_in
= input_line_pointer
;
12826 input_line_pointer
= s
;
12827 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12829 s
= input_line_pointer
;
12830 input_line_pointer
= save_in
;
12831 if (err
!= NULL
&& *err
!= '\0')
12833 as_bad (_("Bad floating point constant: %s"), err
);
12834 memset (temp
, '\0', sizeof temp
);
12835 length
= f64
? 8 : 4;
12838 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12842 && (g_switch_value
< 4
12843 || (temp
[0] == 0 && temp
[1] == 0)
12844 || (temp
[2] == 0 && temp
[3] == 0))))
12846 imm_expr
.X_op
= O_constant
;
12847 if (!target_big_endian
)
12848 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12850 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12852 else if (length
> 4
12853 && !mips_disable_float_construction
12854 /* Constants can only be constructed in GPRs and
12855 copied to FPRs if the GPRs are at least as wide
12856 as the FPRs. Force the constant into memory if
12857 we are using 64-bit FPRs but the GPRs are only
12860 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12861 && ((temp
[0] == 0 && temp
[1] == 0)
12862 || (temp
[2] == 0 && temp
[3] == 0))
12863 && ((temp
[4] == 0 && temp
[5] == 0)
12864 || (temp
[6] == 0 && temp
[7] == 0)))
12866 /* The value is simple enough to load with a couple of
12867 instructions. If using 32-bit registers, set
12868 imm_expr to the high order 32 bits and offset_expr to
12869 the low order 32 bits. Otherwise, set imm_expr to
12870 the entire 64 bit constant. */
12871 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12873 imm_expr
.X_op
= O_constant
;
12874 offset_expr
.X_op
= O_constant
;
12875 if (!target_big_endian
)
12877 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12878 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12882 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12883 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12885 if (offset_expr
.X_add_number
== 0)
12886 offset_expr
.X_op
= O_absent
;
12888 else if (sizeof (imm_expr
.X_add_number
) > 4)
12890 imm_expr
.X_op
= O_constant
;
12891 if (!target_big_endian
)
12892 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12894 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12898 imm_expr
.X_op
= O_big
;
12899 imm_expr
.X_add_number
= 4;
12900 if (!target_big_endian
)
12902 generic_bignum
[0] = bfd_getl16 (temp
);
12903 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
12904 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
12905 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
12909 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
12910 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
12911 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
12912 generic_bignum
[3] = bfd_getb16 (temp
);
12918 const char *newname
;
12921 /* Switch to the right section. */
12923 subseg
= now_subseg
;
12926 default: /* unused default case avoids warnings. */
12928 newname
= RDATA_SECTION_NAME
;
12929 if (g_switch_value
>= 8)
12933 newname
= RDATA_SECTION_NAME
;
12936 gas_assert (g_switch_value
>= 4);
12940 new_seg
= subseg_new (newname
, (subsegT
) 0);
12942 bfd_set_section_flags (stdoutput
, new_seg
,
12947 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12948 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
12949 record_alignment (new_seg
, 4);
12951 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12952 if (seg
== now_seg
)
12953 as_bad (_("Can't use floating point insn in this section"));
12955 /* Set the argument to the current address in the
12957 offset_expr
.X_op
= O_symbol
;
12958 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12959 offset_expr
.X_add_number
= 0;
12961 /* Put the floating point number into the section. */
12962 p
= frag_more ((int) length
);
12963 memcpy (p
, temp
, length
);
12965 /* Switch back to the original section. */
12966 subseg_set (seg
, subseg
);
12971 case 'i': /* 16-bit unsigned immediate. */
12972 case 'j': /* 16-bit signed immediate. */
12973 *imm_reloc
= BFD_RELOC_LO16
;
12974 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12977 offsetT minval
, maxval
;
12979 more
= (insn
+ 1 < past
12980 && strcmp (insn
->name
, insn
[1].name
) == 0);
12982 /* If the expression was written as an unsigned number,
12983 only treat it as signed if there are no more
12987 && sizeof (imm_expr
.X_add_number
) <= 4
12988 && imm_expr
.X_op
== O_constant
12989 && imm_expr
.X_add_number
< 0
12990 && imm_expr
.X_unsigned
12991 && HAVE_64BIT_GPRS
)
12994 /* For compatibility with older assemblers, we accept
12995 0x8000-0xffff as signed 16-bit numbers when only
12996 signed numbers are allowed. */
12998 minval
= 0, maxval
= 0xffff;
13000 minval
= -0x8000, maxval
= 0x7fff;
13002 minval
= -0x8000, maxval
= 0xffff;
13004 if (imm_expr
.X_op
!= O_constant
13005 || imm_expr
.X_add_number
< minval
13006 || imm_expr
.X_add_number
> maxval
)
13010 if (imm_expr
.X_op
== O_constant
13011 || imm_expr
.X_op
== O_big
)
13012 as_bad (_("Expression out of range"));
13018 case 'o': /* 16-bit offset. */
13019 offset_reloc
[0] = BFD_RELOC_LO16
;
13020 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13021 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13023 /* Check whether there is only a single bracketed expression
13024 left. If so, it must be the base register and the
13025 constant must be zero. */
13026 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13028 offset_expr
.X_op
= O_constant
;
13029 offset_expr
.X_add_number
= 0;
13033 /* If this value won't fit into a 16 bit offset, then go
13034 find a macro that will generate the 32 bit offset
13036 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
13037 && (offset_expr
.X_op
!= O_constant
13038 || offset_expr
.X_add_number
>= 0x8000
13039 || offset_expr
.X_add_number
< -0x8000))
13045 case 'p': /* PC-relative offset. */
13046 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
13047 my_getExpression (&offset_expr
, s
);
13051 case 'u': /* Upper 16 bits. */
13052 *imm_reloc
= BFD_RELOC_LO16
;
13053 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
13054 && imm_expr
.X_op
== O_constant
13055 && (imm_expr
.X_add_number
< 0
13056 || imm_expr
.X_add_number
>= 0x10000))
13057 as_bad (_("lui expression (%lu) not in range 0..65535"),
13058 (unsigned long) imm_expr
.X_add_number
);
13062 case 'a': /* 26-bit address. */
13063 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
13064 my_getExpression (&offset_expr
, s
);
13068 case 'N': /* 3-bit branch condition code. */
13069 case 'M': /* 3-bit compare condition code. */
13071 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
13072 rtype
|= RTYPE_FCC
;
13073 if (!reg_lookup (&s
, rtype
, ®no
))
13075 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
13076 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
13077 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
13078 && (regno
& 1) != 0)
13079 as_warn (_("Condition code register should be even for %s, "
13082 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
13083 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
13084 && (regno
& 3) != 0)
13085 as_warn (_("Condition code register should be 0 or 4 for %s, "
13089 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
13091 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
13095 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
13106 while (ISDIGIT (*s
));
13109 c
= 8; /* Invalid sel value. */
13112 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13113 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
13117 gas_assert (!mips_opts
.micromips
);
13118 /* Must be at least one digit. */
13119 my_getExpression (&imm_expr
, s
);
13120 check_absolute_expr (ip
, &imm_expr
);
13122 if ((unsigned long) imm_expr
.X_add_number
13123 > (unsigned long) OP_MASK_VECBYTE
)
13125 as_bad (_("bad byte vector index (%ld)"),
13126 (long) imm_expr
.X_add_number
);
13127 imm_expr
.X_add_number
= 0;
13130 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
13131 imm_expr
.X_op
= O_absent
;
13136 gas_assert (!mips_opts
.micromips
);
13137 my_getExpression (&imm_expr
, s
);
13138 check_absolute_expr (ip
, &imm_expr
);
13140 if ((unsigned long) imm_expr
.X_add_number
13141 > (unsigned long) OP_MASK_VECALIGN
)
13143 as_bad (_("bad byte vector index (%ld)"),
13144 (long) imm_expr
.X_add_number
);
13145 imm_expr
.X_add_number
= 0;
13148 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
13149 imm_expr
.X_op
= O_absent
;
13153 case 'm': /* Opcode extension character. */
13154 gas_assert (mips_opts
.micromips
);
13159 if (strncmp (s
, "$pc", 3) == 0)
13187 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
13188 if (regno
== AT
&& mips_opts
.at
)
13190 if (mips_opts
.at
== ATREG
)
13191 as_warn (_("Used $at without \".set noat\""));
13193 as_warn (_("Used $%u with \".set at=$%u\""),
13194 regno
, mips_opts
.at
);
13200 gas_assert (args
[1] == ',');
13206 gas_assert (args
[1] == ',');
13208 continue; /* Nothing to do. */
13214 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
13216 if (regno
== lastregno
)
13219 = _("Source and destination must be different");
13222 if (regno
== 31 && lastregno
== 0xffffffff)
13225 = _("A destination register must be supplied");
13236 gas_assert (args
[1] == ',');
13243 gas_assert (args
[1] == ',');
13246 continue; /* Nothing to do. */
13250 /* Make sure regno is the same as lastregno. */
13251 if (c
== 't' && regno
!= lastregno
)
13254 /* Make sure regno is the same as destregno. */
13255 if (c
== 'x' && regno
!= destregno
)
13258 /* We need to save regno, before regno maps to the
13259 microMIPS register encoding. */
13269 regno
= ILLEGAL_REG
;
13273 regno
= mips32_to_micromips_reg_b_map
[regno
];
13277 regno
= mips32_to_micromips_reg_c_map
[regno
];
13281 regno
= mips32_to_micromips_reg_d_map
[regno
];
13285 regno
= mips32_to_micromips_reg_e_map
[regno
];
13289 regno
= mips32_to_micromips_reg_f_map
[regno
];
13293 regno
= mips32_to_micromips_reg_g_map
[regno
];
13297 regno
= mips32_to_micromips_reg_h_map
[regno
];
13301 switch (EXTRACT_OPERAND (1, MI
, *ip
))
13306 else if (regno
== 22)
13308 else if (regno
== 5)
13310 else if (regno
== 6)
13312 else if (regno
== 7)
13315 regno
= ILLEGAL_REG
;
13321 else if (regno
== 7)
13324 regno
= ILLEGAL_REG
;
13331 regno
= ILLEGAL_REG
;
13335 regno
= ILLEGAL_REG
;
13341 regno
= mips32_to_micromips_reg_l_map
[regno
];
13345 regno
= mips32_to_micromips_reg_m_map
[regno
];
13349 regno
= mips32_to_micromips_reg_n_map
[regno
];
13353 regno
= mips32_to_micromips_reg_q_map
[regno
];
13358 regno
= ILLEGAL_REG
;
13363 regno
= ILLEGAL_REG
;
13368 regno
= ILLEGAL_REG
;
13371 case 'j': /* Do nothing. */
13381 if (regno
== ILLEGAL_REG
)
13387 INSERT_OPERAND (1, MB
, *ip
, regno
);
13391 INSERT_OPERAND (1, MC
, *ip
, regno
);
13395 INSERT_OPERAND (1, MD
, *ip
, regno
);
13399 INSERT_OPERAND (1, ME
, *ip
, regno
);
13403 INSERT_OPERAND (1, MF
, *ip
, regno
);
13407 INSERT_OPERAND (1, MG
, *ip
, regno
);
13411 INSERT_OPERAND (1, MH
, *ip
, regno
);
13415 INSERT_OPERAND (1, MI
, *ip
, regno
);
13419 INSERT_OPERAND (1, MJ
, *ip
, regno
);
13423 INSERT_OPERAND (1, ML
, *ip
, regno
);
13427 INSERT_OPERAND (1, MM
, *ip
, regno
);
13431 INSERT_OPERAND (1, MN
, *ip
, regno
);
13435 INSERT_OPERAND (1, MP
, *ip
, regno
);
13439 INSERT_OPERAND (1, MQ
, *ip
, regno
);
13442 case 'a': /* Do nothing. */
13443 case 's': /* Do nothing. */
13444 case 't': /* Do nothing. */
13445 case 'x': /* Do nothing. */
13446 case 'y': /* Do nothing. */
13447 case 'z': /* Do nothing. */
13457 bfd_reloc_code_real_type r
[3];
13461 /* Check whether there is only a single bracketed
13462 expression left. If so, it must be the base register
13463 and the constant must be zero. */
13464 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13466 INSERT_OPERAND (1, IMMA
, *ip
, 0);
13470 if (my_getSmallExpression (&ep
, r
, s
) > 0
13471 || !expr_const_in_range (&ep
, -64, 64, 2))
13474 imm
= ep
.X_add_number
>> 2;
13475 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13482 bfd_reloc_code_real_type r
[3];
13486 if (my_getSmallExpression (&ep
, r
, s
) > 0
13487 || ep
.X_op
!= O_constant
)
13490 for (imm
= 0; imm
< 8; imm
++)
13491 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13496 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13503 bfd_reloc_code_real_type r
[3];
13507 if (my_getSmallExpression (&ep
, r
, s
) > 0
13508 || ep
.X_op
!= O_constant
)
13511 for (imm
= 0; imm
< 16; imm
++)
13512 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13517 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13522 case 'D': /* pc relative offset */
13523 case 'E': /* pc relative offset */
13524 my_getExpression (&offset_expr
, s
);
13525 if (offset_expr
.X_op
== O_register
)
13528 if (!forced_insn_length
)
13529 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13531 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13533 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13539 bfd_reloc_code_real_type r
[3];
13543 if (my_getSmallExpression (&ep
, r
, s
) > 0
13544 || !expr_const_in_range (&ep
, 0, 16, 0))
13547 imm
= ep
.X_add_number
;
13548 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13555 bfd_reloc_code_real_type r
[3];
13559 /* Check whether there is only a single bracketed
13560 expression left. If so, it must be the base register
13561 and the constant must be zero. */
13562 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13564 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13568 if (my_getSmallExpression (&ep
, r
, s
) > 0
13569 || !expr_const_in_range (&ep
, -1, 15, 0))
13572 imm
= ep
.X_add_number
& 15;
13573 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13580 bfd_reloc_code_real_type r
[3];
13584 /* Check whether there is only a single bracketed
13585 expression left. If so, it must be the base register
13586 and the constant must be zero. */
13587 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13589 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13593 if (my_getSmallExpression (&ep
, r
, s
) > 0
13594 || !expr_const_in_range (&ep
, 0, 16, 1))
13597 imm
= ep
.X_add_number
>> 1;
13598 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13605 bfd_reloc_code_real_type r
[3];
13609 if (my_getSmallExpression (&ep
, r
, s
) > 0
13610 || !expr_const_in_range (&ep
, -1, 127, 0))
13613 imm
= ep
.X_add_number
& 127;
13614 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13621 bfd_reloc_code_real_type r
[3];
13625 /* Check whether there is only a single bracketed
13626 expression left. If so, it must be the base register
13627 and the constant must be zero. */
13628 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13630 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13634 if (my_getSmallExpression (&ep
, r
, s
) > 0
13635 || !expr_const_in_range (&ep
, 0, 16, 2))
13638 imm
= ep
.X_add_number
>> 2;
13639 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13646 bfd_reloc_code_real_type r
[3];
13650 /* Check whether there is only a single bracketed
13651 expression left. If so, it must be the base register
13652 and the constant must be zero. */
13653 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13655 INSERT_OPERAND (1, IMML
, *ip
, 0);
13659 if (my_getSmallExpression (&ep
, r
, s
) > 0
13660 || !expr_const_in_range (&ep
, 0, 16, 0))
13663 imm
= ep
.X_add_number
;
13664 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13671 bfd_reloc_code_real_type r
[3];
13675 if (my_getSmallExpression (&ep
, r
, s
) > 0
13676 || !expr_const_in_range (&ep
, 1, 9, 0))
13679 imm
= ep
.X_add_number
& 7;
13680 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13685 case 'N': /* Register list for lwm and swm. */
13687 /* A comma-separated list of registers and/or
13688 dash-separated contiguous ranges including
13689 both ra and a set of one or more registers
13690 starting at s0 up to s3 which have to be
13697 and any permutations of these. */
13698 unsigned int reglist
;
13701 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13704 if ((reglist
& 0xfff1ffff) != 0x80010000)
13707 reglist
= (reglist
>> 17) & 7;
13709 if ((reglist
& -reglist
) != reglist
)
13712 imm
= ffs (reglist
) - 1;
13713 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13717 case 'O': /* sdbbp 4-bit code. */
13719 bfd_reloc_code_real_type r
[3];
13723 if (my_getSmallExpression (&ep
, r
, s
) > 0
13724 || !expr_const_in_range (&ep
, 0, 16, 0))
13727 imm
= ep
.X_add_number
;
13728 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13735 bfd_reloc_code_real_type r
[3];
13739 if (my_getSmallExpression (&ep
, r
, s
) > 0
13740 || !expr_const_in_range (&ep
, 0, 32, 2))
13743 imm
= ep
.X_add_number
>> 2;
13744 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13751 bfd_reloc_code_real_type r
[3];
13755 if (my_getSmallExpression (&ep
, r
, s
) > 0
13756 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13759 imm
= ep
.X_add_number
>> 2;
13760 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13767 bfd_reloc_code_real_type r
[3];
13771 /* Check whether there is only a single bracketed
13772 expression left. If so, it must be the base register
13773 and the constant must be zero. */
13774 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13776 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13780 if (my_getSmallExpression (&ep
, r
, s
) > 0
13781 || !expr_const_in_range (&ep
, 0, 32, 2))
13784 imm
= ep
.X_add_number
>> 2;
13785 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13792 bfd_reloc_code_real_type r
[3];
13796 if (my_getSmallExpression (&ep
, r
, s
) > 0
13797 || !expr_const_in_range (&ep
, 0, 64, 2))
13800 imm
= ep
.X_add_number
>> 2;
13801 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13808 bfd_reloc_code_real_type r
[3];
13812 if (my_getSmallExpression (&ep
, r
, s
) > 0
13813 || !expr_const_in_range (&ep
, -8, 8, 0))
13816 imm
= ep
.X_add_number
;
13817 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13824 bfd_reloc_code_real_type r
[3];
13828 if (my_getSmallExpression (&ep
, r
, s
) > 0
13829 || expr_const_in_range (&ep
, -2, 2, 2)
13830 || !expr_const_in_range (&ep
, -258, 258, 2))
13833 imm
= ep
.X_add_number
>> 2;
13834 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13835 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13842 bfd_reloc_code_real_type r
[3];
13845 if (my_getSmallExpression (&ep
, r
, s
) > 0
13846 || !expr_const_in_range (&ep
, 0, 1, 0))
13853 as_bad (_("Internal error: bad microMIPS opcode "
13854 "(unknown extension operand type `m%c'): %s %s"),
13855 *args
, insn
->name
, insn
->args
);
13856 /* Further processing is fruitless. */
13861 case 'n': /* Register list for 32-bit lwm and swm. */
13862 gas_assert (mips_opts
.micromips
);
13864 /* A comma-separated list of registers and/or
13865 dash-separated contiguous ranges including
13866 at least one of ra and a set of one or more
13867 registers starting at s0 up to s7 and then
13868 s8 which have to be consecutive, e.g.:
13876 and any permutations of these. */
13877 unsigned int reglist
;
13881 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13884 if ((reglist
& 0x3f00ffff) != 0)
13887 ra
= (reglist
>> 27) & 0x10;
13888 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13890 if ((reglist
& -reglist
) != reglist
)
13893 imm
= (ffs (reglist
) - 1) | ra
;
13894 INSERT_OPERAND (1, RT
, *ip
, imm
);
13895 imm_expr
.X_op
= O_absent
;
13899 case '|': /* 4-bit trap code. */
13900 gas_assert (mips_opts
.micromips
);
13901 my_getExpression (&imm_expr
, s
);
13902 check_absolute_expr (ip
, &imm_expr
);
13903 if ((unsigned long) imm_expr
.X_add_number
13904 > MICROMIPSOP_MASK_TRAP
)
13905 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13906 (unsigned long) imm_expr
.X_add_number
,
13907 ip
->insn_mo
->name
);
13908 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13909 imm_expr
.X_op
= O_absent
;
13914 as_bad (_("Bad char = '%c'\n"), *args
);
13919 /* Args don't match. */
13921 insn_error
= _("Illegal operands");
13922 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13927 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13929 gas_assert (firstinsn
);
13930 need_delay_slot_ok
= FALSE
;
13939 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13941 /* This routine assembles an instruction into its binary format when
13942 assembling for the mips16. As a side effect, it sets one of the
13943 global variables imm_reloc or offset_reloc to the type of relocation
13944 to do if one of the operands is an address expression. It also sets
13945 forced_insn_length to the resulting instruction size in bytes if the
13946 user explicitly requested a small or extended instruction. */
13949 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13953 struct mips_opcode
*insn
;
13955 unsigned int regno
;
13956 unsigned int lastregno
= 0;
13962 forced_insn_length
= 0;
13964 for (s
= str
; ISLOWER (*s
); ++s
)
13976 if (s
[1] == 't' && s
[2] == ' ')
13979 forced_insn_length
= 2;
13983 else if (s
[1] == 'e' && s
[2] == ' ')
13986 forced_insn_length
= 4;
13990 /* Fall through. */
13992 insn_error
= _("unknown opcode");
13996 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13997 forced_insn_length
= 2;
13999 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
14001 insn_error
= _("unrecognized opcode");
14010 gas_assert (strcmp (insn
->name
, str
) == 0);
14012 ok
= is_opcode_valid_16 (insn
);
14015 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
14016 && strcmp (insn
->name
, insn
[1].name
) == 0)
14025 static char buf
[100];
14027 _("Opcode not supported on this processor: %s (%s)"),
14028 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
14029 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14036 create_insn (ip
, insn
);
14037 imm_expr
.X_op
= O_absent
;
14038 imm_reloc
[0] = BFD_RELOC_UNUSED
;
14039 imm_reloc
[1] = BFD_RELOC_UNUSED
;
14040 imm_reloc
[2] = BFD_RELOC_UNUSED
;
14041 imm2_expr
.X_op
= O_absent
;
14042 offset_expr
.X_op
= O_absent
;
14043 offset_reloc
[0] = BFD_RELOC_UNUSED
;
14044 offset_reloc
[1] = BFD_RELOC_UNUSED
;
14045 offset_reloc
[2] = BFD_RELOC_UNUSED
;
14046 for (args
= insn
->args
; 1; ++args
)
14053 /* In this switch statement we call break if we did not find
14054 a match, continue if we did find a match, or return if we
14065 /* Stuff the immediate value in now, if we can. */
14066 if (imm_expr
.X_op
== O_constant
14067 && *imm_reloc
> BFD_RELOC_UNUSED
14068 && insn
->pinfo
!= INSN_MACRO
14069 && calculate_reloc (*offset_reloc
,
14070 imm_expr
.X_add_number
, &value
))
14072 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
14073 *offset_reloc
, value
, forced_insn_length
,
14075 imm_expr
.X_op
= O_absent
;
14076 *imm_reloc
= BFD_RELOC_UNUSED
;
14077 *offset_reloc
= BFD_RELOC_UNUSED
;
14091 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14094 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14110 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14112 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14116 /* Fall through. */
14127 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
14129 if (c
== 'v' || c
== 'w')
14132 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14134 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14145 if (c
== 'v' || c
== 'w')
14147 regno
= mips16_to_32_reg_map
[lastregno
];
14161 regno
= mips32_to_16_reg_map
[regno
];
14166 regno
= ILLEGAL_REG
;
14171 regno
= ILLEGAL_REG
;
14176 regno
= ILLEGAL_REG
;
14181 if (regno
== AT
&& mips_opts
.at
)
14183 if (mips_opts
.at
== ATREG
)
14184 as_warn (_("used $at without \".set noat\""));
14186 as_warn (_("used $%u with \".set at=$%u\""),
14187 regno
, mips_opts
.at
);
14195 if (regno
== ILLEGAL_REG
)
14202 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
14206 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
14209 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
14212 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
14218 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
14221 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
14222 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
14232 if (strncmp (s
, "$pc", 3) == 0)
14249 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
14252 if (imm_expr
.X_op
!= O_constant
)
14254 forced_insn_length
= 4;
14255 ip
->insn_opcode
|= MIPS16_EXTEND
;
14259 /* We need to relax this instruction. */
14260 *offset_reloc
= *imm_reloc
;
14261 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14266 *imm_reloc
= BFD_RELOC_UNUSED
;
14267 /* Fall through. */
14274 my_getExpression (&imm_expr
, s
);
14275 if (imm_expr
.X_op
== O_register
)
14277 /* What we thought was an expression turned out to
14280 if (s
[0] == '(' && args
[1] == '(')
14282 /* It looks like the expression was omitted
14283 before a register indirection, which means
14284 that the expression is implicitly zero. We
14285 still set up imm_expr, so that we handle
14286 explicit extensions correctly. */
14287 imm_expr
.X_op
= O_constant
;
14288 imm_expr
.X_add_number
= 0;
14289 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14296 /* We need to relax this instruction. */
14297 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14306 /* We use offset_reloc rather than imm_reloc for the PC
14307 relative operands. This lets macros with both
14308 immediate and address operands work correctly. */
14309 my_getExpression (&offset_expr
, s
);
14311 if (offset_expr
.X_op
== O_register
)
14314 /* We need to relax this instruction. */
14315 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14319 case '6': /* break code */
14320 my_getExpression (&imm_expr
, s
);
14321 check_absolute_expr (ip
, &imm_expr
);
14322 if ((unsigned long) imm_expr
.X_add_number
> 63)
14323 as_warn (_("Invalid value for `%s' (%lu)"),
14325 (unsigned long) imm_expr
.X_add_number
);
14326 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
14327 imm_expr
.X_op
= O_absent
;
14331 case 'a': /* 26 bit address */
14332 my_getExpression (&offset_expr
, s
);
14334 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
14335 ip
->insn_opcode
<<= 16;
14338 case 'l': /* register list for entry macro */
14339 case 'L': /* register list for exit macro */
14349 unsigned int freg
, reg1
, reg2
;
14351 while (*s
== ' ' || *s
== ',')
14353 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14355 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
14359 as_bad (_("can't parse register list"));
14369 if (!reg_lookup (&s
, freg
? RTYPE_FPU
14370 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
14372 as_bad (_("invalid register list"));
14376 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
14378 mask
&= ~ (7 << 3);
14381 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
14383 mask
&= ~ (7 << 3);
14386 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
14387 mask
|= (reg2
- 3) << 3;
14388 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
14389 mask
|= (reg2
- 15) << 1;
14390 else if (reg1
== RA
&& reg2
== RA
)
14394 as_bad (_("invalid register list"));
14398 /* The mask is filled in in the opcode table for the
14399 benefit of the disassembler. We remove it before
14400 applying the actual mask. */
14401 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
14402 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
14406 case 'm': /* Register list for save insn. */
14407 case 'M': /* Register list for restore insn. */
14409 int opcode
= ip
->insn_opcode
;
14410 int framesz
= 0, seen_framesz
= 0;
14411 int nargs
= 0, statics
= 0, sregs
= 0;
14415 unsigned int reg1
, reg2
;
14417 SKIP_SPACE_TABS (s
);
14420 SKIP_SPACE_TABS (s
);
14422 my_getExpression (&imm_expr
, s
);
14423 if (imm_expr
.X_op
== O_constant
)
14425 /* Handle the frame size. */
14428 as_bad (_("more than one frame size in list"));
14432 framesz
= imm_expr
.X_add_number
;
14433 imm_expr
.X_op
= O_absent
;
14438 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14440 as_bad (_("can't parse register list"));
14452 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
14455 as_bad (_("can't parse register list"));
14460 while (reg1
<= reg2
)
14462 if (reg1
>= 4 && reg1
<= 7)
14466 nargs
|= 1 << (reg1
- 4);
14468 /* statics $a0-$a3 */
14469 statics
|= 1 << (reg1
- 4);
14471 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
14474 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
14476 else if (reg1
== 31)
14478 /* Add $ra to insn. */
14483 as_bad (_("unexpected register in list"));
14491 /* Encode args/statics combination. */
14492 if (nargs
& statics
)
14493 as_bad (_("arg/static registers overlap"));
14494 else if (nargs
== 0xf)
14495 /* All $a0-$a3 are args. */
14496 opcode
|= MIPS16_ALL_ARGS
<< 16;
14497 else if (statics
== 0xf)
14498 /* All $a0-$a3 are statics. */
14499 opcode
|= MIPS16_ALL_STATICS
<< 16;
14502 int narg
= 0, nstat
= 0;
14504 /* Count arg registers. */
14505 while (nargs
& 0x1)
14511 as_bad (_("invalid arg register list"));
14513 /* Count static registers. */
14514 while (statics
& 0x8)
14516 statics
= (statics
<< 1) & 0xf;
14520 as_bad (_("invalid static register list"));
14522 /* Encode args/statics. */
14523 opcode
|= ((narg
<< 2) | nstat
) << 16;
14526 /* Encode $s0/$s1. */
14527 if (sregs
& (1 << 0)) /* $s0 */
14529 if (sregs
& (1 << 1)) /* $s1 */
14535 /* Count regs $s2-$s8. */
14543 as_bad (_("invalid static register list"));
14544 /* Encode $s2-$s8. */
14545 opcode
|= nsreg
<< 24;
14548 /* Encode frame size. */
14550 as_bad (_("missing frame size"));
14551 else if ((framesz
& 7) != 0 || framesz
< 0
14552 || framesz
> 0xff * 8)
14553 as_bad (_("invalid frame size"));
14554 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14557 opcode
|= (((framesz
& 0xf0) << 16)
14558 | (framesz
& 0x0f));
14561 /* Finally build the instruction. */
14562 if ((opcode
>> 16) != 0 || framesz
== 0)
14563 opcode
|= MIPS16_EXTEND
;
14564 ip
->insn_opcode
= opcode
;
14568 case 'e': /* extend code */
14569 my_getExpression (&imm_expr
, s
);
14570 check_absolute_expr (ip
, &imm_expr
);
14571 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14573 as_warn (_("Invalid value for `%s' (%lu)"),
14575 (unsigned long) imm_expr
.X_add_number
);
14576 imm_expr
.X_add_number
&= 0x7ff;
14578 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14579 imm_expr
.X_op
= O_absent
;
14589 /* Args don't match. */
14590 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14591 strcmp (insn
->name
, insn
[1].name
) == 0)
14598 insn_error
= _("illegal operands");
14604 /* This structure holds information we know about a mips16 immediate
14607 struct mips16_immed_operand
14609 /* The type code used in the argument string in the opcode table. */
14611 /* The number of bits in the short form of the opcode. */
14613 /* The number of bits in the extended form of the opcode. */
14615 /* The amount by which the short form is shifted when it is used;
14616 for example, the sw instruction has a shift count of 2. */
14618 /* The amount by which the short form is shifted when it is stored
14619 into the instruction code. */
14621 /* Non-zero if the short form is unsigned. */
14623 /* Non-zero if the extended form is unsigned. */
14625 /* Non-zero if the value is PC relative. */
14629 /* The mips16 immediate operand types. */
14631 static const struct mips16_immed_operand mips16_immed_operands
[] =
14633 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14634 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14635 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14636 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14637 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14638 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14639 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14640 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14641 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14642 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14643 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14644 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14645 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14646 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14647 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14648 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14649 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14650 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14651 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14652 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14653 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14656 #define MIPS16_NUM_IMMED \
14657 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14659 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14660 NBITS is the number of significant bits in VAL. */
14662 static unsigned long
14663 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14668 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14671 else if (nbits
== 15)
14673 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14678 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14681 return (extval
<< 16) | val
;
14684 /* Install immediate value VAL into MIPS16 instruction *INSN,
14685 extending it if necessary. The instruction in *INSN may
14686 already be extended.
14688 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14689 if none. In the former case, VAL is a 16-bit number with no
14690 defined signedness.
14692 TYPE is the type of the immediate field. USER_INSN_LENGTH
14693 is the length that the user requested, or 0 if none. */
14696 mips16_immed (char *file
, unsigned int line
, int type
,
14697 bfd_reloc_code_real_type reloc
, offsetT val
,
14698 unsigned int user_insn_length
, unsigned long *insn
)
14700 const struct mips16_immed_operand
*op
;
14701 int mintiny
, maxtiny
;
14703 op
= mips16_immed_operands
;
14704 while (op
->type
!= type
)
14707 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14712 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14715 maxtiny
= 1 << op
->nbits
;
14720 maxtiny
= (1 << op
->nbits
) - 1;
14722 if (reloc
!= BFD_RELOC_UNUSED
)
14727 mintiny
= - (1 << (op
->nbits
- 1));
14728 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14729 if (reloc
!= BFD_RELOC_UNUSED
)
14730 val
= SEXT_16BIT (val
);
14733 /* Branch offsets have an implicit 0 in the lowest bit. */
14734 if (type
== 'p' || type
== 'q')
14737 if ((val
& ((1 << op
->shift
) - 1)) != 0
14738 || val
< (mintiny
<< op
->shift
)
14739 || val
> (maxtiny
<< op
->shift
))
14741 /* We need an extended instruction. */
14742 if (user_insn_length
== 2)
14743 as_bad_where (file
, line
, _("invalid unextended operand value"));
14745 *insn
|= MIPS16_EXTEND
;
14747 else if (user_insn_length
== 4)
14749 /* The operand doesn't force an unextended instruction to be extended.
14750 Warn if the user wanted an extended instruction anyway. */
14751 *insn
|= MIPS16_EXTEND
;
14752 as_warn_where (file
, line
,
14753 _("extended operand requested but not required"));
14756 if (mips16_opcode_length (*insn
) == 2)
14760 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14761 insnval
<<= op
->op_shift
;
14766 long minext
, maxext
;
14768 if (reloc
== BFD_RELOC_UNUSED
)
14773 maxext
= (1 << op
->extbits
) - 1;
14777 minext
= - (1 << (op
->extbits
- 1));
14778 maxext
= (1 << (op
->extbits
- 1)) - 1;
14780 if (val
< minext
|| val
> maxext
)
14781 as_bad_where (file
, line
,
14782 _("operand value out of range for instruction"));
14785 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14789 struct percent_op_match
14792 bfd_reloc_code_real_type reloc
;
14795 static const struct percent_op_match mips_percent_op
[] =
14797 {"%lo", BFD_RELOC_LO16
},
14799 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14800 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14801 {"%call16", BFD_RELOC_MIPS_CALL16
},
14802 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14803 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14804 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14805 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14806 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14807 {"%got", BFD_RELOC_MIPS_GOT16
},
14808 {"%gp_rel", BFD_RELOC_GPREL16
},
14809 {"%half", BFD_RELOC_16
},
14810 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14811 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14812 {"%neg", BFD_RELOC_MIPS_SUB
},
14813 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14814 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14815 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14816 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14817 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14818 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14819 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14821 {"%hi", BFD_RELOC_HI16_S
}
14824 static const struct percent_op_match mips16_percent_op
[] =
14826 {"%lo", BFD_RELOC_MIPS16_LO16
},
14827 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14828 {"%got", BFD_RELOC_MIPS16_GOT16
},
14829 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14830 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14831 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14832 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14833 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14834 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14835 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14836 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14837 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14841 /* Return true if *STR points to a relocation operator. When returning true,
14842 move *STR over the operator and store its relocation code in *RELOC.
14843 Leave both *STR and *RELOC alone when returning false. */
14846 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14848 const struct percent_op_match
*percent_op
;
14851 if (mips_opts
.mips16
)
14853 percent_op
= mips16_percent_op
;
14854 limit
= ARRAY_SIZE (mips16_percent_op
);
14858 percent_op
= mips_percent_op
;
14859 limit
= ARRAY_SIZE (mips_percent_op
);
14862 for (i
= 0; i
< limit
; i
++)
14863 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14865 int len
= strlen (percent_op
[i
].str
);
14867 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14870 *str
+= strlen (percent_op
[i
].str
);
14871 *reloc
= percent_op
[i
].reloc
;
14873 /* Check whether the output BFD supports this relocation.
14874 If not, issue an error and fall back on something safe. */
14875 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14877 as_bad (_("relocation %s isn't supported by the current ABI"),
14878 percent_op
[i
].str
);
14879 *reloc
= BFD_RELOC_UNUSED
;
14887 /* Parse string STR as a 16-bit relocatable operand. Store the
14888 expression in *EP and the relocations in the array starting
14889 at RELOC. Return the number of relocation operators used.
14891 On exit, EXPR_END points to the first character after the expression. */
14894 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14897 bfd_reloc_code_real_type reversed_reloc
[3];
14898 size_t reloc_index
, i
;
14899 int crux_depth
, str_depth
;
14902 /* Search for the start of the main expression, recoding relocations
14903 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14904 of the main expression and with CRUX_DEPTH containing the number
14905 of open brackets at that point. */
14912 crux_depth
= str_depth
;
14914 /* Skip over whitespace and brackets, keeping count of the number
14916 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14921 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14922 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14924 my_getExpression (ep
, crux
);
14927 /* Match every open bracket. */
14928 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14932 if (crux_depth
> 0)
14933 as_bad (_("unclosed '('"));
14937 if (reloc_index
!= 0)
14939 prev_reloc_op_frag
= frag_now
;
14940 for (i
= 0; i
< reloc_index
; i
++)
14941 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14944 return reloc_index
;
14948 my_getExpression (expressionS
*ep
, char *str
)
14952 save_in
= input_line_pointer
;
14953 input_line_pointer
= str
;
14955 expr_end
= input_line_pointer
;
14956 input_line_pointer
= save_in
;
14960 md_atof (int type
, char *litP
, int *sizeP
)
14962 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14966 md_number_to_chars (char *buf
, valueT val
, int n
)
14968 if (target_big_endian
)
14969 number_to_chars_bigendian (buf
, val
, n
);
14971 number_to_chars_littleendian (buf
, val
, n
);
14975 static int support_64bit_objects(void)
14977 const char **list
, **l
;
14980 list
= bfd_target_list ();
14981 for (l
= list
; *l
!= NULL
; l
++)
14982 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14983 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14985 yes
= (*l
!= NULL
);
14989 #endif /* OBJ_ELF */
14991 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14992 NEW_VALUE. Warn if another value was already specified. Note:
14993 we have to defer parsing the -march and -mtune arguments in order
14994 to handle 'from-abi' correctly, since the ABI might be specified
14995 in a later argument. */
14998 mips_set_option_string (const char **string_ptr
, const char *new_value
)
15000 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
15001 as_warn (_("A different %s was already specified, is now %s"),
15002 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
15005 *string_ptr
= new_value
;
15009 md_parse_option (int c
, char *arg
)
15013 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
15014 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
15016 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
15017 c
== mips_ases
[i
].option_on
);
15023 case OPTION_CONSTRUCT_FLOATS
:
15024 mips_disable_float_construction
= 0;
15027 case OPTION_NO_CONSTRUCT_FLOATS
:
15028 mips_disable_float_construction
= 1;
15040 target_big_endian
= 1;
15044 target_big_endian
= 0;
15050 else if (arg
[0] == '0')
15052 else if (arg
[0] == '1')
15062 mips_debug
= atoi (arg
);
15066 file_mips_isa
= ISA_MIPS1
;
15070 file_mips_isa
= ISA_MIPS2
;
15074 file_mips_isa
= ISA_MIPS3
;
15078 file_mips_isa
= ISA_MIPS4
;
15082 file_mips_isa
= ISA_MIPS5
;
15085 case OPTION_MIPS32
:
15086 file_mips_isa
= ISA_MIPS32
;
15089 case OPTION_MIPS32R2
:
15090 file_mips_isa
= ISA_MIPS32R2
;
15093 case OPTION_MIPS64R2
:
15094 file_mips_isa
= ISA_MIPS64R2
;
15097 case OPTION_MIPS64
:
15098 file_mips_isa
= ISA_MIPS64
;
15102 mips_set_option_string (&mips_tune_string
, arg
);
15106 mips_set_option_string (&mips_arch_string
, arg
);
15110 mips_set_option_string (&mips_arch_string
, "4650");
15111 mips_set_option_string (&mips_tune_string
, "4650");
15114 case OPTION_NO_M4650
:
15118 mips_set_option_string (&mips_arch_string
, "4010");
15119 mips_set_option_string (&mips_tune_string
, "4010");
15122 case OPTION_NO_M4010
:
15126 mips_set_option_string (&mips_arch_string
, "4100");
15127 mips_set_option_string (&mips_tune_string
, "4100");
15130 case OPTION_NO_M4100
:
15134 mips_set_option_string (&mips_arch_string
, "3900");
15135 mips_set_option_string (&mips_tune_string
, "3900");
15138 case OPTION_NO_M3900
:
15141 case OPTION_MICROMIPS
:
15142 if (mips_opts
.mips16
== 1)
15144 as_bad (_("-mmicromips cannot be used with -mips16"));
15147 mips_opts
.micromips
= 1;
15148 mips_no_prev_insn ();
15151 case OPTION_NO_MICROMIPS
:
15152 mips_opts
.micromips
= 0;
15153 mips_no_prev_insn ();
15156 case OPTION_MIPS16
:
15157 if (mips_opts
.micromips
== 1)
15159 as_bad (_("-mips16 cannot be used with -micromips"));
15162 mips_opts
.mips16
= 1;
15163 mips_no_prev_insn ();
15166 case OPTION_NO_MIPS16
:
15167 mips_opts
.mips16
= 0;
15168 mips_no_prev_insn ();
15171 case OPTION_FIX_24K
:
15175 case OPTION_NO_FIX_24K
:
15179 case OPTION_FIX_LOONGSON2F_JUMP
:
15180 mips_fix_loongson2f_jump
= TRUE
;
15183 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
15184 mips_fix_loongson2f_jump
= FALSE
;
15187 case OPTION_FIX_LOONGSON2F_NOP
:
15188 mips_fix_loongson2f_nop
= TRUE
;
15191 case OPTION_NO_FIX_LOONGSON2F_NOP
:
15192 mips_fix_loongson2f_nop
= FALSE
;
15195 case OPTION_FIX_VR4120
:
15196 mips_fix_vr4120
= 1;
15199 case OPTION_NO_FIX_VR4120
:
15200 mips_fix_vr4120
= 0;
15203 case OPTION_FIX_VR4130
:
15204 mips_fix_vr4130
= 1;
15207 case OPTION_NO_FIX_VR4130
:
15208 mips_fix_vr4130
= 0;
15211 case OPTION_FIX_CN63XXP1
:
15212 mips_fix_cn63xxp1
= TRUE
;
15215 case OPTION_NO_FIX_CN63XXP1
:
15216 mips_fix_cn63xxp1
= FALSE
;
15219 case OPTION_RELAX_BRANCH
:
15220 mips_relax_branch
= 1;
15223 case OPTION_NO_RELAX_BRANCH
:
15224 mips_relax_branch
= 0;
15227 case OPTION_MSHARED
:
15228 mips_in_shared
= TRUE
;
15231 case OPTION_MNO_SHARED
:
15232 mips_in_shared
= FALSE
;
15235 case OPTION_MSYM32
:
15236 mips_opts
.sym32
= TRUE
;
15239 case OPTION_MNO_SYM32
:
15240 mips_opts
.sym32
= FALSE
;
15244 /* When generating ELF code, we permit -KPIC and -call_shared to
15245 select SVR4_PIC, and -non_shared to select no PIC. This is
15246 intended to be compatible with Irix 5. */
15247 case OPTION_CALL_SHARED
:
15250 as_bad (_("-call_shared is supported only for ELF format"));
15253 mips_pic
= SVR4_PIC
;
15254 mips_abicalls
= TRUE
;
15257 case OPTION_CALL_NONPIC
:
15260 as_bad (_("-call_nonpic is supported only for ELF format"));
15264 mips_abicalls
= TRUE
;
15267 case OPTION_NON_SHARED
:
15270 as_bad (_("-non_shared is supported only for ELF format"));
15274 mips_abicalls
= FALSE
;
15277 /* The -xgot option tells the assembler to use 32 bit offsets
15278 when accessing the got in SVR4_PIC mode. It is for Irix
15283 #endif /* OBJ_ELF */
15286 g_switch_value
= atoi (arg
);
15290 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15294 mips_abi
= O32_ABI
;
15295 /* We silently ignore -32 for non-ELF targets. This greatly
15296 simplifies the construction of the MIPS GAS test cases. */
15303 as_bad (_("-n32 is supported for ELF format only"));
15306 mips_abi
= N32_ABI
;
15312 as_bad (_("-64 is supported for ELF format only"));
15315 mips_abi
= N64_ABI
;
15316 if (!support_64bit_objects())
15317 as_fatal (_("No compiled in support for 64 bit object file format"));
15319 #endif /* OBJ_ELF */
15322 file_mips_gp32
= 1;
15326 file_mips_gp32
= 0;
15330 file_mips_fp32
= 1;
15334 file_mips_fp32
= 0;
15337 case OPTION_SINGLE_FLOAT
:
15338 file_mips_single_float
= 1;
15341 case OPTION_DOUBLE_FLOAT
:
15342 file_mips_single_float
= 0;
15345 case OPTION_SOFT_FLOAT
:
15346 file_mips_soft_float
= 1;
15349 case OPTION_HARD_FLOAT
:
15350 file_mips_soft_float
= 0;
15357 as_bad (_("-mabi is supported for ELF format only"));
15360 if (strcmp (arg
, "32") == 0)
15361 mips_abi
= O32_ABI
;
15362 else if (strcmp (arg
, "o64") == 0)
15363 mips_abi
= O64_ABI
;
15364 else if (strcmp (arg
, "n32") == 0)
15365 mips_abi
= N32_ABI
;
15366 else if (strcmp (arg
, "64") == 0)
15368 mips_abi
= N64_ABI
;
15369 if (! support_64bit_objects())
15370 as_fatal (_("No compiled in support for 64 bit object file "
15373 else if (strcmp (arg
, "eabi") == 0)
15374 mips_abi
= EABI_ABI
;
15377 as_fatal (_("invalid abi -mabi=%s"), arg
);
15381 #endif /* OBJ_ELF */
15383 case OPTION_M7000_HILO_FIX
:
15384 mips_7000_hilo_fix
= TRUE
;
15387 case OPTION_MNO_7000_HILO_FIX
:
15388 mips_7000_hilo_fix
= FALSE
;
15392 case OPTION_MDEBUG
:
15393 mips_flag_mdebug
= TRUE
;
15396 case OPTION_NO_MDEBUG
:
15397 mips_flag_mdebug
= FALSE
;
15401 mips_flag_pdr
= TRUE
;
15404 case OPTION_NO_PDR
:
15405 mips_flag_pdr
= FALSE
;
15408 case OPTION_MVXWORKS_PIC
:
15409 mips_pic
= VXWORKS_PIC
;
15411 #endif /* OBJ_ELF */
15417 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15422 /* Set up globals to generate code for the ISA or processor
15423 described by INFO. */
15426 mips_set_architecture (const struct mips_cpu_info
*info
)
15430 file_mips_arch
= info
->cpu
;
15431 mips_opts
.arch
= info
->cpu
;
15432 mips_opts
.isa
= info
->isa
;
15437 /* Likewise for tuning. */
15440 mips_set_tune (const struct mips_cpu_info
*info
)
15443 mips_tune
= info
->cpu
;
15448 mips_after_parse_args (void)
15450 const struct mips_cpu_info
*arch_info
= 0;
15451 const struct mips_cpu_info
*tune_info
= 0;
15453 /* GP relative stuff not working for PE */
15454 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15456 if (g_switch_seen
&& g_switch_value
!= 0)
15457 as_bad (_("-G not supported in this configuration."));
15458 g_switch_value
= 0;
15461 if (mips_abi
== NO_ABI
)
15462 mips_abi
= MIPS_DEFAULT_ABI
;
15464 /* The following code determines the architecture and register size.
15465 Similar code was added to GCC 3.3 (see override_options() in
15466 config/mips/mips.c). The GAS and GCC code should be kept in sync
15467 as much as possible. */
15469 if (mips_arch_string
!= 0)
15470 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15472 if (file_mips_isa
!= ISA_UNKNOWN
)
15474 /* Handle -mipsN. At this point, file_mips_isa contains the
15475 ISA level specified by -mipsN, while arch_info->isa contains
15476 the -march selection (if any). */
15477 if (arch_info
!= 0)
15479 /* -march takes precedence over -mipsN, since it is more descriptive.
15480 There's no harm in specifying both as long as the ISA levels
15482 if (file_mips_isa
!= arch_info
->isa
)
15483 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15484 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15485 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15488 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15491 if (arch_info
== 0)
15493 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15494 gas_assert (arch_info
);
15497 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15498 as_bad (_("-march=%s is not compatible with the selected ABI"),
15501 mips_set_architecture (arch_info
);
15503 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15504 if (mips_tune_string
!= 0)
15505 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15507 if (tune_info
== 0)
15508 mips_set_tune (arch_info
);
15510 mips_set_tune (tune_info
);
15512 if (file_mips_gp32
>= 0)
15514 /* The user specified the size of the integer registers. Make sure
15515 it agrees with the ABI and ISA. */
15516 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15517 as_bad (_("-mgp64 used with a 32-bit processor"));
15518 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15519 as_bad (_("-mgp32 used with a 64-bit ABI"));
15520 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15521 as_bad (_("-mgp64 used with a 32-bit ABI"));
15525 /* Infer the integer register size from the ABI and processor.
15526 Restrict ourselves to 32-bit registers if that's all the
15527 processor has, or if the ABI cannot handle 64-bit registers. */
15528 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15529 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15532 switch (file_mips_fp32
)
15536 /* No user specified float register size.
15537 ??? GAS treats single-float processors as though they had 64-bit
15538 float registers (although it complains when double-precision
15539 instructions are used). As things stand, saying they have 32-bit
15540 registers would lead to spurious "register must be even" messages.
15541 So here we assume float registers are never smaller than the
15543 if (file_mips_gp32
== 0)
15544 /* 64-bit integer registers implies 64-bit float registers. */
15545 file_mips_fp32
= 0;
15546 else if ((mips_opts
.ase
& FP64_ASES
)
15547 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15548 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15549 file_mips_fp32
= 0;
15551 /* 32-bit float registers. */
15552 file_mips_fp32
= 1;
15555 /* The user specified the size of the float registers. Check if it
15556 agrees with the ABI and ISA. */
15558 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15559 as_bad (_("-mfp64 used with a 32-bit fpu"));
15560 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15561 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15562 as_warn (_("-mfp64 used with a 32-bit ABI"));
15565 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15566 as_warn (_("-mfp32 used with a 64-bit ABI"));
15570 /* End of GCC-shared inference code. */
15572 /* This flag is set when we have a 64-bit capable CPU but use only
15573 32-bit wide registers. Note that EABI does not use it. */
15574 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15575 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15576 || mips_abi
== O32_ABI
))
15577 mips_32bitmode
= 1;
15579 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15580 as_bad (_("trap exception not supported at ISA 1"));
15582 /* If the selected architecture includes support for ASEs, enable
15583 generation of code for them. */
15584 if (mips_opts
.mips16
== -1)
15585 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15586 if (mips_opts
.micromips
== -1)
15587 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15589 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15590 ASEs from being selected implicitly. */
15591 if (file_mips_fp32
== 1)
15592 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
15594 /* If the user didn't explicitly select or deselect a particular ASE,
15595 use the default setting for the CPU. */
15596 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
15598 file_mips_isa
= mips_opts
.isa
;
15599 file_ase
= mips_opts
.ase
;
15600 mips_opts
.gp32
= file_mips_gp32
;
15601 mips_opts
.fp32
= file_mips_fp32
;
15602 mips_opts
.soft_float
= file_mips_soft_float
;
15603 mips_opts
.single_float
= file_mips_single_float
;
15605 mips_check_isa_supports_ases ();
15607 if (mips_flag_mdebug
< 0)
15608 mips_flag_mdebug
= 0;
15612 mips_init_after_args (void)
15614 /* initialize opcodes */
15615 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15616 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15620 md_pcrel_from (fixS
*fixP
)
15622 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15623 switch (fixP
->fx_r_type
)
15625 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15626 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15627 /* Return the address of the delay slot. */
15630 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15631 case BFD_RELOC_MICROMIPS_JMP
:
15632 case BFD_RELOC_16_PCREL_S2
:
15633 case BFD_RELOC_MIPS_JMP
:
15634 /* Return the address of the delay slot. */
15637 case BFD_RELOC_32_PCREL
:
15641 /* We have no relocation type for PC relative MIPS16 instructions. */
15642 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15644 _("PC relative MIPS16 instruction references a different section"));
15649 /* This is called before the symbol table is processed. In order to
15650 work with gcc when using mips-tfile, we must keep all local labels.
15651 However, in other cases, we want to discard them. If we were
15652 called with -g, but we didn't see any debugging information, it may
15653 mean that gcc is smuggling debugging information through to
15654 mips-tfile, in which case we must generate all local labels. */
15657 mips_frob_file_before_adjust (void)
15659 #ifndef NO_ECOFF_DEBUGGING
15660 if (ECOFF_DEBUGGING
15662 && ! ecoff_debugging_seen
)
15663 flag_keep_locals
= 1;
15667 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15668 the corresponding LO16 reloc. This is called before md_apply_fix and
15669 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15670 relocation operators.
15672 For our purposes, a %lo() expression matches a %got() or %hi()
15675 (a) it refers to the same symbol; and
15676 (b) the offset applied in the %lo() expression is no lower than
15677 the offset applied in the %got() or %hi().
15679 (b) allows us to cope with code like:
15682 lh $4,%lo(foo+2)($4)
15684 ...which is legal on RELA targets, and has a well-defined behaviour
15685 if the user knows that adding 2 to "foo" will not induce a carry to
15688 When several %lo()s match a particular %got() or %hi(), we use the
15689 following rules to distinguish them:
15691 (1) %lo()s with smaller offsets are a better match than %lo()s with
15694 (2) %lo()s with no matching %got() or %hi() are better than those
15695 that already have a matching %got() or %hi().
15697 (3) later %lo()s are better than earlier %lo()s.
15699 These rules are applied in order.
15701 (1) means, among other things, that %lo()s with identical offsets are
15702 chosen if they exist.
15704 (2) means that we won't associate several high-part relocations with
15705 the same low-part relocation unless there's no alternative. Having
15706 several high parts for the same low part is a GNU extension; this rule
15707 allows careful users to avoid it.
15709 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15710 with the last high-part relocation being at the front of the list.
15711 It therefore makes sense to choose the last matching low-part
15712 relocation, all other things being equal. It's also easier
15713 to code that way. */
15716 mips_frob_file (void)
15718 struct mips_hi_fixup
*l
;
15719 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15721 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15723 segment_info_type
*seginfo
;
15724 bfd_boolean matched_lo_p
;
15725 fixS
**hi_pos
, **lo_pos
, **pos
;
15727 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15729 /* If a GOT16 relocation turns out to be against a global symbol,
15730 there isn't supposed to be a matching LO. Ignore %gots against
15731 constants; we'll report an error for those later. */
15732 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15733 && !(l
->fixp
->fx_addsy
15734 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15737 /* Check quickly whether the next fixup happens to be a matching %lo. */
15738 if (fixup_has_matching_lo_p (l
->fixp
))
15741 seginfo
= seg_info (l
->seg
);
15743 /* Set HI_POS to the position of this relocation in the chain.
15744 Set LO_POS to the position of the chosen low-part relocation.
15745 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15746 relocation that matches an immediately-preceding high-part
15750 matched_lo_p
= FALSE
;
15751 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15753 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15755 if (*pos
== l
->fixp
)
15758 if ((*pos
)->fx_r_type
== looking_for_rtype
15759 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15760 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15762 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15764 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15767 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15768 && fixup_has_matching_lo_p (*pos
));
15771 /* If we found a match, remove the high-part relocation from its
15772 current position and insert it before the low-part relocation.
15773 Make the offsets match so that fixup_has_matching_lo_p()
15776 We don't warn about unmatched high-part relocations since some
15777 versions of gcc have been known to emit dead "lui ...%hi(...)"
15779 if (lo_pos
!= NULL
)
15781 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15782 if (l
->fixp
->fx_next
!= *lo_pos
)
15784 *hi_pos
= l
->fixp
->fx_next
;
15785 l
->fixp
->fx_next
= *lo_pos
;
15793 mips_force_relocation (fixS
*fixp
)
15795 if (generic_force_reloc (fixp
))
15798 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15799 so that the linker relaxation can update targets. */
15800 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15801 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15802 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15808 /* Read the instruction associated with RELOC from BUF. */
15810 static unsigned int
15811 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15813 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15814 return read_compressed_insn (buf
, 4);
15816 return read_insn (buf
);
15819 /* Write instruction INSN to BUF, given that it has been relocated
15823 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15824 unsigned long insn
)
15826 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15827 write_compressed_insn (buf
, insn
, 4);
15829 write_insn (buf
, insn
);
15832 /* Apply a fixup to the object file. */
15835 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15838 unsigned long insn
;
15839 reloc_howto_type
*howto
;
15841 /* We ignore generic BFD relocations we don't know about. */
15842 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15846 gas_assert (fixP
->fx_size
== 2
15847 || fixP
->fx_size
== 4
15848 || fixP
->fx_r_type
== BFD_RELOC_16
15849 || fixP
->fx_r_type
== BFD_RELOC_64
15850 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15851 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15852 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15853 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15854 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15855 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15857 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15859 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15860 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15861 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15862 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15863 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15865 /* Don't treat parts of a composite relocation as done. There are two
15868 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15869 should nevertheless be emitted if the first part is.
15871 (2) In normal usage, composite relocations are never assembly-time
15872 constants. The easiest way of dealing with the pathological
15873 exceptions is to generate a relocation against STN_UNDEF and
15874 leave everything up to the linker. */
15875 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15878 switch (fixP
->fx_r_type
)
15880 case BFD_RELOC_MIPS_TLS_GD
:
15881 case BFD_RELOC_MIPS_TLS_LDM
:
15882 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15883 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15884 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15885 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15886 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15887 case BFD_RELOC_MIPS_TLS_TPREL32
:
15888 case BFD_RELOC_MIPS_TLS_TPREL64
:
15889 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15890 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15891 case BFD_RELOC_MICROMIPS_TLS_GD
:
15892 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15893 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15894 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15895 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15896 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15897 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15898 case BFD_RELOC_MIPS16_TLS_GD
:
15899 case BFD_RELOC_MIPS16_TLS_LDM
:
15900 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15901 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15902 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15903 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15904 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15905 if (!fixP
->fx_addsy
)
15907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15908 _("TLS relocation against a constant"));
15911 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15914 case BFD_RELOC_MIPS_JMP
:
15915 case BFD_RELOC_MIPS_SHIFT5
:
15916 case BFD_RELOC_MIPS_SHIFT6
:
15917 case BFD_RELOC_MIPS_GOT_DISP
:
15918 case BFD_RELOC_MIPS_GOT_PAGE
:
15919 case BFD_RELOC_MIPS_GOT_OFST
:
15920 case BFD_RELOC_MIPS_SUB
:
15921 case BFD_RELOC_MIPS_INSERT_A
:
15922 case BFD_RELOC_MIPS_INSERT_B
:
15923 case BFD_RELOC_MIPS_DELETE
:
15924 case BFD_RELOC_MIPS_HIGHEST
:
15925 case BFD_RELOC_MIPS_HIGHER
:
15926 case BFD_RELOC_MIPS_SCN_DISP
:
15927 case BFD_RELOC_MIPS_REL16
:
15928 case BFD_RELOC_MIPS_RELGOT
:
15929 case BFD_RELOC_MIPS_JALR
:
15930 case BFD_RELOC_HI16
:
15931 case BFD_RELOC_HI16_S
:
15932 case BFD_RELOC_LO16
:
15933 case BFD_RELOC_GPREL16
:
15934 case BFD_RELOC_MIPS_LITERAL
:
15935 case BFD_RELOC_MIPS_CALL16
:
15936 case BFD_RELOC_MIPS_GOT16
:
15937 case BFD_RELOC_GPREL32
:
15938 case BFD_RELOC_MIPS_GOT_HI16
:
15939 case BFD_RELOC_MIPS_GOT_LO16
:
15940 case BFD_RELOC_MIPS_CALL_HI16
:
15941 case BFD_RELOC_MIPS_CALL_LO16
:
15942 case BFD_RELOC_MIPS16_GPREL
:
15943 case BFD_RELOC_MIPS16_GOT16
:
15944 case BFD_RELOC_MIPS16_CALL16
:
15945 case BFD_RELOC_MIPS16_HI16
:
15946 case BFD_RELOC_MIPS16_HI16_S
:
15947 case BFD_RELOC_MIPS16_LO16
:
15948 case BFD_RELOC_MIPS16_JMP
:
15949 case BFD_RELOC_MICROMIPS_JMP
:
15950 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15951 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15952 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15953 case BFD_RELOC_MICROMIPS_SUB
:
15954 case BFD_RELOC_MICROMIPS_HIGHEST
:
15955 case BFD_RELOC_MICROMIPS_HIGHER
:
15956 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15957 case BFD_RELOC_MICROMIPS_JALR
:
15958 case BFD_RELOC_MICROMIPS_HI16
:
15959 case BFD_RELOC_MICROMIPS_HI16_S
:
15960 case BFD_RELOC_MICROMIPS_LO16
:
15961 case BFD_RELOC_MICROMIPS_GPREL16
:
15962 case BFD_RELOC_MICROMIPS_LITERAL
:
15963 case BFD_RELOC_MICROMIPS_CALL16
:
15964 case BFD_RELOC_MICROMIPS_GOT16
:
15965 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15966 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15967 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15968 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15969 case BFD_RELOC_MIPS_EH
:
15974 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15976 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15977 if (mips16_reloc_p (fixP
->fx_r_type
))
15978 insn
|= mips16_immed_extend (value
, 16);
15980 insn
|= (value
& 0xffff);
15981 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15985 _("Unsupported constant in relocation"));
15990 /* This is handled like BFD_RELOC_32, but we output a sign
15991 extended value if we are only 32 bits. */
15994 if (8 <= sizeof (valueT
))
15995 md_number_to_chars (buf
, *valP
, 8);
16000 if ((*valP
& 0x80000000) != 0)
16004 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16005 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16010 case BFD_RELOC_RVA
:
16012 case BFD_RELOC_32_PCREL
:
16014 /* If we are deleting this reloc entry, we must fill in the
16015 value now. This can happen if we have a .word which is not
16016 resolved when it appears but is later defined. */
16018 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16021 case BFD_RELOC_16_PCREL_S2
:
16022 if ((*valP
& 0x3) != 0)
16023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16024 _("Branch to misaligned address (%lx)"), (long) *valP
);
16026 /* We need to save the bits in the instruction since fixup_segment()
16027 might be deleting the relocation entry (i.e., a branch within
16028 the current segment). */
16029 if (! fixP
->fx_done
)
16032 /* Update old instruction data. */
16033 insn
= read_insn (buf
);
16035 if (*valP
+ 0x20000 <= 0x3ffff)
16037 insn
|= (*valP
>> 2) & 0xffff;
16038 write_insn (buf
, insn
);
16040 else if (mips_pic
== NO_PIC
16042 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16043 && (fixP
->fx_frag
->fr_address
16044 < text_section
->vma
+ bfd_get_section_size (text_section
))
16045 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16046 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16047 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16049 /* The branch offset is too large. If this is an
16050 unconditional branch, and we are not generating PIC code,
16051 we can convert it to an absolute jump instruction. */
16052 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16053 insn
= 0x0c000000; /* jal */
16055 insn
= 0x08000000; /* j */
16056 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16058 fixP
->fx_addsy
= section_symbol (text_section
);
16059 *valP
+= md_pcrel_from (fixP
);
16060 write_insn (buf
, insn
);
16064 /* If we got here, we have branch-relaxation disabled,
16065 and there's nothing we can do to fix this instruction
16066 without turning it into a longer sequence. */
16067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16068 _("Branch out of range"));
16072 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16073 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16074 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16075 /* We adjust the offset back to even. */
16076 if ((*valP
& 0x1) != 0)
16079 if (! fixP
->fx_done
)
16082 /* Should never visit here, because we keep the relocation. */
16086 case BFD_RELOC_VTABLE_INHERIT
:
16089 && !S_IS_DEFINED (fixP
->fx_addsy
)
16090 && !S_IS_WEAK (fixP
->fx_addsy
))
16091 S_SET_WEAK (fixP
->fx_addsy
);
16094 case BFD_RELOC_VTABLE_ENTRY
:
16102 /* Remember value for tc_gen_reloc. */
16103 fixP
->fx_addnumber
= *valP
;
16113 name
= input_line_pointer
;
16114 c
= get_symbol_end ();
16115 p
= (symbolS
*) symbol_find_or_make (name
);
16116 *input_line_pointer
= c
;
16120 /* Align the current frag to a given power of two. If a particular
16121 fill byte should be used, FILL points to an integer that contains
16122 that byte, otherwise FILL is null.
16124 This function used to have the comment:
16126 The MIPS assembler also automatically adjusts any preceding label.
16128 The implementation therefore applied the adjustment to a maximum of
16129 one label. However, other label adjustments are applied to batches
16130 of labels, and adjusting just one caused problems when new labels
16131 were added for the sake of debugging or unwind information.
16132 We therefore adjust all preceding labels (given as LABELS) instead. */
16135 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16137 mips_emit_delays ();
16138 mips_record_compressed_mode ();
16139 if (fill
== NULL
&& subseg_text_p (now_seg
))
16140 frag_align_code (to
, 0);
16142 frag_align (to
, fill
? *fill
: 0, 0);
16143 record_alignment (now_seg
, to
);
16144 mips_move_labels (labels
, FALSE
);
16147 /* Align to a given power of two. .align 0 turns off the automatic
16148 alignment used by the data creating pseudo-ops. */
16151 s_align (int x ATTRIBUTE_UNUSED
)
16153 int temp
, fill_value
, *fill_ptr
;
16154 long max_alignment
= 28;
16156 /* o Note that the assembler pulls down any immediately preceding label
16157 to the aligned address.
16158 o It's not documented but auto alignment is reinstated by
16159 a .align pseudo instruction.
16160 o Note also that after auto alignment is turned off the mips assembler
16161 issues an error on attempt to assemble an improperly aligned data item.
16164 temp
= get_absolute_expression ();
16165 if (temp
> max_alignment
)
16166 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
16169 as_warn (_("Alignment negative: 0 assumed."));
16172 if (*input_line_pointer
== ',')
16174 ++input_line_pointer
;
16175 fill_value
= get_absolute_expression ();
16176 fill_ptr
= &fill_value
;
16182 segment_info_type
*si
= seg_info (now_seg
);
16183 struct insn_label_list
*l
= si
->label_list
;
16184 /* Auto alignment should be switched on by next section change. */
16186 mips_align (temp
, fill_ptr
, l
);
16193 demand_empty_rest_of_line ();
16197 s_change_sec (int sec
)
16202 /* The ELF backend needs to know that we are changing sections, so
16203 that .previous works correctly. We could do something like check
16204 for an obj_section_change_hook macro, but that might be confusing
16205 as it would not be appropriate to use it in the section changing
16206 functions in read.c, since obj-elf.c intercepts those. FIXME:
16207 This should be cleaner, somehow. */
16209 obj_elf_section_change_hook ();
16212 mips_emit_delays ();
16223 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16224 demand_empty_rest_of_line ();
16228 seg
= subseg_new (RDATA_SECTION_NAME
,
16229 (subsegT
) get_absolute_expression ());
16232 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16233 | SEC_READONLY
| SEC_RELOC
16235 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16236 record_alignment (seg
, 4);
16238 demand_empty_rest_of_line ();
16242 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16245 bfd_set_section_flags (stdoutput
, seg
,
16246 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16247 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16248 record_alignment (seg
, 4);
16250 demand_empty_rest_of_line ();
16254 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16257 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16258 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16259 record_alignment (seg
, 4);
16261 demand_empty_rest_of_line ();
16269 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16272 char *section_name
;
16277 int section_entry_size
;
16278 int section_alignment
;
16283 section_name
= input_line_pointer
;
16284 c
= get_symbol_end ();
16286 next_c
= *(input_line_pointer
+ 1);
16288 /* Do we have .section Name<,"flags">? */
16289 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16291 /* just after name is now '\0'. */
16292 *input_line_pointer
= c
;
16293 input_line_pointer
= section_name
;
16294 obj_elf_section (ignore
);
16297 input_line_pointer
++;
16299 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16301 section_type
= get_absolute_expression ();
16304 if (*input_line_pointer
++ == ',')
16305 section_flag
= get_absolute_expression ();
16308 if (*input_line_pointer
++ == ',')
16309 section_entry_size
= get_absolute_expression ();
16311 section_entry_size
= 0;
16312 if (*input_line_pointer
++ == ',')
16313 section_alignment
= get_absolute_expression ();
16315 section_alignment
= 0;
16316 /* FIXME: really ignore? */
16317 (void) section_alignment
;
16319 section_name
= xstrdup (section_name
);
16321 /* When using the generic form of .section (as implemented by obj-elf.c),
16322 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16323 traditionally had to fall back on the more common @progbits instead.
16325 There's nothing really harmful in this, since bfd will correct
16326 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16327 means that, for backwards compatibility, the special_section entries
16328 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16330 Even so, we shouldn't force users of the MIPS .section syntax to
16331 incorrectly label the sections as SHT_PROGBITS. The best compromise
16332 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16333 generic type-checking code. */
16334 if (section_type
== SHT_MIPS_DWARF
)
16335 section_type
= SHT_PROGBITS
;
16337 obj_elf_change_section (section_name
, section_type
, section_flag
,
16338 section_entry_size
, 0, 0, 0);
16340 if (now_seg
->name
!= section_name
)
16341 free (section_name
);
16342 #endif /* OBJ_ELF */
16346 mips_enable_auto_align (void)
16352 s_cons (int log_size
)
16354 segment_info_type
*si
= seg_info (now_seg
);
16355 struct insn_label_list
*l
= si
->label_list
;
16357 mips_emit_delays ();
16358 if (log_size
> 0 && auto_align
)
16359 mips_align (log_size
, 0, l
);
16360 cons (1 << log_size
);
16361 mips_clear_insn_labels ();
16365 s_float_cons (int type
)
16367 segment_info_type
*si
= seg_info (now_seg
);
16368 struct insn_label_list
*l
= si
->label_list
;
16370 mips_emit_delays ();
16375 mips_align (3, 0, l
);
16377 mips_align (2, 0, l
);
16381 mips_clear_insn_labels ();
16384 /* Handle .globl. We need to override it because on Irix 5 you are
16387 where foo is an undefined symbol, to mean that foo should be
16388 considered to be the address of a function. */
16391 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16400 name
= input_line_pointer
;
16401 c
= get_symbol_end ();
16402 symbolP
= symbol_find_or_make (name
);
16403 S_SET_EXTERNAL (symbolP
);
16405 *input_line_pointer
= c
;
16406 SKIP_WHITESPACE ();
16408 /* On Irix 5, every global symbol that is not explicitly labelled as
16409 being a function is apparently labelled as being an object. */
16412 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16413 && (*input_line_pointer
!= ','))
16418 secname
= input_line_pointer
;
16419 c
= get_symbol_end ();
16420 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16422 as_bad (_("%s: no such section"), secname
);
16423 *input_line_pointer
= c
;
16425 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16426 flag
= BSF_FUNCTION
;
16429 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16431 c
= *input_line_pointer
;
16434 input_line_pointer
++;
16435 SKIP_WHITESPACE ();
16436 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16442 demand_empty_rest_of_line ();
16446 s_option (int x ATTRIBUTE_UNUSED
)
16451 opt
= input_line_pointer
;
16452 c
= get_symbol_end ();
16456 /* FIXME: What does this mean? */
16458 else if (strncmp (opt
, "pic", 3) == 0)
16462 i
= atoi (opt
+ 3);
16467 mips_pic
= SVR4_PIC
;
16468 mips_abicalls
= TRUE
;
16471 as_bad (_(".option pic%d not supported"), i
);
16473 if (mips_pic
== SVR4_PIC
)
16475 if (g_switch_seen
&& g_switch_value
!= 0)
16476 as_warn (_("-G may not be used with SVR4 PIC code"));
16477 g_switch_value
= 0;
16478 bfd_set_gp_size (stdoutput
, 0);
16482 as_warn (_("Unrecognized option \"%s\""), opt
);
16484 *input_line_pointer
= c
;
16485 demand_empty_rest_of_line ();
16488 /* This structure is used to hold a stack of .set values. */
16490 struct mips_option_stack
16492 struct mips_option_stack
*next
;
16493 struct mips_set_options options
;
16496 static struct mips_option_stack
*mips_opts_stack
;
16498 /* Handle the .set pseudo-op. */
16501 s_mipsset (int x ATTRIBUTE_UNUSED
)
16503 char *name
= input_line_pointer
, ch
;
16504 const struct mips_ase
*ase
;
16506 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16507 ++input_line_pointer
;
16508 ch
= *input_line_pointer
;
16509 *input_line_pointer
= '\0';
16511 if (strcmp (name
, "reorder") == 0)
16513 if (mips_opts
.noreorder
)
16516 else if (strcmp (name
, "noreorder") == 0)
16518 if (!mips_opts
.noreorder
)
16519 start_noreorder ();
16521 else if (strncmp (name
, "at=", 3) == 0)
16523 char *s
= name
+ 3;
16525 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16526 as_bad (_("Unrecognized register name `%s'"), s
);
16528 else if (strcmp (name
, "at") == 0)
16530 mips_opts
.at
= ATREG
;
16532 else if (strcmp (name
, "noat") == 0)
16534 mips_opts
.at
= ZERO
;
16536 else if (strcmp (name
, "macro") == 0)
16538 mips_opts
.warn_about_macros
= 0;
16540 else if (strcmp (name
, "nomacro") == 0)
16542 if (mips_opts
.noreorder
== 0)
16543 as_bad (_("`noreorder' must be set before `nomacro'"));
16544 mips_opts
.warn_about_macros
= 1;
16546 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16548 mips_opts
.nomove
= 0;
16550 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16552 mips_opts
.nomove
= 1;
16554 else if (strcmp (name
, "bopt") == 0)
16556 mips_opts
.nobopt
= 0;
16558 else if (strcmp (name
, "nobopt") == 0)
16560 mips_opts
.nobopt
= 1;
16562 else if (strcmp (name
, "gp=default") == 0)
16563 mips_opts
.gp32
= file_mips_gp32
;
16564 else if (strcmp (name
, "gp=32") == 0)
16565 mips_opts
.gp32
= 1;
16566 else if (strcmp (name
, "gp=64") == 0)
16568 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16569 as_warn (_("%s isa does not support 64-bit registers"),
16570 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16571 mips_opts
.gp32
= 0;
16573 else if (strcmp (name
, "fp=default") == 0)
16574 mips_opts
.fp32
= file_mips_fp32
;
16575 else if (strcmp (name
, "fp=32") == 0)
16576 mips_opts
.fp32
= 1;
16577 else if (strcmp (name
, "fp=64") == 0)
16579 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16580 as_warn (_("%s isa does not support 64-bit floating point registers"),
16581 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16582 mips_opts
.fp32
= 0;
16584 else if (strcmp (name
, "softfloat") == 0)
16585 mips_opts
.soft_float
= 1;
16586 else if (strcmp (name
, "hardfloat") == 0)
16587 mips_opts
.soft_float
= 0;
16588 else if (strcmp (name
, "singlefloat") == 0)
16589 mips_opts
.single_float
= 1;
16590 else if (strcmp (name
, "doublefloat") == 0)
16591 mips_opts
.single_float
= 0;
16592 else if (strcmp (name
, "mips16") == 0
16593 || strcmp (name
, "MIPS-16") == 0)
16595 if (mips_opts
.micromips
== 1)
16596 as_fatal (_("`mips16' cannot be used with `micromips'"));
16597 mips_opts
.mips16
= 1;
16599 else if (strcmp (name
, "nomips16") == 0
16600 || strcmp (name
, "noMIPS-16") == 0)
16601 mips_opts
.mips16
= 0;
16602 else if (strcmp (name
, "micromips") == 0)
16604 if (mips_opts
.mips16
== 1)
16605 as_fatal (_("`micromips' cannot be used with `mips16'"));
16606 mips_opts
.micromips
= 1;
16608 else if (strcmp (name
, "nomicromips") == 0)
16609 mips_opts
.micromips
= 0;
16610 else if (name
[0] == 'n'
16612 && (ase
= mips_lookup_ase (name
+ 2)))
16613 mips_set_ase (ase
, FALSE
);
16614 else if ((ase
= mips_lookup_ase (name
)))
16615 mips_set_ase (ase
, TRUE
);
16616 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16620 /* Permit the user to change the ISA and architecture on the fly.
16621 Needless to say, misuse can cause serious problems. */
16622 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16625 mips_opts
.isa
= file_mips_isa
;
16626 mips_opts
.arch
= file_mips_arch
;
16628 else if (strncmp (name
, "arch=", 5) == 0)
16630 const struct mips_cpu_info
*p
;
16632 p
= mips_parse_cpu("internal use", name
+ 5);
16634 as_bad (_("unknown architecture %s"), name
+ 5);
16637 mips_opts
.arch
= p
->cpu
;
16638 mips_opts
.isa
= p
->isa
;
16641 else if (strncmp (name
, "mips", 4) == 0)
16643 const struct mips_cpu_info
*p
;
16645 p
= mips_parse_cpu("internal use", name
);
16647 as_bad (_("unknown ISA level %s"), name
+ 4);
16650 mips_opts
.arch
= p
->cpu
;
16651 mips_opts
.isa
= p
->isa
;
16655 as_bad (_("unknown ISA or architecture %s"), name
);
16657 switch (mips_opts
.isa
)
16665 mips_opts
.gp32
= 1;
16666 mips_opts
.fp32
= 1;
16673 mips_opts
.gp32
= 0;
16674 if (mips_opts
.arch
== CPU_R5900
)
16676 mips_opts
.fp32
= 1;
16680 mips_opts
.fp32
= 0;
16684 as_bad (_("unknown ISA level %s"), name
+ 4);
16689 mips_opts
.gp32
= file_mips_gp32
;
16690 mips_opts
.fp32
= file_mips_fp32
;
16693 else if (strcmp (name
, "autoextend") == 0)
16694 mips_opts
.noautoextend
= 0;
16695 else if (strcmp (name
, "noautoextend") == 0)
16696 mips_opts
.noautoextend
= 1;
16697 else if (strcmp (name
, "push") == 0)
16699 struct mips_option_stack
*s
;
16701 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16702 s
->next
= mips_opts_stack
;
16703 s
->options
= mips_opts
;
16704 mips_opts_stack
= s
;
16706 else if (strcmp (name
, "pop") == 0)
16708 struct mips_option_stack
*s
;
16710 s
= mips_opts_stack
;
16712 as_bad (_(".set pop with no .set push"));
16715 /* If we're changing the reorder mode we need to handle
16716 delay slots correctly. */
16717 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16718 start_noreorder ();
16719 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16722 mips_opts
= s
->options
;
16723 mips_opts_stack
= s
->next
;
16727 else if (strcmp (name
, "sym32") == 0)
16728 mips_opts
.sym32
= TRUE
;
16729 else if (strcmp (name
, "nosym32") == 0)
16730 mips_opts
.sym32
= FALSE
;
16731 else if (strchr (name
, ','))
16733 /* Generic ".set" directive; use the generic handler. */
16734 *input_line_pointer
= ch
;
16735 input_line_pointer
= name
;
16741 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16743 mips_check_isa_supports_ases ();
16744 *input_line_pointer
= ch
;
16745 demand_empty_rest_of_line ();
16748 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16749 .option pic2. It means to generate SVR4 PIC calls. */
16752 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16754 mips_pic
= SVR4_PIC
;
16755 mips_abicalls
= TRUE
;
16757 if (g_switch_seen
&& g_switch_value
!= 0)
16758 as_warn (_("-G may not be used with SVR4 PIC code"));
16759 g_switch_value
= 0;
16761 bfd_set_gp_size (stdoutput
, 0);
16762 demand_empty_rest_of_line ();
16765 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16766 PIC code. It sets the $gp register for the function based on the
16767 function address, which is in the register named in the argument.
16768 This uses a relocation against _gp_disp, which is handled specially
16769 by the linker. The result is:
16770 lui $gp,%hi(_gp_disp)
16771 addiu $gp,$gp,%lo(_gp_disp)
16772 addu $gp,$gp,.cpload argument
16773 The .cpload argument is normally $25 == $t9.
16775 The -mno-shared option changes this to:
16776 lui $gp,%hi(__gnu_local_gp)
16777 addiu $gp,$gp,%lo(__gnu_local_gp)
16778 and the argument is ignored. This saves an instruction, but the
16779 resulting code is not position independent; it uses an absolute
16780 address for __gnu_local_gp. Thus code assembled with -mno-shared
16781 can go into an ordinary executable, but not into a shared library. */
16784 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16790 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16791 .cpload is ignored. */
16792 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16798 if (mips_opts
.mips16
)
16800 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16801 ignore_rest_of_line ();
16805 /* .cpload should be in a .set noreorder section. */
16806 if (mips_opts
.noreorder
== 0)
16807 as_warn (_(".cpload not in noreorder section"));
16809 reg
= tc_get_register (0);
16811 /* If we need to produce a 64-bit address, we are better off using
16812 the default instruction sequence. */
16813 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16815 ex
.X_op
= O_symbol
;
16816 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16818 ex
.X_op_symbol
= NULL
;
16819 ex
.X_add_number
= 0;
16821 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16822 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16824 mips_mark_labels ();
16825 mips_assembling_insn
= TRUE
;
16828 macro_build_lui (&ex
, mips_gp_register
);
16829 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16830 mips_gp_register
, BFD_RELOC_LO16
);
16832 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16833 mips_gp_register
, reg
);
16836 mips_assembling_insn
= FALSE
;
16837 demand_empty_rest_of_line ();
16840 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16841 .cpsetup $reg1, offset|$reg2, label
16843 If offset is given, this results in:
16844 sd $gp, offset($sp)
16845 lui $gp, %hi(%neg(%gp_rel(label)))
16846 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16847 daddu $gp, $gp, $reg1
16849 If $reg2 is given, this results in:
16850 daddu $reg2, $gp, $0
16851 lui $gp, %hi(%neg(%gp_rel(label)))
16852 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16853 daddu $gp, $gp, $reg1
16854 $reg1 is normally $25 == $t9.
16856 The -mno-shared option replaces the last three instructions with
16858 addiu $gp,$gp,%lo(_gp) */
16861 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16863 expressionS ex_off
;
16864 expressionS ex_sym
;
16867 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16868 We also need NewABI support. */
16869 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16875 if (mips_opts
.mips16
)
16877 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16878 ignore_rest_of_line ();
16882 reg1
= tc_get_register (0);
16883 SKIP_WHITESPACE ();
16884 if (*input_line_pointer
!= ',')
16886 as_bad (_("missing argument separator ',' for .cpsetup"));
16890 ++input_line_pointer
;
16891 SKIP_WHITESPACE ();
16892 if (*input_line_pointer
== '$')
16894 mips_cpreturn_register
= tc_get_register (0);
16895 mips_cpreturn_offset
= -1;
16899 mips_cpreturn_offset
= get_absolute_expression ();
16900 mips_cpreturn_register
= -1;
16902 SKIP_WHITESPACE ();
16903 if (*input_line_pointer
!= ',')
16905 as_bad (_("missing argument separator ',' for .cpsetup"));
16909 ++input_line_pointer
;
16910 SKIP_WHITESPACE ();
16911 expression (&ex_sym
);
16913 mips_mark_labels ();
16914 mips_assembling_insn
= TRUE
;
16917 if (mips_cpreturn_register
== -1)
16919 ex_off
.X_op
= O_constant
;
16920 ex_off
.X_add_symbol
= NULL
;
16921 ex_off
.X_op_symbol
= NULL
;
16922 ex_off
.X_add_number
= mips_cpreturn_offset
;
16924 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16925 BFD_RELOC_LO16
, SP
);
16928 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16929 mips_gp_register
, 0);
16931 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16933 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16934 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16937 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16938 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16939 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16941 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16942 mips_gp_register
, reg1
);
16948 ex
.X_op
= O_symbol
;
16949 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16950 ex
.X_op_symbol
= NULL
;
16951 ex
.X_add_number
= 0;
16953 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16954 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16956 macro_build_lui (&ex
, mips_gp_register
);
16957 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16958 mips_gp_register
, BFD_RELOC_LO16
);
16963 mips_assembling_insn
= FALSE
;
16964 demand_empty_rest_of_line ();
16968 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16970 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16971 .cplocal is ignored. */
16972 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16978 if (mips_opts
.mips16
)
16980 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16981 ignore_rest_of_line ();
16985 mips_gp_register
= tc_get_register (0);
16986 demand_empty_rest_of_line ();
16989 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16990 offset from $sp. The offset is remembered, and after making a PIC
16991 call $gp is restored from that location. */
16994 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16998 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16999 .cprestore is ignored. */
17000 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17006 if (mips_opts
.mips16
)
17008 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17009 ignore_rest_of_line ();
17013 mips_cprestore_offset
= get_absolute_expression ();
17014 mips_cprestore_valid
= 1;
17016 ex
.X_op
= O_constant
;
17017 ex
.X_add_symbol
= NULL
;
17018 ex
.X_op_symbol
= NULL
;
17019 ex
.X_add_number
= mips_cprestore_offset
;
17021 mips_mark_labels ();
17022 mips_assembling_insn
= TRUE
;
17025 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17026 SP
, HAVE_64BIT_ADDRESSES
);
17029 mips_assembling_insn
= FALSE
;
17030 demand_empty_rest_of_line ();
17033 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17034 was given in the preceding .cpsetup, it results in:
17035 ld $gp, offset($sp)
17037 If a register $reg2 was given there, it results in:
17038 daddu $gp, $reg2, $0 */
17041 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17045 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17046 We also need NewABI support. */
17047 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17053 if (mips_opts
.mips16
)
17055 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17056 ignore_rest_of_line ();
17060 mips_mark_labels ();
17061 mips_assembling_insn
= TRUE
;
17064 if (mips_cpreturn_register
== -1)
17066 ex
.X_op
= O_constant
;
17067 ex
.X_add_symbol
= NULL
;
17068 ex
.X_op_symbol
= NULL
;
17069 ex
.X_add_number
= mips_cpreturn_offset
;
17071 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17074 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
17075 mips_cpreturn_register
, 0);
17078 mips_assembling_insn
= FALSE
;
17079 demand_empty_rest_of_line ();
17082 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17083 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17084 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17085 debug information or MIPS16 TLS. */
17088 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17089 bfd_reloc_code_real_type rtype
)
17096 if (ex
.X_op
!= O_symbol
)
17098 as_bad (_("Unsupported use of %s"), dirstr
);
17099 ignore_rest_of_line ();
17102 p
= frag_more (bytes
);
17103 md_number_to_chars (p
, 0, bytes
);
17104 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17105 demand_empty_rest_of_line ();
17106 mips_clear_insn_labels ();
17109 /* Handle .dtprelword. */
17112 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17114 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17117 /* Handle .dtpreldword. */
17120 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17122 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17125 /* Handle .tprelword. */
17128 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17130 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17133 /* Handle .tpreldword. */
17136 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17138 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17141 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17142 code. It sets the offset to use in gp_rel relocations. */
17145 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17147 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17148 We also need NewABI support. */
17149 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17155 mips_gprel_offset
= get_absolute_expression ();
17157 demand_empty_rest_of_line ();
17160 /* Handle the .gpword pseudo-op. This is used when generating PIC
17161 code. It generates a 32 bit GP relative reloc. */
17164 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17166 segment_info_type
*si
;
17167 struct insn_label_list
*l
;
17171 /* When not generating PIC code, this is treated as .word. */
17172 if (mips_pic
!= SVR4_PIC
)
17178 si
= seg_info (now_seg
);
17179 l
= si
->label_list
;
17180 mips_emit_delays ();
17182 mips_align (2, 0, l
);
17185 mips_clear_insn_labels ();
17187 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17189 as_bad (_("Unsupported use of .gpword"));
17190 ignore_rest_of_line ();
17194 md_number_to_chars (p
, 0, 4);
17195 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17196 BFD_RELOC_GPREL32
);
17198 demand_empty_rest_of_line ();
17202 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17204 segment_info_type
*si
;
17205 struct insn_label_list
*l
;
17209 /* When not generating PIC code, this is treated as .dword. */
17210 if (mips_pic
!= SVR4_PIC
)
17216 si
= seg_info (now_seg
);
17217 l
= si
->label_list
;
17218 mips_emit_delays ();
17220 mips_align (3, 0, l
);
17223 mips_clear_insn_labels ();
17225 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17227 as_bad (_("Unsupported use of .gpdword"));
17228 ignore_rest_of_line ();
17232 md_number_to_chars (p
, 0, 8);
17233 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17234 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17236 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17237 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17238 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17240 demand_empty_rest_of_line ();
17243 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17244 tables. It generates a R_MIPS_EH reloc. */
17247 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17252 mips_emit_delays ();
17255 mips_clear_insn_labels ();
17257 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17259 as_bad (_("Unsupported use of .ehword"));
17260 ignore_rest_of_line ();
17264 md_number_to_chars (p
, 0, 4);
17265 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17266 BFD_RELOC_MIPS_EH
);
17268 demand_empty_rest_of_line ();
17271 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17272 tables in SVR4 PIC code. */
17275 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17279 /* This is ignored when not generating SVR4 PIC code. */
17280 if (mips_pic
!= SVR4_PIC
)
17286 mips_mark_labels ();
17287 mips_assembling_insn
= TRUE
;
17289 /* Add $gp to the register named as an argument. */
17291 reg
= tc_get_register (0);
17292 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17295 mips_assembling_insn
= FALSE
;
17296 demand_empty_rest_of_line ();
17299 /* Handle the .insn pseudo-op. This marks instruction labels in
17300 mips16/micromips mode. This permits the linker to handle them specially,
17301 such as generating jalx instructions when needed. We also make
17302 them odd for the duration of the assembly, in order to generate the
17303 right sort of code. We will make them even in the adjust_symtab
17304 routine, while leaving them marked. This is convenient for the
17305 debugger and the disassembler. The linker knows to make them odd
17309 s_insn (int ignore ATTRIBUTE_UNUSED
)
17311 mips_mark_labels ();
17313 demand_empty_rest_of_line ();
17316 /* Handle a .stab[snd] directive. Ideally these directives would be
17317 implemented in a transparent way, so that removing them would not
17318 have any effect on the generated instructions. However, s_stab
17319 internally changes the section, so in practice we need to decide
17320 now whether the preceding label marks compressed code. We do not
17321 support changing the compression mode of a label after a .stab*
17322 directive, such as in:
17328 so the current mode wins. */
17331 s_mips_stab (int type
)
17333 mips_mark_labels ();
17337 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17340 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17347 name
= input_line_pointer
;
17348 c
= get_symbol_end ();
17349 symbolP
= symbol_find_or_make (name
);
17350 S_SET_WEAK (symbolP
);
17351 *input_line_pointer
= c
;
17353 SKIP_WHITESPACE ();
17355 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17357 if (S_IS_DEFINED (symbolP
))
17359 as_bad (_("ignoring attempt to redefine symbol %s"),
17360 S_GET_NAME (symbolP
));
17361 ignore_rest_of_line ();
17365 if (*input_line_pointer
== ',')
17367 ++input_line_pointer
;
17368 SKIP_WHITESPACE ();
17372 if (exp
.X_op
!= O_symbol
)
17374 as_bad (_("bad .weakext directive"));
17375 ignore_rest_of_line ();
17378 symbol_set_value_expression (symbolP
, &exp
);
17381 demand_empty_rest_of_line ();
17384 /* Parse a register string into a number. Called from the ECOFF code
17385 to parse .frame. The argument is non-zero if this is the frame
17386 register, so that we can record it in mips_frame_reg. */
17389 tc_get_register (int frame
)
17393 SKIP_WHITESPACE ();
17394 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17398 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17399 mips_frame_reg_valid
= 1;
17400 mips_cprestore_valid
= 0;
17406 md_section_align (asection
*seg
, valueT addr
)
17408 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17412 /* We don't need to align ELF sections to the full alignment.
17413 However, Irix 5 may prefer that we align them at least to a 16
17414 byte boundary. We don't bother to align the sections if we
17415 are targeted for an embedded system. */
17416 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17422 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17425 /* Utility routine, called from above as well. If called while the
17426 input file is still being read, it's only an approximation. (For
17427 example, a symbol may later become defined which appeared to be
17428 undefined earlier.) */
17431 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17436 if (g_switch_value
> 0)
17438 const char *symname
;
17441 /* Find out whether this symbol can be referenced off the $gp
17442 register. It can be if it is smaller than the -G size or if
17443 it is in the .sdata or .sbss section. Certain symbols can
17444 not be referenced off the $gp, although it appears as though
17446 symname
= S_GET_NAME (sym
);
17447 if (symname
!= (const char *) NULL
17448 && (strcmp (symname
, "eprol") == 0
17449 || strcmp (symname
, "etext") == 0
17450 || strcmp (symname
, "_gp") == 0
17451 || strcmp (symname
, "edata") == 0
17452 || strcmp (symname
, "_fbss") == 0
17453 || strcmp (symname
, "_fdata") == 0
17454 || strcmp (symname
, "_ftext") == 0
17455 || strcmp (symname
, "end") == 0
17456 || strcmp (symname
, "_gp_disp") == 0))
17458 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17460 #ifndef NO_ECOFF_DEBUGGING
17461 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17462 && (symbol_get_obj (sym
)->ecoff_extern_size
17463 <= g_switch_value
))
17465 /* We must defer this decision until after the whole
17466 file has been read, since there might be a .extern
17467 after the first use of this symbol. */
17468 || (before_relaxing
17469 #ifndef NO_ECOFF_DEBUGGING
17470 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17472 && S_GET_VALUE (sym
) == 0)
17473 || (S_GET_VALUE (sym
) != 0
17474 && S_GET_VALUE (sym
) <= g_switch_value
)))
17478 const char *segname
;
17480 segname
= segment_name (S_GET_SEGMENT (sym
));
17481 gas_assert (strcmp (segname
, ".lit8") != 0
17482 && strcmp (segname
, ".lit4") != 0);
17483 change
= (strcmp (segname
, ".sdata") != 0
17484 && strcmp (segname
, ".sbss") != 0
17485 && strncmp (segname
, ".sdata.", 7) != 0
17486 && strncmp (segname
, ".sbss.", 6) != 0
17487 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17488 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17493 /* We are not optimizing for the $gp register. */
17498 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17501 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17505 /* Handle the case of a symbol equated to another symbol. */
17506 while (symbol_equated_reloc_p (sym
))
17510 /* It's possible to get a loop here in a badly written program. */
17511 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17517 if (symbol_section_p (sym
))
17520 symsec
= S_GET_SEGMENT (sym
);
17522 /* This must duplicate the test in adjust_reloc_syms. */
17523 return (!bfd_is_und_section (symsec
)
17524 && !bfd_is_abs_section (symsec
)
17525 && !bfd_is_com_section (symsec
)
17526 && !s_is_linkonce (sym
, segtype
)
17528 /* A global or weak symbol is treated as external. */
17529 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
17535 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17536 extended opcode. SEC is the section the frag is in. */
17539 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17542 const struct mips16_immed_operand
*op
;
17544 int mintiny
, maxtiny
;
17548 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17550 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17553 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17554 op
= mips16_immed_operands
;
17555 while (op
->type
!= type
)
17558 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17563 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17566 maxtiny
= 1 << op
->nbits
;
17571 maxtiny
= (1 << op
->nbits
) - 1;
17576 mintiny
= - (1 << (op
->nbits
- 1));
17577 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17580 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17581 val
= S_GET_VALUE (fragp
->fr_symbol
);
17582 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17588 /* We won't have the section when we are called from
17589 mips_relax_frag. However, we will always have been called
17590 from md_estimate_size_before_relax first. If this is a
17591 branch to a different section, we mark it as such. If SEC is
17592 NULL, and the frag is not marked, then it must be a branch to
17593 the same section. */
17596 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17601 /* Must have been called from md_estimate_size_before_relax. */
17604 fragp
->fr_subtype
=
17605 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17607 /* FIXME: We should support this, and let the linker
17608 catch branches and loads that are out of range. */
17609 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17610 _("unsupported PC relative reference to different section"));
17614 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17615 /* Assume non-extended on the first relaxation pass.
17616 The address we have calculated will be bogus if this is
17617 a forward branch to another frag, as the forward frag
17618 will have fr_address == 0. */
17622 /* In this case, we know for sure that the symbol fragment is in
17623 the same section. If the relax_marker of the symbol fragment
17624 differs from the relax_marker of this fragment, we have not
17625 yet adjusted the symbol fragment fr_address. We want to add
17626 in STRETCH in order to get a better estimate of the address.
17627 This particularly matters because of the shift bits. */
17629 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17633 /* Adjust stretch for any alignment frag. Note that if have
17634 been expanding the earlier code, the symbol may be
17635 defined in what appears to be an earlier frag. FIXME:
17636 This doesn't handle the fr_subtype field, which specifies
17637 a maximum number of bytes to skip when doing an
17639 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17641 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17644 stretch
= - ((- stretch
)
17645 & ~ ((1 << (int) f
->fr_offset
) - 1));
17647 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17656 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17658 /* The base address rules are complicated. The base address of
17659 a branch is the following instruction. The base address of a
17660 PC relative load or add is the instruction itself, but if it
17661 is in a delay slot (in which case it can not be extended) use
17662 the address of the instruction whose delay slot it is in. */
17663 if (type
== 'p' || type
== 'q')
17667 /* If we are currently assuming that this frag should be
17668 extended, then, the current address is two bytes
17670 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17673 /* Ignore the low bit in the target, since it will be set
17674 for a text label. */
17675 if ((val
& 1) != 0)
17678 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17680 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17683 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17685 /* Branch offsets have an implicit 0 in the lowest bit. */
17686 if (type
== 'p' || type
== 'q')
17689 /* If any of the shifted bits are set, we must use an extended
17690 opcode. If the address depends on the size of this
17691 instruction, this can lead to a loop, so we arrange to always
17692 use an extended opcode. We only check this when we are in
17693 the main relaxation loop, when SEC is NULL. */
17694 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17696 fragp
->fr_subtype
=
17697 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17701 /* If we are about to mark a frag as extended because the value
17702 is precisely maxtiny + 1, then there is a chance of an
17703 infinite loop as in the following code:
17708 In this case when the la is extended, foo is 0x3fc bytes
17709 away, so the la can be shrunk, but then foo is 0x400 away, so
17710 the la must be extended. To avoid this loop, we mark the
17711 frag as extended if it was small, and is about to become
17712 extended with a value of maxtiny + 1. */
17713 if (val
== ((maxtiny
+ 1) << op
->shift
)
17714 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17717 fragp
->fr_subtype
=
17718 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17722 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17723 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17725 if ((val
& ((1 << op
->shift
) - 1)) != 0
17726 || val
< (mintiny
<< op
->shift
)
17727 || val
> (maxtiny
<< op
->shift
))
17733 /* Compute the length of a branch sequence, and adjust the
17734 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17735 worst-case length is computed, with UPDATE being used to indicate
17736 whether an unconditional (-1), branch-likely (+1) or regular (0)
17737 branch is to be computed. */
17739 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17741 bfd_boolean toofar
;
17745 && S_IS_DEFINED (fragp
->fr_symbol
)
17746 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17751 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17753 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17757 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17760 /* If the symbol is not defined or it's in a different segment,
17761 assume the user knows what's going on and emit a short
17767 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17769 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17770 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17771 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17772 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17778 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17781 if (mips_pic
!= NO_PIC
)
17783 /* Additional space for PIC loading of target address. */
17785 if (mips_opts
.isa
== ISA_MIPS1
)
17786 /* Additional space for $at-stabilizing nop. */
17790 /* If branch is conditional. */
17791 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17798 /* Compute the length of a branch sequence, and adjust the
17799 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17800 worst-case length is computed, with UPDATE being used to indicate
17801 whether an unconditional (-1), or regular (0) branch is to be
17805 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17807 bfd_boolean toofar
;
17811 && S_IS_DEFINED (fragp
->fr_symbol
)
17812 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17817 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17818 /* Ignore the low bit in the target, since it will be set
17819 for a text label. */
17820 if ((val
& 1) != 0)
17823 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17827 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17830 /* If the symbol is not defined or it's in a different segment,
17831 assume the user knows what's going on and emit a short
17837 if (fragp
&& update
17838 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17839 fragp
->fr_subtype
= (toofar
17840 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17841 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17846 bfd_boolean compact_known
= fragp
!= NULL
;
17847 bfd_boolean compact
= FALSE
;
17848 bfd_boolean uncond
;
17851 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17853 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17855 uncond
= update
< 0;
17857 /* If label is out of range, we turn branch <br>:
17859 <br> label # 4 bytes
17865 nop # 2 bytes if compact && !PIC
17868 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17871 /* If assembling PIC code, we further turn:
17877 lw/ld at, %got(label)(gp) # 4 bytes
17878 d/addiu at, %lo(label) # 4 bytes
17881 if (mips_pic
!= NO_PIC
)
17884 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17886 <brneg> 0f # 4 bytes
17887 nop # 2 bytes if !compact
17890 length
+= (compact_known
&& compact
) ? 4 : 6;
17896 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17897 bit accordingly. */
17900 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17902 bfd_boolean toofar
;
17905 && S_IS_DEFINED (fragp
->fr_symbol
)
17906 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17912 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17913 /* Ignore the low bit in the target, since it will be set
17914 for a text label. */
17915 if ((val
& 1) != 0)
17918 /* Assume this is a 2-byte branch. */
17919 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17921 /* We try to avoid the infinite loop by not adding 2 more bytes for
17926 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17928 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17929 else if (type
== 'E')
17930 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17935 /* If the symbol is not defined or it's in a different segment,
17936 we emit a normal 32-bit branch. */
17939 if (fragp
&& update
17940 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17942 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17943 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17951 /* Estimate the size of a frag before relaxing. Unless this is the
17952 mips16, we are not really relaxing here, and the final size is
17953 encoded in the subtype information. For the mips16, we have to
17954 decide whether we are using an extended opcode or not. */
17957 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17961 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17964 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17966 return fragp
->fr_var
;
17969 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17970 /* We don't want to modify the EXTENDED bit here; it might get us
17971 into infinite loops. We change it only in mips_relax_frag(). */
17972 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17974 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17978 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17979 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17980 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17981 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17982 fragp
->fr_var
= length
;
17987 if (mips_pic
== NO_PIC
)
17988 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17989 else if (mips_pic
== SVR4_PIC
)
17990 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17991 else if (mips_pic
== VXWORKS_PIC
)
17992 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17999 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18000 return -RELAX_FIRST (fragp
->fr_subtype
);
18003 return -RELAX_SECOND (fragp
->fr_subtype
);
18006 /* This is called to see whether a reloc against a defined symbol
18007 should be converted into a reloc against a section. */
18010 mips_fix_adjustable (fixS
*fixp
)
18012 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18013 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18016 if (fixp
->fx_addsy
== NULL
)
18019 /* If symbol SYM is in a mergeable section, relocations of the form
18020 SYM + 0 can usually be made section-relative. The mergeable data
18021 is then identified by the section offset rather than by the symbol.
18023 However, if we're generating REL LO16 relocations, the offset is split
18024 between the LO16 and parterning high part relocation. The linker will
18025 need to recalculate the complete offset in order to correctly identify
18028 The linker has traditionally not looked for the parterning high part
18029 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18030 placed anywhere. Rather than break backwards compatibility by changing
18031 this, it seems better not to force the issue, and instead keep the
18032 original symbol. This will work with either linker behavior. */
18033 if ((lo16_reloc_p (fixp
->fx_r_type
)
18034 || reloc_needs_lo_p (fixp
->fx_r_type
))
18035 && HAVE_IN_PLACE_ADDENDS
18036 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18039 /* There is no place to store an in-place offset for JALR relocations.
18040 Likewise an in-range offset of limited PC-relative relocations may
18041 overflow the in-place relocatable field if recalculated against the
18042 start address of the symbol's containing section. */
18043 if (HAVE_IN_PLACE_ADDENDS
18044 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18045 || jalr_reloc_p (fixp
->fx_r_type
)))
18049 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18050 to a floating-point stub. The same is true for non-R_MIPS16_26
18051 relocations against MIPS16 functions; in this case, the stub becomes
18052 the function's canonical address.
18054 Floating-point stubs are stored in unique .mips16.call.* or
18055 .mips16.fn.* sections. If a stub T for function F is in section S,
18056 the first relocation in section S must be against F; this is how the
18057 linker determines the target function. All relocations that might
18058 resolve to T must also be against F. We therefore have the following
18059 restrictions, which are given in an intentionally-redundant way:
18061 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18064 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18065 if that stub might be used.
18067 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18070 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18071 that stub might be used.
18073 There is a further restriction:
18075 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18076 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
18077 targets with in-place addends; the relocation field cannot
18078 encode the low bit.
18080 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18081 against a MIPS16 symbol. We deal with (5) by by not reducing any
18082 such relocations on REL targets.
18084 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18085 relocation against some symbol R, no relocation against R may be
18086 reduced. (Note that this deals with (2) as well as (1) because
18087 relocations against global symbols will never be reduced on ELF
18088 targets.) This approach is a little simpler than trying to detect
18089 stub sections, and gives the "all or nothing" per-symbol consistency
18090 that we have for MIPS16 symbols. */
18092 && fixp
->fx_subsy
== NULL
18093 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18094 || *symbol_get_tc (fixp
->fx_addsy
)
18095 || (HAVE_IN_PLACE_ADDENDS
18096 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18097 && jmp_reloc_p (fixp
->fx_r_type
))))
18104 /* Translate internal representation of relocation info to BFD target
18108 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18110 static arelent
*retval
[4];
18112 bfd_reloc_code_real_type code
;
18114 memset (retval
, 0, sizeof(retval
));
18115 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
18116 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
18117 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18118 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18120 if (fixp
->fx_pcrel
)
18122 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18123 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18124 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18125 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18126 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
18128 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18129 Relocations want only the symbol offset. */
18130 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18133 /* A gruesome hack which is a result of the gruesome gas
18134 reloc handling. What's worse, for COFF (as opposed to
18135 ECOFF), we might need yet another copy of reloc->address.
18136 See bfd_install_relocation. */
18137 reloc
->addend
+= reloc
->address
;
18141 reloc
->addend
= fixp
->fx_addnumber
;
18143 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18144 entry to be used in the relocation's section offset. */
18145 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18147 reloc
->address
= reloc
->addend
;
18151 code
= fixp
->fx_r_type
;
18153 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18154 if (reloc
->howto
== NULL
)
18156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18157 _("Can not represent %s relocation in this object file format"),
18158 bfd_get_reloc_code_name (code
));
18165 /* Relax a machine dependent frag. This returns the amount by which
18166 the current size of the frag should change. */
18169 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18171 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18173 offsetT old_var
= fragp
->fr_var
;
18175 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18177 return fragp
->fr_var
- old_var
;
18180 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18182 offsetT old_var
= fragp
->fr_var
;
18183 offsetT new_var
= 4;
18185 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18186 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18187 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18188 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18189 fragp
->fr_var
= new_var
;
18191 return new_var
- old_var
;
18194 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18197 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18199 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18201 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18206 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18208 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18215 /* Convert a machine dependent frag. */
18218 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18220 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18223 unsigned long insn
;
18227 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18228 insn
= read_insn (buf
);
18230 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18232 /* We generate a fixup instead of applying it right now
18233 because, if there are linker relaxations, we're going to
18234 need the relocations. */
18235 exp
.X_op
= O_symbol
;
18236 exp
.X_add_symbol
= fragp
->fr_symbol
;
18237 exp
.X_add_number
= fragp
->fr_offset
;
18239 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18240 BFD_RELOC_16_PCREL_S2
);
18241 fixp
->fx_file
= fragp
->fr_file
;
18242 fixp
->fx_line
= fragp
->fr_line
;
18244 buf
= write_insn (buf
, insn
);
18250 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18251 _("Relaxed out-of-range branch into a jump"));
18253 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18256 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18258 /* Reverse the branch. */
18259 switch ((insn
>> 28) & 0xf)
18262 /* bc[0-3][tf]l? instructions can have the condition
18263 reversed by tweaking a single TF bit, and their
18264 opcodes all have 0x4???????. */
18265 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18266 insn
^= 0x00010000;
18270 /* bltz 0x04000000 bgez 0x04010000
18271 bltzal 0x04100000 bgezal 0x04110000 */
18272 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18273 insn
^= 0x00010000;
18277 /* beq 0x10000000 bne 0x14000000
18278 blez 0x18000000 bgtz 0x1c000000 */
18279 insn
^= 0x04000000;
18287 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18289 /* Clear the and-link bit. */
18290 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18292 /* bltzal 0x04100000 bgezal 0x04110000
18293 bltzall 0x04120000 bgezall 0x04130000 */
18294 insn
&= ~0x00100000;
18297 /* Branch over the branch (if the branch was likely) or the
18298 full jump (not likely case). Compute the offset from the
18299 current instruction to branch to. */
18300 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18304 /* How many bytes in instructions we've already emitted? */
18305 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18306 /* How many bytes in instructions from here to the end? */
18307 i
= fragp
->fr_var
- i
;
18309 /* Convert to instruction count. */
18311 /* Branch counts from the next instruction. */
18314 /* Branch over the jump. */
18315 buf
= write_insn (buf
, insn
);
18318 buf
= write_insn (buf
, 0);
18320 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18322 /* beql $0, $0, 2f */
18324 /* Compute the PC offset from the current instruction to
18325 the end of the variable frag. */
18326 /* How many bytes in instructions we've already emitted? */
18327 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18328 /* How many bytes in instructions from here to the end? */
18329 i
= fragp
->fr_var
- i
;
18330 /* Convert to instruction count. */
18332 /* Don't decrement i, because we want to branch over the
18336 buf
= write_insn (buf
, insn
);
18337 buf
= write_insn (buf
, 0);
18341 if (mips_pic
== NO_PIC
)
18344 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18345 ? 0x0c000000 : 0x08000000);
18346 exp
.X_op
= O_symbol
;
18347 exp
.X_add_symbol
= fragp
->fr_symbol
;
18348 exp
.X_add_number
= fragp
->fr_offset
;
18350 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18351 FALSE
, BFD_RELOC_MIPS_JMP
);
18352 fixp
->fx_file
= fragp
->fr_file
;
18353 fixp
->fx_line
= fragp
->fr_line
;
18355 buf
= write_insn (buf
, insn
);
18359 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18361 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18362 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18363 insn
|= at
<< OP_SH_RT
;
18364 exp
.X_op
= O_symbol
;
18365 exp
.X_add_symbol
= fragp
->fr_symbol
;
18366 exp
.X_add_number
= fragp
->fr_offset
;
18368 if (fragp
->fr_offset
)
18370 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18371 exp
.X_add_number
= 0;
18374 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18375 FALSE
, BFD_RELOC_MIPS_GOT16
);
18376 fixp
->fx_file
= fragp
->fr_file
;
18377 fixp
->fx_line
= fragp
->fr_line
;
18379 buf
= write_insn (buf
, insn
);
18381 if (mips_opts
.isa
== ISA_MIPS1
)
18383 buf
= write_insn (buf
, 0);
18385 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18386 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18387 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18389 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18390 FALSE
, BFD_RELOC_LO16
);
18391 fixp
->fx_file
= fragp
->fr_file
;
18392 fixp
->fx_line
= fragp
->fr_line
;
18394 buf
= write_insn (buf
, insn
);
18397 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18401 insn
|= at
<< OP_SH_RS
;
18403 buf
= write_insn (buf
, insn
);
18407 fragp
->fr_fix
+= fragp
->fr_var
;
18408 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18412 /* Relax microMIPS branches. */
18413 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18415 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18416 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18417 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18418 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18419 bfd_boolean short_ds
;
18420 unsigned long insn
;
18424 exp
.X_op
= O_symbol
;
18425 exp
.X_add_symbol
= fragp
->fr_symbol
;
18426 exp
.X_add_number
= fragp
->fr_offset
;
18428 fragp
->fr_fix
+= fragp
->fr_var
;
18430 /* Handle 16-bit branches that fit or are forced to fit. */
18431 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18433 /* We generate a fixup instead of applying it right now,
18434 because if there is linker relaxation, we're going to
18435 need the relocations. */
18437 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18438 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18439 else if (type
== 'E')
18440 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18441 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18445 fixp
->fx_file
= fragp
->fr_file
;
18446 fixp
->fx_line
= fragp
->fr_line
;
18448 /* These relocations can have an addend that won't fit in
18450 fixp
->fx_no_overflow
= 1;
18455 /* Handle 32-bit branches that fit or are forced to fit. */
18456 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18457 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18459 /* We generate a fixup instead of applying it right now,
18460 because if there is linker relaxation, we're going to
18461 need the relocations. */
18462 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18463 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18464 fixp
->fx_file
= fragp
->fr_file
;
18465 fixp
->fx_line
= fragp
->fr_line
;
18471 /* Relax 16-bit branches to 32-bit branches. */
18474 insn
= read_compressed_insn (buf
, 2);
18476 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18477 insn
= 0x94000000; /* beq */
18478 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18480 unsigned long regno
;
18482 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18483 regno
= micromips_to_32_reg_d_map
[regno
];
18484 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18485 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18490 /* Nothing else to do, just write it out. */
18491 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18492 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18494 buf
= write_compressed_insn (buf
, insn
, 4);
18495 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18500 insn
= read_compressed_insn (buf
, 4);
18502 /* Relax 32-bit branches to a sequence of instructions. */
18503 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18504 _("Relaxed out-of-range branch into a jump"));
18506 /* Set the short-delay-slot bit. */
18507 short_ds
= al
&& (insn
& 0x02000000) != 0;
18509 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18513 /* Reverse the branch. */
18514 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18515 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18516 insn
^= 0x20000000;
18517 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18518 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18519 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18520 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18521 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18522 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18523 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18524 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18525 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18526 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18527 insn
^= 0x00400000;
18528 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18529 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18530 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18531 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18532 insn
^= 0x00200000;
18538 /* Clear the and-link and short-delay-slot bits. */
18539 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18541 /* bltzal 0x40200000 bgezal 0x40600000 */
18542 /* bltzals 0x42200000 bgezals 0x42600000 */
18543 insn
&= ~0x02200000;
18546 /* Make a label at the end for use with the branch. */
18547 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18548 micromips_label_inc ();
18549 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18551 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18555 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18556 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18557 fixp
->fx_file
= fragp
->fr_file
;
18558 fixp
->fx_line
= fragp
->fr_line
;
18560 /* Branch over the jump. */
18561 buf
= write_compressed_insn (buf
, insn
, 4);
18564 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18567 if (mips_pic
== NO_PIC
)
18569 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18571 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18572 insn
= al
? jal
: 0xd4000000;
18574 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18575 BFD_RELOC_MICROMIPS_JMP
);
18576 fixp
->fx_file
= fragp
->fr_file
;
18577 fixp
->fx_line
= fragp
->fr_line
;
18579 buf
= write_compressed_insn (buf
, insn
, 4);
18582 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18586 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18587 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18588 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18590 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18591 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18592 insn
|= at
<< MICROMIPSOP_SH_RT
;
18594 if (exp
.X_add_number
)
18596 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18597 exp
.X_add_number
= 0;
18600 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18601 BFD_RELOC_MICROMIPS_GOT16
);
18602 fixp
->fx_file
= fragp
->fr_file
;
18603 fixp
->fx_line
= fragp
->fr_line
;
18605 buf
= write_compressed_insn (buf
, insn
, 4);
18607 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18608 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18609 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18611 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18612 BFD_RELOC_MICROMIPS_LO16
);
18613 fixp
->fx_file
= fragp
->fr_file
;
18614 fixp
->fx_line
= fragp
->fr_line
;
18616 buf
= write_compressed_insn (buf
, insn
, 4);
18618 /* jr/jrc/jalr/jalrs $at */
18619 insn
= al
? jalr
: jr
;
18620 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18622 buf
= write_compressed_insn (buf
, insn
, 2);
18625 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18629 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18632 const struct mips16_immed_operand
*op
;
18635 unsigned int user_length
, length
;
18636 unsigned long insn
;
18639 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18640 op
= mips16_immed_operands
;
18641 while (op
->type
!= type
)
18644 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18645 val
= resolve_symbol_value (fragp
->fr_symbol
);
18650 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18652 /* The rules for the base address of a PC relative reloc are
18653 complicated; see mips16_extended_frag. */
18654 if (type
== 'p' || type
== 'q')
18659 /* Ignore the low bit in the target, since it will be
18660 set for a text label. */
18661 if ((val
& 1) != 0)
18664 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18666 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18669 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18672 /* Make sure the section winds up with the alignment we have
18675 record_alignment (asec
, op
->shift
);
18679 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18680 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18681 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18682 _("extended instruction in delay slot"));
18684 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18686 insn
= read_compressed_insn (buf
, 2);
18688 insn
|= MIPS16_EXTEND
;
18690 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18692 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18697 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18698 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18700 length
= (ext
? 4 : 2);
18701 gas_assert (mips16_opcode_length (insn
) == length
);
18702 write_compressed_insn (buf
, insn
, length
);
18703 fragp
->fr_fix
+= length
;
18707 relax_substateT subtype
= fragp
->fr_subtype
;
18708 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18709 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18713 first
= RELAX_FIRST (subtype
);
18714 second
= RELAX_SECOND (subtype
);
18715 fixp
= (fixS
*) fragp
->fr_opcode
;
18717 /* If the delay slot chosen does not match the size of the instruction,
18718 then emit a warning. */
18719 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18720 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18725 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18726 | RELAX_DELAY_SLOT_SIZE_FIRST
18727 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18728 msg
= macro_warning (s
);
18730 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18734 /* Possibly emit a warning if we've chosen the longer option. */
18735 if (use_second
== second_longer
)
18741 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18742 msg
= macro_warning (s
);
18744 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18748 /* Go through all the fixups for the first sequence. Disable them
18749 (by marking them as done) if we're going to use the second
18750 sequence instead. */
18752 && fixp
->fx_frag
== fragp
18753 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18755 if (subtype
& RELAX_USE_SECOND
)
18757 fixp
= fixp
->fx_next
;
18760 /* Go through the fixups for the second sequence. Disable them if
18761 we're going to use the first sequence, otherwise adjust their
18762 addresses to account for the relaxation. */
18763 while (fixp
&& fixp
->fx_frag
== fragp
)
18765 if (subtype
& RELAX_USE_SECOND
)
18766 fixp
->fx_where
-= first
;
18769 fixp
= fixp
->fx_next
;
18772 /* Now modify the frag contents. */
18773 if (subtype
& RELAX_USE_SECOND
)
18777 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18778 memmove (start
, start
+ first
, second
);
18779 fragp
->fr_fix
-= first
;
18782 fragp
->fr_fix
-= second
;
18788 /* This function is called after the relocs have been generated.
18789 We've been storing mips16 text labels as odd. Here we convert them
18790 back to even for the convenience of the debugger. */
18793 mips_frob_file_after_relocs (void)
18796 unsigned int count
, i
;
18801 syms
= bfd_get_outsymbols (stdoutput
);
18802 count
= bfd_get_symcount (stdoutput
);
18803 for (i
= 0; i
< count
; i
++, syms
++)
18804 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18805 && ((*syms
)->value
& 1) != 0)
18807 (*syms
)->value
&= ~1;
18808 /* If the symbol has an odd size, it was probably computed
18809 incorrectly, so adjust that as well. */
18810 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18811 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18817 /* This function is called whenever a label is defined, including fake
18818 labels instantiated off the dot special symbol. It is used when
18819 handling branch delays; if a branch has a label, we assume we cannot
18820 move it. This also bumps the value of the symbol by 1 in compressed
18824 mips_record_label (symbolS
*sym
)
18826 segment_info_type
*si
= seg_info (now_seg
);
18827 struct insn_label_list
*l
;
18829 if (free_insn_labels
== NULL
)
18830 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18833 l
= free_insn_labels
;
18834 free_insn_labels
= l
->next
;
18838 l
->next
= si
->label_list
;
18839 si
->label_list
= l
;
18842 /* This function is called as tc_frob_label() whenever a label is defined
18843 and adds a DWARF-2 record we only want for true labels. */
18846 mips_define_label (symbolS
*sym
)
18848 mips_record_label (sym
);
18850 dwarf2_emit_label (sym
);
18854 /* This function is called by tc_new_dot_label whenever a new dot symbol
18858 mips_add_dot_label (symbolS
*sym
)
18860 mips_record_label (sym
);
18861 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18862 mips_compressed_mark_label (sym
);
18865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18867 /* Some special processing for a MIPS ELF file. */
18870 mips_elf_final_processing (void)
18872 /* Write out the register information. */
18873 if (mips_abi
!= N64_ABI
)
18877 s
.ri_gprmask
= mips_gprmask
;
18878 s
.ri_cprmask
[0] = mips_cprmask
[0];
18879 s
.ri_cprmask
[1] = mips_cprmask
[1];
18880 s
.ri_cprmask
[2] = mips_cprmask
[2];
18881 s
.ri_cprmask
[3] = mips_cprmask
[3];
18882 /* The gp_value field is set by the MIPS ELF backend. */
18884 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18885 ((Elf32_External_RegInfo
*)
18886 mips_regmask_frag
));
18890 Elf64_Internal_RegInfo s
;
18892 s
.ri_gprmask
= mips_gprmask
;
18894 s
.ri_cprmask
[0] = mips_cprmask
[0];
18895 s
.ri_cprmask
[1] = mips_cprmask
[1];
18896 s
.ri_cprmask
[2] = mips_cprmask
[2];
18897 s
.ri_cprmask
[3] = mips_cprmask
[3];
18898 /* The gp_value field is set by the MIPS ELF backend. */
18900 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18901 ((Elf64_External_RegInfo
*)
18902 mips_regmask_frag
));
18905 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18906 sort of BFD interface for this. */
18907 if (mips_any_noreorder
)
18908 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18909 if (mips_pic
!= NO_PIC
)
18911 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18912 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18915 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18917 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18918 defined at present; this might need to change in future. */
18919 if (file_ase_mips16
)
18920 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18921 if (file_ase_micromips
)
18922 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18923 if (file_ase
& ASE_MDMX
)
18924 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18926 /* Set the MIPS ELF ABI flags. */
18927 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18928 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18929 else if (mips_abi
== O64_ABI
)
18930 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18931 else if (mips_abi
== EABI_ABI
)
18933 if (!file_mips_gp32
)
18934 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18936 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18938 else if (mips_abi
== N32_ABI
)
18939 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18941 /* Nothing to do for N64_ABI. */
18943 if (mips_32bitmode
)
18944 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18946 #if 0 /* XXX FIXME */
18947 /* 32 bit code with 64 bit FP registers. */
18948 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18949 elf_elfheader (stdoutput
)->e_flags
|= ???;
18953 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18955 typedef struct proc
{
18957 symbolS
*func_end_sym
;
18958 unsigned long reg_mask
;
18959 unsigned long reg_offset
;
18960 unsigned long fpreg_mask
;
18961 unsigned long fpreg_offset
;
18962 unsigned long frame_offset
;
18963 unsigned long frame_reg
;
18964 unsigned long pc_reg
;
18967 static procS cur_proc
;
18968 static procS
*cur_proc_ptr
;
18969 static int numprocs
;
18971 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18972 as "2", and a normal nop as "0". */
18974 #define NOP_OPCODE_MIPS 0
18975 #define NOP_OPCODE_MIPS16 1
18976 #define NOP_OPCODE_MICROMIPS 2
18979 mips_nop_opcode (void)
18981 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18982 return NOP_OPCODE_MICROMIPS
;
18983 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18984 return NOP_OPCODE_MIPS16
;
18986 return NOP_OPCODE_MIPS
;
18989 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18990 32-bit microMIPS NOPs here (if applicable). */
18993 mips_handle_align (fragS
*fragp
)
18997 int bytes
, size
, excess
;
19000 if (fragp
->fr_type
!= rs_align_code
)
19003 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19005 switch (nop_opcode
)
19007 case NOP_OPCODE_MICROMIPS
:
19008 opcode
= micromips_nop32_insn
.insn_opcode
;
19011 case NOP_OPCODE_MIPS16
:
19012 opcode
= mips16_nop_insn
.insn_opcode
;
19015 case NOP_OPCODE_MIPS
:
19017 opcode
= nop_insn
.insn_opcode
;
19022 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19023 excess
= bytes
% size
;
19025 /* Handle the leading part if we're not inserting a whole number of
19026 instructions, and make it the end of the fixed part of the frag.
19027 Try to fit in a short microMIPS NOP if applicable and possible,
19028 and use zeroes otherwise. */
19029 gas_assert (excess
< 4);
19030 fragp
->fr_fix
+= excess
;
19035 /* Fall through. */
19037 if (nop_opcode
== NOP_OPCODE_MICROMIPS
)
19039 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19043 /* Fall through. */
19046 /* Fall through. */
19051 md_number_to_chars (p
, opcode
, size
);
19052 fragp
->fr_var
= size
;
19056 md_obj_begin (void)
19063 /* Check for premature end, nesting errors, etc. */
19065 as_warn (_("missing .end at end of assembly"));
19074 if (*input_line_pointer
== '-')
19076 ++input_line_pointer
;
19079 if (!ISDIGIT (*input_line_pointer
))
19080 as_bad (_("expected simple number"));
19081 if (input_line_pointer
[0] == '0')
19083 if (input_line_pointer
[1] == 'x')
19085 input_line_pointer
+= 2;
19086 while (ISXDIGIT (*input_line_pointer
))
19089 val
|= hex_value (*input_line_pointer
++);
19091 return negative
? -val
: val
;
19095 ++input_line_pointer
;
19096 while (ISDIGIT (*input_line_pointer
))
19099 val
|= *input_line_pointer
++ - '0';
19101 return negative
? -val
: val
;
19104 if (!ISDIGIT (*input_line_pointer
))
19106 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19107 *input_line_pointer
, *input_line_pointer
);
19108 as_warn (_("invalid number"));
19111 while (ISDIGIT (*input_line_pointer
))
19114 val
+= *input_line_pointer
++ - '0';
19116 return negative
? -val
: val
;
19119 /* The .file directive; just like the usual .file directive, but there
19120 is an initial number which is the ECOFF file index. In the non-ECOFF
19121 case .file implies DWARF-2. */
19124 s_mips_file (int x ATTRIBUTE_UNUSED
)
19126 static int first_file_directive
= 0;
19128 if (ECOFF_DEBUGGING
)
19137 filename
= dwarf2_directive_file (0);
19139 /* Versions of GCC up to 3.1 start files with a ".file"
19140 directive even for stabs output. Make sure that this
19141 ".file" is handled. Note that you need a version of GCC
19142 after 3.1 in order to support DWARF-2 on MIPS. */
19143 if (filename
!= NULL
&& ! first_file_directive
)
19145 (void) new_logical_line (filename
, -1);
19146 s_app_file_string (filename
, 0);
19148 first_file_directive
= 1;
19152 /* The .loc directive, implying DWARF-2. */
19155 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19157 if (!ECOFF_DEBUGGING
)
19158 dwarf2_directive_loc (0);
19161 /* The .end directive. */
19164 s_mips_end (int x ATTRIBUTE_UNUSED
)
19168 /* Following functions need their own .frame and .cprestore directives. */
19169 mips_frame_reg_valid
= 0;
19170 mips_cprestore_valid
= 0;
19172 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19175 demand_empty_rest_of_line ();
19180 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19181 as_warn (_(".end not in text section"));
19185 as_warn (_(".end directive without a preceding .ent directive."));
19186 demand_empty_rest_of_line ();
19192 gas_assert (S_GET_NAME (p
));
19193 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19194 as_warn (_(".end symbol does not match .ent symbol."));
19196 if (debug_type
== DEBUG_STABS
)
19197 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19201 as_warn (_(".end directive missing or unknown symbol"));
19204 /* Create an expression to calculate the size of the function. */
19205 if (p
&& cur_proc_ptr
)
19207 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19208 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19211 exp
->X_op
= O_subtract
;
19212 exp
->X_add_symbol
= symbol_temp_new_now ();
19213 exp
->X_op_symbol
= p
;
19214 exp
->X_add_number
= 0;
19216 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19219 /* Generate a .pdr section. */
19220 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
19222 segT saved_seg
= now_seg
;
19223 subsegT saved_subseg
= now_subseg
;
19227 #ifdef md_flush_pending_output
19228 md_flush_pending_output ();
19231 gas_assert (pdr_seg
);
19232 subseg_set (pdr_seg
, 0);
19234 /* Write the symbol. */
19235 exp
.X_op
= O_symbol
;
19236 exp
.X_add_symbol
= p
;
19237 exp
.X_add_number
= 0;
19238 emit_expr (&exp
, 4);
19240 fragp
= frag_more (7 * 4);
19242 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19243 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19244 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19245 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19246 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19247 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19248 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19250 subseg_set (saved_seg
, saved_subseg
);
19252 #endif /* OBJ_ELF */
19254 cur_proc_ptr
= NULL
;
19257 /* The .aent and .ent directives. */
19260 s_mips_ent (int aent
)
19264 symbolP
= get_symbol ();
19265 if (*input_line_pointer
== ',')
19266 ++input_line_pointer
;
19267 SKIP_WHITESPACE ();
19268 if (ISDIGIT (*input_line_pointer
)
19269 || *input_line_pointer
== '-')
19272 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19273 as_warn (_(".ent or .aent not in text section."));
19275 if (!aent
&& cur_proc_ptr
)
19276 as_warn (_("missing .end"));
19280 /* This function needs its own .frame and .cprestore directives. */
19281 mips_frame_reg_valid
= 0;
19282 mips_cprestore_valid
= 0;
19284 cur_proc_ptr
= &cur_proc
;
19285 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19287 cur_proc_ptr
->func_sym
= symbolP
;
19291 if (debug_type
== DEBUG_STABS
)
19292 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19293 S_GET_NAME (symbolP
));
19296 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19298 demand_empty_rest_of_line ();
19301 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19302 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19303 s_mips_frame is used so that we can set the PDR information correctly.
19304 We can't use the ecoff routines because they make reference to the ecoff
19305 symbol table (in the mdebug section). */
19308 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19311 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19315 if (cur_proc_ptr
== (procS
*) NULL
)
19317 as_warn (_(".frame outside of .ent"));
19318 demand_empty_rest_of_line ();
19322 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19324 SKIP_WHITESPACE ();
19325 if (*input_line_pointer
++ != ','
19326 || get_absolute_expression_and_terminator (&val
) != ',')
19328 as_warn (_("Bad .frame directive"));
19329 --input_line_pointer
;
19330 demand_empty_rest_of_line ();
19334 cur_proc_ptr
->frame_offset
= val
;
19335 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19337 demand_empty_rest_of_line ();
19340 #endif /* OBJ_ELF */
19344 /* The .fmask and .mask directives. If the mdebug section is present
19345 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19346 embedded targets, s_mips_mask is used so that we can set the PDR
19347 information correctly. We can't use the ecoff routines because they
19348 make reference to the ecoff symbol table (in the mdebug section). */
19351 s_mips_mask (int reg_type
)
19354 if (IS_ELF
&& !ECOFF_DEBUGGING
)
19358 if (cur_proc_ptr
== (procS
*) NULL
)
19360 as_warn (_(".mask/.fmask outside of .ent"));
19361 demand_empty_rest_of_line ();
19365 if (get_absolute_expression_and_terminator (&mask
) != ',')
19367 as_warn (_("Bad .mask/.fmask directive"));
19368 --input_line_pointer
;
19369 demand_empty_rest_of_line ();
19373 off
= get_absolute_expression ();
19375 if (reg_type
== 'F')
19377 cur_proc_ptr
->fpreg_mask
= mask
;
19378 cur_proc_ptr
->fpreg_offset
= off
;
19382 cur_proc_ptr
->reg_mask
= mask
;
19383 cur_proc_ptr
->reg_offset
= off
;
19386 demand_empty_rest_of_line ();
19389 #endif /* OBJ_ELF */
19390 s_ignore (reg_type
);
19393 /* A table describing all the processors gas knows about. Names are
19394 matched in the order listed.
19396 To ease comparison, please keep this table in the same order as
19397 gcc's mips_cpu_info_table[]. */
19398 static const struct mips_cpu_info mips_cpu_info_table
[] =
19400 /* Entries for generic ISAs */
19401 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19402 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19403 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19404 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19405 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19406 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19407 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19408 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19409 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19412 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19413 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19414 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19417 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19420 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19421 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19422 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19423 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19424 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19425 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19426 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19427 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19428 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19429 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19430 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19431 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19432 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19433 /* ST Microelectronics Loongson 2E and 2F cores */
19434 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19435 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19438 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19439 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19440 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19441 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19442 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19443 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19444 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19445 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19446 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19447 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19448 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19449 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19450 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19451 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19452 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19455 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19456 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19457 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19458 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19460 /* MIPS 32 Release 2 */
19461 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19462 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19463 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19464 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19465 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19466 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19467 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19468 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19469 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19470 ISA_MIPS32R2
, CPU_MIPS32R2
},
19471 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19472 ISA_MIPS32R2
, CPU_MIPS32R2
},
19473 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19474 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19475 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19476 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19477 /* Deprecated forms of the above. */
19478 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19479 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19480 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19481 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19482 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19483 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19484 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19485 /* Deprecated forms of the above. */
19486 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19487 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19488 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19489 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19490 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19491 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19492 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19493 /* Deprecated forms of the above. */
19494 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19495 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19496 /* 34Kn is a 34kc without DSP. */
19497 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19498 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19499 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19500 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19501 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19502 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19503 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19504 /* Deprecated forms of the above. */
19505 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19506 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19507 /* 1004K cores are multiprocessor versions of the 34K. */
19508 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19509 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19510 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19511 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19514 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19515 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19516 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19517 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19519 /* Broadcom SB-1 CPU core */
19520 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19521 /* Broadcom SB-1A CPU core */
19522 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19524 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19526 /* MIPS 64 Release 2 */
19528 /* Cavium Networks Octeon CPU core */
19529 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19530 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19531 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19534 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19537 XLP is mostly like XLR, with the prominent exception that it is
19538 MIPS64R2 rather than MIPS64. */
19539 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19542 { NULL
, 0, 0, 0, 0 }
19546 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19547 with a final "000" replaced by "k". Ignore case.
19549 Note: this function is shared between GCC and GAS. */
19552 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19554 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19555 given
++, canonical
++;
19557 return ((*given
== 0 && *canonical
== 0)
19558 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19562 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19563 CPU name. We've traditionally allowed a lot of variation here.
19565 Note: this function is shared between GCC and GAS. */
19568 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19570 /* First see if the name matches exactly, or with a final "000"
19571 turned into "k". */
19572 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19575 /* If not, try comparing based on numerical designation alone.
19576 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19577 if (TOLOWER (*given
) == 'r')
19579 if (!ISDIGIT (*given
))
19582 /* Skip over some well-known prefixes in the canonical name,
19583 hoping to find a number there too. */
19584 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19586 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19588 else if (TOLOWER (canonical
[0]) == 'r')
19591 return mips_strict_matching_cpu_name_p (canonical
, given
);
19595 /* Parse an option that takes the name of a processor as its argument.
19596 OPTION is the name of the option and CPU_STRING is the argument.
19597 Return the corresponding processor enumeration if the CPU_STRING is
19598 recognized, otherwise report an error and return null.
19600 A similar function exists in GCC. */
19602 static const struct mips_cpu_info
*
19603 mips_parse_cpu (const char *option
, const char *cpu_string
)
19605 const struct mips_cpu_info
*p
;
19607 /* 'from-abi' selects the most compatible architecture for the given
19608 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19609 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19610 version. Look first at the -mgp options, if given, otherwise base
19611 the choice on MIPS_DEFAULT_64BIT.
19613 Treat NO_ABI like the EABIs. One reason to do this is that the
19614 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19615 architecture. This code picks MIPS I for 'mips' and MIPS III for
19616 'mips64', just as we did in the days before 'from-abi'. */
19617 if (strcasecmp (cpu_string
, "from-abi") == 0)
19619 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19620 return mips_cpu_info_from_isa (ISA_MIPS1
);
19622 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19623 return mips_cpu_info_from_isa (ISA_MIPS3
);
19625 if (file_mips_gp32
>= 0)
19626 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19628 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19633 /* 'default' has traditionally been a no-op. Probably not very useful. */
19634 if (strcasecmp (cpu_string
, "default") == 0)
19637 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19638 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19641 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19645 /* Return the canonical processor information for ISA (a member of the
19646 ISA_MIPS* enumeration). */
19648 static const struct mips_cpu_info
*
19649 mips_cpu_info_from_isa (int isa
)
19653 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19654 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19655 && isa
== mips_cpu_info_table
[i
].isa
)
19656 return (&mips_cpu_info_table
[i
]);
19661 static const struct mips_cpu_info
*
19662 mips_cpu_info_from_arch (int arch
)
19666 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19667 if (arch
== mips_cpu_info_table
[i
].cpu
)
19668 return (&mips_cpu_info_table
[i
]);
19674 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19678 fprintf (stream
, "%24s", "");
19683 fprintf (stream
, ", ");
19687 if (*col_p
+ strlen (string
) > 72)
19689 fprintf (stream
, "\n%24s", "");
19693 fprintf (stream
, "%s", string
);
19694 *col_p
+= strlen (string
);
19700 md_show_usage (FILE *stream
)
19705 fprintf (stream
, _("\
19707 -EB generate big endian output\n\
19708 -EL generate little endian output\n\
19709 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19710 -G NUM allow referencing objects up to NUM bytes\n\
19711 implicitly with the gp register [default 8]\n"));
19712 fprintf (stream
, _("\
19713 -mips1 generate MIPS ISA I instructions\n\
19714 -mips2 generate MIPS ISA II instructions\n\
19715 -mips3 generate MIPS ISA III instructions\n\
19716 -mips4 generate MIPS ISA IV instructions\n\
19717 -mips5 generate MIPS ISA V instructions\n\
19718 -mips32 generate MIPS32 ISA instructions\n\
19719 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19720 -mips64 generate MIPS64 ISA instructions\n\
19721 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19722 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19726 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19727 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19728 show (stream
, "from-abi", &column
, &first
);
19729 fputc ('\n', stream
);
19731 fprintf (stream
, _("\
19732 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19733 -no-mCPU don't generate code specific to CPU.\n\
19734 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19738 show (stream
, "3900", &column
, &first
);
19739 show (stream
, "4010", &column
, &first
);
19740 show (stream
, "4100", &column
, &first
);
19741 show (stream
, "4650", &column
, &first
);
19742 fputc ('\n', stream
);
19744 fprintf (stream
, _("\
19745 -mips16 generate mips16 instructions\n\
19746 -no-mips16 do not generate mips16 instructions\n"));
19747 fprintf (stream
, _("\
19748 -mmicromips generate microMIPS instructions\n\
19749 -mno-micromips do not generate microMIPS instructions\n"));
19750 fprintf (stream
, _("\
19751 -msmartmips generate smartmips instructions\n\
19752 -mno-smartmips do not generate smartmips instructions\n"));
19753 fprintf (stream
, _("\
19754 -mdsp generate DSP instructions\n\
19755 -mno-dsp do not generate DSP instructions\n"));
19756 fprintf (stream
, _("\
19757 -mdspr2 generate DSP R2 instructions\n\
19758 -mno-dspr2 do not generate DSP R2 instructions\n"));
19759 fprintf (stream
, _("\
19760 -mmt generate MT instructions\n\
19761 -mno-mt do not generate MT instructions\n"));
19762 fprintf (stream
, _("\
19763 -mmcu generate MCU instructions\n\
19764 -mno-mcu do not generate MCU instructions\n"));
19765 fprintf (stream
, _("\
19766 -mvirt generate Virtualization instructions\n\
19767 -mno-virt do not generate Virtualization instructions\n"));
19768 fprintf (stream
, _("\
19769 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19770 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19771 -mfix-vr4120 work around certain VR4120 errata\n\
19772 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19773 -mfix-24k insert a nop after ERET and DERET instructions\n\
19774 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19775 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19776 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19777 -msym32 assume all symbols have 32-bit values\n\
19778 -O0 remove unneeded NOPs, do not swap branches\n\
19779 -O remove unneeded NOPs and swap branches\n\
19780 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19781 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19782 fprintf (stream
, _("\
19783 -mhard-float allow floating-point instructions\n\
19784 -msoft-float do not allow floating-point instructions\n\
19785 -msingle-float only allow 32-bit floating-point operations\n\
19786 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19787 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19788 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19791 fprintf (stream
, _("\
19792 -KPIC, -call_shared generate SVR4 position independent code\n\
19793 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19794 -mvxworks-pic generate VxWorks position independent code\n\
19795 -non_shared do not generate code that can operate with DSOs\n\
19796 -xgot assume a 32 bit GOT\n\
19797 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19798 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19799 position dependent (non shared) code\n\
19800 -mabi=ABI create ABI conformant object file for:\n"));
19804 show (stream
, "32", &column
, &first
);
19805 show (stream
, "o64", &column
, &first
);
19806 show (stream
, "n32", &column
, &first
);
19807 show (stream
, "64", &column
, &first
);
19808 show (stream
, "eabi", &column
, &first
);
19810 fputc ('\n', stream
);
19812 fprintf (stream
, _("\
19813 -32 create o32 ABI object file (default)\n\
19814 -n32 create n32 ABI object file\n\
19815 -64 create 64 ABI object file\n"));
19821 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19823 if (HAVE_64BIT_SYMBOLS
)
19824 return dwarf2_format_64bit_irix
;
19826 return dwarf2_format_32bit
;
19831 mips_dwarf2_addr_size (void)
19833 if (HAVE_64BIT_OBJECTS
)
19839 /* Standard calling conventions leave the CFA at SP on entry. */
19841 mips_cfi_frame_initial_instructions (void)
19843 cfi_add_CFA_def_cfa_register (SP
);
19847 tc_mips_regname_to_dw2regnum (char *regname
)
19849 unsigned int regnum
= -1;
19852 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))