1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int auto_align
= 1;
260 /* When outputting SVR4 PIC code, the assembler needs to know the
261 offset in the stack frame from which to restore the $gp register.
262 This is set by the .cprestore pseudo-op, and saved in this
264 static offsetT mips_cprestore_offset
= -1;
266 /* This is the register which holds the stack frame, as set by the
267 .frame pseudo-op. This is needed to implement .cprestore. */
268 static int mips_frame_reg
= SP
;
270 /* To output NOP instructions correctly, we need to keep information
271 about the previous two instructions. */
273 /* Whether we are optimizing. The default value of 2 means to remove
274 unneeded NOPs and swap branch instructions when possible. A value
275 of 1 means to not swap branches. A value of 0 means to always
277 static int mips_optimize
= 2;
279 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
280 equivalent to seeing no -g option at all. */
281 static int mips_debug
= 0;
283 /* The previous instruction. */
284 static struct mips_cl_insn prev_insn
;
286 /* The instruction before prev_insn. */
287 static struct mips_cl_insn prev_prev_insn
;
289 /* If we don't want information for prev_insn or prev_prev_insn, we
290 point the insn_mo field at this dummy integer. */
291 static const struct mips_opcode dummy_opcode
= { 0 };
293 /* Non-zero if prev_insn is valid. */
294 static int prev_insn_valid
;
296 /* The frag for the previous instruction. */
297 static struct frag
*prev_insn_frag
;
299 /* The offset into prev_insn_frag for the previous instruction. */
300 static long prev_insn_where
;
302 /* The reloc type for the previous instruction, if any. */
303 static bfd_reloc_code_real_type prev_insn_reloc_type
;
305 /* The reloc for the previous instruction, if any. */
306 static fixS
*prev_insn_fixp
;
308 /* Non-zero if the previous instruction was in a delay slot. */
309 static int prev_insn_is_delay_slot
;
311 /* Non-zero if the previous instruction was in a .set noreorder. */
312 static int prev_insn_unreordered
;
314 /* Non-zero if the previous instruction uses an extend opcode (if
316 static int prev_insn_extended
;
318 /* Non-zero if the previous previous instruction was in a .set
320 static int prev_prev_insn_unreordered
;
322 /* For ECOFF and ELF, relocations against symbols are done in two
323 parts, with a HI relocation and a LO relocation. Each relocation
324 has only 16 bits of space to store an addend. This means that in
325 order for the linker to handle carries correctly, it must be able
326 to locate both the HI and the LO relocation. This means that the
327 relocations must appear in order in the relocation table.
329 In order to implement this, we keep track of each unmatched HI
330 relocation. We then sort them so that they immediately precede the
331 corresponding LO relocation. */
336 struct mips_hi_fixup
*next
;
339 /* The section this fixup is in. */
343 /* The list of unmatched HI relocs. */
345 static struct mips_hi_fixup
*mips_hi_fixup_list
;
347 /* Map normal MIPS register numbers to mips16 register numbers. */
349 #define X ILLEGAL_REG
350 static const int mips32_to_16_reg_map
[] =
352 X
, X
, 2, 3, 4, 5, 6, 7,
353 X
, X
, X
, X
, X
, X
, X
, X
,
354 0, 1, X
, X
, X
, X
, X
, X
,
355 X
, X
, X
, X
, X
, X
, X
, X
359 /* Map mips16 register numbers to normal MIPS register numbers. */
361 static const int mips16_to_32_reg_map
[] =
363 16, 17, 2, 3, 4, 5, 6, 7
366 /* Since the MIPS does not have multiple forms of PC relative
367 instructions, we do not have to do relaxing as is done on other
368 platforms. However, we do have to handle GP relative addressing
369 correctly, which turns out to be a similar problem.
371 Every macro that refers to a symbol can occur in (at least) two
372 forms, one with GP relative addressing and one without. For
373 example, loading a global variable into a register generally uses
374 a macro instruction like this:
376 If i can be addressed off the GP register (this is true if it is in
377 the .sbss or .sdata section, or if it is known to be smaller than
378 the -G argument) this will generate the following instruction:
380 This instruction will use a GPREL reloc. If i can not be addressed
381 off the GP register, the following instruction sequence will be used:
384 In this case the first instruction will have a HI16 reloc, and the
385 second reloc will have a LO16 reloc. Both relocs will be against
388 The issue here is that we may not know whether i is GP addressable
389 until after we see the instruction that uses it. Therefore, we
390 want to be able to choose the final instruction sequence only at
391 the end of the assembly. This is similar to the way other
392 platforms choose the size of a PC relative instruction only at the
395 When generating position independent code we do not use GP
396 addressing in quite the same way, but the issue still arises as
397 external symbols and local symbols must be handled differently.
399 We handle these issues by actually generating both possible
400 instruction sequences. The longer one is put in a frag_var with
401 type rs_machine_dependent. We encode what to do with the frag in
402 the subtype field. We encode (1) the number of existing bytes to
403 replace, (2) the number of new bytes to use, (3) the offset from
404 the start of the existing bytes to the first reloc we must generate
405 (that is, the offset is applied from the start of the existing
406 bytes after they are replaced by the new bytes, if any), (4) the
407 offset from the start of the existing bytes to the second reloc,
408 (5) whether a third reloc is needed (the third reloc is always four
409 bytes after the second reloc), and (6) whether to warn if this
410 variant is used (this is sometimes needed if .set nomacro or .set
411 noat is in effect). All these numbers are reasonably small.
413 Generating two instruction sequences must be handled carefully to
414 ensure that delay slots are handled correctly. Fortunately, there
415 are a limited number of cases. When the second instruction
416 sequence is generated, append_insn is directed to maintain the
417 existing delay slot information, so it continues to apply to any
418 code after the second instruction sequence. This means that the
419 second instruction sequence must not impose any requirements not
420 required by the first instruction sequence.
422 These variant frags are then handled in functions called by the
423 machine independent code. md_estimate_size_before_relax returns
424 the final size of the frag. md_convert_frag sets up the final form
425 of the frag. tc_gen_reloc adjust the first reloc and adds a second
427 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
431 | (((reloc1) + 64) << 9) \
432 | (((reloc2) + 64) << 2) \
433 | ((reloc3) ? (1 << 1) : 0) \
435 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
436 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
437 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
438 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
439 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
440 #define RELAX_WARN(i) ((i) & 1)
442 /* For mips16 code, we use an entirely different form of relaxation.
443 mips16 supports two versions of most instructions which take
444 immediate values: a small one which takes some small value, and a
445 larger one which takes a 16 bit value. Since branches also follow
446 this pattern, relaxing these values is required.
448 We can assemble both mips16 and normal MIPS code in a single
449 object. Therefore, we need to support this type of relaxation at
450 the same time that we support the relaxation described above. We
451 use the high bit of the subtype field to distinguish these cases.
453 The information we store for this type of relaxation is the
454 argument code found in the opcode file for this relocation, whether
455 the user explicitly requested a small or extended form, and whether
456 the relocation is in a jump or jal delay slot. That tells us the
457 size of the value, and how it should be stored. We also store
458 whether the fragment is considered to be extended or not. We also
459 store whether this is known to be a branch to a different section,
460 whether we have tried to relax this frag yet, and whether we have
461 ever extended a PC relative fragment because of a shift count. */
462 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
465 | ((small) ? 0x100 : 0) \
466 | ((ext) ? 0x200 : 0) \
467 | ((dslot) ? 0x400 : 0) \
468 | ((jal_dslot) ? 0x800 : 0))
469 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
470 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
471 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
472 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
473 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
474 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
475 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
476 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
477 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
478 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
479 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
480 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
482 /* Prototypes for static functions. */
485 #define internalError() \
486 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
488 #define internalError() as_fatal ("MIPS internal Error");
491 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
493 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
494 unsigned int reg
, enum mips_regclass
class));
495 static int reg_needs_delay
PARAMS ((int));
496 static void append_insn
PARAMS ((char *place
,
497 struct mips_cl_insn
* ip
,
499 bfd_reloc_code_real_type r
,
501 static void mips_no_prev_insn
PARAMS ((void));
502 static void mips_emit_delays
PARAMS ((boolean
));
504 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
505 const char *name
, const char *fmt
,
508 static void macro_build ();
510 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
511 const char *, const char *,
513 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
514 expressionS
* ep
, int regnum
));
515 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
516 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
518 static void load_register
PARAMS ((int *, int, expressionS
*, int));
519 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
520 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
521 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
522 #ifdef LOSING_COMPILER
523 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
525 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
526 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
527 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
528 boolean
, boolean
, unsigned long *,
529 boolean
*, unsigned short *));
530 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
531 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
532 static symbolS
*get_symbol
PARAMS ((void));
533 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
534 static void s_align
PARAMS ((int));
535 static void s_change_sec
PARAMS ((int));
536 static void s_cons
PARAMS ((int));
537 static void s_float_cons
PARAMS ((int));
538 static void s_mips_globl
PARAMS ((int));
539 static void s_option
PARAMS ((int));
540 static void s_mipsset
PARAMS ((int));
541 static void s_abicalls
PARAMS ((int));
542 static void s_cpload
PARAMS ((int));
543 static void s_cprestore
PARAMS ((int));
544 static void s_gpword
PARAMS ((int));
545 static void s_cpadd
PARAMS ((int));
546 static void md_obj_begin
PARAMS ((void));
547 static void md_obj_end
PARAMS ((void));
548 static long get_number
PARAMS ((void));
549 static void s_ent
PARAMS ((int));
550 static void s_mipsend
PARAMS ((int));
551 static void s_file
PARAMS ((int));
552 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
556 The following pseudo-ops from the Kane and Heinrich MIPS book
557 should be defined here, but are currently unsupported: .alias,
558 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
560 The following pseudo-ops from the Kane and Heinrich MIPS book are
561 specific to the type of debugging information being generated, and
562 should be defined by the object format: .aent, .begin, .bend,
563 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
566 The following pseudo-ops from the Kane and Heinrich MIPS book are
567 not MIPS CPU specific, but are also not specific to the object file
568 format. This file is probably the best place to define them, but
569 they are not currently supported: .asm0, .endr, .lab, .repeat,
570 .struct, .weakext. */
572 static const pseudo_typeS mips_pseudo_table
[] =
574 /* MIPS specific pseudo-ops. */
575 {"option", s_option
, 0},
576 {"set", s_mipsset
, 0},
577 {"rdata", s_change_sec
, 'r'},
578 {"sdata", s_change_sec
, 's'},
579 {"livereg", s_ignore
, 0},
580 {"abicalls", s_abicalls
, 0},
581 {"cpload", s_cpload
, 0},
582 {"cprestore", s_cprestore
, 0},
583 {"gpword", s_gpword
, 0},
584 {"cpadd", s_cpadd
, 0},
586 /* Relatively generic pseudo-ops that happen to be used on MIPS
588 {"asciiz", stringer
, 1},
589 {"bss", s_change_sec
, 'b'},
592 {"dword", s_cons
, 3},
594 /* These pseudo-ops are defined in read.c, but must be overridden
595 here for one reason or another. */
596 {"align", s_align
, 0},
598 {"data", s_change_sec
, 'd'},
599 {"double", s_float_cons
, 'd'},
600 {"float", s_float_cons
, 'f'},
601 {"globl", s_mips_globl
, 0},
602 {"global", s_mips_globl
, 0},
603 {"hword", s_cons
, 1},
608 {"short", s_cons
, 1},
609 {"single", s_float_cons
, 'f'},
610 {"text", s_change_sec
, 't'},
615 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
616 /* These pseudo-ops should be defined by the object file format.
617 However, a.out doesn't support them, so we have versions here. */
619 {"bgnb", s_ignore
, 0},
620 {"end", s_mipsend
, 0},
621 {"endb", s_ignore
, 0},
624 {"fmask", s_ignore
, 'F'},
625 {"frame", s_ignore
, 0},
626 {"loc", s_ignore
, 0},
627 {"mask", s_ignore
, 'R'},
628 {"verstamp", s_ignore
, 0},
632 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
637 pop_insert (mips_pseudo_table
);
638 if (! ECOFF_DEBUGGING
)
639 pop_insert (mips_nonecoff_pseudo_table
);
642 /* Symbols labelling the current insn. */
644 struct insn_label_list
646 struct insn_label_list
*next
;
650 static struct insn_label_list
*insn_labels
;
651 static struct insn_label_list
*free_insn_labels
;
653 static void mips_clear_insn_labels
PARAMS ((void));
656 mips_clear_insn_labels ()
658 register struct insn_label_list
**pl
;
660 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
666 static char *expr_end
;
668 /* Expressions which appear in instructions. These are set by
671 static expressionS imm_expr
;
672 static expressionS offset_expr
;
674 /* Relocs associated with imm_expr and offset_expr. */
676 static bfd_reloc_code_real_type imm_reloc
;
677 static bfd_reloc_code_real_type offset_reloc
;
679 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
681 static boolean imm_unmatched_hi
;
683 /* These are set by mips16_ip if an explicit extension is used. */
685 static boolean mips16_small
, mips16_ext
;
688 * This function is called once, at assembler startup time. It should
689 * set up all the tables, etc. that the MD part of the assembler will need.
695 register const char *retval
= NULL
;
696 register unsigned int i
= 0;
704 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
706 a
= xmalloc (sizeof TARGET_CPU
);
707 strcpy (a
, TARGET_CPU
);
708 a
[(sizeof TARGET_CPU
) - 3] = '\0';
712 if (strcmp (cpu
, "mips") == 0)
718 else if (strcmp (cpu
, "r6000") == 0
719 || strcmp (cpu
, "mips2") == 0)
725 else if (strcmp (cpu
, "mips64") == 0
726 || strcmp (cpu
, "r4000") == 0
727 || strcmp (cpu
, "mips3") == 0)
733 else if (strcmp (cpu
, "r4400") == 0)
739 else if (strcmp (cpu
, "mips64orion") == 0
740 || strcmp (cpu
, "r4600") == 0)
746 else if (strcmp (cpu
, "r4650") == 0)
754 else if (strcmp (cpu
, "mips64vr4300") == 0)
760 else if (strcmp (cpu
, "mips64vr4100") == 0)
768 else if (strcmp (cpu
, "r4010") == 0)
776 else if (strcmp (cpu
, "r5000") == 0
777 || strcmp (cpu
, "mips64vr5000") == 0)
783 else if (strcmp (cpu
, "r8000") == 0
784 || strcmp (cpu
, "mips4") == 0)
790 else if (strcmp (cpu
, "r10000") == 0)
796 else if (strcmp (cpu
, "mips16") == 0)
800 mips_cpu
= 0; /* FIXME */
815 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
830 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
835 if (mips_cpu
== 4300)
840 if (mips_isa
< 2 && mips_trap
)
841 as_bad ("trap exception not supported at ISA 1");
846 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
849 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
852 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
855 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
859 as_warn ("Could not set architecture and machine");
861 file_mips_isa
= mips_isa
;
863 op_hash
= hash_new ();
865 for (i
= 0; i
< NUMOPCODES
;)
867 const char *name
= mips_opcodes
[i
].name
;
869 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
872 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
873 mips_opcodes
[i
].name
, retval
);
874 as_fatal ("Broken assembler. No assembly attempted.");
878 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
879 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
880 != mips_opcodes
[i
].match
))
882 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
883 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
884 as_fatal ("Broken assembler. No assembly attempted.");
888 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
891 mips16_op_hash
= hash_new ();
894 while (i
< bfd_mips16_num_opcodes
)
896 const char *name
= mips16_opcodes
[i
].name
;
898 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
900 as_fatal ("internal error: can't hash `%s': %s\n",
901 mips16_opcodes
[i
].name
, retval
);
904 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
905 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
906 != mips16_opcodes
[i
].match
))
907 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
908 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
911 while (i
< bfd_mips16_num_opcodes
912 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
915 mips_no_prev_insn ();
923 /* set the default alignment for the text section (2**2) */
924 record_alignment (text_section
, 2);
926 if (USE_GLOBAL_POINTER_OPT
)
927 bfd_set_gp_size (stdoutput
, g_switch_value
);
929 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
931 /* On a native system, sections must be aligned to 16 byte
932 boundaries. When configured for an embedded ELF target, we
934 if (strcmp (TARGET_OS
, "elf") != 0)
936 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
937 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
938 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
941 /* Create a .reginfo section for register masks and a .mdebug
942 section for debugging information. */
952 /* The ABI says this section should be loaded so that the
953 running program can access it. However, we don't load it
954 if we are configured for an embedded target */
955 flags
= SEC_READONLY
| SEC_DATA
;
956 if (strcmp (TARGET_OS
, "elf") != 0)
957 flags
|= SEC_ALLOC
| SEC_LOAD
;
961 sec
= subseg_new (".reginfo", (subsegT
) 0);
964 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
965 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
968 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
973 /* The 64-bit ABI uses a .MIPS.options section rather than
975 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
976 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
977 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
980 /* Set up the option header. */
982 Elf_Internal_Options opthdr
;
985 opthdr
.kind
= ODK_REGINFO
;
986 opthdr
.size
= (sizeof (Elf_External_Options
)
987 + sizeof (Elf64_External_RegInfo
));
990 f
= frag_more (sizeof (Elf_External_Options
));
991 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
992 (Elf_External_Options
*) f
);
994 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1001 sec
= subseg_new (".mdebug", (subsegT
) 0);
1002 (void) bfd_set_section_flags (stdoutput
, sec
,
1003 SEC_HAS_CONTENTS
| SEC_READONLY
);
1004 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1007 subseg_set (seg
, subseg
);
1011 if (! ECOFF_DEBUGGING
)
1018 if (! ECOFF_DEBUGGING
)
1026 struct mips_cl_insn insn
;
1028 imm_expr
.X_op
= O_absent
;
1029 imm_reloc
= BFD_RELOC_UNUSED
;
1030 imm_unmatched_hi
= false;
1031 offset_expr
.X_op
= O_absent
;
1032 offset_reloc
= BFD_RELOC_UNUSED
;
1035 mips16_ip (str
, &insn
);
1037 mips_ip (str
, &insn
);
1041 as_bad ("%s `%s'", insn_error
, str
);
1045 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1048 mips16_macro (&insn
);
1054 if (imm_expr
.X_op
!= O_absent
)
1055 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1057 else if (offset_expr
.X_op
!= O_absent
)
1058 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1060 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1064 /* See whether instruction IP reads register REG. CLASS is the type
1068 insn_uses_reg (ip
, reg
, class)
1069 struct mips_cl_insn
*ip
;
1071 enum mips_regclass
class;
1073 if (class == MIPS16_REG
)
1076 reg
= mips16_to_32_reg_map
[reg
];
1077 class = MIPS_GR_REG
;
1080 /* Don't report on general register 0, since it never changes. */
1081 if (class == MIPS_GR_REG
&& reg
== 0)
1084 if (class == MIPS_FP_REG
)
1087 /* If we are called with either $f0 or $f1, we must check $f0.
1088 This is not optimal, because it will introduce an unnecessary
1089 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1090 need to distinguish reading both $f0 and $f1 or just one of
1091 them. Note that we don't have to check the other way,
1092 because there is no instruction that sets both $f0 and $f1
1093 and requires a delay. */
1094 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1095 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1096 == (reg
&~ (unsigned) 1)))
1098 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1099 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1100 == (reg
&~ (unsigned) 1)))
1105 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1106 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1108 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1109 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1114 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1115 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1117 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1118 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1120 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1121 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1122 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1124 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1126 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1128 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1130 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1131 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1132 & MIPS16OP_MASK_REGR32
) == reg
)
1139 /* This function returns true if modifying a register requires a
1143 reg_needs_delay (reg
)
1146 unsigned long prev_pinfo
;
1148 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1149 if (! mips_noreorder
1151 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1153 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1155 /* A load from a coprocessor or from memory. All load
1156 delays delay the use of general register rt for one
1157 instruction on the r3000. The r6000 and r4000 use
1159 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1160 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1167 /* Output an instruction. PLACE is where to put the instruction; if
1168 it is NULL, this uses frag_more to get room. IP is the instruction
1169 information. ADDRESS_EXPR is an operand of the instruction to be
1170 used with RELOC_TYPE. */
1173 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1175 struct mips_cl_insn
*ip
;
1176 expressionS
*address_expr
;
1177 bfd_reloc_code_real_type reloc_type
;
1178 boolean unmatched_hi
;
1180 register unsigned long prev_pinfo
, pinfo
;
1185 /* Mark instruction labels in mips16 mode. This permits the linker
1186 to handle them specially, such as generating jalx instructions
1187 when needed. We also make them odd for the duration of the
1188 assembly, in order to generate the right sort of code. We will
1189 make them even in the adjust_symtab routine, while leaving them
1190 marked. This is convenient for the debugger and the
1191 disassembler. The linker knows to make them odd again. */
1194 struct insn_label_list
*l
;
1196 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1199 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1200 S_SET_OTHER (l
->label
, STO_MIPS16
);
1202 ++l
->label
->sy_value
.X_add_number
;
1206 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1207 pinfo
= ip
->insn_mo
->pinfo
;
1209 if (place
== NULL
&& ! mips_noreorder
)
1211 /* If the previous insn required any delay slots, see if we need
1212 to insert a NOP or two. There are eight kinds of possible
1213 hazards, of which an instruction can have at most one type.
1214 (1) a load from memory delay
1215 (2) a load from a coprocessor delay
1216 (3) an unconditional branch delay
1217 (4) a conditional branch delay
1218 (5) a move to coprocessor register delay
1219 (6) a load coprocessor register from memory delay
1220 (7) a coprocessor condition code delay
1221 (8) a HI/LO special register delay
1223 There are a lot of optimizations we could do that we don't.
1224 In particular, we do not, in general, reorder instructions.
1225 If you use gcc with optimization, it will reorder
1226 instructions and generally do much more optimization then we
1227 do here; repeating all that work in the assembler would only
1228 benefit hand written assembly code, and does not seem worth
1231 /* This is how a NOP is emitted. */
1232 #define emit_nop() \
1234 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1235 : md_number_to_chars (frag_more (4), 0, 4))
1237 /* The previous insn might require a delay slot, depending upon
1238 the contents of the current insn. */
1241 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1242 && ! cop_interlocks
)
1244 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1246 /* A load from a coprocessor or from memory. All load
1247 delays delay the use of general register rt for one
1248 instruction on the r3000. The r6000 and r4000 use
1250 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1251 if (mips_optimize
== 0
1252 || insn_uses_reg (ip
,
1253 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1260 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1261 && ! cop_interlocks
)
1263 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1265 /* A generic coprocessor delay. The previous instruction
1266 modified a coprocessor general or control register. If
1267 it modified a control register, we need to avoid any
1268 coprocessor instruction (this is probably not always
1269 required, but it sometimes is). If it modified a general
1270 register, we avoid using that register.
1272 On the r6000 and r4000 loading a coprocessor register
1273 from memory is interlocked, and does not require a delay.
1275 This case is not handled very well. There is no special
1276 knowledge of CP0 handling, and the coprocessors other
1277 than the floating point unit are not distinguished at
1279 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1281 if (mips_optimize
== 0
1282 || insn_uses_reg (ip
,
1283 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1288 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1290 if (mips_optimize
== 0
1291 || insn_uses_reg (ip
,
1292 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1299 /* We don't know exactly what the previous instruction
1300 does. If the current instruction uses a coprocessor
1301 register, we must insert a NOP. If previous
1302 instruction may set the condition codes, and the
1303 current instruction uses them, we must insert two
1305 if (mips_optimize
== 0
1306 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1307 && (pinfo
& INSN_READ_COND_CODE
)))
1309 else if (pinfo
& INSN_COP
)
1315 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1316 && ! cop_interlocks
)
1318 /* The previous instruction sets the coprocessor condition
1319 codes, but does not require a general coprocessor delay
1320 (this means it is a floating point comparison
1321 instruction). If this instruction uses the condition
1322 codes, we need to insert a single NOP. */
1323 if (mips_optimize
== 0
1324 || (pinfo
& INSN_READ_COND_CODE
))
1327 else if (prev_pinfo
& INSN_READ_LO
)
1329 /* The previous instruction reads the LO register; if the
1330 current instruction writes to the LO register, we must
1331 insert two NOPS. Some newer processors have interlocks. */
1333 && (mips_optimize
== 0
1334 || (pinfo
& INSN_WRITE_LO
)))
1337 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1339 /* The previous instruction reads the HI register; if the
1340 current instruction writes to the HI register, we must
1341 insert a NOP. Some newer processors have interlocks. */
1343 && (mips_optimize
== 0
1344 || (pinfo
& INSN_WRITE_HI
)))
1348 /* There are two cases which require two intervening
1349 instructions: 1) setting the condition codes using a move to
1350 coprocessor instruction which requires a general coprocessor
1351 delay and then reading the condition codes 2) reading the HI
1352 or LO register and then writing to it (except on processors
1353 which have interlocks). If we are not already emitting a NOP
1354 instruction, we must check for these cases compared to the
1355 instruction previous to the previous instruction. */
1359 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1360 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1361 && (pinfo
& INSN_READ_COND_CODE
)
1362 && ! cop_interlocks
)
1363 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1364 && (pinfo
& INSN_WRITE_LO
)
1366 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1367 && (pinfo
& INSN_WRITE_HI
)
1371 /* If we are being given a nop instruction, don't bother with
1372 one of the nops we would otherwise output. This will only
1373 happen when a nop instruction is used with mips_optimize set
1375 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1378 /* Now emit the right number of NOP instructions. */
1382 unsigned long old_frag_offset
;
1384 struct insn_label_list
*l
;
1386 old_frag
= frag_now
;
1387 old_frag_offset
= frag_now_fix ();
1389 for (i
= 0; i
< nops
; i
++)
1394 listing_prev_line ();
1395 /* We may be at the start of a variant frag. In case we
1396 are, make sure there is enough space for the frag
1397 after the frags created by listing_prev_line. The
1398 argument to frag_grow here must be at least as large
1399 as the argument to all other calls to frag_grow in
1400 this file. We don't have to worry about being in the
1401 middle of a variant frag, because the variants insert
1402 all needed nop instructions themselves. */
1406 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1408 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1409 l
->label
->sy_frag
= frag_now
;
1410 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1411 /* mips16 text labels are stored as odd. */
1413 ++l
->label
->sy_value
.X_add_number
;
1416 #ifndef NO_ECOFF_DEBUGGING
1417 if (ECOFF_DEBUGGING
)
1418 ecoff_fix_loc (old_frag
, old_frag_offset
);
1423 if (reloc_type
> BFD_RELOC_UNUSED
)
1425 /* We need to set up a variant frag. */
1426 assert (mips16
&& address_expr
!= NULL
);
1427 f
= frag_var (rs_machine_dependent
, 4, 0,
1428 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1429 mips16_small
, mips16_ext
,
1431 & INSN_UNCOND_BRANCH_DELAY
),
1432 (prev_insn_reloc_type
1433 == BFD_RELOC_MIPS16_JMP
)),
1434 make_expr_symbol (address_expr
), (long) 0,
1437 else if (place
!= NULL
)
1439 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1441 /* Make sure there is enough room to swap this instruction with
1442 a following jump instruction. */
1449 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1451 if (address_expr
->X_op
== O_constant
)
1456 ip
->insn_opcode
|= address_expr
->X_add_number
;
1459 case BFD_RELOC_LO16
:
1460 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1463 case BFD_RELOC_MIPS_JMP
:
1464 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1467 case BFD_RELOC_MIPS16_JMP
:
1469 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1470 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1471 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1474 case BFD_RELOC_16_PCREL_S2
:
1484 /* Don't generate a reloc if we are writing into a variant
1488 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1490 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1494 struct mips_hi_fixup
*hi_fixup
;
1496 assert (reloc_type
== BFD_RELOC_HI16_S
);
1497 hi_fixup
= ((struct mips_hi_fixup
*)
1498 xmalloc (sizeof (struct mips_hi_fixup
)));
1499 hi_fixup
->fixp
= fixp
;
1500 hi_fixup
->seg
= now_seg
;
1501 hi_fixup
->next
= mips_hi_fixup_list
;
1502 mips_hi_fixup_list
= hi_fixup
;
1508 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1509 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1514 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1517 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1520 /* Update the register mask information. */
1523 if (pinfo
& INSN_WRITE_GPR_D
)
1524 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1525 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1526 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1527 if (pinfo
& INSN_READ_GPR_S
)
1528 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1529 if (pinfo
& INSN_WRITE_GPR_31
)
1530 mips_gprmask
|= 1 << 31;
1531 if (pinfo
& INSN_WRITE_FPR_D
)
1532 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1533 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1534 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1535 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1536 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1537 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1538 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1539 if (pinfo
& INSN_COP
)
1541 /* We don't keep enough information to sort these cases out. */
1543 /* Never set the bit for $0, which is always zero. */
1544 mips_gprmask
&=~ 1 << 0;
1548 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1549 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1550 & MIPS16OP_MASK_RX
);
1551 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1552 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1553 & MIPS16OP_MASK_RY
);
1554 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1555 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1556 & MIPS16OP_MASK_RZ
);
1557 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1558 mips_gprmask
|= 1 << TREG
;
1559 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1560 mips_gprmask
|= 1 << SP
;
1561 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1562 mips_gprmask
|= 1 << RA
;
1563 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1564 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1565 if (pinfo
& MIPS16_INSN_READ_Z
)
1566 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1567 & MIPS16OP_MASK_MOVE32Z
);
1568 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1569 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1570 & MIPS16OP_MASK_REGR32
);
1573 if (place
== NULL
&& ! mips_noreorder
)
1575 /* Filling the branch delay slot is more complex. We try to
1576 switch the branch with the previous instruction, which we can
1577 do if the previous instruction does not set up a condition
1578 that the branch tests and if the branch is not itself the
1579 target of any branch. */
1580 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1581 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1583 if (mips_optimize
< 2
1584 /* If we have seen .set volatile or .set nomove, don't
1587 /* If we had to emit any NOP instructions, then we
1588 already know we can not swap. */
1590 /* If we don't even know the previous insn, we can not
1592 || ! prev_insn_valid
1593 /* If the previous insn is already in a branch delay
1594 slot, then we can not swap. */
1595 || prev_insn_is_delay_slot
1596 /* If the previous previous insn was in a .set
1597 noreorder, we can't swap. Actually, the MIPS
1598 assembler will swap in this situation. However, gcc
1599 configured -with-gnu-as will generate code like
1605 in which we can not swap the bne and INSN. If gcc is
1606 not configured -with-gnu-as, it does not output the
1607 .set pseudo-ops. We don't have to check
1608 prev_insn_unreordered, because prev_insn_valid will
1609 be 0 in that case. We don't want to use
1610 prev_prev_insn_valid, because we do want to be able
1611 to swap at the start of a function. */
1612 || prev_prev_insn_unreordered
1613 /* If the branch is itself the target of a branch, we
1614 can not swap. We cheat on this; all we check for is
1615 whether there is a label on this instruction. If
1616 there are any branches to anything other than a
1617 label, users must use .set noreorder. */
1618 || insn_labels
!= NULL
1619 /* If the previous instruction is in a variant frag, we
1620 can not do the swap. This does not apply to the
1621 mips16, which uses variant frags for different
1624 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1625 /* If the branch reads the condition codes, we don't
1626 even try to swap, because in the sequence
1631 we can not swap, and I don't feel like handling that
1635 && (pinfo
& INSN_READ_COND_CODE
))
1636 /* We can not swap with an instruction that requires a
1637 delay slot, becase the target of the branch might
1638 interfere with that instruction. */
1642 & (INSN_LOAD_COPROC_DELAY
1643 | INSN_COPROC_MOVE_DELAY
1644 | INSN_WRITE_COND_CODE
)))
1652 & (INSN_LOAD_MEMORY_DELAY
1653 | INSN_COPROC_MEMORY_DELAY
)))
1654 /* We can not swap with a branch instruction. */
1656 & (INSN_UNCOND_BRANCH_DELAY
1657 | INSN_COND_BRANCH_DELAY
1658 | INSN_COND_BRANCH_LIKELY
))
1659 /* We do not swap with a trap instruction, since it
1660 complicates trap handlers to have the trap
1661 instruction be in a delay slot. */
1662 || (prev_pinfo
& INSN_TRAP
)
1663 /* If the branch reads a register that the previous
1664 instruction sets, we can not swap. */
1666 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1667 && insn_uses_reg (ip
,
1668 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1672 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1673 && insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1678 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1679 && insn_uses_reg (ip
,
1680 ((prev_insn
.insn_opcode
1682 & MIPS16OP_MASK_RX
),
1684 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1685 && insn_uses_reg (ip
,
1686 ((prev_insn
.insn_opcode
1688 & MIPS16OP_MASK_RY
),
1690 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1691 && insn_uses_reg (ip
,
1692 ((prev_insn
.insn_opcode
1694 & MIPS16OP_MASK_RZ
),
1696 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1697 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1698 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1699 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1700 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1701 && insn_uses_reg (ip
,
1702 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1705 /* If the branch writes a register that the previous
1706 instruction sets, we can not swap (we know that
1707 branches write only to RD or to $31). */
1709 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1710 && (((pinfo
& INSN_WRITE_GPR_D
)
1711 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1712 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1713 || ((pinfo
& INSN_WRITE_GPR_31
)
1714 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1718 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1719 && (((pinfo
& INSN_WRITE_GPR_D
)
1720 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1721 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1722 || ((pinfo
& INSN_WRITE_GPR_31
)
1723 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1727 && (pinfo
& MIPS16_INSN_WRITE_31
)
1728 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1729 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1730 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1732 /* If the branch writes a register that the previous
1733 instruction reads, we can not swap (we know that
1734 branches only write to RD or to $31). */
1736 && (pinfo
& INSN_WRITE_GPR_D
)
1737 && insn_uses_reg (&prev_insn
,
1738 ((ip
->insn_opcode
>> OP_SH_RD
)
1742 && (pinfo
& INSN_WRITE_GPR_31
)
1743 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1745 && (pinfo
& MIPS16_INSN_WRITE_31
)
1746 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1747 /* If we are generating embedded PIC code, the branch
1748 might be expanded into a sequence which uses $at, so
1749 we can't swap with an instruction which reads it. */
1750 || (mips_pic
== EMBEDDED_PIC
1751 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1752 /* If the previous previous instruction has a load
1753 delay, and sets a register that the branch reads, we
1757 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1759 && (prev_prev_insn
.insn_mo
->pinfo
1760 & INSN_LOAD_MEMORY_DELAY
)))
1761 && insn_uses_reg (ip
,
1762 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1765 /* If one instruction sets a condition code and the
1766 other one uses a condition code, we can not swap. */
1767 || ((pinfo
& INSN_READ_COND_CODE
)
1768 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1769 || ((pinfo
& INSN_WRITE_COND_CODE
)
1770 && (prev_pinfo
& INSN_READ_COND_CODE
))
1771 /* If the previous instruction uses the PC, we can not
1774 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1775 /* If the previous instruction was extended, we can not
1777 || (mips16
&& prev_insn_extended
)
1778 /* If the previous instruction had a fixup in mips16
1779 mode, we can not swap. This normally means that the
1780 previous instruction was a 4 byte branch anyhow. */
1781 || (mips16
&& prev_insn_fixp
))
1783 /* We could do even better for unconditional branches to
1784 portions of this object file; we could pick up the
1785 instruction at the destination, put it in the delay
1786 slot, and bump the destination address. */
1788 /* Update the previous insn information. */
1789 prev_prev_insn
= *ip
;
1790 prev_insn
.insn_mo
= &dummy_opcode
;
1794 /* It looks like we can actually do the swap. */
1800 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1801 memcpy (temp
, prev_f
, 4);
1802 memcpy (prev_f
, f
, 4);
1803 memcpy (f
, temp
, 4);
1806 prev_insn_fixp
->fx_frag
= frag_now
;
1807 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1811 fixp
->fx_frag
= prev_insn_frag
;
1812 fixp
->fx_where
= prev_insn_where
;
1815 else if (reloc_type
> BFD_RELOC_UNUSED
)
1820 /* We are in mips16 mode, and we have just created a
1821 variant frag. We need to extract the old
1822 instruction from the end of the previous frag,
1823 and add it to a new frag. */
1824 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1825 memcpy (temp
, prev_f
, 2);
1826 prev_insn_frag
->fr_fix
-= 2;
1827 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1829 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1830 memcpy (prev_f
, prev_f
+ 2, 2);
1832 memcpy (frag_more (2), temp
, 2);
1839 assert (prev_insn_fixp
== NULL
);
1840 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1841 memcpy (temp
, prev_f
, 2);
1842 memcpy (prev_f
, f
, 2);
1843 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1844 memcpy (f
, temp
, 2);
1847 memcpy (f
, f
+ 2, 2);
1848 memcpy (f
+ 2, temp
, 2);
1852 fixp
->fx_frag
= prev_insn_frag
;
1853 fixp
->fx_where
= prev_insn_where
;
1857 /* Update the previous insn information; leave prev_insn
1859 prev_prev_insn
= *ip
;
1861 prev_insn_is_delay_slot
= 1;
1863 /* If that was an unconditional branch, forget the previous
1864 insn information. */
1865 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1867 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1868 prev_insn
.insn_mo
= &dummy_opcode
;
1871 prev_insn_fixp
= NULL
;
1872 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1873 prev_insn_extended
= 0;
1875 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1877 /* We don't yet optimize a branch likely. What we should do
1878 is look at the target, copy the instruction found there
1879 into the delay slot, and increment the branch to jump to
1880 the next instruction. */
1882 /* Update the previous insn information. */
1883 prev_prev_insn
= *ip
;
1884 prev_insn
.insn_mo
= &dummy_opcode
;
1885 prev_insn_fixp
= NULL
;
1886 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1887 prev_insn_extended
= 0;
1891 /* Update the previous insn information. */
1893 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1895 prev_prev_insn
= prev_insn
;
1898 /* Any time we see a branch, we always fill the delay slot
1899 immediately; since this insn is not a branch, we know it
1900 is not in a delay slot. */
1901 prev_insn_is_delay_slot
= 0;
1903 prev_insn_fixp
= fixp
;
1904 prev_insn_reloc_type
= reloc_type
;
1906 prev_insn_extended
= (ip
->use_extend
1907 || reloc_type
> BFD_RELOC_UNUSED
);
1910 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1911 prev_insn_unreordered
= 0;
1912 prev_insn_frag
= frag_now
;
1913 prev_insn_where
= f
- frag_now
->fr_literal
;
1914 prev_insn_valid
= 1;
1916 else if (place
== NULL
)
1918 /* We need to record a bit of information even when we are not
1919 reordering, in order to determine the base address for mips16
1920 PC relative relocs. */
1922 prev_insn_reloc_type
= reloc_type
;
1925 /* We just output an insn, so the next one doesn't have a label. */
1926 mips_clear_insn_labels ();
1929 /* This function forgets that there was any previous instruction or
1933 mips_no_prev_insn ()
1935 prev_insn
.insn_mo
= &dummy_opcode
;
1936 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1937 prev_insn_valid
= 0;
1938 prev_insn_is_delay_slot
= 0;
1939 prev_insn_unreordered
= 0;
1940 prev_insn_extended
= 0;
1941 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1942 prev_prev_insn_unreordered
= 0;
1943 mips_clear_insn_labels ();
1946 /* This function must be called whenever we turn on noreorder or emit
1947 something other than instructions. It inserts any NOPS which might
1948 be needed by the previous instruction, and clears the information
1949 kept for the previous instructions. The INSNS parameter is true if
1950 instructions are to follow. */
1953 mips_emit_delays (insns
)
1956 if (! mips_noreorder
)
1963 && (! cop_interlocks
1964 && (prev_insn
.insn_mo
->pinfo
1965 & (INSN_LOAD_COPROC_DELAY
1966 | INSN_COPROC_MOVE_DELAY
1967 | INSN_WRITE_COND_CODE
))))
1969 && (prev_insn
.insn_mo
->pinfo
1974 && (prev_insn
.insn_mo
->pinfo
1975 & (INSN_LOAD_MEMORY_DELAY
1976 | INSN_COPROC_MEMORY_DELAY
))))
1981 && (! cop_interlocks
1982 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1984 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1985 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1990 && (! cop_interlocks
1991 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1993 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1994 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1998 struct insn_label_list
*l
;
2001 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2003 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2004 l
->label
->sy_frag
= frag_now
;
2005 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2006 /* mips16 text labels are stored as odd. */
2008 ++l
->label
->sy_value
.X_add_number
;
2013 /* Mark instruction labels in mips16 mode. This permits the linker
2014 to handle them specially, such as generating jalx instructions
2015 when needed. We also make them odd for the duration of the
2016 assembly, in order to generate the right sort of code. We will
2017 make them even in the adjust_symtab routine, while leaving them
2018 marked. This is convenient for the debugger and the
2019 disassembler. The linker knows to make them odd again. */
2020 if (mips16
&& insns
)
2022 struct insn_label_list
*l
;
2024 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2027 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2028 S_SET_OTHER (l
->label
, STO_MIPS16
);
2030 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2031 ++l
->label
->sy_value
.X_add_number
;
2035 mips_no_prev_insn ();
2038 /* Build an instruction created by a macro expansion. This is passed
2039 a pointer to the count of instructions created so far, an
2040 expression, the name of the instruction to build, an operand format
2041 string, and corresponding arguments. */
2045 macro_build (char *place
,
2053 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2062 struct mips_cl_insn insn
;
2063 bfd_reloc_code_real_type r
;
2067 va_start (args
, fmt
);
2073 * If the macro is about to expand into a second instruction,
2074 * print a warning if needed. We need to pass ip as a parameter
2075 * to generate a better warning message here...
2077 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2078 as_warn ("Macro instruction expanded into multiple instructions");
2081 *counter
+= 1; /* bump instruction counter */
2085 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2090 r
= BFD_RELOC_UNUSED
;
2091 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2092 assert (insn
.insn_mo
);
2093 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2095 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2096 || insn
.insn_mo
->pinfo
== INSN_MACRO
2097 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2099 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2101 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2103 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2105 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2107 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2111 assert (insn
.insn_mo
->name
);
2112 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2114 insn
.insn_opcode
= insn
.insn_mo
->match
;
2130 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2136 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2141 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2146 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2153 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2157 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2161 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2168 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2174 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2175 assert (r
== BFD_RELOC_MIPS_GPREL
2176 || r
== BFD_RELOC_MIPS_LITERAL
2177 || r
== BFD_RELOC_LO16
2178 || r
== BFD_RELOC_MIPS_GOT16
2179 || r
== BFD_RELOC_MIPS_CALL16
2180 || r
== BFD_RELOC_MIPS_GOT_LO16
2181 || r
== BFD_RELOC_MIPS_CALL_LO16
2182 || (ep
->X_op
== O_subtract
2183 && now_seg
== text_section
2184 && r
== BFD_RELOC_PCREL_LO16
));
2188 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2190 && (ep
->X_op
== O_constant
2191 || (ep
->X_op
== O_symbol
2192 && (r
== BFD_RELOC_HI16_S
2193 || r
== BFD_RELOC_HI16
2194 || r
== BFD_RELOC_MIPS_GOT_HI16
2195 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2196 || (ep
->X_op
== O_subtract
2197 && now_seg
== text_section
2198 && r
== BFD_RELOC_PCREL_HI16_S
)));
2199 if (ep
->X_op
== O_constant
)
2201 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2203 r
= BFD_RELOC_UNUSED
;
2208 assert (ep
!= NULL
);
2210 * This allows macro() to pass an immediate expression for
2211 * creating short branches without creating a symbol.
2212 * Note that the expression still might come from the assembly
2213 * input, in which case the value is not checked for range nor
2214 * is a relocation entry generated (yuck).
2216 if (ep
->X_op
== O_constant
)
2218 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2222 r
= BFD_RELOC_16_PCREL_S2
;
2226 assert (ep
!= NULL
);
2227 r
= BFD_RELOC_MIPS_JMP
;
2236 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2238 append_insn (place
, &insn
, ep
, r
, false);
2242 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2250 struct mips_cl_insn insn
;
2251 bfd_reloc_code_real_type r
;
2253 r
= BFD_RELOC_UNUSED
;
2254 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2255 assert (insn
.insn_mo
);
2256 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2258 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2259 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2262 assert (insn
.insn_mo
->name
);
2263 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2266 insn
.insn_opcode
= insn
.insn_mo
->match
;
2267 insn
.use_extend
= false;
2286 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2291 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2295 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2299 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2309 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2316 regno
= va_arg (args
, int);
2317 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2318 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2339 assert (ep
!= NULL
);
2341 if (ep
->X_op
!= O_constant
)
2342 r
= BFD_RELOC_UNUSED
+ c
;
2345 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2346 false, false, &insn
.insn_opcode
,
2347 &insn
.use_extend
, &insn
.extend
);
2349 r
= BFD_RELOC_UNUSED
;
2355 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2362 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2364 append_insn (place
, &insn
, ep
, r
, false);
2368 * Generate a "lui" instruction.
2371 macro_build_lui (place
, counter
, ep
, regnum
)
2377 expressionS high_expr
;
2378 struct mips_cl_insn insn
;
2379 bfd_reloc_code_real_type r
;
2380 CONST
char *name
= "lui";
2381 CONST
char *fmt
= "t,u";
2389 high_expr
.X_op
= O_constant
;
2390 high_expr
.X_add_number
= ep
->X_add_number
;
2393 if (high_expr
.X_op
== O_constant
)
2395 /* we can compute the instruction now without a relocation entry */
2396 if (high_expr
.X_add_number
& 0x8000)
2397 high_expr
.X_add_number
+= 0x10000;
2398 high_expr
.X_add_number
=
2399 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2400 r
= BFD_RELOC_UNUSED
;
2404 assert (ep
->X_op
== O_symbol
);
2405 /* _gp_disp is a special case, used from s_cpload. */
2406 assert (mips_pic
== NO_PIC
2407 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2408 r
= BFD_RELOC_HI16_S
;
2412 * If the macro is about to expand into a second instruction,
2413 * print a warning if needed. We need to pass ip as a parameter
2414 * to generate a better warning message here...
2416 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2417 as_warn ("Macro instruction expanded into multiple instructions");
2420 *counter
+= 1; /* bump instruction counter */
2422 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2423 assert (insn
.insn_mo
);
2424 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2425 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2427 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2428 if (r
== BFD_RELOC_UNUSED
)
2430 insn
.insn_opcode
|= high_expr
.X_add_number
;
2431 append_insn (place
, &insn
, NULL
, r
, false);
2434 append_insn (place
, &insn
, &high_expr
, r
, false);
2438 * Generates code to set the $at register to true (one)
2439 * if reg is less than the immediate expression.
2442 set_at (counter
, reg
, unsignedp
)
2447 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2448 macro_build ((char *) NULL
, counter
, &imm_expr
,
2449 unsignedp
? "sltiu" : "slti",
2450 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2453 load_register (counter
, AT
, &imm_expr
, 0);
2454 macro_build ((char *) NULL
, counter
, NULL
,
2455 unsignedp
? "sltu" : "slt",
2456 "d,v,t", AT
, reg
, AT
);
2460 /* Warn if an expression is not a constant. */
2463 check_absolute_expr (ip
, ex
)
2464 struct mips_cl_insn
*ip
;
2467 if (ex
->X_op
!= O_constant
)
2468 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2471 /* Count the leading zeroes by performing a binary chop. This is a
2472 bulky bit of source, but performance is a LOT better for the
2473 majority of values than a simple loop to count the bits:
2474 for (lcnt = 0; (lcnt < 32); lcnt++)
2475 if ((v) & (1 << (31 - lcnt)))
2477 However it is not code size friendly, and the gain will drop a bit
2478 on certain cached systems.
2480 #define COUNT_TOP_ZEROES(v) \
2481 (((v) & ~0xffff) == 0 \
2482 ? ((v) & ~0xff) == 0 \
2483 ? ((v) & ~0xf) == 0 \
2484 ? ((v) & ~0x3) == 0 \
2485 ? ((v) & ~0x1) == 0 \
2490 : ((v) & ~0x7) == 0 \
2493 : ((v) & ~0x3f) == 0 \
2494 ? ((v) & ~0x1f) == 0 \
2497 : ((v) & ~0x7f) == 0 \
2500 : ((v) & ~0xfff) == 0 \
2501 ? ((v) & ~0x3ff) == 0 \
2502 ? ((v) & ~0x1ff) == 0 \
2505 : ((v) & ~0x7ff) == 0 \
2508 : ((v) & ~0x3fff) == 0 \
2509 ? ((v) & ~0x1fff) == 0 \
2512 : ((v) & ~0x7fff) == 0 \
2515 : ((v) & ~0xffffff) == 0 \
2516 ? ((v) & ~0xfffff) == 0 \
2517 ? ((v) & ~0x3ffff) == 0 \
2518 ? ((v) & ~0x1ffff) == 0 \
2521 : ((v) & ~0x7ffff) == 0 \
2524 : ((v) & ~0x3fffff) == 0 \
2525 ? ((v) & ~0x1fffff) == 0 \
2528 : ((v) & ~0x7fffff) == 0 \
2531 : ((v) & ~0xfffffff) == 0 \
2532 ? ((v) & ~0x3ffffff) == 0 \
2533 ? ((v) & ~0x1ffffff) == 0 \
2536 : ((v) & ~0x7ffffff) == 0 \
2539 : ((v) & ~0x3fffffff) == 0 \
2540 ? ((v) & ~0x1fffffff) == 0 \
2543 : ((v) & ~0x7fffffff) == 0 \
2548 * This routine generates the least number of instructions neccessary to load
2549 * an absolute expression value into a register.
2552 load_register (counter
, reg
, ep
, dbl
)
2559 expressionS hi32
, lo32
;
2561 if (ep
->X_op
!= O_big
)
2563 assert (ep
->X_op
== O_constant
);
2564 if (ep
->X_add_number
< 0x8000
2565 && (ep
->X_add_number
>= 0
2566 || (ep
->X_add_number
>= -0x8000
2569 || sizeof (ep
->X_add_number
) > 4))))
2571 /* We can handle 16 bit signed values with an addiu to
2572 $zero. No need to ever use daddiu here, since $zero and
2573 the result are always correct in 32 bit mode. */
2574 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2575 (int) BFD_RELOC_LO16
);
2578 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2580 /* We can handle 16 bit unsigned values with an ori to
2582 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2583 (int) BFD_RELOC_LO16
);
2586 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2587 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2588 == ~ (offsetT
) 0x7fffffff))
2591 || sizeof (ep
->X_add_number
) > 4
2592 || (ep
->X_add_number
& 0x80000000) == 0))
2593 || ((mips_isa
< 3 || !dbl
)
2594 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2596 /* 32 bit values require an lui. */
2597 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2598 (int) BFD_RELOC_HI16
);
2599 if ((ep
->X_add_number
& 0xffff) != 0)
2600 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2601 (int) BFD_RELOC_LO16
);
2606 /* The value is larger than 32 bits. */
2610 as_bad ("Number larger than 32 bits");
2611 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2612 (int) BFD_RELOC_LO16
);
2616 if (ep
->X_op
!= O_big
)
2619 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2620 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2621 hi32
.X_add_number
&= 0xffffffff;
2623 lo32
.X_add_number
&= 0xffffffff;
2627 assert (ep
->X_add_number
> 2);
2628 if (ep
->X_add_number
== 3)
2629 generic_bignum
[3] = 0;
2630 else if (ep
->X_add_number
> 4)
2631 as_bad ("Number larger than 64 bits");
2632 lo32
.X_op
= O_constant
;
2633 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2634 hi32
.X_op
= O_constant
;
2635 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2638 if (hi32
.X_add_number
== 0)
2643 unsigned long hi
, lo
;
2645 if (hi32
.X_add_number
== 0xffffffff)
2647 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2649 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2650 reg
, 0, (int) BFD_RELOC_LO16
);
2653 if (lo32
.X_add_number
& 0x80000000)
2655 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2656 (int) BFD_RELOC_HI16
);
2657 if (lo32
.X_add_number
& 0xffff)
2658 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2659 reg
, reg
, (int) BFD_RELOC_LO16
);
2664 /* Check for 16bit shifted constant. We know that hi32 is
2665 non-zero, so start the mask on the first bit of the hi32
2670 unsigned long himask
, lomask
;
2674 himask
= 0xffff >> (32 - shift
);
2675 lomask
= (0xffff << shift
) & 0xffffffff;
2679 himask
= 0xffff << (shift
- 32);
2682 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2683 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2687 tmp
.X_op
= O_constant
;
2689 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2690 | (lo32
.X_add_number
>> shift
));
2692 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2693 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2694 (int) BFD_RELOC_LO16
);
2695 macro_build ((char *) NULL
, counter
, NULL
,
2696 (shift
>= 32) ? "dsll32" : "dsll",
2698 (shift
>= 32) ? shift
- 32 : shift
);
2702 } while (shift
<= (64 - 16));
2704 /* Find the bit number of the lowest one bit, and store the
2705 shifted value in hi/lo. */
2706 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2707 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2711 while ((lo
& 1) == 0)
2716 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2722 while ((hi
& 1) == 0)
2731 /* Optimize if the shifted value is a (power of 2) - 1. */
2732 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2733 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2735 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2740 /* This instruction will set the register to be all
2742 tmp
.X_op
= O_constant
;
2743 tmp
.X_add_number
= (offsetT
) -1;
2744 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2745 reg
, 0, (int) BFD_RELOC_LO16
);
2749 macro_build ((char *) NULL
, counter
, NULL
,
2750 (bit
>= 32) ? "dsll32" : "dsll",
2752 (bit
>= 32) ? bit
- 32 : bit
);
2754 macro_build ((char *) NULL
, counter
, NULL
,
2755 (shift
>= 32) ? "dsrl32" : "dsrl",
2757 (shift
>= 32) ? shift
- 32 : shift
);
2762 /* Sign extend hi32 before calling load_register, because we can
2763 generally get better code when we load a sign extended value. */
2764 if ((hi32
.X_add_number
& 0x80000000) != 0)
2765 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2766 load_register (counter
, reg
, &hi32
, 0);
2769 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2773 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2782 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2784 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2785 (int) BFD_RELOC_HI16
);
2786 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2793 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2798 mid16
.X_add_number
>>= 16;
2799 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2800 freg
, (int) BFD_RELOC_LO16
);
2801 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2805 if ((lo32
.X_add_number
& 0xffff) != 0)
2806 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2807 (int) BFD_RELOC_LO16
);
2810 /* Load an address into a register. */
2813 load_address (counter
, reg
, ep
)
2820 if (ep
->X_op
!= O_constant
2821 && ep
->X_op
!= O_symbol
)
2823 as_bad ("expression too complex");
2824 ep
->X_op
= O_constant
;
2827 if (ep
->X_op
== O_constant
)
2829 load_register (counter
, reg
, ep
, 0);
2833 if (mips_pic
== NO_PIC
)
2835 /* If this is a reference to a GP relative symbol, we want
2836 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2838 lui $reg,<sym> (BFD_RELOC_HI16_S)
2839 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2840 If we have an addend, we always use the latter form. */
2841 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2842 || nopic_need_relax (ep
->X_add_symbol
))
2847 macro_build ((char *) NULL
, counter
, ep
,
2848 mips_isa
< 3 ? "addiu" : "daddiu",
2849 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2850 p
= frag_var (rs_machine_dependent
, 8, 0,
2851 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2852 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2854 macro_build_lui (p
, counter
, ep
, reg
);
2857 macro_build (p
, counter
, ep
,
2858 mips_isa
< 3 ? "addiu" : "daddiu",
2859 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2861 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2865 /* If this is a reference to an external symbol, we want
2866 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2868 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2870 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2871 If there is a constant, it must be added in after. */
2872 ex
.X_add_number
= ep
->X_add_number
;
2873 ep
->X_add_number
= 0;
2875 macro_build ((char *) NULL
, counter
, ep
,
2876 mips_isa
< 3 ? "lw" : "ld",
2877 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2878 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2879 p
= frag_var (rs_machine_dependent
, 4, 0,
2880 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2881 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2882 macro_build (p
, counter
, ep
,
2883 mips_isa
< 3 ? "addiu" : "daddiu",
2884 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2885 if (ex
.X_add_number
!= 0)
2887 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2888 as_bad ("PIC code offset overflow (max 16 signed bits)");
2889 ex
.X_op
= O_constant
;
2890 macro_build ((char *) NULL
, counter
, &ex
,
2891 mips_isa
< 3 ? "addiu" : "daddiu",
2892 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2895 else if (mips_pic
== SVR4_PIC
)
2900 /* This is the large GOT case. If this is a reference to an
2901 external symbol, we want
2902 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2904 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2905 Otherwise, for a reference to a local symbol, we want
2906 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2908 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2909 If there is a constant, it must be added in after. */
2910 ex
.X_add_number
= ep
->X_add_number
;
2911 ep
->X_add_number
= 0;
2912 if (reg_needs_delay (GP
))
2917 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2918 (int) BFD_RELOC_MIPS_GOT_HI16
);
2919 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2920 mips_isa
< 3 ? "addu" : "daddu",
2921 "d,v,t", reg
, reg
, GP
);
2922 macro_build ((char *) NULL
, counter
, ep
,
2923 mips_isa
< 3 ? "lw" : "ld",
2924 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2925 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2926 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2927 mips_warn_about_macros
),
2928 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2931 /* We need a nop before loading from $gp. This special
2932 check is required because the lui which starts the main
2933 instruction stream does not refer to $gp, and so will not
2934 insert the nop which may be required. */
2935 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2938 macro_build (p
, counter
, ep
,
2939 mips_isa
< 3 ? "lw" : "ld",
2940 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2942 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2944 macro_build (p
, counter
, ep
,
2945 mips_isa
< 3 ? "addiu" : "daddiu",
2946 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2947 if (ex
.X_add_number
!= 0)
2949 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2950 as_bad ("PIC code offset overflow (max 16 signed bits)");
2951 ex
.X_op
= O_constant
;
2952 macro_build ((char *) NULL
, counter
, &ex
,
2953 mips_isa
< 3 ? "addiu" : "daddiu",
2954 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2957 else if (mips_pic
== EMBEDDED_PIC
)
2960 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2962 macro_build ((char *) NULL
, counter
, ep
,
2963 mips_isa
< 3 ? "addiu" : "daddiu",
2964 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2972 * This routine implements the seemingly endless macro or synthesized
2973 * instructions and addressing modes in the mips assembly language. Many
2974 * of these macros are simple and are similar to each other. These could
2975 * probably be handled by some kind of table or grammer aproach instead of
2976 * this verbose method. Others are not simple macros but are more like
2977 * optimizing code generation.
2978 * One interesting optimization is when several store macros appear
2979 * consecutivly that would load AT with the upper half of the same address.
2980 * The ensuing load upper instructions are ommited. This implies some kind
2981 * of global optimization. We currently only optimize within a single macro.
2982 * For many of the load and store macros if the address is specified as a
2983 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2984 * first load register 'at' with zero and use it as the base register. The
2985 * mips assembler simply uses register $zero. Just one tiny optimization
2990 struct mips_cl_insn
*ip
;
2992 register int treg
, sreg
, dreg
, breg
;
3007 bfd_reloc_code_real_type r
;
3009 int hold_mips_optimize
;
3013 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3014 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3015 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3016 mask
= ip
->insn_mo
->mask
;
3018 expr1
.X_op
= O_constant
;
3019 expr1
.X_op_symbol
= NULL
;
3020 expr1
.X_add_symbol
= NULL
;
3021 expr1
.X_add_number
= 1;
3033 mips_emit_delays (true);
3035 mips_any_noreorder
= 1;
3037 expr1
.X_add_number
= 8;
3038 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3040 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3042 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3043 macro_build ((char *) NULL
, &icnt
, NULL
,
3044 dbl
? "dsub" : "sub",
3045 "d,v,t", dreg
, 0, sreg
);
3068 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3070 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3071 (int) BFD_RELOC_LO16
);
3074 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3075 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3094 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3096 if (mask
!= M_NOR_I
)
3097 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3098 sreg
, (int) BFD_RELOC_LO16
);
3101 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3102 treg
, sreg
, (int) BFD_RELOC_LO16
);
3103 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3109 load_register (&icnt
, AT
, &imm_expr
, 0);
3110 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3127 if (imm_expr
.X_add_number
== 0)
3129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3133 load_register (&icnt
, AT
, &imm_expr
, 0);
3134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3142 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3143 likely
? "bgezl" : "bgez",
3149 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3150 likely
? "blezl" : "blez",
3154 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3155 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3156 likely
? "beql" : "beq",
3163 /* check for > max integer */
3164 maxnum
= 0x7fffffff;
3172 if (imm_expr
.X_add_number
>= maxnum
3173 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3176 /* result is always false */
3179 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3180 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3184 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3185 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3190 imm_expr
.X_add_number
++;
3194 if (mask
== M_BGEL_I
)
3196 if (imm_expr
.X_add_number
== 0)
3198 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3199 likely
? "bgezl" : "bgez",
3203 if (imm_expr
.X_add_number
== 1)
3205 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3206 likely
? "bgtzl" : "bgtz",
3210 maxnum
= 0x7fffffff;
3218 maxnum
= - maxnum
- 1;
3219 if (imm_expr
.X_add_number
<= maxnum
3220 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3223 /* result is always true */
3224 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3225 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3228 set_at (&icnt
, sreg
, 0);
3229 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3230 likely
? "beql" : "beq",
3241 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3242 likely
? "beql" : "beq",
3246 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3248 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3249 likely
? "beql" : "beq",
3256 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3258 imm_expr
.X_add_number
++;
3262 if (mask
== M_BGEUL_I
)
3264 if (imm_expr
.X_add_number
== 0)
3266 if (imm_expr
.X_add_number
== 1)
3268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3269 likely
? "bnel" : "bne",
3273 set_at (&icnt
, sreg
, 1);
3274 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3275 likely
? "beql" : "beq",
3284 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3285 likely
? "bgtzl" : "bgtz",
3291 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3292 likely
? "bltzl" : "bltz",
3296 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3297 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3298 likely
? "bnel" : "bne",
3307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3308 likely
? "bnel" : "bne",
3314 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3316 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3317 likely
? "bnel" : "bne",
3326 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3327 likely
? "blezl" : "blez",
3333 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3334 likely
? "bgezl" : "bgez",
3338 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3339 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3340 likely
? "beql" : "beq",
3347 maxnum
= 0x7fffffff;
3355 if (imm_expr
.X_add_number
>= maxnum
3356 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3358 imm_expr
.X_add_number
++;
3362 if (mask
== M_BLTL_I
)
3364 if (imm_expr
.X_add_number
== 0)
3366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3367 likely
? "bltzl" : "bltz",
3371 if (imm_expr
.X_add_number
== 1)
3373 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3374 likely
? "blezl" : "blez",
3378 set_at (&icnt
, sreg
, 0);
3379 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3380 likely
? "bnel" : "bne",
3389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3390 likely
? "beql" : "beq",
3396 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3399 likely
? "beql" : "beq",
3406 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3408 imm_expr
.X_add_number
++;
3412 if (mask
== M_BLTUL_I
)
3414 if (imm_expr
.X_add_number
== 0)
3416 if (imm_expr
.X_add_number
== 1)
3418 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3419 likely
? "beql" : "beq",
3423 set_at (&icnt
, sreg
, 1);
3424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3425 likely
? "bnel" : "bne",
3434 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3435 likely
? "bltzl" : "bltz",
3441 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3442 likely
? "bgtzl" : "bgtz",
3446 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3447 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3448 likely
? "bnel" : "bne",
3459 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3460 likely
? "bnel" : "bne",
3464 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3466 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3467 likely
? "bnel" : "bne",
3483 as_warn ("Divide by zero.");
3485 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3487 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3491 mips_emit_delays (true);
3493 mips_any_noreorder
= 1;
3494 macro_build ((char *) NULL
, &icnt
, NULL
,
3495 dbl
? "ddiv" : "div",
3496 "z,s,t", sreg
, treg
);
3498 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3501 expr1
.X_add_number
= 8;
3502 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3503 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3504 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3506 expr1
.X_add_number
= -1;
3507 macro_build ((char *) NULL
, &icnt
, &expr1
,
3508 dbl
? "daddiu" : "addiu",
3509 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3510 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3511 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3514 expr1
.X_add_number
= 1;
3515 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3516 (int) BFD_RELOC_LO16
);
3517 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3522 expr1
.X_add_number
= 0x80000000;
3523 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3524 (int) BFD_RELOC_HI16
);
3527 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3530 expr1
.X_add_number
= 8;
3531 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3532 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3533 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3575 if (imm_expr
.X_add_number
== 0)
3577 as_warn ("Divide by zero.");
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3581 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3584 if (imm_expr
.X_add_number
== 1)
3586 if (strcmp (s2
, "mflo") == 0)
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3593 if (imm_expr
.X_add_number
== -1
3594 && s
[strlen (s
) - 1] != 'u')
3596 if (strcmp (s2
, "mflo") == 0)
3599 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3602 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3606 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3610 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3611 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3612 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3631 mips_emit_delays (true);
3633 mips_any_noreorder
= 1;
3634 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3636 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3639 expr1
.X_add_number
= 8;
3640 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3641 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3645 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3651 /* Load the address of a symbol into a register. If breg is not
3652 zero, we then add a base register to it. */
3654 /* When generating embedded PIC code, we permit expressions of
3657 where bar is an address in the .text section. These are used
3658 when getting the addresses of functions. We don't permit
3659 X_add_number to be non-zero, because if the symbol is
3660 external the relaxing code needs to know that any addend is
3661 purely the offset to X_op_symbol. */
3662 if (mips_pic
== EMBEDDED_PIC
3663 && offset_expr
.X_op
== O_subtract
3664 && now_seg
== text_section
3665 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3666 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3667 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3668 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3669 ->sy_value
.X_add_symbol
)
3672 && offset_expr
.X_add_number
== 0)
3674 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3675 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3676 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3677 mips_isa
< 3 ? "addiu" : "daddiu",
3678 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3682 if (offset_expr
.X_op
!= O_symbol
3683 && offset_expr
.X_op
!= O_constant
)
3685 as_bad ("expression too complex");
3686 offset_expr
.X_op
= O_constant
;
3700 if (offset_expr
.X_op
== O_constant
)
3701 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3702 else if (mips_pic
== NO_PIC
)
3704 /* If this is a reference to an GP relative symbol, we want
3705 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3707 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3708 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3709 If we have a constant, we need two instructions anyhow,
3710 so we may as well always use the latter form. */
3711 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3712 || nopic_need_relax (offset_expr
.X_add_symbol
))
3717 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3718 mips_isa
< 3 ? "addiu" : "daddiu",
3719 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3720 p
= frag_var (rs_machine_dependent
, 8, 0,
3721 RELAX_ENCODE (4, 8, 0, 4, 0,
3722 mips_warn_about_macros
),
3723 offset_expr
.X_add_symbol
, (long) 0,
3726 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3729 macro_build (p
, &icnt
, &offset_expr
,
3730 mips_isa
< 3 ? "addiu" : "daddiu",
3731 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3733 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3735 /* If this is a reference to an external symbol, and there
3736 is no constant, we want
3737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3738 For a local symbol, we want
3739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3743 If we have a small constant, and this is a reference to
3744 an external symbol, we want
3745 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3747 addiu $tempreg,$tempreg,<constant>
3748 For a local symbol, we want the same instruction
3749 sequence, but we output a BFD_RELOC_LO16 reloc on the
3752 If we have a large constant, and this is a reference to
3753 an external symbol, we want
3754 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3755 lui $at,<hiconstant>
3756 addiu $at,$at,<loconstant>
3757 addu $tempreg,$tempreg,$at
3758 For a local symbol, we want the same instruction
3759 sequence, but we output a BFD_RELOC_LO16 reloc on the
3760 addiu instruction. */
3761 expr1
.X_add_number
= offset_expr
.X_add_number
;
3762 offset_expr
.X_add_number
= 0;
3764 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3766 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3767 if (expr1
.X_add_number
== 0)
3775 /* We're going to put in an addu instruction using
3776 tempreg, so we may as well insert the nop right
3778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3782 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3783 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3785 ? mips_warn_about_macros
3787 offset_expr
.X_add_symbol
, (long) 0,
3791 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3794 macro_build (p
, &icnt
, &expr1
,
3795 mips_isa
< 3 ? "addiu" : "daddiu",
3796 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3797 /* FIXME: If breg == 0, and the next instruction uses
3798 $tempreg, then if this variant case is used an extra
3799 nop will be generated. */
3801 else if (expr1
.X_add_number
>= -0x8000
3802 && expr1
.X_add_number
< 0x8000)
3804 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3806 macro_build ((char *) NULL
, &icnt
, &expr1
,
3807 mips_isa
< 3 ? "addiu" : "daddiu",
3808 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3809 (void) frag_var (rs_machine_dependent
, 0, 0,
3810 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3811 offset_expr
.X_add_symbol
, (long) 0,
3818 /* If we are going to add in a base register, and the
3819 target register and the base register are the same,
3820 then we are using AT as a temporary register. Since
3821 we want to load the constant into AT, we add our
3822 current AT (from the global offset table) and the
3823 register into the register now, and pretend we were
3824 not using a base register. */
3829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3831 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3832 mips_isa
< 3 ? "addu" : "daddu",
3833 "d,v,t", treg
, AT
, breg
);
3839 /* Set mips_optimize around the lui instruction to avoid
3840 inserting an unnecessary nop after the lw. */
3841 hold_mips_optimize
= mips_optimize
;
3843 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3844 mips_optimize
= hold_mips_optimize
;
3846 macro_build ((char *) NULL
, &icnt
, &expr1
,
3847 mips_isa
< 3 ? "addiu" : "daddiu",
3848 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3849 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3850 mips_isa
< 3 ? "addu" : "daddu",
3851 "d,v,t", tempreg
, tempreg
, AT
);
3852 (void) frag_var (rs_machine_dependent
, 0, 0,
3853 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3854 offset_expr
.X_add_symbol
, (long) 0,
3859 else if (mips_pic
== SVR4_PIC
)
3863 /* This is the large GOT case. If this is a reference to an
3864 external symbol, and there is no constant, we want
3865 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3866 addu $tempreg,$tempreg,$gp
3867 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3868 For a local symbol, we want
3869 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3871 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3873 If we have a small constant, and this is a reference to
3874 an external symbol, we want
3875 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3876 addu $tempreg,$tempreg,$gp
3877 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3879 addiu $tempreg,$tempreg,<constant>
3880 For a local symbol, we want
3881 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3883 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3885 If we have a large constant, and this is a reference to
3886 an external symbol, we want
3887 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3888 addu $tempreg,$tempreg,$gp
3889 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3890 lui $at,<hiconstant>
3891 addiu $at,$at,<loconstant>
3892 addu $tempreg,$tempreg,$at
3893 For a local symbol, we want
3894 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3895 lui $at,<hiconstant>
3896 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3897 addu $tempreg,$tempreg,$at
3899 expr1
.X_add_number
= offset_expr
.X_add_number
;
3900 offset_expr
.X_add_number
= 0;
3902 if (reg_needs_delay (GP
))
3906 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3907 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3908 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3909 mips_isa
< 3 ? "addu" : "daddu",
3910 "d,v,t", tempreg
, tempreg
, GP
);
3911 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3913 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3915 if (expr1
.X_add_number
== 0)
3923 /* We're going to put in an addu instruction using
3924 tempreg, so we may as well insert the nop right
3926 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3931 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3932 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3935 ? mips_warn_about_macros
3937 offset_expr
.X_add_symbol
, (long) 0,
3940 else if (expr1
.X_add_number
>= -0x8000
3941 && expr1
.X_add_number
< 0x8000)
3943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3945 macro_build ((char *) NULL
, &icnt
, &expr1
,
3946 mips_isa
< 3 ? "addiu" : "daddiu",
3947 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3949 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3950 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3952 ? mips_warn_about_macros
3954 offset_expr
.X_add_symbol
, (long) 0,
3961 /* If we are going to add in a base register, and the
3962 target register and the base register are the same,
3963 then we are using AT as a temporary register. Since
3964 we want to load the constant into AT, we add our
3965 current AT (from the global offset table) and the
3966 register into the register now, and pretend we were
3967 not using a base register. */
3975 assert (tempreg
== AT
);
3976 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3979 mips_isa
< 3 ? "addu" : "daddu",
3980 "d,v,t", treg
, AT
, breg
);
3985 /* Set mips_optimize around the lui instruction to avoid
3986 inserting an unnecessary nop after the lw. */
3987 hold_mips_optimize
= mips_optimize
;
3989 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3990 mips_optimize
= hold_mips_optimize
;
3992 macro_build ((char *) NULL
, &icnt
, &expr1
,
3993 mips_isa
< 3 ? "addiu" : "daddiu",
3994 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3996 mips_isa
< 3 ? "addu" : "daddu",
3997 "d,v,t", dreg
, dreg
, AT
);
3999 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4000 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4003 ? mips_warn_about_macros
4005 offset_expr
.X_add_symbol
, (long) 0,
4013 /* This is needed because this instruction uses $gp, but
4014 the first instruction on the main stream does not. */
4015 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4018 macro_build (p
, &icnt
, &offset_expr
,
4020 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4022 if (expr1
.X_add_number
>= -0x8000
4023 && expr1
.X_add_number
< 0x8000)
4025 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4027 macro_build (p
, &icnt
, &expr1
,
4028 mips_isa
< 3 ? "addiu" : "daddiu",
4029 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4030 /* FIXME: If add_number is 0, and there was no base
4031 register, the external symbol case ended with a load,
4032 so if the symbol turns out to not be external, and
4033 the next instruction uses tempreg, an unnecessary nop
4034 will be inserted. */
4040 /* We must add in the base register now, as in the
4041 external symbol case. */
4042 assert (tempreg
== AT
);
4043 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4045 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4046 mips_isa
< 3 ? "addu" : "daddu",
4047 "d,v,t", treg
, AT
, breg
);
4050 /* We set breg to 0 because we have arranged to add
4051 it in in both cases. */
4055 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4057 macro_build (p
, &icnt
, &expr1
,
4058 mips_isa
< 3 ? "addiu" : "daddiu",
4059 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4061 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4062 mips_isa
< 3 ? "addu" : "daddu",
4063 "d,v,t", tempreg
, tempreg
, AT
);
4067 else if (mips_pic
== EMBEDDED_PIC
)
4070 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4073 mips_isa
< 3 ? "addiu" : "daddiu",
4074 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4081 mips_isa
< 3 ? "addu" : "daddu",
4082 "d,v,t", treg
, tempreg
, breg
);
4090 /* The j instruction may not be used in PIC code, since it
4091 requires an absolute address. We convert it to a b
4093 if (mips_pic
== NO_PIC
)
4094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4099 /* The jal instructions must be handled as macros because when
4100 generating PIC code they expand to multi-instruction
4101 sequences. Normally they are simple instructions. */
4106 if (mips_pic
== NO_PIC
4107 || mips_pic
== EMBEDDED_PIC
)
4108 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4110 else if (mips_pic
== SVR4_PIC
)
4112 if (sreg
!= PIC_CALL_REG
)
4113 as_warn ("MIPS PIC call to register other than $25");
4115 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4117 if (mips_cprestore_offset
< 0)
4118 as_warn ("No .cprestore pseudo-op used in PIC code");
4121 expr1
.X_add_number
= mips_cprestore_offset
;
4122 macro_build ((char *) NULL
, &icnt
, &expr1
,
4123 mips_isa
< 3 ? "lw" : "ld",
4124 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4133 if (mips_pic
== NO_PIC
)
4134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4135 else if (mips_pic
== SVR4_PIC
)
4137 /* If this is a reference to an external symbol, and we are
4138 using a small GOT, we want
4139 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4143 lw $gp,cprestore($sp)
4144 The cprestore value is set using the .cprestore
4145 pseudo-op. If we are using a big GOT, we want
4146 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4148 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4152 lw $gp,cprestore($sp)
4153 If the symbol is not external, we want
4154 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4156 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4159 lw $gp,cprestore($sp) */
4163 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4164 mips_isa
< 3 ? "lw" : "ld",
4165 "t,o(b)", PIC_CALL_REG
,
4166 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4169 p
= frag_var (rs_machine_dependent
, 4, 0,
4170 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4171 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4177 if (reg_needs_delay (GP
))
4181 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4182 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4183 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4184 mips_isa
< 3 ? "addu" : "daddu",
4185 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4186 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4187 mips_isa
< 3 ? "lw" : "ld",
4188 "t,o(b)", PIC_CALL_REG
,
4189 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4192 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4193 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4195 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4198 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4201 macro_build (p
, &icnt
, &offset_expr
,
4202 mips_isa
< 3 ? "lw" : "ld",
4203 "t,o(b)", PIC_CALL_REG
,
4204 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4206 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4209 macro_build (p
, &icnt
, &offset_expr
,
4210 mips_isa
< 3 ? "addiu" : "daddiu",
4211 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4212 (int) BFD_RELOC_LO16
);
4213 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4214 "jalr", "s", PIC_CALL_REG
);
4215 if (mips_cprestore_offset
< 0)
4216 as_warn ("No .cprestore pseudo-op used in PIC code");
4220 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4222 expr1
.X_add_number
= mips_cprestore_offset
;
4223 macro_build ((char *) NULL
, &icnt
, &expr1
,
4224 mips_isa
< 3 ? "lw" : "ld",
4225 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4229 else if (mips_pic
== EMBEDDED_PIC
)
4231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4232 /* The linker may expand the call to a longer sequence which
4233 uses $at, so we must break rather than return. */
4309 if (breg
== treg
|| coproc
|| lr
)
4378 if (mask
== M_LWC1_AB
4379 || mask
== M_SWC1_AB
4380 || mask
== M_LDC1_AB
4381 || mask
== M_SDC1_AB
4390 if (offset_expr
.X_op
!= O_constant
4391 && offset_expr
.X_op
!= O_symbol
)
4393 as_bad ("expression too complex");
4394 offset_expr
.X_op
= O_constant
;
4397 /* A constant expression in PIC code can be handled just as it
4398 is in non PIC code. */
4399 if (mips_pic
== NO_PIC
4400 || offset_expr
.X_op
== O_constant
)
4402 /* If this is a reference to a GP relative symbol, and there
4403 is no base register, we want
4404 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4405 Otherwise, if there is no base register, we want
4406 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4407 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4408 If we have a constant, we need two instructions anyhow,
4409 so we always use the latter form.
4411 If we have a base register, and this is a reference to a
4412 GP relative symbol, we want
4413 addu $tempreg,$breg,$gp
4414 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4416 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4417 addu $tempreg,$tempreg,$breg
4418 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4419 With a constant we always use the latter case. */
4422 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4423 || nopic_need_relax (offset_expr
.X_add_symbol
))
4428 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4429 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4430 p
= frag_var (rs_machine_dependent
, 8, 0,
4431 RELAX_ENCODE (4, 8, 0, 4, 0,
4432 (mips_warn_about_macros
4433 || (used_at
&& mips_noat
))),
4434 offset_expr
.X_add_symbol
, (long) 0,
4438 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4441 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4442 (int) BFD_RELOC_LO16
, tempreg
);
4446 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4447 || nopic_need_relax (offset_expr
.X_add_symbol
))
4452 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4453 mips_isa
< 3 ? "addu" : "daddu",
4454 "d,v,t", tempreg
, breg
, GP
);
4455 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4456 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4457 p
= frag_var (rs_machine_dependent
, 12, 0,
4458 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4459 offset_expr
.X_add_symbol
, (long) 0,
4462 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4465 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4466 mips_isa
< 3 ? "addu" : "daddu",
4467 "d,v,t", tempreg
, tempreg
, breg
);
4470 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4471 (int) BFD_RELOC_LO16
, tempreg
);
4474 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4476 /* If this is a reference to an external symbol, we want
4477 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4479 <op> $treg,0($tempreg)
4481 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4483 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4484 <op> $treg,0($tempreg)
4485 If there is a base register, we add it to $tempreg before
4486 the <op>. If there is a constant, we stick it in the
4487 <op> instruction. We don't handle constants larger than
4488 16 bits, because we have no way to load the upper 16 bits
4489 (actually, we could handle them for the subset of cases
4490 in which we are not using $at). */
4491 assert (offset_expr
.X_op
== O_symbol
);
4492 expr1
.X_add_number
= offset_expr
.X_add_number
;
4493 offset_expr
.X_add_number
= 0;
4494 if (expr1
.X_add_number
< -0x8000
4495 || expr1
.X_add_number
>= 0x8000)
4496 as_bad ("PIC code offset overflow (max 16 signed bits)");
4498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4499 mips_isa
< 3 ? "lw" : "ld",
4500 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4502 p
= frag_var (rs_machine_dependent
, 4, 0,
4503 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4504 offset_expr
.X_add_symbol
, (long) 0,
4506 macro_build (p
, &icnt
, &offset_expr
,
4507 mips_isa
< 3 ? "addiu" : "daddiu",
4508 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4510 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4511 mips_isa
< 3 ? "addu" : "daddu",
4512 "d,v,t", tempreg
, tempreg
, breg
);
4513 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4514 (int) BFD_RELOC_LO16
, tempreg
);
4516 else if (mips_pic
== SVR4_PIC
)
4520 /* If this is a reference to an external symbol, we want
4521 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4522 addu $tempreg,$tempreg,$gp
4523 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4524 <op> $treg,0($tempreg)
4526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4528 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4529 <op> $treg,0($tempreg)
4530 If there is a base register, we add it to $tempreg before
4531 the <op>. If there is a constant, we stick it in the
4532 <op> instruction. We don't handle constants larger than
4533 16 bits, because we have no way to load the upper 16 bits
4534 (actually, we could handle them for the subset of cases
4535 in which we are not using $at). */
4536 assert (offset_expr
.X_op
== O_symbol
);
4537 expr1
.X_add_number
= offset_expr
.X_add_number
;
4538 offset_expr
.X_add_number
= 0;
4539 if (expr1
.X_add_number
< -0x8000
4540 || expr1
.X_add_number
>= 0x8000)
4541 as_bad ("PIC code offset overflow (max 16 signed bits)");
4542 if (reg_needs_delay (GP
))
4547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4548 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4550 mips_isa
< 3 ? "addu" : "daddu",
4551 "d,v,t", tempreg
, tempreg
, GP
);
4552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4553 mips_isa
< 3 ? "lw" : "ld",
4554 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4556 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4557 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4558 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4561 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4564 macro_build (p
, &icnt
, &offset_expr
,
4565 mips_isa
< 3 ? "lw" : "ld",
4566 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4568 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4570 macro_build (p
, &icnt
, &offset_expr
,
4571 mips_isa
< 3 ? "addiu" : "daddiu",
4572 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4574 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4575 mips_isa
< 3 ? "addu" : "daddu",
4576 "d,v,t", tempreg
, tempreg
, breg
);
4577 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4578 (int) BFD_RELOC_LO16
, tempreg
);
4580 else if (mips_pic
== EMBEDDED_PIC
)
4582 /* If there is no base register, we want
4583 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4584 If there is a base register, we want
4585 addu $tempreg,$breg,$gp
4586 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4588 assert (offset_expr
.X_op
== O_symbol
);
4591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4592 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4597 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4598 mips_isa
< 3 ? "addu" : "daddu",
4599 "d,v,t", tempreg
, breg
, GP
);
4600 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4601 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4614 load_register (&icnt
, treg
, &imm_expr
, 0);
4618 load_register (&icnt
, treg
, &imm_expr
, 1);
4622 if (imm_expr
.X_op
== O_constant
)
4624 load_register (&icnt
, AT
, &imm_expr
, 0);
4625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4626 "mtc1", "t,G", AT
, treg
);
4631 assert (offset_expr
.X_op
== O_symbol
4632 && strcmp (segment_name (S_GET_SEGMENT
4633 (offset_expr
.X_add_symbol
)),
4635 && offset_expr
.X_add_number
== 0);
4636 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4637 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4642 /* We know that sym is in the .rdata section. First we get the
4643 upper 16 bits of the address. */
4644 if (mips_pic
== NO_PIC
)
4646 /* FIXME: This won't work for a 64 bit address. */
4647 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4649 else if (mips_pic
== SVR4_PIC
)
4651 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4652 mips_isa
< 3 ? "lw" : "ld",
4653 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4655 else if (mips_pic
== EMBEDDED_PIC
)
4657 /* For embedded PIC we pick up the entire address off $gp in
4658 a single instruction. */
4659 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4660 mips_isa
< 3 ? "addiu" : "daddiu",
4661 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4662 offset_expr
.X_op
= O_constant
;
4663 offset_expr
.X_add_number
= 0;
4668 /* Now we load the register(s). */
4670 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4671 treg
, (int) BFD_RELOC_LO16
, AT
);
4674 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4675 treg
, (int) BFD_RELOC_LO16
, AT
);
4678 /* FIXME: How in the world do we deal with the possible
4680 offset_expr
.X_add_number
+= 4;
4681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4682 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4686 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4687 does not become a variant frag. */
4688 frag_wane (frag_now
);
4694 assert (offset_expr
.X_op
== O_symbol
4695 && offset_expr
.X_add_number
== 0);
4696 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4697 if (strcmp (s
, ".lit8") == 0)
4701 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4702 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4706 r
= BFD_RELOC_MIPS_LITERAL
;
4711 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4712 if (mips_pic
== SVR4_PIC
)
4713 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4714 mips_isa
< 3 ? "lw" : "ld",
4715 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4718 /* FIXME: This won't work for a 64 bit address. */
4719 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4724 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4725 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4727 /* To avoid confusion in tc_gen_reloc, we must ensure
4728 that this does not become a variant frag. */
4729 frag_wane (frag_now
);
4740 /* Even on a big endian machine $fn comes before $fn+1. We have
4741 to adjust when loading from memory. */
4744 assert (mips_isa
< 2);
4745 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4746 target_big_endian
? treg
+ 1 : treg
,
4748 /* FIXME: A possible overflow which I don't know how to deal
4750 offset_expr
.X_add_number
+= 4;
4751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4752 target_big_endian
? treg
: treg
+ 1,
4755 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4756 does not become a variant frag. */
4757 frag_wane (frag_now
);
4766 * The MIPS assembler seems to check for X_add_number not
4767 * being double aligned and generating:
4770 * addiu at,at,%lo(foo+1)
4773 * But, the resulting address is the same after relocation so why
4774 * generate the extra instruction?
4821 if (offset_expr
.X_op
!= O_symbol
4822 && offset_expr
.X_op
!= O_constant
)
4824 as_bad ("expression too complex");
4825 offset_expr
.X_op
= O_constant
;
4828 /* Even on a big endian machine $fn comes before $fn+1. We have
4829 to adjust when loading from memory. We set coproc if we must
4830 load $fn+1 first. */
4831 if (! target_big_endian
)
4834 if (mips_pic
== NO_PIC
4835 || offset_expr
.X_op
== O_constant
)
4837 /* If this is a reference to a GP relative symbol, we want
4838 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4839 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4840 If we have a base register, we use this
4842 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4843 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4844 If this is not a GP relative symbol, we want
4845 lui $at,<sym> (BFD_RELOC_HI16_S)
4846 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4847 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4848 If there is a base register, we add it to $at after the
4849 lui instruction. If there is a constant, we always use
4851 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4852 || nopic_need_relax (offset_expr
.X_add_symbol
))
4871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4872 mips_isa
< 3 ? "addu" : "daddu",
4873 "d,v,t", AT
, breg
, GP
);
4879 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4880 coproc
? treg
+ 1 : treg
,
4881 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4882 offset_expr
.X_add_number
+= 4;
4884 /* Set mips_optimize to 2 to avoid inserting an
4886 hold_mips_optimize
= mips_optimize
;
4888 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4889 coproc
? treg
: treg
+ 1,
4890 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4891 mips_optimize
= hold_mips_optimize
;
4893 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4894 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4895 used_at
&& mips_noat
),
4896 offset_expr
.X_add_symbol
, (long) 0,
4899 /* We just generated two relocs. When tc_gen_reloc
4900 handles this case, it will skip the first reloc and
4901 handle the second. The second reloc already has an
4902 extra addend of 4, which we added above. We must
4903 subtract it out, and then subtract another 4 to make
4904 the first reloc come out right. The second reloc
4905 will come out right because we are going to add 4 to
4906 offset_expr when we build its instruction below. */
4907 offset_expr
.X_add_number
-= 8;
4908 offset_expr
.X_op
= O_constant
;
4910 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4915 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4916 mips_isa
< 3 ? "addu" : "daddu",
4917 "d,v,t", AT
, breg
, AT
);
4921 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4922 coproc
? treg
+ 1 : treg
,
4923 (int) BFD_RELOC_LO16
, AT
);
4926 /* FIXME: How do we handle overflow here? */
4927 offset_expr
.X_add_number
+= 4;
4928 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4929 coproc
? treg
: treg
+ 1,
4930 (int) BFD_RELOC_LO16
, AT
);
4932 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4936 /* If this is a reference to an external symbol, we want
4937 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4942 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4944 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4945 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4946 If there is a base register we add it to $at before the
4947 lwc1 instructions. If there is a constant we include it
4948 in the lwc1 instructions. */
4950 expr1
.X_add_number
= offset_expr
.X_add_number
;
4951 offset_expr
.X_add_number
= 0;
4952 if (expr1
.X_add_number
< -0x8000
4953 || expr1
.X_add_number
>= 0x8000 - 4)
4954 as_bad ("PIC code offset overflow (max 16 signed bits)");
4959 frag_grow (24 + off
);
4960 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4961 mips_isa
< 3 ? "lw" : "ld",
4962 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4966 mips_isa
< 3 ? "addu" : "daddu",
4967 "d,v,t", AT
, breg
, AT
);
4968 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4969 coproc
? treg
+ 1 : treg
,
4970 (int) BFD_RELOC_LO16
, AT
);
4971 expr1
.X_add_number
+= 4;
4973 /* Set mips_optimize to 2 to avoid inserting an undesired
4975 hold_mips_optimize
= mips_optimize
;
4977 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4978 coproc
? treg
: treg
+ 1,
4979 (int) BFD_RELOC_LO16
, AT
);
4980 mips_optimize
= hold_mips_optimize
;
4982 (void) frag_var (rs_machine_dependent
, 0, 0,
4983 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4984 offset_expr
.X_add_symbol
, (long) 0,
4987 else if (mips_pic
== SVR4_PIC
)
4991 /* If this is a reference to an external symbol, we want
4992 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4994 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4999 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5001 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5002 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5003 If there is a base register we add it to $at before the
5004 lwc1 instructions. If there is a constant we include it
5005 in the lwc1 instructions. */
5007 expr1
.X_add_number
= offset_expr
.X_add_number
;
5008 offset_expr
.X_add_number
= 0;
5009 if (expr1
.X_add_number
< -0x8000
5010 || expr1
.X_add_number
>= 0x8000 - 4)
5011 as_bad ("PIC code offset overflow (max 16 signed bits)");
5012 if (reg_needs_delay (GP
))
5021 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5022 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5024 mips_isa
< 3 ? "addu" : "daddu",
5025 "d,v,t", AT
, AT
, GP
);
5026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5027 mips_isa
< 3 ? "lw" : "ld",
5028 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5029 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5031 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5032 mips_isa
< 3 ? "addu" : "daddu",
5033 "d,v,t", AT
, breg
, AT
);
5034 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5035 coproc
? treg
+ 1 : treg
,
5036 (int) BFD_RELOC_LO16
, AT
);
5037 expr1
.X_add_number
+= 4;
5039 /* Set mips_optimize to 2 to avoid inserting an undesired
5041 hold_mips_optimize
= mips_optimize
;
5043 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5044 coproc
? treg
: treg
+ 1,
5045 (int) BFD_RELOC_LO16
, AT
);
5046 mips_optimize
= hold_mips_optimize
;
5047 expr1
.X_add_number
-= 4;
5049 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5050 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5051 8 + gpdel
+ off
, 1, 0),
5052 offset_expr
.X_add_symbol
, (long) 0,
5056 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5059 macro_build (p
, &icnt
, &offset_expr
,
5060 mips_isa
< 3 ? "lw" : "ld",
5061 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5063 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5067 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5068 mips_isa
< 3 ? "addu" : "daddu",
5069 "d,v,t", AT
, breg
, AT
);
5072 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5073 coproc
? treg
+ 1 : treg
,
5074 (int) BFD_RELOC_LO16
, AT
);
5076 expr1
.X_add_number
+= 4;
5078 /* Set mips_optimize to 2 to avoid inserting an undesired
5080 hold_mips_optimize
= mips_optimize
;
5082 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5083 coproc
? treg
: treg
+ 1,
5084 (int) BFD_RELOC_LO16
, AT
);
5085 mips_optimize
= hold_mips_optimize
;
5087 else if (mips_pic
== EMBEDDED_PIC
)
5089 /* If there is no base register, we use
5090 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5091 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5092 If we have a base register, we use
5094 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5095 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5105 mips_isa
< 3 ? "addu" : "daddu",
5106 "d,v,t", AT
, breg
, GP
);
5111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5112 coproc
? treg
+ 1 : treg
,
5113 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5114 offset_expr
.X_add_number
+= 4;
5115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5116 coproc
? treg
: treg
+ 1,
5117 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5133 assert (mips_isa
< 3);
5134 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5135 (int) BFD_RELOC_LO16
, breg
);
5136 offset_expr
.X_add_number
+= 4;
5137 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5138 (int) BFD_RELOC_LO16
, breg
);
5140 #ifdef LOSING_COMPILER
5146 as_warn ("Macro used $at after \".set noat\"");
5151 struct mips_cl_insn
*ip
;
5153 register int treg
, sreg
, dreg
, breg
;
5168 bfd_reloc_code_real_type r
;
5171 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5172 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5173 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5174 mask
= ip
->insn_mo
->mask
;
5176 expr1
.X_op
= O_constant
;
5177 expr1
.X_op_symbol
= NULL
;
5178 expr1
.X_add_symbol
= NULL
;
5179 expr1
.X_add_number
= 1;
5183 #endif /* LOSING_COMPILER */
5188 macro_build ((char *) NULL
, &icnt
, NULL
,
5189 dbl
? "dmultu" : "multu",
5191 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5197 /* The MIPS assembler some times generates shifts and adds. I'm
5198 not trying to be that fancy. GCC should do this for us
5200 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5201 macro_build ((char *) NULL
, &icnt
, NULL
,
5202 dbl
? "dmult" : "mult",
5204 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5210 mips_emit_delays (true);
5212 mips_any_noreorder
= 1;
5213 macro_build ((char *) NULL
, &icnt
, NULL
,
5214 dbl
? "dmult" : "mult",
5216 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5217 macro_build ((char *) NULL
, &icnt
, NULL
,
5218 dbl
? "dsra32" : "sra",
5219 "d,w,<", dreg
, dreg
, 31);
5220 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5222 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5225 expr1
.X_add_number
= 8;
5226 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5227 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5228 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5231 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5237 mips_emit_delays (true);
5239 mips_any_noreorder
= 1;
5240 macro_build ((char *) NULL
, &icnt
, NULL
,
5241 dbl
? "dmultu" : "multu",
5243 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5244 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5246 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5249 expr1
.X_add_number
= 8;
5250 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5251 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5252 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5258 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5259 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5260 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5262 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5266 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5267 (int) (imm_expr
.X_add_number
& 0x1f));
5268 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5269 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5270 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5274 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5275 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5276 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5278 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5282 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5283 (int) (imm_expr
.X_add_number
& 0x1f));
5284 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5285 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5286 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5290 assert (mips_isa
< 2);
5291 /* Even on a big endian machine $fn comes before $fn+1. We have
5292 to adjust when storing to memory. */
5293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5294 target_big_endian
? treg
+ 1 : treg
,
5295 (int) BFD_RELOC_LO16
, breg
);
5296 offset_expr
.X_add_number
+= 4;
5297 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5298 target_big_endian
? treg
: treg
+ 1,
5299 (int) BFD_RELOC_LO16
, breg
);
5304 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5305 treg
, (int) BFD_RELOC_LO16
);
5307 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5308 sreg
, (int) BFD_RELOC_LO16
);
5311 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5313 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5314 dreg
, (int) BFD_RELOC_LO16
);
5319 if (imm_expr
.X_add_number
== 0)
5321 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5322 sreg
, (int) BFD_RELOC_LO16
);
5327 as_warn ("Instruction %s: result is always false",
5329 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5332 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5334 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5335 sreg
, (int) BFD_RELOC_LO16
);
5338 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5340 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5341 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5342 mips_isa
< 3 ? "addiu" : "daddiu",
5343 "t,r,j", dreg
, sreg
,
5344 (int) BFD_RELOC_LO16
);
5349 load_register (&icnt
, AT
, &imm_expr
, 0);
5350 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5354 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5355 (int) BFD_RELOC_LO16
);
5360 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5366 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5367 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5368 (int) BFD_RELOC_LO16
);
5371 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5373 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5375 macro_build ((char *) NULL
, &icnt
, &expr1
,
5376 mask
== M_SGE_I
? "slti" : "sltiu",
5377 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5382 load_register (&icnt
, AT
, &imm_expr
, 0);
5383 macro_build ((char *) NULL
, &icnt
, NULL
,
5384 mask
== M_SGE_I
? "slt" : "sltu",
5385 "d,v,t", dreg
, sreg
, AT
);
5388 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5389 (int) BFD_RELOC_LO16
);
5394 case M_SGT
: /* sreg > treg <==> treg < sreg */
5400 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5403 case M_SGT_I
: /* sreg > I <==> I < sreg */
5409 load_register (&icnt
, AT
, &imm_expr
, 0);
5410 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5413 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5419 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5420 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5421 (int) BFD_RELOC_LO16
);
5424 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5430 load_register (&icnt
, AT
, &imm_expr
, 0);
5431 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5432 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5433 (int) BFD_RELOC_LO16
);
5437 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5439 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5440 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5443 load_register (&icnt
, AT
, &imm_expr
, 0);
5444 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5448 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5450 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5451 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5454 load_register (&icnt
, AT
, &imm_expr
, 0);
5455 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5461 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5464 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5468 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5470 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5476 if (imm_expr
.X_add_number
== 0)
5478 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5484 as_warn ("Instruction %s: result is always true",
5486 macro_build ((char *) NULL
, &icnt
, &expr1
,
5487 mips_isa
< 3 ? "addiu" : "daddiu",
5488 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5491 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5493 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5494 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5497 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5499 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5500 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5501 mips_isa
< 3 ? "addiu" : "daddiu",
5502 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5507 load_register (&icnt
, AT
, &imm_expr
, 0);
5508 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5512 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5520 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5522 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5523 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5524 dbl
? "daddi" : "addi",
5525 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5528 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5529 macro_build ((char *) NULL
, &icnt
, NULL
,
5530 dbl
? "dsub" : "sub",
5531 "d,v,t", dreg
, sreg
, AT
);
5537 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5539 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5540 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5541 dbl
? "daddiu" : "addiu",
5542 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5545 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5546 macro_build ((char *) NULL
, &icnt
, NULL
,
5547 dbl
? "dsubu" : "subu",
5548 "d,v,t", dreg
, sreg
, AT
);
5569 load_register (&icnt
, AT
, &imm_expr
, 0);
5570 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5575 assert (mips_isa
< 2);
5576 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5577 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5580 * Is the double cfc1 instruction a bug in the mips assembler;
5581 * or is there a reason for it?
5583 mips_emit_delays (true);
5585 mips_any_noreorder
= 1;
5586 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5587 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5588 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5589 expr1
.X_add_number
= 3;
5590 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5591 (int) BFD_RELOC_LO16
);
5592 expr1
.X_add_number
= 2;
5593 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5594 (int) BFD_RELOC_LO16
);
5595 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5596 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5597 macro_build ((char *) NULL
, &icnt
, NULL
,
5598 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5599 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5600 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5610 if (offset_expr
.X_add_number
>= 0x7fff)
5611 as_bad ("operand overflow");
5612 /* avoid load delay */
5613 if (! target_big_endian
)
5614 offset_expr
.X_add_number
+= 1;
5615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5616 (int) BFD_RELOC_LO16
, breg
);
5617 if (! target_big_endian
)
5618 offset_expr
.X_add_number
-= 1;
5620 offset_expr
.X_add_number
+= 1;
5621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5622 (int) BFD_RELOC_LO16
, breg
);
5623 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5624 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5637 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5638 as_bad ("operand overflow");
5639 if (! target_big_endian
)
5640 offset_expr
.X_add_number
+= off
;
5641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5642 (int) BFD_RELOC_LO16
, breg
);
5643 if (! target_big_endian
)
5644 offset_expr
.X_add_number
-= off
;
5646 offset_expr
.X_add_number
+= off
;
5647 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5648 (int) BFD_RELOC_LO16
, breg
);
5661 load_address (&icnt
, AT
, &offset_expr
);
5663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5664 mips_isa
< 3 ? "addu" : "daddu",
5665 "d,v,t", AT
, AT
, breg
);
5666 if (! target_big_endian
)
5667 expr1
.X_add_number
= off
;
5669 expr1
.X_add_number
= 0;
5670 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5671 (int) BFD_RELOC_LO16
, AT
);
5672 if (! target_big_endian
)
5673 expr1
.X_add_number
= 0;
5675 expr1
.X_add_number
= off
;
5676 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5677 (int) BFD_RELOC_LO16
, AT
);
5682 load_address (&icnt
, AT
, &offset_expr
);
5684 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5685 mips_isa
< 3 ? "addu" : "daddu",
5686 "d,v,t", AT
, AT
, breg
);
5687 if (target_big_endian
)
5688 expr1
.X_add_number
= 0;
5689 macro_build ((char *) NULL
, &icnt
, &expr1
,
5690 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5691 (int) BFD_RELOC_LO16
, AT
);
5692 if (target_big_endian
)
5693 expr1
.X_add_number
= 1;
5695 expr1
.X_add_number
= 0;
5696 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5697 (int) BFD_RELOC_LO16
, AT
);
5698 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5700 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5705 if (offset_expr
.X_add_number
>= 0x7fff)
5706 as_bad ("operand overflow");
5707 if (target_big_endian
)
5708 offset_expr
.X_add_number
+= 1;
5709 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5710 (int) BFD_RELOC_LO16
, breg
);
5711 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5712 if (target_big_endian
)
5713 offset_expr
.X_add_number
-= 1;
5715 offset_expr
.X_add_number
+= 1;
5716 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5717 (int) BFD_RELOC_LO16
, breg
);
5730 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5731 as_bad ("operand overflow");
5732 if (! target_big_endian
)
5733 offset_expr
.X_add_number
+= off
;
5734 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5735 (int) BFD_RELOC_LO16
, breg
);
5736 if (! target_big_endian
)
5737 offset_expr
.X_add_number
-= off
;
5739 offset_expr
.X_add_number
+= off
;
5740 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5741 (int) BFD_RELOC_LO16
, breg
);
5754 load_address (&icnt
, AT
, &offset_expr
);
5756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5757 mips_isa
< 3 ? "addu" : "daddu",
5758 "d,v,t", AT
, AT
, breg
);
5759 if (! target_big_endian
)
5760 expr1
.X_add_number
= off
;
5762 expr1
.X_add_number
= 0;
5763 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5764 (int) BFD_RELOC_LO16
, AT
);
5765 if (! target_big_endian
)
5766 expr1
.X_add_number
= 0;
5768 expr1
.X_add_number
= off
;
5769 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5770 (int) BFD_RELOC_LO16
, AT
);
5774 load_address (&icnt
, AT
, &offset_expr
);
5776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5777 mips_isa
< 3 ? "addu" : "daddu",
5778 "d,v,t", AT
, AT
, breg
);
5779 if (! target_big_endian
)
5780 expr1
.X_add_number
= 0;
5781 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5782 (int) BFD_RELOC_LO16
, AT
);
5783 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5785 if (! target_big_endian
)
5786 expr1
.X_add_number
= 1;
5788 expr1
.X_add_number
= 0;
5789 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5790 (int) BFD_RELOC_LO16
, AT
);
5791 if (! target_big_endian
)
5792 expr1
.X_add_number
= 0;
5794 expr1
.X_add_number
= 1;
5795 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5796 (int) BFD_RELOC_LO16
, AT
);
5797 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5799 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5804 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5808 as_warn ("Macro used $at after \".set noat\"");
5811 /* Implement macros in mips16 mode. */
5815 struct mips_cl_insn
*ip
;
5818 int xreg
, yreg
, zreg
, tmp
;
5822 const char *s
, *s2
, *s3
;
5824 mask
= ip
->insn_mo
->mask
;
5826 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5827 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5828 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5832 expr1
.X_op
= O_constant
;
5833 expr1
.X_op_symbol
= NULL
;
5834 expr1
.X_add_symbol
= NULL
;
5835 expr1
.X_add_number
= 1;
5854 mips_emit_delays (true);
5856 mips_any_noreorder
= 1;
5857 macro_build ((char *) NULL
, &icnt
, NULL
,
5858 dbl
? "ddiv" : "div",
5859 "0,x,y", xreg
, yreg
);
5860 expr1
.X_add_number
= 2;
5861 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5862 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5863 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5864 since that causes an overflow. We should do that as well,
5865 but I don't see how to do the comparisons without a temporary
5868 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5887 mips_emit_delays (true);
5889 mips_any_noreorder
= 1;
5890 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5891 expr1
.X_add_number
= 2;
5892 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5893 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5895 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5903 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5904 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5905 dbl
? "daddiu" : "addiu",
5906 "y,x,4", yreg
, xreg
);
5910 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5911 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5916 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5917 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5940 goto do_reverse_branch
;
5944 goto do_reverse_branch
;
5956 goto do_reverse_branch
;
5967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5996 goto do_addone_branch_i
;
6001 goto do_addone_branch_i
;
6016 goto do_addone_branch_i
;
6023 ++imm_expr
.X_add_number
;
6026 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6027 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6031 expr1
.X_add_number
= 0;
6032 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6034 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6035 "move", "y,X", xreg
, yreg
);
6036 expr1
.X_add_number
= 2;
6037 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6038 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6039 "neg", "x,w", xreg
, xreg
);
6043 /* This routine assembles an instruction into its binary format. As a
6044 side effect, it sets one of the global variables imm_reloc or
6045 offset_reloc to the type of relocation to do if one of the operands
6046 is an address expression. */
6051 struct mips_cl_insn
*ip
;
6056 struct mips_opcode
*insn
;
6059 unsigned int lastregno
= 0;
6064 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6076 as_fatal ("Unknown opcode: `%s'", str
);
6078 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6080 insn_error
= "unrecognized opcode";
6088 assert (strcmp (insn
->name
, str
) == 0);
6090 if (insn
->pinfo
== INSN_MACRO
)
6091 insn_isa
= insn
->match
;
6092 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6094 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6096 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6101 if (insn_isa
> mips_isa
6102 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
6104 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6106 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6109 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6110 && strcmp (insn
->name
, insn
[1].name
) == 0)
6115 if (insn_isa
<= mips_isa
)
6116 insn_error
= "opcode not supported on this processor";
6119 static char buf
[100];
6121 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6128 ip
->insn_opcode
= insn
->match
;
6129 for (args
= insn
->args
;; ++args
)
6135 case '\0': /* end of args */
6148 ip
->insn_opcode
|= lastregno
<< 21;
6153 ip
->insn_opcode
|= lastregno
<< 16;
6157 ip
->insn_opcode
|= lastregno
<< 11;
6163 /* handle optional base register.
6164 Either the base register is omitted or
6165 we must have a left paren. */
6166 /* this is dependent on the next operand specifier
6167 is a 'b' for base register */
6168 assert (args
[1] == 'b');
6172 case ')': /* these must match exactly */
6177 case '<': /* must be at least one digit */
6179 * According to the manual, if the shift amount is greater
6180 * than 31 or less than 0 the the shift amount should be
6181 * mod 32. In reality the mips assembler issues an error.
6182 * We issue a warning and mask out all but the low 5 bits.
6184 my_getExpression (&imm_expr
, s
);
6185 check_absolute_expr (ip
, &imm_expr
);
6186 if ((unsigned long) imm_expr
.X_add_number
> 31)
6188 as_warn ("Improper shift amount (%ld)",
6189 (long) imm_expr
.X_add_number
);
6190 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6192 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6193 imm_expr
.X_op
= O_absent
;
6197 case '>': /* shift amount minus 32 */
6198 my_getExpression (&imm_expr
, s
);
6199 check_absolute_expr (ip
, &imm_expr
);
6200 if ((unsigned long) imm_expr
.X_add_number
< 32
6201 || (unsigned long) imm_expr
.X_add_number
> 63)
6203 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6204 imm_expr
.X_op
= O_absent
;
6208 case 'k': /* cache code */
6209 case 'h': /* prefx code */
6210 my_getExpression (&imm_expr
, s
);
6211 check_absolute_expr (ip
, &imm_expr
);
6212 if ((unsigned long) imm_expr
.X_add_number
> 31)
6214 as_warn ("Invalid value for `%s' (%lu)",
6216 (unsigned long) imm_expr
.X_add_number
);
6217 imm_expr
.X_add_number
&= 0x1f;
6220 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6222 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6223 imm_expr
.X_op
= O_absent
;
6227 case 'c': /* break code */
6228 my_getExpression (&imm_expr
, s
);
6229 check_absolute_expr (ip
, &imm_expr
);
6230 if ((unsigned) imm_expr
.X_add_number
> 1023)
6231 as_warn ("Illegal break code (%ld)",
6232 (long) imm_expr
.X_add_number
);
6233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6234 imm_expr
.X_op
= O_absent
;
6238 case 'B': /* syscall code */
6239 my_getExpression (&imm_expr
, s
);
6240 check_absolute_expr (ip
, &imm_expr
);
6241 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6242 as_warn ("Illegal syscall code (%ld)",
6243 (long) imm_expr
.X_add_number
);
6244 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6245 imm_expr
.X_op
= O_absent
;
6249 case 'C': /* Coprocessor code */
6250 my_getExpression (&imm_expr
, s
);
6251 check_absolute_expr (ip
, &imm_expr
);
6252 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6254 as_warn ("Coproccesor code > 25 bits (%ld)",
6255 (long) imm_expr
.X_add_number
);
6256 imm_expr
.X_add_number
&= ((1<<25) - 1);
6258 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6259 imm_expr
.X_op
= O_absent
;
6263 case 'b': /* base register */
6264 case 'd': /* destination register */
6265 case 's': /* source register */
6266 case 't': /* target register */
6267 case 'r': /* both target and source */
6268 case 'v': /* both dest and source */
6269 case 'w': /* both dest and target */
6270 case 'E': /* coprocessor target register */
6271 case 'G': /* coprocessor destination register */
6272 case 'x': /* ignore register name */
6273 case 'z': /* must be zero register */
6287 while (isdigit (*s
));
6289 as_bad ("Invalid register number (%d)", regno
);
6291 else if (*args
== 'E' || *args
== 'G')
6295 if (s
[1] == 'f' && s
[2] == 'p')
6300 else if (s
[1] == 's' && s
[2] == 'p')
6305 else if (s
[1] == 'g' && s
[2] == 'p')
6310 else if (s
[1] == 'a' && s
[2] == 't')
6315 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6320 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6332 as_warn ("Used $at without \".set noat\"");
6338 if (c
== 'r' || c
== 'v' || c
== 'w')
6345 /* 'z' only matches $0. */
6346 if (c
== 'z' && regno
!= 0)
6354 ip
->insn_opcode
|= regno
<< 21;
6358 ip
->insn_opcode
|= regno
<< 11;
6363 ip
->insn_opcode
|= regno
<< 16;
6366 /* This case exists because on the r3000 trunc
6367 expands into a macro which requires a gp
6368 register. On the r6000 or r4000 it is
6369 assembled into a single instruction which
6370 ignores the register. Thus the insn version
6371 is MIPS_ISA2 and uses 'x', and the macro
6372 version is MIPS_ISA1 and uses 't'. */
6375 /* This case is for the div instruction, which
6376 acts differently if the destination argument
6377 is $0. This only matches $0, and is checked
6378 outside the switch. */
6389 ip
->insn_opcode
|= lastregno
<< 21;
6392 ip
->insn_opcode
|= lastregno
<< 16;
6397 case 'D': /* floating point destination register */
6398 case 'S': /* floating point source register */
6399 case 'T': /* floating point target register */
6400 case 'R': /* floating point source register */
6404 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6414 while (isdigit (*s
));
6417 as_bad ("Invalid float register number (%d)", regno
);
6419 if ((regno
& 1) != 0
6421 && ! (strcmp (str
, "mtc1") == 0
6422 || strcmp (str
, "mfc1") == 0
6423 || strcmp (str
, "lwc1") == 0
6424 || strcmp (str
, "swc1") == 0
6425 || strcmp (str
, "l.s") == 0
6426 || strcmp (str
, "s.s") == 0))
6427 as_warn ("Float register should be even, was %d",
6435 if (c
== 'V' || c
== 'W')
6445 ip
->insn_opcode
|= regno
<< 6;
6449 ip
->insn_opcode
|= regno
<< 11;
6453 ip
->insn_opcode
|= regno
<< 16;
6456 ip
->insn_opcode
|= regno
<< 21;
6465 ip
->insn_opcode
|= lastregno
<< 11;
6468 ip
->insn_opcode
|= lastregno
<< 16;
6474 my_getExpression (&imm_expr
, s
);
6475 if (imm_expr
.X_op
!= O_big
6476 && imm_expr
.X_op
!= O_constant
)
6477 insn_error
= "absolute expression required";
6482 my_getExpression (&offset_expr
, s
);
6483 imm_reloc
= BFD_RELOC_32
;
6495 unsigned char temp
[8];
6497 unsigned int length
;
6502 /* These only appear as the last operand in an
6503 instruction, and every instruction that accepts
6504 them in any variant accepts them in all variants.
6505 This means we don't have to worry about backing out
6506 any changes if the instruction does not match.
6508 The difference between them is the size of the
6509 floating point constant and where it goes. For 'F'
6510 and 'L' the constant is 64 bits; for 'f' and 'l' it
6511 is 32 bits. Where the constant is placed is based
6512 on how the MIPS assembler does things:
6515 f -- immediate value
6518 The .lit4 and .lit8 sections are only used if
6519 permitted by the -G argument.
6521 When generating embedded PIC code, we use the
6522 .lit8 section but not the .lit4 section (we can do
6523 .lit4 inline easily; we need to put .lit8
6524 somewhere in the data segment, and using .lit8
6525 permits the linker to eventually combine identical
6528 f64
= *args
== 'F' || *args
== 'L';
6530 save_in
= input_line_pointer
;
6531 input_line_pointer
= s
;
6532 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6534 s
= input_line_pointer
;
6535 input_line_pointer
= save_in
;
6536 if (err
!= NULL
&& *err
!= '\0')
6538 as_bad ("Bad floating point constant: %s", err
);
6539 memset (temp
, '\0', sizeof temp
);
6540 length
= f64
? 8 : 4;
6543 assert (length
== (f64
? 8 : 4));
6547 && (! USE_GLOBAL_POINTER_OPT
6548 || mips_pic
== EMBEDDED_PIC
6549 || g_switch_value
< 4)
6552 imm_expr
.X_op
= O_constant
;
6553 if (! target_big_endian
)
6554 imm_expr
.X_add_number
=
6555 (((((((int) temp
[3] << 8)
6560 imm_expr
.X_add_number
=
6561 (((((((int) temp
[0] << 8)
6568 const char *newname
;
6571 /* Switch to the right section. */
6573 subseg
= now_subseg
;
6576 default: /* unused default case avoids warnings. */
6578 newname
= RDATA_SECTION_NAME
;
6579 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6583 newname
= RDATA_SECTION_NAME
;
6586 assert (!USE_GLOBAL_POINTER_OPT
6587 || g_switch_value
>= 4);
6591 new_seg
= subseg_new (newname
, (subsegT
) 0);
6592 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6593 bfd_set_section_flags (stdoutput
, new_seg
,
6598 frag_align (*args
== 'l' ? 2 : 3, 0);
6599 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6600 record_alignment (new_seg
, 4);
6602 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6604 as_bad ("Can't use floating point insn in this section");
6606 /* Set the argument to the current address in the
6608 offset_expr
.X_op
= O_symbol
;
6609 offset_expr
.X_add_symbol
=
6610 symbol_new ("L0\001", now_seg
,
6611 (valueT
) frag_now_fix (), frag_now
);
6612 offset_expr
.X_add_number
= 0;
6614 /* Put the floating point number into the section. */
6615 p
= frag_more ((int) length
);
6616 memcpy (p
, temp
, length
);
6618 /* Switch back to the original section. */
6619 subseg_set (seg
, subseg
);
6624 case 'i': /* 16 bit unsigned immediate */
6625 case 'j': /* 16 bit signed immediate */
6626 imm_reloc
= BFD_RELOC_LO16
;
6627 c
= my_getSmallExpression (&imm_expr
, s
);
6632 if (imm_expr
.X_op
== O_constant
)
6633 imm_expr
.X_add_number
=
6634 (imm_expr
.X_add_number
>> 16) & 0xffff;
6637 imm_reloc
= BFD_RELOC_HI16_S
;
6638 imm_unmatched_hi
= true;
6641 imm_reloc
= BFD_RELOC_HI16
;
6646 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6647 || ((imm_expr
.X_add_number
< 0
6648 || imm_expr
.X_add_number
>= 0x10000)
6649 && imm_expr
.X_op
== O_constant
))
6651 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6652 !strcmp (insn
->name
, insn
[1].name
))
6654 if (imm_expr
.X_op
!= O_constant
6655 && imm_expr
.X_op
!= O_big
)
6656 insn_error
= "absolute expression required";
6658 as_bad ("16 bit expression not in range 0..65535");
6666 /* The upper bound should be 0x8000, but
6667 unfortunately the MIPS assembler accepts numbers
6668 from 0x8000 to 0xffff and sign extends them, and
6669 we want to be compatible. We only permit this
6670 extended range for an instruction which does not
6671 provide any further alternates, since those
6672 alternates may handle other cases. People should
6673 use the numbers they mean, rather than relying on
6674 a mysterious sign extension. */
6675 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6676 strcmp (insn
->name
, insn
[1].name
) == 0);
6681 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6682 || ((imm_expr
.X_add_number
< -0x8000
6683 || imm_expr
.X_add_number
>= max
)
6684 && imm_expr
.X_op
== O_constant
)
6686 && imm_expr
.X_add_number
< 0
6688 && imm_expr
.X_unsigned
6689 && sizeof (imm_expr
.X_add_number
) <= 4))
6693 if (imm_expr
.X_op
!= O_constant
6694 && imm_expr
.X_op
!= O_big
)
6695 insn_error
= "absolute expression required";
6697 as_bad ("16 bit expression not in range -32768..32767");
6703 case 'o': /* 16 bit offset */
6704 c
= my_getSmallExpression (&offset_expr
, s
);
6706 /* If this value won't fit into a 16 bit offset, then go
6707 find a macro that will generate the 32 bit offset
6708 code pattern. As a special hack, we accept the
6709 difference of two local symbols as a constant. This
6710 is required to suppose embedded PIC switches, which
6711 use an instruction which looks like
6712 lw $4,$L12-$LS12($4)
6713 The problem with handling this in a more general
6714 fashion is that the macro function doesn't expect to
6715 see anything which can be handled in a single
6716 constant instruction. */
6718 && (offset_expr
.X_op
!= O_constant
6719 || offset_expr
.X_add_number
>= 0x8000
6720 || offset_expr
.X_add_number
< -0x8000)
6721 && (mips_pic
!= EMBEDDED_PIC
6722 || offset_expr
.X_op
!= O_subtract
6723 || now_seg
!= text_section
6724 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6728 offset_reloc
= BFD_RELOC_LO16
;
6729 if (c
== 'h' || c
== 'H')
6731 assert (offset_expr
.X_op
== O_constant
);
6732 offset_expr
.X_add_number
=
6733 (offset_expr
.X_add_number
>> 16) & 0xffff;
6738 case 'p': /* pc relative offset */
6739 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6740 my_getExpression (&offset_expr
, s
);
6744 case 'u': /* upper 16 bits */
6745 c
= my_getSmallExpression (&imm_expr
, s
);
6746 if (imm_expr
.X_op
== O_constant
6747 && (imm_expr
.X_add_number
< 0
6748 || imm_expr
.X_add_number
>= 0x10000))
6749 as_bad ("lui expression not in range 0..65535");
6750 imm_reloc
= BFD_RELOC_LO16
;
6755 if (imm_expr
.X_op
== O_constant
)
6756 imm_expr
.X_add_number
=
6757 (imm_expr
.X_add_number
>> 16) & 0xffff;
6760 imm_reloc
= BFD_RELOC_HI16_S
;
6761 imm_unmatched_hi
= true;
6764 imm_reloc
= BFD_RELOC_HI16
;
6770 case 'a': /* 26 bit address */
6771 my_getExpression (&offset_expr
, s
);
6773 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6776 case 'N': /* 3 bit branch condition code */
6777 case 'M': /* 3 bit compare condition code */
6778 if (strncmp (s
, "$fcc", 4) != 0)
6788 while (isdigit (*s
));
6790 as_bad ("invalid condition code register $fcc%d", regno
);
6792 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6794 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6798 fprintf (stderr
, "bad char = '%c'\n", *args
);
6803 /* Args don't match. */
6804 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6805 !strcmp (insn
->name
, insn
[1].name
))
6811 insn_error
= "illegal operands";
6816 /* This routine assembles an instruction into its binary format when
6817 assembling for the mips16. As a side effect, it sets one of the
6818 global variables imm_reloc or offset_reloc to the type of
6819 relocation to do if one of the operands is an address expression.
6820 It also sets mips16_small and mips16_ext if the user explicitly
6821 requested a small or extended instruction. */
6826 struct mips_cl_insn
*ip
;
6830 struct mips_opcode
*insn
;
6833 unsigned int lastregno
= 0;
6838 mips16_small
= false;
6841 for (s
= str
; islower (*s
); ++s
)
6853 if (s
[1] == 't' && s
[2] == ' ')
6856 mips16_small
= true;
6860 else if (s
[1] == 'e' && s
[2] == ' ')
6869 insn_error
= "unknown opcode";
6873 if (! mips16_autoextend
&& ! mips16_ext
)
6874 mips16_small
= true;
6876 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6878 insn_error
= "unrecognized opcode";
6885 assert (strcmp (insn
->name
, str
) == 0);
6888 ip
->insn_opcode
= insn
->match
;
6889 ip
->use_extend
= false;
6890 imm_expr
.X_op
= O_absent
;
6891 imm_reloc
= BFD_RELOC_UNUSED
;
6892 offset_expr
.X_op
= O_absent
;
6893 offset_reloc
= BFD_RELOC_UNUSED
;
6894 for (args
= insn
->args
; 1; ++args
)
6901 /* In this switch statement we call break if we did not find
6902 a match, continue if we did find a match, or return if we
6911 /* Stuff the immediate value in now, if we can. */
6912 if (imm_expr
.X_op
== O_constant
6913 && imm_reloc
> BFD_RELOC_UNUSED
6914 && insn
->pinfo
!= INSN_MACRO
)
6916 mips16_immed ((char *) NULL
, 0,
6917 imm_reloc
- BFD_RELOC_UNUSED
,
6918 imm_expr
.X_add_number
, true, mips16_small
,
6919 mips16_ext
, &ip
->insn_opcode
,
6920 &ip
->use_extend
, &ip
->extend
);
6921 imm_expr
.X_op
= O_absent
;
6922 imm_reloc
= BFD_RELOC_UNUSED
;
6936 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6939 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6955 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6957 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6984 while (isdigit (*s
));
6987 as_bad ("invalid register number (%d)", regno
);
6993 if (s
[1] == 'f' && s
[2] == 'p')
6998 else if (s
[1] == 's' && s
[2] == 'p')
7003 else if (s
[1] == 'g' && s
[2] == 'p')
7008 else if (s
[1] == 'a' && s
[2] == 't')
7013 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7018 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7031 if (c
== 'v' || c
== 'w')
7033 regno
= mips16_to_32_reg_map
[lastregno
];
7047 regno
= mips32_to_16_reg_map
[regno
];
7052 regno
= ILLEGAL_REG
;
7057 regno
= ILLEGAL_REG
;
7062 regno
= ILLEGAL_REG
;
7067 if (regno
== AT
&& ! mips_noat
)
7068 as_warn ("used $at without \".set noat\"");
7075 if (regno
== ILLEGAL_REG
)
7082 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7086 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7089 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7092 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7098 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7101 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7102 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7112 if (strncmp (s
, "$pc", 3) == 0)
7135 if (s
[0] == '$' && isdigit (s
[1]))
7137 /* Looks like a register name. */
7145 /* It looks like the expression was omitted before a
7146 register indirection, which means that the
7147 expression is implicitly zero. */
7151 my_getExpression (&imm_expr
, s
);
7152 /* We need to relax this instruction. */
7153 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7162 /* We use offset_reloc rather than imm_reloc for the PC
7163 relative operands. This lets macros with both
7164 immediate and address operands work correctly. */
7165 if (s
[0] == '$' && isdigit (s
[1]))
7167 /* Looks like a register name. */
7170 my_getExpression (&offset_expr
, s
);
7171 /* We need to relax this instruction. */
7172 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7176 case '6': /* break code */
7177 my_getExpression (&imm_expr
, s
);
7178 check_absolute_expr (ip
, &imm_expr
);
7179 if ((unsigned long) imm_expr
.X_add_number
> 63)
7181 as_warn ("Invalid value for `%s' (%lu)",
7183 (unsigned long) imm_expr
.X_add_number
);
7184 imm_expr
.X_add_number
&= 0x3f;
7186 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7187 imm_expr
.X_op
= O_absent
;
7191 case 'a': /* 26 bit address */
7192 my_getExpression (&offset_expr
, s
);
7194 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7195 ip
->insn_opcode
<<= 16;
7198 case 'l': /* register list for entry macro */
7199 case 'L': /* register list for exit macro */
7211 while (*s
== ' ' || *s
== ',')
7215 as_bad ("can't parse register list");
7220 while (isdigit (*s
))
7237 while (isdigit (*s
))
7244 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7245 mask
|= (reg2
- 3) << 3;
7246 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7247 mask
|= (reg2
- 15) << 1;
7248 else if (reg1
== 31 && reg2
== 31)
7251 as_bad ("invalid register list");
7253 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7263 /* Args don't match. */
7264 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7265 strcmp (insn
->name
, insn
[1].name
) == 0)
7272 insn_error
= "illegal operands";
7278 /* This structure holds information we know about a mips16 immediate
7281 struct mips16_immed_operand
7283 /* The type code used in the argument string in the opcode table. */
7285 /* The number of bits in the short form of the opcode. */
7287 /* The number of bits in the extended form of the opcode. */
7289 /* The amount by which the short form is shifted when it is used;
7290 for example, the sw instruction has a shift count of 2. */
7292 /* The amount by which the short form is shifted when it is stored
7293 into the instruction code. */
7295 /* Non-zero if the short form is unsigned. */
7297 /* Non-zero if the extended form is unsigned. */
7299 /* Non-zero if the value is PC relative. */
7303 /* The mips16 immediate operand types. */
7305 static const struct mips16_immed_operand mips16_immed_operands
[] =
7307 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7308 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7309 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7310 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7311 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7312 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7313 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7314 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7315 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7316 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7317 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7318 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7319 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7320 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7321 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7322 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7323 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7324 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7325 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7326 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7327 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7330 #define MIPS16_NUM_IMMED \
7331 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7333 /* Handle a mips16 instruction with an immediate value. This or's the
7334 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7335 whether an extended value is needed; if one is needed, it sets
7336 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7337 If SMALL is true, an unextended opcode was explicitly requested.
7338 If EXT is true, an extended opcode was explicitly requested. If
7339 WARN is true, warn if EXT does not match reality. */
7342 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7351 unsigned long *insn
;
7352 boolean
*use_extend
;
7353 unsigned short *extend
;
7355 register const struct mips16_immed_operand
*op
;
7356 int mintiny
, maxtiny
;
7359 op
= mips16_immed_operands
;
7360 while (op
->type
!= type
)
7363 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7368 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7371 maxtiny
= 1 << op
->nbits
;
7376 maxtiny
= (1 << op
->nbits
) - 1;
7381 mintiny
= - (1 << (op
->nbits
- 1));
7382 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7385 /* Branch offsets have an implicit 0 in the lowest bit. */
7386 if (type
== 'p' || type
== 'q')
7389 if ((val
& ((1 << op
->shift
) - 1)) != 0
7390 || val
< (mintiny
<< op
->shift
)
7391 || val
> (maxtiny
<< op
->shift
))
7396 if (warn
&& ext
&& ! needext
)
7397 as_warn_where (file
, line
, "extended operand requested but not required");
7398 if (small
&& needext
)
7399 as_bad_where (file
, line
, "invalid unextended operand value");
7401 if (small
|| (! ext
&& ! needext
))
7405 *use_extend
= false;
7406 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7407 insnval
<<= op
->op_shift
;
7412 long minext
, maxext
;
7418 maxext
= (1 << op
->extbits
) - 1;
7422 minext
= - (1 << (op
->extbits
- 1));
7423 maxext
= (1 << (op
->extbits
- 1)) - 1;
7425 if (val
< minext
|| val
> maxext
)
7426 as_bad_where (file
, line
,
7427 "operand value out of range for instruction");
7430 if (op
->extbits
== 16)
7432 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7435 else if (op
->extbits
== 15)
7437 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7442 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7446 *extend
= (unsigned short) extval
;
7455 my_getSmallExpression (ep
, str
)
7466 ((str
[1] == 'h' && str
[2] == 'i')
7467 || (str
[1] == 'H' && str
[2] == 'I')
7468 || (str
[1] == 'l' && str
[2] == 'o'))
7480 * A small expression may be followed by a base register.
7481 * Scan to the end of this operand, and then back over a possible
7482 * base register. Then scan the small expression up to that
7483 * point. (Based on code in sparc.c...)
7485 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7487 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7489 if (isdigit (sp
[-2]))
7491 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7493 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7499 else if (sp
- 5 >= str
7502 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7503 || (sp
[-3] == 's' && sp
[-2] == 'p')
7504 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7505 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7511 /* no expression means zero offset */
7514 /* %xx(reg) is an error */
7515 ep
->X_op
= O_absent
;
7520 ep
->X_op
= O_constant
;
7523 ep
->X_add_symbol
= NULL
;
7524 ep
->X_op_symbol
= NULL
;
7525 ep
->X_add_number
= 0;
7530 my_getExpression (ep
, str
);
7537 my_getExpression (ep
, str
);
7538 return c
; /* => %hi or %lo encountered */
7542 my_getExpression (ep
, str
)
7548 save_in
= input_line_pointer
;
7549 input_line_pointer
= str
;
7551 expr_end
= input_line_pointer
;
7552 input_line_pointer
= save_in
;
7555 /* Turn a string in input_line_pointer into a floating point constant
7556 of type type, and store the appropriate bytes in *litP. The number
7557 of LITTLENUMS emitted is stored in *sizeP . An error message is
7558 returned, or NULL on OK. */
7561 md_atof (type
, litP
, sizeP
)
7567 LITTLENUM_TYPE words
[4];
7583 return "bad call to md_atof";
7586 t
= atof_ieee (input_line_pointer
, type
, words
);
7588 input_line_pointer
= t
;
7592 if (! target_big_endian
)
7594 for (i
= prec
- 1; i
>= 0; i
--)
7596 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7602 for (i
= 0; i
< prec
; i
++)
7604 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7613 md_number_to_chars (buf
, val
, n
)
7618 if (target_big_endian
)
7619 number_to_chars_bigendian (buf
, val
, n
);
7621 number_to_chars_littleendian (buf
, val
, n
);
7624 CONST
char *md_shortopts
= "O::g::G:";
7626 struct option md_longopts
[] = {
7627 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7628 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7629 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7630 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7631 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7632 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7633 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7634 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7635 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7636 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7637 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7638 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7639 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7640 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7641 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7642 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7643 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7644 {"break", no_argument
, NULL
, OPTION_BREAK
},
7645 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7646 #define OPTION_EB (OPTION_MD_BASE + 11)
7647 {"EB", no_argument
, NULL
, OPTION_EB
},
7648 #define OPTION_EL (OPTION_MD_BASE + 12)
7649 {"EL", no_argument
, NULL
, OPTION_EL
},
7650 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7651 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7652 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7653 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7654 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7655 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7656 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7657 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7658 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7659 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7660 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7661 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7662 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7663 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7664 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7665 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7667 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7668 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7669 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7670 #define OPTION_32 (OPTION_MD_BASE + 20)
7671 #define OPTION_64 (OPTION_MD_BASE + 21)
7673 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7674 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7675 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7676 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7677 {"32", no_argument
, NULL
, OPTION_32
},
7678 {"64", no_argument
, NULL
, OPTION_64
},
7681 {NULL
, no_argument
, NULL
, 0}
7683 size_t md_longopts_size
= sizeof(md_longopts
);
7686 md_parse_option (c
, arg
)
7701 target_big_endian
= 1;
7705 target_big_endian
= 0;
7709 if (arg
&& arg
[1] == '0')
7719 mips_debug
= atoi (arg
);
7720 /* When the MIPS assembler sees -g or -g2, it does not do
7721 optimizations which limit full symbolic debugging. We take
7722 that to be equivalent to -O0. */
7723 if (mips_debug
== 2)
7755 /* Identify the processor type */
7757 if (strcmp (p
, "default") == 0
7758 || strcmp (p
, "DEFAULT") == 0)
7764 /* We need to cope with the various "vr" prefixes for the 4300
7766 if (*p
== 'v' || *p
== 'V')
7772 if (*p
== 'r' || *p
== 'R')
7779 if (strcmp (p
, "10000") == 0
7780 || strcmp (p
, "10k") == 0
7781 || strcmp (p
, "10K") == 0)
7786 if (strcmp (p
, "2000") == 0
7787 || strcmp (p
, "2k") == 0
7788 || strcmp (p
, "2K") == 0)
7793 if (strcmp (p
, "3000") == 0
7794 || strcmp (p
, "3k") == 0
7795 || strcmp (p
, "3K") == 0)
7800 if (strcmp (p
, "4000") == 0
7801 || strcmp (p
, "4k") == 0
7802 || strcmp (p
, "4K") == 0)
7804 else if (strcmp (p
, "4100") == 0)
7810 else if (strcmp (p
, "4300") == 0)
7812 else if (strcmp (p
, "4400") == 0)
7814 else if (strcmp (p
, "4600") == 0)
7816 else if (strcmp (p
, "4650") == 0)
7822 else if (strcmp (p
, "4010") == 0)
7831 if (strcmp (p
, "5000") == 0
7832 || strcmp (p
, "5k") == 0
7833 || strcmp (p
, "5K") == 0)
7838 if (strcmp (p
, "6000") == 0
7839 || strcmp (p
, "6k") == 0
7840 || strcmp (p
, "6K") == 0)
7845 if (strcmp (p
, "8000") == 0
7846 || strcmp (p
, "8k") == 0
7847 || strcmp (p
, "8K") == 0)
7852 if (strcmp (p
, "orion") == 0)
7857 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7859 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7865 as_bad ("invalid architecture -mcpu=%s", arg
);
7876 case OPTION_NO_M4650
:
7884 case OPTION_NO_M4010
:
7892 case OPTION_NO_M4100
:
7898 mips_no_prev_insn ();
7901 case OPTION_NO_MIPS16
:
7903 mips_no_prev_insn ();
7906 case OPTION_MEMBEDDED_PIC
:
7907 mips_pic
= EMBEDDED_PIC
;
7908 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7910 as_bad ("-G may not be used with embedded PIC code");
7913 g_switch_value
= 0x7fffffff;
7916 /* When generating ELF code, we permit -KPIC and -call_shared to
7917 select SVR4_PIC, and -non_shared to select no PIC. This is
7918 intended to be compatible with Irix 5. */
7919 case OPTION_CALL_SHARED
:
7920 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7922 as_bad ("-call_shared is supported only for ELF format");
7925 mips_pic
= SVR4_PIC
;
7926 if (g_switch_seen
&& g_switch_value
!= 0)
7928 as_bad ("-G may not be used with SVR4 PIC code");
7934 case OPTION_NON_SHARED
:
7935 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7937 as_bad ("-non_shared is supported only for ELF format");
7943 /* The -xgot option tells the assembler to use 32 offsets when
7944 accessing the got in SVR4_PIC mode. It is for Irix
7951 if (! USE_GLOBAL_POINTER_OPT
)
7953 as_bad ("-G is not supported for this configuration");
7956 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7958 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7962 g_switch_value
= atoi (arg
);
7966 /* The -32 and -64 options tell the assembler to output the 32
7967 bit or the 64 bit MIPS ELF format. */
7974 const char **list
, **l
;
7976 list
= bfd_target_list ();
7977 for (l
= list
; *l
!= NULL
; l
++)
7978 if (strcmp (*l
, "elf64-bigmips") == 0
7979 || strcmp (*l
, "elf64-littlemips") == 0)
7982 as_fatal ("No compiled in support for 64 bit object file format");
7996 md_show_usage (stream
)
8001 -membedded-pic generate embedded position independent code\n\
8002 -EB generate big endian output\n\
8003 -EL generate little endian output\n\
8004 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8005 -G NUM allow referencing objects up to NUM bytes\n\
8006 implicitly with the gp register [default 8]\n");
8008 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8009 -mips2, -mcpu=r6000 generate code for r6000\n\
8010 -mips3, -mcpu=r4000 generate code for r4000\n\
8011 -mips4, -mcpu=r8000 generate code for r8000\n\
8012 -mcpu=vr4300 generate code for vr4300\n\
8013 -mcpu=vr4100 generate code for vr4100\n\
8014 -m4650 permit R4650 instructions\n\
8015 -no-m4650 do not permit R4650 instructions\n\
8016 -m4010 permit R4010 instructions\n\
8017 -no-m4010 do not permit R4010 instructions\n\
8018 -m4100 permit VR4100 instructions\n\
8019 -no-m4100 do not permit VR4100 instructions\n");
8021 -mips16 generate mips16 instructions\n\
8022 -no-mips16 do not generate mips16 instructions\n");
8024 -O0 remove unneeded NOPs, do not swap branches\n\
8025 -O remove unneeded NOPs and swap branches\n\
8026 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8027 --break, --no-trap break exception on div by 0 and mult overflow\n");
8030 -KPIC, -call_shared generate SVR4 position independent code\n\
8031 -non_shared do not generate position independent code\n\
8032 -xgot assume a 32 bit GOT\n\
8033 -32 create 32 bit object file (default)\n\
8034 -64 create 64 bit object file\n");
8039 md_pcrel_from (fixP
)
8042 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8043 && fixP
->fx_addsy
!= (symbolS
*) NULL
8044 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8046 /* This makes a branch to an undefined symbol be a branch to the
8047 current location. */
8051 /* return the address of the delay slot */
8052 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8055 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8056 reloc for a cons. We could use the definition there, except that
8057 we want to handle 64 bit relocs specially. */
8060 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8063 unsigned int nbytes
;
8067 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8069 if (nbytes
== 8 && ! mips_64
)
8071 if (target_big_endian
)
8077 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8078 as_bad ("Unsupported reloc size %d", nbytes
);
8080 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8083 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8086 /* Sort any unmatched HI16_S relocs so that they immediately precede
8087 the corresponding LO reloc. This is called before md_apply_fix and
8088 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8089 explicit use of the %hi modifier. */
8094 struct mips_hi_fixup
*l
;
8096 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8098 segment_info_type
*seginfo
;
8101 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8103 /* Check quickly whether the next fixup happens to be a matching
8105 if (l
->fixp
->fx_next
!= NULL
8106 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8107 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8108 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8111 /* Look through the fixups for this segment for a matching %lo.
8112 When we find one, move the %hi just in front of it. We do
8113 this in two passes. In the first pass, we try to find a
8114 unique %lo. In the second pass, we permit multiple %hi
8115 relocs for a single %lo (this is a GNU extension). */
8116 seginfo
= seg_info (l
->seg
);
8117 for (pass
= 0; pass
< 2; pass
++)
8122 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8124 /* Check whether this is a %lo fixup which matches l->fixp. */
8125 if (f
->fx_r_type
== BFD_RELOC_LO16
8126 && f
->fx_addsy
== l
->fixp
->fx_addsy
8127 && f
->fx_offset
== l
->fixp
->fx_offset
8130 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8131 || prev
->fx_addsy
!= f
->fx_addsy
8132 || prev
->fx_offset
!= f
->fx_offset
))
8136 /* Move l->fixp before f. */
8137 for (pf
= &seginfo
->fix_root
;
8139 pf
= &(*pf
)->fx_next
)
8140 assert (*pf
!= NULL
);
8142 *pf
= l
->fixp
->fx_next
;
8144 l
->fixp
->fx_next
= f
;
8146 seginfo
->fix_root
= l
->fixp
;
8148 prev
->fx_next
= l
->fixp
;
8160 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8161 "Unmatched %%hi reloc");
8166 /* When generating embedded PIC code we need to use a special
8167 relocation to represent the difference of two symbols in the .text
8168 section (switch tables use a difference of this sort). See
8169 include/coff/mips.h for details. This macro checks whether this
8170 fixup requires the special reloc. */
8171 #define SWITCH_TABLE(fixp) \
8172 ((fixp)->fx_r_type == BFD_RELOC_32 \
8173 && (fixp)->fx_addsy != NULL \
8174 && (fixp)->fx_subsy != NULL \
8175 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8176 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8178 /* When generating embedded PIC code we must keep all PC relative
8179 relocations, in case the linker has to relax a call. We also need
8180 to keep relocations for switch table entries. */
8184 mips_force_relocation (fixp
)
8187 return (mips_pic
== EMBEDDED_PIC
8189 || SWITCH_TABLE (fixp
)
8190 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8191 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8194 /* Apply a fixup to the object file. */
8197 md_apply_fix (fixP
, valueP
)
8204 assert (fixP
->fx_size
== 4
8205 || fixP
->fx_r_type
== BFD_RELOC_16
8206 || fixP
->fx_r_type
== BFD_RELOC_64
);
8209 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8211 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8214 switch (fixP
->fx_r_type
)
8216 case BFD_RELOC_MIPS_JMP
:
8217 case BFD_RELOC_HI16
:
8218 case BFD_RELOC_HI16_S
:
8219 case BFD_RELOC_MIPS_GPREL
:
8220 case BFD_RELOC_MIPS_LITERAL
:
8221 case BFD_RELOC_MIPS_CALL16
:
8222 case BFD_RELOC_MIPS_GOT16
:
8223 case BFD_RELOC_MIPS_GPREL32
:
8224 case BFD_RELOC_MIPS_GOT_HI16
:
8225 case BFD_RELOC_MIPS_GOT_LO16
:
8226 case BFD_RELOC_MIPS_CALL_HI16
:
8227 case BFD_RELOC_MIPS_CALL_LO16
:
8229 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8230 "Invalid PC relative reloc");
8231 /* Nothing needed to do. The value comes from the reloc entry */
8234 case BFD_RELOC_MIPS16_JMP
:
8235 /* We currently always generate a reloc against a symbol, which
8236 means that we don't want an addend even if the symbol is
8238 fixP
->fx_addnumber
= 0;
8241 case BFD_RELOC_PCREL_HI16_S
:
8242 /* The addend for this is tricky if it is internal, so we just
8243 do everything here rather than in bfd_perform_relocation. */
8244 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8246 /* For an external symbol adjust by the address to make it
8247 pcrel_offset. We use the address of the RELLO reloc
8248 which follows this one. */
8249 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8250 + fixP
->fx_next
->fx_where
);
8255 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8256 if (target_big_endian
)
8258 md_number_to_chars (buf
, value
, 2);
8261 case BFD_RELOC_PCREL_LO16
:
8262 /* The addend for this is tricky if it is internal, so we just
8263 do everything here rather than in bfd_perform_relocation. */
8264 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8265 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8266 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8267 if (target_big_endian
)
8269 md_number_to_chars (buf
, value
, 2);
8273 /* This is handled like BFD_RELOC_32, but we output a sign
8274 extended value if we are only 32 bits. */
8276 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8278 if (8 <= sizeof (valueT
))
8279 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8286 w1
= w2
= fixP
->fx_where
;
8287 if (target_big_endian
)
8291 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8292 if ((value
& 0x80000000) != 0)
8296 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8302 /* If we are deleting this reloc entry, we must fill in the
8303 value now. This can happen if we have a .word which is not
8304 resolved when it appears but is later defined. We also need
8305 to fill in the value if this is an embedded PIC switch table
8308 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8309 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8314 /* If we are deleting this reloc entry, we must fill in the
8316 assert (fixP
->fx_size
== 2);
8318 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8322 case BFD_RELOC_LO16
:
8323 /* When handling an embedded PIC switch statement, we can wind
8324 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8327 if (value
< -0x8000 || value
> 0x7fff)
8328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8329 "relocation overflow");
8330 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8331 if (target_big_endian
)
8333 md_number_to_chars (buf
, value
, 2);
8337 case BFD_RELOC_16_PCREL_S2
:
8339 * We need to save the bits in the instruction since fixup_segment()
8340 * might be deleting the relocation entry (i.e., a branch within
8341 * the current segment).
8343 if ((value
& 0x3) != 0)
8344 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8345 "Branch to odd address (%lx)", value
);
8348 /* update old instruction data */
8349 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8350 if (target_big_endian
)
8351 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8353 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8355 if (value
>= -0x8000 && value
< 0x8000)
8356 insn
|= value
& 0xffff;
8359 /* The branch offset is too large. If this is an
8360 unconditional branch, and we are not generating PIC code,
8361 we can convert it to an absolute jump instruction. */
8362 if (mips_pic
== NO_PIC
8364 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8365 && (fixP
->fx_frag
->fr_address
8366 < text_section
->vma
+ text_section
->_raw_size
)
8367 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8368 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8369 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8371 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8372 insn
= 0x0c000000; /* jal */
8374 insn
= 0x08000000; /* j */
8375 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8377 fixP
->fx_addsy
= section_symbol (text_section
);
8378 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8382 /* FIXME. It would be possible in principle to handle
8383 conditional branches which overflow. They could be
8384 transformed into a branch around a jump. This would
8385 require setting up variant frags for each different
8386 branch type. The native MIPS assembler attempts to
8387 handle these cases, but it appears to do it
8389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8390 "Relocation overflow");
8394 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8409 const struct mips_opcode
*p
;
8410 int treg
, sreg
, dreg
, shamt
;
8415 for (i
= 0; i
< NUMOPCODES
; ++i
)
8417 p
= &mips_opcodes
[i
];
8418 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8420 printf ("%08lx %s\t", oc
, p
->name
);
8421 treg
= (oc
>> 16) & 0x1f;
8422 sreg
= (oc
>> 21) & 0x1f;
8423 dreg
= (oc
>> 11) & 0x1f;
8424 shamt
= (oc
>> 6) & 0x1f;
8426 for (args
= p
->args
;; ++args
)
8437 printf ("%c", *args
);
8441 assert (treg
== sreg
);
8442 printf ("$%d,$%d", treg
, sreg
);
8447 printf ("$%d", dreg
);
8452 printf ("$%d", treg
);
8456 printf ("0x%x", treg
);
8461 printf ("$%d", sreg
);
8465 printf ("0x%08lx", oc
& 0x1ffffff);
8477 printf ("$%d", shamt
);
8488 printf ("%08lx UNDEFINED\n", oc
);
8499 name
= input_line_pointer
;
8500 c
= get_symbol_end ();
8501 p
= (symbolS
*) symbol_find_or_make (name
);
8502 *input_line_pointer
= c
;
8506 /* Align the current frag to a given power of two. The MIPS assembler
8507 also automatically adjusts any preceding label. */
8510 mips_align (to
, fill
, label
)
8515 mips_emit_delays (false);
8516 frag_align (to
, fill
);
8517 record_alignment (now_seg
, to
);
8520 assert (S_GET_SEGMENT (label
) == now_seg
);
8521 label
->sy_frag
= frag_now
;
8522 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8526 /* Align to a given power of two. .align 0 turns off the automatic
8527 alignment used by the data creating pseudo-ops. */
8534 register long temp_fill
;
8535 long max_alignment
= 15;
8539 o Note that the assembler pulls down any immediately preceeding label
8540 to the aligned address.
8541 o It's not documented but auto alignment is reinstated by
8542 a .align pseudo instruction.
8543 o Note also that after auto alignment is turned off the mips assembler
8544 issues an error on attempt to assemble an improperly aligned data item.
8549 temp
= get_absolute_expression ();
8550 if (temp
> max_alignment
)
8551 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8554 as_warn ("Alignment negative: 0 assumed.");
8557 if (*input_line_pointer
== ',')
8559 input_line_pointer
++;
8560 temp_fill
= get_absolute_expression ();
8567 mips_align (temp
, (int) temp_fill
,
8568 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8575 demand_empty_rest_of_line ();
8579 mips_flush_pending_output ()
8581 mips_emit_delays (false);
8582 mips_clear_insn_labels ();
8591 /* When generating embedded PIC code, we only use the .text, .lit8,
8592 .sdata and .sbss sections. We change the .data and .rdata
8593 pseudo-ops to use .sdata. */
8594 if (mips_pic
== EMBEDDED_PIC
8595 && (sec
== 'd' || sec
== 'r'))
8598 mips_emit_delays (false);
8608 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8609 demand_empty_rest_of_line ();
8613 if (USE_GLOBAL_POINTER_OPT
)
8615 seg
= subseg_new (RDATA_SECTION_NAME
,
8616 (subsegT
) get_absolute_expression ());
8617 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8619 bfd_set_section_flags (stdoutput
, seg
,
8625 if (strcmp (TARGET_OS
, "elf") != 0)
8626 bfd_set_section_alignment (stdoutput
, seg
, 4);
8628 demand_empty_rest_of_line ();
8632 as_bad ("No read only data section in this object file format");
8633 demand_empty_rest_of_line ();
8639 if (USE_GLOBAL_POINTER_OPT
)
8641 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8642 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8644 bfd_set_section_flags (stdoutput
, seg
,
8645 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8647 if (strcmp (TARGET_OS
, "elf") != 0)
8648 bfd_set_section_alignment (stdoutput
, seg
, 4);
8650 demand_empty_rest_of_line ();
8655 as_bad ("Global pointers not supported; recompile -G 0");
8656 demand_empty_rest_of_line ();
8665 mips_enable_auto_align ()
8676 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8677 mips_emit_delays (false);
8678 if (log_size
> 0 && auto_align
)
8679 mips_align (log_size
, 0, label
);
8680 mips_clear_insn_labels ();
8681 cons (1 << log_size
);
8690 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8692 mips_emit_delays (false);
8696 mips_align (3, 0, label
);
8698 mips_align (2, 0, label
);
8700 mips_clear_insn_labels ();
8705 /* Handle .globl. We need to override it because on Irix 5 you are
8708 where foo is an undefined symbol, to mean that foo should be
8709 considered to be the address of a function. */
8720 name
= input_line_pointer
;
8721 c
= get_symbol_end ();
8722 symbolP
= symbol_find_or_make (name
);
8723 *input_line_pointer
= c
;
8726 /* On Irix 5, every global symbol that is not explicitly labelled as
8727 being a function is apparently labelled as being an object. */
8730 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8735 secname
= input_line_pointer
;
8736 c
= get_symbol_end ();
8737 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8739 as_bad ("%s: no such section", secname
);
8740 *input_line_pointer
= c
;
8742 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8743 flag
= BSF_FUNCTION
;
8746 symbolP
->bsym
->flags
|= flag
;
8748 S_SET_EXTERNAL (symbolP
);
8749 demand_empty_rest_of_line ();
8759 opt
= input_line_pointer
;
8760 c
= get_symbol_end ();
8764 /* FIXME: What does this mean? */
8766 else if (strncmp (opt
, "pic", 3) == 0)
8774 mips_pic
= SVR4_PIC
;
8776 as_bad (".option pic%d not supported", i
);
8778 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8780 if (g_switch_seen
&& g_switch_value
!= 0)
8781 as_warn ("-G may not be used with SVR4 PIC code");
8783 bfd_set_gp_size (stdoutput
, 0);
8787 as_warn ("Unrecognized option \"%s\"", opt
);
8789 *input_line_pointer
= c
;
8790 demand_empty_rest_of_line ();
8797 char *name
= input_line_pointer
, ch
;
8799 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8800 input_line_pointer
++;
8801 ch
= *input_line_pointer
;
8802 *input_line_pointer
= '\0';
8804 if (strcmp (name
, "reorder") == 0)
8808 prev_insn_unreordered
= 1;
8809 prev_prev_insn_unreordered
= 1;
8813 else if (strcmp (name
, "noreorder") == 0)
8815 mips_emit_delays (true);
8817 mips_any_noreorder
= 1;
8819 else if (strcmp (name
, "at") == 0)
8823 else if (strcmp (name
, "noat") == 0)
8827 else if (strcmp (name
, "macro") == 0)
8829 mips_warn_about_macros
= 0;
8831 else if (strcmp (name
, "nomacro") == 0)
8833 if (mips_noreorder
== 0)
8834 as_bad ("`noreorder' must be set before `nomacro'");
8835 mips_warn_about_macros
= 1;
8837 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8841 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8845 else if (strcmp (name
, "bopt") == 0)
8849 else if (strcmp (name
, "nobopt") == 0)
8853 else if (strcmp (name
, "mips16") == 0
8854 || strcmp (name
, "MIPS-16") == 0)
8856 else if (strcmp (name
, "nomips16") == 0
8857 || strcmp (name
, "noMIPS-16") == 0)
8859 else if (strncmp (name
, "mips", 4) == 0)
8863 /* Permit the user to change the ISA on the fly. Needless to
8864 say, misuse can cause serious problems. */
8865 isa
= atoi (name
+ 4);
8867 mips_isa
= file_mips_isa
;
8868 else if (isa
< 1 || isa
> 4)
8869 as_bad ("unknown ISA level");
8873 else if (strcmp (name
, "autoextend") == 0)
8874 mips16_autoextend
= 1;
8875 else if (strcmp (name
, "noautoextend") == 0)
8876 mips16_autoextend
= 0;
8879 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8881 *input_line_pointer
= ch
;
8882 demand_empty_rest_of_line ();
8885 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8886 .option pic2. It means to generate SVR4 PIC calls. */
8892 mips_pic
= SVR4_PIC
;
8893 if (USE_GLOBAL_POINTER_OPT
)
8895 if (g_switch_seen
&& g_switch_value
!= 0)
8896 as_warn ("-G may not be used with SVR4 PIC code");
8899 bfd_set_gp_size (stdoutput
, 0);
8900 demand_empty_rest_of_line ();
8903 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8904 PIC code. It sets the $gp register for the function based on the
8905 function address, which is in the register named in the argument.
8906 This uses a relocation against _gp_disp, which is handled specially
8907 by the linker. The result is:
8908 lui $gp,%hi(_gp_disp)
8909 addiu $gp,$gp,%lo(_gp_disp)
8910 addu $gp,$gp,.cpload argument
8911 The .cpload argument is normally $25 == $t9. */
8920 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8921 if (mips_pic
!= SVR4_PIC
)
8927 /* .cpload should be a in .set noreorder section. */
8928 if (mips_noreorder
== 0)
8929 as_warn (".cpload not in noreorder section");
8932 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8933 ex
.X_op_symbol
= NULL
;
8934 ex
.X_add_number
= 0;
8936 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8937 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8939 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8940 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8941 (int) BFD_RELOC_LO16
);
8943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8944 GP
, GP
, tc_get_register (0));
8946 demand_empty_rest_of_line ();
8949 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8950 offset from $sp. The offset is remembered, and after making a PIC
8951 call $gp is restored from that location. */
8954 s_cprestore (ignore
)
8960 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8961 if (mips_pic
!= SVR4_PIC
)
8967 mips_cprestore_offset
= get_absolute_expression ();
8969 ex
.X_op
= O_constant
;
8970 ex
.X_add_symbol
= NULL
;
8971 ex
.X_op_symbol
= NULL
;
8972 ex
.X_add_number
= mips_cprestore_offset
;
8974 macro_build ((char *) NULL
, &icnt
, &ex
,
8975 mips_isa
< 3 ? "sw" : "sd",
8976 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8978 demand_empty_rest_of_line ();
8981 /* Handle the .gpword pseudo-op. This is used when generating PIC
8982 code. It generates a 32 bit GP relative reloc. */
8992 /* When not generating PIC code, this is treated as .word. */
8993 if (mips_pic
!= SVR4_PIC
)
8999 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9000 mips_emit_delays (true);
9002 mips_align (2, 0, label
);
9003 mips_clear_insn_labels ();
9007 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9009 as_bad ("Unsupported use of .gpword");
9010 ignore_rest_of_line ();
9014 md_number_to_chars (p
, (valueT
) 0, 4);
9015 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9016 BFD_RELOC_MIPS_GPREL32
);
9018 demand_empty_rest_of_line ();
9021 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9022 tables in SVR4 PIC code. */
9031 /* This is ignored when not generating SVR4 PIC code. */
9032 if (mips_pic
!= SVR4_PIC
)
9038 /* Add $gp to the register named as an argument. */
9039 reg
= tc_get_register (0);
9040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9041 mips_isa
< 3 ? "addu" : "daddu",
9042 "d,v,t", reg
, reg
, GP
);
9044 demand_empty_rest_of_line ();
9047 /* Parse a register string into a number. Called from the ECOFF code
9048 to parse .frame. The argument is non-zero if this is the frame
9049 register, so that we can record it in mips_frame_reg. */
9052 tc_get_register (frame
)
9058 if (*input_line_pointer
++ != '$')
9060 as_warn ("expected `$'");
9063 else if (isdigit ((unsigned char) *input_line_pointer
))
9065 reg
= get_absolute_expression ();
9066 if (reg
< 0 || reg
>= 32)
9068 as_warn ("Bad register number");
9074 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9076 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9078 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9080 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9084 as_warn ("Unrecognized register name");
9087 input_line_pointer
+= 2;
9090 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9095 md_section_align (seg
, addr
)
9099 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9102 /* We don't need to align ELF sections to the full alignment.
9103 However, Irix 5 may prefer that we align them at least to a 16
9104 byte boundary. We don't bother to align the sections if we are
9105 targeted for an embedded system. */
9106 if (strcmp (TARGET_OS
, "elf") == 0)
9112 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9115 /* Utility routine, called from above as well. If called while the
9116 input file is still being read, it's only an approximation. (For
9117 example, a symbol may later become defined which appeared to be
9118 undefined earlier.) */
9121 nopic_need_relax (sym
)
9127 if (USE_GLOBAL_POINTER_OPT
)
9129 const char *symname
;
9132 /* Find out whether this symbol can be referenced off the GP
9133 register. It can be if it is smaller than the -G size or if
9134 it is in the .sdata or .sbss section. Certain symbols can
9135 not be referenced off the GP, although it appears as though
9137 symname
= S_GET_NAME (sym
);
9138 if (symname
!= (const char *) NULL
9139 && (strcmp (symname
, "eprol") == 0
9140 || strcmp (symname
, "etext") == 0
9141 || strcmp (symname
, "_gp") == 0
9142 || strcmp (symname
, "edata") == 0
9143 || strcmp (symname
, "_fbss") == 0
9144 || strcmp (symname
, "_fdata") == 0
9145 || strcmp (symname
, "_ftext") == 0
9146 || strcmp (symname
, "end") == 0
9147 || strcmp (symname
, "_gp_disp") == 0))
9149 else if (! S_IS_DEFINED (sym
)
9151 #ifndef NO_ECOFF_DEBUGGING
9152 || (sym
->ecoff_extern_size
!= 0
9153 && sym
->ecoff_extern_size
<= g_switch_value
)
9155 || (S_GET_VALUE (sym
) != 0
9156 && S_GET_VALUE (sym
) <= g_switch_value
)))
9160 const char *segname
;
9162 segname
= segment_name (S_GET_SEGMENT (sym
));
9163 assert (strcmp (segname
, ".lit8") != 0
9164 && strcmp (segname
, ".lit4") != 0);
9165 change
= (strcmp (segname
, ".sdata") != 0
9166 && strcmp (segname
, ".sbss") != 0);
9171 /* We are not optimizing for the GP register. */
9175 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9176 extended opcode. SEC is the section the frag is in. */
9179 mips16_extended_frag (fragp
, sec
, stretch
)
9185 register const struct mips16_immed_operand
*op
;
9187 int mintiny
, maxtiny
;
9190 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9192 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9195 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9196 op
= mips16_immed_operands
;
9197 while (op
->type
!= type
)
9200 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9205 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9208 maxtiny
= 1 << op
->nbits
;
9213 maxtiny
= (1 << op
->nbits
) - 1;
9218 mintiny
= - (1 << (op
->nbits
- 1));
9219 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9222 /* We can't call S_GET_VALUE here, because we don't want to lock in
9223 a particular frag address. */
9224 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9226 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9227 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9228 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9230 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9231 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9234 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9235 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9236 + fragp
->fr_symbol
->sy_value
.X_add_number
9237 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9238 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9247 /* We won't have the section when we are called from
9248 mips_relax_frag. However, we will always have been called
9249 from md_estimate_size_before_relax first. If this is a
9250 branch to a different section, we mark it as such. If SEC is
9251 NULL, and the frag is not marked, then it must be a branch to
9252 the same section. */
9255 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9263 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9265 /* FIXME: We should support this, and let the linker
9266 catch branches and loads that are out of range. */
9267 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9268 "unsupported PC relative reference to different section");
9274 /* In this case, we know for sure that the symbol fragment is in
9275 the same section. If the fr_address of the symbol fragment
9276 is greater then the address of this fragment we want to add
9277 in STRETCH in order to get a better estimate of the address.
9278 This particularly matters because of the shift bits. */
9280 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9284 /* Adjust stretch for any alignment frag. */
9285 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9288 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9291 stretch
= - ((- stretch
)
9292 & ~ ((1 << (int) f
->fr_offset
) - 1));
9294 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9302 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9304 /* The base address rules are complicated. The base address of
9305 a branch is the following instruction. The base address of a
9306 PC relative load or add is the instruction itself, but if it
9307 is extended add 2, and if it is in a delay slot (in which
9308 case it can not be extended) use the address of the
9309 instruction whose delay slot it is in. */
9310 if (type
== 'p' || type
== 'q')
9313 /* Ignore the low bit in the target, since it will be set
9314 for a text label. */
9318 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9320 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9323 /* If we are currently assuming that this frag should be
9324 extended, then the current address is two bytes higher. */
9325 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9328 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9330 /* Branch offsets have an implicit 0 in the lowest bit. */
9331 if (type
== 'p' || type
== 'q')
9334 /* If any of the shifted bits are set, we must use an extended
9335 opcode. If the address depends on the size of this
9336 instruction, this can lead to a loop, so we arrange to always
9337 use an extended opcode. We only check this when we are in
9338 the main relaxation loop, when SEC is NULL. */
9339 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9342 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9346 /* If we are about to mark a frag as extended because the value
9347 is precisely maxtiny + 1, then there is a chance of an
9348 infinite loop as in the following code:
9353 In this case when the la is extended, foo is 0x3fc bytes
9354 away, so the la can be shrunk, but then foo is 0x400 away, so
9355 the la must be extended. To avoid this loop, we mark the
9356 frag as extended if it was small, and is about to become
9357 extended with a value of maxtiny + 1. */
9358 if (val
== ((maxtiny
+ 1) << op
->shift
)
9359 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9363 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9367 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9368 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9370 if ((val
& ((1 << op
->shift
) - 1)) != 0
9371 || val
< (mintiny
<< op
->shift
)
9372 || val
> (maxtiny
<< op
->shift
))
9378 /* Estimate the size of a frag before relaxing. Unless this is the
9379 mips16, we are not really relaxing here, and the final size is
9380 encoded in the subtype information. For the mips16, we have to
9381 decide whether we are using an extended opcode or not. */
9385 md_estimate_size_before_relax (fragp
, segtype
)
9391 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9393 if (mips16_extended_frag (fragp
, segtype
, 0))
9395 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9400 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9405 if (mips_pic
== NO_PIC
)
9407 change
= nopic_need_relax (fragp
->fr_symbol
);
9409 else if (mips_pic
== SVR4_PIC
)
9411 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9413 /* This must duplicate the test in adjust_reloc_syms. */
9414 change
= (symsec
!= &bfd_und_section
9415 && symsec
!= &bfd_abs_section
9416 && ! bfd_is_com_section (symsec
));
9423 /* Record the offset to the first reloc in the fr_opcode field.
9424 This lets md_convert_frag and tc_gen_reloc know that the code
9425 must be expanded. */
9426 fragp
->fr_opcode
= (fragp
->fr_literal
9428 - RELAX_OLD (fragp
->fr_subtype
)
9429 + RELAX_RELOC1 (fragp
->fr_subtype
));
9430 /* FIXME: This really needs as_warn_where. */
9431 if (RELAX_WARN (fragp
->fr_subtype
))
9432 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9438 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9441 /* Translate internal representation of relocation info to BFD target
9445 tc_gen_reloc (section
, fixp
)
9449 static arelent
*retval
[4];
9451 bfd_reloc_code_real_type code
;
9453 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9456 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9457 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9459 if (mips_pic
== EMBEDDED_PIC
9460 && SWITCH_TABLE (fixp
))
9462 /* For a switch table entry we use a special reloc. The addend
9463 is actually the difference between the reloc address and the
9465 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9466 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9467 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9468 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9470 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9472 /* We use a special addend for an internal RELLO reloc. */
9473 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9474 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9476 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9478 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9480 assert (fixp
->fx_next
!= NULL
9481 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9482 /* We use a special addend for an internal RELHI reloc. The
9483 reloc is relative to the RELLO; adjust the addend
9485 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9486 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9487 + fixp
->fx_next
->fx_where
9488 - S_GET_VALUE (fixp
->fx_subsy
));
9490 reloc
->addend
= (fixp
->fx_addnumber
9491 + fixp
->fx_next
->fx_frag
->fr_address
9492 + fixp
->fx_next
->fx_where
);
9494 else if (fixp
->fx_pcrel
== 0)
9495 reloc
->addend
= fixp
->fx_addnumber
;
9498 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9499 /* A gruesome hack which is a result of the gruesome gas reloc
9501 reloc
->addend
= reloc
->address
;
9503 reloc
->addend
= -reloc
->address
;
9506 /* If this is a variant frag, we may need to adjust the existing
9507 reloc and generate a new one. */
9508 if (fixp
->fx_frag
->fr_opcode
!= NULL
9509 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9510 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9511 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9512 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9513 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9514 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9515 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9519 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9521 /* If this is not the last reloc in this frag, then we have two
9522 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9523 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9524 the second one handle all of them. */
9525 if (fixp
->fx_next
!= NULL
9526 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9528 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9529 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9530 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9531 && (fixp
->fx_next
->fx_r_type
9532 == BFD_RELOC_MIPS_GOT_LO16
))
9533 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9534 && (fixp
->fx_next
->fx_r_type
9535 == BFD_RELOC_MIPS_CALL_LO16
)));
9540 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9541 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9542 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9544 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9545 reloc2
->address
= (reloc
->address
9546 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9547 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9548 reloc2
->addend
= fixp
->fx_addnumber
;
9549 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9550 assert (reloc2
->howto
!= NULL
);
9552 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9556 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9559 reloc3
->address
+= 4;
9562 if (mips_pic
== NO_PIC
)
9564 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9565 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9567 else if (mips_pic
== SVR4_PIC
)
9569 switch (fixp
->fx_r_type
)
9573 case BFD_RELOC_MIPS_GOT16
:
9575 case BFD_RELOC_MIPS_CALL16
:
9576 case BFD_RELOC_MIPS_GOT_LO16
:
9577 case BFD_RELOC_MIPS_CALL_LO16
:
9578 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9586 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9587 fixup_segment converted a non-PC relative reloc into a PC
9588 relative reloc. In such a case, we need to convert the reloc
9590 code
= fixp
->fx_r_type
;
9596 code
= BFD_RELOC_8_PCREL
;
9599 code
= BFD_RELOC_16_PCREL
;
9602 code
= BFD_RELOC_32_PCREL
;
9605 code
= BFD_RELOC_64_PCREL
;
9607 case BFD_RELOC_8_PCREL
:
9608 case BFD_RELOC_16_PCREL
:
9609 case BFD_RELOC_32_PCREL
:
9610 case BFD_RELOC_64_PCREL
:
9611 case BFD_RELOC_16_PCREL_S2
:
9612 case BFD_RELOC_PCREL_HI16_S
:
9613 case BFD_RELOC_PCREL_LO16
:
9616 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9617 "Cannot make %s relocation PC relative",
9618 bfd_get_reloc_code_name (code
));
9622 /* To support a PC relative reloc when generating embedded PIC code
9623 for ECOFF, we use a Cygnus extension. We check for that here to
9624 make sure that we don't let such a reloc escape normally. */
9625 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9626 && code
== BFD_RELOC_16_PCREL_S2
9627 && mips_pic
!= EMBEDDED_PIC
)
9628 reloc
->howto
= NULL
;
9630 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9632 if (reloc
->howto
== NULL
)
9634 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9635 "Can not represent %s relocation in this object file format",
9636 bfd_get_reloc_code_name (code
));
9643 /* Relax a machine dependent frag. This returns the amount by which
9644 the current size of the frag should change. */
9647 mips_relax_frag (fragp
, stretch
)
9651 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9654 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9656 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9658 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9663 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9665 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9672 /* Convert a machine dependent frag. */
9675 md_convert_frag (abfd
, asec
, fragp
)
9683 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9686 register const struct mips16_immed_operand
*op
;
9692 unsigned short extend
;
9694 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9695 op
= mips16_immed_operands
;
9696 while (op
->type
!= type
)
9699 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9710 resolve_symbol_value (fragp
->fr_symbol
);
9711 val
= S_GET_VALUE (fragp
->fr_symbol
);
9716 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9718 /* The rules for the base address of a PC relative reloc are
9719 complicated; see mips16_extended_frag. */
9720 if (type
== 'p' || type
== 'q')
9723 /* Ignore the low bit in the target, since it will be
9724 set for a text label. */
9728 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9730 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9735 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9738 /* Make sure the section winds up with the alignment we have
9741 record_alignment (asec
, op
->shift
);
9744 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9746 if (target_big_endian
)
9747 insn
= bfd_getb16 (buf
);
9749 insn
= bfd_getl16 (buf
);
9751 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
, false, small
,
9752 ext
, &insn
, &use_extend
, &extend
);
9756 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9761 md_number_to_chars (buf
, insn
, 2);
9767 if (fragp
->fr_opcode
== NULL
)
9770 old
= RELAX_OLD (fragp
->fr_subtype
);
9771 new = RELAX_NEW (fragp
->fr_subtype
);
9772 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9775 memcpy (fixptr
- old
, fixptr
, new);
9777 fragp
->fr_fix
+= new - old
;
9783 /* This function is called after the relocs have been generated.
9784 We've been storing mips16 text labels as odd. Here we convert them
9785 back to even for the convenience of the debugger. */
9788 mips_frob_file_after_relocs ()
9791 unsigned int count
, i
;
9793 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9796 syms
= bfd_get_outsymbols (stdoutput
);
9797 count
= bfd_get_symcount (stdoutput
);
9798 for (i
= 0; i
< count
; i
++, syms
++)
9800 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9801 && ((*syms
)->value
& 1) != 0)
9803 (*syms
)->value
&= ~1;
9804 /* If the symbol has an odd size, it was probably computed
9805 incorrectly, so adjust that as well. */
9806 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
9807 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
9814 /* This function is called whenever a label is defined. It is used
9815 when handling branch delays; if a branch has a label, we assume we
9819 mips_define_label (sym
)
9822 struct insn_label_list
*l
;
9824 if (free_insn_labels
== NULL
)
9825 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
9828 l
= free_insn_labels
;
9829 free_insn_labels
= l
->next
;
9833 l
->next
= insn_labels
;
9837 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9838 In order to work with gcc when using mips-tfile, we must keep all
9839 local labels. However, in other cases, we want to discard them,
9840 since they are useless. */
9843 mips_local_label (name
)
9846 #ifndef NO_ECOFF_DEBUGGING
9849 && ! ecoff_debugging_seen
)
9851 /* We were called with -g, but we didn't see any debugging
9852 information. That may mean that gcc is smuggling debugging
9853 information through to mips-tfile, in which case we must
9854 generate all local labels. */
9859 /* Here it's OK to discard local labels. */
9861 return name
[0] == '$';
9864 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9866 /* Some special processing for a MIPS ELF file. */
9869 mips_elf_final_processing ()
9871 /* Write out the register information. */
9876 s
.ri_gprmask
= mips_gprmask
;
9877 s
.ri_cprmask
[0] = mips_cprmask
[0];
9878 s
.ri_cprmask
[1] = mips_cprmask
[1];
9879 s
.ri_cprmask
[2] = mips_cprmask
[2];
9880 s
.ri_cprmask
[3] = mips_cprmask
[3];
9881 /* The gp_value field is set by the MIPS ELF backend. */
9883 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9884 ((Elf32_External_RegInfo
*)
9885 mips_regmask_frag
));
9889 Elf64_Internal_RegInfo s
;
9891 s
.ri_gprmask
= mips_gprmask
;
9893 s
.ri_cprmask
[0] = mips_cprmask
[0];
9894 s
.ri_cprmask
[1] = mips_cprmask
[1];
9895 s
.ri_cprmask
[2] = mips_cprmask
[2];
9896 s
.ri_cprmask
[3] = mips_cprmask
[3];
9897 /* The gp_value field is set by the MIPS ELF backend. */
9899 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9900 ((Elf64_External_RegInfo
*)
9901 mips_regmask_frag
));
9904 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9905 sort of BFD interface for this. */
9906 if (mips_any_noreorder
)
9907 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9908 if (mips_pic
!= NO_PIC
)
9909 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9912 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9914 /* These functions should really be defined by the object file format,
9915 since they are related to debugging information. However, this
9916 code has to work for the a.out format, which does not define them,
9917 so we provide simple versions here. These don't actually generate
9918 any debugging information, but they do simple checking and someday
9919 somebody may make them useful. */
9923 struct loc
*loc_next
;
9924 unsigned long loc_fileno
;
9925 unsigned long loc_lineno
;
9926 unsigned long loc_offset
;
9927 unsigned short loc_delta
;
9928 unsigned short loc_count
;
9937 struct proc
*proc_next
;
9938 struct symbol
*proc_isym
;
9939 struct symbol
*proc_end
;
9940 unsigned long proc_reg_mask
;
9941 unsigned long proc_reg_offset
;
9942 unsigned long proc_fpreg_mask
;
9943 unsigned long proc_fpreg_offset
;
9944 unsigned long proc_frameoffset
;
9945 unsigned long proc_framereg
;
9946 unsigned long proc_pcreg
;
9948 struct file
*proc_file
;
9955 struct file
*file_next
;
9956 unsigned long file_fileno
;
9957 struct symbol
*file_symbol
;
9958 struct symbol
*file_end
;
9959 struct proc
*file_proc
;
9964 static struct obstack proc_frags
;
9965 static procS
*proc_lastP
;
9966 static procS
*proc_rootP
;
9967 static int numprocs
;
9972 obstack_begin (&proc_frags
, 0x2000);
9978 /* check for premature end, nesting errors, etc */
9979 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9980 as_warn ("missing `.end' at end of assembly");
9989 if (*input_line_pointer
== '-')
9991 ++input_line_pointer
;
9994 if (!isdigit (*input_line_pointer
))
9995 as_bad ("Expected simple number.");
9996 if (input_line_pointer
[0] == '0')
9998 if (input_line_pointer
[1] == 'x')
10000 input_line_pointer
+= 2;
10001 while (isxdigit (*input_line_pointer
))
10004 val
|= hex_value (*input_line_pointer
++);
10006 return negative
? -val
: val
;
10010 ++input_line_pointer
;
10011 while (isdigit (*input_line_pointer
))
10014 val
|= *input_line_pointer
++ - '0';
10016 return negative
? -val
: val
;
10019 if (!isdigit (*input_line_pointer
))
10021 printf (" *input_line_pointer == '%c' 0x%02x\n",
10022 *input_line_pointer
, *input_line_pointer
);
10023 as_warn ("Invalid number");
10026 while (isdigit (*input_line_pointer
))
10029 val
+= *input_line_pointer
++ - '0';
10031 return negative
? -val
: val
;
10034 /* The .file directive; just like the usual .file directive, but there
10035 is an initial number which is the ECOFF file index. */
10043 line
= get_number ();
10048 /* The .end directive. */
10056 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10059 demand_empty_rest_of_line ();
10063 if (now_seg
!= text_section
)
10064 as_warn (".end not in text section");
10067 as_warn (".end and no .ent seen yet.");
10073 assert (S_GET_NAME (p
));
10074 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10075 as_warn (".end symbol does not match .ent symbol.");
10078 proc_lastP
->proc_end
= (symbolS
*) 1;
10081 /* The .aent and .ent directives. */
10091 symbolP
= get_symbol ();
10092 if (*input_line_pointer
== ',')
10093 input_line_pointer
++;
10094 SKIP_WHITESPACE ();
10095 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10096 number
= get_number ();
10097 if (now_seg
!= text_section
)
10098 as_warn (".ent or .aent not in text section.");
10100 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10101 as_warn ("missing `.end'");
10105 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10106 procP
->proc_isym
= symbolP
;
10107 procP
->proc_reg_mask
= 0;
10108 procP
->proc_reg_offset
= 0;
10109 procP
->proc_fpreg_mask
= 0;
10110 procP
->proc_fpreg_offset
= 0;
10111 procP
->proc_frameoffset
= 0;
10112 procP
->proc_framereg
= 0;
10113 procP
->proc_pcreg
= 0;
10114 procP
->proc_end
= NULL
;
10115 procP
->proc_next
= NULL
;
10117 proc_lastP
->proc_next
= procP
;
10119 proc_rootP
= procP
;
10120 proc_lastP
= procP
;
10123 demand_empty_rest_of_line ();
10126 /* The .frame directive. */
10139 frame_reg
= tc_get_register (1);
10140 if (*input_line_pointer
== ',')
10141 input_line_pointer
++;
10142 frame_off
= get_absolute_expression ();
10143 if (*input_line_pointer
== ',')
10144 input_line_pointer
++;
10145 pcreg
= tc_get_register (0);
10147 /* bob third eye */
10148 assert (proc_rootP
);
10149 proc_rootP
->proc_framereg
= frame_reg
;
10150 proc_rootP
->proc_frameoffset
= frame_off
;
10151 proc_rootP
->proc_pcreg
= pcreg
;
10152 /* bob macho .frame */
10154 /* We don't have to write out a frame stab for unoptimized code. */
10155 if (!(frame_reg
== FP
&& frame_off
== 0))
10158 as_warn ("No .ent for .frame to use.");
10159 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10160 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10161 S_SET_TYPE (symP
, N_RMASK
);
10162 S_SET_OTHER (symP
, 0);
10163 S_SET_DESC (symP
, 0);
10164 symP
->sy_forward
= proc_lastP
->proc_isym
;
10165 /* bob perhaps I should have used pseudo set */
10167 demand_empty_rest_of_line ();
10171 /* The .fmask and .mask directives. */
10178 char str
[100], *strP
;
10184 mask
= get_number ();
10185 if (*input_line_pointer
== ',')
10186 input_line_pointer
++;
10187 off
= get_absolute_expression ();
10189 /* bob only for coff */
10190 assert (proc_rootP
);
10191 if (reg_type
== 'F')
10193 proc_rootP
->proc_fpreg_mask
= mask
;
10194 proc_rootP
->proc_fpreg_offset
= off
;
10198 proc_rootP
->proc_reg_mask
= mask
;
10199 proc_rootP
->proc_reg_offset
= off
;
10202 /* bob macho .mask + .fmask */
10204 /* We don't have to write out a mask stab if no saved regs. */
10208 as_warn ("No .ent for .mask to use.");
10210 for (i
= 0; i
< 32; i
++)
10214 sprintf (strP
, "%c%d,", reg_type
, i
);
10215 strP
+= strlen (strP
);
10219 sprintf (strP
, ";%d,", off
);
10220 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10221 S_SET_TYPE (symP
, N_RMASK
);
10222 S_SET_OTHER (symP
, 0);
10223 S_SET_DESC (symP
, 0);
10224 symP
->sy_forward
= proc_lastP
->proc_isym
;
10225 /* bob perhaps I should have used pseudo set */
10230 /* The .loc directive. */
10241 assert (now_seg
== text_section
);
10243 lineno
= get_number ();
10244 addroff
= frag_now_fix ();
10246 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10247 S_SET_TYPE (symbolP
, N_SLINE
);
10248 S_SET_OTHER (symbolP
, 0);
10249 S_SET_DESC (symbolP
, lineno
);
10250 symbolP
->sy_segment
= now_seg
;