1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* This is the set of options which may be modified by the .set
140 pseudo-op. We use a struct so that .set push and .set pop are more
143 struct mips_set_options
145 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
146 if it has not been initialized. Changed by `.set mipsN', and the
147 -mipsN command line option, and the default CPU. */
149 /* Enabled Application Specific Extensions (ASEs). These are set to -1
150 if they have not been initialized. Changed by `.set <asename>', by
151 command line options, and based on the default architecture. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros
;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
180 /* Restrict general purpose registers and floating point registers
181 to 32 bit. This is initially determined when -mgp32 or -mfp32
182 is passed but can changed if the assembler code uses .set mipsN. */
185 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
186 command line option, and the default CPU. */
190 /* True if -mgp32 was passed. */
191 static int file_mips_gp32
= -1;
193 /* True if -mfp32 was passed. */
194 static int file_mips_fp32
= -1;
196 /* This is the struct we use to hold the current set of options. Note
197 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
198 -1 to indicate that they have not been initialized. */
200 static struct mips_set_options mips_opts
=
202 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
205 /* These variables are filled in with the masks of registers used.
206 The object format code reads them and puts them in the appropriate
208 unsigned long mips_gprmask
;
209 unsigned long mips_cprmask
[4];
211 /* MIPS ISA we are using for this output file. */
212 static int file_mips_isa
= ISA_UNKNOWN
;
214 /* True if -mips16 was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mips16
;
218 /* True if -mips3d was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips3d
;
222 /* True if -mdmx was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mdmx
;
226 /* The argument of the -march= flag. The architecture we are assembling. */
227 static int file_mips_arch
= CPU_UNKNOWN
;
228 static const char *mips_arch_string
;
230 /* The argument of the -mtune= flag. The architecture for which we
232 static int mips_tune
= CPU_UNKNOWN
;
233 static const char *mips_tune_string
;
235 /* True when generating 32-bit code for a 64-bit processor. */
236 static int mips_32bitmode
= 0;
238 /* True if the given ABI requires 32-bit registers. */
239 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
241 /* Likewise 64-bit registers. */
242 #define ABI_NEEDS_64BIT_REGS(ABI) \
244 || (ABI) == N64_ABI \
247 /* Return true if ISA supports 64 bit gp register instructions. */
248 #define ISA_HAS_64BIT_REGS(ISA) ( \
250 || (ISA) == ISA_MIPS4 \
251 || (ISA) == ISA_MIPS5 \
252 || (ISA) == ISA_MIPS64 \
253 || (ISA) == ISA_MIPS64R2 \
256 /* Return true if ISA supports 64-bit right rotate (dror et al.)
258 #define ISA_HAS_DROR(ISA) ( \
259 (ISA) == ISA_MIPS64R2 \
262 /* Return true if ISA supports 32-bit right rotate (ror et al.)
264 #define ISA_HAS_ROR(ISA) ( \
265 (ISA) == ISA_MIPS32R2 \
266 || (ISA) == ISA_MIPS64R2 \
269 #define HAVE_32BIT_GPRS \
270 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
272 #define HAVE_32BIT_FPRS \
273 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
275 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
276 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
278 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
280 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
282 /* We can only have 64bit addresses if the object file format
284 #define HAVE_32BIT_ADDRESSES \
286 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
287 || ! HAVE_64BIT_OBJECTS) \
288 && mips_pic != EMBEDDED_PIC))
290 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
292 /* Addresses are loaded in different ways, depending on the address size
293 in use. The n32 ABI Documentation also mandates the use of additions
294 with overflow checking, but existing implementations don't follow it. */
295 #define ADDRESS_ADD_INSN \
296 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
298 #define ADDRESS_ADDI_INSN \
299 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
301 #define ADDRESS_LOAD_INSN \
302 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
304 #define ADDRESS_STORE_INSN \
305 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
307 /* Return true if the given CPU supports the MIPS16 ASE. */
308 #define CPU_HAS_MIPS16(cpu) \
309 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
310 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
312 /* Return true if the given CPU supports the MIPS3D ASE. */
313 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
316 /* Return true if the given CPU supports the MDMX ASE. */
317 #define CPU_HAS_MDMX(cpu) (FALSE \
320 /* True if CPU has a dror instruction. */
321 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
323 /* True if CPU has a ror instruction. */
324 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
326 /* True if mflo and mfhi can be immediately followed by instructions
327 which write to the HI and LO registers.
329 According to MIPS specifications, MIPS ISAs I, II, and III need
330 (at least) two instructions between the reads of HI/LO and
331 instructions which write them, and later ISAs do not. Contradicting
332 the MIPS specifications, some MIPS IV processor user manuals (e.g.
333 the UM for the NEC Vr5000) document needing the instructions between
334 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
335 MIPS64 and later ISAs to have the interlocks, plus any specific
336 earlier-ISA CPUs for which CPU documentation declares that the
337 instructions are really interlocked. */
338 #define hilo_interlocks \
339 (mips_opts.isa == ISA_MIPS32 \
340 || mips_opts.isa == ISA_MIPS32R2 \
341 || mips_opts.isa == ISA_MIPS64 \
342 || mips_opts.isa == ISA_MIPS64R2 \
343 || mips_opts.arch == CPU_R4010 \
344 || mips_opts.arch == CPU_R10000 \
345 || mips_opts.arch == CPU_R12000 \
346 || mips_opts.arch == CPU_RM7000 \
347 || mips_opts.arch == CPU_VR5500 \
350 /* Whether the processor uses hardware interlocks to protect reads
351 from the GPRs after they are loaded from memory, and thus does not
352 require nops to be inserted. This applies to instructions marked
353 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
355 #define gpr_interlocks \
356 (mips_opts.isa != ISA_MIPS1 \
357 || mips_opts.arch == CPU_R3900)
359 /* Whether the processor uses hardware interlocks to avoid delays
360 required by coprocessor instructions, and thus does not require
361 nops to be inserted. This applies to instructions marked
362 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
363 between instructions marked INSN_WRITE_COND_CODE and ones marked
364 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
365 levels I, II, and III. */
366 /* Itbl support may require additional care here. */
367 #define cop_interlocks \
368 ((mips_opts.isa != ISA_MIPS1 \
369 && mips_opts.isa != ISA_MIPS2 \
370 && mips_opts.isa != ISA_MIPS3) \
371 || mips_opts.arch == CPU_R4300 \
374 /* Whether the processor uses hardware interlocks to protect reads
375 from coprocessor registers after they are loaded from memory, and
376 thus does not require nops to be inserted. This applies to
377 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
378 requires at MIPS ISA level I. */
379 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
381 /* Is this a mfhi or mflo instruction? */
382 #define MF_HILO_INSN(PINFO) \
383 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
385 /* MIPS PIC level. */
387 enum mips_pic_level mips_pic
;
389 /* 1 if we should generate 32 bit offsets from the $gp register in
390 SVR4_PIC mode. Currently has no meaning in other modes. */
391 static int mips_big_got
= 0;
393 /* 1 if trap instructions should used for overflow rather than break
395 static int mips_trap
= 0;
397 /* 1 if double width floating point constants should not be constructed
398 by assembling two single width halves into two single width floating
399 point registers which just happen to alias the double width destination
400 register. On some architectures this aliasing can be disabled by a bit
401 in the status register, and the setting of this bit cannot be determined
402 automatically at assemble time. */
403 static int mips_disable_float_construction
;
405 /* Non-zero if any .set noreorder directives were used. */
407 static int mips_any_noreorder
;
409 /* Non-zero if nops should be inserted when the register referenced in
410 an mfhi/mflo instruction is read in the next two instructions. */
411 static int mips_7000_hilo_fix
;
413 /* The size of the small data section. */
414 static unsigned int g_switch_value
= 8;
415 /* Whether the -G option was used. */
416 static int g_switch_seen
= 0;
421 /* If we can determine in advance that GP optimization won't be
422 possible, we can skip the relaxation stuff that tries to produce
423 GP-relative references. This makes delay slot optimization work
426 This function can only provide a guess, but it seems to work for
427 gcc output. It needs to guess right for gcc, otherwise gcc
428 will put what it thinks is a GP-relative instruction in a branch
431 I don't know if a fix is needed for the SVR4_PIC mode. I've only
432 fixed it for the non-PIC mode. KR 95/04/07 */
433 static int nopic_need_relax (symbolS
*, int);
435 /* handle of the OPCODE hash table */
436 static struct hash_control
*op_hash
= NULL
;
438 /* The opcode hash table we use for the mips16. */
439 static struct hash_control
*mips16_op_hash
= NULL
;
441 /* This array holds the chars that always start a comment. If the
442 pre-processor is disabled, these aren't very useful */
443 const char comment_chars
[] = "#";
445 /* This array holds the chars that only start a comment at the beginning of
446 a line. If the line seems to have the form '# 123 filename'
447 .line and .file directives will appear in the pre-processed output */
448 /* Note that input_file.c hand checks for '#' at the beginning of the
449 first line of the input file. This is because the compiler outputs
450 #NO_APP at the beginning of its output. */
451 /* Also note that C style comments are always supported. */
452 const char line_comment_chars
[] = "#";
454 /* This array holds machine specific line separator characters. */
455 const char line_separator_chars
[] = ";";
457 /* Chars that can be used to separate mant from exp in floating point nums */
458 const char EXP_CHARS
[] = "eE";
460 /* Chars that mean this number is a floating point constant */
463 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
465 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
466 changed in read.c . Ideally it shouldn't have to know about it at all,
467 but nothing is ideal around here.
470 static char *insn_error
;
472 static int auto_align
= 1;
474 /* When outputting SVR4 PIC code, the assembler needs to know the
475 offset in the stack frame from which to restore the $gp register.
476 This is set by the .cprestore pseudo-op, and saved in this
478 static offsetT mips_cprestore_offset
= -1;
480 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
481 more optimizations, it can use a register value instead of a memory-saved
482 offset and even an other register than $gp as global pointer. */
483 static offsetT mips_cpreturn_offset
= -1;
484 static int mips_cpreturn_register
= -1;
485 static int mips_gp_register
= GP
;
486 static int mips_gprel_offset
= 0;
488 /* Whether mips_cprestore_offset has been set in the current function
489 (or whether it has already been warned about, if not). */
490 static int mips_cprestore_valid
= 0;
492 /* This is the register which holds the stack frame, as set by the
493 .frame pseudo-op. This is needed to implement .cprestore. */
494 static int mips_frame_reg
= SP
;
496 /* Whether mips_frame_reg has been set in the current function
497 (or whether it has already been warned about, if not). */
498 static int mips_frame_reg_valid
= 0;
500 /* To output NOP instructions correctly, we need to keep information
501 about the previous two instructions. */
503 /* Whether we are optimizing. The default value of 2 means to remove
504 unneeded NOPs and swap branch instructions when possible. A value
505 of 1 means to not swap branches. A value of 0 means to always
507 static int mips_optimize
= 2;
509 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
510 equivalent to seeing no -g option at all. */
511 static int mips_debug
= 0;
513 /* The previous instruction. */
514 static struct mips_cl_insn prev_insn
;
516 /* The instruction before prev_insn. */
517 static struct mips_cl_insn prev_prev_insn
;
519 /* If we don't want information for prev_insn or prev_prev_insn, we
520 point the insn_mo field at this dummy integer. */
521 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
523 /* Non-zero if prev_insn is valid. */
524 static int prev_insn_valid
;
526 /* The frag for the previous instruction. */
527 static struct frag
*prev_insn_frag
;
529 /* The offset into prev_insn_frag for the previous instruction. */
530 static long prev_insn_where
;
532 /* The reloc type for the previous instruction, if any. */
533 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
535 /* The reloc for the previous instruction, if any. */
536 static fixS
*prev_insn_fixp
[3];
538 /* Non-zero if the previous instruction was in a delay slot. */
539 static int prev_insn_is_delay_slot
;
541 /* Non-zero if the previous instruction was in a .set noreorder. */
542 static int prev_insn_unreordered
;
544 /* Non-zero if the previous instruction uses an extend opcode (if
546 static int prev_insn_extended
;
548 /* Non-zero if the previous previous instruction was in a .set
550 static int prev_prev_insn_unreordered
;
552 /* If this is set, it points to a frag holding nop instructions which
553 were inserted before the start of a noreorder section. If those
554 nops turn out to be unnecessary, the size of the frag can be
556 static fragS
*prev_nop_frag
;
558 /* The number of nop instructions we created in prev_nop_frag. */
559 static int prev_nop_frag_holds
;
561 /* The number of nop instructions that we know we need in
563 static int prev_nop_frag_required
;
565 /* The number of instructions we've seen since prev_nop_frag. */
566 static int prev_nop_frag_since
;
568 /* For ECOFF and ELF, relocations against symbols are done in two
569 parts, with a HI relocation and a LO relocation. Each relocation
570 has only 16 bits of space to store an addend. This means that in
571 order for the linker to handle carries correctly, it must be able
572 to locate both the HI and the LO relocation. This means that the
573 relocations must appear in order in the relocation table.
575 In order to implement this, we keep track of each unmatched HI
576 relocation. We then sort them so that they immediately precede the
577 corresponding LO relocation. */
582 struct mips_hi_fixup
*next
;
585 /* The section this fixup is in. */
589 /* The list of unmatched HI relocs. */
591 static struct mips_hi_fixup
*mips_hi_fixup_list
;
593 /* The frag containing the last explicit relocation operator.
594 Null if explicit relocations have not been used. */
596 static fragS
*prev_reloc_op_frag
;
598 /* Map normal MIPS register numbers to mips16 register numbers. */
600 #define X ILLEGAL_REG
601 static const int mips32_to_16_reg_map
[] =
603 X
, X
, 2, 3, 4, 5, 6, 7,
604 X
, X
, X
, X
, X
, X
, X
, X
,
605 0, 1, X
, X
, X
, X
, X
, X
,
606 X
, X
, X
, X
, X
, X
, X
, X
610 /* Map mips16 register numbers to normal MIPS register numbers. */
612 static const unsigned int mips16_to_32_reg_map
[] =
614 16, 17, 2, 3, 4, 5, 6, 7
617 static int mips_fix_vr4120
;
619 /* We don't relax branches by default, since this causes us to expand
620 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
621 fail to compute the offset before expanding the macro to the most
622 efficient expansion. */
624 static int mips_relax_branch
;
626 /* The expansion of many macros depends on the type of symbol that
627 they refer to. For example, when generating position-dependent code,
628 a macro that refers to a symbol may have two different expansions,
629 one which uses GP-relative addresses and one which uses absolute
630 addresses. When generating SVR4-style PIC, a macro may have
631 different expansions for local and global symbols.
633 We handle these situations by generating both sequences and putting
634 them in variant frags. In position-dependent code, the first sequence
635 will be the GP-relative one and the second sequence will be the
636 absolute one. In SVR4 PIC, the first sequence will be for global
637 symbols and the second will be for local symbols.
639 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
640 SECOND are the lengths of the two sequences in bytes. These fields
641 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
642 the subtype has the following flags:
645 Set if it has been decided that we should use the second
646 sequence instead of the first.
649 Set in the first variant frag if the macro's second implementation
650 is longer than its first. This refers to the macro as a whole,
651 not an individual relaxation.
654 Set in the first variant frag if the macro appeared in a .set nomacro
655 block and if one alternative requires a warning but the other does not.
658 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
661 The frag's "opcode" points to the first fixup for relaxable code.
663 Relaxable macros are generated using a sequence such as:
665 relax_start (SYMBOL);
666 ... generate first expansion ...
668 ... generate second expansion ...
671 The code and fixups for the unwanted alternative are discarded
672 by md_convert_frag. */
673 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
675 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
676 #define RELAX_SECOND(X) ((X) & 0xff)
677 #define RELAX_USE_SECOND 0x10000
678 #define RELAX_SECOND_LONGER 0x20000
679 #define RELAX_NOMACRO 0x40000
680 #define RELAX_DELAY_SLOT 0x80000
682 /* Branch without likely bit. If label is out of range, we turn:
684 beq reg1, reg2, label
694 with the following opcode replacements:
701 bltzal <-> bgezal (with jal label instead of j label)
703 Even though keeping the delay slot instruction in the delay slot of
704 the branch would be more efficient, it would be very tricky to do
705 correctly, because we'd have to introduce a variable frag *after*
706 the delay slot instruction, and expand that instead. Let's do it
707 the easy way for now, even if the branch-not-taken case now costs
708 one additional instruction. Out-of-range branches are not supposed
709 to be common, anyway.
711 Branch likely. If label is out of range, we turn:
713 beql reg1, reg2, label
714 delay slot (annulled if branch not taken)
723 delay slot (executed only if branch taken)
726 It would be possible to generate a shorter sequence by losing the
727 likely bit, generating something like:
732 delay slot (executed only if branch taken)
744 bltzall -> bgezal (with jal label instead of j label)
745 bgezall -> bltzal (ditto)
748 but it's not clear that it would actually improve performance. */
749 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
752 | ((toofar) ? 1 : 0) \
754 | ((likely) ? 4 : 0) \
755 | ((uncond) ? 8 : 0)))
756 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
757 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
758 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
759 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
760 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
762 /* For mips16 code, we use an entirely different form of relaxation.
763 mips16 supports two versions of most instructions which take
764 immediate values: a small one which takes some small value, and a
765 larger one which takes a 16 bit value. Since branches also follow
766 this pattern, relaxing these values is required.
768 We can assemble both mips16 and normal MIPS code in a single
769 object. Therefore, we need to support this type of relaxation at
770 the same time that we support the relaxation described above. We
771 use the high bit of the subtype field to distinguish these cases.
773 The information we store for this type of relaxation is the
774 argument code found in the opcode file for this relocation, whether
775 the user explicitly requested a small or extended form, and whether
776 the relocation is in a jump or jal delay slot. That tells us the
777 size of the value, and how it should be stored. We also store
778 whether the fragment is considered to be extended or not. We also
779 store whether this is known to be a branch to a different section,
780 whether we have tried to relax this frag yet, and whether we have
781 ever extended a PC relative fragment because of a shift count. */
782 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
785 | ((small) ? 0x100 : 0) \
786 | ((ext) ? 0x200 : 0) \
787 | ((dslot) ? 0x400 : 0) \
788 | ((jal_dslot) ? 0x800 : 0))
789 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
790 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
791 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
792 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
793 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
794 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
795 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
796 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
797 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
798 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
799 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
800 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
802 /* Is the given value a sign-extended 32-bit value? */
803 #define IS_SEXT_32BIT_NUM(x) \
804 (((x) &~ (offsetT) 0x7fffffff) == 0 \
805 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
807 /* Is the given value a sign-extended 16-bit value? */
808 #define IS_SEXT_16BIT_NUM(x) \
809 (((x) &~ (offsetT) 0x7fff) == 0 \
810 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
813 /* Global variables used when generating relaxable macros. See the
814 comment above RELAX_ENCODE for more details about how relaxation
817 /* 0 if we're not emitting a relaxable macro.
818 1 if we're emitting the first of the two relaxation alternatives.
819 2 if we're emitting the second alternative. */
822 /* The first relaxable fixup in the current frag. (In other words,
823 the first fixup that refers to relaxable code.) */
826 /* sizes[0] says how many bytes of the first alternative are stored in
827 the current frag. Likewise sizes[1] for the second alternative. */
828 unsigned int sizes
[2];
830 /* The symbol on which the choice of sequence depends. */
834 /* Global variables used to decide whether a macro needs a warning. */
836 /* True if the macro is in a branch delay slot. */
837 bfd_boolean delay_slot_p
;
839 /* For relaxable macros, sizes[0] is the length of the first alternative
840 in bytes and sizes[1] is the length of the second alternative.
841 For non-relaxable macros, both elements give the length of the
843 unsigned int sizes
[2];
845 /* The first variant frag for this macro. */
847 } mips_macro_warning
;
849 /* Prototypes for static functions. */
851 #define internalError() \
852 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
854 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
856 static void append_insn
857 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
858 static void mips_no_prev_insn (int);
859 static void mips16_macro_build
860 (expressionS
*, const char *, const char *, va_list);
861 static void load_register (int, expressionS
*, int);
862 static void macro_start (void);
863 static void macro_end (void);
864 static void macro (struct mips_cl_insn
* ip
);
865 static void mips16_macro (struct mips_cl_insn
* ip
);
866 #ifdef LOSING_COMPILER
867 static void macro2 (struct mips_cl_insn
* ip
);
869 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
870 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
871 static void mips16_immed
872 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
873 unsigned long *, bfd_boolean
*, unsigned short *);
874 static size_t my_getSmallExpression
875 (expressionS
*, bfd_reloc_code_real_type
*, char *);
876 static void my_getExpression (expressionS
*, char *);
877 static void s_align (int);
878 static void s_change_sec (int);
879 static void s_change_section (int);
880 static void s_cons (int);
881 static void s_float_cons (int);
882 static void s_mips_globl (int);
883 static void s_option (int);
884 static void s_mipsset (int);
885 static void s_abicalls (int);
886 static void s_cpload (int);
887 static void s_cpsetup (int);
888 static void s_cplocal (int);
889 static void s_cprestore (int);
890 static void s_cpreturn (int);
891 static void s_gpvalue (int);
892 static void s_gpword (int);
893 static void s_gpdword (int);
894 static void s_cpadd (int);
895 static void s_insn (int);
896 static void md_obj_begin (void);
897 static void md_obj_end (void);
898 static void s_mips_ent (int);
899 static void s_mips_end (int);
900 static void s_mips_frame (int);
901 static void s_mips_mask (int reg_type
);
902 static void s_mips_stab (int);
903 static void s_mips_weakext (int);
904 static void s_mips_file (int);
905 static void s_mips_loc (int);
906 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
907 static int relaxed_branch_length (fragS
*, asection
*, int);
908 static int validate_mips_insn (const struct mips_opcode
*);
910 /* Table and functions used to map between CPU/ISA names, and
911 ISA levels, and CPU numbers. */
915 const char *name
; /* CPU or ISA name. */
916 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
917 int isa
; /* ISA level. */
918 int cpu
; /* CPU number (default CPU if ISA). */
921 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
922 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
923 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
927 The following pseudo-ops from the Kane and Heinrich MIPS book
928 should be defined here, but are currently unsupported: .alias,
929 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
931 The following pseudo-ops from the Kane and Heinrich MIPS book are
932 specific to the type of debugging information being generated, and
933 should be defined by the object format: .aent, .begin, .bend,
934 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
937 The following pseudo-ops from the Kane and Heinrich MIPS book are
938 not MIPS CPU specific, but are also not specific to the object file
939 format. This file is probably the best place to define them, but
940 they are not currently supported: .asm0, .endr, .lab, .repeat,
943 static const pseudo_typeS mips_pseudo_table
[] =
945 /* MIPS specific pseudo-ops. */
946 {"option", s_option
, 0},
947 {"set", s_mipsset
, 0},
948 {"rdata", s_change_sec
, 'r'},
949 {"sdata", s_change_sec
, 's'},
950 {"livereg", s_ignore
, 0},
951 {"abicalls", s_abicalls
, 0},
952 {"cpload", s_cpload
, 0},
953 {"cpsetup", s_cpsetup
, 0},
954 {"cplocal", s_cplocal
, 0},
955 {"cprestore", s_cprestore
, 0},
956 {"cpreturn", s_cpreturn
, 0},
957 {"gpvalue", s_gpvalue
, 0},
958 {"gpword", s_gpword
, 0},
959 {"gpdword", s_gpdword
, 0},
960 {"cpadd", s_cpadd
, 0},
963 /* Relatively generic pseudo-ops that happen to be used on MIPS
965 {"asciiz", stringer
, 1},
966 {"bss", s_change_sec
, 'b'},
969 {"dword", s_cons
, 3},
970 {"weakext", s_mips_weakext
, 0},
972 /* These pseudo-ops are defined in read.c, but must be overridden
973 here for one reason or another. */
974 {"align", s_align
, 0},
976 {"data", s_change_sec
, 'd'},
977 {"double", s_float_cons
, 'd'},
978 {"float", s_float_cons
, 'f'},
979 {"globl", s_mips_globl
, 0},
980 {"global", s_mips_globl
, 0},
981 {"hword", s_cons
, 1},
986 {"section", s_change_section
, 0},
987 {"short", s_cons
, 1},
988 {"single", s_float_cons
, 'f'},
989 {"stabn", s_mips_stab
, 'n'},
990 {"text", s_change_sec
, 't'},
993 { "extern", ecoff_directive_extern
, 0},
998 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1000 /* These pseudo-ops should be defined by the object file format.
1001 However, a.out doesn't support them, so we have versions here. */
1002 {"aent", s_mips_ent
, 1},
1003 {"bgnb", s_ignore
, 0},
1004 {"end", s_mips_end
, 0},
1005 {"endb", s_ignore
, 0},
1006 {"ent", s_mips_ent
, 0},
1007 {"file", s_mips_file
, 0},
1008 {"fmask", s_mips_mask
, 'F'},
1009 {"frame", s_mips_frame
, 0},
1010 {"loc", s_mips_loc
, 0},
1011 {"mask", s_mips_mask
, 'R'},
1012 {"verstamp", s_ignore
, 0},
1016 extern void pop_insert (const pseudo_typeS
*);
1019 mips_pop_insert (void)
1021 pop_insert (mips_pseudo_table
);
1022 if (! ECOFF_DEBUGGING
)
1023 pop_insert (mips_nonecoff_pseudo_table
);
1026 /* Symbols labelling the current insn. */
1028 struct insn_label_list
1030 struct insn_label_list
*next
;
1034 static struct insn_label_list
*insn_labels
;
1035 static struct insn_label_list
*free_insn_labels
;
1037 static void mips_clear_insn_labels (void);
1040 mips_clear_insn_labels (void)
1042 register struct insn_label_list
**pl
;
1044 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1050 static char *expr_end
;
1052 /* Expressions which appear in instructions. These are set by
1055 static expressionS imm_expr
;
1056 static expressionS imm2_expr
;
1057 static expressionS offset_expr
;
1059 /* Relocs associated with imm_expr and offset_expr. */
1061 static bfd_reloc_code_real_type imm_reloc
[3]
1062 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1063 static bfd_reloc_code_real_type offset_reloc
[3]
1064 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1066 /* These are set by mips16_ip if an explicit extension is used. */
1068 static bfd_boolean mips16_small
, mips16_ext
;
1071 /* The pdr segment for per procedure frame/regmask info. Not used for
1074 static segT pdr_seg
;
1077 /* The default target format to use. */
1080 mips_target_format (void)
1082 switch (OUTPUT_FLAVOR
)
1084 case bfd_target_ecoff_flavour
:
1085 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1086 case bfd_target_coff_flavour
:
1088 case bfd_target_elf_flavour
:
1090 /* This is traditional mips. */
1091 return (target_big_endian
1092 ? (HAVE_64BIT_OBJECTS
1093 ? "elf64-tradbigmips"
1095 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1096 : (HAVE_64BIT_OBJECTS
1097 ? "elf64-tradlittlemips"
1099 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1101 return (target_big_endian
1102 ? (HAVE_64BIT_OBJECTS
1105 ? "elf32-nbigmips" : "elf32-bigmips"))
1106 : (HAVE_64BIT_OBJECTS
1107 ? "elf64-littlemips"
1109 ? "elf32-nlittlemips" : "elf32-littlemips")));
1117 /* This function is called once, at assembler startup time. It should
1118 set up all the tables, etc. that the MD part of the assembler will need. */
1123 register const char *retval
= NULL
;
1127 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1128 as_warn (_("Could not set architecture and machine"));
1130 op_hash
= hash_new ();
1132 for (i
= 0; i
< NUMOPCODES
;)
1134 const char *name
= mips_opcodes
[i
].name
;
1136 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1139 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1140 mips_opcodes
[i
].name
, retval
);
1141 /* Probably a memory allocation problem? Give up now. */
1142 as_fatal (_("Broken assembler. No assembly attempted."));
1146 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1148 if (!validate_mips_insn (&mips_opcodes
[i
]))
1153 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1156 mips16_op_hash
= hash_new ();
1159 while (i
< bfd_mips16_num_opcodes
)
1161 const char *name
= mips16_opcodes
[i
].name
;
1163 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1165 as_fatal (_("internal: can't hash `%s': %s"),
1166 mips16_opcodes
[i
].name
, retval
);
1169 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1170 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1171 != mips16_opcodes
[i
].match
))
1173 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1174 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1179 while (i
< bfd_mips16_num_opcodes
1180 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1184 as_fatal (_("Broken assembler. No assembly attempted."));
1186 /* We add all the general register names to the symbol table. This
1187 helps us detect invalid uses of them. */
1188 for (i
= 0; i
< 32; i
++)
1192 sprintf (buf
, "$%d", i
);
1193 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1194 &zero_address_frag
));
1196 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1197 &zero_address_frag
));
1198 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1199 &zero_address_frag
));
1200 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1201 &zero_address_frag
));
1202 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1203 &zero_address_frag
));
1204 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1205 &zero_address_frag
));
1206 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1207 &zero_address_frag
));
1208 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1209 &zero_address_frag
));
1210 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1211 &zero_address_frag
));
1212 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1213 &zero_address_frag
));
1215 /* If we don't add these register names to the symbol table, they
1216 may end up being added as regular symbols by operand(), and then
1217 make it to the object file as undefined in case they're not
1218 regarded as local symbols. They're local in o32, since `$' is a
1219 local symbol prefix, but not in n32 or n64. */
1220 for (i
= 0; i
< 8; i
++)
1224 sprintf (buf
, "$fcc%i", i
);
1225 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1226 &zero_address_frag
));
1229 mips_no_prev_insn (FALSE
);
1232 mips_cprmask
[0] = 0;
1233 mips_cprmask
[1] = 0;
1234 mips_cprmask
[2] = 0;
1235 mips_cprmask
[3] = 0;
1237 /* set the default alignment for the text section (2**2) */
1238 record_alignment (text_section
, 2);
1240 bfd_set_gp_size (stdoutput
, g_switch_value
);
1242 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1244 /* On a native system, sections must be aligned to 16 byte
1245 boundaries. When configured for an embedded ELF target, we
1247 if (strcmp (TARGET_OS
, "elf") != 0)
1249 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1250 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1251 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1254 /* Create a .reginfo section for register masks and a .mdebug
1255 section for debugging information. */
1263 subseg
= now_subseg
;
1265 /* The ABI says this section should be loaded so that the
1266 running program can access it. However, we don't load it
1267 if we are configured for an embedded target */
1268 flags
= SEC_READONLY
| SEC_DATA
;
1269 if (strcmp (TARGET_OS
, "elf") != 0)
1270 flags
|= SEC_ALLOC
| SEC_LOAD
;
1272 if (mips_abi
!= N64_ABI
)
1274 sec
= subseg_new (".reginfo", (subsegT
) 0);
1276 bfd_set_section_flags (stdoutput
, sec
, flags
);
1277 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1280 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1285 /* The 64-bit ABI uses a .MIPS.options section rather than
1286 .reginfo section. */
1287 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1288 bfd_set_section_flags (stdoutput
, sec
, flags
);
1289 bfd_set_section_alignment (stdoutput
, sec
, 3);
1292 /* Set up the option header. */
1294 Elf_Internal_Options opthdr
;
1297 opthdr
.kind
= ODK_REGINFO
;
1298 opthdr
.size
= (sizeof (Elf_External_Options
)
1299 + sizeof (Elf64_External_RegInfo
));
1302 f
= frag_more (sizeof (Elf_External_Options
));
1303 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1304 (Elf_External_Options
*) f
);
1306 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1311 if (ECOFF_DEBUGGING
)
1313 sec
= subseg_new (".mdebug", (subsegT
) 0);
1314 (void) bfd_set_section_flags (stdoutput
, sec
,
1315 SEC_HAS_CONTENTS
| SEC_READONLY
);
1316 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1319 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1321 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1322 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1323 SEC_READONLY
| SEC_RELOC
1325 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1329 subseg_set (seg
, subseg
);
1333 if (! ECOFF_DEBUGGING
)
1340 if (! ECOFF_DEBUGGING
)
1345 md_assemble (char *str
)
1347 struct mips_cl_insn insn
;
1348 bfd_reloc_code_real_type unused_reloc
[3]
1349 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1351 imm_expr
.X_op
= O_absent
;
1352 imm2_expr
.X_op
= O_absent
;
1353 offset_expr
.X_op
= O_absent
;
1354 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1355 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1356 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1357 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1358 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1359 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1361 if (mips_opts
.mips16
)
1362 mips16_ip (str
, &insn
);
1365 mips_ip (str
, &insn
);
1366 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1367 str
, insn
.insn_opcode
));
1372 as_bad ("%s `%s'", insn_error
, str
);
1376 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1379 if (mips_opts
.mips16
)
1380 mips16_macro (&insn
);
1387 if (imm_expr
.X_op
!= O_absent
)
1388 append_insn (&insn
, &imm_expr
, imm_reloc
);
1389 else if (offset_expr
.X_op
!= O_absent
)
1390 append_insn (&insn
, &offset_expr
, offset_reloc
);
1392 append_insn (&insn
, NULL
, unused_reloc
);
1396 /* Return true if the given relocation might need a matching %lo().
1397 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1398 applied to local symbols. */
1400 static inline bfd_boolean
1401 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1403 return (reloc
== BFD_RELOC_HI16_S
1404 || reloc
== BFD_RELOC_MIPS_GOT16
);
1407 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1410 static inline bfd_boolean
1411 fixup_has_matching_lo_p (fixS
*fixp
)
1413 return (fixp
->fx_next
!= NULL
1414 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1415 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1416 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1419 /* See whether instruction IP reads register REG. CLASS is the type
1423 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1424 enum mips_regclass
class)
1426 if (class == MIPS16_REG
)
1428 assert (mips_opts
.mips16
);
1429 reg
= mips16_to_32_reg_map
[reg
];
1430 class = MIPS_GR_REG
;
1433 /* Don't report on general register ZERO, since it never changes. */
1434 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1437 if (class == MIPS_FP_REG
)
1439 assert (! mips_opts
.mips16
);
1440 /* If we are called with either $f0 or $f1, we must check $f0.
1441 This is not optimal, because it will introduce an unnecessary
1442 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1443 need to distinguish reading both $f0 and $f1 or just one of
1444 them. Note that we don't have to check the other way,
1445 because there is no instruction that sets both $f0 and $f1
1446 and requires a delay. */
1447 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1448 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1449 == (reg
&~ (unsigned) 1)))
1451 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1452 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1453 == (reg
&~ (unsigned) 1)))
1456 else if (! mips_opts
.mips16
)
1458 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1459 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1461 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1462 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1467 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1468 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1469 & MIPS16OP_MASK_RX
)]
1472 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1473 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1474 & MIPS16OP_MASK_RY
)]
1477 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1478 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1479 & MIPS16OP_MASK_MOVE32Z
)]
1482 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1484 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1486 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1488 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1489 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1490 & MIPS16OP_MASK_REGR32
) == reg
)
1497 /* This function returns true if modifying a register requires a
1501 reg_needs_delay (unsigned int reg
)
1503 unsigned long prev_pinfo
;
1505 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1506 if (! mips_opts
.noreorder
1507 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1508 && ! gpr_interlocks
)
1509 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1510 && ! cop_interlocks
)))
1512 /* A load from a coprocessor or from memory. All load delays
1513 delay the use of general register rt for one instruction. */
1514 /* Itbl support may require additional care here. */
1515 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1516 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1523 /* Mark instruction labels in mips16 mode. This permits the linker to
1524 handle them specially, such as generating jalx instructions when
1525 needed. We also make them odd for the duration of the assembly, in
1526 order to generate the right sort of code. We will make them even
1527 in the adjust_symtab routine, while leaving them marked. This is
1528 convenient for the debugger and the disassembler. The linker knows
1529 to make them odd again. */
1532 mips16_mark_labels (void)
1534 if (mips_opts
.mips16
)
1536 struct insn_label_list
*l
;
1539 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1542 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1543 S_SET_OTHER (l
->label
, STO_MIPS16
);
1545 val
= S_GET_VALUE (l
->label
);
1547 S_SET_VALUE (l
->label
, val
+ 1);
1552 /* End the current frag. Make it a variant frag and record the
1556 relax_close_frag (void)
1558 mips_macro_warning
.first_frag
= frag_now
;
1559 frag_var (rs_machine_dependent
, 0, 0,
1560 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1561 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1563 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1564 mips_relax
.first_fixup
= 0;
1567 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1568 See the comment above RELAX_ENCODE for more details. */
1571 relax_start (symbolS
*symbol
)
1573 assert (mips_relax
.sequence
== 0);
1574 mips_relax
.sequence
= 1;
1575 mips_relax
.symbol
= symbol
;
1578 /* Start generating the second version of a relaxable sequence.
1579 See the comment above RELAX_ENCODE for more details. */
1584 assert (mips_relax
.sequence
== 1);
1585 mips_relax
.sequence
= 2;
1588 /* End the current relaxable sequence. */
1593 assert (mips_relax
.sequence
== 2);
1594 relax_close_frag ();
1595 mips_relax
.sequence
= 0;
1598 /* Output an instruction. IP is the instruction information.
1599 ADDRESS_EXPR is an operand of the instruction to be used with
1603 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1604 bfd_reloc_code_real_type
*reloc_type
)
1606 register unsigned long prev_pinfo
, pinfo
;
1610 relax_stateT prev_insn_frag_type
= 0;
1611 bfd_boolean relaxed_branch
= FALSE
;
1612 bfd_boolean force_new_frag
= FALSE
;
1614 /* Mark instruction labels in mips16 mode. */
1615 mips16_mark_labels ();
1617 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1618 pinfo
= ip
->insn_mo
->pinfo
;
1620 if (mips_relax
.sequence
!= 2
1621 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1625 /* If the previous insn required any delay slots, see if we need
1626 to insert a NOP or two. There are eight kinds of possible
1627 hazards, of which an instruction can have at most one type.
1628 (1) a load from memory delay
1629 (2) a load from a coprocessor delay
1630 (3) an unconditional branch delay
1631 (4) a conditional branch delay
1632 (5) a move to coprocessor register delay
1633 (6) a load coprocessor register from memory delay
1634 (7) a coprocessor condition code delay
1635 (8) a HI/LO special register delay
1637 There are a lot of optimizations we could do that we don't.
1638 In particular, we do not, in general, reorder instructions.
1639 If you use gcc with optimization, it will reorder
1640 instructions and generally do much more optimization then we
1641 do here; repeating all that work in the assembler would only
1642 benefit hand written assembly code, and does not seem worth
1645 /* This is how a NOP is emitted. */
1646 #define emit_nop() \
1648 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1649 : md_number_to_chars (frag_more (4), 0, 4))
1651 /* The previous insn might require a delay slot, depending upon
1652 the contents of the current insn. */
1653 if (! mips_opts
.mips16
1654 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1655 && ! gpr_interlocks
)
1656 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1657 && ! cop_interlocks
)))
1659 /* A load from a coprocessor or from memory. All load
1660 delays delay the use of general register rt for one
1662 /* Itbl support may require additional care here. */
1663 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1664 if (mips_optimize
== 0
1665 || insn_uses_reg (ip
,
1666 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1671 else if (! mips_opts
.mips16
1672 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1673 && ! cop_interlocks
)
1674 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1675 && ! cop_mem_interlocks
)))
1677 /* A generic coprocessor delay. The previous instruction
1678 modified a coprocessor general or control register. If
1679 it modified a control register, we need to avoid any
1680 coprocessor instruction (this is probably not always
1681 required, but it sometimes is). If it modified a general
1682 register, we avoid using that register.
1684 This case is not handled very well. There is no special
1685 knowledge of CP0 handling, and the coprocessors other
1686 than the floating point unit are not distinguished at
1688 /* Itbl support may require additional care here. FIXME!
1689 Need to modify this to include knowledge about
1690 user specified delays! */
1691 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1693 if (mips_optimize
== 0
1694 || insn_uses_reg (ip
,
1695 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1700 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1702 if (mips_optimize
== 0
1703 || insn_uses_reg (ip
,
1704 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1711 /* We don't know exactly what the previous instruction
1712 does. If the current instruction uses a coprocessor
1713 register, we must insert a NOP. If previous
1714 instruction may set the condition codes, and the
1715 current instruction uses them, we must insert two
1717 /* Itbl support may require additional care here. */
1718 if (mips_optimize
== 0
1719 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1720 && (pinfo
& INSN_READ_COND_CODE
)))
1722 else if (pinfo
& INSN_COP
)
1726 else if (! mips_opts
.mips16
1727 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1728 && ! cop_interlocks
)
1730 /* The previous instruction sets the coprocessor condition
1731 codes, but does not require a general coprocessor delay
1732 (this means it is a floating point comparison
1733 instruction). If this instruction uses the condition
1734 codes, we need to insert a single NOP. */
1735 /* Itbl support may require additional care here. */
1736 if (mips_optimize
== 0
1737 || (pinfo
& INSN_READ_COND_CODE
))
1741 /* If we're fixing up mfhi/mflo for the r7000 and the
1742 previous insn was an mfhi/mflo and the current insn
1743 reads the register that the mfhi/mflo wrote to, then
1746 else if (mips_7000_hilo_fix
1747 && MF_HILO_INSN (prev_pinfo
)
1748 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1755 /* If we're fixing up mfhi/mflo for the r7000 and the
1756 2nd previous insn was an mfhi/mflo and the current insn
1757 reads the register that the mfhi/mflo wrote to, then
1760 else if (mips_7000_hilo_fix
1761 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1762 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1770 else if (prev_pinfo
& INSN_READ_LO
)
1772 /* The previous instruction reads the LO register; if the
1773 current instruction writes to the LO register, we must
1774 insert two NOPS. Some newer processors have interlocks.
1775 Also the tx39's multiply instructions can be executed
1776 immediately after a read from HI/LO (without the delay),
1777 though the tx39's divide insns still do require the
1779 if (! (hilo_interlocks
1780 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1781 && (mips_optimize
== 0
1782 || (pinfo
& INSN_WRITE_LO
)))
1784 /* Most mips16 branch insns don't have a delay slot.
1785 If a read from LO is immediately followed by a branch
1786 to a write to LO we have a read followed by a write
1787 less than 2 insns away. We assume the target of
1788 a branch might be a write to LO, and insert a nop
1789 between a read and an immediately following branch. */
1790 else if (mips_opts
.mips16
1791 && (mips_optimize
== 0
1792 || (pinfo
& MIPS16_INSN_BRANCH
)))
1795 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1797 /* The previous instruction reads the HI register; if the
1798 current instruction writes to the HI register, we must
1799 insert a NOP. Some newer processors have interlocks.
1800 Also the note tx39's multiply above. */
1801 if (! (hilo_interlocks
1802 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1803 && (mips_optimize
== 0
1804 || (pinfo
& INSN_WRITE_HI
)))
1806 /* Most mips16 branch insns don't have a delay slot.
1807 If a read from HI is immediately followed by a branch
1808 to a write to HI we have a read followed by a write
1809 less than 2 insns away. We assume the target of
1810 a branch might be a write to HI, and insert a nop
1811 between a read and an immediately following branch. */
1812 else if (mips_opts
.mips16
1813 && (mips_optimize
== 0
1814 || (pinfo
& MIPS16_INSN_BRANCH
)))
1818 /* If the previous instruction was in a noreorder section, then
1819 we don't want to insert the nop after all. */
1820 /* Itbl support may require additional care here. */
1821 if (prev_insn_unreordered
)
1824 /* There are two cases which require two intervening
1825 instructions: 1) setting the condition codes using a move to
1826 coprocessor instruction which requires a general coprocessor
1827 delay and then reading the condition codes 2) reading the HI
1828 or LO register and then writing to it (except on processors
1829 which have interlocks). If we are not already emitting a NOP
1830 instruction, we must check for these cases compared to the
1831 instruction previous to the previous instruction. */
1832 if ((! mips_opts
.mips16
1833 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1834 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1835 && (pinfo
& INSN_READ_COND_CODE
)
1836 && ! cop_interlocks
)
1837 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1838 && (pinfo
& INSN_WRITE_LO
)
1839 && ! (hilo_interlocks
1840 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1841 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1842 && (pinfo
& INSN_WRITE_HI
)
1843 && ! (hilo_interlocks
1844 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1849 if (prev_prev_insn_unreordered
)
1852 if (prev_prev_nop
&& nops
== 0)
1855 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1857 /* We're out of bits in pinfo, so we must resort to string
1858 ops here. Shortcuts are selected based on opcodes being
1859 limited to the VR4120 instruction set. */
1861 const char *pn
= prev_insn
.insn_mo
->name
;
1862 const char *tn
= ip
->insn_mo
->name
;
1863 if (strncmp(pn
, "macc", 4) == 0
1864 || strncmp(pn
, "dmacc", 5) == 0)
1866 /* Errata 21 - [D]DIV[U] after [D]MACC */
1867 if (strstr (tn
, "div"))
1872 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1873 if (pn
[0] == 'd' /* dmacc */
1874 && (strncmp(tn
, "dmult", 5) == 0
1875 || strncmp(tn
, "dmacc", 5) == 0))
1880 /* Errata 24 - MT{LO,HI} after [D]MACC */
1881 if (strcmp (tn
, "mtlo") == 0
1882 || strcmp (tn
, "mthi") == 0)
1888 else if (strncmp(pn
, "dmult", 5) == 0
1889 && (strncmp(tn
, "dmult", 5) == 0
1890 || strncmp(tn
, "dmacc", 5) == 0))
1892 /* Here is the rest of errata 23. */
1895 if (nops
< min_nops
)
1899 /* If we are being given a nop instruction, don't bother with
1900 one of the nops we would otherwise output. This will only
1901 happen when a nop instruction is used with mips_optimize set
1904 && ! mips_opts
.noreorder
1905 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1908 /* Now emit the right number of NOP instructions. */
1909 if (nops
> 0 && ! mips_opts
.noreorder
)
1912 unsigned long old_frag_offset
;
1914 struct insn_label_list
*l
;
1916 old_frag
= frag_now
;
1917 old_frag_offset
= frag_now_fix ();
1919 for (i
= 0; i
< nops
; i
++)
1924 listing_prev_line ();
1925 /* We may be at the start of a variant frag. In case we
1926 are, make sure there is enough space for the frag
1927 after the frags created by listing_prev_line. The
1928 argument to frag_grow here must be at least as large
1929 as the argument to all other calls to frag_grow in
1930 this file. We don't have to worry about being in the
1931 middle of a variant frag, because the variants insert
1932 all needed nop instructions themselves. */
1936 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1940 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1941 symbol_set_frag (l
->label
, frag_now
);
1942 val
= (valueT
) frag_now_fix ();
1943 /* mips16 text labels are stored as odd. */
1944 if (mips_opts
.mips16
)
1946 S_SET_VALUE (l
->label
, val
);
1949 #ifndef NO_ECOFF_DEBUGGING
1950 if (ECOFF_DEBUGGING
)
1951 ecoff_fix_loc (old_frag
, old_frag_offset
);
1954 else if (prev_nop_frag
!= NULL
)
1956 /* We have a frag holding nops we may be able to remove. If
1957 we don't need any nops, we can decrease the size of
1958 prev_nop_frag by the size of one instruction. If we do
1959 need some nops, we count them in prev_nops_required. */
1960 if (prev_nop_frag_since
== 0)
1964 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1965 --prev_nop_frag_holds
;
1968 prev_nop_frag_required
+= nops
;
1972 if (prev_prev_nop
== 0)
1974 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1975 --prev_nop_frag_holds
;
1978 ++prev_nop_frag_required
;
1981 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1982 prev_nop_frag
= NULL
;
1984 ++prev_nop_frag_since
;
1986 /* Sanity check: by the time we reach the second instruction
1987 after prev_nop_frag, we should have used up all the nops
1988 one way or another. */
1989 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1993 /* Record the frag type before frag_var. */
1995 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
1998 && *reloc_type
== BFD_RELOC_16_PCREL_S2
1999 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2000 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2001 && mips_relax_branch
2002 /* Don't try branch relaxation within .set nomacro, or within
2003 .set noat if we use $at for PIC computations. If it turns
2004 out that the branch was out-of-range, we'll get an error. */
2005 && !mips_opts
.warn_about_macros
2006 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2007 && !mips_opts
.mips16
)
2009 relaxed_branch
= TRUE
;
2010 f
= frag_var (rs_machine_dependent
,
2011 relaxed_branch_length
2013 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2014 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2016 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2017 pinfo
& INSN_COND_BRANCH_LIKELY
,
2018 pinfo
& INSN_WRITE_GPR_31
,
2020 address_expr
->X_add_symbol
,
2021 address_expr
->X_add_number
,
2023 *reloc_type
= BFD_RELOC_UNUSED
;
2025 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2027 /* We need to set up a variant frag. */
2028 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2029 f
= frag_var (rs_machine_dependent
, 4, 0,
2030 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2031 mips16_small
, mips16_ext
,
2033 & INSN_UNCOND_BRANCH_DELAY
),
2034 (*prev_insn_reloc_type
2035 == BFD_RELOC_MIPS16_JMP
)),
2036 make_expr_symbol (address_expr
), 0, NULL
);
2038 else if (mips_opts
.mips16
2040 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2042 /* Make sure there is enough room to swap this instruction with
2043 a following jump instruction. */
2049 if (mips_opts
.mips16
2050 && mips_opts
.noreorder
2051 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2052 as_warn (_("extended instruction in delay slot"));
2054 if (mips_relax
.sequence
)
2056 /* If we've reached the end of this frag, turn it into a variant
2057 frag and record the information for the instructions we've
2059 if (frag_room () < 4)
2060 relax_close_frag ();
2061 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2064 if (mips_relax
.sequence
!= 2)
2065 mips_macro_warning
.sizes
[0] += 4;
2066 if (mips_relax
.sequence
!= 1)
2067 mips_macro_warning
.sizes
[1] += 4;
2072 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2073 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2075 if (address_expr
->X_op
== O_constant
)
2079 switch (*reloc_type
)
2082 ip
->insn_opcode
|= address_expr
->X_add_number
;
2085 case BFD_RELOC_MIPS_HIGHEST
:
2086 tmp
= (address_expr
->X_add_number
2087 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2089 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2092 case BFD_RELOC_MIPS_HIGHER
:
2093 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2094 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2097 case BFD_RELOC_HI16_S
:
2098 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2102 case BFD_RELOC_HI16
:
2103 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2106 case BFD_RELOC_LO16
:
2107 case BFD_RELOC_MIPS_GOT_DISP
:
2108 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2111 case BFD_RELOC_MIPS_JMP
:
2112 if ((address_expr
->X_add_number
& 3) != 0)
2113 as_bad (_("jump to misaligned address (0x%lx)"),
2114 (unsigned long) address_expr
->X_add_number
);
2115 if (address_expr
->X_add_number
& ~0xfffffff)
2116 as_bad (_("jump address range overflow (0x%lx)"),
2117 (unsigned long) address_expr
->X_add_number
);
2118 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2121 case BFD_RELOC_MIPS16_JMP
:
2122 if ((address_expr
->X_add_number
& 3) != 0)
2123 as_bad (_("jump to misaligned address (0x%lx)"),
2124 (unsigned long) address_expr
->X_add_number
);
2125 if (address_expr
->X_add_number
& ~0xfffffff)
2126 as_bad (_("jump address range overflow (0x%lx)"),
2127 (unsigned long) address_expr
->X_add_number
);
2129 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2130 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2131 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2134 case BFD_RELOC_16_PCREL_S2
:
2144 reloc_howto_type
*howto
;
2147 /* In a compound relocation, it is the final (outermost)
2148 operator that determines the relocated field. */
2149 for (i
= 1; i
< 3; i
++)
2150 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2153 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2154 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2155 bfd_get_reloc_size(howto
),
2157 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2160 /* These relocations can have an addend that won't fit in
2161 4 octets for 64bit assembly. */
2163 && ! howto
->partial_inplace
2164 && (reloc_type
[0] == BFD_RELOC_16
2165 || reloc_type
[0] == BFD_RELOC_32
2166 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2167 || reloc_type
[0] == BFD_RELOC_HI16_S
2168 || reloc_type
[0] == BFD_RELOC_LO16
2169 || reloc_type
[0] == BFD_RELOC_GPREL16
2170 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2171 || reloc_type
[0] == BFD_RELOC_GPREL32
2172 || reloc_type
[0] == BFD_RELOC_64
2173 || reloc_type
[0] == BFD_RELOC_CTOR
2174 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2175 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2176 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2177 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2178 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2179 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2180 fixp
[0]->fx_no_overflow
= 1;
2182 if (mips_relax
.sequence
)
2184 if (mips_relax
.first_fixup
== 0)
2185 mips_relax
.first_fixup
= fixp
[0];
2187 else if (reloc_needs_lo_p (*reloc_type
))
2189 struct mips_hi_fixup
*hi_fixup
;
2191 /* Reuse the last entry if it already has a matching %lo. */
2192 hi_fixup
= mips_hi_fixup_list
;
2194 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2196 hi_fixup
= ((struct mips_hi_fixup
*)
2197 xmalloc (sizeof (struct mips_hi_fixup
)));
2198 hi_fixup
->next
= mips_hi_fixup_list
;
2199 mips_hi_fixup_list
= hi_fixup
;
2201 hi_fixup
->fixp
= fixp
[0];
2202 hi_fixup
->seg
= now_seg
;
2205 /* Add fixups for the second and third relocations, if given.
2206 Note that the ABI allows the second relocation to be
2207 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2208 moment we only use RSS_UNDEF, but we could add support
2209 for the others if it ever becomes necessary. */
2210 for (i
= 1; i
< 3; i
++)
2211 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2213 address_expr
->X_op
= O_absent
;
2214 address_expr
->X_add_symbol
= 0;
2215 address_expr
->X_add_number
= 0;
2217 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2218 fixp
[0]->fx_size
, address_expr
,
2219 FALSE
, reloc_type
[i
]);
2224 if (! mips_opts
.mips16
)
2226 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2228 dwarf2_emit_insn (4);
2231 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2233 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2234 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2236 dwarf2_emit_insn (4);
2243 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2246 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2248 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2252 /* Update the register mask information. */
2253 if (! mips_opts
.mips16
)
2255 if (pinfo
& INSN_WRITE_GPR_D
)
2256 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2257 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2258 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2259 if (pinfo
& INSN_READ_GPR_S
)
2260 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2261 if (pinfo
& INSN_WRITE_GPR_31
)
2262 mips_gprmask
|= 1 << RA
;
2263 if (pinfo
& INSN_WRITE_FPR_D
)
2264 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2265 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2266 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2267 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2268 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2269 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2270 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2271 if (pinfo
& INSN_COP
)
2273 /* We don't keep enough information to sort these cases out.
2274 The itbl support does keep this information however, although
2275 we currently don't support itbl fprmats as part of the cop
2276 instruction. May want to add this support in the future. */
2278 /* Never set the bit for $0, which is always zero. */
2279 mips_gprmask
&= ~1 << 0;
2283 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2284 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2285 & MIPS16OP_MASK_RX
);
2286 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2287 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2288 & MIPS16OP_MASK_RY
);
2289 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2290 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2291 & MIPS16OP_MASK_RZ
);
2292 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2293 mips_gprmask
|= 1 << TREG
;
2294 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2295 mips_gprmask
|= 1 << SP
;
2296 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2297 mips_gprmask
|= 1 << RA
;
2298 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2299 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2300 if (pinfo
& MIPS16_INSN_READ_Z
)
2301 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2302 & MIPS16OP_MASK_MOVE32Z
);
2303 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2304 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2305 & MIPS16OP_MASK_REGR32
);
2308 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2310 /* Filling the branch delay slot is more complex. We try to
2311 switch the branch with the previous instruction, which we can
2312 do if the previous instruction does not set up a condition
2313 that the branch tests and if the branch is not itself the
2314 target of any branch. */
2315 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2316 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2318 if (mips_optimize
< 2
2319 /* If we have seen .set volatile or .set nomove, don't
2321 || mips_opts
.nomove
!= 0
2322 /* If we had to emit any NOP instructions, then we
2323 already know we can not swap. */
2325 /* If we don't even know the previous insn, we can not
2327 || ! prev_insn_valid
2328 /* If the previous insn is already in a branch delay
2329 slot, then we can not swap. */
2330 || prev_insn_is_delay_slot
2331 /* If the previous previous insn was in a .set
2332 noreorder, we can't swap. Actually, the MIPS
2333 assembler will swap in this situation. However, gcc
2334 configured -with-gnu-as will generate code like
2340 in which we can not swap the bne and INSN. If gcc is
2341 not configured -with-gnu-as, it does not output the
2342 .set pseudo-ops. We don't have to check
2343 prev_insn_unreordered, because prev_insn_valid will
2344 be 0 in that case. We don't want to use
2345 prev_prev_insn_valid, because we do want to be able
2346 to swap at the start of a function. */
2347 || prev_prev_insn_unreordered
2348 /* If the branch is itself the target of a branch, we
2349 can not swap. We cheat on this; all we check for is
2350 whether there is a label on this instruction. If
2351 there are any branches to anything other than a
2352 label, users must use .set noreorder. */
2353 || insn_labels
!= NULL
2354 /* If the previous instruction is in a variant frag
2355 other than this branch's one, we cannot do the swap.
2356 This does not apply to the mips16, which uses variant
2357 frags for different purposes. */
2358 || (! mips_opts
.mips16
2359 && prev_insn_frag_type
== rs_machine_dependent
)
2360 /* If the branch reads the condition codes, we don't
2361 even try to swap, because in the sequence
2366 we can not swap, and I don't feel like handling that
2368 || (! mips_opts
.mips16
2369 && (pinfo
& INSN_READ_COND_CODE
)
2370 && ! cop_interlocks
)
2371 /* We can not swap with an instruction that requires a
2372 delay slot, because the target of the branch might
2373 interfere with that instruction. */
2374 || (! mips_opts
.mips16
2376 /* Itbl support may require additional care here. */
2377 & (INSN_LOAD_COPROC_DELAY
2378 | INSN_COPROC_MOVE_DELAY
2379 | INSN_WRITE_COND_CODE
))
2380 && ! cop_interlocks
)
2381 || (! (hilo_interlocks
2382 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2386 || (! mips_opts
.mips16
2387 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2388 && ! gpr_interlocks
)
2389 || (! mips_opts
.mips16
2390 /* Itbl support may require additional care here. */
2391 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2392 && ! cop_mem_interlocks
)
2393 /* We can not swap with a branch instruction. */
2395 & (INSN_UNCOND_BRANCH_DELAY
2396 | INSN_COND_BRANCH_DELAY
2397 | INSN_COND_BRANCH_LIKELY
))
2398 /* We do not swap with a trap instruction, since it
2399 complicates trap handlers to have the trap
2400 instruction be in a delay slot. */
2401 || (prev_pinfo
& INSN_TRAP
)
2402 /* If the branch reads a register that the previous
2403 instruction sets, we can not swap. */
2404 || (! mips_opts
.mips16
2405 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2406 && insn_uses_reg (ip
,
2407 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2410 || (! mips_opts
.mips16
2411 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2412 && insn_uses_reg (ip
,
2413 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2416 || (mips_opts
.mips16
2417 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2418 && insn_uses_reg (ip
,
2419 ((prev_insn
.insn_opcode
2421 & MIPS16OP_MASK_RX
),
2423 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2424 && insn_uses_reg (ip
,
2425 ((prev_insn
.insn_opcode
2427 & MIPS16OP_MASK_RY
),
2429 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2430 && insn_uses_reg (ip
,
2431 ((prev_insn
.insn_opcode
2433 & MIPS16OP_MASK_RZ
),
2435 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2436 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2437 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2438 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2439 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2440 && insn_uses_reg (ip
,
2441 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2444 /* If the branch writes a register that the previous
2445 instruction sets, we can not swap (we know that
2446 branches write only to RD or to $31). */
2447 || (! mips_opts
.mips16
2448 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2449 && (((pinfo
& INSN_WRITE_GPR_D
)
2450 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2451 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2452 || ((pinfo
& INSN_WRITE_GPR_31
)
2453 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2456 || (! mips_opts
.mips16
2457 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2458 && (((pinfo
& INSN_WRITE_GPR_D
)
2459 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2460 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2461 || ((pinfo
& INSN_WRITE_GPR_31
)
2462 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2465 || (mips_opts
.mips16
2466 && (pinfo
& MIPS16_INSN_WRITE_31
)
2467 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2468 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2469 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2471 /* If the branch writes a register that the previous
2472 instruction reads, we can not swap (we know that
2473 branches only write to RD or to $31). */
2474 || (! mips_opts
.mips16
2475 && (pinfo
& INSN_WRITE_GPR_D
)
2476 && insn_uses_reg (&prev_insn
,
2477 ((ip
->insn_opcode
>> OP_SH_RD
)
2480 || (! mips_opts
.mips16
2481 && (pinfo
& INSN_WRITE_GPR_31
)
2482 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2483 || (mips_opts
.mips16
2484 && (pinfo
& MIPS16_INSN_WRITE_31
)
2485 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2486 /* If we are generating embedded PIC code, the branch
2487 might be expanded into a sequence which uses $at, so
2488 we can't swap with an instruction which reads it. */
2489 || (mips_pic
== EMBEDDED_PIC
2490 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2491 /* If the previous previous instruction has a load
2492 delay, and sets a register that the branch reads, we
2494 || (! mips_opts
.mips16
2495 /* Itbl support may require additional care here. */
2496 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2497 && ! cop_interlocks
)
2498 || ((prev_prev_insn
.insn_mo
->pinfo
2499 & INSN_LOAD_MEMORY_DELAY
)
2500 && ! gpr_interlocks
))
2501 && insn_uses_reg (ip
,
2502 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2505 /* If one instruction sets a condition code and the
2506 other one uses a condition code, we can not swap. */
2507 || ((pinfo
& INSN_READ_COND_CODE
)
2508 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2509 || ((pinfo
& INSN_WRITE_COND_CODE
)
2510 && (prev_pinfo
& INSN_READ_COND_CODE
))
2511 /* If the previous instruction uses the PC, we can not
2513 || (mips_opts
.mips16
2514 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2515 /* If the previous instruction was extended, we can not
2517 || (mips_opts
.mips16
&& prev_insn_extended
)
2518 /* If the previous instruction had a fixup in mips16
2519 mode, we can not swap. This normally means that the
2520 previous instruction was a 4 byte branch anyhow. */
2521 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2522 /* If the previous instruction is a sync, sync.l, or
2523 sync.p, we can not swap. */
2524 || (prev_pinfo
& INSN_SYNC
))
2526 /* We could do even better for unconditional branches to
2527 portions of this object file; we could pick up the
2528 instruction at the destination, put it in the delay
2529 slot, and bump the destination address. */
2531 /* Update the previous insn information. */
2532 prev_prev_insn
= *ip
;
2533 prev_insn
.insn_mo
= &dummy_opcode
;
2537 /* It looks like we can actually do the swap. */
2538 if (! mips_opts
.mips16
)
2543 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2544 if (!relaxed_branch
)
2546 /* If this is not a relaxed branch, then just
2547 swap the instructions. */
2548 memcpy (temp
, prev_f
, 4);
2549 memcpy (prev_f
, f
, 4);
2550 memcpy (f
, temp
, 4);
2554 /* If this is a relaxed branch, then we move the
2555 instruction to be placed in the delay slot to
2556 the current frag, shrinking the fixed part of
2557 the originating frag. If the branch occupies
2558 the tail of the latter, we move it backwards,
2559 into the space freed by the moved instruction. */
2561 memcpy (f
, prev_f
, 4);
2562 prev_insn_frag
->fr_fix
-= 4;
2563 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2564 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2567 if (prev_insn_fixp
[0])
2569 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2570 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2572 if (prev_insn_fixp
[1])
2574 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2575 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2577 if (prev_insn_fixp
[2])
2579 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2580 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2582 if (prev_insn_fixp
[0] && HAVE_NEWABI
2583 && prev_insn_frag
!= frag_now
2584 && (prev_insn_fixp
[0]->fx_r_type
2585 == BFD_RELOC_MIPS_GOT_DISP
2586 || (prev_insn_fixp
[0]->fx_r_type
2587 == BFD_RELOC_MIPS_CALL16
)))
2589 /* To avoid confusion in tc_gen_reloc, we must
2590 ensure that this does not become a variant
2592 force_new_frag
= TRUE
;
2595 if (!relaxed_branch
)
2599 fixp
[0]->fx_frag
= prev_insn_frag
;
2600 fixp
[0]->fx_where
= prev_insn_where
;
2604 fixp
[1]->fx_frag
= prev_insn_frag
;
2605 fixp
[1]->fx_where
= prev_insn_where
;
2609 fixp
[2]->fx_frag
= prev_insn_frag
;
2610 fixp
[2]->fx_where
= prev_insn_where
;
2613 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2616 fixp
[0]->fx_where
-= 4;
2618 fixp
[1]->fx_where
-= 4;
2620 fixp
[2]->fx_where
-= 4;
2628 assert (prev_insn_fixp
[0] == NULL
);
2629 assert (prev_insn_fixp
[1] == NULL
);
2630 assert (prev_insn_fixp
[2] == NULL
);
2631 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2632 memcpy (temp
, prev_f
, 2);
2633 memcpy (prev_f
, f
, 2);
2634 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2636 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2637 memcpy (f
, temp
, 2);
2641 memcpy (f
, f
+ 2, 2);
2642 memcpy (f
+ 2, temp
, 2);
2646 fixp
[0]->fx_frag
= prev_insn_frag
;
2647 fixp
[0]->fx_where
= prev_insn_where
;
2651 fixp
[1]->fx_frag
= prev_insn_frag
;
2652 fixp
[1]->fx_where
= prev_insn_where
;
2656 fixp
[2]->fx_frag
= prev_insn_frag
;
2657 fixp
[2]->fx_where
= prev_insn_where
;
2661 /* Update the previous insn information; leave prev_insn
2663 prev_prev_insn
= *ip
;
2665 prev_insn_is_delay_slot
= 1;
2667 /* If that was an unconditional branch, forget the previous
2668 insn information. */
2669 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2671 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2672 prev_insn
.insn_mo
= &dummy_opcode
;
2675 prev_insn_fixp
[0] = NULL
;
2676 prev_insn_fixp
[1] = NULL
;
2677 prev_insn_fixp
[2] = NULL
;
2678 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2679 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2680 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2681 prev_insn_extended
= 0;
2683 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2685 /* We don't yet optimize a branch likely. What we should do
2686 is look at the target, copy the instruction found there
2687 into the delay slot, and increment the branch to jump to
2688 the next instruction. */
2690 /* Update the previous insn information. */
2691 prev_prev_insn
= *ip
;
2692 prev_insn
.insn_mo
= &dummy_opcode
;
2693 prev_insn_fixp
[0] = NULL
;
2694 prev_insn_fixp
[1] = NULL
;
2695 prev_insn_fixp
[2] = NULL
;
2696 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2697 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2698 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2699 prev_insn_extended
= 0;
2703 /* Update the previous insn information. */
2705 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2707 prev_prev_insn
= prev_insn
;
2710 /* Any time we see a branch, we always fill the delay slot
2711 immediately; since this insn is not a branch, we know it
2712 is not in a delay slot. */
2713 prev_insn_is_delay_slot
= 0;
2715 prev_insn_fixp
[0] = fixp
[0];
2716 prev_insn_fixp
[1] = fixp
[1];
2717 prev_insn_fixp
[2] = fixp
[2];
2718 prev_insn_reloc_type
[0] = reloc_type
[0];
2719 prev_insn_reloc_type
[1] = reloc_type
[1];
2720 prev_insn_reloc_type
[2] = reloc_type
[2];
2721 if (mips_opts
.mips16
)
2722 prev_insn_extended
= (ip
->use_extend
2723 || *reloc_type
> BFD_RELOC_UNUSED
);
2726 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2727 prev_insn_unreordered
= 0;
2728 prev_insn_frag
= frag_now
;
2729 prev_insn_where
= f
- frag_now
->fr_literal
;
2730 prev_insn_valid
= 1;
2732 else if (mips_relax
.sequence
!= 2)
2734 /* We need to record a bit of information even when we are not
2735 reordering, in order to determine the base address for mips16
2736 PC relative relocs. */
2737 prev_prev_insn
= prev_insn
;
2739 prev_insn_reloc_type
[0] = reloc_type
[0];
2740 prev_insn_reloc_type
[1] = reloc_type
[1];
2741 prev_insn_reloc_type
[2] = reloc_type
[2];
2742 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2743 prev_insn_unreordered
= 1;
2746 /* We just output an insn, so the next one doesn't have a label. */
2747 mips_clear_insn_labels ();
2750 /* This function forgets that there was any previous instruction or
2751 label. If PRESERVE is non-zero, it remembers enough information to
2752 know whether nops are needed before a noreorder section. */
2755 mips_no_prev_insn (int preserve
)
2759 prev_insn
.insn_mo
= &dummy_opcode
;
2760 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2761 prev_nop_frag
= NULL
;
2762 prev_nop_frag_holds
= 0;
2763 prev_nop_frag_required
= 0;
2764 prev_nop_frag_since
= 0;
2766 prev_insn_valid
= 0;
2767 prev_insn_is_delay_slot
= 0;
2768 prev_insn_unreordered
= 0;
2769 prev_insn_extended
= 0;
2770 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2771 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2772 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2773 prev_prev_insn_unreordered
= 0;
2774 mips_clear_insn_labels ();
2777 /* This function must be called whenever we turn on noreorder or emit
2778 something other than instructions. It inserts any NOPS which might
2779 be needed by the previous instruction, and clears the information
2780 kept for the previous instructions. The INSNS parameter is true if
2781 instructions are to follow. */
2784 mips_emit_delays (bfd_boolean insns
)
2786 if (! mips_opts
.noreorder
)
2791 if ((! mips_opts
.mips16
2792 && ((prev_insn
.insn_mo
->pinfo
2793 & (INSN_LOAD_COPROC_DELAY
2794 | INSN_COPROC_MOVE_DELAY
2795 | INSN_WRITE_COND_CODE
))
2796 && ! cop_interlocks
))
2797 || (! hilo_interlocks
2798 && (prev_insn
.insn_mo
->pinfo
2801 || (! mips_opts
.mips16
2802 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2803 && ! gpr_interlocks
)
2804 || (! mips_opts
.mips16
2805 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2806 && ! cop_mem_interlocks
))
2808 /* Itbl support may require additional care here. */
2810 if ((! mips_opts
.mips16
2811 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2812 && ! cop_interlocks
))
2813 || (! hilo_interlocks
2814 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2815 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2818 if (prev_insn_unreordered
)
2821 else if ((! mips_opts
.mips16
2822 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2823 && ! cop_interlocks
))
2824 || (! hilo_interlocks
2825 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2826 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2828 /* Itbl support may require additional care here. */
2829 if (! prev_prev_insn_unreordered
)
2833 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2836 const char *pn
= prev_insn
.insn_mo
->name
;
2837 if (strncmp(pn
, "macc", 4) == 0
2838 || strncmp(pn
, "dmacc", 5) == 0
2839 || strncmp(pn
, "dmult", 5) == 0)
2843 if (nops
< min_nops
)
2849 struct insn_label_list
*l
;
2853 /* Record the frag which holds the nop instructions, so
2854 that we can remove them if we don't need them. */
2855 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2856 prev_nop_frag
= frag_now
;
2857 prev_nop_frag_holds
= nops
;
2858 prev_nop_frag_required
= 0;
2859 prev_nop_frag_since
= 0;
2862 for (; nops
> 0; --nops
)
2867 /* Move on to a new frag, so that it is safe to simply
2868 decrease the size of prev_nop_frag. */
2869 frag_wane (frag_now
);
2873 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2877 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2878 symbol_set_frag (l
->label
, frag_now
);
2879 val
= (valueT
) frag_now_fix ();
2880 /* mips16 text labels are stored as odd. */
2881 if (mips_opts
.mips16
)
2883 S_SET_VALUE (l
->label
, val
);
2888 /* Mark instruction labels in mips16 mode. */
2890 mips16_mark_labels ();
2892 mips_no_prev_insn (insns
);
2895 /* Set up global variables for the start of a new macro. */
2900 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2901 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2902 && (prev_insn
.insn_mo
->pinfo
2903 & (INSN_UNCOND_BRANCH_DELAY
2904 | INSN_COND_BRANCH_DELAY
2905 | INSN_COND_BRANCH_LIKELY
)) != 0);
2908 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2909 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2910 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2913 macro_warning (relax_substateT subtype
)
2915 if (subtype
& RELAX_DELAY_SLOT
)
2916 return _("Macro instruction expanded into multiple instructions"
2917 " in a branch delay slot");
2918 else if (subtype
& RELAX_NOMACRO
)
2919 return _("Macro instruction expanded into multiple instructions");
2924 /* Finish up a macro. Emit warnings as appropriate. */
2929 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2931 relax_substateT subtype
;
2933 /* Set up the relaxation warning flags. */
2935 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2936 subtype
|= RELAX_SECOND_LONGER
;
2937 if (mips_opts
.warn_about_macros
)
2938 subtype
|= RELAX_NOMACRO
;
2939 if (mips_macro_warning
.delay_slot_p
)
2940 subtype
|= RELAX_DELAY_SLOT
;
2942 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2944 /* Either the macro has a single implementation or both
2945 implementations are longer than 4 bytes. Emit the
2947 const char *msg
= macro_warning (subtype
);
2953 /* One implementation might need a warning but the other
2954 definitely doesn't. */
2955 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2960 /* Build an instruction created by a macro expansion. This is passed
2961 a pointer to the count of instructions created so far, an
2962 expression, the name of the instruction to build, an operand format
2963 string, and corresponding arguments. */
2966 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2968 struct mips_cl_insn insn
;
2969 bfd_reloc_code_real_type r
[3];
2972 va_start (args
, fmt
);
2974 if (mips_opts
.mips16
)
2976 mips16_macro_build (ep
, name
, fmt
, args
);
2981 r
[0] = BFD_RELOC_UNUSED
;
2982 r
[1] = BFD_RELOC_UNUSED
;
2983 r
[2] = BFD_RELOC_UNUSED
;
2984 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2985 assert (insn
.insn_mo
);
2986 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2988 /* Search until we get a match for NAME. */
2991 /* It is assumed here that macros will never generate
2992 MDMX or MIPS-3D instructions. */
2993 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2994 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2995 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2997 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2999 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3003 assert (insn
.insn_mo
->name
);
3004 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3007 insn
.insn_opcode
= insn
.insn_mo
->match
;
3025 insn
.insn_opcode
|= (va_arg (args
, int)
3026 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3031 /* Note that in the macro case, these arguments are already
3032 in MSB form. (When handling the instruction in the
3033 non-macro case, these arguments are sizes from which
3034 MSB values must be calculated.) */
3035 insn
.insn_opcode
|= (va_arg (args
, int)
3036 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3042 /* Note that in the macro case, these arguments are already
3043 in MSBD form. (When handling the instruction in the
3044 non-macro case, these arguments are sizes from which
3045 MSBD values must be calculated.) */
3046 insn
.insn_opcode
|= (va_arg (args
, int)
3047 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3058 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3062 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3067 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3073 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3078 int tmp
= va_arg (args
, int);
3080 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3081 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3087 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3094 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3098 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3102 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3106 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3110 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3117 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3123 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3124 assert (*r
== BFD_RELOC_GPREL16
3125 || *r
== BFD_RELOC_MIPS_LITERAL
3126 || *r
== BFD_RELOC_MIPS_HIGHER
3127 || *r
== BFD_RELOC_HI16_S
3128 || *r
== BFD_RELOC_LO16
3129 || *r
== BFD_RELOC_MIPS_GOT16
3130 || *r
== BFD_RELOC_MIPS_CALL16
3131 || *r
== BFD_RELOC_MIPS_GOT_DISP
3132 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3133 || *r
== BFD_RELOC_MIPS_GOT_OFST
3134 || *r
== BFD_RELOC_MIPS_GOT_LO16
3135 || *r
== BFD_RELOC_MIPS_CALL_LO16
3136 || (ep
->X_op
== O_subtract
3137 && *r
== BFD_RELOC_PCREL_LO16
));
3141 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3143 && (ep
->X_op
== O_constant
3144 || (ep
->X_op
== O_symbol
3145 && (*r
== BFD_RELOC_MIPS_HIGHEST
3146 || *r
== BFD_RELOC_HI16_S
3147 || *r
== BFD_RELOC_HI16
3148 || *r
== BFD_RELOC_GPREL16
3149 || *r
== BFD_RELOC_MIPS_GOT_HI16
3150 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3151 || (ep
->X_op
== O_subtract
3152 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3156 assert (ep
!= NULL
);
3158 * This allows macro() to pass an immediate expression for
3159 * creating short branches without creating a symbol.
3160 * Note that the expression still might come from the assembly
3161 * input, in which case the value is not checked for range nor
3162 * is a relocation entry generated (yuck).
3164 if (ep
->X_op
== O_constant
)
3166 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3170 *r
= BFD_RELOC_16_PCREL_S2
;
3174 assert (ep
!= NULL
);
3175 *r
= BFD_RELOC_MIPS_JMP
;
3179 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3188 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3190 append_insn (&insn
, ep
, r
);
3194 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3197 struct mips_cl_insn insn
;
3198 bfd_reloc_code_real_type r
[3]
3199 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3201 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3202 assert (insn
.insn_mo
);
3203 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3205 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3206 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3209 assert (insn
.insn_mo
->name
);
3210 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3213 insn
.insn_opcode
= insn
.insn_mo
->match
;
3214 insn
.use_extend
= FALSE
;
3233 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3238 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3242 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3246 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3256 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3263 regno
= va_arg (args
, int);
3264 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3265 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3286 assert (ep
!= NULL
);
3288 if (ep
->X_op
!= O_constant
)
3289 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3292 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3293 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3296 *r
= BFD_RELOC_UNUSED
;
3302 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3309 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3311 append_insn (&insn
, ep
, r
);
3315 * Generate a "jalr" instruction with a relocation hint to the called
3316 * function. This occurs in NewABI PIC code.
3319 macro_build_jalr (expressionS
*ep
)
3328 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3330 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3331 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3335 * Generate a "lui" instruction.
3338 macro_build_lui (expressionS
*ep
, int regnum
)
3340 expressionS high_expr
;
3341 struct mips_cl_insn insn
;
3342 bfd_reloc_code_real_type r
[3]
3343 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3344 const char *name
= "lui";
3345 const char *fmt
= "t,u";
3347 assert (! mips_opts
.mips16
);
3351 if (high_expr
.X_op
== O_constant
)
3353 /* we can compute the instruction now without a relocation entry */
3354 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3356 *r
= BFD_RELOC_UNUSED
;
3360 assert (ep
->X_op
== O_symbol
);
3361 /* _gp_disp is a special case, used from s_cpload. */
3362 assert (mips_pic
== NO_PIC
3364 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3365 *r
= BFD_RELOC_HI16_S
;
3368 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3369 assert (insn
.insn_mo
);
3370 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3371 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3373 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3374 if (*r
== BFD_RELOC_UNUSED
)
3376 insn
.insn_opcode
|= high_expr
.X_add_number
;
3377 append_insn (&insn
, NULL
, r
);
3380 append_insn (&insn
, &high_expr
, r
);
3383 /* Generate a sequence of instructions to do a load or store from a constant
3384 offset off of a base register (breg) into/from a target register (treg),
3385 using AT if necessary. */
3387 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3388 int treg
, int breg
, int dbl
)
3390 assert (ep
->X_op
== O_constant
);
3392 /* Sign-extending 32-bit constants makes their handling easier. */
3393 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3394 == ~((bfd_vma
) 0x7fffffff)))
3396 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3397 as_bad (_("constant too large"));
3399 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3403 /* Right now, this routine can only handle signed 32-bit constants. */
3404 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3405 as_warn (_("operand overflow"));
3407 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3409 /* Signed 16-bit offset will fit in the op. Easy! */
3410 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3414 /* 32-bit offset, need multiple instructions and AT, like:
3415 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3416 addu $tempreg,$tempreg,$breg
3417 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3418 to handle the complete offset. */
3419 macro_build_lui (ep
, AT
);
3420 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3421 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3424 as_warn (_("Macro used $at after \".set noat\""));
3429 * Generates code to set the $at register to true (one)
3430 * if reg is less than the immediate expression.
3433 set_at (int reg
, int unsignedp
)
3435 if (imm_expr
.X_op
== O_constant
3436 && imm_expr
.X_add_number
>= -0x8000
3437 && imm_expr
.X_add_number
< 0x8000)
3438 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3439 AT
, reg
, BFD_RELOC_LO16
);
3442 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3443 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3448 normalize_constant_expr (expressionS
*ex
)
3450 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3451 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3455 /* Warn if an expression is not a constant. */
3458 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3460 if (ex
->X_op
== O_big
)
3461 as_bad (_("unsupported large constant"));
3462 else if (ex
->X_op
!= O_constant
)
3463 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3465 normalize_constant_expr (ex
);
3468 /* Count the leading zeroes by performing a binary chop. This is a
3469 bulky bit of source, but performance is a LOT better for the
3470 majority of values than a simple loop to count the bits:
3471 for (lcnt = 0; (lcnt < 32); lcnt++)
3472 if ((v) & (1 << (31 - lcnt)))
3474 However it is not code size friendly, and the gain will drop a bit
3475 on certain cached systems.
3477 #define COUNT_TOP_ZEROES(v) \
3478 (((v) & ~0xffff) == 0 \
3479 ? ((v) & ~0xff) == 0 \
3480 ? ((v) & ~0xf) == 0 \
3481 ? ((v) & ~0x3) == 0 \
3482 ? ((v) & ~0x1) == 0 \
3487 : ((v) & ~0x7) == 0 \
3490 : ((v) & ~0x3f) == 0 \
3491 ? ((v) & ~0x1f) == 0 \
3494 : ((v) & ~0x7f) == 0 \
3497 : ((v) & ~0xfff) == 0 \
3498 ? ((v) & ~0x3ff) == 0 \
3499 ? ((v) & ~0x1ff) == 0 \
3502 : ((v) & ~0x7ff) == 0 \
3505 : ((v) & ~0x3fff) == 0 \
3506 ? ((v) & ~0x1fff) == 0 \
3509 : ((v) & ~0x7fff) == 0 \
3512 : ((v) & ~0xffffff) == 0 \
3513 ? ((v) & ~0xfffff) == 0 \
3514 ? ((v) & ~0x3ffff) == 0 \
3515 ? ((v) & ~0x1ffff) == 0 \
3518 : ((v) & ~0x7ffff) == 0 \
3521 : ((v) & ~0x3fffff) == 0 \
3522 ? ((v) & ~0x1fffff) == 0 \
3525 : ((v) & ~0x7fffff) == 0 \
3528 : ((v) & ~0xfffffff) == 0 \
3529 ? ((v) & ~0x3ffffff) == 0 \
3530 ? ((v) & ~0x1ffffff) == 0 \
3533 : ((v) & ~0x7ffffff) == 0 \
3536 : ((v) & ~0x3fffffff) == 0 \
3537 ? ((v) & ~0x1fffffff) == 0 \
3540 : ((v) & ~0x7fffffff) == 0 \
3545 * This routine generates the least number of instructions necessary to load
3546 * an absolute expression value into a register.
3549 load_register (int reg
, expressionS
*ep
, int dbl
)
3552 expressionS hi32
, lo32
;
3554 if (ep
->X_op
!= O_big
)
3556 assert (ep
->X_op
== O_constant
);
3558 /* Sign-extending 32-bit constants makes their handling easier. */
3559 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3560 == ~((bfd_vma
) 0x7fffffff)))
3562 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3563 as_bad (_("constant too large"));
3565 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3569 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3571 /* We can handle 16 bit signed values with an addiu to
3572 $zero. No need to ever use daddiu here, since $zero and
3573 the result are always correct in 32 bit mode. */
3574 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3577 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3579 /* We can handle 16 bit unsigned values with an ori to
3581 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3584 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3586 /* 32 bit values require an lui. */
3587 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3588 if ((ep
->X_add_number
& 0xffff) != 0)
3589 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3594 /* The value is larger than 32 bits. */
3596 if (HAVE_32BIT_GPRS
)
3598 as_bad (_("Number (0x%lx) larger than 32 bits"),
3599 (unsigned long) ep
->X_add_number
);
3600 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3604 if (ep
->X_op
!= O_big
)
3607 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3608 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3609 hi32
.X_add_number
&= 0xffffffff;
3611 lo32
.X_add_number
&= 0xffffffff;
3615 assert (ep
->X_add_number
> 2);
3616 if (ep
->X_add_number
== 3)
3617 generic_bignum
[3] = 0;
3618 else if (ep
->X_add_number
> 4)
3619 as_bad (_("Number larger than 64 bits"));
3620 lo32
.X_op
= O_constant
;
3621 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3622 hi32
.X_op
= O_constant
;
3623 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3626 if (hi32
.X_add_number
== 0)
3631 unsigned long hi
, lo
;
3633 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3635 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3637 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3640 if (lo32
.X_add_number
& 0x80000000)
3642 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3643 if (lo32
.X_add_number
& 0xffff)
3644 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3649 /* Check for 16bit shifted constant. We know that hi32 is
3650 non-zero, so start the mask on the first bit of the hi32
3655 unsigned long himask
, lomask
;
3659 himask
= 0xffff >> (32 - shift
);
3660 lomask
= (0xffff << shift
) & 0xffffffff;
3664 himask
= 0xffff << (shift
- 32);
3667 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3668 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3672 tmp
.X_op
= O_constant
;
3674 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3675 | (lo32
.X_add_number
>> shift
));
3677 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3678 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3679 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3680 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3685 while (shift
<= (64 - 16));
3687 /* Find the bit number of the lowest one bit, and store the
3688 shifted value in hi/lo. */
3689 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3690 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3694 while ((lo
& 1) == 0)
3699 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3705 while ((hi
& 1) == 0)
3714 /* Optimize if the shifted value is a (power of 2) - 1. */
3715 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3716 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3718 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3723 /* This instruction will set the register to be all
3725 tmp
.X_op
= O_constant
;
3726 tmp
.X_add_number
= (offsetT
) -1;
3727 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3731 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3732 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3734 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3735 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3740 /* Sign extend hi32 before calling load_register, because we can
3741 generally get better code when we load a sign extended value. */
3742 if ((hi32
.X_add_number
& 0x80000000) != 0)
3743 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3744 load_register (reg
, &hi32
, 0);
3747 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3751 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3759 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3761 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3762 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3768 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3772 mid16
.X_add_number
>>= 16;
3773 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3774 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3777 if ((lo32
.X_add_number
& 0xffff) != 0)
3778 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3782 load_delay_nop (void)
3784 if (!gpr_interlocks
)
3785 macro_build (NULL
, "nop", "");
3788 /* Load an address into a register. */
3791 load_address (int reg
, expressionS
*ep
, int *used_at
)
3793 if (ep
->X_op
!= O_constant
3794 && ep
->X_op
!= O_symbol
)
3796 as_bad (_("expression too complex"));
3797 ep
->X_op
= O_constant
;
3800 if (ep
->X_op
== O_constant
)
3802 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3806 if (mips_pic
== NO_PIC
)
3808 /* If this is a reference to a GP relative symbol, we want
3809 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3811 lui $reg,<sym> (BFD_RELOC_HI16_S)
3812 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3813 If we have an addend, we always use the latter form.
3815 With 64bit address space and a usable $at we want
3816 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3817 lui $at,<sym> (BFD_RELOC_HI16_S)
3818 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3819 daddiu $at,<sym> (BFD_RELOC_LO16)
3823 If $at is already in use, we use a path which is suboptimal
3824 on superscalar processors.
3825 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3826 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3828 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3830 daddiu $reg,<sym> (BFD_RELOC_LO16)
3832 if (HAVE_64BIT_ADDRESSES
)
3834 /* ??? We don't provide a GP-relative alternative for these macros.
3835 It used not to be possible with the original relaxation code,
3836 but it could be done now. */
3838 if (*used_at
== 0 && ! mips_opts
.noat
)
3840 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3841 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3842 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3843 BFD_RELOC_MIPS_HIGHER
);
3844 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3845 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3846 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3851 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3852 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3853 BFD_RELOC_MIPS_HIGHER
);
3854 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3855 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3856 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3857 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3862 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3863 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3865 relax_start (ep
->X_add_symbol
);
3866 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3867 mips_gp_register
, BFD_RELOC_GPREL16
);
3870 macro_build_lui (ep
, reg
);
3871 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3872 reg
, reg
, BFD_RELOC_LO16
);
3873 if (mips_relax
.sequence
)
3877 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3881 /* If this is a reference to an external symbol, we want
3882 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3884 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3886 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3887 If there is a constant, it must be added in after.
3889 If we have NewABI, we want
3890 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3891 unless we're referencing a global symbol with a non-zero
3892 offset, in which case cst must be added separately. */
3895 if (ep
->X_add_number
)
3897 ex
.X_add_number
= ep
->X_add_number
;
3898 ep
->X_add_number
= 0;
3899 relax_start (ep
->X_add_symbol
);
3900 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3901 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3902 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3903 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3904 ex
.X_op
= O_constant
;
3905 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3906 reg
, reg
, BFD_RELOC_LO16
);
3907 ep
->X_add_number
= ex
.X_add_number
;
3910 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3911 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3912 if (mips_relax
.sequence
)
3917 ex
.X_add_number
= ep
->X_add_number
;
3918 ep
->X_add_number
= 0;
3919 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3920 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3922 relax_start (ep
->X_add_symbol
);
3924 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3928 if (ex
.X_add_number
!= 0)
3930 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3931 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3932 ex
.X_op
= O_constant
;
3933 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3934 reg
, reg
, BFD_RELOC_LO16
);
3938 else if (mips_pic
== SVR4_PIC
)
3942 /* This is the large GOT case. If this is a reference to an
3943 external symbol, we want
3944 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3946 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3948 Otherwise, for a reference to a local symbol in old ABI, we want
3949 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3951 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3952 If there is a constant, it must be added in after.
3954 In the NewABI, for local symbols, with or without offsets, we want:
3955 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3956 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3960 ex
.X_add_number
= ep
->X_add_number
;
3961 ep
->X_add_number
= 0;
3962 relax_start (ep
->X_add_symbol
);
3963 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3964 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3965 reg
, reg
, mips_gp_register
);
3966 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3967 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3968 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3969 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3970 else if (ex
.X_add_number
)
3972 ex
.X_op
= O_constant
;
3973 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3977 ep
->X_add_number
= ex
.X_add_number
;
3979 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3980 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3981 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3982 BFD_RELOC_MIPS_GOT_OFST
);
3987 ex
.X_add_number
= ep
->X_add_number
;
3988 ep
->X_add_number
= 0;
3989 relax_start (ep
->X_add_symbol
);
3990 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3991 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3992 reg
, reg
, mips_gp_register
);
3993 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3994 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3996 if (reg_needs_delay (mips_gp_register
))
3998 /* We need a nop before loading from $gp. This special
3999 check is required because the lui which starts the main
4000 instruction stream does not refer to $gp, and so will not
4001 insert the nop which may be required. */
4002 macro_build (NULL
, "nop", "");
4004 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4005 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4007 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4011 if (ex
.X_add_number
!= 0)
4013 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4014 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4015 ex
.X_op
= O_constant
;
4016 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4021 else if (mips_pic
== EMBEDDED_PIC
)
4024 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4026 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4027 reg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4033 /* Move the contents of register SOURCE into register DEST. */
4036 move_register (int dest
, int source
)
4038 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4042 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4043 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4044 The two alternatives are:
4046 Global symbol Local sybmol
4047 ------------- ------------
4048 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4050 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4052 load_got_offset emits the first instruction and add_got_offset
4053 emits the second for a 16-bit offset or add_got_offset_hilo emits
4054 a sequence to add a 32-bit offset using a scratch register. */
4057 load_got_offset (int dest
, expressionS
*local
)
4062 global
.X_add_number
= 0;
4064 relax_start (local
->X_add_symbol
);
4065 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4066 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4068 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4069 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4074 add_got_offset (int dest
, expressionS
*local
)
4078 global
.X_op
= O_constant
;
4079 global
.X_op_symbol
= NULL
;
4080 global
.X_add_symbol
= NULL
;
4081 global
.X_add_number
= local
->X_add_number
;
4083 relax_start (local
->X_add_symbol
);
4084 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4085 dest
, dest
, BFD_RELOC_LO16
);
4087 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4092 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4095 int hold_mips_optimize
;
4097 global
.X_op
= O_constant
;
4098 global
.X_op_symbol
= NULL
;
4099 global
.X_add_symbol
= NULL
;
4100 global
.X_add_number
= local
->X_add_number
;
4102 relax_start (local
->X_add_symbol
);
4103 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4105 /* Set mips_optimize around the lui instruction to avoid
4106 inserting an unnecessary nop after the lw. */
4107 hold_mips_optimize
= mips_optimize
;
4109 macro_build_lui (&global
, tmp
);
4110 mips_optimize
= hold_mips_optimize
;
4111 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4114 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4119 * This routine implements the seemingly endless macro or synthesized
4120 * instructions and addressing modes in the mips assembly language. Many
4121 * of these macros are simple and are similar to each other. These could
4122 * probably be handled by some kind of table or grammar approach instead of
4123 * this verbose method. Others are not simple macros but are more like
4124 * optimizing code generation.
4125 * One interesting optimization is when several store macros appear
4126 * consecutively that would load AT with the upper half of the same address.
4127 * The ensuing load upper instructions are ommited. This implies some kind
4128 * of global optimization. We currently only optimize within a single macro.
4129 * For many of the load and store macros if the address is specified as a
4130 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4131 * first load register 'at' with zero and use it as the base register. The
4132 * mips assembler simply uses register $zero. Just one tiny optimization
4136 macro (struct mips_cl_insn
*ip
)
4138 register int treg
, sreg
, dreg
, breg
;
4154 bfd_reloc_code_real_type r
;
4155 int hold_mips_optimize
;
4157 assert (! mips_opts
.mips16
);
4159 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4160 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4161 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4162 mask
= ip
->insn_mo
->mask
;
4164 expr1
.X_op
= O_constant
;
4165 expr1
.X_op_symbol
= NULL
;
4166 expr1
.X_add_symbol
= NULL
;
4167 expr1
.X_add_number
= 1;
4179 mips_emit_delays (TRUE
);
4180 ++mips_opts
.noreorder
;
4181 mips_any_noreorder
= 1;
4183 expr1
.X_add_number
= 8;
4184 macro_build (&expr1
, "bgez", "s,p", sreg
);
4186 macro_build (NULL
, "nop", "", 0);
4188 move_register (dreg
, sreg
);
4189 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4191 --mips_opts
.noreorder
;
4212 if (imm_expr
.X_op
== O_constant
4213 && imm_expr
.X_add_number
>= -0x8000
4214 && imm_expr
.X_add_number
< 0x8000)
4216 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4219 load_register (AT
, &imm_expr
, dbl
);
4220 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4239 if (imm_expr
.X_op
== O_constant
4240 && imm_expr
.X_add_number
>= 0
4241 && imm_expr
.X_add_number
< 0x10000)
4243 if (mask
!= M_NOR_I
)
4244 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4247 macro_build (&imm_expr
, "ori", "t,r,i",
4248 treg
, sreg
, BFD_RELOC_LO16
);
4249 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4254 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4255 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4272 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4274 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4277 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4278 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4286 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4291 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4294 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4295 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4301 /* check for > max integer */
4302 maxnum
= 0x7fffffff;
4303 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4310 if (imm_expr
.X_op
== O_constant
4311 && imm_expr
.X_add_number
>= maxnum
4312 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4315 /* result is always false */
4317 macro_build (NULL
, "nop", "", 0);
4319 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4322 if (imm_expr
.X_op
!= O_constant
)
4323 as_bad (_("Unsupported large constant"));
4324 ++imm_expr
.X_add_number
;
4328 if (mask
== M_BGEL_I
)
4330 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4332 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4335 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4337 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4340 maxnum
= 0x7fffffff;
4341 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4348 maxnum
= - maxnum
- 1;
4349 if (imm_expr
.X_op
== O_constant
4350 && imm_expr
.X_add_number
<= maxnum
4351 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4354 /* result is always true */
4355 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4356 macro_build (&offset_expr
, "b", "p");
4360 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4370 macro_build (&offset_expr
, likely
? "beql" : "beq",
4374 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4375 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4383 && imm_expr
.X_op
== O_constant
4384 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4386 if (imm_expr
.X_op
!= O_constant
)
4387 as_bad (_("Unsupported large constant"));
4388 ++imm_expr
.X_add_number
;
4392 if (mask
== M_BGEUL_I
)
4394 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4396 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4398 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4403 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4411 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4416 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4419 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4420 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4428 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4434 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4435 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4443 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4448 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4451 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4452 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4458 maxnum
= 0x7fffffff;
4459 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4466 if (imm_expr
.X_op
== O_constant
4467 && imm_expr
.X_add_number
>= maxnum
4468 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4470 if (imm_expr
.X_op
!= O_constant
)
4471 as_bad (_("Unsupported large constant"));
4472 ++imm_expr
.X_add_number
;
4476 if (mask
== M_BLTL_I
)
4478 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4480 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4483 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4485 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4489 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4497 macro_build (&offset_expr
, likely
? "beql" : "beq",
4503 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4504 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4512 && imm_expr
.X_op
== O_constant
4513 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4515 if (imm_expr
.X_op
!= O_constant
)
4516 as_bad (_("Unsupported large constant"));
4517 ++imm_expr
.X_add_number
;
4521 if (mask
== M_BLTUL_I
)
4523 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4525 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4527 macro_build (&offset_expr
, likely
? "beql" : "beq",
4532 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4540 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4545 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4548 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4549 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4559 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4563 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4564 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4572 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4574 as_bad (_("Unsupported large constant"));
4579 pos
= (unsigned long) imm_expr
.X_add_number
;
4580 size
= (unsigned long) imm2_expr
.X_add_number
;
4585 as_bad (_("Improper position (%lu)"), pos
);
4588 if (size
== 0 || size
> 64
4589 || (pos
+ size
- 1) > 63)
4591 as_bad (_("Improper extract size (%lu, position %lu)"),
4596 if (size
<= 32 && pos
< 32)
4601 else if (size
<= 32)
4611 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4620 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4622 as_bad (_("Unsupported large constant"));
4627 pos
= (unsigned long) imm_expr
.X_add_number
;
4628 size
= (unsigned long) imm2_expr
.X_add_number
;
4633 as_bad (_("Improper position (%lu)"), pos
);
4636 if (size
== 0 || size
> 64
4637 || (pos
+ size
- 1) > 63)
4639 as_bad (_("Improper insert size (%lu, position %lu)"),
4644 if (pos
< 32 && (pos
+ size
- 1) < 32)
4659 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4676 as_warn (_("Divide by zero."));
4678 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4680 macro_build (NULL
, "break", "c", 7);
4684 mips_emit_delays (TRUE
);
4685 ++mips_opts
.noreorder
;
4686 mips_any_noreorder
= 1;
4689 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4690 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4694 expr1
.X_add_number
= 8;
4695 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4696 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4697 macro_build (NULL
, "break", "c", 7);
4699 expr1
.X_add_number
= -1;
4700 load_register (AT
, &expr1
, dbl
);
4701 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4702 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4705 expr1
.X_add_number
= 1;
4706 load_register (AT
, &expr1
, dbl
);
4707 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4711 expr1
.X_add_number
= 0x80000000;
4712 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4716 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4717 /* We want to close the noreorder block as soon as possible, so
4718 that later insns are available for delay slot filling. */
4719 --mips_opts
.noreorder
;
4723 expr1
.X_add_number
= 8;
4724 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4725 macro_build (NULL
, "nop", "", 0);
4727 /* We want to close the noreorder block as soon as possible, so
4728 that later insns are available for delay slot filling. */
4729 --mips_opts
.noreorder
;
4731 macro_build (NULL
, "break", "c", 6);
4733 macro_build (NULL
, s
, "d", dreg
);
4772 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4774 as_warn (_("Divide by zero."));
4776 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4778 macro_build (NULL
, "break", "c", 7);
4781 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4783 if (strcmp (s2
, "mflo") == 0)
4784 move_register (dreg
, sreg
);
4786 move_register (dreg
, 0);
4789 if (imm_expr
.X_op
== O_constant
4790 && imm_expr
.X_add_number
== -1
4791 && s
[strlen (s
) - 1] != 'u')
4793 if (strcmp (s2
, "mflo") == 0)
4795 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4798 move_register (dreg
, 0);
4802 load_register (AT
, &imm_expr
, dbl
);
4803 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4804 macro_build (NULL
, s2
, "d", dreg
);
4823 mips_emit_delays (TRUE
);
4824 ++mips_opts
.noreorder
;
4825 mips_any_noreorder
= 1;
4828 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4829 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4830 /* We want to close the noreorder block as soon as possible, so
4831 that later insns are available for delay slot filling. */
4832 --mips_opts
.noreorder
;
4836 expr1
.X_add_number
= 8;
4837 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4838 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4840 /* We want to close the noreorder block as soon as possible, so
4841 that later insns are available for delay slot filling. */
4842 --mips_opts
.noreorder
;
4843 macro_build (NULL
, "break", "c", 7);
4845 macro_build (NULL
, s2
, "d", dreg
);
4857 /* Load the address of a symbol into a register. If breg is not
4858 zero, we then add a base register to it. */
4860 if (dbl
&& HAVE_32BIT_GPRS
)
4861 as_warn (_("dla used to load 32-bit register"));
4863 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4864 as_warn (_("la used to load 64-bit address"));
4866 if (offset_expr
.X_op
== O_constant
4867 && offset_expr
.X_add_number
>= -0x8000
4868 && offset_expr
.X_add_number
< 0x8000)
4870 macro_build (&offset_expr
,
4871 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4872 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4887 /* When generating embedded PIC code, we permit expressions of
4890 la $treg,foo-bar($breg)
4891 where bar is an address in the current section. These are used
4892 when getting the addresses of functions. We don't permit
4893 X_add_number to be non-zero, because if the symbol is
4894 external the relaxing code needs to know that any addend is
4895 purely the offset to X_op_symbol. */
4896 if (mips_pic
== EMBEDDED_PIC
4897 && offset_expr
.X_op
== O_subtract
4898 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4899 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4900 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4902 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4905 && (offset_expr
.X_add_number
== 0
4906 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4912 macro_build (&offset_expr
, "lui", "t,u",
4913 tempreg
, BFD_RELOC_PCREL_HI16_S
);
4917 macro_build (&offset_expr
, "lui", "t,u",
4918 tempreg
, BFD_RELOC_PCREL_HI16_S
);
4920 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4921 "d,v,t", tempreg
, tempreg
, breg
);
4923 macro_build (&offset_expr
,
4924 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4925 "t,r,j", treg
, tempreg
, BFD_RELOC_PCREL_LO16
);
4931 if (offset_expr
.X_op
!= O_symbol
4932 && offset_expr
.X_op
!= O_constant
)
4934 as_bad (_("expression too complex"));
4935 offset_expr
.X_op
= O_constant
;
4938 if (offset_expr
.X_op
== O_constant
)
4939 load_register (tempreg
, &offset_expr
,
4940 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4941 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4942 : HAVE_64BIT_ADDRESSES
));
4943 else if (mips_pic
== NO_PIC
)
4945 /* If this is a reference to a GP relative symbol, we want
4946 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4948 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4949 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4950 If we have a constant, we need two instructions anyhow,
4951 so we may as well always use the latter form.
4953 With 64bit address space and a usable $at we want
4954 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4955 lui $at,<sym> (BFD_RELOC_HI16_S)
4956 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4957 daddiu $at,<sym> (BFD_RELOC_LO16)
4959 daddu $tempreg,$tempreg,$at
4961 If $at is already in use, we use a path which is suboptimal
4962 on superscalar processors.
4963 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4964 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4966 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4968 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4970 if (HAVE_64BIT_ADDRESSES
)
4972 /* ??? We don't provide a GP-relative alternative for
4973 these macros. It used not to be possible with the
4974 original relaxation code, but it could be done now. */
4976 if (used_at
== 0 && ! mips_opts
.noat
)
4978 macro_build (&offset_expr
, "lui", "t,u",
4979 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4980 macro_build (&offset_expr
, "lui", "t,u",
4981 AT
, BFD_RELOC_HI16_S
);
4982 macro_build (&offset_expr
, "daddiu", "t,r,j",
4983 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4984 macro_build (&offset_expr
, "daddiu", "t,r,j",
4985 AT
, AT
, BFD_RELOC_LO16
);
4986 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4987 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4992 macro_build (&offset_expr
, "lui", "t,u",
4993 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4994 macro_build (&offset_expr
, "daddiu", "t,r,j",
4995 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4996 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4997 macro_build (&offset_expr
, "daddiu", "t,r,j",
4998 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4999 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5000 macro_build (&offset_expr
, "daddiu", "t,r,j",
5001 tempreg
, tempreg
, BFD_RELOC_LO16
);
5006 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5007 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5009 relax_start (offset_expr
.X_add_symbol
);
5010 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5011 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5014 macro_build_lui (&offset_expr
, tempreg
);
5015 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5016 tempreg
, tempreg
, BFD_RELOC_LO16
);
5017 if (mips_relax
.sequence
)
5021 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5023 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5025 /* If this is a reference to an external symbol, and there
5026 is no constant, we want
5027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5028 or for lca or if tempreg is PIC_CALL_REG
5029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5030 For a local symbol, we want
5031 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5033 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5035 If we have a small constant, and this is a reference to
5036 an external symbol, we want
5037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5039 addiu $tempreg,$tempreg,<constant>
5040 For a local symbol, we want the same instruction
5041 sequence, but we output a BFD_RELOC_LO16 reloc on the
5044 If we have a large constant, and this is a reference to
5045 an external symbol, we want
5046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5047 lui $at,<hiconstant>
5048 addiu $at,$at,<loconstant>
5049 addu $tempreg,$tempreg,$at
5050 For a local symbol, we want the same instruction
5051 sequence, but we output a BFD_RELOC_LO16 reloc on the
5055 if (offset_expr
.X_add_number
== 0)
5057 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5058 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5060 relax_start (offset_expr
.X_add_symbol
);
5061 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5062 lw_reloc_type
, mips_gp_register
);
5065 /* We're going to put in an addu instruction using
5066 tempreg, so we may as well insert the nop right
5071 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5072 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5074 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5075 tempreg
, tempreg
, BFD_RELOC_LO16
);
5077 /* FIXME: If breg == 0, and the next instruction uses
5078 $tempreg, then if this variant case is used an extra
5079 nop will be generated. */
5081 else if (offset_expr
.X_add_number
>= -0x8000
5082 && offset_expr
.X_add_number
< 0x8000)
5084 load_got_offset (tempreg
, &offset_expr
);
5086 add_got_offset (tempreg
, &offset_expr
);
5090 expr1
.X_add_number
= offset_expr
.X_add_number
;
5091 offset_expr
.X_add_number
=
5092 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5093 load_got_offset (tempreg
, &offset_expr
);
5094 offset_expr
.X_add_number
= expr1
.X_add_number
;
5095 /* If we are going to add in a base register, and the
5096 target register and the base register are the same,
5097 then we are using AT as a temporary register. Since
5098 we want to load the constant into AT, we add our
5099 current AT (from the global offset table) and the
5100 register into the register now, and pretend we were
5101 not using a base register. */
5105 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5110 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5114 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5116 int add_breg_early
= 0;
5118 /* If this is a reference to an external, and there is no
5119 constant, or local symbol (*), with or without a
5121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5122 or for lca or if tempreg is PIC_CALL_REG
5123 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5125 If we have a small constant, and this is a reference to
5126 an external symbol, we want
5127 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5128 addiu $tempreg,$tempreg,<constant>
5130 If we have a large constant, and this is a reference to
5131 an external symbol, we want
5132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5133 lui $at,<hiconstant>
5134 addiu $at,$at,<loconstant>
5135 addu $tempreg,$tempreg,$at
5137 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5138 local symbols, even though it introduces an additional
5141 if (offset_expr
.X_add_number
)
5143 expr1
.X_add_number
= offset_expr
.X_add_number
;
5144 offset_expr
.X_add_number
= 0;
5146 relax_start (offset_expr
.X_add_symbol
);
5147 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5148 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5150 if (expr1
.X_add_number
>= -0x8000
5151 && expr1
.X_add_number
< 0x8000)
5153 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5154 tempreg
, tempreg
, BFD_RELOC_LO16
);
5156 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5160 /* If we are going to add in a base register, and the
5161 target register and the base register are the same,
5162 then we are using AT as a temporary register. Since
5163 we want to load the constant into AT, we add our
5164 current AT (from the global offset table) and the
5165 register into the register now, and pretend we were
5166 not using a base register. */
5171 assert (tempreg
== AT
);
5172 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5178 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5185 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5188 offset_expr
.X_add_number
= expr1
.X_add_number
;
5190 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5191 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5194 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5195 treg
, tempreg
, breg
);
5201 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5203 relax_start (offset_expr
.X_add_symbol
);
5204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5205 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5207 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5208 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5214 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5217 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5220 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5221 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5222 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5224 /* This is the large GOT case. If this is a reference to an
5225 external symbol, and there is no constant, we want
5226 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5227 addu $tempreg,$tempreg,$gp
5228 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5229 or for lca or if tempreg is PIC_CALL_REG
5230 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5231 addu $tempreg,$tempreg,$gp
5232 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5233 For a local symbol, we want
5234 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5236 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5238 If we have a small constant, and this is a reference to
5239 an external symbol, we want
5240 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5241 addu $tempreg,$tempreg,$gp
5242 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5244 addiu $tempreg,$tempreg,<constant>
5245 For a local symbol, we want
5246 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5248 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5250 If we have a large constant, and this is a reference to
5251 an external symbol, we want
5252 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5253 addu $tempreg,$tempreg,$gp
5254 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5255 lui $at,<hiconstant>
5256 addiu $at,$at,<loconstant>
5257 addu $tempreg,$tempreg,$at
5258 For a local symbol, we want
5259 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5260 lui $at,<hiconstant>
5261 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5262 addu $tempreg,$tempreg,$at
5265 expr1
.X_add_number
= offset_expr
.X_add_number
;
5266 offset_expr
.X_add_number
= 0;
5267 relax_start (offset_expr
.X_add_symbol
);
5268 gpdelay
= reg_needs_delay (mips_gp_register
);
5269 if (expr1
.X_add_number
== 0 && breg
== 0
5270 && (call
|| tempreg
== PIC_CALL_REG
))
5272 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5273 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5275 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5276 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5277 tempreg
, tempreg
, mips_gp_register
);
5278 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5279 tempreg
, lw_reloc_type
, tempreg
);
5280 if (expr1
.X_add_number
== 0)
5284 /* We're going to put in an addu instruction using
5285 tempreg, so we may as well insert the nop right
5290 else if (expr1
.X_add_number
>= -0x8000
5291 && expr1
.X_add_number
< 0x8000)
5294 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5295 tempreg
, tempreg
, BFD_RELOC_LO16
);
5301 /* If we are going to add in a base register, and the
5302 target register and the base register are the same,
5303 then we are using AT as a temporary register. Since
5304 we want to load the constant into AT, we add our
5305 current AT (from the global offset table) and the
5306 register into the register now, and pretend we were
5307 not using a base register. */
5312 assert (tempreg
== AT
);
5314 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5319 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5320 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5324 offset_expr
.X_add_number
=
5325 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5330 /* This is needed because this instruction uses $gp, but
5331 the first instruction on the main stream does not. */
5332 macro_build (NULL
, "nop", "");
5335 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5336 local_reloc_type
, mips_gp_register
);
5337 if (expr1
.X_add_number
>= -0x8000
5338 && expr1
.X_add_number
< 0x8000)
5341 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5342 tempreg
, tempreg
, BFD_RELOC_LO16
);
5343 /* FIXME: If add_number is 0, and there was no base
5344 register, the external symbol case ended with a load,
5345 so if the symbol turns out to not be external, and
5346 the next instruction uses tempreg, an unnecessary nop
5347 will be inserted. */
5353 /* We must add in the base register now, as in the
5354 external symbol case. */
5355 assert (tempreg
== AT
);
5357 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5360 /* We set breg to 0 because we have arranged to add
5361 it in in both cases. */
5365 macro_build_lui (&expr1
, AT
);
5366 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5367 AT
, AT
, BFD_RELOC_LO16
);
5368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5369 tempreg
, tempreg
, AT
);
5373 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5375 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5376 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5377 int add_breg_early
= 0;
5379 /* This is the large GOT case. If this is a reference to an
5380 external symbol, and there is no constant, we want
5381 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5382 add $tempreg,$tempreg,$gp
5383 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5384 or for lca or if tempreg is PIC_CALL_REG
5385 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5386 add $tempreg,$tempreg,$gp
5387 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5389 If we have a small constant, and this is a reference to
5390 an external symbol, we want
5391 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5392 add $tempreg,$tempreg,$gp
5393 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5394 addi $tempreg,$tempreg,<constant>
5396 If we have a large constant, and this is a reference to
5397 an external symbol, we want
5398 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5399 addu $tempreg,$tempreg,$gp
5400 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5401 lui $at,<hiconstant>
5402 addi $at,$at,<loconstant>
5403 add $tempreg,$tempreg,$at
5405 If we have NewABI, and we know it's a local symbol, we want
5406 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5407 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5408 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5410 relax_start (offset_expr
.X_add_symbol
);
5412 expr1
.X_add_number
= offset_expr
.X_add_number
;
5413 offset_expr
.X_add_number
= 0;
5415 if (expr1
.X_add_number
== 0 && breg
== 0
5416 && (call
|| tempreg
== PIC_CALL_REG
))
5418 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5419 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5421 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5422 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5423 tempreg
, tempreg
, mips_gp_register
);
5424 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5425 tempreg
, lw_reloc_type
, tempreg
);
5427 if (expr1
.X_add_number
== 0)
5429 else if (expr1
.X_add_number
>= -0x8000
5430 && expr1
.X_add_number
< 0x8000)
5432 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5433 tempreg
, tempreg
, BFD_RELOC_LO16
);
5435 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5439 /* If we are going to add in a base register, and the
5440 target register and the base register are the same,
5441 then we are using AT as a temporary register. Since
5442 we want to load the constant into AT, we add our
5443 current AT (from the global offset table) and the
5444 register into the register now, and pretend we were
5445 not using a base register. */
5450 assert (tempreg
== AT
);
5451 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5457 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5458 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5463 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5466 offset_expr
.X_add_number
= expr1
.X_add_number
;
5467 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5468 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5469 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5470 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5474 treg
, tempreg
, breg
);
5480 else if (mips_pic
== EMBEDDED_PIC
)
5483 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5485 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5486 mips_gp_register
, BFD_RELOC_GPREL16
);
5495 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5496 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5498 s
= ADDRESS_ADD_INSN
;
5500 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5509 /* The j instruction may not be used in PIC code, since it
5510 requires an absolute address. We convert it to a b
5512 if (mips_pic
== NO_PIC
)
5513 macro_build (&offset_expr
, "j", "a");
5515 macro_build (&offset_expr
, "b", "p");
5518 /* The jal instructions must be handled as macros because when
5519 generating PIC code they expand to multi-instruction
5520 sequences. Normally they are simple instructions. */
5525 if (mips_pic
== NO_PIC
5526 || mips_pic
== EMBEDDED_PIC
)
5527 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5528 else if (mips_pic
== SVR4_PIC
)
5530 if (sreg
!= PIC_CALL_REG
)
5531 as_warn (_("MIPS PIC call to register other than $25"));
5533 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5536 if (mips_cprestore_offset
< 0)
5537 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5540 if (! mips_frame_reg_valid
)
5542 as_warn (_("No .frame pseudo-op used in PIC code"));
5543 /* Quiet this warning. */
5544 mips_frame_reg_valid
= 1;
5546 if (! mips_cprestore_valid
)
5548 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5549 /* Quiet this warning. */
5550 mips_cprestore_valid
= 1;
5552 expr1
.X_add_number
= mips_cprestore_offset
;
5553 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5556 HAVE_64BIT_ADDRESSES
);
5566 if (mips_pic
== NO_PIC
)
5567 macro_build (&offset_expr
, "jal", "a");
5568 else if (mips_pic
== SVR4_PIC
)
5570 /* If this is a reference to an external symbol, and we are
5571 using a small GOT, we want
5572 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5576 lw $gp,cprestore($sp)
5577 The cprestore value is set using the .cprestore
5578 pseudo-op. If we are using a big GOT, we want
5579 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5581 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5585 lw $gp,cprestore($sp)
5586 If the symbol is not external, we want
5587 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5589 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5592 lw $gp,cprestore($sp)
5594 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5595 sequences above, minus nops, unless the symbol is local,
5596 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5602 relax_start (offset_expr
.X_add_symbol
);
5603 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5604 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5608 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5614 relax_start (offset_expr
.X_add_symbol
);
5615 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5616 BFD_RELOC_MIPS_CALL_HI16
);
5617 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5618 PIC_CALL_REG
, mips_gp_register
);
5619 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5620 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5623 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5624 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5626 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5627 PIC_CALL_REG
, PIC_CALL_REG
,
5628 BFD_RELOC_MIPS_GOT_OFST
);
5632 macro_build_jalr (&offset_expr
);
5636 relax_start (offset_expr
.X_add_symbol
);
5639 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5640 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5649 gpdelay
= reg_needs_delay (mips_gp_register
);
5650 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5651 BFD_RELOC_MIPS_CALL_HI16
);
5652 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5653 PIC_CALL_REG
, mips_gp_register
);
5654 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5655 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5660 macro_build (NULL
, "nop", "");
5662 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5663 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5666 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5667 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5669 macro_build_jalr (&offset_expr
);
5671 if (mips_cprestore_offset
< 0)
5672 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5675 if (! mips_frame_reg_valid
)
5677 as_warn (_("No .frame pseudo-op used in PIC code"));
5678 /* Quiet this warning. */
5679 mips_frame_reg_valid
= 1;
5681 if (! mips_cprestore_valid
)
5683 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5684 /* Quiet this warning. */
5685 mips_cprestore_valid
= 1;
5687 if (mips_opts
.noreorder
)
5688 macro_build (NULL
, "nop", "");
5689 expr1
.X_add_number
= mips_cprestore_offset
;
5690 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5693 HAVE_64BIT_ADDRESSES
);
5697 else if (mips_pic
== EMBEDDED_PIC
)
5699 macro_build (&offset_expr
, "bal", "p");
5700 /* The linker may expand the call to a longer sequence which
5701 uses $at, so we must break rather than return. */
5726 /* Itbl support may require additional care here. */
5731 /* Itbl support may require additional care here. */
5736 /* Itbl support may require additional care here. */
5741 /* Itbl support may require additional care here. */
5753 if (mips_opts
.arch
== CPU_R4650
)
5755 as_bad (_("opcode not supported on this processor"));
5759 /* Itbl support may require additional care here. */
5764 /* Itbl support may require additional care here. */
5769 /* Itbl support may require additional care here. */
5789 if (breg
== treg
|| coproc
|| lr
)
5811 /* Itbl support may require additional care here. */
5816 /* Itbl support may require additional care here. */
5821 /* Itbl support may require additional care here. */
5826 /* Itbl support may require additional care here. */
5842 if (mips_opts
.arch
== CPU_R4650
)
5844 as_bad (_("opcode not supported on this processor"));
5849 /* Itbl support may require additional care here. */
5853 /* Itbl support may require additional care here. */
5858 /* Itbl support may require additional care here. */
5870 /* Itbl support may require additional care here. */
5871 if (mask
== M_LWC1_AB
5872 || mask
== M_SWC1_AB
5873 || mask
== M_LDC1_AB
5874 || mask
== M_SDC1_AB
5883 /* Sign-extending 32-bit constants makes their handling easier.
5884 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5886 if ((! HAVE_64BIT_ADDRESSES
5887 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5888 && (offset_expr
.X_op
== O_constant
)
5889 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5890 == ~((bfd_vma
) 0x7fffffff)))
5892 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5893 as_bad (_("constant too large"));
5895 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5896 ^ 0x80000000) - 0x80000000);
5899 /* For embedded PIC, we allow loads where the offset is calculated
5900 by subtracting a symbol in the current segment from an unknown
5901 symbol, relative to a base register, e.g.:
5902 <op> $treg, <sym>-<localsym>($breg)
5903 This is used by the compiler for switch statements. */
5904 if (mips_pic
== EMBEDDED_PIC
5905 && offset_expr
.X_op
== O_subtract
5906 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5907 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5908 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5910 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5914 && (offset_expr
.X_add_number
== 0
5915 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5917 /* For this case, we output the instructions:
5918 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5919 addiu $tempreg,$tempreg,$breg
5920 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5921 If the relocation would fit entirely in 16 bits, it would be
5923 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5924 instead, but that seems quite difficult. */
5925 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5926 BFD_RELOC_PCREL_HI16_S
);
5928 ((bfd_arch_bits_per_address (stdoutput
) == 32
5929 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5930 ? "addu" : "daddu"),
5931 "d,v,t", tempreg
, tempreg
, breg
);
5932 macro_build (&offset_expr
, s
, fmt
, treg
,
5933 BFD_RELOC_PCREL_LO16
, tempreg
);
5939 if (offset_expr
.X_op
!= O_constant
5940 && offset_expr
.X_op
!= O_symbol
)
5942 as_bad (_("expression too complex"));
5943 offset_expr
.X_op
= O_constant
;
5946 /* A constant expression in PIC code can be handled just as it
5947 is in non PIC code. */
5948 if (mips_pic
== NO_PIC
5949 || offset_expr
.X_op
== O_constant
)
5951 /* If this is a reference to a GP relative symbol, and there
5952 is no base register, we want
5953 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5954 Otherwise, if there is no base register, we want
5955 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5956 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5957 If we have a constant, we need two instructions anyhow,
5958 so we always use the latter form.
5960 If we have a base register, and this is a reference to a
5961 GP relative symbol, we want
5962 addu $tempreg,$breg,$gp
5963 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5965 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5966 addu $tempreg,$tempreg,$breg
5967 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5968 With a constant we always use the latter case.
5970 With 64bit address space and no base register and $at usable,
5972 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5973 lui $at,<sym> (BFD_RELOC_HI16_S)
5974 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5977 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5978 If we have a base register, we want
5979 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5980 lui $at,<sym> (BFD_RELOC_HI16_S)
5981 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5985 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5987 Without $at we can't generate the optimal path for superscalar
5988 processors here since this would require two temporary registers.
5989 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5990 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5992 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5994 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5995 If we have a base register, we want
5996 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5997 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5999 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6001 daddu $tempreg,$tempreg,$breg
6002 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6004 If we have 64-bit addresses, as an optimization, for
6005 addresses which are 32-bit constants (e.g. kseg0/kseg1
6006 addresses) we fall back to the 32-bit address generation
6007 mechanism since it is more efficient. Note that due to
6008 the signed offset used by memory operations, the 32-bit
6009 range is shifted down by 32768 here. This code should
6010 probably attempt to generate 64-bit constants more
6011 efficiently in general.
6013 As an extension for architectures with 64-bit registers,
6014 we don't truncate 64-bit addresses given as literal
6015 constants down to 32 bits, to support existing practice
6016 in the mips64 Linux (the kernel), that compiles source
6017 files with -mabi=64, assembling them as o32 or n32 (with
6018 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6019 the whole kernel is loaded into a memory region that is
6020 addressable with sign-extended 32-bit addresses, it is
6021 wasteful to compute the upper 32 bits of every
6022 non-literal address, that takes more space and time.
6023 Some day this should probably be implemented as an
6024 assembler option, such that the kernel doesn't have to
6025 use such ugly hacks, even though it will still have to
6026 end up converting the binary to ELF32 for a number of
6027 platforms whose boot loaders don't support ELF64
6029 if ((HAVE_64BIT_ADDRESSES
6030 && ! (offset_expr
.X_op
== O_constant
6031 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6033 && offset_expr
.X_op
== O_constant
6034 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6036 /* ??? We don't provide a GP-relative alternative for
6037 these macros. It used not to be possible with the
6038 original relaxation code, but it could be done now. */
6040 if (used_at
== 0 && ! mips_opts
.noat
)
6042 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6043 BFD_RELOC_MIPS_HIGHEST
);
6044 macro_build (&offset_expr
, "lui", "t,u", AT
,
6046 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6047 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6049 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6050 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6051 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6052 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6058 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6059 BFD_RELOC_MIPS_HIGHEST
);
6060 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6061 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6062 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6063 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6064 tempreg
, BFD_RELOC_HI16_S
);
6065 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6067 macro_build (NULL
, "daddu", "d,v,t",
6068 tempreg
, tempreg
, breg
);
6069 macro_build (&offset_expr
, s
, fmt
, treg
,
6070 BFD_RELOC_LO16
, tempreg
);
6076 if (offset_expr
.X_op
== O_constant
6077 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6078 as_bad (_("load/store address overflow (max 32 bits)"));
6082 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6083 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6085 relax_start (offset_expr
.X_add_symbol
);
6086 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6091 macro_build_lui (&offset_expr
, tempreg
);
6092 macro_build (&offset_expr
, s
, fmt
, treg
,
6093 BFD_RELOC_LO16
, tempreg
);
6094 if (mips_relax
.sequence
)
6099 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6100 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6102 relax_start (offset_expr
.X_add_symbol
);
6103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6104 tempreg
, breg
, mips_gp_register
);
6105 macro_build (&offset_expr
, s
, fmt
, treg
,
6106 BFD_RELOC_GPREL16
, tempreg
);
6109 macro_build_lui (&offset_expr
, tempreg
);
6110 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6111 tempreg
, tempreg
, breg
);
6112 macro_build (&offset_expr
, s
, fmt
, treg
,
6113 BFD_RELOC_LO16
, tempreg
);
6114 if (mips_relax
.sequence
)
6118 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6120 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6122 /* If this is a reference to an external symbol, we want
6123 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6125 <op> $treg,0($tempreg)
6127 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6129 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6130 <op> $treg,0($tempreg)
6133 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6134 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6136 If there is a base register, we add it to $tempreg before
6137 the <op>. If there is a constant, we stick it in the
6138 <op> instruction. We don't handle constants larger than
6139 16 bits, because we have no way to load the upper 16 bits
6140 (actually, we could handle them for the subset of cases
6141 in which we are not using $at). */
6142 assert (offset_expr
.X_op
== O_symbol
);
6145 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6146 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6148 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6149 tempreg
, tempreg
, breg
);
6150 macro_build (&offset_expr
, s
, fmt
, treg
,
6151 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6158 expr1
.X_add_number
= offset_expr
.X_add_number
;
6159 offset_expr
.X_add_number
= 0;
6160 if (expr1
.X_add_number
< -0x8000
6161 || expr1
.X_add_number
>= 0x8000)
6162 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6163 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6164 lw_reloc_type
, mips_gp_register
);
6166 relax_start (offset_expr
.X_add_symbol
);
6168 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6169 tempreg
, BFD_RELOC_LO16
);
6172 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6173 tempreg
, tempreg
, breg
);
6174 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6176 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6180 /* If this is a reference to an external symbol, we want
6181 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6182 addu $tempreg,$tempreg,$gp
6183 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6184 <op> $treg,0($tempreg)
6186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6189 <op> $treg,0($tempreg)
6190 If there is a base register, we add it to $tempreg before
6191 the <op>. If there is a constant, we stick it in the
6192 <op> instruction. We don't handle constants larger than
6193 16 bits, because we have no way to load the upper 16 bits
6194 (actually, we could handle them for the subset of cases
6195 in which we are not using $at). */
6196 assert (offset_expr
.X_op
== O_symbol
);
6197 expr1
.X_add_number
= offset_expr
.X_add_number
;
6198 offset_expr
.X_add_number
= 0;
6199 if (expr1
.X_add_number
< -0x8000
6200 || expr1
.X_add_number
>= 0x8000)
6201 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6202 gpdelay
= reg_needs_delay (mips_gp_register
);
6203 relax_start (offset_expr
.X_add_symbol
);
6204 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6205 BFD_RELOC_MIPS_GOT_HI16
);
6206 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6208 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6209 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6212 macro_build (NULL
, "nop", "");
6213 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6214 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6216 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6217 tempreg
, BFD_RELOC_LO16
);
6221 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6222 tempreg
, tempreg
, breg
);
6223 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6225 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6227 /* If this is a reference to an external symbol, we want
6228 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6229 add $tempreg,$tempreg,$gp
6230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6231 <op> $treg,<ofst>($tempreg)
6232 Otherwise, for local symbols, we want:
6233 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6234 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6235 assert (offset_expr
.X_op
== O_symbol
);
6236 expr1
.X_add_number
= offset_expr
.X_add_number
;
6237 offset_expr
.X_add_number
= 0;
6238 if (expr1
.X_add_number
< -0x8000
6239 || expr1
.X_add_number
>= 0x8000)
6240 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6241 relax_start (offset_expr
.X_add_symbol
);
6242 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6243 BFD_RELOC_MIPS_GOT_HI16
);
6244 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6246 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6247 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6249 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6250 tempreg
, tempreg
, breg
);
6251 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6254 offset_expr
.X_add_number
= expr1
.X_add_number
;
6255 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6256 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6258 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6259 tempreg
, tempreg
, breg
);
6260 macro_build (&offset_expr
, s
, fmt
, treg
,
6261 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6264 else if (mips_pic
== EMBEDDED_PIC
)
6266 /* If there is no base register, we want
6267 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6268 If there is a base register, we want
6269 addu $tempreg,$breg,$gp
6270 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6272 assert (offset_expr
.X_op
== O_symbol
);
6275 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6281 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6282 tempreg
, breg
, mips_gp_register
);
6283 macro_build (&offset_expr
, s
, fmt
, treg
,
6284 BFD_RELOC_GPREL16
, tempreg
);
6297 load_register (treg
, &imm_expr
, 0);
6301 load_register (treg
, &imm_expr
, 1);
6305 if (imm_expr
.X_op
== O_constant
)
6307 load_register (AT
, &imm_expr
, 0);
6308 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6313 assert (offset_expr
.X_op
== O_symbol
6314 && strcmp (segment_name (S_GET_SEGMENT
6315 (offset_expr
.X_add_symbol
)),
6317 && offset_expr
.X_add_number
== 0);
6318 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6319 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6324 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6325 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6326 order 32 bits of the value and the low order 32 bits are either
6327 zero or in OFFSET_EXPR. */
6328 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6330 if (HAVE_64BIT_GPRS
)
6331 load_register (treg
, &imm_expr
, 1);
6336 if (target_big_endian
)
6348 load_register (hreg
, &imm_expr
, 0);
6351 if (offset_expr
.X_op
== O_absent
)
6352 move_register (lreg
, 0);
6355 assert (offset_expr
.X_op
== O_constant
);
6356 load_register (lreg
, &offset_expr
, 0);
6363 /* We know that sym is in the .rdata section. First we get the
6364 upper 16 bits of the address. */
6365 if (mips_pic
== NO_PIC
)
6367 macro_build_lui (&offset_expr
, AT
);
6369 else if (mips_pic
== SVR4_PIC
)
6371 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6372 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6374 else if (mips_pic
== EMBEDDED_PIC
)
6376 /* For embedded PIC we pick up the entire address off $gp in
6377 a single instruction. */
6378 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
,
6379 mips_gp_register
, BFD_RELOC_GPREL16
);
6380 offset_expr
.X_op
= O_constant
;
6381 offset_expr
.X_add_number
= 0;
6386 /* Now we load the register(s). */
6387 if (HAVE_64BIT_GPRS
)
6388 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6391 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6394 /* FIXME: How in the world do we deal with the possible
6396 offset_expr
.X_add_number
+= 4;
6397 macro_build (&offset_expr
, "lw", "t,o(b)",
6398 treg
+ 1, BFD_RELOC_LO16
, AT
);
6404 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6405 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6406 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6407 the value and the low order 32 bits are either zero or in
6409 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6411 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6412 if (HAVE_64BIT_FPRS
)
6414 assert (HAVE_64BIT_GPRS
);
6415 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6419 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6420 if (offset_expr
.X_op
== O_absent
)
6421 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6424 assert (offset_expr
.X_op
== O_constant
);
6425 load_register (AT
, &offset_expr
, 0);
6426 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6432 assert (offset_expr
.X_op
== O_symbol
6433 && offset_expr
.X_add_number
== 0);
6434 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6435 if (strcmp (s
, ".lit8") == 0)
6437 if (mips_opts
.isa
!= ISA_MIPS1
)
6439 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6440 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6443 breg
= mips_gp_register
;
6444 r
= BFD_RELOC_MIPS_LITERAL
;
6449 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6450 if (mips_pic
== SVR4_PIC
)
6451 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6452 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6455 /* FIXME: This won't work for a 64 bit address. */
6456 macro_build_lui (&offset_expr
, AT
);
6459 if (mips_opts
.isa
!= ISA_MIPS1
)
6461 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6462 treg
, BFD_RELOC_LO16
, AT
);
6471 if (mips_opts
.arch
== CPU_R4650
)
6473 as_bad (_("opcode not supported on this processor"));
6476 /* Even on a big endian machine $fn comes before $fn+1. We have
6477 to adjust when loading from memory. */
6480 assert (mips_opts
.isa
== ISA_MIPS1
);
6481 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6482 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6483 /* FIXME: A possible overflow which I don't know how to deal
6485 offset_expr
.X_add_number
+= 4;
6486 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6487 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6495 * The MIPS assembler seems to check for X_add_number not
6496 * being double aligned and generating:
6499 * addiu at,at,%lo(foo+1)
6502 * But, the resulting address is the same after relocation so why
6503 * generate the extra instruction?
6505 if (mips_opts
.arch
== CPU_R4650
)
6507 as_bad (_("opcode not supported on this processor"));
6510 /* Itbl support may require additional care here. */
6512 if (mips_opts
.isa
!= ISA_MIPS1
)
6523 if (mips_opts
.arch
== CPU_R4650
)
6525 as_bad (_("opcode not supported on this processor"));
6529 if (mips_opts
.isa
!= ISA_MIPS1
)
6537 /* Itbl support may require additional care here. */
6542 if (HAVE_64BIT_GPRS
)
6553 if (HAVE_64BIT_GPRS
)
6563 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6564 loads for the case of doing a pair of loads to simulate an 'ld'.
6565 This is not currently done by the compiler, and assembly coders
6566 writing embedded-pic code can cope. */
6568 if (offset_expr
.X_op
!= O_symbol
6569 && offset_expr
.X_op
!= O_constant
)
6571 as_bad (_("expression too complex"));
6572 offset_expr
.X_op
= O_constant
;
6575 /* Even on a big endian machine $fn comes before $fn+1. We have
6576 to adjust when loading from memory. We set coproc if we must
6577 load $fn+1 first. */
6578 /* Itbl support may require additional care here. */
6579 if (! target_big_endian
)
6582 if (mips_pic
== NO_PIC
6583 || offset_expr
.X_op
== O_constant
)
6585 /* If this is a reference to a GP relative symbol, we want
6586 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6587 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6588 If we have a base register, we use this
6590 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6591 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6592 If this is not a GP relative symbol, we want
6593 lui $at,<sym> (BFD_RELOC_HI16_S)
6594 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6595 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6596 If there is a base register, we add it to $at after the
6597 lui instruction. If there is a constant, we always use
6599 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6600 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6604 relax_start (offset_expr
.X_add_symbol
);
6607 tempreg
= mips_gp_register
;
6612 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6613 AT
, breg
, mips_gp_register
);
6618 /* Itbl support may require additional care here. */
6619 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6620 BFD_RELOC_GPREL16
, tempreg
);
6621 offset_expr
.X_add_number
+= 4;
6623 /* Set mips_optimize to 2 to avoid inserting an
6625 hold_mips_optimize
= mips_optimize
;
6627 /* Itbl support may require additional care here. */
6628 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6629 BFD_RELOC_GPREL16
, tempreg
);
6630 mips_optimize
= hold_mips_optimize
;
6634 /* We just generated two relocs. When tc_gen_reloc
6635 handles this case, it will skip the first reloc and
6636 handle the second. The second reloc already has an
6637 extra addend of 4, which we added above. We must
6638 subtract it out, and then subtract another 4 to make
6639 the first reloc come out right. The second reloc
6640 will come out right because we are going to add 4 to
6641 offset_expr when we build its instruction below.
6643 If we have a symbol, then we don't want to include
6644 the offset, because it will wind up being included
6645 when we generate the reloc. */
6647 if (offset_expr
.X_op
== O_constant
)
6648 offset_expr
.X_add_number
-= 8;
6651 offset_expr
.X_add_number
= -4;
6652 offset_expr
.X_op
= O_constant
;
6655 macro_build_lui (&offset_expr
, AT
);
6657 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6658 /* Itbl support may require additional care here. */
6659 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6660 BFD_RELOC_LO16
, AT
);
6661 /* FIXME: How do we handle overflow here? */
6662 offset_expr
.X_add_number
+= 4;
6663 /* Itbl support may require additional care here. */
6664 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6665 BFD_RELOC_LO16
, AT
);
6666 if (mips_relax
.sequence
)
6669 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6671 /* If this is a reference to an external symbol, we want
6672 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6677 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6679 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6680 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6681 If there is a base register we add it to $at before the
6682 lwc1 instructions. If there is a constant we include it
6683 in the lwc1 instructions. */
6685 expr1
.X_add_number
= offset_expr
.X_add_number
;
6686 if (expr1
.X_add_number
< -0x8000
6687 || expr1
.X_add_number
>= 0x8000 - 4)
6688 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6689 load_got_offset (AT
, &offset_expr
);
6692 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6694 /* Set mips_optimize to 2 to avoid inserting an undesired
6696 hold_mips_optimize
= mips_optimize
;
6699 /* Itbl support may require additional care here. */
6700 relax_start (offset_expr
.X_add_symbol
);
6701 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6702 BFD_RELOC_LO16
, AT
);
6703 expr1
.X_add_number
+= 4;
6704 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6705 BFD_RELOC_LO16
, AT
);
6707 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6708 BFD_RELOC_LO16
, AT
);
6709 offset_expr
.X_add_number
+= 4;
6710 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6711 BFD_RELOC_LO16
, AT
);
6714 mips_optimize
= hold_mips_optimize
;
6716 else if (mips_pic
== SVR4_PIC
)
6720 /* If this is a reference to an external symbol, we want
6721 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6723 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6728 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6730 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6731 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6732 If there is a base register we add it to $at before the
6733 lwc1 instructions. If there is a constant we include it
6734 in the lwc1 instructions. */
6736 expr1
.X_add_number
= offset_expr
.X_add_number
;
6737 offset_expr
.X_add_number
= 0;
6738 if (expr1
.X_add_number
< -0x8000
6739 || expr1
.X_add_number
>= 0x8000 - 4)
6740 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6741 gpdelay
= reg_needs_delay (mips_gp_register
);
6742 relax_start (offset_expr
.X_add_symbol
);
6743 macro_build (&offset_expr
, "lui", "t,u",
6744 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6745 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6746 AT
, AT
, mips_gp_register
);
6747 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6748 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6751 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6752 /* Itbl support may require additional care here. */
6753 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6754 BFD_RELOC_LO16
, AT
);
6755 expr1
.X_add_number
+= 4;
6757 /* Set mips_optimize to 2 to avoid inserting an undesired
6759 hold_mips_optimize
= mips_optimize
;
6761 /* Itbl support may require additional care here. */
6762 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6763 BFD_RELOC_LO16
, AT
);
6764 mips_optimize
= hold_mips_optimize
;
6765 expr1
.X_add_number
-= 4;
6768 offset_expr
.X_add_number
= expr1
.X_add_number
;
6770 macro_build (NULL
, "nop", "");
6771 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6772 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6775 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6776 /* Itbl support may require additional care here. */
6777 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6778 BFD_RELOC_LO16
, AT
);
6779 offset_expr
.X_add_number
+= 4;
6781 /* Set mips_optimize to 2 to avoid inserting an undesired
6783 hold_mips_optimize
= mips_optimize
;
6785 /* Itbl support may require additional care here. */
6786 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6787 BFD_RELOC_LO16
, AT
);
6788 mips_optimize
= hold_mips_optimize
;
6791 else if (mips_pic
== EMBEDDED_PIC
)
6793 /* If there is no base register, we use
6794 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6795 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6796 If we have a base register, we use
6798 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6799 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6803 tempreg
= mips_gp_register
;
6808 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6809 AT
, breg
, mips_gp_register
);
6814 /* Itbl support may require additional care here. */
6815 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6816 BFD_RELOC_GPREL16
, tempreg
);
6817 offset_expr
.X_add_number
+= 4;
6818 /* Itbl support may require additional care here. */
6819 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6820 BFD_RELOC_GPREL16
, tempreg
);
6836 assert (HAVE_32BIT_ADDRESSES
);
6837 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6838 offset_expr
.X_add_number
+= 4;
6839 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6842 /* New code added to support COPZ instructions.
6843 This code builds table entries out of the macros in mip_opcodes.
6844 R4000 uses interlocks to handle coproc delays.
6845 Other chips (like the R3000) require nops to be inserted for delays.
6847 FIXME: Currently, we require that the user handle delays.
6848 In order to fill delay slots for non-interlocked chips,
6849 we must have a way to specify delays based on the coprocessor.
6850 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6851 What are the side-effects of the cop instruction?
6852 What cache support might we have and what are its effects?
6853 Both coprocessor & memory require delays. how long???
6854 What registers are read/set/modified?
6856 If an itbl is provided to interpret cop instructions,
6857 this knowledge can be encoded in the itbl spec. */
6871 /* For now we just do C (same as Cz). The parameter will be
6872 stored in insn_opcode by mips_ip. */
6873 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6877 move_register (dreg
, sreg
);
6880 #ifdef LOSING_COMPILER
6882 /* Try and see if this is a new itbl instruction.
6883 This code builds table entries out of the macros in mip_opcodes.
6884 FIXME: For now we just assemble the expression and pass it's
6885 value along as a 32-bit immediate.
6886 We may want to have the assembler assemble this value,
6887 so that we gain the assembler's knowledge of delay slots,
6889 Would it be more efficient to use mask (id) here? */
6890 if (itbl_have_entries
6891 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6893 s
= ip
->insn_mo
->name
;
6895 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6896 macro_build (&immed_expr
, s
, "C");
6903 as_warn (_("Macro used $at after \".set noat\""));
6907 macro2 (struct mips_cl_insn
*ip
)
6909 register int treg
, sreg
, dreg
, breg
;
6924 bfd_reloc_code_real_type r
;
6926 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6927 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6928 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6929 mask
= ip
->insn_mo
->mask
;
6931 expr1
.X_op
= O_constant
;
6932 expr1
.X_op_symbol
= NULL
;
6933 expr1
.X_add_symbol
= NULL
;
6934 expr1
.X_add_number
= 1;
6938 #endif /* LOSING_COMPILER */
6943 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6944 macro_build (NULL
, "mflo", "d", dreg
);
6950 /* The MIPS assembler some times generates shifts and adds. I'm
6951 not trying to be that fancy. GCC should do this for us
6953 load_register (AT
, &imm_expr
, dbl
);
6954 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6955 macro_build (NULL
, "mflo", "d", dreg
);
6968 mips_emit_delays (TRUE
);
6969 ++mips_opts
.noreorder
;
6970 mips_any_noreorder
= 1;
6972 load_register (AT
, &imm_expr
, dbl
);
6973 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6974 macro_build (NULL
, "mflo", "d", dreg
);
6975 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6976 macro_build (NULL
, "mfhi", "d", AT
);
6978 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6981 expr1
.X_add_number
= 8;
6982 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6983 macro_build (NULL
, "nop", "", 0);
6984 macro_build (NULL
, "break", "c", 6);
6986 --mips_opts
.noreorder
;
6987 macro_build (NULL
, "mflo", "d", dreg
);
7000 mips_emit_delays (TRUE
);
7001 ++mips_opts
.noreorder
;
7002 mips_any_noreorder
= 1;
7004 load_register (AT
, &imm_expr
, dbl
);
7005 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7006 sreg
, imm
? AT
: treg
);
7007 macro_build (NULL
, "mfhi", "d", AT
);
7008 macro_build (NULL
, "mflo", "d", dreg
);
7010 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7013 expr1
.X_add_number
= 8;
7014 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7015 macro_build (NULL
, "nop", "", 0);
7016 macro_build (NULL
, "break", "c", 6);
7018 --mips_opts
.noreorder
;
7022 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7034 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7035 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7040 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7041 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7042 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7043 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7047 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7059 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7060 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7065 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7066 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7067 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7068 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7076 if (imm_expr
.X_op
!= O_constant
)
7077 as_bad (_("Improper rotate count"));
7078 rot
= imm_expr
.X_add_number
& 0x3f;
7079 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7081 rot
= (64 - rot
) & 0x3f;
7083 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7085 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7090 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7093 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7094 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7096 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7097 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7098 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7106 if (imm_expr
.X_op
!= O_constant
)
7107 as_bad (_("Improper rotate count"));
7108 rot
= imm_expr
.X_add_number
& 0x1f;
7109 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7111 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7116 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7119 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7120 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7121 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7126 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7128 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7131 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7132 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7133 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7134 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7138 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7140 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7143 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7144 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7145 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7146 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7154 if (imm_expr
.X_op
!= O_constant
)
7155 as_bad (_("Improper rotate count"));
7156 rot
= imm_expr
.X_add_number
& 0x3f;
7157 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7160 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7162 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7167 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7170 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7171 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7173 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7174 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7175 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7183 if (imm_expr
.X_op
!= O_constant
)
7184 as_bad (_("Improper rotate count"));
7185 rot
= imm_expr
.X_add_number
& 0x1f;
7186 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7188 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7193 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7196 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7197 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7198 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7203 if (mips_opts
.arch
== CPU_R4650
)
7205 as_bad (_("opcode not supported on this processor"));
7208 assert (mips_opts
.isa
== ISA_MIPS1
);
7209 /* Even on a big endian machine $fn comes before $fn+1. We have
7210 to adjust when storing to memory. */
7211 macro_build (&offset_expr
, "swc1", "T,o(b)",
7212 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7213 offset_expr
.X_add_number
+= 4;
7214 macro_build (&offset_expr
, "swc1", "T,o(b)",
7215 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7220 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7222 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7225 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7226 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7231 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7233 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7238 as_warn (_("Instruction %s: result is always false"),
7240 move_register (dreg
, 0);
7243 if (imm_expr
.X_op
== O_constant
7244 && imm_expr
.X_add_number
>= 0
7245 && imm_expr
.X_add_number
< 0x10000)
7247 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7250 else if (imm_expr
.X_op
== O_constant
7251 && imm_expr
.X_add_number
> -0x8000
7252 && imm_expr
.X_add_number
< 0)
7254 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7255 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7256 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7261 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7262 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7265 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7270 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7276 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7277 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7280 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7282 if (imm_expr
.X_op
== O_constant
7283 && imm_expr
.X_add_number
>= -0x8000
7284 && imm_expr
.X_add_number
< 0x8000)
7286 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7287 dreg
, sreg
, BFD_RELOC_LO16
);
7292 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7293 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7297 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7302 case M_SGT
: /* sreg > treg <==> treg < sreg */
7308 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7311 case M_SGT_I
: /* sreg > I <==> I < sreg */
7317 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7318 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7321 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7327 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7328 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7331 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7337 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7338 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7339 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7343 if (imm_expr
.X_op
== O_constant
7344 && imm_expr
.X_add_number
>= -0x8000
7345 && imm_expr
.X_add_number
< 0x8000)
7347 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7350 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7351 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7355 if (imm_expr
.X_op
== O_constant
7356 && imm_expr
.X_add_number
>= -0x8000
7357 && imm_expr
.X_add_number
< 0x8000)
7359 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7363 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7364 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7369 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7371 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7374 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7375 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7380 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7382 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7387 as_warn (_("Instruction %s: result is always true"),
7389 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7390 dreg
, 0, BFD_RELOC_LO16
);
7393 if (imm_expr
.X_op
== O_constant
7394 && imm_expr
.X_add_number
>= 0
7395 && imm_expr
.X_add_number
< 0x10000)
7397 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7400 else if (imm_expr
.X_op
== O_constant
7401 && imm_expr
.X_add_number
> -0x8000
7402 && imm_expr
.X_add_number
< 0)
7404 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7405 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7406 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7411 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7412 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7415 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7423 if (imm_expr
.X_op
== O_constant
7424 && imm_expr
.X_add_number
> -0x8000
7425 && imm_expr
.X_add_number
<= 0x8000)
7427 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7428 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7429 dreg
, sreg
, BFD_RELOC_LO16
);
7432 load_register (AT
, &imm_expr
, dbl
);
7433 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7439 if (imm_expr
.X_op
== O_constant
7440 && imm_expr
.X_add_number
> -0x8000
7441 && imm_expr
.X_add_number
<= 0x8000)
7443 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7444 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7445 dreg
, sreg
, BFD_RELOC_LO16
);
7448 load_register (AT
, &imm_expr
, dbl
);
7449 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7470 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7471 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7476 assert (mips_opts
.isa
== ISA_MIPS1
);
7477 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7478 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7481 * Is the double cfc1 instruction a bug in the mips assembler;
7482 * or is there a reason for it?
7484 mips_emit_delays (TRUE
);
7485 ++mips_opts
.noreorder
;
7486 mips_any_noreorder
= 1;
7487 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7488 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7489 macro_build (NULL
, "nop", "");
7490 expr1
.X_add_number
= 3;
7491 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7492 expr1
.X_add_number
= 2;
7493 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7494 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7495 macro_build (NULL
, "nop", "");
7496 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7498 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7499 macro_build (NULL
, "nop", "");
7500 --mips_opts
.noreorder
;
7509 if (offset_expr
.X_add_number
>= 0x7fff)
7510 as_bad (_("operand overflow"));
7511 if (! target_big_endian
)
7512 ++offset_expr
.X_add_number
;
7513 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7514 if (! target_big_endian
)
7515 --offset_expr
.X_add_number
;
7517 ++offset_expr
.X_add_number
;
7518 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7519 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7520 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7533 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7534 as_bad (_("operand overflow"));
7539 if (! target_big_endian
)
7540 offset_expr
.X_add_number
+= off
;
7541 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7542 if (! target_big_endian
)
7543 offset_expr
.X_add_number
-= off
;
7545 offset_expr
.X_add_number
+= off
;
7546 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7548 /* If necessary, move the result in tempreg the final destination. */
7549 if (treg
== tempreg
)
7551 /* Protect second load's delay slot. */
7553 move_register (treg
, tempreg
);
7567 load_address (AT
, &offset_expr
, &used_at
);
7569 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7570 if (! target_big_endian
)
7571 expr1
.X_add_number
= off
;
7573 expr1
.X_add_number
= 0;
7574 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7575 if (! target_big_endian
)
7576 expr1
.X_add_number
= 0;
7578 expr1
.X_add_number
= off
;
7579 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7585 load_address (AT
, &offset_expr
, &used_at
);
7587 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7588 if (target_big_endian
)
7589 expr1
.X_add_number
= 0;
7590 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7591 treg
, BFD_RELOC_LO16
, AT
);
7592 if (target_big_endian
)
7593 expr1
.X_add_number
= 1;
7595 expr1
.X_add_number
= 0;
7596 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7597 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7598 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7602 if (offset_expr
.X_add_number
>= 0x7fff)
7603 as_bad (_("operand overflow"));
7604 if (target_big_endian
)
7605 ++offset_expr
.X_add_number
;
7606 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7607 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7608 if (target_big_endian
)
7609 --offset_expr
.X_add_number
;
7611 ++offset_expr
.X_add_number
;
7612 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7625 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7626 as_bad (_("operand overflow"));
7627 if (! target_big_endian
)
7628 offset_expr
.X_add_number
+= off
;
7629 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7630 if (! target_big_endian
)
7631 offset_expr
.X_add_number
-= off
;
7633 offset_expr
.X_add_number
+= off
;
7634 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7648 load_address (AT
, &offset_expr
, &used_at
);
7650 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7651 if (! target_big_endian
)
7652 expr1
.X_add_number
= off
;
7654 expr1
.X_add_number
= 0;
7655 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7656 if (! target_big_endian
)
7657 expr1
.X_add_number
= 0;
7659 expr1
.X_add_number
= off
;
7660 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7665 load_address (AT
, &offset_expr
, &used_at
);
7667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7668 if (! target_big_endian
)
7669 expr1
.X_add_number
= 0;
7670 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7671 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7672 if (! target_big_endian
)
7673 expr1
.X_add_number
= 1;
7675 expr1
.X_add_number
= 0;
7676 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7677 if (! target_big_endian
)
7678 expr1
.X_add_number
= 0;
7680 expr1
.X_add_number
= 1;
7681 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7682 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7683 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7687 /* FIXME: Check if this is one of the itbl macros, since they
7688 are added dynamically. */
7689 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7693 as_warn (_("Macro used $at after \".set noat\""));
7696 /* Implement macros in mips16 mode. */
7699 mips16_macro (struct mips_cl_insn
*ip
)
7702 int xreg
, yreg
, zreg
, tmp
;
7705 const char *s
, *s2
, *s3
;
7707 mask
= ip
->insn_mo
->mask
;
7709 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7710 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7711 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7713 expr1
.X_op
= O_constant
;
7714 expr1
.X_op_symbol
= NULL
;
7715 expr1
.X_add_symbol
= NULL
;
7716 expr1
.X_add_number
= 1;
7735 mips_emit_delays (TRUE
);
7736 ++mips_opts
.noreorder
;
7737 mips_any_noreorder
= 1;
7738 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7739 expr1
.X_add_number
= 2;
7740 macro_build (&expr1
, "bnez", "x,p", yreg
);
7741 macro_build (NULL
, "break", "6", 7);
7743 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7744 since that causes an overflow. We should do that as well,
7745 but I don't see how to do the comparisons without a temporary
7747 --mips_opts
.noreorder
;
7748 macro_build (NULL
, s
, "x", zreg
);
7767 mips_emit_delays (TRUE
);
7768 ++mips_opts
.noreorder
;
7769 mips_any_noreorder
= 1;
7770 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7771 expr1
.X_add_number
= 2;
7772 macro_build (&expr1
, "bnez", "x,p", yreg
);
7773 macro_build (NULL
, "break", "6", 7);
7774 --mips_opts
.noreorder
;
7775 macro_build (NULL
, s2
, "x", zreg
);
7781 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7782 macro_build (NULL
, "mflo", "x", zreg
);
7790 if (imm_expr
.X_op
!= O_constant
)
7791 as_bad (_("Unsupported large constant"));
7792 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7793 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7797 if (imm_expr
.X_op
!= O_constant
)
7798 as_bad (_("Unsupported large constant"));
7799 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7800 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7804 if (imm_expr
.X_op
!= O_constant
)
7805 as_bad (_("Unsupported large constant"));
7806 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7807 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7829 goto do_reverse_branch
;
7833 goto do_reverse_branch
;
7845 goto do_reverse_branch
;
7856 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7857 macro_build (&offset_expr
, s2
, "p");
7884 goto do_addone_branch_i
;
7889 goto do_addone_branch_i
;
7904 goto do_addone_branch_i
;
7911 if (imm_expr
.X_op
!= O_constant
)
7912 as_bad (_("Unsupported large constant"));
7913 ++imm_expr
.X_add_number
;
7916 macro_build (&imm_expr
, s
, s3
, xreg
);
7917 macro_build (&offset_expr
, s2
, "p");
7921 expr1
.X_add_number
= 0;
7922 macro_build (&expr1
, "slti", "x,8", yreg
);
7924 move_register (xreg
, yreg
);
7925 expr1
.X_add_number
= 2;
7926 macro_build (&expr1
, "bteqz", "p");
7927 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7931 /* For consistency checking, verify that all bits are specified either
7932 by the match/mask part of the instruction definition, or by the
7935 validate_mips_insn (const struct mips_opcode
*opc
)
7937 const char *p
= opc
->args
;
7939 unsigned long used_bits
= opc
->mask
;
7941 if ((used_bits
& opc
->match
) != opc
->match
)
7943 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7944 opc
->name
, opc
->args
);
7947 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7957 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7958 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7959 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7960 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7961 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7962 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7963 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7964 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7965 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7968 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7969 c
, opc
->name
, opc
->args
);
7973 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7974 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7976 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7977 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7978 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7979 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7981 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7982 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7984 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7985 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7987 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7988 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7989 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7990 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7991 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7992 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7993 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7994 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7995 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7996 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7997 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7998 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7999 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8000 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8001 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8002 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8003 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8005 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8006 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8007 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8008 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8010 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8011 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8012 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8013 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8014 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8015 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8016 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8017 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8018 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8021 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8022 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8023 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8024 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8025 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8029 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8030 c
, opc
->name
, opc
->args
);
8034 if (used_bits
!= 0xffffffff)
8036 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8037 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8043 /* This routine assembles an instruction into its binary format. As a
8044 side effect, it sets one of the global variables imm_reloc or
8045 offset_reloc to the type of relocation to do if one of the operands
8046 is an address expression. */
8049 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8054 struct mips_opcode
*insn
;
8057 unsigned int lastregno
= 0;
8058 unsigned int lastpos
= 0;
8059 unsigned int limlo
, limhi
;
8065 /* If the instruction contains a '.', we first try to match an instruction
8066 including the '.'. Then we try again without the '.'. */
8068 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8071 /* If we stopped on whitespace, then replace the whitespace with null for
8072 the call to hash_find. Save the character we replaced just in case we
8073 have to re-parse the instruction. */
8080 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8082 /* If we didn't find the instruction in the opcode table, try again, but
8083 this time with just the instruction up to, but not including the
8087 /* Restore the character we overwrite above (if any). */
8091 /* Scan up to the first '.' or whitespace. */
8093 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8097 /* If we did not find a '.', then we can quit now. */
8100 insn_error
= "unrecognized opcode";
8104 /* Lookup the instruction in the hash table. */
8106 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8108 insn_error
= "unrecognized opcode";
8118 assert (strcmp (insn
->name
, str
) == 0);
8120 if (OPCODE_IS_MEMBER (insn
,
8122 | (file_ase_mips16
? INSN_MIPS16
: 0)
8123 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8124 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8130 if (insn
->pinfo
!= INSN_MACRO
)
8132 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8138 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8139 && strcmp (insn
->name
, insn
[1].name
) == 0)
8148 static char buf
[100];
8150 _("opcode not supported on this processor: %s (%s)"),
8151 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8152 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8162 ip
->insn_opcode
= insn
->match
;
8164 for (args
= insn
->args
;; ++args
)
8168 s
+= strspn (s
, " \t");
8172 case '\0': /* end of args */
8185 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8189 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8193 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8197 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8203 /* Handle optional base register.
8204 Either the base register is omitted or
8205 we must have a left paren. */
8206 /* This is dependent on the next operand specifier
8207 is a base register specification. */
8208 assert (args
[1] == 'b' || args
[1] == '5'
8209 || args
[1] == '-' || args
[1] == '4');
8213 case ')': /* these must match exactly */
8220 case '+': /* Opcode extension character. */
8223 case 'A': /* ins/ext position, becomes LSB. */
8232 my_getExpression (&imm_expr
, s
);
8233 check_absolute_expr (ip
, &imm_expr
);
8234 if ((unsigned long) imm_expr
.X_add_number
< limlo
8235 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8237 as_bad (_("Improper position (%lu)"),
8238 (unsigned long) imm_expr
.X_add_number
);
8239 imm_expr
.X_add_number
= limlo
;
8241 lastpos
= imm_expr
.X_add_number
;
8242 ip
->insn_opcode
|= (imm_expr
.X_add_number
8243 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8244 imm_expr
.X_op
= O_absent
;
8248 case 'B': /* ins size, becomes MSB. */
8257 my_getExpression (&imm_expr
, s
);
8258 check_absolute_expr (ip
, &imm_expr
);
8259 /* Check for negative input so that small negative numbers
8260 will not succeed incorrectly. The checks against
8261 (pos+size) transitively check "size" itself,
8262 assuming that "pos" is reasonable. */
8263 if ((long) imm_expr
.X_add_number
< 0
8264 || ((unsigned long) imm_expr
.X_add_number
8266 || ((unsigned long) imm_expr
.X_add_number
8269 as_bad (_("Improper insert size (%lu, position %lu)"),
8270 (unsigned long) imm_expr
.X_add_number
,
8271 (unsigned long) lastpos
);
8272 imm_expr
.X_add_number
= limlo
- lastpos
;
8274 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8275 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8276 imm_expr
.X_op
= O_absent
;
8280 case 'C': /* ext size, becomes MSBD. */
8293 my_getExpression (&imm_expr
, s
);
8294 check_absolute_expr (ip
, &imm_expr
);
8295 /* Check for negative input so that small negative numbers
8296 will not succeed incorrectly. The checks against
8297 (pos+size) transitively check "size" itself,
8298 assuming that "pos" is reasonable. */
8299 if ((long) imm_expr
.X_add_number
< 0
8300 || ((unsigned long) imm_expr
.X_add_number
8302 || ((unsigned long) imm_expr
.X_add_number
8305 as_bad (_("Improper extract size (%lu, position %lu)"),
8306 (unsigned long) imm_expr
.X_add_number
,
8307 (unsigned long) lastpos
);
8308 imm_expr
.X_add_number
= limlo
- lastpos
;
8310 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8311 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8312 imm_expr
.X_op
= O_absent
;
8317 /* +D is for disassembly only; never match. */
8321 /* "+I" is like "I", except that imm2_expr is used. */
8322 my_getExpression (&imm2_expr
, s
);
8323 if (imm2_expr
.X_op
!= O_big
8324 && imm2_expr
.X_op
!= O_constant
)
8325 insn_error
= _("absolute expression required");
8326 normalize_constant_expr (&imm2_expr
);
8331 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8332 *args
, insn
->name
, insn
->args
);
8333 /* Further processing is fruitless. */
8338 case '<': /* must be at least one digit */
8340 * According to the manual, if the shift amount is greater
8341 * than 31 or less than 0, then the shift amount should be
8342 * mod 32. In reality the mips assembler issues an error.
8343 * We issue a warning and mask out all but the low 5 bits.
8345 my_getExpression (&imm_expr
, s
);
8346 check_absolute_expr (ip
, &imm_expr
);
8347 if ((unsigned long) imm_expr
.X_add_number
> 31)
8349 as_warn (_("Improper shift amount (%lu)"),
8350 (unsigned long) imm_expr
.X_add_number
);
8351 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8353 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8354 imm_expr
.X_op
= O_absent
;
8358 case '>': /* shift amount minus 32 */
8359 my_getExpression (&imm_expr
, s
);
8360 check_absolute_expr (ip
, &imm_expr
);
8361 if ((unsigned long) imm_expr
.X_add_number
< 32
8362 || (unsigned long) imm_expr
.X_add_number
> 63)
8364 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8365 imm_expr
.X_op
= O_absent
;
8369 case 'k': /* cache code */
8370 case 'h': /* prefx code */
8371 my_getExpression (&imm_expr
, s
);
8372 check_absolute_expr (ip
, &imm_expr
);
8373 if ((unsigned long) imm_expr
.X_add_number
> 31)
8375 as_warn (_("Invalid value for `%s' (%lu)"),
8377 (unsigned long) imm_expr
.X_add_number
);
8378 imm_expr
.X_add_number
&= 0x1f;
8381 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8383 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8384 imm_expr
.X_op
= O_absent
;
8388 case 'c': /* break code */
8389 my_getExpression (&imm_expr
, s
);
8390 check_absolute_expr (ip
, &imm_expr
);
8391 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8393 as_warn (_("Illegal break code (%lu)"),
8394 (unsigned long) imm_expr
.X_add_number
);
8395 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8397 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8398 imm_expr
.X_op
= O_absent
;
8402 case 'q': /* lower break code */
8403 my_getExpression (&imm_expr
, s
);
8404 check_absolute_expr (ip
, &imm_expr
);
8405 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8407 as_warn (_("Illegal lower break code (%lu)"),
8408 (unsigned long) imm_expr
.X_add_number
);
8409 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8411 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8412 imm_expr
.X_op
= O_absent
;
8416 case 'B': /* 20-bit syscall/break code. */
8417 my_getExpression (&imm_expr
, s
);
8418 check_absolute_expr (ip
, &imm_expr
);
8419 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8420 as_warn (_("Illegal 20-bit code (%lu)"),
8421 (unsigned long) imm_expr
.X_add_number
);
8422 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8423 imm_expr
.X_op
= O_absent
;
8427 case 'C': /* Coprocessor code */
8428 my_getExpression (&imm_expr
, s
);
8429 check_absolute_expr (ip
, &imm_expr
);
8430 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8432 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8433 (unsigned long) imm_expr
.X_add_number
);
8434 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8436 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8437 imm_expr
.X_op
= O_absent
;
8441 case 'J': /* 19-bit wait code. */
8442 my_getExpression (&imm_expr
, s
);
8443 check_absolute_expr (ip
, &imm_expr
);
8444 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8445 as_warn (_("Illegal 19-bit code (%lu)"),
8446 (unsigned long) imm_expr
.X_add_number
);
8447 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8448 imm_expr
.X_op
= O_absent
;
8452 case 'P': /* Performance register */
8453 my_getExpression (&imm_expr
, s
);
8454 check_absolute_expr (ip
, &imm_expr
);
8455 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8457 as_warn (_("Invalid performance register (%lu)"),
8458 (unsigned long) imm_expr
.X_add_number
);
8459 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8461 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8462 imm_expr
.X_op
= O_absent
;
8466 case 'b': /* base register */
8467 case 'd': /* destination register */
8468 case 's': /* source register */
8469 case 't': /* target register */
8470 case 'r': /* both target and source */
8471 case 'v': /* both dest and source */
8472 case 'w': /* both dest and target */
8473 case 'E': /* coprocessor target register */
8474 case 'G': /* coprocessor destination register */
8475 case 'K': /* 'rdhwr' destination register */
8476 case 'x': /* ignore register name */
8477 case 'z': /* must be zero register */
8478 case 'U': /* destination register (clo/clz). */
8493 while (ISDIGIT (*s
));
8495 as_bad (_("Invalid register number (%d)"), regno
);
8497 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8501 if (s
[1] == 'r' && s
[2] == 'a')
8506 else if (s
[1] == 'f' && s
[2] == 'p')
8511 else if (s
[1] == 's' && s
[2] == 'p')
8516 else if (s
[1] == 'g' && s
[2] == 'p')
8521 else if (s
[1] == 'a' && s
[2] == 't')
8526 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8531 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8536 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8541 else if (itbl_have_entries
)
8546 p
= s
+ 1; /* advance past '$' */
8547 n
= itbl_get_field (&p
); /* n is name */
8549 /* See if this is a register defined in an
8551 if (itbl_get_reg_val (n
, &r
))
8553 /* Get_field advances to the start of
8554 the next field, so we need to back
8555 rack to the end of the last field. */
8559 s
= strchr (s
, '\0');
8573 as_warn (_("Used $at without \".set noat\""));
8579 if (c
== 'r' || c
== 'v' || c
== 'w')
8586 /* 'z' only matches $0. */
8587 if (c
== 'z' && regno
!= 0)
8590 /* Now that we have assembled one operand, we use the args string
8591 * to figure out where it goes in the instruction. */
8598 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8603 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8606 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8607 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8612 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8615 /* This case exists because on the r3000 trunc
8616 expands into a macro which requires a gp
8617 register. On the r6000 or r4000 it is
8618 assembled into a single instruction which
8619 ignores the register. Thus the insn version
8620 is MIPS_ISA2 and uses 'x', and the macro
8621 version is MIPS_ISA1 and uses 't'. */
8624 /* This case is for the div instruction, which
8625 acts differently if the destination argument
8626 is $0. This only matches $0, and is checked
8627 outside the switch. */
8630 /* Itbl operand; not yet implemented. FIXME ?? */
8632 /* What about all other operands like 'i', which
8633 can be specified in the opcode table? */
8643 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8646 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8651 case 'O': /* MDMX alignment immediate constant. */
8652 my_getExpression (&imm_expr
, s
);
8653 check_absolute_expr (ip
, &imm_expr
);
8654 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8656 as_warn ("Improper align amount (%ld), using low bits",
8657 (long) imm_expr
.X_add_number
);
8658 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8660 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8661 imm_expr
.X_op
= O_absent
;
8665 case 'Q': /* MDMX vector, element sel, or const. */
8668 /* MDMX Immediate. */
8669 my_getExpression (&imm_expr
, s
);
8670 check_absolute_expr (ip
, &imm_expr
);
8671 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8673 as_warn (_("Invalid MDMX Immediate (%ld)"),
8674 (long) imm_expr
.X_add_number
);
8675 imm_expr
.X_add_number
&= OP_MASK_FT
;
8677 imm_expr
.X_add_number
&= OP_MASK_FT
;
8678 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8679 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8681 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8682 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8683 imm_expr
.X_op
= O_absent
;
8687 /* Not MDMX Immediate. Fall through. */
8688 case 'X': /* MDMX destination register. */
8689 case 'Y': /* MDMX source register. */
8690 case 'Z': /* MDMX target register. */
8692 case 'D': /* floating point destination register */
8693 case 'S': /* floating point source register */
8694 case 'T': /* floating point target register */
8695 case 'R': /* floating point source register */
8699 /* Accept $fN for FP and MDMX register numbers, and in
8700 addition accept $vN for MDMX register numbers. */
8701 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8702 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8713 while (ISDIGIT (*s
));
8716 as_bad (_("Invalid float register number (%d)"), regno
);
8718 if ((regno
& 1) != 0
8720 && ! (strcmp (str
, "mtc1") == 0
8721 || strcmp (str
, "mfc1") == 0
8722 || strcmp (str
, "lwc1") == 0
8723 || strcmp (str
, "swc1") == 0
8724 || strcmp (str
, "l.s") == 0
8725 || strcmp (str
, "s.s") == 0))
8726 as_warn (_("Float register should be even, was %d"),
8734 if (c
== 'V' || c
== 'W')
8745 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8750 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8753 /* This is like 'Z', but also needs to fix the MDMX
8754 vector/scalar select bits. Note that the
8755 scalar immediate case is handled above. */
8758 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8759 int max_el
= (is_qh
? 3 : 7);
8761 my_getExpression(&imm_expr
, s
);
8762 check_absolute_expr (ip
, &imm_expr
);
8764 if (imm_expr
.X_add_number
> max_el
)
8765 as_bad(_("Bad element selector %ld"),
8766 (long) imm_expr
.X_add_number
);
8767 imm_expr
.X_add_number
&= max_el
;
8768 ip
->insn_opcode
|= (imm_expr
.X_add_number
8772 as_warn(_("Expecting ']' found '%s'"), s
);
8778 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8779 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8782 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8789 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8792 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8802 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8805 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8811 my_getExpression (&imm_expr
, s
);
8812 if (imm_expr
.X_op
!= O_big
8813 && imm_expr
.X_op
!= O_constant
)
8814 insn_error
= _("absolute expression required");
8815 normalize_constant_expr (&imm_expr
);
8820 my_getExpression (&offset_expr
, s
);
8821 *imm_reloc
= BFD_RELOC_32
;
8834 unsigned char temp
[8];
8836 unsigned int length
;
8841 /* These only appear as the last operand in an
8842 instruction, and every instruction that accepts
8843 them in any variant accepts them in all variants.
8844 This means we don't have to worry about backing out
8845 any changes if the instruction does not match.
8847 The difference between them is the size of the
8848 floating point constant and where it goes. For 'F'
8849 and 'L' the constant is 64 bits; for 'f' and 'l' it
8850 is 32 bits. Where the constant is placed is based
8851 on how the MIPS assembler does things:
8854 f -- immediate value
8857 The .lit4 and .lit8 sections are only used if
8858 permitted by the -G argument.
8860 When generating embedded PIC code, we use the
8861 .lit8 section but not the .lit4 section (we can do
8862 .lit4 inline easily; we need to put .lit8
8863 somewhere in the data segment, and using .lit8
8864 permits the linker to eventually combine identical
8867 The code below needs to know whether the target register
8868 is 32 or 64 bits wide. It relies on the fact 'f' and
8869 'F' are used with GPR-based instructions and 'l' and
8870 'L' are used with FPR-based instructions. */
8872 f64
= *args
== 'F' || *args
== 'L';
8873 using_gprs
= *args
== 'F' || *args
== 'f';
8875 save_in
= input_line_pointer
;
8876 input_line_pointer
= s
;
8877 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8879 s
= input_line_pointer
;
8880 input_line_pointer
= save_in
;
8881 if (err
!= NULL
&& *err
!= '\0')
8883 as_bad (_("Bad floating point constant: %s"), err
);
8884 memset (temp
, '\0', sizeof temp
);
8885 length
= f64
? 8 : 4;
8888 assert (length
== (unsigned) (f64
? 8 : 4));
8892 && (mips_pic
== EMBEDDED_PIC
8893 || g_switch_value
< 4
8894 || (temp
[0] == 0 && temp
[1] == 0)
8895 || (temp
[2] == 0 && temp
[3] == 0))))
8897 imm_expr
.X_op
= O_constant
;
8898 if (! target_big_endian
)
8899 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8901 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8904 && ! mips_disable_float_construction
8905 /* Constants can only be constructed in GPRs and
8906 copied to FPRs if the GPRs are at least as wide
8907 as the FPRs. Force the constant into memory if
8908 we are using 64-bit FPRs but the GPRs are only
8911 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8912 && ((temp
[0] == 0 && temp
[1] == 0)
8913 || (temp
[2] == 0 && temp
[3] == 0))
8914 && ((temp
[4] == 0 && temp
[5] == 0)
8915 || (temp
[6] == 0 && temp
[7] == 0)))
8917 /* The value is simple enough to load with a couple of
8918 instructions. If using 32-bit registers, set
8919 imm_expr to the high order 32 bits and offset_expr to
8920 the low order 32 bits. Otherwise, set imm_expr to
8921 the entire 64 bit constant. */
8922 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8924 imm_expr
.X_op
= O_constant
;
8925 offset_expr
.X_op
= O_constant
;
8926 if (! target_big_endian
)
8928 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8929 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8933 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8934 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8936 if (offset_expr
.X_add_number
== 0)
8937 offset_expr
.X_op
= O_absent
;
8939 else if (sizeof (imm_expr
.X_add_number
) > 4)
8941 imm_expr
.X_op
= O_constant
;
8942 if (! target_big_endian
)
8943 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8945 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8949 imm_expr
.X_op
= O_big
;
8950 imm_expr
.X_add_number
= 4;
8951 if (! target_big_endian
)
8953 generic_bignum
[0] = bfd_getl16 (temp
);
8954 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8955 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8956 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8960 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8961 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8962 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8963 generic_bignum
[3] = bfd_getb16 (temp
);
8969 const char *newname
;
8972 /* Switch to the right section. */
8974 subseg
= now_subseg
;
8977 default: /* unused default case avoids warnings. */
8979 newname
= RDATA_SECTION_NAME
;
8980 if ((g_switch_value
>= 8)
8981 || mips_pic
== EMBEDDED_PIC
)
8985 if (mips_pic
== EMBEDDED_PIC
)
8988 newname
= RDATA_SECTION_NAME
;
8991 assert (g_switch_value
>= 4);
8995 new_seg
= subseg_new (newname
, (subsegT
) 0);
8996 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8997 bfd_set_section_flags (stdoutput
, new_seg
,
9002 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9003 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9004 && strcmp (TARGET_OS
, "elf") != 0)
9005 record_alignment (new_seg
, 4);
9007 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9009 as_bad (_("Can't use floating point insn in this section"));
9011 /* Set the argument to the current address in the
9013 offset_expr
.X_op
= O_symbol
;
9014 offset_expr
.X_add_symbol
=
9015 symbol_new ("L0\001", now_seg
,
9016 (valueT
) frag_now_fix (), frag_now
);
9017 offset_expr
.X_add_number
= 0;
9019 /* Put the floating point number into the section. */
9020 p
= frag_more ((int) length
);
9021 memcpy (p
, temp
, length
);
9023 /* Switch back to the original section. */
9024 subseg_set (seg
, subseg
);
9029 case 'i': /* 16 bit unsigned immediate */
9030 case 'j': /* 16 bit signed immediate */
9031 *imm_reloc
= BFD_RELOC_LO16
;
9032 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9035 offsetT minval
, maxval
;
9037 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9038 && strcmp (insn
->name
, insn
[1].name
) == 0);
9040 /* If the expression was written as an unsigned number,
9041 only treat it as signed if there are no more
9045 && sizeof (imm_expr
.X_add_number
) <= 4
9046 && imm_expr
.X_op
== O_constant
9047 && imm_expr
.X_add_number
< 0
9048 && imm_expr
.X_unsigned
9052 /* For compatibility with older assemblers, we accept
9053 0x8000-0xffff as signed 16-bit numbers when only
9054 signed numbers are allowed. */
9056 minval
= 0, maxval
= 0xffff;
9058 minval
= -0x8000, maxval
= 0x7fff;
9060 minval
= -0x8000, maxval
= 0xffff;
9062 if (imm_expr
.X_op
!= O_constant
9063 || imm_expr
.X_add_number
< minval
9064 || imm_expr
.X_add_number
> maxval
)
9068 if (imm_expr
.X_op
== O_constant
9069 || imm_expr
.X_op
== O_big
)
9070 as_bad (_("expression out of range"));
9076 case 'o': /* 16 bit offset */
9077 /* Check whether there is only a single bracketed expression
9078 left. If so, it must be the base register and the
9079 constant must be zero. */
9080 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9082 offset_expr
.X_op
= O_constant
;
9083 offset_expr
.X_add_number
= 0;
9087 /* If this value won't fit into a 16 bit offset, then go
9088 find a macro that will generate the 32 bit offset
9090 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9091 && (offset_expr
.X_op
!= O_constant
9092 || offset_expr
.X_add_number
>= 0x8000
9093 || offset_expr
.X_add_number
< -0x8000))
9099 case 'p': /* pc relative offset */
9100 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9101 my_getExpression (&offset_expr
, s
);
9105 case 'u': /* upper 16 bits */
9106 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9107 && imm_expr
.X_op
== O_constant
9108 && (imm_expr
.X_add_number
< 0
9109 || imm_expr
.X_add_number
>= 0x10000))
9110 as_bad (_("lui expression not in range 0..65535"));
9114 case 'a': /* 26 bit address */
9115 my_getExpression (&offset_expr
, s
);
9117 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9120 case 'N': /* 3 bit branch condition code */
9121 case 'M': /* 3 bit compare condition code */
9122 if (strncmp (s
, "$fcc", 4) != 0)
9132 while (ISDIGIT (*s
));
9134 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9135 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9136 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9137 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9138 && (regno
& 1) != 0)
9139 as_warn(_("Condition code register should be even for %s, was %d"),
9141 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9142 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9143 && (regno
& 3) != 0)
9144 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9147 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9149 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9153 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9164 while (ISDIGIT (*s
));
9167 c
= 8; /* Invalid sel value. */
9170 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9171 ip
->insn_opcode
|= c
;
9175 /* Must be at least one digit. */
9176 my_getExpression (&imm_expr
, s
);
9177 check_absolute_expr (ip
, &imm_expr
);
9179 if ((unsigned long) imm_expr
.X_add_number
9180 > (unsigned long) OP_MASK_VECBYTE
)
9182 as_bad (_("bad byte vector index (%ld)"),
9183 (long) imm_expr
.X_add_number
);
9184 imm_expr
.X_add_number
= 0;
9187 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9188 imm_expr
.X_op
= O_absent
;
9193 my_getExpression (&imm_expr
, s
);
9194 check_absolute_expr (ip
, &imm_expr
);
9196 if ((unsigned long) imm_expr
.X_add_number
9197 > (unsigned long) OP_MASK_VECALIGN
)
9199 as_bad (_("bad byte vector index (%ld)"),
9200 (long) imm_expr
.X_add_number
);
9201 imm_expr
.X_add_number
= 0;
9204 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9205 imm_expr
.X_op
= O_absent
;
9210 as_bad (_("bad char = '%c'\n"), *args
);
9215 /* Args don't match. */
9216 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9217 !strcmp (insn
->name
, insn
[1].name
))
9221 insn_error
= _("illegal operands");
9226 insn_error
= _("illegal operands");
9231 /* This routine assembles an instruction into its binary format when
9232 assembling for the mips16. As a side effect, it sets one of the
9233 global variables imm_reloc or offset_reloc to the type of
9234 relocation to do if one of the operands is an address expression.
9235 It also sets mips16_small and mips16_ext if the user explicitly
9236 requested a small or extended instruction. */
9239 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9243 struct mips_opcode
*insn
;
9246 unsigned int lastregno
= 0;
9251 mips16_small
= FALSE
;
9254 for (s
= str
; ISLOWER (*s
); ++s
)
9266 if (s
[1] == 't' && s
[2] == ' ')
9269 mips16_small
= TRUE
;
9273 else if (s
[1] == 'e' && s
[2] == ' ')
9282 insn_error
= _("unknown opcode");
9286 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9287 mips16_small
= TRUE
;
9289 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9291 insn_error
= _("unrecognized opcode");
9298 assert (strcmp (insn
->name
, str
) == 0);
9301 ip
->insn_opcode
= insn
->match
;
9302 ip
->use_extend
= FALSE
;
9303 imm_expr
.X_op
= O_absent
;
9304 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9305 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9306 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9307 imm2_expr
.X_op
= O_absent
;
9308 offset_expr
.X_op
= O_absent
;
9309 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9310 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9311 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9312 for (args
= insn
->args
; 1; ++args
)
9319 /* In this switch statement we call break if we did not find
9320 a match, continue if we did find a match, or return if we
9329 /* Stuff the immediate value in now, if we can. */
9330 if (imm_expr
.X_op
== O_constant
9331 && *imm_reloc
> BFD_RELOC_UNUSED
9332 && insn
->pinfo
!= INSN_MACRO
)
9334 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9335 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9336 mips16_ext
, &ip
->insn_opcode
,
9337 &ip
->use_extend
, &ip
->extend
);
9338 imm_expr
.X_op
= O_absent
;
9339 *imm_reloc
= BFD_RELOC_UNUSED
;
9353 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9356 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9372 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9374 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9401 while (ISDIGIT (*s
));
9404 as_bad (_("invalid register number (%d)"), regno
);
9410 if (s
[1] == 'r' && s
[2] == 'a')
9415 else if (s
[1] == 'f' && s
[2] == 'p')
9420 else if (s
[1] == 's' && s
[2] == 'p')
9425 else if (s
[1] == 'g' && s
[2] == 'p')
9430 else if (s
[1] == 'a' && s
[2] == 't')
9435 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9440 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9445 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9458 if (c
== 'v' || c
== 'w')
9460 regno
= mips16_to_32_reg_map
[lastregno
];
9474 regno
= mips32_to_16_reg_map
[regno
];
9479 regno
= ILLEGAL_REG
;
9484 regno
= ILLEGAL_REG
;
9489 regno
= ILLEGAL_REG
;
9494 if (regno
== AT
&& ! mips_opts
.noat
)
9495 as_warn (_("used $at without \".set noat\""));
9502 if (regno
== ILLEGAL_REG
)
9509 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9513 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9516 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9519 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9525 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9528 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9529 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9539 if (strncmp (s
, "$pc", 3) == 0)
9563 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9565 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9566 and generate the appropriate reloc. If the text
9567 inside %gprel is not a symbol name with an
9568 optional offset, then we generate a normal reloc
9569 and will probably fail later. */
9570 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9571 if (imm_expr
.X_op
== O_symbol
)
9574 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9576 ip
->use_extend
= TRUE
;
9583 /* Just pick up a normal expression. */
9584 my_getExpression (&imm_expr
, s
);
9587 if (imm_expr
.X_op
== O_register
)
9589 /* What we thought was an expression turned out to
9592 if (s
[0] == '(' && args
[1] == '(')
9594 /* It looks like the expression was omitted
9595 before a register indirection, which means
9596 that the expression is implicitly zero. We
9597 still set up imm_expr, so that we handle
9598 explicit extensions correctly. */
9599 imm_expr
.X_op
= O_constant
;
9600 imm_expr
.X_add_number
= 0;
9601 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9608 /* We need to relax this instruction. */
9609 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9618 /* We use offset_reloc rather than imm_reloc for the PC
9619 relative operands. This lets macros with both
9620 immediate and address operands work correctly. */
9621 my_getExpression (&offset_expr
, s
);
9623 if (offset_expr
.X_op
== O_register
)
9626 /* We need to relax this instruction. */
9627 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9631 case '6': /* break code */
9632 my_getExpression (&imm_expr
, s
);
9633 check_absolute_expr (ip
, &imm_expr
);
9634 if ((unsigned long) imm_expr
.X_add_number
> 63)
9636 as_warn (_("Invalid value for `%s' (%lu)"),
9638 (unsigned long) imm_expr
.X_add_number
);
9639 imm_expr
.X_add_number
&= 0x3f;
9641 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9642 imm_expr
.X_op
= O_absent
;
9646 case 'a': /* 26 bit address */
9647 my_getExpression (&offset_expr
, s
);
9649 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9650 ip
->insn_opcode
<<= 16;
9653 case 'l': /* register list for entry macro */
9654 case 'L': /* register list for exit macro */
9664 int freg
, reg1
, reg2
;
9666 while (*s
== ' ' || *s
== ',')
9670 as_bad (_("can't parse register list"));
9682 while (ISDIGIT (*s
))
9704 as_bad (_("invalid register list"));
9709 while (ISDIGIT (*s
))
9716 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9721 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9726 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9727 mask
|= (reg2
- 3) << 3;
9728 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9729 mask
|= (reg2
- 15) << 1;
9730 else if (reg1
== RA
&& reg2
== RA
)
9734 as_bad (_("invalid register list"));
9738 /* The mask is filled in in the opcode table for the
9739 benefit of the disassembler. We remove it before
9740 applying the actual mask. */
9741 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9742 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9746 case 'e': /* extend code */
9747 my_getExpression (&imm_expr
, s
);
9748 check_absolute_expr (ip
, &imm_expr
);
9749 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9751 as_warn (_("Invalid value for `%s' (%lu)"),
9753 (unsigned long) imm_expr
.X_add_number
);
9754 imm_expr
.X_add_number
&= 0x7ff;
9756 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9757 imm_expr
.X_op
= O_absent
;
9767 /* Args don't match. */
9768 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9769 strcmp (insn
->name
, insn
[1].name
) == 0)
9776 insn_error
= _("illegal operands");
9782 /* This structure holds information we know about a mips16 immediate
9785 struct mips16_immed_operand
9787 /* The type code used in the argument string in the opcode table. */
9789 /* The number of bits in the short form of the opcode. */
9791 /* The number of bits in the extended form of the opcode. */
9793 /* The amount by which the short form is shifted when it is used;
9794 for example, the sw instruction has a shift count of 2. */
9796 /* The amount by which the short form is shifted when it is stored
9797 into the instruction code. */
9799 /* Non-zero if the short form is unsigned. */
9801 /* Non-zero if the extended form is unsigned. */
9803 /* Non-zero if the value is PC relative. */
9807 /* The mips16 immediate operand types. */
9809 static const struct mips16_immed_operand mips16_immed_operands
[] =
9811 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9812 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9813 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9814 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9815 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9816 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9817 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9818 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9819 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9820 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9821 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9822 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9823 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9824 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9825 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9826 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9827 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9828 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9829 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9830 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9831 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9834 #define MIPS16_NUM_IMMED \
9835 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9837 /* Handle a mips16 instruction with an immediate value. This or's the
9838 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9839 whether an extended value is needed; if one is needed, it sets
9840 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9841 If SMALL is true, an unextended opcode was explicitly requested.
9842 If EXT is true, an extended opcode was explicitly requested. If
9843 WARN is true, warn if EXT does not match reality. */
9846 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9847 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9848 unsigned long *insn
, bfd_boolean
*use_extend
,
9849 unsigned short *extend
)
9851 register const struct mips16_immed_operand
*op
;
9852 int mintiny
, maxtiny
;
9853 bfd_boolean needext
;
9855 op
= mips16_immed_operands
;
9856 while (op
->type
!= type
)
9859 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9864 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9867 maxtiny
= 1 << op
->nbits
;
9872 maxtiny
= (1 << op
->nbits
) - 1;
9877 mintiny
= - (1 << (op
->nbits
- 1));
9878 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9881 /* Branch offsets have an implicit 0 in the lowest bit. */
9882 if (type
== 'p' || type
== 'q')
9885 if ((val
& ((1 << op
->shift
) - 1)) != 0
9886 || val
< (mintiny
<< op
->shift
)
9887 || val
> (maxtiny
<< op
->shift
))
9892 if (warn
&& ext
&& ! needext
)
9893 as_warn_where (file
, line
,
9894 _("extended operand requested but not required"));
9895 if (small
&& needext
)
9896 as_bad_where (file
, line
, _("invalid unextended operand value"));
9898 if (small
|| (! ext
&& ! needext
))
9902 *use_extend
= FALSE
;
9903 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9904 insnval
<<= op
->op_shift
;
9909 long minext
, maxext
;
9915 maxext
= (1 << op
->extbits
) - 1;
9919 minext
= - (1 << (op
->extbits
- 1));
9920 maxext
= (1 << (op
->extbits
- 1)) - 1;
9922 if (val
< minext
|| val
> maxext
)
9923 as_bad_where (file
, line
,
9924 _("operand value out of range for instruction"));
9927 if (op
->extbits
== 16)
9929 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9932 else if (op
->extbits
== 15)
9934 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9939 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9943 *extend
= (unsigned short) extval
;
9948 static const struct percent_op_match
9951 bfd_reloc_code_real_type reloc
;
9954 {"%lo", BFD_RELOC_LO16
},
9956 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9957 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9958 {"%call16", BFD_RELOC_MIPS_CALL16
},
9959 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9960 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9961 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9962 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9963 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9964 {"%got", BFD_RELOC_MIPS_GOT16
},
9965 {"%gp_rel", BFD_RELOC_GPREL16
},
9966 {"%half", BFD_RELOC_16
},
9967 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9968 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9969 {"%neg", BFD_RELOC_MIPS_SUB
},
9971 {"%hi", BFD_RELOC_HI16_S
}
9975 /* Return true if *STR points to a relocation operator. When returning true,
9976 move *STR over the operator and store its relocation code in *RELOC.
9977 Leave both *STR and *RELOC alone when returning false. */
9980 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9984 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9985 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9987 *str
+= strlen (percent_op
[i
].str
);
9988 *reloc
= percent_op
[i
].reloc
;
9990 /* Check whether the output BFD supports this relocation.
9991 If not, issue an error and fall back on something safe. */
9992 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9994 as_bad ("relocation %s isn't supported by the current ABI",
9996 *reloc
= BFD_RELOC_LO16
;
10004 /* Parse string STR as a 16-bit relocatable operand. Store the
10005 expression in *EP and the relocations in the array starting
10006 at RELOC. Return the number of relocation operators used.
10008 On exit, EXPR_END points to the first character after the expression.
10009 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10012 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10015 bfd_reloc_code_real_type reversed_reloc
[3];
10016 size_t reloc_index
, i
;
10017 int crux_depth
, str_depth
;
10020 /* Search for the start of the main expression, recoding relocations
10021 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10022 of the main expression and with CRUX_DEPTH containing the number
10023 of open brackets at that point. */
10030 crux_depth
= str_depth
;
10032 /* Skip over whitespace and brackets, keeping count of the number
10034 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10039 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10040 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10042 my_getExpression (ep
, crux
);
10045 /* Match every open bracket. */
10046 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10050 if (crux_depth
> 0)
10051 as_bad ("unclosed '('");
10055 if (reloc_index
== 0)
10056 reloc
[0] = BFD_RELOC_LO16
;
10059 prev_reloc_op_frag
= frag_now
;
10060 for (i
= 0; i
< reloc_index
; i
++)
10061 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10064 return reloc_index
;
10068 my_getExpression (expressionS
*ep
, char *str
)
10073 save_in
= input_line_pointer
;
10074 input_line_pointer
= str
;
10076 expr_end
= input_line_pointer
;
10077 input_line_pointer
= save_in
;
10079 /* If we are in mips16 mode, and this is an expression based on `.',
10080 then we bump the value of the symbol by 1 since that is how other
10081 text symbols are handled. We don't bother to handle complex
10082 expressions, just `.' plus or minus a constant. */
10083 if (mips_opts
.mips16
10084 && ep
->X_op
== O_symbol
10085 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10086 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10087 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10088 && symbol_constant_p (ep
->X_add_symbol
)
10089 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10090 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10093 /* Turn a string in input_line_pointer into a floating point constant
10094 of type TYPE, and store the appropriate bytes in *LITP. The number
10095 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10096 returned, or NULL on OK. */
10099 md_atof (int type
, char *litP
, int *sizeP
)
10102 LITTLENUM_TYPE words
[4];
10118 return _("bad call to md_atof");
10121 t
= atof_ieee (input_line_pointer
, type
, words
);
10123 input_line_pointer
= t
;
10127 if (! target_big_endian
)
10129 for (i
= prec
- 1; i
>= 0; i
--)
10131 md_number_to_chars (litP
, words
[i
], 2);
10137 for (i
= 0; i
< prec
; i
++)
10139 md_number_to_chars (litP
, words
[i
], 2);
10148 md_number_to_chars (char *buf
, valueT val
, int n
)
10150 if (target_big_endian
)
10151 number_to_chars_bigendian (buf
, val
, n
);
10153 number_to_chars_littleendian (buf
, val
, n
);
10157 static int support_64bit_objects(void)
10159 const char **list
, **l
;
10162 list
= bfd_target_list ();
10163 for (l
= list
; *l
!= NULL
; l
++)
10165 /* This is traditional mips */
10166 if (strcmp (*l
, "elf64-tradbigmips") == 0
10167 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10169 if (strcmp (*l
, "elf64-bigmips") == 0
10170 || strcmp (*l
, "elf64-littlemips") == 0)
10173 yes
= (*l
!= NULL
);
10177 #endif /* OBJ_ELF */
10179 const char *md_shortopts
= "O::g::G:";
10181 struct option md_longopts
[] =
10183 /* Options which specify architecture. */
10184 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10185 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10186 {"march", required_argument
, NULL
, OPTION_MARCH
},
10187 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10188 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10189 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10190 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10191 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10192 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10193 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10194 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10195 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10196 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10197 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10198 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10199 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10200 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10201 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10202 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10203 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10204 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10205 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10206 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10207 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10209 /* Options which specify Application Specific Extensions (ASEs). */
10210 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10211 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10212 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10213 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10214 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10215 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10216 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10217 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10218 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10219 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10220 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10221 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10222 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10224 /* Old-style architecture options. Don't add more of these. */
10225 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10226 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10227 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10228 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10229 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10230 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10231 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10232 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10233 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10234 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10235 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10236 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10237 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10238 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10239 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10240 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10241 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10243 /* Options which enable bug fixes. */
10244 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10245 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10246 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10247 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10248 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10249 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10250 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10251 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10252 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10253 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10255 /* Miscellaneous options. */
10256 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10257 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10258 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10259 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10260 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10261 {"break", no_argument
, NULL
, OPTION_BREAK
},
10262 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10263 #define OPTION_EB (OPTION_MISC_BASE + 2)
10264 {"EB", no_argument
, NULL
, OPTION_EB
},
10265 #define OPTION_EL (OPTION_MISC_BASE + 3)
10266 {"EL", no_argument
, NULL
, OPTION_EL
},
10267 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10268 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10269 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10270 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10271 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10272 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10273 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10274 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10275 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10276 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10277 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10278 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10279 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10280 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10281 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10282 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10284 /* ELF-specific options. */
10286 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
10287 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10288 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10289 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10290 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10291 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10292 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10293 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10294 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10295 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10296 #define OPTION_32 (OPTION_ELF_BASE + 4)
10297 {"32", no_argument
, NULL
, OPTION_32
},
10298 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10299 {"n32", no_argument
, NULL
, OPTION_N32
},
10300 #define OPTION_64 (OPTION_ELF_BASE + 6)
10301 {"64", no_argument
, NULL
, OPTION_64
},
10302 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10303 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10304 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10305 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10306 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10307 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10308 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10309 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10310 #endif /* OBJ_ELF */
10312 {NULL
, no_argument
, NULL
, 0}
10314 size_t md_longopts_size
= sizeof (md_longopts
);
10316 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10317 NEW_VALUE. Warn if another value was already specified. Note:
10318 we have to defer parsing the -march and -mtune arguments in order
10319 to handle 'from-abi' correctly, since the ABI might be specified
10320 in a later argument. */
10323 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10325 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10326 as_warn (_("A different %s was already specified, is now %s"),
10327 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10330 *string_ptr
= new_value
;
10334 md_parse_option (int c
, char *arg
)
10338 case OPTION_CONSTRUCT_FLOATS
:
10339 mips_disable_float_construction
= 0;
10342 case OPTION_NO_CONSTRUCT_FLOATS
:
10343 mips_disable_float_construction
= 1;
10355 target_big_endian
= 1;
10359 target_big_endian
= 0;
10363 if (arg
&& arg
[1] == '0')
10373 mips_debug
= atoi (arg
);
10374 /* When the MIPS assembler sees -g or -g2, it does not do
10375 optimizations which limit full symbolic debugging. We take
10376 that to be equivalent to -O0. */
10377 if (mips_debug
== 2)
10382 file_mips_isa
= ISA_MIPS1
;
10386 file_mips_isa
= ISA_MIPS2
;
10390 file_mips_isa
= ISA_MIPS3
;
10394 file_mips_isa
= ISA_MIPS4
;
10398 file_mips_isa
= ISA_MIPS5
;
10401 case OPTION_MIPS32
:
10402 file_mips_isa
= ISA_MIPS32
;
10405 case OPTION_MIPS32R2
:
10406 file_mips_isa
= ISA_MIPS32R2
;
10409 case OPTION_MIPS64R2
:
10410 file_mips_isa
= ISA_MIPS64R2
;
10413 case OPTION_MIPS64
:
10414 file_mips_isa
= ISA_MIPS64
;
10418 mips_set_option_string (&mips_tune_string
, arg
);
10422 mips_set_option_string (&mips_arch_string
, arg
);
10426 mips_set_option_string (&mips_arch_string
, "4650");
10427 mips_set_option_string (&mips_tune_string
, "4650");
10430 case OPTION_NO_M4650
:
10434 mips_set_option_string (&mips_arch_string
, "4010");
10435 mips_set_option_string (&mips_tune_string
, "4010");
10438 case OPTION_NO_M4010
:
10442 mips_set_option_string (&mips_arch_string
, "4100");
10443 mips_set_option_string (&mips_tune_string
, "4100");
10446 case OPTION_NO_M4100
:
10450 mips_set_option_string (&mips_arch_string
, "3900");
10451 mips_set_option_string (&mips_tune_string
, "3900");
10454 case OPTION_NO_M3900
:
10458 mips_opts
.ase_mdmx
= 1;
10461 case OPTION_NO_MDMX
:
10462 mips_opts
.ase_mdmx
= 0;
10465 case OPTION_MIPS16
:
10466 mips_opts
.mips16
= 1;
10467 mips_no_prev_insn (FALSE
);
10470 case OPTION_NO_MIPS16
:
10471 mips_opts
.mips16
= 0;
10472 mips_no_prev_insn (FALSE
);
10475 case OPTION_MIPS3D
:
10476 mips_opts
.ase_mips3d
= 1;
10479 case OPTION_NO_MIPS3D
:
10480 mips_opts
.ase_mips3d
= 0;
10483 case OPTION_FIX_VR4120
:
10484 mips_fix_vr4120
= 1;
10487 case OPTION_NO_FIX_VR4120
:
10488 mips_fix_vr4120
= 0;
10491 case OPTION_RELAX_BRANCH
:
10492 mips_relax_branch
= 1;
10495 case OPTION_NO_RELAX_BRANCH
:
10496 mips_relax_branch
= 0;
10500 /* When generating ELF code, we permit -KPIC and -call_shared to
10501 select SVR4_PIC, and -non_shared to select no PIC. This is
10502 intended to be compatible with Irix 5. */
10503 case OPTION_CALL_SHARED
:
10504 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10506 as_bad (_("-call_shared is supported only for ELF format"));
10509 mips_pic
= SVR4_PIC
;
10510 mips_abicalls
= TRUE
;
10511 if (g_switch_seen
&& g_switch_value
!= 0)
10513 as_bad (_("-G may not be used with SVR4 PIC code"));
10516 g_switch_value
= 0;
10519 case OPTION_NON_SHARED
:
10520 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10522 as_bad (_("-non_shared is supported only for ELF format"));
10526 mips_abicalls
= FALSE
;
10529 /* The -xgot option tells the assembler to use 32 offsets when
10530 accessing the got in SVR4_PIC mode. It is for Irix
10535 #endif /* OBJ_ELF */
10538 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10540 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10544 g_switch_value
= atoi (arg
);
10549 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10552 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10554 as_bad (_("-32 is supported for ELF format only"));
10557 mips_abi
= O32_ABI
;
10561 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10563 as_bad (_("-n32 is supported for ELF format only"));
10566 mips_abi
= N32_ABI
;
10570 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10572 as_bad (_("-64 is supported for ELF format only"));
10575 mips_abi
= N64_ABI
;
10576 if (! support_64bit_objects())
10577 as_fatal (_("No compiled in support for 64 bit object file format"));
10579 #endif /* OBJ_ELF */
10582 file_mips_gp32
= 1;
10586 file_mips_gp32
= 0;
10590 file_mips_fp32
= 1;
10594 file_mips_fp32
= 0;
10599 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10601 as_bad (_("-mabi is supported for ELF format only"));
10604 if (strcmp (arg
, "32") == 0)
10605 mips_abi
= O32_ABI
;
10606 else if (strcmp (arg
, "o64") == 0)
10607 mips_abi
= O64_ABI
;
10608 else if (strcmp (arg
, "n32") == 0)
10609 mips_abi
= N32_ABI
;
10610 else if (strcmp (arg
, "64") == 0)
10612 mips_abi
= N64_ABI
;
10613 if (! support_64bit_objects())
10614 as_fatal (_("No compiled in support for 64 bit object file "
10617 else if (strcmp (arg
, "eabi") == 0)
10618 mips_abi
= EABI_ABI
;
10621 as_fatal (_("invalid abi -mabi=%s"), arg
);
10625 #endif /* OBJ_ELF */
10627 case OPTION_M7000_HILO_FIX
:
10628 mips_7000_hilo_fix
= TRUE
;
10631 case OPTION_MNO_7000_HILO_FIX
:
10632 mips_7000_hilo_fix
= FALSE
;
10636 case OPTION_MDEBUG
:
10637 mips_flag_mdebug
= TRUE
;
10640 case OPTION_NO_MDEBUG
:
10641 mips_flag_mdebug
= FALSE
;
10645 mips_flag_pdr
= TRUE
;
10648 case OPTION_NO_PDR
:
10649 mips_flag_pdr
= FALSE
;
10651 #endif /* OBJ_ELF */
10660 /* Set up globals to generate code for the ISA or processor
10661 described by INFO. */
10664 mips_set_architecture (const struct mips_cpu_info
*info
)
10668 file_mips_arch
= info
->cpu
;
10669 mips_opts
.arch
= info
->cpu
;
10670 mips_opts
.isa
= info
->isa
;
10675 /* Likewise for tuning. */
10678 mips_set_tune (const struct mips_cpu_info
*info
)
10681 mips_tune
= info
->cpu
;
10686 mips_after_parse_args (void)
10688 const struct mips_cpu_info
*arch_info
= 0;
10689 const struct mips_cpu_info
*tune_info
= 0;
10691 /* GP relative stuff not working for PE */
10692 if (strncmp (TARGET_OS
, "pe", 2) == 0
10693 && g_switch_value
!= 0)
10696 as_bad (_("-G not supported in this configuration."));
10697 g_switch_value
= 0;
10700 if (mips_abi
== NO_ABI
)
10701 mips_abi
= MIPS_DEFAULT_ABI
;
10703 /* The following code determines the architecture and register size.
10704 Similar code was added to GCC 3.3 (see override_options() in
10705 config/mips/mips.c). The GAS and GCC code should be kept in sync
10706 as much as possible. */
10708 if (mips_arch_string
!= 0)
10709 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10711 if (file_mips_isa
!= ISA_UNKNOWN
)
10713 /* Handle -mipsN. At this point, file_mips_isa contains the
10714 ISA level specified by -mipsN, while arch_info->isa contains
10715 the -march selection (if any). */
10716 if (arch_info
!= 0)
10718 /* -march takes precedence over -mipsN, since it is more descriptive.
10719 There's no harm in specifying both as long as the ISA levels
10721 if (file_mips_isa
!= arch_info
->isa
)
10722 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10723 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10724 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10727 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10730 if (arch_info
== 0)
10731 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10733 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10734 as_bad ("-march=%s is not compatible with the selected ABI",
10737 mips_set_architecture (arch_info
);
10739 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10740 if (mips_tune_string
!= 0)
10741 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10743 if (tune_info
== 0)
10744 mips_set_tune (arch_info
);
10746 mips_set_tune (tune_info
);
10748 if (file_mips_gp32
>= 0)
10750 /* The user specified the size of the integer registers. Make sure
10751 it agrees with the ABI and ISA. */
10752 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10753 as_bad (_("-mgp64 used with a 32-bit processor"));
10754 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10755 as_bad (_("-mgp32 used with a 64-bit ABI"));
10756 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10757 as_bad (_("-mgp64 used with a 32-bit ABI"));
10761 /* Infer the integer register size from the ABI and processor.
10762 Restrict ourselves to 32-bit registers if that's all the
10763 processor has, or if the ABI cannot handle 64-bit registers. */
10764 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10765 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10768 /* ??? GAS treats single-float processors as though they had 64-bit
10769 float registers (although it complains when double-precision
10770 instructions are used). As things stand, saying they have 32-bit
10771 registers would lead to spurious "register must be even" messages.
10772 So here we assume float registers are always the same size as
10773 integer ones, unless the user says otherwise. */
10774 if (file_mips_fp32
< 0)
10775 file_mips_fp32
= file_mips_gp32
;
10777 /* End of GCC-shared inference code. */
10779 /* This flag is set when we have a 64-bit capable CPU but use only
10780 32-bit wide registers. Note that EABI does not use it. */
10781 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10782 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10783 || mips_abi
== O32_ABI
))
10784 mips_32bitmode
= 1;
10786 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10787 as_bad (_("trap exception not supported at ISA 1"));
10789 /* If the selected architecture includes support for ASEs, enable
10790 generation of code for them. */
10791 if (mips_opts
.mips16
== -1)
10792 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10793 if (mips_opts
.ase_mips3d
== -1)
10794 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10795 if (mips_opts
.ase_mdmx
== -1)
10796 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10798 file_mips_isa
= mips_opts
.isa
;
10799 file_ase_mips16
= mips_opts
.mips16
;
10800 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10801 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10802 mips_opts
.gp32
= file_mips_gp32
;
10803 mips_opts
.fp32
= file_mips_fp32
;
10805 if (mips_flag_mdebug
< 0)
10807 #ifdef OBJ_MAYBE_ECOFF
10808 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10809 mips_flag_mdebug
= 1;
10811 #endif /* OBJ_MAYBE_ECOFF */
10812 mips_flag_mdebug
= 0;
10817 mips_init_after_args (void)
10819 /* initialize opcodes */
10820 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10821 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10825 md_pcrel_from (fixS
*fixP
)
10827 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10828 switch (fixP
->fx_r_type
)
10830 case BFD_RELOC_16_PCREL_S2
:
10831 case BFD_RELOC_MIPS_JMP
:
10832 /* Return the address of the delay slot. */
10839 /* This is called before the symbol table is processed. In order to
10840 work with gcc when using mips-tfile, we must keep all local labels.
10841 However, in other cases, we want to discard them. If we were
10842 called with -g, but we didn't see any debugging information, it may
10843 mean that gcc is smuggling debugging information through to
10844 mips-tfile, in which case we must generate all local labels. */
10847 mips_frob_file_before_adjust (void)
10849 #ifndef NO_ECOFF_DEBUGGING
10850 if (ECOFF_DEBUGGING
10852 && ! ecoff_debugging_seen
)
10853 flag_keep_locals
= 1;
10857 /* Sort any unmatched HI16_S relocs so that they immediately precede
10858 the corresponding LO reloc. This is called before md_apply_fix3 and
10859 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10860 explicit use of the %hi modifier. */
10863 mips_frob_file (void)
10865 struct mips_hi_fixup
*l
;
10867 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10869 segment_info_type
*seginfo
;
10872 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10874 /* If a GOT16 relocation turns out to be against a global symbol,
10875 there isn't supposed to be a matching LO. */
10876 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10877 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10880 /* Check quickly whether the next fixup happens to be a matching %lo. */
10881 if (fixup_has_matching_lo_p (l
->fixp
))
10884 /* Look through the fixups for this segment for a matching %lo.
10885 When we find one, move the %hi just in front of it. We do
10886 this in two passes. In the first pass, we try to find a
10887 unique %lo. In the second pass, we permit multiple %hi
10888 relocs for a single %lo (this is a GNU extension). */
10889 seginfo
= seg_info (l
->seg
);
10890 for (pass
= 0; pass
< 2; pass
++)
10895 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10897 /* Check whether this is a %lo fixup which matches l->fixp. */
10898 if (f
->fx_r_type
== BFD_RELOC_LO16
10899 && f
->fx_addsy
== l
->fixp
->fx_addsy
10900 && f
->fx_offset
== l
->fixp
->fx_offset
10903 || !reloc_needs_lo_p (prev
->fx_r_type
)
10904 || !fixup_has_matching_lo_p (prev
)))
10908 /* Move l->fixp before f. */
10909 for (pf
= &seginfo
->fix_root
;
10911 pf
= &(*pf
)->fx_next
)
10912 assert (*pf
!= NULL
);
10914 *pf
= l
->fixp
->fx_next
;
10916 l
->fixp
->fx_next
= f
;
10918 seginfo
->fix_root
= l
->fixp
;
10920 prev
->fx_next
= l
->fixp
;
10931 #if 0 /* GCC code motion plus incomplete dead code elimination
10932 can leave a %hi without a %lo. */
10934 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10935 _("Unmatched %%hi reloc"));
10941 /* When generating embedded PIC code we need to use a special
10942 relocation to represent the difference of two symbols in the .text
10943 section (switch tables use a difference of this sort). See
10944 include/coff/mips.h for details. This macro checks whether this
10945 fixup requires the special reloc. */
10946 #define SWITCH_TABLE(fixp) \
10947 ((fixp)->fx_r_type == BFD_RELOC_32 \
10948 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10949 && (fixp)->fx_addsy != NULL \
10950 && (fixp)->fx_subsy != NULL \
10951 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10952 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10954 /* When generating embedded PIC code we must keep all PC relative
10955 relocations, in case the linker has to relax a call. We also need
10956 to keep relocations for switch table entries.
10958 We may have combined relocations without symbols in the N32/N64 ABI.
10959 We have to prevent gas from dropping them. */
10962 mips_force_relocation (fixS
*fixp
)
10964 if (generic_force_reloc (fixp
))
10968 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10969 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10970 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10971 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10974 return (mips_pic
== EMBEDDED_PIC
10976 || SWITCH_TABLE (fixp
)
10977 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10978 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10981 /* This hook is called before a fix is simplified. We don't really
10982 decide whether to skip a fix here. Rather, we turn global symbols
10983 used as branch targets into local symbols, such that they undergo
10984 simplification. We can only do this if the symbol is defined and
10985 it is in the same section as the branch. If this doesn't hold, we
10986 emit a better error message than just saying the relocation is not
10987 valid for the selected object format.
10989 FIXP is the fix-up we're going to try to simplify, SEG is the
10990 segment in which the fix up occurs. The return value should be
10991 non-zero to indicate the fix-up is valid for further
10992 simplifications. */
10995 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10997 /* There's a lot of discussion on whether it should be possible to
10998 use R_MIPS_PC16 to represent branch relocations. The outcome
10999 seems to be that it can, but gas/bfd are very broken in creating
11000 RELA relocations for this, so for now we only accept branches to
11001 symbols in the same section. Anything else is of dubious value,
11002 since there's no guarantee that at link time the symbol would be
11003 in range. Even for branches to local symbols this is arguably
11004 wrong, since it we assume the symbol is not going to be
11005 overridden, which should be possible per ELF library semantics,
11006 but then, there isn't a dynamic relocation that could be used to
11007 this effect, and the target would likely be out of range as well.
11009 Unfortunately, it seems that there is too much code out there
11010 that relies on branches to symbols that are global to be resolved
11011 as if they were local, like the IRIX tools do, so we do it as
11012 well, but with a warning so that people are reminded to fix their
11013 code. If we ever get back to using R_MIPS_PC16 for branch
11014 targets, this entire block should go away (and probably the
11015 whole function). */
11017 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11018 && (((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11019 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11020 && mips_pic
!= EMBEDDED_PIC
)
11021 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11024 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11027 _("Cannot branch to undefined symbol."));
11028 /* Avoid any further errors about this fixup. */
11031 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11034 _("Cannot branch to symbol in another section."));
11037 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11039 symbolS
*sym
= fixP
->fx_addsy
;
11041 if (mips_pic
== SVR4_PIC
)
11042 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11043 _("Pretending global symbol used as branch target is local."));
11045 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11046 S_GET_SEGMENT (sym
),
11048 symbol_get_frag (sym
));
11049 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11050 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11051 assert (symbol_resolved_p (sym
));
11052 symbol_mark_resolved (fixP
->fx_addsy
);
11059 /* Apply a fixup to the object file. */
11062 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11066 static int previous_fx_r_type
= 0;
11067 reloc_howto_type
*howto
;
11069 /* We ignore generic BFD relocations we don't know about. */
11070 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11074 assert (fixP
->fx_size
== 4
11075 || fixP
->fx_r_type
== BFD_RELOC_16
11076 || fixP
->fx_r_type
== BFD_RELOC_64
11077 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11078 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11079 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11080 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11082 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11084 /* We are not done if this is a composite relocation to set up gp. */
11085 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11086 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11087 || (fixP
->fx_r_type
== BFD_RELOC_64
11088 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11089 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11090 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11091 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11092 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11094 previous_fx_r_type
= fixP
->fx_r_type
;
11096 switch (fixP
->fx_r_type
)
11098 case BFD_RELOC_MIPS_JMP
:
11099 case BFD_RELOC_MIPS_SHIFT5
:
11100 case BFD_RELOC_MIPS_SHIFT6
:
11101 case BFD_RELOC_MIPS_GOT_DISP
:
11102 case BFD_RELOC_MIPS_GOT_PAGE
:
11103 case BFD_RELOC_MIPS_GOT_OFST
:
11104 case BFD_RELOC_MIPS_SUB
:
11105 case BFD_RELOC_MIPS_INSERT_A
:
11106 case BFD_RELOC_MIPS_INSERT_B
:
11107 case BFD_RELOC_MIPS_DELETE
:
11108 case BFD_RELOC_MIPS_HIGHEST
:
11109 case BFD_RELOC_MIPS_HIGHER
:
11110 case BFD_RELOC_MIPS_SCN_DISP
:
11111 case BFD_RELOC_MIPS_REL16
:
11112 case BFD_RELOC_MIPS_RELGOT
:
11113 case BFD_RELOC_MIPS_JALR
:
11114 case BFD_RELOC_HI16
:
11115 case BFD_RELOC_HI16_S
:
11116 case BFD_RELOC_GPREL16
:
11117 case BFD_RELOC_MIPS_LITERAL
:
11118 case BFD_RELOC_MIPS_CALL16
:
11119 case BFD_RELOC_MIPS_GOT16
:
11120 case BFD_RELOC_GPREL32
:
11121 case BFD_RELOC_MIPS_GOT_HI16
:
11122 case BFD_RELOC_MIPS_GOT_LO16
:
11123 case BFD_RELOC_MIPS_CALL_HI16
:
11124 case BFD_RELOC_MIPS_CALL_LO16
:
11125 case BFD_RELOC_MIPS16_GPREL
:
11126 if (fixP
->fx_pcrel
)
11127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11128 _("Invalid PC relative reloc"));
11129 /* Nothing needed to do. The value comes from the reloc entry */
11132 case BFD_RELOC_MIPS16_JMP
:
11133 /* We currently always generate a reloc against a symbol, which
11134 means that we don't want an addend even if the symbol is
11139 case BFD_RELOC_PCREL_HI16_S
:
11140 /* The addend for this is tricky if it is internal, so we just
11141 do everything here rather than in bfd_install_relocation. */
11142 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11145 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11147 /* For an external symbol adjust by the address to make it
11148 pcrel_offset. We use the address of the RELLO reloc
11149 which follows this one. */
11150 *valP
+= (fixP
->fx_next
->fx_frag
->fr_address
11151 + fixP
->fx_next
->fx_where
);
11153 *valP
= ((*valP
+ 0x8000) >> 16) & 0xffff;
11154 if (target_big_endian
)
11156 md_number_to_chars (buf
, *valP
, 2);
11159 case BFD_RELOC_PCREL_LO16
:
11160 /* The addend for this is tricky if it is internal, so we just
11161 do everything here rather than in bfd_install_relocation. */
11162 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11165 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11166 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11167 if (target_big_endian
)
11169 md_number_to_chars (buf
, *valP
, 2);
11173 /* This is handled like BFD_RELOC_32, but we output a sign
11174 extended value if we are only 32 bits. */
11176 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11178 if (8 <= sizeof (valueT
))
11179 md_number_to_chars (buf
, *valP
, 8);
11184 if ((*valP
& 0x80000000) != 0)
11188 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11190 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11196 case BFD_RELOC_RVA
:
11198 /* If we are deleting this reloc entry, we must fill in the
11199 value now. This can happen if we have a .word which is not
11200 resolved when it appears but is later defined. We also need
11201 to fill in the value if this is an embedded PIC switch table
11204 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11205 md_number_to_chars (buf
, *valP
, 4);
11209 /* If we are deleting this reloc entry, we must fill in the
11211 assert (fixP
->fx_size
== 2);
11213 md_number_to_chars (buf
, *valP
, 2);
11216 case BFD_RELOC_LO16
:
11217 /* When handling an embedded PIC switch statement, we can wind
11218 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11221 if (*valP
+ 0x8000 > 0xffff)
11222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11223 _("relocation overflow"));
11224 if (target_big_endian
)
11226 md_number_to_chars (buf
, *valP
, 2);
11230 case BFD_RELOC_16_PCREL_S2
:
11231 if ((*valP
& 0x3) != 0)
11232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11233 _("Branch to odd address (%lx)"), (long) *valP
);
11236 * We need to save the bits in the instruction since fixup_segment()
11237 * might be deleting the relocation entry (i.e., a branch within
11238 * the current segment).
11240 if (! fixP
->fx_done
)
11243 /* update old instruction data */
11244 if (target_big_endian
)
11245 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11247 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11249 if (*valP
+ 0x20000 <= 0x3ffff)
11251 insn
|= (*valP
>> 2) & 0xffff;
11252 md_number_to_chars (buf
, insn
, 4);
11254 else if (mips_pic
== NO_PIC
11256 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11257 && (fixP
->fx_frag
->fr_address
11258 < text_section
->vma
+ text_section
->_raw_size
)
11259 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11260 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11261 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11263 /* The branch offset is too large. If this is an
11264 unconditional branch, and we are not generating PIC code,
11265 we can convert it to an absolute jump instruction. */
11266 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11267 insn
= 0x0c000000; /* jal */
11269 insn
= 0x08000000; /* j */
11270 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11272 fixP
->fx_addsy
= section_symbol (text_section
);
11273 *valP
+= md_pcrel_from (fixP
);
11274 md_number_to_chars (buf
, insn
, 4);
11278 /* If we got here, we have branch-relaxation disabled,
11279 and there's nothing we can do to fix this instruction
11280 without turning it into a longer sequence. */
11281 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11282 _("Branch out of range"));
11286 case BFD_RELOC_VTABLE_INHERIT
:
11289 && !S_IS_DEFINED (fixP
->fx_addsy
)
11290 && !S_IS_WEAK (fixP
->fx_addsy
))
11291 S_SET_WEAK (fixP
->fx_addsy
);
11294 case BFD_RELOC_VTABLE_ENTRY
:
11302 /* Remember value for tc_gen_reloc. */
11303 fixP
->fx_addnumber
= *valP
;
11308 printInsn (unsigned long oc
)
11310 const struct mips_opcode
*p
;
11311 int treg
, sreg
, dreg
, shamt
;
11316 for (i
= 0; i
< NUMOPCODES
; ++i
)
11318 p
= &mips_opcodes
[i
];
11319 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11321 printf ("%08lx %s\t", oc
, p
->name
);
11322 treg
= (oc
>> 16) & 0x1f;
11323 sreg
= (oc
>> 21) & 0x1f;
11324 dreg
= (oc
>> 11) & 0x1f;
11325 shamt
= (oc
>> 6) & 0x1f;
11327 for (args
= p
->args
;; ++args
)
11338 printf ("%c", *args
);
11342 assert (treg
== sreg
);
11343 printf ("$%d,$%d", treg
, sreg
);
11348 printf ("$%d", dreg
);
11353 printf ("$%d", treg
);
11357 printf ("0x%x", treg
);
11362 printf ("$%d", sreg
);
11366 printf ("0x%08lx", oc
& 0x1ffffff);
11373 printf ("%d", imm
);
11378 printf ("$%d", shamt
);
11389 printf (_("%08lx UNDEFINED\n"), oc
);
11400 name
= input_line_pointer
;
11401 c
= get_symbol_end ();
11402 p
= (symbolS
*) symbol_find_or_make (name
);
11403 *input_line_pointer
= c
;
11407 /* Align the current frag to a given power of two. The MIPS assembler
11408 also automatically adjusts any preceding label. */
11411 mips_align (int to
, int fill
, symbolS
*label
)
11413 mips_emit_delays (FALSE
);
11414 frag_align (to
, fill
, 0);
11415 record_alignment (now_seg
, to
);
11418 assert (S_GET_SEGMENT (label
) == now_seg
);
11419 symbol_set_frag (label
, frag_now
);
11420 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11424 /* Align to a given power of two. .align 0 turns off the automatic
11425 alignment used by the data creating pseudo-ops. */
11428 s_align (int x ATTRIBUTE_UNUSED
)
11431 register long temp_fill
;
11432 long max_alignment
= 15;
11436 o Note that the assembler pulls down any immediately preceding label
11437 to the aligned address.
11438 o It's not documented but auto alignment is reinstated by
11439 a .align pseudo instruction.
11440 o Note also that after auto alignment is turned off the mips assembler
11441 issues an error on attempt to assemble an improperly aligned data item.
11446 temp
= get_absolute_expression ();
11447 if (temp
> max_alignment
)
11448 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11451 as_warn (_("Alignment negative: 0 assumed."));
11454 if (*input_line_pointer
== ',')
11456 ++input_line_pointer
;
11457 temp_fill
= get_absolute_expression ();
11464 mips_align (temp
, (int) temp_fill
,
11465 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11472 demand_empty_rest_of_line ();
11476 mips_flush_pending_output (void)
11478 mips_emit_delays (FALSE
);
11479 mips_clear_insn_labels ();
11483 s_change_sec (int sec
)
11487 /* When generating embedded PIC code, we only use the .text, .lit8,
11488 .sdata and .sbss sections. We change the .data and .rdata
11489 pseudo-ops to use .sdata. */
11490 if (mips_pic
== EMBEDDED_PIC
11491 && (sec
== 'd' || sec
== 'r'))
11495 /* The ELF backend needs to know that we are changing sections, so
11496 that .previous works correctly. We could do something like check
11497 for an obj_section_change_hook macro, but that might be confusing
11498 as it would not be appropriate to use it in the section changing
11499 functions in read.c, since obj-elf.c intercepts those. FIXME:
11500 This should be cleaner, somehow. */
11501 obj_elf_section_change_hook ();
11504 mips_emit_delays (FALSE
);
11514 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11515 demand_empty_rest_of_line ();
11519 seg
= subseg_new (RDATA_SECTION_NAME
,
11520 (subsegT
) get_absolute_expression ());
11521 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11523 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11524 | SEC_READONLY
| SEC_RELOC
11526 if (strcmp (TARGET_OS
, "elf") != 0)
11527 record_alignment (seg
, 4);
11529 demand_empty_rest_of_line ();
11533 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11534 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11536 bfd_set_section_flags (stdoutput
, seg
,
11537 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11538 if (strcmp (TARGET_OS
, "elf") != 0)
11539 record_alignment (seg
, 4);
11541 demand_empty_rest_of_line ();
11549 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11552 char *section_name
;
11557 int section_entry_size
;
11558 int section_alignment
;
11560 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11563 section_name
= input_line_pointer
;
11564 c
= get_symbol_end ();
11566 next_c
= *(input_line_pointer
+ 1);
11568 /* Do we have .section Name<,"flags">? */
11569 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11571 /* just after name is now '\0'. */
11572 *input_line_pointer
= c
;
11573 input_line_pointer
= section_name
;
11574 obj_elf_section (ignore
);
11577 input_line_pointer
++;
11579 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11581 section_type
= get_absolute_expression ();
11584 if (*input_line_pointer
++ == ',')
11585 section_flag
= get_absolute_expression ();
11588 if (*input_line_pointer
++ == ',')
11589 section_entry_size
= get_absolute_expression ();
11591 section_entry_size
= 0;
11592 if (*input_line_pointer
++ == ',')
11593 section_alignment
= get_absolute_expression ();
11595 section_alignment
= 0;
11597 section_name
= xstrdup (section_name
);
11599 /* When using the generic form of .section (as implemented by obj-elf.c),
11600 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11601 traditionally had to fall back on the more common @progbits instead.
11603 There's nothing really harmful in this, since bfd will correct
11604 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11605 means that, for backwards compatibiltiy, the special_section entries
11606 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11608 Even so, we shouldn't force users of the MIPS .section syntax to
11609 incorrectly label the sections as SHT_PROGBITS. The best compromise
11610 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11611 generic type-checking code. */
11612 if (section_type
== SHT_MIPS_DWARF
)
11613 section_type
= SHT_PROGBITS
;
11615 obj_elf_change_section (section_name
, section_type
, section_flag
,
11616 section_entry_size
, 0, 0, 0);
11618 if (now_seg
->name
!= section_name
)
11619 free (section_name
);
11620 #endif /* OBJ_ELF */
11624 mips_enable_auto_align (void)
11630 s_cons (int log_size
)
11634 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11635 mips_emit_delays (FALSE
);
11636 if (log_size
> 0 && auto_align
)
11637 mips_align (log_size
, 0, label
);
11638 mips_clear_insn_labels ();
11639 cons (1 << log_size
);
11643 s_float_cons (int type
)
11647 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11649 mips_emit_delays (FALSE
);
11654 mips_align (3, 0, label
);
11656 mips_align (2, 0, label
);
11659 mips_clear_insn_labels ();
11664 /* Handle .globl. We need to override it because on Irix 5 you are
11667 where foo is an undefined symbol, to mean that foo should be
11668 considered to be the address of a function. */
11671 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11678 name
= input_line_pointer
;
11679 c
= get_symbol_end ();
11680 symbolP
= symbol_find_or_make (name
);
11681 *input_line_pointer
= c
;
11682 SKIP_WHITESPACE ();
11684 /* On Irix 5, every global symbol that is not explicitly labelled as
11685 being a function is apparently labelled as being an object. */
11688 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11693 secname
= input_line_pointer
;
11694 c
= get_symbol_end ();
11695 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11697 as_bad (_("%s: no such section"), secname
);
11698 *input_line_pointer
= c
;
11700 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11701 flag
= BSF_FUNCTION
;
11704 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11706 S_SET_EXTERNAL (symbolP
);
11707 demand_empty_rest_of_line ();
11711 s_option (int x ATTRIBUTE_UNUSED
)
11716 opt
= input_line_pointer
;
11717 c
= get_symbol_end ();
11721 /* FIXME: What does this mean? */
11723 else if (strncmp (opt
, "pic", 3) == 0)
11727 i
= atoi (opt
+ 3);
11732 mips_pic
= SVR4_PIC
;
11733 mips_abicalls
= TRUE
;
11736 as_bad (_(".option pic%d not supported"), i
);
11738 if (mips_pic
== SVR4_PIC
)
11740 if (g_switch_seen
&& g_switch_value
!= 0)
11741 as_warn (_("-G may not be used with SVR4 PIC code"));
11742 g_switch_value
= 0;
11743 bfd_set_gp_size (stdoutput
, 0);
11747 as_warn (_("Unrecognized option \"%s\""), opt
);
11749 *input_line_pointer
= c
;
11750 demand_empty_rest_of_line ();
11753 /* This structure is used to hold a stack of .set values. */
11755 struct mips_option_stack
11757 struct mips_option_stack
*next
;
11758 struct mips_set_options options
;
11761 static struct mips_option_stack
*mips_opts_stack
;
11763 /* Handle the .set pseudo-op. */
11766 s_mipsset (int x ATTRIBUTE_UNUSED
)
11768 char *name
= input_line_pointer
, ch
;
11770 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11771 ++input_line_pointer
;
11772 ch
= *input_line_pointer
;
11773 *input_line_pointer
= '\0';
11775 if (strcmp (name
, "reorder") == 0)
11777 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11779 /* If we still have pending nops, we can discard them. The
11780 usual nop handling will insert any that are still
11782 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11783 * (mips_opts
.mips16
? 2 : 4));
11784 prev_nop_frag
= NULL
;
11786 mips_opts
.noreorder
= 0;
11788 else if (strcmp (name
, "noreorder") == 0)
11790 mips_emit_delays (TRUE
);
11791 mips_opts
.noreorder
= 1;
11792 mips_any_noreorder
= 1;
11794 else if (strcmp (name
, "at") == 0)
11796 mips_opts
.noat
= 0;
11798 else if (strcmp (name
, "noat") == 0)
11800 mips_opts
.noat
= 1;
11802 else if (strcmp (name
, "macro") == 0)
11804 mips_opts
.warn_about_macros
= 0;
11806 else if (strcmp (name
, "nomacro") == 0)
11808 if (mips_opts
.noreorder
== 0)
11809 as_bad (_("`noreorder' must be set before `nomacro'"));
11810 mips_opts
.warn_about_macros
= 1;
11812 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11814 mips_opts
.nomove
= 0;
11816 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11818 mips_opts
.nomove
= 1;
11820 else if (strcmp (name
, "bopt") == 0)
11822 mips_opts
.nobopt
= 0;
11824 else if (strcmp (name
, "nobopt") == 0)
11826 mips_opts
.nobopt
= 1;
11828 else if (strcmp (name
, "mips16") == 0
11829 || strcmp (name
, "MIPS-16") == 0)
11830 mips_opts
.mips16
= 1;
11831 else if (strcmp (name
, "nomips16") == 0
11832 || strcmp (name
, "noMIPS-16") == 0)
11833 mips_opts
.mips16
= 0;
11834 else if (strcmp (name
, "mips3d") == 0)
11835 mips_opts
.ase_mips3d
= 1;
11836 else if (strcmp (name
, "nomips3d") == 0)
11837 mips_opts
.ase_mips3d
= 0;
11838 else if (strcmp (name
, "mdmx") == 0)
11839 mips_opts
.ase_mdmx
= 1;
11840 else if (strcmp (name
, "nomdmx") == 0)
11841 mips_opts
.ase_mdmx
= 0;
11842 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11846 /* Permit the user to change the ISA and architecture on the fly.
11847 Needless to say, misuse can cause serious problems. */
11848 if (strcmp (name
, "mips0") == 0)
11851 mips_opts
.isa
= file_mips_isa
;
11853 else if (strcmp (name
, "mips1") == 0)
11854 mips_opts
.isa
= ISA_MIPS1
;
11855 else if (strcmp (name
, "mips2") == 0)
11856 mips_opts
.isa
= ISA_MIPS2
;
11857 else if (strcmp (name
, "mips3") == 0)
11858 mips_opts
.isa
= ISA_MIPS3
;
11859 else if (strcmp (name
, "mips4") == 0)
11860 mips_opts
.isa
= ISA_MIPS4
;
11861 else if (strcmp (name
, "mips5") == 0)
11862 mips_opts
.isa
= ISA_MIPS5
;
11863 else if (strcmp (name
, "mips32") == 0)
11864 mips_opts
.isa
= ISA_MIPS32
;
11865 else if (strcmp (name
, "mips32r2") == 0)
11866 mips_opts
.isa
= ISA_MIPS32R2
;
11867 else if (strcmp (name
, "mips64") == 0)
11868 mips_opts
.isa
= ISA_MIPS64
;
11869 else if (strcmp (name
, "mips64r2") == 0)
11870 mips_opts
.isa
= ISA_MIPS64R2
;
11871 else if (strcmp (name
, "arch=default") == 0)
11874 mips_opts
.arch
= file_mips_arch
;
11875 mips_opts
.isa
= file_mips_isa
;
11877 else if (strncmp (name
, "arch=", 5) == 0)
11879 const struct mips_cpu_info
*p
;
11881 p
= mips_parse_cpu("internal use", name
+ 5);
11883 as_bad (_("unknown architecture %s"), name
+ 5);
11886 mips_opts
.arch
= p
->cpu
;
11887 mips_opts
.isa
= p
->isa
;
11891 as_bad (_("unknown ISA level %s"), name
+ 4);
11893 switch (mips_opts
.isa
)
11901 mips_opts
.gp32
= 1;
11902 mips_opts
.fp32
= 1;
11909 mips_opts
.gp32
= 0;
11910 mips_opts
.fp32
= 0;
11913 as_bad (_("unknown ISA level %s"), name
+ 4);
11918 mips_opts
.gp32
= file_mips_gp32
;
11919 mips_opts
.fp32
= file_mips_fp32
;
11922 else if (strcmp (name
, "autoextend") == 0)
11923 mips_opts
.noautoextend
= 0;
11924 else if (strcmp (name
, "noautoextend") == 0)
11925 mips_opts
.noautoextend
= 1;
11926 else if (strcmp (name
, "push") == 0)
11928 struct mips_option_stack
*s
;
11930 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11931 s
->next
= mips_opts_stack
;
11932 s
->options
= mips_opts
;
11933 mips_opts_stack
= s
;
11935 else if (strcmp (name
, "pop") == 0)
11937 struct mips_option_stack
*s
;
11939 s
= mips_opts_stack
;
11941 as_bad (_(".set pop with no .set push"));
11944 /* If we're changing the reorder mode we need to handle
11945 delay slots correctly. */
11946 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11947 mips_emit_delays (TRUE
);
11948 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11950 if (prev_nop_frag
!= NULL
)
11952 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11953 * (mips_opts
.mips16
? 2 : 4));
11954 prev_nop_frag
= NULL
;
11958 mips_opts
= s
->options
;
11959 mips_opts_stack
= s
->next
;
11965 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11967 *input_line_pointer
= ch
;
11968 demand_empty_rest_of_line ();
11971 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11972 .option pic2. It means to generate SVR4 PIC calls. */
11975 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11977 mips_pic
= SVR4_PIC
;
11978 mips_abicalls
= TRUE
;
11980 if (g_switch_seen
&& g_switch_value
!= 0)
11981 as_warn (_("-G may not be used with SVR4 PIC code"));
11982 g_switch_value
= 0;
11984 bfd_set_gp_size (stdoutput
, 0);
11985 demand_empty_rest_of_line ();
11988 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11989 PIC code. It sets the $gp register for the function based on the
11990 function address, which is in the register named in the argument.
11991 This uses a relocation against _gp_disp, which is handled specially
11992 by the linker. The result is:
11993 lui $gp,%hi(_gp_disp)
11994 addiu $gp,$gp,%lo(_gp_disp)
11995 addu $gp,$gp,.cpload argument
11996 The .cpload argument is normally $25 == $t9. */
11999 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12003 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12004 .cpload is ignored. */
12005 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12011 /* .cpload should be in a .set noreorder section. */
12012 if (mips_opts
.noreorder
== 0)
12013 as_warn (_(".cpload not in noreorder section"));
12015 ex
.X_op
= O_symbol
;
12016 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12017 ex
.X_op_symbol
= NULL
;
12018 ex
.X_add_number
= 0;
12020 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12021 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12024 macro_build_lui (&ex
, mips_gp_register
);
12025 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12026 mips_gp_register
, BFD_RELOC_LO16
);
12027 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12028 mips_gp_register
, tc_get_register (0));
12031 demand_empty_rest_of_line ();
12034 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12035 .cpsetup $reg1, offset|$reg2, label
12037 If offset is given, this results in:
12038 sd $gp, offset($sp)
12039 lui $gp, %hi(%neg(%gp_rel(label)))
12040 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12041 daddu $gp, $gp, $reg1
12043 If $reg2 is given, this results in:
12044 daddu $reg2, $gp, $0
12045 lui $gp, %hi(%neg(%gp_rel(label)))
12046 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12047 daddu $gp, $gp, $reg1
12048 $reg1 is normally $25 == $t9. */
12050 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12052 expressionS ex_off
;
12053 expressionS ex_sym
;
12057 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12058 We also need NewABI support. */
12059 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12065 reg1
= tc_get_register (0);
12066 SKIP_WHITESPACE ();
12067 if (*input_line_pointer
!= ',')
12069 as_bad (_("missing argument separator ',' for .cpsetup"));
12073 ++input_line_pointer
;
12074 SKIP_WHITESPACE ();
12075 if (*input_line_pointer
== '$')
12077 mips_cpreturn_register
= tc_get_register (0);
12078 mips_cpreturn_offset
= -1;
12082 mips_cpreturn_offset
= get_absolute_expression ();
12083 mips_cpreturn_register
= -1;
12085 SKIP_WHITESPACE ();
12086 if (*input_line_pointer
!= ',')
12088 as_bad (_("missing argument separator ',' for .cpsetup"));
12092 ++input_line_pointer
;
12093 SKIP_WHITESPACE ();
12094 expression (&ex_sym
);
12097 if (mips_cpreturn_register
== -1)
12099 ex_off
.X_op
= O_constant
;
12100 ex_off
.X_add_symbol
= NULL
;
12101 ex_off
.X_op_symbol
= NULL
;
12102 ex_off
.X_add_number
= mips_cpreturn_offset
;
12104 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12105 BFD_RELOC_LO16
, SP
);
12108 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12109 mips_gp_register
, 0);
12111 /* Ensure there's room for the next two instructions, so that `f'
12112 doesn't end up with an address in the wrong frag. */
12115 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
, BFD_RELOC_GPREL16
);
12116 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12117 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12118 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12119 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12122 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12123 mips_gp_register
, BFD_RELOC_GPREL16
);
12124 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12125 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12126 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12127 4, NULL
, 0, 0, BFD_RELOC_LO16
);
12129 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12130 mips_gp_register
, reg1
);
12133 demand_empty_rest_of_line ();
12137 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12139 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12140 .cplocal is ignored. */
12141 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12147 mips_gp_register
= tc_get_register (0);
12148 demand_empty_rest_of_line ();
12151 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12152 offset from $sp. The offset is remembered, and after making a PIC
12153 call $gp is restored from that location. */
12156 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12160 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12161 .cprestore is ignored. */
12162 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12168 mips_cprestore_offset
= get_absolute_expression ();
12169 mips_cprestore_valid
= 1;
12171 ex
.X_op
= O_constant
;
12172 ex
.X_add_symbol
= NULL
;
12173 ex
.X_op_symbol
= NULL
;
12174 ex
.X_add_number
= mips_cprestore_offset
;
12177 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12178 SP
, HAVE_64BIT_ADDRESSES
);
12181 demand_empty_rest_of_line ();
12184 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12185 was given in the preceding .cpsetup, it results in:
12186 ld $gp, offset($sp)
12188 If a register $reg2 was given there, it results in:
12189 daddu $gp, $reg2, $0
12192 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12196 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12197 We also need NewABI support. */
12198 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12205 if (mips_cpreturn_register
== -1)
12207 ex
.X_op
= O_constant
;
12208 ex
.X_add_symbol
= NULL
;
12209 ex
.X_op_symbol
= NULL
;
12210 ex
.X_add_number
= mips_cpreturn_offset
;
12212 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12215 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12216 mips_cpreturn_register
, 0);
12219 demand_empty_rest_of_line ();
12222 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12223 code. It sets the offset to use in gp_rel relocations. */
12226 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12228 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12229 We also need NewABI support. */
12230 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12236 mips_gprel_offset
= get_absolute_expression ();
12238 demand_empty_rest_of_line ();
12241 /* Handle the .gpword pseudo-op. This is used when generating PIC
12242 code. It generates a 32 bit GP relative reloc. */
12245 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12251 /* When not generating PIC code, this is treated as .word. */
12252 if (mips_pic
!= SVR4_PIC
)
12258 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12259 mips_emit_delays (TRUE
);
12261 mips_align (2, 0, label
);
12262 mips_clear_insn_labels ();
12266 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12268 as_bad (_("Unsupported use of .gpword"));
12269 ignore_rest_of_line ();
12273 md_number_to_chars (p
, 0, 4);
12274 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12275 BFD_RELOC_GPREL32
);
12277 demand_empty_rest_of_line ();
12281 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12287 /* When not generating PIC code, this is treated as .dword. */
12288 if (mips_pic
!= SVR4_PIC
)
12294 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12295 mips_emit_delays (TRUE
);
12297 mips_align (3, 0, label
);
12298 mips_clear_insn_labels ();
12302 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12304 as_bad (_("Unsupported use of .gpdword"));
12305 ignore_rest_of_line ();
12309 md_number_to_chars (p
, 0, 8);
12310 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12311 BFD_RELOC_GPREL32
);
12313 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12314 ex
.X_op
= O_absent
;
12315 ex
.X_add_symbol
= 0;
12316 ex
.X_add_number
= 0;
12317 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12320 demand_empty_rest_of_line ();
12323 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12324 tables in SVR4 PIC code. */
12327 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12331 /* This is ignored when not generating SVR4 PIC code. */
12332 if (mips_pic
!= SVR4_PIC
)
12338 /* Add $gp to the register named as an argument. */
12340 reg
= tc_get_register (0);
12341 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12344 demand_empty_rest_of_line ();
12347 /* Handle the .insn pseudo-op. This marks instruction labels in
12348 mips16 mode. This permits the linker to handle them specially,
12349 such as generating jalx instructions when needed. We also make
12350 them odd for the duration of the assembly, in order to generate the
12351 right sort of code. We will make them even in the adjust_symtab
12352 routine, while leaving them marked. This is convenient for the
12353 debugger and the disassembler. The linker knows to make them odd
12357 s_insn (int ignore ATTRIBUTE_UNUSED
)
12359 mips16_mark_labels ();
12361 demand_empty_rest_of_line ();
12364 /* Handle a .stabn directive. We need these in order to mark a label
12365 as being a mips16 text label correctly. Sometimes the compiler
12366 will emit a label, followed by a .stabn, and then switch sections.
12367 If the label and .stabn are in mips16 mode, then the label is
12368 really a mips16 text label. */
12371 s_mips_stab (int type
)
12374 mips16_mark_labels ();
12379 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12383 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12390 name
= input_line_pointer
;
12391 c
= get_symbol_end ();
12392 symbolP
= symbol_find_or_make (name
);
12393 S_SET_WEAK (symbolP
);
12394 *input_line_pointer
= c
;
12396 SKIP_WHITESPACE ();
12398 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12400 if (S_IS_DEFINED (symbolP
))
12402 as_bad ("ignoring attempt to redefine symbol %s",
12403 S_GET_NAME (symbolP
));
12404 ignore_rest_of_line ();
12408 if (*input_line_pointer
== ',')
12410 ++input_line_pointer
;
12411 SKIP_WHITESPACE ();
12415 if (exp
.X_op
!= O_symbol
)
12417 as_bad ("bad .weakext directive");
12418 ignore_rest_of_line ();
12421 symbol_set_value_expression (symbolP
, &exp
);
12424 demand_empty_rest_of_line ();
12427 /* Parse a register string into a number. Called from the ECOFF code
12428 to parse .frame. The argument is non-zero if this is the frame
12429 register, so that we can record it in mips_frame_reg. */
12432 tc_get_register (int frame
)
12436 SKIP_WHITESPACE ();
12437 if (*input_line_pointer
++ != '$')
12439 as_warn (_("expected `$'"));
12442 else if (ISDIGIT (*input_line_pointer
))
12444 reg
= get_absolute_expression ();
12445 if (reg
< 0 || reg
>= 32)
12447 as_warn (_("Bad register number"));
12453 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12456 input_line_pointer
+= 2;
12458 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12461 input_line_pointer
+= 2;
12463 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12466 input_line_pointer
+= 2;
12468 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12471 input_line_pointer
+= 2;
12473 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12476 input_line_pointer
+= 2;
12478 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12481 input_line_pointer
+= 3;
12483 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12486 input_line_pointer
+= 3;
12488 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12491 input_line_pointer
+= 4;
12495 as_warn (_("Unrecognized register name"));
12497 while (ISALNUM(*input_line_pointer
))
12498 input_line_pointer
++;
12503 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12504 mips_frame_reg_valid
= 1;
12505 mips_cprestore_valid
= 0;
12511 md_section_align (asection
*seg
, valueT addr
)
12513 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12516 /* We don't need to align ELF sections to the full alignment.
12517 However, Irix 5 may prefer that we align them at least to a 16
12518 byte boundary. We don't bother to align the sections if we are
12519 targeted for an embedded system. */
12520 if (strcmp (TARGET_OS
, "elf") == 0)
12526 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12529 /* Utility routine, called from above as well. If called while the
12530 input file is still being read, it's only an approximation. (For
12531 example, a symbol may later become defined which appeared to be
12532 undefined earlier.) */
12535 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12540 if (g_switch_value
> 0)
12542 const char *symname
;
12545 /* Find out whether this symbol can be referenced off the $gp
12546 register. It can be if it is smaller than the -G size or if
12547 it is in the .sdata or .sbss section. Certain symbols can
12548 not be referenced off the $gp, although it appears as though
12550 symname
= S_GET_NAME (sym
);
12551 if (symname
!= (const char *) NULL
12552 && (strcmp (symname
, "eprol") == 0
12553 || strcmp (symname
, "etext") == 0
12554 || strcmp (symname
, "_gp") == 0
12555 || strcmp (symname
, "edata") == 0
12556 || strcmp (symname
, "_fbss") == 0
12557 || strcmp (symname
, "_fdata") == 0
12558 || strcmp (symname
, "_ftext") == 0
12559 || strcmp (symname
, "end") == 0
12560 || strcmp (symname
, "_gp_disp") == 0))
12562 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12564 #ifndef NO_ECOFF_DEBUGGING
12565 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12566 && (symbol_get_obj (sym
)->ecoff_extern_size
12567 <= g_switch_value
))
12569 /* We must defer this decision until after the whole
12570 file has been read, since there might be a .extern
12571 after the first use of this symbol. */
12572 || (before_relaxing
12573 #ifndef NO_ECOFF_DEBUGGING
12574 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12576 && S_GET_VALUE (sym
) == 0)
12577 || (S_GET_VALUE (sym
) != 0
12578 && S_GET_VALUE (sym
) <= g_switch_value
)))
12582 const char *segname
;
12584 segname
= segment_name (S_GET_SEGMENT (sym
));
12585 assert (strcmp (segname
, ".lit8") != 0
12586 && strcmp (segname
, ".lit4") != 0);
12587 change
= (strcmp (segname
, ".sdata") != 0
12588 && strcmp (segname
, ".sbss") != 0
12589 && strncmp (segname
, ".sdata.", 7) != 0
12590 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12595 /* We are not optimizing for the $gp register. */
12600 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12603 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12606 bfd_boolean linkonce
;
12608 /* Handle the case of a symbol equated to another symbol. */
12609 while (symbol_equated_reloc_p (sym
))
12613 /* It's possible to get a loop here in a badly written
12615 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12621 symsec
= S_GET_SEGMENT (sym
);
12623 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12625 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12627 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12631 /* The GNU toolchain uses an extension for ELF: a section
12632 beginning with the magic string .gnu.linkonce is a linkonce
12634 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12635 sizeof ".gnu.linkonce" - 1) == 0)
12639 /* This must duplicate the test in adjust_reloc_syms. */
12640 return (symsec
!= &bfd_und_section
12641 && symsec
!= &bfd_abs_section
12642 && ! bfd_is_com_section (symsec
)
12645 /* A global or weak symbol is treated as external. */
12646 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12647 || (! S_IS_WEAK (sym
)
12648 && (! S_IS_EXTERNAL (sym
)
12649 || mips_pic
== EMBEDDED_PIC
)))
12655 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12656 extended opcode. SEC is the section the frag is in. */
12659 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12662 register const struct mips16_immed_operand
*op
;
12664 int mintiny
, maxtiny
;
12668 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12670 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12673 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12674 op
= mips16_immed_operands
;
12675 while (op
->type
!= type
)
12678 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12683 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12686 maxtiny
= 1 << op
->nbits
;
12691 maxtiny
= (1 << op
->nbits
) - 1;
12696 mintiny
= - (1 << (op
->nbits
- 1));
12697 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12700 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12701 val
= S_GET_VALUE (fragp
->fr_symbol
);
12702 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12708 /* We won't have the section when we are called from
12709 mips_relax_frag. However, we will always have been called
12710 from md_estimate_size_before_relax first. If this is a
12711 branch to a different section, we mark it as such. If SEC is
12712 NULL, and the frag is not marked, then it must be a branch to
12713 the same section. */
12716 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12721 /* Must have been called from md_estimate_size_before_relax. */
12724 fragp
->fr_subtype
=
12725 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12727 /* FIXME: We should support this, and let the linker
12728 catch branches and loads that are out of range. */
12729 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12730 _("unsupported PC relative reference to different section"));
12734 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12735 /* Assume non-extended on the first relaxation pass.
12736 The address we have calculated will be bogus if this is
12737 a forward branch to another frag, as the forward frag
12738 will have fr_address == 0. */
12742 /* In this case, we know for sure that the symbol fragment is in
12743 the same section. If the relax_marker of the symbol fragment
12744 differs from the relax_marker of this fragment, we have not
12745 yet adjusted the symbol fragment fr_address. We want to add
12746 in STRETCH in order to get a better estimate of the address.
12747 This particularly matters because of the shift bits. */
12749 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12753 /* Adjust stretch for any alignment frag. Note that if have
12754 been expanding the earlier code, the symbol may be
12755 defined in what appears to be an earlier frag. FIXME:
12756 This doesn't handle the fr_subtype field, which specifies
12757 a maximum number of bytes to skip when doing an
12759 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12761 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12764 stretch
= - ((- stretch
)
12765 & ~ ((1 << (int) f
->fr_offset
) - 1));
12767 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12776 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12778 /* The base address rules are complicated. The base address of
12779 a branch is the following instruction. The base address of a
12780 PC relative load or add is the instruction itself, but if it
12781 is in a delay slot (in which case it can not be extended) use
12782 the address of the instruction whose delay slot it is in. */
12783 if (type
== 'p' || type
== 'q')
12787 /* If we are currently assuming that this frag should be
12788 extended, then, the current address is two bytes
12790 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12793 /* Ignore the low bit in the target, since it will be set
12794 for a text label. */
12795 if ((val
& 1) != 0)
12798 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12800 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12803 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12805 /* Branch offsets have an implicit 0 in the lowest bit. */
12806 if (type
== 'p' || type
== 'q')
12809 /* If any of the shifted bits are set, we must use an extended
12810 opcode. If the address depends on the size of this
12811 instruction, this can lead to a loop, so we arrange to always
12812 use an extended opcode. We only check this when we are in
12813 the main relaxation loop, when SEC is NULL. */
12814 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12816 fragp
->fr_subtype
=
12817 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12821 /* If we are about to mark a frag as extended because the value
12822 is precisely maxtiny + 1, then there is a chance of an
12823 infinite loop as in the following code:
12828 In this case when the la is extended, foo is 0x3fc bytes
12829 away, so the la can be shrunk, but then foo is 0x400 away, so
12830 the la must be extended. To avoid this loop, we mark the
12831 frag as extended if it was small, and is about to become
12832 extended with a value of maxtiny + 1. */
12833 if (val
== ((maxtiny
+ 1) << op
->shift
)
12834 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12837 fragp
->fr_subtype
=
12838 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12842 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12843 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12845 if ((val
& ((1 << op
->shift
) - 1)) != 0
12846 || val
< (mintiny
<< op
->shift
)
12847 || val
> (maxtiny
<< op
->shift
))
12853 /* Compute the length of a branch sequence, and adjust the
12854 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12855 worst-case length is computed, with UPDATE being used to indicate
12856 whether an unconditional (-1), branch-likely (+1) or regular (0)
12857 branch is to be computed. */
12859 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12861 bfd_boolean toofar
;
12865 && S_IS_DEFINED (fragp
->fr_symbol
)
12866 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12871 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12873 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12877 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12880 /* If the symbol is not defined or it's in a different segment,
12881 assume the user knows what's going on and emit a short
12887 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12889 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12890 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12891 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12897 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12900 if (mips_pic
!= NO_PIC
)
12902 /* Additional space for PIC loading of target address. */
12904 if (mips_opts
.isa
== ISA_MIPS1
)
12905 /* Additional space for $at-stabilizing nop. */
12909 /* If branch is conditional. */
12910 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12917 /* Estimate the size of a frag before relaxing. Unless this is the
12918 mips16, we are not really relaxing here, and the final size is
12919 encoded in the subtype information. For the mips16, we have to
12920 decide whether we are using an extended opcode or not. */
12923 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12927 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12930 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12932 return fragp
->fr_var
;
12935 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12936 /* We don't want to modify the EXTENDED bit here; it might get us
12937 into infinite loops. We change it only in mips_relax_frag(). */
12938 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12940 if (mips_pic
== NO_PIC
)
12941 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12942 else if (mips_pic
== SVR4_PIC
)
12943 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12949 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12950 return -RELAX_FIRST (fragp
->fr_subtype
);
12953 return -RELAX_SECOND (fragp
->fr_subtype
);
12956 /* This is called to see whether a reloc against a defined symbol
12957 should be converted into a reloc against a section. Don't adjust
12958 MIPS16 jump relocations, so we don't have to worry about the format
12959 of the offset in the .o file. Don't adjust relocations against
12960 mips16 symbols, so that the linker can find them if it needs to set
12964 mips_fix_adjustable (fixS
*fixp
)
12966 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12969 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12970 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12973 if (fixp
->fx_addsy
== NULL
)
12977 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12978 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12979 && fixp
->fx_subsy
== NULL
)
12986 /* Translate internal representation of relocation info to BFD target
12990 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12992 static arelent
*retval
[4];
12994 bfd_reloc_code_real_type code
;
12996 memset (retval
, 0, sizeof(retval
));
12997 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12998 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12999 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13000 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13002 if (mips_pic
== EMBEDDED_PIC
13003 && SWITCH_TABLE (fixp
))
13005 /* For a switch table entry we use a special reloc. The addend
13006 is actually the difference between the reloc address and the
13008 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13009 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13010 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13011 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13013 else if (fixp
->fx_pcrel
)
13015 bfd_vma pcrel_address
;
13017 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13018 high-part relocs is the address of the low-part reloc. */
13019 if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13021 assert (fixp
->fx_next
!= NULL
13022 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13023 pcrel_address
= (fixp
->fx_next
->fx_where
13024 + fixp
->fx_next
->fx_frag
->fr_address
);
13027 pcrel_address
= reloc
->address
;
13029 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13031 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13032 Relocations want only the symbol offset. */
13033 reloc
->addend
= fixp
->fx_addnumber
+ pcrel_address
;
13035 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
13036 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13038 /* We use a special addend for an internal RELLO or RELHI reloc. */
13039 if (symbol_section_p (fixp
->fx_addsy
))
13040 reloc
->addend
= pcrel_address
- S_GET_VALUE (fixp
->fx_subsy
);
13042 reloc
->addend
= fixp
->fx_addnumber
+ pcrel_address
;
13046 /* A gruesome hack which is a result of the gruesome gas reloc
13048 reloc
->addend
= pcrel_address
;
13052 reloc
->addend
= fixp
->fx_addnumber
;
13054 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13055 entry to be used in the relocation's section offset. */
13056 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13058 reloc
->address
= reloc
->addend
;
13062 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13063 fixup_segment converted a non-PC relative reloc into a PC
13064 relative reloc. In such a case, we need to convert the reloc
13066 code
= fixp
->fx_r_type
;
13067 if (fixp
->fx_pcrel
)
13072 code
= BFD_RELOC_8_PCREL
;
13075 code
= BFD_RELOC_16_PCREL
;
13078 code
= BFD_RELOC_32_PCREL
;
13081 code
= BFD_RELOC_64_PCREL
;
13083 case BFD_RELOC_8_PCREL
:
13084 case BFD_RELOC_16_PCREL
:
13085 case BFD_RELOC_32_PCREL
:
13086 case BFD_RELOC_64_PCREL
:
13087 case BFD_RELOC_16_PCREL_S2
:
13088 case BFD_RELOC_PCREL_HI16_S
:
13089 case BFD_RELOC_PCREL_LO16
:
13092 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13093 _("Cannot make %s relocation PC relative"),
13094 bfd_get_reloc_code_name (code
));
13098 /* To support a PC relative reloc when generating embedded PIC code
13099 for ECOFF, we use a Cygnus extension. We check for that here to
13100 make sure that we don't let such a reloc escape normally. */
13101 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13102 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13103 && code
== BFD_RELOC_16_PCREL_S2
13104 && mips_pic
!= EMBEDDED_PIC
)
13105 reloc
->howto
= NULL
;
13107 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13109 if (reloc
->howto
== NULL
)
13111 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13112 _("Can not represent %s relocation in this object file format"),
13113 bfd_get_reloc_code_name (code
));
13120 /* Relax a machine dependent frag. This returns the amount by which
13121 the current size of the frag should change. */
13124 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13126 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13128 offsetT old_var
= fragp
->fr_var
;
13130 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13132 return fragp
->fr_var
- old_var
;
13135 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13138 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13140 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13142 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13147 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13149 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13156 /* Convert a machine dependent frag. */
13159 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13161 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13164 unsigned long insn
;
13168 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13170 if (target_big_endian
)
13171 insn
= bfd_getb32 (buf
);
13173 insn
= bfd_getl32 (buf
);
13175 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13177 /* We generate a fixup instead of applying it right now
13178 because, if there are linker relaxations, we're going to
13179 need the relocations. */
13180 exp
.X_op
= O_symbol
;
13181 exp
.X_add_symbol
= fragp
->fr_symbol
;
13182 exp
.X_add_number
= fragp
->fr_offset
;
13184 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13186 BFD_RELOC_16_PCREL_S2
);
13187 fixp
->fx_file
= fragp
->fr_file
;
13188 fixp
->fx_line
= fragp
->fr_line
;
13190 md_number_to_chars (buf
, insn
, 4);
13197 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13198 _("relaxed out-of-range branch into a jump"));
13200 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13203 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13205 /* Reverse the branch. */
13206 switch ((insn
>> 28) & 0xf)
13209 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13210 have the condition reversed by tweaking a single
13211 bit, and their opcodes all have 0x4???????. */
13212 assert ((insn
& 0xf1000000) == 0x41000000);
13213 insn
^= 0x00010000;
13217 /* bltz 0x04000000 bgez 0x04010000
13218 bltzal 0x04100000 bgezal 0x04110000 */
13219 assert ((insn
& 0xfc0e0000) == 0x04000000);
13220 insn
^= 0x00010000;
13224 /* beq 0x10000000 bne 0x14000000
13225 blez 0x18000000 bgtz 0x1c000000 */
13226 insn
^= 0x04000000;
13234 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13236 /* Clear the and-link bit. */
13237 assert ((insn
& 0xfc1c0000) == 0x04100000);
13239 /* bltzal 0x04100000 bgezal 0x04110000
13240 bltzall 0x04120000 bgezall 0x04130000 */
13241 insn
&= ~0x00100000;
13244 /* Branch over the branch (if the branch was likely) or the
13245 full jump (not likely case). Compute the offset from the
13246 current instruction to branch to. */
13247 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13251 /* How many bytes in instructions we've already emitted? */
13252 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13253 /* How many bytes in instructions from here to the end? */
13254 i
= fragp
->fr_var
- i
;
13256 /* Convert to instruction count. */
13258 /* Branch counts from the next instruction. */
13261 /* Branch over the jump. */
13262 md_number_to_chars (buf
, insn
, 4);
13266 md_number_to_chars (buf
, 0, 4);
13269 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13271 /* beql $0, $0, 2f */
13273 /* Compute the PC offset from the current instruction to
13274 the end of the variable frag. */
13275 /* How many bytes in instructions we've already emitted? */
13276 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13277 /* How many bytes in instructions from here to the end? */
13278 i
= fragp
->fr_var
- i
;
13279 /* Convert to instruction count. */
13281 /* Don't decrement i, because we want to branch over the
13285 md_number_to_chars (buf
, insn
, 4);
13288 md_number_to_chars (buf
, 0, 4);
13293 if (mips_pic
== NO_PIC
)
13296 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13297 ? 0x0c000000 : 0x08000000);
13298 exp
.X_op
= O_symbol
;
13299 exp
.X_add_symbol
= fragp
->fr_symbol
;
13300 exp
.X_add_number
= fragp
->fr_offset
;
13302 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13303 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13304 fixp
->fx_file
= fragp
->fr_file
;
13305 fixp
->fx_line
= fragp
->fr_line
;
13307 md_number_to_chars (buf
, insn
, 4);
13312 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13313 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13314 exp
.X_op
= O_symbol
;
13315 exp
.X_add_symbol
= fragp
->fr_symbol
;
13316 exp
.X_add_number
= fragp
->fr_offset
;
13318 if (fragp
->fr_offset
)
13320 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13321 exp
.X_add_number
= 0;
13324 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13325 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13326 fixp
->fx_file
= fragp
->fr_file
;
13327 fixp
->fx_line
= fragp
->fr_line
;
13329 md_number_to_chars (buf
, insn
, 4);
13332 if (mips_opts
.isa
== ISA_MIPS1
)
13335 md_number_to_chars (buf
, 0, 4);
13339 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13340 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13342 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13343 4, &exp
, 0, BFD_RELOC_LO16
);
13344 fixp
->fx_file
= fragp
->fr_file
;
13345 fixp
->fx_line
= fragp
->fr_line
;
13347 md_number_to_chars (buf
, insn
, 4);
13351 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13356 md_number_to_chars (buf
, insn
, 4);
13361 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13362 + fragp
->fr_fix
+ fragp
->fr_var
);
13364 fragp
->fr_fix
+= fragp
->fr_var
;
13369 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13372 register const struct mips16_immed_operand
*op
;
13373 bfd_boolean small
, ext
;
13376 unsigned long insn
;
13377 bfd_boolean use_extend
;
13378 unsigned short extend
;
13380 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13381 op
= mips16_immed_operands
;
13382 while (op
->type
!= type
)
13385 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13396 resolve_symbol_value (fragp
->fr_symbol
);
13397 val
= S_GET_VALUE (fragp
->fr_symbol
);
13402 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13404 /* The rules for the base address of a PC relative reloc are
13405 complicated; see mips16_extended_frag. */
13406 if (type
== 'p' || type
== 'q')
13411 /* Ignore the low bit in the target, since it will be
13412 set for a text label. */
13413 if ((val
& 1) != 0)
13416 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13418 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13421 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13424 /* Make sure the section winds up with the alignment we have
13427 record_alignment (asec
, op
->shift
);
13431 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13432 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13433 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13434 _("extended instruction in delay slot"));
13436 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13438 if (target_big_endian
)
13439 insn
= bfd_getb16 (buf
);
13441 insn
= bfd_getl16 (buf
);
13443 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13444 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13445 small
, ext
, &insn
, &use_extend
, &extend
);
13449 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13450 fragp
->fr_fix
+= 2;
13454 md_number_to_chars (buf
, insn
, 2);
13455 fragp
->fr_fix
+= 2;
13463 first
= RELAX_FIRST (fragp
->fr_subtype
);
13464 second
= RELAX_SECOND (fragp
->fr_subtype
);
13465 fixp
= (fixS
*) fragp
->fr_opcode
;
13467 /* Possibly emit a warning if we've chosen the longer option. */
13468 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13469 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13471 const char *msg
= macro_warning (fragp
->fr_subtype
);
13473 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13476 /* Go through all the fixups for the first sequence. Disable them
13477 (by marking them as done) if we're going to use the second
13478 sequence instead. */
13480 && fixp
->fx_frag
== fragp
13481 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13483 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13485 fixp
= fixp
->fx_next
;
13488 /* Go through the fixups for the second sequence. Disable them if
13489 we're going to use the first sequence, otherwise adjust their
13490 addresses to account for the relaxation. */
13491 while (fixp
&& fixp
->fx_frag
== fragp
)
13493 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13494 fixp
->fx_where
-= first
;
13497 fixp
= fixp
->fx_next
;
13500 /* Now modify the frag contents. */
13501 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13505 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13506 memmove (start
, start
+ first
, second
);
13507 fragp
->fr_fix
-= first
;
13510 fragp
->fr_fix
-= second
;
13516 /* This function is called after the relocs have been generated.
13517 We've been storing mips16 text labels as odd. Here we convert them
13518 back to even for the convenience of the debugger. */
13521 mips_frob_file_after_relocs (void)
13524 unsigned int count
, i
;
13526 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13529 syms
= bfd_get_outsymbols (stdoutput
);
13530 count
= bfd_get_symcount (stdoutput
);
13531 for (i
= 0; i
< count
; i
++, syms
++)
13533 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13534 && ((*syms
)->value
& 1) != 0)
13536 (*syms
)->value
&= ~1;
13537 /* If the symbol has an odd size, it was probably computed
13538 incorrectly, so adjust that as well. */
13539 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13540 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13547 /* This function is called whenever a label is defined. It is used
13548 when handling branch delays; if a branch has a label, we assume we
13549 can not move it. */
13552 mips_define_label (symbolS
*sym
)
13554 struct insn_label_list
*l
;
13556 if (free_insn_labels
== NULL
)
13557 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13560 l
= free_insn_labels
;
13561 free_insn_labels
= l
->next
;
13565 l
->next
= insn_labels
;
13569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13571 /* Some special processing for a MIPS ELF file. */
13574 mips_elf_final_processing (void)
13576 /* Write out the register information. */
13577 if (mips_abi
!= N64_ABI
)
13581 s
.ri_gprmask
= mips_gprmask
;
13582 s
.ri_cprmask
[0] = mips_cprmask
[0];
13583 s
.ri_cprmask
[1] = mips_cprmask
[1];
13584 s
.ri_cprmask
[2] = mips_cprmask
[2];
13585 s
.ri_cprmask
[3] = mips_cprmask
[3];
13586 /* The gp_value field is set by the MIPS ELF backend. */
13588 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13589 ((Elf32_External_RegInfo
*)
13590 mips_regmask_frag
));
13594 Elf64_Internal_RegInfo s
;
13596 s
.ri_gprmask
= mips_gprmask
;
13598 s
.ri_cprmask
[0] = mips_cprmask
[0];
13599 s
.ri_cprmask
[1] = mips_cprmask
[1];
13600 s
.ri_cprmask
[2] = mips_cprmask
[2];
13601 s
.ri_cprmask
[3] = mips_cprmask
[3];
13602 /* The gp_value field is set by the MIPS ELF backend. */
13604 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13605 ((Elf64_External_RegInfo
*)
13606 mips_regmask_frag
));
13609 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13610 sort of BFD interface for this. */
13611 if (mips_any_noreorder
)
13612 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13613 if (mips_pic
!= NO_PIC
)
13615 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13616 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13619 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13621 /* Set MIPS ELF flags for ASEs. */
13622 if (file_ase_mips16
)
13623 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13624 #if 0 /* XXX FIXME */
13625 if (file_ase_mips3d
)
13626 elf_elfheader (stdoutput
)->e_flags
|= ???;
13629 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13631 /* Set the MIPS ELF ABI flags. */
13632 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13633 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13634 else if (mips_abi
== O64_ABI
)
13635 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13636 else if (mips_abi
== EABI_ABI
)
13638 if (!file_mips_gp32
)
13639 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13641 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13643 else if (mips_abi
== N32_ABI
)
13644 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13646 /* Nothing to do for N64_ABI. */
13648 if (mips_32bitmode
)
13649 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13652 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13654 typedef struct proc
{
13656 unsigned long reg_mask
;
13657 unsigned long reg_offset
;
13658 unsigned long fpreg_mask
;
13659 unsigned long fpreg_offset
;
13660 unsigned long frame_offset
;
13661 unsigned long frame_reg
;
13662 unsigned long pc_reg
;
13665 static procS cur_proc
;
13666 static procS
*cur_proc_ptr
;
13667 static int numprocs
;
13669 /* Fill in an rs_align_code fragment. */
13672 mips_handle_align (fragS
*fragp
)
13674 if (fragp
->fr_type
!= rs_align_code
)
13677 if (mips_opts
.mips16
)
13679 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13680 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13685 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13686 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13694 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13698 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13702 md_obj_begin (void)
13709 /* check for premature end, nesting errors, etc */
13711 as_warn (_("missing .end at end of assembly"));
13720 if (*input_line_pointer
== '-')
13722 ++input_line_pointer
;
13725 if (!ISDIGIT (*input_line_pointer
))
13726 as_bad (_("expected simple number"));
13727 if (input_line_pointer
[0] == '0')
13729 if (input_line_pointer
[1] == 'x')
13731 input_line_pointer
+= 2;
13732 while (ISXDIGIT (*input_line_pointer
))
13735 val
|= hex_value (*input_line_pointer
++);
13737 return negative
? -val
: val
;
13741 ++input_line_pointer
;
13742 while (ISDIGIT (*input_line_pointer
))
13745 val
|= *input_line_pointer
++ - '0';
13747 return negative
? -val
: val
;
13750 if (!ISDIGIT (*input_line_pointer
))
13752 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13753 *input_line_pointer
, *input_line_pointer
);
13754 as_warn (_("invalid number"));
13757 while (ISDIGIT (*input_line_pointer
))
13760 val
+= *input_line_pointer
++ - '0';
13762 return negative
? -val
: val
;
13765 /* The .file directive; just like the usual .file directive, but there
13766 is an initial number which is the ECOFF file index. In the non-ECOFF
13767 case .file implies DWARF-2. */
13770 s_mips_file (int x ATTRIBUTE_UNUSED
)
13772 static int first_file_directive
= 0;
13774 if (ECOFF_DEBUGGING
)
13783 filename
= dwarf2_directive_file (0);
13785 /* Versions of GCC up to 3.1 start files with a ".file"
13786 directive even for stabs output. Make sure that this
13787 ".file" is handled. Note that you need a version of GCC
13788 after 3.1 in order to support DWARF-2 on MIPS. */
13789 if (filename
!= NULL
&& ! first_file_directive
)
13791 (void) new_logical_line (filename
, -1);
13792 s_app_file_string (filename
);
13794 first_file_directive
= 1;
13798 /* The .loc directive, implying DWARF-2. */
13801 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13803 if (!ECOFF_DEBUGGING
)
13804 dwarf2_directive_loc (0);
13807 /* The .end directive. */
13810 s_mips_end (int x ATTRIBUTE_UNUSED
)
13814 /* Following functions need their own .frame and .cprestore directives. */
13815 mips_frame_reg_valid
= 0;
13816 mips_cprestore_valid
= 0;
13818 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13821 demand_empty_rest_of_line ();
13826 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13827 as_warn (_(".end not in text section"));
13831 as_warn (_(".end directive without a preceding .ent directive."));
13832 demand_empty_rest_of_line ();
13838 assert (S_GET_NAME (p
));
13839 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13840 as_warn (_(".end symbol does not match .ent symbol."));
13842 if (debug_type
== DEBUG_STABS
)
13843 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13847 as_warn (_(".end directive missing or unknown symbol"));
13850 /* Generate a .pdr section. */
13851 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13854 segT saved_seg
= now_seg
;
13855 subsegT saved_subseg
= now_subseg
;
13860 dot
= frag_now_fix ();
13862 #ifdef md_flush_pending_output
13863 md_flush_pending_output ();
13867 subseg_set (pdr_seg
, 0);
13869 /* Write the symbol. */
13870 exp
.X_op
= O_symbol
;
13871 exp
.X_add_symbol
= p
;
13872 exp
.X_add_number
= 0;
13873 emit_expr (&exp
, 4);
13875 fragp
= frag_more (7 * 4);
13877 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13878 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13879 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13880 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13881 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13882 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13883 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13885 subseg_set (saved_seg
, saved_subseg
);
13887 #endif /* OBJ_ELF */
13889 cur_proc_ptr
= NULL
;
13892 /* The .aent and .ent directives. */
13895 s_mips_ent (int aent
)
13899 symbolP
= get_symbol ();
13900 if (*input_line_pointer
== ',')
13901 ++input_line_pointer
;
13902 SKIP_WHITESPACE ();
13903 if (ISDIGIT (*input_line_pointer
)
13904 || *input_line_pointer
== '-')
13907 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13908 as_warn (_(".ent or .aent not in text section."));
13910 if (!aent
&& cur_proc_ptr
)
13911 as_warn (_("missing .end"));
13915 /* This function needs its own .frame and .cprestore directives. */
13916 mips_frame_reg_valid
= 0;
13917 mips_cprestore_valid
= 0;
13919 cur_proc_ptr
= &cur_proc
;
13920 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13922 cur_proc_ptr
->isym
= symbolP
;
13924 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13928 if (debug_type
== DEBUG_STABS
)
13929 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13930 S_GET_NAME (symbolP
));
13933 demand_empty_rest_of_line ();
13936 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13937 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13938 s_mips_frame is used so that we can set the PDR information correctly.
13939 We can't use the ecoff routines because they make reference to the ecoff
13940 symbol table (in the mdebug section). */
13943 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13946 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13950 if (cur_proc_ptr
== (procS
*) NULL
)
13952 as_warn (_(".frame outside of .ent"));
13953 demand_empty_rest_of_line ();
13957 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13959 SKIP_WHITESPACE ();
13960 if (*input_line_pointer
++ != ','
13961 || get_absolute_expression_and_terminator (&val
) != ',')
13963 as_warn (_("Bad .frame directive"));
13964 --input_line_pointer
;
13965 demand_empty_rest_of_line ();
13969 cur_proc_ptr
->frame_offset
= val
;
13970 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13972 demand_empty_rest_of_line ();
13975 #endif /* OBJ_ELF */
13979 /* The .fmask and .mask directives. If the mdebug section is present
13980 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13981 embedded targets, s_mips_mask is used so that we can set the PDR
13982 information correctly. We can't use the ecoff routines because they
13983 make reference to the ecoff symbol table (in the mdebug section). */
13986 s_mips_mask (int reg_type
)
13989 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13993 if (cur_proc_ptr
== (procS
*) NULL
)
13995 as_warn (_(".mask/.fmask outside of .ent"));
13996 demand_empty_rest_of_line ();
14000 if (get_absolute_expression_and_terminator (&mask
) != ',')
14002 as_warn (_("Bad .mask/.fmask directive"));
14003 --input_line_pointer
;
14004 demand_empty_rest_of_line ();
14008 off
= get_absolute_expression ();
14010 if (reg_type
== 'F')
14012 cur_proc_ptr
->fpreg_mask
= mask
;
14013 cur_proc_ptr
->fpreg_offset
= off
;
14017 cur_proc_ptr
->reg_mask
= mask
;
14018 cur_proc_ptr
->reg_offset
= off
;
14021 demand_empty_rest_of_line ();
14024 #endif /* OBJ_ELF */
14025 s_ignore (reg_type
);
14028 /* The .loc directive. */
14038 assert (now_seg
== text_section
);
14040 lineno
= get_number ();
14041 addroff
= frag_now_fix ();
14043 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14044 S_SET_TYPE (symbolP
, N_SLINE
);
14045 S_SET_OTHER (symbolP
, 0);
14046 S_SET_DESC (symbolP
, lineno
);
14047 symbolP
->sy_segment
= now_seg
;
14051 /* A table describing all the processors gas knows about. Names are
14052 matched in the order listed.
14054 To ease comparison, please keep this table in the same order as
14055 gcc's mips_cpu_info_table[]. */
14056 static const struct mips_cpu_info mips_cpu_info_table
[] =
14058 /* Entries for generic ISAs */
14059 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14060 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14061 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14062 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14063 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14064 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14065 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14066 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14067 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14070 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14071 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14072 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14075 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14078 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14079 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14080 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14081 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14082 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14083 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14084 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14085 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14086 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14087 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14088 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14089 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14092 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14093 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14094 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14095 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14096 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14097 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14098 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14099 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14100 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14101 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14102 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14103 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14104 { "rm9000", 0, ISA_MIPS4
, CPU_RM7000
},
14107 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14108 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14109 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14112 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14113 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14115 /* Broadcom SB-1 CPU core */
14116 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14123 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14124 with a final "000" replaced by "k". Ignore case.
14126 Note: this function is shared between GCC and GAS. */
14129 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14131 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14132 given
++, canonical
++;
14134 return ((*given
== 0 && *canonical
== 0)
14135 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14139 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14140 CPU name. We've traditionally allowed a lot of variation here.
14142 Note: this function is shared between GCC and GAS. */
14145 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14147 /* First see if the name matches exactly, or with a final "000"
14148 turned into "k". */
14149 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14152 /* If not, try comparing based on numerical designation alone.
14153 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14154 if (TOLOWER (*given
) == 'r')
14156 if (!ISDIGIT (*given
))
14159 /* Skip over some well-known prefixes in the canonical name,
14160 hoping to find a number there too. */
14161 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14163 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14165 else if (TOLOWER (canonical
[0]) == 'r')
14168 return mips_strict_matching_cpu_name_p (canonical
, given
);
14172 /* Parse an option that takes the name of a processor as its argument.
14173 OPTION is the name of the option and CPU_STRING is the argument.
14174 Return the corresponding processor enumeration if the CPU_STRING is
14175 recognized, otherwise report an error and return null.
14177 A similar function exists in GCC. */
14179 static const struct mips_cpu_info
*
14180 mips_parse_cpu (const char *option
, const char *cpu_string
)
14182 const struct mips_cpu_info
*p
;
14184 /* 'from-abi' selects the most compatible architecture for the given
14185 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14186 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14187 version. Look first at the -mgp options, if given, otherwise base
14188 the choice on MIPS_DEFAULT_64BIT.
14190 Treat NO_ABI like the EABIs. One reason to do this is that the
14191 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14192 architecture. This code picks MIPS I for 'mips' and MIPS III for
14193 'mips64', just as we did in the days before 'from-abi'. */
14194 if (strcasecmp (cpu_string
, "from-abi") == 0)
14196 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14197 return mips_cpu_info_from_isa (ISA_MIPS1
);
14199 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14200 return mips_cpu_info_from_isa (ISA_MIPS3
);
14202 if (file_mips_gp32
>= 0)
14203 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14205 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14210 /* 'default' has traditionally been a no-op. Probably not very useful. */
14211 if (strcasecmp (cpu_string
, "default") == 0)
14214 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14215 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14218 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14222 /* Return the canonical processor information for ISA (a member of the
14223 ISA_MIPS* enumeration). */
14225 static const struct mips_cpu_info
*
14226 mips_cpu_info_from_isa (int isa
)
14230 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14231 if (mips_cpu_info_table
[i
].is_isa
14232 && isa
== mips_cpu_info_table
[i
].isa
)
14233 return (&mips_cpu_info_table
[i
]);
14238 static const struct mips_cpu_info
*
14239 mips_cpu_info_from_arch (int arch
)
14243 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14244 if (arch
== mips_cpu_info_table
[i
].cpu
)
14245 return (&mips_cpu_info_table
[i
]);
14251 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14255 fprintf (stream
, "%24s", "");
14260 fprintf (stream
, ", ");
14264 if (*col_p
+ strlen (string
) > 72)
14266 fprintf (stream
, "\n%24s", "");
14270 fprintf (stream
, "%s", string
);
14271 *col_p
+= strlen (string
);
14277 md_show_usage (FILE *stream
)
14282 fprintf (stream
, _("\
14284 -EB generate big endian output\n\
14285 -EL generate little endian output\n\
14286 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14287 -G NUM allow referencing objects up to NUM bytes\n\
14288 implicitly with the gp register [default 8]\n"));
14289 fprintf (stream
, _("\
14290 -mips1 generate MIPS ISA I instructions\n\
14291 -mips2 generate MIPS ISA II instructions\n\
14292 -mips3 generate MIPS ISA III instructions\n\
14293 -mips4 generate MIPS ISA IV instructions\n\
14294 -mips5 generate MIPS ISA V instructions\n\
14295 -mips32 generate MIPS32 ISA instructions\n\
14296 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14297 -mips64 generate MIPS64 ISA instructions\n\
14298 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14299 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14303 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14304 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14305 show (stream
, "from-abi", &column
, &first
);
14306 fputc ('\n', stream
);
14308 fprintf (stream
, _("\
14309 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14310 -no-mCPU don't generate code specific to CPU.\n\
14311 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14315 show (stream
, "3900", &column
, &first
);
14316 show (stream
, "4010", &column
, &first
);
14317 show (stream
, "4100", &column
, &first
);
14318 show (stream
, "4650", &column
, &first
);
14319 fputc ('\n', stream
);
14321 fprintf (stream
, _("\
14322 -mips16 generate mips16 instructions\n\
14323 -no-mips16 do not generate mips16 instructions\n"));
14324 fprintf (stream
, _("\
14325 -mfix-vr4120 work around certain VR4120 errata\n\
14326 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14327 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14328 -O0 remove unneeded NOPs, do not swap branches\n\
14329 -O remove unneeded NOPs and swap branches\n\
14330 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14331 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14332 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14334 fprintf (stream
, _("\
14335 -KPIC, -call_shared generate SVR4 position independent code\n\
14336 -non_shared do not generate position independent code\n\
14337 -xgot assume a 32 bit GOT\n\
14338 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14339 -mabi=ABI create ABI conformant object file for:\n"));
14343 show (stream
, "32", &column
, &first
);
14344 show (stream
, "o64", &column
, &first
);
14345 show (stream
, "n32", &column
, &first
);
14346 show (stream
, "64", &column
, &first
);
14347 show (stream
, "eabi", &column
, &first
);
14349 fputc ('\n', stream
);
14351 fprintf (stream
, _("\
14352 -32 create o32 ABI object file (default)\n\
14353 -n32 create n32 ABI object file\n\
14354 -64 create 64 ABI object file\n"));
14359 mips_dwarf2_format (void)
14361 if (mips_abi
== N64_ABI
)
14364 return dwarf2_format_64bit_irix
;
14366 return dwarf2_format_64bit
;
14370 return dwarf2_format_32bit
;
14374 mips_dwarf2_addr_size (void)
14376 if (mips_abi
== N64_ABI
)