1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2019 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && ((CPU) != CPU_GS464 \
426 || (CPU) != CPU_GS464E \
427 || (CPU) != CPU_GS264E))
429 /* Return true if ISA supports move to/from high part of a 64-bit
430 floating-point register. */
431 #define ISA_HAS_MXHC1(ISA) \
432 ((ISA) == ISA_MIPS32R2 \
433 || (ISA) == ISA_MIPS32R3 \
434 || (ISA) == ISA_MIPS32R5 \
435 || (ISA) == ISA_MIPS32R6 \
436 || (ISA) == ISA_MIPS64R2 \
437 || (ISA) == ISA_MIPS64R3 \
438 || (ISA) == ISA_MIPS64R5 \
439 || (ISA) == ISA_MIPS64R6)
441 /* Return true if ISA supports legacy NAN. */
442 #define ISA_HAS_LEGACY_NAN(ISA) \
443 ((ISA) == ISA_MIPS1 \
444 || (ISA) == ISA_MIPS2 \
445 || (ISA) == ISA_MIPS3 \
446 || (ISA) == ISA_MIPS4 \
447 || (ISA) == ISA_MIPS5 \
448 || (ISA) == ISA_MIPS32 \
449 || (ISA) == ISA_MIPS32R2 \
450 || (ISA) == ISA_MIPS32R3 \
451 || (ISA) == ISA_MIPS32R5 \
452 || (ISA) == ISA_MIPS64 \
453 || (ISA) == ISA_MIPS64R2 \
454 || (ISA) == ISA_MIPS64R3 \
455 || (ISA) == ISA_MIPS64R5)
458 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
463 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
467 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
469 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
471 /* True if relocations are stored in-place. */
472 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
474 /* The ABI-derived address size. */
475 #define HAVE_64BIT_ADDRESSES \
476 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
477 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
479 /* The size of symbolic constants (i.e., expressions of the form
480 "SYMBOL" or "SYMBOL + OFFSET"). */
481 #define HAVE_32BIT_SYMBOLS \
482 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
483 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
485 /* Addresses are loaded in different ways, depending on the address size
486 in use. The n32 ABI Documentation also mandates the use of additions
487 with overflow checking, but existing implementations don't follow it. */
488 #define ADDRESS_ADD_INSN \
489 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
491 #define ADDRESS_ADDI_INSN \
492 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
494 #define ADDRESS_LOAD_INSN \
495 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
497 #define ADDRESS_STORE_INSN \
498 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
500 /* Return true if the given CPU supports the MIPS16 ASE. */
501 #define CPU_HAS_MIPS16(cpu) \
502 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
503 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
505 /* Return true if the given CPU supports the microMIPS ASE. */
506 #define CPU_HAS_MICROMIPS(cpu) 0
508 /* True if CPU has a dror instruction. */
509 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
511 /* True if CPU has a ror instruction. */
512 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
514 /* True if CPU is in the Octeon family */
515 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
516 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
518 /* True if CPU has seq/sne and seqi/snei instructions. */
519 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
521 /* True, if CPU has support for ldc1 and sdc1. */
522 #define CPU_HAS_LDC1_SDC1(CPU) \
523 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
525 /* True if mflo and mfhi can be immediately followed by instructions
526 which write to the HI and LO registers.
528 According to MIPS specifications, MIPS ISAs I, II, and III need
529 (at least) two instructions between the reads of HI/LO and
530 instructions which write them, and later ISAs do not. Contradicting
531 the MIPS specifications, some MIPS IV processor user manuals (e.g.
532 the UM for the NEC Vr5000) document needing the instructions between
533 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
534 MIPS64 and later ISAs to have the interlocks, plus any specific
535 earlier-ISA CPUs for which CPU documentation declares that the
536 instructions are really interlocked. */
537 #define hilo_interlocks \
538 (mips_opts.isa == ISA_MIPS32 \
539 || mips_opts.isa == ISA_MIPS32R2 \
540 || mips_opts.isa == ISA_MIPS32R3 \
541 || mips_opts.isa == ISA_MIPS32R5 \
542 || mips_opts.isa == ISA_MIPS32R6 \
543 || mips_opts.isa == ISA_MIPS64 \
544 || mips_opts.isa == ISA_MIPS64R2 \
545 || mips_opts.isa == ISA_MIPS64R3 \
546 || mips_opts.isa == ISA_MIPS64R5 \
547 || mips_opts.isa == ISA_MIPS64R6 \
548 || mips_opts.arch == CPU_R4010 \
549 || mips_opts.arch == CPU_R5900 \
550 || mips_opts.arch == CPU_R10000 \
551 || mips_opts.arch == CPU_R12000 \
552 || mips_opts.arch == CPU_R14000 \
553 || mips_opts.arch == CPU_R16000 \
554 || mips_opts.arch == CPU_RM7000 \
555 || mips_opts.arch == CPU_VR5500 \
556 || mips_opts.micromips \
559 /* Whether the processor uses hardware interlocks to protect reads
560 from the GPRs after they are loaded from memory, and thus does not
561 require nops to be inserted. This applies to instructions marked
562 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
563 level I and microMIPS mode instructions are always interlocked. */
564 #define gpr_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.arch == CPU_R3900 \
567 || mips_opts.arch == CPU_R5900 \
568 || mips_opts.micromips \
571 /* Whether the processor uses hardware interlocks to avoid delays
572 required by coprocessor instructions, and thus does not require
573 nops to be inserted. This applies to instructions marked
574 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
575 instructions marked INSN_WRITE_COND_CODE and ones marked
576 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
577 levels I, II, and III and microMIPS mode instructions are always
579 /* Itbl support may require additional care here. */
580 #define cop_interlocks \
581 ((mips_opts.isa != ISA_MIPS1 \
582 && mips_opts.isa != ISA_MIPS2 \
583 && mips_opts.isa != ISA_MIPS3) \
584 || mips_opts.arch == CPU_R4300 \
585 || mips_opts.micromips \
588 /* Whether the processor uses hardware interlocks to protect reads
589 from coprocessor registers after they are loaded from memory, and
590 thus does not require nops to be inserted. This applies to
591 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
592 requires at MIPS ISA level I and microMIPS mode instructions are
593 always interlocked. */
594 #define cop_mem_interlocks \
595 (mips_opts.isa != ISA_MIPS1 \
596 || mips_opts.micromips \
599 /* Is this a mfhi or mflo instruction? */
600 #define MF_HILO_INSN(PINFO) \
601 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
603 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
604 has been selected. This implies, in particular, that addresses of text
605 labels have their LSB set. */
606 #define HAVE_CODE_COMPRESSION \
607 ((mips_opts.mips16 | mips_opts.micromips) != 0)
609 /* The minimum and maximum signed values that can be stored in a GPR. */
610 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
611 #define GPR_SMIN (-GPR_SMAX - 1)
613 /* MIPS PIC level. */
615 enum mips_pic_level mips_pic
;
617 /* 1 if we should generate 32 bit offsets from the $gp register in
618 SVR4_PIC mode. Currently has no meaning in other modes. */
619 static int mips_big_got
= 0;
621 /* 1 if trap instructions should used for overflow rather than break
623 static int mips_trap
= 0;
625 /* 1 if double width floating point constants should not be constructed
626 by assembling two single width halves into two single width floating
627 point registers which just happen to alias the double width destination
628 register. On some architectures this aliasing can be disabled by a bit
629 in the status register, and the setting of this bit cannot be determined
630 automatically at assemble time. */
631 static int mips_disable_float_construction
;
633 /* Non-zero if any .set noreorder directives were used. */
635 static int mips_any_noreorder
;
637 /* Non-zero if nops should be inserted when the register referenced in
638 an mfhi/mflo instruction is read in the next two instructions. */
639 static int mips_7000_hilo_fix
;
641 /* The size of objects in the small data section. */
642 static unsigned int g_switch_value
= 8;
643 /* Whether the -G option was used. */
644 static int g_switch_seen
= 0;
649 /* If we can determine in advance that GP optimization won't be
650 possible, we can skip the relaxation stuff that tries to produce
651 GP-relative references. This makes delay slot optimization work
654 This function can only provide a guess, but it seems to work for
655 gcc output. It needs to guess right for gcc, otherwise gcc
656 will put what it thinks is a GP-relative instruction in a branch
659 I don't know if a fix is needed for the SVR4_PIC mode. I've only
660 fixed it for the non-PIC mode. KR 95/04/07 */
661 static int nopic_need_relax (symbolS
*, int);
663 /* handle of the OPCODE hash table */
664 static struct hash_control
*op_hash
= NULL
;
666 /* The opcode hash table we use for the mips16. */
667 static struct hash_control
*mips16_op_hash
= NULL
;
669 /* The opcode hash table we use for the microMIPS ASE. */
670 static struct hash_control
*micromips_op_hash
= NULL
;
672 /* This array holds the chars that always start a comment. If the
673 pre-processor is disabled, these aren't very useful */
674 const char comment_chars
[] = "#";
676 /* This array holds the chars that only start a comment at the beginning of
677 a line. If the line seems to have the form '# 123 filename'
678 .line and .file directives will appear in the pre-processed output */
679 /* Note that input_file.c hand checks for '#' at the beginning of the
680 first line of the input file. This is because the compiler outputs
681 #NO_APP at the beginning of its output. */
682 /* Also note that C style comments are always supported. */
683 const char line_comment_chars
[] = "#";
685 /* This array holds machine specific line separator characters. */
686 const char line_separator_chars
[] = ";";
688 /* Chars that can be used to separate mant from exp in floating point nums */
689 const char EXP_CHARS
[] = "eE";
691 /* Chars that mean this number is a floating point constant */
694 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
696 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
697 changed in read.c . Ideally it shouldn't have to know about it at all,
698 but nothing is ideal around here.
701 /* Types of printf format used for instruction-related error messages.
702 "I" means int ("%d") and "S" means string ("%s"). */
703 enum mips_insn_error_format
{
709 /* Information about an error that was found while assembling the current
711 struct mips_insn_error
{
712 /* We sometimes need to match an instruction against more than one
713 opcode table entry. Errors found during this matching are reported
714 against a particular syntactic argument rather than against the
715 instruction as a whole. We grade these messages so that errors
716 against argument N have a greater priority than an error against
717 any argument < N, since the former implies that arguments up to N
718 were acceptable and that the opcode entry was therefore a closer match.
719 If several matches report an error against the same argument,
720 we only use that error if it is the same in all cases.
722 min_argnum is the minimum argument number for which an error message
723 should be accepted. It is 0 if MSG is against the instruction as
727 /* The printf()-style message, including its format and arguments. */
728 enum mips_insn_error_format format
;
736 /* The error that should be reported for the current instruction. */
737 static struct mips_insn_error insn_error
;
739 static int auto_align
= 1;
741 /* When outputting SVR4 PIC code, the assembler needs to know the
742 offset in the stack frame from which to restore the $gp register.
743 This is set by the .cprestore pseudo-op, and saved in this
745 static offsetT mips_cprestore_offset
= -1;
747 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
748 more optimizations, it can use a register value instead of a memory-saved
749 offset and even an other register than $gp as global pointer. */
750 static offsetT mips_cpreturn_offset
= -1;
751 static int mips_cpreturn_register
= -1;
752 static int mips_gp_register
= GP
;
753 static int mips_gprel_offset
= 0;
755 /* Whether mips_cprestore_offset has been set in the current function
756 (or whether it has already been warned about, if not). */
757 static int mips_cprestore_valid
= 0;
759 /* This is the register which holds the stack frame, as set by the
760 .frame pseudo-op. This is needed to implement .cprestore. */
761 static int mips_frame_reg
= SP
;
763 /* Whether mips_frame_reg has been set in the current function
764 (or whether it has already been warned about, if not). */
765 static int mips_frame_reg_valid
= 0;
767 /* To output NOP instructions correctly, we need to keep information
768 about the previous two instructions. */
770 /* Whether we are optimizing. The default value of 2 means to remove
771 unneeded NOPs and swap branch instructions when possible. A value
772 of 1 means to not swap branches. A value of 0 means to always
774 static int mips_optimize
= 2;
776 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
777 equivalent to seeing no -g option at all. */
778 static int mips_debug
= 0;
780 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
781 #define MAX_VR4130_NOPS 4
783 /* The maximum number of NOPs needed to fill delay slots. */
784 #define MAX_DELAY_NOPS 2
786 /* The maximum number of NOPs needed for any purpose. */
789 /* A list of previous instructions, with index 0 being the most recent.
790 We need to look back MAX_NOPS instructions when filling delay slots
791 or working around processor errata. We need to look back one
792 instruction further if we're thinking about using history[0] to
793 fill a branch delay slot. */
794 static struct mips_cl_insn history
[1 + MAX_NOPS
];
796 /* Arrays of operands for each instruction. */
797 #define MAX_OPERANDS 6
798 struct mips_operand_array
{
799 const struct mips_operand
*operand
[MAX_OPERANDS
];
801 static struct mips_operand_array
*mips_operands
;
802 static struct mips_operand_array
*mips16_operands
;
803 static struct mips_operand_array
*micromips_operands
;
805 /* Nop instructions used by emit_nop. */
806 static struct mips_cl_insn nop_insn
;
807 static struct mips_cl_insn mips16_nop_insn
;
808 static struct mips_cl_insn micromips_nop16_insn
;
809 static struct mips_cl_insn micromips_nop32_insn
;
811 /* The appropriate nop for the current mode. */
812 #define NOP_INSN (mips_opts.mips16 \
814 : (mips_opts.micromips \
815 ? (mips_opts.insn32 \
816 ? µmips_nop32_insn \
817 : µmips_nop16_insn) \
820 /* The size of NOP_INSN in bytes. */
821 #define NOP_INSN_SIZE ((mips_opts.mips16 \
822 || (mips_opts.micromips && !mips_opts.insn32)) \
825 /* If this is set, it points to a frag holding nop instructions which
826 were inserted before the start of a noreorder section. If those
827 nops turn out to be unnecessary, the size of the frag can be
829 static fragS
*prev_nop_frag
;
831 /* The number of nop instructions we created in prev_nop_frag. */
832 static int prev_nop_frag_holds
;
834 /* The number of nop instructions that we know we need in
836 static int prev_nop_frag_required
;
838 /* The number of instructions we've seen since prev_nop_frag. */
839 static int prev_nop_frag_since
;
841 /* Relocations against symbols are sometimes done in two parts, with a HI
842 relocation and a LO relocation. Each relocation has only 16 bits of
843 space to store an addend. This means that in order for the linker to
844 handle carries correctly, it must be able to locate both the HI and
845 the LO relocation. This means that the relocations must appear in
846 order in the relocation table.
848 In order to implement this, we keep track of each unmatched HI
849 relocation. We then sort them so that they immediately precede the
850 corresponding LO relocation. */
855 struct mips_hi_fixup
*next
;
858 /* The section this fixup is in. */
862 /* The list of unmatched HI relocs. */
864 static struct mips_hi_fixup
*mips_hi_fixup_list
;
866 /* The frag containing the last explicit relocation operator.
867 Null if explicit relocations have not been used. */
869 static fragS
*prev_reloc_op_frag
;
871 /* Map mips16 register numbers to normal MIPS register numbers. */
873 static const unsigned int mips16_to_32_reg_map
[] =
875 16, 17, 2, 3, 4, 5, 6, 7
878 /* Map microMIPS register numbers to normal MIPS register numbers. */
880 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
882 /* The microMIPS registers with type h. */
883 static const unsigned int micromips_to_32_reg_h_map1
[] =
885 5, 5, 6, 4, 4, 4, 4, 4
887 static const unsigned int micromips_to_32_reg_h_map2
[] =
889 6, 7, 7, 21, 22, 5, 6, 7
892 /* The microMIPS registers with type m. */
893 static const unsigned int micromips_to_32_reg_m_map
[] =
895 0, 17, 2, 3, 16, 18, 19, 20
898 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
900 /* Classifies the kind of instructions we're interested in when
901 implementing -mfix-vr4120. */
902 enum fix_vr4120_class
910 NUM_FIX_VR4120_CLASSES
913 /* ...likewise -mfix-loongson2f-jump. */
914 static bfd_boolean mips_fix_loongson2f_jump
;
916 /* ...likewise -mfix-loongson2f-nop. */
917 static bfd_boolean mips_fix_loongson2f_nop
;
919 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
920 static bfd_boolean mips_fix_loongson2f
;
922 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
923 there must be at least one other instruction between an instruction
924 of type X and an instruction of type Y. */
925 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
927 /* True if -mfix-vr4120 is in force. */
928 static int mips_fix_vr4120
;
930 /* ...likewise -mfix-vr4130. */
931 static int mips_fix_vr4130
;
933 /* ...likewise -mfix-24k. */
934 static int mips_fix_24k
;
936 /* ...likewise -mfix-rm7000 */
937 static int mips_fix_rm7000
;
939 /* ...likewise -mfix-cn63xxp1 */
940 static bfd_boolean mips_fix_cn63xxp1
;
942 /* ...likewise -mfix-r5900 */
943 static bfd_boolean mips_fix_r5900
;
944 static bfd_boolean mips_fix_r5900_explicit
;
946 /* We don't relax branches by default, since this causes us to expand
947 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
948 fail to compute the offset before expanding the macro to the most
949 efficient expansion. */
951 static int mips_relax_branch
;
953 /* TRUE if checks are suppressed for invalid branches between ISA modes.
954 Needed for broken assembly produced by some GCC versions and some
955 sloppy code out there, where branches to data labels are present. */
956 static bfd_boolean mips_ignore_branch_isa
;
958 /* The expansion of many macros depends on the type of symbol that
959 they refer to. For example, when generating position-dependent code,
960 a macro that refers to a symbol may have two different expansions,
961 one which uses GP-relative addresses and one which uses absolute
962 addresses. When generating SVR4-style PIC, a macro may have
963 different expansions for local and global symbols.
965 We handle these situations by generating both sequences and putting
966 them in variant frags. In position-dependent code, the first sequence
967 will be the GP-relative one and the second sequence will be the
968 absolute one. In SVR4 PIC, the first sequence will be for global
969 symbols and the second will be for local symbols.
971 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
972 SECOND are the lengths of the two sequences in bytes. These fields
973 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
974 the subtype has the following flags:
977 Set if generating PIC code.
980 Set if it has been decided that we should use the second
981 sequence instead of the first.
984 Set in the first variant frag if the macro's second implementation
985 is longer than its first. This refers to the macro as a whole,
986 not an individual relaxation.
989 Set in the first variant frag if the macro appeared in a .set nomacro
990 block and if one alternative requires a warning but the other does not.
993 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
996 RELAX_DELAY_SLOT_16BIT
997 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1000 RELAX_DELAY_SLOT_SIZE_FIRST
1001 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1002 the macro is of the wrong size for the branch delay slot.
1004 RELAX_DELAY_SLOT_SIZE_SECOND
1005 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1006 the macro is of the wrong size for the branch delay slot.
1008 The frag's "opcode" points to the first fixup for relaxable code.
1010 Relaxable macros are generated using a sequence such as:
1012 relax_start (SYMBOL);
1013 ... generate first expansion ...
1015 ... generate second expansion ...
1018 The code and fixups for the unwanted alternative are discarded
1019 by md_convert_frag. */
1020 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1021 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1023 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1024 #define RELAX_SECOND(X) ((X) & 0xff)
1025 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1026 #define RELAX_USE_SECOND 0x20000
1027 #define RELAX_SECOND_LONGER 0x40000
1028 #define RELAX_NOMACRO 0x80000
1029 #define RELAX_DELAY_SLOT 0x100000
1030 #define RELAX_DELAY_SLOT_16BIT 0x200000
1031 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1032 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1034 /* Branch without likely bit. If label is out of range, we turn:
1036 beq reg1, reg2, label
1046 with the following opcode replacements:
1053 bltzal <-> bgezal (with jal label instead of j label)
1055 Even though keeping the delay slot instruction in the delay slot of
1056 the branch would be more efficient, it would be very tricky to do
1057 correctly, because we'd have to introduce a variable frag *after*
1058 the delay slot instruction, and expand that instead. Let's do it
1059 the easy way for now, even if the branch-not-taken case now costs
1060 one additional instruction. Out-of-range branches are not supposed
1061 to be common, anyway.
1063 Branch likely. If label is out of range, we turn:
1065 beql reg1, reg2, label
1066 delay slot (annulled if branch not taken)
1075 delay slot (executed only if branch taken)
1078 It would be possible to generate a shorter sequence by losing the
1079 likely bit, generating something like:
1084 delay slot (executed only if branch taken)
1096 bltzall -> bgezal (with jal label instead of j label)
1097 bgezall -> bltzal (ditto)
1100 but it's not clear that it would actually improve performance. */
1101 #define RELAX_BRANCH_ENCODE(at, pic, \
1102 uncond, likely, link, toofar) \
1103 ((relax_substateT) \
1106 | ((pic) ? 0x20 : 0) \
1107 | ((toofar) ? 0x40 : 0) \
1108 | ((link) ? 0x80 : 0) \
1109 | ((likely) ? 0x100 : 0) \
1110 | ((uncond) ? 0x200 : 0)))
1111 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1112 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1113 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1114 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1115 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1116 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1117 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1119 /* For mips16 code, we use an entirely different form of relaxation.
1120 mips16 supports two versions of most instructions which take
1121 immediate values: a small one which takes some small value, and a
1122 larger one which takes a 16 bit value. Since branches also follow
1123 this pattern, relaxing these values is required.
1125 We can assemble both mips16 and normal MIPS code in a single
1126 object. Therefore, we need to support this type of relaxation at
1127 the same time that we support the relaxation described above. We
1128 use the high bit of the subtype field to distinguish these cases.
1130 The information we store for this type of relaxation is the
1131 argument code found in the opcode file for this relocation, whether
1132 the user explicitly requested a small or extended form, and whether
1133 the relocation is in a jump or jal delay slot. That tells us the
1134 size of the value, and how it should be stored. We also store
1135 whether the fragment is considered to be extended or not. We also
1136 store whether this is known to be a branch to a different section,
1137 whether we have tried to relax this frag yet, and whether we have
1138 ever extended a PC relative fragment because of a shift count. */
1139 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1144 | ((e2) ? 0x100 : 0) \
1145 | ((pic) ? 0x200 : 0) \
1146 | ((sym32) ? 0x400 : 0) \
1147 | ((nomacro) ? 0x800 : 0) \
1148 | ((small) ? 0x1000 : 0) \
1149 | ((ext) ? 0x2000 : 0) \
1150 | ((dslot) ? 0x4000 : 0) \
1151 | ((jal_dslot) ? 0x8000 : 0))
1153 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1154 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1155 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1156 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1157 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1158 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1159 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1160 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1161 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1162 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1164 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1165 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1166 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1167 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1168 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1169 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1170 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1171 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1172 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1174 /* For microMIPS code, we use relaxation similar to one we use for
1175 MIPS16 code. Some instructions that take immediate values support
1176 two encodings: a small one which takes some small value, and a
1177 larger one which takes a 16 bit value. As some branches also follow
1178 this pattern, relaxing these values is required.
1180 We can assemble both microMIPS and normal MIPS code in a single
1181 object. Therefore, we need to support this type of relaxation at
1182 the same time that we support the relaxation described above. We
1183 use one of the high bits of the subtype field to distinguish these
1186 The information we store for this type of relaxation is the argument
1187 code found in the opcode file for this relocation, the register
1188 selected as the assembler temporary, whether in the 32-bit
1189 instruction mode, whether the branch is unconditional, whether it is
1190 compact, whether there is no delay-slot instruction available to fill
1191 in, whether it stores the link address implicitly in $ra, whether
1192 relaxation of out-of-range 32-bit branches to a sequence of
1193 instructions is enabled, and whether the displacement of a branch is
1194 too large to fit as an immediate argument of a 16-bit and a 32-bit
1195 branch, respectively. */
1196 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1197 uncond, compact, link, nods, \
1198 relax32, toofar16, toofar32) \
1201 | (((at) & 0x1f) << 8) \
1202 | ((insn32) ? 0x2000 : 0) \
1203 | ((pic) ? 0x4000 : 0) \
1204 | ((uncond) ? 0x8000 : 0) \
1205 | ((compact) ? 0x10000 : 0) \
1206 | ((link) ? 0x20000 : 0) \
1207 | ((nods) ? 0x40000 : 0) \
1208 | ((relax32) ? 0x80000 : 0) \
1209 | ((toofar16) ? 0x100000 : 0) \
1210 | ((toofar32) ? 0x200000 : 0))
1211 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1212 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1213 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1214 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1215 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1216 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1217 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1218 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1219 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1220 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1222 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1223 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1224 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1225 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1226 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1227 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1229 /* Sign-extend 16-bit value X. */
1230 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1232 /* Is the given value a sign-extended 32-bit value? */
1233 #define IS_SEXT_32BIT_NUM(x) \
1234 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1235 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1237 /* Is the given value a sign-extended 16-bit value? */
1238 #define IS_SEXT_16BIT_NUM(x) \
1239 (((x) &~ (offsetT) 0x7fff) == 0 \
1240 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1242 /* Is the given value a sign-extended 12-bit value? */
1243 #define IS_SEXT_12BIT_NUM(x) \
1244 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1246 /* Is the given value a sign-extended 9-bit value? */
1247 #define IS_SEXT_9BIT_NUM(x) \
1248 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1250 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1251 #define IS_ZEXT_32BIT_NUM(x) \
1252 (((x) &~ (offsetT) 0xffffffff) == 0 \
1253 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1255 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1257 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1258 (((STRUCT) >> (SHIFT)) & (MASK))
1260 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1261 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1263 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1264 : EXTRACT_BITS ((INSN).insn_opcode, \
1265 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1266 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1267 EXTRACT_BITS ((INSN).insn_opcode, \
1268 MIPS16OP_MASK_##FIELD, \
1269 MIPS16OP_SH_##FIELD)
1271 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1272 #define MIPS16_EXTEND (0xf000U << 16)
1274 /* Whether or not we are emitting a branch-likely macro. */
1275 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1277 /* Global variables used when generating relaxable macros. See the
1278 comment above RELAX_ENCODE for more details about how relaxation
1281 /* 0 if we're not emitting a relaxable macro.
1282 1 if we're emitting the first of the two relaxation alternatives.
1283 2 if we're emitting the second alternative. */
1286 /* The first relaxable fixup in the current frag. (In other words,
1287 the first fixup that refers to relaxable code.) */
1290 /* sizes[0] says how many bytes of the first alternative are stored in
1291 the current frag. Likewise sizes[1] for the second alternative. */
1292 unsigned int sizes
[2];
1294 /* The symbol on which the choice of sequence depends. */
1298 /* Global variables used to decide whether a macro needs a warning. */
1300 /* True if the macro is in a branch delay slot. */
1301 bfd_boolean delay_slot_p
;
1303 /* Set to the length in bytes required if the macro is in a delay slot
1304 that requires a specific length of instruction, otherwise zero. */
1305 unsigned int delay_slot_length
;
1307 /* For relaxable macros, sizes[0] is the length of the first alternative
1308 in bytes and sizes[1] is the length of the second alternative.
1309 For non-relaxable macros, both elements give the length of the
1311 unsigned int sizes
[2];
1313 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1314 instruction of the first alternative in bytes and first_insn_sizes[1]
1315 is the length of the first instruction of the second alternative.
1316 For non-relaxable macros, both elements give the length of the first
1317 instruction in bytes.
1319 Set to zero if we haven't yet seen the first instruction. */
1320 unsigned int first_insn_sizes
[2];
1322 /* For relaxable macros, insns[0] is the number of instructions for the
1323 first alternative and insns[1] is the number of instructions for the
1326 For non-relaxable macros, both elements give the number of
1327 instructions for the macro. */
1328 unsigned int insns
[2];
1330 /* The first variant frag for this macro. */
1332 } mips_macro_warning
;
1334 /* Prototypes for static functions. */
1336 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1338 static void append_insn
1339 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1340 bfd_boolean expansionp
);
1341 static void mips_no_prev_insn (void);
1342 static void macro_build (expressionS
*, const char *, const char *, ...);
1343 static void mips16_macro_build
1344 (expressionS
*, const char *, const char *, va_list *);
1345 static void load_register (int, expressionS
*, int);
1346 static void macro_start (void);
1347 static void macro_end (void);
1348 static void macro (struct mips_cl_insn
*ip
, char *str
);
1349 static void mips16_macro (struct mips_cl_insn
* ip
);
1350 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1351 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1352 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1353 static void mips16_immed
1354 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1355 unsigned int, unsigned long *);
1356 static size_t my_getSmallExpression
1357 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1358 static void my_getExpression (expressionS
*, char *);
1359 static void s_align (int);
1360 static void s_change_sec (int);
1361 static void s_change_section (int);
1362 static void s_cons (int);
1363 static void s_float_cons (int);
1364 static void s_mips_globl (int);
1365 static void s_option (int);
1366 static void s_mipsset (int);
1367 static void s_abicalls (int);
1368 static void s_cpload (int);
1369 static void s_cpsetup (int);
1370 static void s_cplocal (int);
1371 static void s_cprestore (int);
1372 static void s_cpreturn (int);
1373 static void s_dtprelword (int);
1374 static void s_dtpreldword (int);
1375 static void s_tprelword (int);
1376 static void s_tpreldword (int);
1377 static void s_gpvalue (int);
1378 static void s_gpword (int);
1379 static void s_gpdword (int);
1380 static void s_ehword (int);
1381 static void s_cpadd (int);
1382 static void s_insn (int);
1383 static void s_nan (int);
1384 static void s_module (int);
1385 static void s_mips_ent (int);
1386 static void s_mips_end (int);
1387 static void s_mips_frame (int);
1388 static void s_mips_mask (int reg_type
);
1389 static void s_mips_stab (int);
1390 static void s_mips_weakext (int);
1391 static void s_mips_file (int);
1392 static void s_mips_loc (int);
1393 static bfd_boolean
pic_need_relax (symbolS
*);
1394 static int relaxed_branch_length (fragS
*, asection
*, int);
1395 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1396 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1397 static void file_mips_check_options (void);
1399 /* Table and functions used to map between CPU/ISA names, and
1400 ISA levels, and CPU numbers. */
1402 struct mips_cpu_info
1404 const char *name
; /* CPU or ISA name. */
1405 int flags
; /* MIPS_CPU_* flags. */
1406 int ase
; /* Set of ASEs implemented by the CPU. */
1407 int isa
; /* ISA level. */
1408 int cpu
; /* CPU number (default CPU if ISA). */
1411 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1413 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1414 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1415 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1417 /* Command-line options. */
1418 const char *md_shortopts
= "O::g::G:";
1422 OPTION_MARCH
= OPTION_MD_BASE
,
1454 OPTION_NO_SMARTMIPS
,
1464 OPTION_NO_MICROMIPS
,
1479 OPTION_M7000_HILO_FIX
,
1480 OPTION_MNO_7000_HILO_FIX
,
1484 OPTION_NO_FIX_RM7000
,
1485 OPTION_FIX_LOONGSON2F_JUMP
,
1486 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1487 OPTION_FIX_LOONGSON2F_NOP
,
1488 OPTION_NO_FIX_LOONGSON2F_NOP
,
1490 OPTION_NO_FIX_VR4120
,
1492 OPTION_NO_FIX_VR4130
,
1493 OPTION_FIX_CN63XXP1
,
1494 OPTION_NO_FIX_CN63XXP1
,
1496 OPTION_NO_FIX_R5900
,
1503 OPTION_CONSTRUCT_FLOATS
,
1504 OPTION_NO_CONSTRUCT_FLOATS
,
1508 OPTION_RELAX_BRANCH
,
1509 OPTION_NO_RELAX_BRANCH
,
1510 OPTION_IGNORE_BRANCH_ISA
,
1511 OPTION_NO_IGNORE_BRANCH_ISA
,
1520 OPTION_SINGLE_FLOAT
,
1521 OPTION_DOUBLE_FLOAT
,
1534 OPTION_MVXWORKS_PIC
,
1537 OPTION_NO_ODD_SPREG
,
1540 OPTION_LOONGSON_MMI
,
1541 OPTION_NO_LOONGSON_MMI
,
1542 OPTION_LOONGSON_CAM
,
1543 OPTION_NO_LOONGSON_CAM
,
1544 OPTION_LOONGSON_EXT
,
1545 OPTION_NO_LOONGSON_EXT
,
1546 OPTION_LOONGSON_EXT2
,
1547 OPTION_NO_LOONGSON_EXT2
,
1551 struct option md_longopts
[] =
1553 /* Options which specify architecture. */
1554 {"march", required_argument
, NULL
, OPTION_MARCH
},
1555 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1556 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1557 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1558 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1559 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1560 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1561 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1562 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1563 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1564 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1565 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1566 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1567 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1568 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1569 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1570 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1571 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1573 /* Options which specify Application Specific Extensions (ASEs). */
1574 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1575 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1576 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1577 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1578 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1579 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1580 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1581 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1582 {"mmt", no_argument
, NULL
, OPTION_MT
},
1583 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1584 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1585 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1586 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1587 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1588 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1589 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1590 {"meva", no_argument
, NULL
, OPTION_EVA
},
1591 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1592 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1593 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1594 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1595 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1596 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1597 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1598 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1599 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1600 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1601 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1602 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1603 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1604 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1605 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1606 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1607 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1608 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1609 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1610 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1611 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1612 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1613 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1614 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1615 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1617 /* Old-style architecture options. Don't add more of these. */
1618 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1619 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1620 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1621 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1622 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1623 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1624 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1625 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1627 /* Options which enable bug fixes. */
1628 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1629 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1630 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1631 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1632 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1633 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1634 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1635 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1636 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1637 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1638 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1639 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1640 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1641 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1642 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1643 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1644 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1645 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1646 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1648 /* Miscellaneous options. */
1649 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1650 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1651 {"break", no_argument
, NULL
, OPTION_BREAK
},
1652 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1653 {"EB", no_argument
, NULL
, OPTION_EB
},
1654 {"EL", no_argument
, NULL
, OPTION_EL
},
1655 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1656 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1657 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1658 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1659 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1660 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1661 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1662 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1663 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1664 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1665 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1666 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1667 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1668 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1669 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1670 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1671 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1672 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1673 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1674 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1675 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1676 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1677 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1679 /* Strictly speaking this next option is ELF specific,
1680 but we allow it for other ports as well in order to
1681 make testing easier. */
1682 {"32", no_argument
, NULL
, OPTION_32
},
1684 /* ELF-specific options. */
1685 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1686 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1687 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1688 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1689 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1690 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1691 {"n32", no_argument
, NULL
, OPTION_N32
},
1692 {"64", no_argument
, NULL
, OPTION_64
},
1693 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1694 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1695 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1696 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1697 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1698 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1700 {NULL
, no_argument
, NULL
, 0}
1702 size_t md_longopts_size
= sizeof (md_longopts
);
1704 /* Information about either an Application Specific Extension or an
1705 optional architecture feature that, for simplicity, we treat in the
1706 same way as an ASE. */
1709 /* The name of the ASE, used in both the command-line and .set options. */
1712 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1713 and 64-bit architectures, the flags here refer to the subset that
1714 is available on both. */
1717 /* The ASE_* flag used for instructions that are available on 64-bit
1718 architectures but that are not included in FLAGS. */
1719 unsigned int flags64
;
1721 /* The command-line options that turn the ASE on and off. */
1725 /* The minimum required architecture revisions for MIPS32, MIPS64,
1726 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1729 int micromips32_rev
;
1730 int micromips64_rev
;
1732 /* The architecture where the ASE was removed or -1 if the extension has not
1737 /* A table of all supported ASEs. */
1738 static const struct mips_ase mips_ases
[] = {
1739 { "dsp", ASE_DSP
, ASE_DSP64
,
1740 OPTION_DSP
, OPTION_NO_DSP
,
1744 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1745 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1749 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1750 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1754 { "eva", ASE_EVA
, 0,
1755 OPTION_EVA
, OPTION_NO_EVA
,
1759 { "mcu", ASE_MCU
, 0,
1760 OPTION_MCU
, OPTION_NO_MCU
,
1764 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1765 { "mdmx", ASE_MDMX
, 0,
1766 OPTION_MDMX
, OPTION_NO_MDMX
,
1770 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1771 { "mips3d", ASE_MIPS3D
, 0,
1772 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1777 OPTION_MT
, OPTION_NO_MT
,
1781 { "smartmips", ASE_SMARTMIPS
, 0,
1782 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1786 { "virt", ASE_VIRT
, ASE_VIRT64
,
1787 OPTION_VIRT
, OPTION_NO_VIRT
,
1791 { "msa", ASE_MSA
, ASE_MSA64
,
1792 OPTION_MSA
, OPTION_NO_MSA
,
1796 { "xpa", ASE_XPA
, 0,
1797 OPTION_XPA
, OPTION_NO_XPA
,
1801 { "mips16e2", ASE_MIPS16E2
, 0,
1802 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1806 { "crc", ASE_CRC
, ASE_CRC64
,
1807 OPTION_CRC
, OPTION_NO_CRC
,
1811 { "ginv", ASE_GINV
, 0,
1812 OPTION_GINV
, OPTION_NO_GINV
,
1816 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1817 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1821 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1822 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1826 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1827 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1831 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1832 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1837 /* The set of ASEs that require -mfp64. */
1838 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1840 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1841 static const unsigned int mips_ase_groups
[] = {
1842 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1843 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1848 The following pseudo-ops from the Kane and Heinrich MIPS book
1849 should be defined here, but are currently unsupported: .alias,
1850 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1852 The following pseudo-ops from the Kane and Heinrich MIPS book are
1853 specific to the type of debugging information being generated, and
1854 should be defined by the object format: .aent, .begin, .bend,
1855 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1858 The following pseudo-ops from the Kane and Heinrich MIPS book are
1859 not MIPS CPU specific, but are also not specific to the object file
1860 format. This file is probably the best place to define them, but
1861 they are not currently supported: .asm0, .endr, .lab, .struct. */
1863 static const pseudo_typeS mips_pseudo_table
[] =
1865 /* MIPS specific pseudo-ops. */
1866 {"option", s_option
, 0},
1867 {"set", s_mipsset
, 0},
1868 {"rdata", s_change_sec
, 'r'},
1869 {"sdata", s_change_sec
, 's'},
1870 {"livereg", s_ignore
, 0},
1871 {"abicalls", s_abicalls
, 0},
1872 {"cpload", s_cpload
, 0},
1873 {"cpsetup", s_cpsetup
, 0},
1874 {"cplocal", s_cplocal
, 0},
1875 {"cprestore", s_cprestore
, 0},
1876 {"cpreturn", s_cpreturn
, 0},
1877 {"dtprelword", s_dtprelword
, 0},
1878 {"dtpreldword", s_dtpreldword
, 0},
1879 {"tprelword", s_tprelword
, 0},
1880 {"tpreldword", s_tpreldword
, 0},
1881 {"gpvalue", s_gpvalue
, 0},
1882 {"gpword", s_gpword
, 0},
1883 {"gpdword", s_gpdword
, 0},
1884 {"ehword", s_ehword
, 0},
1885 {"cpadd", s_cpadd
, 0},
1886 {"insn", s_insn
, 0},
1888 {"module", s_module
, 0},
1890 /* Relatively generic pseudo-ops that happen to be used on MIPS
1892 {"asciiz", stringer
, 8 + 1},
1893 {"bss", s_change_sec
, 'b'},
1895 {"half", s_cons
, 1},
1896 {"dword", s_cons
, 3},
1897 {"weakext", s_mips_weakext
, 0},
1898 {"origin", s_org
, 0},
1899 {"repeat", s_rept
, 0},
1901 /* For MIPS this is non-standard, but we define it for consistency. */
1902 {"sbss", s_change_sec
, 'B'},
1904 /* These pseudo-ops are defined in read.c, but must be overridden
1905 here for one reason or another. */
1906 {"align", s_align
, 0},
1907 {"byte", s_cons
, 0},
1908 {"data", s_change_sec
, 'd'},
1909 {"double", s_float_cons
, 'd'},
1910 {"float", s_float_cons
, 'f'},
1911 {"globl", s_mips_globl
, 0},
1912 {"global", s_mips_globl
, 0},
1913 {"hword", s_cons
, 1},
1915 {"long", s_cons
, 2},
1916 {"octa", s_cons
, 4},
1917 {"quad", s_cons
, 3},
1918 {"section", s_change_section
, 0},
1919 {"short", s_cons
, 1},
1920 {"single", s_float_cons
, 'f'},
1921 {"stabd", s_mips_stab
, 'd'},
1922 {"stabn", s_mips_stab
, 'n'},
1923 {"stabs", s_mips_stab
, 's'},
1924 {"text", s_change_sec
, 't'},
1925 {"word", s_cons
, 2},
1927 { "extern", ecoff_directive_extern
, 0},
1932 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1934 /* These pseudo-ops should be defined by the object file format.
1935 However, a.out doesn't support them, so we have versions here. */
1936 {"aent", s_mips_ent
, 1},
1937 {"bgnb", s_ignore
, 0},
1938 {"end", s_mips_end
, 0},
1939 {"endb", s_ignore
, 0},
1940 {"ent", s_mips_ent
, 0},
1941 {"file", s_mips_file
, 0},
1942 {"fmask", s_mips_mask
, 'F'},
1943 {"frame", s_mips_frame
, 0},
1944 {"loc", s_mips_loc
, 0},
1945 {"mask", s_mips_mask
, 'R'},
1946 {"verstamp", s_ignore
, 0},
1950 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1951 purpose of the `.dc.a' internal pseudo-op. */
1954 mips_address_bytes (void)
1956 file_mips_check_options ();
1957 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1960 extern void pop_insert (const pseudo_typeS
*);
1963 mips_pop_insert (void)
1965 pop_insert (mips_pseudo_table
);
1966 if (! ECOFF_DEBUGGING
)
1967 pop_insert (mips_nonecoff_pseudo_table
);
1970 /* Symbols labelling the current insn. */
1972 struct insn_label_list
1974 struct insn_label_list
*next
;
1978 static struct insn_label_list
*free_insn_labels
;
1979 #define label_list tc_segment_info_data.labels
1981 static void mips_clear_insn_labels (void);
1982 static void mips_mark_labels (void);
1983 static void mips_compressed_mark_labels (void);
1986 mips_clear_insn_labels (void)
1988 struct insn_label_list
**pl
;
1989 segment_info_type
*si
;
1993 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1996 si
= seg_info (now_seg
);
1997 *pl
= si
->label_list
;
1998 si
->label_list
= NULL
;
2002 /* Mark instruction labels in MIPS16/microMIPS mode. */
2005 mips_mark_labels (void)
2007 if (HAVE_CODE_COMPRESSION
)
2008 mips_compressed_mark_labels ();
2011 static char *expr_end
;
2013 /* An expression in a macro instruction. This is set by mips_ip and
2014 mips16_ip and when populated is always an O_constant. */
2016 static expressionS imm_expr
;
2018 /* The relocatable field in an instruction and the relocs associated
2019 with it. These variables are used for instructions like LUI and
2020 JAL as well as true offsets. They are also used for address
2021 operands in macros. */
2023 static expressionS offset_expr
;
2024 static bfd_reloc_code_real_type offset_reloc
[3]
2025 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2027 /* This is set to the resulting size of the instruction to be produced
2028 by mips16_ip if an explicit extension is used or by mips_ip if an
2029 explicit size is supplied. */
2031 static unsigned int forced_insn_length
;
2033 /* True if we are assembling an instruction. All dot symbols defined during
2034 this time should be treated as code labels. */
2036 static bfd_boolean mips_assembling_insn
;
2038 /* The pdr segment for per procedure frame/regmask info. Not used for
2041 static segT pdr_seg
;
2043 /* The default target format to use. */
2045 #if defined (TE_FreeBSD)
2046 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2047 #elif defined (TE_TMIPS)
2048 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2050 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2054 mips_target_format (void)
2056 switch (OUTPUT_FLAVOR
)
2058 case bfd_target_elf_flavour
:
2060 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2061 return (target_big_endian
2062 ? "elf32-bigmips-vxworks"
2063 : "elf32-littlemips-vxworks");
2065 return (target_big_endian
2066 ? (HAVE_64BIT_OBJECTS
2067 ? ELF_TARGET ("elf64-", "big")
2069 ? ELF_TARGET ("elf32-n", "big")
2070 : ELF_TARGET ("elf32-", "big")))
2071 : (HAVE_64BIT_OBJECTS
2072 ? ELF_TARGET ("elf64-", "little")
2074 ? ELF_TARGET ("elf32-n", "little")
2075 : ELF_TARGET ("elf32-", "little"))));
2082 /* Return the ISA revision that is currently in use, or 0 if we are
2083 generating code for MIPS V or below. */
2088 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2091 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2094 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2097 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2100 /* microMIPS implies revision 2 or above. */
2101 if (mips_opts
.micromips
)
2104 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2110 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2113 mips_ase_mask (unsigned int flags
)
2117 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2118 if (flags
& mips_ase_groups
[i
])
2119 flags
|= mips_ase_groups
[i
];
2123 /* Check whether the current ISA supports ASE. Issue a warning if
2127 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2131 static unsigned int warned_isa
;
2132 static unsigned int warned_fp32
;
2134 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2135 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2137 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2138 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2139 && (warned_isa
& ase
->flags
) != ase
->flags
)
2141 warned_isa
|= ase
->flags
;
2142 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2143 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2145 as_warn (_("the %d-bit %s architecture does not support the"
2146 " `%s' extension"), size
, base
, ase
->name
);
2148 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2149 ase
->name
, base
, size
, min_rev
);
2151 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2152 && (warned_isa
& ase
->flags
) != ase
->flags
)
2154 warned_isa
|= ase
->flags
;
2155 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2156 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2157 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2158 ase
->name
, base
, size
, ase
->rem_rev
);
2161 if ((ase
->flags
& FP64_ASES
)
2162 && mips_opts
.fp
!= 64
2163 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2165 warned_fp32
|= ase
->flags
;
2166 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2170 /* Check all enabled ASEs to see whether they are supported by the
2171 chosen architecture. */
2174 mips_check_isa_supports_ases (void)
2176 unsigned int i
, mask
;
2178 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2180 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2181 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2182 mips_check_isa_supports_ase (&mips_ases
[i
]);
2186 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2187 that were affected. */
2190 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2191 bfd_boolean enabled_p
)
2195 mask
= mips_ase_mask (ase
->flags
);
2198 /* Clear combination ASE flags, which need to be recalculated based on
2199 updated regular ASE settings. */
2200 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
);
2203 opts
->ase
|= ase
->flags
;
2205 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2206 instructions which are only valid when both ASEs are enabled.
2207 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2208 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2210 opts
->ase
|= ASE_XPA_VIRT
;
2211 mask
|= ASE_XPA_VIRT
;
2213 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2215 opts
->ase
|= ASE_MIPS16E2_MT
;
2216 mask
|= ASE_MIPS16E2_MT
;
2222 /* Return the ASE called NAME, or null if none. */
2224 static const struct mips_ase
*
2225 mips_lookup_ase (const char *name
)
2229 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2230 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2231 return &mips_ases
[i
];
2235 /* Return the length of a microMIPS instruction in bytes. If bits of
2236 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2237 otherwise it is a 32-bit instruction. */
2239 static inline unsigned int
2240 micromips_insn_length (const struct mips_opcode
*mo
)
2242 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2245 /* Return the length of MIPS16 instruction OPCODE. */
2247 static inline unsigned int
2248 mips16_opcode_length (unsigned long opcode
)
2250 return (opcode
>> 16) == 0 ? 2 : 4;
2253 /* Return the length of instruction INSN. */
2255 static inline unsigned int
2256 insn_length (const struct mips_cl_insn
*insn
)
2258 if (mips_opts
.micromips
)
2259 return micromips_insn_length (insn
->insn_mo
);
2260 else if (mips_opts
.mips16
)
2261 return mips16_opcode_length (insn
->insn_opcode
);
2266 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2269 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2274 insn
->insn_opcode
= mo
->match
;
2277 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2278 insn
->fixp
[i
] = NULL
;
2279 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2280 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2281 insn
->mips16_absolute_jump_p
= 0;
2282 insn
->complete_p
= 0;
2283 insn
->cleared_p
= 0;
2286 /* Get a list of all the operands in INSN. */
2288 static const struct mips_operand_array
*
2289 insn_operands (const struct mips_cl_insn
*insn
)
2291 if (insn
->insn_mo
>= &mips_opcodes
[0]
2292 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2293 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2295 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2296 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2297 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2299 if (insn
->insn_mo
>= µmips_opcodes
[0]
2300 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2301 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2306 /* Get a description of operand OPNO of INSN. */
2308 static const struct mips_operand
*
2309 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2311 const struct mips_operand_array
*operands
;
2313 operands
= insn_operands (insn
);
2314 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2316 return operands
->operand
[opno
];
2319 /* Install UVAL as the value of OPERAND in INSN. */
2322 insn_insert_operand (struct mips_cl_insn
*insn
,
2323 const struct mips_operand
*operand
, unsigned int uval
)
2325 if (mips_opts
.mips16
2326 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2327 && mips_opcode_32bit_p (insn
->insn_mo
))
2328 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2330 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2333 /* Extract the value of OPERAND from INSN. */
2335 static inline unsigned
2336 insn_extract_operand (const struct mips_cl_insn
*insn
,
2337 const struct mips_operand
*operand
)
2339 return mips_extract_operand (operand
, insn
->insn_opcode
);
2342 /* Record the current MIPS16/microMIPS mode in now_seg. */
2345 mips_record_compressed_mode (void)
2347 segment_info_type
*si
;
2349 si
= seg_info (now_seg
);
2350 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2351 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2352 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2353 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2356 /* Read a standard MIPS instruction from BUF. */
2358 static unsigned long
2359 read_insn (char *buf
)
2361 if (target_big_endian
)
2362 return bfd_getb32 ((bfd_byte
*) buf
);
2364 return bfd_getl32 ((bfd_byte
*) buf
);
2367 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2371 write_insn (char *buf
, unsigned int insn
)
2373 md_number_to_chars (buf
, insn
, 4);
2377 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2378 has length LENGTH. */
2380 static unsigned long
2381 read_compressed_insn (char *buf
, unsigned int length
)
2387 for (i
= 0; i
< length
; i
+= 2)
2390 if (target_big_endian
)
2391 insn
|= bfd_getb16 ((char *) buf
);
2393 insn
|= bfd_getl16 ((char *) buf
);
2399 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2400 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2403 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2407 for (i
= 0; i
< length
; i
+= 2)
2408 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2409 return buf
+ length
;
2412 /* Install INSN at the location specified by its "frag" and "where" fields. */
2415 install_insn (const struct mips_cl_insn
*insn
)
2417 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2418 if (HAVE_CODE_COMPRESSION
)
2419 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2421 write_insn (f
, insn
->insn_opcode
);
2422 mips_record_compressed_mode ();
2425 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2426 and install the opcode in the new location. */
2429 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2434 insn
->where
= where
;
2435 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2436 if (insn
->fixp
[i
] != NULL
)
2438 insn
->fixp
[i
]->fx_frag
= frag
;
2439 insn
->fixp
[i
]->fx_where
= where
;
2441 install_insn (insn
);
2444 /* Add INSN to the end of the output. */
2447 add_fixed_insn (struct mips_cl_insn
*insn
)
2449 char *f
= frag_more (insn_length (insn
));
2450 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2453 /* Start a variant frag and move INSN to the start of the variant part,
2454 marking it as fixed. The other arguments are as for frag_var. */
2457 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2458 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2460 frag_grow (max_chars
);
2461 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2463 frag_var (rs_machine_dependent
, max_chars
, var
,
2464 subtype
, symbol
, offset
, NULL
);
2467 /* Insert N copies of INSN into the history buffer, starting at
2468 position FIRST. Neither FIRST nor N need to be clipped. */
2471 insert_into_history (unsigned int first
, unsigned int n
,
2472 const struct mips_cl_insn
*insn
)
2474 if (mips_relax
.sequence
!= 2)
2478 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2480 history
[i
] = history
[i
- n
];
2486 /* Clear the error in insn_error. */
2489 clear_insn_error (void)
2491 memset (&insn_error
, 0, sizeof (insn_error
));
2494 /* Possibly record error message MSG for the current instruction.
2495 If the error is about a particular argument, ARGNUM is the 1-based
2496 number of that argument, otherwise it is 0. FORMAT is the format
2497 of MSG. Return true if MSG was used, false if the current message
2501 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2506 /* Give priority to errors against specific arguments, and to
2507 the first whole-instruction message. */
2513 /* Keep insn_error if it is against a later argument. */
2514 if (argnum
< insn_error
.min_argnum
)
2517 /* If both errors are against the same argument but are different,
2518 give up on reporting a specific error for this argument.
2519 See the comment about mips_insn_error for details. */
2520 if (argnum
== insn_error
.min_argnum
2522 && strcmp (insn_error
.msg
, msg
) != 0)
2525 insn_error
.min_argnum
+= 1;
2529 insn_error
.min_argnum
= argnum
;
2530 insn_error
.format
= format
;
2531 insn_error
.msg
= msg
;
2535 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2536 as for set_insn_error_format. */
2539 set_insn_error (int argnum
, const char *msg
)
2541 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2544 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2545 as for set_insn_error_format. */
2548 set_insn_error_i (int argnum
, const char *msg
, int i
)
2550 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2554 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2555 are as for set_insn_error_format. */
2558 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2560 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2562 insn_error
.u
.ss
[0] = s1
;
2563 insn_error
.u
.ss
[1] = s2
;
2567 /* Report the error in insn_error, which is against assembly code STR. */
2570 report_insn_error (const char *str
)
2572 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2574 switch (insn_error
.format
)
2581 as_bad (msg
, insn_error
.u
.i
, str
);
2585 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2589 free ((char *) msg
);
2592 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2593 the idea is to make it obvious at a glance that each errata is
2597 init_vr4120_conflicts (void)
2599 #define CONFLICT(FIRST, SECOND) \
2600 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2602 /* Errata 21 - [D]DIV[U] after [D]MACC */
2603 CONFLICT (MACC
, DIV
);
2604 CONFLICT (DMACC
, DIV
);
2606 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2607 CONFLICT (DMULT
, DMULT
);
2608 CONFLICT (DMULT
, DMACC
);
2609 CONFLICT (DMACC
, DMULT
);
2610 CONFLICT (DMACC
, DMACC
);
2612 /* Errata 24 - MT{LO,HI} after [D]MACC */
2613 CONFLICT (MACC
, MTHILO
);
2614 CONFLICT (DMACC
, MTHILO
);
2616 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2617 instruction is executed immediately after a MACC or DMACC
2618 instruction, the result of [either instruction] is incorrect." */
2619 CONFLICT (MACC
, MULT
);
2620 CONFLICT (MACC
, DMULT
);
2621 CONFLICT (DMACC
, MULT
);
2622 CONFLICT (DMACC
, DMULT
);
2624 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2625 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2626 DDIV or DDIVU instruction, the result of the MACC or
2627 DMACC instruction is incorrect.". */
2628 CONFLICT (DMULT
, MACC
);
2629 CONFLICT (DMULT
, DMACC
);
2630 CONFLICT (DIV
, MACC
);
2631 CONFLICT (DIV
, DMACC
);
2641 #define RNUM_MASK 0x00000ff
2642 #define RTYPE_MASK 0x0ffff00
2643 #define RTYPE_NUM 0x0000100
2644 #define RTYPE_FPU 0x0000200
2645 #define RTYPE_FCC 0x0000400
2646 #define RTYPE_VEC 0x0000800
2647 #define RTYPE_GP 0x0001000
2648 #define RTYPE_CP0 0x0002000
2649 #define RTYPE_PC 0x0004000
2650 #define RTYPE_ACC 0x0008000
2651 #define RTYPE_CCC 0x0010000
2652 #define RTYPE_VI 0x0020000
2653 #define RTYPE_VF 0x0040000
2654 #define RTYPE_R5900_I 0x0080000
2655 #define RTYPE_R5900_Q 0x0100000
2656 #define RTYPE_R5900_R 0x0200000
2657 #define RTYPE_R5900_ACC 0x0400000
2658 #define RTYPE_MSA 0x0800000
2659 #define RWARN 0x8000000
2661 #define GENERIC_REGISTER_NUMBERS \
2662 {"$0", RTYPE_NUM | 0}, \
2663 {"$1", RTYPE_NUM | 1}, \
2664 {"$2", RTYPE_NUM | 2}, \
2665 {"$3", RTYPE_NUM | 3}, \
2666 {"$4", RTYPE_NUM | 4}, \
2667 {"$5", RTYPE_NUM | 5}, \
2668 {"$6", RTYPE_NUM | 6}, \
2669 {"$7", RTYPE_NUM | 7}, \
2670 {"$8", RTYPE_NUM | 8}, \
2671 {"$9", RTYPE_NUM | 9}, \
2672 {"$10", RTYPE_NUM | 10}, \
2673 {"$11", RTYPE_NUM | 11}, \
2674 {"$12", RTYPE_NUM | 12}, \
2675 {"$13", RTYPE_NUM | 13}, \
2676 {"$14", RTYPE_NUM | 14}, \
2677 {"$15", RTYPE_NUM | 15}, \
2678 {"$16", RTYPE_NUM | 16}, \
2679 {"$17", RTYPE_NUM | 17}, \
2680 {"$18", RTYPE_NUM | 18}, \
2681 {"$19", RTYPE_NUM | 19}, \
2682 {"$20", RTYPE_NUM | 20}, \
2683 {"$21", RTYPE_NUM | 21}, \
2684 {"$22", RTYPE_NUM | 22}, \
2685 {"$23", RTYPE_NUM | 23}, \
2686 {"$24", RTYPE_NUM | 24}, \
2687 {"$25", RTYPE_NUM | 25}, \
2688 {"$26", RTYPE_NUM | 26}, \
2689 {"$27", RTYPE_NUM | 27}, \
2690 {"$28", RTYPE_NUM | 28}, \
2691 {"$29", RTYPE_NUM | 29}, \
2692 {"$30", RTYPE_NUM | 30}, \
2693 {"$31", RTYPE_NUM | 31}
2695 #define FPU_REGISTER_NAMES \
2696 {"$f0", RTYPE_FPU | 0}, \
2697 {"$f1", RTYPE_FPU | 1}, \
2698 {"$f2", RTYPE_FPU | 2}, \
2699 {"$f3", RTYPE_FPU | 3}, \
2700 {"$f4", RTYPE_FPU | 4}, \
2701 {"$f5", RTYPE_FPU | 5}, \
2702 {"$f6", RTYPE_FPU | 6}, \
2703 {"$f7", RTYPE_FPU | 7}, \
2704 {"$f8", RTYPE_FPU | 8}, \
2705 {"$f9", RTYPE_FPU | 9}, \
2706 {"$f10", RTYPE_FPU | 10}, \
2707 {"$f11", RTYPE_FPU | 11}, \
2708 {"$f12", RTYPE_FPU | 12}, \
2709 {"$f13", RTYPE_FPU | 13}, \
2710 {"$f14", RTYPE_FPU | 14}, \
2711 {"$f15", RTYPE_FPU | 15}, \
2712 {"$f16", RTYPE_FPU | 16}, \
2713 {"$f17", RTYPE_FPU | 17}, \
2714 {"$f18", RTYPE_FPU | 18}, \
2715 {"$f19", RTYPE_FPU | 19}, \
2716 {"$f20", RTYPE_FPU | 20}, \
2717 {"$f21", RTYPE_FPU | 21}, \
2718 {"$f22", RTYPE_FPU | 22}, \
2719 {"$f23", RTYPE_FPU | 23}, \
2720 {"$f24", RTYPE_FPU | 24}, \
2721 {"$f25", RTYPE_FPU | 25}, \
2722 {"$f26", RTYPE_FPU | 26}, \
2723 {"$f27", RTYPE_FPU | 27}, \
2724 {"$f28", RTYPE_FPU | 28}, \
2725 {"$f29", RTYPE_FPU | 29}, \
2726 {"$f30", RTYPE_FPU | 30}, \
2727 {"$f31", RTYPE_FPU | 31}
2729 #define FPU_CONDITION_CODE_NAMES \
2730 {"$fcc0", RTYPE_FCC | 0}, \
2731 {"$fcc1", RTYPE_FCC | 1}, \
2732 {"$fcc2", RTYPE_FCC | 2}, \
2733 {"$fcc3", RTYPE_FCC | 3}, \
2734 {"$fcc4", RTYPE_FCC | 4}, \
2735 {"$fcc5", RTYPE_FCC | 5}, \
2736 {"$fcc6", RTYPE_FCC | 6}, \
2737 {"$fcc7", RTYPE_FCC | 7}
2739 #define COPROC_CONDITION_CODE_NAMES \
2740 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2741 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2742 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2743 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2744 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2745 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2746 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2747 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2749 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2750 {"$a4", RTYPE_GP | 8}, \
2751 {"$a5", RTYPE_GP | 9}, \
2752 {"$a6", RTYPE_GP | 10}, \
2753 {"$a7", RTYPE_GP | 11}, \
2754 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2755 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2756 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2757 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2758 {"$t0", RTYPE_GP | 12}, \
2759 {"$t1", RTYPE_GP | 13}, \
2760 {"$t2", RTYPE_GP | 14}, \
2761 {"$t3", RTYPE_GP | 15}
2763 #define O32_SYMBOLIC_REGISTER_NAMES \
2764 {"$t0", RTYPE_GP | 8}, \
2765 {"$t1", RTYPE_GP | 9}, \
2766 {"$t2", RTYPE_GP | 10}, \
2767 {"$t3", RTYPE_GP | 11}, \
2768 {"$t4", RTYPE_GP | 12}, \
2769 {"$t5", RTYPE_GP | 13}, \
2770 {"$t6", RTYPE_GP | 14}, \
2771 {"$t7", RTYPE_GP | 15}, \
2772 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2773 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2774 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2775 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2777 /* Remaining symbolic register names */
2778 #define SYMBOLIC_REGISTER_NAMES \
2779 {"$zero", RTYPE_GP | 0}, \
2780 {"$at", RTYPE_GP | 1}, \
2781 {"$AT", RTYPE_GP | 1}, \
2782 {"$v0", RTYPE_GP | 2}, \
2783 {"$v1", RTYPE_GP | 3}, \
2784 {"$a0", RTYPE_GP | 4}, \
2785 {"$a1", RTYPE_GP | 5}, \
2786 {"$a2", RTYPE_GP | 6}, \
2787 {"$a3", RTYPE_GP | 7}, \
2788 {"$s0", RTYPE_GP | 16}, \
2789 {"$s1", RTYPE_GP | 17}, \
2790 {"$s2", RTYPE_GP | 18}, \
2791 {"$s3", RTYPE_GP | 19}, \
2792 {"$s4", RTYPE_GP | 20}, \
2793 {"$s5", RTYPE_GP | 21}, \
2794 {"$s6", RTYPE_GP | 22}, \
2795 {"$s7", RTYPE_GP | 23}, \
2796 {"$t8", RTYPE_GP | 24}, \
2797 {"$t9", RTYPE_GP | 25}, \
2798 {"$k0", RTYPE_GP | 26}, \
2799 {"$kt0", RTYPE_GP | 26}, \
2800 {"$k1", RTYPE_GP | 27}, \
2801 {"$kt1", RTYPE_GP | 27}, \
2802 {"$gp", RTYPE_GP | 28}, \
2803 {"$sp", RTYPE_GP | 29}, \
2804 {"$s8", RTYPE_GP | 30}, \
2805 {"$fp", RTYPE_GP | 30}, \
2806 {"$ra", RTYPE_GP | 31}
2808 #define MIPS16_SPECIAL_REGISTER_NAMES \
2809 {"$pc", RTYPE_PC | 0}
2811 #define MDMX_VECTOR_REGISTER_NAMES \
2812 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2813 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2814 {"$v2", RTYPE_VEC | 2}, \
2815 {"$v3", RTYPE_VEC | 3}, \
2816 {"$v4", RTYPE_VEC | 4}, \
2817 {"$v5", RTYPE_VEC | 5}, \
2818 {"$v6", RTYPE_VEC | 6}, \
2819 {"$v7", RTYPE_VEC | 7}, \
2820 {"$v8", RTYPE_VEC | 8}, \
2821 {"$v9", RTYPE_VEC | 9}, \
2822 {"$v10", RTYPE_VEC | 10}, \
2823 {"$v11", RTYPE_VEC | 11}, \
2824 {"$v12", RTYPE_VEC | 12}, \
2825 {"$v13", RTYPE_VEC | 13}, \
2826 {"$v14", RTYPE_VEC | 14}, \
2827 {"$v15", RTYPE_VEC | 15}, \
2828 {"$v16", RTYPE_VEC | 16}, \
2829 {"$v17", RTYPE_VEC | 17}, \
2830 {"$v18", RTYPE_VEC | 18}, \
2831 {"$v19", RTYPE_VEC | 19}, \
2832 {"$v20", RTYPE_VEC | 20}, \
2833 {"$v21", RTYPE_VEC | 21}, \
2834 {"$v22", RTYPE_VEC | 22}, \
2835 {"$v23", RTYPE_VEC | 23}, \
2836 {"$v24", RTYPE_VEC | 24}, \
2837 {"$v25", RTYPE_VEC | 25}, \
2838 {"$v26", RTYPE_VEC | 26}, \
2839 {"$v27", RTYPE_VEC | 27}, \
2840 {"$v28", RTYPE_VEC | 28}, \
2841 {"$v29", RTYPE_VEC | 29}, \
2842 {"$v30", RTYPE_VEC | 30}, \
2843 {"$v31", RTYPE_VEC | 31}
2845 #define R5900_I_NAMES \
2846 {"$I", RTYPE_R5900_I | 0}
2848 #define R5900_Q_NAMES \
2849 {"$Q", RTYPE_R5900_Q | 0}
2851 #define R5900_R_NAMES \
2852 {"$R", RTYPE_R5900_R | 0}
2854 #define R5900_ACC_NAMES \
2855 {"$ACC", RTYPE_R5900_ACC | 0 }
2857 #define MIPS_DSP_ACCUMULATOR_NAMES \
2858 {"$ac0", RTYPE_ACC | 0}, \
2859 {"$ac1", RTYPE_ACC | 1}, \
2860 {"$ac2", RTYPE_ACC | 2}, \
2861 {"$ac3", RTYPE_ACC | 3}
2863 static const struct regname reg_names
[] = {
2864 GENERIC_REGISTER_NUMBERS
,
2866 FPU_CONDITION_CODE_NAMES
,
2867 COPROC_CONDITION_CODE_NAMES
,
2869 /* The $txx registers depends on the abi,
2870 these will be added later into the symbol table from
2871 one of the tables below once mips_abi is set after
2872 parsing of arguments from the command line. */
2873 SYMBOLIC_REGISTER_NAMES
,
2875 MIPS16_SPECIAL_REGISTER_NAMES
,
2876 MDMX_VECTOR_REGISTER_NAMES
,
2881 MIPS_DSP_ACCUMULATOR_NAMES
,
2885 static const struct regname reg_names_o32
[] = {
2886 O32_SYMBOLIC_REGISTER_NAMES
,
2890 static const struct regname reg_names_n32n64
[] = {
2891 N32N64_SYMBOLIC_REGISTER_NAMES
,
2895 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2896 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2897 of these register symbols, return the associated vector register,
2898 otherwise return SYMVAL itself. */
2901 mips_prefer_vec_regno (unsigned int symval
)
2903 if ((symval
& -2) == (RTYPE_GP
| 2))
2904 return RTYPE_VEC
| (symval
& 1);
2908 /* Return true if string [S, E) is a valid register name, storing its
2909 symbol value in *SYMVAL_PTR if so. */
2912 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2917 /* Terminate name. */
2921 /* Look up the name. */
2922 symbol
= symbol_find (s
);
2925 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2928 *symval_ptr
= S_GET_VALUE (symbol
);
2932 /* Return true if the string at *SPTR is a valid register name. Allow it
2933 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2936 When returning true, move *SPTR past the register, store the
2937 register's symbol value in *SYMVAL_PTR and the channel mask in
2938 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2939 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2940 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2943 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2944 unsigned int *channels_ptr
)
2948 unsigned int channels
, symval
, bit
;
2950 /* Find end of name. */
2952 if (is_name_beginner (*e
))
2954 while (is_part_of_name (*e
))
2958 if (!mips_parse_register_1 (s
, e
, &symval
))
2963 /* Eat characters from the end of the string that are valid
2964 channel suffixes. The preceding register must be $ACC or
2965 end with a digit, so there is no ambiguity. */
2968 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2969 if (m
> s
&& m
[-1] == *q
)
2976 || !mips_parse_register_1 (s
, m
, &symval
)
2977 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2982 *symval_ptr
= symval
;
2984 *channels_ptr
= channels
;
2988 /* Check if SPTR points at a valid register specifier according to TYPES.
2989 If so, then return 1, advance S to consume the specifier and store
2990 the register's number in REGNOP, otherwise return 0. */
2993 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2997 if (mips_parse_register (s
, ®no
, NULL
))
2999 if (types
& RTYPE_VEC
)
3000 regno
= mips_prefer_vec_regno (regno
);
3009 as_warn (_("unrecognized register name `%s'"), *s
);
3014 return regno
<= RNUM_MASK
;
3017 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3018 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3021 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3026 for (i
= 0; i
< 4; i
++)
3027 if (*s
== "xyzw"[i
])
3029 *channels
|= 1 << (3 - i
);
3035 /* Token types for parsed operand lists. */
3036 enum mips_operand_token_type
{
3037 /* A plain register, e.g. $f2. */
3040 /* A 4-bit XYZW channel mask. */
3043 /* A constant vector index, e.g. [1]. */
3046 /* A register vector index, e.g. [$2]. */
3049 /* A continuous range of registers, e.g. $s0-$s4. */
3052 /* A (possibly relocated) expression. */
3055 /* A floating-point value. */
3058 /* A single character. This can be '(', ')' or ',', but '(' only appears
3062 /* A doubled character, either "--" or "++". */
3065 /* The end of the operand list. */
3069 /* A parsed operand token. */
3070 struct mips_operand_token
3072 /* The type of token. */
3073 enum mips_operand_token_type type
;
3076 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3079 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3080 unsigned int channels
;
3082 /* The integer value of an OT_INTEGER_INDEX. */
3085 /* The two register symbol values involved in an OT_REG_RANGE. */
3087 unsigned int regno1
;
3088 unsigned int regno2
;
3091 /* The value of an OT_INTEGER. The value is represented as an
3092 expression and the relocation operators that were applied to
3093 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3094 relocation operators were used. */
3097 bfd_reloc_code_real_type relocs
[3];
3100 /* The binary data for an OT_FLOAT constant, and the number of bytes
3103 unsigned char data
[8];
3107 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3112 /* An obstack used to construct lists of mips_operand_tokens. */
3113 static struct obstack mips_operand_tokens
;
3115 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3118 mips_add_token (struct mips_operand_token
*token
,
3119 enum mips_operand_token_type type
)
3122 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3125 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3126 and OT_REG tokens for them if so, and return a pointer to the first
3127 unconsumed character. Return null otherwise. */
3130 mips_parse_base_start (char *s
)
3132 struct mips_operand_token token
;
3133 unsigned int regno
, channels
;
3134 bfd_boolean decrement_p
;
3140 SKIP_SPACE_TABS (s
);
3142 /* Only match "--" as part of a base expression. In other contexts "--X"
3143 is a double negative. */
3144 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3148 SKIP_SPACE_TABS (s
);
3151 /* Allow a channel specifier because that leads to better error messages
3152 than treating something like "$vf0x++" as an expression. */
3153 if (!mips_parse_register (&s
, ®no
, &channels
))
3157 mips_add_token (&token
, OT_CHAR
);
3162 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3165 token
.u
.regno
= regno
;
3166 mips_add_token (&token
, OT_REG
);
3170 token
.u
.channels
= channels
;
3171 mips_add_token (&token
, OT_CHANNELS
);
3174 /* For consistency, only match "++" as part of base expressions too. */
3175 SKIP_SPACE_TABS (s
);
3176 if (s
[0] == '+' && s
[1] == '+')
3180 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3186 /* Parse one or more tokens from S. Return a pointer to the first
3187 unconsumed character on success. Return null if an error was found
3188 and store the error text in insn_error. FLOAT_FORMAT is as for
3189 mips_parse_arguments. */
3192 mips_parse_argument_token (char *s
, char float_format
)
3194 char *end
, *save_in
;
3196 unsigned int regno1
, regno2
, channels
;
3197 struct mips_operand_token token
;
3199 /* First look for "($reg", since we want to treat that as an
3200 OT_CHAR and OT_REG rather than an expression. */
3201 end
= mips_parse_base_start (s
);
3205 /* Handle other characters that end up as OT_CHARs. */
3206 if (*s
== ')' || *s
== ',')
3209 mips_add_token (&token
, OT_CHAR
);
3214 /* Handle tokens that start with a register. */
3215 if (mips_parse_register (&s
, ®no1
, &channels
))
3219 /* A register and a VU0 channel suffix. */
3220 token
.u
.regno
= regno1
;
3221 mips_add_token (&token
, OT_REG
);
3223 token
.u
.channels
= channels
;
3224 mips_add_token (&token
, OT_CHANNELS
);
3228 SKIP_SPACE_TABS (s
);
3231 /* A register range. */
3233 SKIP_SPACE_TABS (s
);
3234 if (!mips_parse_register (&s
, ®no2
, NULL
))
3236 set_insn_error (0, _("invalid register range"));
3240 token
.u
.reg_range
.regno1
= regno1
;
3241 token
.u
.reg_range
.regno2
= regno2
;
3242 mips_add_token (&token
, OT_REG_RANGE
);
3246 /* Add the register itself. */
3247 token
.u
.regno
= regno1
;
3248 mips_add_token (&token
, OT_REG
);
3250 /* Check for a vector index. */
3254 SKIP_SPACE_TABS (s
);
3255 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3256 mips_add_token (&token
, OT_REG_INDEX
);
3259 expressionS element
;
3261 my_getExpression (&element
, s
);
3262 if (element
.X_op
!= O_constant
)
3264 set_insn_error (0, _("vector element must be constant"));
3268 token
.u
.index
= element
.X_add_number
;
3269 mips_add_token (&token
, OT_INTEGER_INDEX
);
3271 SKIP_SPACE_TABS (s
);
3274 set_insn_error (0, _("missing `]'"));
3284 /* First try to treat expressions as floats. */
3285 save_in
= input_line_pointer
;
3286 input_line_pointer
= s
;
3287 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3288 &token
.u
.flt
.length
);
3289 end
= input_line_pointer
;
3290 input_line_pointer
= save_in
;
3293 set_insn_error (0, err
);
3298 mips_add_token (&token
, OT_FLOAT
);
3303 /* Treat everything else as an integer expression. */
3304 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3305 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3306 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3307 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3309 mips_add_token (&token
, OT_INTEGER
);
3313 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3314 if expressions should be treated as 32-bit floating-point constants,
3315 'd' if they should be treated as 64-bit floating-point constants,
3316 or 0 if they should be treated as integer expressions (the usual case).
3318 Return a list of tokens on success, otherwise return 0. The caller
3319 must obstack_free the list after use. */
3321 static struct mips_operand_token
*
3322 mips_parse_arguments (char *s
, char float_format
)
3324 struct mips_operand_token token
;
3326 SKIP_SPACE_TABS (s
);
3329 s
= mips_parse_argument_token (s
, float_format
);
3332 obstack_free (&mips_operand_tokens
,
3333 obstack_finish (&mips_operand_tokens
));
3336 SKIP_SPACE_TABS (s
);
3338 mips_add_token (&token
, OT_END
);
3339 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3342 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3343 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3346 is_opcode_valid (const struct mips_opcode
*mo
)
3348 int isa
= mips_opts
.isa
;
3349 int ase
= mips_opts
.ase
;
3353 if (ISA_HAS_64BIT_REGS (isa
))
3354 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3355 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3356 ase
|= mips_ases
[i
].flags64
;
3358 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3361 /* Check whether the instruction or macro requires single-precision or
3362 double-precision floating-point support. Note that this information is
3363 stored differently in the opcode table for insns and macros. */
3364 if (mo
->pinfo
== INSN_MACRO
)
3366 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3367 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3371 fp_s
= mo
->pinfo
& FP_S
;
3372 fp_d
= mo
->pinfo
& FP_D
;
3375 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3378 if (fp_s
&& mips_opts
.soft_float
)
3384 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3385 selected ISA and architecture. */
3388 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3390 int isa
= mips_opts
.isa
;
3391 int ase
= mips_opts
.ase
;
3394 if (ISA_HAS_64BIT_REGS (isa
))
3395 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3396 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3397 ase
|= mips_ases
[i
].flags64
;
3399 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3402 /* Return TRUE if the size of the microMIPS opcode MO matches one
3403 explicitly requested. Always TRUE in the standard MIPS mode.
3404 Use is_size_valid_16 for MIPS16 opcodes. */
3407 is_size_valid (const struct mips_opcode
*mo
)
3409 if (!mips_opts
.micromips
)
3412 if (mips_opts
.insn32
)
3414 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3416 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3419 if (!forced_insn_length
)
3421 if (mo
->pinfo
== INSN_MACRO
)
3423 return forced_insn_length
== micromips_insn_length (mo
);
3426 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3427 explicitly requested. */
3430 is_size_valid_16 (const struct mips_opcode
*mo
)
3432 if (!forced_insn_length
)
3434 if (mo
->pinfo
== INSN_MACRO
)
3436 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3438 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3443 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3444 of the preceding instruction. Always TRUE in the standard MIPS mode.
3446 We don't accept macros in 16-bit delay slots to avoid a case where
3447 a macro expansion fails because it relies on a preceding 32-bit real
3448 instruction to have matched and does not handle the operands correctly.
3449 The only macros that may expand to 16-bit instructions are JAL that
3450 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3451 and BGT (that likewise cannot be placed in a delay slot) that decay to
3452 a NOP. In all these cases the macros precede any corresponding real
3453 instruction definitions in the opcode table, so they will match in the
3454 second pass where the size of the delay slot is ignored and therefore
3455 produce correct code. */
3458 is_delay_slot_valid (const struct mips_opcode
*mo
)
3460 if (!mips_opts
.micromips
)
3463 if (mo
->pinfo
== INSN_MACRO
)
3464 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3465 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3466 && micromips_insn_length (mo
) != 4)
3468 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3469 && micromips_insn_length (mo
) != 2)
3475 /* For consistency checking, verify that all bits of OPCODE are specified
3476 either by the match/mask part of the instruction definition, or by the
3477 operand list. Also build up a list of operands in OPERANDS.
3479 INSN_BITS says which bits of the instruction are significant.
3480 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3481 provides the mips_operand description of each operand. DECODE_OPERAND
3482 is null for MIPS16 instructions. */
3485 validate_mips_insn (const struct mips_opcode
*opcode
,
3486 unsigned long insn_bits
,
3487 const struct mips_operand
*(*decode_operand
) (const char *),
3488 struct mips_operand_array
*operands
)
3491 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3492 const struct mips_operand
*operand
;
3494 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3495 if ((mask
& opcode
->match
) != opcode
->match
)
3497 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3498 opcode
->name
, opcode
->args
);
3503 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3504 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3505 for (s
= opcode
->args
; *s
; ++s
)
3518 if (!decode_operand
)
3519 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3521 operand
= decode_operand (s
);
3522 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3524 as_bad (_("internal: unknown operand type: %s %s"),
3525 opcode
->name
, opcode
->args
);
3528 gas_assert (opno
< MAX_OPERANDS
);
3529 operands
->operand
[opno
] = operand
;
3530 if (!decode_operand
&& operand
3531 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3532 && mips_opcode_32bit_p (opcode
))
3533 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3534 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3536 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3537 if (operand
->type
== OP_MDMX_IMM_REG
)
3538 /* Bit 5 is the format selector (OB vs QH). The opcode table
3539 has separate entries for each format. */
3540 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3541 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3542 used_bits
&= ~(mask
& 0x700);
3543 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3544 operand field that cannot be fully described with LSB/SIZE. */
3545 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3546 used_bits
&= ~0x6000;
3548 /* Skip prefix characters. */
3549 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3554 doubled
= used_bits
& mask
& insn_bits
;
3557 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3558 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3562 undefined
= ~used_bits
& insn_bits
;
3563 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3565 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3566 undefined
, opcode
->name
, opcode
->args
);
3569 used_bits
&= ~insn_bits
;
3572 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3573 used_bits
, opcode
->name
, opcode
->args
);
3579 /* The MIPS16 version of validate_mips_insn. */
3582 validate_mips16_insn (const struct mips_opcode
*opcode
,
3583 struct mips_operand_array
*operands
)
3585 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3587 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3590 /* The microMIPS version of validate_mips_insn. */
3593 validate_micromips_insn (const struct mips_opcode
*opc
,
3594 struct mips_operand_array
*operands
)
3596 unsigned long insn_bits
;
3597 unsigned long major
;
3598 unsigned int length
;
3600 if (opc
->pinfo
== INSN_MACRO
)
3601 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3604 length
= micromips_insn_length (opc
);
3605 if (length
!= 2 && length
!= 4)
3607 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3608 "%s %s"), length
, opc
->name
, opc
->args
);
3611 major
= opc
->match
>> (10 + 8 * (length
- 2));
3612 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3613 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3615 as_bad (_("internal error: bad microMIPS opcode "
3616 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3620 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3621 insn_bits
= 1 << 4 * length
;
3622 insn_bits
<<= 4 * length
;
3624 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3628 /* This function is called once, at assembler startup time. It should set up
3629 all the tables, etc. that the MD part of the assembler will need. */
3634 const char *retval
= NULL
;
3638 if (mips_pic
!= NO_PIC
)
3640 if (g_switch_seen
&& g_switch_value
!= 0)
3641 as_bad (_("-G may not be used in position-independent code"));
3644 else if (mips_abicalls
)
3646 if (g_switch_seen
&& g_switch_value
!= 0)
3647 as_bad (_("-G may not be used with abicalls"));
3651 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3652 as_warn (_("could not set architecture and machine"));
3654 op_hash
= hash_new ();
3656 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3657 for (i
= 0; i
< NUMOPCODES
;)
3659 const char *name
= mips_opcodes
[i
].name
;
3661 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3664 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3665 mips_opcodes
[i
].name
, retval
);
3666 /* Probably a memory allocation problem? Give up now. */
3667 as_fatal (_("broken assembler, no assembly attempted"));
3671 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3672 decode_mips_operand
, &mips_operands
[i
]))
3674 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3676 create_insn (&nop_insn
, mips_opcodes
+ i
);
3677 if (mips_fix_loongson2f_nop
)
3678 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3679 nop_insn
.fixed_p
= 1;
3683 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3686 mips16_op_hash
= hash_new ();
3687 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3688 bfd_mips16_num_opcodes
);
3691 while (i
< bfd_mips16_num_opcodes
)
3693 const char *name
= mips16_opcodes
[i
].name
;
3695 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3697 as_fatal (_("internal: can't hash `%s': %s"),
3698 mips16_opcodes
[i
].name
, retval
);
3701 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3703 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3705 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3706 mips16_nop_insn
.fixed_p
= 1;
3710 while (i
< bfd_mips16_num_opcodes
3711 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3714 micromips_op_hash
= hash_new ();
3715 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3716 bfd_micromips_num_opcodes
);
3719 while (i
< bfd_micromips_num_opcodes
)
3721 const char *name
= micromips_opcodes
[i
].name
;
3723 retval
= hash_insert (micromips_op_hash
, name
,
3724 (void *) µmips_opcodes
[i
]);
3726 as_fatal (_("internal: can't hash `%s': %s"),
3727 micromips_opcodes
[i
].name
, retval
);
3730 struct mips_cl_insn
*micromips_nop_insn
;
3732 if (!validate_micromips_insn (µmips_opcodes
[i
],
3733 µmips_operands
[i
]))
3736 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3738 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3739 micromips_nop_insn
= µmips_nop16_insn
;
3740 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3741 micromips_nop_insn
= µmips_nop32_insn
;
3745 if (micromips_nop_insn
->insn_mo
== NULL
3746 && strcmp (name
, "nop") == 0)
3748 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3749 micromips_nop_insn
->fixed_p
= 1;
3753 while (++i
< bfd_micromips_num_opcodes
3754 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3758 as_fatal (_("broken assembler, no assembly attempted"));
3760 /* We add all the general register names to the symbol table. This
3761 helps us detect invalid uses of them. */
3762 for (i
= 0; reg_names
[i
].name
; i
++)
3763 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3764 reg_names
[i
].num
, /* & RNUM_MASK, */
3765 &zero_address_frag
));
3767 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3768 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3769 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3770 &zero_address_frag
));
3772 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3773 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3774 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3775 &zero_address_frag
));
3777 for (i
= 0; i
< 32; i
++)
3781 /* R5900 VU0 floating-point register. */
3782 sprintf (regname
, "$vf%d", i
);
3783 symbol_table_insert (symbol_new (regname
, reg_section
,
3784 RTYPE_VF
| i
, &zero_address_frag
));
3786 /* R5900 VU0 integer register. */
3787 sprintf (regname
, "$vi%d", i
);
3788 symbol_table_insert (symbol_new (regname
, reg_section
,
3789 RTYPE_VI
| i
, &zero_address_frag
));
3792 sprintf (regname
, "$w%d", i
);
3793 symbol_table_insert (symbol_new (regname
, reg_section
,
3794 RTYPE_MSA
| i
, &zero_address_frag
));
3797 obstack_init (&mips_operand_tokens
);
3799 mips_no_prev_insn ();
3802 mips_cprmask
[0] = 0;
3803 mips_cprmask
[1] = 0;
3804 mips_cprmask
[2] = 0;
3805 mips_cprmask
[3] = 0;
3807 /* set the default alignment for the text section (2**2) */
3808 record_alignment (text_section
, 2);
3810 bfd_set_gp_size (stdoutput
, g_switch_value
);
3812 /* On a native system other than VxWorks, sections must be aligned
3813 to 16 byte boundaries. When configured for an embedded ELF
3814 target, we don't bother. */
3815 if (strncmp (TARGET_OS
, "elf", 3) != 0
3816 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3818 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3819 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3820 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3823 /* Create a .reginfo section for register masks and a .mdebug
3824 section for debugging information. */
3832 subseg
= now_subseg
;
3834 /* The ABI says this section should be loaded so that the
3835 running program can access it. However, we don't load it
3836 if we are configured for an embedded target */
3837 flags
= SEC_READONLY
| SEC_DATA
;
3838 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3839 flags
|= SEC_ALLOC
| SEC_LOAD
;
3841 if (mips_abi
!= N64_ABI
)
3843 sec
= subseg_new (".reginfo", (subsegT
) 0);
3845 bfd_set_section_flags (stdoutput
, sec
, flags
);
3846 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3848 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3852 /* The 64-bit ABI uses a .MIPS.options section rather than
3853 .reginfo section. */
3854 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3855 bfd_set_section_flags (stdoutput
, sec
, flags
);
3856 bfd_set_section_alignment (stdoutput
, sec
, 3);
3858 /* Set up the option header. */
3860 Elf_Internal_Options opthdr
;
3863 opthdr
.kind
= ODK_REGINFO
;
3864 opthdr
.size
= (sizeof (Elf_External_Options
)
3865 + sizeof (Elf64_External_RegInfo
));
3868 f
= frag_more (sizeof (Elf_External_Options
));
3869 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3870 (Elf_External_Options
*) f
);
3872 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3876 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3877 bfd_set_section_flags (stdoutput
, sec
,
3878 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3879 bfd_set_section_alignment (stdoutput
, sec
, 3);
3880 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3882 if (ECOFF_DEBUGGING
)
3884 sec
= subseg_new (".mdebug", (subsegT
) 0);
3885 (void) bfd_set_section_flags (stdoutput
, sec
,
3886 SEC_HAS_CONTENTS
| SEC_READONLY
);
3887 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3889 else if (mips_flag_pdr
)
3891 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3892 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3893 SEC_READONLY
| SEC_RELOC
3895 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3898 subseg_set (seg
, subseg
);
3901 if (mips_fix_vr4120
)
3902 init_vr4120_conflicts ();
3906 fpabi_incompatible_with (int fpabi
, const char *what
)
3908 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3909 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3913 fpabi_requires (int fpabi
, const char *what
)
3915 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3916 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3919 /* Check -mabi and register sizes against the specified FP ABI. */
3921 check_fpabi (int fpabi
)
3925 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3926 if (file_mips_opts
.soft_float
)
3927 fpabi_incompatible_with (fpabi
, "softfloat");
3928 else if (file_mips_opts
.single_float
)
3929 fpabi_incompatible_with (fpabi
, "singlefloat");
3930 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3931 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3932 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3933 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3936 case Val_GNU_MIPS_ABI_FP_XX
:
3937 if (mips_abi
!= O32_ABI
)
3938 fpabi_requires (fpabi
, "-mabi=32");
3939 else if (file_mips_opts
.soft_float
)
3940 fpabi_incompatible_with (fpabi
, "softfloat");
3941 else if (file_mips_opts
.single_float
)
3942 fpabi_incompatible_with (fpabi
, "singlefloat");
3943 else if (file_mips_opts
.fp
!= 0)
3944 fpabi_requires (fpabi
, "fp=xx");
3947 case Val_GNU_MIPS_ABI_FP_64A
:
3948 case Val_GNU_MIPS_ABI_FP_64
:
3949 if (mips_abi
!= O32_ABI
)
3950 fpabi_requires (fpabi
, "-mabi=32");
3951 else if (file_mips_opts
.soft_float
)
3952 fpabi_incompatible_with (fpabi
, "softfloat");
3953 else if (file_mips_opts
.single_float
)
3954 fpabi_incompatible_with (fpabi
, "singlefloat");
3955 else if (file_mips_opts
.fp
!= 64)
3956 fpabi_requires (fpabi
, "fp=64");
3957 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3958 fpabi_incompatible_with (fpabi
, "nooddspreg");
3959 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3960 fpabi_requires (fpabi
, "nooddspreg");
3963 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3964 if (file_mips_opts
.soft_float
)
3965 fpabi_incompatible_with (fpabi
, "softfloat");
3966 else if (!file_mips_opts
.single_float
)
3967 fpabi_requires (fpabi
, "singlefloat");
3970 case Val_GNU_MIPS_ABI_FP_SOFT
:
3971 if (!file_mips_opts
.soft_float
)
3972 fpabi_requires (fpabi
, "softfloat");
3975 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3976 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3977 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3980 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3981 /* Silently ignore compatibility value. */
3985 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3986 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3991 /* Perform consistency checks on the current options. */
3994 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3996 /* Check the size of integer registers agrees with the ABI and ISA. */
3997 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3998 as_bad (_("`gp=64' used with a 32-bit processor"));
4000 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4001 as_bad (_("`gp=32' used with a 64-bit ABI"));
4003 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4004 as_bad (_("`gp=64' used with a 32-bit ABI"));
4006 /* Check the size of the float registers agrees with the ABI and ISA. */
4010 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4011 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4012 else if (opts
->single_float
== 1)
4013 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4016 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4017 as_bad (_("`fp=64' used with a 32-bit fpu"));
4019 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4020 && !ISA_HAS_MXHC1 (opts
->isa
))
4021 as_warn (_("`fp=64' used with a 32-bit ABI"));
4025 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4026 as_warn (_("`fp=32' used with a 64-bit ABI"));
4027 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4028 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4031 as_bad (_("Unknown size of floating point registers"));
4035 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4036 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4038 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4039 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4040 else if (ISA_IS_R6 (opts
->isa
)
4041 && (opts
->micromips
== 1
4042 || opts
->mips16
== 1))
4043 as_fatal (_("`%s' cannot be used with `%s'"),
4044 opts
->micromips
? "micromips" : "mips16",
4045 mips_cpu_info_from_isa (opts
->isa
)->name
);
4047 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4048 as_fatal (_("branch relaxation is not supported in `%s'"),
4049 mips_cpu_info_from_isa (opts
->isa
)->name
);
4052 /* Perform consistency checks on the module level options exactly once.
4053 This is a deferred check that happens:
4054 at the first .set directive
4055 or, at the first pseudo op that generates code (inc .dc.a)
4056 or, at the first instruction
4060 file_mips_check_options (void)
4062 const struct mips_cpu_info
*arch_info
= 0;
4064 if (file_mips_opts_checked
)
4067 /* The following code determines the register size.
4068 Similar code was added to GCC 3.3 (see override_options() in
4069 config/mips/mips.c). The GAS and GCC code should be kept in sync
4070 as much as possible. */
4072 if (file_mips_opts
.gp
< 0)
4074 /* Infer the integer register size from the ABI and processor.
4075 Restrict ourselves to 32-bit registers if that's all the
4076 processor has, or if the ABI cannot handle 64-bit registers. */
4077 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4078 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4082 if (file_mips_opts
.fp
< 0)
4084 /* No user specified float register size.
4085 ??? GAS treats single-float processors as though they had 64-bit
4086 float registers (although it complains when double-precision
4087 instructions are used). As things stand, saying they have 32-bit
4088 registers would lead to spurious "register must be even" messages.
4089 So here we assume float registers are never smaller than the
4091 if (file_mips_opts
.gp
== 64)
4092 /* 64-bit integer registers implies 64-bit float registers. */
4093 file_mips_opts
.fp
= 64;
4094 else if ((file_mips_opts
.ase
& FP64_ASES
)
4095 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4096 /* Handle ASEs that require 64-bit float registers, if possible. */
4097 file_mips_opts
.fp
= 64;
4098 else if (ISA_IS_R6 (mips_opts
.isa
))
4099 /* R6 implies 64-bit float registers. */
4100 file_mips_opts
.fp
= 64;
4102 /* 32-bit float registers. */
4103 file_mips_opts
.fp
= 32;
4106 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
4108 /* Disable operations on odd-numbered floating-point registers by default
4109 when using the FPXX ABI. */
4110 if (file_mips_opts
.oddspreg
< 0)
4112 if (file_mips_opts
.fp
== 0)
4113 file_mips_opts
.oddspreg
= 0;
4115 file_mips_opts
.oddspreg
= 1;
4118 /* End of GCC-shared inference code. */
4120 /* This flag is set when we have a 64-bit capable CPU but use only
4121 32-bit wide registers. Note that EABI does not use it. */
4122 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4123 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4124 || mips_abi
== O32_ABI
))
4127 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4128 as_bad (_("trap exception not supported at ISA 1"));
4130 /* If the selected architecture includes support for ASEs, enable
4131 generation of code for them. */
4132 if (file_mips_opts
.mips16
== -1)
4133 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4134 if (file_mips_opts
.micromips
== -1)
4135 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4138 if (mips_nan2008
== -1)
4139 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4140 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4141 as_fatal (_("`%s' does not support legacy NaN"),
4142 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4144 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4145 being selected implicitly. */
4146 if (file_mips_opts
.fp
!= 64)
4147 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4149 /* If the user didn't explicitly select or deselect a particular ASE,
4150 use the default setting for the CPU. */
4151 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4153 /* Set up the current options. These may change throughout assembly. */
4154 mips_opts
= file_mips_opts
;
4156 mips_check_isa_supports_ases ();
4157 mips_check_options (&file_mips_opts
, TRUE
);
4158 file_mips_opts_checked
= TRUE
;
4160 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4161 as_warn (_("could not set architecture and machine"));
4165 md_assemble (char *str
)
4167 struct mips_cl_insn insn
;
4168 bfd_reloc_code_real_type unused_reloc
[3]
4169 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4171 file_mips_check_options ();
4173 imm_expr
.X_op
= O_absent
;
4174 offset_expr
.X_op
= O_absent
;
4175 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4176 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4177 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4179 mips_mark_labels ();
4180 mips_assembling_insn
= TRUE
;
4181 clear_insn_error ();
4183 if (mips_opts
.mips16
)
4184 mips16_ip (str
, &insn
);
4187 mips_ip (str
, &insn
);
4188 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4189 str
, insn
.insn_opcode
));
4193 report_insn_error (str
);
4194 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4197 if (mips_opts
.mips16
)
4198 mips16_macro (&insn
);
4205 if (offset_expr
.X_op
!= O_absent
)
4206 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4208 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4211 mips_assembling_insn
= FALSE
;
4214 /* Convenience functions for abstracting away the differences between
4215 MIPS16 and non-MIPS16 relocations. */
4217 static inline bfd_boolean
4218 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4222 case BFD_RELOC_MIPS16_JMP
:
4223 case BFD_RELOC_MIPS16_GPREL
:
4224 case BFD_RELOC_MIPS16_GOT16
:
4225 case BFD_RELOC_MIPS16_CALL16
:
4226 case BFD_RELOC_MIPS16_HI16_S
:
4227 case BFD_RELOC_MIPS16_HI16
:
4228 case BFD_RELOC_MIPS16_LO16
:
4229 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4237 static inline bfd_boolean
4238 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4242 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4243 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4244 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4245 case BFD_RELOC_MICROMIPS_GPREL16
:
4246 case BFD_RELOC_MICROMIPS_JMP
:
4247 case BFD_RELOC_MICROMIPS_HI16
:
4248 case BFD_RELOC_MICROMIPS_HI16_S
:
4249 case BFD_RELOC_MICROMIPS_LO16
:
4250 case BFD_RELOC_MICROMIPS_LITERAL
:
4251 case BFD_RELOC_MICROMIPS_GOT16
:
4252 case BFD_RELOC_MICROMIPS_CALL16
:
4253 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4254 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4255 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4256 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4257 case BFD_RELOC_MICROMIPS_SUB
:
4258 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4259 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4260 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4261 case BFD_RELOC_MICROMIPS_HIGHEST
:
4262 case BFD_RELOC_MICROMIPS_HIGHER
:
4263 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4264 case BFD_RELOC_MICROMIPS_JALR
:
4272 static inline bfd_boolean
4273 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4275 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4278 static inline bfd_boolean
4279 b_reloc_p (bfd_reloc_code_real_type reloc
)
4281 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4282 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4283 || reloc
== BFD_RELOC_16_PCREL_S2
4284 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4285 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4286 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4287 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4290 static inline bfd_boolean
4291 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4293 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4294 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4297 static inline bfd_boolean
4298 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4300 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4301 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4304 static inline bfd_boolean
4305 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4307 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4308 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4311 static inline bfd_boolean
4312 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4314 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4317 static inline bfd_boolean
4318 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4320 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4321 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4324 /* Return true if RELOC is a PC-relative relocation that does not have
4325 full address range. */
4327 static inline bfd_boolean
4328 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4332 case BFD_RELOC_16_PCREL_S2
:
4333 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4334 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4335 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4336 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4337 case BFD_RELOC_MIPS_21_PCREL_S2
:
4338 case BFD_RELOC_MIPS_26_PCREL_S2
:
4339 case BFD_RELOC_MIPS_18_PCREL_S3
:
4340 case BFD_RELOC_MIPS_19_PCREL_S2
:
4343 case BFD_RELOC_32_PCREL
:
4344 case BFD_RELOC_HI16_S_PCREL
:
4345 case BFD_RELOC_LO16_PCREL
:
4346 return HAVE_64BIT_ADDRESSES
;
4353 /* Return true if the given relocation might need a matching %lo().
4354 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4355 need a matching %lo() when applied to local symbols. */
4357 static inline bfd_boolean
4358 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4360 return (HAVE_IN_PLACE_ADDENDS
4361 && (hi16_reloc_p (reloc
)
4362 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4363 all GOT16 relocations evaluate to "G". */
4364 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4367 /* Return the type of %lo() reloc needed by RELOC, given that
4368 reloc_needs_lo_p. */
4370 static inline bfd_reloc_code_real_type
4371 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4373 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4374 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4378 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4381 static inline bfd_boolean
4382 fixup_has_matching_lo_p (fixS
*fixp
)
4384 return (fixp
->fx_next
!= NULL
4385 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4386 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4387 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4390 /* Move all labels in LABELS to the current insertion point. TEXT_P
4391 says whether the labels refer to text or data. */
4394 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4396 struct insn_label_list
*l
;
4399 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4401 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4402 symbol_set_frag (l
->label
, frag_now
);
4403 val
= (valueT
) frag_now_fix ();
4404 /* MIPS16/microMIPS text labels are stored as odd. */
4405 if (text_p
&& HAVE_CODE_COMPRESSION
)
4407 S_SET_VALUE (l
->label
, val
);
4411 /* Move all labels in insn_labels to the current insertion point
4412 and treat them as text labels. */
4415 mips_move_text_labels (void)
4417 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4420 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4423 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4425 bfd_boolean linkonce
= FALSE
;
4426 segT symseg
= S_GET_SEGMENT (sym
);
4428 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4430 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4432 /* The GNU toolchain uses an extension for ELF: a section
4433 beginning with the magic string .gnu.linkonce is a
4434 linkonce section. */
4435 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4436 sizeof ".gnu.linkonce" - 1) == 0)
4442 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4443 linker to handle them specially, such as generating jalx instructions
4444 when needed. We also make them odd for the duration of the assembly,
4445 in order to generate the right sort of code. We will make them even
4446 in the adjust_symtab routine, while leaving them marked. This is
4447 convenient for the debugger and the disassembler. The linker knows
4448 to make them odd again. */
4451 mips_compressed_mark_label (symbolS
*label
)
4453 gas_assert (HAVE_CODE_COMPRESSION
);
4455 if (mips_opts
.mips16
)
4456 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4458 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4459 if ((S_GET_VALUE (label
) & 1) == 0
4460 /* Don't adjust the address if the label is global or weak, or
4461 in a link-once section, since we'll be emitting symbol reloc
4462 references to it which will be patched up by the linker, and
4463 the final value of the symbol may or may not be MIPS16/microMIPS. */
4464 && !S_IS_WEAK (label
)
4465 && !S_IS_EXTERNAL (label
)
4466 && !s_is_linkonce (label
, now_seg
))
4467 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4470 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4473 mips_compressed_mark_labels (void)
4475 struct insn_label_list
*l
;
4477 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4478 mips_compressed_mark_label (l
->label
);
4481 /* End the current frag. Make it a variant frag and record the
4485 relax_close_frag (void)
4487 mips_macro_warning
.first_frag
= frag_now
;
4488 frag_var (rs_machine_dependent
, 0, 0,
4489 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4490 mips_pic
!= NO_PIC
),
4491 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4493 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4494 mips_relax
.first_fixup
= 0;
4497 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4498 See the comment above RELAX_ENCODE for more details. */
4501 relax_start (symbolS
*symbol
)
4503 gas_assert (mips_relax
.sequence
== 0);
4504 mips_relax
.sequence
= 1;
4505 mips_relax
.symbol
= symbol
;
4508 /* Start generating the second version of a relaxable sequence.
4509 See the comment above RELAX_ENCODE for more details. */
4514 gas_assert (mips_relax
.sequence
== 1);
4515 mips_relax
.sequence
= 2;
4518 /* End the current relaxable sequence. */
4523 gas_assert (mips_relax
.sequence
== 2);
4524 relax_close_frag ();
4525 mips_relax
.sequence
= 0;
4528 /* Return true if IP is a delayed branch or jump. */
4530 static inline bfd_boolean
4531 delayed_branch_p (const struct mips_cl_insn
*ip
)
4533 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4534 | INSN_COND_BRANCH_DELAY
4535 | INSN_COND_BRANCH_LIKELY
)) != 0;
4538 /* Return true if IP is a compact branch or jump. */
4540 static inline bfd_boolean
4541 compact_branch_p (const struct mips_cl_insn
*ip
)
4543 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4544 | INSN2_COND_BRANCH
)) != 0;
4547 /* Return true if IP is an unconditional branch or jump. */
4549 static inline bfd_boolean
4550 uncond_branch_p (const struct mips_cl_insn
*ip
)
4552 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4553 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4556 /* Return true if IP is a branch-likely instruction. */
4558 static inline bfd_boolean
4559 branch_likely_p (const struct mips_cl_insn
*ip
)
4561 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4564 /* Return the type of nop that should be used to fill the delay slot
4565 of delayed branch IP. */
4567 static struct mips_cl_insn
*
4568 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4570 if (mips_opts
.micromips
4571 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4572 return µmips_nop32_insn
;
4576 /* Return a mask that has bit N set if OPCODE reads the register(s)
4580 insn_read_mask (const struct mips_opcode
*opcode
)
4582 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4585 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4589 insn_write_mask (const struct mips_opcode
*opcode
)
4591 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4594 /* Return a mask of the registers specified by operand OPERAND of INSN.
4595 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4599 operand_reg_mask (const struct mips_cl_insn
*insn
,
4600 const struct mips_operand
*operand
,
4601 unsigned int type_mask
)
4603 unsigned int uval
, vsel
;
4605 switch (operand
->type
)
4612 case OP_ADDIUSP_INT
:
4613 case OP_ENTRY_EXIT_LIST
:
4614 case OP_REPEAT_DEST_REG
:
4615 case OP_REPEAT_PREV_REG
:
4618 case OP_VU0_MATCH_SUFFIX
:
4626 case OP_OPTIONAL_REG
:
4628 const struct mips_reg_operand
*reg_op
;
4630 reg_op
= (const struct mips_reg_operand
*) operand
;
4631 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4633 uval
= insn_extract_operand (insn
, operand
);
4634 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4639 const struct mips_reg_pair_operand
*pair_op
;
4641 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4642 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4644 uval
= insn_extract_operand (insn
, operand
);
4645 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4648 case OP_CLO_CLZ_DEST
:
4649 if (!(type_mask
& (1 << OP_REG_GP
)))
4651 uval
= insn_extract_operand (insn
, operand
);
4652 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4655 if (!(type_mask
& (1 << OP_REG_GP
)))
4657 uval
= insn_extract_operand (insn
, operand
);
4658 gas_assert ((uval
& 31) == (uval
>> 5));
4659 return 1 << (uval
& 31);
4662 case OP_NON_ZERO_REG
:
4663 if (!(type_mask
& (1 << OP_REG_GP
)))
4665 uval
= insn_extract_operand (insn
, operand
);
4666 return 1 << (uval
& 31);
4668 case OP_LWM_SWM_LIST
:
4671 case OP_SAVE_RESTORE_LIST
:
4674 case OP_MDMX_IMM_REG
:
4675 if (!(type_mask
& (1 << OP_REG_VEC
)))
4677 uval
= insn_extract_operand (insn
, operand
);
4679 if ((vsel
& 0x18) == 0x18)
4681 return 1 << (uval
& 31);
4684 if (!(type_mask
& (1 << OP_REG_GP
)))
4686 return 1 << insn_extract_operand (insn
, operand
);
4691 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4692 where bit N of OPNO_MASK is set if operand N should be included.
4693 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4697 insn_reg_mask (const struct mips_cl_insn
*insn
,
4698 unsigned int type_mask
, unsigned int opno_mask
)
4700 unsigned int opno
, reg_mask
;
4704 while (opno_mask
!= 0)
4707 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4714 /* Return the mask of core registers that IP reads. */
4717 gpr_read_mask (const struct mips_cl_insn
*ip
)
4719 unsigned long pinfo
, pinfo2
;
4722 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4723 pinfo
= ip
->insn_mo
->pinfo
;
4724 pinfo2
= ip
->insn_mo
->pinfo2
;
4725 if (pinfo
& INSN_UDI
)
4727 /* UDI instructions have traditionally been assumed to read RS
4729 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4730 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4732 if (pinfo
& INSN_READ_GPR_24
)
4734 if (pinfo2
& INSN2_READ_GPR_16
)
4736 if (pinfo2
& INSN2_READ_SP
)
4738 if (pinfo2
& INSN2_READ_GPR_31
)
4740 /* Don't include register 0. */
4744 /* Return the mask of core registers that IP writes. */
4747 gpr_write_mask (const struct mips_cl_insn
*ip
)
4749 unsigned long pinfo
, pinfo2
;
4752 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4753 pinfo
= ip
->insn_mo
->pinfo
;
4754 pinfo2
= ip
->insn_mo
->pinfo2
;
4755 if (pinfo
& INSN_WRITE_GPR_24
)
4757 if (pinfo
& INSN_WRITE_GPR_31
)
4759 if (pinfo
& INSN_UDI
)
4760 /* UDI instructions have traditionally been assumed to write to RD. */
4761 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4762 if (pinfo2
& INSN2_WRITE_SP
)
4764 /* Don't include register 0. */
4768 /* Return the mask of floating-point registers that IP reads. */
4771 fpr_read_mask (const struct mips_cl_insn
*ip
)
4773 unsigned long pinfo
;
4776 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4777 | (1 << OP_REG_MSA
)),
4778 insn_read_mask (ip
->insn_mo
));
4779 pinfo
= ip
->insn_mo
->pinfo
;
4780 /* Conservatively treat all operands to an FP_D instruction are doubles.
4781 (This is overly pessimistic for things like cvt.d.s.) */
4782 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4787 /* Return the mask of floating-point registers that IP writes. */
4790 fpr_write_mask (const struct mips_cl_insn
*ip
)
4792 unsigned long pinfo
;
4795 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4796 | (1 << OP_REG_MSA
)),
4797 insn_write_mask (ip
->insn_mo
));
4798 pinfo
= ip
->insn_mo
->pinfo
;
4799 /* Conservatively treat all operands to an FP_D instruction are doubles.
4800 (This is overly pessimistic for things like cvt.s.d.) */
4801 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4806 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4807 Check whether that is allowed. */
4810 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4812 const char *s
= insn
->name
;
4813 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4815 && mips_opts
.oddspreg
;
4817 if (insn
->pinfo
== INSN_MACRO
)
4818 /* Let a macro pass, we'll catch it later when it is expanded. */
4821 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4822 otherwise it depends on oddspreg. */
4823 if ((insn
->pinfo
& FP_S
)
4824 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4825 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4826 return FPR_SIZE
== 32 || oddspreg
;
4828 /* Allow odd registers for single-precision ops and double-precision if the
4829 floating-point registers are 64-bit wide. */
4830 switch (insn
->pinfo
& (FP_S
| FP_D
))
4836 return FPR_SIZE
== 64;
4841 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4842 s
= strchr (insn
->name
, '.');
4843 if (s
!= NULL
&& opnum
== 2)
4844 s
= strchr (s
+ 1, '.');
4845 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4848 return FPR_SIZE
== 64;
4851 /* Information about an instruction argument that we're trying to match. */
4852 struct mips_arg_info
4854 /* The instruction so far. */
4855 struct mips_cl_insn
*insn
;
4857 /* The first unconsumed operand token. */
4858 struct mips_operand_token
*token
;
4860 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4863 /* The 1-based argument number, for error reporting. This does not
4864 count elided optional registers, etc.. */
4867 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4868 unsigned int last_regno
;
4870 /* If the first operand was an OP_REG, this is the register that it
4871 specified, otherwise it is ILLEGAL_REG. */
4872 unsigned int dest_regno
;
4874 /* The value of the last OP_INT operand. Only used for OP_MSB,
4875 where it gives the lsb position. */
4876 unsigned int last_op_int
;
4878 /* If true, match routines should assume that no later instruction
4879 alternative matches and should therefore be as accommodating as
4880 possible. Match routines should not report errors if something
4881 is only invalid for !LAX_MATCH. */
4882 bfd_boolean lax_match
;
4884 /* True if a reference to the current AT register was seen. */
4885 bfd_boolean seen_at
;
4888 /* Record that the argument is out of range. */
4891 match_out_of_range (struct mips_arg_info
*arg
)
4893 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4896 /* Record that the argument isn't constant but needs to be. */
4899 match_not_constant (struct mips_arg_info
*arg
)
4901 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4905 /* Try to match an OT_CHAR token for character CH. Consume the token
4906 and return true on success, otherwise return false. */
4909 match_char (struct mips_arg_info
*arg
, char ch
)
4911 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4921 /* Try to get an expression from the next tokens in ARG. Consume the
4922 tokens and return true on success, storing the expression value in
4923 VALUE and relocation types in R. */
4926 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4927 bfd_reloc_code_real_type
*r
)
4929 /* If the next token is a '(' that was parsed as being part of a base
4930 expression, assume we have an elided offset. The later match will fail
4931 if this turns out to be wrong. */
4932 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4934 value
->X_op
= O_constant
;
4935 value
->X_add_number
= 0;
4936 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4940 /* Reject register-based expressions such as "0+$2" and "(($2))".
4941 For plain registers the default error seems more appropriate. */
4942 if (arg
->token
->type
== OT_INTEGER
4943 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4945 set_insn_error (arg
->argnum
, _("register value used as expression"));
4949 if (arg
->token
->type
== OT_INTEGER
)
4951 *value
= arg
->token
->u
.integer
.value
;
4952 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4958 (arg
->argnum
, _("operand %d must be an immediate expression"),
4963 /* Try to get a constant expression from the next tokens in ARG. Consume
4964 the tokens and return true on success, storing the constant value
4968 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4971 bfd_reloc_code_real_type r
[3];
4973 if (!match_expression (arg
, &ex
, r
))
4976 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4977 *value
= ex
.X_add_number
;
4980 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
4981 match_out_of_range (arg
);
4983 match_not_constant (arg
);
4989 /* Return the RTYPE_* flags for a register operand of type TYPE that
4990 appears in instruction OPCODE. */
4993 convert_reg_type (const struct mips_opcode
*opcode
,
4994 enum mips_reg_operand_type type
)
4999 return RTYPE_NUM
| RTYPE_GP
;
5002 /* Allow vector register names for MDMX if the instruction is a 64-bit
5003 FPR load, store or move (including moves to and from GPRs). */
5004 if ((mips_opts
.ase
& ASE_MDMX
)
5005 && (opcode
->pinfo
& FP_D
)
5006 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5007 | INSN_COPROC_MEMORY_DELAY
5010 | INSN_STORE_MEMORY
)))
5011 return RTYPE_FPU
| RTYPE_VEC
;
5015 if (opcode
->pinfo
& (FP_D
| FP_S
))
5016 return RTYPE_CCC
| RTYPE_FCC
;
5020 if (opcode
->membership
& INSN_5400
)
5022 return RTYPE_FPU
| RTYPE_VEC
;
5028 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5029 return RTYPE_NUM
| RTYPE_CP0
;
5036 return RTYPE_NUM
| RTYPE_VI
;
5039 return RTYPE_NUM
| RTYPE_VF
;
5041 case OP_REG_R5900_I
:
5042 return RTYPE_R5900_I
;
5044 case OP_REG_R5900_Q
:
5045 return RTYPE_R5900_Q
;
5047 case OP_REG_R5900_R
:
5048 return RTYPE_R5900_R
;
5050 case OP_REG_R5900_ACC
:
5051 return RTYPE_R5900_ACC
;
5056 case OP_REG_MSA_CTRL
:
5062 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5065 check_regno (struct mips_arg_info
*arg
,
5066 enum mips_reg_operand_type type
, unsigned int regno
)
5068 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5069 arg
->seen_at
= TRUE
;
5071 if (type
== OP_REG_FP
5073 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5075 /* This was a warning prior to introducing O32 FPXX and FP64 support
5076 so maintain a warning for FP32 but raise an error for the new
5079 as_warn (_("float register should be even, was %d"), regno
);
5081 as_bad (_("float register should be even, was %d"), regno
);
5084 if (type
== OP_REG_CCC
)
5089 name
= arg
->insn
->insn_mo
->name
;
5090 length
= strlen (name
);
5091 if ((regno
& 1) != 0
5092 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5093 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5094 as_warn (_("condition code register should be even for %s, was %d"),
5097 if ((regno
& 3) != 0
5098 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5099 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5104 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5105 a register of type TYPE. Return true on success, storing the register
5106 number in *REGNO and warning about any dubious uses. */
5109 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5110 unsigned int symval
, unsigned int *regno
)
5112 if (type
== OP_REG_VEC
)
5113 symval
= mips_prefer_vec_regno (symval
);
5114 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5117 *regno
= symval
& RNUM_MASK
;
5118 check_regno (arg
, type
, *regno
);
5122 /* Try to interpret the next token in ARG as a register of type TYPE.
5123 Consume the token and return true on success, storing the register
5124 number in *REGNO. Return false on failure. */
5127 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5128 unsigned int *regno
)
5130 if (arg
->token
->type
== OT_REG
5131 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5139 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5140 Consume the token and return true on success, storing the register numbers
5141 in *REGNO1 and *REGNO2. Return false on failure. */
5144 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5145 unsigned int *regno1
, unsigned int *regno2
)
5147 if (match_reg (arg
, type
, regno1
))
5152 if (arg
->token
->type
== OT_REG_RANGE
5153 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5154 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5155 && *regno1
<= *regno2
)
5163 /* OP_INT matcher. */
5166 match_int_operand (struct mips_arg_info
*arg
,
5167 const struct mips_operand
*operand_base
)
5169 const struct mips_int_operand
*operand
;
5171 int min_val
, max_val
, factor
;
5174 operand
= (const struct mips_int_operand
*) operand_base
;
5175 factor
= 1 << operand
->shift
;
5176 min_val
= mips_int_operand_min (operand
);
5177 max_val
= mips_int_operand_max (operand
);
5179 if (operand_base
->lsb
== 0
5180 && operand_base
->size
== 16
5181 && operand
->shift
== 0
5182 && operand
->bias
== 0
5183 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5185 /* The operand can be relocated. */
5186 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5189 if (offset_expr
.X_op
== O_big
)
5191 match_out_of_range (arg
);
5195 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5196 /* Relocation operators were used. Accept the argument and
5197 leave the relocation value in offset_expr and offset_relocs
5198 for the caller to process. */
5201 if (offset_expr
.X_op
!= O_constant
)
5203 /* Accept non-constant operands if no later alternative matches,
5204 leaving it for the caller to process. */
5205 if (!arg
->lax_match
)
5207 match_not_constant (arg
);
5210 offset_reloc
[0] = BFD_RELOC_LO16
;
5214 /* Clear the global state; we're going to install the operand
5216 sval
= offset_expr
.X_add_number
;
5217 offset_expr
.X_op
= O_absent
;
5219 /* For compatibility with older assemblers, we accept
5220 0x8000-0xffff as signed 16-bit numbers when only
5221 signed numbers are allowed. */
5224 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5225 if (!arg
->lax_match
&& sval
<= max_val
)
5227 match_out_of_range (arg
);
5234 if (!match_const_int (arg
, &sval
))
5238 arg
->last_op_int
= sval
;
5240 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5242 match_out_of_range (arg
);
5246 uval
= (unsigned int) sval
>> operand
->shift
;
5247 uval
-= operand
->bias
;
5249 /* Handle -mfix-cn63xxp1. */
5251 && mips_fix_cn63xxp1
5252 && !mips_opts
.micromips
5253 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5268 /* The rest must be changed to 28. */
5273 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5277 /* OP_MAPPED_INT matcher. */
5280 match_mapped_int_operand (struct mips_arg_info
*arg
,
5281 const struct mips_operand
*operand_base
)
5283 const struct mips_mapped_int_operand
*operand
;
5284 unsigned int uval
, num_vals
;
5287 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5288 if (!match_const_int (arg
, &sval
))
5291 num_vals
= 1 << operand_base
->size
;
5292 for (uval
= 0; uval
< num_vals
; uval
++)
5293 if (operand
->int_map
[uval
] == sval
)
5295 if (uval
== num_vals
)
5297 match_out_of_range (arg
);
5301 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5305 /* OP_MSB matcher. */
5308 match_msb_operand (struct mips_arg_info
*arg
,
5309 const struct mips_operand
*operand_base
)
5311 const struct mips_msb_operand
*operand
;
5312 int min_val
, max_val
, max_high
;
5313 offsetT size
, sval
, high
;
5315 operand
= (const struct mips_msb_operand
*) operand_base
;
5316 min_val
= operand
->bias
;
5317 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5318 max_high
= operand
->opsize
;
5320 if (!match_const_int (arg
, &size
))
5323 high
= size
+ arg
->last_op_int
;
5324 sval
= operand
->add_lsb
? high
: size
;
5326 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5328 match_out_of_range (arg
);
5331 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5335 /* OP_REG matcher. */
5338 match_reg_operand (struct mips_arg_info
*arg
,
5339 const struct mips_operand
*operand_base
)
5341 const struct mips_reg_operand
*operand
;
5342 unsigned int regno
, uval
, num_vals
;
5344 operand
= (const struct mips_reg_operand
*) operand_base
;
5345 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5348 if (operand
->reg_map
)
5350 num_vals
= 1 << operand
->root
.size
;
5351 for (uval
= 0; uval
< num_vals
; uval
++)
5352 if (operand
->reg_map
[uval
] == regno
)
5354 if (num_vals
== uval
)
5360 arg
->last_regno
= regno
;
5361 if (arg
->opnum
== 1)
5362 arg
->dest_regno
= regno
;
5363 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5367 /* OP_REG_PAIR matcher. */
5370 match_reg_pair_operand (struct mips_arg_info
*arg
,
5371 const struct mips_operand
*operand_base
)
5373 const struct mips_reg_pair_operand
*operand
;
5374 unsigned int regno1
, regno2
, uval
, num_vals
;
5376 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5377 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5378 || !match_char (arg
, ',')
5379 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5382 num_vals
= 1 << operand_base
->size
;
5383 for (uval
= 0; uval
< num_vals
; uval
++)
5384 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5386 if (uval
== num_vals
)
5389 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5393 /* OP_PCREL matcher. The caller chooses the relocation type. */
5396 match_pcrel_operand (struct mips_arg_info
*arg
)
5398 bfd_reloc_code_real_type r
[3];
5400 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5403 /* OP_PERF_REG matcher. */
5406 match_perf_reg_operand (struct mips_arg_info
*arg
,
5407 const struct mips_operand
*operand
)
5411 if (!match_const_int (arg
, &sval
))
5416 || (mips_opts
.arch
== CPU_R5900
5417 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5418 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5420 set_insn_error (arg
->argnum
, _("invalid performance register"));
5424 insn_insert_operand (arg
->insn
, operand
, sval
);
5428 /* OP_ADDIUSP matcher. */
5431 match_addiusp_operand (struct mips_arg_info
*arg
,
5432 const struct mips_operand
*operand
)
5437 if (!match_const_int (arg
, &sval
))
5442 match_out_of_range (arg
);
5447 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5449 match_out_of_range (arg
);
5453 uval
= (unsigned int) sval
;
5454 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5455 insn_insert_operand (arg
->insn
, operand
, uval
);
5459 /* OP_CLO_CLZ_DEST matcher. */
5462 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5463 const struct mips_operand
*operand
)
5467 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5470 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5474 /* OP_CHECK_PREV matcher. */
5477 match_check_prev_operand (struct mips_arg_info
*arg
,
5478 const struct mips_operand
*operand_base
)
5480 const struct mips_check_prev_operand
*operand
;
5483 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5485 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5488 if (!operand
->zero_ok
&& regno
== 0)
5491 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5492 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5493 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5495 arg
->last_regno
= regno
;
5496 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5503 /* OP_SAME_RS_RT matcher. */
5506 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5507 const struct mips_operand
*operand
)
5511 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5516 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5520 arg
->last_regno
= regno
;
5522 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5526 /* OP_LWM_SWM_LIST matcher. */
5529 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5530 const struct mips_operand
*operand
)
5532 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5533 struct mips_arg_info reset
;
5536 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5540 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5545 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5548 while (match_char (arg
, ',')
5549 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5552 if (operand
->size
== 2)
5554 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5560 and any permutations of these. */
5561 if ((reglist
& 0xfff1ffff) != 0x80010000)
5564 sregs
= (reglist
>> 17) & 7;
5569 /* The list must include at least one of ra and s0-sN,
5570 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5571 which are $23 and $30 respectively.) E.g.:
5579 and any permutations of these. */
5580 if ((reglist
& 0x3f00ffff) != 0)
5583 ra
= (reglist
>> 27) & 0x10;
5584 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5587 if ((sregs
& -sregs
) != sregs
)
5590 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5594 /* OP_ENTRY_EXIT_LIST matcher. */
5597 match_entry_exit_operand (struct mips_arg_info
*arg
,
5598 const struct mips_operand
*operand
)
5601 bfd_boolean is_exit
;
5603 /* The format is the same for both ENTRY and EXIT, but the constraints
5605 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5606 mask
= (is_exit
? 7 << 3 : 0);
5609 unsigned int regno1
, regno2
;
5610 bfd_boolean is_freg
;
5612 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5614 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5619 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5622 mask
|= (5 + regno2
) << 3;
5624 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5625 mask
|= (regno2
- 3) << 3;
5626 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5627 mask
|= (regno2
- 15) << 1;
5628 else if (regno1
== RA
&& regno2
== RA
)
5633 while (match_char (arg
, ','));
5635 insn_insert_operand (arg
->insn
, operand
, mask
);
5639 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5640 the argument register mask AMASK, the number of static registers
5641 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5642 respectively, and the frame size FRAME_SIZE. */
5645 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5646 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5647 unsigned int frame_size
)
5649 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5650 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5653 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5654 argument register mask AMASK, the number of static registers saved
5655 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5656 respectively, and the frame size FRAME_SIZE. */
5659 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5660 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5661 unsigned int frame_size
)
5665 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5666 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5667 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5668 | ((frame_size
& 0xf0) << 16));
5672 /* OP_SAVE_RESTORE_LIST matcher. */
5675 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5677 unsigned int opcode
, args
, statics
, sregs
;
5678 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5679 unsigned int arg_mask
, ra
, s0
, s1
;
5682 opcode
= arg
->insn
->insn_opcode
;
5684 num_frame_sizes
= 0;
5693 unsigned int regno1
, regno2
;
5695 if (arg
->token
->type
== OT_INTEGER
)
5697 /* Handle the frame size. */
5698 if (!match_const_int (arg
, &frame_size
))
5700 num_frame_sizes
+= 1;
5704 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5707 while (regno1
<= regno2
)
5709 if (regno1
>= 4 && regno1
<= 7)
5711 if (num_frame_sizes
== 0)
5713 args
|= 1 << (regno1
- 4);
5715 /* statics $a0-$a3 */
5716 statics
|= 1 << (regno1
- 4);
5718 else if (regno1
>= 16 && regno1
<= 23)
5720 sregs
|= 1 << (regno1
- 16);
5721 else if (regno1
== 30)
5724 else if (regno1
== 31)
5725 /* Add $ra to insn. */
5735 while (match_char (arg
, ','));
5737 /* Encode args/statics combination. */
5740 else if (args
== 0xf)
5741 /* All $a0-$a3 are args. */
5742 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5743 else if (statics
== 0xf)
5744 /* All $a0-$a3 are statics. */
5745 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5748 /* Count arg registers. */
5758 /* Count static registers. */
5760 while (statics
& 0x8)
5762 statics
= (statics
<< 1) & 0xf;
5768 /* Encode args/statics. */
5769 arg_mask
= (num_args
<< 2) | num_statics
;
5772 /* Encode $s0/$s1. */
5773 if (sregs
& (1 << 0)) /* $s0 */
5775 if (sregs
& (1 << 1)) /* $s1 */
5779 /* Encode $s2-$s8. */
5789 /* Encode frame size. */
5790 if (num_frame_sizes
== 0)
5792 set_insn_error (arg
->argnum
, _("missing frame size"));
5795 if (num_frame_sizes
> 1)
5797 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5800 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5802 set_insn_error (arg
->argnum
, _("invalid frame size"));
5807 /* Finally build the instruction. */
5808 if (mips_opts
.mips16
)
5809 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5811 else if (!mips_opts
.micromips
)
5812 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5817 arg
->insn
->insn_opcode
= opcode
;
5821 /* OP_MDMX_IMM_REG matcher. */
5824 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5825 const struct mips_operand
*operand
)
5827 unsigned int regno
, uval
;
5829 const struct mips_opcode
*opcode
;
5831 /* The mips_opcode records whether this is an octobyte or quadhalf
5832 instruction. Start out with that bit in place. */
5833 opcode
= arg
->insn
->insn_mo
;
5834 uval
= mips_extract_operand (operand
, opcode
->match
);
5835 is_qh
= (uval
!= 0);
5837 if (arg
->token
->type
== OT_REG
)
5839 if ((opcode
->membership
& INSN_5400
)
5840 && strcmp (opcode
->name
, "rzu.ob") == 0)
5842 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5847 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5851 /* Check whether this is a vector register or a broadcast of
5852 a single element. */
5853 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5855 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5857 set_insn_error (arg
->argnum
, _("invalid element selector"));
5860 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5865 /* A full vector. */
5866 if ((opcode
->membership
& INSN_5400
)
5867 && (strcmp (opcode
->name
, "sll.ob") == 0
5868 || strcmp (opcode
->name
, "srl.ob") == 0))
5870 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5876 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5878 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5886 if (!match_const_int (arg
, &sval
))
5888 if (sval
< 0 || sval
> 31)
5890 match_out_of_range (arg
);
5893 uval
|= (sval
& 31);
5895 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5897 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5899 insn_insert_operand (arg
->insn
, operand
, uval
);
5903 /* OP_IMM_INDEX matcher. */
5906 match_imm_index_operand (struct mips_arg_info
*arg
,
5907 const struct mips_operand
*operand
)
5909 unsigned int max_val
;
5911 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5914 max_val
= (1 << operand
->size
) - 1;
5915 if (arg
->token
->u
.index
> max_val
)
5917 match_out_of_range (arg
);
5920 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5925 /* OP_REG_INDEX matcher. */
5928 match_reg_index_operand (struct mips_arg_info
*arg
,
5929 const struct mips_operand
*operand
)
5933 if (arg
->token
->type
!= OT_REG_INDEX
)
5936 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5939 insn_insert_operand (arg
->insn
, operand
, regno
);
5944 /* OP_PC matcher. */
5947 match_pc_operand (struct mips_arg_info
*arg
)
5949 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5957 /* OP_REG28 matcher. */
5960 match_reg28_operand (struct mips_arg_info
*arg
)
5964 if (arg
->token
->type
== OT_REG
5965 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5974 /* OP_NON_ZERO_REG matcher. */
5977 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5978 const struct mips_operand
*operand
)
5982 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5988 arg
->last_regno
= regno
;
5989 insn_insert_operand (arg
->insn
, operand
, regno
);
5993 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5994 register that we need to match. */
5997 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6001 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6004 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6005 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6006 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6008 Return the constant in IMM and OFFSET as follows:
6010 - If the constant should be loaded via memory, set IMM to O_absent and
6011 OFFSET to the memory address.
6013 - Otherwise, if the constant should be loaded into two 32-bit registers,
6014 set IMM to the O_constant to load into the high register and OFFSET
6015 to the corresponding value for the low register.
6017 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6019 These constants only appear as the last operand in an instruction,
6020 and every instruction that accepts them in any variant accepts them
6021 in all variants. This means we don't have to worry about backing out
6022 any changes if the instruction does not match. We just match
6023 unconditionally and report an error if the constant is invalid. */
6026 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6027 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6032 const char *newname
;
6033 unsigned char *data
;
6035 /* Where the constant is placed is based on how the MIPS assembler
6038 length == 4 && using_gprs -- immediate value only
6039 length == 8 && using_gprs -- .rdata or immediate value
6040 length == 4 && !using_gprs -- .lit4 or immediate value
6041 length == 8 && !using_gprs -- .lit8 or immediate value
6043 The .lit4 and .lit8 sections are only used if permitted by the
6045 if (arg
->token
->type
!= OT_FLOAT
)
6047 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6051 gas_assert (arg
->token
->u
.flt
.length
== length
);
6052 data
= arg
->token
->u
.flt
.data
;
6055 /* Handle 32-bit constants for which an immediate value is best. */
6058 || g_switch_value
< 4
6059 || (data
[0] == 0 && data
[1] == 0)
6060 || (data
[2] == 0 && data
[3] == 0)))
6062 imm
->X_op
= O_constant
;
6063 if (!target_big_endian
)
6064 imm
->X_add_number
= bfd_getl32 (data
);
6066 imm
->X_add_number
= bfd_getb32 (data
);
6067 offset
->X_op
= O_absent
;
6071 /* Handle 64-bit constants for which an immediate value is best. */
6073 && !mips_disable_float_construction
6074 /* Constants can only be constructed in GPRs and copied to FPRs if the
6075 GPRs are at least as wide as the FPRs or MTHC1 is available.
6076 Unlike most tests for 32-bit floating-point registers this check
6077 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6078 permit 64-bit moves without MXHC1.
6079 Force the constant into memory otherwise. */
6082 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6084 && ((data
[0] == 0 && data
[1] == 0)
6085 || (data
[2] == 0 && data
[3] == 0))
6086 && ((data
[4] == 0 && data
[5] == 0)
6087 || (data
[6] == 0 && data
[7] == 0)))
6089 /* The value is simple enough to load with a couple of instructions.
6090 If using 32-bit registers, set IMM to the high order 32 bits and
6091 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6093 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6095 imm
->X_op
= O_constant
;
6096 offset
->X_op
= O_constant
;
6097 if (!target_big_endian
)
6099 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6100 offset
->X_add_number
= bfd_getl32 (data
);
6104 imm
->X_add_number
= bfd_getb32 (data
);
6105 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6107 if (offset
->X_add_number
== 0)
6108 offset
->X_op
= O_absent
;
6112 imm
->X_op
= O_constant
;
6113 if (!target_big_endian
)
6114 imm
->X_add_number
= bfd_getl64 (data
);
6116 imm
->X_add_number
= bfd_getb64 (data
);
6117 offset
->X_op
= O_absent
;
6122 /* Switch to the right section. */
6124 subseg
= now_subseg
;
6127 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6132 if (using_gprs
|| g_switch_value
< 8)
6133 newname
= RDATA_SECTION_NAME
;
6138 new_seg
= subseg_new (newname
, (subsegT
) 0);
6139 bfd_set_section_flags (stdoutput
, new_seg
,
6140 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6141 frag_align (length
== 4 ? 2 : 3, 0, 0);
6142 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6143 record_alignment (new_seg
, 4);
6145 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6147 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6149 /* Set the argument to the current address in the section. */
6150 imm
->X_op
= O_absent
;
6151 offset
->X_op
= O_symbol
;
6152 offset
->X_add_symbol
= symbol_temp_new_now ();
6153 offset
->X_add_number
= 0;
6155 /* Put the floating point number into the section. */
6156 p
= frag_more (length
);
6157 memcpy (p
, data
, length
);
6159 /* Switch back to the original section. */
6160 subseg_set (seg
, subseg
);
6164 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6168 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6169 const struct mips_operand
*operand
,
6170 bfd_boolean match_p
)
6174 /* The operand can be an XYZW mask or a single 2-bit channel index
6175 (with X being 0). */
6176 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6178 /* The suffix can be omitted when it is already part of the opcode. */
6179 if (arg
->token
->type
!= OT_CHANNELS
)
6182 uval
= arg
->token
->u
.channels
;
6183 if (operand
->size
== 2)
6185 /* Check that a single bit is set and convert it into a 2-bit index. */
6186 if ((uval
& -uval
) != uval
)
6188 uval
= 4 - ffs (uval
);
6191 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6196 insn_insert_operand (arg
->insn
, operand
, uval
);
6200 /* Try to match a token from ARG against OPERAND. Consume the token
6201 and return true on success, otherwise return false. */
6204 match_operand (struct mips_arg_info
*arg
,
6205 const struct mips_operand
*operand
)
6207 switch (operand
->type
)
6210 return match_int_operand (arg
, operand
);
6213 return match_mapped_int_operand (arg
, operand
);
6216 return match_msb_operand (arg
, operand
);
6219 case OP_OPTIONAL_REG
:
6220 return match_reg_operand (arg
, operand
);
6223 return match_reg_pair_operand (arg
, operand
);
6226 return match_pcrel_operand (arg
);
6229 return match_perf_reg_operand (arg
, operand
);
6231 case OP_ADDIUSP_INT
:
6232 return match_addiusp_operand (arg
, operand
);
6234 case OP_CLO_CLZ_DEST
:
6235 return match_clo_clz_dest_operand (arg
, operand
);
6237 case OP_LWM_SWM_LIST
:
6238 return match_lwm_swm_list_operand (arg
, operand
);
6240 case OP_ENTRY_EXIT_LIST
:
6241 return match_entry_exit_operand (arg
, operand
);
6243 case OP_SAVE_RESTORE_LIST
:
6244 return match_save_restore_list_operand (arg
);
6246 case OP_MDMX_IMM_REG
:
6247 return match_mdmx_imm_reg_operand (arg
, operand
);
6249 case OP_REPEAT_DEST_REG
:
6250 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6252 case OP_REPEAT_PREV_REG
:
6253 return match_tied_reg_operand (arg
, arg
->last_regno
);
6256 return match_pc_operand (arg
);
6259 return match_reg28_operand (arg
);
6262 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6264 case OP_VU0_MATCH_SUFFIX
:
6265 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6268 return match_imm_index_operand (arg
, operand
);
6271 return match_reg_index_operand (arg
, operand
);
6274 return match_same_rs_rt_operand (arg
, operand
);
6277 return match_check_prev_operand (arg
, operand
);
6279 case OP_NON_ZERO_REG
:
6280 return match_non_zero_reg_operand (arg
, operand
);
6285 /* ARG is the state after successfully matching an instruction.
6286 Issue any queued-up warnings. */
6289 check_completed_insn (struct mips_arg_info
*arg
)
6294 as_warn (_("used $at without \".set noat\""));
6296 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6300 /* Return true if modifying general-purpose register REG needs a delay. */
6303 reg_needs_delay (unsigned int reg
)
6305 unsigned long prev_pinfo
;
6307 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6308 if (!mips_opts
.noreorder
6309 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6310 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6311 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6317 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6318 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6319 by VR4120 errata. */
6322 classify_vr4120_insn (const char *name
)
6324 if (strncmp (name
, "macc", 4) == 0)
6325 return FIX_VR4120_MACC
;
6326 if (strncmp (name
, "dmacc", 5) == 0)
6327 return FIX_VR4120_DMACC
;
6328 if (strncmp (name
, "mult", 4) == 0)
6329 return FIX_VR4120_MULT
;
6330 if (strncmp (name
, "dmult", 5) == 0)
6331 return FIX_VR4120_DMULT
;
6332 if (strstr (name
, "div"))
6333 return FIX_VR4120_DIV
;
6334 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6335 return FIX_VR4120_MTHILO
;
6336 return NUM_FIX_VR4120_CLASSES
;
6339 #define INSN_ERET 0x42000018
6340 #define INSN_DERET 0x4200001f
6341 #define INSN_DMULT 0x1c
6342 #define INSN_DMULTU 0x1d
6344 /* Return the number of instructions that must separate INSN1 and INSN2,
6345 where INSN1 is the earlier instruction. Return the worst-case value
6346 for any INSN2 if INSN2 is null. */
6349 insns_between (const struct mips_cl_insn
*insn1
,
6350 const struct mips_cl_insn
*insn2
)
6352 unsigned long pinfo1
, pinfo2
;
6355 /* If INFO2 is null, pessimistically assume that all flags are set for
6356 the second instruction. */
6357 pinfo1
= insn1
->insn_mo
->pinfo
;
6358 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6360 /* For most targets, write-after-read dependencies on the HI and LO
6361 registers must be separated by at least two instructions. */
6362 if (!hilo_interlocks
)
6364 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6366 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6370 /* If we're working around r7000 errata, there must be two instructions
6371 between an mfhi or mflo and any instruction that uses the result. */
6372 if (mips_7000_hilo_fix
6373 && !mips_opts
.micromips
6374 && MF_HILO_INSN (pinfo1
)
6375 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6378 /* If we're working around 24K errata, one instruction is required
6379 if an ERET or DERET is followed by a branch instruction. */
6380 if (mips_fix_24k
&& !mips_opts
.micromips
)
6382 if (insn1
->insn_opcode
== INSN_ERET
6383 || insn1
->insn_opcode
== INSN_DERET
)
6386 || insn2
->insn_opcode
== INSN_ERET
6387 || insn2
->insn_opcode
== INSN_DERET
6388 || delayed_branch_p (insn2
))
6393 /* If we're working around PMC RM7000 errata, there must be three
6394 nops between a dmult and a load instruction. */
6395 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6397 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6398 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6400 if (pinfo2
& INSN_LOAD_MEMORY
)
6405 /* If working around VR4120 errata, check for combinations that need
6406 a single intervening instruction. */
6407 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6409 unsigned int class1
, class2
;
6411 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6412 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6416 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6417 if (vr4120_conflicts
[class1
] & (1 << class2
))
6422 if (!HAVE_CODE_COMPRESSION
)
6424 /* Check for GPR or coprocessor load delays. All such delays
6425 are on the RT register. */
6426 /* Itbl support may require additional care here. */
6427 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6428 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6430 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6434 /* Check for generic coprocessor hazards.
6436 This case is not handled very well. There is no special
6437 knowledge of CP0 handling, and the coprocessors other than
6438 the floating point unit are not distinguished at all. */
6439 /* Itbl support may require additional care here. FIXME!
6440 Need to modify this to include knowledge about
6441 user specified delays! */
6442 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6443 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6445 /* Handle cases where INSN1 writes to a known general coprocessor
6446 register. There must be a one instruction delay before INSN2
6447 if INSN2 reads that register, otherwise no delay is needed. */
6448 mask
= fpr_write_mask (insn1
);
6451 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6456 /* Read-after-write dependencies on the control registers
6457 require a two-instruction gap. */
6458 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6459 && (pinfo2
& INSN_READ_COND_CODE
))
6462 /* We don't know exactly what INSN1 does. If INSN2 is
6463 also a coprocessor instruction, assume there must be
6464 a one instruction gap. */
6465 if (pinfo2
& INSN_COP
)
6470 /* Check for read-after-write dependencies on the coprocessor
6471 control registers in cases where INSN1 does not need a general
6472 coprocessor delay. This means that INSN1 is a floating point
6473 comparison instruction. */
6474 /* Itbl support may require additional care here. */
6475 else if (!cop_interlocks
6476 && (pinfo1
& INSN_WRITE_COND_CODE
)
6477 && (pinfo2
& INSN_READ_COND_CODE
))
6481 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6482 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6484 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6485 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6486 || (insn2
&& delayed_branch_p (insn2
))))
6492 /* Return the number of nops that would be needed to work around the
6493 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6494 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6495 that are contained within the first IGNORE instructions of HIST. */
6498 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6499 const struct mips_cl_insn
*insn
)
6504 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6505 are not affected by the errata. */
6507 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6508 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6509 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6512 /* Search for the first MFLO or MFHI. */
6513 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6514 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6516 /* Extract the destination register. */
6517 mask
= gpr_write_mask (&hist
[i
]);
6519 /* No nops are needed if INSN reads that register. */
6520 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6523 /* ...or if any of the intervening instructions do. */
6524 for (j
= 0; j
< i
; j
++)
6525 if (gpr_read_mask (&hist
[j
]) & mask
)
6529 return MAX_VR4130_NOPS
- i
;
6534 #define BASE_REG_EQ(INSN1, INSN2) \
6535 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6536 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6538 /* Return the minimum alignment for this store instruction. */
6541 fix_24k_align_to (const struct mips_opcode
*mo
)
6543 if (strcmp (mo
->name
, "sh") == 0)
6546 if (strcmp (mo
->name
, "swc1") == 0
6547 || strcmp (mo
->name
, "swc2") == 0
6548 || strcmp (mo
->name
, "sw") == 0
6549 || strcmp (mo
->name
, "sc") == 0
6550 || strcmp (mo
->name
, "s.s") == 0)
6553 if (strcmp (mo
->name
, "sdc1") == 0
6554 || strcmp (mo
->name
, "sdc2") == 0
6555 || strcmp (mo
->name
, "s.d") == 0)
6562 struct fix_24k_store_info
6564 /* Immediate offset, if any, for this store instruction. */
6566 /* Alignment required by this store instruction. */
6568 /* True for register offsets. */
6569 int register_offset
;
6572 /* Comparison function used by qsort. */
6575 fix_24k_sort (const void *a
, const void *b
)
6577 const struct fix_24k_store_info
*pos1
= a
;
6578 const struct fix_24k_store_info
*pos2
= b
;
6580 return (pos1
->off
- pos2
->off
);
6583 /* INSN is a store instruction. Try to record the store information
6584 in STINFO. Return false if the information isn't known. */
6587 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6588 const struct mips_cl_insn
*insn
)
6590 /* The instruction must have a known offset. */
6591 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6594 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6595 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6599 /* Return the number of nops that would be needed to work around the 24k
6600 "lost data on stores during refill" errata if instruction INSN
6601 immediately followed the 2 instructions described by HIST.
6602 Ignore hazards that are contained within the first IGNORE
6603 instructions of HIST.
6605 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6606 for the data cache refills and store data. The following describes
6607 the scenario where the store data could be lost.
6609 * A data cache miss, due to either a load or a store, causing fill
6610 data to be supplied by the memory subsystem
6611 * The first three doublewords of fill data are returned and written
6613 * A sequence of four stores occurs in consecutive cycles around the
6614 final doubleword of the fill:
6618 * Zero, One or more instructions
6621 The four stores A-D must be to different doublewords of the line that
6622 is being filled. The fourth instruction in the sequence above permits
6623 the fill of the final doubleword to be transferred from the FSB into
6624 the cache. In the sequence above, the stores may be either integer
6625 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6626 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6627 different doublewords on the line. If the floating point unit is
6628 running in 1:2 mode, it is not possible to create the sequence above
6629 using only floating point store instructions.
6631 In this case, the cache line being filled is incorrectly marked
6632 invalid, thereby losing the data from any store to the line that
6633 occurs between the original miss and the completion of the five
6634 cycle sequence shown above.
6636 The workarounds are:
6638 * Run the data cache in write-through mode.
6639 * Insert a non-store instruction between
6640 Store A and Store B or Store B and Store C. */
6643 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6644 const struct mips_cl_insn
*insn
)
6646 struct fix_24k_store_info pos
[3];
6647 int align
, i
, base_offset
;
6652 /* If the previous instruction wasn't a store, there's nothing to
6654 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6657 /* If the instructions after the previous one are unknown, we have
6658 to assume the worst. */
6662 /* Check whether we are dealing with three consecutive stores. */
6663 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6664 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6667 /* If we don't know the relationship between the store addresses,
6668 assume the worst. */
6669 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6670 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6673 if (!fix_24k_record_store_info (&pos
[0], insn
)
6674 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6675 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6678 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6680 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6681 X bytes and such that the base register + X is known to be aligned
6684 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6688 align
= pos
[0].align_to
;
6689 base_offset
= pos
[0].off
;
6690 for (i
= 1; i
< 3; i
++)
6691 if (align
< pos
[i
].align_to
)
6693 align
= pos
[i
].align_to
;
6694 base_offset
= pos
[i
].off
;
6696 for (i
= 0; i
< 3; i
++)
6697 pos
[i
].off
-= base_offset
;
6700 pos
[0].off
&= ~align
+ 1;
6701 pos
[1].off
&= ~align
+ 1;
6702 pos
[2].off
&= ~align
+ 1;
6704 /* If any two stores write to the same chunk, they also write to the
6705 same doubleword. The offsets are still sorted at this point. */
6706 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6709 /* A range of at least 9 bytes is needed for the stores to be in
6710 non-overlapping doublewords. */
6711 if (pos
[2].off
- pos
[0].off
<= 8)
6714 if (pos
[2].off
- pos
[1].off
>= 24
6715 || pos
[1].off
- pos
[0].off
>= 24
6716 || pos
[2].off
- pos
[0].off
>= 32)
6722 /* Return the number of nops that would be needed if instruction INSN
6723 immediately followed the MAX_NOPS instructions given by HIST,
6724 where HIST[0] is the most recent instruction. Ignore hazards
6725 between INSN and the first IGNORE instructions in HIST.
6727 If INSN is null, return the worse-case number of nops for any
6731 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6732 const struct mips_cl_insn
*insn
)
6734 int i
, nops
, tmp_nops
;
6737 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6739 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6740 if (tmp_nops
> nops
)
6744 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6746 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6747 if (tmp_nops
> nops
)
6751 if (mips_fix_24k
&& !mips_opts
.micromips
)
6753 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6754 if (tmp_nops
> nops
)
6761 /* The variable arguments provide NUM_INSNS extra instructions that
6762 might be added to HIST. Return the largest number of nops that
6763 would be needed after the extended sequence, ignoring hazards
6764 in the first IGNORE instructions. */
6767 nops_for_sequence (int num_insns
, int ignore
,
6768 const struct mips_cl_insn
*hist
, ...)
6771 struct mips_cl_insn buffer
[MAX_NOPS
];
6772 struct mips_cl_insn
*cursor
;
6775 va_start (args
, hist
);
6776 cursor
= buffer
+ num_insns
;
6777 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6778 while (cursor
> buffer
)
6779 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6781 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6786 /* Like nops_for_insn, but if INSN is a branch, take into account the
6787 worst-case delay for the branch target. */
6790 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6791 const struct mips_cl_insn
*insn
)
6795 nops
= nops_for_insn (ignore
, hist
, insn
);
6796 if (delayed_branch_p (insn
))
6798 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6799 hist
, insn
, get_delay_slot_nop (insn
));
6800 if (tmp_nops
> nops
)
6803 else if (compact_branch_p (insn
))
6805 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6806 if (tmp_nops
> nops
)
6812 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6815 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6817 gas_assert (!HAVE_CODE_COMPRESSION
);
6818 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6819 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6822 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6823 jr target pc &= 'hffff_ffff_cfff_ffff. */
6826 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6828 gas_assert (!HAVE_CODE_COMPRESSION
);
6829 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6830 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6831 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6839 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6840 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6843 ep
.X_op
= O_constant
;
6844 ep
.X_add_number
= 0xcfff0000;
6845 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6846 ep
.X_add_number
= 0xffff;
6847 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6848 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6853 fix_loongson2f (struct mips_cl_insn
* ip
)
6855 if (mips_fix_loongson2f_nop
)
6856 fix_loongson2f_nop (ip
);
6858 if (mips_fix_loongson2f_jump
)
6859 fix_loongson2f_jump (ip
);
6862 /* IP is a branch that has a delay slot, and we need to fill it
6863 automatically. Return true if we can do that by swapping IP
6864 with the previous instruction.
6865 ADDRESS_EXPR is an operand of the instruction to be used with
6869 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6870 bfd_reloc_code_real_type
*reloc_type
)
6872 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6873 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6874 unsigned int fpr_read
, prev_fpr_write
;
6876 /* -O2 and above is required for this optimization. */
6877 if (mips_optimize
< 2)
6880 /* If we have seen .set volatile or .set nomove, don't optimize. */
6881 if (mips_opts
.nomove
)
6884 /* We can't swap if the previous instruction's position is fixed. */
6885 if (history
[0].fixed_p
)
6888 /* If the previous previous insn was in a .set noreorder, we can't
6889 swap. Actually, the MIPS assembler will swap in this situation.
6890 However, gcc configured -with-gnu-as will generate code like
6898 in which we can not swap the bne and INSN. If gcc is not configured
6899 -with-gnu-as, it does not output the .set pseudo-ops. */
6900 if (history
[1].noreorder_p
)
6903 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6904 This means that the previous instruction was a 4-byte one anyhow. */
6905 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6908 /* If the branch is itself the target of a branch, we can not swap.
6909 We cheat on this; all we check for is whether there is a label on
6910 this instruction. If there are any branches to anything other than
6911 a label, users must use .set noreorder. */
6912 if (seg_info (now_seg
)->label_list
)
6915 /* If the previous instruction is in a variant frag other than this
6916 branch's one, we cannot do the swap. This does not apply to
6917 MIPS16 code, which uses variant frags for different purposes. */
6918 if (!mips_opts
.mips16
6920 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6923 /* We do not swap with instructions that cannot architecturally
6924 be placed in a branch delay slot, such as SYNC or ERET. We
6925 also refrain from swapping with a trap instruction, since it
6926 complicates trap handlers to have the trap instruction be in
6928 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6929 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6932 /* Check for conflicts between the branch and the instructions
6933 before the candidate delay slot. */
6934 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6937 /* Check for conflicts between the swapped sequence and the
6938 target of the branch. */
6939 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6942 /* If the branch reads a register that the previous
6943 instruction sets, we can not swap. */
6944 gpr_read
= gpr_read_mask (ip
);
6945 prev_gpr_write
= gpr_write_mask (&history
[0]);
6946 if (gpr_read
& prev_gpr_write
)
6949 fpr_read
= fpr_read_mask (ip
);
6950 prev_fpr_write
= fpr_write_mask (&history
[0]);
6951 if (fpr_read
& prev_fpr_write
)
6954 /* If the branch writes a register that the previous
6955 instruction sets, we can not swap. */
6956 gpr_write
= gpr_write_mask (ip
);
6957 if (gpr_write
& prev_gpr_write
)
6960 /* If the branch writes a register that the previous
6961 instruction reads, we can not swap. */
6962 prev_gpr_read
= gpr_read_mask (&history
[0]);
6963 if (gpr_write
& prev_gpr_read
)
6966 /* If one instruction sets a condition code and the
6967 other one uses a condition code, we can not swap. */
6968 pinfo
= ip
->insn_mo
->pinfo
;
6969 if ((pinfo
& INSN_READ_COND_CODE
)
6970 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6972 if ((pinfo
& INSN_WRITE_COND_CODE
)
6973 && (prev_pinfo
& INSN_READ_COND_CODE
))
6976 /* If the previous instruction uses the PC, we can not swap. */
6977 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6978 if (prev_pinfo2
& INSN2_READ_PC
)
6981 /* If the previous instruction has an incorrect size for a fixed
6982 branch delay slot in microMIPS mode, we cannot swap. */
6983 pinfo2
= ip
->insn_mo
->pinfo2
;
6984 if (mips_opts
.micromips
6985 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6986 && insn_length (history
) != 2)
6988 if (mips_opts
.micromips
6989 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6990 && insn_length (history
) != 4)
6993 /* On the R5900 short loops need to be fixed by inserting a NOP in the
6996 The short loop bug under certain conditions causes loops to execute
6997 only once or twice. We must ensure that the assembler never
6998 generates loops that satisfy all of the following conditions:
7000 - a loop consists of less than or equal to six instructions
7001 (including the branch delay slot);
7002 - a loop contains only one conditional branch instruction at the end
7004 - a loop does not contain any other branch or jump instructions;
7005 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7007 We need to do this because of a hardware bug in the R5900 chip. */
7009 /* Check if instruction has a parameter, ignore "j $31". */
7010 && (address_expr
!= NULL
)
7011 /* Parameter must be 16 bit. */
7012 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7013 /* Branch to same segment. */
7014 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7015 /* Branch to same code fragment. */
7016 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7017 /* Can only calculate branch offset if value is known. */
7018 && symbol_constant_p (address_expr
->X_add_symbol
)
7019 /* Check if branch is really conditional. */
7020 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7021 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7022 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7025 /* Check if loop is shorter than or equal to 6 instructions
7026 including branch and delay slot. */
7027 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7034 /* When the loop includes branches or jumps,
7035 it is not a short loop. */
7036 for (i
= 0; i
< (distance
/ 4); i
++)
7038 if ((history
[i
].cleared_p
)
7039 || delayed_branch_p (&history
[i
]))
7047 /* Insert nop after branch to fix short loop. */
7056 /* Decide how we should add IP to the instruction stream.
7057 ADDRESS_EXPR is an operand of the instruction to be used with
7060 static enum append_method
7061 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7062 bfd_reloc_code_real_type
*reloc_type
)
7064 /* The relaxed version of a macro sequence must be inherently
7066 if (mips_relax
.sequence
== 2)
7069 /* We must not dabble with instructions in a ".set noreorder" block. */
7070 if (mips_opts
.noreorder
)
7073 /* Otherwise, it's our responsibility to fill branch delay slots. */
7074 if (delayed_branch_p (ip
))
7076 if (!branch_likely_p (ip
)
7077 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7080 if (mips_opts
.mips16
7081 && ISA_SUPPORTS_MIPS16E
7082 && gpr_read_mask (ip
) != 0)
7083 return APPEND_ADD_COMPACT
;
7085 if (mips_opts
.micromips
7086 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7087 || (!forced_insn_length
7088 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7089 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7090 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7091 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7092 return APPEND_ADD_COMPACT
;
7094 return APPEND_ADD_WITH_NOP
;
7100 /* IP is an instruction whose opcode we have just changed, END points
7101 to the end of the opcode table processed. Point IP->insn_mo to the
7102 new opcode's definition. */
7105 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7107 const struct mips_opcode
*mo
;
7109 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7110 if (mo
->pinfo
!= INSN_MACRO
7111 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7119 /* IP is a MIPS16 instruction whose opcode we have just changed.
7120 Point IP->insn_mo to the new opcode's definition. */
7123 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7125 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7128 /* IP is a microMIPS instruction whose opcode we have just changed.
7129 Point IP->insn_mo to the new opcode's definition. */
7132 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7134 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7137 /* For microMIPS macros, we need to generate a local number label
7138 as the target of branches. */
7139 #define MICROMIPS_LABEL_CHAR '\037'
7140 static unsigned long micromips_target_label
;
7141 static char micromips_target_name
[32];
7144 micromips_label_name (void)
7146 char *p
= micromips_target_name
;
7147 char symbol_name_temporary
[24];
7155 l
= micromips_target_label
;
7156 #ifdef LOCAL_LABEL_PREFIX
7157 *p
++ = LOCAL_LABEL_PREFIX
;
7160 *p
++ = MICROMIPS_LABEL_CHAR
;
7163 symbol_name_temporary
[i
++] = l
% 10 + '0';
7168 *p
++ = symbol_name_temporary
[--i
];
7171 return micromips_target_name
;
7175 micromips_label_expr (expressionS
*label_expr
)
7177 label_expr
->X_op
= O_symbol
;
7178 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7179 label_expr
->X_add_number
= 0;
7183 micromips_label_inc (void)
7185 micromips_target_label
++;
7186 *micromips_target_name
= '\0';
7190 micromips_add_label (void)
7194 s
= colon (micromips_label_name ());
7195 micromips_label_inc ();
7196 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7199 /* If assembling microMIPS code, then return the microMIPS reloc
7200 corresponding to the requested one if any. Otherwise return
7201 the reloc unchanged. */
7203 static bfd_reloc_code_real_type
7204 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7206 static const bfd_reloc_code_real_type relocs
[][2] =
7208 /* Keep sorted incrementally by the left-hand key. */
7209 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7210 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7211 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7212 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7213 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7214 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7215 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7216 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7217 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7218 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7219 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7220 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7221 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7222 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7223 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7224 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7225 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7226 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7227 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7228 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7229 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7230 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7231 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7232 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7233 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7234 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7235 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7237 bfd_reloc_code_real_type r
;
7240 if (!mips_opts
.micromips
)
7242 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7248 return relocs
[i
][1];
7253 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7254 Return true on success, storing the resolved value in RESULT. */
7257 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7262 case BFD_RELOC_MIPS_HIGHEST
:
7263 case BFD_RELOC_MICROMIPS_HIGHEST
:
7264 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7267 case BFD_RELOC_MIPS_HIGHER
:
7268 case BFD_RELOC_MICROMIPS_HIGHER
:
7269 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7272 case BFD_RELOC_HI16_S
:
7273 case BFD_RELOC_HI16_S_PCREL
:
7274 case BFD_RELOC_MICROMIPS_HI16_S
:
7275 case BFD_RELOC_MIPS16_HI16_S
:
7276 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7279 case BFD_RELOC_HI16
:
7280 case BFD_RELOC_MICROMIPS_HI16
:
7281 case BFD_RELOC_MIPS16_HI16
:
7282 *result
= (operand
>> 16) & 0xffff;
7285 case BFD_RELOC_LO16
:
7286 case BFD_RELOC_LO16_PCREL
:
7287 case BFD_RELOC_MICROMIPS_LO16
:
7288 case BFD_RELOC_MIPS16_LO16
:
7289 *result
= operand
& 0xffff;
7292 case BFD_RELOC_UNUSED
:
7301 /* Output an instruction. IP is the instruction information.
7302 ADDRESS_EXPR is an operand of the instruction to be used with
7303 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7304 a macro expansion. */
7307 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7308 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7310 unsigned long prev_pinfo2
, pinfo
;
7311 bfd_boolean relaxed_branch
= FALSE
;
7312 enum append_method method
;
7313 bfd_boolean relax32
;
7316 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7317 fix_loongson2f (ip
);
7319 file_ase_mips16
|= mips_opts
.mips16
;
7320 file_ase_micromips
|= mips_opts
.micromips
;
7322 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7323 pinfo
= ip
->insn_mo
->pinfo
;
7325 /* Don't raise alarm about `nods' frags as they'll fill in the right
7326 kind of nop in relaxation if required. */
7327 if (mips_opts
.micromips
7329 && !(history
[0].frag
7330 && history
[0].frag
->fr_type
== rs_machine_dependent
7331 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7332 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7333 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7334 && micromips_insn_length (ip
->insn_mo
) != 2)
7335 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7336 && micromips_insn_length (ip
->insn_mo
) != 4)))
7337 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7338 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7340 if (address_expr
== NULL
)
7342 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7343 && reloc_type
[1] == BFD_RELOC_UNUSED
7344 && reloc_type
[2] == BFD_RELOC_UNUSED
7345 && address_expr
->X_op
== O_constant
)
7347 switch (*reloc_type
)
7349 case BFD_RELOC_MIPS_JMP
:
7353 /* Shift is 2, unusually, for microMIPS JALX. */
7354 shift
= (mips_opts
.micromips
7355 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7356 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7357 as_bad (_("jump to misaligned address (0x%lx)"),
7358 (unsigned long) address_expr
->X_add_number
);
7359 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7365 case BFD_RELOC_MIPS16_JMP
:
7366 if ((address_expr
->X_add_number
& 3) != 0)
7367 as_bad (_("jump to misaligned address (0x%lx)"),
7368 (unsigned long) address_expr
->X_add_number
);
7370 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7371 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7372 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7376 case BFD_RELOC_16_PCREL_S2
:
7380 shift
= mips_opts
.micromips
? 1 : 2;
7381 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7382 as_bad (_("branch to misaligned address (0x%lx)"),
7383 (unsigned long) address_expr
->X_add_number
);
7384 if (!mips_relax_branch
)
7386 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7387 & ~((1 << (shift
+ 16)) - 1))
7388 as_bad (_("branch address range overflow (0x%lx)"),
7389 (unsigned long) address_expr
->X_add_number
);
7390 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7396 case BFD_RELOC_MIPS_21_PCREL_S2
:
7401 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7402 as_bad (_("branch to misaligned address (0x%lx)"),
7403 (unsigned long) address_expr
->X_add_number
);
7404 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7405 & ~((1 << (shift
+ 21)) - 1))
7406 as_bad (_("branch address range overflow (0x%lx)"),
7407 (unsigned long) address_expr
->X_add_number
);
7408 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7413 case BFD_RELOC_MIPS_26_PCREL_S2
:
7418 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7419 as_bad (_("branch to misaligned address (0x%lx)"),
7420 (unsigned long) address_expr
->X_add_number
);
7421 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7422 & ~((1 << (shift
+ 26)) - 1))
7423 as_bad (_("branch address range overflow (0x%lx)"),
7424 (unsigned long) address_expr
->X_add_number
);
7425 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7434 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7437 ip
->insn_opcode
|= value
& 0xffff;
7445 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7447 /* There are a lot of optimizations we could do that we don't.
7448 In particular, we do not, in general, reorder instructions.
7449 If you use gcc with optimization, it will reorder
7450 instructions and generally do much more optimization then we
7451 do here; repeating all that work in the assembler would only
7452 benefit hand written assembly code, and does not seem worth
7454 int nops
= (mips_optimize
== 0
7455 ? nops_for_insn (0, history
, NULL
)
7456 : nops_for_insn_or_target (0, history
, ip
));
7460 unsigned long old_frag_offset
;
7463 old_frag
= frag_now
;
7464 old_frag_offset
= frag_now_fix ();
7466 for (i
= 0; i
< nops
; i
++)
7467 add_fixed_insn (NOP_INSN
);
7468 insert_into_history (0, nops
, NOP_INSN
);
7472 listing_prev_line ();
7473 /* We may be at the start of a variant frag. In case we
7474 are, make sure there is enough space for the frag
7475 after the frags created by listing_prev_line. The
7476 argument to frag_grow here must be at least as large
7477 as the argument to all other calls to frag_grow in
7478 this file. We don't have to worry about being in the
7479 middle of a variant frag, because the variants insert
7480 all needed nop instructions themselves. */
7484 mips_move_text_labels ();
7486 #ifndef NO_ECOFF_DEBUGGING
7487 if (ECOFF_DEBUGGING
)
7488 ecoff_fix_loc (old_frag
, old_frag_offset
);
7492 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7496 /* Work out how many nops in prev_nop_frag are needed by IP,
7497 ignoring hazards generated by the first prev_nop_frag_since
7499 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7500 gas_assert (nops
<= prev_nop_frag_holds
);
7502 /* Enforce NOPS as a minimum. */
7503 if (nops
> prev_nop_frag_required
)
7504 prev_nop_frag_required
= nops
;
7506 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7508 /* Settle for the current number of nops. Update the history
7509 accordingly (for the benefit of any future .set reorder code). */
7510 prev_nop_frag
= NULL
;
7511 insert_into_history (prev_nop_frag_since
,
7512 prev_nop_frag_holds
, NOP_INSN
);
7516 /* Allow this instruction to replace one of the nops that was
7517 tentatively added to prev_nop_frag. */
7518 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7519 prev_nop_frag_holds
--;
7520 prev_nop_frag_since
++;
7524 method
= get_append_method (ip
, address_expr
, reloc_type
);
7525 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7527 dwarf2_emit_insn (0);
7528 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7529 so "move" the instruction address accordingly.
7531 Also, it doesn't seem appropriate for the assembler to reorder .loc
7532 entries. If this instruction is a branch that we are going to swap
7533 with the previous instruction, the two instructions should be
7534 treated as a unit, and the debug information for both instructions
7535 should refer to the start of the branch sequence. Using the
7536 current position is certainly wrong when swapping a 32-bit branch
7537 and a 16-bit delay slot, since the current position would then be
7538 in the middle of a branch. */
7539 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7541 relax32
= (mips_relax_branch
7542 /* Don't try branch relaxation within .set nomacro, or within
7543 .set noat if we use $at for PIC computations. If it turns
7544 out that the branch was out-of-range, we'll get an error. */
7545 && !mips_opts
.warn_about_macros
7546 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7547 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7548 as they have no complementing branches. */
7549 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7551 if (!HAVE_CODE_COMPRESSION
7554 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7555 && delayed_branch_p (ip
))
7557 relaxed_branch
= TRUE
;
7558 add_relaxed_insn (ip
, (relaxed_branch_length
7560 uncond_branch_p (ip
) ? -1
7561 : branch_likely_p (ip
) ? 1
7564 (AT
, mips_pic
!= NO_PIC
,
7565 uncond_branch_p (ip
),
7566 branch_likely_p (ip
),
7567 pinfo
& INSN_WRITE_GPR_31
,
7569 address_expr
->X_add_symbol
,
7570 address_expr
->X_add_number
);
7571 *reloc_type
= BFD_RELOC_UNUSED
;
7573 else if (mips_opts
.micromips
7575 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7576 || *reloc_type
> BFD_RELOC_UNUSED
)
7577 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7578 /* Don't try branch relaxation when users specify
7579 16-bit/32-bit instructions. */
7580 && !forced_insn_length
)
7582 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7583 && *reloc_type
> BFD_RELOC_UNUSED
);
7584 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7585 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7586 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7587 int nods
= method
== APPEND_ADD_WITH_NOP
;
7588 int al
= pinfo
& INSN_WRITE_GPR_31
;
7589 int length32
= nods
? 8 : 4;
7591 gas_assert (address_expr
!= NULL
);
7592 gas_assert (!mips_relax
.sequence
);
7594 relaxed_branch
= TRUE
;
7596 method
= APPEND_ADD
;
7598 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7599 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7600 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7602 uncond
, compact
, al
, nods
,
7604 address_expr
->X_add_symbol
,
7605 address_expr
->X_add_number
);
7606 *reloc_type
= BFD_RELOC_UNUSED
;
7608 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7610 bfd_boolean require_unextended
;
7611 bfd_boolean require_extended
;
7615 if (forced_insn_length
!= 0)
7617 require_unextended
= forced_insn_length
== 2;
7618 require_extended
= forced_insn_length
== 4;
7622 require_unextended
= (mips_opts
.noautoextend
7623 && !mips_opcode_32bit_p (ip
->insn_mo
));
7624 require_extended
= 0;
7627 /* We need to set up a variant frag. */
7628 gas_assert (address_expr
!= NULL
);
7629 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7630 symbol created by `make_expr_symbol' may not get a necessary
7631 external relocation produced. */
7632 if (address_expr
->X_op
== O_symbol
)
7634 symbol
= address_expr
->X_add_symbol
;
7635 offset
= address_expr
->X_add_number
;
7639 symbol
= make_expr_symbol (address_expr
);
7640 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7643 add_relaxed_insn (ip
, 12, 0,
7645 (*reloc_type
- BFD_RELOC_UNUSED
,
7646 mips_opts
.ase
& ASE_MIPS16E2
,
7649 mips_opts
.warn_about_macros
,
7650 require_unextended
, require_extended
,
7651 delayed_branch_p (&history
[0]),
7652 history
[0].mips16_absolute_jump_p
),
7655 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7657 if (!delayed_branch_p (ip
))
7658 /* Make sure there is enough room to swap this instruction with
7659 a following jump instruction. */
7661 add_fixed_insn (ip
);
7665 if (mips_opts
.mips16
7666 && mips_opts
.noreorder
7667 && delayed_branch_p (&history
[0]))
7668 as_warn (_("extended instruction in delay slot"));
7670 if (mips_relax
.sequence
)
7672 /* If we've reached the end of this frag, turn it into a variant
7673 frag and record the information for the instructions we've
7675 if (frag_room () < 4)
7676 relax_close_frag ();
7677 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7680 if (mips_relax
.sequence
!= 2)
7682 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7683 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7684 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7685 mips_macro_warning
.insns
[0]++;
7687 if (mips_relax
.sequence
!= 1)
7689 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7690 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7691 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7692 mips_macro_warning
.insns
[1]++;
7695 if (mips_opts
.mips16
)
7698 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7700 add_fixed_insn (ip
);
7703 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7705 bfd_reloc_code_real_type final_type
[3];
7706 reloc_howto_type
*howto0
;
7707 reloc_howto_type
*howto
;
7710 /* Perform any necessary conversion to microMIPS relocations
7711 and find out how many relocations there actually are. */
7712 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7713 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7715 /* In a compound relocation, it is the final (outermost)
7716 operator that determines the relocated field. */
7717 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7722 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7723 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7724 bfd_get_reloc_size (howto
),
7726 howto0
&& howto0
->pc_relative
,
7728 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7729 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7731 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7732 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7733 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7735 /* These relocations can have an addend that won't fit in
7736 4 octets for 64bit assembly. */
7738 && ! howto
->partial_inplace
7739 && (reloc_type
[0] == BFD_RELOC_16
7740 || reloc_type
[0] == BFD_RELOC_32
7741 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7742 || reloc_type
[0] == BFD_RELOC_GPREL16
7743 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7744 || reloc_type
[0] == BFD_RELOC_GPREL32
7745 || reloc_type
[0] == BFD_RELOC_64
7746 || reloc_type
[0] == BFD_RELOC_CTOR
7747 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7748 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7749 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7750 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7751 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7752 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7753 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7754 || hi16_reloc_p (reloc_type
[0])
7755 || lo16_reloc_p (reloc_type
[0])))
7756 ip
->fixp
[0]->fx_no_overflow
= 1;
7758 /* These relocations can have an addend that won't fit in 2 octets. */
7759 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7760 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7761 ip
->fixp
[0]->fx_no_overflow
= 1;
7763 if (mips_relax
.sequence
)
7765 if (mips_relax
.first_fixup
== 0)
7766 mips_relax
.first_fixup
= ip
->fixp
[0];
7768 else if (reloc_needs_lo_p (*reloc_type
))
7770 struct mips_hi_fixup
*hi_fixup
;
7772 /* Reuse the last entry if it already has a matching %lo. */
7773 hi_fixup
= mips_hi_fixup_list
;
7775 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7777 hi_fixup
= XNEW (struct mips_hi_fixup
);
7778 hi_fixup
->next
= mips_hi_fixup_list
;
7779 mips_hi_fixup_list
= hi_fixup
;
7781 hi_fixup
->fixp
= ip
->fixp
[0];
7782 hi_fixup
->seg
= now_seg
;
7785 /* Add fixups for the second and third relocations, if given.
7786 Note that the ABI allows the second relocation to be
7787 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7788 moment we only use RSS_UNDEF, but we could add support
7789 for the others if it ever becomes necessary. */
7790 for (i
= 1; i
< 3; i
++)
7791 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7793 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7794 ip
->fixp
[0]->fx_size
, NULL
, 0,
7795 FALSE
, final_type
[i
]);
7797 /* Use fx_tcbit to mark compound relocs. */
7798 ip
->fixp
[0]->fx_tcbit
= 1;
7799 ip
->fixp
[i
]->fx_tcbit
= 1;
7803 /* Update the register mask information. */
7804 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7805 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7810 insert_into_history (0, 1, ip
);
7813 case APPEND_ADD_WITH_NOP
:
7815 struct mips_cl_insn
*nop
;
7817 insert_into_history (0, 1, ip
);
7818 nop
= get_delay_slot_nop (ip
);
7819 add_fixed_insn (nop
);
7820 insert_into_history (0, 1, nop
);
7821 if (mips_relax
.sequence
)
7822 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7826 case APPEND_ADD_COMPACT
:
7827 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7828 if (mips_opts
.mips16
)
7830 ip
->insn_opcode
|= 0x0080;
7831 find_altered_mips16_opcode (ip
);
7833 /* Convert microMIPS instructions. */
7834 else if (mips_opts
.micromips
)
7837 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7838 ip
->insn_opcode
|= 0x0020;
7840 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7841 ip
->insn_opcode
= 0x40e00000;
7842 /* beqz16->beqzc, bnez16->bnezc */
7843 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7845 unsigned long regno
;
7847 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7848 regno
&= MICROMIPSOP_MASK_MD
;
7849 regno
= micromips_to_32_reg_d_map
[regno
];
7850 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7851 | (regno
<< MICROMIPSOP_SH_RS
)
7852 | 0x40a00000) ^ 0x00400000;
7854 /* beqz->beqzc, bnez->bnezc */
7855 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7856 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7857 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7858 | 0x40a00000) ^ 0x00400000;
7859 /* beq $0->beqzc, bne $0->bnezc */
7860 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7861 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7862 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7863 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7864 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7865 | 0x40a00000) ^ 0x00400000;
7868 find_altered_micromips_opcode (ip
);
7873 insert_into_history (0, 1, ip
);
7878 struct mips_cl_insn delay
= history
[0];
7880 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7882 /* Add the delay slot instruction to the end of the
7883 current frag and shrink the fixed part of the
7884 original frag. If the branch occupies the tail of
7885 the latter, move it backwards to cover the gap. */
7886 delay
.frag
->fr_fix
-= branch_disp
;
7887 if (delay
.frag
== ip
->frag
)
7888 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7889 add_fixed_insn (&delay
);
7893 /* If this is not a relaxed branch and we are in the
7894 same frag, then just swap the instructions. */
7895 move_insn (ip
, delay
.frag
, delay
.where
);
7896 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7900 insert_into_history (0, 1, &delay
);
7905 /* If we have just completed an unconditional branch, clear the history. */
7906 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7907 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7911 mips_no_prev_insn ();
7913 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7914 history
[i
].cleared_p
= 1;
7917 /* We need to emit a label at the end of branch-likely macros. */
7918 if (emit_branch_likely_macro
)
7920 emit_branch_likely_macro
= FALSE
;
7921 micromips_add_label ();
7924 /* We just output an insn, so the next one doesn't have a label. */
7925 mips_clear_insn_labels ();
7928 /* Forget that there was any previous instruction or label.
7929 When BRANCH is true, the branch history is also flushed. */
7932 mips_no_prev_insn (void)
7934 prev_nop_frag
= NULL
;
7935 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7936 mips_clear_insn_labels ();
7939 /* This function must be called before we emit something other than
7940 instructions. It is like mips_no_prev_insn except that it inserts
7941 any NOPS that might be needed by previous instructions. */
7944 mips_emit_delays (void)
7946 if (! mips_opts
.noreorder
)
7948 int nops
= nops_for_insn (0, history
, NULL
);
7952 add_fixed_insn (NOP_INSN
);
7953 mips_move_text_labels ();
7956 mips_no_prev_insn ();
7959 /* Start a (possibly nested) noreorder block. */
7962 start_noreorder (void)
7964 if (mips_opts
.noreorder
== 0)
7969 /* None of the instructions before the .set noreorder can be moved. */
7970 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7971 history
[i
].fixed_p
= 1;
7973 /* Insert any nops that might be needed between the .set noreorder
7974 block and the previous instructions. We will later remove any
7975 nops that turn out not to be needed. */
7976 nops
= nops_for_insn (0, history
, NULL
);
7979 if (mips_optimize
!= 0)
7981 /* Record the frag which holds the nop instructions, so
7982 that we can remove them if we don't need them. */
7983 frag_grow (nops
* NOP_INSN_SIZE
);
7984 prev_nop_frag
= frag_now
;
7985 prev_nop_frag_holds
= nops
;
7986 prev_nop_frag_required
= 0;
7987 prev_nop_frag_since
= 0;
7990 for (; nops
> 0; --nops
)
7991 add_fixed_insn (NOP_INSN
);
7993 /* Move on to a new frag, so that it is safe to simply
7994 decrease the size of prev_nop_frag. */
7995 frag_wane (frag_now
);
7997 mips_move_text_labels ();
7999 mips_mark_labels ();
8000 mips_clear_insn_labels ();
8002 mips_opts
.noreorder
++;
8003 mips_any_noreorder
= 1;
8006 /* End a nested noreorder block. */
8009 end_noreorder (void)
8011 mips_opts
.noreorder
--;
8012 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8014 /* Commit to inserting prev_nop_frag_required nops and go back to
8015 handling nop insertion the .set reorder way. */
8016 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8018 insert_into_history (prev_nop_frag_since
,
8019 prev_nop_frag_required
, NOP_INSN
);
8020 prev_nop_frag
= NULL
;
8024 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8025 higher bits unset. */
8028 normalize_constant_expr (expressionS
*ex
)
8030 if (ex
->X_op
== O_constant
8031 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8032 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8036 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8037 all higher bits unset. */
8040 normalize_address_expr (expressionS
*ex
)
8042 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8043 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8044 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8045 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8049 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8050 Return true if the match was successful.
8052 OPCODE_EXTRA is a value that should be ORed into the opcode
8053 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8054 there are more alternatives after OPCODE and SOFT_MATCH is
8055 as for mips_arg_info. */
8058 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8059 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8060 bfd_boolean lax_match
, bfd_boolean complete_p
)
8063 struct mips_arg_info arg
;
8064 const struct mips_operand
*operand
;
8067 imm_expr
.X_op
= O_absent
;
8068 offset_expr
.X_op
= O_absent
;
8069 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8070 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8071 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8073 create_insn (insn
, opcode
);
8074 /* When no opcode suffix is specified, assume ".xyzw". */
8075 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8076 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8078 insn
->insn_opcode
|= opcode_extra
;
8079 memset (&arg
, 0, sizeof (arg
));
8083 arg
.last_regno
= ILLEGAL_REG
;
8084 arg
.dest_regno
= ILLEGAL_REG
;
8085 arg
.lax_match
= lax_match
;
8086 for (args
= opcode
->args
;; ++args
)
8088 if (arg
.token
->type
== OT_END
)
8090 /* Handle unary instructions in which only one operand is given.
8091 The source is then the same as the destination. */
8092 if (arg
.opnum
== 1 && *args
== ',')
8094 operand
= (mips_opts
.micromips
8095 ? decode_micromips_operand (args
+ 1)
8096 : decode_mips_operand (args
+ 1));
8097 if (operand
&& mips_optional_operand_p (operand
))
8105 /* Treat elided base registers as $0. */
8106 if (strcmp (args
, "(b)") == 0)
8114 /* The register suffix is optional. */
8119 /* Fail the match if there were too few operands. */
8123 /* Successful match. */
8126 clear_insn_error ();
8127 if (arg
.dest_regno
== arg
.last_regno
8128 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8132 (0, _("source and destination must be different"));
8133 else if (arg
.last_regno
== 31)
8135 (0, _("a destination register must be supplied"));
8137 else if (arg
.last_regno
== 31
8138 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8139 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8140 set_insn_error (0, _("the source register must not be $31"));
8141 check_completed_insn (&arg
);
8145 /* Fail the match if the line has too many operands. */
8149 /* Handle characters that need to match exactly. */
8150 if (*args
== '(' || *args
== ')' || *args
== ',')
8152 if (match_char (&arg
, *args
))
8159 if (arg
.token
->type
== OT_DOUBLE_CHAR
8160 && arg
.token
->u
.ch
== *args
)
8168 /* Handle special macro operands. Work out the properties of
8177 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8181 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8190 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8194 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8198 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8204 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8206 imm_expr
.X_op
= O_constant
;
8208 normalize_constant_expr (&imm_expr
);
8212 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8214 /* Assume that the offset has been elided and that what
8215 we saw was a base register. The match will fail later
8216 if that assumption turns out to be wrong. */
8217 offset_expr
.X_op
= O_constant
;
8218 offset_expr
.X_add_number
= 0;
8222 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8224 normalize_address_expr (&offset_expr
);
8229 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8235 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8241 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8247 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8253 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8257 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8261 gas_assert (mips_opts
.micromips
);
8267 if (!forced_insn_length
)
8268 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8270 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8272 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8278 operand
= (mips_opts
.micromips
8279 ? decode_micromips_operand (args
)
8280 : decode_mips_operand (args
));
8284 /* Skip prefixes. */
8285 if (*args
== '+' || *args
== 'm' || *args
== '-')
8288 if (mips_optional_operand_p (operand
)
8290 && (arg
.token
[0].type
!= OT_REG
8291 || arg
.token
[1].type
== OT_END
))
8293 /* Assume that the register has been elided and is the
8294 same as the first operand. */
8299 if (!match_operand (&arg
, operand
))
8304 /* Like match_insn, but for MIPS16. */
8307 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8308 struct mips_operand_token
*tokens
)
8311 const struct mips_operand
*operand
;
8312 const struct mips_operand
*ext_operand
;
8313 bfd_boolean pcrel
= FALSE
;
8314 int required_insn_length
;
8315 struct mips_arg_info arg
;
8318 if (forced_insn_length
)
8319 required_insn_length
= forced_insn_length
;
8320 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8321 required_insn_length
= 2;
8323 required_insn_length
= 0;
8325 create_insn (insn
, opcode
);
8326 imm_expr
.X_op
= O_absent
;
8327 offset_expr
.X_op
= O_absent
;
8328 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8329 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8330 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8333 memset (&arg
, 0, sizeof (arg
));
8337 arg
.last_regno
= ILLEGAL_REG
;
8338 arg
.dest_regno
= ILLEGAL_REG
;
8340 for (args
= opcode
->args
;; ++args
)
8344 if (arg
.token
->type
== OT_END
)
8348 /* Handle unary instructions in which only one operand is given.
8349 The source is then the same as the destination. */
8350 if (arg
.opnum
== 1 && *args
== ',')
8352 operand
= decode_mips16_operand (args
[1], FALSE
);
8353 if (operand
&& mips_optional_operand_p (operand
))
8361 /* Fail the match if there were too few operands. */
8365 /* Successful match. Stuff the immediate value in now, if
8367 clear_insn_error ();
8368 if (opcode
->pinfo
== INSN_MACRO
)
8370 gas_assert (relax_char
== 0 || relax_char
== 'p');
8371 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8374 && offset_expr
.X_op
== O_constant
8376 && calculate_reloc (*offset_reloc
,
8377 offset_expr
.X_add_number
,
8380 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8381 required_insn_length
, &insn
->insn_opcode
);
8382 offset_expr
.X_op
= O_absent
;
8383 *offset_reloc
= BFD_RELOC_UNUSED
;
8385 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8387 if (required_insn_length
== 2)
8388 set_insn_error (0, _("invalid unextended operand value"));
8389 else if (!mips_opcode_32bit_p (opcode
))
8391 forced_insn_length
= 4;
8392 insn
->insn_opcode
|= MIPS16_EXTEND
;
8395 else if (relax_char
)
8396 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8398 check_completed_insn (&arg
);
8402 /* Fail the match if the line has too many operands. */
8406 /* Handle characters that need to match exactly. */
8407 if (*args
== '(' || *args
== ')' || *args
== ',')
8409 if (match_char (&arg
, *args
))
8429 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8431 imm_expr
.X_op
= O_constant
;
8433 normalize_constant_expr (&imm_expr
);
8438 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8442 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8446 if (operand
->type
== OP_PCREL
)
8450 ext_operand
= decode_mips16_operand (c
, TRUE
);
8451 if (operand
!= ext_operand
)
8453 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8455 offset_expr
.X_op
= O_constant
;
8456 offset_expr
.X_add_number
= 0;
8461 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8464 /* '8' is used for SLTI(U) and has traditionally not
8465 been allowed to take relocation operators. */
8466 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8467 && (ext_operand
->size
!= 16 || c
== '8'))
8469 match_not_constant (&arg
);
8473 if (offset_expr
.X_op
== O_big
)
8475 match_out_of_range (&arg
);
8484 if (mips_optional_operand_p (operand
)
8486 && (arg
.token
[0].type
!= OT_REG
8487 || arg
.token
[1].type
== OT_END
))
8489 /* Assume that the register has been elided and is the
8490 same as the first operand. */
8495 if (!match_operand (&arg
, operand
))
8500 /* Record that the current instruction is invalid for the current ISA. */
8503 match_invalid_for_isa (void)
8506 (0, _("opcode not supported on this processor: %s (%s)"),
8507 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8508 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8511 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8512 Return true if a definite match or failure was found, storing any match
8513 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8514 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8515 tried and failed to match under normal conditions and now want to try a
8516 more relaxed match. */
8519 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8520 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8521 int opcode_extra
, bfd_boolean lax_match
)
8523 const struct mips_opcode
*opcode
;
8524 const struct mips_opcode
*invalid_delay_slot
;
8525 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8527 /* Search for a match, ignoring alternatives that don't satisfy the
8528 current ISA or forced_length. */
8529 invalid_delay_slot
= 0;
8530 seen_valid_for_isa
= FALSE
;
8531 seen_valid_for_size
= FALSE
;
8535 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8536 if (is_opcode_valid (opcode
))
8538 seen_valid_for_isa
= TRUE
;
8539 if (is_size_valid (opcode
))
8541 bfd_boolean delay_slot_ok
;
8543 seen_valid_for_size
= TRUE
;
8544 delay_slot_ok
= is_delay_slot_valid (opcode
);
8545 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8546 lax_match
, delay_slot_ok
))
8550 if (!invalid_delay_slot
)
8551 invalid_delay_slot
= opcode
;
8560 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8562 /* If the only matches we found had the wrong length for the delay slot,
8563 pick the first such match. We'll issue an appropriate warning later. */
8564 if (invalid_delay_slot
)
8566 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8572 /* Handle the case where we didn't try to match an instruction because
8573 all the alternatives were incompatible with the current ISA. */
8574 if (!seen_valid_for_isa
)
8576 match_invalid_for_isa ();
8580 /* Handle the case where we didn't try to match an instruction because
8581 all the alternatives were of the wrong size. */
8582 if (!seen_valid_for_size
)
8584 if (mips_opts
.insn32
)
8585 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8588 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8589 8 * forced_insn_length
);
8596 /* Like match_insns, but for MIPS16. */
8599 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8600 struct mips_operand_token
*tokens
)
8602 const struct mips_opcode
*opcode
;
8603 bfd_boolean seen_valid_for_isa
;
8604 bfd_boolean seen_valid_for_size
;
8606 /* Search for a match, ignoring alternatives that don't satisfy the
8607 current ISA. There are no separate entries for extended forms so
8608 we deal with forced_length later. */
8609 seen_valid_for_isa
= FALSE
;
8610 seen_valid_for_size
= FALSE
;
8614 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8615 if (is_opcode_valid_16 (opcode
))
8617 seen_valid_for_isa
= TRUE
;
8618 if (is_size_valid_16 (opcode
))
8620 seen_valid_for_size
= TRUE
;
8621 if (match_mips16_insn (insn
, opcode
, tokens
))
8627 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8628 && strcmp (opcode
->name
, first
->name
) == 0);
8630 /* Handle the case where we didn't try to match an instruction because
8631 all the alternatives were incompatible with the current ISA. */
8632 if (!seen_valid_for_isa
)
8634 match_invalid_for_isa ();
8638 /* Handle the case where we didn't try to match an instruction because
8639 all the alternatives were of the wrong size. */
8640 if (!seen_valid_for_size
)
8642 if (forced_insn_length
== 2)
8644 (0, _("unrecognized unextended version of MIPS16 opcode"));
8647 (0, _("unrecognized extended version of MIPS16 opcode"));
8654 /* Set up global variables for the start of a new macro. */
8659 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8660 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8661 sizeof (mips_macro_warning
.first_insn_sizes
));
8662 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8663 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8664 && delayed_branch_p (&history
[0]));
8666 && history
[0].frag
->fr_type
== rs_machine_dependent
8667 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8668 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8669 mips_macro_warning
.delay_slot_length
= 0;
8671 switch (history
[0].insn_mo
->pinfo2
8672 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8674 case INSN2_BRANCH_DELAY_32BIT
:
8675 mips_macro_warning
.delay_slot_length
= 4;
8677 case INSN2_BRANCH_DELAY_16BIT
:
8678 mips_macro_warning
.delay_slot_length
= 2;
8681 mips_macro_warning
.delay_slot_length
= 0;
8684 mips_macro_warning
.first_frag
= NULL
;
8687 /* Given that a macro is longer than one instruction or of the wrong size,
8688 return the appropriate warning for it. Return null if no warning is
8689 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8690 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8691 and RELAX_NOMACRO. */
8694 macro_warning (relax_substateT subtype
)
8696 if (subtype
& RELAX_DELAY_SLOT
)
8697 return _("macro instruction expanded into multiple instructions"
8698 " in a branch delay slot");
8699 else if (subtype
& RELAX_NOMACRO
)
8700 return _("macro instruction expanded into multiple instructions");
8701 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8702 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8703 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8704 ? _("macro instruction expanded into a wrong size instruction"
8705 " in a 16-bit branch delay slot")
8706 : _("macro instruction expanded into a wrong size instruction"
8707 " in a 32-bit branch delay slot"));
8712 /* Finish up a macro. Emit warnings as appropriate. */
8717 /* Relaxation warning flags. */
8718 relax_substateT subtype
= 0;
8720 /* Check delay slot size requirements. */
8721 if (mips_macro_warning
.delay_slot_length
== 2)
8722 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8723 if (mips_macro_warning
.delay_slot_length
!= 0)
8725 if (mips_macro_warning
.delay_slot_length
8726 != mips_macro_warning
.first_insn_sizes
[0])
8727 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8728 if (mips_macro_warning
.delay_slot_length
8729 != mips_macro_warning
.first_insn_sizes
[1])
8730 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8733 /* Check instruction count requirements. */
8734 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8736 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8737 subtype
|= RELAX_SECOND_LONGER
;
8738 if (mips_opts
.warn_about_macros
)
8739 subtype
|= RELAX_NOMACRO
;
8740 if (mips_macro_warning
.delay_slot_p
)
8741 subtype
|= RELAX_DELAY_SLOT
;
8744 /* If both alternatives fail to fill a delay slot correctly,
8745 emit the warning now. */
8746 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8747 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8752 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8753 | RELAX_DELAY_SLOT_SIZE_FIRST
8754 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8755 msg
= macro_warning (s
);
8757 as_warn ("%s", msg
);
8761 /* If both implementations are longer than 1 instruction, then emit the
8763 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8768 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8769 msg
= macro_warning (s
);
8771 as_warn ("%s", msg
);
8775 /* If any flags still set, then one implementation might need a warning
8776 and the other either will need one of a different kind or none at all.
8777 Pass any remaining flags over to relaxation. */
8778 if (mips_macro_warning
.first_frag
!= NULL
)
8779 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8782 /* Instruction operand formats used in macros that vary between
8783 standard MIPS and microMIPS code. */
8785 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8786 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8787 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8788 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8789 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8790 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8791 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8792 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8794 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8795 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8796 : cop12_fmt[mips_opts.micromips])
8797 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8798 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8799 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8800 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8801 : mem12_fmt[mips_opts.micromips])
8802 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8803 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8804 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8806 /* Read a macro's relocation codes from *ARGS and store them in *R.
8807 The first argument in *ARGS will be either the code for a single
8808 relocation or -1 followed by the three codes that make up a
8809 composite relocation. */
8812 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8816 next
= va_arg (*args
, int);
8818 r
[0] = (bfd_reloc_code_real_type
) next
;
8821 for (i
= 0; i
< 3; i
++)
8822 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8823 /* This function is only used for 16-bit relocation fields.
8824 To make the macro code simpler, treat an unrelocated value
8825 in the same way as BFD_RELOC_LO16. */
8826 if (r
[0] == BFD_RELOC_UNUSED
)
8827 r
[0] = BFD_RELOC_LO16
;
8831 /* Build an instruction created by a macro expansion. This is passed
8832 a pointer to the count of instructions created so far, an
8833 expression, the name of the instruction to build, an operand format
8834 string, and corresponding arguments. */
8837 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8839 const struct mips_opcode
*mo
= NULL
;
8840 bfd_reloc_code_real_type r
[3];
8841 const struct mips_opcode
*amo
;
8842 const struct mips_operand
*operand
;
8843 struct hash_control
*hash
;
8844 struct mips_cl_insn insn
;
8848 va_start (args
, fmt
);
8850 if (mips_opts
.mips16
)
8852 mips16_macro_build (ep
, name
, fmt
, &args
);
8857 r
[0] = BFD_RELOC_UNUSED
;
8858 r
[1] = BFD_RELOC_UNUSED
;
8859 r
[2] = BFD_RELOC_UNUSED
;
8860 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8861 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8863 gas_assert (strcmp (name
, amo
->name
) == 0);
8867 /* Search until we get a match for NAME. It is assumed here that
8868 macros will never generate MDMX, MIPS-3D, or MT instructions.
8869 We try to match an instruction that fulfills the branch delay
8870 slot instruction length requirement (if any) of the previous
8871 instruction. While doing this we record the first instruction
8872 seen that matches all the other conditions and use it anyway
8873 if the requirement cannot be met; we will issue an appropriate
8874 warning later on. */
8875 if (strcmp (fmt
, amo
->args
) == 0
8876 && amo
->pinfo
!= INSN_MACRO
8877 && is_opcode_valid (amo
)
8878 && is_size_valid (amo
))
8880 if (is_delay_slot_valid (amo
))
8890 gas_assert (amo
->name
);
8892 while (strcmp (name
, amo
->name
) == 0);
8895 create_insn (&insn
, mo
);
8908 macro_read_relocs (&args
, r
);
8909 gas_assert (*r
== BFD_RELOC_GPREL16
8910 || *r
== BFD_RELOC_MIPS_HIGHER
8911 || *r
== BFD_RELOC_HI16_S
8912 || *r
== BFD_RELOC_LO16
8913 || *r
== BFD_RELOC_MIPS_GOT_OFST
8914 || (mips_opts
.micromips
8915 && (*r
== BFD_RELOC_16
8916 || *r
== BFD_RELOC_MIPS_GOT16
8917 || *r
== BFD_RELOC_MIPS_CALL16
8918 || *r
== BFD_RELOC_MIPS_GOT_HI16
8919 || *r
== BFD_RELOC_MIPS_GOT_LO16
8920 || *r
== BFD_RELOC_MIPS_CALL_HI16
8921 || *r
== BFD_RELOC_MIPS_CALL_LO16
8922 || *r
== BFD_RELOC_MIPS_SUB
8923 || *r
== BFD_RELOC_MIPS_GOT_PAGE
8924 || *r
== BFD_RELOC_MIPS_HIGHEST
8925 || *r
== BFD_RELOC_MIPS_GOT_DISP
8926 || *r
== BFD_RELOC_MIPS_TLS_GD
8927 || *r
== BFD_RELOC_MIPS_TLS_LDM
8928 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
8929 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
8930 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
8931 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
8932 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
8936 macro_read_relocs (&args
, r
);
8940 macro_read_relocs (&args
, r
);
8941 gas_assert (ep
!= NULL
8942 && (ep
->X_op
== O_constant
8943 || (ep
->X_op
== O_symbol
8944 && (*r
== BFD_RELOC_MIPS_HIGHEST
8945 || *r
== BFD_RELOC_HI16_S
8946 || *r
== BFD_RELOC_HI16
8947 || *r
== BFD_RELOC_GPREL16
8948 || *r
== BFD_RELOC_MIPS_GOT_HI16
8949 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8953 gas_assert (ep
!= NULL
);
8956 * This allows macro() to pass an immediate expression for
8957 * creating short branches without creating a symbol.
8959 * We don't allow branch relaxation for these branches, as
8960 * they should only appear in ".set nomacro" anyway.
8962 if (ep
->X_op
== O_constant
)
8964 /* For microMIPS we always use relocations for branches.
8965 So we should not resolve immediate values. */
8966 gas_assert (!mips_opts
.micromips
);
8968 if ((ep
->X_add_number
& 3) != 0)
8969 as_bad (_("branch to misaligned address (0x%lx)"),
8970 (unsigned long) ep
->X_add_number
);
8971 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8972 as_bad (_("branch address range overflow (0x%lx)"),
8973 (unsigned long) ep
->X_add_number
);
8974 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8978 *r
= BFD_RELOC_16_PCREL_S2
;
8982 gas_assert (ep
!= NULL
);
8983 *r
= BFD_RELOC_MIPS_JMP
;
8987 operand
= (mips_opts
.micromips
8988 ? decode_micromips_operand (fmt
)
8989 : decode_mips_operand (fmt
));
8993 uval
= va_arg (args
, int);
8994 if (operand
->type
== OP_CLO_CLZ_DEST
)
8995 uval
|= (uval
<< 5);
8996 insn_insert_operand (&insn
, operand
, uval
);
8998 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9004 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9006 append_insn (&insn
, ep
, r
, TRUE
);
9010 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9013 struct mips_opcode
*mo
;
9014 struct mips_cl_insn insn
;
9015 const struct mips_operand
*operand
;
9016 bfd_reloc_code_real_type r
[3]
9017 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9019 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9021 gas_assert (strcmp (name
, mo
->name
) == 0);
9023 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9026 gas_assert (mo
->name
);
9027 gas_assert (strcmp (name
, mo
->name
) == 0);
9030 create_insn (&insn
, mo
);
9067 gas_assert (ep
!= NULL
);
9069 if (ep
->X_op
!= O_constant
)
9070 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9071 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9073 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9075 *r
= BFD_RELOC_UNUSED
;
9081 operand
= decode_mips16_operand (c
, FALSE
);
9085 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9090 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9092 append_insn (&insn
, ep
, r
, TRUE
);
9096 * Generate a "jalr" instruction with a relocation hint to the called
9097 * function. This occurs in NewABI PIC code.
9100 macro_build_jalr (expressionS
*ep
, int cprestore
)
9102 static const bfd_reloc_code_real_type jalr_relocs
[2]
9103 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9104 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9108 if (MIPS_JALR_HINT_P (ep
))
9113 if (mips_opts
.micromips
)
9115 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9116 ? "jalr" : "jalrs");
9117 if (MIPS_JALR_HINT_P (ep
)
9119 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9120 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9122 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9125 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9126 if (MIPS_JALR_HINT_P (ep
))
9127 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9131 * Generate a "lui" instruction.
9134 macro_build_lui (expressionS
*ep
, int regnum
)
9136 gas_assert (! mips_opts
.mips16
);
9138 if (ep
->X_op
!= O_constant
)
9140 gas_assert (ep
->X_op
== O_symbol
);
9141 /* _gp_disp is a special case, used from s_cpload.
9142 __gnu_local_gp is used if mips_no_shared. */
9143 gas_assert (mips_pic
== NO_PIC
9145 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9146 || (! mips_in_shared
9147 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9148 "__gnu_local_gp") == 0));
9151 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9154 /* Generate a sequence of instructions to do a load or store from a constant
9155 offset off of a base register (breg) into/from a target register (treg),
9156 using AT if necessary. */
9158 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9159 int treg
, int breg
, int dbl
)
9161 gas_assert (ep
->X_op
== O_constant
);
9163 /* Sign-extending 32-bit constants makes their handling easier. */
9165 normalize_constant_expr (ep
);
9167 /* Right now, this routine can only handle signed 32-bit constants. */
9168 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9169 as_warn (_("operand overflow"));
9171 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9173 /* Signed 16-bit offset will fit in the op. Easy! */
9174 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9178 /* 32-bit offset, need multiple instructions and AT, like:
9179 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9180 addu $tempreg,$tempreg,$breg
9181 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9182 to handle the complete offset. */
9183 macro_build_lui (ep
, AT
);
9184 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9185 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9188 as_bad (_("macro used $at after \".set noat\""));
9193 * Generates code to set the $at register to true (one)
9194 * if reg is less than the immediate expression.
9197 set_at (int reg
, int unsignedp
)
9199 if (imm_expr
.X_add_number
>= -0x8000
9200 && imm_expr
.X_add_number
< 0x8000)
9201 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9202 AT
, reg
, BFD_RELOC_LO16
);
9205 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9206 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9210 /* Count the leading zeroes by performing a binary chop. This is a
9211 bulky bit of source, but performance is a LOT better for the
9212 majority of values than a simple loop to count the bits:
9213 for (lcnt = 0; (lcnt < 32); lcnt++)
9214 if ((v) & (1 << (31 - lcnt)))
9216 However it is not code size friendly, and the gain will drop a bit
9217 on certain cached systems.
9219 #define COUNT_TOP_ZEROES(v) \
9220 (((v) & ~0xffff) == 0 \
9221 ? ((v) & ~0xff) == 0 \
9222 ? ((v) & ~0xf) == 0 \
9223 ? ((v) & ~0x3) == 0 \
9224 ? ((v) & ~0x1) == 0 \
9229 : ((v) & ~0x7) == 0 \
9232 : ((v) & ~0x3f) == 0 \
9233 ? ((v) & ~0x1f) == 0 \
9236 : ((v) & ~0x7f) == 0 \
9239 : ((v) & ~0xfff) == 0 \
9240 ? ((v) & ~0x3ff) == 0 \
9241 ? ((v) & ~0x1ff) == 0 \
9244 : ((v) & ~0x7ff) == 0 \
9247 : ((v) & ~0x3fff) == 0 \
9248 ? ((v) & ~0x1fff) == 0 \
9251 : ((v) & ~0x7fff) == 0 \
9254 : ((v) & ~0xffffff) == 0 \
9255 ? ((v) & ~0xfffff) == 0 \
9256 ? ((v) & ~0x3ffff) == 0 \
9257 ? ((v) & ~0x1ffff) == 0 \
9260 : ((v) & ~0x7ffff) == 0 \
9263 : ((v) & ~0x3fffff) == 0 \
9264 ? ((v) & ~0x1fffff) == 0 \
9267 : ((v) & ~0x7fffff) == 0 \
9270 : ((v) & ~0xfffffff) == 0 \
9271 ? ((v) & ~0x3ffffff) == 0 \
9272 ? ((v) & ~0x1ffffff) == 0 \
9275 : ((v) & ~0x7ffffff) == 0 \
9278 : ((v) & ~0x3fffffff) == 0 \
9279 ? ((v) & ~0x1fffffff) == 0 \
9282 : ((v) & ~0x7fffffff) == 0 \
9287 * This routine generates the least number of instructions necessary to load
9288 * an absolute expression value into a register.
9291 load_register (int reg
, expressionS
*ep
, int dbl
)
9294 expressionS hi32
, lo32
;
9296 if (ep
->X_op
!= O_big
)
9298 gas_assert (ep
->X_op
== O_constant
);
9300 /* Sign-extending 32-bit constants makes their handling easier. */
9302 normalize_constant_expr (ep
);
9304 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9306 /* We can handle 16 bit signed values with an addiu to
9307 $zero. No need to ever use daddiu here, since $zero and
9308 the result are always correct in 32 bit mode. */
9309 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9312 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9314 /* We can handle 16 bit unsigned values with an ori to
9316 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9319 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9321 /* 32 bit values require an lui. */
9322 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9323 if ((ep
->X_add_number
& 0xffff) != 0)
9324 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9329 /* The value is larger than 32 bits. */
9331 if (!dbl
|| GPR_SIZE
== 32)
9335 sprintf_vma (value
, ep
->X_add_number
);
9336 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9337 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9341 if (ep
->X_op
!= O_big
)
9344 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9345 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9346 hi32
.X_add_number
&= 0xffffffff;
9348 lo32
.X_add_number
&= 0xffffffff;
9352 gas_assert (ep
->X_add_number
> 2);
9353 if (ep
->X_add_number
== 3)
9354 generic_bignum
[3] = 0;
9355 else if (ep
->X_add_number
> 4)
9356 as_bad (_("number larger than 64 bits"));
9357 lo32
.X_op
= O_constant
;
9358 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9359 hi32
.X_op
= O_constant
;
9360 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9363 if (hi32
.X_add_number
== 0)
9368 unsigned long hi
, lo
;
9370 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9372 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9374 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9377 if (lo32
.X_add_number
& 0x80000000)
9379 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9380 if (lo32
.X_add_number
& 0xffff)
9381 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9386 /* Check for 16bit shifted constant. We know that hi32 is
9387 non-zero, so start the mask on the first bit of the hi32
9392 unsigned long himask
, lomask
;
9396 himask
= 0xffff >> (32 - shift
);
9397 lomask
= (0xffff << shift
) & 0xffffffff;
9401 himask
= 0xffff << (shift
- 32);
9404 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9405 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9409 tmp
.X_op
= O_constant
;
9411 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9412 | (lo32
.X_add_number
>> shift
));
9414 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9415 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9416 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9417 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9422 while (shift
<= (64 - 16));
9424 /* Find the bit number of the lowest one bit, and store the
9425 shifted value in hi/lo. */
9426 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9427 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9431 while ((lo
& 1) == 0)
9436 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9442 while ((hi
& 1) == 0)
9451 /* Optimize if the shifted value is a (power of 2) - 1. */
9452 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9453 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9455 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9460 /* This instruction will set the register to be all
9462 tmp
.X_op
= O_constant
;
9463 tmp
.X_add_number
= (offsetT
) -1;
9464 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9468 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9469 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9471 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9472 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9477 /* Sign extend hi32 before calling load_register, because we can
9478 generally get better code when we load a sign extended value. */
9479 if ((hi32
.X_add_number
& 0x80000000) != 0)
9480 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9481 load_register (reg
, &hi32
, 0);
9484 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9488 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9496 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9498 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9499 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9505 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9509 mid16
.X_add_number
>>= 16;
9510 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9511 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9514 if ((lo32
.X_add_number
& 0xffff) != 0)
9515 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9519 load_delay_nop (void)
9521 if (!gpr_interlocks
)
9522 macro_build (NULL
, "nop", "");
9525 /* Load an address into a register. */
9528 load_address (int reg
, expressionS
*ep
, int *used_at
)
9530 if (ep
->X_op
!= O_constant
9531 && ep
->X_op
!= O_symbol
)
9533 as_bad (_("expression too complex"));
9534 ep
->X_op
= O_constant
;
9537 if (ep
->X_op
== O_constant
)
9539 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9543 if (mips_pic
== NO_PIC
)
9545 /* If this is a reference to a GP relative symbol, we want
9546 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9548 lui $reg,<sym> (BFD_RELOC_HI16_S)
9549 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9550 If we have an addend, we always use the latter form.
9552 With 64bit address space and a usable $at we want
9553 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9554 lui $at,<sym> (BFD_RELOC_HI16_S)
9555 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9556 daddiu $at,<sym> (BFD_RELOC_LO16)
9560 If $at is already in use, we use a path which is suboptimal
9561 on superscalar processors.
9562 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9563 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9565 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9567 daddiu $reg,<sym> (BFD_RELOC_LO16)
9569 For GP relative symbols in 64bit address space we can use
9570 the same sequence as in 32bit address space. */
9571 if (HAVE_64BIT_SYMBOLS
)
9573 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9574 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9576 relax_start (ep
->X_add_symbol
);
9577 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9578 mips_gp_register
, BFD_RELOC_GPREL16
);
9582 if (*used_at
== 0 && mips_opts
.at
)
9584 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9585 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9586 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9587 BFD_RELOC_MIPS_HIGHER
);
9588 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9589 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9590 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9595 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9596 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9597 BFD_RELOC_MIPS_HIGHER
);
9598 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9599 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9600 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9601 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9604 if (mips_relax
.sequence
)
9609 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9610 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9612 relax_start (ep
->X_add_symbol
);
9613 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9614 mips_gp_register
, BFD_RELOC_GPREL16
);
9617 macro_build_lui (ep
, reg
);
9618 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9619 reg
, reg
, BFD_RELOC_LO16
);
9620 if (mips_relax
.sequence
)
9624 else if (!mips_big_got
)
9628 /* If this is a reference to an external symbol, we want
9629 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9631 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9633 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9634 If there is a constant, it must be added in after.
9636 If we have NewABI, we want
9637 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9638 unless we're referencing a global symbol with a non-zero
9639 offset, in which case cst must be added separately. */
9642 if (ep
->X_add_number
)
9644 ex
.X_add_number
= ep
->X_add_number
;
9645 ep
->X_add_number
= 0;
9646 relax_start (ep
->X_add_symbol
);
9647 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9648 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9649 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9650 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9651 ex
.X_op
= O_constant
;
9652 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9653 reg
, reg
, BFD_RELOC_LO16
);
9654 ep
->X_add_number
= ex
.X_add_number
;
9657 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9658 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9659 if (mips_relax
.sequence
)
9664 ex
.X_add_number
= ep
->X_add_number
;
9665 ep
->X_add_number
= 0;
9666 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9667 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9669 relax_start (ep
->X_add_symbol
);
9671 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9675 if (ex
.X_add_number
!= 0)
9677 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9678 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9679 ex
.X_op
= O_constant
;
9680 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9681 reg
, reg
, BFD_RELOC_LO16
);
9685 else if (mips_big_got
)
9689 /* This is the large GOT case. If this is a reference to an
9690 external symbol, we want
9691 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9693 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9695 Otherwise, for a reference to a local symbol in old ABI, we want
9696 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9698 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9699 If there is a constant, it must be added in after.
9701 In the NewABI, for local symbols, with or without offsets, we want:
9702 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9703 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9707 ex
.X_add_number
= ep
->X_add_number
;
9708 ep
->X_add_number
= 0;
9709 relax_start (ep
->X_add_symbol
);
9710 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9711 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9712 reg
, reg
, mips_gp_register
);
9713 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9714 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9715 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9716 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9717 else if (ex
.X_add_number
)
9719 ex
.X_op
= O_constant
;
9720 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9724 ep
->X_add_number
= ex
.X_add_number
;
9726 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9727 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9728 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9729 BFD_RELOC_MIPS_GOT_OFST
);
9734 ex
.X_add_number
= ep
->X_add_number
;
9735 ep
->X_add_number
= 0;
9736 relax_start (ep
->X_add_symbol
);
9737 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9738 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9739 reg
, reg
, mips_gp_register
);
9740 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9741 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9743 if (reg_needs_delay (mips_gp_register
))
9745 /* We need a nop before loading from $gp. This special
9746 check is required because the lui which starts the main
9747 instruction stream does not refer to $gp, and so will not
9748 insert the nop which may be required. */
9749 macro_build (NULL
, "nop", "");
9751 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9752 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9754 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9758 if (ex
.X_add_number
!= 0)
9760 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9761 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9762 ex
.X_op
= O_constant
;
9763 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9771 if (!mips_opts
.at
&& *used_at
== 1)
9772 as_bad (_("macro used $at after \".set noat\""));
9775 /* Move the contents of register SOURCE into register DEST. */
9778 move_register (int dest
, int source
)
9780 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9781 instruction specifically requires a 32-bit one. */
9782 if (mips_opts
.micromips
9783 && !mips_opts
.insn32
9784 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9785 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9787 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9790 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9791 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9792 The two alternatives are:
9794 Global symbol Local symbol
9795 ------------- ------------
9796 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9798 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9800 load_got_offset emits the first instruction and add_got_offset
9801 emits the second for a 16-bit offset or add_got_offset_hilo emits
9802 a sequence to add a 32-bit offset using a scratch register. */
9805 load_got_offset (int dest
, expressionS
*local
)
9810 global
.X_add_number
= 0;
9812 relax_start (local
->X_add_symbol
);
9813 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9814 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9816 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9817 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9822 add_got_offset (int dest
, expressionS
*local
)
9826 global
.X_op
= O_constant
;
9827 global
.X_op_symbol
= NULL
;
9828 global
.X_add_symbol
= NULL
;
9829 global
.X_add_number
= local
->X_add_number
;
9831 relax_start (local
->X_add_symbol
);
9832 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9833 dest
, dest
, BFD_RELOC_LO16
);
9835 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9840 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9843 int hold_mips_optimize
;
9845 global
.X_op
= O_constant
;
9846 global
.X_op_symbol
= NULL
;
9847 global
.X_add_symbol
= NULL
;
9848 global
.X_add_number
= local
->X_add_number
;
9850 relax_start (local
->X_add_symbol
);
9851 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9853 /* Set mips_optimize around the lui instruction to avoid
9854 inserting an unnecessary nop after the lw. */
9855 hold_mips_optimize
= mips_optimize
;
9857 macro_build_lui (&global
, tmp
);
9858 mips_optimize
= hold_mips_optimize
;
9859 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9862 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9865 /* Emit a sequence of instructions to emulate a branch likely operation.
9866 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9867 is its complementing branch with the original condition negated.
9868 CALL is set if the original branch specified the link operation.
9869 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9871 Code like this is produced in the noreorder mode:
9876 delay slot (executed only if branch taken)
9884 delay slot (executed only if branch taken)
9887 In the reorder mode the delay slot would be filled with a nop anyway,
9888 so code produced is simply:
9893 This function is used when producing code for the microMIPS ASE that
9894 does not implement branch likely instructions in hardware. */
9897 macro_build_branch_likely (const char *br
, const char *brneg
,
9898 int call
, expressionS
*ep
, const char *fmt
,
9899 unsigned int sreg
, unsigned int treg
)
9901 int noreorder
= mips_opts
.noreorder
;
9904 gas_assert (mips_opts
.micromips
);
9908 micromips_label_expr (&expr1
);
9909 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9910 macro_build (NULL
, "nop", "");
9911 macro_build (ep
, call
? "bal" : "b", "p");
9913 /* Set to true so that append_insn adds a label. */
9914 emit_branch_likely_macro
= TRUE
;
9918 macro_build (ep
, br
, fmt
, sreg
, treg
);
9919 macro_build (NULL
, "nop", "");
9924 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9925 the condition code tested. EP specifies the branch target. */
9928 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9955 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9958 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9959 the register tested. EP specifies the branch target. */
9962 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9964 const char *brneg
= NULL
;
9974 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9978 gas_assert (mips_opts
.micromips
);
9979 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9987 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9994 br
= mips_opts
.micromips
? "blez" : "blezl";
10001 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10005 gas_assert (mips_opts
.micromips
);
10006 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10013 if (mips_opts
.micromips
&& brneg
)
10014 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10016 macro_build (ep
, br
, "s,p", sreg
);
10019 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10020 TREG as the registers tested. EP specifies the branch target. */
10023 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10024 unsigned int sreg
, unsigned int treg
)
10026 const char *brneg
= NULL
;
10027 const int call
= 0;
10038 br
= mips_opts
.micromips
? "beq" : "beql";
10047 br
= mips_opts
.micromips
? "bne" : "bnel";
10053 if (mips_opts
.micromips
&& brneg
)
10054 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10056 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10059 /* Return the high part that should be loaded in order to make the low
10060 part of VALUE accessible using an offset of OFFBITS bits. */
10063 offset_high_part (offsetT value
, unsigned int offbits
)
10070 bias
= 1 << (offbits
- 1);
10071 low_mask
= bias
* 2 - 1;
10072 return (value
+ bias
) & ~low_mask
;
10075 /* Return true if the value stored in offset_expr and offset_reloc
10076 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10077 amount that the caller wants to add without inducing overflow
10078 and ALIGN is the known alignment of the value in bytes. */
10081 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10085 /* Accept any relocation operator if overflow isn't a concern. */
10086 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10089 /* These relocations are guaranteed not to overflow in correct links. */
10090 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10091 || gprel16_reloc_p (*offset_reloc
))
10094 if (offset_expr
.X_op
== O_constant
10095 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10096 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10103 * This routine implements the seemingly endless macro or synthesized
10104 * instructions and addressing modes in the mips assembly language. Many
10105 * of these macros are simple and are similar to each other. These could
10106 * probably be handled by some kind of table or grammar approach instead of
10107 * this verbose method. Others are not simple macros but are more like
10108 * optimizing code generation.
10109 * One interesting optimization is when several store macros appear
10110 * consecutively that would load AT with the upper half of the same address.
10111 * The ensuing load upper instructions are omitted. This implies some kind
10112 * of global optimization. We currently only optimize within a single macro.
10113 * For many of the load and store macros if the address is specified as a
10114 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10115 * first load register 'at' with zero and use it as the base register. The
10116 * mips assembler simply uses register $zero. Just one tiny optimization
10120 macro (struct mips_cl_insn
*ip
, char *str
)
10122 const struct mips_operand_array
*operands
;
10123 unsigned int breg
, i
;
10124 unsigned int tempreg
;
10127 expressionS label_expr
;
10142 bfd_boolean large_offset
;
10144 int hold_mips_optimize
;
10145 unsigned int align
;
10146 unsigned int op
[MAX_OPERANDS
];
10148 gas_assert (! mips_opts
.mips16
);
10150 operands
= insn_operands (ip
);
10151 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10152 if (operands
->operand
[i
])
10153 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10157 mask
= ip
->insn_mo
->mask
;
10159 label_expr
.X_op
= O_constant
;
10160 label_expr
.X_op_symbol
= NULL
;
10161 label_expr
.X_add_symbol
= NULL
;
10162 label_expr
.X_add_number
= 0;
10164 expr1
.X_op
= O_constant
;
10165 expr1
.X_op_symbol
= NULL
;
10166 expr1
.X_add_symbol
= NULL
;
10167 expr1
.X_add_number
= 1;
10174 /* Fall through. */
10182 start_noreorder ();
10184 if (mips_opts
.micromips
)
10185 micromips_label_expr (&label_expr
);
10187 label_expr
.X_add_number
= 8;
10188 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10189 if (op
[0] == op
[1])
10190 macro_build (NULL
, "nop", "");
10192 move_register (op
[0], op
[1]);
10193 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10194 if (mips_opts
.micromips
)
10195 micromips_add_label ();
10212 if (!mips_opts
.micromips
)
10214 if (imm_expr
.X_add_number
>= -0x200
10215 && imm_expr
.X_add_number
< 0x200)
10217 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10218 (int) imm_expr
.X_add_number
);
10227 if (imm_expr
.X_add_number
>= -0x8000
10228 && imm_expr
.X_add_number
< 0x8000)
10230 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10235 load_register (AT
, &imm_expr
, dbl
);
10236 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10255 if (imm_expr
.X_add_number
>= 0
10256 && imm_expr
.X_add_number
< 0x10000)
10258 if (mask
!= M_NOR_I
)
10259 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10262 macro_build (&imm_expr
, "ori", "t,r,i",
10263 op
[0], op
[1], BFD_RELOC_LO16
);
10264 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10270 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10271 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10275 switch (imm_expr
.X_add_number
)
10278 macro_build (NULL
, "nop", "");
10281 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10285 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10286 (int) imm_expr
.X_add_number
);
10289 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10290 (unsigned long) imm_expr
.X_add_number
);
10299 gas_assert (mips_opts
.micromips
);
10300 macro_build_branch_ccl (mask
, &offset_expr
,
10301 EXTRACT_OPERAND (1, BCC
, *ip
));
10308 if (imm_expr
.X_add_number
== 0)
10314 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10316 /* Fall through. */
10319 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10324 /* Fall through. */
10327 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10328 else if (op
[0] == 0)
10329 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10333 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10334 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10335 &offset_expr
, AT
, ZERO
);
10345 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10350 /* Fall through. */
10352 /* Check for > max integer. */
10353 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10356 /* Result is always false. */
10358 macro_build (NULL
, "nop", "");
10360 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10363 ++imm_expr
.X_add_number
;
10367 if (mask
== M_BGEL_I
)
10369 if (imm_expr
.X_add_number
== 0)
10371 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10372 &offset_expr
, op
[0]);
10375 if (imm_expr
.X_add_number
== 1)
10377 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10378 &offset_expr
, op
[0]);
10381 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10384 /* result is always true */
10385 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10386 macro_build (&offset_expr
, "b", "p");
10391 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10392 &offset_expr
, AT
, ZERO
);
10397 /* Fall through. */
10401 else if (op
[0] == 0)
10402 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10403 &offset_expr
, ZERO
, op
[1]);
10407 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10408 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10409 &offset_expr
, AT
, ZERO
);
10415 /* Fall through. */
10419 && imm_expr
.X_add_number
== -1))
10421 ++imm_expr
.X_add_number
;
10425 if (mask
== M_BGEUL_I
)
10427 if (imm_expr
.X_add_number
== 0)
10429 else if (imm_expr
.X_add_number
== 1)
10430 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10431 &offset_expr
, op
[0], ZERO
);
10436 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10437 &offset_expr
, AT
, ZERO
);
10443 /* Fall through. */
10446 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10447 else if (op
[0] == 0)
10448 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10452 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10453 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10454 &offset_expr
, AT
, ZERO
);
10460 /* Fall through. */
10463 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10464 &offset_expr
, op
[0], ZERO
);
10465 else if (op
[0] == 0)
10470 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10471 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10472 &offset_expr
, AT
, ZERO
);
10478 /* Fall through. */
10481 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10482 else if (op
[0] == 0)
10483 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10487 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10488 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10489 &offset_expr
, AT
, ZERO
);
10495 /* Fall through. */
10497 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10499 ++imm_expr
.X_add_number
;
10503 if (mask
== M_BLTL_I
)
10505 if (imm_expr
.X_add_number
== 0)
10506 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10507 else if (imm_expr
.X_add_number
== 1)
10508 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10513 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10514 &offset_expr
, AT
, ZERO
);
10520 /* Fall through. */
10523 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10524 &offset_expr
, op
[0], ZERO
);
10525 else if (op
[0] == 0)
10530 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10531 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10532 &offset_expr
, AT
, ZERO
);
10538 /* Fall through. */
10542 && imm_expr
.X_add_number
== -1))
10544 ++imm_expr
.X_add_number
;
10548 if (mask
== M_BLTUL_I
)
10550 if (imm_expr
.X_add_number
== 0)
10552 else if (imm_expr
.X_add_number
== 1)
10553 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10554 &offset_expr
, op
[0], ZERO
);
10559 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10560 &offset_expr
, AT
, ZERO
);
10566 /* Fall through. */
10569 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10570 else if (op
[0] == 0)
10571 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10575 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10576 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10577 &offset_expr
, AT
, ZERO
);
10583 /* Fall through. */
10587 else if (op
[0] == 0)
10588 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10589 &offset_expr
, ZERO
, op
[1]);
10593 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10594 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10595 &offset_expr
, AT
, ZERO
);
10601 /* Fall through. */
10607 /* Fall through. */
10613 as_warn (_("divide by zero"));
10615 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10617 macro_build (NULL
, "break", BRK_FMT
, 7);
10621 start_noreorder ();
10624 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10625 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10629 if (mips_opts
.micromips
)
10630 micromips_label_expr (&label_expr
);
10632 label_expr
.X_add_number
= 8;
10633 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10634 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10635 macro_build (NULL
, "break", BRK_FMT
, 7);
10636 if (mips_opts
.micromips
)
10637 micromips_add_label ();
10639 expr1
.X_add_number
= -1;
10641 load_register (AT
, &expr1
, dbl
);
10642 if (mips_opts
.micromips
)
10643 micromips_label_expr (&label_expr
);
10645 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10646 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10649 expr1
.X_add_number
= 1;
10650 load_register (AT
, &expr1
, dbl
);
10651 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10655 expr1
.X_add_number
= 0x80000000;
10656 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10660 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10661 /* We want to close the noreorder block as soon as possible, so
10662 that later insns are available for delay slot filling. */
10667 if (mips_opts
.micromips
)
10668 micromips_label_expr (&label_expr
);
10670 label_expr
.X_add_number
= 8;
10671 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10672 macro_build (NULL
, "nop", "");
10674 /* We want to close the noreorder block as soon as possible, so
10675 that later insns are available for delay slot filling. */
10678 macro_build (NULL
, "break", BRK_FMT
, 6);
10680 if (mips_opts
.micromips
)
10681 micromips_add_label ();
10682 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10721 if (imm_expr
.X_add_number
== 0)
10723 as_warn (_("divide by zero"));
10725 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10727 macro_build (NULL
, "break", BRK_FMT
, 7);
10730 if (imm_expr
.X_add_number
== 1)
10732 if (strcmp (s2
, "mflo") == 0)
10733 move_register (op
[0], op
[1]);
10735 move_register (op
[0], ZERO
);
10738 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10740 if (strcmp (s2
, "mflo") == 0)
10741 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10743 move_register (op
[0], ZERO
);
10748 load_register (AT
, &imm_expr
, dbl
);
10749 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10750 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10769 start_noreorder ();
10772 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10773 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10774 /* We want to close the noreorder block as soon as possible, so
10775 that later insns are available for delay slot filling. */
10780 if (mips_opts
.micromips
)
10781 micromips_label_expr (&label_expr
);
10783 label_expr
.X_add_number
= 8;
10784 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10785 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10787 /* We want to close the noreorder block as soon as possible, so
10788 that later insns are available for delay slot filling. */
10790 macro_build (NULL
, "break", BRK_FMT
, 7);
10791 if (mips_opts
.micromips
)
10792 micromips_add_label ();
10794 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10799 /* Fall through. */
10805 /* Fall through. */
10808 /* Load the address of a symbol into a register. If breg is not
10809 zero, we then add a base register to it. */
10812 if (dbl
&& GPR_SIZE
== 32)
10813 as_warn (_("dla used to load 32-bit register; recommend using la "
10816 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10817 as_warn (_("la used to load 64-bit address; recommend using dla "
10820 if (small_offset_p (0, align
, 16))
10822 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10823 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10827 if (mips_opts
.at
&& (op
[0] == breg
))
10835 if (offset_expr
.X_op
!= O_symbol
10836 && offset_expr
.X_op
!= O_constant
)
10838 as_bad (_("expression too complex"));
10839 offset_expr
.X_op
= O_constant
;
10842 if (offset_expr
.X_op
== O_constant
)
10843 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10844 else if (mips_pic
== NO_PIC
)
10846 /* If this is a reference to a GP relative symbol, we want
10847 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10849 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10850 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10851 If we have a constant, we need two instructions anyhow,
10852 so we may as well always use the latter form.
10854 With 64bit address space and a usable $at we want
10855 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10856 lui $at,<sym> (BFD_RELOC_HI16_S)
10857 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10858 daddiu $at,<sym> (BFD_RELOC_LO16)
10860 daddu $tempreg,$tempreg,$at
10862 If $at is already in use, we use a path which is suboptimal
10863 on superscalar processors.
10864 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10865 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10867 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10869 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10871 For GP relative symbols in 64bit address space we can use
10872 the same sequence as in 32bit address space. */
10873 if (HAVE_64BIT_SYMBOLS
)
10875 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10876 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10878 relax_start (offset_expr
.X_add_symbol
);
10879 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10880 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10884 if (used_at
== 0 && mips_opts
.at
)
10886 macro_build (&offset_expr
, "lui", LUI_FMT
,
10887 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10888 macro_build (&offset_expr
, "lui", LUI_FMT
,
10889 AT
, BFD_RELOC_HI16_S
);
10890 macro_build (&offset_expr
, "daddiu", "t,r,j",
10891 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10892 macro_build (&offset_expr
, "daddiu", "t,r,j",
10893 AT
, AT
, BFD_RELOC_LO16
);
10894 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10895 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10900 macro_build (&offset_expr
, "lui", LUI_FMT
,
10901 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10902 macro_build (&offset_expr
, "daddiu", "t,r,j",
10903 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10904 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10905 macro_build (&offset_expr
, "daddiu", "t,r,j",
10906 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10907 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10908 macro_build (&offset_expr
, "daddiu", "t,r,j",
10909 tempreg
, tempreg
, BFD_RELOC_LO16
);
10912 if (mips_relax
.sequence
)
10917 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10918 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10920 relax_start (offset_expr
.X_add_symbol
);
10921 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10922 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10925 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10926 as_bad (_("offset too large"));
10927 macro_build_lui (&offset_expr
, tempreg
);
10928 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10929 tempreg
, tempreg
, BFD_RELOC_LO16
);
10930 if (mips_relax
.sequence
)
10934 else if (!mips_big_got
&& !HAVE_NEWABI
)
10936 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10938 /* If this is a reference to an external symbol, and there
10939 is no constant, we want
10940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10941 or for lca or if tempreg is PIC_CALL_REG
10942 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10943 For a local symbol, we want
10944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10946 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10948 If we have a small constant, and this is a reference to
10949 an external symbol, we want
10950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10952 addiu $tempreg,$tempreg,<constant>
10953 For a local symbol, we want the same instruction
10954 sequence, but we output a BFD_RELOC_LO16 reloc on the
10957 If we have a large constant, and this is a reference to
10958 an external symbol, we want
10959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10960 lui $at,<hiconstant>
10961 addiu $at,$at,<loconstant>
10962 addu $tempreg,$tempreg,$at
10963 For a local symbol, we want the same instruction
10964 sequence, but we output a BFD_RELOC_LO16 reloc on the
10968 if (offset_expr
.X_add_number
== 0)
10970 if (mips_pic
== SVR4_PIC
10972 && (call
|| tempreg
== PIC_CALL_REG
))
10973 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10975 relax_start (offset_expr
.X_add_symbol
);
10976 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10977 lw_reloc_type
, mips_gp_register
);
10980 /* We're going to put in an addu instruction using
10981 tempreg, so we may as well insert the nop right
10986 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10987 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10989 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10990 tempreg
, tempreg
, BFD_RELOC_LO16
);
10992 /* FIXME: If breg == 0, and the next instruction uses
10993 $tempreg, then if this variant case is used an extra
10994 nop will be generated. */
10996 else if (offset_expr
.X_add_number
>= -0x8000
10997 && offset_expr
.X_add_number
< 0x8000)
10999 load_got_offset (tempreg
, &offset_expr
);
11001 add_got_offset (tempreg
, &offset_expr
);
11005 expr1
.X_add_number
= offset_expr
.X_add_number
;
11006 offset_expr
.X_add_number
=
11007 SEXT_16BIT (offset_expr
.X_add_number
);
11008 load_got_offset (tempreg
, &offset_expr
);
11009 offset_expr
.X_add_number
= expr1
.X_add_number
;
11010 /* If we are going to add in a base register, and the
11011 target register and the base register are the same,
11012 then we are using AT as a temporary register. Since
11013 we want to load the constant into AT, we add our
11014 current AT (from the global offset table) and the
11015 register into the register now, and pretend we were
11016 not using a base register. */
11020 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11025 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11029 else if (!mips_big_got
&& HAVE_NEWABI
)
11031 int add_breg_early
= 0;
11033 /* If this is a reference to an external, and there is no
11034 constant, or local symbol (*), with or without a
11036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11037 or for lca or if tempreg is PIC_CALL_REG
11038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11040 If we have a small constant, and this is a reference to
11041 an external symbol, we want
11042 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11043 addiu $tempreg,$tempreg,<constant>
11045 If we have a large constant, and this is a reference to
11046 an external symbol, we want
11047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11048 lui $at,<hiconstant>
11049 addiu $at,$at,<loconstant>
11050 addu $tempreg,$tempreg,$at
11052 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11053 local symbols, even though it introduces an additional
11056 if (offset_expr
.X_add_number
)
11058 expr1
.X_add_number
= offset_expr
.X_add_number
;
11059 offset_expr
.X_add_number
= 0;
11061 relax_start (offset_expr
.X_add_symbol
);
11062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11063 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11065 if (expr1
.X_add_number
>= -0x8000
11066 && expr1
.X_add_number
< 0x8000)
11068 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11069 tempreg
, tempreg
, BFD_RELOC_LO16
);
11071 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11075 /* If we are going to add in a base register, and the
11076 target register and the base register are the same,
11077 then we are using AT as a temporary register. Since
11078 we want to load the constant into AT, we add our
11079 current AT (from the global offset table) and the
11080 register into the register now, and pretend we were
11081 not using a base register. */
11086 gas_assert (tempreg
== AT
);
11087 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11090 add_breg_early
= 1;
11093 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11100 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11103 offset_expr
.X_add_number
= expr1
.X_add_number
;
11105 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11106 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11107 if (add_breg_early
)
11109 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11110 op
[0], tempreg
, breg
);
11116 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11118 relax_start (offset_expr
.X_add_symbol
);
11119 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11120 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11122 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11123 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11129 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11132 else if (mips_big_got
&& !HAVE_NEWABI
)
11135 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11136 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11137 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11139 /* This is the large GOT case. If this is a reference to an
11140 external symbol, and there is no constant, we want
11141 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11142 addu $tempreg,$tempreg,$gp
11143 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11144 or for lca or if tempreg is PIC_CALL_REG
11145 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11146 addu $tempreg,$tempreg,$gp
11147 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11148 For a local symbol, we want
11149 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11151 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11153 If we have a small constant, and this is a reference to
11154 an external symbol, we want
11155 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11156 addu $tempreg,$tempreg,$gp
11157 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11159 addiu $tempreg,$tempreg,<constant>
11160 For a local symbol, we want
11161 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11163 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11165 If we have a large constant, and this is a reference to
11166 an external symbol, we want
11167 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11168 addu $tempreg,$tempreg,$gp
11169 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11170 lui $at,<hiconstant>
11171 addiu $at,$at,<loconstant>
11172 addu $tempreg,$tempreg,$at
11173 For a local symbol, we want
11174 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11175 lui $at,<hiconstant>
11176 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11177 addu $tempreg,$tempreg,$at
11180 expr1
.X_add_number
= offset_expr
.X_add_number
;
11181 offset_expr
.X_add_number
= 0;
11182 relax_start (offset_expr
.X_add_symbol
);
11183 gpdelay
= reg_needs_delay (mips_gp_register
);
11184 if (expr1
.X_add_number
== 0 && breg
== 0
11185 && (call
|| tempreg
== PIC_CALL_REG
))
11187 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11188 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11190 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11191 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11192 tempreg
, tempreg
, mips_gp_register
);
11193 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11194 tempreg
, lw_reloc_type
, tempreg
);
11195 if (expr1
.X_add_number
== 0)
11199 /* We're going to put in an addu instruction using
11200 tempreg, so we may as well insert the nop right
11205 else if (expr1
.X_add_number
>= -0x8000
11206 && expr1
.X_add_number
< 0x8000)
11209 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11210 tempreg
, tempreg
, BFD_RELOC_LO16
);
11216 /* If we are going to add in a base register, and the
11217 target register and the base register are the same,
11218 then we are using AT as a temporary register. Since
11219 we want to load the constant into AT, we add our
11220 current AT (from the global offset table) and the
11221 register into the register now, and pretend we were
11222 not using a base register. */
11227 gas_assert (tempreg
== AT
);
11229 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11234 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11235 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11239 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11244 /* This is needed because this instruction uses $gp, but
11245 the first instruction on the main stream does not. */
11246 macro_build (NULL
, "nop", "");
11249 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11250 local_reloc_type
, mips_gp_register
);
11251 if (expr1
.X_add_number
>= -0x8000
11252 && expr1
.X_add_number
< 0x8000)
11255 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11256 tempreg
, tempreg
, BFD_RELOC_LO16
);
11257 /* FIXME: If add_number is 0, and there was no base
11258 register, the external symbol case ended with a load,
11259 so if the symbol turns out to not be external, and
11260 the next instruction uses tempreg, an unnecessary nop
11261 will be inserted. */
11267 /* We must add in the base register now, as in the
11268 external symbol case. */
11269 gas_assert (tempreg
== AT
);
11271 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11274 /* We set breg to 0 because we have arranged to add
11275 it in in both cases. */
11279 macro_build_lui (&expr1
, AT
);
11280 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11281 AT
, AT
, BFD_RELOC_LO16
);
11282 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11283 tempreg
, tempreg
, AT
);
11288 else if (mips_big_got
&& HAVE_NEWABI
)
11290 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11291 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11292 int add_breg_early
= 0;
11294 /* This is the large GOT case. If this is a reference to an
11295 external symbol, and there is no constant, we want
11296 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11297 add $tempreg,$tempreg,$gp
11298 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11299 or for lca or if tempreg is PIC_CALL_REG
11300 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11301 add $tempreg,$tempreg,$gp
11302 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11304 If we have a small constant, and this is a reference to
11305 an external symbol, we want
11306 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11307 add $tempreg,$tempreg,$gp
11308 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11309 addi $tempreg,$tempreg,<constant>
11311 If we have a large constant, and this is a reference to
11312 an external symbol, we want
11313 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11314 addu $tempreg,$tempreg,$gp
11315 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11316 lui $at,<hiconstant>
11317 addi $at,$at,<loconstant>
11318 add $tempreg,$tempreg,$at
11320 If we have NewABI, and we know it's a local symbol, we want
11321 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11322 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11323 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11325 relax_start (offset_expr
.X_add_symbol
);
11327 expr1
.X_add_number
= offset_expr
.X_add_number
;
11328 offset_expr
.X_add_number
= 0;
11330 if (expr1
.X_add_number
== 0 && breg
== 0
11331 && (call
|| tempreg
== PIC_CALL_REG
))
11333 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11334 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11336 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11337 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11338 tempreg
, tempreg
, mips_gp_register
);
11339 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11340 tempreg
, lw_reloc_type
, tempreg
);
11342 if (expr1
.X_add_number
== 0)
11344 else if (expr1
.X_add_number
>= -0x8000
11345 && expr1
.X_add_number
< 0x8000)
11347 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11348 tempreg
, tempreg
, BFD_RELOC_LO16
);
11350 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11354 /* If we are going to add in a base register, and the
11355 target register and the base register are the same,
11356 then we are using AT as a temporary register. Since
11357 we want to load the constant into AT, we add our
11358 current AT (from the global offset table) and the
11359 register into the register now, and pretend we were
11360 not using a base register. */
11365 gas_assert (tempreg
== AT
);
11366 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11369 add_breg_early
= 1;
11372 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11373 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11378 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11381 offset_expr
.X_add_number
= expr1
.X_add_number
;
11382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11383 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11384 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11385 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11386 if (add_breg_early
)
11388 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11389 op
[0], tempreg
, breg
);
11399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11403 gas_assert (!mips_opts
.micromips
);
11404 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11408 gas_assert (!mips_opts
.micromips
);
11409 macro_build (NULL
, "c2", "C", 0x02);
11413 gas_assert (!mips_opts
.micromips
);
11414 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11418 gas_assert (!mips_opts
.micromips
);
11419 macro_build (NULL
, "c2", "C", 3);
11423 gas_assert (!mips_opts
.micromips
);
11424 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11428 /* The j instruction may not be used in PIC code, since it
11429 requires an absolute address. We convert it to a b
11431 if (mips_pic
== NO_PIC
)
11432 macro_build (&offset_expr
, "j", "a");
11434 macro_build (&offset_expr
, "b", "p");
11437 /* The jal instructions must be handled as macros because when
11438 generating PIC code they expand to multi-instruction
11439 sequences. Normally they are simple instructions. */
11443 /* Fall through. */
11445 gas_assert (mips_opts
.micromips
);
11446 if (mips_opts
.insn32
)
11448 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11456 /* Fall through. */
11459 if (mips_pic
== NO_PIC
)
11461 s
= jals
? "jalrs" : "jalr";
11462 if (mips_opts
.micromips
11463 && !mips_opts
.insn32
11465 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11466 macro_build (NULL
, s
, "mj", op
[1]);
11468 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11472 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11473 && mips_cprestore_offset
>= 0);
11475 if (op
[1] != PIC_CALL_REG
)
11476 as_warn (_("MIPS PIC call to register other than $25"));
11478 s
= ((mips_opts
.micromips
11479 && !mips_opts
.insn32
11480 && (!mips_opts
.noreorder
|| cprestore
))
11481 ? "jalrs" : "jalr");
11482 if (mips_opts
.micromips
11483 && !mips_opts
.insn32
11485 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11486 macro_build (NULL
, s
, "mj", op
[1]);
11488 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11489 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11491 if (mips_cprestore_offset
< 0)
11492 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11495 if (!mips_frame_reg_valid
)
11497 as_warn (_("no .frame pseudo-op used in PIC code"));
11498 /* Quiet this warning. */
11499 mips_frame_reg_valid
= 1;
11501 if (!mips_cprestore_valid
)
11503 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11504 /* Quiet this warning. */
11505 mips_cprestore_valid
= 1;
11507 if (mips_opts
.noreorder
)
11508 macro_build (NULL
, "nop", "");
11509 expr1
.X_add_number
= mips_cprestore_offset
;
11510 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11513 HAVE_64BIT_ADDRESSES
);
11521 gas_assert (mips_opts
.micromips
);
11522 if (mips_opts
.insn32
)
11524 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11528 /* Fall through. */
11530 if (mips_pic
== NO_PIC
)
11531 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11532 else if (mips_pic
== SVR4_PIC
)
11534 /* If this is a reference to an external symbol, and we are
11535 using a small GOT, we want
11536 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11540 lw $gp,cprestore($sp)
11541 The cprestore value is set using the .cprestore
11542 pseudo-op. If we are using a big GOT, we want
11543 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11545 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11549 lw $gp,cprestore($sp)
11550 If the symbol is not external, we want
11551 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11553 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11556 lw $gp,cprestore($sp)
11558 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11559 sequences above, minus nops, unless the symbol is local,
11560 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11566 relax_start (offset_expr
.X_add_symbol
);
11567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11568 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11571 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11572 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11578 relax_start (offset_expr
.X_add_symbol
);
11579 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11580 BFD_RELOC_MIPS_CALL_HI16
);
11581 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11582 PIC_CALL_REG
, mips_gp_register
);
11583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11584 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11587 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11588 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11590 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11591 PIC_CALL_REG
, PIC_CALL_REG
,
11592 BFD_RELOC_MIPS_GOT_OFST
);
11596 macro_build_jalr (&offset_expr
, 0);
11600 relax_start (offset_expr
.X_add_symbol
);
11603 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11604 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11613 gpdelay
= reg_needs_delay (mips_gp_register
);
11614 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11615 BFD_RELOC_MIPS_CALL_HI16
);
11616 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11617 PIC_CALL_REG
, mips_gp_register
);
11618 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11619 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11624 macro_build (NULL
, "nop", "");
11626 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11627 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11630 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11631 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11633 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11635 if (mips_cprestore_offset
< 0)
11636 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11639 if (!mips_frame_reg_valid
)
11641 as_warn (_("no .frame pseudo-op used in PIC code"));
11642 /* Quiet this warning. */
11643 mips_frame_reg_valid
= 1;
11645 if (!mips_cprestore_valid
)
11647 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11648 /* Quiet this warning. */
11649 mips_cprestore_valid
= 1;
11651 if (mips_opts
.noreorder
)
11652 macro_build (NULL
, "nop", "");
11653 expr1
.X_add_number
= mips_cprestore_offset
;
11654 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11657 HAVE_64BIT_ADDRESSES
);
11661 else if (mips_pic
== VXWORKS_PIC
)
11662 as_bad (_("non-PIC jump used in PIC library"));
11769 gas_assert (!mips_opts
.micromips
);
11772 /* Itbl support may require additional care here. */
11778 /* Itbl support may require additional care here. */
11784 offbits
= (mips_opts
.micromips
? 12
11785 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11787 /* Itbl support may require additional care here. */
11791 gas_assert (!mips_opts
.micromips
);
11794 /* Itbl support may require additional care here. */
11800 offbits
= (mips_opts
.micromips
? 12 : 16);
11805 offbits
= (mips_opts
.micromips
? 12 : 16);
11810 /* Itbl support may require additional care here. */
11816 offbits
= (mips_opts
.micromips
? 12
11817 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11819 /* Itbl support may require additional care here. */
11825 /* Itbl support may require additional care here. */
11831 /* Itbl support may require additional care here. */
11837 offbits
= (mips_opts
.micromips
? 12 : 16);
11842 offbits
= (mips_opts
.micromips
? 12 : 16);
11847 offbits
= (mips_opts
.micromips
? 12
11848 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11854 offbits
= (mips_opts
.micromips
? 12
11855 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11861 offbits
= (mips_opts
.micromips
? 12 : 16);
11864 gas_assert (mips_opts
.micromips
);
11871 gas_assert (mips_opts
.micromips
);
11878 gas_assert (mips_opts
.micromips
);
11884 gas_assert (mips_opts
.micromips
);
11891 /* We don't want to use $0 as tempreg. */
11892 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11895 tempreg
= op
[0] + lp
;
11911 gas_assert (!mips_opts
.micromips
);
11914 /* Itbl support may require additional care here. */
11920 /* Itbl support may require additional care here. */
11926 offbits
= (mips_opts
.micromips
? 12
11927 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11929 /* Itbl support may require additional care here. */
11933 gas_assert (!mips_opts
.micromips
);
11936 /* Itbl support may require additional care here. */
11942 offbits
= (mips_opts
.micromips
? 12 : 16);
11947 offbits
= (mips_opts
.micromips
? 12 : 16);
11952 offbits
= (mips_opts
.micromips
? 12
11953 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11959 offbits
= (mips_opts
.micromips
? 12
11960 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11965 fmt
= (mips_opts
.micromips
? "k,~(b)"
11966 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11968 offbits
= (mips_opts
.micromips
? 12
11969 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11979 fmt
= (mips_opts
.micromips
? "k,~(b)"
11980 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11982 offbits
= (mips_opts
.micromips
? 12
11983 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11995 /* Itbl support may require additional care here. */
12000 offbits
= (mips_opts
.micromips
? 12
12001 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12003 /* Itbl support may require additional care here. */
12009 /* Itbl support may require additional care here. */
12013 gas_assert (!mips_opts
.micromips
);
12016 /* Itbl support may require additional care here. */
12022 offbits
= (mips_opts
.micromips
? 12 : 16);
12027 offbits
= (mips_opts
.micromips
? 12 : 16);
12030 gas_assert (mips_opts
.micromips
);
12036 gas_assert (mips_opts
.micromips
);
12042 gas_assert (mips_opts
.micromips
);
12048 gas_assert (mips_opts
.micromips
);
12057 if (small_offset_p (0, align
, 16))
12059 /* The first case exists for M_LD_AB and M_SD_AB, which are
12060 macros for o32 but which should act like normal instructions
12063 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12064 offset_reloc
[1], offset_reloc
[2], breg
);
12065 else if (small_offset_p (0, align
, offbits
))
12068 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12070 macro_build (NULL
, s
, fmt
, op
[0],
12071 (int) offset_expr
.X_add_number
, breg
);
12077 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12078 tempreg
, breg
, -1, offset_reloc
[0],
12079 offset_reloc
[1], offset_reloc
[2]);
12081 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12083 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12091 if (offset_expr
.X_op
!= O_constant
12092 && offset_expr
.X_op
!= O_symbol
)
12094 as_bad (_("expression too complex"));
12095 offset_expr
.X_op
= O_constant
;
12098 if (HAVE_32BIT_ADDRESSES
12099 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12103 sprintf_vma (value
, offset_expr
.X_add_number
);
12104 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12107 /* A constant expression in PIC code can be handled just as it
12108 is in non PIC code. */
12109 if (offset_expr
.X_op
== O_constant
)
12111 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12112 offbits
== 0 ? 16 : offbits
);
12113 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12115 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12118 tempreg
, tempreg
, breg
);
12121 if (offset_expr
.X_add_number
!= 0)
12122 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12123 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12124 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12126 else if (offbits
== 16)
12127 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12129 macro_build (NULL
, s
, fmt
, op
[0],
12130 (int) offset_expr
.X_add_number
, tempreg
);
12132 else if (offbits
!= 16)
12134 /* The offset field is too narrow to be used for a low-part
12135 relocation, so load the whole address into the auxiliary
12137 load_address (tempreg
, &offset_expr
, &used_at
);
12139 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12140 tempreg
, tempreg
, breg
);
12142 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12144 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12146 else if (mips_pic
== NO_PIC
)
12148 /* If this is a reference to a GP relative symbol, and there
12149 is no base register, we want
12150 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12151 Otherwise, if there is no base register, we want
12152 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12153 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12154 If we have a constant, we need two instructions anyhow,
12155 so we always use the latter form.
12157 If we have a base register, and this is a reference to a
12158 GP relative symbol, we want
12159 addu $tempreg,$breg,$gp
12160 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12162 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12163 addu $tempreg,$tempreg,$breg
12164 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12165 With a constant we always use the latter case.
12167 With 64bit address space and no base register and $at usable,
12169 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12170 lui $at,<sym> (BFD_RELOC_HI16_S)
12171 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12174 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12175 If we have a base register, we want
12176 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12177 lui $at,<sym> (BFD_RELOC_HI16_S)
12178 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12182 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12184 Without $at we can't generate the optimal path for superscalar
12185 processors here since this would require two temporary registers.
12186 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12187 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12189 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12191 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12192 If we have a base register, we want
12193 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12194 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12196 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12198 daddu $tempreg,$tempreg,$breg
12199 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12201 For GP relative symbols in 64bit address space we can use
12202 the same sequence as in 32bit address space. */
12203 if (HAVE_64BIT_SYMBOLS
)
12205 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12206 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12208 relax_start (offset_expr
.X_add_symbol
);
12211 macro_build (&offset_expr
, s
, fmt
, op
[0],
12212 BFD_RELOC_GPREL16
, mips_gp_register
);
12216 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12217 tempreg
, breg
, mips_gp_register
);
12218 macro_build (&offset_expr
, s
, fmt
, op
[0],
12219 BFD_RELOC_GPREL16
, tempreg
);
12224 if (used_at
== 0 && mips_opts
.at
)
12226 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12227 BFD_RELOC_MIPS_HIGHEST
);
12228 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12230 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12231 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12233 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12234 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12235 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12236 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12242 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12243 BFD_RELOC_MIPS_HIGHEST
);
12244 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12245 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12246 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12247 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12248 tempreg
, BFD_RELOC_HI16_S
);
12249 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12251 macro_build (NULL
, "daddu", "d,v,t",
12252 tempreg
, tempreg
, breg
);
12253 macro_build (&offset_expr
, s
, fmt
, op
[0],
12254 BFD_RELOC_LO16
, tempreg
);
12257 if (mips_relax
.sequence
)
12264 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12265 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12267 relax_start (offset_expr
.X_add_symbol
);
12268 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12272 macro_build_lui (&offset_expr
, tempreg
);
12273 macro_build (&offset_expr
, s
, fmt
, op
[0],
12274 BFD_RELOC_LO16
, tempreg
);
12275 if (mips_relax
.sequence
)
12280 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12281 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12283 relax_start (offset_expr
.X_add_symbol
);
12284 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12285 tempreg
, breg
, mips_gp_register
);
12286 macro_build (&offset_expr
, s
, fmt
, op
[0],
12287 BFD_RELOC_GPREL16
, tempreg
);
12290 macro_build_lui (&offset_expr
, tempreg
);
12291 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12292 tempreg
, tempreg
, breg
);
12293 macro_build (&offset_expr
, s
, fmt
, op
[0],
12294 BFD_RELOC_LO16
, tempreg
);
12295 if (mips_relax
.sequence
)
12299 else if (!mips_big_got
)
12301 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12303 /* If this is a reference to an external symbol, we want
12304 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12306 <op> op[0],0($tempreg)
12308 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12310 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12311 <op> op[0],0($tempreg)
12313 For NewABI, we want
12314 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12315 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12317 If there is a base register, we add it to $tempreg before
12318 the <op>. If there is a constant, we stick it in the
12319 <op> instruction. We don't handle constants larger than
12320 16 bits, because we have no way to load the upper 16 bits
12321 (actually, we could handle them for the subset of cases
12322 in which we are not using $at). */
12323 gas_assert (offset_expr
.X_op
== O_symbol
);
12326 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12327 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12330 tempreg
, tempreg
, breg
);
12331 macro_build (&offset_expr
, s
, fmt
, op
[0],
12332 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12335 expr1
.X_add_number
= offset_expr
.X_add_number
;
12336 offset_expr
.X_add_number
= 0;
12337 if (expr1
.X_add_number
< -0x8000
12338 || expr1
.X_add_number
>= 0x8000)
12339 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12340 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12341 lw_reloc_type
, mips_gp_register
);
12343 relax_start (offset_expr
.X_add_symbol
);
12345 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12346 tempreg
, BFD_RELOC_LO16
);
12349 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12350 tempreg
, tempreg
, breg
);
12351 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12353 else if (mips_big_got
&& !HAVE_NEWABI
)
12357 /* If this is a reference to an external symbol, we want
12358 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12359 addu $tempreg,$tempreg,$gp
12360 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12361 <op> op[0],0($tempreg)
12363 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12365 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12366 <op> op[0],0($tempreg)
12367 If there is a base register, we add it to $tempreg before
12368 the <op>. If there is a constant, we stick it in the
12369 <op> instruction. We don't handle constants larger than
12370 16 bits, because we have no way to load the upper 16 bits
12371 (actually, we could handle them for the subset of cases
12372 in which we are not using $at). */
12373 gas_assert (offset_expr
.X_op
== O_symbol
);
12374 expr1
.X_add_number
= offset_expr
.X_add_number
;
12375 offset_expr
.X_add_number
= 0;
12376 if (expr1
.X_add_number
< -0x8000
12377 || expr1
.X_add_number
>= 0x8000)
12378 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12379 gpdelay
= reg_needs_delay (mips_gp_register
);
12380 relax_start (offset_expr
.X_add_symbol
);
12381 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12382 BFD_RELOC_MIPS_GOT_HI16
);
12383 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12385 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12386 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12389 macro_build (NULL
, "nop", "");
12390 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12391 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12393 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12394 tempreg
, BFD_RELOC_LO16
);
12398 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12399 tempreg
, tempreg
, breg
);
12400 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12402 else if (mips_big_got
&& HAVE_NEWABI
)
12404 /* If this is a reference to an external symbol, we want
12405 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12406 add $tempreg,$tempreg,$gp
12407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12408 <op> op[0],<ofst>($tempreg)
12409 Otherwise, for local symbols, we want:
12410 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12411 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12412 gas_assert (offset_expr
.X_op
== O_symbol
);
12413 expr1
.X_add_number
= offset_expr
.X_add_number
;
12414 offset_expr
.X_add_number
= 0;
12415 if (expr1
.X_add_number
< -0x8000
12416 || expr1
.X_add_number
>= 0x8000)
12417 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12418 relax_start (offset_expr
.X_add_symbol
);
12419 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12420 BFD_RELOC_MIPS_GOT_HI16
);
12421 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12423 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12424 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12426 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12427 tempreg
, tempreg
, breg
);
12428 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12431 offset_expr
.X_add_number
= expr1
.X_add_number
;
12432 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12433 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12435 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12436 tempreg
, tempreg
, breg
);
12437 macro_build (&offset_expr
, s
, fmt
, op
[0],
12438 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12447 gas_assert (mips_opts
.micromips
);
12448 gas_assert (mips_opts
.insn32
);
12449 start_noreorder ();
12450 macro_build (NULL
, "jr", "s", RA
);
12451 expr1
.X_add_number
= op
[0] << 2;
12452 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12457 gas_assert (mips_opts
.micromips
);
12458 gas_assert (mips_opts
.insn32
);
12459 macro_build (NULL
, "jr", "s", op
[0]);
12460 if (mips_opts
.noreorder
)
12461 macro_build (NULL
, "nop", "");
12466 load_register (op
[0], &imm_expr
, 0);
12470 load_register (op
[0], &imm_expr
, 1);
12474 if (imm_expr
.X_op
== O_constant
)
12477 load_register (AT
, &imm_expr
, 0);
12478 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12483 gas_assert (imm_expr
.X_op
== O_absent
12484 && offset_expr
.X_op
== O_symbol
12485 && strcmp (segment_name (S_GET_SEGMENT
12486 (offset_expr
.X_add_symbol
)),
12488 && offset_expr
.X_add_number
== 0);
12489 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12490 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12495 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12496 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12497 order 32 bits of the value and the low order 32 bits are either
12498 zero or in OFFSET_EXPR. */
12499 if (imm_expr
.X_op
== O_constant
)
12501 if (GPR_SIZE
== 64)
12502 load_register (op
[0], &imm_expr
, 1);
12507 if (target_big_endian
)
12519 load_register (hreg
, &imm_expr
, 0);
12522 if (offset_expr
.X_op
== O_absent
)
12523 move_register (lreg
, 0);
12526 gas_assert (offset_expr
.X_op
== O_constant
);
12527 load_register (lreg
, &offset_expr
, 0);
12533 gas_assert (imm_expr
.X_op
== O_absent
);
12535 /* We know that sym is in the .rdata section. First we get the
12536 upper 16 bits of the address. */
12537 if (mips_pic
== NO_PIC
)
12539 macro_build_lui (&offset_expr
, AT
);
12544 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12545 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12549 /* Now we load the register(s). */
12550 if (GPR_SIZE
== 64)
12553 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12554 BFD_RELOC_LO16
, AT
);
12559 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12560 BFD_RELOC_LO16
, AT
);
12563 /* FIXME: How in the world do we deal with the possible
12565 offset_expr
.X_add_number
+= 4;
12566 macro_build (&offset_expr
, "lw", "t,o(b)",
12567 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12573 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12574 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12575 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12576 the value and the low order 32 bits are either zero or in
12578 if (imm_expr
.X_op
== O_constant
)
12581 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12582 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12583 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12586 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12587 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12588 else if (FPR_SIZE
!= 32)
12589 as_bad (_("Unable to generate `%s' compliant code "
12591 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12593 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12594 if (offset_expr
.X_op
== O_absent
)
12595 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12598 gas_assert (offset_expr
.X_op
== O_constant
);
12599 load_register (AT
, &offset_expr
, 0);
12600 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12606 gas_assert (imm_expr
.X_op
== O_absent
12607 && offset_expr
.X_op
== O_symbol
12608 && offset_expr
.X_add_number
== 0);
12609 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12610 if (strcmp (s
, ".lit8") == 0)
12612 op
[2] = mips_gp_register
;
12613 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12614 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12615 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12619 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12621 if (mips_pic
!= NO_PIC
)
12622 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12623 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12626 /* FIXME: This won't work for a 64 bit address. */
12627 macro_build_lui (&offset_expr
, AT
);
12631 offset_reloc
[0] = BFD_RELOC_LO16
;
12632 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12633 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12640 * The MIPS assembler seems to check for X_add_number not
12641 * being double aligned and generating:
12642 * lui at,%hi(foo+1)
12644 * addiu at,at,%lo(foo+1)
12647 * But, the resulting address is the same after relocation so why
12648 * generate the extra instruction?
12650 /* Itbl support may require additional care here. */
12653 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12662 gas_assert (!mips_opts
.micromips
);
12663 /* Itbl support may require additional care here. */
12666 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12686 if (GPR_SIZE
== 64)
12696 if (GPR_SIZE
== 64)
12704 /* Even on a big endian machine $fn comes before $fn+1. We have
12705 to adjust when loading from memory. We set coproc if we must
12706 load $fn+1 first. */
12707 /* Itbl support may require additional care here. */
12708 if (!target_big_endian
)
12712 if (small_offset_p (0, align
, 16))
12715 if (!small_offset_p (4, align
, 16))
12717 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12718 -1, offset_reloc
[0], offset_reloc
[1],
12720 expr1
.X_add_number
= 0;
12724 offset_reloc
[0] = BFD_RELOC_LO16
;
12725 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12726 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12728 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12730 ep
->X_add_number
+= 4;
12731 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12732 offset_reloc
[1], offset_reloc
[2], breg
);
12733 ep
->X_add_number
-= 4;
12734 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12735 offset_reloc
[1], offset_reloc
[2], breg
);
12739 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12740 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12742 ep
->X_add_number
+= 4;
12743 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12744 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12750 if (offset_expr
.X_op
!= O_symbol
12751 && offset_expr
.X_op
!= O_constant
)
12753 as_bad (_("expression too complex"));
12754 offset_expr
.X_op
= O_constant
;
12757 if (HAVE_32BIT_ADDRESSES
12758 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12762 sprintf_vma (value
, offset_expr
.X_add_number
);
12763 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12766 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12768 /* If this is a reference to a GP relative symbol, we want
12769 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12770 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12771 If we have a base register, we use this
12773 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12774 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12775 If this is not a GP relative symbol, we want
12776 lui $at,<sym> (BFD_RELOC_HI16_S)
12777 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12778 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12779 If there is a base register, we add it to $at after the
12780 lui instruction. If there is a constant, we always use
12782 if (offset_expr
.X_op
== O_symbol
12783 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12784 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12786 relax_start (offset_expr
.X_add_symbol
);
12789 tempreg
= mips_gp_register
;
12793 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12794 AT
, breg
, mips_gp_register
);
12799 /* Itbl support may require additional care here. */
12800 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12801 BFD_RELOC_GPREL16
, tempreg
);
12802 offset_expr
.X_add_number
+= 4;
12804 /* Set mips_optimize to 2 to avoid inserting an
12806 hold_mips_optimize
= mips_optimize
;
12808 /* Itbl support may require additional care here. */
12809 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12810 BFD_RELOC_GPREL16
, tempreg
);
12811 mips_optimize
= hold_mips_optimize
;
12815 offset_expr
.X_add_number
-= 4;
12818 if (offset_high_part (offset_expr
.X_add_number
, 16)
12819 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12821 load_address (AT
, &offset_expr
, &used_at
);
12822 offset_expr
.X_op
= O_constant
;
12823 offset_expr
.X_add_number
= 0;
12826 macro_build_lui (&offset_expr
, AT
);
12828 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12829 /* Itbl support may require additional care here. */
12830 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12831 BFD_RELOC_LO16
, AT
);
12832 /* FIXME: How do we handle overflow here? */
12833 offset_expr
.X_add_number
+= 4;
12834 /* Itbl support may require additional care here. */
12835 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12836 BFD_RELOC_LO16
, AT
);
12837 if (mips_relax
.sequence
)
12840 else if (!mips_big_got
)
12842 /* If this is a reference to an external symbol, we want
12843 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12846 <op> op[0]+1,4($at)
12848 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12850 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12851 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12852 If there is a base register we add it to $at before the
12853 lwc1 instructions. If there is a constant we include it
12854 in the lwc1 instructions. */
12856 expr1
.X_add_number
= offset_expr
.X_add_number
;
12857 if (expr1
.X_add_number
< -0x8000
12858 || expr1
.X_add_number
>= 0x8000 - 4)
12859 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12860 load_got_offset (AT
, &offset_expr
);
12863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12865 /* Set mips_optimize to 2 to avoid inserting an undesired
12867 hold_mips_optimize
= mips_optimize
;
12870 /* Itbl support may require additional care here. */
12871 relax_start (offset_expr
.X_add_symbol
);
12872 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12873 BFD_RELOC_LO16
, AT
);
12874 expr1
.X_add_number
+= 4;
12875 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12876 BFD_RELOC_LO16
, AT
);
12878 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12879 BFD_RELOC_LO16
, AT
);
12880 offset_expr
.X_add_number
+= 4;
12881 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12882 BFD_RELOC_LO16
, AT
);
12885 mips_optimize
= hold_mips_optimize
;
12887 else if (mips_big_got
)
12891 /* If this is a reference to an external symbol, we want
12892 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12894 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12897 <op> op[0]+1,4($at)
12899 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12901 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12902 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12903 If there is a base register we add it to $at before the
12904 lwc1 instructions. If there is a constant we include it
12905 in the lwc1 instructions. */
12907 expr1
.X_add_number
= offset_expr
.X_add_number
;
12908 offset_expr
.X_add_number
= 0;
12909 if (expr1
.X_add_number
< -0x8000
12910 || expr1
.X_add_number
>= 0x8000 - 4)
12911 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12912 gpdelay
= reg_needs_delay (mips_gp_register
);
12913 relax_start (offset_expr
.X_add_symbol
);
12914 macro_build (&offset_expr
, "lui", LUI_FMT
,
12915 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12916 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12917 AT
, AT
, mips_gp_register
);
12918 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12919 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12922 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12923 /* Itbl support may require additional care here. */
12924 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12925 BFD_RELOC_LO16
, AT
);
12926 expr1
.X_add_number
+= 4;
12928 /* Set mips_optimize to 2 to avoid inserting an undesired
12930 hold_mips_optimize
= mips_optimize
;
12932 /* Itbl support may require additional care here. */
12933 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12934 BFD_RELOC_LO16
, AT
);
12935 mips_optimize
= hold_mips_optimize
;
12936 expr1
.X_add_number
-= 4;
12939 offset_expr
.X_add_number
= expr1
.X_add_number
;
12941 macro_build (NULL
, "nop", "");
12942 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12943 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12946 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12947 /* Itbl support may require additional care here. */
12948 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12949 BFD_RELOC_LO16
, AT
);
12950 offset_expr
.X_add_number
+= 4;
12952 /* Set mips_optimize to 2 to avoid inserting an undesired
12954 hold_mips_optimize
= mips_optimize
;
12956 /* Itbl support may require additional care here. */
12957 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12958 BFD_RELOC_LO16
, AT
);
12959 mips_optimize
= hold_mips_optimize
;
12973 gas_assert (!mips_opts
.micromips
);
12978 /* New code added to support COPZ instructions.
12979 This code builds table entries out of the macros in mip_opcodes.
12980 R4000 uses interlocks to handle coproc delays.
12981 Other chips (like the R3000) require nops to be inserted for delays.
12983 FIXME: Currently, we require that the user handle delays.
12984 In order to fill delay slots for non-interlocked chips,
12985 we must have a way to specify delays based on the coprocessor.
12986 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12987 What are the side-effects of the cop instruction?
12988 What cache support might we have and what are its effects?
12989 Both coprocessor & memory require delays. how long???
12990 What registers are read/set/modified?
12992 If an itbl is provided to interpret cop instructions,
12993 this knowledge can be encoded in the itbl spec. */
13007 gas_assert (!mips_opts
.micromips
);
13008 /* For now we just do C (same as Cz). The parameter will be
13009 stored in insn_opcode by mips_ip. */
13010 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13014 move_register (op
[0], op
[1]);
13018 gas_assert (mips_opts
.micromips
);
13019 gas_assert (mips_opts
.insn32
);
13020 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13021 micromips_to_32_reg_m_map
[op
[1]]);
13022 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13023 micromips_to_32_reg_n_map
[op
[2]]);
13028 /* Fall through. */
13030 if (mips_opts
.arch
== CPU_R5900
)
13031 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13035 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13036 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13042 /* Fall through. */
13044 /* The MIPS assembler some times generates shifts and adds. I'm
13045 not trying to be that fancy. GCC should do this for us
13048 load_register (AT
, &imm_expr
, dbl
);
13049 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13050 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13055 /* Fall through. */
13062 /* Fall through. */
13065 start_noreorder ();
13068 load_register (AT
, &imm_expr
, dbl
);
13069 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13070 op
[1], imm
? AT
: op
[2]);
13071 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13072 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13073 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13075 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13078 if (mips_opts
.micromips
)
13079 micromips_label_expr (&label_expr
);
13081 label_expr
.X_add_number
= 8;
13082 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13083 macro_build (NULL
, "nop", "");
13084 macro_build (NULL
, "break", BRK_FMT
, 6);
13085 if (mips_opts
.micromips
)
13086 micromips_add_label ();
13089 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13094 /* Fall through. */
13101 /* Fall through. */
13104 start_noreorder ();
13107 load_register (AT
, &imm_expr
, dbl
);
13108 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13109 op
[1], imm
? AT
: op
[2]);
13110 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13111 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13113 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13116 if (mips_opts
.micromips
)
13117 micromips_label_expr (&label_expr
);
13119 label_expr
.X_add_number
= 8;
13120 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13121 macro_build (NULL
, "nop", "");
13122 macro_build (NULL
, "break", BRK_FMT
, 6);
13123 if (mips_opts
.micromips
)
13124 micromips_add_label ();
13130 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13132 if (op
[0] == op
[1])
13139 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13140 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13144 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13145 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13146 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13147 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13151 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13153 if (op
[0] == op
[1])
13160 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13161 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13165 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13166 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13167 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13168 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13177 rot
= imm_expr
.X_add_number
& 0x3f;
13178 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13180 rot
= (64 - rot
) & 0x3f;
13182 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13184 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13189 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13192 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13193 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13196 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13197 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13198 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13206 rot
= imm_expr
.X_add_number
& 0x1f;
13207 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13209 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13210 (32 - rot
) & 0x1f);
13215 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13219 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13220 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13221 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13226 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13228 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13232 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13233 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13234 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13235 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13239 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13241 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13245 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13246 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13247 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13248 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13257 rot
= imm_expr
.X_add_number
& 0x3f;
13258 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13261 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13263 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13268 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13271 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13272 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13275 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13276 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13277 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13285 rot
= imm_expr
.X_add_number
& 0x1f;
13286 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13288 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13293 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13297 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13298 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13299 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13305 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13306 else if (op
[2] == 0)
13307 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13310 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13311 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13316 if (imm_expr
.X_add_number
== 0)
13318 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13323 as_warn (_("instruction %s: result is always false"),
13324 ip
->insn_mo
->name
);
13325 move_register (op
[0], 0);
13328 if (CPU_HAS_SEQ (mips_opts
.arch
)
13329 && -512 <= imm_expr
.X_add_number
13330 && imm_expr
.X_add_number
< 512)
13332 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13333 (int) imm_expr
.X_add_number
);
13336 if (imm_expr
.X_add_number
>= 0
13337 && imm_expr
.X_add_number
< 0x10000)
13338 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13339 else if (imm_expr
.X_add_number
> -0x8000
13340 && imm_expr
.X_add_number
< 0)
13342 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13343 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13344 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13346 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13349 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13350 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13355 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13356 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13359 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13362 case M_SGE
: /* X >= Y <==> not (X < Y) */
13368 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13369 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13372 case M_SGE_I
: /* X >= I <==> not (X < I) */
13374 if (imm_expr
.X_add_number
>= -0x8000
13375 && imm_expr
.X_add_number
< 0x8000)
13376 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13377 op
[0], op
[1], BFD_RELOC_LO16
);
13380 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13381 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13385 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13388 case M_SGT
: /* X > Y <==> Y < X */
13394 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13397 case M_SGT_I
: /* X > I <==> I < X */
13404 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13405 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13408 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13414 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13415 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13418 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13425 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13426 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13427 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13431 if (imm_expr
.X_add_number
>= -0x8000
13432 && imm_expr
.X_add_number
< 0x8000)
13434 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13439 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13440 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13444 if (imm_expr
.X_add_number
>= -0x8000
13445 && imm_expr
.X_add_number
< 0x8000)
13447 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13452 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13453 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13458 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13459 else if (op
[2] == 0)
13460 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13463 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13464 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13469 if (imm_expr
.X_add_number
== 0)
13471 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13476 as_warn (_("instruction %s: result is always true"),
13477 ip
->insn_mo
->name
);
13478 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13479 op
[0], 0, BFD_RELOC_LO16
);
13482 if (CPU_HAS_SEQ (mips_opts
.arch
)
13483 && -512 <= imm_expr
.X_add_number
13484 && imm_expr
.X_add_number
< 512)
13486 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13487 (int) imm_expr
.X_add_number
);
13490 if (imm_expr
.X_add_number
>= 0
13491 && imm_expr
.X_add_number
< 0x10000)
13493 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13496 else if (imm_expr
.X_add_number
> -0x8000
13497 && imm_expr
.X_add_number
< 0)
13499 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13500 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13501 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13503 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13506 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13507 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13512 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13513 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13516 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13531 if (!mips_opts
.micromips
)
13533 if (imm_expr
.X_add_number
> -0x200
13534 && imm_expr
.X_add_number
<= 0x200)
13536 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13537 (int) -imm_expr
.X_add_number
);
13546 if (imm_expr
.X_add_number
> -0x8000
13547 && imm_expr
.X_add_number
<= 0x8000)
13549 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13550 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13555 load_register (AT
, &imm_expr
, dbl
);
13556 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13578 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13579 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13584 gas_assert (!mips_opts
.micromips
);
13585 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13589 * Is the double cfc1 instruction a bug in the mips assembler;
13590 * or is there a reason for it?
13592 start_noreorder ();
13593 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13594 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13595 macro_build (NULL
, "nop", "");
13596 expr1
.X_add_number
= 3;
13597 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13598 expr1
.X_add_number
= 2;
13599 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13600 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13601 macro_build (NULL
, "nop", "");
13602 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13604 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13605 macro_build (NULL
, "nop", "");
13622 offbits
= (mips_opts
.micromips
? 12 : 16);
13628 offbits
= (mips_opts
.micromips
? 12 : 16);
13640 offbits
= (mips_opts
.micromips
? 12 : 16);
13647 offbits
= (mips_opts
.micromips
? 12 : 16);
13653 large_offset
= !small_offset_p (off
, align
, offbits
);
13655 expr1
.X_add_number
= 0;
13660 if (small_offset_p (0, align
, 16))
13661 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13662 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13665 load_address (tempreg
, ep
, &used_at
);
13667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13668 tempreg
, tempreg
, breg
);
13670 offset_reloc
[0] = BFD_RELOC_LO16
;
13671 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13672 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13677 else if (!ust
&& op
[0] == breg
)
13688 if (!target_big_endian
)
13689 ep
->X_add_number
+= off
;
13691 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13693 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13694 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13696 if (!target_big_endian
)
13697 ep
->X_add_number
-= off
;
13699 ep
->X_add_number
+= off
;
13701 macro_build (NULL
, s2
, "t,~(b)",
13702 tempreg
, (int) ep
->X_add_number
, breg
);
13704 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13705 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13707 /* If necessary, move the result in tempreg to the final destination. */
13708 if (!ust
&& op
[0] != tempreg
)
13710 /* Protect second load's delay slot. */
13712 move_register (op
[0], tempreg
);
13718 if (target_big_endian
== ust
)
13719 ep
->X_add_number
+= off
;
13720 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13721 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13722 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13724 /* For halfword transfers we need a temporary register to shuffle
13725 bytes. Unfortunately for M_USH_A we have none available before
13726 the next store as AT holds the base address. We deal with this
13727 case by clobbering TREG and then restoring it as with ULH. */
13728 tempreg
= ust
== large_offset
? op
[0] : AT
;
13730 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13732 if (target_big_endian
== ust
)
13733 ep
->X_add_number
-= off
;
13735 ep
->X_add_number
+= off
;
13736 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13737 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13739 /* For M_USH_A re-retrieve the LSB. */
13740 if (ust
&& large_offset
)
13742 if (target_big_endian
)
13743 ep
->X_add_number
+= off
;
13745 ep
->X_add_number
-= off
;
13746 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13747 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13749 /* For ULH and M_USH_A OR the LSB in. */
13750 if (!ust
|| large_offset
)
13752 tempreg
= !large_offset
? AT
: op
[0];
13753 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13754 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13759 /* FIXME: Check if this is one of the itbl macros, since they
13760 are added dynamically. */
13761 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13764 if (!mips_opts
.at
&& used_at
)
13765 as_bad (_("macro used $at after \".set noat\""));
13768 /* Implement macros in mips16 mode. */
13771 mips16_macro (struct mips_cl_insn
*ip
)
13773 const struct mips_operand_array
*operands
;
13778 const char *s
, *s2
, *s3
;
13779 unsigned int op
[MAX_OPERANDS
];
13782 mask
= ip
->insn_mo
->mask
;
13784 operands
= insn_operands (ip
);
13785 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13786 if (operands
->operand
[i
])
13787 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13791 expr1
.X_op
= O_constant
;
13792 expr1
.X_op_symbol
= NULL
;
13793 expr1
.X_add_symbol
= NULL
;
13794 expr1
.X_add_number
= 1;
13805 /* Fall through. */
13811 /* Fall through. */
13815 start_noreorder ();
13816 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13817 expr1
.X_add_number
= 2;
13818 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13819 macro_build (NULL
, "break", "6", 7);
13821 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13822 since that causes an overflow. We should do that as well,
13823 but I don't see how to do the comparisons without a temporary
13826 macro_build (NULL
, s
, "x", op
[0]);
13845 start_noreorder ();
13846 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13847 expr1
.X_add_number
= 2;
13848 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13849 macro_build (NULL
, "break", "6", 7);
13851 macro_build (NULL
, s2
, "x", op
[0]);
13856 /* Fall through. */
13858 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13859 macro_build (NULL
, "mflo", "x", op
[0]);
13867 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13868 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13872 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13873 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13877 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13878 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13900 goto do_reverse_branch
;
13904 goto do_reverse_branch
;
13916 goto do_reverse_branch
;
13927 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13928 macro_build (&offset_expr
, s2
, "p");
13955 goto do_addone_branch_i
;
13960 goto do_addone_branch_i
;
13975 goto do_addone_branch_i
;
13981 do_addone_branch_i
:
13982 ++imm_expr
.X_add_number
;
13985 macro_build (&imm_expr
, s
, s3
, op
[0]);
13986 macro_build (&offset_expr
, s2
, "p");
13990 expr1
.X_add_number
= 0;
13991 macro_build (&expr1
, "slti", "x,8", op
[1]);
13992 if (op
[0] != op
[1])
13993 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13994 expr1
.X_add_number
= 2;
13995 macro_build (&expr1
, "bteqz", "p");
13996 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14001 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14002 opcode bits in *OPCODE_EXTRA. */
14004 static struct mips_opcode
*
14005 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14006 ssize_t length
, unsigned int *opcode_extra
)
14008 char *name
, *dot
, *p
;
14009 unsigned int mask
, suffix
;
14011 struct mips_opcode
*insn
;
14013 /* Make a copy of the instruction so that we can fiddle with it. */
14014 name
= xstrndup (start
, length
);
14016 /* Look up the instruction as-is. */
14017 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14021 dot
= strchr (name
, '.');
14024 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14025 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14026 if (*p
== 0 && mask
!= 0)
14029 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14031 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14033 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14039 if (mips_opts
.micromips
)
14041 /* See if there's an instruction size override suffix,
14042 either `16' or `32', at the end of the mnemonic proper,
14043 that defines the operation, i.e. before the first `.'
14044 character if any. Strip it and retry. */
14045 opend
= dot
!= NULL
? dot
- name
: length
;
14046 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14048 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14054 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14055 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14058 forced_insn_length
= suffix
;
14070 /* Assemble an instruction into its binary format. If the instruction
14071 is a macro, set imm_expr and offset_expr to the values associated
14072 with "I" and "A" operands respectively. Otherwise store the value
14073 of the relocatable field (if any) in offset_expr. In both cases
14074 set offset_reloc to the relocation operators applied to offset_expr. */
14077 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14079 const struct mips_opcode
*first
, *past
;
14080 struct hash_control
*hash
;
14083 struct mips_operand_token
*tokens
;
14084 unsigned int opcode_extra
;
14086 if (mips_opts
.micromips
)
14088 hash
= micromips_op_hash
;
14089 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14094 past
= &mips_opcodes
[NUMOPCODES
];
14096 forced_insn_length
= 0;
14099 /* We first try to match an instruction up to a space or to the end. */
14100 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14103 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14106 set_insn_error (0, _("unrecognized opcode"));
14110 if (strcmp (first
->name
, "li.s") == 0)
14112 else if (strcmp (first
->name
, "li.d") == 0)
14116 tokens
= mips_parse_arguments (str
+ end
, format
);
14120 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14121 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14122 set_insn_error (0, _("invalid operands"));
14124 obstack_free (&mips_operand_tokens
, tokens
);
14127 /* As for mips_ip, but used when assembling MIPS16 code.
14128 Also set forced_insn_length to the resulting instruction size in
14129 bytes if the user explicitly requested a small or extended instruction. */
14132 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14135 struct mips_opcode
*first
;
14136 struct mips_operand_token
*tokens
;
14139 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14161 else if (*s
== 'e')
14168 else if (*s
++ == ' ')
14170 set_insn_error (0, _("unrecognized opcode"));
14173 forced_insn_length
= l
;
14176 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14181 set_insn_error (0, _("unrecognized opcode"));
14185 tokens
= mips_parse_arguments (s
, 0);
14189 if (!match_mips16_insns (insn
, first
, tokens
))
14190 set_insn_error (0, _("invalid operands"));
14192 obstack_free (&mips_operand_tokens
, tokens
);
14195 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14196 NBITS is the number of significant bits in VAL. */
14198 static unsigned long
14199 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14204 val
&= (1U << nbits
) - 1;
14205 if (nbits
== 16 || nbits
== 9)
14207 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14210 else if (nbits
== 15)
14212 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14215 else if (nbits
== 6)
14217 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14220 return (extval
<< 16) | val
;
14223 /* Like decode_mips16_operand, but require the operand to be defined and
14224 require it to be an integer. */
14226 static const struct mips_int_operand
*
14227 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14229 const struct mips_operand
*operand
;
14231 operand
= decode_mips16_operand (type
, extended_p
);
14232 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14234 return (const struct mips_int_operand
*) operand
;
14237 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14240 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14241 bfd_reloc_code_real_type reloc
, offsetT sval
)
14243 int min_val
, max_val
;
14245 min_val
= mips_int_operand_min (operand
);
14246 max_val
= mips_int_operand_max (operand
);
14247 if (reloc
!= BFD_RELOC_UNUSED
)
14250 sval
= SEXT_16BIT (sval
);
14255 return (sval
>= min_val
14257 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14260 /* Install immediate value VAL into MIPS16 instruction *INSN,
14261 extending it if necessary. The instruction in *INSN may
14262 already be extended.
14264 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14265 if none. In the former case, VAL is a 16-bit number with no
14266 defined signedness.
14268 TYPE is the type of the immediate field. USER_INSN_LENGTH
14269 is the length that the user requested, or 0 if none. */
14272 mips16_immed (const char *file
, unsigned int line
, int type
,
14273 bfd_reloc_code_real_type reloc
, offsetT val
,
14274 unsigned int user_insn_length
, unsigned long *insn
)
14276 const struct mips_int_operand
*operand
;
14277 unsigned int uval
, length
;
14279 operand
= mips16_immed_operand (type
, FALSE
);
14280 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14282 /* We need an extended instruction. */
14283 if (user_insn_length
== 2)
14284 as_bad_where (file
, line
, _("invalid unextended operand value"));
14286 *insn
|= MIPS16_EXTEND
;
14288 else if (user_insn_length
== 4)
14290 /* The operand doesn't force an unextended instruction to be extended.
14291 Warn if the user wanted an extended instruction anyway. */
14292 *insn
|= MIPS16_EXTEND
;
14293 as_warn_where (file
, line
,
14294 _("extended operand requested but not required"));
14297 length
= mips16_opcode_length (*insn
);
14300 operand
= mips16_immed_operand (type
, TRUE
);
14301 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14302 as_bad_where (file
, line
,
14303 _("operand value out of range for instruction"));
14305 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14306 if (length
== 2 || operand
->root
.lsb
!= 0)
14307 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14309 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14312 struct percent_op_match
14315 bfd_reloc_code_real_type reloc
;
14318 static const struct percent_op_match mips_percent_op
[] =
14320 {"%lo", BFD_RELOC_LO16
},
14321 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14322 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14323 {"%call16", BFD_RELOC_MIPS_CALL16
},
14324 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14325 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14326 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14327 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14328 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14329 {"%got", BFD_RELOC_MIPS_GOT16
},
14330 {"%gp_rel", BFD_RELOC_GPREL16
},
14331 {"%gprel", BFD_RELOC_GPREL16
},
14332 {"%half", BFD_RELOC_16
},
14333 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14334 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14335 {"%neg", BFD_RELOC_MIPS_SUB
},
14336 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14337 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14338 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14339 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14340 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14341 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14342 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14343 {"%hi", BFD_RELOC_HI16_S
},
14344 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14345 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14348 static const struct percent_op_match mips16_percent_op
[] =
14350 {"%lo", BFD_RELOC_MIPS16_LO16
},
14351 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14352 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14353 {"%got", BFD_RELOC_MIPS16_GOT16
},
14354 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14355 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14356 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14357 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14358 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14359 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14360 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14361 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14362 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14366 /* Return true if *STR points to a relocation operator. When returning true,
14367 move *STR over the operator and store its relocation code in *RELOC.
14368 Leave both *STR and *RELOC alone when returning false. */
14371 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14373 const struct percent_op_match
*percent_op
;
14376 if (mips_opts
.mips16
)
14378 percent_op
= mips16_percent_op
;
14379 limit
= ARRAY_SIZE (mips16_percent_op
);
14383 percent_op
= mips_percent_op
;
14384 limit
= ARRAY_SIZE (mips_percent_op
);
14387 for (i
= 0; i
< limit
; i
++)
14388 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14390 int len
= strlen (percent_op
[i
].str
);
14392 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14395 *str
+= strlen (percent_op
[i
].str
);
14396 *reloc
= percent_op
[i
].reloc
;
14398 /* Check whether the output BFD supports this relocation.
14399 If not, issue an error and fall back on something safe. */
14400 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14402 as_bad (_("relocation %s isn't supported by the current ABI"),
14403 percent_op
[i
].str
);
14404 *reloc
= BFD_RELOC_UNUSED
;
14412 /* Parse string STR as a 16-bit relocatable operand. Store the
14413 expression in *EP and the relocations in the array starting
14414 at RELOC. Return the number of relocation operators used.
14416 On exit, EXPR_END points to the first character after the expression. */
14419 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14422 bfd_reloc_code_real_type reversed_reloc
[3];
14423 size_t reloc_index
, i
;
14424 int crux_depth
, str_depth
;
14427 /* Search for the start of the main expression, recoding relocations
14428 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14429 of the main expression and with CRUX_DEPTH containing the number
14430 of open brackets at that point. */
14437 crux_depth
= str_depth
;
14439 /* Skip over whitespace and brackets, keeping count of the number
14441 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14446 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14447 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14449 my_getExpression (ep
, crux
);
14452 /* Match every open bracket. */
14453 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14457 if (crux_depth
> 0)
14458 as_bad (_("unclosed '('"));
14462 if (reloc_index
!= 0)
14464 prev_reloc_op_frag
= frag_now
;
14465 for (i
= 0; i
< reloc_index
; i
++)
14466 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14469 return reloc_index
;
14473 my_getExpression (expressionS
*ep
, char *str
)
14477 save_in
= input_line_pointer
;
14478 input_line_pointer
= str
;
14480 expr_end
= input_line_pointer
;
14481 input_line_pointer
= save_in
;
14485 md_atof (int type
, char *litP
, int *sizeP
)
14487 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14491 md_number_to_chars (char *buf
, valueT val
, int n
)
14493 if (target_big_endian
)
14494 number_to_chars_bigendian (buf
, val
, n
);
14496 number_to_chars_littleendian (buf
, val
, n
);
14499 static int support_64bit_objects(void)
14501 const char **list
, **l
;
14504 list
= bfd_target_list ();
14505 for (l
= list
; *l
!= NULL
; l
++)
14506 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14507 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14509 yes
= (*l
!= NULL
);
14514 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14515 NEW_VALUE. Warn if another value was already specified. Note:
14516 we have to defer parsing the -march and -mtune arguments in order
14517 to handle 'from-abi' correctly, since the ABI might be specified
14518 in a later argument. */
14521 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14523 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14524 as_warn (_("a different %s was already specified, is now %s"),
14525 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14528 *string_ptr
= new_value
;
14532 md_parse_option (int c
, const char *arg
)
14536 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14537 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14539 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14540 c
== mips_ases
[i
].option_on
);
14546 case OPTION_CONSTRUCT_FLOATS
:
14547 mips_disable_float_construction
= 0;
14550 case OPTION_NO_CONSTRUCT_FLOATS
:
14551 mips_disable_float_construction
= 1;
14563 target_big_endian
= 1;
14567 target_big_endian
= 0;
14573 else if (arg
[0] == '0')
14575 else if (arg
[0] == '1')
14585 mips_debug
= atoi (arg
);
14589 file_mips_opts
.isa
= ISA_MIPS1
;
14593 file_mips_opts
.isa
= ISA_MIPS2
;
14597 file_mips_opts
.isa
= ISA_MIPS3
;
14601 file_mips_opts
.isa
= ISA_MIPS4
;
14605 file_mips_opts
.isa
= ISA_MIPS5
;
14608 case OPTION_MIPS32
:
14609 file_mips_opts
.isa
= ISA_MIPS32
;
14612 case OPTION_MIPS32R2
:
14613 file_mips_opts
.isa
= ISA_MIPS32R2
;
14616 case OPTION_MIPS32R3
:
14617 file_mips_opts
.isa
= ISA_MIPS32R3
;
14620 case OPTION_MIPS32R5
:
14621 file_mips_opts
.isa
= ISA_MIPS32R5
;
14624 case OPTION_MIPS32R6
:
14625 file_mips_opts
.isa
= ISA_MIPS32R6
;
14628 case OPTION_MIPS64R2
:
14629 file_mips_opts
.isa
= ISA_MIPS64R2
;
14632 case OPTION_MIPS64R3
:
14633 file_mips_opts
.isa
= ISA_MIPS64R3
;
14636 case OPTION_MIPS64R5
:
14637 file_mips_opts
.isa
= ISA_MIPS64R5
;
14640 case OPTION_MIPS64R6
:
14641 file_mips_opts
.isa
= ISA_MIPS64R6
;
14644 case OPTION_MIPS64
:
14645 file_mips_opts
.isa
= ISA_MIPS64
;
14649 mips_set_option_string (&mips_tune_string
, arg
);
14653 mips_set_option_string (&mips_arch_string
, arg
);
14657 mips_set_option_string (&mips_arch_string
, "4650");
14658 mips_set_option_string (&mips_tune_string
, "4650");
14661 case OPTION_NO_M4650
:
14665 mips_set_option_string (&mips_arch_string
, "4010");
14666 mips_set_option_string (&mips_tune_string
, "4010");
14669 case OPTION_NO_M4010
:
14673 mips_set_option_string (&mips_arch_string
, "4100");
14674 mips_set_option_string (&mips_tune_string
, "4100");
14677 case OPTION_NO_M4100
:
14681 mips_set_option_string (&mips_arch_string
, "3900");
14682 mips_set_option_string (&mips_tune_string
, "3900");
14685 case OPTION_NO_M3900
:
14688 case OPTION_MICROMIPS
:
14689 if (file_mips_opts
.mips16
== 1)
14691 as_bad (_("-mmicromips cannot be used with -mips16"));
14694 file_mips_opts
.micromips
= 1;
14695 mips_no_prev_insn ();
14698 case OPTION_NO_MICROMIPS
:
14699 file_mips_opts
.micromips
= 0;
14700 mips_no_prev_insn ();
14703 case OPTION_MIPS16
:
14704 if (file_mips_opts
.micromips
== 1)
14706 as_bad (_("-mips16 cannot be used with -micromips"));
14709 file_mips_opts
.mips16
= 1;
14710 mips_no_prev_insn ();
14713 case OPTION_NO_MIPS16
:
14714 file_mips_opts
.mips16
= 0;
14715 mips_no_prev_insn ();
14718 case OPTION_FIX_24K
:
14722 case OPTION_NO_FIX_24K
:
14726 case OPTION_FIX_RM7000
:
14727 mips_fix_rm7000
= 1;
14730 case OPTION_NO_FIX_RM7000
:
14731 mips_fix_rm7000
= 0;
14734 case OPTION_FIX_LOONGSON2F_JUMP
:
14735 mips_fix_loongson2f_jump
= TRUE
;
14738 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14739 mips_fix_loongson2f_jump
= FALSE
;
14742 case OPTION_FIX_LOONGSON2F_NOP
:
14743 mips_fix_loongson2f_nop
= TRUE
;
14746 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14747 mips_fix_loongson2f_nop
= FALSE
;
14750 case OPTION_FIX_VR4120
:
14751 mips_fix_vr4120
= 1;
14754 case OPTION_NO_FIX_VR4120
:
14755 mips_fix_vr4120
= 0;
14758 case OPTION_FIX_VR4130
:
14759 mips_fix_vr4130
= 1;
14762 case OPTION_NO_FIX_VR4130
:
14763 mips_fix_vr4130
= 0;
14766 case OPTION_FIX_CN63XXP1
:
14767 mips_fix_cn63xxp1
= TRUE
;
14770 case OPTION_NO_FIX_CN63XXP1
:
14771 mips_fix_cn63xxp1
= FALSE
;
14774 case OPTION_FIX_R5900
:
14775 mips_fix_r5900
= TRUE
;
14776 mips_fix_r5900_explicit
= TRUE
;
14779 case OPTION_NO_FIX_R5900
:
14780 mips_fix_r5900
= FALSE
;
14781 mips_fix_r5900_explicit
= TRUE
;
14784 case OPTION_RELAX_BRANCH
:
14785 mips_relax_branch
= 1;
14788 case OPTION_NO_RELAX_BRANCH
:
14789 mips_relax_branch
= 0;
14792 case OPTION_IGNORE_BRANCH_ISA
:
14793 mips_ignore_branch_isa
= TRUE
;
14796 case OPTION_NO_IGNORE_BRANCH_ISA
:
14797 mips_ignore_branch_isa
= FALSE
;
14800 case OPTION_INSN32
:
14801 file_mips_opts
.insn32
= TRUE
;
14804 case OPTION_NO_INSN32
:
14805 file_mips_opts
.insn32
= FALSE
;
14808 case OPTION_MSHARED
:
14809 mips_in_shared
= TRUE
;
14812 case OPTION_MNO_SHARED
:
14813 mips_in_shared
= FALSE
;
14816 case OPTION_MSYM32
:
14817 file_mips_opts
.sym32
= TRUE
;
14820 case OPTION_MNO_SYM32
:
14821 file_mips_opts
.sym32
= FALSE
;
14824 /* When generating ELF code, we permit -KPIC and -call_shared to
14825 select SVR4_PIC, and -non_shared to select no PIC. This is
14826 intended to be compatible with Irix 5. */
14827 case OPTION_CALL_SHARED
:
14828 mips_pic
= SVR4_PIC
;
14829 mips_abicalls
= TRUE
;
14832 case OPTION_CALL_NONPIC
:
14834 mips_abicalls
= TRUE
;
14837 case OPTION_NON_SHARED
:
14839 mips_abicalls
= FALSE
;
14842 /* The -xgot option tells the assembler to use 32 bit offsets
14843 when accessing the got in SVR4_PIC mode. It is for Irix
14850 g_switch_value
= atoi (arg
);
14854 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14857 mips_abi
= O32_ABI
;
14861 mips_abi
= N32_ABI
;
14865 mips_abi
= N64_ABI
;
14866 if (!support_64bit_objects())
14867 as_fatal (_("no compiled in support for 64 bit object file format"));
14871 file_mips_opts
.gp
= 32;
14875 file_mips_opts
.gp
= 64;
14879 file_mips_opts
.fp
= 32;
14883 file_mips_opts
.fp
= 0;
14887 file_mips_opts
.fp
= 64;
14890 case OPTION_ODD_SPREG
:
14891 file_mips_opts
.oddspreg
= 1;
14894 case OPTION_NO_ODD_SPREG
:
14895 file_mips_opts
.oddspreg
= 0;
14898 case OPTION_SINGLE_FLOAT
:
14899 file_mips_opts
.single_float
= 1;
14902 case OPTION_DOUBLE_FLOAT
:
14903 file_mips_opts
.single_float
= 0;
14906 case OPTION_SOFT_FLOAT
:
14907 file_mips_opts
.soft_float
= 1;
14910 case OPTION_HARD_FLOAT
:
14911 file_mips_opts
.soft_float
= 0;
14915 if (strcmp (arg
, "32") == 0)
14916 mips_abi
= O32_ABI
;
14917 else if (strcmp (arg
, "o64") == 0)
14918 mips_abi
= O64_ABI
;
14919 else if (strcmp (arg
, "n32") == 0)
14920 mips_abi
= N32_ABI
;
14921 else if (strcmp (arg
, "64") == 0)
14923 mips_abi
= N64_ABI
;
14924 if (! support_64bit_objects())
14925 as_fatal (_("no compiled in support for 64 bit object file "
14928 else if (strcmp (arg
, "eabi") == 0)
14929 mips_abi
= EABI_ABI
;
14932 as_fatal (_("invalid abi -mabi=%s"), arg
);
14937 case OPTION_M7000_HILO_FIX
:
14938 mips_7000_hilo_fix
= TRUE
;
14941 case OPTION_MNO_7000_HILO_FIX
:
14942 mips_7000_hilo_fix
= FALSE
;
14945 case OPTION_MDEBUG
:
14946 mips_flag_mdebug
= TRUE
;
14949 case OPTION_NO_MDEBUG
:
14950 mips_flag_mdebug
= FALSE
;
14954 mips_flag_pdr
= TRUE
;
14957 case OPTION_NO_PDR
:
14958 mips_flag_pdr
= FALSE
;
14961 case OPTION_MVXWORKS_PIC
:
14962 mips_pic
= VXWORKS_PIC
;
14966 if (strcmp (arg
, "2008") == 0)
14968 else if (strcmp (arg
, "legacy") == 0)
14972 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14981 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14986 /* Set up globals to tune for the ISA or processor described by INFO. */
14989 mips_set_tune (const struct mips_cpu_info
*info
)
14992 mips_tune
= info
->cpu
;
14997 mips_after_parse_args (void)
14999 const struct mips_cpu_info
*arch_info
= 0;
15000 const struct mips_cpu_info
*tune_info
= 0;
15002 /* GP relative stuff not working for PE */
15003 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15005 if (g_switch_seen
&& g_switch_value
!= 0)
15006 as_bad (_("-G not supported in this configuration"));
15007 g_switch_value
= 0;
15010 if (mips_abi
== NO_ABI
)
15011 mips_abi
= MIPS_DEFAULT_ABI
;
15013 /* The following code determines the architecture.
15014 Similar code was added to GCC 3.3 (see override_options() in
15015 config/mips/mips.c). The GAS and GCC code should be kept in sync
15016 as much as possible. */
15018 if (mips_arch_string
!= 0)
15019 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15021 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15023 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15024 ISA level specified by -mipsN, while arch_info->isa contains
15025 the -march selection (if any). */
15026 if (arch_info
!= 0)
15028 /* -march takes precedence over -mipsN, since it is more descriptive.
15029 There's no harm in specifying both as long as the ISA levels
15031 if (file_mips_opts
.isa
!= arch_info
->isa
)
15032 as_bad (_("-%s conflicts with the other architecture options,"
15033 " which imply -%s"),
15034 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15035 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15038 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15041 if (arch_info
== 0)
15043 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15044 gas_assert (arch_info
);
15047 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15048 as_bad (_("-march=%s is not compatible with the selected ABI"),
15051 file_mips_opts
.arch
= arch_info
->cpu
;
15052 file_mips_opts
.isa
= arch_info
->isa
;
15054 /* Set up initial mips_opts state. */
15055 mips_opts
= file_mips_opts
;
15057 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15058 if (!mips_fix_r5900_explicit
)
15059 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15061 /* The register size inference code is now placed in
15062 file_mips_check_options. */
15064 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15066 if (mips_tune_string
!= 0)
15067 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15069 if (tune_info
== 0)
15070 mips_set_tune (arch_info
);
15072 mips_set_tune (tune_info
);
15074 if (mips_flag_mdebug
< 0)
15075 mips_flag_mdebug
= 0;
15079 mips_init_after_args (void)
15081 /* initialize opcodes */
15082 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15083 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15087 md_pcrel_from (fixS
*fixP
)
15089 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15090 switch (fixP
->fx_r_type
)
15092 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15093 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15094 /* Return the address of the delay slot. */
15097 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15098 case BFD_RELOC_MICROMIPS_JMP
:
15099 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15100 case BFD_RELOC_16_PCREL_S2
:
15101 case BFD_RELOC_MIPS_21_PCREL_S2
:
15102 case BFD_RELOC_MIPS_26_PCREL_S2
:
15103 case BFD_RELOC_MIPS_JMP
:
15104 /* Return the address of the delay slot. */
15107 case BFD_RELOC_MIPS_18_PCREL_S3
:
15108 /* Return the aligned address of the doubleword containing
15109 the instruction. */
15117 /* This is called before the symbol table is processed. In order to
15118 work with gcc when using mips-tfile, we must keep all local labels.
15119 However, in other cases, we want to discard them. If we were
15120 called with -g, but we didn't see any debugging information, it may
15121 mean that gcc is smuggling debugging information through to
15122 mips-tfile, in which case we must generate all local labels. */
15125 mips_frob_file_before_adjust (void)
15127 #ifndef NO_ECOFF_DEBUGGING
15128 if (ECOFF_DEBUGGING
15130 && ! ecoff_debugging_seen
)
15131 flag_keep_locals
= 1;
15135 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15136 the corresponding LO16 reloc. This is called before md_apply_fix and
15137 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15138 relocation operators.
15140 For our purposes, a %lo() expression matches a %got() or %hi()
15143 (a) it refers to the same symbol; and
15144 (b) the offset applied in the %lo() expression is no lower than
15145 the offset applied in the %got() or %hi().
15147 (b) allows us to cope with code like:
15150 lh $4,%lo(foo+2)($4)
15152 ...which is legal on RELA targets, and has a well-defined behaviour
15153 if the user knows that adding 2 to "foo" will not induce a carry to
15156 When several %lo()s match a particular %got() or %hi(), we use the
15157 following rules to distinguish them:
15159 (1) %lo()s with smaller offsets are a better match than %lo()s with
15162 (2) %lo()s with no matching %got() or %hi() are better than those
15163 that already have a matching %got() or %hi().
15165 (3) later %lo()s are better than earlier %lo()s.
15167 These rules are applied in order.
15169 (1) means, among other things, that %lo()s with identical offsets are
15170 chosen if they exist.
15172 (2) means that we won't associate several high-part relocations with
15173 the same low-part relocation unless there's no alternative. Having
15174 several high parts for the same low part is a GNU extension; this rule
15175 allows careful users to avoid it.
15177 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15178 with the last high-part relocation being at the front of the list.
15179 It therefore makes sense to choose the last matching low-part
15180 relocation, all other things being equal. It's also easier
15181 to code that way. */
15184 mips_frob_file (void)
15186 struct mips_hi_fixup
*l
;
15187 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15189 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15191 segment_info_type
*seginfo
;
15192 bfd_boolean matched_lo_p
;
15193 fixS
**hi_pos
, **lo_pos
, **pos
;
15195 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15197 /* If a GOT16 relocation turns out to be against a global symbol,
15198 there isn't supposed to be a matching LO. Ignore %gots against
15199 constants; we'll report an error for those later. */
15200 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15201 && !(l
->fixp
->fx_addsy
15202 && pic_need_relax (l
->fixp
->fx_addsy
)))
15205 /* Check quickly whether the next fixup happens to be a matching %lo. */
15206 if (fixup_has_matching_lo_p (l
->fixp
))
15209 seginfo
= seg_info (l
->seg
);
15211 /* Set HI_POS to the position of this relocation in the chain.
15212 Set LO_POS to the position of the chosen low-part relocation.
15213 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15214 relocation that matches an immediately-preceding high-part
15218 matched_lo_p
= FALSE
;
15219 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15221 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15223 if (*pos
== l
->fixp
)
15226 if ((*pos
)->fx_r_type
== looking_for_rtype
15227 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15228 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15230 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15232 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15235 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15236 && fixup_has_matching_lo_p (*pos
));
15239 /* If we found a match, remove the high-part relocation from its
15240 current position and insert it before the low-part relocation.
15241 Make the offsets match so that fixup_has_matching_lo_p()
15244 We don't warn about unmatched high-part relocations since some
15245 versions of gcc have been known to emit dead "lui ...%hi(...)"
15247 if (lo_pos
!= NULL
)
15249 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15250 if (l
->fixp
->fx_next
!= *lo_pos
)
15252 *hi_pos
= l
->fixp
->fx_next
;
15253 l
->fixp
->fx_next
= *lo_pos
;
15261 mips_force_relocation (fixS
*fixp
)
15263 if (generic_force_reloc (fixp
))
15266 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15267 so that the linker relaxation can update targets. */
15268 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15269 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15270 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15273 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15274 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15275 microMIPS symbols so that we can do cross-mode branch diagnostics
15276 and BAL to JALX conversion by the linker. */
15277 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15278 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15279 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15281 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15284 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15285 if (ISA_IS_R6 (file_mips_opts
.isa
)
15286 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15287 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15288 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15289 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15290 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15291 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15292 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15298 /* Implement TC_FORCE_RELOCATION_ABS. */
15301 mips_force_relocation_abs (fixS
*fixp
)
15303 if (generic_force_reloc (fixp
))
15306 /* These relocations do not have enough bits in the in-place addend
15307 to hold an arbitrary absolute section's offset. */
15308 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15314 /* Read the instruction associated with RELOC from BUF. */
15316 static unsigned int
15317 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15319 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15320 return read_compressed_insn (buf
, 4);
15322 return read_insn (buf
);
15325 /* Write instruction INSN to BUF, given that it has been relocated
15329 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15330 unsigned long insn
)
15332 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15333 write_compressed_insn (buf
, insn
, 4);
15335 write_insn (buf
, insn
);
15338 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15339 to a symbol in another ISA mode, which cannot be converted to JALX. */
15342 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15344 unsigned long opcode
;
15348 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15351 other
= S_GET_OTHER (fixP
->fx_addsy
);
15352 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15353 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15354 switch (fixP
->fx_r_type
)
15356 case BFD_RELOC_MIPS_JMP
:
15357 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15358 case BFD_RELOC_MICROMIPS_JMP
:
15359 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15365 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15366 jump to a symbol in the same ISA mode. */
15369 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15371 unsigned long opcode
;
15375 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15378 other
= S_GET_OTHER (fixP
->fx_addsy
);
15379 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15380 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15381 switch (fixP
->fx_r_type
)
15383 case BFD_RELOC_MIPS_JMP
:
15384 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15385 case BFD_RELOC_MIPS16_JMP
:
15386 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15387 case BFD_RELOC_MICROMIPS_JMP
:
15388 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15394 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15395 to a symbol whose value plus addend is not aligned according to the
15396 ultimate (after linker relaxation) jump instruction's immediate field
15397 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15398 regular MIPS code, to (1 << 2). */
15401 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15403 bfd_boolean micro_to_mips_p
;
15407 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15410 other
= S_GET_OTHER (fixP
->fx_addsy
);
15411 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15412 val
+= fixP
->fx_offset
;
15413 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15414 && !ELF_ST_IS_MICROMIPS (other
));
15415 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15416 != ELF_ST_IS_COMPRESSED (other
));
15419 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15420 to a symbol whose annotation indicates another ISA mode. For absolute
15421 symbols check the ISA bit instead.
15423 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15424 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15425 MIPS symbols and associated with BAL instructions as these instructions
15426 may be converted to JALX by the linker. */
15429 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15431 bfd_boolean absolute_p
;
15432 unsigned long opcode
;
15438 if (mips_ignore_branch_isa
)
15441 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15444 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15445 absolute_p
= bfd_is_abs_section (symsec
);
15447 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15448 other
= S_GET_OTHER (fixP
->fx_addsy
);
15450 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15451 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15452 switch (fixP
->fx_r_type
)
15454 case BFD_RELOC_16_PCREL_S2
:
15455 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15456 && opcode
!= 0x0411);
15457 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15458 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15459 && opcode
!= 0x4060);
15460 case BFD_RELOC_MIPS_21_PCREL_S2
:
15461 case BFD_RELOC_MIPS_26_PCREL_S2
:
15462 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15463 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15464 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15465 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15466 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15467 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15473 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15474 branch instruction pointed to by FIXP is not aligned according to the
15475 branch instruction's immediate field requirement. We need the addend
15476 to preserve the ISA bit and also the sum must not have bit 2 set. We
15477 must explicitly OR in the ISA bit from symbol annotation as the bit
15478 won't be set in the symbol's value then. */
15481 fix_bad_misaligned_branch_p (fixS
*fixP
)
15483 bfd_boolean absolute_p
;
15490 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15493 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15494 absolute_p
= bfd_is_abs_section (symsec
);
15496 val
= S_GET_VALUE (fixP
->fx_addsy
);
15497 other
= S_GET_OTHER (fixP
->fx_addsy
);
15498 off
= fixP
->fx_offset
;
15500 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15501 val
|= ELF_ST_IS_COMPRESSED (other
);
15503 return (val
& 0x3) != isa_bit
;
15506 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15507 and its calculated value VAL. */
15510 fix_validate_branch (fixS
*fixP
, valueT val
)
15512 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15514 _("branch to misaligned address (0x%lx)"),
15515 (long) (val
+ md_pcrel_from (fixP
)));
15516 else if (fix_bad_cross_mode_branch_p (fixP
))
15517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15518 _("branch to a symbol in another ISA mode"));
15519 else if (fix_bad_misaligned_branch_p (fixP
))
15520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15521 _("branch to misaligned address (0x%lx)"),
15522 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15523 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15525 _("cannot encode misaligned addend "
15526 "in the relocatable field (0x%lx)"),
15527 (long) fixP
->fx_offset
);
15530 /* Apply a fixup to the object file. */
15533 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15536 unsigned long insn
;
15537 reloc_howto_type
*howto
;
15539 if (fixP
->fx_pcrel
)
15540 switch (fixP
->fx_r_type
)
15542 case BFD_RELOC_16_PCREL_S2
:
15543 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15544 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15545 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15546 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15547 case BFD_RELOC_32_PCREL
:
15548 case BFD_RELOC_MIPS_21_PCREL_S2
:
15549 case BFD_RELOC_MIPS_26_PCREL_S2
:
15550 case BFD_RELOC_MIPS_18_PCREL_S3
:
15551 case BFD_RELOC_MIPS_19_PCREL_S2
:
15552 case BFD_RELOC_HI16_S_PCREL
:
15553 case BFD_RELOC_LO16_PCREL
:
15557 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15562 _("PC-relative reference to a different section"));
15566 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15567 that have no MIPS ELF equivalent. */
15568 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15570 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15575 gas_assert (fixP
->fx_size
== 2
15576 || fixP
->fx_size
== 4
15577 || fixP
->fx_r_type
== BFD_RELOC_8
15578 || fixP
->fx_r_type
== BFD_RELOC_16
15579 || fixP
->fx_r_type
== BFD_RELOC_64
15580 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15581 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15582 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15583 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15584 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15585 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15586 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15588 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15590 /* Don't treat parts of a composite relocation as done. There are two
15593 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15594 should nevertheless be emitted if the first part is.
15596 (2) In normal usage, composite relocations are never assembly-time
15597 constants. The easiest way of dealing with the pathological
15598 exceptions is to generate a relocation against STN_UNDEF and
15599 leave everything up to the linker. */
15600 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15603 switch (fixP
->fx_r_type
)
15605 case BFD_RELOC_MIPS_TLS_GD
:
15606 case BFD_RELOC_MIPS_TLS_LDM
:
15607 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15608 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15609 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15610 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15611 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15612 case BFD_RELOC_MIPS_TLS_TPREL32
:
15613 case BFD_RELOC_MIPS_TLS_TPREL64
:
15614 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15615 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15616 case BFD_RELOC_MICROMIPS_TLS_GD
:
15617 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15618 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15619 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15620 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15621 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15622 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15623 case BFD_RELOC_MIPS16_TLS_GD
:
15624 case BFD_RELOC_MIPS16_TLS_LDM
:
15625 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15626 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15627 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15628 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15629 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15630 if (fixP
->fx_addsy
)
15631 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15634 _("TLS relocation against a constant"));
15637 case BFD_RELOC_MIPS_JMP
:
15638 case BFD_RELOC_MIPS16_JMP
:
15639 case BFD_RELOC_MICROMIPS_JMP
:
15643 gas_assert (!fixP
->fx_done
);
15645 /* Shift is 2, unusually, for microMIPS JALX. */
15646 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15647 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15652 if (fix_bad_cross_mode_jump_p (fixP
))
15653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15654 _("jump to a symbol in another ISA mode"));
15655 else if (fix_bad_same_mode_jalx_p (fixP
))
15656 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15657 _("JALX to a symbol in the same ISA mode"));
15658 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15660 _("jump to misaligned address (0x%lx)"),
15661 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15662 + fixP
->fx_offset
));
15663 else if (HAVE_IN_PLACE_ADDENDS
15664 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15666 _("cannot encode misaligned addend "
15667 "in the relocatable field (0x%lx)"),
15668 (long) fixP
->fx_offset
);
15670 /* Fall through. */
15672 case BFD_RELOC_MIPS_SHIFT5
:
15673 case BFD_RELOC_MIPS_SHIFT6
:
15674 case BFD_RELOC_MIPS_GOT_DISP
:
15675 case BFD_RELOC_MIPS_GOT_PAGE
:
15676 case BFD_RELOC_MIPS_GOT_OFST
:
15677 case BFD_RELOC_MIPS_SUB
:
15678 case BFD_RELOC_MIPS_INSERT_A
:
15679 case BFD_RELOC_MIPS_INSERT_B
:
15680 case BFD_RELOC_MIPS_DELETE
:
15681 case BFD_RELOC_MIPS_HIGHEST
:
15682 case BFD_RELOC_MIPS_HIGHER
:
15683 case BFD_RELOC_MIPS_SCN_DISP
:
15684 case BFD_RELOC_MIPS_REL16
:
15685 case BFD_RELOC_MIPS_RELGOT
:
15686 case BFD_RELOC_MIPS_JALR
:
15687 case BFD_RELOC_HI16
:
15688 case BFD_RELOC_HI16_S
:
15689 case BFD_RELOC_LO16
:
15690 case BFD_RELOC_GPREL16
:
15691 case BFD_RELOC_MIPS_LITERAL
:
15692 case BFD_RELOC_MIPS_CALL16
:
15693 case BFD_RELOC_MIPS_GOT16
:
15694 case BFD_RELOC_GPREL32
:
15695 case BFD_RELOC_MIPS_GOT_HI16
:
15696 case BFD_RELOC_MIPS_GOT_LO16
:
15697 case BFD_RELOC_MIPS_CALL_HI16
:
15698 case BFD_RELOC_MIPS_CALL_LO16
:
15699 case BFD_RELOC_HI16_S_PCREL
:
15700 case BFD_RELOC_LO16_PCREL
:
15701 case BFD_RELOC_MIPS16_GPREL
:
15702 case BFD_RELOC_MIPS16_GOT16
:
15703 case BFD_RELOC_MIPS16_CALL16
:
15704 case BFD_RELOC_MIPS16_HI16
:
15705 case BFD_RELOC_MIPS16_HI16_S
:
15706 case BFD_RELOC_MIPS16_LO16
:
15707 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15708 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15709 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15710 case BFD_RELOC_MICROMIPS_SUB
:
15711 case BFD_RELOC_MICROMIPS_HIGHEST
:
15712 case BFD_RELOC_MICROMIPS_HIGHER
:
15713 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15714 case BFD_RELOC_MICROMIPS_JALR
:
15715 case BFD_RELOC_MICROMIPS_HI16
:
15716 case BFD_RELOC_MICROMIPS_HI16_S
:
15717 case BFD_RELOC_MICROMIPS_LO16
:
15718 case BFD_RELOC_MICROMIPS_GPREL16
:
15719 case BFD_RELOC_MICROMIPS_LITERAL
:
15720 case BFD_RELOC_MICROMIPS_CALL16
:
15721 case BFD_RELOC_MICROMIPS_GOT16
:
15722 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15723 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15724 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15725 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15726 case BFD_RELOC_MIPS_EH
:
15731 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15733 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15734 if (mips16_reloc_p (fixP
->fx_r_type
))
15735 insn
|= mips16_immed_extend (value
, 16);
15737 insn
|= (value
& 0xffff);
15738 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15742 _("unsupported constant in relocation"));
15747 /* This is handled like BFD_RELOC_32, but we output a sign
15748 extended value if we are only 32 bits. */
15751 if (8 <= sizeof (valueT
))
15752 md_number_to_chars (buf
, *valP
, 8);
15757 if ((*valP
& 0x80000000) != 0)
15761 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15762 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15767 case BFD_RELOC_RVA
:
15769 case BFD_RELOC_32_PCREL
:
15772 /* If we are deleting this reloc entry, we must fill in the
15773 value now. This can happen if we have a .word which is not
15774 resolved when it appears but is later defined. */
15776 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15779 case BFD_RELOC_MIPS_21_PCREL_S2
:
15780 fix_validate_branch (fixP
, *valP
);
15781 if (!fixP
->fx_done
)
15784 if (*valP
+ 0x400000 <= 0x7fffff)
15786 insn
= read_insn (buf
);
15787 insn
|= (*valP
>> 2) & 0x1fffff;
15788 write_insn (buf
, insn
);
15791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15792 _("branch out of range"));
15795 case BFD_RELOC_MIPS_26_PCREL_S2
:
15796 fix_validate_branch (fixP
, *valP
);
15797 if (!fixP
->fx_done
)
15800 if (*valP
+ 0x8000000 <= 0xfffffff)
15802 insn
= read_insn (buf
);
15803 insn
|= (*valP
>> 2) & 0x3ffffff;
15804 write_insn (buf
, insn
);
15807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15808 _("branch out of range"));
15811 case BFD_RELOC_MIPS_18_PCREL_S3
:
15812 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15814 _("PC-relative access using misaligned symbol (%lx)"),
15815 (long) S_GET_VALUE (fixP
->fx_addsy
));
15816 if ((fixP
->fx_offset
& 0x7) != 0)
15817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15818 _("PC-relative access using misaligned offset (%lx)"),
15819 (long) fixP
->fx_offset
);
15820 if (!fixP
->fx_done
)
15823 if (*valP
+ 0x100000 <= 0x1fffff)
15825 insn
= read_insn (buf
);
15826 insn
|= (*valP
>> 3) & 0x3ffff;
15827 write_insn (buf
, insn
);
15830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15831 _("PC-relative access out of range"));
15834 case BFD_RELOC_MIPS_19_PCREL_S2
:
15835 if ((*valP
& 0x3) != 0)
15836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15837 _("PC-relative access to misaligned address (%lx)"),
15839 if (!fixP
->fx_done
)
15842 if (*valP
+ 0x100000 <= 0x1fffff)
15844 insn
= read_insn (buf
);
15845 insn
|= (*valP
>> 2) & 0x7ffff;
15846 write_insn (buf
, insn
);
15849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15850 _("PC-relative access out of range"));
15853 case BFD_RELOC_16_PCREL_S2
:
15854 fix_validate_branch (fixP
, *valP
);
15856 /* We need to save the bits in the instruction since fixup_segment()
15857 might be deleting the relocation entry (i.e., a branch within
15858 the current segment). */
15859 if (! fixP
->fx_done
)
15862 /* Update old instruction data. */
15863 insn
= read_insn (buf
);
15865 if (*valP
+ 0x20000 <= 0x3ffff)
15867 insn
|= (*valP
>> 2) & 0xffff;
15868 write_insn (buf
, insn
);
15870 else if (fixP
->fx_tcbit2
15872 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15873 && (fixP
->fx_frag
->fr_address
15874 < text_section
->vma
+ bfd_get_section_size (text_section
))
15875 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15876 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15877 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15879 /* The branch offset is too large. If this is an
15880 unconditional branch, and we are not generating PIC code,
15881 we can convert it to an absolute jump instruction. */
15882 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15883 insn
= 0x0c000000; /* jal */
15885 insn
= 0x08000000; /* j */
15886 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15888 fixP
->fx_addsy
= section_symbol (text_section
);
15889 *valP
+= md_pcrel_from (fixP
);
15890 write_insn (buf
, insn
);
15894 /* If we got here, we have branch-relaxation disabled,
15895 and there's nothing we can do to fix this instruction
15896 without turning it into a longer sequence. */
15897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15898 _("branch out of range"));
15902 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15903 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15904 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15905 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15906 gas_assert (!fixP
->fx_done
);
15907 if (fix_bad_cross_mode_branch_p (fixP
))
15908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15909 _("branch to a symbol in another ISA mode"));
15910 else if (fixP
->fx_addsy
15911 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15912 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15913 && (fixP
->fx_offset
& 0x1) != 0)
15914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15915 _("branch to misaligned address (0x%lx)"),
15916 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15917 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15919 _("cannot encode misaligned addend "
15920 "in the relocatable field (0x%lx)"),
15921 (long) fixP
->fx_offset
);
15924 case BFD_RELOC_VTABLE_INHERIT
:
15927 && !S_IS_DEFINED (fixP
->fx_addsy
)
15928 && !S_IS_WEAK (fixP
->fx_addsy
))
15929 S_SET_WEAK (fixP
->fx_addsy
);
15932 case BFD_RELOC_NONE
:
15933 case BFD_RELOC_VTABLE_ENTRY
:
15941 /* Remember value for tc_gen_reloc. */
15942 fixP
->fx_addnumber
= *valP
;
15952 c
= get_symbol_name (&name
);
15953 p
= (symbolS
*) symbol_find_or_make (name
);
15954 (void) restore_line_pointer (c
);
15958 /* Align the current frag to a given power of two. If a particular
15959 fill byte should be used, FILL points to an integer that contains
15960 that byte, otherwise FILL is null.
15962 This function used to have the comment:
15964 The MIPS assembler also automatically adjusts any preceding label.
15966 The implementation therefore applied the adjustment to a maximum of
15967 one label. However, other label adjustments are applied to batches
15968 of labels, and adjusting just one caused problems when new labels
15969 were added for the sake of debugging or unwind information.
15970 We therefore adjust all preceding labels (given as LABELS) instead. */
15973 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15975 mips_emit_delays ();
15976 mips_record_compressed_mode ();
15977 if (fill
== NULL
&& subseg_text_p (now_seg
))
15978 frag_align_code (to
, 0);
15980 frag_align (to
, fill
? *fill
: 0, 0);
15981 record_alignment (now_seg
, to
);
15982 mips_move_labels (labels
, FALSE
);
15985 /* Align to a given power of two. .align 0 turns off the automatic
15986 alignment used by the data creating pseudo-ops. */
15989 s_align (int x ATTRIBUTE_UNUSED
)
15991 int temp
, fill_value
, *fill_ptr
;
15992 long max_alignment
= 28;
15994 /* o Note that the assembler pulls down any immediately preceding label
15995 to the aligned address.
15996 o It's not documented but auto alignment is reinstated by
15997 a .align pseudo instruction.
15998 o Note also that after auto alignment is turned off the mips assembler
15999 issues an error on attempt to assemble an improperly aligned data item.
16002 temp
= get_absolute_expression ();
16003 if (temp
> max_alignment
)
16004 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16007 as_warn (_("alignment negative, 0 assumed"));
16010 if (*input_line_pointer
== ',')
16012 ++input_line_pointer
;
16013 fill_value
= get_absolute_expression ();
16014 fill_ptr
= &fill_value
;
16020 segment_info_type
*si
= seg_info (now_seg
);
16021 struct insn_label_list
*l
= si
->label_list
;
16022 /* Auto alignment should be switched on by next section change. */
16024 mips_align (temp
, fill_ptr
, l
);
16031 demand_empty_rest_of_line ();
16035 s_change_sec (int sec
)
16039 /* The ELF backend needs to know that we are changing sections, so
16040 that .previous works correctly. We could do something like check
16041 for an obj_section_change_hook macro, but that might be confusing
16042 as it would not be appropriate to use it in the section changing
16043 functions in read.c, since obj-elf.c intercepts those. FIXME:
16044 This should be cleaner, somehow. */
16045 obj_elf_section_change_hook ();
16047 mips_emit_delays ();
16058 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16059 demand_empty_rest_of_line ();
16063 seg
= subseg_new (RDATA_SECTION_NAME
,
16064 (subsegT
) get_absolute_expression ());
16065 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16066 | SEC_READONLY
| SEC_RELOC
16068 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16069 record_alignment (seg
, 4);
16070 demand_empty_rest_of_line ();
16074 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16075 bfd_set_section_flags (stdoutput
, seg
,
16076 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16077 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16078 record_alignment (seg
, 4);
16079 demand_empty_rest_of_line ();
16083 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16084 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16085 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16086 record_alignment (seg
, 4);
16087 demand_empty_rest_of_line ();
16095 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16098 char *section_name
;
16103 int section_entry_size
;
16104 int section_alignment
;
16106 saved_ilp
= input_line_pointer
;
16107 endc
= get_symbol_name (§ion_name
);
16108 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16110 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16112 /* Do we have .section Name<,"flags">? */
16113 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16115 /* Just after name is now '\0'. */
16116 (void) restore_line_pointer (endc
);
16117 input_line_pointer
= saved_ilp
;
16118 obj_elf_section (ignore
);
16122 section_name
= xstrdup (section_name
);
16123 c
= restore_line_pointer (endc
);
16125 input_line_pointer
++;
16127 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16129 section_type
= get_absolute_expression ();
16133 if (*input_line_pointer
++ == ',')
16134 section_flag
= get_absolute_expression ();
16138 if (*input_line_pointer
++ == ',')
16139 section_entry_size
= get_absolute_expression ();
16141 section_entry_size
= 0;
16143 if (*input_line_pointer
++ == ',')
16144 section_alignment
= get_absolute_expression ();
16146 section_alignment
= 0;
16148 /* FIXME: really ignore? */
16149 (void) section_alignment
;
16151 /* When using the generic form of .section (as implemented by obj-elf.c),
16152 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16153 traditionally had to fall back on the more common @progbits instead.
16155 There's nothing really harmful in this, since bfd will correct
16156 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16157 means that, for backwards compatibility, the special_section entries
16158 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16160 Even so, we shouldn't force users of the MIPS .section syntax to
16161 incorrectly label the sections as SHT_PROGBITS. The best compromise
16162 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16163 generic type-checking code. */
16164 if (section_type
== SHT_MIPS_DWARF
)
16165 section_type
= SHT_PROGBITS
;
16167 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
16168 section_entry_size
, 0, 0, 0);
16170 if (now_seg
->name
!= section_name
)
16171 free (section_name
);
16175 mips_enable_auto_align (void)
16181 s_cons (int log_size
)
16183 segment_info_type
*si
= seg_info (now_seg
);
16184 struct insn_label_list
*l
= si
->label_list
;
16186 mips_emit_delays ();
16187 if (log_size
> 0 && auto_align
)
16188 mips_align (log_size
, 0, l
);
16189 cons (1 << log_size
);
16190 mips_clear_insn_labels ();
16194 s_float_cons (int type
)
16196 segment_info_type
*si
= seg_info (now_seg
);
16197 struct insn_label_list
*l
= si
->label_list
;
16199 mips_emit_delays ();
16204 mips_align (3, 0, l
);
16206 mips_align (2, 0, l
);
16210 mips_clear_insn_labels ();
16213 /* Handle .globl. We need to override it because on Irix 5 you are
16216 where foo is an undefined symbol, to mean that foo should be
16217 considered to be the address of a function. */
16220 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16229 c
= get_symbol_name (&name
);
16230 symbolP
= symbol_find_or_make (name
);
16231 S_SET_EXTERNAL (symbolP
);
16233 *input_line_pointer
= c
;
16234 SKIP_WHITESPACE_AFTER_NAME ();
16236 /* On Irix 5, every global symbol that is not explicitly labelled as
16237 being a function is apparently labelled as being an object. */
16240 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16241 && (*input_line_pointer
!= ','))
16246 c
= get_symbol_name (&secname
);
16247 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16249 as_bad (_("%s: no such section"), secname
);
16250 (void) restore_line_pointer (c
);
16252 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16253 flag
= BSF_FUNCTION
;
16256 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16258 c
= *input_line_pointer
;
16261 input_line_pointer
++;
16262 SKIP_WHITESPACE ();
16263 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16269 demand_empty_rest_of_line ();
16273 s_option (int x ATTRIBUTE_UNUSED
)
16278 c
= get_symbol_name (&opt
);
16282 /* FIXME: What does this mean? */
16284 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16288 i
= atoi (opt
+ 3);
16289 if (i
!= 0 && i
!= 2)
16290 as_bad (_(".option pic%d not supported"), i
);
16291 else if (mips_pic
== VXWORKS_PIC
)
16292 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16297 mips_pic
= SVR4_PIC
;
16298 mips_abicalls
= TRUE
;
16301 if (mips_pic
== SVR4_PIC
)
16303 if (g_switch_seen
&& g_switch_value
!= 0)
16304 as_warn (_("-G may not be used with SVR4 PIC code"));
16305 g_switch_value
= 0;
16306 bfd_set_gp_size (stdoutput
, 0);
16310 as_warn (_("unrecognized option \"%s\""), opt
);
16312 (void) restore_line_pointer (c
);
16313 demand_empty_rest_of_line ();
16316 /* This structure is used to hold a stack of .set values. */
16318 struct mips_option_stack
16320 struct mips_option_stack
*next
;
16321 struct mips_set_options options
;
16324 static struct mips_option_stack
*mips_opts_stack
;
16326 /* Return status for .set/.module option handling. */
16328 enum code_option_type
16330 /* Unrecognized option. */
16331 OPTION_TYPE_BAD
= -1,
16333 /* Ordinary option. */
16334 OPTION_TYPE_NORMAL
,
16336 /* ISA changing option. */
16340 /* Handle common .set/.module options. Return status indicating option
16343 static enum code_option_type
16344 parse_code_option (char * name
)
16346 bfd_boolean isa_set
= FALSE
;
16347 const struct mips_ase
*ase
;
16349 if (strncmp (name
, "at=", 3) == 0)
16351 char *s
= name
+ 3;
16353 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16354 as_bad (_("unrecognized register name `%s'"), s
);
16356 else if (strcmp (name
, "at") == 0)
16357 mips_opts
.at
= ATREG
;
16358 else if (strcmp (name
, "noat") == 0)
16359 mips_opts
.at
= ZERO
;
16360 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16361 mips_opts
.nomove
= 0;
16362 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16363 mips_opts
.nomove
= 1;
16364 else if (strcmp (name
, "bopt") == 0)
16365 mips_opts
.nobopt
= 0;
16366 else if (strcmp (name
, "nobopt") == 0)
16367 mips_opts
.nobopt
= 1;
16368 else if (strcmp (name
, "gp=32") == 0)
16370 else if (strcmp (name
, "gp=64") == 0)
16372 else if (strcmp (name
, "fp=32") == 0)
16374 else if (strcmp (name
, "fp=xx") == 0)
16376 else if (strcmp (name
, "fp=64") == 0)
16378 else if (strcmp (name
, "softfloat") == 0)
16379 mips_opts
.soft_float
= 1;
16380 else if (strcmp (name
, "hardfloat") == 0)
16381 mips_opts
.soft_float
= 0;
16382 else if (strcmp (name
, "singlefloat") == 0)
16383 mips_opts
.single_float
= 1;
16384 else if (strcmp (name
, "doublefloat") == 0)
16385 mips_opts
.single_float
= 0;
16386 else if (strcmp (name
, "nooddspreg") == 0)
16387 mips_opts
.oddspreg
= 0;
16388 else if (strcmp (name
, "oddspreg") == 0)
16389 mips_opts
.oddspreg
= 1;
16390 else if (strcmp (name
, "mips16") == 0
16391 || strcmp (name
, "MIPS-16") == 0)
16392 mips_opts
.mips16
= 1;
16393 else if (strcmp (name
, "nomips16") == 0
16394 || strcmp (name
, "noMIPS-16") == 0)
16395 mips_opts
.mips16
= 0;
16396 else if (strcmp (name
, "micromips") == 0)
16397 mips_opts
.micromips
= 1;
16398 else if (strcmp (name
, "nomicromips") == 0)
16399 mips_opts
.micromips
= 0;
16400 else if (name
[0] == 'n'
16402 && (ase
= mips_lookup_ase (name
+ 2)))
16403 mips_set_ase (ase
, &mips_opts
, FALSE
);
16404 else if ((ase
= mips_lookup_ase (name
)))
16405 mips_set_ase (ase
, &mips_opts
, TRUE
);
16406 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16408 /* Permit the user to change the ISA and architecture on the fly.
16409 Needless to say, misuse can cause serious problems. */
16410 if (strncmp (name
, "arch=", 5) == 0)
16412 const struct mips_cpu_info
*p
;
16414 p
= mips_parse_cpu ("internal use", name
+ 5);
16416 as_bad (_("unknown architecture %s"), name
+ 5);
16419 mips_opts
.arch
= p
->cpu
;
16420 mips_opts
.isa
= p
->isa
;
16424 else if (strncmp (name
, "mips", 4) == 0)
16426 const struct mips_cpu_info
*p
;
16428 p
= mips_parse_cpu ("internal use", name
);
16430 as_bad (_("unknown ISA level %s"), name
+ 4);
16433 mips_opts
.arch
= p
->cpu
;
16434 mips_opts
.isa
= p
->isa
;
16439 as_bad (_("unknown ISA or architecture %s"), name
);
16441 else if (strcmp (name
, "autoextend") == 0)
16442 mips_opts
.noautoextend
= 0;
16443 else if (strcmp (name
, "noautoextend") == 0)
16444 mips_opts
.noautoextend
= 1;
16445 else if (strcmp (name
, "insn32") == 0)
16446 mips_opts
.insn32
= TRUE
;
16447 else if (strcmp (name
, "noinsn32") == 0)
16448 mips_opts
.insn32
= FALSE
;
16449 else if (strcmp (name
, "sym32") == 0)
16450 mips_opts
.sym32
= TRUE
;
16451 else if (strcmp (name
, "nosym32") == 0)
16452 mips_opts
.sym32
= FALSE
;
16454 return OPTION_TYPE_BAD
;
16456 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16459 /* Handle the .set pseudo-op. */
16462 s_mipsset (int x ATTRIBUTE_UNUSED
)
16464 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16465 char *name
= input_line_pointer
, ch
;
16467 file_mips_check_options ();
16469 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16470 ++input_line_pointer
;
16471 ch
= *input_line_pointer
;
16472 *input_line_pointer
= '\0';
16474 if (strchr (name
, ','))
16476 /* Generic ".set" directive; use the generic handler. */
16477 *input_line_pointer
= ch
;
16478 input_line_pointer
= name
;
16483 if (strcmp (name
, "reorder") == 0)
16485 if (mips_opts
.noreorder
)
16488 else if (strcmp (name
, "noreorder") == 0)
16490 if (!mips_opts
.noreorder
)
16491 start_noreorder ();
16493 else if (strcmp (name
, "macro") == 0)
16494 mips_opts
.warn_about_macros
= 0;
16495 else if (strcmp (name
, "nomacro") == 0)
16497 if (mips_opts
.noreorder
== 0)
16498 as_bad (_("`noreorder' must be set before `nomacro'"));
16499 mips_opts
.warn_about_macros
= 1;
16501 else if (strcmp (name
, "gp=default") == 0)
16502 mips_opts
.gp
= file_mips_opts
.gp
;
16503 else if (strcmp (name
, "fp=default") == 0)
16504 mips_opts
.fp
= file_mips_opts
.fp
;
16505 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16507 mips_opts
.isa
= file_mips_opts
.isa
;
16508 mips_opts
.arch
= file_mips_opts
.arch
;
16509 mips_opts
.gp
= file_mips_opts
.gp
;
16510 mips_opts
.fp
= file_mips_opts
.fp
;
16512 else if (strcmp (name
, "push") == 0)
16514 struct mips_option_stack
*s
;
16516 s
= XNEW (struct mips_option_stack
);
16517 s
->next
= mips_opts_stack
;
16518 s
->options
= mips_opts
;
16519 mips_opts_stack
= s
;
16521 else if (strcmp (name
, "pop") == 0)
16523 struct mips_option_stack
*s
;
16525 s
= mips_opts_stack
;
16527 as_bad (_(".set pop with no .set push"));
16530 /* If we're changing the reorder mode we need to handle
16531 delay slots correctly. */
16532 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16533 start_noreorder ();
16534 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16537 mips_opts
= s
->options
;
16538 mips_opts_stack
= s
->next
;
16544 type
= parse_code_option (name
);
16545 if (type
== OPTION_TYPE_BAD
)
16546 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16549 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16550 registers based on what is supported by the arch/cpu. */
16551 if (type
== OPTION_TYPE_ISA
)
16553 switch (mips_opts
.isa
)
16558 /* MIPS I cannot support FPXX. */
16560 /* fall-through. */
16567 if (mips_opts
.fp
!= 0)
16583 if (mips_opts
.fp
!= 0)
16585 if (mips_opts
.arch
== CPU_R5900
)
16592 as_bad (_("unknown ISA level %s"), name
+ 4);
16597 mips_check_options (&mips_opts
, FALSE
);
16599 mips_check_isa_supports_ases ();
16600 *input_line_pointer
= ch
;
16601 demand_empty_rest_of_line ();
16604 /* Handle the .module pseudo-op. */
16607 s_module (int ignore ATTRIBUTE_UNUSED
)
16609 char *name
= input_line_pointer
, ch
;
16611 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16612 ++input_line_pointer
;
16613 ch
= *input_line_pointer
;
16614 *input_line_pointer
= '\0';
16616 if (!file_mips_opts_checked
)
16618 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16619 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16621 /* Update module level settings from mips_opts. */
16622 file_mips_opts
= mips_opts
;
16625 as_bad (_(".module is not permitted after generating code"));
16627 *input_line_pointer
= ch
;
16628 demand_empty_rest_of_line ();
16631 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16632 .option pic2. It means to generate SVR4 PIC calls. */
16635 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16637 mips_pic
= SVR4_PIC
;
16638 mips_abicalls
= TRUE
;
16640 if (g_switch_seen
&& g_switch_value
!= 0)
16641 as_warn (_("-G may not be used with SVR4 PIC code"));
16642 g_switch_value
= 0;
16644 bfd_set_gp_size (stdoutput
, 0);
16645 demand_empty_rest_of_line ();
16648 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16649 PIC code. It sets the $gp register for the function based on the
16650 function address, which is in the register named in the argument.
16651 This uses a relocation against _gp_disp, which is handled specially
16652 by the linker. The result is:
16653 lui $gp,%hi(_gp_disp)
16654 addiu $gp,$gp,%lo(_gp_disp)
16655 addu $gp,$gp,.cpload argument
16656 The .cpload argument is normally $25 == $t9.
16658 The -mno-shared option changes this to:
16659 lui $gp,%hi(__gnu_local_gp)
16660 addiu $gp,$gp,%lo(__gnu_local_gp)
16661 and the argument is ignored. This saves an instruction, but the
16662 resulting code is not position independent; it uses an absolute
16663 address for __gnu_local_gp. Thus code assembled with -mno-shared
16664 can go into an ordinary executable, but not into a shared library. */
16667 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16673 file_mips_check_options ();
16675 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16676 .cpload is ignored. */
16677 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16683 if (mips_opts
.mips16
)
16685 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16686 ignore_rest_of_line ();
16690 /* .cpload should be in a .set noreorder section. */
16691 if (mips_opts
.noreorder
== 0)
16692 as_warn (_(".cpload not in noreorder section"));
16694 reg
= tc_get_register (0);
16696 /* If we need to produce a 64-bit address, we are better off using
16697 the default instruction sequence. */
16698 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16700 ex
.X_op
= O_symbol
;
16701 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16703 ex
.X_op_symbol
= NULL
;
16704 ex
.X_add_number
= 0;
16706 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16707 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16709 mips_mark_labels ();
16710 mips_assembling_insn
= TRUE
;
16713 macro_build_lui (&ex
, mips_gp_register
);
16714 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16715 mips_gp_register
, BFD_RELOC_LO16
);
16717 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16718 mips_gp_register
, reg
);
16721 mips_assembling_insn
= FALSE
;
16722 demand_empty_rest_of_line ();
16725 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16726 .cpsetup $reg1, offset|$reg2, label
16728 If offset is given, this results in:
16729 sd $gp, offset($sp)
16730 lui $gp, %hi(%neg(%gp_rel(label)))
16731 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16732 daddu $gp, $gp, $reg1
16734 If $reg2 is given, this results in:
16736 lui $gp, %hi(%neg(%gp_rel(label)))
16737 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16738 daddu $gp, $gp, $reg1
16739 $reg1 is normally $25 == $t9.
16741 The -mno-shared option replaces the last three instructions with
16743 addiu $gp,$gp,%lo(_gp) */
16746 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16748 expressionS ex_off
;
16749 expressionS ex_sym
;
16752 file_mips_check_options ();
16754 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16755 We also need NewABI support. */
16756 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16762 if (mips_opts
.mips16
)
16764 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16765 ignore_rest_of_line ();
16769 reg1
= tc_get_register (0);
16770 SKIP_WHITESPACE ();
16771 if (*input_line_pointer
!= ',')
16773 as_bad (_("missing argument separator ',' for .cpsetup"));
16777 ++input_line_pointer
;
16778 SKIP_WHITESPACE ();
16779 if (*input_line_pointer
== '$')
16781 mips_cpreturn_register
= tc_get_register (0);
16782 mips_cpreturn_offset
= -1;
16786 mips_cpreturn_offset
= get_absolute_expression ();
16787 mips_cpreturn_register
= -1;
16789 SKIP_WHITESPACE ();
16790 if (*input_line_pointer
!= ',')
16792 as_bad (_("missing argument separator ',' for .cpsetup"));
16796 ++input_line_pointer
;
16797 SKIP_WHITESPACE ();
16798 expression (&ex_sym
);
16800 mips_mark_labels ();
16801 mips_assembling_insn
= TRUE
;
16804 if (mips_cpreturn_register
== -1)
16806 ex_off
.X_op
= O_constant
;
16807 ex_off
.X_add_symbol
= NULL
;
16808 ex_off
.X_op_symbol
= NULL
;
16809 ex_off
.X_add_number
= mips_cpreturn_offset
;
16811 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16812 BFD_RELOC_LO16
, SP
);
16815 move_register (mips_cpreturn_register
, mips_gp_register
);
16817 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16819 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16820 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16823 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16824 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16825 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16827 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16828 mips_gp_register
, reg1
);
16834 ex
.X_op
= O_symbol
;
16835 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16836 ex
.X_op_symbol
= NULL
;
16837 ex
.X_add_number
= 0;
16839 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16840 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16842 macro_build_lui (&ex
, mips_gp_register
);
16843 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16844 mips_gp_register
, BFD_RELOC_LO16
);
16849 mips_assembling_insn
= FALSE
;
16850 demand_empty_rest_of_line ();
16854 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16856 file_mips_check_options ();
16858 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16859 .cplocal is ignored. */
16860 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16866 if (mips_opts
.mips16
)
16868 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16869 ignore_rest_of_line ();
16873 mips_gp_register
= tc_get_register (0);
16874 demand_empty_rest_of_line ();
16877 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16878 offset from $sp. The offset is remembered, and after making a PIC
16879 call $gp is restored from that location. */
16882 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16886 file_mips_check_options ();
16888 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16889 .cprestore is ignored. */
16890 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16896 if (mips_opts
.mips16
)
16898 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16899 ignore_rest_of_line ();
16903 mips_cprestore_offset
= get_absolute_expression ();
16904 mips_cprestore_valid
= 1;
16906 ex
.X_op
= O_constant
;
16907 ex
.X_add_symbol
= NULL
;
16908 ex
.X_op_symbol
= NULL
;
16909 ex
.X_add_number
= mips_cprestore_offset
;
16911 mips_mark_labels ();
16912 mips_assembling_insn
= TRUE
;
16915 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16916 SP
, HAVE_64BIT_ADDRESSES
);
16919 mips_assembling_insn
= FALSE
;
16920 demand_empty_rest_of_line ();
16923 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16924 was given in the preceding .cpsetup, it results in:
16925 ld $gp, offset($sp)
16927 If a register $reg2 was given there, it results in:
16928 or $gp, $reg2, $0 */
16931 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16935 file_mips_check_options ();
16937 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16938 We also need NewABI support. */
16939 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16945 if (mips_opts
.mips16
)
16947 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16948 ignore_rest_of_line ();
16952 mips_mark_labels ();
16953 mips_assembling_insn
= TRUE
;
16956 if (mips_cpreturn_register
== -1)
16958 ex
.X_op
= O_constant
;
16959 ex
.X_add_symbol
= NULL
;
16960 ex
.X_op_symbol
= NULL
;
16961 ex
.X_add_number
= mips_cpreturn_offset
;
16963 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16966 move_register (mips_gp_register
, mips_cpreturn_register
);
16970 mips_assembling_insn
= FALSE
;
16971 demand_empty_rest_of_line ();
16974 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16975 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16976 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16977 debug information or MIPS16 TLS. */
16980 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16981 bfd_reloc_code_real_type rtype
)
16988 if (ex
.X_op
!= O_symbol
)
16990 as_bad (_("unsupported use of %s"), dirstr
);
16991 ignore_rest_of_line ();
16994 p
= frag_more (bytes
);
16995 md_number_to_chars (p
, 0, bytes
);
16996 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16997 demand_empty_rest_of_line ();
16998 mips_clear_insn_labels ();
17001 /* Handle .dtprelword. */
17004 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17006 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17009 /* Handle .dtpreldword. */
17012 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17014 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17017 /* Handle .tprelword. */
17020 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17022 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17025 /* Handle .tpreldword. */
17028 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17030 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17033 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17034 code. It sets the offset to use in gp_rel relocations. */
17037 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17039 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17040 We also need NewABI support. */
17041 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17047 mips_gprel_offset
= get_absolute_expression ();
17049 demand_empty_rest_of_line ();
17052 /* Handle the .gpword pseudo-op. This is used when generating PIC
17053 code. It generates a 32 bit GP relative reloc. */
17056 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17058 segment_info_type
*si
;
17059 struct insn_label_list
*l
;
17063 /* When not generating PIC code, this is treated as .word. */
17064 if (mips_pic
!= SVR4_PIC
)
17070 si
= seg_info (now_seg
);
17071 l
= si
->label_list
;
17072 mips_emit_delays ();
17074 mips_align (2, 0, l
);
17077 mips_clear_insn_labels ();
17079 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17081 as_bad (_("unsupported use of .gpword"));
17082 ignore_rest_of_line ();
17086 md_number_to_chars (p
, 0, 4);
17087 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17088 BFD_RELOC_GPREL32
);
17090 demand_empty_rest_of_line ();
17094 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17096 segment_info_type
*si
;
17097 struct insn_label_list
*l
;
17101 /* When not generating PIC code, this is treated as .dword. */
17102 if (mips_pic
!= SVR4_PIC
)
17108 si
= seg_info (now_seg
);
17109 l
= si
->label_list
;
17110 mips_emit_delays ();
17112 mips_align (3, 0, l
);
17115 mips_clear_insn_labels ();
17117 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17119 as_bad (_("unsupported use of .gpdword"));
17120 ignore_rest_of_line ();
17124 md_number_to_chars (p
, 0, 8);
17125 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17126 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17128 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17129 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17130 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17132 demand_empty_rest_of_line ();
17135 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17136 tables. It generates a R_MIPS_EH reloc. */
17139 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17144 mips_emit_delays ();
17147 mips_clear_insn_labels ();
17149 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17151 as_bad (_("unsupported use of .ehword"));
17152 ignore_rest_of_line ();
17156 md_number_to_chars (p
, 0, 4);
17157 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17158 BFD_RELOC_32_PCREL
);
17160 demand_empty_rest_of_line ();
17163 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17164 tables in SVR4 PIC code. */
17167 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17171 file_mips_check_options ();
17173 /* This is ignored when not generating SVR4 PIC code. */
17174 if (mips_pic
!= SVR4_PIC
)
17180 mips_mark_labels ();
17181 mips_assembling_insn
= TRUE
;
17183 /* Add $gp to the register named as an argument. */
17185 reg
= tc_get_register (0);
17186 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17189 mips_assembling_insn
= FALSE
;
17190 demand_empty_rest_of_line ();
17193 /* Handle the .insn pseudo-op. This marks instruction labels in
17194 mips16/micromips mode. This permits the linker to handle them specially,
17195 such as generating jalx instructions when needed. We also make
17196 them odd for the duration of the assembly, in order to generate the
17197 right sort of code. We will make them even in the adjust_symtab
17198 routine, while leaving them marked. This is convenient for the
17199 debugger and the disassembler. The linker knows to make them odd
17203 s_insn (int ignore ATTRIBUTE_UNUSED
)
17205 file_mips_check_options ();
17206 file_ase_mips16
|= mips_opts
.mips16
;
17207 file_ase_micromips
|= mips_opts
.micromips
;
17209 mips_mark_labels ();
17211 demand_empty_rest_of_line ();
17214 /* Handle the .nan pseudo-op. */
17217 s_nan (int ignore ATTRIBUTE_UNUSED
)
17219 static const char str_legacy
[] = "legacy";
17220 static const char str_2008
[] = "2008";
17223 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17225 if (i
== sizeof (str_2008
) - 1
17226 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17228 else if (i
== sizeof (str_legacy
) - 1
17229 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17231 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17234 as_bad (_("`%s' does not support legacy NaN"),
17235 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17238 as_bad (_("bad .nan directive"));
17240 input_line_pointer
+= i
;
17241 demand_empty_rest_of_line ();
17244 /* Handle a .stab[snd] directive. Ideally these directives would be
17245 implemented in a transparent way, so that removing them would not
17246 have any effect on the generated instructions. However, s_stab
17247 internally changes the section, so in practice we need to decide
17248 now whether the preceding label marks compressed code. We do not
17249 support changing the compression mode of a label after a .stab*
17250 directive, such as in:
17256 so the current mode wins. */
17259 s_mips_stab (int type
)
17261 file_mips_check_options ();
17262 mips_mark_labels ();
17266 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17269 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17276 c
= get_symbol_name (&name
);
17277 symbolP
= symbol_find_or_make (name
);
17278 S_SET_WEAK (symbolP
);
17279 *input_line_pointer
= c
;
17281 SKIP_WHITESPACE_AFTER_NAME ();
17283 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17285 if (S_IS_DEFINED (symbolP
))
17287 as_bad (_("ignoring attempt to redefine symbol %s"),
17288 S_GET_NAME (symbolP
));
17289 ignore_rest_of_line ();
17293 if (*input_line_pointer
== ',')
17295 ++input_line_pointer
;
17296 SKIP_WHITESPACE ();
17300 if (exp
.X_op
!= O_symbol
)
17302 as_bad (_("bad .weakext directive"));
17303 ignore_rest_of_line ();
17306 symbol_set_value_expression (symbolP
, &exp
);
17309 demand_empty_rest_of_line ();
17312 /* Parse a register string into a number. Called from the ECOFF code
17313 to parse .frame. The argument is non-zero if this is the frame
17314 register, so that we can record it in mips_frame_reg. */
17317 tc_get_register (int frame
)
17321 SKIP_WHITESPACE ();
17322 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17326 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17327 mips_frame_reg_valid
= 1;
17328 mips_cprestore_valid
= 0;
17334 md_section_align (asection
*seg
, valueT addr
)
17336 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17338 /* We don't need to align ELF sections to the full alignment.
17339 However, Irix 5 may prefer that we align them at least to a 16
17340 byte boundary. We don't bother to align the sections if we
17341 are targeted for an embedded system. */
17342 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17347 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17350 /* Utility routine, called from above as well. If called while the
17351 input file is still being read, it's only an approximation. (For
17352 example, a symbol may later become defined which appeared to be
17353 undefined earlier.) */
17356 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17361 if (g_switch_value
> 0)
17363 const char *symname
;
17366 /* Find out whether this symbol can be referenced off the $gp
17367 register. It can be if it is smaller than the -G size or if
17368 it is in the .sdata or .sbss section. Certain symbols can
17369 not be referenced off the $gp, although it appears as though
17371 symname
= S_GET_NAME (sym
);
17372 if (symname
!= (const char *) NULL
17373 && (strcmp (symname
, "eprol") == 0
17374 || strcmp (symname
, "etext") == 0
17375 || strcmp (symname
, "_gp") == 0
17376 || strcmp (symname
, "edata") == 0
17377 || strcmp (symname
, "_fbss") == 0
17378 || strcmp (symname
, "_fdata") == 0
17379 || strcmp (symname
, "_ftext") == 0
17380 || strcmp (symname
, "end") == 0
17381 || strcmp (symname
, "_gp_disp") == 0))
17383 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17385 #ifndef NO_ECOFF_DEBUGGING
17386 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17387 && (symbol_get_obj (sym
)->ecoff_extern_size
17388 <= g_switch_value
))
17390 /* We must defer this decision until after the whole
17391 file has been read, since there might be a .extern
17392 after the first use of this symbol. */
17393 || (before_relaxing
17394 #ifndef NO_ECOFF_DEBUGGING
17395 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17397 && S_GET_VALUE (sym
) == 0)
17398 || (S_GET_VALUE (sym
) != 0
17399 && S_GET_VALUE (sym
) <= g_switch_value
)))
17403 const char *segname
;
17405 segname
= segment_name (S_GET_SEGMENT (sym
));
17406 gas_assert (strcmp (segname
, ".lit8") != 0
17407 && strcmp (segname
, ".lit4") != 0);
17408 change
= (strcmp (segname
, ".sdata") != 0
17409 && strcmp (segname
, ".sbss") != 0
17410 && strncmp (segname
, ".sdata.", 7) != 0
17411 && strncmp (segname
, ".sbss.", 6) != 0
17412 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17413 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17418 /* We are not optimizing for the $gp register. */
17423 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17426 pic_need_relax (symbolS
*sym
)
17430 /* Handle the case of a symbol equated to another symbol. */
17431 while (symbol_equated_reloc_p (sym
))
17435 /* It's possible to get a loop here in a badly written program. */
17436 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17442 if (symbol_section_p (sym
))
17445 symsec
= S_GET_SEGMENT (sym
);
17447 /* This must duplicate the test in adjust_reloc_syms. */
17448 return (!bfd_is_und_section (symsec
)
17449 && !bfd_is_abs_section (symsec
)
17450 && !bfd_is_com_section (symsec
)
17451 /* A global or weak symbol is treated as external. */
17452 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17455 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17456 convert a section-relative value VAL to the equivalent PC-relative
17460 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17461 offsetT val
, long stretch
)
17466 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17468 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17470 /* If the relax_marker of the symbol fragment differs from the
17471 relax_marker of this fragment, we have not yet adjusted the
17472 symbol fragment fr_address. We want to add in STRETCH in
17473 order to get a better estimate of the address. This
17474 particularly matters because of the shift bits. */
17475 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17479 /* Adjust stretch for any alignment frag. Note that if have
17480 been expanding the earlier code, the symbol may be
17481 defined in what appears to be an earlier frag. FIXME:
17482 This doesn't handle the fr_subtype field, which specifies
17483 a maximum number of bytes to skip when doing an
17485 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17487 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17490 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17492 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17501 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17503 /* The base address rules are complicated. The base address of
17504 a branch is the following instruction. The base address of a
17505 PC relative load or add is the instruction itself, but if it
17506 is in a delay slot (in which case it can not be extended) use
17507 the address of the instruction whose delay slot it is in. */
17508 if (pcrel_op
->include_isa_bit
)
17512 /* If we are currently assuming that this frag should be
17513 extended, then the current address is two bytes higher. */
17514 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17517 /* Ignore the low bit in the target, since it will be set
17518 for a text label. */
17521 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17523 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17526 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17531 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17532 extended opcode. SEC is the section the frag is in. */
17535 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17537 const struct mips_int_operand
*operand
;
17542 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17544 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17547 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17548 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17549 operand
= mips16_immed_operand (type
, FALSE
);
17550 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17551 || (operand
->root
.type
== OP_PCREL
17553 : !bfd_is_abs_section (symsec
)))
17556 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17558 if (operand
->root
.type
== OP_PCREL
)
17560 const struct mips_pcrel_operand
*pcrel_op
;
17563 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17566 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17567 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17569 /* If any of the shifted bits are set, we must use an extended
17570 opcode. If the address depends on the size of this
17571 instruction, this can lead to a loop, so we arrange to always
17572 use an extended opcode. */
17573 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17575 fragp
->fr_subtype
=
17576 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17580 /* If we are about to mark a frag as extended because the value
17581 is precisely the next value above maxtiny, then there is a
17582 chance of an infinite loop as in the following code:
17587 In this case when the la is extended, foo is 0x3fc bytes
17588 away, so the la can be shrunk, but then foo is 0x400 away, so
17589 the la must be extended. To avoid this loop, we mark the
17590 frag as extended if it was small, and is about to become
17591 extended with the next value above maxtiny. */
17592 maxtiny
= mips_int_operand_max (operand
);
17593 if (val
== maxtiny
+ (1 << operand
->shift
)
17594 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17596 fragp
->fr_subtype
=
17597 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17602 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17605 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17606 macro expansion. SEC is the section the frag is in. We only
17607 support PC-relative instructions (LA, DLA, LW, LD) here, in
17608 non-PIC code using 32-bit addressing. */
17611 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17613 const struct mips_pcrel_operand
*pcrel_op
;
17614 const struct mips_int_operand
*operand
;
17619 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17621 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17623 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17626 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17632 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17633 if (bfd_is_abs_section (symsec
))
17635 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17637 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17640 operand
= mips16_immed_operand (type
, TRUE
);
17641 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17642 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17643 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17645 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17652 /* Compute the length of a branch sequence, and adjust the
17653 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17654 worst-case length is computed, with UPDATE being used to indicate
17655 whether an unconditional (-1), branch-likely (+1) or regular (0)
17656 branch is to be computed. */
17658 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17660 bfd_boolean toofar
;
17664 && S_IS_DEFINED (fragp
->fr_symbol
)
17665 && !S_IS_WEAK (fragp
->fr_symbol
)
17666 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17671 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17673 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17677 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17680 /* If the symbol is not defined or it's in a different segment,
17681 we emit the long sequence. */
17684 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17686 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17687 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17688 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17689 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17690 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17696 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17699 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17701 /* Additional space for PIC loading of target address. */
17703 if (mips_opts
.isa
== ISA_MIPS1
)
17704 /* Additional space for $at-stabilizing nop. */
17708 /* If branch is conditional. */
17709 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17716 /* Get a FRAG's branch instruction delay slot size, either from the
17717 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17718 or SHORT_INSN_SIZE otherwise. */
17721 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17723 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17726 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17728 return short_insn_size
;
17731 /* Compute the length of a branch sequence, and adjust the
17732 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17733 worst-case length is computed, with UPDATE being used to indicate
17734 whether an unconditional (-1), or regular (0) branch is to be
17738 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17740 bfd_boolean insn32
= TRUE
;
17741 bfd_boolean nods
= TRUE
;
17742 bfd_boolean pic
= TRUE
;
17743 bfd_boolean al
= TRUE
;
17744 int short_insn_size
;
17745 bfd_boolean toofar
;
17750 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17751 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17752 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17753 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17755 short_insn_size
= insn32
? 4 : 2;
17758 && S_IS_DEFINED (fragp
->fr_symbol
)
17759 && !S_IS_WEAK (fragp
->fr_symbol
)
17760 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17765 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17766 /* Ignore the low bit in the target, since it will be set
17767 for a text label. */
17768 if ((val
& 1) != 0)
17771 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17775 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17778 /* If the symbol is not defined or it's in a different segment,
17779 we emit the long sequence. */
17782 if (fragp
&& update
17783 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17784 fragp
->fr_subtype
= (toofar
17785 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17786 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17791 bfd_boolean compact_known
= fragp
!= NULL
;
17792 bfd_boolean compact
= FALSE
;
17793 bfd_boolean uncond
;
17797 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17798 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17801 uncond
= update
< 0;
17803 /* If label is out of range, we turn branch <br>:
17805 <br> label # 4 bytes
17812 # compact && (!PIC || insn32)
17815 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17816 length
+= short_insn_size
;
17818 /* If assembling PIC code, we further turn:
17824 lw/ld at, %got(label)(gp) # 4 bytes
17825 d/addiu at, %lo(label) # 4 bytes
17826 jr/c at # 2/4 bytes
17829 length
+= 4 + short_insn_size
;
17831 /* Add an extra nop if the jump has no compact form and we need
17832 to fill the delay slot. */
17833 if ((!pic
|| al
) && nods
)
17835 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17836 : short_insn_size
);
17838 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17840 <brneg> 0f # 4 bytes
17841 nop # 2/4 bytes if !compact
17844 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17848 /* Add an extra nop to fill the delay slot. */
17849 gas_assert (fragp
);
17850 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17856 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17857 bit accordingly. */
17860 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17862 bfd_boolean toofar
;
17865 && S_IS_DEFINED (fragp
->fr_symbol
)
17866 && !S_IS_WEAK (fragp
->fr_symbol
)
17867 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17873 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17874 /* Ignore the low bit in the target, since it will be set
17875 for a text label. */
17876 if ((val
& 1) != 0)
17879 /* Assume this is a 2-byte branch. */
17880 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17882 /* We try to avoid the infinite loop by not adding 2 more bytes for
17887 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17889 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17890 else if (type
== 'E')
17891 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17896 /* If the symbol is not defined or it's in a different segment,
17897 we emit a normal 32-bit branch. */
17900 if (fragp
&& update
17901 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17903 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17904 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17912 /* Estimate the size of a frag before relaxing. Unless this is the
17913 mips16, we are not really relaxing here, and the final size is
17914 encoded in the subtype information. For the mips16, we have to
17915 decide whether we are using an extended opcode or not. */
17918 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17922 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17925 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17927 return fragp
->fr_var
;
17930 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17932 /* We don't want to modify the EXTENDED bit here; it might get us
17933 into infinite loops. We change it only in mips_relax_frag(). */
17934 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
17935 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
17937 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
17940 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17944 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17945 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17946 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17947 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17948 fragp
->fr_var
= length
;
17953 if (mips_pic
== VXWORKS_PIC
)
17954 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17956 else if (RELAX_PIC (fragp
->fr_subtype
))
17957 change
= pic_need_relax (fragp
->fr_symbol
);
17959 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17963 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17964 return -RELAX_FIRST (fragp
->fr_subtype
);
17967 return -RELAX_SECOND (fragp
->fr_subtype
);
17970 /* This is called to see whether a reloc against a defined symbol
17971 should be converted into a reloc against a section. */
17974 mips_fix_adjustable (fixS
*fixp
)
17976 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17977 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17980 if (fixp
->fx_addsy
== NULL
)
17983 /* Allow relocs used for EH tables. */
17984 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17987 /* If symbol SYM is in a mergeable section, relocations of the form
17988 SYM + 0 can usually be made section-relative. The mergeable data
17989 is then identified by the section offset rather than by the symbol.
17991 However, if we're generating REL LO16 relocations, the offset is split
17992 between the LO16 and partnering high part relocation. The linker will
17993 need to recalculate the complete offset in order to correctly identify
17996 The linker has traditionally not looked for the partnering high part
17997 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17998 placed anywhere. Rather than break backwards compatibility by changing
17999 this, it seems better not to force the issue, and instead keep the
18000 original symbol. This will work with either linker behavior. */
18001 if ((lo16_reloc_p (fixp
->fx_r_type
)
18002 || reloc_needs_lo_p (fixp
->fx_r_type
))
18003 && HAVE_IN_PLACE_ADDENDS
18004 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18007 /* There is no place to store an in-place offset for JALR relocations. */
18008 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18011 /* Likewise an in-range offset of limited PC-relative relocations may
18012 overflow the in-place relocatable field if recalculated against the
18013 start address of the symbol's containing section.
18015 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18016 section relative to allow linker relaxations to be performed later on. */
18017 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18018 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18021 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18022 to a floating-point stub. The same is true for non-R_MIPS16_26
18023 relocations against MIPS16 functions; in this case, the stub becomes
18024 the function's canonical address.
18026 Floating-point stubs are stored in unique .mips16.call.* or
18027 .mips16.fn.* sections. If a stub T for function F is in section S,
18028 the first relocation in section S must be against F; this is how the
18029 linker determines the target function. All relocations that might
18030 resolve to T must also be against F. We therefore have the following
18031 restrictions, which are given in an intentionally-redundant way:
18033 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18036 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18037 if that stub might be used.
18039 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18042 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18043 that stub might be used.
18045 There is a further restriction:
18047 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18048 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18049 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18050 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18051 against MIPS16 or microMIPS symbols because we need to keep the
18052 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18053 detection and JAL or BAL to JALX instruction conversion in the
18056 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18057 against a MIPS16 symbol. We deal with (5) by additionally leaving
18058 alone any jump and branch relocations against a microMIPS symbol.
18060 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18061 relocation against some symbol R, no relocation against R may be
18062 reduced. (Note that this deals with (2) as well as (1) because
18063 relocations against global symbols will never be reduced on ELF
18064 targets.) This approach is a little simpler than trying to detect
18065 stub sections, and gives the "all or nothing" per-symbol consistency
18066 that we have for MIPS16 symbols. */
18067 if (fixp
->fx_subsy
== NULL
18068 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18069 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18070 && (jmp_reloc_p (fixp
->fx_r_type
)
18071 || b_reloc_p (fixp
->fx_r_type
)))
18072 || *symbol_get_tc (fixp
->fx_addsy
)))
18078 /* Translate internal representation of relocation info to BFD target
18082 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18084 static arelent
*retval
[4];
18086 bfd_reloc_code_real_type code
;
18088 memset (retval
, 0, sizeof(retval
));
18089 reloc
= retval
[0] = XCNEW (arelent
);
18090 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18091 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18092 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18094 if (fixp
->fx_pcrel
)
18096 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18097 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18098 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18099 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18100 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18101 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18102 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18103 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18104 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18105 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18106 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18107 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18109 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18110 Relocations want only the symbol offset. */
18111 switch (fixp
->fx_r_type
)
18113 case BFD_RELOC_MIPS_18_PCREL_S3
:
18114 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18117 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18121 else if (HAVE_IN_PLACE_ADDENDS
18122 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18123 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18124 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18126 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18127 addend accordingly. */
18128 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18131 reloc
->addend
= fixp
->fx_addnumber
;
18133 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18134 entry to be used in the relocation's section offset. */
18135 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18137 reloc
->address
= reloc
->addend
;
18141 code
= fixp
->fx_r_type
;
18143 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18144 if (reloc
->howto
== NULL
)
18146 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18147 _("cannot represent %s relocation in this object file"
18149 bfd_get_reloc_code_name (code
));
18156 /* Relax a machine dependent frag. This returns the amount by which
18157 the current size of the frag should change. */
18160 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18162 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18164 offsetT old_var
= fragp
->fr_var
;
18166 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18168 return fragp
->fr_var
- old_var
;
18171 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18173 offsetT old_var
= fragp
->fr_var
;
18174 offsetT new_var
= 4;
18176 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18177 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18178 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18179 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18180 fragp
->fr_var
= new_var
;
18182 return new_var
- old_var
;
18185 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18188 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18190 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18192 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18193 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18195 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18197 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18203 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18205 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18207 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18208 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18209 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18211 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18213 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18221 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18223 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18225 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18226 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18227 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18231 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18232 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18239 /* Convert a machine dependent frag. */
18242 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18244 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18247 unsigned long insn
;
18250 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18251 insn
= read_insn (buf
);
18253 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18255 /* We generate a fixup instead of applying it right now
18256 because, if there are linker relaxations, we're going to
18257 need the relocations. */
18258 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18259 fragp
->fr_symbol
, fragp
->fr_offset
,
18260 TRUE
, BFD_RELOC_16_PCREL_S2
);
18261 fixp
->fx_file
= fragp
->fr_file
;
18262 fixp
->fx_line
= fragp
->fr_line
;
18264 buf
= write_insn (buf
, insn
);
18270 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18271 _("relaxed out-of-range branch into a jump"));
18273 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18276 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18278 /* Reverse the branch. */
18279 switch ((insn
>> 28) & 0xf)
18282 if ((insn
& 0xff000000) == 0x47000000
18283 || (insn
& 0xff600000) == 0x45600000)
18285 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18286 reversed by tweaking bit 23. */
18287 insn
^= 0x00800000;
18291 /* bc[0-3][tf]l? instructions can have the condition
18292 reversed by tweaking a single TF bit, and their
18293 opcodes all have 0x4???????. */
18294 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18295 insn
^= 0x00010000;
18300 /* bltz 0x04000000 bgez 0x04010000
18301 bltzal 0x04100000 bgezal 0x04110000 */
18302 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18303 insn
^= 0x00010000;
18307 /* beq 0x10000000 bne 0x14000000
18308 blez 0x18000000 bgtz 0x1c000000 */
18309 insn
^= 0x04000000;
18317 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18319 /* Clear the and-link bit. */
18320 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18322 /* bltzal 0x04100000 bgezal 0x04110000
18323 bltzall 0x04120000 bgezall 0x04130000 */
18324 insn
&= ~0x00100000;
18327 /* Branch over the branch (if the branch was likely) or the
18328 full jump (not likely case). Compute the offset from the
18329 current instruction to branch to. */
18330 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18334 /* How many bytes in instructions we've already emitted? */
18335 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18336 /* How many bytes in instructions from here to the end? */
18337 i
= fragp
->fr_var
- i
;
18339 /* Convert to instruction count. */
18341 /* Branch counts from the next instruction. */
18344 /* Branch over the jump. */
18345 buf
= write_insn (buf
, insn
);
18348 buf
= write_insn (buf
, 0);
18350 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18352 /* beql $0, $0, 2f */
18354 /* Compute the PC offset from the current instruction to
18355 the end of the variable frag. */
18356 /* How many bytes in instructions we've already emitted? */
18357 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18358 /* How many bytes in instructions from here to the end? */
18359 i
= fragp
->fr_var
- i
;
18360 /* Convert to instruction count. */
18362 /* Don't decrement i, because we want to branch over the
18366 buf
= write_insn (buf
, insn
);
18367 buf
= write_insn (buf
, 0);
18371 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18374 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18375 ? 0x0c000000 : 0x08000000);
18377 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18378 fragp
->fr_symbol
, fragp
->fr_offset
,
18379 FALSE
, BFD_RELOC_MIPS_JMP
);
18380 fixp
->fx_file
= fragp
->fr_file
;
18381 fixp
->fx_line
= fragp
->fr_line
;
18383 buf
= write_insn (buf
, insn
);
18387 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18389 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18390 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18391 insn
|= at
<< OP_SH_RT
;
18393 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18394 fragp
->fr_symbol
, fragp
->fr_offset
,
18395 FALSE
, BFD_RELOC_MIPS_GOT16
);
18396 fixp
->fx_file
= fragp
->fr_file
;
18397 fixp
->fx_line
= fragp
->fr_line
;
18399 buf
= write_insn (buf
, insn
);
18401 if (mips_opts
.isa
== ISA_MIPS1
)
18403 buf
= write_insn (buf
, 0);
18405 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18406 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18407 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18409 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18410 fragp
->fr_symbol
, fragp
->fr_offset
,
18411 FALSE
, BFD_RELOC_LO16
);
18412 fixp
->fx_file
= fragp
->fr_file
;
18413 fixp
->fx_line
= fragp
->fr_line
;
18415 buf
= write_insn (buf
, insn
);
18418 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18422 insn
|= at
<< OP_SH_RS
;
18424 buf
= write_insn (buf
, insn
);
18428 fragp
->fr_fix
+= fragp
->fr_var
;
18429 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18433 /* Relax microMIPS branches. */
18434 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18436 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18437 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18438 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18439 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18440 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18441 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18442 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18443 bfd_boolean short_ds
;
18444 unsigned long insn
;
18447 fragp
->fr_fix
+= fragp
->fr_var
;
18449 /* Handle 16-bit branches that fit or are forced to fit. */
18450 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18452 /* We generate a fixup instead of applying it right now,
18453 because if there is linker relaxation, we're going to
18454 need the relocations. */
18458 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18459 fragp
->fr_symbol
, fragp
->fr_offset
,
18460 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18463 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18464 fragp
->fr_symbol
, fragp
->fr_offset
,
18465 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18471 fixp
->fx_file
= fragp
->fr_file
;
18472 fixp
->fx_line
= fragp
->fr_line
;
18474 /* These relocations can have an addend that won't fit in
18476 fixp
->fx_no_overflow
= 1;
18481 /* Handle 32-bit branches that fit or are forced to fit. */
18482 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18483 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18485 /* We generate a fixup instead of applying it right now,
18486 because if there is linker relaxation, we're going to
18487 need the relocations. */
18488 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18489 fragp
->fr_symbol
, fragp
->fr_offset
,
18490 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18491 fixp
->fx_file
= fragp
->fr_file
;
18492 fixp
->fx_line
= fragp
->fr_line
;
18496 insn
= read_compressed_insn (buf
, 4);
18501 /* Check the short-delay-slot bit. */
18502 if (!al
|| (insn
& 0x02000000) != 0)
18503 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18505 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18508 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18513 /* Relax 16-bit branches to 32-bit branches. */
18516 insn
= read_compressed_insn (buf
, 2);
18518 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18519 insn
= 0x94000000; /* beq */
18520 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18522 unsigned long regno
;
18524 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18525 regno
= micromips_to_32_reg_d_map
[regno
];
18526 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18527 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18532 /* Nothing else to do, just write it out. */
18533 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18534 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18536 buf
= write_compressed_insn (buf
, insn
, 4);
18538 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18539 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18544 insn
= read_compressed_insn (buf
, 4);
18546 /* Relax 32-bit branches to a sequence of instructions. */
18547 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18548 _("relaxed out-of-range branch into a jump"));
18550 /* Set the short-delay-slot bit. */
18551 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18553 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18557 /* Reverse the branch. */
18558 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18559 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18560 insn
^= 0x20000000;
18561 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18562 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18563 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18564 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18565 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18566 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18567 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18568 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18569 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18570 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18571 insn
^= 0x00400000;
18572 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18573 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18574 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18575 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18576 insn
^= 0x00200000;
18577 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18579 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18581 insn
^= 0x00800000;
18587 /* Clear the and-link and short-delay-slot bits. */
18588 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18590 /* bltzal 0x40200000 bgezal 0x40600000 */
18591 /* bltzals 0x42200000 bgezals 0x42600000 */
18592 insn
&= ~0x02200000;
18595 /* Make a label at the end for use with the branch. */
18596 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18597 micromips_label_inc ();
18598 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18601 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18602 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18603 fixp
->fx_file
= fragp
->fr_file
;
18604 fixp
->fx_line
= fragp
->fr_line
;
18606 /* Branch over the jump. */
18607 buf
= write_compressed_insn (buf
, insn
, 4);
18613 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18615 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18621 unsigned long jal
= (short_ds
|| nods
18622 ? 0x74000000 : 0xf4000000); /* jal/s */
18624 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18625 insn
= al
? jal
: 0xd4000000;
18627 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18628 fragp
->fr_symbol
, fragp
->fr_offset
,
18629 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18630 fixp
->fx_file
= fragp
->fr_file
;
18631 fixp
->fx_line
= fragp
->fr_line
;
18633 buf
= write_compressed_insn (buf
, insn
, 4);
18635 if (compact
|| nods
)
18639 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18641 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18646 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18648 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18649 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18650 insn
|= at
<< MICROMIPSOP_SH_RT
;
18652 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18653 fragp
->fr_symbol
, fragp
->fr_offset
,
18654 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18655 fixp
->fx_file
= fragp
->fr_file
;
18656 fixp
->fx_line
= fragp
->fr_line
;
18658 buf
= write_compressed_insn (buf
, insn
, 4);
18660 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18661 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18662 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18664 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18665 fragp
->fr_symbol
, fragp
->fr_offset
,
18666 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18667 fixp
->fx_file
= fragp
->fr_file
;
18668 fixp
->fx_line
= fragp
->fr_line
;
18670 buf
= write_compressed_insn (buf
, insn
, 4);
18675 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18676 insn
|= at
<< MICROMIPSOP_SH_RS
;
18678 buf
= write_compressed_insn (buf
, insn
, 4);
18680 if (compact
|| nods
)
18682 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18686 /* jr/jrc/jalr/jalrs $at */
18687 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18688 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18690 insn
= al
? jalr
: jr
;
18691 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18693 buf
= write_compressed_insn (buf
, insn
, 2);
18698 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18700 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18705 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18709 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18712 const struct mips_int_operand
*operand
;
18715 unsigned int user_length
;
18716 bfd_boolean need_reloc
;
18717 unsigned long insn
;
18722 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18723 operand
= mips16_immed_operand (type
, FALSE
);
18725 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18726 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18727 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18729 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18730 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18731 || (operand
->root
.type
== OP_PCREL
&& !mac
18733 : !bfd_is_abs_section (symsec
)));
18735 if (operand
->root
.type
== OP_PCREL
&& !mac
)
18737 const struct mips_pcrel_operand
*pcrel_op
;
18739 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18741 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18743 if (!mips_ignore_branch_isa
18744 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18745 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18746 _("branch to a symbol in another ISA mode"));
18747 else if ((fragp
->fr_offset
& 0x1) != 0)
18748 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18749 _("branch to misaligned address (0x%lx)"),
18753 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18755 /* Make sure the section winds up with the alignment we have
18757 if (operand
->shift
> 0)
18758 record_alignment (asec
, operand
->shift
);
18761 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18762 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18765 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18766 _("macro instruction expanded into multiple "
18767 "instructions in a branch delay slot"));
18769 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18770 _("extended instruction in a branch delay slot"));
18772 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
18773 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18774 _("macro instruction expanded into multiple "
18777 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18779 insn
= read_compressed_insn (buf
, 2);
18781 insn
|= MIPS16_EXTEND
;
18783 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18785 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18797 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
18798 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
18800 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
18806 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
18808 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18809 fragp
->fr_symbol
, fragp
->fr_offset
,
18810 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
18811 fixp
->fx_file
= fragp
->fr_file
;
18812 fixp
->fx_line
= fragp
->fr_line
;
18814 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
18815 fragp
->fr_symbol
, fragp
->fr_offset
,
18816 FALSE
, BFD_RELOC_MIPS16_LO16
);
18817 fixp
->fx_file
= fragp
->fr_file
;
18818 fixp
->fx_line
= fragp
->fr_line
;
18823 switch (insn
& 0xf800)
18825 case 0x0800: /* ADDIU */
18826 reg
= (insn
>> 8) & 0x7;
18827 op
= 0xf0004800 | (reg
<< 8);
18829 case 0xb000: /* LW */
18830 reg
= (insn
>> 8) & 0x7;
18831 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
18833 case 0xf800: /* I64 */
18834 reg
= (insn
>> 5) & 0x7;
18835 switch (insn
& 0x0700)
18837 case 0x0400: /* LD */
18838 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
18840 case 0x0600: /* DADDIU */
18841 op
= 0xf000fd00 | (reg
<< 5);
18851 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
18852 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
18853 buf
= write_compressed_insn (buf
, new, 4);
18856 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
18857 buf
= write_compressed_insn (buf
, new, 4);
18859 op
|= mips16_immed_extend (val
, 16);
18860 buf
= write_compressed_insn (buf
, op
, 4);
18862 fragp
->fr_fix
+= e2
? 8 : 12;
18866 unsigned int length
= ext
? 4 : 2;
18870 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18877 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18882 if (mac
|| reloc
== BFD_RELOC_NONE
)
18883 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18884 _("unsupported relocation"));
18887 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18888 fragp
->fr_symbol
, fragp
->fr_offset
,
18890 fixp
->fx_file
= fragp
->fr_file
;
18891 fixp
->fx_line
= fragp
->fr_line
;
18894 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18895 _("invalid unextended operand value"));
18898 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18899 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18901 gas_assert (mips16_opcode_length (insn
) == length
);
18902 write_compressed_insn (buf
, insn
, length
);
18903 fragp
->fr_fix
+= length
;
18908 relax_substateT subtype
= fragp
->fr_subtype
;
18909 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18910 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18914 first
= RELAX_FIRST (subtype
);
18915 second
= RELAX_SECOND (subtype
);
18916 fixp
= (fixS
*) fragp
->fr_opcode
;
18918 /* If the delay slot chosen does not match the size of the instruction,
18919 then emit a warning. */
18920 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18921 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18926 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18927 | RELAX_DELAY_SLOT_SIZE_FIRST
18928 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18929 msg
= macro_warning (s
);
18931 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18935 /* Possibly emit a warning if we've chosen the longer option. */
18936 if (use_second
== second_longer
)
18942 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18943 msg
= macro_warning (s
);
18945 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18949 /* Go through all the fixups for the first sequence. Disable them
18950 (by marking them as done) if we're going to use the second
18951 sequence instead. */
18953 && fixp
->fx_frag
== fragp
18954 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18956 if (subtype
& RELAX_USE_SECOND
)
18958 fixp
= fixp
->fx_next
;
18961 /* Go through the fixups for the second sequence. Disable them if
18962 we're going to use the first sequence, otherwise adjust their
18963 addresses to account for the relaxation. */
18964 while (fixp
&& fixp
->fx_frag
== fragp
)
18966 if (subtype
& RELAX_USE_SECOND
)
18967 fixp
->fx_where
-= first
;
18970 fixp
= fixp
->fx_next
;
18973 /* Now modify the frag contents. */
18974 if (subtype
& RELAX_USE_SECOND
)
18978 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18979 memmove (start
, start
+ first
, second
);
18980 fragp
->fr_fix
-= first
;
18983 fragp
->fr_fix
-= second
;
18987 /* This function is called after the relocs have been generated.
18988 We've been storing mips16 text labels as odd. Here we convert them
18989 back to even for the convenience of the debugger. */
18992 mips_frob_file_after_relocs (void)
18995 unsigned int count
, i
;
18997 syms
= bfd_get_outsymbols (stdoutput
);
18998 count
= bfd_get_symcount (stdoutput
);
18999 for (i
= 0; i
< count
; i
++, syms
++)
19000 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19001 && ((*syms
)->value
& 1) != 0)
19003 (*syms
)->value
&= ~1;
19004 /* If the symbol has an odd size, it was probably computed
19005 incorrectly, so adjust that as well. */
19006 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19007 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19011 /* This function is called whenever a label is defined, including fake
19012 labels instantiated off the dot special symbol. It is used when
19013 handling branch delays; if a branch has a label, we assume we cannot
19014 move it. This also bumps the value of the symbol by 1 in compressed
19018 mips_record_label (symbolS
*sym
)
19020 segment_info_type
*si
= seg_info (now_seg
);
19021 struct insn_label_list
*l
;
19023 if (free_insn_labels
== NULL
)
19024 l
= XNEW (struct insn_label_list
);
19027 l
= free_insn_labels
;
19028 free_insn_labels
= l
->next
;
19032 l
->next
= si
->label_list
;
19033 si
->label_list
= l
;
19036 /* This function is called as tc_frob_label() whenever a label is defined
19037 and adds a DWARF-2 record we only want for true labels. */
19040 mips_define_label (symbolS
*sym
)
19042 mips_record_label (sym
);
19043 dwarf2_emit_label (sym
);
19046 /* This function is called by tc_new_dot_label whenever a new dot symbol
19050 mips_add_dot_label (symbolS
*sym
)
19052 mips_record_label (sym
);
19053 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19054 mips_compressed_mark_label (sym
);
19057 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19058 static unsigned int
19059 mips_convert_ase_flags (int ase
)
19061 unsigned int ext_ases
= 0;
19064 ext_ases
|= AFL_ASE_DSP
;
19065 if (ase
& ASE_DSPR2
)
19066 ext_ases
|= AFL_ASE_DSPR2
;
19067 if (ase
& ASE_DSPR3
)
19068 ext_ases
|= AFL_ASE_DSPR3
;
19070 ext_ases
|= AFL_ASE_EVA
;
19072 ext_ases
|= AFL_ASE_MCU
;
19073 if (ase
& ASE_MDMX
)
19074 ext_ases
|= AFL_ASE_MDMX
;
19075 if (ase
& ASE_MIPS3D
)
19076 ext_ases
|= AFL_ASE_MIPS3D
;
19078 ext_ases
|= AFL_ASE_MT
;
19079 if (ase
& ASE_SMARTMIPS
)
19080 ext_ases
|= AFL_ASE_SMARTMIPS
;
19081 if (ase
& ASE_VIRT
)
19082 ext_ases
|= AFL_ASE_VIRT
;
19084 ext_ases
|= AFL_ASE_MSA
;
19086 ext_ases
|= AFL_ASE_XPA
;
19087 if (ase
& ASE_MIPS16E2
)
19088 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19090 ext_ases
|= AFL_ASE_CRC
;
19091 if (ase
& ASE_GINV
)
19092 ext_ases
|= AFL_ASE_GINV
;
19093 if (ase
& ASE_LOONGSON_MMI
)
19094 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19095 if (ase
& ASE_LOONGSON_CAM
)
19096 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19097 if (ase
& ASE_LOONGSON_EXT
)
19098 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19099 if (ase
& ASE_LOONGSON_EXT2
)
19100 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19104 /* Some special processing for a MIPS ELF file. */
19107 mips_elf_final_processing (void)
19110 Elf_Internal_ABIFlags_v0 flags
;
19114 switch (file_mips_opts
.isa
)
19117 flags
.isa_level
= 1;
19120 flags
.isa_level
= 2;
19123 flags
.isa_level
= 3;
19126 flags
.isa_level
= 4;
19129 flags
.isa_level
= 5;
19132 flags
.isa_level
= 32;
19136 flags
.isa_level
= 32;
19140 flags
.isa_level
= 32;
19144 flags
.isa_level
= 32;
19148 flags
.isa_level
= 32;
19152 flags
.isa_level
= 64;
19156 flags
.isa_level
= 64;
19160 flags
.isa_level
= 64;
19164 flags
.isa_level
= 64;
19168 flags
.isa_level
= 64;
19173 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19174 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19175 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19176 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19178 flags
.cpr2_size
= AFL_REG_NONE
;
19179 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19180 Tag_GNU_MIPS_ABI_FP
);
19181 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19182 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19183 if (file_ase_mips16
)
19184 flags
.ases
|= AFL_ASE_MIPS16
;
19185 if (file_ase_micromips
)
19186 flags
.ases
|= AFL_ASE_MICROMIPS
;
19188 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19189 || file_mips_opts
.fp
== 64)
19190 && file_mips_opts
.oddspreg
)
19191 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19194 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19195 ((Elf_External_ABIFlags_v0
*)
19198 /* Write out the register information. */
19199 if (mips_abi
!= N64_ABI
)
19203 s
.ri_gprmask
= mips_gprmask
;
19204 s
.ri_cprmask
[0] = mips_cprmask
[0];
19205 s
.ri_cprmask
[1] = mips_cprmask
[1];
19206 s
.ri_cprmask
[2] = mips_cprmask
[2];
19207 s
.ri_cprmask
[3] = mips_cprmask
[3];
19208 /* The gp_value field is set by the MIPS ELF backend. */
19210 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19211 ((Elf32_External_RegInfo
*)
19212 mips_regmask_frag
));
19216 Elf64_Internal_RegInfo s
;
19218 s
.ri_gprmask
= mips_gprmask
;
19220 s
.ri_cprmask
[0] = mips_cprmask
[0];
19221 s
.ri_cprmask
[1] = mips_cprmask
[1];
19222 s
.ri_cprmask
[2] = mips_cprmask
[2];
19223 s
.ri_cprmask
[3] = mips_cprmask
[3];
19224 /* The gp_value field is set by the MIPS ELF backend. */
19226 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19227 ((Elf64_External_RegInfo
*)
19228 mips_regmask_frag
));
19231 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19232 sort of BFD interface for this. */
19233 if (mips_any_noreorder
)
19234 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19235 if (mips_pic
!= NO_PIC
)
19237 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19238 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19241 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19243 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19244 defined at present; this might need to change in future. */
19245 if (file_ase_mips16
)
19246 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19247 if (file_ase_micromips
)
19248 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19249 if (file_mips_opts
.ase
& ASE_MDMX
)
19250 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19252 /* Set the MIPS ELF ABI flags. */
19253 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19254 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19255 else if (mips_abi
== O64_ABI
)
19256 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19257 else if (mips_abi
== EABI_ABI
)
19259 if (file_mips_opts
.gp
== 64)
19260 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19262 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19265 /* Nothing to do for N32_ABI or N64_ABI. */
19267 if (mips_32bitmode
)
19268 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19270 if (mips_nan2008
== 1)
19271 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19273 /* 32 bit code with 64 bit FP registers. */
19274 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19275 Tag_GNU_MIPS_ABI_FP
);
19276 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19277 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19280 typedef struct proc
{
19282 symbolS
*func_end_sym
;
19283 unsigned long reg_mask
;
19284 unsigned long reg_offset
;
19285 unsigned long fpreg_mask
;
19286 unsigned long fpreg_offset
;
19287 unsigned long frame_offset
;
19288 unsigned long frame_reg
;
19289 unsigned long pc_reg
;
19292 static procS cur_proc
;
19293 static procS
*cur_proc_ptr
;
19294 static int numprocs
;
19296 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19297 as "2", and a normal nop as "0". */
19299 #define NOP_OPCODE_MIPS 0
19300 #define NOP_OPCODE_MIPS16 1
19301 #define NOP_OPCODE_MICROMIPS 2
19304 mips_nop_opcode (void)
19306 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19307 return NOP_OPCODE_MICROMIPS
;
19308 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19309 return NOP_OPCODE_MIPS16
;
19311 return NOP_OPCODE_MIPS
;
19314 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19315 32-bit microMIPS NOPs here (if applicable). */
19318 mips_handle_align (fragS
*fragp
)
19322 int bytes
, size
, excess
;
19325 if (fragp
->fr_type
!= rs_align_code
)
19328 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19330 switch (nop_opcode
)
19332 case NOP_OPCODE_MICROMIPS
:
19333 opcode
= micromips_nop32_insn
.insn_opcode
;
19336 case NOP_OPCODE_MIPS16
:
19337 opcode
= mips16_nop_insn
.insn_opcode
;
19340 case NOP_OPCODE_MIPS
:
19342 opcode
= nop_insn
.insn_opcode
;
19347 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19348 excess
= bytes
% size
;
19350 /* Handle the leading part if we're not inserting a whole number of
19351 instructions, and make it the end of the fixed part of the frag.
19352 Try to fit in a short microMIPS NOP if applicable and possible,
19353 and use zeroes otherwise. */
19354 gas_assert (excess
< 4);
19355 fragp
->fr_fix
+= excess
;
19360 /* Fall through. */
19362 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19364 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19368 /* Fall through. */
19371 /* Fall through. */
19376 md_number_to_chars (p
, opcode
, size
);
19377 fragp
->fr_var
= size
;
19386 if (*input_line_pointer
== '-')
19388 ++input_line_pointer
;
19391 if (!ISDIGIT (*input_line_pointer
))
19392 as_bad (_("expected simple number"));
19393 if (input_line_pointer
[0] == '0')
19395 if (input_line_pointer
[1] == 'x')
19397 input_line_pointer
+= 2;
19398 while (ISXDIGIT (*input_line_pointer
))
19401 val
|= hex_value (*input_line_pointer
++);
19403 return negative
? -val
: val
;
19407 ++input_line_pointer
;
19408 while (ISDIGIT (*input_line_pointer
))
19411 val
|= *input_line_pointer
++ - '0';
19413 return negative
? -val
: val
;
19416 if (!ISDIGIT (*input_line_pointer
))
19418 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19419 *input_line_pointer
, *input_line_pointer
);
19420 as_warn (_("invalid number"));
19423 while (ISDIGIT (*input_line_pointer
))
19426 val
+= *input_line_pointer
++ - '0';
19428 return negative
? -val
: val
;
19431 /* The .file directive; just like the usual .file directive, but there
19432 is an initial number which is the ECOFF file index. In the non-ECOFF
19433 case .file implies DWARF-2. */
19436 s_mips_file (int x ATTRIBUTE_UNUSED
)
19438 static int first_file_directive
= 0;
19440 if (ECOFF_DEBUGGING
)
19449 filename
= dwarf2_directive_filename ();
19451 /* Versions of GCC up to 3.1 start files with a ".file"
19452 directive even for stabs output. Make sure that this
19453 ".file" is handled. Note that you need a version of GCC
19454 after 3.1 in order to support DWARF-2 on MIPS. */
19455 if (filename
!= NULL
&& ! first_file_directive
)
19457 (void) new_logical_line (filename
, -1);
19458 s_app_file_string (filename
, 0);
19460 first_file_directive
= 1;
19464 /* The .loc directive, implying DWARF-2. */
19467 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19469 if (!ECOFF_DEBUGGING
)
19470 dwarf2_directive_loc (0);
19473 /* The .end directive. */
19476 s_mips_end (int x ATTRIBUTE_UNUSED
)
19480 /* Following functions need their own .frame and .cprestore directives. */
19481 mips_frame_reg_valid
= 0;
19482 mips_cprestore_valid
= 0;
19484 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19487 demand_empty_rest_of_line ();
19492 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19493 as_warn (_(".end not in text section"));
19497 as_warn (_(".end directive without a preceding .ent directive"));
19498 demand_empty_rest_of_line ();
19504 gas_assert (S_GET_NAME (p
));
19505 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19506 as_warn (_(".end symbol does not match .ent symbol"));
19508 if (debug_type
== DEBUG_STABS
)
19509 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19513 as_warn (_(".end directive missing or unknown symbol"));
19515 /* Create an expression to calculate the size of the function. */
19516 if (p
&& cur_proc_ptr
)
19518 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19519 expressionS
*exp
= XNEW (expressionS
);
19522 exp
->X_op
= O_subtract
;
19523 exp
->X_add_symbol
= symbol_temp_new_now ();
19524 exp
->X_op_symbol
= p
;
19525 exp
->X_add_number
= 0;
19527 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19530 #ifdef md_flush_pending_output
19531 md_flush_pending_output ();
19534 /* Generate a .pdr section. */
19535 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19537 segT saved_seg
= now_seg
;
19538 subsegT saved_subseg
= now_subseg
;
19542 gas_assert (pdr_seg
);
19543 subseg_set (pdr_seg
, 0);
19545 /* Write the symbol. */
19546 exp
.X_op
= O_symbol
;
19547 exp
.X_add_symbol
= p
;
19548 exp
.X_add_number
= 0;
19549 emit_expr (&exp
, 4);
19551 fragp
= frag_more (7 * 4);
19553 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19554 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19555 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19556 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19557 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19558 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19559 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19561 subseg_set (saved_seg
, saved_subseg
);
19564 cur_proc_ptr
= NULL
;
19567 /* The .aent and .ent directives. */
19570 s_mips_ent (int aent
)
19574 symbolP
= get_symbol ();
19575 if (*input_line_pointer
== ',')
19576 ++input_line_pointer
;
19577 SKIP_WHITESPACE ();
19578 if (ISDIGIT (*input_line_pointer
)
19579 || *input_line_pointer
== '-')
19582 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19583 as_warn (_(".ent or .aent not in text section"));
19585 if (!aent
&& cur_proc_ptr
)
19586 as_warn (_("missing .end"));
19590 /* This function needs its own .frame and .cprestore directives. */
19591 mips_frame_reg_valid
= 0;
19592 mips_cprestore_valid
= 0;
19594 cur_proc_ptr
= &cur_proc
;
19595 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19597 cur_proc_ptr
->func_sym
= symbolP
;
19601 if (debug_type
== DEBUG_STABS
)
19602 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19603 S_GET_NAME (symbolP
));
19606 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19608 demand_empty_rest_of_line ();
19611 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19612 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19613 s_mips_frame is used so that we can set the PDR information correctly.
19614 We can't use the ecoff routines because they make reference to the ecoff
19615 symbol table (in the mdebug section). */
19618 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19620 if (ECOFF_DEBUGGING
)
19626 if (cur_proc_ptr
== (procS
*) NULL
)
19628 as_warn (_(".frame outside of .ent"));
19629 demand_empty_rest_of_line ();
19633 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19635 SKIP_WHITESPACE ();
19636 if (*input_line_pointer
++ != ','
19637 || get_absolute_expression_and_terminator (&val
) != ',')
19639 as_warn (_("bad .frame directive"));
19640 --input_line_pointer
;
19641 demand_empty_rest_of_line ();
19645 cur_proc_ptr
->frame_offset
= val
;
19646 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19648 demand_empty_rest_of_line ();
19652 /* The .fmask and .mask directives. If the mdebug section is present
19653 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19654 embedded targets, s_mips_mask is used so that we can set the PDR
19655 information correctly. We can't use the ecoff routines because they
19656 make reference to the ecoff symbol table (in the mdebug section). */
19659 s_mips_mask (int reg_type
)
19661 if (ECOFF_DEBUGGING
)
19662 s_ignore (reg_type
);
19667 if (cur_proc_ptr
== (procS
*) NULL
)
19669 as_warn (_(".mask/.fmask outside of .ent"));
19670 demand_empty_rest_of_line ();
19674 if (get_absolute_expression_and_terminator (&mask
) != ',')
19676 as_warn (_("bad .mask/.fmask directive"));
19677 --input_line_pointer
;
19678 demand_empty_rest_of_line ();
19682 off
= get_absolute_expression ();
19684 if (reg_type
== 'F')
19686 cur_proc_ptr
->fpreg_mask
= mask
;
19687 cur_proc_ptr
->fpreg_offset
= off
;
19691 cur_proc_ptr
->reg_mask
= mask
;
19692 cur_proc_ptr
->reg_offset
= off
;
19695 demand_empty_rest_of_line ();
19699 /* A table describing all the processors gas knows about. Names are
19700 matched in the order listed.
19702 To ease comparison, please keep this table in the same order as
19703 gcc's mips_cpu_info_table[]. */
19704 static const struct mips_cpu_info mips_cpu_info_table
[] =
19706 /* Entries for generic ISAs */
19707 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19708 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19709 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19710 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19711 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19712 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19713 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19714 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19715 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19716 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19717 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19718 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19719 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19720 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19721 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19724 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19725 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19726 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19729 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19732 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19733 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19734 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19735 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19736 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19737 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19738 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19739 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19740 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19741 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19742 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19743 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19744 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19745 /* ST Microelectronics Loongson 2E and 2F cores */
19746 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19747 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
19750 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19751 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19752 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19753 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19754 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19755 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19756 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19757 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19758 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19759 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19760 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19761 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19762 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19763 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19764 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19767 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19768 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19769 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19770 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19772 /* MIPS 32 Release 2 */
19773 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19774 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19775 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19776 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19777 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19778 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19779 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19780 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19781 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19782 ISA_MIPS32R2
, CPU_MIPS32R2
},
19783 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19784 ISA_MIPS32R2
, CPU_MIPS32R2
},
19785 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19786 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19787 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19788 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19789 /* Deprecated forms of the above. */
19790 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19791 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19792 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19793 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19794 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19795 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19796 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19797 /* Deprecated forms of the above. */
19798 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19799 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19800 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19801 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19802 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19803 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19804 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19805 /* Deprecated forms of the above. */
19806 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19807 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19808 /* 34Kn is a 34kc without DSP. */
19809 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19810 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19811 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19812 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19813 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19814 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19815 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19816 /* Deprecated forms of the above. */
19817 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19818 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19819 /* 1004K cores are multiprocessor versions of the 34K. */
19820 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19821 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19822 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19823 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19824 /* interaptiv is the new name for 1004kf */
19825 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19826 { "interaptiv-mr2", 0,
19827 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
19828 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
19830 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19831 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19832 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19833 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19836 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19837 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19838 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19839 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19841 /* Broadcom SB-1 CPU core */
19842 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19843 /* Broadcom SB-1A CPU core */
19844 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19846 /* MIPS 64 Release 2 */
19847 /* Loongson CPU core */
19848 /* -march=loongson3a is an alias of -march=gs464 for compatibility */
19849 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19850 ISA_MIPS64R2
, CPU_GS464
},
19851 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
19852 ISA_MIPS64R2
, CPU_GS464
},
19853 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
19854 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
19855 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
19856 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
19858 /* Cavium Networks Octeon CPU core */
19859 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19860 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19861 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19862 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19865 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19868 XLP is mostly like XLR, with the prominent exception that it is
19869 MIPS64R2 rather than MIPS64. */
19870 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19872 /* MIPS 64 Release 6 */
19873 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19874 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19877 { NULL
, 0, 0, 0, 0 }
19881 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19882 with a final "000" replaced by "k". Ignore case.
19884 Note: this function is shared between GCC and GAS. */
19887 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19889 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19890 given
++, canonical
++;
19892 return ((*given
== 0 && *canonical
== 0)
19893 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19897 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19898 CPU name. We've traditionally allowed a lot of variation here.
19900 Note: this function is shared between GCC and GAS. */
19903 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19905 /* First see if the name matches exactly, or with a final "000"
19906 turned into "k". */
19907 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19910 /* If not, try comparing based on numerical designation alone.
19911 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19912 if (TOLOWER (*given
) == 'r')
19914 if (!ISDIGIT (*given
))
19917 /* Skip over some well-known prefixes in the canonical name,
19918 hoping to find a number there too. */
19919 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19921 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19923 else if (TOLOWER (canonical
[0]) == 'r')
19926 return mips_strict_matching_cpu_name_p (canonical
, given
);
19930 /* Parse an option that takes the name of a processor as its argument.
19931 OPTION is the name of the option and CPU_STRING is the argument.
19932 Return the corresponding processor enumeration if the CPU_STRING is
19933 recognized, otherwise report an error and return null.
19935 A similar function exists in GCC. */
19937 static const struct mips_cpu_info
*
19938 mips_parse_cpu (const char *option
, const char *cpu_string
)
19940 const struct mips_cpu_info
*p
;
19942 /* 'from-abi' selects the most compatible architecture for the given
19943 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19944 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19945 version. Look first at the -mgp options, if given, otherwise base
19946 the choice on MIPS_DEFAULT_64BIT.
19948 Treat NO_ABI like the EABIs. One reason to do this is that the
19949 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19950 architecture. This code picks MIPS I for 'mips' and MIPS III for
19951 'mips64', just as we did in the days before 'from-abi'. */
19952 if (strcasecmp (cpu_string
, "from-abi") == 0)
19954 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19955 return mips_cpu_info_from_isa (ISA_MIPS1
);
19957 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19958 return mips_cpu_info_from_isa (ISA_MIPS3
);
19960 if (file_mips_opts
.gp
>= 0)
19961 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19962 ? ISA_MIPS1
: ISA_MIPS3
);
19964 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19969 /* 'default' has traditionally been a no-op. Probably not very useful. */
19970 if (strcasecmp (cpu_string
, "default") == 0)
19973 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19974 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19977 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19981 /* Return the canonical processor information for ISA (a member of the
19982 ISA_MIPS* enumeration). */
19984 static const struct mips_cpu_info
*
19985 mips_cpu_info_from_isa (int isa
)
19989 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19990 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19991 && isa
== mips_cpu_info_table
[i
].isa
)
19992 return (&mips_cpu_info_table
[i
]);
19997 static const struct mips_cpu_info
*
19998 mips_cpu_info_from_arch (int arch
)
20002 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20003 if (arch
== mips_cpu_info_table
[i
].cpu
)
20004 return (&mips_cpu_info_table
[i
]);
20010 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20014 fprintf (stream
, "%24s", "");
20019 fprintf (stream
, ", ");
20023 if (*col_p
+ strlen (string
) > 72)
20025 fprintf (stream
, "\n%24s", "");
20029 fprintf (stream
, "%s", string
);
20030 *col_p
+= strlen (string
);
20036 md_show_usage (FILE *stream
)
20041 fprintf (stream
, _("\
20043 -EB generate big endian output\n\
20044 -EL generate little endian output\n\
20045 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20046 -G NUM allow referencing objects up to NUM bytes\n\
20047 implicitly with the gp register [default 8]\n"));
20048 fprintf (stream
, _("\
20049 -mips1 generate MIPS ISA I instructions\n\
20050 -mips2 generate MIPS ISA II instructions\n\
20051 -mips3 generate MIPS ISA III instructions\n\
20052 -mips4 generate MIPS ISA IV instructions\n\
20053 -mips5 generate MIPS ISA V instructions\n\
20054 -mips32 generate MIPS32 ISA instructions\n\
20055 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20056 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20057 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20058 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20059 -mips64 generate MIPS64 ISA instructions\n\
20060 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20061 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20062 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20063 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20064 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20068 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20069 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20070 show (stream
, "from-abi", &column
, &first
);
20071 fputc ('\n', stream
);
20073 fprintf (stream
, _("\
20074 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20075 -no-mCPU don't generate code specific to CPU.\n\
20076 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20080 show (stream
, "3900", &column
, &first
);
20081 show (stream
, "4010", &column
, &first
);
20082 show (stream
, "4100", &column
, &first
);
20083 show (stream
, "4650", &column
, &first
);
20084 fputc ('\n', stream
);
20086 fprintf (stream
, _("\
20087 -mips16 generate mips16 instructions\n\
20088 -no-mips16 do not generate mips16 instructions\n"));
20089 fprintf (stream
, _("\
20090 -mmips16e2 generate MIPS16e2 instructions\n\
20091 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20092 fprintf (stream
, _("\
20093 -mmicromips generate microMIPS instructions\n\
20094 -mno-micromips do not generate microMIPS instructions\n"));
20095 fprintf (stream
, _("\
20096 -msmartmips generate smartmips instructions\n\
20097 -mno-smartmips do not generate smartmips instructions\n"));
20098 fprintf (stream
, _("\
20099 -mdsp generate DSP instructions\n\
20100 -mno-dsp do not generate DSP instructions\n"));
20101 fprintf (stream
, _("\
20102 -mdspr2 generate DSP R2 instructions\n\
20103 -mno-dspr2 do not generate DSP R2 instructions\n"));
20104 fprintf (stream
, _("\
20105 -mdspr3 generate DSP R3 instructions\n\
20106 -mno-dspr3 do not generate DSP R3 instructions\n"));
20107 fprintf (stream
, _("\
20108 -mmt generate MT instructions\n\
20109 -mno-mt do not generate MT instructions\n"));
20110 fprintf (stream
, _("\
20111 -mmcu generate MCU instructions\n\
20112 -mno-mcu do not generate MCU instructions\n"));
20113 fprintf (stream
, _("\
20114 -mmsa generate MSA instructions\n\
20115 -mno-msa do not generate MSA instructions\n"));
20116 fprintf (stream
, _("\
20117 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20118 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20119 fprintf (stream
, _("\
20120 -mvirt generate Virtualization instructions\n\
20121 -mno-virt do not generate Virtualization instructions\n"));
20122 fprintf (stream
, _("\
20123 -mcrc generate CRC instructions\n\
20124 -mno-crc do not generate CRC instructions\n"));
20125 fprintf (stream
, _("\
20126 -mginv generate Global INValidate (GINV) instructions\n\
20127 -mno-ginv do not generate Global INValidate instructions\n"));
20128 fprintf (stream
, _("\
20129 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20130 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20131 fprintf (stream
, _("\
20132 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20133 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20134 fprintf (stream
, _("\
20135 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20136 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20137 fprintf (stream
, _("\
20138 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20139 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20140 fprintf (stream
, _("\
20141 -minsn32 only generate 32-bit microMIPS instructions\n\
20142 -mno-insn32 generate all microMIPS instructions\n"));
20143 fprintf (stream
, _("\
20144 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20145 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20146 -mfix-vr4120 work around certain VR4120 errata\n\
20147 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20148 -mfix-24k insert a nop after ERET and DERET instructions\n\
20149 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20150 -mfix-r5900 work around R5900 short loop errata\n\
20151 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20152 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20153 -msym32 assume all symbols have 32-bit values\n\
20154 -O0 do not remove unneeded NOPs, do not swap branches\n\
20155 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20156 -O2 remove unneeded NOPs and swap branches\n\
20157 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20158 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20159 fprintf (stream
, _("\
20160 -mhard-float allow floating-point instructions\n\
20161 -msoft-float do not allow floating-point instructions\n\
20162 -msingle-float only allow 32-bit floating-point operations\n\
20163 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20164 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20165 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20166 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20167 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20168 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20172 show (stream
, "legacy", &column
, &first
);
20173 show (stream
, "2008", &column
, &first
);
20175 fputc ('\n', stream
);
20177 fprintf (stream
, _("\
20178 -KPIC, -call_shared generate SVR4 position independent code\n\
20179 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20180 -mvxworks-pic generate VxWorks position independent code\n\
20181 -non_shared do not generate code that can operate with DSOs\n\
20182 -xgot assume a 32 bit GOT\n\
20183 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20184 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20185 position dependent (non shared) code\n\
20186 -mabi=ABI create ABI conformant object file for:\n"));
20190 show (stream
, "32", &column
, &first
);
20191 show (stream
, "o64", &column
, &first
);
20192 show (stream
, "n32", &column
, &first
);
20193 show (stream
, "64", &column
, &first
);
20194 show (stream
, "eabi", &column
, &first
);
20196 fputc ('\n', stream
);
20198 fprintf (stream
, _("\
20199 -32 create o32 ABI object file%s\n"),
20200 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20201 fprintf (stream
, _("\
20202 -n32 create n32 ABI object file%s\n"),
20203 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20204 fprintf (stream
, _("\
20205 -64 create 64 ABI object file%s\n"),
20206 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20211 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20213 if (HAVE_64BIT_SYMBOLS
)
20214 return dwarf2_format_64bit_irix
;
20216 return dwarf2_format_32bit
;
20221 mips_dwarf2_addr_size (void)
20223 if (HAVE_64BIT_OBJECTS
)
20229 /* Standard calling conventions leave the CFA at SP on entry. */
20231 mips_cfi_frame_initial_instructions (void)
20233 cfi_add_CFA_def_cfa_register (SP
);
20237 tc_mips_regname_to_dw2regnum (char *regname
)
20239 unsigned int regnum
= -1;
20242 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20248 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20249 Given a symbolic attribute NAME, return the proper integer value.
20250 Returns -1 if the attribute is not known. */
20253 mips_convert_symbolic_attribute (const char *name
)
20255 static const struct
20260 attribute_table
[] =
20262 #define T(tag) {#tag, tag}
20263 T (Tag_GNU_MIPS_ABI_FP
),
20264 T (Tag_GNU_MIPS_ABI_MSA
),
20272 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20273 if (streq (name
, attribute_table
[i
].name
))
20274 return attribute_table
[i
].tag
;
20282 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20284 mips_emit_delays ();
20286 as_warn (_("missing .end at end of assembly"));
20288 /* Just in case no code was emitted, do the consistency check. */
20289 file_mips_check_options ();
20291 /* Set a floating-point ABI if the user did not. */
20292 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20294 /* Perform consistency checks on the floating-point ABI. */
20295 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20296 Tag_GNU_MIPS_ABI_FP
);
20297 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20298 check_fpabi (fpabi
);
20302 /* Soft-float gets precedence over single-float, the two options should
20303 not be used together so this should not matter. */
20304 if (file_mips_opts
.soft_float
== 1)
20305 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20306 /* Single-float gets precedence over all double_float cases. */
20307 else if (file_mips_opts
.single_float
== 1)
20308 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20311 switch (file_mips_opts
.fp
)
20314 if (file_mips_opts
.gp
== 32)
20315 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20318 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20321 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20322 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20323 else if (file_mips_opts
.gp
== 32)
20324 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20326 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20331 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20332 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20336 /* Returns the relocation type required for a particular CFI encoding. */
20338 bfd_reloc_code_real_type
20339 mips_cfi_reloc_for_encoding (int encoding
)
20341 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20342 return BFD_RELOC_32_PCREL
;
20343 else return BFD_RELOC_NONE
;