1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float
;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float
;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32
= -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32
= -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float
= 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float
= 0;
265 static struct mips_set_options mips_opts
=
267 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
272 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask
;
279 unsigned long mips_cprmask
[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa
= ISA_UNKNOWN
;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d
;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx
;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips
;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp
;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2
;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt
;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_R14000 \
476 || mips_opts.arch == CPU_R16000 \
477 || mips_opts.arch == CPU_RM7000 \
478 || mips_opts.arch == CPU_VR5500 \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900)
490 /* Whether the processor uses hardware interlocks to avoid delays
491 required by coprocessor instructions, and thus does not require
492 nops to be inserted. This applies to instructions marked
493 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
494 between instructions marked INSN_WRITE_COND_CODE and ones marked
495 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
496 levels I, II, and III. */
497 /* Itbl support may require additional care here. */
498 #define cop_interlocks \
499 ((mips_opts.isa != ISA_MIPS1 \
500 && mips_opts.isa != ISA_MIPS2 \
501 && mips_opts.isa != ISA_MIPS3) \
502 || mips_opts.arch == CPU_R4300 \
505 /* Whether the processor uses hardware interlocks to protect reads
506 from coprocessor registers after they are loaded from memory, and
507 thus does not require nops to be inserted. This applies to
508 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
509 requires at MIPS ISA level I. */
510 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
512 /* Is this a mfhi or mflo instruction? */
513 #define MF_HILO_INSN(PINFO) \
514 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
516 /* Returns true for a (non floating-point) coprocessor instruction. Reading
517 or writing the condition code is only possible on the coprocessors and
518 these insns are not marked with INSN_COP. Thus for these insns use the
519 condition-code flags. */
520 #define COP_INSN(PINFO) \
521 (PINFO != INSN_MACRO \
522 && ((PINFO) & (FP_S | FP_D)) == 0 \
523 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
525 /* MIPS PIC level. */
527 enum mips_pic_level mips_pic
;
529 /* 1 if we should generate 32 bit offsets from the $gp register in
530 SVR4_PIC mode. Currently has no meaning in other modes. */
531 static int mips_big_got
= 0;
533 /* 1 if trap instructions should used for overflow rather than break
535 static int mips_trap
= 0;
537 /* 1 if double width floating point constants should not be constructed
538 by assembling two single width halves into two single width floating
539 point registers which just happen to alias the double width destination
540 register. On some architectures this aliasing can be disabled by a bit
541 in the status register, and the setting of this bit cannot be determined
542 automatically at assemble time. */
543 static int mips_disable_float_construction
;
545 /* Non-zero if any .set noreorder directives were used. */
547 static int mips_any_noreorder
;
549 /* Non-zero if nops should be inserted when the register referenced in
550 an mfhi/mflo instruction is read in the next two instructions. */
551 static int mips_7000_hilo_fix
;
553 /* The size of objects in the small data section. */
554 static unsigned int g_switch_value
= 8;
555 /* Whether the -G option was used. */
556 static int g_switch_seen
= 0;
561 /* If we can determine in advance that GP optimization won't be
562 possible, we can skip the relaxation stuff that tries to produce
563 GP-relative references. This makes delay slot optimization work
566 This function can only provide a guess, but it seems to work for
567 gcc output. It needs to guess right for gcc, otherwise gcc
568 will put what it thinks is a GP-relative instruction in a branch
571 I don't know if a fix is needed for the SVR4_PIC mode. I've only
572 fixed it for the non-PIC mode. KR 95/04/07 */
573 static int nopic_need_relax (symbolS
*, int);
575 /* handle of the OPCODE hash table */
576 static struct hash_control
*op_hash
= NULL
;
578 /* The opcode hash table we use for the mips16. */
579 static struct hash_control
*mips16_op_hash
= NULL
;
581 /* This array holds the chars that always start a comment. If the
582 pre-processor is disabled, these aren't very useful */
583 const char comment_chars
[] = "#";
585 /* This array holds the chars that only start a comment at the beginning of
586 a line. If the line seems to have the form '# 123 filename'
587 .line and .file directives will appear in the pre-processed output */
588 /* Note that input_file.c hand checks for '#' at the beginning of the
589 first line of the input file. This is because the compiler outputs
590 #NO_APP at the beginning of its output. */
591 /* Also note that C style comments are always supported. */
592 const char line_comment_chars
[] = "#";
594 /* This array holds machine specific line separator characters. */
595 const char line_separator_chars
[] = ";";
597 /* Chars that can be used to separate mant from exp in floating point nums */
598 const char EXP_CHARS
[] = "eE";
600 /* Chars that mean this number is a floating point constant */
603 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
605 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
606 changed in read.c . Ideally it shouldn't have to know about it at all,
607 but nothing is ideal around here.
610 static char *insn_error
;
612 static int auto_align
= 1;
614 /* When outputting SVR4 PIC code, the assembler needs to know the
615 offset in the stack frame from which to restore the $gp register.
616 This is set by the .cprestore pseudo-op, and saved in this
618 static offsetT mips_cprestore_offset
= -1;
620 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
621 more optimizations, it can use a register value instead of a memory-saved
622 offset and even an other register than $gp as global pointer. */
623 static offsetT mips_cpreturn_offset
= -1;
624 static int mips_cpreturn_register
= -1;
625 static int mips_gp_register
= GP
;
626 static int mips_gprel_offset
= 0;
628 /* Whether mips_cprestore_offset has been set in the current function
629 (or whether it has already been warned about, if not). */
630 static int mips_cprestore_valid
= 0;
632 /* This is the register which holds the stack frame, as set by the
633 .frame pseudo-op. This is needed to implement .cprestore. */
634 static int mips_frame_reg
= SP
;
636 /* Whether mips_frame_reg has been set in the current function
637 (or whether it has already been warned about, if not). */
638 static int mips_frame_reg_valid
= 0;
640 /* To output NOP instructions correctly, we need to keep information
641 about the previous two instructions. */
643 /* Whether we are optimizing. The default value of 2 means to remove
644 unneeded NOPs and swap branch instructions when possible. A value
645 of 1 means to not swap branches. A value of 0 means to always
647 static int mips_optimize
= 2;
649 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
650 equivalent to seeing no -g option at all. */
651 static int mips_debug
= 0;
653 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
654 #define MAX_VR4130_NOPS 4
656 /* The maximum number of NOPs needed to fill delay slots. */
657 #define MAX_DELAY_NOPS 2
659 /* The maximum number of NOPs needed for any purpose. */
662 /* A list of previous instructions, with index 0 being the most recent.
663 We need to look back MAX_NOPS instructions when filling delay slots
664 or working around processor errata. We need to look back one
665 instruction further if we're thinking about using history[0] to
666 fill a branch delay slot. */
667 static struct mips_cl_insn history
[1 + MAX_NOPS
];
669 /* Nop instructions used by emit_nop. */
670 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
672 /* The appropriate nop for the current mode. */
673 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
675 /* If this is set, it points to a frag holding nop instructions which
676 were inserted before the start of a noreorder section. If those
677 nops turn out to be unnecessary, the size of the frag can be
679 static fragS
*prev_nop_frag
;
681 /* The number of nop instructions we created in prev_nop_frag. */
682 static int prev_nop_frag_holds
;
684 /* The number of nop instructions that we know we need in
686 static int prev_nop_frag_required
;
688 /* The number of instructions we've seen since prev_nop_frag. */
689 static int prev_nop_frag_since
;
691 /* For ECOFF and ELF, relocations against symbols are done in two
692 parts, with a HI relocation and a LO relocation. Each relocation
693 has only 16 bits of space to store an addend. This means that in
694 order for the linker to handle carries correctly, it must be able
695 to locate both the HI and the LO relocation. This means that the
696 relocations must appear in order in the relocation table.
698 In order to implement this, we keep track of each unmatched HI
699 relocation. We then sort them so that they immediately precede the
700 corresponding LO relocation. */
705 struct mips_hi_fixup
*next
;
708 /* The section this fixup is in. */
712 /* The list of unmatched HI relocs. */
714 static struct mips_hi_fixup
*mips_hi_fixup_list
;
716 /* The frag containing the last explicit relocation operator.
717 Null if explicit relocations have not been used. */
719 static fragS
*prev_reloc_op_frag
;
721 /* Map normal MIPS register numbers to mips16 register numbers. */
723 #define X ILLEGAL_REG
724 static const int mips32_to_16_reg_map
[] =
726 X
, X
, 2, 3, 4, 5, 6, 7,
727 X
, X
, X
, X
, X
, X
, X
, X
,
728 0, 1, X
, X
, X
, X
, X
, X
,
729 X
, X
, X
, X
, X
, X
, X
, X
733 /* Map mips16 register numbers to normal MIPS register numbers. */
735 static const unsigned int mips16_to_32_reg_map
[] =
737 16, 17, 2, 3, 4, 5, 6, 7
740 /* Classifies the kind of instructions we're interested in when
741 implementing -mfix-vr4120. */
742 enum fix_vr4120_class
{
749 NUM_FIX_VR4120_CLASSES
752 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
753 there must be at least one other instruction between an instruction
754 of type X and an instruction of type Y. */
755 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
757 /* True if -mfix-vr4120 is in force. */
758 static int mips_fix_vr4120
;
760 /* ...likewise -mfix-vr4130. */
761 static int mips_fix_vr4130
;
763 /* We don't relax branches by default, since this causes us to expand
764 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
765 fail to compute the offset before expanding the macro to the most
766 efficient expansion. */
768 static int mips_relax_branch
;
770 /* The expansion of many macros depends on the type of symbol that
771 they refer to. For example, when generating position-dependent code,
772 a macro that refers to a symbol may have two different expansions,
773 one which uses GP-relative addresses and one which uses absolute
774 addresses. When generating SVR4-style PIC, a macro may have
775 different expansions for local and global symbols.
777 We handle these situations by generating both sequences and putting
778 them in variant frags. In position-dependent code, the first sequence
779 will be the GP-relative one and the second sequence will be the
780 absolute one. In SVR4 PIC, the first sequence will be for global
781 symbols and the second will be for local symbols.
783 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
784 SECOND are the lengths of the two sequences in bytes. These fields
785 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
786 the subtype has the following flags:
789 Set if it has been decided that we should use the second
790 sequence instead of the first.
793 Set in the first variant frag if the macro's second implementation
794 is longer than its first. This refers to the macro as a whole,
795 not an individual relaxation.
798 Set in the first variant frag if the macro appeared in a .set nomacro
799 block and if one alternative requires a warning but the other does not.
802 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
805 The frag's "opcode" points to the first fixup for relaxable code.
807 Relaxable macros are generated using a sequence such as:
809 relax_start (SYMBOL);
810 ... generate first expansion ...
812 ... generate second expansion ...
815 The code and fixups for the unwanted alternative are discarded
816 by md_convert_frag. */
817 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
819 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
820 #define RELAX_SECOND(X) ((X) & 0xff)
821 #define RELAX_USE_SECOND 0x10000
822 #define RELAX_SECOND_LONGER 0x20000
823 #define RELAX_NOMACRO 0x40000
824 #define RELAX_DELAY_SLOT 0x80000
826 /* Branch without likely bit. If label is out of range, we turn:
828 beq reg1, reg2, label
838 with the following opcode replacements:
845 bltzal <-> bgezal (with jal label instead of j label)
847 Even though keeping the delay slot instruction in the delay slot of
848 the branch would be more efficient, it would be very tricky to do
849 correctly, because we'd have to introduce a variable frag *after*
850 the delay slot instruction, and expand that instead. Let's do it
851 the easy way for now, even if the branch-not-taken case now costs
852 one additional instruction. Out-of-range branches are not supposed
853 to be common, anyway.
855 Branch likely. If label is out of range, we turn:
857 beql reg1, reg2, label
858 delay slot (annulled if branch not taken)
867 delay slot (executed only if branch taken)
870 It would be possible to generate a shorter sequence by losing the
871 likely bit, generating something like:
876 delay slot (executed only if branch taken)
888 bltzall -> bgezal (with jal label instead of j label)
889 bgezall -> bltzal (ditto)
892 but it's not clear that it would actually improve performance. */
893 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
896 | ((toofar) ? 1 : 0) \
898 | ((likely) ? 4 : 0) \
899 | ((uncond) ? 8 : 0)))
900 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
901 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
902 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
903 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
904 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
906 /* For mips16 code, we use an entirely different form of relaxation.
907 mips16 supports two versions of most instructions which take
908 immediate values: a small one which takes some small value, and a
909 larger one which takes a 16 bit value. Since branches also follow
910 this pattern, relaxing these values is required.
912 We can assemble both mips16 and normal MIPS code in a single
913 object. Therefore, we need to support this type of relaxation at
914 the same time that we support the relaxation described above. We
915 use the high bit of the subtype field to distinguish these cases.
917 The information we store for this type of relaxation is the
918 argument code found in the opcode file for this relocation, whether
919 the user explicitly requested a small or extended form, and whether
920 the relocation is in a jump or jal delay slot. That tells us the
921 size of the value, and how it should be stored. We also store
922 whether the fragment is considered to be extended or not. We also
923 store whether this is known to be a branch to a different section,
924 whether we have tried to relax this frag yet, and whether we have
925 ever extended a PC relative fragment because of a shift count. */
926 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
929 | ((small) ? 0x100 : 0) \
930 | ((ext) ? 0x200 : 0) \
931 | ((dslot) ? 0x400 : 0) \
932 | ((jal_dslot) ? 0x800 : 0))
933 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
934 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
935 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
936 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
937 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
938 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
939 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
940 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
941 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
942 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
943 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
944 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
946 /* Is the given value a sign-extended 32-bit value? */
947 #define IS_SEXT_32BIT_NUM(x) \
948 (((x) &~ (offsetT) 0x7fffffff) == 0 \
949 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
951 /* Is the given value a sign-extended 16-bit value? */
952 #define IS_SEXT_16BIT_NUM(x) \
953 (((x) &~ (offsetT) 0x7fff) == 0 \
954 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
956 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
957 #define IS_ZEXT_32BIT_NUM(x) \
958 (((x) &~ (offsetT) 0xffffffff) == 0 \
959 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
961 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
962 VALUE << SHIFT. VALUE is evaluated exactly once. */
963 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
964 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
965 | (((VALUE) & (MASK)) << (SHIFT)))
967 /* Extract bits MASK << SHIFT from STRUCT and shift them right
969 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
970 (((STRUCT) >> (SHIFT)) & (MASK))
972 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
973 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
975 include/opcode/mips.h specifies operand fields using the macros
976 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
977 with "MIPS16OP" instead of "OP". */
978 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
979 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
980 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
981 INSERT_BITS ((INSN).insn_opcode, VALUE, \
982 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
984 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
985 #define EXTRACT_OPERAND(FIELD, INSN) \
986 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
987 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
988 EXTRACT_BITS ((INSN).insn_opcode, \
989 MIPS16OP_MASK_##FIELD, \
992 /* Global variables used when generating relaxable macros. See the
993 comment above RELAX_ENCODE for more details about how relaxation
996 /* 0 if we're not emitting a relaxable macro.
997 1 if we're emitting the first of the two relaxation alternatives.
998 2 if we're emitting the second alternative. */
1001 /* The first relaxable fixup in the current frag. (In other words,
1002 the first fixup that refers to relaxable code.) */
1005 /* sizes[0] says how many bytes of the first alternative are stored in
1006 the current frag. Likewise sizes[1] for the second alternative. */
1007 unsigned int sizes
[2];
1009 /* The symbol on which the choice of sequence depends. */
1013 /* Global variables used to decide whether a macro needs a warning. */
1015 /* True if the macro is in a branch delay slot. */
1016 bfd_boolean delay_slot_p
;
1018 /* For relaxable macros, sizes[0] is the length of the first alternative
1019 in bytes and sizes[1] is the length of the second alternative.
1020 For non-relaxable macros, both elements give the length of the
1022 unsigned int sizes
[2];
1024 /* The first variant frag for this macro. */
1026 } mips_macro_warning
;
1028 /* Prototypes for static functions. */
1030 #define internalError() \
1031 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1033 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1035 static void append_insn
1036 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
1037 static void mips_no_prev_insn (void);
1038 static void mips16_macro_build
1039 (expressionS
*, const char *, const char *, va_list);
1040 static void load_register (int, expressionS
*, int);
1041 static void macro_start (void);
1042 static void macro_end (void);
1043 static void macro (struct mips_cl_insn
* ip
);
1044 static void mips16_macro (struct mips_cl_insn
* ip
);
1045 #ifdef LOSING_COMPILER
1046 static void macro2 (struct mips_cl_insn
* ip
);
1048 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1049 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1050 static void mips16_immed
1051 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1052 unsigned long *, bfd_boolean
*, unsigned short *);
1053 static size_t my_getSmallExpression
1054 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1055 static void my_getExpression (expressionS
*, char *);
1056 static void s_align (int);
1057 static void s_change_sec (int);
1058 static void s_change_section (int);
1059 static void s_cons (int);
1060 static void s_float_cons (int);
1061 static void s_mips_globl (int);
1062 static void s_option (int);
1063 static void s_mipsset (int);
1064 static void s_abicalls (int);
1065 static void s_cpload (int);
1066 static void s_cpsetup (int);
1067 static void s_cplocal (int);
1068 static void s_cprestore (int);
1069 static void s_cpreturn (int);
1070 static void s_dtprelword (int);
1071 static void s_dtpreldword (int);
1072 static void s_gpvalue (int);
1073 static void s_gpword (int);
1074 static void s_gpdword (int);
1075 static void s_cpadd (int);
1076 static void s_insn (int);
1077 static void md_obj_begin (void);
1078 static void md_obj_end (void);
1079 static void s_mips_ent (int);
1080 static void s_mips_end (int);
1081 static void s_mips_frame (int);
1082 static void s_mips_mask (int reg_type
);
1083 static void s_mips_stab (int);
1084 static void s_mips_weakext (int);
1085 static void s_mips_file (int);
1086 static void s_mips_loc (int);
1087 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1088 static int relaxed_branch_length (fragS
*, asection
*, int);
1089 static int validate_mips_insn (const struct mips_opcode
*);
1091 /* Table and functions used to map between CPU/ISA names, and
1092 ISA levels, and CPU numbers. */
1094 struct mips_cpu_info
1096 const char *name
; /* CPU or ISA name. */
1097 int flags
; /* ASEs available, or ISA flag. */
1098 int isa
; /* ISA level. */
1099 int cpu
; /* CPU number (default CPU if ISA). */
1102 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1103 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1104 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1105 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1106 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1107 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1108 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1110 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1111 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1112 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1116 The following pseudo-ops from the Kane and Heinrich MIPS book
1117 should be defined here, but are currently unsupported: .alias,
1118 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1120 The following pseudo-ops from the Kane and Heinrich MIPS book are
1121 specific to the type of debugging information being generated, and
1122 should be defined by the object format: .aent, .begin, .bend,
1123 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1126 The following pseudo-ops from the Kane and Heinrich MIPS book are
1127 not MIPS CPU specific, but are also not specific to the object file
1128 format. This file is probably the best place to define them, but
1129 they are not currently supported: .asm0, .endr, .lab, .struct. */
1131 static const pseudo_typeS mips_pseudo_table
[] =
1133 /* MIPS specific pseudo-ops. */
1134 {"option", s_option
, 0},
1135 {"set", s_mipsset
, 0},
1136 {"rdata", s_change_sec
, 'r'},
1137 {"sdata", s_change_sec
, 's'},
1138 {"livereg", s_ignore
, 0},
1139 {"abicalls", s_abicalls
, 0},
1140 {"cpload", s_cpload
, 0},
1141 {"cpsetup", s_cpsetup
, 0},
1142 {"cplocal", s_cplocal
, 0},
1143 {"cprestore", s_cprestore
, 0},
1144 {"cpreturn", s_cpreturn
, 0},
1145 {"dtprelword", s_dtprelword
, 0},
1146 {"dtpreldword", s_dtpreldword
, 0},
1147 {"gpvalue", s_gpvalue
, 0},
1148 {"gpword", s_gpword
, 0},
1149 {"gpdword", s_gpdword
, 0},
1150 {"cpadd", s_cpadd
, 0},
1151 {"insn", s_insn
, 0},
1153 /* Relatively generic pseudo-ops that happen to be used on MIPS
1155 {"asciiz", stringer
, 8 + 1},
1156 {"bss", s_change_sec
, 'b'},
1158 {"half", s_cons
, 1},
1159 {"dword", s_cons
, 3},
1160 {"weakext", s_mips_weakext
, 0},
1161 {"origin", s_org
, 0},
1162 {"repeat", s_rept
, 0},
1164 /* These pseudo-ops are defined in read.c, but must be overridden
1165 here for one reason or another. */
1166 {"align", s_align
, 0},
1167 {"byte", s_cons
, 0},
1168 {"data", s_change_sec
, 'd'},
1169 {"double", s_float_cons
, 'd'},
1170 {"float", s_float_cons
, 'f'},
1171 {"globl", s_mips_globl
, 0},
1172 {"global", s_mips_globl
, 0},
1173 {"hword", s_cons
, 1},
1175 {"long", s_cons
, 2},
1176 {"octa", s_cons
, 4},
1177 {"quad", s_cons
, 3},
1178 {"section", s_change_section
, 0},
1179 {"short", s_cons
, 1},
1180 {"single", s_float_cons
, 'f'},
1181 {"stabn", s_mips_stab
, 'n'},
1182 {"text", s_change_sec
, 't'},
1183 {"word", s_cons
, 2},
1185 { "extern", ecoff_directive_extern
, 0},
1190 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1192 /* These pseudo-ops should be defined by the object file format.
1193 However, a.out doesn't support them, so we have versions here. */
1194 {"aent", s_mips_ent
, 1},
1195 {"bgnb", s_ignore
, 0},
1196 {"end", s_mips_end
, 0},
1197 {"endb", s_ignore
, 0},
1198 {"ent", s_mips_ent
, 0},
1199 {"file", s_mips_file
, 0},
1200 {"fmask", s_mips_mask
, 'F'},
1201 {"frame", s_mips_frame
, 0},
1202 {"loc", s_mips_loc
, 0},
1203 {"mask", s_mips_mask
, 'R'},
1204 {"verstamp", s_ignore
, 0},
1208 extern void pop_insert (const pseudo_typeS
*);
1211 mips_pop_insert (void)
1213 pop_insert (mips_pseudo_table
);
1214 if (! ECOFF_DEBUGGING
)
1215 pop_insert (mips_nonecoff_pseudo_table
);
1218 /* Symbols labelling the current insn. */
1220 struct insn_label_list
1222 struct insn_label_list
*next
;
1226 static struct insn_label_list
*free_insn_labels
;
1227 #define label_list tc_segment_info_data.labels
1229 static void mips_clear_insn_labels (void);
1232 mips_clear_insn_labels (void)
1234 register struct insn_label_list
**pl
;
1235 segment_info_type
*si
;
1239 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1242 si
= seg_info (now_seg
);
1243 *pl
= si
->label_list
;
1244 si
->label_list
= NULL
;
1249 static char *expr_end
;
1251 /* Expressions which appear in instructions. These are set by
1254 static expressionS imm_expr
;
1255 static expressionS imm2_expr
;
1256 static expressionS offset_expr
;
1258 /* Relocs associated with imm_expr and offset_expr. */
1260 static bfd_reloc_code_real_type imm_reloc
[3]
1261 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1262 static bfd_reloc_code_real_type offset_reloc
[3]
1263 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1265 /* These are set by mips16_ip if an explicit extension is used. */
1267 static bfd_boolean mips16_small
, mips16_ext
;
1270 /* The pdr segment for per procedure frame/regmask info. Not used for
1273 static segT pdr_seg
;
1276 /* The default target format to use. */
1279 mips_target_format (void)
1281 switch (OUTPUT_FLAVOR
)
1283 case bfd_target_ecoff_flavour
:
1284 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1285 case bfd_target_coff_flavour
:
1287 case bfd_target_elf_flavour
:
1289 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1290 return (target_big_endian
1291 ? "elf32-bigmips-vxworks"
1292 : "elf32-littlemips-vxworks");
1295 /* This is traditional mips. */
1296 return (target_big_endian
1297 ? (HAVE_64BIT_OBJECTS
1298 ? "elf64-tradbigmips"
1300 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1301 : (HAVE_64BIT_OBJECTS
1302 ? "elf64-tradlittlemips"
1304 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1306 return (target_big_endian
1307 ? (HAVE_64BIT_OBJECTS
1310 ? "elf32-nbigmips" : "elf32-bigmips"))
1311 : (HAVE_64BIT_OBJECTS
1312 ? "elf64-littlemips"
1314 ? "elf32-nlittlemips" : "elf32-littlemips")));
1322 /* Return the length of instruction INSN. */
1324 static inline unsigned int
1325 insn_length (const struct mips_cl_insn
*insn
)
1327 if (!mips_opts
.mips16
)
1329 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1332 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1335 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1340 insn
->use_extend
= FALSE
;
1342 insn
->insn_opcode
= mo
->match
;
1345 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1346 insn
->fixp
[i
] = NULL
;
1347 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1348 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1349 insn
->mips16_absolute_jump_p
= 0;
1352 /* Record the current MIPS16 mode in now_seg. */
1355 mips_record_mips16_mode (void)
1357 segment_info_type
*si
;
1359 si
= seg_info (now_seg
);
1360 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1361 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1364 /* Install INSN at the location specified by its "frag" and "where" fields. */
1367 install_insn (const struct mips_cl_insn
*insn
)
1369 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1370 if (!mips_opts
.mips16
)
1371 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1372 else if (insn
->mips16_absolute_jump_p
)
1374 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1375 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1379 if (insn
->use_extend
)
1381 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1384 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1386 mips_record_mips16_mode ();
1389 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1390 and install the opcode in the new location. */
1393 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1398 insn
->where
= where
;
1399 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1400 if (insn
->fixp
[i
] != NULL
)
1402 insn
->fixp
[i
]->fx_frag
= frag
;
1403 insn
->fixp
[i
]->fx_where
= where
;
1405 install_insn (insn
);
1408 /* Add INSN to the end of the output. */
1411 add_fixed_insn (struct mips_cl_insn
*insn
)
1413 char *f
= frag_more (insn_length (insn
));
1414 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1417 /* Start a variant frag and move INSN to the start of the variant part,
1418 marking it as fixed. The other arguments are as for frag_var. */
1421 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1422 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1424 frag_grow (max_chars
);
1425 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1427 frag_var (rs_machine_dependent
, max_chars
, var
,
1428 subtype
, symbol
, offset
, NULL
);
1431 /* Insert N copies of INSN into the history buffer, starting at
1432 position FIRST. Neither FIRST nor N need to be clipped. */
1435 insert_into_history (unsigned int first
, unsigned int n
,
1436 const struct mips_cl_insn
*insn
)
1438 if (mips_relax
.sequence
!= 2)
1442 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1444 history
[i
] = history
[i
- n
];
1450 /* Emit a nop instruction, recording it in the history buffer. */
1455 add_fixed_insn (NOP_INSN
);
1456 insert_into_history (0, 1, NOP_INSN
);
1459 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1460 the idea is to make it obvious at a glance that each errata is
1464 init_vr4120_conflicts (void)
1466 #define CONFLICT(FIRST, SECOND) \
1467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1469 /* Errata 21 - [D]DIV[U] after [D]MACC */
1470 CONFLICT (MACC
, DIV
);
1471 CONFLICT (DMACC
, DIV
);
1473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1474 CONFLICT (DMULT
, DMULT
);
1475 CONFLICT (DMULT
, DMACC
);
1476 CONFLICT (DMACC
, DMULT
);
1477 CONFLICT (DMACC
, DMACC
);
1479 /* Errata 24 - MT{LO,HI} after [D]MACC */
1480 CONFLICT (MACC
, MTHILO
);
1481 CONFLICT (DMACC
, MTHILO
);
1483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1484 instruction is executed immediately after a MACC or DMACC
1485 instruction, the result of [either instruction] is incorrect." */
1486 CONFLICT (MACC
, MULT
);
1487 CONFLICT (MACC
, DMULT
);
1488 CONFLICT (DMACC
, MULT
);
1489 CONFLICT (DMACC
, DMULT
);
1491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1493 DDIV or DDIVU instruction, the result of the MACC or
1494 DMACC instruction is incorrect.". */
1495 CONFLICT (DMULT
, MACC
);
1496 CONFLICT (DMULT
, DMACC
);
1497 CONFLICT (DIV
, MACC
);
1498 CONFLICT (DIV
, DMACC
);
1508 #define RTYPE_MASK 0x1ff00
1509 #define RTYPE_NUM 0x00100
1510 #define RTYPE_FPU 0x00200
1511 #define RTYPE_FCC 0x00400
1512 #define RTYPE_VEC 0x00800
1513 #define RTYPE_GP 0x01000
1514 #define RTYPE_CP0 0x02000
1515 #define RTYPE_PC 0x04000
1516 #define RTYPE_ACC 0x08000
1517 #define RTYPE_CCC 0x10000
1518 #define RNUM_MASK 0x000ff
1519 #define RWARN 0x80000
1521 #define GENERIC_REGISTER_NUMBERS \
1522 {"$0", RTYPE_NUM | 0}, \
1523 {"$1", RTYPE_NUM | 1}, \
1524 {"$2", RTYPE_NUM | 2}, \
1525 {"$3", RTYPE_NUM | 3}, \
1526 {"$4", RTYPE_NUM | 4}, \
1527 {"$5", RTYPE_NUM | 5}, \
1528 {"$6", RTYPE_NUM | 6}, \
1529 {"$7", RTYPE_NUM | 7}, \
1530 {"$8", RTYPE_NUM | 8}, \
1531 {"$9", RTYPE_NUM | 9}, \
1532 {"$10", RTYPE_NUM | 10}, \
1533 {"$11", RTYPE_NUM | 11}, \
1534 {"$12", RTYPE_NUM | 12}, \
1535 {"$13", RTYPE_NUM | 13}, \
1536 {"$14", RTYPE_NUM | 14}, \
1537 {"$15", RTYPE_NUM | 15}, \
1538 {"$16", RTYPE_NUM | 16}, \
1539 {"$17", RTYPE_NUM | 17}, \
1540 {"$18", RTYPE_NUM | 18}, \
1541 {"$19", RTYPE_NUM | 19}, \
1542 {"$20", RTYPE_NUM | 20}, \
1543 {"$21", RTYPE_NUM | 21}, \
1544 {"$22", RTYPE_NUM | 22}, \
1545 {"$23", RTYPE_NUM | 23}, \
1546 {"$24", RTYPE_NUM | 24}, \
1547 {"$25", RTYPE_NUM | 25}, \
1548 {"$26", RTYPE_NUM | 26}, \
1549 {"$27", RTYPE_NUM | 27}, \
1550 {"$28", RTYPE_NUM | 28}, \
1551 {"$29", RTYPE_NUM | 29}, \
1552 {"$30", RTYPE_NUM | 30}, \
1553 {"$31", RTYPE_NUM | 31}
1555 #define FPU_REGISTER_NAMES \
1556 {"$f0", RTYPE_FPU | 0}, \
1557 {"$f1", RTYPE_FPU | 1}, \
1558 {"$f2", RTYPE_FPU | 2}, \
1559 {"$f3", RTYPE_FPU | 3}, \
1560 {"$f4", RTYPE_FPU | 4}, \
1561 {"$f5", RTYPE_FPU | 5}, \
1562 {"$f6", RTYPE_FPU | 6}, \
1563 {"$f7", RTYPE_FPU | 7}, \
1564 {"$f8", RTYPE_FPU | 8}, \
1565 {"$f9", RTYPE_FPU | 9}, \
1566 {"$f10", RTYPE_FPU | 10}, \
1567 {"$f11", RTYPE_FPU | 11}, \
1568 {"$f12", RTYPE_FPU | 12}, \
1569 {"$f13", RTYPE_FPU | 13}, \
1570 {"$f14", RTYPE_FPU | 14}, \
1571 {"$f15", RTYPE_FPU | 15}, \
1572 {"$f16", RTYPE_FPU | 16}, \
1573 {"$f17", RTYPE_FPU | 17}, \
1574 {"$f18", RTYPE_FPU | 18}, \
1575 {"$f19", RTYPE_FPU | 19}, \
1576 {"$f20", RTYPE_FPU | 20}, \
1577 {"$f21", RTYPE_FPU | 21}, \
1578 {"$f22", RTYPE_FPU | 22}, \
1579 {"$f23", RTYPE_FPU | 23}, \
1580 {"$f24", RTYPE_FPU | 24}, \
1581 {"$f25", RTYPE_FPU | 25}, \
1582 {"$f26", RTYPE_FPU | 26}, \
1583 {"$f27", RTYPE_FPU | 27}, \
1584 {"$f28", RTYPE_FPU | 28}, \
1585 {"$f29", RTYPE_FPU | 29}, \
1586 {"$f30", RTYPE_FPU | 30}, \
1587 {"$f31", RTYPE_FPU | 31}
1589 #define FPU_CONDITION_CODE_NAMES \
1590 {"$fcc0", RTYPE_FCC | 0}, \
1591 {"$fcc1", RTYPE_FCC | 1}, \
1592 {"$fcc2", RTYPE_FCC | 2}, \
1593 {"$fcc3", RTYPE_FCC | 3}, \
1594 {"$fcc4", RTYPE_FCC | 4}, \
1595 {"$fcc5", RTYPE_FCC | 5}, \
1596 {"$fcc6", RTYPE_FCC | 6}, \
1597 {"$fcc7", RTYPE_FCC | 7}
1599 #define COPROC_CONDITION_CODE_NAMES \
1600 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1601 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1602 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1603 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1604 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1605 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1606 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1607 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1609 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1610 {"$a4", RTYPE_GP | 8}, \
1611 {"$a5", RTYPE_GP | 9}, \
1612 {"$a6", RTYPE_GP | 10}, \
1613 {"$a7", RTYPE_GP | 11}, \
1614 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1615 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1616 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1617 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1618 {"$t0", RTYPE_GP | 12}, \
1619 {"$t1", RTYPE_GP | 13}, \
1620 {"$t2", RTYPE_GP | 14}, \
1621 {"$t3", RTYPE_GP | 15}
1623 #define O32_SYMBOLIC_REGISTER_NAMES \
1624 {"$t0", RTYPE_GP | 8}, \
1625 {"$t1", RTYPE_GP | 9}, \
1626 {"$t2", RTYPE_GP | 10}, \
1627 {"$t3", RTYPE_GP | 11}, \
1628 {"$t4", RTYPE_GP | 12}, \
1629 {"$t5", RTYPE_GP | 13}, \
1630 {"$t6", RTYPE_GP | 14}, \
1631 {"$t7", RTYPE_GP | 15}, \
1632 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1633 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1634 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1635 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1637 /* Remaining symbolic register names */
1638 #define SYMBOLIC_REGISTER_NAMES \
1639 {"$zero", RTYPE_GP | 0}, \
1640 {"$at", RTYPE_GP | 1}, \
1641 {"$AT", RTYPE_GP | 1}, \
1642 {"$v0", RTYPE_GP | 2}, \
1643 {"$v1", RTYPE_GP | 3}, \
1644 {"$a0", RTYPE_GP | 4}, \
1645 {"$a1", RTYPE_GP | 5}, \
1646 {"$a2", RTYPE_GP | 6}, \
1647 {"$a3", RTYPE_GP | 7}, \
1648 {"$s0", RTYPE_GP | 16}, \
1649 {"$s1", RTYPE_GP | 17}, \
1650 {"$s2", RTYPE_GP | 18}, \
1651 {"$s3", RTYPE_GP | 19}, \
1652 {"$s4", RTYPE_GP | 20}, \
1653 {"$s5", RTYPE_GP | 21}, \
1654 {"$s6", RTYPE_GP | 22}, \
1655 {"$s7", RTYPE_GP | 23}, \
1656 {"$t8", RTYPE_GP | 24}, \
1657 {"$t9", RTYPE_GP | 25}, \
1658 {"$k0", RTYPE_GP | 26}, \
1659 {"$kt0", RTYPE_GP | 26}, \
1660 {"$k1", RTYPE_GP | 27}, \
1661 {"$kt1", RTYPE_GP | 27}, \
1662 {"$gp", RTYPE_GP | 28}, \
1663 {"$sp", RTYPE_GP | 29}, \
1664 {"$s8", RTYPE_GP | 30}, \
1665 {"$fp", RTYPE_GP | 30}, \
1666 {"$ra", RTYPE_GP | 31}
1668 #define MIPS16_SPECIAL_REGISTER_NAMES \
1669 {"$pc", RTYPE_PC | 0}
1671 #define MDMX_VECTOR_REGISTER_NAMES \
1672 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1673 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1674 {"$v2", RTYPE_VEC | 2}, \
1675 {"$v3", RTYPE_VEC | 3}, \
1676 {"$v4", RTYPE_VEC | 4}, \
1677 {"$v5", RTYPE_VEC | 5}, \
1678 {"$v6", RTYPE_VEC | 6}, \
1679 {"$v7", RTYPE_VEC | 7}, \
1680 {"$v8", RTYPE_VEC | 8}, \
1681 {"$v9", RTYPE_VEC | 9}, \
1682 {"$v10", RTYPE_VEC | 10}, \
1683 {"$v11", RTYPE_VEC | 11}, \
1684 {"$v12", RTYPE_VEC | 12}, \
1685 {"$v13", RTYPE_VEC | 13}, \
1686 {"$v14", RTYPE_VEC | 14}, \
1687 {"$v15", RTYPE_VEC | 15}, \
1688 {"$v16", RTYPE_VEC | 16}, \
1689 {"$v17", RTYPE_VEC | 17}, \
1690 {"$v18", RTYPE_VEC | 18}, \
1691 {"$v19", RTYPE_VEC | 19}, \
1692 {"$v20", RTYPE_VEC | 20}, \
1693 {"$v21", RTYPE_VEC | 21}, \
1694 {"$v22", RTYPE_VEC | 22}, \
1695 {"$v23", RTYPE_VEC | 23}, \
1696 {"$v24", RTYPE_VEC | 24}, \
1697 {"$v25", RTYPE_VEC | 25}, \
1698 {"$v26", RTYPE_VEC | 26}, \
1699 {"$v27", RTYPE_VEC | 27}, \
1700 {"$v28", RTYPE_VEC | 28}, \
1701 {"$v29", RTYPE_VEC | 29}, \
1702 {"$v30", RTYPE_VEC | 30}, \
1703 {"$v31", RTYPE_VEC | 31}
1705 #define MIPS_DSP_ACCUMULATOR_NAMES \
1706 {"$ac0", RTYPE_ACC | 0}, \
1707 {"$ac1", RTYPE_ACC | 1}, \
1708 {"$ac2", RTYPE_ACC | 2}, \
1709 {"$ac3", RTYPE_ACC | 3}
1711 static const struct regname reg_names
[] = {
1712 GENERIC_REGISTER_NUMBERS
,
1714 FPU_CONDITION_CODE_NAMES
,
1715 COPROC_CONDITION_CODE_NAMES
,
1717 /* The $txx registers depends on the abi,
1718 these will be added later into the symbol table from
1719 one of the tables below once mips_abi is set after
1720 parsing of arguments from the command line. */
1721 SYMBOLIC_REGISTER_NAMES
,
1723 MIPS16_SPECIAL_REGISTER_NAMES
,
1724 MDMX_VECTOR_REGISTER_NAMES
,
1725 MIPS_DSP_ACCUMULATOR_NAMES
,
1729 static const struct regname reg_names_o32
[] = {
1730 O32_SYMBOLIC_REGISTER_NAMES
,
1734 static const struct regname reg_names_n32n64
[] = {
1735 N32N64_SYMBOLIC_REGISTER_NAMES
,
1740 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1747 /* Find end of name. */
1749 if (is_name_beginner (*e
))
1751 while (is_part_of_name (*e
))
1754 /* Terminate name. */
1758 /* Look for a register symbol. */
1759 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1761 int r
= S_GET_VALUE (symbolP
);
1763 reg
= r
& RNUM_MASK
;
1764 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1765 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1766 reg
= (r
& RNUM_MASK
) - 2;
1768 /* Else see if this is a register defined in an itbl entry. */
1769 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1776 if (itbl_get_reg_val (n
, &r
))
1777 reg
= r
& RNUM_MASK
;
1780 /* Advance to next token if a register was recognised. */
1783 else if (types
& RWARN
)
1784 as_warn ("Unrecognized register name `%s'", *s
);
1792 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1793 architecture. If EXPANSIONP is TRUE then this check is done while
1794 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1797 is_opcode_valid (const struct mips_opcode
*mo
, bfd_boolean expansionp
)
1799 int isa
= mips_opts
.isa
;
1802 if (mips_opts
.ase_mdmx
)
1804 if (mips_opts
.ase_dsp
)
1806 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1808 if (mips_opts
.ase_dspr2
)
1810 if (mips_opts
.ase_mt
)
1812 if (mips_opts
.ase_mips3d
)
1814 if (mips_opts
.ase_smartmips
)
1815 isa
|= INSN_SMARTMIPS
;
1817 /* For user code we don't check for mips_opts.mips16 since we want
1818 to allow jalx if -mips16 was specified on the command line. */
1819 if (expansionp
? mips_opts
.mips16
: file_ase_mips16
)
1822 /* Don't accept instructions based on the ISA if the CPU does not implement
1823 all the coprocessor insns. */
1824 if (NO_ISA_COP (mips_opts
.arch
)
1825 && COP_INSN (mo
->pinfo
))
1828 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1831 /* Check whether the instruction or macro requires single-precision or
1832 double-precision floating-point support. Note that this information is
1833 stored differently in the opcode table for insns and macros. */
1834 if (mo
->pinfo
== INSN_MACRO
)
1836 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1837 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1841 fp_s
= mo
->pinfo
& FP_S
;
1842 fp_d
= mo
->pinfo
& FP_D
;
1845 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1848 if (fp_s
&& mips_opts
.soft_float
)
1854 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1855 selected ISA and architecture. */
1858 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1860 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1863 /* This function is called once, at assembler startup time. It should set up
1864 all the tables, etc. that the MD part of the assembler will need. */
1869 const char *retval
= NULL
;
1873 if (mips_pic
!= NO_PIC
)
1875 if (g_switch_seen
&& g_switch_value
!= 0)
1876 as_bad (_("-G may not be used in position-independent code"));
1880 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1881 as_warn (_("Could not set architecture and machine"));
1883 op_hash
= hash_new ();
1885 for (i
= 0; i
< NUMOPCODES
;)
1887 const char *name
= mips_opcodes
[i
].name
;
1889 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1892 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1893 mips_opcodes
[i
].name
, retval
);
1894 /* Probably a memory allocation problem? Give up now. */
1895 as_fatal (_("Broken assembler. No assembly attempted."));
1899 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1901 if (!validate_mips_insn (&mips_opcodes
[i
]))
1903 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1905 create_insn (&nop_insn
, mips_opcodes
+ i
);
1906 nop_insn
.fixed_p
= 1;
1911 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1914 mips16_op_hash
= hash_new ();
1917 while (i
< bfd_mips16_num_opcodes
)
1919 const char *name
= mips16_opcodes
[i
].name
;
1921 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1923 as_fatal (_("internal: can't hash `%s': %s"),
1924 mips16_opcodes
[i
].name
, retval
);
1927 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1928 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1929 != mips16_opcodes
[i
].match
))
1931 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1932 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1935 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1937 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1938 mips16_nop_insn
.fixed_p
= 1;
1942 while (i
< bfd_mips16_num_opcodes
1943 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1947 as_fatal (_("Broken assembler. No assembly attempted."));
1949 /* We add all the general register names to the symbol table. This
1950 helps us detect invalid uses of them. */
1951 for (i
= 0; reg_names
[i
].name
; i
++)
1952 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1953 reg_names
[i
].num
, /* & RNUM_MASK, */
1954 &zero_address_frag
));
1956 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1957 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1958 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1959 &zero_address_frag
));
1961 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1962 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1963 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1964 &zero_address_frag
));
1966 mips_no_prev_insn ();
1969 mips_cprmask
[0] = 0;
1970 mips_cprmask
[1] = 0;
1971 mips_cprmask
[2] = 0;
1972 mips_cprmask
[3] = 0;
1974 /* set the default alignment for the text section (2**2) */
1975 record_alignment (text_section
, 2);
1977 bfd_set_gp_size (stdoutput
, g_switch_value
);
1982 /* On a native system other than VxWorks, sections must be aligned
1983 to 16 byte boundaries. When configured for an embedded ELF
1984 target, we don't bother. */
1985 if (strncmp (TARGET_OS
, "elf", 3) != 0
1986 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
1988 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1989 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1990 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1993 /* Create a .reginfo section for register masks and a .mdebug
1994 section for debugging information. */
2002 subseg
= now_subseg
;
2004 /* The ABI says this section should be loaded so that the
2005 running program can access it. However, we don't load it
2006 if we are configured for an embedded target */
2007 flags
= SEC_READONLY
| SEC_DATA
;
2008 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2009 flags
|= SEC_ALLOC
| SEC_LOAD
;
2011 if (mips_abi
!= N64_ABI
)
2013 sec
= subseg_new (".reginfo", (subsegT
) 0);
2015 bfd_set_section_flags (stdoutput
, sec
, flags
);
2016 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2018 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2022 /* The 64-bit ABI uses a .MIPS.options section rather than
2023 .reginfo section. */
2024 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2025 bfd_set_section_flags (stdoutput
, sec
, flags
);
2026 bfd_set_section_alignment (stdoutput
, sec
, 3);
2028 /* Set up the option header. */
2030 Elf_Internal_Options opthdr
;
2033 opthdr
.kind
= ODK_REGINFO
;
2034 opthdr
.size
= (sizeof (Elf_External_Options
)
2035 + sizeof (Elf64_External_RegInfo
));
2038 f
= frag_more (sizeof (Elf_External_Options
));
2039 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2040 (Elf_External_Options
*) f
);
2042 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2046 if (ECOFF_DEBUGGING
)
2048 sec
= subseg_new (".mdebug", (subsegT
) 0);
2049 (void) bfd_set_section_flags (stdoutput
, sec
,
2050 SEC_HAS_CONTENTS
| SEC_READONLY
);
2051 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2053 else if (mips_flag_pdr
)
2055 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2056 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2057 SEC_READONLY
| SEC_RELOC
2059 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2062 subseg_set (seg
, subseg
);
2065 #endif /* OBJ_ELF */
2067 if (! ECOFF_DEBUGGING
)
2070 if (mips_fix_vr4120
)
2071 init_vr4120_conflicts ();
2077 if (! ECOFF_DEBUGGING
)
2082 md_assemble (char *str
)
2084 struct mips_cl_insn insn
;
2085 bfd_reloc_code_real_type unused_reloc
[3]
2086 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2088 imm_expr
.X_op
= O_absent
;
2089 imm2_expr
.X_op
= O_absent
;
2090 offset_expr
.X_op
= O_absent
;
2091 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2092 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2093 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2094 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2095 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2096 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2098 if (mips_opts
.mips16
)
2099 mips16_ip (str
, &insn
);
2102 mips_ip (str
, &insn
);
2103 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2104 str
, insn
.insn_opcode
));
2109 as_bad ("%s `%s'", insn_error
, str
);
2113 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2116 if (mips_opts
.mips16
)
2117 mips16_macro (&insn
);
2124 if (imm_expr
.X_op
!= O_absent
)
2125 append_insn (&insn
, &imm_expr
, imm_reloc
);
2126 else if (offset_expr
.X_op
!= O_absent
)
2127 append_insn (&insn
, &offset_expr
, offset_reloc
);
2129 append_insn (&insn
, NULL
, unused_reloc
);
2133 /* Convenience functions for abstracting away the differences between
2134 MIPS16 and non-MIPS16 relocations. */
2136 static inline bfd_boolean
2137 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2141 case BFD_RELOC_MIPS16_JMP
:
2142 case BFD_RELOC_MIPS16_GPREL
:
2143 case BFD_RELOC_MIPS16_GOT16
:
2144 case BFD_RELOC_MIPS16_CALL16
:
2145 case BFD_RELOC_MIPS16_HI16_S
:
2146 case BFD_RELOC_MIPS16_HI16
:
2147 case BFD_RELOC_MIPS16_LO16
:
2155 static inline bfd_boolean
2156 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2158 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2161 static inline bfd_boolean
2162 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2164 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2167 static inline bfd_boolean
2168 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2170 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2173 /* Return true if the given relocation might need a matching %lo().
2174 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2175 need a matching %lo() when applied to local symbols. */
2177 static inline bfd_boolean
2178 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2180 return (HAVE_IN_PLACE_ADDENDS
2181 && (hi16_reloc_p (reloc
)
2182 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2183 all GOT16 relocations evaluate to "G". */
2184 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2187 /* Return the type of %lo() reloc needed by RELOC, given that
2188 reloc_needs_lo_p. */
2190 static inline bfd_reloc_code_real_type
2191 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2193 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2196 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2199 static inline bfd_boolean
2200 fixup_has_matching_lo_p (fixS
*fixp
)
2202 return (fixp
->fx_next
!= NULL
2203 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2204 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2205 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2208 /* See whether instruction IP reads register REG. CLASS is the type
2212 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2213 enum mips_regclass
class)
2215 if (class == MIPS16_REG
)
2217 assert (mips_opts
.mips16
);
2218 reg
= mips16_to_32_reg_map
[reg
];
2219 class = MIPS_GR_REG
;
2222 /* Don't report on general register ZERO, since it never changes. */
2223 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2226 if (class == MIPS_FP_REG
)
2228 assert (! mips_opts
.mips16
);
2229 /* If we are called with either $f0 or $f1, we must check $f0.
2230 This is not optimal, because it will introduce an unnecessary
2231 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2232 need to distinguish reading both $f0 and $f1 or just one of
2233 them. Note that we don't have to check the other way,
2234 because there is no instruction that sets both $f0 and $f1
2235 and requires a delay. */
2236 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2237 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2238 == (reg
&~ (unsigned) 1)))
2240 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2241 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2242 == (reg
&~ (unsigned) 1)))
2245 else if (! mips_opts
.mips16
)
2247 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2248 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2250 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2251 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2256 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2257 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2259 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2260 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2262 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2263 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2266 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2268 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2270 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2272 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2273 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2280 /* This function returns true if modifying a register requires a
2284 reg_needs_delay (unsigned int reg
)
2286 unsigned long prev_pinfo
;
2288 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2289 if (! mips_opts
.noreorder
2290 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2291 && ! gpr_interlocks
)
2292 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2293 && ! cop_interlocks
)))
2295 /* A load from a coprocessor or from memory. All load delays
2296 delay the use of general register rt for one instruction. */
2297 /* Itbl support may require additional care here. */
2298 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2299 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2306 /* Move all labels in insn_labels to the current insertion point. */
2309 mips_move_labels (void)
2311 segment_info_type
*si
= seg_info (now_seg
);
2312 struct insn_label_list
*l
;
2315 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2317 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2318 symbol_set_frag (l
->label
, frag_now
);
2319 val
= (valueT
) frag_now_fix ();
2320 /* mips16 text labels are stored as odd. */
2321 if (mips_opts
.mips16
)
2323 S_SET_VALUE (l
->label
, val
);
2328 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2330 bfd_boolean linkonce
= FALSE
;
2331 segT symseg
= S_GET_SEGMENT (sym
);
2333 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2335 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2338 /* The GNU toolchain uses an extension for ELF: a section
2339 beginning with the magic string .gnu.linkonce is a
2340 linkonce section. */
2341 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2342 sizeof ".gnu.linkonce" - 1) == 0)
2349 /* Mark instruction labels in mips16 mode. This permits the linker to
2350 handle them specially, such as generating jalx instructions when
2351 needed. We also make them odd for the duration of the assembly, in
2352 order to generate the right sort of code. We will make them even
2353 in the adjust_symtab routine, while leaving them marked. This is
2354 convenient for the debugger and the disassembler. The linker knows
2355 to make them odd again. */
2358 mips16_mark_labels (void)
2360 segment_info_type
*si
= seg_info (now_seg
);
2361 struct insn_label_list
*l
;
2363 if (!mips_opts
.mips16
)
2366 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2368 symbolS
*label
= l
->label
;
2370 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2372 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2374 if ((S_GET_VALUE (label
) & 1) == 0
2375 /* Don't adjust the address if the label is global or weak, or
2376 in a link-once section, since we'll be emitting symbol reloc
2377 references to it which will be patched up by the linker, and
2378 the final value of the symbol may or may not be MIPS16. */
2379 && ! S_IS_WEAK (label
)
2380 && ! S_IS_EXTERNAL (label
)
2381 && ! s_is_linkonce (label
, now_seg
))
2382 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2386 /* End the current frag. Make it a variant frag and record the
2390 relax_close_frag (void)
2392 mips_macro_warning
.first_frag
= frag_now
;
2393 frag_var (rs_machine_dependent
, 0, 0,
2394 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2395 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2397 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2398 mips_relax
.first_fixup
= 0;
2401 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2402 See the comment above RELAX_ENCODE for more details. */
2405 relax_start (symbolS
*symbol
)
2407 assert (mips_relax
.sequence
== 0);
2408 mips_relax
.sequence
= 1;
2409 mips_relax
.symbol
= symbol
;
2412 /* Start generating the second version of a relaxable sequence.
2413 See the comment above RELAX_ENCODE for more details. */
2418 assert (mips_relax
.sequence
== 1);
2419 mips_relax
.sequence
= 2;
2422 /* End the current relaxable sequence. */
2427 assert (mips_relax
.sequence
== 2);
2428 relax_close_frag ();
2429 mips_relax
.sequence
= 0;
2432 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2433 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2434 by VR4120 errata. */
2437 classify_vr4120_insn (const char *name
)
2439 if (strncmp (name
, "macc", 4) == 0)
2440 return FIX_VR4120_MACC
;
2441 if (strncmp (name
, "dmacc", 5) == 0)
2442 return FIX_VR4120_DMACC
;
2443 if (strncmp (name
, "mult", 4) == 0)
2444 return FIX_VR4120_MULT
;
2445 if (strncmp (name
, "dmult", 5) == 0)
2446 return FIX_VR4120_DMULT
;
2447 if (strstr (name
, "div"))
2448 return FIX_VR4120_DIV
;
2449 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2450 return FIX_VR4120_MTHILO
;
2451 return NUM_FIX_VR4120_CLASSES
;
2454 /* Return the number of instructions that must separate INSN1 and INSN2,
2455 where INSN1 is the earlier instruction. Return the worst-case value
2456 for any INSN2 if INSN2 is null. */
2459 insns_between (const struct mips_cl_insn
*insn1
,
2460 const struct mips_cl_insn
*insn2
)
2462 unsigned long pinfo1
, pinfo2
;
2464 /* This function needs to know which pinfo flags are set for INSN2
2465 and which registers INSN2 uses. The former is stored in PINFO2 and
2466 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2467 will have every flag set and INSN2_USES_REG will always return true. */
2468 pinfo1
= insn1
->insn_mo
->pinfo
;
2469 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2471 #define INSN2_USES_REG(REG, CLASS) \
2472 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2474 /* For most targets, write-after-read dependencies on the HI and LO
2475 registers must be separated by at least two instructions. */
2476 if (!hilo_interlocks
)
2478 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2480 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2484 /* If we're working around r7000 errata, there must be two instructions
2485 between an mfhi or mflo and any instruction that uses the result. */
2486 if (mips_7000_hilo_fix
2487 && MF_HILO_INSN (pinfo1
)
2488 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2491 /* If working around VR4120 errata, check for combinations that need
2492 a single intervening instruction. */
2493 if (mips_fix_vr4120
)
2495 unsigned int class1
, class2
;
2497 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2498 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2502 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2503 if (vr4120_conflicts
[class1
] & (1 << class2
))
2508 if (!mips_opts
.mips16
)
2510 /* Check for GPR or coprocessor load delays. All such delays
2511 are on the RT register. */
2512 /* Itbl support may require additional care here. */
2513 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2514 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2516 know (pinfo1
& INSN_WRITE_GPR_T
);
2517 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2521 /* Check for generic coprocessor hazards.
2523 This case is not handled very well. There is no special
2524 knowledge of CP0 handling, and the coprocessors other than
2525 the floating point unit are not distinguished at all. */
2526 /* Itbl support may require additional care here. FIXME!
2527 Need to modify this to include knowledge about
2528 user specified delays! */
2529 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2530 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2532 /* Handle cases where INSN1 writes to a known general coprocessor
2533 register. There must be a one instruction delay before INSN2
2534 if INSN2 reads that register, otherwise no delay is needed. */
2535 if (pinfo1
& INSN_WRITE_FPR_T
)
2537 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2540 else if (pinfo1
& INSN_WRITE_FPR_S
)
2542 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2547 /* Read-after-write dependencies on the control registers
2548 require a two-instruction gap. */
2549 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2550 && (pinfo2
& INSN_READ_COND_CODE
))
2553 /* We don't know exactly what INSN1 does. If INSN2 is
2554 also a coprocessor instruction, assume there must be
2555 a one instruction gap. */
2556 if (pinfo2
& INSN_COP
)
2561 /* Check for read-after-write dependencies on the coprocessor
2562 control registers in cases where INSN1 does not need a general
2563 coprocessor delay. This means that INSN1 is a floating point
2564 comparison instruction. */
2565 /* Itbl support may require additional care here. */
2566 else if (!cop_interlocks
2567 && (pinfo1
& INSN_WRITE_COND_CODE
)
2568 && (pinfo2
& INSN_READ_COND_CODE
))
2572 #undef INSN2_USES_REG
2577 /* Return the number of nops that would be needed to work around the
2578 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2579 the MAX_VR4130_NOPS instructions described by HISTORY. */
2582 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2583 const struct mips_cl_insn
*insn
)
2587 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2588 are not affected by the errata. */
2590 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2591 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2592 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2595 /* Search for the first MFLO or MFHI. */
2596 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2597 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2599 /* Extract the destination register. */
2600 if (mips_opts
.mips16
)
2601 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2603 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2605 /* No nops are needed if INSN reads that register. */
2606 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2609 /* ...or if any of the intervening instructions do. */
2610 for (j
= 0; j
< i
; j
++)
2611 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2614 return MAX_VR4130_NOPS
- i
;
2619 /* Return the number of nops that would be needed if instruction INSN
2620 immediately followed the MAX_NOPS instructions given by HISTORY,
2621 where HISTORY[0] is the most recent instruction. If INSN is null,
2622 return the worse-case number of nops for any instruction. */
2625 nops_for_insn (const struct mips_cl_insn
*history
,
2626 const struct mips_cl_insn
*insn
)
2628 int i
, nops
, tmp_nops
;
2631 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2632 if (!history
[i
].noreorder_p
)
2634 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2635 if (tmp_nops
> nops
)
2639 if (mips_fix_vr4130
)
2641 tmp_nops
= nops_for_vr4130 (history
, insn
);
2642 if (tmp_nops
> nops
)
2649 /* The variable arguments provide NUM_INSNS extra instructions that
2650 might be added to HISTORY. Return the largest number of nops that
2651 would be needed after the extended sequence. */
2654 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2657 struct mips_cl_insn buffer
[MAX_NOPS
];
2658 struct mips_cl_insn
*cursor
;
2661 va_start (args
, history
);
2662 cursor
= buffer
+ num_insns
;
2663 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2664 while (cursor
> buffer
)
2665 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2667 nops
= nops_for_insn (buffer
, NULL
);
2672 /* Like nops_for_insn, but if INSN is a branch, take into account the
2673 worst-case delay for the branch target. */
2676 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2677 const struct mips_cl_insn
*insn
)
2681 nops
= nops_for_insn (history
, insn
);
2682 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2683 | INSN_COND_BRANCH_DELAY
2684 | INSN_COND_BRANCH_LIKELY
))
2686 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2687 if (tmp_nops
> nops
)
2690 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2692 tmp_nops
= nops_for_sequence (1, history
, insn
);
2693 if (tmp_nops
> nops
)
2699 /* Output an instruction. IP is the instruction information.
2700 ADDRESS_EXPR is an operand of the instruction to be used with
2704 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2705 bfd_reloc_code_real_type
*reloc_type
)
2707 unsigned long prev_pinfo
, pinfo
;
2708 relax_stateT prev_insn_frag_type
= 0;
2709 bfd_boolean relaxed_branch
= FALSE
;
2710 segment_info_type
*si
= seg_info (now_seg
);
2712 /* Mark instruction labels in mips16 mode. */
2713 mips16_mark_labels ();
2715 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2716 pinfo
= ip
->insn_mo
->pinfo
;
2718 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2720 /* There are a lot of optimizations we could do that we don't.
2721 In particular, we do not, in general, reorder instructions.
2722 If you use gcc with optimization, it will reorder
2723 instructions and generally do much more optimization then we
2724 do here; repeating all that work in the assembler would only
2725 benefit hand written assembly code, and does not seem worth
2727 int nops
= (mips_optimize
== 0
2728 ? nops_for_insn (history
, NULL
)
2729 : nops_for_insn_or_target (history
, ip
));
2733 unsigned long old_frag_offset
;
2736 old_frag
= frag_now
;
2737 old_frag_offset
= frag_now_fix ();
2739 for (i
= 0; i
< nops
; i
++)
2744 listing_prev_line ();
2745 /* We may be at the start of a variant frag. In case we
2746 are, make sure there is enough space for the frag
2747 after the frags created by listing_prev_line. The
2748 argument to frag_grow here must be at least as large
2749 as the argument to all other calls to frag_grow in
2750 this file. We don't have to worry about being in the
2751 middle of a variant frag, because the variants insert
2752 all needed nop instructions themselves. */
2756 mips_move_labels ();
2758 #ifndef NO_ECOFF_DEBUGGING
2759 if (ECOFF_DEBUGGING
)
2760 ecoff_fix_loc (old_frag
, old_frag_offset
);
2764 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2766 /* Work out how many nops in prev_nop_frag are needed by IP. */
2767 int nops
= nops_for_insn_or_target (history
, ip
);
2768 assert (nops
<= prev_nop_frag_holds
);
2770 /* Enforce NOPS as a minimum. */
2771 if (nops
> prev_nop_frag_required
)
2772 prev_nop_frag_required
= nops
;
2774 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2776 /* Settle for the current number of nops. Update the history
2777 accordingly (for the benefit of any future .set reorder code). */
2778 prev_nop_frag
= NULL
;
2779 insert_into_history (prev_nop_frag_since
,
2780 prev_nop_frag_holds
, NOP_INSN
);
2784 /* Allow this instruction to replace one of the nops that was
2785 tentatively added to prev_nop_frag. */
2786 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2787 prev_nop_frag_holds
--;
2788 prev_nop_frag_since
++;
2793 /* The value passed to dwarf2_emit_insn is the distance between
2794 the beginning of the current instruction and the address that
2795 should be recorded in the debug tables. For MIPS16 debug info
2796 we want to use ISA-encoded addresses, so we pass -1 for an
2797 address higher by one than the current. */
2798 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2801 /* Record the frag type before frag_var. */
2802 if (history
[0].frag
)
2803 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2806 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2807 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2808 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2809 && mips_relax_branch
2810 /* Don't try branch relaxation within .set nomacro, or within
2811 .set noat if we use $at for PIC computations. If it turns
2812 out that the branch was out-of-range, we'll get an error. */
2813 && !mips_opts
.warn_about_macros
2814 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2815 && !mips_opts
.mips16
)
2817 relaxed_branch
= TRUE
;
2818 add_relaxed_insn (ip
, (relaxed_branch_length
2820 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2821 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2824 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2825 pinfo
& INSN_COND_BRANCH_LIKELY
,
2826 pinfo
& INSN_WRITE_GPR_31
,
2828 address_expr
->X_add_symbol
,
2829 address_expr
->X_add_number
);
2830 *reloc_type
= BFD_RELOC_UNUSED
;
2832 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2834 /* We need to set up a variant frag. */
2835 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2836 add_relaxed_insn (ip
, 4, 0,
2838 (*reloc_type
- BFD_RELOC_UNUSED
,
2839 mips16_small
, mips16_ext
,
2840 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2841 history
[0].mips16_absolute_jump_p
),
2842 make_expr_symbol (address_expr
), 0);
2844 else if (mips_opts
.mips16
2846 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2848 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2849 /* Make sure there is enough room to swap this instruction with
2850 a following jump instruction. */
2852 add_fixed_insn (ip
);
2856 if (mips_opts
.mips16
2857 && mips_opts
.noreorder
2858 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2859 as_warn (_("extended instruction in delay slot"));
2861 if (mips_relax
.sequence
)
2863 /* If we've reached the end of this frag, turn it into a variant
2864 frag and record the information for the instructions we've
2866 if (frag_room () < 4)
2867 relax_close_frag ();
2868 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2871 if (mips_relax
.sequence
!= 2)
2872 mips_macro_warning
.sizes
[0] += 4;
2873 if (mips_relax
.sequence
!= 1)
2874 mips_macro_warning
.sizes
[1] += 4;
2876 if (mips_opts
.mips16
)
2879 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2881 add_fixed_insn (ip
);
2884 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2886 if (address_expr
->X_op
== O_constant
)
2890 switch (*reloc_type
)
2893 ip
->insn_opcode
|= address_expr
->X_add_number
;
2896 case BFD_RELOC_MIPS_HIGHEST
:
2897 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2898 ip
->insn_opcode
|= tmp
& 0xffff;
2901 case BFD_RELOC_MIPS_HIGHER
:
2902 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2903 ip
->insn_opcode
|= tmp
& 0xffff;
2906 case BFD_RELOC_HI16_S
:
2907 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2908 ip
->insn_opcode
|= tmp
& 0xffff;
2911 case BFD_RELOC_HI16
:
2912 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2915 case BFD_RELOC_UNUSED
:
2916 case BFD_RELOC_LO16
:
2917 case BFD_RELOC_MIPS_GOT_DISP
:
2918 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2921 case BFD_RELOC_MIPS_JMP
:
2922 if ((address_expr
->X_add_number
& 3) != 0)
2923 as_bad (_("jump to misaligned address (0x%lx)"),
2924 (unsigned long) address_expr
->X_add_number
);
2925 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2928 case BFD_RELOC_MIPS16_JMP
:
2929 if ((address_expr
->X_add_number
& 3) != 0)
2930 as_bad (_("jump to misaligned address (0x%lx)"),
2931 (unsigned long) address_expr
->X_add_number
);
2933 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2934 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2935 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2938 case BFD_RELOC_16_PCREL_S2
:
2939 if ((address_expr
->X_add_number
& 3) != 0)
2940 as_bad (_("branch to misaligned address (0x%lx)"),
2941 (unsigned long) address_expr
->X_add_number
);
2942 if (mips_relax_branch
)
2944 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2945 as_bad (_("branch address range overflow (0x%lx)"),
2946 (unsigned long) address_expr
->X_add_number
);
2947 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2954 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2957 reloc_howto_type
*howto
;
2960 /* In a compound relocation, it is the final (outermost)
2961 operator that determines the relocated field. */
2962 for (i
= 1; i
< 3; i
++)
2963 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2966 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2969 /* To reproduce this failure try assembling gas/testsuites/
2970 gas/mips/mips16-intermix.s with a mips-ecoff targeted
2972 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
2973 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
2976 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2977 bfd_get_reloc_size (howto
),
2979 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2982 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2983 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2984 && ip
->fixp
[0]->fx_addsy
)
2985 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2987 /* These relocations can have an addend that won't fit in
2988 4 octets for 64bit assembly. */
2990 && ! howto
->partial_inplace
2991 && (reloc_type
[0] == BFD_RELOC_16
2992 || reloc_type
[0] == BFD_RELOC_32
2993 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2994 || reloc_type
[0] == BFD_RELOC_GPREL16
2995 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2996 || reloc_type
[0] == BFD_RELOC_GPREL32
2997 || reloc_type
[0] == BFD_RELOC_64
2998 || reloc_type
[0] == BFD_RELOC_CTOR
2999 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3000 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3001 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3002 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3003 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3004 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3005 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3006 || hi16_reloc_p (reloc_type
[0])
3007 || lo16_reloc_p (reloc_type
[0])))
3008 ip
->fixp
[0]->fx_no_overflow
= 1;
3010 if (mips_relax
.sequence
)
3012 if (mips_relax
.first_fixup
== 0)
3013 mips_relax
.first_fixup
= ip
->fixp
[0];
3015 else if (reloc_needs_lo_p (*reloc_type
))
3017 struct mips_hi_fixup
*hi_fixup
;
3019 /* Reuse the last entry if it already has a matching %lo. */
3020 hi_fixup
= mips_hi_fixup_list
;
3022 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3024 hi_fixup
= ((struct mips_hi_fixup
*)
3025 xmalloc (sizeof (struct mips_hi_fixup
)));
3026 hi_fixup
->next
= mips_hi_fixup_list
;
3027 mips_hi_fixup_list
= hi_fixup
;
3029 hi_fixup
->fixp
= ip
->fixp
[0];
3030 hi_fixup
->seg
= now_seg
;
3033 /* Add fixups for the second and third relocations, if given.
3034 Note that the ABI allows the second relocation to be
3035 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3036 moment we only use RSS_UNDEF, but we could add support
3037 for the others if it ever becomes necessary. */
3038 for (i
= 1; i
< 3; i
++)
3039 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3041 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3042 ip
->fixp
[0]->fx_size
, NULL
, 0,
3043 FALSE
, reloc_type
[i
]);
3045 /* Use fx_tcbit to mark compound relocs. */
3046 ip
->fixp
[0]->fx_tcbit
= 1;
3047 ip
->fixp
[i
]->fx_tcbit
= 1;
3053 /* Update the register mask information. */
3054 if (! mips_opts
.mips16
)
3056 if (pinfo
& INSN_WRITE_GPR_D
)
3057 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3058 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3059 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3060 if (pinfo
& INSN_READ_GPR_S
)
3061 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3062 if (pinfo
& INSN_WRITE_GPR_31
)
3063 mips_gprmask
|= 1 << RA
;
3064 if (pinfo
& INSN_WRITE_FPR_D
)
3065 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3066 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3067 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3068 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3069 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3070 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3071 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3072 if (pinfo
& INSN_COP
)
3074 /* We don't keep enough information to sort these cases out.
3075 The itbl support does keep this information however, although
3076 we currently don't support itbl fprmats as part of the cop
3077 instruction. May want to add this support in the future. */
3079 /* Never set the bit for $0, which is always zero. */
3080 mips_gprmask
&= ~1 << 0;
3084 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3085 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3086 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3087 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3088 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3089 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3090 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3091 mips_gprmask
|= 1 << TREG
;
3092 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3093 mips_gprmask
|= 1 << SP
;
3094 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3095 mips_gprmask
|= 1 << RA
;
3096 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3097 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3098 if (pinfo
& MIPS16_INSN_READ_Z
)
3099 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3100 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3101 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3104 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3106 /* Filling the branch delay slot is more complex. We try to
3107 switch the branch with the previous instruction, which we can
3108 do if the previous instruction does not set up a condition
3109 that the branch tests and if the branch is not itself the
3110 target of any branch. */
3111 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3112 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3114 if (mips_optimize
< 2
3115 /* If we have seen .set volatile or .set nomove, don't
3117 || mips_opts
.nomove
!= 0
3118 /* We can't swap if the previous instruction's position
3120 || history
[0].fixed_p
3121 /* If the previous previous insn was in a .set
3122 noreorder, we can't swap. Actually, the MIPS
3123 assembler will swap in this situation. However, gcc
3124 configured -with-gnu-as will generate code like
3130 in which we can not swap the bne and INSN. If gcc is
3131 not configured -with-gnu-as, it does not output the
3133 || history
[1].noreorder_p
3134 /* If the branch is itself the target of a branch, we
3135 can not swap. We cheat on this; all we check for is
3136 whether there is a label on this instruction. If
3137 there are any branches to anything other than a
3138 label, users must use .set noreorder. */
3139 || si
->label_list
!= NULL
3140 /* If the previous instruction is in a variant frag
3141 other than this branch's one, we cannot do the swap.
3142 This does not apply to the mips16, which uses variant
3143 frags for different purposes. */
3144 || (! mips_opts
.mips16
3145 && prev_insn_frag_type
== rs_machine_dependent
)
3146 /* Check for conflicts between the branch and the instructions
3147 before the candidate delay slot. */
3148 || nops_for_insn (history
+ 1, ip
) > 0
3149 /* Check for conflicts between the swapped sequence and the
3150 target of the branch. */
3151 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3152 /* We do not swap with a trap instruction, since it
3153 complicates trap handlers to have the trap
3154 instruction be in a delay slot. */
3155 || (prev_pinfo
& INSN_TRAP
)
3156 /* If the branch reads a register that the previous
3157 instruction sets, we can not swap. */
3158 || (! mips_opts
.mips16
3159 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3160 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3162 || (! mips_opts
.mips16
3163 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3164 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3166 || (mips_opts
.mips16
3167 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3169 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3171 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3173 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3175 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3177 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3179 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3180 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3181 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3182 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3183 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3184 && insn_uses_reg (ip
,
3185 MIPS16OP_EXTRACT_REG32R
3186 (history
[0].insn_opcode
),
3188 /* If the branch writes a register that the previous
3189 instruction sets, we can not swap (we know that
3190 branches write only to RD or to $31). */
3191 || (! mips_opts
.mips16
3192 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3193 && (((pinfo
& INSN_WRITE_GPR_D
)
3194 && (EXTRACT_OPERAND (RT
, history
[0])
3195 == EXTRACT_OPERAND (RD
, *ip
)))
3196 || ((pinfo
& INSN_WRITE_GPR_31
)
3197 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3198 || (! mips_opts
.mips16
3199 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3200 && (((pinfo
& INSN_WRITE_GPR_D
)
3201 && (EXTRACT_OPERAND (RD
, history
[0])
3202 == EXTRACT_OPERAND (RD
, *ip
)))
3203 || ((pinfo
& INSN_WRITE_GPR_31
)
3204 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3205 || (mips_opts
.mips16
3206 && (pinfo
& MIPS16_INSN_WRITE_31
)
3207 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3208 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3209 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3211 /* If the branch writes a register that the previous
3212 instruction reads, we can not swap (we know that
3213 branches only write to RD or to $31). */
3214 || (! mips_opts
.mips16
3215 && (pinfo
& INSN_WRITE_GPR_D
)
3216 && insn_uses_reg (&history
[0],
3217 EXTRACT_OPERAND (RD
, *ip
),
3219 || (! mips_opts
.mips16
3220 && (pinfo
& INSN_WRITE_GPR_31
)
3221 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3222 || (mips_opts
.mips16
3223 && (pinfo
& MIPS16_INSN_WRITE_31
)
3224 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3225 /* If one instruction sets a condition code and the
3226 other one uses a condition code, we can not swap. */
3227 || ((pinfo
& INSN_READ_COND_CODE
)
3228 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3229 || ((pinfo
& INSN_WRITE_COND_CODE
)
3230 && (prev_pinfo
& INSN_READ_COND_CODE
))
3231 /* If the previous instruction uses the PC, we can not
3233 || (mips_opts
.mips16
3234 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3235 /* If the previous instruction had a fixup in mips16
3236 mode, we can not swap. This normally means that the
3237 previous instruction was a 4 byte branch anyhow. */
3238 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3239 /* If the previous instruction is a sync, sync.l, or
3240 sync.p, we can not swap. */
3241 || (prev_pinfo
& INSN_SYNC
))
3243 if (mips_opts
.mips16
3244 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3245 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3246 && ISA_SUPPORTS_MIPS16E
)
3248 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3249 ip
->insn_opcode
|= 0x0080;
3251 insert_into_history (0, 1, ip
);
3255 /* We could do even better for unconditional branches to
3256 portions of this object file; we could pick up the
3257 instruction at the destination, put it in the delay
3258 slot, and bump the destination address. */
3259 insert_into_history (0, 1, ip
);
3263 if (mips_relax
.sequence
)
3264 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3268 /* It looks like we can actually do the swap. */
3269 struct mips_cl_insn delay
= history
[0];
3270 if (mips_opts
.mips16
)
3272 know (delay
.frag
== ip
->frag
);
3273 move_insn (ip
, delay
.frag
, delay
.where
);
3274 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3276 else if (relaxed_branch
)
3278 /* Add the delay slot instruction to the end of the
3279 current frag and shrink the fixed part of the
3280 original frag. If the branch occupies the tail of
3281 the latter, move it backwards to cover the gap. */
3282 delay
.frag
->fr_fix
-= 4;
3283 if (delay
.frag
== ip
->frag
)
3284 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3285 add_fixed_insn (&delay
);
3289 move_insn (&delay
, ip
->frag
, ip
->where
);
3290 move_insn (ip
, history
[0].frag
, history
[0].where
);
3294 insert_into_history (0, 1, &delay
);
3297 /* If that was an unconditional branch, forget the previous
3298 insn information. */
3299 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3300 mips_no_prev_insn ();
3302 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3304 /* We don't yet optimize a branch likely. What we should do
3305 is look at the target, copy the instruction found there
3306 into the delay slot, and increment the branch to jump to
3307 the next instruction. */
3308 insert_into_history (0, 1, ip
);
3312 insert_into_history (0, 1, ip
);
3315 insert_into_history (0, 1, ip
);
3317 /* We just output an insn, so the next one doesn't have a label. */
3318 mips_clear_insn_labels ();
3321 /* Forget that there was any previous instruction or label. */
3324 mips_no_prev_insn (void)
3326 prev_nop_frag
= NULL
;
3327 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3328 mips_clear_insn_labels ();
3331 /* This function must be called before we emit something other than
3332 instructions. It is like mips_no_prev_insn except that it inserts
3333 any NOPS that might be needed by previous instructions. */
3336 mips_emit_delays (void)
3338 if (! mips_opts
.noreorder
)
3340 int nops
= nops_for_insn (history
, NULL
);
3344 add_fixed_insn (NOP_INSN
);
3345 mips_move_labels ();
3348 mips_no_prev_insn ();
3351 /* Start a (possibly nested) noreorder block. */
3354 start_noreorder (void)
3356 if (mips_opts
.noreorder
== 0)
3361 /* None of the instructions before the .set noreorder can be moved. */
3362 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3363 history
[i
].fixed_p
= 1;
3365 /* Insert any nops that might be needed between the .set noreorder
3366 block and the previous instructions. We will later remove any
3367 nops that turn out not to be needed. */
3368 nops
= nops_for_insn (history
, NULL
);
3371 if (mips_optimize
!= 0)
3373 /* Record the frag which holds the nop instructions, so
3374 that we can remove them if we don't need them. */
3375 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3376 prev_nop_frag
= frag_now
;
3377 prev_nop_frag_holds
= nops
;
3378 prev_nop_frag_required
= 0;
3379 prev_nop_frag_since
= 0;
3382 for (; nops
> 0; --nops
)
3383 add_fixed_insn (NOP_INSN
);
3385 /* Move on to a new frag, so that it is safe to simply
3386 decrease the size of prev_nop_frag. */
3387 frag_wane (frag_now
);
3389 mips_move_labels ();
3391 mips16_mark_labels ();
3392 mips_clear_insn_labels ();
3394 mips_opts
.noreorder
++;
3395 mips_any_noreorder
= 1;
3398 /* End a nested noreorder block. */
3401 end_noreorder (void)
3403 mips_opts
.noreorder
--;
3404 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3406 /* Commit to inserting prev_nop_frag_required nops and go back to
3407 handling nop insertion the .set reorder way. */
3408 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3409 * (mips_opts
.mips16
? 2 : 4));
3410 insert_into_history (prev_nop_frag_since
,
3411 prev_nop_frag_required
, NOP_INSN
);
3412 prev_nop_frag
= NULL
;
3416 /* Set up global variables for the start of a new macro. */
3421 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3422 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3423 && (history
[0].insn_mo
->pinfo
3424 & (INSN_UNCOND_BRANCH_DELAY
3425 | INSN_COND_BRANCH_DELAY
3426 | INSN_COND_BRANCH_LIKELY
)) != 0);
3429 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3430 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3431 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3434 macro_warning (relax_substateT subtype
)
3436 if (subtype
& RELAX_DELAY_SLOT
)
3437 return _("Macro instruction expanded into multiple instructions"
3438 " in a branch delay slot");
3439 else if (subtype
& RELAX_NOMACRO
)
3440 return _("Macro instruction expanded into multiple instructions");
3445 /* Finish up a macro. Emit warnings as appropriate. */
3450 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3452 relax_substateT subtype
;
3454 /* Set up the relaxation warning flags. */
3456 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3457 subtype
|= RELAX_SECOND_LONGER
;
3458 if (mips_opts
.warn_about_macros
)
3459 subtype
|= RELAX_NOMACRO
;
3460 if (mips_macro_warning
.delay_slot_p
)
3461 subtype
|= RELAX_DELAY_SLOT
;
3463 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3465 /* Either the macro has a single implementation or both
3466 implementations are longer than 4 bytes. Emit the
3468 const char *msg
= macro_warning (subtype
);
3474 /* One implementation might need a warning but the other
3475 definitely doesn't. */
3476 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3481 /* Read a macro's relocation codes from *ARGS and store them in *R.
3482 The first argument in *ARGS will be either the code for a single
3483 relocation or -1 followed by the three codes that make up a
3484 composite relocation. */
3487 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3491 next
= va_arg (*args
, int);
3493 r
[0] = (bfd_reloc_code_real_type
) next
;
3495 for (i
= 0; i
< 3; i
++)
3496 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3499 /* Build an instruction created by a macro expansion. This is passed
3500 a pointer to the count of instructions created so far, an
3501 expression, the name of the instruction to build, an operand format
3502 string, and corresponding arguments. */
3505 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3507 const struct mips_opcode
*mo
;
3508 struct mips_cl_insn insn
;
3509 bfd_reloc_code_real_type r
[3];
3512 va_start (args
, fmt
);
3514 if (mips_opts
.mips16
)
3516 mips16_macro_build (ep
, name
, fmt
, args
);
3521 r
[0] = BFD_RELOC_UNUSED
;
3522 r
[1] = BFD_RELOC_UNUSED
;
3523 r
[2] = BFD_RELOC_UNUSED
;
3524 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3526 assert (strcmp (name
, mo
->name
) == 0);
3530 /* Search until we get a match for NAME. It is assumed here that
3531 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3532 if (strcmp (fmt
, mo
->args
) == 0
3533 && mo
->pinfo
!= INSN_MACRO
3534 && is_opcode_valid (mo
, TRUE
))
3539 assert (strcmp (name
, mo
->name
) == 0);
3542 create_insn (&insn
, mo
);
3560 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3565 /* Note that in the macro case, these arguments are already
3566 in MSB form. (When handling the instruction in the
3567 non-macro case, these arguments are sizes from which
3568 MSB values must be calculated.) */
3569 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3575 /* Note that in the macro case, these arguments are already
3576 in MSBD form. (When handling the instruction in the
3577 non-macro case, these arguments are sizes from which
3578 MSBD values must be calculated.) */
3579 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3583 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3592 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3598 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3602 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3607 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3613 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3618 int tmp
= va_arg (args
, int);
3620 INSERT_OPERAND (RT
, insn
, tmp
);
3621 INSERT_OPERAND (RD
, insn
, tmp
);
3627 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3634 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3638 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3642 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3646 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3650 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3657 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3663 macro_read_relocs (&args
, r
);
3664 assert (*r
== BFD_RELOC_GPREL16
3665 || *r
== BFD_RELOC_MIPS_LITERAL
3666 || *r
== BFD_RELOC_MIPS_HIGHER
3667 || *r
== BFD_RELOC_HI16_S
3668 || *r
== BFD_RELOC_LO16
3669 || *r
== BFD_RELOC_MIPS_GOT16
3670 || *r
== BFD_RELOC_MIPS_CALL16
3671 || *r
== BFD_RELOC_MIPS_GOT_DISP
3672 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3673 || *r
== BFD_RELOC_MIPS_GOT_OFST
3674 || *r
== BFD_RELOC_MIPS_GOT_LO16
3675 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3679 macro_read_relocs (&args
, r
);
3681 && (ep
->X_op
== O_constant
3682 || (ep
->X_op
== O_symbol
3683 && (*r
== BFD_RELOC_MIPS_HIGHEST
3684 || *r
== BFD_RELOC_HI16_S
3685 || *r
== BFD_RELOC_HI16
3686 || *r
== BFD_RELOC_GPREL16
3687 || *r
== BFD_RELOC_MIPS_GOT_HI16
3688 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3692 assert (ep
!= NULL
);
3695 * This allows macro() to pass an immediate expression for
3696 * creating short branches without creating a symbol.
3698 * We don't allow branch relaxation for these branches, as
3699 * they should only appear in ".set nomacro" anyway.
3701 if (ep
->X_op
== O_constant
)
3703 if ((ep
->X_add_number
& 3) != 0)
3704 as_bad (_("branch to misaligned address (0x%lx)"),
3705 (unsigned long) ep
->X_add_number
);
3706 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3707 as_bad (_("branch address range overflow (0x%lx)"),
3708 (unsigned long) ep
->X_add_number
);
3709 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3713 *r
= BFD_RELOC_16_PCREL_S2
;
3717 assert (ep
!= NULL
);
3718 *r
= BFD_RELOC_MIPS_JMP
;
3722 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3726 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3735 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3737 append_insn (&insn
, ep
, r
);
3741 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3744 struct mips_opcode
*mo
;
3745 struct mips_cl_insn insn
;
3746 bfd_reloc_code_real_type r
[3]
3747 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3749 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3751 assert (strcmp (name
, mo
->name
) == 0);
3753 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3757 assert (strcmp (name
, mo
->name
) == 0);
3760 create_insn (&insn
, mo
);
3778 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3783 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3787 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3791 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3801 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3808 regno
= va_arg (args
, int);
3809 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3810 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3831 assert (ep
!= NULL
);
3833 if (ep
->X_op
!= O_constant
)
3834 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3837 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3838 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3841 *r
= BFD_RELOC_UNUSED
;
3847 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3854 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3856 append_insn (&insn
, ep
, r
);
3860 * Sign-extend 32-bit mode constants that have bit 31 set and all
3861 * higher bits unset.
3864 normalize_constant_expr (expressionS
*ex
)
3866 if (ex
->X_op
== O_constant
3867 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3868 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3873 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3874 * all higher bits unset.
3877 normalize_address_expr (expressionS
*ex
)
3879 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3880 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3881 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3882 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3887 * Generate a "jalr" instruction with a relocation hint to the called
3888 * function. This occurs in NewABI PIC code.
3891 macro_build_jalr (expressionS
*ep
)
3900 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3902 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3903 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3907 * Generate a "lui" instruction.
3910 macro_build_lui (expressionS
*ep
, int regnum
)
3912 expressionS high_expr
;
3913 const struct mips_opcode
*mo
;
3914 struct mips_cl_insn insn
;
3915 bfd_reloc_code_real_type r
[3]
3916 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3917 const char *name
= "lui";
3918 const char *fmt
= "t,u";
3920 assert (! mips_opts
.mips16
);
3924 if (high_expr
.X_op
== O_constant
)
3926 /* We can compute the instruction now without a relocation entry. */
3927 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3929 *r
= BFD_RELOC_UNUSED
;
3933 assert (ep
->X_op
== O_symbol
);
3934 /* _gp_disp is a special case, used from s_cpload.
3935 __gnu_local_gp is used if mips_no_shared. */
3936 assert (mips_pic
== NO_PIC
3938 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3939 || (! mips_in_shared
3940 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3941 "__gnu_local_gp") == 0));
3942 *r
= BFD_RELOC_HI16_S
;
3945 mo
= hash_find (op_hash
, name
);
3946 assert (strcmp (name
, mo
->name
) == 0);
3947 assert (strcmp (fmt
, mo
->args
) == 0);
3948 create_insn (&insn
, mo
);
3950 insn
.insn_opcode
= insn
.insn_mo
->match
;
3951 INSERT_OPERAND (RT
, insn
, regnum
);
3952 if (*r
== BFD_RELOC_UNUSED
)
3954 insn
.insn_opcode
|= high_expr
.X_add_number
;
3955 append_insn (&insn
, NULL
, r
);
3958 append_insn (&insn
, &high_expr
, r
);
3961 /* Generate a sequence of instructions to do a load or store from a constant
3962 offset off of a base register (breg) into/from a target register (treg),
3963 using AT if necessary. */
3965 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3966 int treg
, int breg
, int dbl
)
3968 assert (ep
->X_op
== O_constant
);
3970 /* Sign-extending 32-bit constants makes their handling easier. */
3972 normalize_constant_expr (ep
);
3974 /* Right now, this routine can only handle signed 32-bit constants. */
3975 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3976 as_warn (_("operand overflow"));
3978 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3980 /* Signed 16-bit offset will fit in the op. Easy! */
3981 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3985 /* 32-bit offset, need multiple instructions and AT, like:
3986 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3987 addu $tempreg,$tempreg,$breg
3988 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3989 to handle the complete offset. */
3990 macro_build_lui (ep
, AT
);
3991 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3992 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3995 as_bad (_("Macro used $at after \".set noat\""));
4000 * Generates code to set the $at register to true (one)
4001 * if reg is less than the immediate expression.
4004 set_at (int reg
, int unsignedp
)
4006 if (imm_expr
.X_op
== O_constant
4007 && imm_expr
.X_add_number
>= -0x8000
4008 && imm_expr
.X_add_number
< 0x8000)
4009 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4010 AT
, reg
, BFD_RELOC_LO16
);
4013 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4014 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4018 /* Warn if an expression is not a constant. */
4021 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4023 if (ex
->X_op
== O_big
)
4024 as_bad (_("unsupported large constant"));
4025 else if (ex
->X_op
!= O_constant
)
4026 as_bad (_("Instruction %s requires absolute expression"),
4029 if (HAVE_32BIT_GPRS
)
4030 normalize_constant_expr (ex
);
4033 /* Count the leading zeroes by performing a binary chop. This is a
4034 bulky bit of source, but performance is a LOT better for the
4035 majority of values than a simple loop to count the bits:
4036 for (lcnt = 0; (lcnt < 32); lcnt++)
4037 if ((v) & (1 << (31 - lcnt)))
4039 However it is not code size friendly, and the gain will drop a bit
4040 on certain cached systems.
4042 #define COUNT_TOP_ZEROES(v) \
4043 (((v) & ~0xffff) == 0 \
4044 ? ((v) & ~0xff) == 0 \
4045 ? ((v) & ~0xf) == 0 \
4046 ? ((v) & ~0x3) == 0 \
4047 ? ((v) & ~0x1) == 0 \
4052 : ((v) & ~0x7) == 0 \
4055 : ((v) & ~0x3f) == 0 \
4056 ? ((v) & ~0x1f) == 0 \
4059 : ((v) & ~0x7f) == 0 \
4062 : ((v) & ~0xfff) == 0 \
4063 ? ((v) & ~0x3ff) == 0 \
4064 ? ((v) & ~0x1ff) == 0 \
4067 : ((v) & ~0x7ff) == 0 \
4070 : ((v) & ~0x3fff) == 0 \
4071 ? ((v) & ~0x1fff) == 0 \
4074 : ((v) & ~0x7fff) == 0 \
4077 : ((v) & ~0xffffff) == 0 \
4078 ? ((v) & ~0xfffff) == 0 \
4079 ? ((v) & ~0x3ffff) == 0 \
4080 ? ((v) & ~0x1ffff) == 0 \
4083 : ((v) & ~0x7ffff) == 0 \
4086 : ((v) & ~0x3fffff) == 0 \
4087 ? ((v) & ~0x1fffff) == 0 \
4090 : ((v) & ~0x7fffff) == 0 \
4093 : ((v) & ~0xfffffff) == 0 \
4094 ? ((v) & ~0x3ffffff) == 0 \
4095 ? ((v) & ~0x1ffffff) == 0 \
4098 : ((v) & ~0x7ffffff) == 0 \
4101 : ((v) & ~0x3fffffff) == 0 \
4102 ? ((v) & ~0x1fffffff) == 0 \
4105 : ((v) & ~0x7fffffff) == 0 \
4110 * This routine generates the least number of instructions necessary to load
4111 * an absolute expression value into a register.
4114 load_register (int reg
, expressionS
*ep
, int dbl
)
4117 expressionS hi32
, lo32
;
4119 if (ep
->X_op
!= O_big
)
4121 assert (ep
->X_op
== O_constant
);
4123 /* Sign-extending 32-bit constants makes their handling easier. */
4125 normalize_constant_expr (ep
);
4127 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4129 /* We can handle 16 bit signed values with an addiu to
4130 $zero. No need to ever use daddiu here, since $zero and
4131 the result are always correct in 32 bit mode. */
4132 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4135 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4137 /* We can handle 16 bit unsigned values with an ori to
4139 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4142 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4144 /* 32 bit values require an lui. */
4145 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4146 if ((ep
->X_add_number
& 0xffff) != 0)
4147 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4152 /* The value is larger than 32 bits. */
4154 if (!dbl
|| HAVE_32BIT_GPRS
)
4158 sprintf_vma (value
, ep
->X_add_number
);
4159 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4160 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4164 if (ep
->X_op
!= O_big
)
4167 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4168 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4169 hi32
.X_add_number
&= 0xffffffff;
4171 lo32
.X_add_number
&= 0xffffffff;
4175 assert (ep
->X_add_number
> 2);
4176 if (ep
->X_add_number
== 3)
4177 generic_bignum
[3] = 0;
4178 else if (ep
->X_add_number
> 4)
4179 as_bad (_("Number larger than 64 bits"));
4180 lo32
.X_op
= O_constant
;
4181 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4182 hi32
.X_op
= O_constant
;
4183 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4186 if (hi32
.X_add_number
== 0)
4191 unsigned long hi
, lo
;
4193 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4195 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4197 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4200 if (lo32
.X_add_number
& 0x80000000)
4202 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4203 if (lo32
.X_add_number
& 0xffff)
4204 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4209 /* Check for 16bit shifted constant. We know that hi32 is
4210 non-zero, so start the mask on the first bit of the hi32
4215 unsigned long himask
, lomask
;
4219 himask
= 0xffff >> (32 - shift
);
4220 lomask
= (0xffff << shift
) & 0xffffffff;
4224 himask
= 0xffff << (shift
- 32);
4227 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4228 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4232 tmp
.X_op
= O_constant
;
4234 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4235 | (lo32
.X_add_number
>> shift
));
4237 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4238 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4239 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4240 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4245 while (shift
<= (64 - 16));
4247 /* Find the bit number of the lowest one bit, and store the
4248 shifted value in hi/lo. */
4249 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4250 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4254 while ((lo
& 1) == 0)
4259 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4265 while ((hi
& 1) == 0)
4274 /* Optimize if the shifted value is a (power of 2) - 1. */
4275 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4276 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4278 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4283 /* This instruction will set the register to be all
4285 tmp
.X_op
= O_constant
;
4286 tmp
.X_add_number
= (offsetT
) -1;
4287 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4291 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4292 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4294 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4295 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4300 /* Sign extend hi32 before calling load_register, because we can
4301 generally get better code when we load a sign extended value. */
4302 if ((hi32
.X_add_number
& 0x80000000) != 0)
4303 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4304 load_register (reg
, &hi32
, 0);
4307 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4311 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4319 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4321 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4322 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4328 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4332 mid16
.X_add_number
>>= 16;
4333 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4334 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4337 if ((lo32
.X_add_number
& 0xffff) != 0)
4338 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4342 load_delay_nop (void)
4344 if (!gpr_interlocks
)
4345 macro_build (NULL
, "nop", "");
4348 /* Load an address into a register. */
4351 load_address (int reg
, expressionS
*ep
, int *used_at
)
4353 if (ep
->X_op
!= O_constant
4354 && ep
->X_op
!= O_symbol
)
4356 as_bad (_("expression too complex"));
4357 ep
->X_op
= O_constant
;
4360 if (ep
->X_op
== O_constant
)
4362 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4366 if (mips_pic
== NO_PIC
)
4368 /* If this is a reference to a GP relative symbol, we want
4369 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4371 lui $reg,<sym> (BFD_RELOC_HI16_S)
4372 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4373 If we have an addend, we always use the latter form.
4375 With 64bit address space and a usable $at we want
4376 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4377 lui $at,<sym> (BFD_RELOC_HI16_S)
4378 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4379 daddiu $at,<sym> (BFD_RELOC_LO16)
4383 If $at is already in use, we use a path which is suboptimal
4384 on superscalar processors.
4385 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4386 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4388 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4390 daddiu $reg,<sym> (BFD_RELOC_LO16)
4392 For GP relative symbols in 64bit address space we can use
4393 the same sequence as in 32bit address space. */
4394 if (HAVE_64BIT_SYMBOLS
)
4396 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4397 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4399 relax_start (ep
->X_add_symbol
);
4400 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4401 mips_gp_register
, BFD_RELOC_GPREL16
);
4405 if (*used_at
== 0 && mips_opts
.at
)
4407 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4408 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4409 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4410 BFD_RELOC_MIPS_HIGHER
);
4411 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4412 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4413 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4418 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4419 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4420 BFD_RELOC_MIPS_HIGHER
);
4421 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4422 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4423 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4424 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4427 if (mips_relax
.sequence
)
4432 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4433 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4435 relax_start (ep
->X_add_symbol
);
4436 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4437 mips_gp_register
, BFD_RELOC_GPREL16
);
4440 macro_build_lui (ep
, reg
);
4441 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4442 reg
, reg
, BFD_RELOC_LO16
);
4443 if (mips_relax
.sequence
)
4447 else if (!mips_big_got
)
4451 /* If this is a reference to an external symbol, we want
4452 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4454 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4456 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4457 If there is a constant, it must be added in after.
4459 If we have NewABI, we want
4460 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4461 unless we're referencing a global symbol with a non-zero
4462 offset, in which case cst must be added separately. */
4465 if (ep
->X_add_number
)
4467 ex
.X_add_number
= ep
->X_add_number
;
4468 ep
->X_add_number
= 0;
4469 relax_start (ep
->X_add_symbol
);
4470 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4471 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4472 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4473 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4474 ex
.X_op
= O_constant
;
4475 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4476 reg
, reg
, BFD_RELOC_LO16
);
4477 ep
->X_add_number
= ex
.X_add_number
;
4480 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4481 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4482 if (mips_relax
.sequence
)
4487 ex
.X_add_number
= ep
->X_add_number
;
4488 ep
->X_add_number
= 0;
4489 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4490 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4492 relax_start (ep
->X_add_symbol
);
4494 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4498 if (ex
.X_add_number
!= 0)
4500 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4501 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4502 ex
.X_op
= O_constant
;
4503 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4504 reg
, reg
, BFD_RELOC_LO16
);
4508 else if (mips_big_got
)
4512 /* This is the large GOT case. If this is a reference to an
4513 external symbol, we want
4514 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4516 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4518 Otherwise, for a reference to a local symbol in old ABI, we want
4519 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4521 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4522 If there is a constant, it must be added in after.
4524 In the NewABI, for local symbols, with or without offsets, we want:
4525 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4526 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4530 ex
.X_add_number
= ep
->X_add_number
;
4531 ep
->X_add_number
= 0;
4532 relax_start (ep
->X_add_symbol
);
4533 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4534 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4535 reg
, reg
, mips_gp_register
);
4536 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4537 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4538 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4539 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4540 else if (ex
.X_add_number
)
4542 ex
.X_op
= O_constant
;
4543 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4547 ep
->X_add_number
= ex
.X_add_number
;
4549 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4550 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4551 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4552 BFD_RELOC_MIPS_GOT_OFST
);
4557 ex
.X_add_number
= ep
->X_add_number
;
4558 ep
->X_add_number
= 0;
4559 relax_start (ep
->X_add_symbol
);
4560 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4562 reg
, reg
, mips_gp_register
);
4563 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4564 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4566 if (reg_needs_delay (mips_gp_register
))
4568 /* We need a nop before loading from $gp. This special
4569 check is required because the lui which starts the main
4570 instruction stream does not refer to $gp, and so will not
4571 insert the nop which may be required. */
4572 macro_build (NULL
, "nop", "");
4574 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4575 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4577 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4581 if (ex
.X_add_number
!= 0)
4583 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4584 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4585 ex
.X_op
= O_constant
;
4586 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4594 if (!mips_opts
.at
&& *used_at
== 1)
4595 as_bad (_("Macro used $at after \".set noat\""));
4598 /* Move the contents of register SOURCE into register DEST. */
4601 move_register (int dest
, int source
)
4603 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4607 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4608 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4609 The two alternatives are:
4611 Global symbol Local sybmol
4612 ------------- ------------
4613 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4615 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4617 load_got_offset emits the first instruction and add_got_offset
4618 emits the second for a 16-bit offset or add_got_offset_hilo emits
4619 a sequence to add a 32-bit offset using a scratch register. */
4622 load_got_offset (int dest
, expressionS
*local
)
4627 global
.X_add_number
= 0;
4629 relax_start (local
->X_add_symbol
);
4630 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4631 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4633 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4634 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4639 add_got_offset (int dest
, expressionS
*local
)
4643 global
.X_op
= O_constant
;
4644 global
.X_op_symbol
= NULL
;
4645 global
.X_add_symbol
= NULL
;
4646 global
.X_add_number
= local
->X_add_number
;
4648 relax_start (local
->X_add_symbol
);
4649 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4650 dest
, dest
, BFD_RELOC_LO16
);
4652 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4657 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4660 int hold_mips_optimize
;
4662 global
.X_op
= O_constant
;
4663 global
.X_op_symbol
= NULL
;
4664 global
.X_add_symbol
= NULL
;
4665 global
.X_add_number
= local
->X_add_number
;
4667 relax_start (local
->X_add_symbol
);
4668 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4670 /* Set mips_optimize around the lui instruction to avoid
4671 inserting an unnecessary nop after the lw. */
4672 hold_mips_optimize
= mips_optimize
;
4674 macro_build_lui (&global
, tmp
);
4675 mips_optimize
= hold_mips_optimize
;
4676 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4679 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4684 * This routine implements the seemingly endless macro or synthesized
4685 * instructions and addressing modes in the mips assembly language. Many
4686 * of these macros are simple and are similar to each other. These could
4687 * probably be handled by some kind of table or grammar approach instead of
4688 * this verbose method. Others are not simple macros but are more like
4689 * optimizing code generation.
4690 * One interesting optimization is when several store macros appear
4691 * consecutively that would load AT with the upper half of the same address.
4692 * The ensuing load upper instructions are ommited. This implies some kind
4693 * of global optimization. We currently only optimize within a single macro.
4694 * For many of the load and store macros if the address is specified as a
4695 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4696 * first load register 'at' with zero and use it as the base register. The
4697 * mips assembler simply uses register $zero. Just one tiny optimization
4701 macro (struct mips_cl_insn
*ip
)
4703 unsigned int treg
, sreg
, dreg
, breg
;
4704 unsigned int tempreg
;
4719 bfd_reloc_code_real_type r
;
4720 int hold_mips_optimize
;
4722 assert (! mips_opts
.mips16
);
4724 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4725 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4726 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4727 mask
= ip
->insn_mo
->mask
;
4729 expr1
.X_op
= O_constant
;
4730 expr1
.X_op_symbol
= NULL
;
4731 expr1
.X_add_symbol
= NULL
;
4732 expr1
.X_add_number
= 1;
4746 expr1
.X_add_number
= 8;
4747 macro_build (&expr1
, "bgez", "s,p", sreg
);
4749 macro_build (NULL
, "nop", "", 0);
4751 move_register (dreg
, sreg
);
4752 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4775 if (imm_expr
.X_op
== O_constant
4776 && imm_expr
.X_add_number
>= -0x8000
4777 && imm_expr
.X_add_number
< 0x8000)
4779 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4783 load_register (AT
, &imm_expr
, dbl
);
4784 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4803 if (imm_expr
.X_op
== O_constant
4804 && imm_expr
.X_add_number
>= 0
4805 && imm_expr
.X_add_number
< 0x10000)
4807 if (mask
!= M_NOR_I
)
4808 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4811 macro_build (&imm_expr
, "ori", "t,r,i",
4812 treg
, sreg
, BFD_RELOC_LO16
);
4813 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4819 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4820 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4824 switch (imm_expr
.X_add_number
)
4827 macro_build (NULL
, "nop", "");
4830 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4833 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4834 (int)imm_expr
.X_add_number
);
4853 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4855 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4859 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4860 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4868 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4873 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4877 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4878 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4884 /* check for > max integer */
4885 maxnum
= 0x7fffffff;
4886 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4893 if (imm_expr
.X_op
== O_constant
4894 && imm_expr
.X_add_number
>= maxnum
4895 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4898 /* result is always false */
4900 macro_build (NULL
, "nop", "", 0);
4902 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4905 if (imm_expr
.X_op
!= O_constant
)
4906 as_bad (_("Unsupported large constant"));
4907 ++imm_expr
.X_add_number
;
4911 if (mask
== M_BGEL_I
)
4913 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4915 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4918 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4920 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4923 maxnum
= 0x7fffffff;
4924 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4931 maxnum
= - maxnum
- 1;
4932 if (imm_expr
.X_op
== O_constant
4933 && imm_expr
.X_add_number
<= maxnum
4934 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4937 /* result is always true */
4938 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4939 macro_build (&offset_expr
, "b", "p");
4944 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4954 macro_build (&offset_expr
, likely
? "beql" : "beq",
4959 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4960 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4968 && imm_expr
.X_op
== O_constant
4969 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4971 if (imm_expr
.X_op
!= O_constant
)
4972 as_bad (_("Unsupported large constant"));
4973 ++imm_expr
.X_add_number
;
4977 if (mask
== M_BGEUL_I
)
4979 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4981 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4983 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4989 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4997 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5002 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5006 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5007 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5015 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5022 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5023 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5031 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5036 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5040 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5041 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5047 maxnum
= 0x7fffffff;
5048 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5055 if (imm_expr
.X_op
== O_constant
5056 && imm_expr
.X_add_number
>= maxnum
5057 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5059 if (imm_expr
.X_op
!= O_constant
)
5060 as_bad (_("Unsupported large constant"));
5061 ++imm_expr
.X_add_number
;
5065 if (mask
== M_BLTL_I
)
5067 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5069 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5072 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5074 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5079 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5087 macro_build (&offset_expr
, likely
? "beql" : "beq",
5094 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5095 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5103 && imm_expr
.X_op
== O_constant
5104 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5106 if (imm_expr
.X_op
!= O_constant
)
5107 as_bad (_("Unsupported large constant"));
5108 ++imm_expr
.X_add_number
;
5112 if (mask
== M_BLTUL_I
)
5114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5116 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5118 macro_build (&offset_expr
, likely
? "beql" : "beq",
5124 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5132 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5137 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5141 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5142 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5152 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5157 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5158 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5166 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5168 as_bad (_("Unsupported large constant"));
5173 pos
= (unsigned long) imm_expr
.X_add_number
;
5174 size
= (unsigned long) imm2_expr
.X_add_number
;
5179 as_bad (_("Improper position (%lu)"), pos
);
5182 if (size
== 0 || size
> 64
5183 || (pos
+ size
- 1) > 63)
5185 as_bad (_("Improper extract size (%lu, position %lu)"),
5190 if (size
<= 32 && pos
< 32)
5195 else if (size
<= 32)
5205 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5214 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5216 as_bad (_("Unsupported large constant"));
5221 pos
= (unsigned long) imm_expr
.X_add_number
;
5222 size
= (unsigned long) imm2_expr
.X_add_number
;
5227 as_bad (_("Improper position (%lu)"), pos
);
5230 if (size
== 0 || size
> 64
5231 || (pos
+ size
- 1) > 63)
5233 as_bad (_("Improper insert size (%lu, position %lu)"),
5238 if (pos
< 32 && (pos
+ size
- 1) < 32)
5253 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5254 (int) (pos
+ size
- 1));
5270 as_warn (_("Divide by zero."));
5272 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5274 macro_build (NULL
, "break", "c", 7);
5281 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5282 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5286 expr1
.X_add_number
= 8;
5287 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5288 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5289 macro_build (NULL
, "break", "c", 7);
5291 expr1
.X_add_number
= -1;
5293 load_register (AT
, &expr1
, dbl
);
5294 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5295 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5298 expr1
.X_add_number
= 1;
5299 load_register (AT
, &expr1
, dbl
);
5300 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5304 expr1
.X_add_number
= 0x80000000;
5305 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5309 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5310 /* We want to close the noreorder block as soon as possible, so
5311 that later insns are available for delay slot filling. */
5316 expr1
.X_add_number
= 8;
5317 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5318 macro_build (NULL
, "nop", "", 0);
5320 /* We want to close the noreorder block as soon as possible, so
5321 that later insns are available for delay slot filling. */
5324 macro_build (NULL
, "break", "c", 6);
5326 macro_build (NULL
, s
, "d", dreg
);
5365 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5367 as_warn (_("Divide by zero."));
5369 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5371 macro_build (NULL
, "break", "c", 7);
5374 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5376 if (strcmp (s2
, "mflo") == 0)
5377 move_register (dreg
, sreg
);
5379 move_register (dreg
, 0);
5382 if (imm_expr
.X_op
== O_constant
5383 && imm_expr
.X_add_number
== -1
5384 && s
[strlen (s
) - 1] != 'u')
5386 if (strcmp (s2
, "mflo") == 0)
5388 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5391 move_register (dreg
, 0);
5396 load_register (AT
, &imm_expr
, dbl
);
5397 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5398 macro_build (NULL
, s2
, "d", dreg
);
5420 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5421 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5422 /* We want to close the noreorder block as soon as possible, so
5423 that later insns are available for delay slot filling. */
5428 expr1
.X_add_number
= 8;
5429 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5430 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5432 /* We want to close the noreorder block as soon as possible, so
5433 that later insns are available for delay slot filling. */
5435 macro_build (NULL
, "break", "c", 7);
5437 macro_build (NULL
, s2
, "d", dreg
);
5449 /* Load the address of a symbol into a register. If breg is not
5450 zero, we then add a base register to it. */
5452 if (dbl
&& HAVE_32BIT_GPRS
)
5453 as_warn (_("dla used to load 32-bit register"));
5455 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5456 as_warn (_("la used to load 64-bit address"));
5458 if (offset_expr
.X_op
== O_constant
5459 && offset_expr
.X_add_number
>= -0x8000
5460 && offset_expr
.X_add_number
< 0x8000)
5462 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5463 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5467 if (mips_opts
.at
&& (treg
== breg
))
5477 if (offset_expr
.X_op
!= O_symbol
5478 && offset_expr
.X_op
!= O_constant
)
5480 as_bad (_("expression too complex"));
5481 offset_expr
.X_op
= O_constant
;
5484 if (offset_expr
.X_op
== O_constant
)
5485 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5486 else if (mips_pic
== NO_PIC
)
5488 /* If this is a reference to a GP relative symbol, we want
5489 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5491 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5492 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5493 If we have a constant, we need two instructions anyhow,
5494 so we may as well always use the latter form.
5496 With 64bit address space and a usable $at we want
5497 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5498 lui $at,<sym> (BFD_RELOC_HI16_S)
5499 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5500 daddiu $at,<sym> (BFD_RELOC_LO16)
5502 daddu $tempreg,$tempreg,$at
5504 If $at is already in use, we use a path which is suboptimal
5505 on superscalar processors.
5506 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5507 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5509 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5511 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5513 For GP relative symbols in 64bit address space we can use
5514 the same sequence as in 32bit address space. */
5515 if (HAVE_64BIT_SYMBOLS
)
5517 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5518 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5520 relax_start (offset_expr
.X_add_symbol
);
5521 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5522 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5526 if (used_at
== 0 && mips_opts
.at
)
5528 macro_build (&offset_expr
, "lui", "t,u",
5529 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5530 macro_build (&offset_expr
, "lui", "t,u",
5531 AT
, BFD_RELOC_HI16_S
);
5532 macro_build (&offset_expr
, "daddiu", "t,r,j",
5533 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5534 macro_build (&offset_expr
, "daddiu", "t,r,j",
5535 AT
, AT
, BFD_RELOC_LO16
);
5536 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5537 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5542 macro_build (&offset_expr
, "lui", "t,u",
5543 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5544 macro_build (&offset_expr
, "daddiu", "t,r,j",
5545 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5546 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5547 macro_build (&offset_expr
, "daddiu", "t,r,j",
5548 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5549 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5550 macro_build (&offset_expr
, "daddiu", "t,r,j",
5551 tempreg
, tempreg
, BFD_RELOC_LO16
);
5554 if (mips_relax
.sequence
)
5559 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5560 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5562 relax_start (offset_expr
.X_add_symbol
);
5563 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5564 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5567 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5568 as_bad (_("offset too large"));
5569 macro_build_lui (&offset_expr
, tempreg
);
5570 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5571 tempreg
, tempreg
, BFD_RELOC_LO16
);
5572 if (mips_relax
.sequence
)
5576 else if (!mips_big_got
&& !HAVE_NEWABI
)
5578 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5580 /* If this is a reference to an external symbol, and there
5581 is no constant, we want
5582 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5583 or for lca or if tempreg is PIC_CALL_REG
5584 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5585 For a local symbol, we want
5586 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5588 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5590 If we have a small constant, and this is a reference to
5591 an external symbol, we want
5592 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5594 addiu $tempreg,$tempreg,<constant>
5595 For a local symbol, we want the same instruction
5596 sequence, but we output a BFD_RELOC_LO16 reloc on the
5599 If we have a large constant, and this is a reference to
5600 an external symbol, we want
5601 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5602 lui $at,<hiconstant>
5603 addiu $at,$at,<loconstant>
5604 addu $tempreg,$tempreg,$at
5605 For a local symbol, we want the same instruction
5606 sequence, but we output a BFD_RELOC_LO16 reloc on the
5610 if (offset_expr
.X_add_number
== 0)
5612 if (mips_pic
== SVR4_PIC
5614 && (call
|| tempreg
== PIC_CALL_REG
))
5615 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5617 relax_start (offset_expr
.X_add_symbol
);
5618 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5619 lw_reloc_type
, mips_gp_register
);
5622 /* We're going to put in an addu instruction using
5623 tempreg, so we may as well insert the nop right
5628 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5629 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5631 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5632 tempreg
, tempreg
, BFD_RELOC_LO16
);
5634 /* FIXME: If breg == 0, and the next instruction uses
5635 $tempreg, then if this variant case is used an extra
5636 nop will be generated. */
5638 else if (offset_expr
.X_add_number
>= -0x8000
5639 && offset_expr
.X_add_number
< 0x8000)
5641 load_got_offset (tempreg
, &offset_expr
);
5643 add_got_offset (tempreg
, &offset_expr
);
5647 expr1
.X_add_number
= offset_expr
.X_add_number
;
5648 offset_expr
.X_add_number
=
5649 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5650 load_got_offset (tempreg
, &offset_expr
);
5651 offset_expr
.X_add_number
= expr1
.X_add_number
;
5652 /* If we are going to add in a base register, and the
5653 target register and the base register are the same,
5654 then we are using AT as a temporary register. Since
5655 we want to load the constant into AT, we add our
5656 current AT (from the global offset table) and the
5657 register into the register now, and pretend we were
5658 not using a base register. */
5662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5667 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5671 else if (!mips_big_got
&& HAVE_NEWABI
)
5673 int add_breg_early
= 0;
5675 /* If this is a reference to an external, and there is no
5676 constant, or local symbol (*), with or without a
5678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5679 or for lca or if tempreg is PIC_CALL_REG
5680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5682 If we have a small constant, and this is a reference to
5683 an external symbol, we want
5684 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5685 addiu $tempreg,$tempreg,<constant>
5687 If we have a large constant, and this is a reference to
5688 an external symbol, we want
5689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5690 lui $at,<hiconstant>
5691 addiu $at,$at,<loconstant>
5692 addu $tempreg,$tempreg,$at
5694 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5695 local symbols, even though it introduces an additional
5698 if (offset_expr
.X_add_number
)
5700 expr1
.X_add_number
= offset_expr
.X_add_number
;
5701 offset_expr
.X_add_number
= 0;
5703 relax_start (offset_expr
.X_add_symbol
);
5704 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5705 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5707 if (expr1
.X_add_number
>= -0x8000
5708 && expr1
.X_add_number
< 0x8000)
5710 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5711 tempreg
, tempreg
, BFD_RELOC_LO16
);
5713 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5717 /* If we are going to add in a base register, and the
5718 target register and the base register are the same,
5719 then we are using AT as a temporary register. Since
5720 we want to load the constant into AT, we add our
5721 current AT (from the global offset table) and the
5722 register into the register now, and pretend we were
5723 not using a base register. */
5728 assert (tempreg
== AT
);
5729 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5735 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5736 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5742 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5745 offset_expr
.X_add_number
= expr1
.X_add_number
;
5747 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5748 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5751 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5752 treg
, tempreg
, breg
);
5758 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5760 relax_start (offset_expr
.X_add_symbol
);
5761 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5762 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5764 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5765 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5770 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5771 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5774 else if (mips_big_got
&& !HAVE_NEWABI
)
5777 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5778 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5779 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5781 /* This is the large GOT case. If this is a reference to an
5782 external symbol, and there is no constant, we want
5783 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5784 addu $tempreg,$tempreg,$gp
5785 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5786 or for lca or if tempreg is PIC_CALL_REG
5787 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5788 addu $tempreg,$tempreg,$gp
5789 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5790 For a local symbol, we want
5791 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5793 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5795 If we have a small constant, and this is a reference to
5796 an external symbol, we want
5797 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5798 addu $tempreg,$tempreg,$gp
5799 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5801 addiu $tempreg,$tempreg,<constant>
5802 For a local symbol, we want
5803 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5805 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5807 If we have a large constant, and this is a reference to
5808 an external symbol, we want
5809 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5810 addu $tempreg,$tempreg,$gp
5811 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5812 lui $at,<hiconstant>
5813 addiu $at,$at,<loconstant>
5814 addu $tempreg,$tempreg,$at
5815 For a local symbol, we want
5816 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5817 lui $at,<hiconstant>
5818 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5819 addu $tempreg,$tempreg,$at
5822 expr1
.X_add_number
= offset_expr
.X_add_number
;
5823 offset_expr
.X_add_number
= 0;
5824 relax_start (offset_expr
.X_add_symbol
);
5825 gpdelay
= reg_needs_delay (mips_gp_register
);
5826 if (expr1
.X_add_number
== 0 && breg
== 0
5827 && (call
|| tempreg
== PIC_CALL_REG
))
5829 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5830 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5832 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5834 tempreg
, tempreg
, mips_gp_register
);
5835 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5836 tempreg
, lw_reloc_type
, tempreg
);
5837 if (expr1
.X_add_number
== 0)
5841 /* We're going to put in an addu instruction using
5842 tempreg, so we may as well insert the nop right
5847 else if (expr1
.X_add_number
>= -0x8000
5848 && expr1
.X_add_number
< 0x8000)
5851 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5852 tempreg
, tempreg
, BFD_RELOC_LO16
);
5858 /* If we are going to add in a base register, and the
5859 target register and the base register are the same,
5860 then we are using AT as a temporary register. Since
5861 we want to load the constant into AT, we add our
5862 current AT (from the global offset table) and the
5863 register into the register now, and pretend we were
5864 not using a base register. */
5869 assert (tempreg
== AT
);
5871 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5876 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5877 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5881 offset_expr
.X_add_number
=
5882 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5887 /* This is needed because this instruction uses $gp, but
5888 the first instruction on the main stream does not. */
5889 macro_build (NULL
, "nop", "");
5892 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5893 local_reloc_type
, mips_gp_register
);
5894 if (expr1
.X_add_number
>= -0x8000
5895 && expr1
.X_add_number
< 0x8000)
5898 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5899 tempreg
, tempreg
, BFD_RELOC_LO16
);
5900 /* FIXME: If add_number is 0, and there was no base
5901 register, the external symbol case ended with a load,
5902 so if the symbol turns out to not be external, and
5903 the next instruction uses tempreg, an unnecessary nop
5904 will be inserted. */
5910 /* We must add in the base register now, as in the
5911 external symbol case. */
5912 assert (tempreg
== AT
);
5914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5917 /* We set breg to 0 because we have arranged to add
5918 it in in both cases. */
5922 macro_build_lui (&expr1
, AT
);
5923 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5924 AT
, AT
, BFD_RELOC_LO16
);
5925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5926 tempreg
, tempreg
, AT
);
5931 else if (mips_big_got
&& HAVE_NEWABI
)
5933 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5934 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5935 int add_breg_early
= 0;
5937 /* This is the large GOT case. If this is a reference to an
5938 external symbol, and there is no constant, we want
5939 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5940 add $tempreg,$tempreg,$gp
5941 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5942 or for lca or if tempreg is PIC_CALL_REG
5943 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5944 add $tempreg,$tempreg,$gp
5945 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5947 If we have a small constant, and this is a reference to
5948 an external symbol, we want
5949 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5950 add $tempreg,$tempreg,$gp
5951 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5952 addi $tempreg,$tempreg,<constant>
5954 If we have a large constant, and this is a reference to
5955 an external symbol, we want
5956 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5957 addu $tempreg,$tempreg,$gp
5958 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5959 lui $at,<hiconstant>
5960 addi $at,$at,<loconstant>
5961 add $tempreg,$tempreg,$at
5963 If we have NewABI, and we know it's a local symbol, we want
5964 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5965 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5966 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5968 relax_start (offset_expr
.X_add_symbol
);
5970 expr1
.X_add_number
= offset_expr
.X_add_number
;
5971 offset_expr
.X_add_number
= 0;
5973 if (expr1
.X_add_number
== 0 && breg
== 0
5974 && (call
|| tempreg
== PIC_CALL_REG
))
5976 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5977 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5979 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5980 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5981 tempreg
, tempreg
, mips_gp_register
);
5982 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5983 tempreg
, lw_reloc_type
, tempreg
);
5985 if (expr1
.X_add_number
== 0)
5987 else if (expr1
.X_add_number
>= -0x8000
5988 && expr1
.X_add_number
< 0x8000)
5990 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5991 tempreg
, tempreg
, BFD_RELOC_LO16
);
5993 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5997 /* If we are going to add in a base register, and the
5998 target register and the base register are the same,
5999 then we are using AT as a temporary register. Since
6000 we want to load the constant into AT, we add our
6001 current AT (from the global offset table) and the
6002 register into the register now, and pretend we were
6003 not using a base register. */
6008 assert (tempreg
== AT
);
6009 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6015 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6021 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6024 offset_expr
.X_add_number
= expr1
.X_add_number
;
6025 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6026 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6027 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6028 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6032 treg
, tempreg
, breg
);
6042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6047 unsigned long temp
= (treg
<< 16) | (0x01);
6048 macro_build (NULL
, "c2", "C", temp
);
6050 /* AT is not used, just return */
6055 unsigned long temp
= (0x02);
6056 macro_build (NULL
, "c2", "C", temp
);
6058 /* AT is not used, just return */
6063 unsigned long temp
= (treg
<< 16) | (0x02);
6064 macro_build (NULL
, "c2", "C", temp
);
6066 /* AT is not used, just return */
6070 macro_build (NULL
, "c2", "C", 3);
6071 /* AT is not used, just return */
6076 unsigned long temp
= (treg
<< 16) | 0x03;
6077 macro_build (NULL
, "c2", "C", temp
);
6079 /* AT is not used, just return */
6083 /* The j instruction may not be used in PIC code, since it
6084 requires an absolute address. We convert it to a b
6086 if (mips_pic
== NO_PIC
)
6087 macro_build (&offset_expr
, "j", "a");
6089 macro_build (&offset_expr
, "b", "p");
6092 /* The jal instructions must be handled as macros because when
6093 generating PIC code they expand to multi-instruction
6094 sequences. Normally they are simple instructions. */
6099 if (mips_pic
== NO_PIC
)
6100 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6103 if (sreg
!= PIC_CALL_REG
)
6104 as_warn (_("MIPS PIC call to register other than $25"));
6106 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6107 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6109 if (mips_cprestore_offset
< 0)
6110 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6113 if (! mips_frame_reg_valid
)
6115 as_warn (_("No .frame pseudo-op used in PIC code"));
6116 /* Quiet this warning. */
6117 mips_frame_reg_valid
= 1;
6119 if (! mips_cprestore_valid
)
6121 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6122 /* Quiet this warning. */
6123 mips_cprestore_valid
= 1;
6125 expr1
.X_add_number
= mips_cprestore_offset
;
6126 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6129 HAVE_64BIT_ADDRESSES
);
6137 if (mips_pic
== NO_PIC
)
6138 macro_build (&offset_expr
, "jal", "a");
6139 else if (mips_pic
== SVR4_PIC
)
6141 /* If this is a reference to an external symbol, and we are
6142 using a small GOT, we want
6143 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6147 lw $gp,cprestore($sp)
6148 The cprestore value is set using the .cprestore
6149 pseudo-op. If we are using a big GOT, we want
6150 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6152 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6156 lw $gp,cprestore($sp)
6157 If the symbol is not external, we want
6158 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6160 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6163 lw $gp,cprestore($sp)
6165 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6166 sequences above, minus nops, unless the symbol is local,
6167 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6173 relax_start (offset_expr
.X_add_symbol
);
6174 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6175 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6178 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6179 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6185 relax_start (offset_expr
.X_add_symbol
);
6186 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6187 BFD_RELOC_MIPS_CALL_HI16
);
6188 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6189 PIC_CALL_REG
, mips_gp_register
);
6190 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6191 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6194 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6195 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6197 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6198 PIC_CALL_REG
, PIC_CALL_REG
,
6199 BFD_RELOC_MIPS_GOT_OFST
);
6203 macro_build_jalr (&offset_expr
);
6207 relax_start (offset_expr
.X_add_symbol
);
6210 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6211 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6220 gpdelay
= reg_needs_delay (mips_gp_register
);
6221 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6222 BFD_RELOC_MIPS_CALL_HI16
);
6223 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6224 PIC_CALL_REG
, mips_gp_register
);
6225 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6226 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6231 macro_build (NULL
, "nop", "");
6233 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6234 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6237 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6238 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6240 macro_build_jalr (&offset_expr
);
6242 if (mips_cprestore_offset
< 0)
6243 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6246 if (! mips_frame_reg_valid
)
6248 as_warn (_("No .frame pseudo-op used in PIC code"));
6249 /* Quiet this warning. */
6250 mips_frame_reg_valid
= 1;
6252 if (! mips_cprestore_valid
)
6254 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6255 /* Quiet this warning. */
6256 mips_cprestore_valid
= 1;
6258 if (mips_opts
.noreorder
)
6259 macro_build (NULL
, "nop", "");
6260 expr1
.X_add_number
= mips_cprestore_offset
;
6261 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6264 HAVE_64BIT_ADDRESSES
);
6268 else if (mips_pic
== VXWORKS_PIC
)
6269 as_bad (_("Non-PIC jump used in PIC library"));
6292 /* Itbl support may require additional care here. */
6297 /* Itbl support may require additional care here. */
6302 /* Itbl support may require additional care here. */
6307 /* Itbl support may require additional care here. */
6320 /* Itbl support may require additional care here. */
6325 /* Itbl support may require additional care here. */
6330 /* Itbl support may require additional care here. */
6350 if (breg
== treg
|| coproc
|| lr
)
6371 /* Itbl support may require additional care here. */
6376 /* Itbl support may require additional care here. */
6381 /* Itbl support may require additional care here. */
6386 /* Itbl support may require additional care here. */
6407 /* Itbl support may require additional care here. */
6411 /* Itbl support may require additional care here. */
6416 /* Itbl support may require additional care here. */
6429 && NO_ISA_COP (mips_opts
.arch
)
6430 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6432 as_bad (_("opcode not supported on this processor: %s"),
6433 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6437 /* Itbl support may require additional care here. */
6438 if (mask
== M_LWC1_AB
6439 || mask
== M_SWC1_AB
6440 || mask
== M_LDC1_AB
6441 || mask
== M_SDC1_AB
6445 else if (mask
== M_CACHE_AB
)
6452 if (offset_expr
.X_op
!= O_constant
6453 && offset_expr
.X_op
!= O_symbol
)
6455 as_bad (_("expression too complex"));
6456 offset_expr
.X_op
= O_constant
;
6459 if (HAVE_32BIT_ADDRESSES
6460 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6464 sprintf_vma (value
, offset_expr
.X_add_number
);
6465 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6468 /* A constant expression in PIC code can be handled just as it
6469 is in non PIC code. */
6470 if (offset_expr
.X_op
== O_constant
)
6472 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6473 & ~(bfd_vma
) 0xffff);
6474 normalize_address_expr (&expr1
);
6475 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6477 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6478 tempreg
, tempreg
, breg
);
6479 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6481 else if (mips_pic
== NO_PIC
)
6483 /* If this is a reference to a GP relative symbol, and there
6484 is no base register, we want
6485 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6486 Otherwise, if there is no base register, we want
6487 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6488 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6489 If we have a constant, we need two instructions anyhow,
6490 so we always use the latter form.
6492 If we have a base register, and this is a reference to a
6493 GP relative symbol, we want
6494 addu $tempreg,$breg,$gp
6495 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6497 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6498 addu $tempreg,$tempreg,$breg
6499 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6500 With a constant we always use the latter case.
6502 With 64bit address space and no base register and $at usable,
6504 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6505 lui $at,<sym> (BFD_RELOC_HI16_S)
6506 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6509 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6510 If we have a base register, we want
6511 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6512 lui $at,<sym> (BFD_RELOC_HI16_S)
6513 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6517 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6519 Without $at we can't generate the optimal path for superscalar
6520 processors here since this would require two temporary registers.
6521 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6522 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6524 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6526 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6527 If we have a base register, we want
6528 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6529 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6531 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6533 daddu $tempreg,$tempreg,$breg
6534 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6536 For GP relative symbols in 64bit address space we can use
6537 the same sequence as in 32bit address space. */
6538 if (HAVE_64BIT_SYMBOLS
)
6540 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6541 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6543 relax_start (offset_expr
.X_add_symbol
);
6546 macro_build (&offset_expr
, s
, fmt
, treg
,
6547 BFD_RELOC_GPREL16
, mips_gp_register
);
6551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6552 tempreg
, breg
, mips_gp_register
);
6553 macro_build (&offset_expr
, s
, fmt
, treg
,
6554 BFD_RELOC_GPREL16
, tempreg
);
6559 if (used_at
== 0 && mips_opts
.at
)
6561 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6562 BFD_RELOC_MIPS_HIGHEST
);
6563 macro_build (&offset_expr
, "lui", "t,u", AT
,
6565 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6566 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6568 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6569 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6570 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6571 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6577 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6578 BFD_RELOC_MIPS_HIGHEST
);
6579 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6580 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6581 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6582 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6583 tempreg
, BFD_RELOC_HI16_S
);
6584 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6586 macro_build (NULL
, "daddu", "d,v,t",
6587 tempreg
, tempreg
, breg
);
6588 macro_build (&offset_expr
, s
, fmt
, treg
,
6589 BFD_RELOC_LO16
, tempreg
);
6592 if (mips_relax
.sequence
)
6599 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6600 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6602 relax_start (offset_expr
.X_add_symbol
);
6603 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6607 macro_build_lui (&offset_expr
, tempreg
);
6608 macro_build (&offset_expr
, s
, fmt
, treg
,
6609 BFD_RELOC_LO16
, tempreg
);
6610 if (mips_relax
.sequence
)
6615 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6616 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6618 relax_start (offset_expr
.X_add_symbol
);
6619 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6620 tempreg
, breg
, mips_gp_register
);
6621 macro_build (&offset_expr
, s
, fmt
, treg
,
6622 BFD_RELOC_GPREL16
, tempreg
);
6625 macro_build_lui (&offset_expr
, tempreg
);
6626 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6627 tempreg
, tempreg
, breg
);
6628 macro_build (&offset_expr
, s
, fmt
, treg
,
6629 BFD_RELOC_LO16
, tempreg
);
6630 if (mips_relax
.sequence
)
6634 else if (!mips_big_got
)
6636 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6638 /* If this is a reference to an external symbol, we want
6639 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6641 <op> $treg,0($tempreg)
6643 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6645 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6646 <op> $treg,0($tempreg)
6649 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6650 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6652 If there is a base register, we add it to $tempreg before
6653 the <op>. If there is a constant, we stick it in the
6654 <op> instruction. We don't handle constants larger than
6655 16 bits, because we have no way to load the upper 16 bits
6656 (actually, we could handle them for the subset of cases
6657 in which we are not using $at). */
6658 assert (offset_expr
.X_op
== O_symbol
);
6661 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6662 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6664 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6665 tempreg
, tempreg
, breg
);
6666 macro_build (&offset_expr
, s
, fmt
, treg
,
6667 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6670 expr1
.X_add_number
= offset_expr
.X_add_number
;
6671 offset_expr
.X_add_number
= 0;
6672 if (expr1
.X_add_number
< -0x8000
6673 || expr1
.X_add_number
>= 0x8000)
6674 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6675 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6676 lw_reloc_type
, mips_gp_register
);
6678 relax_start (offset_expr
.X_add_symbol
);
6680 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6681 tempreg
, BFD_RELOC_LO16
);
6684 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6685 tempreg
, tempreg
, breg
);
6686 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6688 else if (mips_big_got
&& !HAVE_NEWABI
)
6692 /* If this is a reference to an external symbol, we want
6693 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6694 addu $tempreg,$tempreg,$gp
6695 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6696 <op> $treg,0($tempreg)
6698 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6700 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6701 <op> $treg,0($tempreg)
6702 If there is a base register, we add it to $tempreg before
6703 the <op>. If there is a constant, we stick it in the
6704 <op> instruction. We don't handle constants larger than
6705 16 bits, because we have no way to load the upper 16 bits
6706 (actually, we could handle them for the subset of cases
6707 in which we are not using $at). */
6708 assert (offset_expr
.X_op
== O_symbol
);
6709 expr1
.X_add_number
= offset_expr
.X_add_number
;
6710 offset_expr
.X_add_number
= 0;
6711 if (expr1
.X_add_number
< -0x8000
6712 || expr1
.X_add_number
>= 0x8000)
6713 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6714 gpdelay
= reg_needs_delay (mips_gp_register
);
6715 relax_start (offset_expr
.X_add_symbol
);
6716 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6717 BFD_RELOC_MIPS_GOT_HI16
);
6718 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6720 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6721 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6724 macro_build (NULL
, "nop", "");
6725 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6726 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6728 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6729 tempreg
, BFD_RELOC_LO16
);
6733 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6734 tempreg
, tempreg
, breg
);
6735 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6737 else if (mips_big_got
&& HAVE_NEWABI
)
6739 /* If this is a reference to an external symbol, we want
6740 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6741 add $tempreg,$tempreg,$gp
6742 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6743 <op> $treg,<ofst>($tempreg)
6744 Otherwise, for local symbols, we want:
6745 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6746 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6747 assert (offset_expr
.X_op
== O_symbol
);
6748 expr1
.X_add_number
= offset_expr
.X_add_number
;
6749 offset_expr
.X_add_number
= 0;
6750 if (expr1
.X_add_number
< -0x8000
6751 || expr1
.X_add_number
>= 0x8000)
6752 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6753 relax_start (offset_expr
.X_add_symbol
);
6754 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6755 BFD_RELOC_MIPS_GOT_HI16
);
6756 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6758 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6759 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6761 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6762 tempreg
, tempreg
, breg
);
6763 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6766 offset_expr
.X_add_number
= expr1
.X_add_number
;
6767 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6768 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6770 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6771 tempreg
, tempreg
, breg
);
6772 macro_build (&offset_expr
, s
, fmt
, treg
,
6773 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6783 load_register (treg
, &imm_expr
, 0);
6787 load_register (treg
, &imm_expr
, 1);
6791 if (imm_expr
.X_op
== O_constant
)
6794 load_register (AT
, &imm_expr
, 0);
6795 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6800 assert (offset_expr
.X_op
== O_symbol
6801 && strcmp (segment_name (S_GET_SEGMENT
6802 (offset_expr
.X_add_symbol
)),
6804 && offset_expr
.X_add_number
== 0);
6805 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6806 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6811 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6812 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6813 order 32 bits of the value and the low order 32 bits are either
6814 zero or in OFFSET_EXPR. */
6815 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6817 if (HAVE_64BIT_GPRS
)
6818 load_register (treg
, &imm_expr
, 1);
6823 if (target_big_endian
)
6835 load_register (hreg
, &imm_expr
, 0);
6838 if (offset_expr
.X_op
== O_absent
)
6839 move_register (lreg
, 0);
6842 assert (offset_expr
.X_op
== O_constant
);
6843 load_register (lreg
, &offset_expr
, 0);
6850 /* We know that sym is in the .rdata section. First we get the
6851 upper 16 bits of the address. */
6852 if (mips_pic
== NO_PIC
)
6854 macro_build_lui (&offset_expr
, AT
);
6859 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6860 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6864 /* Now we load the register(s). */
6865 if (HAVE_64BIT_GPRS
)
6868 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6873 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6876 /* FIXME: How in the world do we deal with the possible
6878 offset_expr
.X_add_number
+= 4;
6879 macro_build (&offset_expr
, "lw", "t,o(b)",
6880 treg
+ 1, BFD_RELOC_LO16
, AT
);
6886 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6887 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6888 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6889 the value and the low order 32 bits are either zero or in
6891 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6894 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6895 if (HAVE_64BIT_FPRS
)
6897 assert (HAVE_64BIT_GPRS
);
6898 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6902 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6903 if (offset_expr
.X_op
== O_absent
)
6904 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6907 assert (offset_expr
.X_op
== O_constant
);
6908 load_register (AT
, &offset_expr
, 0);
6909 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6915 assert (offset_expr
.X_op
== O_symbol
6916 && offset_expr
.X_add_number
== 0);
6917 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6918 if (strcmp (s
, ".lit8") == 0)
6920 if (mips_opts
.isa
!= ISA_MIPS1
)
6922 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6923 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6926 breg
= mips_gp_register
;
6927 r
= BFD_RELOC_MIPS_LITERAL
;
6932 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6934 if (mips_pic
!= NO_PIC
)
6935 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6936 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6939 /* FIXME: This won't work for a 64 bit address. */
6940 macro_build_lui (&offset_expr
, AT
);
6943 if (mips_opts
.isa
!= ISA_MIPS1
)
6945 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6946 treg
, BFD_RELOC_LO16
, AT
);
6955 /* Even on a big endian machine $fn comes before $fn+1. We have
6956 to adjust when loading from memory. */
6959 assert (mips_opts
.isa
== ISA_MIPS1
);
6960 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6961 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6962 /* FIXME: A possible overflow which I don't know how to deal
6964 offset_expr
.X_add_number
+= 4;
6965 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6966 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6971 * The MIPS assembler seems to check for X_add_number not
6972 * being double aligned and generating:
6975 * addiu at,at,%lo(foo+1)
6978 * But, the resulting address is the same after relocation so why
6979 * generate the extra instruction?
6981 /* Itbl support may require additional care here. */
6983 if (mips_opts
.isa
!= ISA_MIPS1
)
6994 if (mips_opts
.isa
!= ISA_MIPS1
)
7002 /* Itbl support may require additional care here. */
7007 if (HAVE_64BIT_GPRS
)
7018 if (HAVE_64BIT_GPRS
)
7028 if (offset_expr
.X_op
!= O_symbol
7029 && offset_expr
.X_op
!= O_constant
)
7031 as_bad (_("expression too complex"));
7032 offset_expr
.X_op
= O_constant
;
7035 if (HAVE_32BIT_ADDRESSES
7036 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7040 sprintf_vma (value
, offset_expr
.X_add_number
);
7041 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7044 /* Even on a big endian machine $fn comes before $fn+1. We have
7045 to adjust when loading from memory. We set coproc if we must
7046 load $fn+1 first. */
7047 /* Itbl support may require additional care here. */
7048 if (! target_big_endian
)
7051 if (mips_pic
== NO_PIC
7052 || offset_expr
.X_op
== O_constant
)
7054 /* If this is a reference to a GP relative symbol, we want
7055 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7056 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7057 If we have a base register, we use this
7059 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7060 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7061 If this is not a GP relative symbol, we want
7062 lui $at,<sym> (BFD_RELOC_HI16_S)
7063 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7064 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7065 If there is a base register, we add it to $at after the
7066 lui instruction. If there is a constant, we always use
7068 if (offset_expr
.X_op
== O_symbol
7069 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7070 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7072 relax_start (offset_expr
.X_add_symbol
);
7075 tempreg
= mips_gp_register
;
7079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7080 AT
, breg
, mips_gp_register
);
7085 /* Itbl support may require additional care here. */
7086 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7087 BFD_RELOC_GPREL16
, tempreg
);
7088 offset_expr
.X_add_number
+= 4;
7090 /* Set mips_optimize to 2 to avoid inserting an
7092 hold_mips_optimize
= mips_optimize
;
7094 /* Itbl support may require additional care here. */
7095 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7096 BFD_RELOC_GPREL16
, tempreg
);
7097 mips_optimize
= hold_mips_optimize
;
7101 /* We just generated two relocs. When tc_gen_reloc
7102 handles this case, it will skip the first reloc and
7103 handle the second. The second reloc already has an
7104 extra addend of 4, which we added above. We must
7105 subtract it out, and then subtract another 4 to make
7106 the first reloc come out right. The second reloc
7107 will come out right because we are going to add 4 to
7108 offset_expr when we build its instruction below.
7110 If we have a symbol, then we don't want to include
7111 the offset, because it will wind up being included
7112 when we generate the reloc. */
7114 if (offset_expr
.X_op
== O_constant
)
7115 offset_expr
.X_add_number
-= 8;
7118 offset_expr
.X_add_number
= -4;
7119 offset_expr
.X_op
= O_constant
;
7123 macro_build_lui (&offset_expr
, AT
);
7125 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7126 /* Itbl support may require additional care here. */
7127 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7128 BFD_RELOC_LO16
, AT
);
7129 /* FIXME: How do we handle overflow here? */
7130 offset_expr
.X_add_number
+= 4;
7131 /* Itbl support may require additional care here. */
7132 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7133 BFD_RELOC_LO16
, AT
);
7134 if (mips_relax
.sequence
)
7137 else if (!mips_big_got
)
7139 /* If this is a reference to an external symbol, we want
7140 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7145 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7147 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7148 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7149 If there is a base register we add it to $at before the
7150 lwc1 instructions. If there is a constant we include it
7151 in the lwc1 instructions. */
7153 expr1
.X_add_number
= offset_expr
.X_add_number
;
7154 if (expr1
.X_add_number
< -0x8000
7155 || expr1
.X_add_number
>= 0x8000 - 4)
7156 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7157 load_got_offset (AT
, &offset_expr
);
7160 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7162 /* Set mips_optimize to 2 to avoid inserting an undesired
7164 hold_mips_optimize
= mips_optimize
;
7167 /* Itbl support may require additional care here. */
7168 relax_start (offset_expr
.X_add_symbol
);
7169 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7170 BFD_RELOC_LO16
, AT
);
7171 expr1
.X_add_number
+= 4;
7172 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7173 BFD_RELOC_LO16
, AT
);
7175 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7176 BFD_RELOC_LO16
, AT
);
7177 offset_expr
.X_add_number
+= 4;
7178 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7179 BFD_RELOC_LO16
, AT
);
7182 mips_optimize
= hold_mips_optimize
;
7184 else if (mips_big_got
)
7188 /* If this is a reference to an external symbol, we want
7189 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7191 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7196 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7198 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7199 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7200 If there is a base register we add it to $at before the
7201 lwc1 instructions. If there is a constant we include it
7202 in the lwc1 instructions. */
7204 expr1
.X_add_number
= offset_expr
.X_add_number
;
7205 offset_expr
.X_add_number
= 0;
7206 if (expr1
.X_add_number
< -0x8000
7207 || expr1
.X_add_number
>= 0x8000 - 4)
7208 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7209 gpdelay
= reg_needs_delay (mips_gp_register
);
7210 relax_start (offset_expr
.X_add_symbol
);
7211 macro_build (&offset_expr
, "lui", "t,u",
7212 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7213 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7214 AT
, AT
, mips_gp_register
);
7215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7216 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7219 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7220 /* Itbl support may require additional care here. */
7221 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7222 BFD_RELOC_LO16
, AT
);
7223 expr1
.X_add_number
+= 4;
7225 /* Set mips_optimize to 2 to avoid inserting an undesired
7227 hold_mips_optimize
= mips_optimize
;
7229 /* Itbl support may require additional care here. */
7230 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7231 BFD_RELOC_LO16
, AT
);
7232 mips_optimize
= hold_mips_optimize
;
7233 expr1
.X_add_number
-= 4;
7236 offset_expr
.X_add_number
= expr1
.X_add_number
;
7238 macro_build (NULL
, "nop", "");
7239 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7240 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7243 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7244 /* Itbl support may require additional care here. */
7245 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7246 BFD_RELOC_LO16
, AT
);
7247 offset_expr
.X_add_number
+= 4;
7249 /* Set mips_optimize to 2 to avoid inserting an undesired
7251 hold_mips_optimize
= mips_optimize
;
7253 /* Itbl support may require additional care here. */
7254 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7255 BFD_RELOC_LO16
, AT
);
7256 mips_optimize
= hold_mips_optimize
;
7270 assert (HAVE_32BIT_ADDRESSES
);
7271 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7272 offset_expr
.X_add_number
+= 4;
7273 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7276 /* New code added to support COPZ instructions.
7277 This code builds table entries out of the macros in mip_opcodes.
7278 R4000 uses interlocks to handle coproc delays.
7279 Other chips (like the R3000) require nops to be inserted for delays.
7281 FIXME: Currently, we require that the user handle delays.
7282 In order to fill delay slots for non-interlocked chips,
7283 we must have a way to specify delays based on the coprocessor.
7284 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7285 What are the side-effects of the cop instruction?
7286 What cache support might we have and what are its effects?
7287 Both coprocessor & memory require delays. how long???
7288 What registers are read/set/modified?
7290 If an itbl is provided to interpret cop instructions,
7291 this knowledge can be encoded in the itbl spec. */
7305 if (NO_ISA_COP (mips_opts
.arch
)
7306 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7308 as_bad (_("opcode not supported on this processor: %s"),
7309 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7313 /* For now we just do C (same as Cz). The parameter will be
7314 stored in insn_opcode by mips_ip. */
7315 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7319 move_register (dreg
, sreg
);
7322 #ifdef LOSING_COMPILER
7324 /* Try and see if this is a new itbl instruction.
7325 This code builds table entries out of the macros in mip_opcodes.
7326 FIXME: For now we just assemble the expression and pass it's
7327 value along as a 32-bit immediate.
7328 We may want to have the assembler assemble this value,
7329 so that we gain the assembler's knowledge of delay slots,
7331 Would it be more efficient to use mask (id) here? */
7332 if (itbl_have_entries
7333 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7335 s
= ip
->insn_mo
->name
;
7337 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7338 macro_build (&immed_expr
, s
, "C");
7344 if (!mips_opts
.at
&& used_at
)
7345 as_bad (_("Macro used $at after \".set noat\""));
7349 macro2 (struct mips_cl_insn
*ip
)
7351 unsigned int treg
, sreg
, dreg
, breg
;
7352 unsigned int tempreg
;
7366 bfd_reloc_code_real_type r
;
7368 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7369 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7370 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7371 mask
= ip
->insn_mo
->mask
;
7373 expr1
.X_op
= O_constant
;
7374 expr1
.X_op_symbol
= NULL
;
7375 expr1
.X_add_symbol
= NULL
;
7376 expr1
.X_add_number
= 1;
7380 #endif /* LOSING_COMPILER */
7385 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7386 macro_build (NULL
, "mflo", "d", dreg
);
7392 /* The MIPS assembler some times generates shifts and adds. I'm
7393 not trying to be that fancy. GCC should do this for us
7396 load_register (AT
, &imm_expr
, dbl
);
7397 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7398 macro_build (NULL
, "mflo", "d", dreg
);
7414 load_register (AT
, &imm_expr
, dbl
);
7415 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7416 macro_build (NULL
, "mflo", "d", dreg
);
7417 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7418 macro_build (NULL
, "mfhi", "d", AT
);
7420 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7423 expr1
.X_add_number
= 8;
7424 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7425 macro_build (NULL
, "nop", "", 0);
7426 macro_build (NULL
, "break", "c", 6);
7429 macro_build (NULL
, "mflo", "d", dreg
);
7445 load_register (AT
, &imm_expr
, dbl
);
7446 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7447 sreg
, imm
? AT
: treg
);
7448 macro_build (NULL
, "mfhi", "d", AT
);
7449 macro_build (NULL
, "mflo", "d", dreg
);
7451 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7454 expr1
.X_add_number
= 8;
7455 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7456 macro_build (NULL
, "nop", "", 0);
7457 macro_build (NULL
, "break", "c", 6);
7463 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7474 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7475 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7479 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7480 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7481 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7482 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7486 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7497 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7498 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7502 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7503 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7504 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7505 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7513 if (imm_expr
.X_op
!= O_constant
)
7514 as_bad (_("Improper rotate count"));
7515 rot
= imm_expr
.X_add_number
& 0x3f;
7516 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7518 rot
= (64 - rot
) & 0x3f;
7520 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7522 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7527 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7530 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7531 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7534 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7535 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7536 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7544 if (imm_expr
.X_op
!= O_constant
)
7545 as_bad (_("Improper rotate count"));
7546 rot
= imm_expr
.X_add_number
& 0x1f;
7547 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7549 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7554 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7558 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7559 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7560 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7565 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7567 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7571 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7572 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7573 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7574 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7578 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7580 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7584 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7585 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7586 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7587 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7595 if (imm_expr
.X_op
!= O_constant
)
7596 as_bad (_("Improper rotate count"));
7597 rot
= imm_expr
.X_add_number
& 0x3f;
7598 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7601 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7603 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7608 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7611 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7612 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7615 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7616 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7617 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7625 if (imm_expr
.X_op
!= O_constant
)
7626 as_bad (_("Improper rotate count"));
7627 rot
= imm_expr
.X_add_number
& 0x1f;
7628 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7630 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7635 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7639 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7640 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7641 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7646 assert (mips_opts
.isa
== ISA_MIPS1
);
7647 /* Even on a big endian machine $fn comes before $fn+1. We have
7648 to adjust when storing to memory. */
7649 macro_build (&offset_expr
, "swc1", "T,o(b)",
7650 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7651 offset_expr
.X_add_number
+= 4;
7652 macro_build (&offset_expr
, "swc1", "T,o(b)",
7653 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7658 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7660 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7663 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7664 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7669 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7671 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7676 as_warn (_("Instruction %s: result is always false"),
7678 move_register (dreg
, 0);
7681 if (CPU_HAS_SEQ (mips_opts
.arch
)
7682 && -512 <= imm_expr
.X_add_number
7683 && imm_expr
.X_add_number
< 512)
7685 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7686 (int) imm_expr
.X_add_number
);
7689 if (imm_expr
.X_op
== O_constant
7690 && imm_expr
.X_add_number
>= 0
7691 && imm_expr
.X_add_number
< 0x10000)
7693 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7695 else if (imm_expr
.X_op
== O_constant
7696 && imm_expr
.X_add_number
> -0x8000
7697 && imm_expr
.X_add_number
< 0)
7699 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7700 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7701 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7703 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7706 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7707 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7712 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7713 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7716 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7719 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7725 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7726 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7729 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7731 if (imm_expr
.X_op
== O_constant
7732 && imm_expr
.X_add_number
>= -0x8000
7733 && imm_expr
.X_add_number
< 0x8000)
7735 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7736 dreg
, sreg
, BFD_RELOC_LO16
);
7740 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7741 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7745 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7748 case M_SGT
: /* sreg > treg <==> treg < sreg */
7754 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7757 case M_SGT_I
: /* sreg > I <==> I < sreg */
7764 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7765 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7768 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7774 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7775 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7778 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7785 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7786 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7787 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7791 if (imm_expr
.X_op
== O_constant
7792 && imm_expr
.X_add_number
>= -0x8000
7793 && imm_expr
.X_add_number
< 0x8000)
7795 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7799 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7800 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7804 if (imm_expr
.X_op
== O_constant
7805 && imm_expr
.X_add_number
>= -0x8000
7806 && imm_expr
.X_add_number
< 0x8000)
7808 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7813 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7814 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7819 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7821 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7824 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7825 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7830 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7832 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7837 as_warn (_("Instruction %s: result is always true"),
7839 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7840 dreg
, 0, BFD_RELOC_LO16
);
7843 if (CPU_HAS_SEQ (mips_opts
.arch
)
7844 && -512 <= imm_expr
.X_add_number
7845 && imm_expr
.X_add_number
< 512)
7847 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7848 (int) imm_expr
.X_add_number
);
7851 if (imm_expr
.X_op
== O_constant
7852 && imm_expr
.X_add_number
>= 0
7853 && imm_expr
.X_add_number
< 0x10000)
7855 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7857 else if (imm_expr
.X_op
== O_constant
7858 && imm_expr
.X_add_number
> -0x8000
7859 && imm_expr
.X_add_number
< 0)
7861 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7862 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7863 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7865 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7868 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7869 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7874 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7875 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7878 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7884 if (imm_expr
.X_op
== O_constant
7885 && imm_expr
.X_add_number
> -0x8000
7886 && imm_expr
.X_add_number
<= 0x8000)
7888 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7889 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7890 dreg
, sreg
, BFD_RELOC_LO16
);
7894 load_register (AT
, &imm_expr
, dbl
);
7895 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7901 if (imm_expr
.X_op
== O_constant
7902 && imm_expr
.X_add_number
> -0x8000
7903 && imm_expr
.X_add_number
<= 0x8000)
7905 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7906 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7907 dreg
, sreg
, BFD_RELOC_LO16
);
7911 load_register (AT
, &imm_expr
, dbl
);
7912 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7934 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7935 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7940 assert (mips_opts
.isa
== ISA_MIPS1
);
7942 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7943 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7946 * Is the double cfc1 instruction a bug in the mips assembler;
7947 * or is there a reason for it?
7950 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7951 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7952 macro_build (NULL
, "nop", "");
7953 expr1
.X_add_number
= 3;
7954 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7955 expr1
.X_add_number
= 2;
7956 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7957 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7958 macro_build (NULL
, "nop", "");
7959 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7961 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7962 macro_build (NULL
, "nop", "");
7973 if (offset_expr
.X_add_number
>= 0x7fff)
7974 as_bad (_("operand overflow"));
7975 if (! target_big_endian
)
7976 ++offset_expr
.X_add_number
;
7977 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7978 if (! target_big_endian
)
7979 --offset_expr
.X_add_number
;
7981 ++offset_expr
.X_add_number
;
7982 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7983 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7984 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7997 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7998 as_bad (_("operand overflow"));
8006 if (! target_big_endian
)
8007 offset_expr
.X_add_number
+= off
;
8008 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8009 if (! target_big_endian
)
8010 offset_expr
.X_add_number
-= off
;
8012 offset_expr
.X_add_number
+= off
;
8013 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8015 /* If necessary, move the result in tempreg the final destination. */
8016 if (treg
== tempreg
)
8018 /* Protect second load's delay slot. */
8020 move_register (treg
, tempreg
);
8034 load_address (AT
, &offset_expr
, &used_at
);
8036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8037 if (! target_big_endian
)
8038 expr1
.X_add_number
= off
;
8040 expr1
.X_add_number
= 0;
8041 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8042 if (! target_big_endian
)
8043 expr1
.X_add_number
= 0;
8045 expr1
.X_add_number
= off
;
8046 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8052 load_address (AT
, &offset_expr
, &used_at
);
8054 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8055 if (target_big_endian
)
8056 expr1
.X_add_number
= 0;
8057 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8058 treg
, BFD_RELOC_LO16
, AT
);
8059 if (target_big_endian
)
8060 expr1
.X_add_number
= 1;
8062 expr1
.X_add_number
= 0;
8063 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8064 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8065 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8070 if (offset_expr
.X_add_number
>= 0x7fff)
8071 as_bad (_("operand overflow"));
8072 if (target_big_endian
)
8073 ++offset_expr
.X_add_number
;
8074 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8075 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8076 if (target_big_endian
)
8077 --offset_expr
.X_add_number
;
8079 ++offset_expr
.X_add_number
;
8080 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8093 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8094 as_bad (_("operand overflow"));
8095 if (! target_big_endian
)
8096 offset_expr
.X_add_number
+= off
;
8097 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8098 if (! target_big_endian
)
8099 offset_expr
.X_add_number
-= off
;
8101 offset_expr
.X_add_number
+= off
;
8102 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8116 load_address (AT
, &offset_expr
, &used_at
);
8118 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8119 if (! target_big_endian
)
8120 expr1
.X_add_number
= off
;
8122 expr1
.X_add_number
= 0;
8123 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8124 if (! target_big_endian
)
8125 expr1
.X_add_number
= 0;
8127 expr1
.X_add_number
= off
;
8128 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8133 load_address (AT
, &offset_expr
, &used_at
);
8135 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8136 if (! target_big_endian
)
8137 expr1
.X_add_number
= 0;
8138 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8139 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8140 if (! target_big_endian
)
8141 expr1
.X_add_number
= 1;
8143 expr1
.X_add_number
= 0;
8144 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8145 if (! target_big_endian
)
8146 expr1
.X_add_number
= 0;
8148 expr1
.X_add_number
= 1;
8149 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8150 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8151 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8155 /* FIXME: Check if this is one of the itbl macros, since they
8156 are added dynamically. */
8157 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8160 if (!mips_opts
.at
&& used_at
)
8161 as_bad (_("Macro used $at after \".set noat\""));
8164 /* Implement macros in mips16 mode. */
8167 mips16_macro (struct mips_cl_insn
*ip
)
8170 int xreg
, yreg
, zreg
, tmp
;
8173 const char *s
, *s2
, *s3
;
8175 mask
= ip
->insn_mo
->mask
;
8177 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8178 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8179 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8181 expr1
.X_op
= O_constant
;
8182 expr1
.X_op_symbol
= NULL
;
8183 expr1
.X_add_symbol
= NULL
;
8184 expr1
.X_add_number
= 1;
8204 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8205 expr1
.X_add_number
= 2;
8206 macro_build (&expr1
, "bnez", "x,p", yreg
);
8207 macro_build (NULL
, "break", "6", 7);
8209 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8210 since that causes an overflow. We should do that as well,
8211 but I don't see how to do the comparisons without a temporary
8214 macro_build (NULL
, s
, "x", zreg
);
8234 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8235 expr1
.X_add_number
= 2;
8236 macro_build (&expr1
, "bnez", "x,p", yreg
);
8237 macro_build (NULL
, "break", "6", 7);
8239 macro_build (NULL
, s2
, "x", zreg
);
8245 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8246 macro_build (NULL
, "mflo", "x", zreg
);
8254 if (imm_expr
.X_op
!= O_constant
)
8255 as_bad (_("Unsupported large constant"));
8256 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8257 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8261 if (imm_expr
.X_op
!= O_constant
)
8262 as_bad (_("Unsupported large constant"));
8263 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8264 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8268 if (imm_expr
.X_op
!= O_constant
)
8269 as_bad (_("Unsupported large constant"));
8270 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8271 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8293 goto do_reverse_branch
;
8297 goto do_reverse_branch
;
8309 goto do_reverse_branch
;
8320 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8321 macro_build (&offset_expr
, s2
, "p");
8348 goto do_addone_branch_i
;
8353 goto do_addone_branch_i
;
8368 goto do_addone_branch_i
;
8375 if (imm_expr
.X_op
!= O_constant
)
8376 as_bad (_("Unsupported large constant"));
8377 ++imm_expr
.X_add_number
;
8380 macro_build (&imm_expr
, s
, s3
, xreg
);
8381 macro_build (&offset_expr
, s2
, "p");
8385 expr1
.X_add_number
= 0;
8386 macro_build (&expr1
, "slti", "x,8", yreg
);
8388 move_register (xreg
, yreg
);
8389 expr1
.X_add_number
= 2;
8390 macro_build (&expr1
, "bteqz", "p");
8391 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8395 /* For consistency checking, verify that all bits are specified either
8396 by the match/mask part of the instruction definition, or by the
8399 validate_mips_insn (const struct mips_opcode
*opc
)
8401 const char *p
= opc
->args
;
8403 unsigned long used_bits
= opc
->mask
;
8405 if ((used_bits
& opc
->match
) != opc
->match
)
8407 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8408 opc
->name
, opc
->args
);
8411 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8421 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8422 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8423 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8424 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8425 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8426 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8427 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8428 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8429 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8430 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8431 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8432 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8433 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8435 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8436 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8437 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8438 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8439 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8440 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8441 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8442 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8443 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8444 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8447 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8448 c
, opc
->name
, opc
->args
);
8452 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8453 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8455 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8456 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8457 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8458 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8460 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8461 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8463 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8464 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8466 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8467 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8468 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8469 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8470 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8471 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8472 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8473 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8474 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8475 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8476 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8477 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8478 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8479 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8480 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8481 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8482 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8484 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8485 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8486 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8487 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8489 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8490 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8491 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8492 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8493 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8494 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8495 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8496 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8497 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8500 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8501 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8502 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8503 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8504 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8507 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8508 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8509 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8510 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8511 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8512 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8513 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8514 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8515 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8516 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8517 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8518 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8519 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8520 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8521 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8522 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8523 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8524 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8526 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8527 c
, opc
->name
, opc
->args
);
8531 if (used_bits
!= 0xffffffff)
8533 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8534 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8540 /* UDI immediates. */
8548 static const struct mips_immed mips_immed
[] = {
8549 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8550 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8551 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8552 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8556 /* Check whether an odd floating-point register is allowed. */
8558 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8560 const char *s
= insn
->name
;
8562 if (insn
->pinfo
== INSN_MACRO
)
8563 /* Let a macro pass, we'll catch it later when it is expanded. */
8566 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8568 /* Allow odd registers for single-precision ops. */
8569 switch (insn
->pinfo
& (FP_S
| FP_D
))
8573 return 1; /* both single precision - ok */
8575 return 0; /* both double precision - fail */
8580 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8581 s
= strchr (insn
->name
, '.');
8583 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8584 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8587 /* Single-precision coprocessor loads and moves are OK too. */
8588 if ((insn
->pinfo
& FP_S
)
8589 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8590 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8596 /* This routine assembles an instruction into its binary format. As a
8597 side effect, it sets one of the global variables imm_reloc or
8598 offset_reloc to the type of relocation to do if one of the operands
8599 is an address expression. */
8602 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8607 struct mips_opcode
*insn
;
8610 unsigned int lastregno
= 0;
8611 unsigned int lastpos
= 0;
8612 unsigned int limlo
, limhi
;
8615 offsetT min_range
, max_range
;
8621 /* If the instruction contains a '.', we first try to match an instruction
8622 including the '.'. Then we try again without the '.'. */
8624 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8627 /* If we stopped on whitespace, then replace the whitespace with null for
8628 the call to hash_find. Save the character we replaced just in case we
8629 have to re-parse the instruction. */
8636 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8638 /* If we didn't find the instruction in the opcode table, try again, but
8639 this time with just the instruction up to, but not including the
8643 /* Restore the character we overwrite above (if any). */
8647 /* Scan up to the first '.' or whitespace. */
8649 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8653 /* If we did not find a '.', then we can quit now. */
8656 insn_error
= "unrecognized opcode";
8660 /* Lookup the instruction in the hash table. */
8662 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8664 insn_error
= "unrecognized opcode";
8674 assert (strcmp (insn
->name
, str
) == 0);
8676 ok
= is_opcode_valid (insn
, FALSE
);
8679 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8680 && strcmp (insn
->name
, insn
[1].name
) == 0)
8689 static char buf
[100];
8691 _("opcode not supported on this processor: %s (%s)"),
8692 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8693 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8702 create_insn (ip
, insn
);
8705 lastregno
= 0xffffffff;
8706 for (args
= insn
->args
;; ++args
)
8710 s
+= strspn (s
, " \t");
8714 case '\0': /* end of args */
8719 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8720 my_getExpression (&imm_expr
, s
);
8721 check_absolute_expr (ip
, &imm_expr
);
8722 if ((unsigned long) imm_expr
.X_add_number
!= 1
8723 && (unsigned long) imm_expr
.X_add_number
!= 3)
8725 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8726 (unsigned long) imm_expr
.X_add_number
);
8728 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8729 imm_expr
.X_op
= O_absent
;
8733 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8734 my_getExpression (&imm_expr
, s
);
8735 check_absolute_expr (ip
, &imm_expr
);
8736 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8738 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8739 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8741 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8742 imm_expr
.X_op
= O_absent
;
8746 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8747 my_getExpression (&imm_expr
, s
);
8748 check_absolute_expr (ip
, &imm_expr
);
8749 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8751 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8752 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8754 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8755 imm_expr
.X_op
= O_absent
;
8759 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8760 my_getExpression (&imm_expr
, s
);
8761 check_absolute_expr (ip
, &imm_expr
);
8762 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8764 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8765 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8767 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8768 imm_expr
.X_op
= O_absent
;
8772 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8773 my_getExpression (&imm_expr
, s
);
8774 check_absolute_expr (ip
, &imm_expr
);
8775 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8777 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8778 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8780 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8781 imm_expr
.X_op
= O_absent
;
8785 case '7': /* four dsp accumulators in bits 11,12 */
8786 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8787 s
[3] >= '0' && s
[3] <= '3')
8791 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8795 as_bad (_("Invalid dsp acc register"));
8798 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8799 my_getExpression (&imm_expr
, s
);
8800 check_absolute_expr (ip
, &imm_expr
);
8801 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8803 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8805 (unsigned long) imm_expr
.X_add_number
);
8807 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8808 imm_expr
.X_op
= O_absent
;
8812 case '9': /* four dsp accumulators in bits 21,22 */
8813 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8814 s
[3] >= '0' && s
[3] <= '3')
8818 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8822 as_bad (_("Invalid dsp acc register"));
8825 case '0': /* dsp 6-bit signed immediate in bit 20 */
8826 my_getExpression (&imm_expr
, s
);
8827 check_absolute_expr (ip
, &imm_expr
);
8828 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8829 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8830 if (imm_expr
.X_add_number
< min_range
||
8831 imm_expr
.X_add_number
> max_range
)
8833 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8834 (long) min_range
, (long) max_range
,
8835 (long) imm_expr
.X_add_number
);
8837 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8838 imm_expr
.X_op
= O_absent
;
8842 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8843 my_getExpression (&imm_expr
, s
);
8844 check_absolute_expr (ip
, &imm_expr
);
8845 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8847 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8849 (unsigned long) imm_expr
.X_add_number
);
8851 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8852 imm_expr
.X_op
= O_absent
;
8856 case ':': /* dsp 7-bit signed immediate in bit 19 */
8857 my_getExpression (&imm_expr
, s
);
8858 check_absolute_expr (ip
, &imm_expr
);
8859 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8860 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8861 if (imm_expr
.X_add_number
< min_range
||
8862 imm_expr
.X_add_number
> max_range
)
8864 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8865 (long) min_range
, (long) max_range
,
8866 (long) imm_expr
.X_add_number
);
8868 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8869 imm_expr
.X_op
= O_absent
;
8873 case '@': /* dsp 10-bit signed immediate in bit 16 */
8874 my_getExpression (&imm_expr
, s
);
8875 check_absolute_expr (ip
, &imm_expr
);
8876 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8877 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8878 if (imm_expr
.X_add_number
< min_range
||
8879 imm_expr
.X_add_number
> max_range
)
8881 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8882 (long) min_range
, (long) max_range
,
8883 (long) imm_expr
.X_add_number
);
8885 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8886 imm_expr
.X_op
= O_absent
;
8890 case '!': /* MT usermode flag bit. */
8891 my_getExpression (&imm_expr
, s
);
8892 check_absolute_expr (ip
, &imm_expr
);
8893 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8894 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8895 (unsigned long) imm_expr
.X_add_number
);
8896 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8897 imm_expr
.X_op
= O_absent
;
8901 case '$': /* MT load high flag bit. */
8902 my_getExpression (&imm_expr
, s
);
8903 check_absolute_expr (ip
, &imm_expr
);
8904 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8905 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8906 (unsigned long) imm_expr
.X_add_number
);
8907 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8908 imm_expr
.X_op
= O_absent
;
8912 case '*': /* four dsp accumulators in bits 18,19 */
8913 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8914 s
[3] >= '0' && s
[3] <= '3')
8918 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8922 as_bad (_("Invalid dsp/smartmips acc register"));
8925 case '&': /* four dsp accumulators in bits 13,14 */
8926 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8927 s
[3] >= '0' && s
[3] <= '3')
8931 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8935 as_bad (_("Invalid dsp/smartmips acc register"));
8947 INSERT_OPERAND (RS
, *ip
, lastregno
);
8951 INSERT_OPERAND (RT
, *ip
, lastregno
);
8955 INSERT_OPERAND (FT
, *ip
, lastregno
);
8959 INSERT_OPERAND (FS
, *ip
, lastregno
);
8965 /* Handle optional base register.
8966 Either the base register is omitted or
8967 we must have a left paren. */
8968 /* This is dependent on the next operand specifier
8969 is a base register specification. */
8970 assert (args
[1] == 'b' || args
[1] == '5'
8971 || args
[1] == '-' || args
[1] == '4');
8975 case ')': /* these must match exactly */
8982 case '+': /* Opcode extension character. */
8985 case '1': /* UDI immediates. */
8990 const struct mips_immed
*imm
= mips_immed
;
8992 while (imm
->type
&& imm
->type
!= *args
)
8996 my_getExpression (&imm_expr
, s
);
8997 check_absolute_expr (ip
, &imm_expr
);
8998 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
9000 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9001 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
9002 (unsigned long) imm_expr
.X_add_number
,
9003 (unsigned long) imm_expr
.X_add_number
);
9004 imm_expr
.X_add_number
&= imm
->mask
;
9006 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
9008 imm_expr
.X_op
= O_absent
;
9013 case 'A': /* ins/ext position, becomes LSB. */
9022 my_getExpression (&imm_expr
, s
);
9023 check_absolute_expr (ip
, &imm_expr
);
9024 if ((unsigned long) imm_expr
.X_add_number
< limlo
9025 || (unsigned long) imm_expr
.X_add_number
> limhi
)
9027 as_bad (_("Improper position (%lu)"),
9028 (unsigned long) imm_expr
.X_add_number
);
9029 imm_expr
.X_add_number
= limlo
;
9031 lastpos
= imm_expr
.X_add_number
;
9032 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9033 imm_expr
.X_op
= O_absent
;
9037 case 'B': /* ins size, becomes MSB. */
9046 my_getExpression (&imm_expr
, s
);
9047 check_absolute_expr (ip
, &imm_expr
);
9048 /* Check for negative input so that small negative numbers
9049 will not succeed incorrectly. The checks against
9050 (pos+size) transitively check "size" itself,
9051 assuming that "pos" is reasonable. */
9052 if ((long) imm_expr
.X_add_number
< 0
9053 || ((unsigned long) imm_expr
.X_add_number
9055 || ((unsigned long) imm_expr
.X_add_number
9058 as_bad (_("Improper insert size (%lu, position %lu)"),
9059 (unsigned long) imm_expr
.X_add_number
,
9060 (unsigned long) lastpos
);
9061 imm_expr
.X_add_number
= limlo
- lastpos
;
9063 INSERT_OPERAND (INSMSB
, *ip
,
9064 lastpos
+ imm_expr
.X_add_number
- 1);
9065 imm_expr
.X_op
= O_absent
;
9069 case 'C': /* ext size, becomes MSBD. */
9082 my_getExpression (&imm_expr
, s
);
9083 check_absolute_expr (ip
, &imm_expr
);
9084 /* Check for negative input so that small negative numbers
9085 will not succeed incorrectly. The checks against
9086 (pos+size) transitively check "size" itself,
9087 assuming that "pos" is reasonable. */
9088 if ((long) imm_expr
.X_add_number
< 0
9089 || ((unsigned long) imm_expr
.X_add_number
9091 || ((unsigned long) imm_expr
.X_add_number
9094 as_bad (_("Improper extract size (%lu, position %lu)"),
9095 (unsigned long) imm_expr
.X_add_number
,
9096 (unsigned long) lastpos
);
9097 imm_expr
.X_add_number
= limlo
- lastpos
;
9099 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9100 imm_expr
.X_op
= O_absent
;
9105 /* +D is for disassembly only; never match. */
9109 /* "+I" is like "I", except that imm2_expr is used. */
9110 my_getExpression (&imm2_expr
, s
);
9111 if (imm2_expr
.X_op
!= O_big
9112 && imm2_expr
.X_op
!= O_constant
)
9113 insn_error
= _("absolute expression required");
9114 if (HAVE_32BIT_GPRS
)
9115 normalize_constant_expr (&imm2_expr
);
9119 case 'T': /* Coprocessor register. */
9120 /* +T is for disassembly only; never match. */
9123 case 't': /* Coprocessor register number. */
9124 if (s
[0] == '$' && ISDIGIT (s
[1]))
9134 while (ISDIGIT (*s
));
9136 as_bad (_("Invalid register number (%d)"), regno
);
9139 INSERT_OPERAND (RT
, *ip
, regno
);
9144 as_bad (_("Invalid coprocessor 0 register number"));
9148 /* bbit[01] and bbit[01]32 bit index. Give error if index
9149 is not in the valid range. */
9150 my_getExpression (&imm_expr
, s
);
9151 check_absolute_expr (ip
, &imm_expr
);
9152 if ((unsigned) imm_expr
.X_add_number
> 31)
9154 as_bad (_("Improper bit index (%lu)"),
9155 (unsigned long) imm_expr
.X_add_number
);
9156 imm_expr
.X_add_number
= 0;
9158 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9159 imm_expr
.X_op
= O_absent
;
9164 /* bbit[01] bit index when bbit is used but we generate
9165 bbit[01]32 because the index is over 32. Move to the
9166 next candidate if index is not in the valid range. */
9167 my_getExpression (&imm_expr
, s
);
9168 check_absolute_expr (ip
, &imm_expr
);
9169 if ((unsigned) imm_expr
.X_add_number
< 32
9170 || (unsigned) imm_expr
.X_add_number
> 63)
9172 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9173 imm_expr
.X_op
= O_absent
;
9178 /* cins, cins32, exts and exts32 position field. Give error
9179 if it's not in the valid range. */
9180 my_getExpression (&imm_expr
, s
);
9181 check_absolute_expr (ip
, &imm_expr
);
9182 if ((unsigned) imm_expr
.X_add_number
> 31)
9184 as_bad (_("Improper position (%lu)"),
9185 (unsigned long) imm_expr
.X_add_number
);
9186 imm_expr
.X_add_number
= 0;
9188 /* Make the pos explicit to simplify +S. */
9189 lastpos
= imm_expr
.X_add_number
+ 32;
9190 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9191 imm_expr
.X_op
= O_absent
;
9196 /* cins, cins32, exts and exts32 position field. Move to
9197 the next candidate if it's not in the valid range. */
9198 my_getExpression (&imm_expr
, s
);
9199 check_absolute_expr (ip
, &imm_expr
);
9200 if ((unsigned) imm_expr
.X_add_number
< 32
9201 || (unsigned) imm_expr
.X_add_number
> 63)
9203 lastpos
= imm_expr
.X_add_number
;
9204 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9205 imm_expr
.X_op
= O_absent
;
9210 /* cins and exts length-minus-one field. */
9211 my_getExpression (&imm_expr
, s
);
9212 check_absolute_expr (ip
, &imm_expr
);
9213 if ((unsigned long) imm_expr
.X_add_number
> 31)
9215 as_bad (_("Improper size (%lu)"),
9216 (unsigned long) imm_expr
.X_add_number
);
9217 imm_expr
.X_add_number
= 0;
9219 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9220 imm_expr
.X_op
= O_absent
;
9225 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9226 length-minus-one field. */
9227 my_getExpression (&imm_expr
, s
);
9228 check_absolute_expr (ip
, &imm_expr
);
9229 if ((long) imm_expr
.X_add_number
< 0
9230 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9232 as_bad (_("Improper size (%lu)"),
9233 (unsigned long) imm_expr
.X_add_number
);
9234 imm_expr
.X_add_number
= 0;
9236 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9237 imm_expr
.X_op
= O_absent
;
9242 /* seqi/snei immediate field. */
9243 my_getExpression (&imm_expr
, s
);
9244 check_absolute_expr (ip
, &imm_expr
);
9245 if ((long) imm_expr
.X_add_number
< -512
9246 || (long) imm_expr
.X_add_number
>= 512)
9248 as_bad (_("Improper immediate (%ld)"),
9249 (long) imm_expr
.X_add_number
);
9250 imm_expr
.X_add_number
= 0;
9252 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9253 imm_expr
.X_op
= O_absent
;
9258 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9259 *args
, insn
->name
, insn
->args
);
9260 /* Further processing is fruitless. */
9265 case '<': /* must be at least one digit */
9267 * According to the manual, if the shift amount is greater
9268 * than 31 or less than 0, then the shift amount should be
9269 * mod 32. In reality the mips assembler issues an error.
9270 * We issue a warning and mask out all but the low 5 bits.
9272 my_getExpression (&imm_expr
, s
);
9273 check_absolute_expr (ip
, &imm_expr
);
9274 if ((unsigned long) imm_expr
.X_add_number
> 31)
9275 as_warn (_("Improper shift amount (%lu)"),
9276 (unsigned long) imm_expr
.X_add_number
);
9277 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9278 imm_expr
.X_op
= O_absent
;
9282 case '>': /* shift amount minus 32 */
9283 my_getExpression (&imm_expr
, s
);
9284 check_absolute_expr (ip
, &imm_expr
);
9285 if ((unsigned long) imm_expr
.X_add_number
< 32
9286 || (unsigned long) imm_expr
.X_add_number
> 63)
9288 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9289 imm_expr
.X_op
= O_absent
;
9293 case 'k': /* cache code */
9294 case 'h': /* prefx code */
9295 case '1': /* sync type */
9296 my_getExpression (&imm_expr
, s
);
9297 check_absolute_expr (ip
, &imm_expr
);
9298 if ((unsigned long) imm_expr
.X_add_number
> 31)
9299 as_warn (_("Invalid value for `%s' (%lu)"),
9301 (unsigned long) imm_expr
.X_add_number
);
9303 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9304 else if (*args
== 'h')
9305 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9307 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9308 imm_expr
.X_op
= O_absent
;
9312 case 'c': /* break code */
9313 my_getExpression (&imm_expr
, s
);
9314 check_absolute_expr (ip
, &imm_expr
);
9315 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9316 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9318 (unsigned long) imm_expr
.X_add_number
);
9319 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9320 imm_expr
.X_op
= O_absent
;
9324 case 'q': /* lower break code */
9325 my_getExpression (&imm_expr
, s
);
9326 check_absolute_expr (ip
, &imm_expr
);
9327 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9328 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9330 (unsigned long) imm_expr
.X_add_number
);
9331 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9332 imm_expr
.X_op
= O_absent
;
9336 case 'B': /* 20-bit syscall/break code. */
9337 my_getExpression (&imm_expr
, s
);
9338 check_absolute_expr (ip
, &imm_expr
);
9339 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9340 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9342 (unsigned long) imm_expr
.X_add_number
);
9343 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9344 imm_expr
.X_op
= O_absent
;
9348 case 'C': /* Coprocessor code */
9349 my_getExpression (&imm_expr
, s
);
9350 check_absolute_expr (ip
, &imm_expr
);
9351 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9353 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9354 (unsigned long) imm_expr
.X_add_number
);
9355 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9357 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9358 imm_expr
.X_op
= O_absent
;
9362 case 'J': /* 19-bit wait code. */
9363 my_getExpression (&imm_expr
, s
);
9364 check_absolute_expr (ip
, &imm_expr
);
9365 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9367 as_warn (_("Illegal 19-bit code (%lu)"),
9368 (unsigned long) imm_expr
.X_add_number
);
9369 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9371 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9372 imm_expr
.X_op
= O_absent
;
9376 case 'P': /* Performance register. */
9377 my_getExpression (&imm_expr
, s
);
9378 check_absolute_expr (ip
, &imm_expr
);
9379 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9380 as_warn (_("Invalid performance register (%lu)"),
9381 (unsigned long) imm_expr
.X_add_number
);
9382 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9383 imm_expr
.X_op
= O_absent
;
9387 case 'G': /* Coprocessor destination register. */
9388 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9389 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9391 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9392 INSERT_OPERAND (RD
, *ip
, regno
);
9401 case 'b': /* base register */
9402 case 'd': /* destination register */
9403 case 's': /* source register */
9404 case 't': /* target register */
9405 case 'r': /* both target and source */
9406 case 'v': /* both dest and source */
9407 case 'w': /* both dest and target */
9408 case 'E': /* coprocessor target register */
9409 case 'K': /* 'rdhwr' destination register */
9410 case 'x': /* ignore register name */
9411 case 'z': /* must be zero register */
9412 case 'U': /* destination register (clo/clz). */
9413 case 'g': /* coprocessor destination register */
9415 if (*args
== 'E' || *args
== 'K')
9416 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9419 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9420 if (regno
== AT
&& mips_opts
.at
)
9422 if (mips_opts
.at
== ATREG
)
9423 as_warn (_("used $at without \".set noat\""));
9425 as_warn (_("used $%u with \".set at=$%u\""),
9426 regno
, mips_opts
.at
);
9436 if (c
== 'r' || c
== 'v' || c
== 'w')
9443 /* 'z' only matches $0. */
9444 if (c
== 'z' && regno
!= 0)
9447 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9449 if (regno
== lastregno
)
9451 insn_error
= _("source and destination must be different");
9454 if (regno
== 31 && lastregno
== 0xffffffff)
9456 insn_error
= _("a destination register must be supplied");
9460 /* Now that we have assembled one operand, we use the args string
9461 * to figure out where it goes in the instruction. */
9468 INSERT_OPERAND (RS
, *ip
, regno
);
9474 INSERT_OPERAND (RD
, *ip
, regno
);
9477 INSERT_OPERAND (RD
, *ip
, regno
);
9478 INSERT_OPERAND (RT
, *ip
, regno
);
9483 INSERT_OPERAND (RT
, *ip
, regno
);
9486 /* This case exists because on the r3000 trunc
9487 expands into a macro which requires a gp
9488 register. On the r6000 or r4000 it is
9489 assembled into a single instruction which
9490 ignores the register. Thus the insn version
9491 is MIPS_ISA2 and uses 'x', and the macro
9492 version is MIPS_ISA1 and uses 't'. */
9495 /* This case is for the div instruction, which
9496 acts differently if the destination argument
9497 is $0. This only matches $0, and is checked
9498 outside the switch. */
9501 /* Itbl operand; not yet implemented. FIXME ?? */
9503 /* What about all other operands like 'i', which
9504 can be specified in the opcode table? */
9513 INSERT_OPERAND (RS
, *ip
, lastregno
);
9516 INSERT_OPERAND (RT
, *ip
, lastregno
);
9521 case 'O': /* MDMX alignment immediate constant. */
9522 my_getExpression (&imm_expr
, s
);
9523 check_absolute_expr (ip
, &imm_expr
);
9524 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9525 as_warn ("Improper align amount (%ld), using low bits",
9526 (long) imm_expr
.X_add_number
);
9527 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9528 imm_expr
.X_op
= O_absent
;
9532 case 'Q': /* MDMX vector, element sel, or const. */
9535 /* MDMX Immediate. */
9536 my_getExpression (&imm_expr
, s
);
9537 check_absolute_expr (ip
, &imm_expr
);
9538 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9539 as_warn (_("Invalid MDMX Immediate (%ld)"),
9540 (long) imm_expr
.X_add_number
);
9541 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9542 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9543 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9545 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9546 imm_expr
.X_op
= O_absent
;
9550 /* Not MDMX Immediate. Fall through. */
9551 case 'X': /* MDMX destination register. */
9552 case 'Y': /* MDMX source register. */
9553 case 'Z': /* MDMX target register. */
9555 case 'D': /* floating point destination register */
9556 case 'S': /* floating point source register */
9557 case 'T': /* floating point target register */
9558 case 'R': /* floating point source register */
9563 || (mips_opts
.ase_mdmx
9564 && (ip
->insn_mo
->pinfo
& FP_D
)
9565 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9566 | INSN_COPROC_MEMORY_DELAY
9567 | INSN_LOAD_COPROC_DELAY
9568 | INSN_LOAD_MEMORY_DELAY
9569 | INSN_STORE_MEMORY
))))
9572 if (reg_lookup (&s
, rtype
, ®no
))
9574 if ((regno
& 1) != 0
9576 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9577 as_warn (_("Float register should be even, was %d"),
9585 if (c
== 'V' || c
== 'W')
9596 INSERT_OPERAND (FD
, *ip
, regno
);
9601 INSERT_OPERAND (FS
, *ip
, regno
);
9604 /* This is like 'Z', but also needs to fix the MDMX
9605 vector/scalar select bits. Note that the
9606 scalar immediate case is handled above. */
9609 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9610 int max_el
= (is_qh
? 3 : 7);
9612 my_getExpression(&imm_expr
, s
);
9613 check_absolute_expr (ip
, &imm_expr
);
9615 if (imm_expr
.X_add_number
> max_el
)
9616 as_bad(_("Bad element selector %ld"),
9617 (long) imm_expr
.X_add_number
);
9618 imm_expr
.X_add_number
&= max_el
;
9619 ip
->insn_opcode
|= (imm_expr
.X_add_number
9622 imm_expr
.X_op
= O_absent
;
9624 as_warn(_("Expecting ']' found '%s'"), s
);
9630 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9631 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9634 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9641 INSERT_OPERAND (FT
, *ip
, regno
);
9644 INSERT_OPERAND (FR
, *ip
, regno
);
9654 INSERT_OPERAND (FS
, *ip
, lastregno
);
9657 INSERT_OPERAND (FT
, *ip
, lastregno
);
9663 my_getExpression (&imm_expr
, s
);
9664 if (imm_expr
.X_op
!= O_big
9665 && imm_expr
.X_op
!= O_constant
)
9666 insn_error
= _("absolute expression required");
9667 if (HAVE_32BIT_GPRS
)
9668 normalize_constant_expr (&imm_expr
);
9673 my_getExpression (&offset_expr
, s
);
9674 normalize_address_expr (&offset_expr
);
9675 *imm_reloc
= BFD_RELOC_32
;
9688 unsigned char temp
[8];
9690 unsigned int length
;
9695 /* These only appear as the last operand in an
9696 instruction, and every instruction that accepts
9697 them in any variant accepts them in all variants.
9698 This means we don't have to worry about backing out
9699 any changes if the instruction does not match.
9701 The difference between them is the size of the
9702 floating point constant and where it goes. For 'F'
9703 and 'L' the constant is 64 bits; for 'f' and 'l' it
9704 is 32 bits. Where the constant is placed is based
9705 on how the MIPS assembler does things:
9708 f -- immediate value
9711 The .lit4 and .lit8 sections are only used if
9712 permitted by the -G argument.
9714 The code below needs to know whether the target register
9715 is 32 or 64 bits wide. It relies on the fact 'f' and
9716 'F' are used with GPR-based instructions and 'l' and
9717 'L' are used with FPR-based instructions. */
9719 f64
= *args
== 'F' || *args
== 'L';
9720 using_gprs
= *args
== 'F' || *args
== 'f';
9722 save_in
= input_line_pointer
;
9723 input_line_pointer
= s
;
9724 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9726 s
= input_line_pointer
;
9727 input_line_pointer
= save_in
;
9728 if (err
!= NULL
&& *err
!= '\0')
9730 as_bad (_("Bad floating point constant: %s"), err
);
9731 memset (temp
, '\0', sizeof temp
);
9732 length
= f64
? 8 : 4;
9735 assert (length
== (unsigned) (f64
? 8 : 4));
9739 && (g_switch_value
< 4
9740 || (temp
[0] == 0 && temp
[1] == 0)
9741 || (temp
[2] == 0 && temp
[3] == 0))))
9743 imm_expr
.X_op
= O_constant
;
9744 if (! target_big_endian
)
9745 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9747 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9750 && ! mips_disable_float_construction
9751 /* Constants can only be constructed in GPRs and
9752 copied to FPRs if the GPRs are at least as wide
9753 as the FPRs. Force the constant into memory if
9754 we are using 64-bit FPRs but the GPRs are only
9757 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9758 && ((temp
[0] == 0 && temp
[1] == 0)
9759 || (temp
[2] == 0 && temp
[3] == 0))
9760 && ((temp
[4] == 0 && temp
[5] == 0)
9761 || (temp
[6] == 0 && temp
[7] == 0)))
9763 /* The value is simple enough to load with a couple of
9764 instructions. If using 32-bit registers, set
9765 imm_expr to the high order 32 bits and offset_expr to
9766 the low order 32 bits. Otherwise, set imm_expr to
9767 the entire 64 bit constant. */
9768 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9770 imm_expr
.X_op
= O_constant
;
9771 offset_expr
.X_op
= O_constant
;
9772 if (! target_big_endian
)
9774 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9775 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9779 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9780 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9782 if (offset_expr
.X_add_number
== 0)
9783 offset_expr
.X_op
= O_absent
;
9785 else if (sizeof (imm_expr
.X_add_number
) > 4)
9787 imm_expr
.X_op
= O_constant
;
9788 if (! target_big_endian
)
9789 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9791 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9795 imm_expr
.X_op
= O_big
;
9796 imm_expr
.X_add_number
= 4;
9797 if (! target_big_endian
)
9799 generic_bignum
[0] = bfd_getl16 (temp
);
9800 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9801 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9802 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9806 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9807 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9808 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9809 generic_bignum
[3] = bfd_getb16 (temp
);
9815 const char *newname
;
9818 /* Switch to the right section. */
9820 subseg
= now_subseg
;
9823 default: /* unused default case avoids warnings. */
9825 newname
= RDATA_SECTION_NAME
;
9826 if (g_switch_value
>= 8)
9830 newname
= RDATA_SECTION_NAME
;
9833 assert (g_switch_value
>= 4);
9837 new_seg
= subseg_new (newname
, (subsegT
) 0);
9839 bfd_set_section_flags (stdoutput
, new_seg
,
9844 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9845 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9846 record_alignment (new_seg
, 4);
9848 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9850 as_bad (_("Can't use floating point insn in this section"));
9852 /* Set the argument to the current address in the
9854 offset_expr
.X_op
= O_symbol
;
9855 offset_expr
.X_add_symbol
=
9856 symbol_new ("L0\001", now_seg
,
9857 (valueT
) frag_now_fix (), frag_now
);
9858 offset_expr
.X_add_number
= 0;
9860 /* Put the floating point number into the section. */
9861 p
= frag_more ((int) length
);
9862 memcpy (p
, temp
, length
);
9864 /* Switch back to the original section. */
9865 subseg_set (seg
, subseg
);
9870 case 'i': /* 16 bit unsigned immediate */
9871 case 'j': /* 16 bit signed immediate */
9872 *imm_reloc
= BFD_RELOC_LO16
;
9873 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9876 offsetT minval
, maxval
;
9878 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9879 && strcmp (insn
->name
, insn
[1].name
) == 0);
9881 /* If the expression was written as an unsigned number,
9882 only treat it as signed if there are no more
9886 && sizeof (imm_expr
.X_add_number
) <= 4
9887 && imm_expr
.X_op
== O_constant
9888 && imm_expr
.X_add_number
< 0
9889 && imm_expr
.X_unsigned
9893 /* For compatibility with older assemblers, we accept
9894 0x8000-0xffff as signed 16-bit numbers when only
9895 signed numbers are allowed. */
9897 minval
= 0, maxval
= 0xffff;
9899 minval
= -0x8000, maxval
= 0x7fff;
9901 minval
= -0x8000, maxval
= 0xffff;
9903 if (imm_expr
.X_op
!= O_constant
9904 || imm_expr
.X_add_number
< minval
9905 || imm_expr
.X_add_number
> maxval
)
9909 if (imm_expr
.X_op
== O_constant
9910 || imm_expr
.X_op
== O_big
)
9911 as_bad (_("expression out of range"));
9917 case 'o': /* 16 bit offset */
9918 /* Check whether there is only a single bracketed expression
9919 left. If so, it must be the base register and the
9920 constant must be zero. */
9921 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9923 offset_expr
.X_op
= O_constant
;
9924 offset_expr
.X_add_number
= 0;
9928 /* If this value won't fit into a 16 bit offset, then go
9929 find a macro that will generate the 32 bit offset
9931 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9932 && (offset_expr
.X_op
!= O_constant
9933 || offset_expr
.X_add_number
>= 0x8000
9934 || offset_expr
.X_add_number
< -0x8000))
9940 case 'p': /* pc relative offset */
9941 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9942 my_getExpression (&offset_expr
, s
);
9946 case 'u': /* upper 16 bits */
9947 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9948 && imm_expr
.X_op
== O_constant
9949 && (imm_expr
.X_add_number
< 0
9950 || imm_expr
.X_add_number
>= 0x10000))
9951 as_bad (_("lui expression not in range 0..65535"));
9955 case 'a': /* 26 bit address */
9956 my_getExpression (&offset_expr
, s
);
9958 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9961 case 'N': /* 3 bit branch condition code */
9962 case 'M': /* 3 bit compare condition code */
9964 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9966 if (!reg_lookup (&s
, rtype
, ®no
))
9968 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9969 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9970 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9971 && (regno
& 1) != 0)
9972 as_warn(_("Condition code register should be even for %s, was %d"),
9974 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9975 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9976 && (regno
& 3) != 0)
9977 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9980 INSERT_OPERAND (BCC
, *ip
, regno
);
9982 INSERT_OPERAND (CCC
, *ip
, regno
);
9986 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9997 while (ISDIGIT (*s
));
10000 c
= 8; /* Invalid sel value. */
10003 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10004 ip
->insn_opcode
|= c
;
10008 /* Must be at least one digit. */
10009 my_getExpression (&imm_expr
, s
);
10010 check_absolute_expr (ip
, &imm_expr
);
10012 if ((unsigned long) imm_expr
.X_add_number
10013 > (unsigned long) OP_MASK_VECBYTE
)
10015 as_bad (_("bad byte vector index (%ld)"),
10016 (long) imm_expr
.X_add_number
);
10017 imm_expr
.X_add_number
= 0;
10020 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
10021 imm_expr
.X_op
= O_absent
;
10026 my_getExpression (&imm_expr
, s
);
10027 check_absolute_expr (ip
, &imm_expr
);
10029 if ((unsigned long) imm_expr
.X_add_number
10030 > (unsigned long) OP_MASK_VECALIGN
)
10032 as_bad (_("bad byte vector index (%ld)"),
10033 (long) imm_expr
.X_add_number
);
10034 imm_expr
.X_add_number
= 0;
10037 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10038 imm_expr
.X_op
= O_absent
;
10043 as_bad (_("bad char = '%c'\n"), *args
);
10048 /* Args don't match. */
10049 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10050 !strcmp (insn
->name
, insn
[1].name
))
10054 insn_error
= _("illegal operands");
10058 *(--argsStart
) = save_c
;
10059 insn_error
= _("illegal operands");
10064 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10066 /* This routine assembles an instruction into its binary format when
10067 assembling for the mips16. As a side effect, it sets one of the
10068 global variables imm_reloc or offset_reloc to the type of
10069 relocation to do if one of the operands is an address expression.
10070 It also sets mips16_small and mips16_ext if the user explicitly
10071 requested a small or extended instruction. */
10074 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10078 struct mips_opcode
*insn
;
10080 unsigned int regno
;
10081 unsigned int lastregno
= 0;
10087 mips16_small
= FALSE
;
10088 mips16_ext
= FALSE
;
10090 for (s
= str
; ISLOWER (*s
); ++s
)
10102 if (s
[1] == 't' && s
[2] == ' ')
10105 mips16_small
= TRUE
;
10109 else if (s
[1] == 'e' && s
[2] == ' ')
10116 /* Fall through. */
10118 insn_error
= _("unknown opcode");
10122 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10123 mips16_small
= TRUE
;
10125 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10127 insn_error
= _("unrecognized opcode");
10136 assert (strcmp (insn
->name
, str
) == 0);
10138 ok
= is_opcode_valid_16 (insn
);
10141 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10142 && strcmp (insn
->name
, insn
[1].name
) == 0)
10151 static char buf
[100];
10153 _("opcode not supported on this processor: %s (%s)"),
10154 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10155 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10162 create_insn (ip
, insn
);
10163 imm_expr
.X_op
= O_absent
;
10164 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10165 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10166 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10167 imm2_expr
.X_op
= O_absent
;
10168 offset_expr
.X_op
= O_absent
;
10169 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10170 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10171 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10172 for (args
= insn
->args
; 1; ++args
)
10179 /* In this switch statement we call break if we did not find
10180 a match, continue if we did find a match, or return if we
10189 /* Stuff the immediate value in now, if we can. */
10190 if (imm_expr
.X_op
== O_constant
10191 && *imm_reloc
> BFD_RELOC_UNUSED
10192 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10193 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10194 && insn
->pinfo
!= INSN_MACRO
)
10198 switch (*offset_reloc
)
10200 case BFD_RELOC_MIPS16_HI16_S
:
10201 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10204 case BFD_RELOC_MIPS16_HI16
:
10205 tmp
= imm_expr
.X_add_number
>> 16;
10208 case BFD_RELOC_MIPS16_LO16
:
10209 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10213 case BFD_RELOC_UNUSED
:
10214 tmp
= imm_expr
.X_add_number
;
10220 *offset_reloc
= BFD_RELOC_UNUSED
;
10222 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10223 tmp
, TRUE
, mips16_small
,
10224 mips16_ext
, &ip
->insn_opcode
,
10225 &ip
->use_extend
, &ip
->extend
);
10226 imm_expr
.X_op
= O_absent
;
10227 *imm_reloc
= BFD_RELOC_UNUSED
;
10241 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10244 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10260 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10262 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10266 /* Fall through. */
10277 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10279 if (c
== 'v' || c
== 'w')
10282 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10284 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10295 if (c
== 'v' || c
== 'w')
10297 regno
= mips16_to_32_reg_map
[lastregno
];
10311 regno
= mips32_to_16_reg_map
[regno
];
10316 regno
= ILLEGAL_REG
;
10321 regno
= ILLEGAL_REG
;
10326 regno
= ILLEGAL_REG
;
10331 if (regno
== AT
&& mips_opts
.at
)
10333 if (mips_opts
.at
== ATREG
)
10334 as_warn (_("used $at without \".set noat\""));
10336 as_warn (_("used $%u with \".set at=$%u\""),
10337 regno
, mips_opts
.at
);
10345 if (regno
== ILLEGAL_REG
)
10352 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10356 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10359 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10362 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10368 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10371 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10372 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10382 if (strncmp (s
, "$pc", 3) == 0)
10399 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10402 if (imm_expr
.X_op
!= O_constant
)
10405 ip
->use_extend
= TRUE
;
10410 /* We need to relax this instruction. */
10411 *offset_reloc
= *imm_reloc
;
10412 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10417 *imm_reloc
= BFD_RELOC_UNUSED
;
10418 /* Fall through. */
10425 my_getExpression (&imm_expr
, s
);
10426 if (imm_expr
.X_op
== O_register
)
10428 /* What we thought was an expression turned out to
10431 if (s
[0] == '(' && args
[1] == '(')
10433 /* It looks like the expression was omitted
10434 before a register indirection, which means
10435 that the expression is implicitly zero. We
10436 still set up imm_expr, so that we handle
10437 explicit extensions correctly. */
10438 imm_expr
.X_op
= O_constant
;
10439 imm_expr
.X_add_number
= 0;
10440 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10447 /* We need to relax this instruction. */
10448 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10457 /* We use offset_reloc rather than imm_reloc for the PC
10458 relative operands. This lets macros with both
10459 immediate and address operands work correctly. */
10460 my_getExpression (&offset_expr
, s
);
10462 if (offset_expr
.X_op
== O_register
)
10465 /* We need to relax this instruction. */
10466 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10470 case '6': /* break code */
10471 my_getExpression (&imm_expr
, s
);
10472 check_absolute_expr (ip
, &imm_expr
);
10473 if ((unsigned long) imm_expr
.X_add_number
> 63)
10474 as_warn (_("Invalid value for `%s' (%lu)"),
10476 (unsigned long) imm_expr
.X_add_number
);
10477 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10478 imm_expr
.X_op
= O_absent
;
10482 case 'a': /* 26 bit address */
10483 my_getExpression (&offset_expr
, s
);
10485 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10486 ip
->insn_opcode
<<= 16;
10489 case 'l': /* register list for entry macro */
10490 case 'L': /* register list for exit macro */
10500 unsigned int freg
, reg1
, reg2
;
10502 while (*s
== ' ' || *s
== ',')
10504 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10506 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10510 as_bad (_("can't parse register list"));
10520 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10521 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10523 as_bad (_("invalid register list"));
10527 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10529 mask
&= ~ (7 << 3);
10532 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10534 mask
&= ~ (7 << 3);
10537 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10538 mask
|= (reg2
- 3) << 3;
10539 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10540 mask
|= (reg2
- 15) << 1;
10541 else if (reg1
== RA
&& reg2
== RA
)
10545 as_bad (_("invalid register list"));
10549 /* The mask is filled in in the opcode table for the
10550 benefit of the disassembler. We remove it before
10551 applying the actual mask. */
10552 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10553 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10557 case 'm': /* Register list for save insn. */
10558 case 'M': /* Register list for restore insn. */
10561 int framesz
= 0, seen_framesz
= 0;
10562 int args
= 0, statics
= 0, sregs
= 0;
10566 unsigned int reg1
, reg2
;
10568 SKIP_SPACE_TABS (s
);
10571 SKIP_SPACE_TABS (s
);
10573 my_getExpression (&imm_expr
, s
);
10574 if (imm_expr
.X_op
== O_constant
)
10576 /* Handle the frame size. */
10579 as_bad (_("more than one frame size in list"));
10583 framesz
= imm_expr
.X_add_number
;
10584 imm_expr
.X_op
= O_absent
;
10589 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10591 as_bad (_("can't parse register list"));
10603 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10606 as_bad (_("can't parse register list"));
10611 while (reg1
<= reg2
)
10613 if (reg1
>= 4 && reg1
<= 7)
10617 args
|= 1 << (reg1
- 4);
10619 /* statics $a0-$a3 */
10620 statics
|= 1 << (reg1
- 4);
10622 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10625 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10627 else if (reg1
== 31)
10629 /* Add $ra to insn. */
10634 as_bad (_("unexpected register in list"));
10642 /* Encode args/statics combination. */
10643 if (args
& statics
)
10644 as_bad (_("arg/static registers overlap"));
10645 else if (args
== 0xf)
10646 /* All $a0-$a3 are args. */
10647 opcode
|= MIPS16_ALL_ARGS
<< 16;
10648 else if (statics
== 0xf)
10649 /* All $a0-$a3 are statics. */
10650 opcode
|= MIPS16_ALL_STATICS
<< 16;
10653 int narg
= 0, nstat
= 0;
10655 /* Count arg registers. */
10662 as_bad (_("invalid arg register list"));
10664 /* Count static registers. */
10665 while (statics
& 0x8)
10667 statics
= (statics
<< 1) & 0xf;
10671 as_bad (_("invalid static register list"));
10673 /* Encode args/statics. */
10674 opcode
|= ((narg
<< 2) | nstat
) << 16;
10677 /* Encode $s0/$s1. */
10678 if (sregs
& (1 << 0)) /* $s0 */
10680 if (sregs
& (1 << 1)) /* $s1 */
10686 /* Count regs $s2-$s8. */
10694 as_bad (_("invalid static register list"));
10695 /* Encode $s2-$s8. */
10696 opcode
|= nsreg
<< 24;
10699 /* Encode frame size. */
10701 as_bad (_("missing frame size"));
10702 else if ((framesz
& 7) != 0 || framesz
< 0
10703 || framesz
> 0xff * 8)
10704 as_bad (_("invalid frame size"));
10705 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10708 opcode
|= (((framesz
& 0xf0) << 16)
10709 | (framesz
& 0x0f));
10712 /* Finally build the instruction. */
10713 if ((opcode
>> 16) != 0 || framesz
== 0)
10715 ip
->use_extend
= TRUE
;
10716 ip
->extend
= opcode
>> 16;
10718 ip
->insn_opcode
|= opcode
& 0x7f;
10722 case 'e': /* extend code */
10723 my_getExpression (&imm_expr
, s
);
10724 check_absolute_expr (ip
, &imm_expr
);
10725 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10727 as_warn (_("Invalid value for `%s' (%lu)"),
10729 (unsigned long) imm_expr
.X_add_number
);
10730 imm_expr
.X_add_number
&= 0x7ff;
10732 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10733 imm_expr
.X_op
= O_absent
;
10743 /* Args don't match. */
10744 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10745 strcmp (insn
->name
, insn
[1].name
) == 0)
10752 insn_error
= _("illegal operands");
10758 /* This structure holds information we know about a mips16 immediate
10761 struct mips16_immed_operand
10763 /* The type code used in the argument string in the opcode table. */
10765 /* The number of bits in the short form of the opcode. */
10767 /* The number of bits in the extended form of the opcode. */
10769 /* The amount by which the short form is shifted when it is used;
10770 for example, the sw instruction has a shift count of 2. */
10772 /* The amount by which the short form is shifted when it is stored
10773 into the instruction code. */
10775 /* Non-zero if the short form is unsigned. */
10777 /* Non-zero if the extended form is unsigned. */
10779 /* Non-zero if the value is PC relative. */
10783 /* The mips16 immediate operand types. */
10785 static const struct mips16_immed_operand mips16_immed_operands
[] =
10787 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10788 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10789 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10790 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10791 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10792 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10793 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10794 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10795 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10796 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10797 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10798 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10799 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10800 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10801 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10802 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10803 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10804 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10805 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10806 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10807 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10810 #define MIPS16_NUM_IMMED \
10811 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10813 /* Handle a mips16 instruction with an immediate value. This or's the
10814 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10815 whether an extended value is needed; if one is needed, it sets
10816 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10817 If SMALL is true, an unextended opcode was explicitly requested.
10818 If EXT is true, an extended opcode was explicitly requested. If
10819 WARN is true, warn if EXT does not match reality. */
10822 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10823 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10824 unsigned long *insn
, bfd_boolean
*use_extend
,
10825 unsigned short *extend
)
10827 const struct mips16_immed_operand
*op
;
10828 int mintiny
, maxtiny
;
10829 bfd_boolean needext
;
10831 op
= mips16_immed_operands
;
10832 while (op
->type
!= type
)
10835 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10840 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10843 maxtiny
= 1 << op
->nbits
;
10848 maxtiny
= (1 << op
->nbits
) - 1;
10853 mintiny
= - (1 << (op
->nbits
- 1));
10854 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10857 /* Branch offsets have an implicit 0 in the lowest bit. */
10858 if (type
== 'p' || type
== 'q')
10861 if ((val
& ((1 << op
->shift
) - 1)) != 0
10862 || val
< (mintiny
<< op
->shift
)
10863 || val
> (maxtiny
<< op
->shift
))
10868 if (warn
&& ext
&& ! needext
)
10869 as_warn_where (file
, line
,
10870 _("extended operand requested but not required"));
10871 if (small
&& needext
)
10872 as_bad_where (file
, line
, _("invalid unextended operand value"));
10874 if (small
|| (! ext
&& ! needext
))
10878 *use_extend
= FALSE
;
10879 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10880 insnval
<<= op
->op_shift
;
10885 long minext
, maxext
;
10891 maxext
= (1 << op
->extbits
) - 1;
10895 minext
= - (1 << (op
->extbits
- 1));
10896 maxext
= (1 << (op
->extbits
- 1)) - 1;
10898 if (val
< minext
|| val
> maxext
)
10899 as_bad_where (file
, line
,
10900 _("operand value out of range for instruction"));
10902 *use_extend
= TRUE
;
10903 if (op
->extbits
== 16)
10905 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10908 else if (op
->extbits
== 15)
10910 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10915 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10919 *extend
= (unsigned short) extval
;
10924 struct percent_op_match
10927 bfd_reloc_code_real_type reloc
;
10930 static const struct percent_op_match mips_percent_op
[] =
10932 {"%lo", BFD_RELOC_LO16
},
10934 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10935 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10936 {"%call16", BFD_RELOC_MIPS_CALL16
},
10937 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10938 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10939 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10940 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10941 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10942 {"%got", BFD_RELOC_MIPS_GOT16
},
10943 {"%gp_rel", BFD_RELOC_GPREL16
},
10944 {"%half", BFD_RELOC_16
},
10945 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10946 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10947 {"%neg", BFD_RELOC_MIPS_SUB
},
10948 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10949 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10950 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10951 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10952 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10953 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10954 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10956 {"%hi", BFD_RELOC_HI16_S
}
10959 static const struct percent_op_match mips16_percent_op
[] =
10961 {"%lo", BFD_RELOC_MIPS16_LO16
},
10962 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10963 {"%got", BFD_RELOC_MIPS16_GOT16
},
10964 {"%call16", BFD_RELOC_MIPS16_CALL16
},
10965 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10969 /* Return true if *STR points to a relocation operator. When returning true,
10970 move *STR over the operator and store its relocation code in *RELOC.
10971 Leave both *STR and *RELOC alone when returning false. */
10974 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10976 const struct percent_op_match
*percent_op
;
10979 if (mips_opts
.mips16
)
10981 percent_op
= mips16_percent_op
;
10982 limit
= ARRAY_SIZE (mips16_percent_op
);
10986 percent_op
= mips_percent_op
;
10987 limit
= ARRAY_SIZE (mips_percent_op
);
10990 for (i
= 0; i
< limit
; i
++)
10991 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10993 int len
= strlen (percent_op
[i
].str
);
10995 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10998 *str
+= strlen (percent_op
[i
].str
);
10999 *reloc
= percent_op
[i
].reloc
;
11001 /* Check whether the output BFD supports this relocation.
11002 If not, issue an error and fall back on something safe. */
11003 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
11005 as_bad ("relocation %s isn't supported by the current ABI",
11006 percent_op
[i
].str
);
11007 *reloc
= BFD_RELOC_UNUSED
;
11015 /* Parse string STR as a 16-bit relocatable operand. Store the
11016 expression in *EP and the relocations in the array starting
11017 at RELOC. Return the number of relocation operators used.
11019 On exit, EXPR_END points to the first character after the expression. */
11022 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
11025 bfd_reloc_code_real_type reversed_reloc
[3];
11026 size_t reloc_index
, i
;
11027 int crux_depth
, str_depth
;
11030 /* Search for the start of the main expression, recoding relocations
11031 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11032 of the main expression and with CRUX_DEPTH containing the number
11033 of open brackets at that point. */
11040 crux_depth
= str_depth
;
11042 /* Skip over whitespace and brackets, keeping count of the number
11044 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11049 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11050 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11052 my_getExpression (ep
, crux
);
11055 /* Match every open bracket. */
11056 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11060 if (crux_depth
> 0)
11061 as_bad ("unclosed '('");
11065 if (reloc_index
!= 0)
11067 prev_reloc_op_frag
= frag_now
;
11068 for (i
= 0; i
< reloc_index
; i
++)
11069 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11072 return reloc_index
;
11076 my_getExpression (expressionS
*ep
, char *str
)
11081 save_in
= input_line_pointer
;
11082 input_line_pointer
= str
;
11084 expr_end
= input_line_pointer
;
11085 input_line_pointer
= save_in
;
11087 /* If we are in mips16 mode, and this is an expression based on `.',
11088 then we bump the value of the symbol by 1 since that is how other
11089 text symbols are handled. We don't bother to handle complex
11090 expressions, just `.' plus or minus a constant. */
11091 if (mips_opts
.mips16
11092 && ep
->X_op
== O_symbol
11093 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
11094 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
11095 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
11096 && symbol_constant_p (ep
->X_add_symbol
)
11097 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
11098 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
11102 md_atof (int type
, char *litP
, int *sizeP
)
11104 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11108 md_number_to_chars (char *buf
, valueT val
, int n
)
11110 if (target_big_endian
)
11111 number_to_chars_bigendian (buf
, val
, n
);
11113 number_to_chars_littleendian (buf
, val
, n
);
11117 static int support_64bit_objects(void)
11119 const char **list
, **l
;
11122 list
= bfd_target_list ();
11123 for (l
= list
; *l
!= NULL
; l
++)
11125 /* This is traditional mips */
11126 if (strcmp (*l
, "elf64-tradbigmips") == 0
11127 || strcmp (*l
, "elf64-tradlittlemips") == 0)
11129 if (strcmp (*l
, "elf64-bigmips") == 0
11130 || strcmp (*l
, "elf64-littlemips") == 0)
11133 yes
= (*l
!= NULL
);
11137 #endif /* OBJ_ELF */
11139 const char *md_shortopts
= "O::g::G:";
11143 OPTION_MARCH
= OPTION_MD_BASE
,
11165 OPTION_NO_SMARTMIPS
,
11168 OPTION_COMPAT_ARCH_BASE
,
11177 OPTION_M7000_HILO_FIX
,
11178 OPTION_MNO_7000_HILO_FIX
,
11180 OPTION_NO_FIX_VR4120
,
11182 OPTION_NO_FIX_VR4130
,
11189 OPTION_CONSTRUCT_FLOATS
,
11190 OPTION_NO_CONSTRUCT_FLOATS
,
11193 OPTION_RELAX_BRANCH
,
11194 OPTION_NO_RELAX_BRANCH
,
11201 OPTION_SINGLE_FLOAT
,
11202 OPTION_DOUBLE_FLOAT
,
11205 OPTION_CALL_SHARED
,
11206 OPTION_CALL_NONPIC
,
11216 OPTION_MVXWORKS_PIC
,
11217 #endif /* OBJ_ELF */
11221 struct option md_longopts
[] =
11223 /* Options which specify architecture. */
11224 {"march", required_argument
, NULL
, OPTION_MARCH
},
11225 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11226 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11227 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11228 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11229 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11230 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11231 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11232 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11233 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11234 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11235 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11237 /* Options which specify Application Specific Extensions (ASEs). */
11238 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11239 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11240 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11241 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11242 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11243 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11244 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11245 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11246 {"mmt", no_argument
, NULL
, OPTION_MT
},
11247 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11248 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11249 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11250 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11251 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11253 /* Old-style architecture options. Don't add more of these. */
11254 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11255 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11256 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11257 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11258 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11259 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11260 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11261 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11263 /* Options which enable bug fixes. */
11264 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11265 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11266 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11267 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11268 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11269 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11270 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11272 /* Miscellaneous options. */
11273 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11274 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11275 {"break", no_argument
, NULL
, OPTION_BREAK
},
11276 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11277 {"EB", no_argument
, NULL
, OPTION_EB
},
11278 {"EL", no_argument
, NULL
, OPTION_EL
},
11279 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11280 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11281 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11282 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11283 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11284 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11285 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11286 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11287 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11288 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11289 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11290 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11291 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11292 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11293 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11294 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11296 /* Strictly speaking this next option is ELF specific,
11297 but we allow it for other ports as well in order to
11298 make testing easier. */
11299 {"32", no_argument
, NULL
, OPTION_32
},
11301 /* ELF-specific options. */
11303 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11304 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11305 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11306 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11307 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11308 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11309 {"n32", no_argument
, NULL
, OPTION_N32
},
11310 {"64", no_argument
, NULL
, OPTION_64
},
11311 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11312 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11313 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11314 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11315 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11316 #endif /* OBJ_ELF */
11318 {NULL
, no_argument
, NULL
, 0}
11320 size_t md_longopts_size
= sizeof (md_longopts
);
11322 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11323 NEW_VALUE. Warn if another value was already specified. Note:
11324 we have to defer parsing the -march and -mtune arguments in order
11325 to handle 'from-abi' correctly, since the ABI might be specified
11326 in a later argument. */
11329 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11331 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11332 as_warn (_("A different %s was already specified, is now %s"),
11333 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11336 *string_ptr
= new_value
;
11340 md_parse_option (int c
, char *arg
)
11344 case OPTION_CONSTRUCT_FLOATS
:
11345 mips_disable_float_construction
= 0;
11348 case OPTION_NO_CONSTRUCT_FLOATS
:
11349 mips_disable_float_construction
= 1;
11361 target_big_endian
= 1;
11365 target_big_endian
= 0;
11371 else if (arg
[0] == '0')
11373 else if (arg
[0] == '1')
11383 mips_debug
= atoi (arg
);
11387 file_mips_isa
= ISA_MIPS1
;
11391 file_mips_isa
= ISA_MIPS2
;
11395 file_mips_isa
= ISA_MIPS3
;
11399 file_mips_isa
= ISA_MIPS4
;
11403 file_mips_isa
= ISA_MIPS5
;
11406 case OPTION_MIPS32
:
11407 file_mips_isa
= ISA_MIPS32
;
11410 case OPTION_MIPS32R2
:
11411 file_mips_isa
= ISA_MIPS32R2
;
11414 case OPTION_MIPS64R2
:
11415 file_mips_isa
= ISA_MIPS64R2
;
11418 case OPTION_MIPS64
:
11419 file_mips_isa
= ISA_MIPS64
;
11423 mips_set_option_string (&mips_tune_string
, arg
);
11427 mips_set_option_string (&mips_arch_string
, arg
);
11431 mips_set_option_string (&mips_arch_string
, "4650");
11432 mips_set_option_string (&mips_tune_string
, "4650");
11435 case OPTION_NO_M4650
:
11439 mips_set_option_string (&mips_arch_string
, "4010");
11440 mips_set_option_string (&mips_tune_string
, "4010");
11443 case OPTION_NO_M4010
:
11447 mips_set_option_string (&mips_arch_string
, "4100");
11448 mips_set_option_string (&mips_tune_string
, "4100");
11451 case OPTION_NO_M4100
:
11455 mips_set_option_string (&mips_arch_string
, "3900");
11456 mips_set_option_string (&mips_tune_string
, "3900");
11459 case OPTION_NO_M3900
:
11463 mips_opts
.ase_mdmx
= 1;
11466 case OPTION_NO_MDMX
:
11467 mips_opts
.ase_mdmx
= 0;
11471 mips_opts
.ase_dsp
= 1;
11472 mips_opts
.ase_dspr2
= 0;
11475 case OPTION_NO_DSP
:
11476 mips_opts
.ase_dsp
= 0;
11477 mips_opts
.ase_dspr2
= 0;
11481 mips_opts
.ase_dspr2
= 1;
11482 mips_opts
.ase_dsp
= 1;
11485 case OPTION_NO_DSPR2
:
11486 mips_opts
.ase_dspr2
= 0;
11487 mips_opts
.ase_dsp
= 0;
11491 mips_opts
.ase_mt
= 1;
11495 mips_opts
.ase_mt
= 0;
11498 case OPTION_MIPS16
:
11499 mips_opts
.mips16
= 1;
11500 mips_no_prev_insn ();
11503 case OPTION_NO_MIPS16
:
11504 mips_opts
.mips16
= 0;
11505 mips_no_prev_insn ();
11508 case OPTION_MIPS3D
:
11509 mips_opts
.ase_mips3d
= 1;
11512 case OPTION_NO_MIPS3D
:
11513 mips_opts
.ase_mips3d
= 0;
11516 case OPTION_SMARTMIPS
:
11517 mips_opts
.ase_smartmips
= 1;
11520 case OPTION_NO_SMARTMIPS
:
11521 mips_opts
.ase_smartmips
= 0;
11524 case OPTION_FIX_VR4120
:
11525 mips_fix_vr4120
= 1;
11528 case OPTION_NO_FIX_VR4120
:
11529 mips_fix_vr4120
= 0;
11532 case OPTION_FIX_VR4130
:
11533 mips_fix_vr4130
= 1;
11536 case OPTION_NO_FIX_VR4130
:
11537 mips_fix_vr4130
= 0;
11540 case OPTION_RELAX_BRANCH
:
11541 mips_relax_branch
= 1;
11544 case OPTION_NO_RELAX_BRANCH
:
11545 mips_relax_branch
= 0;
11548 case OPTION_MSHARED
:
11549 mips_in_shared
= TRUE
;
11552 case OPTION_MNO_SHARED
:
11553 mips_in_shared
= FALSE
;
11556 case OPTION_MSYM32
:
11557 mips_opts
.sym32
= TRUE
;
11560 case OPTION_MNO_SYM32
:
11561 mips_opts
.sym32
= FALSE
;
11565 /* When generating ELF code, we permit -KPIC and -call_shared to
11566 select SVR4_PIC, and -non_shared to select no PIC. This is
11567 intended to be compatible with Irix 5. */
11568 case OPTION_CALL_SHARED
:
11571 as_bad (_("-call_shared is supported only for ELF format"));
11574 mips_pic
= SVR4_PIC
;
11575 mips_abicalls
= TRUE
;
11578 case OPTION_CALL_NONPIC
:
11581 as_bad (_("-call_nonpic is supported only for ELF format"));
11585 mips_abicalls
= TRUE
;
11588 case OPTION_NON_SHARED
:
11591 as_bad (_("-non_shared is supported only for ELF format"));
11595 mips_abicalls
= FALSE
;
11598 /* The -xgot option tells the assembler to use 32 bit offsets
11599 when accessing the got in SVR4_PIC mode. It is for Irix
11604 #endif /* OBJ_ELF */
11607 g_switch_value
= atoi (arg
);
11611 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11615 mips_abi
= O32_ABI
;
11616 /* We silently ignore -32 for non-ELF targets. This greatly
11617 simplifies the construction of the MIPS GAS test cases. */
11624 as_bad (_("-n32 is supported for ELF format only"));
11627 mips_abi
= N32_ABI
;
11633 as_bad (_("-64 is supported for ELF format only"));
11636 mips_abi
= N64_ABI
;
11637 if (!support_64bit_objects())
11638 as_fatal (_("No compiled in support for 64 bit object file format"));
11640 #endif /* OBJ_ELF */
11643 file_mips_gp32
= 1;
11647 file_mips_gp32
= 0;
11651 file_mips_fp32
= 1;
11655 file_mips_fp32
= 0;
11658 case OPTION_SINGLE_FLOAT
:
11659 file_mips_single_float
= 1;
11662 case OPTION_DOUBLE_FLOAT
:
11663 file_mips_single_float
= 0;
11666 case OPTION_SOFT_FLOAT
:
11667 file_mips_soft_float
= 1;
11670 case OPTION_HARD_FLOAT
:
11671 file_mips_soft_float
= 0;
11678 as_bad (_("-mabi is supported for ELF format only"));
11681 if (strcmp (arg
, "32") == 0)
11682 mips_abi
= O32_ABI
;
11683 else if (strcmp (arg
, "o64") == 0)
11684 mips_abi
= O64_ABI
;
11685 else if (strcmp (arg
, "n32") == 0)
11686 mips_abi
= N32_ABI
;
11687 else if (strcmp (arg
, "64") == 0)
11689 mips_abi
= N64_ABI
;
11690 if (! support_64bit_objects())
11691 as_fatal (_("No compiled in support for 64 bit object file "
11694 else if (strcmp (arg
, "eabi") == 0)
11695 mips_abi
= EABI_ABI
;
11698 as_fatal (_("invalid abi -mabi=%s"), arg
);
11702 #endif /* OBJ_ELF */
11704 case OPTION_M7000_HILO_FIX
:
11705 mips_7000_hilo_fix
= TRUE
;
11708 case OPTION_MNO_7000_HILO_FIX
:
11709 mips_7000_hilo_fix
= FALSE
;
11713 case OPTION_MDEBUG
:
11714 mips_flag_mdebug
= TRUE
;
11717 case OPTION_NO_MDEBUG
:
11718 mips_flag_mdebug
= FALSE
;
11722 mips_flag_pdr
= TRUE
;
11725 case OPTION_NO_PDR
:
11726 mips_flag_pdr
= FALSE
;
11729 case OPTION_MVXWORKS_PIC
:
11730 mips_pic
= VXWORKS_PIC
;
11732 #endif /* OBJ_ELF */
11741 /* Set up globals to generate code for the ISA or processor
11742 described by INFO. */
11745 mips_set_architecture (const struct mips_cpu_info
*info
)
11749 file_mips_arch
= info
->cpu
;
11750 mips_opts
.arch
= info
->cpu
;
11751 mips_opts
.isa
= info
->isa
;
11756 /* Likewise for tuning. */
11759 mips_set_tune (const struct mips_cpu_info
*info
)
11762 mips_tune
= info
->cpu
;
11767 mips_after_parse_args (void)
11769 const struct mips_cpu_info
*arch_info
= 0;
11770 const struct mips_cpu_info
*tune_info
= 0;
11772 /* GP relative stuff not working for PE */
11773 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11775 if (g_switch_seen
&& g_switch_value
!= 0)
11776 as_bad (_("-G not supported in this configuration."));
11777 g_switch_value
= 0;
11780 if (mips_abi
== NO_ABI
)
11781 mips_abi
= MIPS_DEFAULT_ABI
;
11783 /* The following code determines the architecture and register size.
11784 Similar code was added to GCC 3.3 (see override_options() in
11785 config/mips/mips.c). The GAS and GCC code should be kept in sync
11786 as much as possible. */
11788 if (mips_arch_string
!= 0)
11789 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11791 if (file_mips_isa
!= ISA_UNKNOWN
)
11793 /* Handle -mipsN. At this point, file_mips_isa contains the
11794 ISA level specified by -mipsN, while arch_info->isa contains
11795 the -march selection (if any). */
11796 if (arch_info
!= 0)
11798 /* -march takes precedence over -mipsN, since it is more descriptive.
11799 There's no harm in specifying both as long as the ISA levels
11801 if (file_mips_isa
!= arch_info
->isa
)
11802 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11803 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11804 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11807 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11810 if (arch_info
== 0)
11811 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11813 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11814 as_bad ("-march=%s is not compatible with the selected ABI",
11817 mips_set_architecture (arch_info
);
11819 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11820 if (mips_tune_string
!= 0)
11821 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11823 if (tune_info
== 0)
11824 mips_set_tune (arch_info
);
11826 mips_set_tune (tune_info
);
11828 if (file_mips_gp32
>= 0)
11830 /* The user specified the size of the integer registers. Make sure
11831 it agrees with the ABI and ISA. */
11832 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11833 as_bad (_("-mgp64 used with a 32-bit processor"));
11834 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11835 as_bad (_("-mgp32 used with a 64-bit ABI"));
11836 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11837 as_bad (_("-mgp64 used with a 32-bit ABI"));
11841 /* Infer the integer register size from the ABI and processor.
11842 Restrict ourselves to 32-bit registers if that's all the
11843 processor has, or if the ABI cannot handle 64-bit registers. */
11844 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11845 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11848 switch (file_mips_fp32
)
11852 /* No user specified float register size.
11853 ??? GAS treats single-float processors as though they had 64-bit
11854 float registers (although it complains when double-precision
11855 instructions are used). As things stand, saying they have 32-bit
11856 registers would lead to spurious "register must be even" messages.
11857 So here we assume float registers are never smaller than the
11859 if (file_mips_gp32
== 0)
11860 /* 64-bit integer registers implies 64-bit float registers. */
11861 file_mips_fp32
= 0;
11862 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11863 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11864 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11865 file_mips_fp32
= 0;
11867 /* 32-bit float registers. */
11868 file_mips_fp32
= 1;
11871 /* The user specified the size of the float registers. Check if it
11872 agrees with the ABI and ISA. */
11874 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11875 as_bad (_("-mfp64 used with a 32-bit fpu"));
11876 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11877 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11878 as_warn (_("-mfp64 used with a 32-bit ABI"));
11881 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11882 as_warn (_("-mfp32 used with a 64-bit ABI"));
11886 /* End of GCC-shared inference code. */
11888 /* This flag is set when we have a 64-bit capable CPU but use only
11889 32-bit wide registers. Note that EABI does not use it. */
11890 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11891 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11892 || mips_abi
== O32_ABI
))
11893 mips_32bitmode
= 1;
11895 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11896 as_bad (_("trap exception not supported at ISA 1"));
11898 /* If the selected architecture includes support for ASEs, enable
11899 generation of code for them. */
11900 if (mips_opts
.mips16
== -1)
11901 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11902 if (mips_opts
.ase_mips3d
== -1)
11903 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11904 && file_mips_fp32
== 0) ? 1 : 0;
11905 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11906 as_bad (_("-mfp32 used with -mips3d"));
11908 if (mips_opts
.ase_mdmx
== -1)
11909 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11910 && file_mips_fp32
== 0) ? 1 : 0;
11911 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11912 as_bad (_("-mfp32 used with -mdmx"));
11914 if (mips_opts
.ase_smartmips
== -1)
11915 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11916 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11917 as_warn ("%s ISA does not support SmartMIPS",
11918 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11920 if (mips_opts
.ase_dsp
== -1)
11921 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11922 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11923 as_warn ("%s ISA does not support DSP ASE",
11924 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11926 if (mips_opts
.ase_dspr2
== -1)
11928 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11929 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11931 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11932 as_warn ("%s ISA does not support DSP R2 ASE",
11933 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11935 if (mips_opts
.ase_mt
== -1)
11936 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11937 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11938 as_warn ("%s ISA does not support MT ASE",
11939 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11941 file_mips_isa
= mips_opts
.isa
;
11942 file_ase_mips16
= mips_opts
.mips16
;
11943 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11944 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11945 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11946 file_ase_dsp
= mips_opts
.ase_dsp
;
11947 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11948 file_ase_mt
= mips_opts
.ase_mt
;
11949 mips_opts
.gp32
= file_mips_gp32
;
11950 mips_opts
.fp32
= file_mips_fp32
;
11951 mips_opts
.soft_float
= file_mips_soft_float
;
11952 mips_opts
.single_float
= file_mips_single_float
;
11954 if (mips_flag_mdebug
< 0)
11956 #ifdef OBJ_MAYBE_ECOFF
11957 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11958 mips_flag_mdebug
= 1;
11960 #endif /* OBJ_MAYBE_ECOFF */
11961 mips_flag_mdebug
= 0;
11966 mips_init_after_args (void)
11968 /* initialize opcodes */
11969 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11970 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11974 md_pcrel_from (fixS
*fixP
)
11976 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11977 switch (fixP
->fx_r_type
)
11979 case BFD_RELOC_16_PCREL_S2
:
11980 case BFD_RELOC_MIPS_JMP
:
11981 /* Return the address of the delay slot. */
11984 /* We have no relocation type for PC relative MIPS16 instructions. */
11985 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11987 _("PC relative MIPS16 instruction references a different section"));
11992 /* This is called before the symbol table is processed. In order to
11993 work with gcc when using mips-tfile, we must keep all local labels.
11994 However, in other cases, we want to discard them. If we were
11995 called with -g, but we didn't see any debugging information, it may
11996 mean that gcc is smuggling debugging information through to
11997 mips-tfile, in which case we must generate all local labels. */
12000 mips_frob_file_before_adjust (void)
12002 #ifndef NO_ECOFF_DEBUGGING
12003 if (ECOFF_DEBUGGING
12005 && ! ecoff_debugging_seen
)
12006 flag_keep_locals
= 1;
12010 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12011 the corresponding LO16 reloc. This is called before md_apply_fix and
12012 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12013 relocation operators.
12015 For our purposes, a %lo() expression matches a %got() or %hi()
12018 (a) it refers to the same symbol; and
12019 (b) the offset applied in the %lo() expression is no lower than
12020 the offset applied in the %got() or %hi().
12022 (b) allows us to cope with code like:
12025 lh $4,%lo(foo+2)($4)
12027 ...which is legal on RELA targets, and has a well-defined behaviour
12028 if the user knows that adding 2 to "foo" will not induce a carry to
12031 When several %lo()s match a particular %got() or %hi(), we use the
12032 following rules to distinguish them:
12034 (1) %lo()s with smaller offsets are a better match than %lo()s with
12037 (2) %lo()s with no matching %got() or %hi() are better than those
12038 that already have a matching %got() or %hi().
12040 (3) later %lo()s are better than earlier %lo()s.
12042 These rules are applied in order.
12044 (1) means, among other things, that %lo()s with identical offsets are
12045 chosen if they exist.
12047 (2) means that we won't associate several high-part relocations with
12048 the same low-part relocation unless there's no alternative. Having
12049 several high parts for the same low part is a GNU extension; this rule
12050 allows careful users to avoid it.
12052 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12053 with the last high-part relocation being at the front of the list.
12054 It therefore makes sense to choose the last matching low-part
12055 relocation, all other things being equal. It's also easier
12056 to code that way. */
12059 mips_frob_file (void)
12061 struct mips_hi_fixup
*l
;
12062 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12064 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12066 segment_info_type
*seginfo
;
12067 bfd_boolean matched_lo_p
;
12068 fixS
**hi_pos
, **lo_pos
, **pos
;
12070 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12072 /* If a GOT16 relocation turns out to be against a global symbol,
12073 there isn't supposed to be a matching LO. */
12074 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12075 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12078 /* Check quickly whether the next fixup happens to be a matching %lo. */
12079 if (fixup_has_matching_lo_p (l
->fixp
))
12082 seginfo
= seg_info (l
->seg
);
12084 /* Set HI_POS to the position of this relocation in the chain.
12085 Set LO_POS to the position of the chosen low-part relocation.
12086 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12087 relocation that matches an immediately-preceding high-part
12091 matched_lo_p
= FALSE
;
12092 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12094 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12096 if (*pos
== l
->fixp
)
12099 if ((*pos
)->fx_r_type
== looking_for_rtype
12100 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
12101 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12103 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12105 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12108 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12109 && fixup_has_matching_lo_p (*pos
));
12112 /* If we found a match, remove the high-part relocation from its
12113 current position and insert it before the low-part relocation.
12114 Make the offsets match so that fixup_has_matching_lo_p()
12117 We don't warn about unmatched high-part relocations since some
12118 versions of gcc have been known to emit dead "lui ...%hi(...)"
12120 if (lo_pos
!= NULL
)
12122 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12123 if (l
->fixp
->fx_next
!= *lo_pos
)
12125 *hi_pos
= l
->fixp
->fx_next
;
12126 l
->fixp
->fx_next
= *lo_pos
;
12133 /* We may have combined relocations without symbols in the N32/N64 ABI.
12134 We have to prevent gas from dropping them. */
12137 mips_force_relocation (fixS
*fixp
)
12139 if (generic_force_reloc (fixp
))
12143 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12144 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12145 || hi16_reloc_p (fixp
->fx_r_type
)
12146 || lo16_reloc_p (fixp
->fx_r_type
)))
12152 /* Apply a fixup to the object file. */
12155 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12159 reloc_howto_type
*howto
;
12161 /* We ignore generic BFD relocations we don't know about. */
12162 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12166 assert (fixP
->fx_size
== 4
12167 || fixP
->fx_r_type
== BFD_RELOC_16
12168 || fixP
->fx_r_type
== BFD_RELOC_64
12169 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12170 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12171 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12172 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12173 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12175 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12177 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12179 /* Don't treat parts of a composite relocation as done. There are two
12182 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12183 should nevertheless be emitted if the first part is.
12185 (2) In normal usage, composite relocations are never assembly-time
12186 constants. The easiest way of dealing with the pathological
12187 exceptions is to generate a relocation against STN_UNDEF and
12188 leave everything up to the linker. */
12189 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12192 switch (fixP
->fx_r_type
)
12194 case BFD_RELOC_MIPS_TLS_GD
:
12195 case BFD_RELOC_MIPS_TLS_LDM
:
12196 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12197 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12198 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12199 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12200 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12201 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12202 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12203 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12206 case BFD_RELOC_MIPS_JMP
:
12207 case BFD_RELOC_MIPS_SHIFT5
:
12208 case BFD_RELOC_MIPS_SHIFT6
:
12209 case BFD_RELOC_MIPS_GOT_DISP
:
12210 case BFD_RELOC_MIPS_GOT_PAGE
:
12211 case BFD_RELOC_MIPS_GOT_OFST
:
12212 case BFD_RELOC_MIPS_SUB
:
12213 case BFD_RELOC_MIPS_INSERT_A
:
12214 case BFD_RELOC_MIPS_INSERT_B
:
12215 case BFD_RELOC_MIPS_DELETE
:
12216 case BFD_RELOC_MIPS_HIGHEST
:
12217 case BFD_RELOC_MIPS_HIGHER
:
12218 case BFD_RELOC_MIPS_SCN_DISP
:
12219 case BFD_RELOC_MIPS_REL16
:
12220 case BFD_RELOC_MIPS_RELGOT
:
12221 case BFD_RELOC_MIPS_JALR
:
12222 case BFD_RELOC_HI16
:
12223 case BFD_RELOC_HI16_S
:
12224 case BFD_RELOC_GPREL16
:
12225 case BFD_RELOC_MIPS_LITERAL
:
12226 case BFD_RELOC_MIPS_CALL16
:
12227 case BFD_RELOC_MIPS_GOT16
:
12228 case BFD_RELOC_GPREL32
:
12229 case BFD_RELOC_MIPS_GOT_HI16
:
12230 case BFD_RELOC_MIPS_GOT_LO16
:
12231 case BFD_RELOC_MIPS_CALL_HI16
:
12232 case BFD_RELOC_MIPS_CALL_LO16
:
12233 case BFD_RELOC_MIPS16_GPREL
:
12234 case BFD_RELOC_MIPS16_GOT16
:
12235 case BFD_RELOC_MIPS16_CALL16
:
12236 case BFD_RELOC_MIPS16_HI16
:
12237 case BFD_RELOC_MIPS16_HI16_S
:
12238 case BFD_RELOC_MIPS16_JMP
:
12239 /* Nothing needed to do. The value comes from the reloc entry. */
12243 /* This is handled like BFD_RELOC_32, but we output a sign
12244 extended value if we are only 32 bits. */
12247 if (8 <= sizeof (valueT
))
12248 md_number_to_chars ((char *) buf
, *valP
, 8);
12253 if ((*valP
& 0x80000000) != 0)
12257 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12259 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12265 case BFD_RELOC_RVA
:
12268 /* If we are deleting this reloc entry, we must fill in the
12269 value now. This can happen if we have a .word which is not
12270 resolved when it appears but is later defined. */
12272 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12275 case BFD_RELOC_LO16
:
12276 case BFD_RELOC_MIPS16_LO16
:
12277 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12278 may be safe to remove, but if so it's not obvious. */
12279 /* When handling an embedded PIC switch statement, we can wind
12280 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12283 if (*valP
+ 0x8000 > 0xffff)
12284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12285 _("relocation overflow"));
12286 if (target_big_endian
)
12288 md_number_to_chars ((char *) buf
, *valP
, 2);
12292 case BFD_RELOC_16_PCREL_S2
:
12293 if ((*valP
& 0x3) != 0)
12294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12295 _("Branch to misaligned address (%lx)"), (long) *valP
);
12297 /* We need to save the bits in the instruction since fixup_segment()
12298 might be deleting the relocation entry (i.e., a branch within
12299 the current segment). */
12300 if (! fixP
->fx_done
)
12303 /* Update old instruction data. */
12304 if (target_big_endian
)
12305 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12307 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12309 if (*valP
+ 0x20000 <= 0x3ffff)
12311 insn
|= (*valP
>> 2) & 0xffff;
12312 md_number_to_chars ((char *) buf
, insn
, 4);
12314 else if (mips_pic
== NO_PIC
12316 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12317 && (fixP
->fx_frag
->fr_address
12318 < text_section
->vma
+ bfd_get_section_size (text_section
))
12319 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12320 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12321 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12323 /* The branch offset is too large. If this is an
12324 unconditional branch, and we are not generating PIC code,
12325 we can convert it to an absolute jump instruction. */
12326 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12327 insn
= 0x0c000000; /* jal */
12329 insn
= 0x08000000; /* j */
12330 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12332 fixP
->fx_addsy
= section_symbol (text_section
);
12333 *valP
+= md_pcrel_from (fixP
);
12334 md_number_to_chars ((char *) buf
, insn
, 4);
12338 /* If we got here, we have branch-relaxation disabled,
12339 and there's nothing we can do to fix this instruction
12340 without turning it into a longer sequence. */
12341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12342 _("Branch out of range"));
12346 case BFD_RELOC_VTABLE_INHERIT
:
12349 && !S_IS_DEFINED (fixP
->fx_addsy
)
12350 && !S_IS_WEAK (fixP
->fx_addsy
))
12351 S_SET_WEAK (fixP
->fx_addsy
);
12354 case BFD_RELOC_VTABLE_ENTRY
:
12362 /* Remember value for tc_gen_reloc. */
12363 fixP
->fx_addnumber
= *valP
;
12373 name
= input_line_pointer
;
12374 c
= get_symbol_end ();
12375 p
= (symbolS
*) symbol_find_or_make (name
);
12376 *input_line_pointer
= c
;
12380 /* Align the current frag to a given power of two. If a particular
12381 fill byte should be used, FILL points to an integer that contains
12382 that byte, otherwise FILL is null.
12384 The MIPS assembler also automatically adjusts any preceding
12388 mips_align (int to
, int *fill
, symbolS
*label
)
12390 mips_emit_delays ();
12391 mips_record_mips16_mode ();
12392 if (fill
== NULL
&& subseg_text_p (now_seg
))
12393 frag_align_code (to
, 0);
12395 frag_align (to
, fill
? *fill
: 0, 0);
12396 record_alignment (now_seg
, to
);
12399 assert (S_GET_SEGMENT (label
) == now_seg
);
12400 symbol_set_frag (label
, frag_now
);
12401 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12405 /* Align to a given power of two. .align 0 turns off the automatic
12406 alignment used by the data creating pseudo-ops. */
12409 s_align (int x ATTRIBUTE_UNUSED
)
12411 int temp
, fill_value
, *fill_ptr
;
12412 long max_alignment
= 28;
12414 /* o Note that the assembler pulls down any immediately preceding label
12415 to the aligned address.
12416 o It's not documented but auto alignment is reinstated by
12417 a .align pseudo instruction.
12418 o Note also that after auto alignment is turned off the mips assembler
12419 issues an error on attempt to assemble an improperly aligned data item.
12422 temp
= get_absolute_expression ();
12423 if (temp
> max_alignment
)
12424 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12427 as_warn (_("Alignment negative: 0 assumed."));
12430 if (*input_line_pointer
== ',')
12432 ++input_line_pointer
;
12433 fill_value
= get_absolute_expression ();
12434 fill_ptr
= &fill_value
;
12440 segment_info_type
*si
= seg_info (now_seg
);
12441 struct insn_label_list
*l
= si
->label_list
;
12442 /* Auto alignment should be switched on by next section change. */
12444 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12451 demand_empty_rest_of_line ();
12455 s_change_sec (int sec
)
12460 /* The ELF backend needs to know that we are changing sections, so
12461 that .previous works correctly. We could do something like check
12462 for an obj_section_change_hook macro, but that might be confusing
12463 as it would not be appropriate to use it in the section changing
12464 functions in read.c, since obj-elf.c intercepts those. FIXME:
12465 This should be cleaner, somehow. */
12467 obj_elf_section_change_hook ();
12470 mips_emit_delays ();
12480 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12481 demand_empty_rest_of_line ();
12485 seg
= subseg_new (RDATA_SECTION_NAME
,
12486 (subsegT
) get_absolute_expression ());
12489 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12490 | SEC_READONLY
| SEC_RELOC
12492 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12493 record_alignment (seg
, 4);
12495 demand_empty_rest_of_line ();
12499 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12502 bfd_set_section_flags (stdoutput
, seg
,
12503 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12504 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12505 record_alignment (seg
, 4);
12507 demand_empty_rest_of_line ();
12515 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12518 char *section_name
;
12523 int section_entry_size
;
12524 int section_alignment
;
12529 section_name
= input_line_pointer
;
12530 c
= get_symbol_end ();
12532 next_c
= *(input_line_pointer
+ 1);
12534 /* Do we have .section Name<,"flags">? */
12535 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12537 /* just after name is now '\0'. */
12538 *input_line_pointer
= c
;
12539 input_line_pointer
= section_name
;
12540 obj_elf_section (ignore
);
12543 input_line_pointer
++;
12545 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12547 section_type
= get_absolute_expression ();
12550 if (*input_line_pointer
++ == ',')
12551 section_flag
= get_absolute_expression ();
12554 if (*input_line_pointer
++ == ',')
12555 section_entry_size
= get_absolute_expression ();
12557 section_entry_size
= 0;
12558 if (*input_line_pointer
++ == ',')
12559 section_alignment
= get_absolute_expression ();
12561 section_alignment
= 0;
12563 section_name
= xstrdup (section_name
);
12565 /* When using the generic form of .section (as implemented by obj-elf.c),
12566 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12567 traditionally had to fall back on the more common @progbits instead.
12569 There's nothing really harmful in this, since bfd will correct
12570 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12571 means that, for backwards compatibility, the special_section entries
12572 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12574 Even so, we shouldn't force users of the MIPS .section syntax to
12575 incorrectly label the sections as SHT_PROGBITS. The best compromise
12576 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12577 generic type-checking code. */
12578 if (section_type
== SHT_MIPS_DWARF
)
12579 section_type
= SHT_PROGBITS
;
12581 obj_elf_change_section (section_name
, section_type
, section_flag
,
12582 section_entry_size
, 0, 0, 0);
12584 if (now_seg
->name
!= section_name
)
12585 free (section_name
);
12586 #endif /* OBJ_ELF */
12590 mips_enable_auto_align (void)
12596 s_cons (int log_size
)
12598 segment_info_type
*si
= seg_info (now_seg
);
12599 struct insn_label_list
*l
= si
->label_list
;
12602 label
= l
!= NULL
? l
->label
: NULL
;
12603 mips_emit_delays ();
12604 if (log_size
> 0 && auto_align
)
12605 mips_align (log_size
, 0, label
);
12606 mips_clear_insn_labels ();
12607 cons (1 << log_size
);
12611 s_float_cons (int type
)
12613 segment_info_type
*si
= seg_info (now_seg
);
12614 struct insn_label_list
*l
= si
->label_list
;
12617 label
= l
!= NULL
? l
->label
: NULL
;
12619 mips_emit_delays ();
12624 mips_align (3, 0, label
);
12626 mips_align (2, 0, label
);
12629 mips_clear_insn_labels ();
12634 /* Handle .globl. We need to override it because on Irix 5 you are
12637 where foo is an undefined symbol, to mean that foo should be
12638 considered to be the address of a function. */
12641 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12650 name
= input_line_pointer
;
12651 c
= get_symbol_end ();
12652 symbolP
= symbol_find_or_make (name
);
12653 S_SET_EXTERNAL (symbolP
);
12655 *input_line_pointer
= c
;
12656 SKIP_WHITESPACE ();
12658 /* On Irix 5, every global symbol that is not explicitly labelled as
12659 being a function is apparently labelled as being an object. */
12662 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12663 && (*input_line_pointer
!= ','))
12668 secname
= input_line_pointer
;
12669 c
= get_symbol_end ();
12670 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12672 as_bad (_("%s: no such section"), secname
);
12673 *input_line_pointer
= c
;
12675 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12676 flag
= BSF_FUNCTION
;
12679 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12681 c
= *input_line_pointer
;
12684 input_line_pointer
++;
12685 SKIP_WHITESPACE ();
12686 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12692 demand_empty_rest_of_line ();
12696 s_option (int x ATTRIBUTE_UNUSED
)
12701 opt
= input_line_pointer
;
12702 c
= get_symbol_end ();
12706 /* FIXME: What does this mean? */
12708 else if (strncmp (opt
, "pic", 3) == 0)
12712 i
= atoi (opt
+ 3);
12717 mips_pic
= SVR4_PIC
;
12718 mips_abicalls
= TRUE
;
12721 as_bad (_(".option pic%d not supported"), i
);
12723 if (mips_pic
== SVR4_PIC
)
12725 if (g_switch_seen
&& g_switch_value
!= 0)
12726 as_warn (_("-G may not be used with SVR4 PIC code"));
12727 g_switch_value
= 0;
12728 bfd_set_gp_size (stdoutput
, 0);
12732 as_warn (_("Unrecognized option \"%s\""), opt
);
12734 *input_line_pointer
= c
;
12735 demand_empty_rest_of_line ();
12738 /* This structure is used to hold a stack of .set values. */
12740 struct mips_option_stack
12742 struct mips_option_stack
*next
;
12743 struct mips_set_options options
;
12746 static struct mips_option_stack
*mips_opts_stack
;
12748 /* Handle the .set pseudo-op. */
12751 s_mipsset (int x ATTRIBUTE_UNUSED
)
12753 char *name
= input_line_pointer
, ch
;
12755 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12756 ++input_line_pointer
;
12757 ch
= *input_line_pointer
;
12758 *input_line_pointer
= '\0';
12760 if (strcmp (name
, "reorder") == 0)
12762 if (mips_opts
.noreorder
)
12765 else if (strcmp (name
, "noreorder") == 0)
12767 if (!mips_opts
.noreorder
)
12768 start_noreorder ();
12770 else if (strncmp (name
, "at=", 3) == 0)
12772 char *s
= name
+ 3;
12774 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12775 as_bad (_("Unrecognized register name `%s'"), s
);
12777 else if (strcmp (name
, "at") == 0)
12779 mips_opts
.at
= ATREG
;
12781 else if (strcmp (name
, "noat") == 0)
12783 mips_opts
.at
= ZERO
;
12785 else if (strcmp (name
, "macro") == 0)
12787 mips_opts
.warn_about_macros
= 0;
12789 else if (strcmp (name
, "nomacro") == 0)
12791 if (mips_opts
.noreorder
== 0)
12792 as_bad (_("`noreorder' must be set before `nomacro'"));
12793 mips_opts
.warn_about_macros
= 1;
12795 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12797 mips_opts
.nomove
= 0;
12799 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12801 mips_opts
.nomove
= 1;
12803 else if (strcmp (name
, "bopt") == 0)
12805 mips_opts
.nobopt
= 0;
12807 else if (strcmp (name
, "nobopt") == 0)
12809 mips_opts
.nobopt
= 1;
12811 else if (strcmp (name
, "gp=default") == 0)
12812 mips_opts
.gp32
= file_mips_gp32
;
12813 else if (strcmp (name
, "gp=32") == 0)
12814 mips_opts
.gp32
= 1;
12815 else if (strcmp (name
, "gp=64") == 0)
12817 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12818 as_warn ("%s isa does not support 64-bit registers",
12819 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12820 mips_opts
.gp32
= 0;
12822 else if (strcmp (name
, "fp=default") == 0)
12823 mips_opts
.fp32
= file_mips_fp32
;
12824 else if (strcmp (name
, "fp=32") == 0)
12825 mips_opts
.fp32
= 1;
12826 else if (strcmp (name
, "fp=64") == 0)
12828 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12829 as_warn ("%s isa does not support 64-bit floating point registers",
12830 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12831 mips_opts
.fp32
= 0;
12833 else if (strcmp (name
, "softfloat") == 0)
12834 mips_opts
.soft_float
= 1;
12835 else if (strcmp (name
, "hardfloat") == 0)
12836 mips_opts
.soft_float
= 0;
12837 else if (strcmp (name
, "singlefloat") == 0)
12838 mips_opts
.single_float
= 1;
12839 else if (strcmp (name
, "doublefloat") == 0)
12840 mips_opts
.single_float
= 0;
12841 else if (strcmp (name
, "mips16") == 0
12842 || strcmp (name
, "MIPS-16") == 0)
12843 mips_opts
.mips16
= 1;
12844 else if (strcmp (name
, "nomips16") == 0
12845 || strcmp (name
, "noMIPS-16") == 0)
12846 mips_opts
.mips16
= 0;
12847 else if (strcmp (name
, "smartmips") == 0)
12849 if (!ISA_SUPPORTS_SMARTMIPS
)
12850 as_warn ("%s ISA does not support SmartMIPS ASE",
12851 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12852 mips_opts
.ase_smartmips
= 1;
12854 else if (strcmp (name
, "nosmartmips") == 0)
12855 mips_opts
.ase_smartmips
= 0;
12856 else if (strcmp (name
, "mips3d") == 0)
12857 mips_opts
.ase_mips3d
= 1;
12858 else if (strcmp (name
, "nomips3d") == 0)
12859 mips_opts
.ase_mips3d
= 0;
12860 else if (strcmp (name
, "mdmx") == 0)
12861 mips_opts
.ase_mdmx
= 1;
12862 else if (strcmp (name
, "nomdmx") == 0)
12863 mips_opts
.ase_mdmx
= 0;
12864 else if (strcmp (name
, "dsp") == 0)
12866 if (!ISA_SUPPORTS_DSP_ASE
)
12867 as_warn ("%s ISA does not support DSP ASE",
12868 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12869 mips_opts
.ase_dsp
= 1;
12870 mips_opts
.ase_dspr2
= 0;
12872 else if (strcmp (name
, "nodsp") == 0)
12874 mips_opts
.ase_dsp
= 0;
12875 mips_opts
.ase_dspr2
= 0;
12877 else if (strcmp (name
, "dspr2") == 0)
12879 if (!ISA_SUPPORTS_DSPR2_ASE
)
12880 as_warn ("%s ISA does not support DSP R2 ASE",
12881 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12882 mips_opts
.ase_dspr2
= 1;
12883 mips_opts
.ase_dsp
= 1;
12885 else if (strcmp (name
, "nodspr2") == 0)
12887 mips_opts
.ase_dspr2
= 0;
12888 mips_opts
.ase_dsp
= 0;
12890 else if (strcmp (name
, "mt") == 0)
12892 if (!ISA_SUPPORTS_MT_ASE
)
12893 as_warn ("%s ISA does not support MT ASE",
12894 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12895 mips_opts
.ase_mt
= 1;
12897 else if (strcmp (name
, "nomt") == 0)
12898 mips_opts
.ase_mt
= 0;
12899 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12903 /* Permit the user to change the ISA and architecture on the fly.
12904 Needless to say, misuse can cause serious problems. */
12905 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12908 mips_opts
.isa
= file_mips_isa
;
12909 mips_opts
.arch
= file_mips_arch
;
12911 else if (strncmp (name
, "arch=", 5) == 0)
12913 const struct mips_cpu_info
*p
;
12915 p
= mips_parse_cpu("internal use", name
+ 5);
12917 as_bad (_("unknown architecture %s"), name
+ 5);
12920 mips_opts
.arch
= p
->cpu
;
12921 mips_opts
.isa
= p
->isa
;
12924 else if (strncmp (name
, "mips", 4) == 0)
12926 const struct mips_cpu_info
*p
;
12928 p
= mips_parse_cpu("internal use", name
);
12930 as_bad (_("unknown ISA level %s"), name
+ 4);
12933 mips_opts
.arch
= p
->cpu
;
12934 mips_opts
.isa
= p
->isa
;
12938 as_bad (_("unknown ISA or architecture %s"), name
);
12940 switch (mips_opts
.isa
)
12948 mips_opts
.gp32
= 1;
12949 mips_opts
.fp32
= 1;
12956 mips_opts
.gp32
= 0;
12957 mips_opts
.fp32
= 0;
12960 as_bad (_("unknown ISA level %s"), name
+ 4);
12965 mips_opts
.gp32
= file_mips_gp32
;
12966 mips_opts
.fp32
= file_mips_fp32
;
12969 else if (strcmp (name
, "autoextend") == 0)
12970 mips_opts
.noautoextend
= 0;
12971 else if (strcmp (name
, "noautoextend") == 0)
12972 mips_opts
.noautoextend
= 1;
12973 else if (strcmp (name
, "push") == 0)
12975 struct mips_option_stack
*s
;
12977 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12978 s
->next
= mips_opts_stack
;
12979 s
->options
= mips_opts
;
12980 mips_opts_stack
= s
;
12982 else if (strcmp (name
, "pop") == 0)
12984 struct mips_option_stack
*s
;
12986 s
= mips_opts_stack
;
12988 as_bad (_(".set pop with no .set push"));
12991 /* If we're changing the reorder mode we need to handle
12992 delay slots correctly. */
12993 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12994 start_noreorder ();
12995 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12998 mips_opts
= s
->options
;
12999 mips_opts_stack
= s
->next
;
13003 else if (strcmp (name
, "sym32") == 0)
13004 mips_opts
.sym32
= TRUE
;
13005 else if (strcmp (name
, "nosym32") == 0)
13006 mips_opts
.sym32
= FALSE
;
13007 else if (strchr (name
, ','))
13009 /* Generic ".set" directive; use the generic handler. */
13010 *input_line_pointer
= ch
;
13011 input_line_pointer
= name
;
13017 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
13019 *input_line_pointer
= ch
;
13020 demand_empty_rest_of_line ();
13023 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13024 .option pic2. It means to generate SVR4 PIC calls. */
13027 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
13029 mips_pic
= SVR4_PIC
;
13030 mips_abicalls
= TRUE
;
13032 if (g_switch_seen
&& g_switch_value
!= 0)
13033 as_warn (_("-G may not be used with SVR4 PIC code"));
13034 g_switch_value
= 0;
13036 bfd_set_gp_size (stdoutput
, 0);
13037 demand_empty_rest_of_line ();
13040 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13041 PIC code. It sets the $gp register for the function based on the
13042 function address, which is in the register named in the argument.
13043 This uses a relocation against _gp_disp, which is handled specially
13044 by the linker. The result is:
13045 lui $gp,%hi(_gp_disp)
13046 addiu $gp,$gp,%lo(_gp_disp)
13047 addu $gp,$gp,.cpload argument
13048 The .cpload argument is normally $25 == $t9.
13050 The -mno-shared option changes this to:
13051 lui $gp,%hi(__gnu_local_gp)
13052 addiu $gp,$gp,%lo(__gnu_local_gp)
13053 and the argument is ignored. This saves an instruction, but the
13054 resulting code is not position independent; it uses an absolute
13055 address for __gnu_local_gp. Thus code assembled with -mno-shared
13056 can go into an ordinary executable, but not into a shared library. */
13059 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13065 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13066 .cpload is ignored. */
13067 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13073 /* .cpload should be in a .set noreorder section. */
13074 if (mips_opts
.noreorder
== 0)
13075 as_warn (_(".cpload not in noreorder section"));
13077 reg
= tc_get_register (0);
13079 /* If we need to produce a 64-bit address, we are better off using
13080 the default instruction sequence. */
13081 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13083 ex
.X_op
= O_symbol
;
13084 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13086 ex
.X_op_symbol
= NULL
;
13087 ex
.X_add_number
= 0;
13089 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13090 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13093 macro_build_lui (&ex
, mips_gp_register
);
13094 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13095 mips_gp_register
, BFD_RELOC_LO16
);
13097 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13098 mips_gp_register
, reg
);
13101 demand_empty_rest_of_line ();
13104 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13105 .cpsetup $reg1, offset|$reg2, label
13107 If offset is given, this results in:
13108 sd $gp, offset($sp)
13109 lui $gp, %hi(%neg(%gp_rel(label)))
13110 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13111 daddu $gp, $gp, $reg1
13113 If $reg2 is given, this results in:
13114 daddu $reg2, $gp, $0
13115 lui $gp, %hi(%neg(%gp_rel(label)))
13116 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13117 daddu $gp, $gp, $reg1
13118 $reg1 is normally $25 == $t9.
13120 The -mno-shared option replaces the last three instructions with
13122 addiu $gp,$gp,%lo(_gp) */
13125 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13127 expressionS ex_off
;
13128 expressionS ex_sym
;
13131 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13132 We also need NewABI support. */
13133 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13139 reg1
= tc_get_register (0);
13140 SKIP_WHITESPACE ();
13141 if (*input_line_pointer
!= ',')
13143 as_bad (_("missing argument separator ',' for .cpsetup"));
13147 ++input_line_pointer
;
13148 SKIP_WHITESPACE ();
13149 if (*input_line_pointer
== '$')
13151 mips_cpreturn_register
= tc_get_register (0);
13152 mips_cpreturn_offset
= -1;
13156 mips_cpreturn_offset
= get_absolute_expression ();
13157 mips_cpreturn_register
= -1;
13159 SKIP_WHITESPACE ();
13160 if (*input_line_pointer
!= ',')
13162 as_bad (_("missing argument separator ',' for .cpsetup"));
13166 ++input_line_pointer
;
13167 SKIP_WHITESPACE ();
13168 expression (&ex_sym
);
13171 if (mips_cpreturn_register
== -1)
13173 ex_off
.X_op
= O_constant
;
13174 ex_off
.X_add_symbol
= NULL
;
13175 ex_off
.X_op_symbol
= NULL
;
13176 ex_off
.X_add_number
= mips_cpreturn_offset
;
13178 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13179 BFD_RELOC_LO16
, SP
);
13182 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13183 mips_gp_register
, 0);
13185 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13187 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13188 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13191 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13192 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13193 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13195 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13196 mips_gp_register
, reg1
);
13202 ex
.X_op
= O_symbol
;
13203 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13204 ex
.X_op_symbol
= NULL
;
13205 ex
.X_add_number
= 0;
13207 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13208 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13210 macro_build_lui (&ex
, mips_gp_register
);
13211 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13212 mips_gp_register
, BFD_RELOC_LO16
);
13217 demand_empty_rest_of_line ();
13221 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13223 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13224 .cplocal is ignored. */
13225 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13231 mips_gp_register
= tc_get_register (0);
13232 demand_empty_rest_of_line ();
13235 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13236 offset from $sp. The offset is remembered, and after making a PIC
13237 call $gp is restored from that location. */
13240 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13244 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13245 .cprestore is ignored. */
13246 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13252 mips_cprestore_offset
= get_absolute_expression ();
13253 mips_cprestore_valid
= 1;
13255 ex
.X_op
= O_constant
;
13256 ex
.X_add_symbol
= NULL
;
13257 ex
.X_op_symbol
= NULL
;
13258 ex
.X_add_number
= mips_cprestore_offset
;
13261 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13262 SP
, HAVE_64BIT_ADDRESSES
);
13265 demand_empty_rest_of_line ();
13268 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13269 was given in the preceding .cpsetup, it results in:
13270 ld $gp, offset($sp)
13272 If a register $reg2 was given there, it results in:
13273 daddu $gp, $reg2, $0 */
13276 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13280 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13281 We also need NewABI support. */
13282 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13289 if (mips_cpreturn_register
== -1)
13291 ex
.X_op
= O_constant
;
13292 ex
.X_add_symbol
= NULL
;
13293 ex
.X_op_symbol
= NULL
;
13294 ex
.X_add_number
= mips_cpreturn_offset
;
13296 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13299 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13300 mips_cpreturn_register
, 0);
13303 demand_empty_rest_of_line ();
13306 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13307 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13308 use in DWARF debug information. */
13311 s_dtprel_internal (size_t bytes
)
13318 if (ex
.X_op
!= O_symbol
)
13320 as_bad (_("Unsupported use of %s"), (bytes
== 8
13323 ignore_rest_of_line ();
13326 p
= frag_more (bytes
);
13327 md_number_to_chars (p
, 0, bytes
);
13328 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13330 ? BFD_RELOC_MIPS_TLS_DTPREL64
13331 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13333 demand_empty_rest_of_line ();
13336 /* Handle .dtprelword. */
13339 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13341 s_dtprel_internal (4);
13344 /* Handle .dtpreldword. */
13347 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13349 s_dtprel_internal (8);
13352 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13353 code. It sets the offset to use in gp_rel relocations. */
13356 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13358 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13359 We also need NewABI support. */
13360 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13366 mips_gprel_offset
= get_absolute_expression ();
13368 demand_empty_rest_of_line ();
13371 /* Handle the .gpword pseudo-op. This is used when generating PIC
13372 code. It generates a 32 bit GP relative reloc. */
13375 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13377 segment_info_type
*si
;
13378 struct insn_label_list
*l
;
13383 /* When not generating PIC code, this is treated as .word. */
13384 if (mips_pic
!= SVR4_PIC
)
13390 si
= seg_info (now_seg
);
13391 l
= si
->label_list
;
13392 label
= l
!= NULL
? l
->label
: NULL
;
13393 mips_emit_delays ();
13395 mips_align (2, 0, label
);
13396 mips_clear_insn_labels ();
13400 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13402 as_bad (_("Unsupported use of .gpword"));
13403 ignore_rest_of_line ();
13407 md_number_to_chars (p
, 0, 4);
13408 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13409 BFD_RELOC_GPREL32
);
13411 demand_empty_rest_of_line ();
13415 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13417 segment_info_type
*si
;
13418 struct insn_label_list
*l
;
13423 /* When not generating PIC code, this is treated as .dword. */
13424 if (mips_pic
!= SVR4_PIC
)
13430 si
= seg_info (now_seg
);
13431 l
= si
->label_list
;
13432 label
= l
!= NULL
? l
->label
: NULL
;
13433 mips_emit_delays ();
13435 mips_align (3, 0, label
);
13436 mips_clear_insn_labels ();
13440 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13442 as_bad (_("Unsupported use of .gpdword"));
13443 ignore_rest_of_line ();
13447 md_number_to_chars (p
, 0, 8);
13448 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13449 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13451 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13452 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13453 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13455 demand_empty_rest_of_line ();
13458 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13459 tables in SVR4 PIC code. */
13462 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13466 /* This is ignored when not generating SVR4 PIC code. */
13467 if (mips_pic
!= SVR4_PIC
)
13473 /* Add $gp to the register named as an argument. */
13475 reg
= tc_get_register (0);
13476 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13479 demand_empty_rest_of_line ();
13482 /* Handle the .insn pseudo-op. This marks instruction labels in
13483 mips16 mode. This permits the linker to handle them specially,
13484 such as generating jalx instructions when needed. We also make
13485 them odd for the duration of the assembly, in order to generate the
13486 right sort of code. We will make them even in the adjust_symtab
13487 routine, while leaving them marked. This is convenient for the
13488 debugger and the disassembler. The linker knows to make them odd
13492 s_insn (int ignore ATTRIBUTE_UNUSED
)
13494 mips16_mark_labels ();
13496 demand_empty_rest_of_line ();
13499 /* Handle a .stabn directive. We need these in order to mark a label
13500 as being a mips16 text label correctly. Sometimes the compiler
13501 will emit a label, followed by a .stabn, and then switch sections.
13502 If the label and .stabn are in mips16 mode, then the label is
13503 really a mips16 text label. */
13506 s_mips_stab (int type
)
13509 mips16_mark_labels ();
13514 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13517 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13524 name
= input_line_pointer
;
13525 c
= get_symbol_end ();
13526 symbolP
= symbol_find_or_make (name
);
13527 S_SET_WEAK (symbolP
);
13528 *input_line_pointer
= c
;
13530 SKIP_WHITESPACE ();
13532 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13534 if (S_IS_DEFINED (symbolP
))
13536 as_bad ("ignoring attempt to redefine symbol %s",
13537 S_GET_NAME (symbolP
));
13538 ignore_rest_of_line ();
13542 if (*input_line_pointer
== ',')
13544 ++input_line_pointer
;
13545 SKIP_WHITESPACE ();
13549 if (exp
.X_op
!= O_symbol
)
13551 as_bad ("bad .weakext directive");
13552 ignore_rest_of_line ();
13555 symbol_set_value_expression (symbolP
, &exp
);
13558 demand_empty_rest_of_line ();
13561 /* Parse a register string into a number. Called from the ECOFF code
13562 to parse .frame. The argument is non-zero if this is the frame
13563 register, so that we can record it in mips_frame_reg. */
13566 tc_get_register (int frame
)
13570 SKIP_WHITESPACE ();
13571 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13575 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13576 mips_frame_reg_valid
= 1;
13577 mips_cprestore_valid
= 0;
13583 md_section_align (asection
*seg
, valueT addr
)
13585 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13589 /* We don't need to align ELF sections to the full alignment.
13590 However, Irix 5 may prefer that we align them at least to a 16
13591 byte boundary. We don't bother to align the sections if we
13592 are targeted for an embedded system. */
13593 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13599 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13602 /* Utility routine, called from above as well. If called while the
13603 input file is still being read, it's only an approximation. (For
13604 example, a symbol may later become defined which appeared to be
13605 undefined earlier.) */
13608 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13613 if (g_switch_value
> 0)
13615 const char *symname
;
13618 /* Find out whether this symbol can be referenced off the $gp
13619 register. It can be if it is smaller than the -G size or if
13620 it is in the .sdata or .sbss section. Certain symbols can
13621 not be referenced off the $gp, although it appears as though
13623 symname
= S_GET_NAME (sym
);
13624 if (symname
!= (const char *) NULL
13625 && (strcmp (symname
, "eprol") == 0
13626 || strcmp (symname
, "etext") == 0
13627 || strcmp (symname
, "_gp") == 0
13628 || strcmp (symname
, "edata") == 0
13629 || strcmp (symname
, "_fbss") == 0
13630 || strcmp (symname
, "_fdata") == 0
13631 || strcmp (symname
, "_ftext") == 0
13632 || strcmp (symname
, "end") == 0
13633 || strcmp (symname
, "_gp_disp") == 0))
13635 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13637 #ifndef NO_ECOFF_DEBUGGING
13638 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13639 && (symbol_get_obj (sym
)->ecoff_extern_size
13640 <= g_switch_value
))
13642 /* We must defer this decision until after the whole
13643 file has been read, since there might be a .extern
13644 after the first use of this symbol. */
13645 || (before_relaxing
13646 #ifndef NO_ECOFF_DEBUGGING
13647 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13649 && S_GET_VALUE (sym
) == 0)
13650 || (S_GET_VALUE (sym
) != 0
13651 && S_GET_VALUE (sym
) <= g_switch_value
)))
13655 const char *segname
;
13657 segname
= segment_name (S_GET_SEGMENT (sym
));
13658 assert (strcmp (segname
, ".lit8") != 0
13659 && strcmp (segname
, ".lit4") != 0);
13660 change
= (strcmp (segname
, ".sdata") != 0
13661 && strcmp (segname
, ".sbss") != 0
13662 && strncmp (segname
, ".sdata.", 7) != 0
13663 && strncmp (segname
, ".sbss.", 6) != 0
13664 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13665 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13670 /* We are not optimizing for the $gp register. */
13675 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13678 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13682 /* Handle the case of a symbol equated to another symbol. */
13683 while (symbol_equated_reloc_p (sym
))
13687 /* It's possible to get a loop here in a badly written program. */
13688 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13694 if (symbol_section_p (sym
))
13697 symsec
= S_GET_SEGMENT (sym
);
13699 /* This must duplicate the test in adjust_reloc_syms. */
13700 return (symsec
!= &bfd_und_section
13701 && symsec
!= &bfd_abs_section
13702 && !bfd_is_com_section (symsec
)
13703 && !s_is_linkonce (sym
, segtype
)
13705 /* A global or weak symbol is treated as external. */
13706 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13712 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13713 extended opcode. SEC is the section the frag is in. */
13716 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13719 const struct mips16_immed_operand
*op
;
13721 int mintiny
, maxtiny
;
13725 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13727 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13730 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13731 op
= mips16_immed_operands
;
13732 while (op
->type
!= type
)
13735 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13740 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13743 maxtiny
= 1 << op
->nbits
;
13748 maxtiny
= (1 << op
->nbits
) - 1;
13753 mintiny
= - (1 << (op
->nbits
- 1));
13754 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13757 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13758 val
= S_GET_VALUE (fragp
->fr_symbol
);
13759 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13765 /* We won't have the section when we are called from
13766 mips_relax_frag. However, we will always have been called
13767 from md_estimate_size_before_relax first. If this is a
13768 branch to a different section, we mark it as such. If SEC is
13769 NULL, and the frag is not marked, then it must be a branch to
13770 the same section. */
13773 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13778 /* Must have been called from md_estimate_size_before_relax. */
13781 fragp
->fr_subtype
=
13782 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13784 /* FIXME: We should support this, and let the linker
13785 catch branches and loads that are out of range. */
13786 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13787 _("unsupported PC relative reference to different section"));
13791 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13792 /* Assume non-extended on the first relaxation pass.
13793 The address we have calculated will be bogus if this is
13794 a forward branch to another frag, as the forward frag
13795 will have fr_address == 0. */
13799 /* In this case, we know for sure that the symbol fragment is in
13800 the same section. If the relax_marker of the symbol fragment
13801 differs from the relax_marker of this fragment, we have not
13802 yet adjusted the symbol fragment fr_address. We want to add
13803 in STRETCH in order to get a better estimate of the address.
13804 This particularly matters because of the shift bits. */
13806 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13810 /* Adjust stretch for any alignment frag. Note that if have
13811 been expanding the earlier code, the symbol may be
13812 defined in what appears to be an earlier frag. FIXME:
13813 This doesn't handle the fr_subtype field, which specifies
13814 a maximum number of bytes to skip when doing an
13816 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13818 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13821 stretch
= - ((- stretch
)
13822 & ~ ((1 << (int) f
->fr_offset
) - 1));
13824 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13833 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13835 /* The base address rules are complicated. The base address of
13836 a branch is the following instruction. The base address of a
13837 PC relative load or add is the instruction itself, but if it
13838 is in a delay slot (in which case it can not be extended) use
13839 the address of the instruction whose delay slot it is in. */
13840 if (type
== 'p' || type
== 'q')
13844 /* If we are currently assuming that this frag should be
13845 extended, then, the current address is two bytes
13847 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13850 /* Ignore the low bit in the target, since it will be set
13851 for a text label. */
13852 if ((val
& 1) != 0)
13855 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13857 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13860 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13862 /* Branch offsets have an implicit 0 in the lowest bit. */
13863 if (type
== 'p' || type
== 'q')
13866 /* If any of the shifted bits are set, we must use an extended
13867 opcode. If the address depends on the size of this
13868 instruction, this can lead to a loop, so we arrange to always
13869 use an extended opcode. We only check this when we are in
13870 the main relaxation loop, when SEC is NULL. */
13871 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13873 fragp
->fr_subtype
=
13874 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13878 /* If we are about to mark a frag as extended because the value
13879 is precisely maxtiny + 1, then there is a chance of an
13880 infinite loop as in the following code:
13885 In this case when the la is extended, foo is 0x3fc bytes
13886 away, so the la can be shrunk, but then foo is 0x400 away, so
13887 the la must be extended. To avoid this loop, we mark the
13888 frag as extended if it was small, and is about to become
13889 extended with a value of maxtiny + 1. */
13890 if (val
== ((maxtiny
+ 1) << op
->shift
)
13891 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13894 fragp
->fr_subtype
=
13895 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13899 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13900 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13902 if ((val
& ((1 << op
->shift
) - 1)) != 0
13903 || val
< (mintiny
<< op
->shift
)
13904 || val
> (maxtiny
<< op
->shift
))
13910 /* Compute the length of a branch sequence, and adjust the
13911 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13912 worst-case length is computed, with UPDATE being used to indicate
13913 whether an unconditional (-1), branch-likely (+1) or regular (0)
13914 branch is to be computed. */
13916 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13918 bfd_boolean toofar
;
13922 && S_IS_DEFINED (fragp
->fr_symbol
)
13923 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13928 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13930 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13934 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13937 /* If the symbol is not defined or it's in a different segment,
13938 assume the user knows what's going on and emit a short
13944 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13946 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13947 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13948 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13954 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13957 if (mips_pic
!= NO_PIC
)
13959 /* Additional space for PIC loading of target address. */
13961 if (mips_opts
.isa
== ISA_MIPS1
)
13962 /* Additional space for $at-stabilizing nop. */
13966 /* If branch is conditional. */
13967 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13974 /* Estimate the size of a frag before relaxing. Unless this is the
13975 mips16, we are not really relaxing here, and the final size is
13976 encoded in the subtype information. For the mips16, we have to
13977 decide whether we are using an extended opcode or not. */
13980 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13984 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13987 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13989 return fragp
->fr_var
;
13992 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13993 /* We don't want to modify the EXTENDED bit here; it might get us
13994 into infinite loops. We change it only in mips_relax_frag(). */
13995 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13997 if (mips_pic
== NO_PIC
)
13998 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13999 else if (mips_pic
== SVR4_PIC
)
14000 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
14001 else if (mips_pic
== VXWORKS_PIC
)
14002 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14009 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
14010 return -RELAX_FIRST (fragp
->fr_subtype
);
14013 return -RELAX_SECOND (fragp
->fr_subtype
);
14016 /* This is called to see whether a reloc against a defined symbol
14017 should be converted into a reloc against a section. */
14020 mips_fix_adjustable (fixS
*fixp
)
14022 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14023 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14026 if (fixp
->fx_addsy
== NULL
)
14029 /* If symbol SYM is in a mergeable section, relocations of the form
14030 SYM + 0 can usually be made section-relative. The mergeable data
14031 is then identified by the section offset rather than by the symbol.
14033 However, if we're generating REL LO16 relocations, the offset is split
14034 between the LO16 and parterning high part relocation. The linker will
14035 need to recalculate the complete offset in order to correctly identify
14038 The linker has traditionally not looked for the parterning high part
14039 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14040 placed anywhere. Rather than break backwards compatibility by changing
14041 this, it seems better not to force the issue, and instead keep the
14042 original symbol. This will work with either linker behavior. */
14043 if ((lo16_reloc_p (fixp
->fx_r_type
)
14044 || reloc_needs_lo_p (fixp
->fx_r_type
))
14045 && HAVE_IN_PLACE_ADDENDS
14046 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14050 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14051 to a floating-point stub. The same is true for non-R_MIPS16_26
14052 relocations against MIPS16 functions; in this case, the stub becomes
14053 the function's canonical address.
14055 Floating-point stubs are stored in unique .mips16.call.* or
14056 .mips16.fn.* sections. If a stub T for function F is in section S,
14057 the first relocation in section S must be against F; this is how the
14058 linker determines the target function. All relocations that might
14059 resolve to T must also be against F. We therefore have the following
14060 restrictions, which are given in an intentionally-redundant way:
14062 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14065 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14066 if that stub might be used.
14068 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14071 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14072 that stub might be used.
14074 There is a further restriction:
14076 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14077 on targets with in-place addends; the relocation field cannot
14078 encode the low bit.
14080 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14081 against a MIPS16 symbol.
14083 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14084 relocation against some symbol R, no relocation against R may be
14085 reduced. (Note that this deals with (2) as well as (1) because
14086 relocations against global symbols will never be reduced on ELF
14087 targets.) This approach is a little simpler than trying to detect
14088 stub sections, and gives the "all or nothing" per-symbol consistency
14089 that we have for MIPS16 symbols. */
14091 && fixp
->fx_subsy
== NULL
14092 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14093 || *symbol_get_tc (fixp
->fx_addsy
)))
14100 /* Translate internal representation of relocation info to BFD target
14104 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14106 static arelent
*retval
[4];
14108 bfd_reloc_code_real_type code
;
14110 memset (retval
, 0, sizeof(retval
));
14111 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14112 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14113 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14114 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14116 if (fixp
->fx_pcrel
)
14118 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14120 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14121 Relocations want only the symbol offset. */
14122 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14125 /* A gruesome hack which is a result of the gruesome gas
14126 reloc handling. What's worse, for COFF (as opposed to
14127 ECOFF), we might need yet another copy of reloc->address.
14128 See bfd_install_relocation. */
14129 reloc
->addend
+= reloc
->address
;
14133 reloc
->addend
= fixp
->fx_addnumber
;
14135 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14136 entry to be used in the relocation's section offset. */
14137 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14139 reloc
->address
= reloc
->addend
;
14143 code
= fixp
->fx_r_type
;
14145 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14146 if (reloc
->howto
== NULL
)
14148 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14149 _("Can not represent %s relocation in this object file format"),
14150 bfd_get_reloc_code_name (code
));
14157 /* Relax a machine dependent frag. This returns the amount by which
14158 the current size of the frag should change. */
14161 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14163 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14165 offsetT old_var
= fragp
->fr_var
;
14167 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14169 return fragp
->fr_var
- old_var
;
14172 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14175 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14177 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14179 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14184 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14186 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14193 /* Convert a machine dependent frag. */
14196 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14198 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14201 unsigned long insn
;
14205 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14207 if (target_big_endian
)
14208 insn
= bfd_getb32 (buf
);
14210 insn
= bfd_getl32 (buf
);
14212 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14214 /* We generate a fixup instead of applying it right now
14215 because, if there are linker relaxations, we're going to
14216 need the relocations. */
14217 exp
.X_op
= O_symbol
;
14218 exp
.X_add_symbol
= fragp
->fr_symbol
;
14219 exp
.X_add_number
= fragp
->fr_offset
;
14221 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14222 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14223 fixp
->fx_file
= fragp
->fr_file
;
14224 fixp
->fx_line
= fragp
->fr_line
;
14226 md_number_to_chars ((char *) buf
, insn
, 4);
14233 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14234 _("relaxed out-of-range branch into a jump"));
14236 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14239 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14241 /* Reverse the branch. */
14242 switch ((insn
>> 28) & 0xf)
14245 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14246 have the condition reversed by tweaking a single
14247 bit, and their opcodes all have 0x4???????. */
14248 assert ((insn
& 0xf1000000) == 0x41000000);
14249 insn
^= 0x00010000;
14253 /* bltz 0x04000000 bgez 0x04010000
14254 bltzal 0x04100000 bgezal 0x04110000 */
14255 assert ((insn
& 0xfc0e0000) == 0x04000000);
14256 insn
^= 0x00010000;
14260 /* beq 0x10000000 bne 0x14000000
14261 blez 0x18000000 bgtz 0x1c000000 */
14262 insn
^= 0x04000000;
14270 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14272 /* Clear the and-link bit. */
14273 assert ((insn
& 0xfc1c0000) == 0x04100000);
14275 /* bltzal 0x04100000 bgezal 0x04110000
14276 bltzall 0x04120000 bgezall 0x04130000 */
14277 insn
&= ~0x00100000;
14280 /* Branch over the branch (if the branch was likely) or the
14281 full jump (not likely case). Compute the offset from the
14282 current instruction to branch to. */
14283 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14287 /* How many bytes in instructions we've already emitted? */
14288 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14289 /* How many bytes in instructions from here to the end? */
14290 i
= fragp
->fr_var
- i
;
14292 /* Convert to instruction count. */
14294 /* Branch counts from the next instruction. */
14297 /* Branch over the jump. */
14298 md_number_to_chars ((char *) buf
, insn
, 4);
14302 md_number_to_chars ((char *) buf
, 0, 4);
14305 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14307 /* beql $0, $0, 2f */
14309 /* Compute the PC offset from the current instruction to
14310 the end of the variable frag. */
14311 /* How many bytes in instructions we've already emitted? */
14312 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14313 /* How many bytes in instructions from here to the end? */
14314 i
= fragp
->fr_var
- i
;
14315 /* Convert to instruction count. */
14317 /* Don't decrement i, because we want to branch over the
14321 md_number_to_chars ((char *) buf
, insn
, 4);
14324 md_number_to_chars ((char *) buf
, 0, 4);
14329 if (mips_pic
== NO_PIC
)
14332 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14333 ? 0x0c000000 : 0x08000000);
14334 exp
.X_op
= O_symbol
;
14335 exp
.X_add_symbol
= fragp
->fr_symbol
;
14336 exp
.X_add_number
= fragp
->fr_offset
;
14338 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14339 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14340 fixp
->fx_file
= fragp
->fr_file
;
14341 fixp
->fx_line
= fragp
->fr_line
;
14343 md_number_to_chars ((char *) buf
, insn
, 4);
14348 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14349 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14350 exp
.X_op
= O_symbol
;
14351 exp
.X_add_symbol
= fragp
->fr_symbol
;
14352 exp
.X_add_number
= fragp
->fr_offset
;
14354 if (fragp
->fr_offset
)
14356 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14357 exp
.X_add_number
= 0;
14360 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14361 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14362 fixp
->fx_file
= fragp
->fr_file
;
14363 fixp
->fx_line
= fragp
->fr_line
;
14365 md_number_to_chars ((char *) buf
, insn
, 4);
14368 if (mips_opts
.isa
== ISA_MIPS1
)
14371 md_number_to_chars ((char *) buf
, 0, 4);
14375 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14376 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14378 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14379 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14380 fixp
->fx_file
= fragp
->fr_file
;
14381 fixp
->fx_line
= fragp
->fr_line
;
14383 md_number_to_chars ((char *) buf
, insn
, 4);
14387 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14392 md_number_to_chars ((char *) buf
, insn
, 4);
14397 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14398 + fragp
->fr_fix
+ fragp
->fr_var
);
14400 fragp
->fr_fix
+= fragp
->fr_var
;
14405 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14408 const struct mips16_immed_operand
*op
;
14409 bfd_boolean small
, ext
;
14412 unsigned long insn
;
14413 bfd_boolean use_extend
;
14414 unsigned short extend
;
14416 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14417 op
= mips16_immed_operands
;
14418 while (op
->type
!= type
)
14421 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14432 resolve_symbol_value (fragp
->fr_symbol
);
14433 val
= S_GET_VALUE (fragp
->fr_symbol
);
14438 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14440 /* The rules for the base address of a PC relative reloc are
14441 complicated; see mips16_extended_frag. */
14442 if (type
== 'p' || type
== 'q')
14447 /* Ignore the low bit in the target, since it will be
14448 set for a text label. */
14449 if ((val
& 1) != 0)
14452 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14454 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14457 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14460 /* Make sure the section winds up with the alignment we have
14463 record_alignment (asec
, op
->shift
);
14467 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14468 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14469 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14470 _("extended instruction in delay slot"));
14472 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14474 if (target_big_endian
)
14475 insn
= bfd_getb16 (buf
);
14477 insn
= bfd_getl16 (buf
);
14479 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14480 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14481 small
, ext
, &insn
, &use_extend
, &extend
);
14485 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14486 fragp
->fr_fix
+= 2;
14490 md_number_to_chars ((char *) buf
, insn
, 2);
14491 fragp
->fr_fix
+= 2;
14499 first
= RELAX_FIRST (fragp
->fr_subtype
);
14500 second
= RELAX_SECOND (fragp
->fr_subtype
);
14501 fixp
= (fixS
*) fragp
->fr_opcode
;
14503 /* Possibly emit a warning if we've chosen the longer option. */
14504 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14505 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14507 const char *msg
= macro_warning (fragp
->fr_subtype
);
14509 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14512 /* Go through all the fixups for the first sequence. Disable them
14513 (by marking them as done) if we're going to use the second
14514 sequence instead. */
14516 && fixp
->fx_frag
== fragp
14517 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14519 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14521 fixp
= fixp
->fx_next
;
14524 /* Go through the fixups for the second sequence. Disable them if
14525 we're going to use the first sequence, otherwise adjust their
14526 addresses to account for the relaxation. */
14527 while (fixp
&& fixp
->fx_frag
== fragp
)
14529 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14530 fixp
->fx_where
-= first
;
14533 fixp
= fixp
->fx_next
;
14536 /* Now modify the frag contents. */
14537 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14541 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14542 memmove (start
, start
+ first
, second
);
14543 fragp
->fr_fix
-= first
;
14546 fragp
->fr_fix
-= second
;
14552 /* This function is called after the relocs have been generated.
14553 We've been storing mips16 text labels as odd. Here we convert them
14554 back to even for the convenience of the debugger. */
14557 mips_frob_file_after_relocs (void)
14560 unsigned int count
, i
;
14565 syms
= bfd_get_outsymbols (stdoutput
);
14566 count
= bfd_get_symcount (stdoutput
);
14567 for (i
= 0; i
< count
; i
++, syms
++)
14569 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14570 && ((*syms
)->value
& 1) != 0)
14572 (*syms
)->value
&= ~1;
14573 /* If the symbol has an odd size, it was probably computed
14574 incorrectly, so adjust that as well. */
14575 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14576 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14583 /* This function is called whenever a label is defined. It is used
14584 when handling branch delays; if a branch has a label, we assume we
14585 can not move it. */
14588 mips_define_label (symbolS
*sym
)
14590 segment_info_type
*si
= seg_info (now_seg
);
14591 struct insn_label_list
*l
;
14593 if (free_insn_labels
== NULL
)
14594 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14597 l
= free_insn_labels
;
14598 free_insn_labels
= l
->next
;
14602 l
->next
= si
->label_list
;
14603 si
->label_list
= l
;
14606 dwarf2_emit_label (sym
);
14610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14612 /* Some special processing for a MIPS ELF file. */
14615 mips_elf_final_processing (void)
14617 /* Write out the register information. */
14618 if (mips_abi
!= N64_ABI
)
14622 s
.ri_gprmask
= mips_gprmask
;
14623 s
.ri_cprmask
[0] = mips_cprmask
[0];
14624 s
.ri_cprmask
[1] = mips_cprmask
[1];
14625 s
.ri_cprmask
[2] = mips_cprmask
[2];
14626 s
.ri_cprmask
[3] = mips_cprmask
[3];
14627 /* The gp_value field is set by the MIPS ELF backend. */
14629 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14630 ((Elf32_External_RegInfo
*)
14631 mips_regmask_frag
));
14635 Elf64_Internal_RegInfo s
;
14637 s
.ri_gprmask
= mips_gprmask
;
14639 s
.ri_cprmask
[0] = mips_cprmask
[0];
14640 s
.ri_cprmask
[1] = mips_cprmask
[1];
14641 s
.ri_cprmask
[2] = mips_cprmask
[2];
14642 s
.ri_cprmask
[3] = mips_cprmask
[3];
14643 /* The gp_value field is set by the MIPS ELF backend. */
14645 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14646 ((Elf64_External_RegInfo
*)
14647 mips_regmask_frag
));
14650 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14651 sort of BFD interface for this. */
14652 if (mips_any_noreorder
)
14653 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14654 if (mips_pic
!= NO_PIC
)
14656 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14657 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14660 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14662 /* Set MIPS ELF flags for ASEs. */
14663 /* We may need to define a new flag for DSP ASE, and set this flag when
14664 file_ase_dsp is true. */
14665 /* Same for DSP R2. */
14666 /* We may need to define a new flag for MT ASE, and set this flag when
14667 file_ase_mt is true. */
14668 if (file_ase_mips16
)
14669 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14670 #if 0 /* XXX FIXME */
14671 if (file_ase_mips3d
)
14672 elf_elfheader (stdoutput
)->e_flags
|= ???;
14675 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14677 /* Set the MIPS ELF ABI flags. */
14678 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14679 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14680 else if (mips_abi
== O64_ABI
)
14681 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14682 else if (mips_abi
== EABI_ABI
)
14684 if (!file_mips_gp32
)
14685 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14687 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14689 else if (mips_abi
== N32_ABI
)
14690 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14692 /* Nothing to do for N64_ABI. */
14694 if (mips_32bitmode
)
14695 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14697 #if 0 /* XXX FIXME */
14698 /* 32 bit code with 64 bit FP registers. */
14699 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14700 elf_elfheader (stdoutput
)->e_flags
|= ???;
14704 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14706 typedef struct proc
{
14708 symbolS
*func_end_sym
;
14709 unsigned long reg_mask
;
14710 unsigned long reg_offset
;
14711 unsigned long fpreg_mask
;
14712 unsigned long fpreg_offset
;
14713 unsigned long frame_offset
;
14714 unsigned long frame_reg
;
14715 unsigned long pc_reg
;
14718 static procS cur_proc
;
14719 static procS
*cur_proc_ptr
;
14720 static int numprocs
;
14722 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14726 mips_nop_opcode (void)
14728 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14731 /* Fill in an rs_align_code fragment. This only needs to do something
14732 for MIPS16 code, where 0 is not a nop. */
14735 mips_handle_align (fragS
*fragp
)
14739 if (fragp
->fr_type
!= rs_align_code
)
14742 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14747 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14753 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14759 md_obj_begin (void)
14766 /* Check for premature end, nesting errors, etc. */
14768 as_warn (_("missing .end at end of assembly"));
14777 if (*input_line_pointer
== '-')
14779 ++input_line_pointer
;
14782 if (!ISDIGIT (*input_line_pointer
))
14783 as_bad (_("expected simple number"));
14784 if (input_line_pointer
[0] == '0')
14786 if (input_line_pointer
[1] == 'x')
14788 input_line_pointer
+= 2;
14789 while (ISXDIGIT (*input_line_pointer
))
14792 val
|= hex_value (*input_line_pointer
++);
14794 return negative
? -val
: val
;
14798 ++input_line_pointer
;
14799 while (ISDIGIT (*input_line_pointer
))
14802 val
|= *input_line_pointer
++ - '0';
14804 return negative
? -val
: val
;
14807 if (!ISDIGIT (*input_line_pointer
))
14809 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14810 *input_line_pointer
, *input_line_pointer
);
14811 as_warn (_("invalid number"));
14814 while (ISDIGIT (*input_line_pointer
))
14817 val
+= *input_line_pointer
++ - '0';
14819 return negative
? -val
: val
;
14822 /* The .file directive; just like the usual .file directive, but there
14823 is an initial number which is the ECOFF file index. In the non-ECOFF
14824 case .file implies DWARF-2. */
14827 s_mips_file (int x ATTRIBUTE_UNUSED
)
14829 static int first_file_directive
= 0;
14831 if (ECOFF_DEBUGGING
)
14840 filename
= dwarf2_directive_file (0);
14842 /* Versions of GCC up to 3.1 start files with a ".file"
14843 directive even for stabs output. Make sure that this
14844 ".file" is handled. Note that you need a version of GCC
14845 after 3.1 in order to support DWARF-2 on MIPS. */
14846 if (filename
!= NULL
&& ! first_file_directive
)
14848 (void) new_logical_line (filename
, -1);
14849 s_app_file_string (filename
, 0);
14851 first_file_directive
= 1;
14855 /* The .loc directive, implying DWARF-2. */
14858 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14860 if (!ECOFF_DEBUGGING
)
14861 dwarf2_directive_loc (0);
14864 /* The .end directive. */
14867 s_mips_end (int x ATTRIBUTE_UNUSED
)
14871 /* Following functions need their own .frame and .cprestore directives. */
14872 mips_frame_reg_valid
= 0;
14873 mips_cprestore_valid
= 0;
14875 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14878 demand_empty_rest_of_line ();
14883 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14884 as_warn (_(".end not in text section"));
14888 as_warn (_(".end directive without a preceding .ent directive."));
14889 demand_empty_rest_of_line ();
14895 assert (S_GET_NAME (p
));
14896 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14897 as_warn (_(".end symbol does not match .ent symbol."));
14899 if (debug_type
== DEBUG_STABS
)
14900 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14904 as_warn (_(".end directive missing or unknown symbol"));
14907 /* Create an expression to calculate the size of the function. */
14908 if (p
&& cur_proc_ptr
)
14910 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14911 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14914 exp
->X_op
= O_subtract
;
14915 exp
->X_add_symbol
= symbol_temp_new_now ();
14916 exp
->X_op_symbol
= p
;
14917 exp
->X_add_number
= 0;
14919 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14922 /* Generate a .pdr section. */
14923 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14925 segT saved_seg
= now_seg
;
14926 subsegT saved_subseg
= now_subseg
;
14931 dot
= frag_now_fix ();
14933 #ifdef md_flush_pending_output
14934 md_flush_pending_output ();
14938 subseg_set (pdr_seg
, 0);
14940 /* Write the symbol. */
14941 exp
.X_op
= O_symbol
;
14942 exp
.X_add_symbol
= p
;
14943 exp
.X_add_number
= 0;
14944 emit_expr (&exp
, 4);
14946 fragp
= frag_more (7 * 4);
14948 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14949 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14950 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14951 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14952 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14953 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14954 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14956 subseg_set (saved_seg
, saved_subseg
);
14958 #endif /* OBJ_ELF */
14960 cur_proc_ptr
= NULL
;
14963 /* The .aent and .ent directives. */
14966 s_mips_ent (int aent
)
14970 symbolP
= get_symbol ();
14971 if (*input_line_pointer
== ',')
14972 ++input_line_pointer
;
14973 SKIP_WHITESPACE ();
14974 if (ISDIGIT (*input_line_pointer
)
14975 || *input_line_pointer
== '-')
14978 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14979 as_warn (_(".ent or .aent not in text section."));
14981 if (!aent
&& cur_proc_ptr
)
14982 as_warn (_("missing .end"));
14986 /* This function needs its own .frame and .cprestore directives. */
14987 mips_frame_reg_valid
= 0;
14988 mips_cprestore_valid
= 0;
14990 cur_proc_ptr
= &cur_proc
;
14991 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14993 cur_proc_ptr
->func_sym
= symbolP
;
14995 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14999 if (debug_type
== DEBUG_STABS
)
15000 stabs_generate_asm_func (S_GET_NAME (symbolP
),
15001 S_GET_NAME (symbolP
));
15004 demand_empty_rest_of_line ();
15007 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15008 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15009 s_mips_frame is used so that we can set the PDR information correctly.
15010 We can't use the ecoff routines because they make reference to the ecoff
15011 symbol table (in the mdebug section). */
15014 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
15017 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15021 if (cur_proc_ptr
== (procS
*) NULL
)
15023 as_warn (_(".frame outside of .ent"));
15024 demand_empty_rest_of_line ();
15028 cur_proc_ptr
->frame_reg
= tc_get_register (1);
15030 SKIP_WHITESPACE ();
15031 if (*input_line_pointer
++ != ','
15032 || get_absolute_expression_and_terminator (&val
) != ',')
15034 as_warn (_("Bad .frame directive"));
15035 --input_line_pointer
;
15036 demand_empty_rest_of_line ();
15040 cur_proc_ptr
->frame_offset
= val
;
15041 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15043 demand_empty_rest_of_line ();
15046 #endif /* OBJ_ELF */
15050 /* The .fmask and .mask directives. If the mdebug section is present
15051 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15052 embedded targets, s_mips_mask is used so that we can set the PDR
15053 information correctly. We can't use the ecoff routines because they
15054 make reference to the ecoff symbol table (in the mdebug section). */
15057 s_mips_mask (int reg_type
)
15060 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15064 if (cur_proc_ptr
== (procS
*) NULL
)
15066 as_warn (_(".mask/.fmask outside of .ent"));
15067 demand_empty_rest_of_line ();
15071 if (get_absolute_expression_and_terminator (&mask
) != ',')
15073 as_warn (_("Bad .mask/.fmask directive"));
15074 --input_line_pointer
;
15075 demand_empty_rest_of_line ();
15079 off
= get_absolute_expression ();
15081 if (reg_type
== 'F')
15083 cur_proc_ptr
->fpreg_mask
= mask
;
15084 cur_proc_ptr
->fpreg_offset
= off
;
15088 cur_proc_ptr
->reg_mask
= mask
;
15089 cur_proc_ptr
->reg_offset
= off
;
15092 demand_empty_rest_of_line ();
15095 #endif /* OBJ_ELF */
15096 s_ignore (reg_type
);
15099 /* A table describing all the processors gas knows about. Names are
15100 matched in the order listed.
15102 To ease comparison, please keep this table in the same order as
15103 gcc's mips_cpu_info_table[]. */
15104 static const struct mips_cpu_info mips_cpu_info_table
[] =
15106 /* Entries for generic ISAs */
15107 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15108 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15109 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15110 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15111 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15112 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15113 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15114 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15115 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15118 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15119 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15120 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15123 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15126 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15127 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15128 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15129 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15130 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15131 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15132 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15133 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15134 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15135 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15136 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15137 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15138 /* ST Microelectronics Loongson 2E and 2F cores */
15139 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15140 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15143 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15144 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15145 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15146 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15147 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15148 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15149 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15150 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15151 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15152 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15153 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15154 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15155 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15156 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15157 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15160 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15161 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15162 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15163 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15165 /* MIPS 32 Release 2 */
15166 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15167 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15168 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15169 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15170 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15171 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15172 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15173 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15174 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15175 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15176 /* Deprecated forms of the above. */
15177 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15178 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15179 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15180 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15181 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15182 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15183 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15184 /* Deprecated forms of the above. */
15185 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15186 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15187 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15188 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15189 ISA_MIPS32R2
, CPU_MIPS32R2
},
15190 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15191 ISA_MIPS32R2
, CPU_MIPS32R2
},
15192 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15193 ISA_MIPS32R2
, CPU_MIPS32R2
},
15194 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15195 ISA_MIPS32R2
, CPU_MIPS32R2
},
15196 /* Deprecated forms of the above. */
15197 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15198 ISA_MIPS32R2
, CPU_MIPS32R2
},
15199 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15200 ISA_MIPS32R2
, CPU_MIPS32R2
},
15201 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15202 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15203 ISA_MIPS32R2
, CPU_MIPS32R2
},
15204 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15205 ISA_MIPS32R2
, CPU_MIPS32R2
},
15206 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15207 ISA_MIPS32R2
, CPU_MIPS32R2
},
15208 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15209 ISA_MIPS32R2
, CPU_MIPS32R2
},
15210 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15211 ISA_MIPS32R2
, CPU_MIPS32R2
},
15212 /* Deprecated forms of the above. */
15213 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15214 ISA_MIPS32R2
, CPU_MIPS32R2
},
15215 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15216 ISA_MIPS32R2
, CPU_MIPS32R2
},
15219 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15220 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15221 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15222 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15224 /* Broadcom SB-1 CPU core */
15225 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15226 ISA_MIPS64
, CPU_SB1
},
15227 /* Broadcom SB-1A CPU core */
15228 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15229 ISA_MIPS64
, CPU_SB1
},
15231 /* MIPS 64 Release 2 */
15233 /* Cavium Networks Octeon CPU core */
15234 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15237 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
15244 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15245 with a final "000" replaced by "k". Ignore case.
15247 Note: this function is shared between GCC and GAS. */
15250 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15252 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15253 given
++, canonical
++;
15255 return ((*given
== 0 && *canonical
== 0)
15256 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15260 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15261 CPU name. We've traditionally allowed a lot of variation here.
15263 Note: this function is shared between GCC and GAS. */
15266 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15268 /* First see if the name matches exactly, or with a final "000"
15269 turned into "k". */
15270 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15273 /* If not, try comparing based on numerical designation alone.
15274 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15275 if (TOLOWER (*given
) == 'r')
15277 if (!ISDIGIT (*given
))
15280 /* Skip over some well-known prefixes in the canonical name,
15281 hoping to find a number there too. */
15282 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15284 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15286 else if (TOLOWER (canonical
[0]) == 'r')
15289 return mips_strict_matching_cpu_name_p (canonical
, given
);
15293 /* Parse an option that takes the name of a processor as its argument.
15294 OPTION is the name of the option and CPU_STRING is the argument.
15295 Return the corresponding processor enumeration if the CPU_STRING is
15296 recognized, otherwise report an error and return null.
15298 A similar function exists in GCC. */
15300 static const struct mips_cpu_info
*
15301 mips_parse_cpu (const char *option
, const char *cpu_string
)
15303 const struct mips_cpu_info
*p
;
15305 /* 'from-abi' selects the most compatible architecture for the given
15306 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15307 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15308 version. Look first at the -mgp options, if given, otherwise base
15309 the choice on MIPS_DEFAULT_64BIT.
15311 Treat NO_ABI like the EABIs. One reason to do this is that the
15312 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15313 architecture. This code picks MIPS I for 'mips' and MIPS III for
15314 'mips64', just as we did in the days before 'from-abi'. */
15315 if (strcasecmp (cpu_string
, "from-abi") == 0)
15317 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15318 return mips_cpu_info_from_isa (ISA_MIPS1
);
15320 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15321 return mips_cpu_info_from_isa (ISA_MIPS3
);
15323 if (file_mips_gp32
>= 0)
15324 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15326 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15331 /* 'default' has traditionally been a no-op. Probably not very useful. */
15332 if (strcasecmp (cpu_string
, "default") == 0)
15335 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15336 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15339 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15343 /* Return the canonical processor information for ISA (a member of the
15344 ISA_MIPS* enumeration). */
15346 static const struct mips_cpu_info
*
15347 mips_cpu_info_from_isa (int isa
)
15351 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15352 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15353 && isa
== mips_cpu_info_table
[i
].isa
)
15354 return (&mips_cpu_info_table
[i
]);
15359 static const struct mips_cpu_info
*
15360 mips_cpu_info_from_arch (int arch
)
15364 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15365 if (arch
== mips_cpu_info_table
[i
].cpu
)
15366 return (&mips_cpu_info_table
[i
]);
15372 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15376 fprintf (stream
, "%24s", "");
15381 fprintf (stream
, ", ");
15385 if (*col_p
+ strlen (string
) > 72)
15387 fprintf (stream
, "\n%24s", "");
15391 fprintf (stream
, "%s", string
);
15392 *col_p
+= strlen (string
);
15398 md_show_usage (FILE *stream
)
15403 fprintf (stream
, _("\
15405 -EB generate big endian output\n\
15406 -EL generate little endian output\n\
15407 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15408 -G NUM allow referencing objects up to NUM bytes\n\
15409 implicitly with the gp register [default 8]\n"));
15410 fprintf (stream
, _("\
15411 -mips1 generate MIPS ISA I instructions\n\
15412 -mips2 generate MIPS ISA II instructions\n\
15413 -mips3 generate MIPS ISA III instructions\n\
15414 -mips4 generate MIPS ISA IV instructions\n\
15415 -mips5 generate MIPS ISA V instructions\n\
15416 -mips32 generate MIPS32 ISA instructions\n\
15417 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15418 -mips64 generate MIPS64 ISA instructions\n\
15419 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15420 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15424 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15425 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15426 show (stream
, "from-abi", &column
, &first
);
15427 fputc ('\n', stream
);
15429 fprintf (stream
, _("\
15430 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15431 -no-mCPU don't generate code specific to CPU.\n\
15432 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15436 show (stream
, "3900", &column
, &first
);
15437 show (stream
, "4010", &column
, &first
);
15438 show (stream
, "4100", &column
, &first
);
15439 show (stream
, "4650", &column
, &first
);
15440 fputc ('\n', stream
);
15442 fprintf (stream
, _("\
15443 -mips16 generate mips16 instructions\n\
15444 -no-mips16 do not generate mips16 instructions\n"));
15445 fprintf (stream
, _("\
15446 -msmartmips generate smartmips instructions\n\
15447 -mno-smartmips do not generate smartmips instructions\n"));
15448 fprintf (stream
, _("\
15449 -mdsp generate DSP instructions\n\
15450 -mno-dsp do not generate DSP instructions\n"));
15451 fprintf (stream
, _("\
15452 -mdspr2 generate DSP R2 instructions\n\
15453 -mno-dspr2 do not generate DSP R2 instructions\n"));
15454 fprintf (stream
, _("\
15455 -mmt generate MT instructions\n\
15456 -mno-mt do not generate MT instructions\n"));
15457 fprintf (stream
, _("\
15458 -mfix-vr4120 work around certain VR4120 errata\n\
15459 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15460 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15461 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15462 -msym32 assume all symbols have 32-bit values\n\
15463 -O0 remove unneeded NOPs, do not swap branches\n\
15464 -O remove unneeded NOPs and swap branches\n\
15465 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15466 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15467 fprintf (stream
, _("\
15468 -mhard-float allow floating-point instructions\n\
15469 -msoft-float do not allow floating-point instructions\n\
15470 -msingle-float only allow 32-bit floating-point operations\n\
15471 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15472 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15475 fprintf (stream
, _("\
15476 -KPIC, -call_shared generate SVR4 position independent code\n\
15477 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15478 -mvxworks-pic generate VxWorks position independent code\n\
15479 -non_shared do not generate code that can operate with DSOs\n\
15480 -xgot assume a 32 bit GOT\n\
15481 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15482 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15483 position dependent (non shared) code\n\
15484 -mabi=ABI create ABI conformant object file for:\n"));
15488 show (stream
, "32", &column
, &first
);
15489 show (stream
, "o64", &column
, &first
);
15490 show (stream
, "n32", &column
, &first
);
15491 show (stream
, "64", &column
, &first
);
15492 show (stream
, "eabi", &column
, &first
);
15494 fputc ('\n', stream
);
15496 fprintf (stream
, _("\
15497 -32 create o32 ABI object file (default)\n\
15498 -n32 create n32 ABI object file\n\
15499 -64 create 64 ABI object file\n"));
15504 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15506 if (HAVE_64BIT_SYMBOLS
)
15509 return dwarf2_format_64bit_irix
;
15511 return dwarf2_format_64bit
;
15515 return dwarf2_format_32bit
;
15519 mips_dwarf2_addr_size (void)
15521 if (HAVE_64BIT_SYMBOLS
)
15527 /* Standard calling conventions leave the CFA at SP on entry. */
15529 mips_cfi_frame_initial_instructions (void)
15531 cfi_add_CFA_def_cfa_register (SP
);
15535 tc_mips_regname_to_dw2regnum (char *regname
)
15537 unsigned int regnum
= -1;
15540 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))