1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* These variables are filled in with the masks of registers used.
69 The object format code reads them and puts them in the appropriate
71 unsigned long mips_gprmask
;
72 unsigned long mips_cprmask
[4];
74 /* MIPS ISA (Instruction Set Architecture) level. */
75 static int mips_isa
= -1;
77 /* MIPS PIC level. 0 is normal, non-PIC code. 2 means to generate
78 SVR4 ABI PIC calls. 1 doesn't mean anything. */
81 static int mips_warn_about_macros
;
82 static int mips_noreorder
;
83 static int mips_any_noreorder
;
84 static int mips_nomove
;
86 static int mips_nobopt
;
89 /* The size of the small data section. */
90 static int g_switch_value
= 8;
96 /* handle of the OPCODE hash table */
97 static struct hash_control
*op_hash
= NULL
;
99 /* This array holds the chars that always start a comment. If the
100 pre-processor is disabled, these aren't very useful */
101 const char comment_chars
[] = "#";
103 /* This array holds the chars that only start a comment at the beginning of
104 a line. If the line seems to have the form '# 123 filename'
105 .line and .file directives will appear in the pre-processed output */
106 /* Note that input_file.c hand checks for '#' at the beginning of the
107 first line of the input file. This is because the compiler outputs
108 #NO_APP at the beginning of its output. */
109 /* Also note that C style comments are always supported. */
110 const char line_comment_chars
[] = "#";
112 /* This array holds machine specific line separator characters. */
113 const char line_separator_chars
[] = "";
115 /* Chars that can be used to separate mant from exp in floating point nums */
116 const char EXP_CHARS
[] = "eE";
118 /* Chars that mean this number is a floating point constant */
121 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
123 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
124 changed in read.c . Ideally it shouldn't have to know about it at all,
125 but nothing is ideal around here.
128 static char *insn_error
;
130 static int byte_order
= BYTE_ORDER
;
132 static int auto_align
= 1;
134 /* Symbol labelling the current insn. */
135 static symbolS
*insn_label
;
137 /* When outputting SVR4 PIC code, the assembler needs to know the
138 offset in the stack frame from which to restore the $gp register.
139 This is set by the .cprestore pseudo-op, and saved in this
141 static offsetT mips_cprestore_offset
= -1;
143 /* This is the register which holds the stack frame, as set by the
144 .frame pseudo-op. This is needed to implement .cprestore. */
145 static int mips_frame_reg
= SP
;
147 /* To output NOP instructions correctly, we need to keep information
148 about the previous two instructions. */
150 /* Whether we are optimizing. The default value of 2 means to remove
151 unneeded NOPs and swap branch instructions when possible. A value
152 of 1 means to not swap branches. A value of 0 means to always
154 static int mips_optimize
= 2;
156 /* The previous instruction. */
157 static struct mips_cl_insn prev_insn
;
159 /* The instruction before prev_insn. */
160 static struct mips_cl_insn prev_prev_insn
;
162 /* If we don't want information for prev_insn or prev_prev_insn, we
163 point the insn_mo field at this dummy integer. */
164 static const struct mips_opcode dummy_opcode
= { 0 };
166 /* Non-zero if prev_insn is valid. */
167 static int prev_insn_valid
;
169 /* The frag for the previous instruction. */
170 static struct frag
*prev_insn_frag
;
172 /* The offset into prev_insn_frag for the previous instruction. */
173 static long prev_insn_where
;
175 /* The reloc for the previous instruction, if any. */
176 static fixS
*prev_insn_fixp
;
178 /* Non-zero if the previous instruction was in a delay slot. */
179 static int prev_insn_is_delay_slot
;
181 /* Non-zero if the previous instruction was in a .set noreorder. */
182 static int prev_insn_unreordered
;
184 /* Non-zero if the previous previous instruction was in a .set
186 static int prev_prev_insn_unreordered
;
188 /* Since the MIPS does not have multiple forms of PC relative
189 instructions, we do not have to do relaxing as is done on other
190 platforms. However, we do have to handle GP relative addressing
191 correctly, which turns out to be a similar problem.
193 Every macro that refers to a symbol can occur in (at least) two
194 forms, one with GP relative addressing and one without. For
195 example, loading a global variable into a register generally uses
196 an macroinstruction like this:
198 If i can be addressed off the GP register (this is true if it is in
199 the .sbss or .sdata section, or if it is known to be smaller than
200 the -G argument) this will generate the following instruction:
202 This instruction will use a GPREL reloc. If i can not be addressed
203 off the GP register, the following instruction sequence will be used:
206 In this case the first instruction will have a HI16 reloc, and the
207 second reloc will have a LO16 reloc. Both relocs will be against
210 The issue here is that we may not know whether i is GP addressable
211 until after we see the instruction that uses it. Therefore, we
212 want to be able to choose the final instruction sequence only at
213 the end of the assembly. This is similar to the way other
214 platforms choose the form of a PC relative instruction only at the
217 When generating position independent code we do not use GP
218 addressing in the same way, but the issue still arises as external
219 symbols and local symbols must be handled differently.
221 We handle these issues by actually generating both possible
222 instruction sequences. The longer one is put in a frag_var with
223 type rs_machine_dependent. We encode what to do with the frag in
224 the subtype field. We encode (1) the number of existing bytes to
225 replace, (2) the number of new bytes to use, (3) the offset from
226 the start of the existing bytes to the first reloc we must generate
227 (that is, the offset is applied from the start of the existing
228 bytes after they are replaced by the new bytes, if any), (4) the
229 offset from the start of the existing bytes to the second reloc,
230 (5) whether a third reloc is needed (the third reloc is always four
231 bytes after the second reloc), and (6) whether to warn if this
232 variant is used (this is sometimes needed if .set nomacro or .set
233 noat is in effect). All these numbers are reasonably small.
235 Generating two instruction sequences must be handled carefully to
236 ensure that delay slots are handled correctly. Fortunately, the
237 issue only arises in a restricted number of cases. When the second
238 instruction sequence is generated, append_insn is directed to
239 maintain the existing delay slot information, so it continues to
240 apply to any code after the second instruction sequence. This
241 means that the second instruction sequence must not impose any
242 requirements not required by the first instruction sequence.
244 These variant frags are then handled in functions called by the
245 machine independent code. md_estimate_size_before_relax returns
246 the final size of the frag. md_convert_frag sets up the final form
247 of the frag. tc_gen_reloc adjust the first reloc and adds a second
249 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
253 | (((reloc1) + 64) << 9) \
254 | (((reloc2) + 64) << 2) \
255 | ((reloc3) ? (1 << 1) : 0) \
257 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
258 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
259 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
260 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
261 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
262 #define RELAX_WARN(i) ((i) & 1)
264 /* Prototypes for static functions. */
267 #define internalError() \
268 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
270 #define internalError() as_fatal ("MIPS internal Error");
273 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
274 unsigned int reg
, int fpr
));
275 static void append_insn
PARAMS ((char *place
,
276 struct mips_cl_insn
* ip
,
278 bfd_reloc_code_real_type r
));
279 static void mips_no_prev_insn
PARAMS ((void));
280 static void mips_emit_delays
PARAMS ((void));
281 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
282 const char *name
, const char *fmt
,
284 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
285 expressionS
* ep
, int regnum
));
286 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
287 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
289 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
290 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
291 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
292 #ifdef LOSING_COMPILER
293 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
295 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
296 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
297 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
298 static symbolS
*get_symbol
PARAMS ((void));
299 static void mips_align
PARAMS ((int to
, int fill
));
300 static void s_align
PARAMS ((int));
301 static void s_stringer
PARAMS ((int));
302 static void s_change_sec
PARAMS ((int));
303 static void s_cons
PARAMS ((int));
304 static void s_err
PARAMS ((int));
305 static void s_extern
PARAMS ((int));
306 static void s_float_cons
PARAMS ((int));
307 static void s_option
PARAMS ((int));
308 static void s_mipsset
PARAMS ((int));
309 static void s_mips_space
PARAMS ((int));
310 static void s_abicalls
PARAMS ((int));
311 static void s_cpload
PARAMS ((int));
312 static void s_cprestore
PARAMS ((int));
313 static void s_gpword
PARAMS ((int));
314 static void s_cpadd
PARAMS ((int));
315 #ifndef ECOFF_DEBUGGING
316 static void md_obj_begin
PARAMS ((void));
317 static void md_obj_end
PARAMS ((void));
318 static long get_number
PARAMS ((void));
319 static void s_ent
PARAMS ((int));
320 static void s_mipsend
PARAMS ((int));
321 static void s_file
PARAMS ((int));
323 static void s_frame
PARAMS ((int));
324 static void s_loc
PARAMS ((int));
325 static void s_mask
PARAMS ((char));
331 The following pseudo-ops from the Kane and Heinrich MIPS book
332 should be defined here, but are currently unsupported: .alias,
333 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
335 The following pseudo-ops from the Kane and Heinrich MIPS book are
336 specific to the type of debugging information being generated, and
337 should be defined by the object format: .aent, .begin, .bend,
338 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
341 The following pseudo-ops from the Kane and Heinrich MIPS book are
342 not MIPS CPU specific, but are also not specific to the object file
343 format. This file is probably the best place to define them, but
344 they are not currently supported: .asm0, .endr, .lab, .repeat,
345 .struct, .weakext. */
347 const pseudo_typeS md_pseudo_table
[] =
349 /* MIPS specific pseudo-ops. */
350 {"option", s_option
, 0},
351 {"set", s_mipsset
, 0},
352 {"rdata", s_change_sec
, 'r'},
353 {"sdata", s_change_sec
, 's'},
354 {"livereg", s_ignore
, 0},
355 { "abicalls", s_abicalls
, 0},
356 { "cpload", s_cpload
, 0},
357 { "cprestore", s_cprestore
, 0},
358 { "gpword", s_gpword
, 0},
359 { "cpadd", s_cpadd
, 0},
361 /* Relatively generic pseudo-ops that happen to be used on MIPS
363 {"asciiz", s_stringer
, 1},
364 {"bss", s_change_sec
, 'b'},
367 {"dword", s_cons
, 3},
369 /* These pseudo-ops are defined in read.c, but must be overridden
370 here for one reason or another. */
371 {"align", s_align
, 0},
372 {"ascii", s_stringer
, 0},
373 {"asciz", s_stringer
, 1},
375 {"data", s_change_sec
, 'd'},
376 {"double", s_float_cons
, 'd'},
377 {"extern", s_extern
, 0},
378 {"float", s_float_cons
, 'f'},
379 {"space", s_mips_space
, 0},
380 {"text", s_change_sec
, 't'},
383 #ifndef ECOFF_DEBUGGING
384 /* These pseudo-ops should be defined by the object file format.
385 However, a.out doesn't support them, so we have versions here. */
387 {"bgnb", s_ignore
, 0},
388 {"end", s_mipsend
, 0},
389 {"endb", s_ignore
, 0},
392 {"fmask", s_ignore
, 'F'},
393 {"frame", s_ignore
, 0},
394 {"loc", s_ignore
, 0},
395 {"mask", s_ignore
, 'R'},
396 {"verstamp", s_ignore
, 0},
403 const relax_typeS md_relax_table
[] =
409 static char *expr_end
;
411 static expressionS imm_expr
;
412 static expressionS offset_expr
;
413 static bfd_reloc_code_real_type imm_reloc
;
414 static bfd_reloc_code_real_type offset_reloc
;
416 /* FIXME: This should be handled in a different way. */
417 extern int target_big_endian
;
420 * This function is called once, at assembler startup time. It should
421 * set up all the tables, etc. that the MD part of the assembler will need.
427 register const char *retval
= NULL
;
428 register unsigned int i
= 0;
432 if (strcmp (TARGET_CPU
, "mips") == 0)
434 else if (strcmp (TARGET_CPU
, "r6000") == 0
435 || strcmp (TARGET_CPU
, "mips2") == 0)
437 else if (strcmp (TARGET_CPU
, "mips64") == 0
438 || strcmp (TARGET_CPU
, "r4000") == 0
439 || strcmp (TARGET_CPU
, "mips3") == 0)
448 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
451 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
454 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
458 as_warn ("Could not set architecture and machine");
460 op_hash
= hash_new ();
462 for (i
= 0; i
< NUMOPCODES
;)
464 const char *name
= mips_opcodes
[i
].name
;
466 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
469 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
470 mips_opcodes
[i
].name
, retval
);
471 as_fatal ("Broken assembler. No assembly attempted.");
475 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
476 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
477 != mips_opcodes
[i
].match
))
479 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
480 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
481 as_fatal ("Broken assembler. No assembly attempted.");
485 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
488 mips_no_prev_insn ();
496 /* set the default alignment for the text section (2**2) */
497 record_alignment (text_section
, 2);
499 /* FIXME: This should be handled in a different way. */
500 target_big_endian
= byte_order
== BIG_ENDIAN
;
503 bfd_set_gp_size (stdoutput
, g_switch_value
);
507 /* Sections must be aligned to 16 byte boundaries. */
508 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
509 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
510 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
512 /* Create a .reginfo section for register masks and a .mdebug
513 section for debugging information. */
521 sec
= subseg_new (".reginfo", (subsegT
) 0);
523 /* I don't know why this section should be loaded, but the ABI
524 says that SHF_ALLOC should be set. */
525 (void) bfd_set_section_flags (stdoutput
, sec
,
526 (SEC_ALLOC
| SEC_LOAD
527 | SEC_READONLY
| SEC_DATA
));
528 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
530 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
532 #ifdef ECOFF_DEBUGGING
533 sec
= subseg_new (".mdebug", (subsegT
) 0);
534 (void) bfd_set_section_flags (stdoutput
, sec
,
535 SEC_HAS_CONTENTS
| SEC_READONLY
);
536 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
539 subseg_set (seg
, subseg
);
543 #ifndef ECOFF_DEBUGGING
551 #ifndef ECOFF_DEBUGGING
560 struct mips_cl_insn insn
;
562 imm_expr
.X_op
= O_absent
;
563 offset_expr
.X_op
= O_absent
;
565 mips_ip (str
, &insn
);
568 as_bad ("%s `%s'", insn_error
, str
);
571 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
577 if (imm_expr
.X_op
!= O_absent
)
578 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
579 else if (offset_expr
.X_op
!= O_absent
)
580 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
582 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
586 /* See whether instruction IP reads register REG. If FPR is non-zero,
587 REG is a floating point register. */
590 insn_uses_reg (ip
, reg
, fpr
)
591 struct mips_cl_insn
*ip
;
595 /* Don't report on general register 0, since it never changes. */
596 if (! fpr
&& reg
== 0)
601 /* If we are called with either $f0 or $f1, we must check $f0.
602 This is not optimal, because it will introduce an unnecessary
603 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
604 need to distinguish reading both $f0 and $f1 or just one of
605 them. Note that we don't have to check the other way,
606 because there is no instruction that sets both $f0 and $f1
607 and requires a delay. */
608 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
609 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
610 == (reg
&~ (unsigned) 1)))
612 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
613 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
614 == (reg
&~ (unsigned) 1)))
619 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
620 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
622 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
623 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
630 /* Output an instruction. PLACE is where to put the instruction; if
631 it is NULL, this uses frag_more to get room. IP is the instruction
632 information. ADDRESS_EXPR is an operand of the instruction to be
633 used with RELOC_TYPE. */
636 append_insn (place
, ip
, address_expr
, reloc_type
)
638 struct mips_cl_insn
*ip
;
639 expressionS
*address_expr
;
640 bfd_reloc_code_real_type reloc_type
;
642 register unsigned long prev_pinfo
, pinfo
;
647 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
648 pinfo
= ip
->insn_mo
->pinfo
;
650 if (place
== NULL
&& ! mips_noreorder
)
652 /* If the previous insn required any delay slots, see if we need
653 to insert a NOP or two. There are eight kinds of possible
654 hazards, of which an instruction can have at most one type.
655 (1) a load from memory delay
656 (2) a load from a coprocessor delay
657 (3) an unconditional branch delay
658 (4) a conditional branch delay
659 (5) a move to coprocessor register delay
660 (6) a load coprocessor register from memory delay
661 (7) a coprocessor condition code delay
662 (8) a HI/LO special register delay
664 There are a lot of optimizations we could do that we don't.
665 In particular, we do not, in general, reorder instructions.
666 If you use gcc with optimization, it will reorder
667 instructions and generally do much more optimization then we
668 do here; repeating all that work in the assembler would only
669 benefit hand written assembly code, and does not seem worth
672 /* This is how a NOP is emitted. */
673 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
675 /* The previous insn might require a delay slot, depending upon
676 the contents of the current insn. */
677 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
679 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
681 /* A load from a coprocessor or from memory. All load
682 delays delay the use of general register rt for one
683 instruction on the r3000. The r6000 and r4000 use
685 know (prev_pinfo
& INSN_WRITE_GPR_T
);
686 if (mips_optimize
== 0
687 || insn_uses_reg (ip
,
688 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
693 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
695 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
697 /* A generic coprocessor delay. The previous instruction
698 modified a coprocessor general or control register. If
699 it modified a control register, we need to avoid any
700 coprocessor instruction (this is probably not always
701 required, but it sometimes is). If it modified a general
702 register, we avoid using that register.
704 On the r6000 and r4000 loading a coprocessor register
705 from memory is interlocked, and does not require a delay.
707 This case is not handled very well. There is no special
708 knowledge of CP0 handling, and the coprocessors other
709 than the floating point unit are not distinguished at
711 if (prev_pinfo
& INSN_WRITE_FPR_T
)
713 if (mips_optimize
== 0
714 || insn_uses_reg (ip
,
715 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
720 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
722 if (mips_optimize
== 0
723 || insn_uses_reg (ip
,
724 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
731 /* We don't know exactly what the previous instruction
732 does. If the current instruction uses a coprocessor
733 register, we must insert a NOP. If previous
734 instruction may set the condition codes, and the
735 current instruction uses them, we must insert two
737 if (mips_optimize
== 0
738 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
739 && (pinfo
& INSN_READ_COND_CODE
)))
741 else if (pinfo
& INSN_COP
)
745 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
747 /* The previous instruction sets the coprocessor condition
748 codes, but does not require a general coprocessor delay
749 (this means it is a floating point comparison
750 instruction). If this instruction uses the condition
751 codes, we need to insert a single NOP. */
752 if (mips_optimize
== 0
753 || (pinfo
& INSN_READ_COND_CODE
))
756 else if (prev_pinfo
& INSN_READ_LO
)
758 /* The previous instruction reads the LO register; if the
759 current instruction writes to the LO register, we must
761 if (mips_optimize
== 0
762 || (pinfo
& INSN_WRITE_LO
))
765 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
767 /* The previous instruction reads the HI register; if the
768 current instruction writes to the HI register, we must
770 if (mips_optimize
== 0
771 || (pinfo
& INSN_WRITE_HI
))
775 /* There are two cases which require two intervening
776 instructions: 1) setting the condition codes using a move to
777 coprocessor instruction which requires a general coprocessor
778 delay and then reading the condition codes 2) reading the HI
779 or LO register and then writing to it. If we are not already
780 emitting a NOP instruction, we must check for these cases
781 compared to the instruction previous to the previous
784 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
785 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
786 && (pinfo
& INSN_READ_COND_CODE
))
787 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
788 && (pinfo
& INSN_WRITE_LO
))
789 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
790 && (pinfo
& INSN_WRITE_HI
))))
793 /* If we are being given a nop instruction, don't bother with
794 one of the nops we would otherwise output. This will only
795 happen when a nop instruction is used with mips_optimize set
797 if (nops
> 0 && ip
->insn_opcode
== 0)
800 /* Now emit the right number of NOP instructions. */
807 listing_prev_line ();
808 if (insn_label
!= NULL
)
810 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
811 insn_label
->sy_frag
= frag_now
;
812 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
822 if (address_expr
!= NULL
)
824 if (address_expr
->X_op
== O_constant
)
829 ip
->insn_opcode
|= address_expr
->X_add_number
;
833 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
836 case BFD_RELOC_MIPS_JMP
:
837 case BFD_RELOC_16_PCREL_S2
:
846 assert (reloc_type
!= BFD_RELOC_UNUSED
);
848 /* Don't generate a reloc if we are writing into a variant
851 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
853 reloc_type
== BFD_RELOC_16_PCREL_S2
,
858 md_number_to_chars (f
, ip
->insn_opcode
, 4);
860 /* Update the register mask information. */
861 if (pinfo
& INSN_WRITE_GPR_D
)
862 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
863 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
864 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
865 if (pinfo
& INSN_READ_GPR_S
)
866 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
867 if (pinfo
& INSN_WRITE_GPR_31
)
868 mips_gprmask
|= 1 << 31;
869 if (pinfo
& INSN_WRITE_FPR_D
)
870 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
871 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
872 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
873 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
874 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
875 if (pinfo
& INSN_COP
)
877 /* We don't keep enough information to sort these cases out. */
879 /* Never set the bit for $0, which is always zero. */
880 mips_gprmask
&=~ 1 << 0;
882 if (place
== NULL
&& ! mips_noreorder
)
884 /* Filling the branch delay slot is more complex. We try to
885 switch the branch with the previous instruction, which we can
886 do if the previous instruction does not set up a condition
887 that the branch tests and if the branch is not itself the
888 target of any branch. */
889 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
890 || (pinfo
& INSN_COND_BRANCH_DELAY
))
892 if (mips_optimize
< 2
893 /* If we have seen .set nobopt, don't optimize. */
895 /* If we have seen .set volatile or .set nomove, don't
898 /* If we had to emit any NOP instructions, then we
899 already know we can not swap. */
901 /* If we don't even know the previous insn, we can not
904 /* If the previous insn is already in a branch delay
905 slot, then we can not swap. */
906 || prev_insn_is_delay_slot
907 /* If the previous previous insn was in a .set
908 noreorder, we can't swap. Actually, the MIPS
909 assembler will swap in this situation. However, gcc
910 configured -with-gnu-as will generate code like
916 in which we can not swap the bne and INSN. If gcc is
917 not configured -with-gnu-as, it does not output the
918 .set pseudo-ops. We don't have to check
919 prev_insn_unreordered, because prev_insn_valid will
920 be 0 in that case. We don't want to use
921 prev_prev_insn_valid, because we do want to be able
922 to swap at the start of a function. */
923 || prev_prev_insn_unreordered
924 /* If the branch is itself the target of a branch, we
925 can not swap. We cheat on this; all we check for is
926 whether there is a label on this instruction. If
927 there are any branches to anything other than a
928 label, users must use .set noreorder. */
929 || insn_label
!= NULL
930 /* If the previous instruction is in a variant frag, we
931 can not do the swap. */
932 || prev_insn_frag
->fr_type
== rs_machine_dependent
933 /* If the branch reads the condition codes, we don't
934 even try to swap, because in the sequence
939 we can not swap, and I don't feel like handling that
941 || (pinfo
& INSN_READ_COND_CODE
)
942 /* We can not swap with an instruction that requires a
943 delay slot, becase the target of the branch might
944 interfere with that instruction. */
946 & (INSN_LOAD_COPROC_DELAY
947 | INSN_COPROC_MOVE_DELAY
948 | INSN_WRITE_COND_CODE
953 & (INSN_LOAD_MEMORY_DELAY
954 | INSN_COPROC_MEMORY_DELAY
)))
955 /* We can not swap with a branch instruction. */
957 & (INSN_UNCOND_BRANCH_DELAY
958 | INSN_COND_BRANCH_DELAY
959 | INSN_COND_BRANCH_LIKELY
))
960 /* We do not swap with a trap instruction, since it
961 complicates trap handlers to have the trap
962 instruction be in a delay slot. */
963 || (prev_pinfo
& INSN_TRAP
)
964 /* If the branch reads a register that the previous
965 instruction sets, we can not swap. */
966 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
967 && insn_uses_reg (ip
,
968 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
971 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
972 && insn_uses_reg (ip
,
973 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
976 /* If the branch writes a register that the previous
977 instruction sets, we can not swap (we know that
978 branches write only to RD or to $31). */
979 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
980 && (((pinfo
& INSN_WRITE_GPR_D
)
981 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
982 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
983 || ((pinfo
& INSN_WRITE_GPR_31
)
984 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
987 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
988 && (((pinfo
& INSN_WRITE_GPR_D
)
989 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
990 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
991 || ((pinfo
& INSN_WRITE_GPR_31
)
992 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
995 /* If the branch writes a register that the previous
996 instruction reads, we can not swap (we know that
997 branches only write to RD or to $31). */
998 || ((pinfo
& INSN_WRITE_GPR_D
)
999 && insn_uses_reg (&prev_insn
,
1000 ((ip
->insn_opcode
>> OP_SH_RD
)
1003 || ((pinfo
& INSN_WRITE_GPR_31
)
1004 && insn_uses_reg (&prev_insn
, 31, 0))
1005 /* If the previous previous instruction has a load
1006 delay, and sets a register that the branch reads, we
1008 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1010 && (prev_prev_insn
.insn_mo
->pinfo
1011 & INSN_LOAD_MEMORY_DELAY
)))
1012 && insn_uses_reg (ip
,
1013 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1017 /* We could do even better for unconditional branches to
1018 portions of this object file; we could pick up the
1019 instruction at the destination, put it in the delay
1020 slot, and bump the destination address. */
1022 /* Update the previous insn information. */
1023 prev_prev_insn
= *ip
;
1024 prev_insn
.insn_mo
= &dummy_opcode
;
1031 /* It looks like we can actually do the swap. */
1032 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1033 memcpy (temp
, prev_f
, 4);
1034 memcpy (prev_f
, f
, 4);
1035 memcpy (f
, temp
, 4);
1038 prev_insn_fixp
->fx_frag
= frag_now
;
1039 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1043 fixp
->fx_frag
= prev_insn_frag
;
1044 fixp
->fx_where
= prev_insn_where
;
1046 /* Update the previous insn information; leave prev_insn
1048 prev_prev_insn
= *ip
;
1050 prev_insn_is_delay_slot
= 1;
1052 /* If that was an unconditional branch, forget the previous
1053 insn information. */
1054 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1056 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1057 prev_insn
.insn_mo
= &dummy_opcode
;
1060 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1062 /* We don't yet optimize a branch likely. What we should do
1063 is look at the target, copy the instruction found there
1064 into the delay slot, and increment the branch to jump to
1065 the next instruction. */
1067 /* Update the previous insn information. */
1068 prev_prev_insn
= *ip
;
1069 prev_insn
.insn_mo
= &dummy_opcode
;
1073 /* Update the previous insn information. */
1075 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1077 prev_prev_insn
= prev_insn
;
1080 /* Any time we see a branch, we always fill the delay slot
1081 immediately; since this insn is not a branch, we know it
1082 is not in a delay slot. */
1083 prev_insn_is_delay_slot
= 0;
1086 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1087 prev_insn_unreordered
= 0;
1088 prev_insn_frag
= frag_now
;
1089 prev_insn_where
= f
- frag_now
->fr_literal
;
1090 prev_insn_fixp
= fixp
;
1091 prev_insn_valid
= 1;
1094 /* We just output an insn, so the next one doesn't have a label. */
1098 /* This function forgets that there was any previous instruction or
1102 mips_no_prev_insn ()
1104 prev_insn
.insn_mo
= &dummy_opcode
;
1105 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1106 prev_insn_valid
= 0;
1107 prev_insn_is_delay_slot
= 0;
1108 prev_insn_unreordered
= 0;
1109 prev_prev_insn_unreordered
= 0;
1113 /* This function must be called whenever we turn on noreorder or emit
1114 something other than instructions. It inserts any NOPS which might
1115 be needed by the previous instruction, and clears the information
1116 kept for the previous instructions. */
1121 if (! mips_noreorder
)
1126 if ((prev_insn
.insn_mo
->pinfo
1127 & (INSN_LOAD_COPROC_DELAY
1128 | INSN_COPROC_MOVE_DELAY
1129 | INSN_WRITE_COND_CODE
1133 && (prev_insn
.insn_mo
->pinfo
1134 & (INSN_LOAD_MEMORY_DELAY
1135 | INSN_COPROC_MEMORY_DELAY
))))
1138 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1139 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1140 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1143 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1144 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1145 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1150 if (insn_label
!= NULL
)
1152 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1153 insn_label
->sy_frag
= frag_now
;
1154 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1157 mips_no_prev_insn ();
1161 /* Build an instruction created by a macro expansion. This is passed
1162 a pointer to the count of instructions created so far, an
1163 expression, the name of the instruction to build, an operand format
1164 string, and corresponding arguments. */
1168 macro_build (char *place
,
1174 #else /* ! defined (NO_STDARG) */
1176 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1183 #endif /* ! defined (NO_STDARG) */
1185 struct mips_cl_insn insn
;
1186 bfd_reloc_code_real_type r
;
1190 va_start (args
, fmt
);
1196 * If the macro is about to expand into a second instruction,
1197 * print a warning if needed. We need to pass ip as a parameter
1198 * to generate a better warning message here...
1200 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1201 as_warn ("Macro instruction expanded into multiple instructions");
1204 *counter
+= 1; /* bump instruction counter */
1206 r
= BFD_RELOC_UNUSED
;
1207 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1208 assert (insn
.insn_mo
);
1209 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1211 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1212 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1215 assert (insn
.insn_mo
->name
);
1216 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1218 insn
.insn_opcode
= insn
.insn_mo
->match
;
1234 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1240 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1245 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1250 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1257 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1261 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1265 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1272 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1278 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1279 assert (r
== BFD_RELOC_MIPS_GPREL
1280 || r
== BFD_RELOC_MIPS_LITERAL
1281 || r
== BFD_RELOC_LO16
1282 || r
== BFD_RELOC_MIPS_GOT16
1283 || r
== BFD_RELOC_MIPS_CALL16
);
1287 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1288 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1293 assert (ep
!= NULL
);
1295 * This allows macro() to pass an immediate expression for
1296 * creating short branches without creating a symbol.
1297 * Note that the expression still might come from the assembly
1298 * input, in which case the value is not checked for range nor
1299 * is a relocation entry generated (yuck).
1301 if (ep
->X_op
== O_constant
)
1303 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1307 r
= BFD_RELOC_16_PCREL_S2
;
1311 assert (ep
!= NULL
);
1312 r
= BFD_RELOC_MIPS_JMP
;
1321 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1323 append_insn (place
, &insn
, ep
, r
);
1327 * Generate a "lui" instruction.
1330 macro_build_lui (place
, counter
, ep
, regnum
)
1336 expressionS high_expr
;
1337 struct mips_cl_insn insn
;
1338 bfd_reloc_code_real_type r
;
1339 CONST
char *name
= "lui";
1340 CONST
char *fmt
= "t,u";
1346 high_expr
.X_op
= O_constant
;
1347 high_expr
.X_add_number
= 0;
1350 if (high_expr
.X_op
== O_constant
)
1352 /* we can compute the instruction now without a relocation entry */
1353 if (high_expr
.X_add_number
& 0x8000)
1354 high_expr
.X_add_number
+= 0x10000;
1355 high_expr
.X_add_number
=
1356 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1357 r
= BFD_RELOC_UNUSED
;
1361 assert (ep
->X_op
== O_symbol
);
1362 /* _gp_disp is a special case, used from s_cpload. */
1363 assert (mips_pic
== 0
1364 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1365 r
= BFD_RELOC_HI16_S
;
1369 * If the macro is about to expand into a second instruction,
1370 * print a warning if needed. We need to pass ip as a parameter
1371 * to generate a better warning message here...
1373 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1374 as_warn ("Macro instruction expanded into multiple instructions");
1377 *counter
+= 1; /* bump instruction counter */
1379 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1380 assert (insn
.insn_mo
);
1381 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1382 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1384 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1385 if (r
== BFD_RELOC_UNUSED
)
1387 insn
.insn_opcode
|= high_expr
.X_add_number
;
1388 append_insn (place
, &insn
, NULL
, r
);
1391 append_insn (place
, &insn
, &high_expr
, r
);
1395 * Generates code to set the $at register to true (one)
1396 * if reg is less than the immediate expression.
1399 set_at (counter
, reg
, unsignedp
)
1404 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1405 macro_build ((char *) NULL
, counter
, &imm_expr
,
1406 unsignedp
? "sltiu" : "slti",
1407 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1410 load_register (counter
, AT
, &imm_expr
);
1411 macro_build ((char *) NULL
, counter
, NULL
,
1412 unsignedp
? "sltu" : "slt",
1413 "d,v,t", AT
, reg
, AT
);
1417 /* Warn if an expression is not a constant. */
1420 check_absolute_expr (ip
, ex
)
1421 struct mips_cl_insn
*ip
;
1424 if (ex
->X_op
!= O_constant
)
1425 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1429 * This routine generates the least number of instructions neccessary to load
1430 * an absolute expression value into a register.
1433 load_register (counter
, reg
, ep
)
1438 assert (ep
->X_op
== O_constant
);
1439 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1440 macro_build ((char *) NULL
, counter
, ep
,
1441 mips_isa
< 3 ? "addiu" : "daddiu",
1442 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1443 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1444 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1445 (int) BFD_RELOC_LO16
);
1446 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1447 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1448 == ~ (offsetT
) 0x7fffffff))
1450 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1451 if ((ep
->X_add_number
& 0xffff) != 0)
1452 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1453 (int) BFD_RELOC_LO16
);
1455 else if (mips_isa
< 3)
1457 as_bad ("Number larger than 32 bits");
1458 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1459 (int) BFD_RELOC_LO16
);
1464 expressionS hi32
, lo32
;
1468 hi32
.X_add_number
>>= shift
;
1469 hi32
.X_add_number
&= 0xffffffff;
1470 if ((hi32
.X_add_number
& 0x80000000) != 0)
1471 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1472 load_register (counter
, reg
, &hi32
);
1474 lo32
.X_add_number
&= 0xffffffff;
1475 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1476 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1482 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1485 mid16
.X_add_number
>>= 16;
1486 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1487 reg
, (int) BFD_RELOC_LO16
);
1488 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1491 if ((lo32
.X_add_number
& 0xffff) != 0)
1492 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1493 (int) BFD_RELOC_LO16
);
1497 /* Load an address into a register. */
1500 load_address (counter
, reg
, ep
)
1507 if (ep
->X_op
!= O_constant
1508 && ep
->X_op
!= O_symbol
)
1510 as_bad ("expression too complex");
1511 ep
->X_op
= O_constant
;
1514 if (ep
->X_op
== O_constant
)
1515 load_register (counter
, reg
, ep
);
1516 else if (mips_pic
== 0)
1518 /* If this is a reference to a GP relative symbol, we want
1519 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1521 lui $reg,$gp,<sym> (BFD_RELOC_HI16_S)
1522 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1523 If we have an addend, we always use the latter form. */
1524 if (ep
->X_add_number
!= 0)
1529 macro_build ((char *) NULL
, counter
, ep
,
1530 mips_isa
< 3 ? "addiu" : "daddiu",
1531 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1532 p
= frag_var (rs_machine_dependent
, 8, 0,
1533 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1534 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1536 macro_build_lui (p
, counter
, ep
, reg
);
1539 macro_build (p
, counter
, ep
,
1540 mips_isa
< 3 ? "addiu" : "daddiu",
1541 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1547 /* If this is a reference to an external symbol, we want
1548 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1550 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1552 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1553 If there is a constant, it must be added in afterward. */
1554 ex
.X_add_number
= ep
->X_add_number
;
1555 ep
->X_add_number
= 0;
1557 macro_build ((char *) NULL
, counter
, ep
,
1558 mips_isa
< 3 ? "lw" : "ld",
1559 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1560 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1561 p
= frag_var (rs_machine_dependent
, 4, 0,
1562 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1563 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1564 macro_build (p
, counter
, ep
,
1565 mips_isa
< 3 ? "addiu" : "daddiu",
1566 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1567 if (ex
.X_add_number
!= 0)
1569 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1570 as_bad ("PIC code offset overflow (max 16 signed bits)");
1571 ex
.X_op
= O_constant
;
1572 macro_build (p
, counter
, &ex
,
1573 mips_isa
< 3 ? "addiu" : "daddiu",
1574 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1581 * This routine implements the seemingly endless macro or synthesized
1582 * instructions and addressing modes in the mips assembly language. Many
1583 * of these macros are simple and are similar to each other. These could
1584 * probably be handled by some kind of table or grammer aproach instead of
1585 * this verbose method. Others are not simple macros but are more like
1586 * optimizing code generation.
1587 * One interesting optimization is when several store macros appear
1588 * consecutivly that would load AT with the upper half of the same address.
1589 * The ensuing load upper instructions are ommited. This implies some kind
1590 * of global optimization. We currently only optimize within a single macro.
1591 * For many of the load and store macros if the address is specified as a
1592 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1593 * first load register 'at' with zero and use it as the base register. The
1594 * mips assembler simply uses register $zero. Just one tiny optimization
1599 struct mips_cl_insn
*ip
;
1601 register int treg
, sreg
, dreg
, breg
;
1614 bfd_reloc_code_real_type r
;
1617 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1618 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1619 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1620 mask
= ip
->insn_mo
->mask
;
1622 expr1
.X_op
= O_constant
;
1623 expr1
.X_op_symbol
= NULL
;
1624 expr1
.X_add_symbol
= NULL
;
1625 expr1
.X_add_number
= 1;
1637 mips_emit_delays ();
1639 mips_any_noreorder
= 1;
1641 expr1
.X_add_number
= 8;
1642 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1644 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1646 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1647 macro_build ((char *) NULL
, &icnt
, NULL
,
1648 dbl
? "dsub" : "sub",
1649 "d,v,t", dreg
, 0, sreg
);
1672 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1674 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1675 (int) BFD_RELOC_LO16
);
1678 load_register (&icnt
, AT
, &imm_expr
);
1679 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1698 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1700 if (mask
!= M_NOR_I
)
1701 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1702 sreg
, (int) BFD_RELOC_LO16
);
1705 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1706 treg
, sreg
, (int) BFD_RELOC_LO16
);
1707 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1713 load_register (&icnt
, AT
, &imm_expr
);
1714 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1731 if (imm_expr
.X_add_number
== 0)
1733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1737 load_register (&icnt
, AT
, &imm_expr
);
1738 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1747 likely
? "bgezl" : "bgez",
1753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1754 likely
? "blezl" : "blez",
1758 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1759 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1760 likely
? "beql" : "beq",
1767 /* check for > max integer */
1768 maxnum
= 0x7fffffff;
1776 if (imm_expr
.X_add_number
>= maxnum
)
1779 /* result is always false */
1782 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1783 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1787 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1788 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1793 imm_expr
.X_add_number
++;
1797 if (mask
== M_BGEL_I
)
1799 if (imm_expr
.X_add_number
== 0)
1801 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1802 likely
? "bgezl" : "bgez",
1806 if (imm_expr
.X_add_number
== 1)
1808 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1809 likely
? "bgtzl" : "bgtz",
1813 maxnum
= 0x7fffffff;
1821 maxnum
= - maxnum
- 1;
1822 if (imm_expr
.X_add_number
<= maxnum
)
1825 /* result is always true */
1826 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1830 set_at (&icnt
, sreg
, 0);
1831 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1832 likely
? "beql" : "beq",
1843 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1844 likely
? "beql" : "beq",
1848 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1850 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1851 likely
? "beql" : "beq",
1858 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1860 imm_expr
.X_add_number
++;
1864 if (mask
== M_BGEUL_I
)
1866 if (imm_expr
.X_add_number
== 0)
1868 if (imm_expr
.X_add_number
== 1)
1870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1871 likely
? "bnel" : "bne",
1875 set_at (&icnt
, sreg
, 1);
1876 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1877 likely
? "beql" : "beq",
1886 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1887 likely
? "bgtzl" : "bgtz",
1893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1894 likely
? "bltzl" : "bltz",
1898 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1899 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1900 likely
? "bnel" : "bne",
1909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1910 likely
? "bnel" : "bne",
1916 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1918 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1919 likely
? "bnel" : "bne",
1928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1929 likely
? "blezl" : "blez",
1935 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1936 likely
? "bgezl" : "bgez",
1940 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1941 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1942 likely
? "beql" : "beq",
1949 maxnum
= 0x7fffffff;
1957 if (imm_expr
.X_add_number
>= maxnum
)
1959 imm_expr
.X_add_number
++;
1963 if (mask
== M_BLTL_I
)
1965 if (imm_expr
.X_add_number
== 0)
1967 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1968 likely
? "bltzl" : "bltz",
1972 if (imm_expr
.X_add_number
== 1)
1974 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1975 likely
? "blezl" : "blez",
1979 set_at (&icnt
, sreg
, 0);
1980 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1981 likely
? "bnel" : "bne",
1990 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1991 likely
? "beql" : "beq",
1997 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1999 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2000 likely
? "beql" : "beq",
2007 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2009 imm_expr
.X_add_number
++;
2013 if (mask
== M_BLTUL_I
)
2015 if (imm_expr
.X_add_number
== 0)
2017 if (imm_expr
.X_add_number
== 1)
2019 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2020 likely
? "beql" : "beq",
2024 set_at (&icnt
, sreg
, 1);
2025 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2026 likely
? "bnel" : "bne",
2035 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2036 likely
? "bltzl" : "bltz",
2042 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2043 likely
? "bgtzl" : "bgtz",
2047 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2049 likely
? "bnel" : "bne",
2060 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2061 likely
? "bnel" : "bne",
2065 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2068 likely
? "bnel" : "bne",
2084 as_warn ("Divide by zero.");
2085 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2089 mips_emit_delays ();
2091 mips_any_noreorder
= 1;
2092 macro_build ((char *) NULL
, &icnt
, NULL
,
2093 dbl
? "ddiv" : "div",
2094 "z,s,t", sreg
, treg
);
2095 expr1
.X_add_number
= 8;
2096 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2097 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2098 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2099 expr1
.X_add_number
= -1;
2100 macro_build ((char *) NULL
, &icnt
, &expr1
,
2101 dbl
? "daddiu" : "addiu",
2102 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2103 expr1
.X_add_number
= dbl
? 20 : 16;
2104 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2107 expr1
.X_add_number
= 1;
2108 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2109 (int) BFD_RELOC_LO16
);
2110 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2115 expr1
.X_add_number
= 0x80000000;
2116 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2118 expr1
.X_add_number
= 8;
2119 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2120 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2121 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2123 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2162 if (imm_expr
.X_add_number
== 0)
2164 as_warn ("Divide by zero.");
2165 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2168 if (imm_expr
.X_add_number
== 1)
2170 if (strcmp (s2
, "mflo") == 0)
2171 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2174 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2177 if (imm_expr
.X_add_number
== -1
2178 && s
[strlen (s
) - 1] != 'u')
2180 if (strcmp (s2
, "mflo") == 0)
2183 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2186 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2190 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2194 load_register (&icnt
, AT
, &imm_expr
);
2195 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2196 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2215 mips_emit_delays ();
2217 mips_any_noreorder
= 1;
2218 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2219 expr1
.X_add_number
= 8;
2220 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2221 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2222 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2224 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2228 /* Load the address of a symbol into a register. If M_LA_AB, we
2229 then add a base register to it. */
2230 if (offset_expr
.X_op
!= O_symbol
2231 && offset_expr
.X_op
!= O_constant
)
2233 as_bad ("expression too complex");
2234 offset_expr
.X_op
= O_constant
;
2248 if (offset_expr
.X_op
== O_constant
)
2249 load_register (&icnt
, tempreg
, &offset_expr
);
2250 else if (mips_pic
== 0)
2252 /* If this is a reference to an GP relative symbol, we want
2253 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2255 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2256 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2257 If we have a constant, we need two instructions anyhow,
2258 so we may as well always use the latter form. */
2259 if (offset_expr
.X_add_number
!= 0)
2264 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2265 mips_isa
< 3 ? "addiu" : "daddiu",
2266 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2267 p
= frag_var (rs_machine_dependent
, 8, 0,
2268 RELAX_ENCODE (4, 8, 0, 4, 0,
2269 mips_warn_about_macros
),
2270 offset_expr
.X_add_symbol
, (long) 0,
2273 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2276 macro_build (p
, &icnt
, &offset_expr
,
2277 mips_isa
< 3 ? "addiu" : "daddiu",
2278 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2282 /* If this is a reference to an external symbol, and there
2283 is no constant, we want
2284 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2285 For a local symbol, we want
2286 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2288 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2290 If we have a small constant, and this is a reference to
2291 an external symbol, we want
2292 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2294 addiu $tempreg,$tempreg,<constant>
2295 For a local symbol, we want the same instruction
2296 sequence, but we output a BFD_RELOC_LO16 reloc on the
2299 If we have a large constant, and this is a reference to
2300 an external symbol, we want
2301 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2302 lui $at,<hiconstant>
2303 addiu $at,$at,<loconstant>
2304 addu $tempreg,$tempreg,$at
2305 For a local symbol, we want the same instruction
2306 sequence, but we output a BFD_RELOC_LO16 reloc on the
2307 addiu instruction. */
2308 expr1
.X_add_number
= offset_expr
.X_add_number
;
2309 offset_expr
.X_add_number
= 0;
2311 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2312 mips_isa
< 3 ? "lw" : "ld",
2313 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2314 if (expr1
.X_add_number
== 0)
2322 /* We're going to put in an addu instruction using
2323 tempreg, so we may as well insert the nop right
2325 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2329 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2330 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2332 ? mips_warn_about_macros
2334 offset_expr
.X_add_symbol
, (long) 0,
2338 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2341 macro_build (p
, &icnt
, &expr1
,
2342 mips_isa
< 3 ? "addiu" : "daddiu",
2343 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2344 /* FIXME: If breg == 0, and the next instruction uses
2345 $tempreg, then if this variant case is used an extra
2346 nop will be generated. */
2348 else if (expr1
.X_add_number
>= -0x8000
2349 && expr1
.X_add_number
< 0x8000)
2351 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2353 macro_build ((char *) NULL
, &icnt
, &expr1
,
2354 mips_isa
< 3 ? "addiu" : "daddiu",
2355 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2356 (void) frag_var (rs_machine_dependent
, 0, 0,
2357 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2358 offset_expr
.X_add_symbol
, (long) 0,
2365 /* If we are going to add in a base register, and the
2366 target register and the base register are the same,
2367 then we are using AT as a temporary register. Since
2368 we want to load the constant into AT, we add our
2369 current AT (from the global offset table) and the
2370 register into the register now, and pretend we were
2371 not using a base register. */
2376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2379 mips_isa
< 3 ? "addu" : "daddu",
2380 "d,v,t", treg
, AT
, breg
);
2386 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2387 macro_build ((char *) NULL
, &icnt
, &expr1
,
2388 mips_isa
< 3 ? "addiu" : "daddiu",
2389 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2391 mips_isa
< 3 ? "addu" : "daddu",
2392 "d,v,t", tempreg
, tempreg
, AT
);
2393 (void) frag_var (rs_machine_dependent
, 0, 0,
2394 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2395 offset_expr
.X_add_symbol
, (long) 0,
2402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2403 mips_isa
< 3 ? "addu" : "daddu",
2404 "d,v,t", treg
, tempreg
, breg
);
2412 /* The j instruction may not be used in PIC code, since it
2413 requires an absolute address. We convert it to a b
2416 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2418 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2421 /* The jal instructions must be handled as macros because when
2422 generating PIC code they expand to multi-instruction
2423 sequences. Normally they are simple instructions. */
2430 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2435 /* I only know how to handle pic2. */
2436 assert (mips_pic
== 2);
2438 if (sreg
!= PIC_CALL_REG
)
2439 as_warn ("MIPS PIC call to register other than $25");
2441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
2443 if (mips_cprestore_offset
< 0)
2444 as_warn ("No .cprestore pseudo-op used in PIC code");
2447 expr1
.X_add_number
= mips_cprestore_offset
;
2448 macro_build ((char *) NULL
, &icnt
, &expr1
,
2449 mips_isa
< 3 ? "lw" : "ld",
2450 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2457 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2461 /* I only know how to handle pic2. */
2462 assert (mips_pic
== 2);
2464 /* If this is a reference to an external symbol, we want
2465 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2469 lw $gp,cprestore($sp)
2470 The cprestore value is set using the .cprestore pseudo-op.
2471 If the symbol is not external, we want
2472 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2474 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2477 lw $gp,cprestore($sp)
2480 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2481 mips_isa
< 3 ? "lw" : "ld",
2482 "t,o(b)", PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL16
, GP
);
2483 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2484 p
= frag_var (rs_machine_dependent
, 4, 0,
2485 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2486 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2487 macro_build (p
, &icnt
, &offset_expr
,
2488 mips_isa
< 3 ? "addiu" : "daddiu",
2489 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2490 (int) BFD_RELOC_LO16
);
2491 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "s",
2493 if (mips_cprestore_offset
< 0)
2494 as_warn ("No .cprestore pseudo-op used in PIC code");
2498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2500 expr1
.X_add_number
= mips_cprestore_offset
;
2501 macro_build ((char *) NULL
, &icnt
, &expr1
,
2502 mips_isa
< 3 ? "lw" : "ld",
2503 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2571 if (breg
== treg
|| coproc
)
2640 if (mask
== M_LWC1_AB
2641 || mask
== M_SWC1_AB
2642 || mask
== M_LDC1_AB
2643 || mask
== M_SDC1_AB
2652 if (offset_expr
.X_op
!= O_constant
2653 && offset_expr
.X_op
!= O_symbol
)
2655 as_bad ("expression too complex");
2656 offset_expr
.X_op
= O_constant
;
2659 /* A constant expression in PIC code can be handled just as it
2660 is in non PIC code. */
2662 || offset_expr
.X_op
== O_constant
)
2664 /* If this is a reference to a GP relative symbol, and there
2665 is no base register, we want
2666 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2668 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2669 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2670 If we have a constant, we need two instructions anyhow,
2671 so we always use the latter form.
2673 If we have a base register, and this is a reference to a
2674 GP relative symbol, we want
2675 addu $tempreg,$breg,$gp
2676 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2678 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2679 addu $tempreg,$tempreg,$breg
2680 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2681 With a constant we always use the latter case. */
2684 if (offset_expr
.X_add_number
!= 0)
2689 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2690 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2691 p
= frag_var (rs_machine_dependent
, 8, 0,
2692 RELAX_ENCODE (4, 8, 0, 4, 0,
2693 (mips_warn_about_macros
2694 || (used_at
&& mips_noat
))),
2695 offset_expr
.X_add_symbol
, (long) 0,
2699 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2702 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2703 (int) BFD_RELOC_LO16
, tempreg
);
2707 if (offset_expr
.X_add_number
!= 0)
2712 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2713 mips_isa
< 3 ? "addu" : "daddu",
2714 "d,v,t", tempreg
, breg
, GP
);
2715 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2716 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2717 p
= frag_var (rs_machine_dependent
, 12, 0,
2718 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2719 offset_expr
.X_add_symbol
, (long) 0,
2722 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2725 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2726 mips_isa
< 3 ? "addu" : "daddu",
2727 "d,v,t", tempreg
, tempreg
, breg
);
2730 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2731 (int) BFD_RELOC_LO16
, tempreg
);
2736 /* If this is a reference to an external symbol, we want
2737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2739 <op> $treg,0($tempreg)
2741 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2743 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2744 <op> $treg,0($tempreg)
2745 If there is a base register, we add it to $tempreg before
2746 the <op>. If there is a constant, we stick it in the
2747 <op> instruction. We don't handle constants larger than
2748 16 bits, because we have no way to load the upper 16 bits
2749 (actually, we could handle them for the subset of cases
2750 in which we are not using $at). */
2751 assert (offset_expr
.X_op
== O_symbol
);
2752 expr1
.X_add_number
= offset_expr
.X_add_number
;
2753 offset_expr
.X_add_number
= 0;
2754 if (expr1
.X_add_number
< -0x8000
2755 || expr1
.X_add_number
>= 0x8000)
2756 as_bad ("PIC code offset overflow (max 16 signed bits)");
2758 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2759 mips_isa
< 3 ? "lw" : "ld",
2760 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2762 p
= frag_var (rs_machine_dependent
, 4, 0,
2763 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2764 offset_expr
.X_add_symbol
, (long) 0,
2766 macro_build (p
, &icnt
, &offset_expr
,
2767 mips_isa
< 3 ? "addiu" : "daddiu",
2768 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2770 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2771 mips_isa
< 3 ? "addu" : "daddu",
2772 "d,v,t", tempreg
, tempreg
, breg
);
2773 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2774 (int) BFD_RELOC_LO16
, tempreg
);
2784 load_register (&icnt
, treg
, &imm_expr
);
2790 assert (offset_expr
.X_op
== O_symbol
2791 && strcmp (segment_name (S_GET_SEGMENT
2792 (offset_expr
.X_add_symbol
)),
2794 && offset_expr
.X_add_number
== 0);
2795 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2796 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2800 assert (imm_expr
.X_op
== O_constant
);
2801 load_register (&icnt
, treg
, &imm_expr
);
2806 /* We know that sym is in the .rdata instruction. First we get
2807 the upper 16 bits of the address. */
2810 /* FIXME: This won't work for a 64 bit address. */
2811 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2815 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2816 mips_isa
< 3 ? "lw" : "ld",
2817 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2819 /* Now we load the register(s). */
2821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2822 treg
, (int) BFD_RELOC_LO16
, AT
);
2825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2826 treg
, (int) BFD_RELOC_LO16
, AT
);
2829 /* FIXME: How in the world do we deal with the possible
2831 offset_expr
.X_add_number
+= 4;
2832 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2833 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2842 /* Load a floating point number from the .lit8 section. */
2843 assert (offset_expr
.X_op
== O_symbol
2844 && strcmp (segment_name (S_GET_SEGMENT
2845 (offset_expr
.X_add_symbol
)),
2847 && offset_expr
.X_add_number
== 0);
2850 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2851 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2855 r
= BFD_RELOC_MIPS_LITERAL
;
2860 /* Load the double from the .rdata section. */
2861 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2862 mips_isa
< 3 ? "lw" : "ld",
2863 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2866 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2867 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
2876 /* Even on a big endian machine $fn comes before $fn+1. We have
2877 to adjust when loading from memory. */
2880 assert (mips_isa
< 2);
2881 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2882 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2884 /* FIXME: A possible overflow which I don't know how to deal
2886 offset_expr
.X_add_number
+= 4;
2887 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2888 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2896 * The MIPS assembler seems to check for X_add_number not
2897 * being double aligned and generating:
2900 * addiu at,at,%lo(foo+1)
2903 * But, the resulting address is the same after relocation so why
2904 * generate the extra instruction?
2951 if (offset_expr
.X_op
!= O_symbol
2952 && offset_expr
.X_op
!= O_constant
)
2954 as_bad ("expression too complex");
2955 offset_expr
.X_op
= O_constant
;
2958 /* Even on a big endian machine $fn comes before $fn+1. We have
2959 to adjust when loading from memory. We set coproc if we must
2960 load $fn+1 first. */
2961 if (byte_order
== LITTLE_ENDIAN
)
2965 || offset_expr
.X_op
== O_constant
)
2967 /* If this is a reference to a GP relative symbol, we want
2968 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2969 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
2970 If we have a base register, we use this
2972 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
2973 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
2974 If this is not a GP relative symbol, we want
2975 lui $at,<sym> (BFD_RELOC_HI16_S)
2976 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
2977 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
2978 If there is a base register, we add it to $at after the
2979 lui instruction. If there is a constant, we always use
2981 if (offset_expr
.X_add_number
!= 0)
3000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3001 mips_isa
< 3 ? "addu" : "daddu",
3002 "d,v,t", AT
, breg
, GP
);
3008 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3009 coproc
? treg
+ 1 : treg
,
3010 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3011 offset_expr
.X_add_number
+= 4;
3012 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3013 coproc
? treg
: treg
+ 1,
3014 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3015 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3016 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3017 used_at
&& mips_noat
),
3018 offset_expr
.X_add_symbol
, (long) 0,
3021 /* We just generated two relocs. When tc_gen_reloc
3022 handles this case, it will skip the first reloc and
3023 handle the second. The second reloc already has an
3024 extra addend of 4, which we added above. We must
3025 subtract it out, and then subtract another 4 to make
3026 the first reloc come out right. The second reloc
3027 will come out right because we are going to add 4 to
3028 offset_expr when we build its instruction below. */
3029 offset_expr
.X_add_number
-= 8;
3030 offset_expr
.X_op
= O_constant
;
3032 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3037 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3038 mips_isa
< 3 ? "addu" : "daddu",
3039 "d,v,t", AT
, breg
, AT
);
3043 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3044 coproc
? treg
+ 1 : treg
,
3045 (int) BFD_RELOC_LO16
, AT
);
3048 /* FIXME: How do we handle overflow here? */
3049 offset_expr
.X_add_number
+= 4;
3050 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3051 coproc
? treg
: treg
+ 1,
3052 (int) BFD_RELOC_LO16
, AT
);
3058 /* If this is a reference to an external symbol, we want
3059 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3064 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3066 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3067 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3068 If there is a base register we add it to $at before the
3069 lwc1 instructions. If there is a constant we include it
3070 in the lwc1 instructions. */
3072 expr1
.X_add_number
= offset_expr
.X_add_number
;
3073 offset_expr
.X_add_number
= 0;
3074 if (expr1
.X_add_number
< -0x8000
3075 || expr1
.X_add_number
>= 0x8000 - 4)
3076 as_bad ("PIC code offset overflow (max 16 signed bits)");
3081 frag_grow (16 + off
);
3082 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3083 mips_isa
< 3 ? "lw" : "ld",
3084 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3085 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3087 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3088 mips_isa
< 3 ? "addu" : "daddu",
3089 "d,v,t", AT
, breg
, AT
);
3090 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3091 coproc
? treg
+ 1 : treg
,
3092 (int) BFD_RELOC_LO16
, AT
);
3093 expr1
.X_add_number
+= 4;
3094 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3095 coproc
? treg
: treg
+ 1,
3096 (int) BFD_RELOC_LO16
, AT
);
3097 (void) frag_var (rs_machine_dependent
, 0, 0,
3098 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3099 offset_expr
.X_add_symbol
, (long) 0,
3114 assert (mips_isa
< 3);
3115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3116 (int) BFD_RELOC_LO16
, breg
);
3117 offset_expr
.X_add_number
+= 4;
3118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3119 (int) BFD_RELOC_LO16
, breg
);
3121 #ifdef LOSING_COMPILER
3127 as_warn ("Macro used $at after \".set noat\"");
3132 struct mips_cl_insn
*ip
;
3134 register int treg
, sreg
, dreg
, breg
;
3147 bfd_reloc_code_real_type r
;
3150 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3151 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3152 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3153 mask
= ip
->insn_mo
->mask
;
3155 expr1
.X_op
= O_constant
;
3156 expr1
.X_op_symbol
= NULL
;
3157 expr1
.X_add_symbol
= NULL
;
3158 expr1
.X_add_number
= 1;
3162 #endif /* LOSING_COMPILER */
3167 macro_build ((char *) NULL
, &icnt
, NULL
,
3168 dbl
? "dmultu" : "multu",
3170 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3176 /* The MIPS assembler some times generates shifts and adds. I'm
3177 not trying to be that fancy. GCC should do this for us
3179 load_register (&icnt
, AT
, &imm_expr
);
3180 macro_build ((char *) NULL
, &icnt
, NULL
,
3181 dbl
? "dmult" : "mult",
3183 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3189 mips_emit_delays ();
3191 mips_any_noreorder
= 1;
3192 macro_build ((char *) NULL
, &icnt
, NULL
,
3193 dbl
? "dmult" : "mult",
3195 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3196 macro_build ((char *) NULL
, &icnt
, NULL
,
3197 dbl
? "dsra32" : "sra",
3198 "d,w,<", dreg
, dreg
, 31);
3199 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3200 expr1
.X_add_number
= 8;
3201 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3202 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3203 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3205 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3211 mips_emit_delays ();
3213 mips_any_noreorder
= 1;
3214 macro_build ((char *) NULL
, &icnt
, NULL
,
3215 dbl
? "dmultu" : "multu",
3217 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3218 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3219 expr1
.X_add_number
= 8;
3220 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3221 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3222 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3227 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3228 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3229 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3231 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3235 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3236 imm_expr
.X_add_number
& 0x1f);
3237 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3238 (0 - imm_expr
.X_add_number
) & 0x1f);
3239 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3243 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3244 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3245 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3247 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3251 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3252 imm_expr
.X_add_number
& 0x1f);
3253 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3254 (0 - imm_expr
.X_add_number
) & 0x1f);
3255 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3259 assert (mips_isa
< 2);
3260 /* Even on a big endian machine $fn comes before $fn+1. We have
3261 to adjust when storing to memory. */
3262 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3263 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3264 (int) BFD_RELOC_LO16
, breg
);
3265 offset_expr
.X_add_number
+= 4;
3266 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3267 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3268 (int) BFD_RELOC_LO16
, breg
);
3273 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3274 treg
, (int) BFD_RELOC_LO16
);
3276 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3277 sreg
, (int) BFD_RELOC_LO16
);
3280 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3282 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3283 dreg
, (int) BFD_RELOC_LO16
);
3288 if (imm_expr
.X_add_number
== 0)
3290 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3291 sreg
, (int) BFD_RELOC_LO16
);
3296 as_warn ("Instruction %s: result is always false",
3298 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3301 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3303 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3304 sreg
, (int) BFD_RELOC_LO16
);
3307 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3309 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3310 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3311 mips_isa
< 3 ? "addiu" : "daddiu",
3312 "t,r,j", dreg
, sreg
,
3313 (int) BFD_RELOC_LO16
);
3318 load_register (&icnt
, AT
, &imm_expr
);
3319 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3323 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3324 (int) BFD_RELOC_LO16
);
3329 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3335 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3336 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3337 (int) BFD_RELOC_LO16
);
3340 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3342 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3344 macro_build ((char *) NULL
, &icnt
, &expr1
,
3345 mask
== M_SGE_I
? "slti" : "sltiu",
3346 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3351 load_register (&icnt
, AT
, &imm_expr
);
3352 macro_build ((char *) NULL
, &icnt
, NULL
,
3353 mask
== M_SGE_I
? "slt" : "sltu",
3354 "d,v,t", dreg
, sreg
, AT
);
3357 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3358 (int) BFD_RELOC_LO16
);
3363 case M_SGT
: /* sreg > treg <==> treg < sreg */
3369 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3372 case M_SGT_I
: /* sreg > I <==> I < sreg */
3378 load_register (&icnt
, AT
, &imm_expr
);
3379 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3382 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3388 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3389 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3390 (int) BFD_RELOC_LO16
);
3393 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3399 load_register (&icnt
, AT
, &imm_expr
);
3400 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3401 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3402 (int) BFD_RELOC_LO16
);
3406 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3408 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3409 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3412 load_register (&icnt
, AT
, &imm_expr
);
3413 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3417 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3419 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3420 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3423 load_register (&icnt
, AT
, &imm_expr
);
3424 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3430 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3433 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3437 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3439 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3445 if (imm_expr
.X_add_number
== 0)
3447 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3453 as_warn ("Instruction %s: result is always true",
3455 macro_build ((char *) NULL
, &icnt
, &expr1
,
3456 mips_isa
< 3 ? "addiu" : "daddiu",
3457 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3460 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3462 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3463 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3466 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3468 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3469 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3470 mips_isa
< 3 ? "addiu" : "daddiu",
3471 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3476 load_register (&icnt
, AT
, &imm_expr
);
3477 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3481 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3489 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3491 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3492 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3493 dbl
? "daddi" : "addi",
3494 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3497 load_register (&icnt
, AT
, &imm_expr
);
3498 macro_build ((char *) NULL
, &icnt
, NULL
,
3499 dbl
? "dsub" : "sub",
3500 "d,v,t", dreg
, sreg
, AT
);
3506 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3508 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3509 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3510 dbl
? "daddiu" : "addiu",
3511 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3514 load_register (&icnt
, AT
, &imm_expr
);
3515 macro_build ((char *) NULL
, &icnt
, NULL
,
3516 dbl
? "dsubu" : "subu",
3517 "d,v,t", dreg
, sreg
, AT
);
3538 load_register (&icnt
, AT
, &imm_expr
);
3539 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3544 assert (mips_isa
< 2);
3545 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3546 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3549 * Is the double cfc1 instruction a bug in the mips assembler;
3550 * or is there a reason for it?
3552 mips_emit_delays ();
3554 mips_any_noreorder
= 1;
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3556 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3557 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3558 expr1
.X_add_number
= 3;
3559 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3560 (int) BFD_RELOC_LO16
);
3561 expr1
.X_add_number
= 2;
3562 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3563 (int) BFD_RELOC_LO16
);
3564 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3565 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3566 macro_build ((char *) NULL
, &icnt
, NULL
,
3567 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3568 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3569 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3579 /* avoid load delay */
3580 offset_expr
.X_add_number
+= 1;
3581 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3582 (int) BFD_RELOC_LO16
, breg
);
3583 offset_expr
.X_add_number
-= 1;
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3585 (int) BFD_RELOC_LO16
, breg
);
3586 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3591 /* does this work on a big endian machine? */
3592 offset_expr
.X_add_number
+= 3;
3593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3594 (int) BFD_RELOC_LO16
, breg
);
3595 offset_expr
.X_add_number
-= 3;
3596 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3597 (int) BFD_RELOC_LO16
, breg
);
3603 load_address (&icnt
, AT
, &offset_expr
);
3604 if (mask
== M_ULW_A
)
3606 expr1
.X_add_number
= 3;
3607 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3608 (int) BFD_RELOC_LO16
, AT
);
3609 expr1
.X_add_number
= 0;
3610 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3611 (int) BFD_RELOC_LO16
, AT
);
3615 macro_build ((char *) NULL
, &icnt
, &expr1
,
3616 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3617 (int) BFD_RELOC_LO16
, AT
);
3618 expr1
.X_add_number
= 0;
3619 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3620 (int) BFD_RELOC_LO16
, AT
);
3621 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3623 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3630 (int) BFD_RELOC_LO16
, breg
);
3631 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3632 offset_expr
.X_add_number
+= 1;
3633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3634 (int) BFD_RELOC_LO16
, breg
);
3638 offset_expr
.X_add_number
+= 3;
3639 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3640 (int) BFD_RELOC_LO16
, breg
);
3641 offset_expr
.X_add_number
-= 3;
3642 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3643 (int) BFD_RELOC_LO16
, breg
);
3648 load_address (&icnt
, AT
, &offset_expr
);
3649 if (mask
== M_USW_A
)
3651 expr1
.X_add_number
= 3;
3652 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3653 (int) BFD_RELOC_LO16
, AT
);
3654 expr1
.X_add_number
= 0;
3655 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3656 (int) BFD_RELOC_LO16
, AT
);
3660 expr1
.X_add_number
= 0;
3661 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3662 (int) BFD_RELOC_LO16
, AT
);
3663 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3665 expr1
.X_add_number
= 1;
3666 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3667 (int) BFD_RELOC_LO16
, AT
);
3668 expr1
.X_add_number
= 0;
3669 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3670 (int) BFD_RELOC_LO16
, AT
);
3671 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3673 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3679 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3683 as_warn ("Macro used $at after \".set noat\"");
3688 This routine assembles an instruction into its binary format. As a side
3689 effect it sets one of the global variables imm_reloc or offset_reloc to the
3690 type of relocation to do if one of the operands is an address expression.
3695 struct mips_cl_insn
*ip
;
3700 struct mips_opcode
*insn
;
3703 unsigned int lastregno
= 0;
3708 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3720 as_warn ("Unknown opcode: `%s'", str
);
3723 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3725 as_warn ("`%s' not in hash table.", str
);
3726 insn_error
= "ERROR: Unrecognized opcode";
3734 assert (strcmp (insn
->name
, str
) == 0);
3736 if (insn
->pinfo
== INSN_MACRO
)
3737 insn_isa
= insn
->match
;
3738 else if (insn
->pinfo
& INSN_ISA2
)
3740 else if (insn
->pinfo
& INSN_ISA3
)
3745 if (insn_isa
> mips_isa
)
3747 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
3748 && strcmp (insn
->name
, insn
[1].name
) == 0)
3753 insn_error
= "ERROR: instruction not supported on this processor";
3758 ip
->insn_opcode
= insn
->match
;
3759 for (args
= insn
->args
;; ++args
)
3765 case '\0': /* end of args */
3778 ip
->insn_opcode
|= lastregno
<< 21;
3783 ip
->insn_opcode
|= lastregno
<< 16;
3787 ip
->insn_opcode
|= lastregno
<< 11;
3793 /* handle optional base register.
3794 Either the base register is omitted or
3795 we must have a left paren. */
3796 /* this is dependent on the next operand specifier
3797 is a 'b' for base register */
3798 assert (args
[1] == 'b');
3802 case ')': /* these must match exactly */
3807 case '<': /* must be at least one digit */
3809 * According to the manual, if the shift amount is greater
3810 * than 31 or less than 0 the the shift amount should be
3811 * mod 32. In reality the mips assembler issues an error.
3812 * We issue a warning and mask out all but the low 5 bits.
3814 my_getExpression (&imm_expr
, s
);
3815 check_absolute_expr (ip
, &imm_expr
);
3816 if ((unsigned long) imm_expr
.X_add_number
> 31)
3818 as_warn ("Improper shift amount (%ld)",
3819 (long) imm_expr
.X_add_number
);
3820 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
3822 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3823 imm_expr
.X_op
= O_absent
;
3827 case '>': /* shift amount minus 32 */
3828 my_getExpression (&imm_expr
, s
);
3829 check_absolute_expr (ip
, &imm_expr
);
3830 if ((unsigned long) imm_expr
.X_add_number
< 32
3831 || (unsigned long) imm_expr
.X_add_number
> 63)
3833 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3834 imm_expr
.X_op
= O_absent
;
3838 case 'k': /* cache code */
3839 my_getExpression (&imm_expr
, s
);
3840 check_absolute_expr (ip
, &imm_expr
);
3841 if ((unsigned long) imm_expr
.X_add_number
> 31)
3843 as_warn ("Invalid cahce opcode (%lu)",
3844 (unsigned long) imm_expr
.X_add_number
);
3845 imm_expr
.X_add_number
&= 0x1f;
3847 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
3848 imm_expr
.X_op
= O_absent
;
3852 case 'c': /* break code */
3853 my_getExpression (&imm_expr
, s
);
3854 check_absolute_expr (ip
, &imm_expr
);
3855 if ((unsigned) imm_expr
.X_add_number
> 1023)
3856 as_warn ("Illegal break code (%ld)",
3857 (long) imm_expr
.X_add_number
);
3858 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3859 imm_expr
.X_op
= O_absent
;
3863 case 'B': /* syscall code */
3864 my_getExpression (&imm_expr
, s
);
3865 check_absolute_expr (ip
, &imm_expr
);
3866 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3867 as_warn ("Illegal syscall code (%ld)",
3868 (long) imm_expr
.X_add_number
);
3869 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3870 imm_expr
.X_op
= O_absent
;
3874 case 'C': /* Coprocessor code */
3875 my_getExpression (&imm_expr
, s
);
3876 check_absolute_expr (ip
, &imm_expr
);
3877 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3879 as_warn ("Coproccesor code > 25 bits (%ld)",
3880 (long) imm_expr
.X_add_number
);
3881 imm_expr
.X_add_number
&= ((1<<25) - 1);
3883 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3884 imm_expr
.X_op
= O_absent
;
3888 case 'b': /* base register */
3889 case 'd': /* destination register */
3890 case 's': /* source register */
3891 case 't': /* target register */
3892 case 'r': /* both target and source */
3893 case 'v': /* both dest and source */
3894 case 'w': /* both dest and target */
3895 case 'E': /* coprocessor target register */
3896 case 'G': /* coprocessor destination register */
3897 case 'x': /* ignore register name */
3898 case 'z': /* must be zero register */
3912 while (isdigit (*s
));
3914 as_bad ("Invalid register number (%d)", regno
);
3916 else if (*args
== 'E' || *args
== 'G')
3920 if (s
[1] == 'f' && s
[2] == 'p')
3925 else if (s
[1] == 's' && s
[2] == 'p')
3930 else if (s
[1] == 'g' && s
[2] == 'p')
3935 else if (s
[1] == 'a' && s
[2] == 't')
3943 if (regno
== AT
&& ! mips_noat
)
3944 as_warn ("Used $at without \".set noat\"");
3950 if (c
== 'r' || c
== 'v' || c
== 'w')
3957 /* 'z' only matches $0. */
3958 if (c
== 'z' && regno
!= 0)
3966 ip
->insn_opcode
|= regno
<< 21;
3970 ip
->insn_opcode
|= regno
<< 11;
3975 ip
->insn_opcode
|= regno
<< 16;
3978 /* This case exists because on the r3000 trunc
3979 expands into a macro which requires a gp
3980 register. On the r6000 or r4000 it is
3981 assembled into a single instruction which
3982 ignores the register. Thus the insn version
3983 is MIPS_ISA2 and uses 'x', and the macro
3984 version is MIPS_ISA1 and uses 't'. */
3987 /* This case is for the div instruction, which
3988 acts differently if the destination argument
3989 is $0. This only matches $0, and is checked
3990 outside the switch. */
4001 ip
->insn_opcode
|= lastregno
<< 21;
4004 ip
->insn_opcode
|= lastregno
<< 16;
4009 case 'D': /* floating point destination register */
4010 case 'S': /* floating point source register */
4011 case 'T': /* floating point target register */
4015 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4025 while (isdigit (*s
));
4028 as_bad ("Invalid float register number (%d)", regno
);
4030 if ((regno
& 1) != 0
4032 && ! (strcmp (str
, "mtc1") == 0 ||
4033 strcmp (str
, "mfc1") == 0 ||
4034 strcmp (str
, "lwc1") == 0 ||
4035 strcmp (str
, "swc1") == 0))
4036 as_warn ("Float register should be even, was %d",
4044 if (c
== 'V' || c
== 'W')
4054 ip
->insn_opcode
|= regno
<< 6;
4058 ip
->insn_opcode
|= regno
<< 11;
4062 ip
->insn_opcode
|= regno
<< 16;
4070 ip
->insn_opcode
|= lastregno
<< 11;
4073 ip
->insn_opcode
|= lastregno
<< 16;
4079 my_getExpression (&imm_expr
, s
);
4080 check_absolute_expr (ip
, &imm_expr
);
4085 my_getExpression (&offset_expr
, s
);
4086 imm_reloc
= BFD_RELOC_32
;
4098 unsigned char temp
[8];
4100 unsigned int length
;
4105 /* These only appear as the last operand in an
4106 instruction, and every instruction that accepts
4107 them in any variant accepts them in all variants.
4108 This means we don't have to worry about backing out
4109 any changes if the instruction does not match.
4111 The difference between them is the size of the
4112 floating point constant and where it goes. For 'F'
4113 and 'L' the constant is 64 bits; for 'f' and 'l' it
4114 is 32 bits. Where the constant is placed is based
4115 on how the MIPS assembler does things:
4118 f -- immediate value
4121 When generating PIC code, we do not use the .lit8
4122 or .lit4 sections at all, in order to reserve the
4123 entire global offset table. */
4125 f64
= *args
== 'F' || *args
== 'L';
4127 save_in
= input_line_pointer
;
4128 input_line_pointer
= s
;
4129 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4131 s
= input_line_pointer
;
4132 input_line_pointer
= save_in
;
4133 if (err
!= NULL
&& *err
!= '\0')
4135 as_bad ("Bad floating point constant: %s", err
);
4136 memset (temp
, '\0', sizeof temp
);
4137 length
= f64
? 8 : 4;
4140 assert (length
== (f64
? 8 : 4));
4143 || (mips_pic
!= 0 && *args
== 'l'))
4145 imm_expr
.X_op
= O_constant
;
4146 if (byte_order
== LITTLE_ENDIAN
)
4147 imm_expr
.X_add_number
=
4148 (((((((int) temp
[3] << 8)
4153 imm_expr
.X_add_number
=
4154 (((((((int) temp
[0] << 8)
4161 const char *newname
;
4164 /* Switch to the right section. */
4166 subseg
= now_subseg
;
4169 default: /* unused default case avoids warnings. */
4171 newname
= (mips_pic
== 0 ? ".lit8" : ".rdata");
4177 assert (mips_pic
== 0);
4181 new_seg
= subseg_new (newname
, (subsegT
) 0);
4183 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4186 as_bad ("Can't use floating point insn in this section");
4188 /* Set the argument to the current address in the
4190 offset_expr
.X_op
= O_symbol
;
4191 offset_expr
.X_add_symbol
=
4192 symbol_new ("L0\001", now_seg
,
4193 (valueT
) frag_now_fix (), frag_now
);
4194 offset_expr
.X_add_number
= 0;
4196 /* Put the floating point number into the section. */
4197 p
= frag_more ((int) length
);
4198 memcpy (p
, temp
, length
);
4200 /* Switch back to the original section. */
4201 subseg_set (seg
, subseg
);
4206 case 'i': /* 16 bit unsigned immediate */
4207 case 'j': /* 16 bit signed immediate */
4208 imm_reloc
= BFD_RELOC_LO16
;
4209 c
= my_getSmallExpression (&imm_expr
, s
);
4214 if (imm_expr
.X_op
== O_constant
)
4215 imm_expr
.X_add_number
=
4216 (imm_expr
.X_add_number
>> 16) & 0xffff;
4218 imm_reloc
= BFD_RELOC_HI16_S
;
4220 imm_reloc
= BFD_RELOC_HI16
;
4224 check_absolute_expr (ip
, &imm_expr
);
4227 if (imm_expr
.X_add_number
< 0
4228 || imm_expr
.X_add_number
>= 0x10000)
4230 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4231 !strcmp (insn
->name
, insn
[1].name
))
4233 as_bad ("16 bit expression not in range 0..65535");
4238 if (imm_expr
.X_add_number
< -0x8000 ||
4239 imm_expr
.X_add_number
>= 0x8000)
4241 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4242 !strcmp (insn
->name
, insn
[1].name
))
4244 as_bad ("16 bit expression not in range -32768..32767");
4250 case 'o': /* 16 bit offset */
4251 c
= my_getSmallExpression (&offset_expr
, s
);
4253 * If this value won't fit into a 16 bit offset, then
4254 * go find a macro that will generate the 32 bit offset
4257 if (offset_expr
.X_op
!= O_constant
4258 || offset_expr
.X_add_number
>= 0x8000
4259 || offset_expr
.X_add_number
< -0x8000)
4262 offset_reloc
= BFD_RELOC_LO16
;
4263 if (c
== 'h' || c
== 'H')
4265 assert (offset_expr
.X_op
== O_constant
);
4266 offset_expr
.X_add_number
=
4267 (offset_expr
.X_add_number
>> 16) & 0xffff;
4272 case 'p': /* pc relative offset */
4273 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4274 my_getExpression (&offset_expr
, s
);
4278 case 'u': /* upper 16 bits */
4279 c
= my_getSmallExpression (&imm_expr
, s
);
4280 if (imm_expr
.X_op
!= O_constant
4281 || imm_expr
.X_add_number
< 0
4282 || imm_expr
.X_add_number
>= 0x10000)
4283 as_bad ("lui expression not in range 0..65535");
4284 imm_reloc
= BFD_RELOC_LO16
;
4289 if (imm_expr
.X_op
== O_constant
)
4290 imm_expr
.X_add_number
=
4291 (imm_expr
.X_add_number
>> 16) & 0xffff;
4293 imm_reloc
= BFD_RELOC_HI16_S
;
4295 imm_reloc
= BFD_RELOC_HI16
;
4301 case 'a': /* 26 bit address */
4302 my_getExpression (&offset_expr
, s
);
4304 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4308 fprintf (stderr
, "bad char = '%c'\n", *args
);
4313 /* Args don't match. */
4314 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4315 !strcmp (insn
->name
, insn
[1].name
))
4321 insn_error
= "ERROR: Illegal operands";
4330 my_getSmallExpression (ep
, str
)
4341 ((str
[1] == 'h' && str
[2] == 'i')
4342 || (str
[1] == 'H' && str
[2] == 'I')
4343 || (str
[1] == 'l' && str
[2] == 'o'))
4355 * A small expression may be followed by a base register.
4356 * Scan to the end of this operand, and then back over a possible
4357 * base register. Then scan the small expression up to that
4358 * point. (Based on code in sparc.c...)
4360 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4362 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4364 if (isdigit (sp
[-2]))
4366 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4368 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4374 else if (sp
- 5 >= str
4377 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4378 || (sp
[-3] == 's' && sp
[-2] == 'p')
4379 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4380 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4386 /* no expression means zero offset */
4389 /* %xx(reg) is an error */
4390 ep
->X_op
= O_absent
;
4395 ep
->X_op
= O_constant
;
4398 ep
->X_add_symbol
= NULL
;
4399 ep
->X_op_symbol
= NULL
;
4400 ep
->X_add_number
= 0;
4405 my_getExpression (ep
, str
);
4412 my_getExpression (ep
, str
);
4413 return c
; /* => %hi or %lo encountered */
4417 my_getExpression (ep
, str
)
4423 save_in
= input_line_pointer
;
4424 input_line_pointer
= str
;
4426 expr_end
= input_line_pointer
;
4427 input_line_pointer
= save_in
;
4430 /* Turn a string in input_line_pointer into a floating point constant
4431 of type type, and store the appropriate bytes in *litP. The number
4432 of LITTLENUMS emitted is stored in *sizeP . An error message is
4433 returned, or NULL on OK. */
4436 md_atof (type
, litP
, sizeP
)
4442 LITTLENUM_TYPE words
[4];
4458 return "bad call to md_atof";
4461 t
= atof_ieee (input_line_pointer
, type
, words
);
4463 input_line_pointer
= t
;
4467 if (byte_order
== LITTLE_ENDIAN
)
4469 for (i
= prec
- 1; i
>= 0; i
--)
4471 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4477 for (i
= 0; i
< prec
; i
++)
4479 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4488 md_number_to_chars (buf
, val
, n
)
4496 number_to_chars_littleendian (buf
, val
, n
);
4500 number_to_chars_bigendian (buf
, val
, n
);
4509 md_parse_option (argP
, cntP
, vecP
)
4514 /* Accept -nocpp but ignore it. */
4515 if (strcmp (*argP
, "nocpp") == 0)
4521 if (strcmp (*argP
, "EL") == 0
4522 || strcmp (*argP
, "EB") == 0)
4524 /* FIXME: This breaks -L -EL. */
4532 if ((*argP
)[1] == '0')
4541 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4546 if (strncmp (*argP
, "mips", 4) == 0)
4548 mips_isa
= atol (*argP
+ 4);
4551 else if (mips_isa
< 1 || mips_isa
> 3)
4553 as_bad ("-mips%d not supported", mips_isa
);
4560 if (strncmp (*argP
, "mcpu=", 5) == 0)
4564 /* Identify the processor type */
4566 if (strcmp (p
, "default") == 0
4567 || strcmp (p
, "DEFAULT") == 0)
4571 if (*p
== 'r' || *p
== 'R')
4578 if (strcmp (p
, "2000") == 0
4579 || strcmp (p
, "2k") == 0
4580 || strcmp (p
, "2K") == 0)
4585 if (strcmp (p
, "3000") == 0
4586 || strcmp (p
, "3k") == 0
4587 || strcmp (p
, "3K") == 0)
4592 if (strcmp (p
, "4000") == 0
4593 || strcmp (p
, "4k") == 0
4594 || strcmp (p
, "4K") == 0)
4599 if (strcmp (p
, "6000") == 0
4600 || strcmp (p
, "6k") == 0
4601 || strcmp (p
, "6K") == 0)
4608 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4621 if ((*argP
)[1] != '\0')
4622 g_switch_value
= atoi (*argP
+ 1);
4625 **vecP
= (char *) NULL
;
4628 g_switch_value
= atoi (**vecP
);
4631 as_warn ("Number expected after -G");
4637 return 1; /* pretend you parsed the character */
4641 md_pcrel_from (fixP
)
4644 /* return the address of the delay slot */
4645 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4648 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4649 reloc for a cons. We could use the definition there, except that
4650 we want to handle 64 bit relocs specially. */
4653 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
4656 unsigned int nbytes
;
4659 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
4661 FIXME: There is no way to select anything but 32 bit mode right
4665 if (byte_order
== BIG_ENDIAN
)
4670 if (nbytes
!= 2 && nbytes
!= 4)
4671 as_bad ("Unsupported reloc size %d", nbytes
);
4673 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
4674 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
4678 md_apply_fix (fixP
, valueP
)
4685 assert (fixP
->fx_size
== 4);
4688 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
4690 switch (fixP
->fx_r_type
)
4693 case BFD_RELOC_MIPS_JMP
:
4694 case BFD_RELOC_HI16
:
4695 case BFD_RELOC_HI16_S
:
4696 case BFD_RELOC_LO16
:
4697 case BFD_RELOC_MIPS_GPREL
:
4698 case BFD_RELOC_MIPS_LITERAL
:
4699 case BFD_RELOC_MIPS_CALL16
:
4700 case BFD_RELOC_MIPS_GOT16
:
4701 case BFD_RELOC_MIPS_GPREL32
:
4702 /* Nothing needed to do. The value comes from the reloc entry */
4705 case BFD_RELOC_16_PCREL_S2
:
4707 * We need to save the bits in the instruction since fixup_segment()
4708 * might be deleting the relocation entry (i.e., a branch within
4709 * the current segment).
4712 as_warn ("Branch to odd address (%lx)", value
);
4714 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
4715 as_bad ("Relocation overflow");
4717 /* update old instruction data */
4718 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
4722 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
4726 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
4733 insn
|= value
& 0xFFFF;
4734 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4748 const struct mips_opcode
*p
;
4749 int treg
, sreg
, dreg
, shamt
;
4754 for (i
= 0; i
< NUMOPCODES
; ++i
)
4756 p
= &mips_opcodes
[i
];
4757 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4759 printf ("%08lx %s\t", oc
, p
->name
);
4760 treg
= (oc
>> 16) & 0x1f;
4761 sreg
= (oc
>> 21) & 0x1f;
4762 dreg
= (oc
>> 11) & 0x1f;
4763 shamt
= (oc
>> 6) & 0x1f;
4765 for (args
= p
->args
;; ++args
)
4776 printf ("%c", *args
);
4780 assert (treg
== sreg
);
4781 printf ("$%d,$%d", treg
, sreg
);
4786 printf ("$%d", dreg
);
4791 printf ("$%d", treg
);
4795 printf ("0x%x", treg
);
4800 printf ("$%d", sreg
);
4804 printf ("0x%08lx", oc
& 0x1ffffff);
4816 printf ("$%d", shamt
);
4827 printf ("%08lx UNDEFINED\n", oc
);
4838 name
= input_line_pointer
;
4839 c
= get_symbol_end ();
4840 p
= (symbolS
*) symbol_find_or_make (name
);
4841 *input_line_pointer
= c
;
4845 /* Align the current frag to a given power of two. The MIPS assembler
4846 also automatically adjusts any preceding label. */
4849 mips_align (to
, fill
)
4853 mips_emit_delays ();
4854 frag_align (to
, fill
);
4855 record_alignment (now_seg
, to
);
4856 if (insn_label
!= NULL
)
4858 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4859 insn_label
->sy_frag
= frag_now
;
4860 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4865 /* Align to a given power of two. .align 0 turns off the automatic
4866 alignment used by the data creating pseudo-ops. */
4873 register long temp_fill
;
4874 long max_alignment
= 15;
4878 o Note that the assembler pulls down any immediately preceeding label
4879 to the aligned address.
4880 o It's not documented but auto alignment is reinstated by
4881 a .align pseudo instruction.
4882 o Note also that after auto alignment is turned off the mips assembler
4883 issues an error on attempt to assemble an improperly aligned data item.
4888 temp
= get_absolute_expression ();
4889 if (temp
> max_alignment
)
4890 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4893 as_warn ("Alignment negative: 0 assumed.");
4896 if (*input_line_pointer
== ',')
4898 input_line_pointer
++;
4899 temp_fill
= get_absolute_expression ();
4906 mips_align (temp
, (int) temp_fill
);
4913 demand_empty_rest_of_line ();
4916 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4917 that there was a previous instruction. */
4920 s_stringer (append_zero
)
4923 mips_emit_delays ();
4925 stringer (append_zero
);
4936 mips_emit_delays ();
4946 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4947 demand_empty_rest_of_line ();
4952 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4953 demand_empty_rest_of_line ();
4955 #else /* ! defined (OBJ_ECOFF) */
4957 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
4958 bfd_set_section_flags (stdoutput
, seg
,
4964 bfd_set_section_alignment (stdoutput
, seg
, 4);
4965 demand_empty_rest_of_line ();
4967 #else /* ! defined (OBJ_ELF) */
4970 #endif /* ! defined (OBJ_ELF) */
4971 #endif /* ! defined (OBJ_ECOFF) */
4975 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4977 bfd_set_section_flags (stdoutput
, seg
,
4978 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
4979 bfd_set_section_alignment (stdoutput
, seg
, 4);
4981 demand_empty_rest_of_line ();
4983 #else /* ! defined (GPOPT) */
4984 as_bad ("Global pointers not supported; recompile -G 0");
4985 demand_empty_rest_of_line ();
4987 #endif /* ! defined (GPOPT) */
4997 mips_emit_delays ();
4998 if (log_size
> 0 && auto_align
)
4999 mips_align (log_size
, 0);
5001 cons (1 << log_size
);
5008 as_fatal ("Encountered `.err', aborting assembly");
5018 symbolP
= get_symbol ();
5019 if (*input_line_pointer
== ',')
5020 input_line_pointer
++;
5021 size
= get_absolute_expression ();
5022 S_SET_VALUE (symbolP
, size
);
5023 S_SET_EXTERNAL (symbolP
);
5025 #ifdef ECOFF_DEBUGGING
5026 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
5027 so we use an additional ECOFF specific field. */
5028 symbolP
->ecoff_undefined
= 1;
5036 mips_emit_delays ();
5056 opt
= input_line_pointer
;
5057 c
= get_symbol_end ();
5061 /* FIXME: What does this mean? */
5063 else if (strncmp (opt
, "pic", 3) == 0)
5065 mips_pic
= atoi (opt
+ 3);
5066 /* Supposedly no other values are used. */
5067 assert (mips_pic
== 0 || mips_pic
== 2);
5070 as_warn ("Unrecognized option \"%s\"", opt
);
5072 *input_line_pointer
= c
;
5073 demand_empty_rest_of_line ();
5080 char *name
= input_line_pointer
, ch
;
5082 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5083 input_line_pointer
++;
5084 ch
= *input_line_pointer
;
5085 *input_line_pointer
= '\0';
5087 if (strcmp (name
, "reorder") == 0)
5091 prev_insn_unreordered
= 1;
5092 prev_prev_insn_unreordered
= 1;
5096 else if (strcmp (name
, "noreorder") == 0)
5098 mips_emit_delays ();
5100 mips_any_noreorder
= 1;
5102 else if (strcmp (name
, "at") == 0)
5106 else if (strcmp (name
, "noat") == 0)
5110 else if (strcmp (name
, "macro") == 0)
5112 mips_warn_about_macros
= 0;
5114 else if (strcmp (name
, "nomacro") == 0)
5116 if (mips_noreorder
== 0)
5117 as_bad ("`noreorder' must be set before `nomacro'");
5118 mips_warn_about_macros
= 1;
5120 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5124 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5128 else if (strcmp (name
, "bopt") == 0)
5132 else if (strcmp (name
, "nobopt") == 0)
5138 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5140 *input_line_pointer
= ch
;
5141 demand_empty_rest_of_line ();
5144 /* The same as the usual .space directive, except that we have to
5145 forget about any previous instruction. */
5148 s_mips_space (param
)
5151 mips_emit_delays ();
5156 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5157 .option pic2. It means to generate SVR4 PIC calls. */
5164 demand_empty_rest_of_line ();
5167 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5168 PIC code. It sets the $gp register for the function based on the
5169 function address, which is in the register named in the argument.
5170 This uses a relocation against _gp_disp, which is handled specially
5171 by the linker. The result is:
5172 lui $gp,%hi(_gp_disp)
5173 addiu $gp,$gp,%lo(_gp_disp)
5174 addu $gp,$gp,.cpload argument
5175 The .cpload argument is normally $25 == $t9. */
5184 /* If we are not generating PIC code, .cpload is ignored. */
5191 /* .cpload should be a in .set noreorder section. */
5192 if (mips_noreorder
== 0)
5193 as_warn (".cpload not in noreorder section");
5196 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5197 ex
.X_op_symbol
= NULL
;
5198 ex
.X_add_number
= 0;
5200 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5201 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5202 (int) BFD_RELOC_LO16
);
5204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5205 GP
, GP
, tc_get_register (0));
5207 demand_empty_rest_of_line ();
5210 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5211 offset from $sp. The offset is remembered, and after making a PIC
5212 call $gp is restored from that location. */
5215 s_cprestore (ignore
)
5221 /* If we are not generating PIC code, .cprestore is ignored. */
5228 mips_cprestore_offset
= get_absolute_expression ();
5230 ex
.X_op
= O_constant
;
5231 ex
.X_add_symbol
= NULL
;
5232 ex
.X_op_symbol
= NULL
;
5233 ex
.X_add_number
= mips_cprestore_offset
;
5235 macro_build ((char *) NULL
, &icnt
, &ex
,
5236 mips_isa
< 3 ? "sw" : "sd",
5237 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5239 demand_empty_rest_of_line ();
5242 /* Handle the .gpword pseudo-op. This is used when generating PIC
5243 code. It generates a 32 bit GP relative reloc. */
5252 /* When not generating PIC code, this is treated as .word. */
5259 mips_emit_delays ();
5266 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5268 as_bad ("Unsupported use of .gpword");
5269 ignore_rest_of_line ();
5273 md_number_to_chars (p
, (valueT
) 0, 4);
5274 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5275 BFD_RELOC_MIPS_GPREL32
);
5277 demand_empty_rest_of_line ();
5280 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5281 tables in SVR4 PIC code. */
5290 /* This is ignored when not generating SVR4 PIC code. */
5297 /* Add $gp to the register named as an argument. */
5298 reg
= tc_get_register (0);
5299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5300 mips_isa
< 3 ? "addu" : "daddu",
5301 "d,v,t", reg
, reg
, GP
);
5303 demand_empty_rest_of_line ();
5306 /* Parse a register string into a number. Called from the ECOFF code
5307 to parse .frame. The argument is non-zero if this is the frame
5308 register, so that we can record it in mips_frame_reg. */
5311 tc_get_register (frame
)
5317 if (*input_line_pointer
++ != '$')
5319 as_warn ("expected `$'");
5322 else if (isdigit ((unsigned char) *input_line_pointer
))
5324 reg
= get_absolute_expression ();
5325 if (reg
< 0 || reg
>= 32)
5327 as_warn ("Bad register number");
5333 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5335 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5337 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5339 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5343 as_warn ("Unrecognized register name");
5346 input_line_pointer
+= 2;
5349 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5354 md_section_align (seg
, addr
)
5358 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5360 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5363 /* Estimate the size of a frag before relaxing. We are not really
5364 relaxing here, and the final size is encoded in the subtype
5369 md_estimate_size_before_relax (fragp
, segtype
)
5378 const char *symname
;
5380 /* Find out whether this symbol can be referenced off the GP
5381 register. It can be if it is smaller than the -G size or if
5382 it is in the .sdata or .sbss section. Certain symbols can
5383 not be referenced off the GP, although it appears as though
5385 symname
= S_GET_NAME (fragp
->fr_symbol
);
5386 if (symname
!= (const char *) NULL
5387 && (strcmp (symname
, "eprol") == 0
5388 || strcmp (symname
, "etext") == 0
5389 || strcmp (symname
, "_gp") == 0
5390 || strcmp (symname
, "edata") == 0
5391 || strcmp (symname
, "_fbss") == 0
5392 || strcmp (symname
, "_fdata") == 0
5393 || strcmp (symname
, "_ftext") == 0
5394 || strcmp (symname
, "end") == 0
5395 || strcmp (symname
, "_gp_disp") == 0))
5397 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5398 && S_GET_VALUE (fragp
->fr_symbol
) != 0
5399 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)
5403 const char *segname
;
5405 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5406 assert (strcmp (segname
, ".lit8") != 0
5407 && strcmp (segname
, ".lit4") != 0);
5408 change
= (strcmp (segname
, ".sdata") != 0
5409 && strcmp (segname
, ".sbss") != 0);
5411 #else /* ! defined (GPOPT) */
5412 /* We are not optimizing for the GP register. */
5414 #endif /* ! defined (GPOPT) */
5418 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5420 /* This must duplicate the test in adjust_reloc_syms. */
5421 change
= (symsec
!= &bfd_und_section
5422 && symsec
!= &bfd_abs_section
5423 && ! bfd_is_com_section (symsec
));
5428 /* Record the offset to the first reloc in the fr_opcode field.
5429 This lets md_convert_frag and tc_gen_reloc know that the code
5430 must be expanded. */
5431 fragp
->fr_opcode
= (fragp
->fr_literal
5433 - RELAX_OLD (fragp
->fr_subtype
)
5434 + RELAX_RELOC1 (fragp
->fr_subtype
));
5435 /* FIXME: This really needs as_warn_where. */
5436 if (RELAX_WARN (fragp
->fr_subtype
))
5437 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5443 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5446 /* Translate internal representation of relocation info to BFD target
5450 tc_gen_reloc (section
, fixp
)
5454 static arelent
*retval
[4];
5457 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5460 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5461 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5462 if (fixp
->fx_pcrel
== 0)
5463 reloc
->addend
= fixp
->fx_addnumber
;
5468 reloc
->addend
= -reloc
->address
;
5471 /* If this is a variant frag, we may need to adjust the existing
5472 reloc and generate a new one. */
5473 if (fixp
->fx_frag
->fr_opcode
!= NULL
5474 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5475 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5476 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5480 /* If this is not the last reloc in this frag, then we have two
5481 GPREL relocs, both of which are being replaced. Let the
5482 second one handle all of them. */
5483 if (fixp
->fx_next
!= NULL
5484 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5486 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5487 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5492 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5493 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5494 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5496 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5497 reloc2
->address
= (reloc
->address
5498 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5499 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5500 reloc2
->addend
= fixp
->fx_addnumber
;
5501 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5502 assert (reloc2
->howto
!= NULL
);
5504 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5508 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5511 reloc3
->address
+= 4;
5516 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5517 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5521 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5523 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5524 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5529 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5531 if (reloc
->howto
== NULL
)
5533 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5534 "Can not represent relocation in this object file format");
5541 /* Convert a machine dependent frag. */
5544 md_convert_frag (abfd
, asec
, fragp
)
5552 if (fragp
->fr_opcode
== NULL
)
5555 old
= RELAX_OLD (fragp
->fr_subtype
);
5556 new = RELAX_NEW (fragp
->fr_subtype
);
5557 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5560 memcpy (fixptr
- old
, fixptr
, new);
5562 fragp
->fr_fix
+= new - old
;
5565 /* This function is called whenever a label is defined. It is used
5566 when handling branch delays; if a branch has a label, we assume we
5570 mips_define_label (sym
)
5578 /* Some special processing for a MIPS ELF file. */
5581 mips_elf_final_processing ()
5585 /* Write out the .reginfo section. */
5586 s
.ri_gprmask
= mips_gprmask
;
5587 s
.ri_cprmask
[0] = mips_cprmask
[0];
5588 s
.ri_cprmask
[1] = mips_cprmask
[1];
5589 s
.ri_cprmask
[2] = mips_cprmask
[2];
5590 s
.ri_cprmask
[3] = mips_cprmask
[3];
5591 /* The gp_value field is set by the MIPS ELF backend. */
5593 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
5594 ((Elf32_External_RegInfo
*)
5595 mips_regmask_frag
));
5597 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
5598 sort of BFD interface for this. */
5599 if (mips_any_noreorder
)
5600 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
5602 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
5605 #endif /* OBJ_ELF */
5607 #ifndef ECOFF_DEBUGGING
5609 /* These functions should really be defined by the object file format,
5610 since they are related to debugging information. However, this
5611 code has to work for the a.out format, which does not define them,
5612 so we provide simple versions here. These don't actually generate
5613 any debugging information, but they do simple checking and someday
5614 somebody may make them useful. */
5618 struct loc
*loc_next
;
5619 unsigned long loc_fileno
;
5620 unsigned long loc_lineno
;
5621 unsigned long loc_offset
;
5622 unsigned short loc_delta
;
5623 unsigned short loc_count
;
5632 struct proc
*proc_next
;
5633 struct symbol
*proc_isym
;
5634 struct symbol
*proc_end
;
5635 unsigned long proc_reg_mask
;
5636 unsigned long proc_reg_offset
;
5637 unsigned long proc_fpreg_mask
;
5638 unsigned long proc_fpreg_offset
;
5639 unsigned long proc_frameoffset
;
5640 unsigned long proc_framereg
;
5641 unsigned long proc_pcreg
;
5643 struct file
*proc_file
;
5650 struct file
*file_next
;
5651 unsigned long file_fileno
;
5652 struct symbol
*file_symbol
;
5653 struct symbol
*file_end
;
5654 struct proc
*file_proc
;
5659 static struct obstack proc_frags
;
5660 static procS
*proc_lastP
;
5661 static procS
*proc_rootP
;
5662 static int numprocs
;
5667 obstack_begin (&proc_frags
, 0x2000);
5673 /* check for premature end, nesting errors, etc */
5674 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5675 as_warn ("missing `.end' at end of assembly");
5678 extern char hex_value
[];
5686 if (*input_line_pointer
== '-')
5688 ++input_line_pointer
;
5691 if (!isdigit (*input_line_pointer
))
5692 as_bad ("Expected simple number.");
5693 if (input_line_pointer
[0] == '0')
5695 if (input_line_pointer
[1] == 'x')
5697 input_line_pointer
+= 2;
5698 while (isxdigit (*input_line_pointer
))
5701 val
|= hex_value
[(int) *input_line_pointer
++];
5703 return negative
? -val
: val
;
5707 ++input_line_pointer
;
5708 while (isdigit (*input_line_pointer
))
5711 val
|= *input_line_pointer
++ - '0';
5713 return negative
? -val
: val
;
5716 if (!isdigit (*input_line_pointer
))
5718 printf (" *input_line_pointer == '%c' 0x%02x\n",
5719 *input_line_pointer
, *input_line_pointer
);
5720 as_warn ("Invalid number");
5723 while (isdigit (*input_line_pointer
))
5726 val
+= *input_line_pointer
++ - '0';
5728 return negative
? -val
: val
;
5731 /* The .file directive; just like the usual .file directive, but there
5732 is an initial number which is the ECOFF file index. */
5740 line
= get_number ();
5745 /* The .end directive. */
5753 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5756 demand_empty_rest_of_line ();
5760 if (now_seg
!= text_section
)
5761 as_warn (".end not in text section");
5764 as_warn (".end and no .ent seen yet.");
5770 assert (S_GET_NAME (p
));
5771 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
5772 as_warn (".end symbol does not match .ent symbol.");
5775 proc_lastP
->proc_end
= (symbolS
*) 1;
5778 /* The .aent and .ent directives. */
5788 symbolP
= get_symbol ();
5789 if (*input_line_pointer
== ',')
5790 input_line_pointer
++;
5792 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
5793 number
= get_number ();
5794 if (now_seg
!= text_section
)
5795 as_warn (".ent or .aent not in text section.");
5797 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5798 as_warn ("missing `.end'");
5802 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
5803 procP
->proc_isym
= symbolP
;
5804 procP
->proc_reg_mask
= 0;
5805 procP
->proc_reg_offset
= 0;
5806 procP
->proc_fpreg_mask
= 0;
5807 procP
->proc_fpreg_offset
= 0;
5808 procP
->proc_frameoffset
= 0;
5809 procP
->proc_framereg
= 0;
5810 procP
->proc_pcreg
= 0;
5811 procP
->proc_end
= NULL
;
5812 procP
->proc_next
= NULL
;
5814 proc_lastP
->proc_next
= procP
;
5820 demand_empty_rest_of_line ();
5823 /* The .frame directive. */
5836 frame_reg
= tc_get_register (1);
5837 if (*input_line_pointer
== ',')
5838 input_line_pointer
++;
5839 frame_off
= get_absolute_expression ();
5840 if (*input_line_pointer
== ',')
5841 input_line_pointer
++;
5842 pcreg
= tc_get_register (0);
5845 assert (proc_rootP
);
5846 proc_rootP
->proc_framereg
= frame_reg
;
5847 proc_rootP
->proc_frameoffset
= frame_off
;
5848 proc_rootP
->proc_pcreg
= pcreg
;
5849 /* bob macho .frame */
5851 /* We don't have to write out a frame stab for unoptimized code. */
5852 if (!(frame_reg
== FP
&& frame_off
== 0))
5855 as_warn ("No .ent for .frame to use.");
5856 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
5857 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
5858 S_SET_TYPE (symP
, N_RMASK
);
5859 S_SET_OTHER (symP
, 0);
5860 S_SET_DESC (symP
, 0);
5861 symP
->sy_forward
= proc_lastP
->proc_isym
;
5862 /* bob perhaps I should have used pseudo set */
5864 demand_empty_rest_of_line ();
5868 /* The .fmask and .mask directives. */
5875 char str
[100], *strP
;
5881 mask
= get_number ();
5882 if (*input_line_pointer
== ',')
5883 input_line_pointer
++;
5884 off
= get_absolute_expression ();
5886 /* bob only for coff */
5887 assert (proc_rootP
);
5888 if (reg_type
== 'F')
5890 proc_rootP
->proc_fpreg_mask
= mask
;
5891 proc_rootP
->proc_fpreg_offset
= off
;
5895 proc_rootP
->proc_reg_mask
= mask
;
5896 proc_rootP
->proc_reg_offset
= off
;
5899 /* bob macho .mask + .fmask */
5901 /* We don't have to write out a mask stab if no saved regs. */
5905 as_warn ("No .ent for .mask to use.");
5907 for (i
= 0; i
< 32; i
++)
5911 sprintf (strP
, "%c%d,", reg_type
, i
);
5912 strP
+= strlen (strP
);
5916 sprintf (strP
, ";%d,", off
);
5917 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
5918 S_SET_TYPE (symP
, N_RMASK
);
5919 S_SET_OTHER (symP
, 0);
5920 S_SET_DESC (symP
, 0);
5921 symP
->sy_forward
= proc_lastP
->proc_isym
;
5922 /* bob perhaps I should have used pseudo set */
5927 /* The .loc directive. */
5938 assert (now_seg
== text_section
);
5940 lineno
= get_number ();
5941 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
5943 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
5944 S_SET_TYPE (symbolP
, N_SLINE
);
5945 S_SET_OTHER (symbolP
, 0);
5946 S_SET_DESC (symbolP
, lineno
);
5947 symbolP
->sy_segment
= now_seg
;
5951 #endif /* ! defined (ECOFF_DEBUGGING) */