1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
50 #undef OBJ_PROCESS_STAB
56 #undef TARGET_SYMBOL_FIELDS
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
80 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
81 static char *mips_regmask_frag
;
86 #define PIC_CALL_REG 25
94 #define ILLEGAL_REG (32)
96 extern int target_big_endian
;
98 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
99 32 bit ABI. This has no meaning for ECOFF. */
102 /* The default target format to use. */
104 mips_target_format ()
106 switch (OUTPUT_FLAVOR
)
108 case bfd_target_aout_flavour
:
109 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
110 case bfd_target_ecoff_flavour
:
111 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
112 case bfd_target_elf_flavour
:
113 return (target_big_endian
114 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
115 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
121 /* The name of the readonly data section. */
122 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
124 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
126 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
130 /* These variables are filled in with the masks of registers used.
131 The object format code reads them and puts them in the appropriate
133 unsigned long mips_gprmask
;
134 unsigned long mips_cprmask
[4];
136 /* MIPS ISA (Instruction Set Architecture) level (may be changed
137 temporarily using .set mipsN). */
138 static int mips_isa
= -1;
140 /* MIPS ISA we are using for this output file. */
141 static int file_mips_isa
;
143 /* Whether we are assembling for the mips16 processor. */
144 static int mips16
= -1;
146 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
147 static int mips_cpu
= -1;
149 /* Whether the 4650 instructions (mad/madu) are permitted. */
150 static int mips_4650
= -1;
152 /* Whether the 4010 instructions are permitted. */
153 static int mips_4010
= -1;
155 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
156 static int mips_4100
= -1;
158 /* start-sanitize-r5900 */
159 /* Whether Toshiba r5900 instructions are permitted. */
160 static int mips_5900
= -1;
161 /* end-sanitize-r5900 */
163 /* Whether the processor uses hardware interlocks, and thus does not
164 require nops to be inserted. */
165 static int interlocks
= -1;
167 /* As with "interlocks" this is used by hardware that has FP
168 (co-processor) interlocks. */
169 /* Itbl support may require additional care here. */
170 static int cop_interlocks
= -1;
172 /* MIPS PIC level. */
176 /* Do not generate PIC code. */
179 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
180 not sure what it is supposed to do. */
183 /* Generate PIC code as in the SVR4 MIPS ABI. */
186 /* Generate PIC code without using a global offset table: the data
187 segment has a maximum size of 64K, all data references are off
188 the $gp register, and all text references are PC relative. This
189 is used on some embedded systems. */
193 static enum mips_pic_level mips_pic
;
195 /* 1 if we should generate 32 bit offsets from the GP register in
196 SVR4_PIC mode. Currently has no meaning in other modes. */
197 static int mips_big_got
;
199 /* 1 if trap instructions should used for overflow rather than break
201 static int mips_trap
;
203 /* 1 if we should autoextend mips16 instructions. */
204 static int mips16_autoextend
= 1;
206 static int mips_warn_about_macros
;
207 static int mips_noreorder
;
208 static int mips_any_noreorder
;
209 static int mips_nomove
;
210 static int mips_noat
;
211 static int mips_nobopt
;
213 /* The size of the small data section. */
214 static int g_switch_value
= 8;
215 /* Whether the -G option was used. */
216 static int g_switch_seen
= 0;
221 /* If we can determine in advance that GP optimization won't be
222 possible, we can skip the relaxation stuff that tries to produce
223 GP-relative references. This makes delay slot optimization work
226 This function can only provide a guess, but it seems to work for
227 gcc output. If it guesses wrong, the only loss should be in
228 efficiency; it shouldn't introduce any bugs.
230 I don't know if a fix is needed for the SVR4_PIC mode. I've only
231 fixed it for the non-PIC mode. KR 95/04/07 */
232 static int nopic_need_relax
PARAMS ((symbolS
*));
234 /* handle of the OPCODE hash table */
235 static struct hash_control
*op_hash
= NULL
;
237 /* The opcode hash table we use for the mips16. */
238 static struct hash_control
*mips16_op_hash
= NULL
;
240 /* This array holds the chars that always start a comment. If the
241 pre-processor is disabled, these aren't very useful */
242 const char comment_chars
[] = "#";
244 /* This array holds the chars that only start a comment at the beginning of
245 a line. If the line seems to have the form '# 123 filename'
246 .line and .file directives will appear in the pre-processed output */
247 /* Note that input_file.c hand checks for '#' at the beginning of the
248 first line of the input file. This is because the compiler outputs
249 #NO_APP at the beginning of its output. */
250 /* Also note that C style comments are always supported. */
251 const char line_comment_chars
[] = "#";
253 /* This array holds machine specific line separator characters. */
254 const char line_separator_chars
[] = "";
256 /* Chars that can be used to separate mant from exp in floating point nums */
257 const char EXP_CHARS
[] = "eE";
259 /* Chars that mean this number is a floating point constant */
262 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
264 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
265 changed in read.c . Ideally it shouldn't have to know about it at all,
266 but nothing is ideal around here.
269 static char *insn_error
;
271 static int auto_align
= 1;
273 /* When outputting SVR4 PIC code, the assembler needs to know the
274 offset in the stack frame from which to restore the $gp register.
275 This is set by the .cprestore pseudo-op, and saved in this
277 static offsetT mips_cprestore_offset
= -1;
279 /* This is the register which holds the stack frame, as set by the
280 .frame pseudo-op. This is needed to implement .cprestore. */
281 static int mips_frame_reg
= SP
;
283 /* To output NOP instructions correctly, we need to keep information
284 about the previous two instructions. */
286 /* Whether we are optimizing. The default value of 2 means to remove
287 unneeded NOPs and swap branch instructions when possible. A value
288 of 1 means to not swap branches. A value of 0 means to always
290 static int mips_optimize
= 2;
292 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
293 equivalent to seeing no -g option at all. */
294 static int mips_debug
= 0;
296 /* The previous instruction. */
297 static struct mips_cl_insn prev_insn
;
299 /* The instruction before prev_insn. */
300 static struct mips_cl_insn prev_prev_insn
;
302 /* If we don't want information for prev_insn or prev_prev_insn, we
303 point the insn_mo field at this dummy integer. */
304 static const struct mips_opcode dummy_opcode
= { 0 };
306 /* Non-zero if prev_insn is valid. */
307 static int prev_insn_valid
;
309 /* The frag for the previous instruction. */
310 static struct frag
*prev_insn_frag
;
312 /* The offset into prev_insn_frag for the previous instruction. */
313 static long prev_insn_where
;
315 /* The reloc type for the previous instruction, if any. */
316 static bfd_reloc_code_real_type prev_insn_reloc_type
;
318 /* The reloc for the previous instruction, if any. */
319 static fixS
*prev_insn_fixp
;
321 /* Non-zero if the previous instruction was in a delay slot. */
322 static int prev_insn_is_delay_slot
;
324 /* Non-zero if the previous instruction was in a .set noreorder. */
325 static int prev_insn_unreordered
;
327 /* Non-zero if the previous instruction uses an extend opcode (if
329 static int prev_insn_extended
;
331 /* Non-zero if the previous previous instruction was in a .set
333 static int prev_prev_insn_unreordered
;
335 /* If this is set, it points to a frag holding nop instructions which
336 were inserted before the start of a noreorder section. If those
337 nops turn out to be unnecessary, the size of the frag can be
339 static fragS
*prev_nop_frag
;
341 /* The number of nop instructions we created in prev_nop_frag. */
342 static int prev_nop_frag_holds
;
344 /* The number of nop instructions that we know we need in
346 static int prev_nop_frag_required
;
348 /* The number of instructions we've seen since prev_nop_frag. */
349 static int prev_nop_frag_since
;
351 /* For ECOFF and ELF, relocations against symbols are done in two
352 parts, with a HI relocation and a LO relocation. Each relocation
353 has only 16 bits of space to store an addend. This means that in
354 order for the linker to handle carries correctly, it must be able
355 to locate both the HI and the LO relocation. This means that the
356 relocations must appear in order in the relocation table.
358 In order to implement this, we keep track of each unmatched HI
359 relocation. We then sort them so that they immediately precede the
360 corresponding LO relocation. */
365 struct mips_hi_fixup
*next
;
368 /* The section this fixup is in. */
372 /* The list of unmatched HI relocs. */
374 static struct mips_hi_fixup
*mips_hi_fixup_list
;
376 /* Map normal MIPS register numbers to mips16 register numbers. */
378 #define X ILLEGAL_REG
379 static const int mips32_to_16_reg_map
[] =
381 X
, X
, 2, 3, 4, 5, 6, 7,
382 X
, X
, X
, X
, X
, X
, X
, X
,
383 0, 1, X
, X
, X
, X
, X
, X
,
384 X
, X
, X
, X
, X
, X
, X
, X
388 /* Map mips16 register numbers to normal MIPS register numbers. */
390 static const int mips16_to_32_reg_map
[] =
392 16, 17, 2, 3, 4, 5, 6, 7
395 /* Since the MIPS does not have multiple forms of PC relative
396 instructions, we do not have to do relaxing as is done on other
397 platforms. However, we do have to handle GP relative addressing
398 correctly, which turns out to be a similar problem.
400 Every macro that refers to a symbol can occur in (at least) two
401 forms, one with GP relative addressing and one without. For
402 example, loading a global variable into a register generally uses
403 a macro instruction like this:
405 If i can be addressed off the GP register (this is true if it is in
406 the .sbss or .sdata section, or if it is known to be smaller than
407 the -G argument) this will generate the following instruction:
409 This instruction will use a GPREL reloc. If i can not be addressed
410 off the GP register, the following instruction sequence will be used:
413 In this case the first instruction will have a HI16 reloc, and the
414 second reloc will have a LO16 reloc. Both relocs will be against
417 The issue here is that we may not know whether i is GP addressable
418 until after we see the instruction that uses it. Therefore, we
419 want to be able to choose the final instruction sequence only at
420 the end of the assembly. This is similar to the way other
421 platforms choose the size of a PC relative instruction only at the
424 When generating position independent code we do not use GP
425 addressing in quite the same way, but the issue still arises as
426 external symbols and local symbols must be handled differently.
428 We handle these issues by actually generating both possible
429 instruction sequences. The longer one is put in a frag_var with
430 type rs_machine_dependent. We encode what to do with the frag in
431 the subtype field. We encode (1) the number of existing bytes to
432 replace, (2) the number of new bytes to use, (3) the offset from
433 the start of the existing bytes to the first reloc we must generate
434 (that is, the offset is applied from the start of the existing
435 bytes after they are replaced by the new bytes, if any), (4) the
436 offset from the start of the existing bytes to the second reloc,
437 (5) whether a third reloc is needed (the third reloc is always four
438 bytes after the second reloc), and (6) whether to warn if this
439 variant is used (this is sometimes needed if .set nomacro or .set
440 noat is in effect). All these numbers are reasonably small.
442 Generating two instruction sequences must be handled carefully to
443 ensure that delay slots are handled correctly. Fortunately, there
444 are a limited number of cases. When the second instruction
445 sequence is generated, append_insn is directed to maintain the
446 existing delay slot information, so it continues to apply to any
447 code after the second instruction sequence. This means that the
448 second instruction sequence must not impose any requirements not
449 required by the first instruction sequence.
451 These variant frags are then handled in functions called by the
452 machine independent code. md_estimate_size_before_relax returns
453 the final size of the frag. md_convert_frag sets up the final form
454 of the frag. tc_gen_reloc adjust the first reloc and adds a second
456 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
460 | (((reloc1) + 64) << 9) \
461 | (((reloc2) + 64) << 2) \
462 | ((reloc3) ? (1 << 1) : 0) \
464 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
465 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
466 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
467 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
468 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
469 #define RELAX_WARN(i) ((i) & 1)
471 /* For mips16 code, we use an entirely different form of relaxation.
472 mips16 supports two versions of most instructions which take
473 immediate values: a small one which takes some small value, and a
474 larger one which takes a 16 bit value. Since branches also follow
475 this pattern, relaxing these values is required.
477 We can assemble both mips16 and normal MIPS code in a single
478 object. Therefore, we need to support this type of relaxation at
479 the same time that we support the relaxation described above. We
480 use the high bit of the subtype field to distinguish these cases.
482 The information we store for this type of relaxation is the
483 argument code found in the opcode file for this relocation, whether
484 the user explicitly requested a small or extended form, and whether
485 the relocation is in a jump or jal delay slot. That tells us the
486 size of the value, and how it should be stored. We also store
487 whether the fragment is considered to be extended or not. We also
488 store whether this is known to be a branch to a different section,
489 whether we have tried to relax this frag yet, and whether we have
490 ever extended a PC relative fragment because of a shift count. */
491 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
494 | ((small) ? 0x100 : 0) \
495 | ((ext) ? 0x200 : 0) \
496 | ((dslot) ? 0x400 : 0) \
497 | ((jal_dslot) ? 0x800 : 0))
498 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
499 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
500 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
501 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
502 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
503 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
504 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
505 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
506 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
507 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
508 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
509 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
511 /* Prototypes for static functions. */
514 #define internalError() \
515 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
517 #define internalError() as_fatal ("MIPS internal Error");
520 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
522 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
523 unsigned int reg
, enum mips_regclass
class));
524 static int reg_needs_delay
PARAMS ((int));
525 static void append_insn
PARAMS ((char *place
,
526 struct mips_cl_insn
* ip
,
528 bfd_reloc_code_real_type r
,
530 static void mips_no_prev_insn
PARAMS ((int));
531 static void mips_emit_delays
PARAMS ((boolean
));
533 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
534 const char *name
, const char *fmt
,
537 static void macro_build ();
539 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
540 const char *, const char *,
542 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
543 expressionS
* ep
, int regnum
));
544 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
545 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
547 static void load_register
PARAMS ((int *, int, expressionS
*, int));
548 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
549 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
550 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
551 #ifdef LOSING_COMPILER
552 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
554 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
555 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
556 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
557 boolean
, boolean
, unsigned long *,
558 boolean
*, unsigned short *));
559 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
560 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
561 static symbolS
*get_symbol
PARAMS ((void));
562 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
563 static void s_align
PARAMS ((int));
564 static void s_change_sec
PARAMS ((int));
565 static void s_cons
PARAMS ((int));
566 static void s_float_cons
PARAMS ((int));
567 static void s_mips_globl
PARAMS ((int));
568 static void s_option
PARAMS ((int));
569 static void s_mipsset
PARAMS ((int));
570 static void s_abicalls
PARAMS ((int));
571 static void s_cpload
PARAMS ((int));
572 static void s_cprestore
PARAMS ((int));
573 static void s_gpword
PARAMS ((int));
574 static void s_cpadd
PARAMS ((int));
575 static void s_insn
PARAMS ((int));
576 static void md_obj_begin
PARAMS ((void));
577 static void md_obj_end
PARAMS ((void));
578 static long get_number
PARAMS ((void));
579 static void s_ent
PARAMS ((int));
580 static void s_mipsend
PARAMS ((int));
581 static void s_file
PARAMS ((int));
582 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
586 The following pseudo-ops from the Kane and Heinrich MIPS book
587 should be defined here, but are currently unsupported: .alias,
588 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
590 The following pseudo-ops from the Kane and Heinrich MIPS book are
591 specific to the type of debugging information being generated, and
592 should be defined by the object format: .aent, .begin, .bend,
593 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
596 The following pseudo-ops from the Kane and Heinrich MIPS book are
597 not MIPS CPU specific, but are also not specific to the object file
598 format. This file is probably the best place to define them, but
599 they are not currently supported: .asm0, .endr, .lab, .repeat,
600 .struct, .weakext. */
602 static const pseudo_typeS mips_pseudo_table
[] =
604 /* MIPS specific pseudo-ops. */
605 {"option", s_option
, 0},
606 {"set", s_mipsset
, 0},
607 {"rdata", s_change_sec
, 'r'},
608 {"sdata", s_change_sec
, 's'},
609 {"livereg", s_ignore
, 0},
610 {"abicalls", s_abicalls
, 0},
611 {"cpload", s_cpload
, 0},
612 {"cprestore", s_cprestore
, 0},
613 {"gpword", s_gpword
, 0},
614 {"cpadd", s_cpadd
, 0},
617 /* Relatively generic pseudo-ops that happen to be used on MIPS
619 {"asciiz", stringer
, 1},
620 {"bss", s_change_sec
, 'b'},
623 {"dword", s_cons
, 3},
625 /* These pseudo-ops are defined in read.c, but must be overridden
626 here for one reason or another. */
627 {"align", s_align
, 0},
629 {"data", s_change_sec
, 'd'},
630 {"double", s_float_cons
, 'd'},
631 {"float", s_float_cons
, 'f'},
632 {"globl", s_mips_globl
, 0},
633 {"global", s_mips_globl
, 0},
634 {"hword", s_cons
, 1},
639 {"short", s_cons
, 1},
640 {"single", s_float_cons
, 'f'},
641 {"text", s_change_sec
, 't'},
646 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
647 /* These pseudo-ops should be defined by the object file format.
648 However, a.out doesn't support them, so we have versions here. */
650 {"bgnb", s_ignore
, 0},
651 {"end", s_mipsend
, 0},
652 {"endb", s_ignore
, 0},
655 {"fmask", s_ignore
, 'F'},
656 {"frame", s_ignore
, 0},
657 {"loc", s_ignore
, 0},
658 {"mask", s_ignore
, 'R'},
659 {"verstamp", s_ignore
, 0},
663 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
668 pop_insert (mips_pseudo_table
);
669 if (! ECOFF_DEBUGGING
)
670 pop_insert (mips_nonecoff_pseudo_table
);
673 /* Symbols labelling the current insn. */
675 struct insn_label_list
677 struct insn_label_list
*next
;
681 static struct insn_label_list
*insn_labels
;
682 static struct insn_label_list
*free_insn_labels
;
684 static void mips_clear_insn_labels
PARAMS ((void));
687 mips_clear_insn_labels ()
689 register struct insn_label_list
**pl
;
691 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
697 static char *expr_end
;
699 /* Expressions which appear in instructions. These are set by
702 static expressionS imm_expr
;
703 static expressionS offset_expr
;
705 /* Relocs associated with imm_expr and offset_expr. */
707 static bfd_reloc_code_real_type imm_reloc
;
708 static bfd_reloc_code_real_type offset_reloc
;
710 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
712 static boolean imm_unmatched_hi
;
714 /* These are set by mips16_ip if an explicit extension is used. */
716 static boolean mips16_small
, mips16_ext
;
719 * This function is called once, at assembler startup time. It should
720 * set up all the tables, etc. that the MD part of the assembler will need.
726 register const char *retval
= NULL
;
727 register unsigned int i
= 0;
735 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
737 a
= xmalloc (sizeof TARGET_CPU
);
738 strcpy (a
, TARGET_CPU
);
739 a
[(sizeof TARGET_CPU
) - 3] = '\0';
743 if (strcmp (cpu
, "mips") == 0)
749 else if (strcmp (cpu
, "r6000") == 0
750 || strcmp (cpu
, "mips2") == 0)
756 else if (strcmp (cpu
, "mips64") == 0
757 || strcmp (cpu
, "r4000") == 0
758 || strcmp (cpu
, "mips3") == 0)
764 else if (strcmp (cpu
, "r4400") == 0)
770 else if (strcmp (cpu
, "mips64orion") == 0
771 || strcmp (cpu
, "r4600") == 0)
777 else if (strcmp (cpu
, "r4650") == 0)
785 else if (strcmp (cpu
, "mips64vr4300") == 0)
791 else if (strcmp (cpu
, "mips64vr4100") == 0)
799 else if (strcmp (cpu
, "r4010") == 0)
807 else if (strcmp (cpu
, "r5000") == 0
808 || strcmp (cpu
, "mips64vr5000") == 0)
814 /* start-sanitize-r5900 */
815 else if (strcmp (cpu
, "r5900") == 0
816 || strcmp (cpu
, "mips64vr5900") == 0
817 || strcmp (cpu
, "mips64vr5900el") == 0)
825 /* end-sanitize-r5900 */
826 else if (strcmp (cpu
, "r8000") == 0
827 || strcmp (cpu
, "mips4") == 0)
833 else if (strcmp (cpu
, "r10000") == 0)
839 else if (strcmp (cpu
, "mips16") == 0)
843 mips_cpu
= 0; /* FIXME */
858 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
873 /* start-sanitize-r5900 */
876 /* end-sanitize-r5900 */
878 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
883 /* Itbl support may require additional care here. */
884 if (mips_cpu
== 4300)
889 if (mips_isa
< 2 && mips_trap
)
890 as_bad ("trap exception not supported at ISA 1");
895 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
898 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
901 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
904 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
908 as_warn ("Could not set architecture and machine");
910 file_mips_isa
= mips_isa
;
912 op_hash
= hash_new ();
914 for (i
= 0; i
< NUMOPCODES
;)
916 const char *name
= mips_opcodes
[i
].name
;
918 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
921 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
922 mips_opcodes
[i
].name
, retval
);
923 as_fatal ("Broken assembler. No assembly attempted.");
927 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
928 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
929 != mips_opcodes
[i
].match
))
931 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
932 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
933 as_fatal ("Broken assembler. No assembly attempted.");
937 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
940 mips16_op_hash
= hash_new ();
943 while (i
< bfd_mips16_num_opcodes
)
945 const char *name
= mips16_opcodes
[i
].name
;
947 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
949 as_fatal ("internal error: can't hash `%s': %s\n",
950 mips16_opcodes
[i
].name
, retval
);
953 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
954 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
955 != mips16_opcodes
[i
].match
))
956 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
957 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
960 while (i
< bfd_mips16_num_opcodes
961 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
964 /* We add all the general register names to the symbol table. This
965 helps us detect invalid uses of them. */
966 for (i
= 0; i
< 32; i
++)
970 sprintf (buf
, "$%d", i
);
971 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
972 &zero_address_frag
));
974 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
975 &zero_address_frag
));
976 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
977 &zero_address_frag
));
978 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
979 &zero_address_frag
));
980 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
981 &zero_address_frag
));
982 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
983 &zero_address_frag
));
984 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
985 &zero_address_frag
));
986 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
987 &zero_address_frag
));
989 mips_no_prev_insn (false);
997 /* set the default alignment for the text section (2**2) */
998 record_alignment (text_section
, 2);
1000 if (USE_GLOBAL_POINTER_OPT
)
1001 bfd_set_gp_size (stdoutput
, g_switch_value
);
1003 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1005 /* On a native system, sections must be aligned to 16 byte
1006 boundaries. When configured for an embedded ELF target, we
1008 if (strcmp (TARGET_OS
, "elf") != 0)
1010 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1011 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1012 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1015 /* Create a .reginfo section for register masks and a .mdebug
1016 section for debugging information. */
1024 subseg
= now_subseg
;
1026 /* The ABI says this section should be loaded so that the
1027 running program can access it. However, we don't load it
1028 if we are configured for an embedded target */
1029 flags
= SEC_READONLY
| SEC_DATA
;
1030 if (strcmp (TARGET_OS
, "elf") != 0)
1031 flags
|= SEC_ALLOC
| SEC_LOAD
;
1035 sec
= subseg_new (".reginfo", (subsegT
) 0);
1038 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1039 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1042 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1047 /* The 64-bit ABI uses a .MIPS.options section rather than
1048 .reginfo section. */
1049 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1050 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1051 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1054 /* Set up the option header. */
1056 Elf_Internal_Options opthdr
;
1059 opthdr
.kind
= ODK_REGINFO
;
1060 opthdr
.size
= (sizeof (Elf_External_Options
)
1061 + sizeof (Elf64_External_RegInfo
));
1064 f
= frag_more (sizeof (Elf_External_Options
));
1065 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1066 (Elf_External_Options
*) f
);
1068 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1073 if (ECOFF_DEBUGGING
)
1075 sec
= subseg_new (".mdebug", (subsegT
) 0);
1076 (void) bfd_set_section_flags (stdoutput
, sec
,
1077 SEC_HAS_CONTENTS
| SEC_READONLY
);
1078 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1081 subseg_set (seg
, subseg
);
1085 if (! ECOFF_DEBUGGING
)
1092 if (! ECOFF_DEBUGGING
)
1100 struct mips_cl_insn insn
;
1102 imm_expr
.X_op
= O_absent
;
1103 imm_reloc
= BFD_RELOC_UNUSED
;
1104 imm_unmatched_hi
= false;
1105 offset_expr
.X_op
= O_absent
;
1106 offset_reloc
= BFD_RELOC_UNUSED
;
1109 mips16_ip (str
, &insn
);
1112 mips_ip (str
, &insn
);
1113 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1114 str
, insn
.insn_opcode
));
1119 as_bad ("%s `%s'", insn_error
, str
);
1123 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1126 mips16_macro (&insn
);
1132 if (imm_expr
.X_op
!= O_absent
)
1133 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1135 else if (offset_expr
.X_op
!= O_absent
)
1136 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1138 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1142 /* See whether instruction IP reads register REG. CLASS is the type
1146 insn_uses_reg (ip
, reg
, class)
1147 struct mips_cl_insn
*ip
;
1149 enum mips_regclass
class;
1151 if (class == MIPS16_REG
)
1154 reg
= mips16_to_32_reg_map
[reg
];
1155 class = MIPS_GR_REG
;
1158 /* Don't report on general register 0, since it never changes. */
1159 if (class == MIPS_GR_REG
&& reg
== 0)
1162 if (class == MIPS_FP_REG
)
1165 /* If we are called with either $f0 or $f1, we must check $f0.
1166 This is not optimal, because it will introduce an unnecessary
1167 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1168 need to distinguish reading both $f0 and $f1 or just one of
1169 them. Note that we don't have to check the other way,
1170 because there is no instruction that sets both $f0 and $f1
1171 and requires a delay. */
1172 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1173 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1174 == (reg
&~ (unsigned) 1)))
1176 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1177 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1178 == (reg
&~ (unsigned) 1)))
1183 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1184 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1186 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1187 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1192 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1193 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1195 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1196 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1198 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1199 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1200 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1202 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1204 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1206 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1208 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1209 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1210 & MIPS16OP_MASK_REGR32
) == reg
)
1217 /* This function returns true if modifying a register requires a
1221 reg_needs_delay (reg
)
1224 unsigned long prev_pinfo
;
1226 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1227 if (! mips_noreorder
1229 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1231 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1233 /* A load from a coprocessor or from memory. All load
1234 delays delay the use of general register rt for one
1235 instruction on the r3000. The r6000 and r4000 use
1237 /* Itbl support may require additional care here. */
1238 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1239 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1246 /* Output an instruction. PLACE is where to put the instruction; if
1247 it is NULL, this uses frag_more to get room. IP is the instruction
1248 information. ADDRESS_EXPR is an operand of the instruction to be
1249 used with RELOC_TYPE. */
1252 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1254 struct mips_cl_insn
*ip
;
1255 expressionS
*address_expr
;
1256 bfd_reloc_code_real_type reloc_type
;
1257 boolean unmatched_hi
;
1259 register unsigned long prev_pinfo
, pinfo
;
1264 /* Mark instruction labels in mips16 mode. This permits the linker
1265 to handle them specially, such as generating jalx instructions
1266 when needed. We also make them odd for the duration of the
1267 assembly, in order to generate the right sort of code. We will
1268 make them even in the adjust_symtab routine, while leaving them
1269 marked. This is convenient for the debugger and the
1270 disassembler. The linker knows to make them odd again. */
1273 struct insn_label_list
*l
;
1275 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1278 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1279 S_SET_OTHER (l
->label
, STO_MIPS16
);
1281 ++l
->label
->sy_value
.X_add_number
;
1285 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1286 pinfo
= ip
->insn_mo
->pinfo
;
1288 if (place
== NULL
&& (! mips_noreorder
|| prev_nop_frag
!= NULL
))
1292 /* If the previous insn required any delay slots, see if we need
1293 to insert a NOP or two. There are eight kinds of possible
1294 hazards, of which an instruction can have at most one type.
1295 (1) a load from memory delay
1296 (2) a load from a coprocessor delay
1297 (3) an unconditional branch delay
1298 (4) a conditional branch delay
1299 (5) a move to coprocessor register delay
1300 (6) a load coprocessor register from memory delay
1301 (7) a coprocessor condition code delay
1302 (8) a HI/LO special register delay
1304 There are a lot of optimizations we could do that we don't.
1305 In particular, we do not, in general, reorder instructions.
1306 If you use gcc with optimization, it will reorder
1307 instructions and generally do much more optimization then we
1308 do here; repeating all that work in the assembler would only
1309 benefit hand written assembly code, and does not seem worth
1312 /* This is how a NOP is emitted. */
1313 #define emit_nop() \
1315 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1316 : md_number_to_chars (frag_more (4), 0, 4))
1318 /* The previous insn might require a delay slot, depending upon
1319 the contents of the current insn. */
1322 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1323 && ! cop_interlocks
)
1325 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1327 /* A load from a coprocessor or from memory. All load
1328 delays delay the use of general register rt for one
1329 instruction on the r3000. The r6000 and r4000 use
1331 /* Itbl support may require additional care here. */
1332 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1333 if (mips_optimize
== 0
1334 || insn_uses_reg (ip
,
1335 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1342 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1343 && ! cop_interlocks
)
1345 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1347 /* A generic coprocessor delay. The previous instruction
1348 modified a coprocessor general or control register. If
1349 it modified a control register, we need to avoid any
1350 coprocessor instruction (this is probably not always
1351 required, but it sometimes is). If it modified a general
1352 register, we avoid using that register.
1354 On the r6000 and r4000 loading a coprocessor register
1355 from memory is interlocked, and does not require a delay.
1357 This case is not handled very well. There is no special
1358 knowledge of CP0 handling, and the coprocessors other
1359 than the floating point unit are not distinguished at
1361 /* Itbl support may require additional care here. FIXME!
1362 Need to modify this to include knowledge about
1363 user specified delays! */
1364 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1366 if (mips_optimize
== 0
1367 || insn_uses_reg (ip
,
1368 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1373 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1375 if (mips_optimize
== 0
1376 || insn_uses_reg (ip
,
1377 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1384 /* We don't know exactly what the previous instruction
1385 does. If the current instruction uses a coprocessor
1386 register, we must insert a NOP. If previous
1387 instruction may set the condition codes, and the
1388 current instruction uses them, we must insert two
1390 /* Itbl support may require additional care here. */
1391 if (mips_optimize
== 0
1392 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1393 && (pinfo
& INSN_READ_COND_CODE
)))
1395 else if (pinfo
& INSN_COP
)
1401 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1402 && ! cop_interlocks
)
1404 /* The previous instruction sets the coprocessor condition
1405 codes, but does not require a general coprocessor delay
1406 (this means it is a floating point comparison
1407 instruction). If this instruction uses the condition
1408 codes, we need to insert a single NOP. */
1409 /* Itbl support may require additional care here. */
1410 if (mips_optimize
== 0
1411 || (pinfo
& INSN_READ_COND_CODE
))
1414 else if (prev_pinfo
& INSN_READ_LO
)
1416 /* The previous instruction reads the LO register; if the
1417 current instruction writes to the LO register, we must
1418 insert two NOPS. Some newer processors have interlocks. */
1420 && (mips_optimize
== 0
1421 || (pinfo
& INSN_WRITE_LO
)))
1424 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1426 /* The previous instruction reads the HI register; if the
1427 current instruction writes to the HI register, we must
1428 insert a NOP. Some newer processors have interlocks. */
1430 && (mips_optimize
== 0
1431 || (pinfo
& INSN_WRITE_HI
)))
1435 /* If the previous instruction was in a noreorder section, then
1436 we don't want to insert the nop after all. */
1437 /* Itbl support may require additional care here. */
1438 if (prev_insn_unreordered
)
1441 /* There are two cases which require two intervening
1442 instructions: 1) setting the condition codes using a move to
1443 coprocessor instruction which requires a general coprocessor
1444 delay and then reading the condition codes 2) reading the HI
1445 or LO register and then writing to it (except on processors
1446 which have interlocks). If we are not already emitting a NOP
1447 instruction, we must check for these cases compared to the
1448 instruction previous to the previous instruction. */
1451 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1452 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1453 && (pinfo
& INSN_READ_COND_CODE
)
1454 && ! cop_interlocks
)
1455 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1456 && (pinfo
& INSN_WRITE_LO
)
1458 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1459 && (pinfo
& INSN_WRITE_HI
)
1465 if (prev_prev_insn_unreordered
)
1468 if (prev_prev_nop
&& nops
== 0)
1471 /* If we are being given a nop instruction, don't bother with
1472 one of the nops we would otherwise output. This will only
1473 happen when a nop instruction is used with mips_optimize set
1477 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1480 /* Now emit the right number of NOP instructions. */
1481 if (nops
> 0 && ! mips_noreorder
)
1484 unsigned long old_frag_offset
;
1486 struct insn_label_list
*l
;
1488 old_frag
= frag_now
;
1489 old_frag_offset
= frag_now_fix ();
1491 for (i
= 0; i
< nops
; i
++)
1496 listing_prev_line ();
1497 /* We may be at the start of a variant frag. In case we
1498 are, make sure there is enough space for the frag
1499 after the frags created by listing_prev_line. The
1500 argument to frag_grow here must be at least as large
1501 as the argument to all other calls to frag_grow in
1502 this file. We don't have to worry about being in the
1503 middle of a variant frag, because the variants insert
1504 all needed nop instructions themselves. */
1508 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1510 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1511 l
->label
->sy_frag
= frag_now
;
1512 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1513 /* mips16 text labels are stored as odd. */
1515 ++l
->label
->sy_value
.X_add_number
;
1518 #ifndef NO_ECOFF_DEBUGGING
1519 if (ECOFF_DEBUGGING
)
1520 ecoff_fix_loc (old_frag
, old_frag_offset
);
1523 else if (prev_nop_frag
!= NULL
)
1525 /* We have a frag holding nops we may be able to remove. If
1526 we don't need any nops, we can decrease the size of
1527 prev_nop_frag by the size of one instruction. If we do
1528 need some nops, we count them in prev_nops_required. */
1529 if (prev_nop_frag_since
== 0)
1533 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1534 --prev_nop_frag_holds
;
1537 prev_nop_frag_required
+= nops
;
1541 if (prev_prev_nop
== 0)
1543 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1544 --prev_nop_frag_holds
;
1547 ++prev_nop_frag_required
;
1550 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1551 prev_nop_frag
= NULL
;
1553 ++prev_nop_frag_since
;
1555 /* Sanity check: by the time we reach the second instruction
1556 after prev_nop_frag, we should have used up all the nops
1557 one way or another. */
1558 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1562 if (reloc_type
> BFD_RELOC_UNUSED
)
1564 /* We need to set up a variant frag. */
1565 assert (mips16
&& address_expr
!= NULL
);
1566 f
= frag_var (rs_machine_dependent
, 4, 0,
1567 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1568 mips16_small
, mips16_ext
,
1570 & INSN_UNCOND_BRANCH_DELAY
),
1571 (prev_insn_reloc_type
1572 == BFD_RELOC_MIPS16_JMP
)),
1573 make_expr_symbol (address_expr
), (long) 0,
1576 else if (place
!= NULL
)
1578 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1580 /* Make sure there is enough room to swap this instruction with
1581 a following jump instruction. */
1589 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1590 as_warn ("extended instruction in delay slot");
1596 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1598 if (address_expr
->X_op
== O_constant
)
1603 ip
->insn_opcode
|= address_expr
->X_add_number
;
1606 case BFD_RELOC_LO16
:
1607 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1610 case BFD_RELOC_MIPS_JMP
:
1611 if ((address_expr
->X_add_number
& 3) != 0)
1612 as_bad ("jump to misaligned address (0x%lx)",
1613 (unsigned long) address_expr
->X_add_number
);
1614 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1617 case BFD_RELOC_MIPS16_JMP
:
1618 if ((address_expr
->X_add_number
& 3) != 0)
1619 as_bad ("jump to misaligned address (0x%lx)",
1620 (unsigned long) address_expr
->X_add_number
);
1622 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1623 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1624 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1627 case BFD_RELOC_16_PCREL_S2
:
1637 /* Don't generate a reloc if we are writing into a variant
1641 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1643 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1647 struct mips_hi_fixup
*hi_fixup
;
1649 assert (reloc_type
== BFD_RELOC_HI16_S
);
1650 hi_fixup
= ((struct mips_hi_fixup
*)
1651 xmalloc (sizeof (struct mips_hi_fixup
)));
1652 hi_fixup
->fixp
= fixp
;
1653 hi_fixup
->seg
= now_seg
;
1654 hi_fixup
->next
= mips_hi_fixup_list
;
1655 mips_hi_fixup_list
= hi_fixup
;
1662 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1663 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1665 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1666 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1672 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1675 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1678 /* Update the register mask information. */
1681 if (pinfo
& INSN_WRITE_GPR_D
)
1682 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1683 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1684 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1685 if (pinfo
& INSN_READ_GPR_S
)
1686 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1687 if (pinfo
& INSN_WRITE_GPR_31
)
1688 mips_gprmask
|= 1 << 31;
1689 if (pinfo
& INSN_WRITE_FPR_D
)
1690 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1691 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1692 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1693 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1694 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1695 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1696 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1697 if (pinfo
& INSN_COP
)
1699 /* We don't keep enough information to sort these cases out.
1700 The itbl support does keep this information however, although
1701 we currently don't support itbl fprmats as part of the cop
1702 instruction. May want to add this support in the future. */
1704 /* Never set the bit for $0, which is always zero. */
1705 mips_gprmask
&=~ 1 << 0;
1709 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1710 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1711 & MIPS16OP_MASK_RX
);
1712 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1713 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1714 & MIPS16OP_MASK_RY
);
1715 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1716 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1717 & MIPS16OP_MASK_RZ
);
1718 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1719 mips_gprmask
|= 1 << TREG
;
1720 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1721 mips_gprmask
|= 1 << SP
;
1722 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1723 mips_gprmask
|= 1 << RA
;
1724 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1725 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1726 if (pinfo
& MIPS16_INSN_READ_Z
)
1727 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1728 & MIPS16OP_MASK_MOVE32Z
);
1729 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1730 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1731 & MIPS16OP_MASK_REGR32
);
1734 if (place
== NULL
&& ! mips_noreorder
)
1736 /* Filling the branch delay slot is more complex. We try to
1737 switch the branch with the previous instruction, which we can
1738 do if the previous instruction does not set up a condition
1739 that the branch tests and if the branch is not itself the
1740 target of any branch. */
1741 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1742 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1744 if (mips_optimize
< 2
1745 /* If we have seen .set volatile or .set nomove, don't
1748 /* If we had to emit any NOP instructions, then we
1749 already know we can not swap. */
1751 /* If we don't even know the previous insn, we can not
1753 || ! prev_insn_valid
1754 /* If the previous insn is already in a branch delay
1755 slot, then we can not swap. */
1756 || prev_insn_is_delay_slot
1757 /* If the previous previous insn was in a .set
1758 noreorder, we can't swap. Actually, the MIPS
1759 assembler will swap in this situation. However, gcc
1760 configured -with-gnu-as will generate code like
1766 in which we can not swap the bne and INSN. If gcc is
1767 not configured -with-gnu-as, it does not output the
1768 .set pseudo-ops. We don't have to check
1769 prev_insn_unreordered, because prev_insn_valid will
1770 be 0 in that case. We don't want to use
1771 prev_prev_insn_valid, because we do want to be able
1772 to swap at the start of a function. */
1773 || prev_prev_insn_unreordered
1774 /* If the branch is itself the target of a branch, we
1775 can not swap. We cheat on this; all we check for is
1776 whether there is a label on this instruction. If
1777 there are any branches to anything other than a
1778 label, users must use .set noreorder. */
1779 || insn_labels
!= NULL
1780 /* If the previous instruction is in a variant frag, we
1781 can not do the swap. This does not apply to the
1782 mips16, which uses variant frags for different
1785 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1786 /* If the branch reads the condition codes, we don't
1787 even try to swap, because in the sequence
1792 we can not swap, and I don't feel like handling that
1796 && (pinfo
& INSN_READ_COND_CODE
))
1797 /* We can not swap with an instruction that requires a
1798 delay slot, becase the target of the branch might
1799 interfere with that instruction. */
1803 /* Itbl support may require additional care here. */
1804 & (INSN_LOAD_COPROC_DELAY
1805 | INSN_COPROC_MOVE_DELAY
1806 | INSN_WRITE_COND_CODE
)))
1814 & (INSN_LOAD_MEMORY_DELAY
1815 /* Itbl support may require additional care here. */
1816 | INSN_COPROC_MEMORY_DELAY
)))
1817 /* We can not swap with a branch instruction. */
1819 & (INSN_UNCOND_BRANCH_DELAY
1820 | INSN_COND_BRANCH_DELAY
1821 | INSN_COND_BRANCH_LIKELY
))
1822 /* We do not swap with a trap instruction, since it
1823 complicates trap handlers to have the trap
1824 instruction be in a delay slot. */
1825 || (prev_pinfo
& INSN_TRAP
)
1826 /* If the branch reads a register that the previous
1827 instruction sets, we can not swap. */
1829 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1830 && insn_uses_reg (ip
,
1831 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1835 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1836 && insn_uses_reg (ip
,
1837 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1841 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1842 && insn_uses_reg (ip
,
1843 ((prev_insn
.insn_opcode
1845 & MIPS16OP_MASK_RX
),
1847 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1848 && insn_uses_reg (ip
,
1849 ((prev_insn
.insn_opcode
1851 & MIPS16OP_MASK_RY
),
1853 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1854 && insn_uses_reg (ip
,
1855 ((prev_insn
.insn_opcode
1857 & MIPS16OP_MASK_RZ
),
1859 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1860 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1861 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1862 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1863 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1864 && insn_uses_reg (ip
,
1865 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1868 /* If the branch writes a register that the previous
1869 instruction sets, we can not swap (we know that
1870 branches write only to RD or to $31). */
1872 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1873 && (((pinfo
& INSN_WRITE_GPR_D
)
1874 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1875 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1876 || ((pinfo
& INSN_WRITE_GPR_31
)
1877 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1881 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1882 && (((pinfo
& INSN_WRITE_GPR_D
)
1883 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1884 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1885 || ((pinfo
& INSN_WRITE_GPR_31
)
1886 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1890 && (pinfo
& MIPS16_INSN_WRITE_31
)
1891 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1892 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1893 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1895 /* If the branch writes a register that the previous
1896 instruction reads, we can not swap (we know that
1897 branches only write to RD or to $31). */
1899 && (pinfo
& INSN_WRITE_GPR_D
)
1900 && insn_uses_reg (&prev_insn
,
1901 ((ip
->insn_opcode
>> OP_SH_RD
)
1905 && (pinfo
& INSN_WRITE_GPR_31
)
1906 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1908 && (pinfo
& MIPS16_INSN_WRITE_31
)
1909 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1910 /* If we are generating embedded PIC code, the branch
1911 might be expanded into a sequence which uses $at, so
1912 we can't swap with an instruction which reads it. */
1913 || (mips_pic
== EMBEDDED_PIC
1914 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1915 /* If the previous previous instruction has a load
1916 delay, and sets a register that the branch reads, we
1920 /* Itbl support may require additional care here. */
1921 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1923 && (prev_prev_insn
.insn_mo
->pinfo
1924 & INSN_LOAD_MEMORY_DELAY
)))
1925 && insn_uses_reg (ip
,
1926 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1929 /* If one instruction sets a condition code and the
1930 other one uses a condition code, we can not swap. */
1931 || ((pinfo
& INSN_READ_COND_CODE
)
1932 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1933 || ((pinfo
& INSN_WRITE_COND_CODE
)
1934 && (prev_pinfo
& INSN_READ_COND_CODE
))
1935 /* If the previous instruction uses the PC, we can not
1938 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1939 /* If the previous instruction was extended, we can not
1941 || (mips16
&& prev_insn_extended
)
1942 /* If the previous instruction had a fixup in mips16
1943 mode, we can not swap. This normally means that the
1944 previous instruction was a 4 byte branch anyhow. */
1945 || (mips16
&& prev_insn_fixp
))
1947 /* We could do even better for unconditional branches to
1948 portions of this object file; we could pick up the
1949 instruction at the destination, put it in the delay
1950 slot, and bump the destination address. */
1952 /* Update the previous insn information. */
1953 prev_prev_insn
= *ip
;
1954 prev_insn
.insn_mo
= &dummy_opcode
;
1958 /* It looks like we can actually do the swap. */
1964 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1965 memcpy (temp
, prev_f
, 4);
1966 memcpy (prev_f
, f
, 4);
1967 memcpy (f
, temp
, 4);
1970 prev_insn_fixp
->fx_frag
= frag_now
;
1971 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1975 fixp
->fx_frag
= prev_insn_frag
;
1976 fixp
->fx_where
= prev_insn_where
;
1984 assert (prev_insn_fixp
== NULL
);
1985 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1986 memcpy (temp
, prev_f
, 2);
1987 memcpy (prev_f
, f
, 2);
1988 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1990 assert (reloc_type
== BFD_RELOC_UNUSED
);
1991 memcpy (f
, temp
, 2);
1995 memcpy (f
, f
+ 2, 2);
1996 memcpy (f
+ 2, temp
, 2);
2000 fixp
->fx_frag
= prev_insn_frag
;
2001 fixp
->fx_where
= prev_insn_where
;
2005 /* Update the previous insn information; leave prev_insn
2007 prev_prev_insn
= *ip
;
2009 prev_insn_is_delay_slot
= 1;
2011 /* If that was an unconditional branch, forget the previous
2012 insn information. */
2013 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2015 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2016 prev_insn
.insn_mo
= &dummy_opcode
;
2019 prev_insn_fixp
= NULL
;
2020 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2021 prev_insn_extended
= 0;
2023 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2025 /* We don't yet optimize a branch likely. What we should do
2026 is look at the target, copy the instruction found there
2027 into the delay slot, and increment the branch to jump to
2028 the next instruction. */
2030 /* Update the previous insn information. */
2031 prev_prev_insn
= *ip
;
2032 prev_insn
.insn_mo
= &dummy_opcode
;
2033 prev_insn_fixp
= NULL
;
2034 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2035 prev_insn_extended
= 0;
2039 /* Update the previous insn information. */
2041 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2043 prev_prev_insn
= prev_insn
;
2046 /* Any time we see a branch, we always fill the delay slot
2047 immediately; since this insn is not a branch, we know it
2048 is not in a delay slot. */
2049 prev_insn_is_delay_slot
= 0;
2051 prev_insn_fixp
= fixp
;
2052 prev_insn_reloc_type
= reloc_type
;
2054 prev_insn_extended
= (ip
->use_extend
2055 || reloc_type
> BFD_RELOC_UNUSED
);
2058 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2059 prev_insn_unreordered
= 0;
2060 prev_insn_frag
= frag_now
;
2061 prev_insn_where
= f
- frag_now
->fr_literal
;
2062 prev_insn_valid
= 1;
2064 else if (place
== NULL
)
2066 /* We need to record a bit of information even when we are not
2067 reordering, in order to determine the base address for mips16
2068 PC relative relocs. */
2069 prev_prev_insn
= prev_insn
;
2071 prev_insn_reloc_type
= reloc_type
;
2072 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2073 prev_insn_unreordered
= 1;
2076 /* We just output an insn, so the next one doesn't have a label. */
2077 mips_clear_insn_labels ();
2080 /* This function forgets that there was any previous instruction or
2081 label. If PRESERVE is non-zero, it remembers enough information to
2082 know whether nops are needed before a noreorder section. */
2085 mips_no_prev_insn (preserve
)
2090 prev_insn
.insn_mo
= &dummy_opcode
;
2091 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2092 prev_nop_frag
= NULL
;
2093 prev_nop_frag_holds
= 0;
2094 prev_nop_frag_required
= 0;
2095 prev_nop_frag_since
= 0;
2097 prev_insn_valid
= 0;
2098 prev_insn_is_delay_slot
= 0;
2099 prev_insn_unreordered
= 0;
2100 prev_insn_extended
= 0;
2101 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2102 prev_prev_insn_unreordered
= 0;
2103 mips_clear_insn_labels ();
2106 /* This function must be called whenever we turn on noreorder or emit
2107 something other than instructions. It inserts any NOPS which might
2108 be needed by the previous instruction, and clears the information
2109 kept for the previous instructions. The INSNS parameter is true if
2110 instructions are to follow. */
2113 mips_emit_delays (insns
)
2116 if (! mips_noreorder
)
2123 && (! cop_interlocks
2124 && (prev_insn
.insn_mo
->pinfo
2125 & (INSN_LOAD_COPROC_DELAY
2126 | INSN_COPROC_MOVE_DELAY
2127 | INSN_WRITE_COND_CODE
))))
2129 && (prev_insn
.insn_mo
->pinfo
2134 && (prev_insn
.insn_mo
->pinfo
2135 & (INSN_LOAD_MEMORY_DELAY
2136 | INSN_COPROC_MEMORY_DELAY
))))
2138 /* Itbl support may require additional care here. */
2142 && (! cop_interlocks
2143 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2145 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2146 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2149 if (prev_insn_unreordered
)
2154 && (! cop_interlocks
2155 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2157 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2158 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2160 /* Itbl support may require additional care here. */
2161 if (! prev_prev_insn_unreordered
)
2167 struct insn_label_list
*l
;
2171 /* Record the frag which holds the nop instructions, so
2172 that we can remove them if we don't need them. */
2173 frag_grow (mips16
? nops
* 2 : nops
* 4);
2174 prev_nop_frag
= frag_now
;
2175 prev_nop_frag_holds
= nops
;
2176 prev_nop_frag_required
= 0;
2177 prev_nop_frag_since
= 0;
2180 for (; nops
> 0; --nops
)
2185 /* Move on to a new frag, so that it is safe to simply
2186 decrease the size of prev_nop_frag. */
2187 frag_wane (frag_now
);
2191 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2193 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2194 l
->label
->sy_frag
= frag_now
;
2195 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2196 /* mips16 text labels are stored as odd. */
2198 ++l
->label
->sy_value
.X_add_number
;
2203 /* Mark instruction labels in mips16 mode. This permits the linker
2204 to handle them specially, such as generating jalx instructions
2205 when needed. We also make them odd for the duration of the
2206 assembly, in order to generate the right sort of code. We will
2207 make them even in the adjust_symtab routine, while leaving them
2208 marked. This is convenient for the debugger and the
2209 disassembler. The linker knows to make them odd again. */
2210 if (mips16
&& insns
)
2212 struct insn_label_list
*l
;
2214 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2217 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2218 S_SET_OTHER (l
->label
, STO_MIPS16
);
2220 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2221 ++l
->label
->sy_value
.X_add_number
;
2225 mips_no_prev_insn (insns
);
2228 /* Build an instruction created by a macro expansion. This is passed
2229 a pointer to the count of instructions created so far, an
2230 expression, the name of the instruction to build, an operand format
2231 string, and corresponding arguments. */
2235 macro_build (char *place
,
2243 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2252 struct mips_cl_insn insn
;
2253 bfd_reloc_code_real_type r
;
2257 va_start (args
, fmt
);
2263 * If the macro is about to expand into a second instruction,
2264 * print a warning if needed. We need to pass ip as a parameter
2265 * to generate a better warning message here...
2267 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2268 as_warn ("Macro instruction expanded into multiple instructions");
2271 *counter
+= 1; /* bump instruction counter */
2275 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2280 r
= BFD_RELOC_UNUSED
;
2281 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2282 assert (insn
.insn_mo
);
2283 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2285 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2286 || insn
.insn_mo
->pinfo
== INSN_MACRO
2287 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2289 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2291 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2293 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2295 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2297 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2299 /* start-sanitize-r5900 */
2300 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2302 /* end-sanitize-r5900 */
2306 assert (insn
.insn_mo
->name
);
2307 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2309 insn
.insn_opcode
= insn
.insn_mo
->match
;
2325 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2331 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2336 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2341 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2348 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2352 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2356 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2363 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2369 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2370 assert (r
== BFD_RELOC_MIPS_GPREL
2371 || r
== BFD_RELOC_MIPS_LITERAL
2372 || r
== BFD_RELOC_LO16
2373 || r
== BFD_RELOC_MIPS_GOT16
2374 || r
== BFD_RELOC_MIPS_CALL16
2375 || r
== BFD_RELOC_MIPS_GOT_LO16
2376 || r
== BFD_RELOC_MIPS_CALL_LO16
2377 || (ep
->X_op
== O_subtract
2378 && now_seg
== text_section
2379 && r
== BFD_RELOC_PCREL_LO16
));
2383 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2385 && (ep
->X_op
== O_constant
2386 || (ep
->X_op
== O_symbol
2387 && (r
== BFD_RELOC_HI16_S
2388 || r
== BFD_RELOC_HI16
2389 || r
== BFD_RELOC_MIPS_GOT_HI16
2390 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2391 || (ep
->X_op
== O_subtract
2392 && now_seg
== text_section
2393 && r
== BFD_RELOC_PCREL_HI16_S
)));
2394 if (ep
->X_op
== O_constant
)
2396 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2398 r
= BFD_RELOC_UNUSED
;
2403 assert (ep
!= NULL
);
2405 * This allows macro() to pass an immediate expression for
2406 * creating short branches without creating a symbol.
2407 * Note that the expression still might come from the assembly
2408 * input, in which case the value is not checked for range nor
2409 * is a relocation entry generated (yuck).
2411 if (ep
->X_op
== O_constant
)
2413 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2417 r
= BFD_RELOC_16_PCREL_S2
;
2421 assert (ep
!= NULL
);
2422 r
= BFD_RELOC_MIPS_JMP
;
2431 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2433 append_insn (place
, &insn
, ep
, r
, false);
2437 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2445 struct mips_cl_insn insn
;
2446 bfd_reloc_code_real_type r
;
2448 r
= BFD_RELOC_UNUSED
;
2449 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2450 assert (insn
.insn_mo
);
2451 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2453 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2454 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2457 assert (insn
.insn_mo
->name
);
2458 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2461 insn
.insn_opcode
= insn
.insn_mo
->match
;
2462 insn
.use_extend
= false;
2481 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2486 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2490 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2494 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2504 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2511 regno
= va_arg (args
, int);
2512 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2513 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2534 assert (ep
!= NULL
);
2536 if (ep
->X_op
!= O_constant
)
2537 r
= BFD_RELOC_UNUSED
+ c
;
2540 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2541 false, false, &insn
.insn_opcode
,
2542 &insn
.use_extend
, &insn
.extend
);
2544 r
= BFD_RELOC_UNUSED
;
2550 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2557 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2559 append_insn (place
, &insn
, ep
, r
, false);
2563 * Generate a "lui" instruction.
2566 macro_build_lui (place
, counter
, ep
, regnum
)
2572 expressionS high_expr
;
2573 struct mips_cl_insn insn
;
2574 bfd_reloc_code_real_type r
;
2575 CONST
char *name
= "lui";
2576 CONST
char *fmt
= "t,u";
2584 high_expr
.X_op
= O_constant
;
2585 high_expr
.X_add_number
= ep
->X_add_number
;
2588 if (high_expr
.X_op
== O_constant
)
2590 /* we can compute the instruction now without a relocation entry */
2591 if (high_expr
.X_add_number
& 0x8000)
2592 high_expr
.X_add_number
+= 0x10000;
2593 high_expr
.X_add_number
=
2594 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2595 r
= BFD_RELOC_UNUSED
;
2599 assert (ep
->X_op
== O_symbol
);
2600 /* _gp_disp is a special case, used from s_cpload. */
2601 assert (mips_pic
== NO_PIC
2602 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2603 r
= BFD_RELOC_HI16_S
;
2607 * If the macro is about to expand into a second instruction,
2608 * print a warning if needed. We need to pass ip as a parameter
2609 * to generate a better warning message here...
2611 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2612 as_warn ("Macro instruction expanded into multiple instructions");
2615 *counter
+= 1; /* bump instruction counter */
2617 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2618 assert (insn
.insn_mo
);
2619 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2620 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2622 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2623 if (r
== BFD_RELOC_UNUSED
)
2625 insn
.insn_opcode
|= high_expr
.X_add_number
;
2626 append_insn (place
, &insn
, NULL
, r
, false);
2629 append_insn (place
, &insn
, &high_expr
, r
, false);
2633 * Generates code to set the $at register to true (one)
2634 * if reg is less than the immediate expression.
2637 set_at (counter
, reg
, unsignedp
)
2642 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2643 macro_build ((char *) NULL
, counter
, &imm_expr
,
2644 unsignedp
? "sltiu" : "slti",
2645 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2648 load_register (counter
, AT
, &imm_expr
, 0);
2649 macro_build ((char *) NULL
, counter
, NULL
,
2650 unsignedp
? "sltu" : "slt",
2651 "d,v,t", AT
, reg
, AT
);
2655 /* Warn if an expression is not a constant. */
2658 check_absolute_expr (ip
, ex
)
2659 struct mips_cl_insn
*ip
;
2662 if (ex
->X_op
!= O_constant
)
2663 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2666 /* Count the leading zeroes by performing a binary chop. This is a
2667 bulky bit of source, but performance is a LOT better for the
2668 majority of values than a simple loop to count the bits:
2669 for (lcnt = 0; (lcnt < 32); lcnt++)
2670 if ((v) & (1 << (31 - lcnt)))
2672 However it is not code size friendly, and the gain will drop a bit
2673 on certain cached systems.
2675 #define COUNT_TOP_ZEROES(v) \
2676 (((v) & ~0xffff) == 0 \
2677 ? ((v) & ~0xff) == 0 \
2678 ? ((v) & ~0xf) == 0 \
2679 ? ((v) & ~0x3) == 0 \
2680 ? ((v) & ~0x1) == 0 \
2685 : ((v) & ~0x7) == 0 \
2688 : ((v) & ~0x3f) == 0 \
2689 ? ((v) & ~0x1f) == 0 \
2692 : ((v) & ~0x7f) == 0 \
2695 : ((v) & ~0xfff) == 0 \
2696 ? ((v) & ~0x3ff) == 0 \
2697 ? ((v) & ~0x1ff) == 0 \
2700 : ((v) & ~0x7ff) == 0 \
2703 : ((v) & ~0x3fff) == 0 \
2704 ? ((v) & ~0x1fff) == 0 \
2707 : ((v) & ~0x7fff) == 0 \
2710 : ((v) & ~0xffffff) == 0 \
2711 ? ((v) & ~0xfffff) == 0 \
2712 ? ((v) & ~0x3ffff) == 0 \
2713 ? ((v) & ~0x1ffff) == 0 \
2716 : ((v) & ~0x7ffff) == 0 \
2719 : ((v) & ~0x3fffff) == 0 \
2720 ? ((v) & ~0x1fffff) == 0 \
2723 : ((v) & ~0x7fffff) == 0 \
2726 : ((v) & ~0xfffffff) == 0 \
2727 ? ((v) & ~0x3ffffff) == 0 \
2728 ? ((v) & ~0x1ffffff) == 0 \
2731 : ((v) & ~0x7ffffff) == 0 \
2734 : ((v) & ~0x3fffffff) == 0 \
2735 ? ((v) & ~0x1fffffff) == 0 \
2738 : ((v) & ~0x7fffffff) == 0 \
2743 * This routine generates the least number of instructions neccessary to load
2744 * an absolute expression value into a register.
2747 load_register (counter
, reg
, ep
, dbl
)
2754 expressionS hi32
, lo32
;
2756 if (ep
->X_op
!= O_big
)
2758 assert (ep
->X_op
== O_constant
);
2759 if (ep
->X_add_number
< 0x8000
2760 && (ep
->X_add_number
>= 0
2761 || (ep
->X_add_number
>= -0x8000
2764 || sizeof (ep
->X_add_number
) > 4))))
2766 /* We can handle 16 bit signed values with an addiu to
2767 $zero. No need to ever use daddiu here, since $zero and
2768 the result are always correct in 32 bit mode. */
2769 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2770 (int) BFD_RELOC_LO16
);
2773 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2775 /* We can handle 16 bit unsigned values with an ori to
2777 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2778 (int) BFD_RELOC_LO16
);
2781 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2782 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2783 == ~ (offsetT
) 0x7fffffff))
2786 || sizeof (ep
->X_add_number
) > 4
2787 || (ep
->X_add_number
& 0x80000000) == 0))
2788 || ((mips_isa
< 3 || !dbl
)
2789 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2791 /* 32 bit values require an lui. */
2792 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2793 (int) BFD_RELOC_HI16
);
2794 if ((ep
->X_add_number
& 0xffff) != 0)
2795 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2796 (int) BFD_RELOC_LO16
);
2801 /* The value is larger than 32 bits. */
2805 as_bad ("Number larger than 32 bits");
2806 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2807 (int) BFD_RELOC_LO16
);
2811 if (ep
->X_op
!= O_big
)
2814 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2815 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2816 hi32
.X_add_number
&= 0xffffffff;
2818 lo32
.X_add_number
&= 0xffffffff;
2822 assert (ep
->X_add_number
> 2);
2823 if (ep
->X_add_number
== 3)
2824 generic_bignum
[3] = 0;
2825 else if (ep
->X_add_number
> 4)
2826 as_bad ("Number larger than 64 bits");
2827 lo32
.X_op
= O_constant
;
2828 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2829 hi32
.X_op
= O_constant
;
2830 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2833 if (hi32
.X_add_number
== 0)
2838 unsigned long hi
, lo
;
2840 if (hi32
.X_add_number
== 0xffffffff)
2842 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2844 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2845 reg
, 0, (int) BFD_RELOC_LO16
);
2848 if (lo32
.X_add_number
& 0x80000000)
2850 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2851 (int) BFD_RELOC_HI16
);
2852 if (lo32
.X_add_number
& 0xffff)
2853 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2854 reg
, reg
, (int) BFD_RELOC_LO16
);
2859 /* Check for 16bit shifted constant. We know that hi32 is
2860 non-zero, so start the mask on the first bit of the hi32
2865 unsigned long himask
, lomask
;
2869 himask
= 0xffff >> (32 - shift
);
2870 lomask
= (0xffff << shift
) & 0xffffffff;
2874 himask
= 0xffff << (shift
- 32);
2877 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2878 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2882 tmp
.X_op
= O_constant
;
2884 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2885 | (lo32
.X_add_number
>> shift
));
2887 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2888 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2889 (int) BFD_RELOC_LO16
);
2890 macro_build ((char *) NULL
, counter
, NULL
,
2891 (shift
>= 32) ? "dsll32" : "dsll",
2893 (shift
>= 32) ? shift
- 32 : shift
);
2897 } while (shift
<= (64 - 16));
2899 /* Find the bit number of the lowest one bit, and store the
2900 shifted value in hi/lo. */
2901 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2902 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2906 while ((lo
& 1) == 0)
2911 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2917 while ((hi
& 1) == 0)
2926 /* Optimize if the shifted value is a (power of 2) - 1. */
2927 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2928 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2930 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2935 /* This instruction will set the register to be all
2937 tmp
.X_op
= O_constant
;
2938 tmp
.X_add_number
= (offsetT
) -1;
2939 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2940 reg
, 0, (int) BFD_RELOC_LO16
);
2944 macro_build ((char *) NULL
, counter
, NULL
,
2945 (bit
>= 32) ? "dsll32" : "dsll",
2947 (bit
>= 32) ? bit
- 32 : bit
);
2949 macro_build ((char *) NULL
, counter
, NULL
,
2950 (shift
>= 32) ? "dsrl32" : "dsrl",
2952 (shift
>= 32) ? shift
- 32 : shift
);
2957 /* Sign extend hi32 before calling load_register, because we can
2958 generally get better code when we load a sign extended value. */
2959 if ((hi32
.X_add_number
& 0x80000000) != 0)
2960 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2961 load_register (counter
, reg
, &hi32
, 0);
2964 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2968 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2977 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2979 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2980 (int) BFD_RELOC_HI16
);
2981 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2988 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2993 mid16
.X_add_number
>>= 16;
2994 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2995 freg
, (int) BFD_RELOC_LO16
);
2996 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3000 if ((lo32
.X_add_number
& 0xffff) != 0)
3001 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3002 (int) BFD_RELOC_LO16
);
3005 /* Load an address into a register. */
3008 load_address (counter
, reg
, ep
)
3015 if (ep
->X_op
!= O_constant
3016 && ep
->X_op
!= O_symbol
)
3018 as_bad ("expression too complex");
3019 ep
->X_op
= O_constant
;
3022 if (ep
->X_op
== O_constant
)
3024 load_register (counter
, reg
, ep
, 0);
3028 if (mips_pic
== NO_PIC
)
3030 /* If this is a reference to a GP relative symbol, we want
3031 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3033 lui $reg,<sym> (BFD_RELOC_HI16_S)
3034 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3035 If we have an addend, we always use the latter form. */
3036 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3037 || nopic_need_relax (ep
->X_add_symbol
))
3042 macro_build ((char *) NULL
, counter
, ep
,
3043 mips_isa
< 3 ? "addiu" : "daddiu",
3044 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3045 p
= frag_var (rs_machine_dependent
, 8, 0,
3046 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
3047 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3049 macro_build_lui (p
, counter
, ep
, reg
);
3052 macro_build (p
, counter
, ep
,
3053 mips_isa
< 3 ? "addiu" : "daddiu",
3054 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3056 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3060 /* If this is a reference to an external symbol, we want
3061 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3063 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3065 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3066 If there is a constant, it must be added in after. */
3067 ex
.X_add_number
= ep
->X_add_number
;
3068 ep
->X_add_number
= 0;
3070 macro_build ((char *) NULL
, counter
, ep
,
3071 mips_isa
< 3 ? "lw" : "ld",
3072 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3073 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3074 p
= frag_var (rs_machine_dependent
, 4, 0,
3075 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
3076 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3077 macro_build (p
, counter
, ep
,
3078 mips_isa
< 3 ? "addiu" : "daddiu",
3079 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3080 if (ex
.X_add_number
!= 0)
3082 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3083 as_bad ("PIC code offset overflow (max 16 signed bits)");
3084 ex
.X_op
= O_constant
;
3085 macro_build ((char *) NULL
, counter
, &ex
,
3086 mips_isa
< 3 ? "addiu" : "daddiu",
3087 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3090 else if (mips_pic
== SVR4_PIC
)
3095 /* This is the large GOT case. If this is a reference to an
3096 external symbol, we want
3097 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3099 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3100 Otherwise, for a reference to a local symbol, we want
3101 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3103 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3104 If there is a constant, it must be added in after. */
3105 ex
.X_add_number
= ep
->X_add_number
;
3106 ep
->X_add_number
= 0;
3107 if (reg_needs_delay (GP
))
3112 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3113 (int) BFD_RELOC_MIPS_GOT_HI16
);
3114 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3115 mips_isa
< 3 ? "addu" : "daddu",
3116 "d,v,t", reg
, reg
, GP
);
3117 macro_build ((char *) NULL
, counter
, ep
,
3118 mips_isa
< 3 ? "lw" : "ld",
3119 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3120 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3121 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3122 mips_warn_about_macros
),
3123 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3126 /* We need a nop before loading from $gp. This special
3127 check is required because the lui which starts the main
3128 instruction stream does not refer to $gp, and so will not
3129 insert the nop which may be required. */
3130 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3133 macro_build (p
, counter
, ep
,
3134 mips_isa
< 3 ? "lw" : "ld",
3135 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3137 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3139 macro_build (p
, counter
, ep
,
3140 mips_isa
< 3 ? "addiu" : "daddiu",
3141 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3142 if (ex
.X_add_number
!= 0)
3144 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3145 as_bad ("PIC code offset overflow (max 16 signed bits)");
3146 ex
.X_op
= O_constant
;
3147 macro_build ((char *) NULL
, counter
, &ex
,
3148 mips_isa
< 3 ? "addiu" : "daddiu",
3149 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3152 else if (mips_pic
== EMBEDDED_PIC
)
3155 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3157 macro_build ((char *) NULL
, counter
, ep
,
3158 mips_isa
< 3 ? "addiu" : "daddiu",
3159 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3167 * This routine implements the seemingly endless macro or synthesized
3168 * instructions and addressing modes in the mips assembly language. Many
3169 * of these macros are simple and are similar to each other. These could
3170 * probably be handled by some kind of table or grammer aproach instead of
3171 * this verbose method. Others are not simple macros but are more like
3172 * optimizing code generation.
3173 * One interesting optimization is when several store macros appear
3174 * consecutivly that would load AT with the upper half of the same address.
3175 * The ensuing load upper instructions are ommited. This implies some kind
3176 * of global optimization. We currently only optimize within a single macro.
3177 * For many of the load and store macros if the address is specified as a
3178 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3179 * first load register 'at' with zero and use it as the base register. The
3180 * mips assembler simply uses register $zero. Just one tiny optimization
3185 struct mips_cl_insn
*ip
;
3187 register int treg
, sreg
, dreg
, breg
;
3202 bfd_reloc_code_real_type r
;
3204 int hold_mips_optimize
;
3208 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3209 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3210 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3211 mask
= ip
->insn_mo
->mask
;
3213 expr1
.X_op
= O_constant
;
3214 expr1
.X_op_symbol
= NULL
;
3215 expr1
.X_add_symbol
= NULL
;
3216 expr1
.X_add_number
= 1;
3228 mips_emit_delays (true);
3230 mips_any_noreorder
= 1;
3232 expr1
.X_add_number
= 8;
3233 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3235 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3237 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3238 macro_build ((char *) NULL
, &icnt
, NULL
,
3239 dbl
? "dsub" : "sub",
3240 "d,v,t", dreg
, 0, sreg
);
3263 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3265 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3266 (int) BFD_RELOC_LO16
);
3269 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3270 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3289 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3291 if (mask
!= M_NOR_I
)
3292 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3293 sreg
, (int) BFD_RELOC_LO16
);
3296 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3297 treg
, sreg
, (int) BFD_RELOC_LO16
);
3298 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3304 load_register (&icnt
, AT
, &imm_expr
, 0);
3305 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3322 if (imm_expr
.X_add_number
== 0)
3324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3328 load_register (&icnt
, AT
, &imm_expr
, 0);
3329 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3337 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3338 likely
? "bgezl" : "bgez",
3344 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3345 likely
? "blezl" : "blez",
3349 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3350 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3351 likely
? "beql" : "beq",
3358 /* check for > max integer */
3359 maxnum
= 0x7fffffff;
3367 if (imm_expr
.X_add_number
>= maxnum
3368 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3371 /* result is always false */
3374 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3375 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3379 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3380 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3385 imm_expr
.X_add_number
++;
3389 if (mask
== M_BGEL_I
)
3391 if (imm_expr
.X_add_number
== 0)
3393 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3394 likely
? "bgezl" : "bgez",
3398 if (imm_expr
.X_add_number
== 1)
3400 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3401 likely
? "bgtzl" : "bgtz",
3405 maxnum
= 0x7fffffff;
3413 maxnum
= - maxnum
- 1;
3414 if (imm_expr
.X_add_number
<= maxnum
3415 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3418 /* result is always true */
3419 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3420 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3423 set_at (&icnt
, sreg
, 0);
3424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3425 likely
? "beql" : "beq",
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3437 likely
? "beql" : "beq",
3441 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3443 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3444 likely
? "beql" : "beq",
3451 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3453 imm_expr
.X_add_number
++;
3457 if (mask
== M_BGEUL_I
)
3459 if (imm_expr
.X_add_number
== 0)
3461 if (imm_expr
.X_add_number
== 1)
3463 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3464 likely
? "bnel" : "bne",
3468 set_at (&icnt
, sreg
, 1);
3469 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3470 likely
? "beql" : "beq",
3479 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3480 likely
? "bgtzl" : "bgtz",
3486 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3487 likely
? "bltzl" : "bltz",
3491 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3493 likely
? "bnel" : "bne",
3502 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3503 likely
? "bnel" : "bne",
3509 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3511 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3512 likely
? "bnel" : "bne",
3521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3522 likely
? "blezl" : "blez",
3528 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3529 likely
? "bgezl" : "bgez",
3533 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3534 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3535 likely
? "beql" : "beq",
3542 maxnum
= 0x7fffffff;
3550 if (imm_expr
.X_add_number
>= maxnum
3551 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3553 imm_expr
.X_add_number
++;
3557 if (mask
== M_BLTL_I
)
3559 if (imm_expr
.X_add_number
== 0)
3561 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3562 likely
? "bltzl" : "bltz",
3566 if (imm_expr
.X_add_number
== 1)
3568 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3569 likely
? "blezl" : "blez",
3573 set_at (&icnt
, sreg
, 0);
3574 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3575 likely
? "bnel" : "bne",
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3585 likely
? "beql" : "beq",
3591 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3593 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3594 likely
? "beql" : "beq",
3601 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3603 imm_expr
.X_add_number
++;
3607 if (mask
== M_BLTUL_I
)
3609 if (imm_expr
.X_add_number
== 0)
3611 if (imm_expr
.X_add_number
== 1)
3613 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3614 likely
? "beql" : "beq",
3618 set_at (&icnt
, sreg
, 1);
3619 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3620 likely
? "bnel" : "bne",
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3630 likely
? "bltzl" : "bltz",
3636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3637 likely
? "bgtzl" : "bgtz",
3641 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3642 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3643 likely
? "bnel" : "bne",
3654 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3655 likely
? "bnel" : "bne",
3659 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3661 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3662 likely
? "bnel" : "bne",
3678 as_warn ("Divide by zero.");
3680 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3682 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3686 mips_emit_delays (true);
3688 mips_any_noreorder
= 1;
3689 macro_build ((char *) NULL
, &icnt
, NULL
,
3690 dbl
? "ddiv" : "div",
3691 "z,s,t", sreg
, treg
);
3693 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3696 expr1
.X_add_number
= 8;
3697 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3698 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3701 expr1
.X_add_number
= -1;
3702 macro_build ((char *) NULL
, &icnt
, &expr1
,
3703 dbl
? "daddiu" : "addiu",
3704 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3705 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3706 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3709 expr1
.X_add_number
= 1;
3710 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3711 (int) BFD_RELOC_LO16
);
3712 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3717 expr1
.X_add_number
= 0x80000000;
3718 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3719 (int) BFD_RELOC_HI16
);
3722 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3725 expr1
.X_add_number
= 8;
3726 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3727 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3728 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3731 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3770 if (imm_expr
.X_add_number
== 0)
3772 as_warn ("Divide by zero.");
3774 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3776 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3779 if (imm_expr
.X_add_number
== 1)
3781 if (strcmp (s2
, "mflo") == 0)
3782 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3785 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3788 if (imm_expr
.X_add_number
== -1
3789 && s
[strlen (s
) - 1] != 'u')
3791 if (strcmp (s2
, "mflo") == 0)
3794 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3801 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3805 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3806 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3807 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3826 mips_emit_delays (true);
3828 mips_any_noreorder
= 1;
3829 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3831 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3834 expr1
.X_add_number
= 8;
3835 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3836 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3837 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3840 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3846 /* Load the address of a symbol into a register. If breg is not
3847 zero, we then add a base register to it. */
3849 /* When generating embedded PIC code, we permit expressions of
3852 where bar is an address in the .text section. These are used
3853 when getting the addresses of functions. We don't permit
3854 X_add_number to be non-zero, because if the symbol is
3855 external the relaxing code needs to know that any addend is
3856 purely the offset to X_op_symbol. */
3857 if (mips_pic
== EMBEDDED_PIC
3858 && offset_expr
.X_op
== O_subtract
3859 && now_seg
== text_section
3860 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3861 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3862 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3863 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3864 ->sy_value
.X_add_symbol
)
3867 && offset_expr
.X_add_number
== 0)
3869 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3870 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3871 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3872 mips_isa
< 3 ? "addiu" : "daddiu",
3873 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3877 if (offset_expr
.X_op
!= O_symbol
3878 && offset_expr
.X_op
!= O_constant
)
3880 as_bad ("expression too complex");
3881 offset_expr
.X_op
= O_constant
;
3895 if (offset_expr
.X_op
== O_constant
)
3896 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3897 else if (mips_pic
== NO_PIC
)
3899 /* If this is a reference to an GP relative symbol, we want
3900 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3902 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3903 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3904 If we have a constant, we need two instructions anyhow,
3905 so we may as well always use the latter form. */
3906 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3907 || nopic_need_relax (offset_expr
.X_add_symbol
))
3912 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3913 mips_isa
< 3 ? "addiu" : "daddiu",
3914 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3915 p
= frag_var (rs_machine_dependent
, 8, 0,
3916 RELAX_ENCODE (4, 8, 0, 4, 0,
3917 mips_warn_about_macros
),
3918 offset_expr
.X_add_symbol
, (long) 0,
3921 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3924 macro_build (p
, &icnt
, &offset_expr
,
3925 mips_isa
< 3 ? "addiu" : "daddiu",
3926 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3928 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3930 /* If this is a reference to an external symbol, and there
3931 is no constant, we want
3932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3933 For a local symbol, we want
3934 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3936 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3938 If we have a small constant, and this is a reference to
3939 an external symbol, we want
3940 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3942 addiu $tempreg,$tempreg,<constant>
3943 For a local symbol, we want the same instruction
3944 sequence, but we output a BFD_RELOC_LO16 reloc on the
3947 If we have a large constant, and this is a reference to
3948 an external symbol, we want
3949 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3950 lui $at,<hiconstant>
3951 addiu $at,$at,<loconstant>
3952 addu $tempreg,$tempreg,$at
3953 For a local symbol, we want the same instruction
3954 sequence, but we output a BFD_RELOC_LO16 reloc on the
3955 addiu instruction. */
3956 expr1
.X_add_number
= offset_expr
.X_add_number
;
3957 offset_expr
.X_add_number
= 0;
3959 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3961 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3962 if (expr1
.X_add_number
== 0)
3970 /* We're going to put in an addu instruction using
3971 tempreg, so we may as well insert the nop right
3973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3977 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3978 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3980 ? mips_warn_about_macros
3982 offset_expr
.X_add_symbol
, (long) 0,
3986 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3989 macro_build (p
, &icnt
, &expr1
,
3990 mips_isa
< 3 ? "addiu" : "daddiu",
3991 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3992 /* FIXME: If breg == 0, and the next instruction uses
3993 $tempreg, then if this variant case is used an extra
3994 nop will be generated. */
3996 else if (expr1
.X_add_number
>= -0x8000
3997 && expr1
.X_add_number
< 0x8000)
3999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4001 macro_build ((char *) NULL
, &icnt
, &expr1
,
4002 mips_isa
< 3 ? "addiu" : "daddiu",
4003 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4004 (void) frag_var (rs_machine_dependent
, 0, 0,
4005 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4006 offset_expr
.X_add_symbol
, (long) 0,
4013 /* If we are going to add in a base register, and the
4014 target register and the base register are the same,
4015 then we are using AT as a temporary register. Since
4016 we want to load the constant into AT, we add our
4017 current AT (from the global offset table) and the
4018 register into the register now, and pretend we were
4019 not using a base register. */
4024 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4027 mips_isa
< 3 ? "addu" : "daddu",
4028 "d,v,t", treg
, AT
, breg
);
4034 /* Set mips_optimize around the lui instruction to avoid
4035 inserting an unnecessary nop after the lw. */
4036 hold_mips_optimize
= mips_optimize
;
4038 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4039 mips_optimize
= hold_mips_optimize
;
4041 macro_build ((char *) NULL
, &icnt
, &expr1
,
4042 mips_isa
< 3 ? "addiu" : "daddiu",
4043 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4044 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4045 mips_isa
< 3 ? "addu" : "daddu",
4046 "d,v,t", tempreg
, tempreg
, AT
);
4047 (void) frag_var (rs_machine_dependent
, 0, 0,
4048 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4049 offset_expr
.X_add_symbol
, (long) 0,
4054 else if (mips_pic
== SVR4_PIC
)
4058 /* This is the large GOT case. If this is a reference to an
4059 external symbol, and there is no constant, we want
4060 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4061 addu $tempreg,$tempreg,$gp
4062 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4063 For a local symbol, we want
4064 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4066 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4068 If we have a small constant, and this is a reference to
4069 an external symbol, we want
4070 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4071 addu $tempreg,$tempreg,$gp
4072 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4074 addiu $tempreg,$tempreg,<constant>
4075 For a local symbol, we want
4076 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4078 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4080 If we have a large constant, and this is a reference to
4081 an external symbol, we want
4082 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4083 addu $tempreg,$tempreg,$gp
4084 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4085 lui $at,<hiconstant>
4086 addiu $at,$at,<loconstant>
4087 addu $tempreg,$tempreg,$at
4088 For a local symbol, we want
4089 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4090 lui $at,<hiconstant>
4091 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4092 addu $tempreg,$tempreg,$at
4094 expr1
.X_add_number
= offset_expr
.X_add_number
;
4095 offset_expr
.X_add_number
= 0;
4097 if (reg_needs_delay (GP
))
4101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4102 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4103 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4104 mips_isa
< 3 ? "addu" : "daddu",
4105 "d,v,t", tempreg
, tempreg
, GP
);
4106 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4108 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4110 if (expr1
.X_add_number
== 0)
4118 /* We're going to put in an addu instruction using
4119 tempreg, so we may as well insert the nop right
4121 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4126 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4127 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4130 ? mips_warn_about_macros
4132 offset_expr
.X_add_symbol
, (long) 0,
4135 else if (expr1
.X_add_number
>= -0x8000
4136 && expr1
.X_add_number
< 0x8000)
4138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4140 macro_build ((char *) NULL
, &icnt
, &expr1
,
4141 mips_isa
< 3 ? "addiu" : "daddiu",
4142 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4144 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4145 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4147 ? mips_warn_about_macros
4149 offset_expr
.X_add_symbol
, (long) 0,
4156 /* If we are going to add in a base register, and the
4157 target register and the base register are the same,
4158 then we are using AT as a temporary register. Since
4159 we want to load the constant into AT, we add our
4160 current AT (from the global offset table) and the
4161 register into the register now, and pretend we were
4162 not using a base register. */
4170 assert (tempreg
== AT
);
4171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4173 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4174 mips_isa
< 3 ? "addu" : "daddu",
4175 "d,v,t", treg
, AT
, breg
);
4180 /* Set mips_optimize around the lui instruction to avoid
4181 inserting an unnecessary nop after the lw. */
4182 hold_mips_optimize
= mips_optimize
;
4184 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4185 mips_optimize
= hold_mips_optimize
;
4187 macro_build ((char *) NULL
, &icnt
, &expr1
,
4188 mips_isa
< 3 ? "addiu" : "daddiu",
4189 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4191 mips_isa
< 3 ? "addu" : "daddu",
4192 "d,v,t", dreg
, dreg
, AT
);
4194 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4195 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4198 ? mips_warn_about_macros
4200 offset_expr
.X_add_symbol
, (long) 0,
4208 /* This is needed because this instruction uses $gp, but
4209 the first instruction on the main stream does not. */
4210 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4213 macro_build (p
, &icnt
, &offset_expr
,
4215 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4217 if (expr1
.X_add_number
>= -0x8000
4218 && expr1
.X_add_number
< 0x8000)
4220 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4222 macro_build (p
, &icnt
, &expr1
,
4223 mips_isa
< 3 ? "addiu" : "daddiu",
4224 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4225 /* FIXME: If add_number is 0, and there was no base
4226 register, the external symbol case ended with a load,
4227 so if the symbol turns out to not be external, and
4228 the next instruction uses tempreg, an unnecessary nop
4229 will be inserted. */
4235 /* We must add in the base register now, as in the
4236 external symbol case. */
4237 assert (tempreg
== AT
);
4238 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4240 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4241 mips_isa
< 3 ? "addu" : "daddu",
4242 "d,v,t", treg
, AT
, breg
);
4245 /* We set breg to 0 because we have arranged to add
4246 it in in both cases. */
4250 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4252 macro_build (p
, &icnt
, &expr1
,
4253 mips_isa
< 3 ? "addiu" : "daddiu",
4254 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4256 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4257 mips_isa
< 3 ? "addu" : "daddu",
4258 "d,v,t", tempreg
, tempreg
, AT
);
4262 else if (mips_pic
== EMBEDDED_PIC
)
4265 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4267 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4268 mips_isa
< 3 ? "addiu" : "daddiu",
4269 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4275 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4276 mips_isa
< 3 ? "addu" : "daddu",
4277 "d,v,t", treg
, tempreg
, breg
);
4285 /* The j instruction may not be used in PIC code, since it
4286 requires an absolute address. We convert it to a b
4288 if (mips_pic
== NO_PIC
)
4289 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4291 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4294 /* The jal instructions must be handled as macros because when
4295 generating PIC code they expand to multi-instruction
4296 sequences. Normally they are simple instructions. */
4301 if (mips_pic
== NO_PIC
4302 || mips_pic
== EMBEDDED_PIC
)
4303 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4305 else if (mips_pic
== SVR4_PIC
)
4307 if (sreg
!= PIC_CALL_REG
)
4308 as_warn ("MIPS PIC call to register other than $25");
4310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4312 if (mips_cprestore_offset
< 0)
4313 as_warn ("No .cprestore pseudo-op used in PIC code");
4316 expr1
.X_add_number
= mips_cprestore_offset
;
4317 macro_build ((char *) NULL
, &icnt
, &expr1
,
4318 mips_isa
< 3 ? "lw" : "ld",
4319 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4328 if (mips_pic
== NO_PIC
)
4329 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4330 else if (mips_pic
== SVR4_PIC
)
4332 /* If this is a reference to an external symbol, and we are
4333 using a small GOT, we want
4334 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4338 lw $gp,cprestore($sp)
4339 The cprestore value is set using the .cprestore
4340 pseudo-op. If we are using a big GOT, we want
4341 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4343 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4347 lw $gp,cprestore($sp)
4348 If the symbol is not external, we want
4349 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4351 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4354 lw $gp,cprestore($sp) */
4358 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4359 mips_isa
< 3 ? "lw" : "ld",
4360 "t,o(b)", PIC_CALL_REG
,
4361 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4362 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4364 p
= frag_var (rs_machine_dependent
, 4, 0,
4365 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4366 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4372 if (reg_needs_delay (GP
))
4376 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4377 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4379 mips_isa
< 3 ? "addu" : "daddu",
4380 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4382 mips_isa
< 3 ? "lw" : "ld",
4383 "t,o(b)", PIC_CALL_REG
,
4384 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4387 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4388 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4390 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4393 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4396 macro_build (p
, &icnt
, &offset_expr
,
4397 mips_isa
< 3 ? "lw" : "ld",
4398 "t,o(b)", PIC_CALL_REG
,
4399 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4401 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4404 macro_build (p
, &icnt
, &offset_expr
,
4405 mips_isa
< 3 ? "addiu" : "daddiu",
4406 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4407 (int) BFD_RELOC_LO16
);
4408 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4409 "jalr", "s", PIC_CALL_REG
);
4410 if (mips_cprestore_offset
< 0)
4411 as_warn ("No .cprestore pseudo-op used in PIC code");
4415 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4417 expr1
.X_add_number
= mips_cprestore_offset
;
4418 macro_build ((char *) NULL
, &icnt
, &expr1
,
4419 mips_isa
< 3 ? "lw" : "ld",
4420 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4424 else if (mips_pic
== EMBEDDED_PIC
)
4426 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4427 /* The linker may expand the call to a longer sequence which
4428 uses $at, so we must break rather than return. */
4453 /* Itbl support may require additional care here. */
4458 /* Itbl support may require additional care here. */
4463 /* Itbl support may require additional care here. */
4468 /* Itbl support may require additional care here. */
4481 /* Itbl support may require additional care here. */
4486 /* Itbl support may require additional care here. */
4491 /* Itbl support may require additional care here. */
4511 if (breg
== treg
|| coproc
|| lr
)
4533 /* Itbl support may require additional care here. */
4538 /* Itbl support may require additional care here. */
4543 /* Itbl support may require additional care here. */
4548 /* Itbl support may require additional care here. */
4566 /* Itbl support may require additional care here. */
4570 /* Itbl support may require additional care here. */
4575 /* Itbl support may require additional care here. */
4587 /* Itbl support may require additional care here. */
4588 if (mask
== M_LWC1_AB
4589 || mask
== M_SWC1_AB
4590 || mask
== M_LDC1_AB
4591 || mask
== M_SDC1_AB
4600 if (offset_expr
.X_op
!= O_constant
4601 && offset_expr
.X_op
!= O_symbol
)
4603 as_bad ("expression too complex");
4604 offset_expr
.X_op
= O_constant
;
4607 /* A constant expression in PIC code can be handled just as it
4608 is in non PIC code. */
4609 if (mips_pic
== NO_PIC
4610 || offset_expr
.X_op
== O_constant
)
4612 /* If this is a reference to a GP relative symbol, and there
4613 is no base register, we want
4614 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4615 Otherwise, if there is no base register, we want
4616 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4617 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4618 If we have a constant, we need two instructions anyhow,
4619 so we always use the latter form.
4621 If we have a base register, and this is a reference to a
4622 GP relative symbol, we want
4623 addu $tempreg,$breg,$gp
4624 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4626 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4627 addu $tempreg,$tempreg,$breg
4628 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4629 With a constant we always use the latter case. */
4632 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4633 || nopic_need_relax (offset_expr
.X_add_symbol
))
4638 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4639 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4640 p
= frag_var (rs_machine_dependent
, 8, 0,
4641 RELAX_ENCODE (4, 8, 0, 4, 0,
4642 (mips_warn_about_macros
4643 || (used_at
&& mips_noat
))),
4644 offset_expr
.X_add_symbol
, (long) 0,
4648 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4651 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4652 (int) BFD_RELOC_LO16
, tempreg
);
4656 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4657 || nopic_need_relax (offset_expr
.X_add_symbol
))
4662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4663 mips_isa
< 3 ? "addu" : "daddu",
4664 "d,v,t", tempreg
, breg
, GP
);
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4666 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4667 p
= frag_var (rs_machine_dependent
, 12, 0,
4668 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4669 offset_expr
.X_add_symbol
, (long) 0,
4672 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4675 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4676 mips_isa
< 3 ? "addu" : "daddu",
4677 "d,v,t", tempreg
, tempreg
, breg
);
4680 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4681 (int) BFD_RELOC_LO16
, tempreg
);
4684 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4686 /* If this is a reference to an external symbol, we want
4687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4689 <op> $treg,0($tempreg)
4691 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4693 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4694 <op> $treg,0($tempreg)
4695 If there is a base register, we add it to $tempreg before
4696 the <op>. If there is a constant, we stick it in the
4697 <op> instruction. We don't handle constants larger than
4698 16 bits, because we have no way to load the upper 16 bits
4699 (actually, we could handle them for the subset of cases
4700 in which we are not using $at). */
4701 assert (offset_expr
.X_op
== O_symbol
);
4702 expr1
.X_add_number
= offset_expr
.X_add_number
;
4703 offset_expr
.X_add_number
= 0;
4704 if (expr1
.X_add_number
< -0x8000
4705 || expr1
.X_add_number
>= 0x8000)
4706 as_bad ("PIC code offset overflow (max 16 signed bits)");
4708 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4709 mips_isa
< 3 ? "lw" : "ld",
4710 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4711 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4712 p
= frag_var (rs_machine_dependent
, 4, 0,
4713 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4714 offset_expr
.X_add_symbol
, (long) 0,
4716 macro_build (p
, &icnt
, &offset_expr
,
4717 mips_isa
< 3 ? "addiu" : "daddiu",
4718 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4721 mips_isa
< 3 ? "addu" : "daddu",
4722 "d,v,t", tempreg
, tempreg
, breg
);
4723 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4724 (int) BFD_RELOC_LO16
, tempreg
);
4726 else if (mips_pic
== SVR4_PIC
)
4730 /* If this is a reference to an external symbol, we want
4731 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4732 addu $tempreg,$tempreg,$gp
4733 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4734 <op> $treg,0($tempreg)
4736 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4738 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4739 <op> $treg,0($tempreg)
4740 If there is a base register, we add it to $tempreg before
4741 the <op>. If there is a constant, we stick it in the
4742 <op> instruction. We don't handle constants larger than
4743 16 bits, because we have no way to load the upper 16 bits
4744 (actually, we could handle them for the subset of cases
4745 in which we are not using $at). */
4746 assert (offset_expr
.X_op
== O_symbol
);
4747 expr1
.X_add_number
= offset_expr
.X_add_number
;
4748 offset_expr
.X_add_number
= 0;
4749 if (expr1
.X_add_number
< -0x8000
4750 || expr1
.X_add_number
>= 0x8000)
4751 as_bad ("PIC code offset overflow (max 16 signed bits)");
4752 if (reg_needs_delay (GP
))
4757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4758 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4760 mips_isa
< 3 ? "addu" : "daddu",
4761 "d,v,t", tempreg
, tempreg
, GP
);
4762 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4763 mips_isa
< 3 ? "lw" : "ld",
4764 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4766 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4767 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4768 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4771 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4774 macro_build (p
, &icnt
, &offset_expr
,
4775 mips_isa
< 3 ? "lw" : "ld",
4776 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4778 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4780 macro_build (p
, &icnt
, &offset_expr
,
4781 mips_isa
< 3 ? "addiu" : "daddiu",
4782 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4784 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4785 mips_isa
< 3 ? "addu" : "daddu",
4786 "d,v,t", tempreg
, tempreg
, breg
);
4787 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4788 (int) BFD_RELOC_LO16
, tempreg
);
4790 else if (mips_pic
== EMBEDDED_PIC
)
4792 /* If there is no base register, we want
4793 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4794 If there is a base register, we want
4795 addu $tempreg,$breg,$gp
4796 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4798 assert (offset_expr
.X_op
== O_symbol
);
4801 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4802 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4807 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4808 mips_isa
< 3 ? "addu" : "daddu",
4809 "d,v,t", tempreg
, breg
, GP
);
4810 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4811 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4824 load_register (&icnt
, treg
, &imm_expr
, 0);
4828 load_register (&icnt
, treg
, &imm_expr
, 1);
4832 if (imm_expr
.X_op
== O_constant
)
4834 load_register (&icnt
, AT
, &imm_expr
, 0);
4835 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4836 "mtc1", "t,G", AT
, treg
);
4841 assert (offset_expr
.X_op
== O_symbol
4842 && strcmp (segment_name (S_GET_SEGMENT
4843 (offset_expr
.X_add_symbol
)),
4845 && offset_expr
.X_add_number
== 0);
4846 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4847 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4852 /* We know that sym is in the .rdata section. First we get the
4853 upper 16 bits of the address. */
4854 if (mips_pic
== NO_PIC
)
4856 /* FIXME: This won't work for a 64 bit address. */
4857 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4859 else if (mips_pic
== SVR4_PIC
)
4861 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4862 mips_isa
< 3 ? "lw" : "ld",
4863 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4865 else if (mips_pic
== EMBEDDED_PIC
)
4867 /* For embedded PIC we pick up the entire address off $gp in
4868 a single instruction. */
4869 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4870 mips_isa
< 3 ? "addiu" : "daddiu",
4871 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4872 offset_expr
.X_op
= O_constant
;
4873 offset_expr
.X_add_number
= 0;
4878 /* Now we load the register(s). */
4880 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4881 treg
, (int) BFD_RELOC_LO16
, AT
);
4884 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4885 treg
, (int) BFD_RELOC_LO16
, AT
);
4888 /* FIXME: How in the world do we deal with the possible
4890 offset_expr
.X_add_number
+= 4;
4891 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4892 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4896 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4897 does not become a variant frag. */
4898 frag_wane (frag_now
);
4904 assert (offset_expr
.X_op
== O_symbol
4905 && offset_expr
.X_add_number
== 0);
4906 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4907 if (strcmp (s
, ".lit8") == 0)
4911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4912 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4916 r
= BFD_RELOC_MIPS_LITERAL
;
4921 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4922 if (mips_pic
== SVR4_PIC
)
4923 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4924 mips_isa
< 3 ? "lw" : "ld",
4925 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4928 /* FIXME: This won't work for a 64 bit address. */
4929 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4934 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4935 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4937 /* To avoid confusion in tc_gen_reloc, we must ensure
4938 that this does not become a variant frag. */
4939 frag_wane (frag_now
);
4950 /* Even on a big endian machine $fn comes before $fn+1. We have
4951 to adjust when loading from memory. */
4954 assert (mips_isa
< 2);
4955 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4956 target_big_endian
? treg
+ 1 : treg
,
4958 /* FIXME: A possible overflow which I don't know how to deal
4960 offset_expr
.X_add_number
+= 4;
4961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4962 target_big_endian
? treg
: treg
+ 1,
4965 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4966 does not become a variant frag. */
4967 frag_wane (frag_now
);
4976 * The MIPS assembler seems to check for X_add_number not
4977 * being double aligned and generating:
4980 * addiu at,at,%lo(foo+1)
4983 * But, the resulting address is the same after relocation so why
4984 * generate the extra instruction?
4986 /* Itbl support may require additional care here. */
5007 /* Itbl support may require additional care here. */
5033 if (offset_expr
.X_op
!= O_symbol
5034 && offset_expr
.X_op
!= O_constant
)
5036 as_bad ("expression too complex");
5037 offset_expr
.X_op
= O_constant
;
5040 /* Even on a big endian machine $fn comes before $fn+1. We have
5041 to adjust when loading from memory. We set coproc if we must
5042 load $fn+1 first. */
5043 /* Itbl support may require additional care here. */
5044 if (! target_big_endian
)
5047 if (mips_pic
== NO_PIC
5048 || offset_expr
.X_op
== O_constant
)
5050 /* If this is a reference to a GP relative symbol, we want
5051 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5052 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5053 If we have a base register, we use this
5055 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5056 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5057 If this is not a GP relative symbol, we want
5058 lui $at,<sym> (BFD_RELOC_HI16_S)
5059 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5060 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5061 If there is a base register, we add it to $at after the
5062 lui instruction. If there is a constant, we always use
5064 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5065 || nopic_need_relax (offset_expr
.X_add_symbol
))
5084 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5085 mips_isa
< 3 ? "addu" : "daddu",
5086 "d,v,t", AT
, breg
, GP
);
5092 /* Itbl support may require additional care here. */
5093 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5094 coproc
? treg
+ 1 : treg
,
5095 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5096 offset_expr
.X_add_number
+= 4;
5098 /* Set mips_optimize to 2 to avoid inserting an
5100 hold_mips_optimize
= mips_optimize
;
5102 /* Itbl support may require additional care here. */
5103 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5104 coproc
? treg
: treg
+ 1,
5105 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5106 mips_optimize
= hold_mips_optimize
;
5108 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5109 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5110 used_at
&& mips_noat
),
5111 offset_expr
.X_add_symbol
, (long) 0,
5114 /* We just generated two relocs. When tc_gen_reloc
5115 handles this case, it will skip the first reloc and
5116 handle the second. The second reloc already has an
5117 extra addend of 4, which we added above. We must
5118 subtract it out, and then subtract another 4 to make
5119 the first reloc come out right. The second reloc
5120 will come out right because we are going to add 4 to
5121 offset_expr when we build its instruction below. */
5122 offset_expr
.X_add_number
-= 8;
5123 offset_expr
.X_op
= O_constant
;
5125 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5130 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5131 mips_isa
< 3 ? "addu" : "daddu",
5132 "d,v,t", AT
, breg
, AT
);
5136 /* Itbl support may require additional care here. */
5137 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5138 coproc
? treg
+ 1 : treg
,
5139 (int) BFD_RELOC_LO16
, AT
);
5142 /* FIXME: How do we handle overflow here? */
5143 offset_expr
.X_add_number
+= 4;
5144 /* Itbl support may require additional care here. */
5145 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5146 coproc
? treg
: treg
+ 1,
5147 (int) BFD_RELOC_LO16
, AT
);
5149 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5153 /* If this is a reference to an external symbol, we want
5154 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5159 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5161 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5162 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5163 If there is a base register we add it to $at before the
5164 lwc1 instructions. If there is a constant we include it
5165 in the lwc1 instructions. */
5167 expr1
.X_add_number
= offset_expr
.X_add_number
;
5168 offset_expr
.X_add_number
= 0;
5169 if (expr1
.X_add_number
< -0x8000
5170 || expr1
.X_add_number
>= 0x8000 - 4)
5171 as_bad ("PIC code offset overflow (max 16 signed bits)");
5176 frag_grow (24 + off
);
5177 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5178 mips_isa
< 3 ? "lw" : "ld",
5179 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5183 mips_isa
< 3 ? "addu" : "daddu",
5184 "d,v,t", AT
, breg
, AT
);
5185 /* Itbl support may require additional care here. */
5186 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5187 coproc
? treg
+ 1 : treg
,
5188 (int) BFD_RELOC_LO16
, AT
);
5189 expr1
.X_add_number
+= 4;
5191 /* Set mips_optimize to 2 to avoid inserting an undesired
5193 hold_mips_optimize
= mips_optimize
;
5195 /* Itbl support may require additional care here. */
5196 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5197 coproc
? treg
: treg
+ 1,
5198 (int) BFD_RELOC_LO16
, AT
);
5199 mips_optimize
= hold_mips_optimize
;
5201 (void) frag_var (rs_machine_dependent
, 0, 0,
5202 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5203 offset_expr
.X_add_symbol
, (long) 0,
5206 else if (mips_pic
== SVR4_PIC
)
5210 /* If this is a reference to an external symbol, we want
5211 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5213 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5218 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5220 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5221 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5222 If there is a base register we add it to $at before the
5223 lwc1 instructions. If there is a constant we include it
5224 in the lwc1 instructions. */
5226 expr1
.X_add_number
= offset_expr
.X_add_number
;
5227 offset_expr
.X_add_number
= 0;
5228 if (expr1
.X_add_number
< -0x8000
5229 || expr1
.X_add_number
>= 0x8000 - 4)
5230 as_bad ("PIC code offset overflow (max 16 signed bits)");
5231 if (reg_needs_delay (GP
))
5240 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5241 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5243 mips_isa
< 3 ? "addu" : "daddu",
5244 "d,v,t", AT
, AT
, GP
);
5245 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5246 mips_isa
< 3 ? "lw" : "ld",
5247 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5251 mips_isa
< 3 ? "addu" : "daddu",
5252 "d,v,t", AT
, breg
, AT
);
5253 /* Itbl support may require additional care here. */
5254 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5255 coproc
? treg
+ 1 : treg
,
5256 (int) BFD_RELOC_LO16
, AT
);
5257 expr1
.X_add_number
+= 4;
5259 /* Set mips_optimize to 2 to avoid inserting an undesired
5261 hold_mips_optimize
= mips_optimize
;
5263 /* Itbl support may require additional care here. */
5264 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5265 coproc
? treg
: treg
+ 1,
5266 (int) BFD_RELOC_LO16
, AT
);
5267 mips_optimize
= hold_mips_optimize
;
5268 expr1
.X_add_number
-= 4;
5270 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5271 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5272 8 + gpdel
+ off
, 1, 0),
5273 offset_expr
.X_add_symbol
, (long) 0,
5277 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5280 macro_build (p
, &icnt
, &offset_expr
,
5281 mips_isa
< 3 ? "lw" : "ld",
5282 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5284 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5288 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5289 mips_isa
< 3 ? "addu" : "daddu",
5290 "d,v,t", AT
, breg
, AT
);
5293 /* Itbl support may require additional care here. */
5294 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5295 coproc
? treg
+ 1 : treg
,
5296 (int) BFD_RELOC_LO16
, AT
);
5298 expr1
.X_add_number
+= 4;
5300 /* Set mips_optimize to 2 to avoid inserting an undesired
5302 hold_mips_optimize
= mips_optimize
;
5304 /* Itbl support may require additional care here. */
5305 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5306 coproc
? treg
: treg
+ 1,
5307 (int) BFD_RELOC_LO16
, AT
);
5308 mips_optimize
= hold_mips_optimize
;
5310 else if (mips_pic
== EMBEDDED_PIC
)
5312 /* If there is no base register, we use
5313 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5314 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5315 If we have a base register, we use
5317 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5318 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5328 mips_isa
< 3 ? "addu" : "daddu",
5329 "d,v,t", AT
, breg
, GP
);
5334 /* Itbl support may require additional care here. */
5335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5336 coproc
? treg
+ 1 : treg
,
5337 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5338 offset_expr
.X_add_number
+= 4;
5339 /* Itbl support may require additional care here. */
5340 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5341 coproc
? treg
: treg
+ 1,
5342 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5358 assert (mips_isa
< 3);
5359 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5360 (int) BFD_RELOC_LO16
, breg
);
5361 offset_expr
.X_add_number
+= 4;
5362 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5363 (int) BFD_RELOC_LO16
, breg
);
5366 /* New code added to support COPZ instructions.
5367 This code builds table entries out of the macros in mip_opcodes.
5368 R4000 uses interlocks to handle coproc delays.
5369 Other chips (like the R3000) require nops to be inserted for delays.
5371 FIXME: Currently, we require that the user handle delays.
5372 In order to fill delay slots for non-interlocked chips,
5373 we must have a way to specify delays based on the coprocessor.
5374 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5375 What are the side-effects of the cop instruction?
5376 What cache support might we have and what are its effects?
5377 Both coprocessor & memory require delays. how long???
5378 What registers are read/set/modified?
5380 If an itbl is provided to interpret cop instructions,
5381 this knowledge can be encoded in the itbl spec. */
5395 /* For now we just do C (same as Cz). */
5396 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5399 #ifdef LOSING_COMPILER
5401 /* Try and see if this is a new itbl instruction.
5402 This code builds table entries out of the macros in mip_opcodes.
5403 FIXME: For now we just assemble the expression and pass it's
5404 value along as a 32-bit immediate.
5405 We may want to have the assembler assemble this value,
5406 so that we gain the assembler's knowledge of delay slots,
5408 Would it be more efficient to use mask (id) here? */
5409 if (itbl_have_entries
5410 && immed_expr
= itbl_assemble(ip
->insn_mo
->name
, ""), immed_expr
)
5412 s
= ip
->insn_mo
->name
;
5414 coproc
= ITBL_DECODE_PNUM(immed_expr
);;
5415 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5422 as_warn ("Macro used $at after \".set noat\"");
5427 struct mips_cl_insn
*ip
;
5429 register int treg
, sreg
, dreg
, breg
;
5444 bfd_reloc_code_real_type r
;
5447 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5448 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5449 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5450 mask
= ip
->insn_mo
->mask
;
5452 expr1
.X_op
= O_constant
;
5453 expr1
.X_op_symbol
= NULL
;
5454 expr1
.X_add_symbol
= NULL
;
5455 expr1
.X_add_number
= 1;
5459 #endif /* LOSING_COMPILER */
5464 macro_build ((char *) NULL
, &icnt
, NULL
,
5465 dbl
? "dmultu" : "multu",
5467 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5473 /* The MIPS assembler some times generates shifts and adds. I'm
5474 not trying to be that fancy. GCC should do this for us
5476 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5477 macro_build ((char *) NULL
, &icnt
, NULL
,
5478 dbl
? "dmult" : "mult",
5480 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5486 mips_emit_delays (true);
5488 mips_any_noreorder
= 1;
5489 macro_build ((char *) NULL
, &icnt
, NULL
,
5490 dbl
? "dmult" : "mult",
5492 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5493 macro_build ((char *) NULL
, &icnt
, NULL
,
5494 dbl
? "dsra32" : "sra",
5495 "d,w,<", dreg
, dreg
, 31);
5496 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5498 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5501 expr1
.X_add_number
= 8;
5502 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5503 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5504 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5507 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5513 mips_emit_delays (true);
5515 mips_any_noreorder
= 1;
5516 macro_build ((char *) NULL
, &icnt
, NULL
,
5517 dbl
? "dmultu" : "multu",
5519 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5520 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5522 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5525 expr1
.X_add_number
= 8;
5526 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5527 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5528 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5534 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5535 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5536 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5538 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5542 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5543 (int) (imm_expr
.X_add_number
& 0x1f));
5544 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5545 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5546 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5550 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5551 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5552 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5554 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5558 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5559 (int) (imm_expr
.X_add_number
& 0x1f));
5560 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5561 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5562 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5566 assert (mips_isa
< 2);
5567 /* Even on a big endian machine $fn comes before $fn+1. We have
5568 to adjust when storing to memory. */
5569 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5570 target_big_endian
? treg
+ 1 : treg
,
5571 (int) BFD_RELOC_LO16
, breg
);
5572 offset_expr
.X_add_number
+= 4;
5573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5574 target_big_endian
? treg
: treg
+ 1,
5575 (int) BFD_RELOC_LO16
, breg
);
5580 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5581 treg
, (int) BFD_RELOC_LO16
);
5583 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5584 sreg
, (int) BFD_RELOC_LO16
);
5587 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5589 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5590 dreg
, (int) BFD_RELOC_LO16
);
5595 if (imm_expr
.X_add_number
== 0)
5597 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5598 sreg
, (int) BFD_RELOC_LO16
);
5603 as_warn ("Instruction %s: result is always false",
5605 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5608 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5610 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5611 sreg
, (int) BFD_RELOC_LO16
);
5614 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5616 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5617 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5618 mips_isa
< 3 ? "addiu" : "daddiu",
5619 "t,r,j", dreg
, sreg
,
5620 (int) BFD_RELOC_LO16
);
5625 load_register (&icnt
, AT
, &imm_expr
, 0);
5626 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5630 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5631 (int) BFD_RELOC_LO16
);
5636 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5642 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5643 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5644 (int) BFD_RELOC_LO16
);
5647 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5649 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5651 macro_build ((char *) NULL
, &icnt
, &expr1
,
5652 mask
== M_SGE_I
? "slti" : "sltiu",
5653 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5658 load_register (&icnt
, AT
, &imm_expr
, 0);
5659 macro_build ((char *) NULL
, &icnt
, NULL
,
5660 mask
== M_SGE_I
? "slt" : "sltu",
5661 "d,v,t", dreg
, sreg
, AT
);
5664 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5665 (int) BFD_RELOC_LO16
);
5670 case M_SGT
: /* sreg > treg <==> treg < sreg */
5676 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5679 case M_SGT_I
: /* sreg > I <==> I < sreg */
5685 load_register (&icnt
, AT
, &imm_expr
, 0);
5686 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5689 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5695 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5696 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5697 (int) BFD_RELOC_LO16
);
5700 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5706 load_register (&icnt
, AT
, &imm_expr
, 0);
5707 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5708 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5709 (int) BFD_RELOC_LO16
);
5713 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5715 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5716 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5719 load_register (&icnt
, AT
, &imm_expr
, 0);
5720 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5724 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5726 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5727 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5730 load_register (&icnt
, AT
, &imm_expr
, 0);
5731 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5737 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5740 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5744 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5746 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5752 if (imm_expr
.X_add_number
== 0)
5754 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5760 as_warn ("Instruction %s: result is always true",
5762 macro_build ((char *) NULL
, &icnt
, &expr1
,
5763 mips_isa
< 3 ? "addiu" : "daddiu",
5764 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5767 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5769 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5770 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5773 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5775 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5776 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5777 mips_isa
< 3 ? "addiu" : "daddiu",
5778 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5783 load_register (&icnt
, AT
, &imm_expr
, 0);
5784 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5788 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5796 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5798 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5799 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5800 dbl
? "daddi" : "addi",
5801 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5804 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5805 macro_build ((char *) NULL
, &icnt
, NULL
,
5806 dbl
? "dsub" : "sub",
5807 "d,v,t", dreg
, sreg
, AT
);
5813 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5815 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5816 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5817 dbl
? "daddiu" : "addiu",
5818 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5821 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5822 macro_build ((char *) NULL
, &icnt
, NULL
,
5823 dbl
? "dsubu" : "subu",
5824 "d,v,t", dreg
, sreg
, AT
);
5845 load_register (&icnt
, AT
, &imm_expr
, 0);
5846 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5851 assert (mips_isa
< 2);
5852 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5853 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5856 * Is the double cfc1 instruction a bug in the mips assembler;
5857 * or is there a reason for it?
5859 mips_emit_delays (true);
5861 mips_any_noreorder
= 1;
5862 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5863 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5864 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5865 expr1
.X_add_number
= 3;
5866 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5867 (int) BFD_RELOC_LO16
);
5868 expr1
.X_add_number
= 2;
5869 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5870 (int) BFD_RELOC_LO16
);
5871 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5872 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5873 macro_build ((char *) NULL
, &icnt
, NULL
,
5874 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5875 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5876 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5886 if (offset_expr
.X_add_number
>= 0x7fff)
5887 as_bad ("operand overflow");
5888 /* avoid load delay */
5889 if (! target_big_endian
)
5890 offset_expr
.X_add_number
+= 1;
5891 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5892 (int) BFD_RELOC_LO16
, breg
);
5893 if (! target_big_endian
)
5894 offset_expr
.X_add_number
-= 1;
5896 offset_expr
.X_add_number
+= 1;
5897 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5898 (int) BFD_RELOC_LO16
, breg
);
5899 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5900 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5913 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5914 as_bad ("operand overflow");
5915 if (! target_big_endian
)
5916 offset_expr
.X_add_number
+= off
;
5917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5918 (int) BFD_RELOC_LO16
, breg
);
5919 if (! target_big_endian
)
5920 offset_expr
.X_add_number
-= off
;
5922 offset_expr
.X_add_number
+= off
;
5923 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5924 (int) BFD_RELOC_LO16
, breg
);
5937 load_address (&icnt
, AT
, &offset_expr
);
5939 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5940 mips_isa
< 3 ? "addu" : "daddu",
5941 "d,v,t", AT
, AT
, breg
);
5942 if (! target_big_endian
)
5943 expr1
.X_add_number
= off
;
5945 expr1
.X_add_number
= 0;
5946 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5947 (int) BFD_RELOC_LO16
, AT
);
5948 if (! target_big_endian
)
5949 expr1
.X_add_number
= 0;
5951 expr1
.X_add_number
= off
;
5952 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5953 (int) BFD_RELOC_LO16
, AT
);
5958 load_address (&icnt
, AT
, &offset_expr
);
5960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5961 mips_isa
< 3 ? "addu" : "daddu",
5962 "d,v,t", AT
, AT
, breg
);
5963 if (target_big_endian
)
5964 expr1
.X_add_number
= 0;
5965 macro_build ((char *) NULL
, &icnt
, &expr1
,
5966 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5967 (int) BFD_RELOC_LO16
, AT
);
5968 if (target_big_endian
)
5969 expr1
.X_add_number
= 1;
5971 expr1
.X_add_number
= 0;
5972 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5973 (int) BFD_RELOC_LO16
, AT
);
5974 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5976 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5981 if (offset_expr
.X_add_number
>= 0x7fff)
5982 as_bad ("operand overflow");
5983 if (target_big_endian
)
5984 offset_expr
.X_add_number
+= 1;
5985 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5986 (int) BFD_RELOC_LO16
, breg
);
5987 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5988 if (target_big_endian
)
5989 offset_expr
.X_add_number
-= 1;
5991 offset_expr
.X_add_number
+= 1;
5992 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5993 (int) BFD_RELOC_LO16
, breg
);
6006 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6007 as_bad ("operand overflow");
6008 if (! target_big_endian
)
6009 offset_expr
.X_add_number
+= off
;
6010 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6011 (int) BFD_RELOC_LO16
, breg
);
6012 if (! target_big_endian
)
6013 offset_expr
.X_add_number
-= off
;
6015 offset_expr
.X_add_number
+= off
;
6016 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6017 (int) BFD_RELOC_LO16
, breg
);
6030 load_address (&icnt
, AT
, &offset_expr
);
6032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6033 mips_isa
< 3 ? "addu" : "daddu",
6034 "d,v,t", AT
, AT
, breg
);
6035 if (! target_big_endian
)
6036 expr1
.X_add_number
= off
;
6038 expr1
.X_add_number
= 0;
6039 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6040 (int) BFD_RELOC_LO16
, AT
);
6041 if (! target_big_endian
)
6042 expr1
.X_add_number
= 0;
6044 expr1
.X_add_number
= off
;
6045 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6046 (int) BFD_RELOC_LO16
, AT
);
6050 load_address (&icnt
, AT
, &offset_expr
);
6052 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6053 mips_isa
< 3 ? "addu" : "daddu",
6054 "d,v,t", AT
, AT
, breg
);
6055 if (! target_big_endian
)
6056 expr1
.X_add_number
= 0;
6057 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6058 (int) BFD_RELOC_LO16
, AT
);
6059 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6061 if (! target_big_endian
)
6062 expr1
.X_add_number
= 1;
6064 expr1
.X_add_number
= 0;
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6066 (int) BFD_RELOC_LO16
, AT
);
6067 if (! target_big_endian
)
6068 expr1
.X_add_number
= 0;
6070 expr1
.X_add_number
= 1;
6071 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6072 (int) BFD_RELOC_LO16
, AT
);
6073 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6075 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6080 /* FIXME: Check if this is one of the itbl macros, since they are
6081 added dynamically. */
6082 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6086 as_warn ("Macro used $at after \".set noat\"");
6089 /* Implement macros in mips16 mode. */
6093 struct mips_cl_insn
*ip
;
6096 int xreg
, yreg
, zreg
, tmp
;
6100 const char *s
, *s2
, *s3
;
6102 mask
= ip
->insn_mo
->mask
;
6104 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6105 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6106 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6110 expr1
.X_op
= O_constant
;
6111 expr1
.X_op_symbol
= NULL
;
6112 expr1
.X_add_symbol
= NULL
;
6113 expr1
.X_add_number
= 1;
6132 mips_emit_delays (true);
6134 mips_any_noreorder
= 1;
6135 macro_build ((char *) NULL
, &icnt
, NULL
,
6136 dbl
? "ddiv" : "div",
6137 "0,x,y", xreg
, yreg
);
6138 expr1
.X_add_number
= 2;
6139 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6140 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6141 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6142 since that causes an overflow. We should do that as well,
6143 but I don't see how to do the comparisons without a temporary
6146 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6165 mips_emit_delays (true);
6167 mips_any_noreorder
= 1;
6168 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6169 expr1
.X_add_number
= 2;
6170 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6171 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6173 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6181 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6182 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6183 dbl
? "daddiu" : "addiu",
6184 "y,x,4", yreg
, xreg
);
6188 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6189 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6194 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6195 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6218 goto do_reverse_branch
;
6222 goto do_reverse_branch
;
6234 goto do_reverse_branch
;
6245 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6247 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6274 goto do_addone_branch_i
;
6279 goto do_addone_branch_i
;
6294 goto do_addone_branch_i
;
6301 ++imm_expr
.X_add_number
;
6304 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6309 expr1
.X_add_number
= 0;
6310 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6312 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6313 "move", "y,X", xreg
, yreg
);
6314 expr1
.X_add_number
= 2;
6315 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6317 "neg", "x,w", xreg
, xreg
);
6321 /* This routine assembles an instruction into its binary format. As a
6322 side effect, it sets one of the global variables imm_reloc or
6323 offset_reloc to the type of relocation to do if one of the operands
6324 is an address expression. */
6329 struct mips_cl_insn
*ip
;
6334 struct mips_opcode
*insn
;
6337 unsigned int lastregno
= 0;
6342 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6347 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6349 insn_error
= "unrecognized opcode";
6357 assert (strcmp (insn
->name
, str
) == 0);
6359 if (insn
->pinfo
== INSN_MACRO
)
6360 insn_isa
= insn
->match
;
6361 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6363 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6365 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6370 if (insn_isa
> mips_isa
6371 || (insn
->pinfo
!= INSN_MACRO
6372 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6374 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6376 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6378 /* start-sanitize-r5900 */
6379 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6381 /* end-sanitize-r5900 */
6384 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6385 && strcmp (insn
->name
, insn
[1].name
) == 0)
6390 if (insn_isa
<= mips_isa
)
6391 insn_error
= "opcode not supported on this processor";
6394 static char buf
[100];
6396 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6403 ip
->insn_opcode
= insn
->match
;
6404 for (args
= insn
->args
;; ++args
)
6410 case '\0': /* end of args */
6423 ip
->insn_opcode
|= lastregno
<< 21;
6428 ip
->insn_opcode
|= lastregno
<< 16;
6432 ip
->insn_opcode
|= lastregno
<< 11;
6438 /* handle optional base register.
6439 Either the base register is omitted or
6440 we must have a left paren. */
6441 /* this is dependent on the next operand specifier
6442 is a 'b' for base register */
6443 assert (args
[1] == 'b');
6447 case ')': /* these must match exactly */
6452 case '<': /* must be at least one digit */
6454 * According to the manual, if the shift amount is greater
6455 * than 31 or less than 0 the the shift amount should be
6456 * mod 32. In reality the mips assembler issues an error.
6457 * We issue a warning and mask out all but the low 5 bits.
6459 my_getExpression (&imm_expr
, s
);
6460 check_absolute_expr (ip
, &imm_expr
);
6461 if ((unsigned long) imm_expr
.X_add_number
> 31)
6463 as_warn ("Improper shift amount (%ld)",
6464 (long) imm_expr
.X_add_number
);
6465 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6467 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6468 imm_expr
.X_op
= O_absent
;
6472 case '>': /* shift amount minus 32 */
6473 my_getExpression (&imm_expr
, s
);
6474 check_absolute_expr (ip
, &imm_expr
);
6475 if ((unsigned long) imm_expr
.X_add_number
< 32
6476 || (unsigned long) imm_expr
.X_add_number
> 63)
6478 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6479 imm_expr
.X_op
= O_absent
;
6483 case 'k': /* cache code */
6484 case 'h': /* prefx code */
6485 my_getExpression (&imm_expr
, s
);
6486 check_absolute_expr (ip
, &imm_expr
);
6487 if ((unsigned long) imm_expr
.X_add_number
> 31)
6489 as_warn ("Invalid value for `%s' (%lu)",
6491 (unsigned long) imm_expr
.X_add_number
);
6492 imm_expr
.X_add_number
&= 0x1f;
6495 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6497 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6498 imm_expr
.X_op
= O_absent
;
6502 case 'c': /* break code */
6503 my_getExpression (&imm_expr
, s
);
6504 check_absolute_expr (ip
, &imm_expr
);
6505 if ((unsigned) imm_expr
.X_add_number
> 1023)
6506 as_warn ("Illegal break code (%ld)",
6507 (long) imm_expr
.X_add_number
);
6508 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6509 imm_expr
.X_op
= O_absent
;
6513 case 'B': /* syscall code */
6514 my_getExpression (&imm_expr
, s
);
6515 check_absolute_expr (ip
, &imm_expr
);
6516 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6517 as_warn ("Illegal syscall code (%ld)",
6518 (long) imm_expr
.X_add_number
);
6519 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6520 imm_expr
.X_op
= O_absent
;
6524 case 'C': /* Coprocessor code */
6525 my_getExpression (&imm_expr
, s
);
6526 check_absolute_expr (ip
, &imm_expr
);
6527 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6529 as_warn ("Coproccesor code > 25 bits (%ld)",
6530 (long) imm_expr
.X_add_number
);
6531 imm_expr
.X_add_number
&= ((1<<25) - 1);
6533 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6534 imm_expr
.X_op
= O_absent
;
6538 case 'b': /* base register */
6539 case 'd': /* destination register */
6540 case 's': /* source register */
6541 case 't': /* target register */
6542 case 'r': /* both target and source */
6543 case 'v': /* both dest and source */
6544 case 'w': /* both dest and target */
6545 case 'E': /* coprocessor target register */
6546 case 'G': /* coprocessor destination register */
6547 case 'x': /* ignore register name */
6548 case 'z': /* must be zero register */
6562 while (isdigit (*s
));
6564 as_bad ("Invalid register number (%d)", regno
);
6566 else if (*args
== 'E' || *args
== 'G')
6570 if (s
[1] == 'f' && s
[2] == 'p')
6575 else if (s
[1] == 's' && s
[2] == 'p')
6580 else if (s
[1] == 'g' && s
[2] == 'p')
6585 else if (s
[1] == 'a' && s
[2] == 't')
6590 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6595 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6600 else if (itbl_have_entries
)
6605 p
= s
+1; /* advance past '$' */
6606 n
= itbl_get_field(&p
); /* n is name */
6608 /* See if this is a register defined in an
6610 if (r
= itbl_get_reg_val(n
), r
)
6612 /* Get_field advances to the start of the next
6613 field, so we need to back rack to the end of
6631 as_warn ("Used $at without \".set noat\"");
6637 if (c
== 'r' || c
== 'v' || c
== 'w')
6644 /* 'z' only matches $0. */
6645 if (c
== 'z' && regno
!= 0)
6648 /* Now that we have assembled one operand, we use the args string
6649 * to figure out where it goes in the instruction. */
6656 ip
->insn_opcode
|= regno
<< 21;
6660 ip
->insn_opcode
|= regno
<< 11;
6665 ip
->insn_opcode
|= regno
<< 16;
6668 /* This case exists because on the r3000 trunc
6669 expands into a macro which requires a gp
6670 register. On the r6000 or r4000 it is
6671 assembled into a single instruction which
6672 ignores the register. Thus the insn version
6673 is MIPS_ISA2 and uses 'x', and the macro
6674 version is MIPS_ISA1 and uses 't'. */
6677 /* This case is for the div instruction, which
6678 acts differently if the destination argument
6679 is $0. This only matches $0, and is checked
6680 outside the switch. */
6683 /* Itbl operand; not yet implemented. FIXME ?? */
6685 /* What about all other operands like 'i',
6686 which can be specified in the opcode table? */
6696 ip
->insn_opcode
|= lastregno
<< 21;
6699 ip
->insn_opcode
|= lastregno
<< 16;
6704 case 'D': /* floating point destination register */
6705 case 'S': /* floating point source register */
6706 case 'T': /* floating point target register */
6707 case 'R': /* floating point source register */
6711 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6721 while (isdigit (*s
));
6724 as_bad ("Invalid float register number (%d)", regno
);
6726 if ((regno
& 1) != 0
6728 && ! (strcmp (str
, "mtc1") == 0
6729 || strcmp (str
, "mfc1") == 0
6730 || strcmp (str
, "lwc1") == 0
6731 || strcmp (str
, "swc1") == 0
6732 || strcmp (str
, "l.s") == 0
6733 || strcmp (str
, "s.s") == 0))
6734 as_warn ("Float register should be even, was %d",
6742 if (c
== 'V' || c
== 'W')
6752 ip
->insn_opcode
|= regno
<< 6;
6756 ip
->insn_opcode
|= regno
<< 11;
6760 ip
->insn_opcode
|= regno
<< 16;
6763 ip
->insn_opcode
|= regno
<< 21;
6772 ip
->insn_opcode
|= lastregno
<< 11;
6775 ip
->insn_opcode
|= lastregno
<< 16;
6781 my_getExpression (&imm_expr
, s
);
6782 if (imm_expr
.X_op
!= O_big
6783 && imm_expr
.X_op
!= O_constant
)
6784 insn_error
= "absolute expression required";
6789 my_getExpression (&offset_expr
, s
);
6790 imm_reloc
= BFD_RELOC_32
;
6802 unsigned char temp
[8];
6804 unsigned int length
;
6809 /* These only appear as the last operand in an
6810 instruction, and every instruction that accepts
6811 them in any variant accepts them in all variants.
6812 This means we don't have to worry about backing out
6813 any changes if the instruction does not match.
6815 The difference between them is the size of the
6816 floating point constant and where it goes. For 'F'
6817 and 'L' the constant is 64 bits; for 'f' and 'l' it
6818 is 32 bits. Where the constant is placed is based
6819 on how the MIPS assembler does things:
6822 f -- immediate value
6825 The .lit4 and .lit8 sections are only used if
6826 permitted by the -G argument.
6828 When generating embedded PIC code, we use the
6829 .lit8 section but not the .lit4 section (we can do
6830 .lit4 inline easily; we need to put .lit8
6831 somewhere in the data segment, and using .lit8
6832 permits the linker to eventually combine identical
6835 f64
= *args
== 'F' || *args
== 'L';
6837 save_in
= input_line_pointer
;
6838 input_line_pointer
= s
;
6839 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6841 s
= input_line_pointer
;
6842 input_line_pointer
= save_in
;
6843 if (err
!= NULL
&& *err
!= '\0')
6845 as_bad ("Bad floating point constant: %s", err
);
6846 memset (temp
, '\0', sizeof temp
);
6847 length
= f64
? 8 : 4;
6850 assert (length
== (f64
? 8 : 4));
6854 && (! USE_GLOBAL_POINTER_OPT
6855 || mips_pic
== EMBEDDED_PIC
6856 || g_switch_value
< 4)
6859 imm_expr
.X_op
= O_constant
;
6860 if (! target_big_endian
)
6861 imm_expr
.X_add_number
=
6862 (((((((int) temp
[3] << 8)
6867 imm_expr
.X_add_number
=
6868 (((((((int) temp
[0] << 8)
6875 const char *newname
;
6878 /* Switch to the right section. */
6880 subseg
= now_subseg
;
6883 default: /* unused default case avoids warnings. */
6885 newname
= RDATA_SECTION_NAME
;
6886 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6890 newname
= RDATA_SECTION_NAME
;
6893 assert (!USE_GLOBAL_POINTER_OPT
6894 || g_switch_value
>= 4);
6898 new_seg
= subseg_new (newname
, (subsegT
) 0);
6899 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6900 bfd_set_section_flags (stdoutput
, new_seg
,
6905 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
6906 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
6907 && strcmp (TARGET_OS
, "elf") != 0)
6908 record_alignment (new_seg
, 4);
6910 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6912 as_bad ("Can't use floating point insn in this section");
6914 /* Set the argument to the current address in the
6916 offset_expr
.X_op
= O_symbol
;
6917 offset_expr
.X_add_symbol
=
6918 symbol_new ("L0\001", now_seg
,
6919 (valueT
) frag_now_fix (), frag_now
);
6920 offset_expr
.X_add_number
= 0;
6922 /* Put the floating point number into the section. */
6923 p
= frag_more ((int) length
);
6924 memcpy (p
, temp
, length
);
6926 /* Switch back to the original section. */
6927 subseg_set (seg
, subseg
);
6932 case 'i': /* 16 bit unsigned immediate */
6933 case 'j': /* 16 bit signed immediate */
6934 imm_reloc
= BFD_RELOC_LO16
;
6935 c
= my_getSmallExpression (&imm_expr
, s
);
6940 if (imm_expr
.X_op
== O_constant
)
6941 imm_expr
.X_add_number
=
6942 (imm_expr
.X_add_number
>> 16) & 0xffff;
6945 imm_reloc
= BFD_RELOC_HI16_S
;
6946 imm_unmatched_hi
= true;
6949 imm_reloc
= BFD_RELOC_HI16
;
6954 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6955 || ((imm_expr
.X_add_number
< 0
6956 || imm_expr
.X_add_number
>= 0x10000)
6957 && imm_expr
.X_op
== O_constant
))
6959 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6960 !strcmp (insn
->name
, insn
[1].name
))
6962 if (imm_expr
.X_op
!= O_constant
6963 && imm_expr
.X_op
!= O_big
)
6964 insn_error
= "absolute expression required";
6966 as_bad ("16 bit expression not in range 0..65535");
6974 /* The upper bound should be 0x8000, but
6975 unfortunately the MIPS assembler accepts numbers
6976 from 0x8000 to 0xffff and sign extends them, and
6977 we want to be compatible. We only permit this
6978 extended range for an instruction which does not
6979 provide any further alternates, since those
6980 alternates may handle other cases. People should
6981 use the numbers they mean, rather than relying on
6982 a mysterious sign extension. */
6983 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6984 strcmp (insn
->name
, insn
[1].name
) == 0);
6989 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6990 || ((imm_expr
.X_add_number
< -0x8000
6991 || imm_expr
.X_add_number
>= max
)
6992 && imm_expr
.X_op
== O_constant
)
6994 && imm_expr
.X_add_number
< 0
6996 && imm_expr
.X_unsigned
6997 && sizeof (imm_expr
.X_add_number
) <= 4))
7001 if (imm_expr
.X_op
!= O_constant
7002 && imm_expr
.X_op
!= O_big
)
7003 insn_error
= "absolute expression required";
7005 as_bad ("16 bit expression not in range -32768..32767");
7011 case 'o': /* 16 bit offset */
7012 c
= my_getSmallExpression (&offset_expr
, s
);
7014 /* If this value won't fit into a 16 bit offset, then go
7015 find a macro that will generate the 32 bit offset
7016 code pattern. As a special hack, we accept the
7017 difference of two local symbols as a constant. This
7018 is required to suppose embedded PIC switches, which
7019 use an instruction which looks like
7020 lw $4,$L12-$LS12($4)
7021 The problem with handling this in a more general
7022 fashion is that the macro function doesn't expect to
7023 see anything which can be handled in a single
7024 constant instruction. */
7026 && (offset_expr
.X_op
!= O_constant
7027 || offset_expr
.X_add_number
>= 0x8000
7028 || offset_expr
.X_add_number
< -0x8000)
7029 && (mips_pic
!= EMBEDDED_PIC
7030 || offset_expr
.X_op
!= O_subtract
7031 || now_seg
!= text_section
7032 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7036 offset_reloc
= BFD_RELOC_LO16
;
7037 if (c
== 'h' || c
== 'H')
7039 assert (offset_expr
.X_op
== O_constant
);
7040 offset_expr
.X_add_number
=
7041 (offset_expr
.X_add_number
>> 16) & 0xffff;
7046 case 'p': /* pc relative offset */
7047 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7048 my_getExpression (&offset_expr
, s
);
7052 case 'u': /* upper 16 bits */
7053 c
= my_getSmallExpression (&imm_expr
, s
);
7054 if (imm_expr
.X_op
== O_constant
7055 && (imm_expr
.X_add_number
< 0
7056 || imm_expr
.X_add_number
>= 0x10000))
7057 as_bad ("lui expression not in range 0..65535");
7058 imm_reloc
= BFD_RELOC_LO16
;
7063 if (imm_expr
.X_op
== O_constant
)
7064 imm_expr
.X_add_number
=
7065 (imm_expr
.X_add_number
>> 16) & 0xffff;
7068 imm_reloc
= BFD_RELOC_HI16_S
;
7069 imm_unmatched_hi
= true;
7072 imm_reloc
= BFD_RELOC_HI16
;
7078 case 'a': /* 26 bit address */
7079 my_getExpression (&offset_expr
, s
);
7081 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7084 case 'N': /* 3 bit branch condition code */
7085 case 'M': /* 3 bit compare condition code */
7086 if (strncmp (s
, "$fcc", 4) != 0)
7096 while (isdigit (*s
));
7098 as_bad ("invalid condition code register $fcc%d", regno
);
7100 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7102 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7106 fprintf (stderr
, "bad char = '%c'\n", *args
);
7111 /* Args don't match. */
7112 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7113 !strcmp (insn
->name
, insn
[1].name
))
7119 insn_error
= "illegal operands";
7124 /* This routine assembles an instruction into its binary format when
7125 assembling for the mips16. As a side effect, it sets one of the
7126 global variables imm_reloc or offset_reloc to the type of
7127 relocation to do if one of the operands is an address expression.
7128 It also sets mips16_small and mips16_ext if the user explicitly
7129 requested a small or extended instruction. */
7134 struct mips_cl_insn
*ip
;
7138 struct mips_opcode
*insn
;
7141 unsigned int lastregno
= 0;
7146 mips16_small
= false;
7149 for (s
= str
; islower (*s
); ++s
)
7161 if (s
[1] == 't' && s
[2] == ' ')
7164 mips16_small
= true;
7168 else if (s
[1] == 'e' && s
[2] == ' ')
7177 insn_error
= "unknown opcode";
7181 if (! mips16_autoextend
&& ! mips16_ext
)
7182 mips16_small
= true;
7184 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7186 insn_error
= "unrecognized opcode";
7193 assert (strcmp (insn
->name
, str
) == 0);
7196 ip
->insn_opcode
= insn
->match
;
7197 ip
->use_extend
= false;
7198 imm_expr
.X_op
= O_absent
;
7199 imm_reloc
= BFD_RELOC_UNUSED
;
7200 offset_expr
.X_op
= O_absent
;
7201 offset_reloc
= BFD_RELOC_UNUSED
;
7202 for (args
= insn
->args
; 1; ++args
)
7209 /* In this switch statement we call break if we did not find
7210 a match, continue if we did find a match, or return if we
7219 /* Stuff the immediate value in now, if we can. */
7220 if (imm_expr
.X_op
== O_constant
7221 && imm_reloc
> BFD_RELOC_UNUSED
7222 && insn
->pinfo
!= INSN_MACRO
)
7224 mips16_immed ((char *) NULL
, 0,
7225 imm_reloc
- BFD_RELOC_UNUSED
,
7226 imm_expr
.X_add_number
, true, mips16_small
,
7227 mips16_ext
, &ip
->insn_opcode
,
7228 &ip
->use_extend
, &ip
->extend
);
7229 imm_expr
.X_op
= O_absent
;
7230 imm_reloc
= BFD_RELOC_UNUSED
;
7244 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7247 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7263 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7265 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7292 while (isdigit (*s
));
7295 as_bad ("invalid register number (%d)", regno
);
7301 if (s
[1] == 'f' && s
[2] == 'p')
7306 else if (s
[1] == 's' && s
[2] == 'p')
7311 else if (s
[1] == 'g' && s
[2] == 'p')
7316 else if (s
[1] == 'a' && s
[2] == 't')
7321 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7326 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7339 if (c
== 'v' || c
== 'w')
7341 regno
= mips16_to_32_reg_map
[lastregno
];
7355 regno
= mips32_to_16_reg_map
[regno
];
7360 regno
= ILLEGAL_REG
;
7365 regno
= ILLEGAL_REG
;
7370 regno
= ILLEGAL_REG
;
7375 if (regno
== AT
&& ! mips_noat
)
7376 as_warn ("used $at without \".set noat\"");
7383 if (regno
== ILLEGAL_REG
)
7390 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7394 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7397 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7400 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7406 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7409 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7410 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7420 if (strncmp (s
, "$pc", 3) == 0)
7444 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7446 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7447 and generate the appropriate reloc. If the text
7448 inside %gprel is not a symbol name with an
7449 optional offset, then we generate a normal reloc
7450 and will probably fail later. */
7451 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7452 if (imm_expr
.X_op
== O_symbol
)
7455 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7457 ip
->use_extend
= true;
7464 /* Just pick up a normal expression. */
7465 my_getExpression (&imm_expr
, s
);
7468 if (imm_expr
.X_op
== O_register
)
7470 /* What we thought was an expression turned out to
7473 if (s
[0] == '(' && args
[1] == '(')
7475 /* It looks like the expression was omitted
7476 before a register indirection, which means
7477 that the expression is implicitly zero. We
7478 still set up imm_expr, so that we handle
7479 explicit extensions correctly. */
7480 imm_expr
.X_op
= O_constant
;
7481 imm_expr
.X_add_number
= 0;
7482 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7489 /* We need to relax this instruction. */
7490 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7499 /* We use offset_reloc rather than imm_reloc for the PC
7500 relative operands. This lets macros with both
7501 immediate and address operands work correctly. */
7502 my_getExpression (&offset_expr
, s
);
7504 if (offset_expr
.X_op
== O_register
)
7507 /* We need to relax this instruction. */
7508 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7512 case '6': /* break code */
7513 my_getExpression (&imm_expr
, s
);
7514 check_absolute_expr (ip
, &imm_expr
);
7515 if ((unsigned long) imm_expr
.X_add_number
> 63)
7517 as_warn ("Invalid value for `%s' (%lu)",
7519 (unsigned long) imm_expr
.X_add_number
);
7520 imm_expr
.X_add_number
&= 0x3f;
7522 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7523 imm_expr
.X_op
= O_absent
;
7527 case 'a': /* 26 bit address */
7528 my_getExpression (&offset_expr
, s
);
7530 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7531 ip
->insn_opcode
<<= 16;
7534 case 'l': /* register list for entry macro */
7535 case 'L': /* register list for exit macro */
7545 int freg
, reg1
, reg2
;
7547 while (*s
== ' ' || *s
== ',')
7551 as_bad ("can't parse register list");
7563 while (isdigit (*s
))
7585 as_bad ("invalid register list");
7590 while (isdigit (*s
))
7597 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7602 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7607 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7608 mask
|= (reg2
- 3) << 3;
7609 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7610 mask
|= (reg2
- 15) << 1;
7611 else if (reg1
== 31 && reg2
== 31)
7615 as_bad ("invalid register list");
7619 /* The mask is filled in in the opcode table for the
7620 benefit of the disassembler. We remove it before
7621 applying the actual mask. */
7622 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7623 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7627 case 'e': /* extend code */
7628 my_getExpression (&imm_expr
, s
);
7629 check_absolute_expr (ip
, &imm_expr
);
7630 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7632 as_warn ("Invalid value for `%s' (%lu)",
7634 (unsigned long) imm_expr
.X_add_number
);
7635 imm_expr
.X_add_number
&= 0x7ff;
7637 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7638 imm_expr
.X_op
= O_absent
;
7648 /* Args don't match. */
7649 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7650 strcmp (insn
->name
, insn
[1].name
) == 0)
7657 insn_error
= "illegal operands";
7663 /* This structure holds information we know about a mips16 immediate
7666 struct mips16_immed_operand
7668 /* The type code used in the argument string in the opcode table. */
7670 /* The number of bits in the short form of the opcode. */
7672 /* The number of bits in the extended form of the opcode. */
7674 /* The amount by which the short form is shifted when it is used;
7675 for example, the sw instruction has a shift count of 2. */
7677 /* The amount by which the short form is shifted when it is stored
7678 into the instruction code. */
7680 /* Non-zero if the short form is unsigned. */
7682 /* Non-zero if the extended form is unsigned. */
7684 /* Non-zero if the value is PC relative. */
7688 /* The mips16 immediate operand types. */
7690 static const struct mips16_immed_operand mips16_immed_operands
[] =
7692 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7693 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7694 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7695 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7696 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7697 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7698 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7699 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7700 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7701 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7702 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7703 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7704 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7705 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7706 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7707 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7708 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7709 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7710 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7711 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7712 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7715 #define MIPS16_NUM_IMMED \
7716 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7718 /* Handle a mips16 instruction with an immediate value. This or's the
7719 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7720 whether an extended value is needed; if one is needed, it sets
7721 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7722 If SMALL is true, an unextended opcode was explicitly requested.
7723 If EXT is true, an extended opcode was explicitly requested. If
7724 WARN is true, warn if EXT does not match reality. */
7727 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7736 unsigned long *insn
;
7737 boolean
*use_extend
;
7738 unsigned short *extend
;
7740 register const struct mips16_immed_operand
*op
;
7741 int mintiny
, maxtiny
;
7744 op
= mips16_immed_operands
;
7745 while (op
->type
!= type
)
7748 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7753 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7756 maxtiny
= 1 << op
->nbits
;
7761 maxtiny
= (1 << op
->nbits
) - 1;
7766 mintiny
= - (1 << (op
->nbits
- 1));
7767 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7770 /* Branch offsets have an implicit 0 in the lowest bit. */
7771 if (type
== 'p' || type
== 'q')
7774 if ((val
& ((1 << op
->shift
) - 1)) != 0
7775 || val
< (mintiny
<< op
->shift
)
7776 || val
> (maxtiny
<< op
->shift
))
7781 if (warn
&& ext
&& ! needext
)
7782 as_warn_where (file
, line
, "extended operand requested but not required");
7783 if (small
&& needext
)
7784 as_bad_where (file
, line
, "invalid unextended operand value");
7786 if (small
|| (! ext
&& ! needext
))
7790 *use_extend
= false;
7791 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7792 insnval
<<= op
->op_shift
;
7797 long minext
, maxext
;
7803 maxext
= (1 << op
->extbits
) - 1;
7807 minext
= - (1 << (op
->extbits
- 1));
7808 maxext
= (1 << (op
->extbits
- 1)) - 1;
7810 if (val
< minext
|| val
> maxext
)
7811 as_bad_where (file
, line
,
7812 "operand value out of range for instruction");
7815 if (op
->extbits
== 16)
7817 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7820 else if (op
->extbits
== 15)
7822 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7827 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7831 *extend
= (unsigned short) extval
;
7840 my_getSmallExpression (ep
, str
)
7851 ((str
[1] == 'h' && str
[2] == 'i')
7852 || (str
[1] == 'H' && str
[2] == 'I')
7853 || (str
[1] == 'l' && str
[2] == 'o'))
7865 * A small expression may be followed by a base register.
7866 * Scan to the end of this operand, and then back over a possible
7867 * base register. Then scan the small expression up to that
7868 * point. (Based on code in sparc.c...)
7870 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7872 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7874 if (isdigit (sp
[-2]))
7876 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7878 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7884 else if (sp
- 5 >= str
7887 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7888 || (sp
[-3] == 's' && sp
[-2] == 'p')
7889 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7890 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7896 /* no expression means zero offset */
7899 /* %xx(reg) is an error */
7900 ep
->X_op
= O_absent
;
7905 ep
->X_op
= O_constant
;
7908 ep
->X_add_symbol
= NULL
;
7909 ep
->X_op_symbol
= NULL
;
7910 ep
->X_add_number
= 0;
7915 my_getExpression (ep
, str
);
7922 my_getExpression (ep
, str
);
7923 return c
; /* => %hi or %lo encountered */
7927 my_getExpression (ep
, str
)
7933 save_in
= input_line_pointer
;
7934 input_line_pointer
= str
;
7936 expr_end
= input_line_pointer
;
7937 input_line_pointer
= save_in
;
7939 /* If we are in mips16 mode, and this is an expression based on `.',
7940 then we bump the value of the symbol by 1 since that is how other
7941 text symbols are handled. We don't bother to handle complex
7942 expressions, just `.' plus or minus a constant. */
7944 && ep
->X_op
== O_symbol
7945 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
7946 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
7947 && ep
->X_add_symbol
->sy_frag
== frag_now
7948 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
7949 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
7950 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
7953 /* Turn a string in input_line_pointer into a floating point constant
7954 of type type, and store the appropriate bytes in *litP. The number
7955 of LITTLENUMS emitted is stored in *sizeP . An error message is
7956 returned, or NULL on OK. */
7959 md_atof (type
, litP
, sizeP
)
7965 LITTLENUM_TYPE words
[4];
7981 return "bad call to md_atof";
7984 t
= atof_ieee (input_line_pointer
, type
, words
);
7986 input_line_pointer
= t
;
7990 if (! target_big_endian
)
7992 for (i
= prec
- 1; i
>= 0; i
--)
7994 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8000 for (i
= 0; i
< prec
; i
++)
8002 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8011 md_number_to_chars (buf
, val
, n
)
8016 if (target_big_endian
)
8017 number_to_chars_bigendian (buf
, val
, n
);
8019 number_to_chars_littleendian (buf
, val
, n
);
8022 CONST
char *md_shortopts
= "O::g::G:";
8024 struct option md_longopts
[] = {
8025 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8026 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8027 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8028 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8029 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8030 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8031 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8032 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8033 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8034 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8035 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8036 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8037 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8038 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8039 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8040 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8041 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8042 {"break", no_argument
, NULL
, OPTION_BREAK
},
8043 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8044 #define OPTION_EB (OPTION_MD_BASE + 11)
8045 {"EB", no_argument
, NULL
, OPTION_EB
},
8046 #define OPTION_EL (OPTION_MD_BASE + 12)
8047 {"EL", no_argument
, NULL
, OPTION_EL
},
8048 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8049 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8050 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8051 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8052 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8053 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8054 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8055 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8056 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8057 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8058 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8059 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8060 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8061 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8062 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8063 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8064 /* start-sanitize-5900 */
8065 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8066 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8067 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8068 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8069 /* end-sanitize-5900 */
8071 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8072 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8073 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8074 #define OPTION_32 (OPTION_MD_BASE + 20)
8075 #define OPTION_64 (OPTION_MD_BASE + 21)
8077 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8078 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8079 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8080 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8081 {"32", no_argument
, NULL
, OPTION_32
},
8082 {"64", no_argument
, NULL
, OPTION_64
},
8085 {NULL
, no_argument
, NULL
, 0}
8087 size_t md_longopts_size
= sizeof(md_longopts
);
8090 md_parse_option (c
, arg
)
8105 target_big_endian
= 1;
8109 target_big_endian
= 0;
8113 if (arg
&& arg
[1] == '0')
8123 mips_debug
= atoi (arg
);
8124 /* When the MIPS assembler sees -g or -g2, it does not do
8125 optimizations which limit full symbolic debugging. We take
8126 that to be equivalent to -O0. */
8127 if (mips_debug
== 2)
8159 /* Identify the processor type */
8161 if (strcmp (p
, "default") == 0
8162 || strcmp (p
, "DEFAULT") == 0)
8168 /* We need to cope with the various "vr" prefixes for the 4300
8170 if (*p
== 'v' || *p
== 'V')
8176 if (*p
== 'r' || *p
== 'R')
8183 if (strcmp (p
, "10000") == 0
8184 || strcmp (p
, "10k") == 0
8185 || strcmp (p
, "10K") == 0)
8190 if (strcmp (p
, "2000") == 0
8191 || strcmp (p
, "2k") == 0
8192 || strcmp (p
, "2K") == 0)
8197 if (strcmp (p
, "3000") == 0
8198 || strcmp (p
, "3k") == 0
8199 || strcmp (p
, "3K") == 0)
8204 if (strcmp (p
, "4000") == 0
8205 || strcmp (p
, "4k") == 0
8206 || strcmp (p
, "4K") == 0)
8208 else if (strcmp (p
, "4100") == 0)
8214 else if (strcmp (p
, "4300") == 0)
8216 else if (strcmp (p
, "4400") == 0)
8218 else if (strcmp (p
, "4600") == 0)
8220 else if (strcmp (p
, "4650") == 0)
8226 else if (strcmp (p
, "4010") == 0)
8235 if (strcmp (p
, "5000") == 0
8236 || strcmp (p
, "5k") == 0
8237 || strcmp (p
, "5K") == 0)
8239 /* start-sanitize-r5900 */
8240 else if (strcmp (p
, "5900") == 0)
8242 /* end-sanitize-r5900 */
8246 if (strcmp (p
, "6000") == 0
8247 || strcmp (p
, "6k") == 0
8248 || strcmp (p
, "6K") == 0)
8253 if (strcmp (p
, "8000") == 0
8254 || strcmp (p
, "8k") == 0
8255 || strcmp (p
, "8K") == 0)
8260 if (strcmp (p
, "orion") == 0)
8265 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8267 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8273 as_bad ("invalid architecture -mcpu=%s", arg
);
8284 case OPTION_NO_M4650
:
8292 case OPTION_NO_M4010
:
8300 case OPTION_NO_M4100
:
8304 /* start-sanitize-r5900 */
8309 case OPTION_NO_M5900
:
8312 /* end-sanitize-r5900 */
8316 mips_no_prev_insn (false);
8319 case OPTION_NO_MIPS16
:
8321 mips_no_prev_insn (false);
8324 case OPTION_MEMBEDDED_PIC
:
8325 mips_pic
= EMBEDDED_PIC
;
8326 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8328 as_bad ("-G may not be used with embedded PIC code");
8331 g_switch_value
= 0x7fffffff;
8334 /* When generating ELF code, we permit -KPIC and -call_shared to
8335 select SVR4_PIC, and -non_shared to select no PIC. This is
8336 intended to be compatible with Irix 5. */
8337 case OPTION_CALL_SHARED
:
8338 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8340 as_bad ("-call_shared is supported only for ELF format");
8343 mips_pic
= SVR4_PIC
;
8344 if (g_switch_seen
&& g_switch_value
!= 0)
8346 as_bad ("-G may not be used with SVR4 PIC code");
8352 case OPTION_NON_SHARED
:
8353 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8355 as_bad ("-non_shared is supported only for ELF format");
8361 /* The -xgot option tells the assembler to use 32 offsets when
8362 accessing the got in SVR4_PIC mode. It is for Irix
8369 if (! USE_GLOBAL_POINTER_OPT
)
8371 as_bad ("-G is not supported for this configuration");
8374 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8376 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8380 g_switch_value
= atoi (arg
);
8384 /* The -32 and -64 options tell the assembler to output the 32
8385 bit or the 64 bit MIPS ELF format. */
8392 const char **list
, **l
;
8394 list
= bfd_target_list ();
8395 for (l
= list
; *l
!= NULL
; l
++)
8396 if (strcmp (*l
, "elf64-bigmips") == 0
8397 || strcmp (*l
, "elf64-littlemips") == 0)
8400 as_fatal ("No compiled in support for 64 bit object file format");
8414 md_show_usage (stream
)
8419 -membedded-pic generate embedded position independent code\n\
8420 -EB generate big endian output\n\
8421 -EL generate little endian output\n\
8422 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8423 -G NUM allow referencing objects up to NUM bytes\n\
8424 implicitly with the gp register [default 8]\n");
8426 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8427 -mips2, -mcpu=r6000 generate code for r6000\n\
8428 -mips3, -mcpu=r4000 generate code for r4000\n\
8429 -mips4, -mcpu=r8000 generate code for r8000\n\
8430 -mcpu=vr4300 generate code for vr4300\n\
8431 -mcpu=vr4100 generate code for vr4100\n\
8432 -m4650 permit R4650 instructions\n\
8433 -no-m4650 do not permit R4650 instructions\n\
8434 -m4010 permit R4010 instructions\n\
8435 -no-m4010 do not permit R4010 instructions\n\
8436 -m4100 permit VR4100 instructions\n\
8437 -no-m4100 do not permit VR4100 instructions\n");
8439 -mips16 generate mips16 instructions\n\
8440 -no-mips16 do not generate mips16 instructions\n");
8442 -O0 remove unneeded NOPs, do not swap branches\n\
8443 -O remove unneeded NOPs and swap branches\n\
8444 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8445 --break, --no-trap break exception on div by 0 and mult overflow\n");
8448 -KPIC, -call_shared generate SVR4 position independent code\n\
8449 -non_shared do not generate position independent code\n\
8450 -xgot assume a 32 bit GOT\n\
8451 -32 create 32 bit object file (default)\n\
8452 -64 create 64 bit object file\n");
8458 mips_init_after_args ()
8460 if (itbl_have_entries
)
8462 /* initialize opcodes */
8463 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8464 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8470 md_pcrel_from (fixP
)
8473 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8474 && fixP
->fx_addsy
!= (symbolS
*) NULL
8475 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8477 /* This makes a branch to an undefined symbol be a branch to the
8478 current location. */
8482 /* return the address of the delay slot */
8483 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8486 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8487 reloc for a cons. We could use the definition there, except that
8488 we want to handle 64 bit relocs specially. */
8491 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8494 unsigned int nbytes
;
8498 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8500 if (nbytes
== 8 && ! mips_64
)
8502 if (target_big_endian
)
8508 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8509 as_bad ("Unsupported reloc size %d", nbytes
);
8511 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8514 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8517 /* Sort any unmatched HI16_S relocs so that they immediately precede
8518 the corresponding LO reloc. This is called before md_apply_fix and
8519 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8520 explicit use of the %hi modifier. */
8525 struct mips_hi_fixup
*l
;
8527 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8529 segment_info_type
*seginfo
;
8532 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8534 /* Check quickly whether the next fixup happens to be a matching
8536 if (l
->fixp
->fx_next
!= NULL
8537 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8538 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8539 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8542 /* Look through the fixups for this segment for a matching %lo.
8543 When we find one, move the %hi just in front of it. We do
8544 this in two passes. In the first pass, we try to find a
8545 unique %lo. In the second pass, we permit multiple %hi
8546 relocs for a single %lo (this is a GNU extension). */
8547 seginfo
= seg_info (l
->seg
);
8548 for (pass
= 0; pass
< 2; pass
++)
8553 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8555 /* Check whether this is a %lo fixup which matches l->fixp. */
8556 if (f
->fx_r_type
== BFD_RELOC_LO16
8557 && f
->fx_addsy
== l
->fixp
->fx_addsy
8558 && f
->fx_offset
== l
->fixp
->fx_offset
8561 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8562 || prev
->fx_addsy
!= f
->fx_addsy
8563 || prev
->fx_offset
!= f
->fx_offset
))
8567 /* Move l->fixp before f. */
8568 for (pf
= &seginfo
->fix_root
;
8570 pf
= &(*pf
)->fx_next
)
8571 assert (*pf
!= NULL
);
8573 *pf
= l
->fixp
->fx_next
;
8575 l
->fixp
->fx_next
= f
;
8577 seginfo
->fix_root
= l
->fixp
;
8579 prev
->fx_next
= l
->fixp
;
8591 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8592 "Unmatched %%hi reloc");
8597 /* When generating embedded PIC code we need to use a special
8598 relocation to represent the difference of two symbols in the .text
8599 section (switch tables use a difference of this sort). See
8600 include/coff/mips.h for details. This macro checks whether this
8601 fixup requires the special reloc. */
8602 #define SWITCH_TABLE(fixp) \
8603 ((fixp)->fx_r_type == BFD_RELOC_32 \
8604 && (fixp)->fx_addsy != NULL \
8605 && (fixp)->fx_subsy != NULL \
8606 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8607 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8609 /* When generating embedded PIC code we must keep all PC relative
8610 relocations, in case the linker has to relax a call. We also need
8611 to keep relocations for switch table entries. */
8615 mips_force_relocation (fixp
)
8618 return (mips_pic
== EMBEDDED_PIC
8620 || SWITCH_TABLE (fixp
)
8621 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8622 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8625 /* Apply a fixup to the object file. */
8628 md_apply_fix (fixP
, valueP
)
8635 assert (fixP
->fx_size
== 4
8636 || fixP
->fx_r_type
== BFD_RELOC_16
8637 || fixP
->fx_r_type
== BFD_RELOC_64
);
8641 /* If we aren't adjusting this fixup to be against the section
8642 symbol, we need to adjust the value. */
8644 if (fixP
->fx_addsy
!= NULL
8645 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8646 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8648 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8649 if (value
!= 0 && ! fixP
->fx_pcrel
)
8651 /* In this case, the bfd_install_relocation routine will
8652 incorrectly add the symbol value back in. We just want
8653 the addend to appear in the object file. */
8654 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8659 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8661 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8664 switch (fixP
->fx_r_type
)
8666 case BFD_RELOC_MIPS_JMP
:
8667 case BFD_RELOC_HI16
:
8668 case BFD_RELOC_HI16_S
:
8669 case BFD_RELOC_MIPS_GPREL
:
8670 case BFD_RELOC_MIPS_LITERAL
:
8671 case BFD_RELOC_MIPS_CALL16
:
8672 case BFD_RELOC_MIPS_GOT16
:
8673 case BFD_RELOC_MIPS_GPREL32
:
8674 case BFD_RELOC_MIPS_GOT_HI16
:
8675 case BFD_RELOC_MIPS_GOT_LO16
:
8676 case BFD_RELOC_MIPS_CALL_HI16
:
8677 case BFD_RELOC_MIPS_CALL_LO16
:
8678 case BFD_RELOC_MIPS16_GPREL
:
8680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8681 "Invalid PC relative reloc");
8682 /* Nothing needed to do. The value comes from the reloc entry */
8685 case BFD_RELOC_MIPS16_JMP
:
8686 /* We currently always generate a reloc against a symbol, which
8687 means that we don't want an addend even if the symbol is
8689 fixP
->fx_addnumber
= 0;
8692 case BFD_RELOC_PCREL_HI16_S
:
8693 /* The addend for this is tricky if it is internal, so we just
8694 do everything here rather than in bfd_install_relocation. */
8695 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8697 /* For an external symbol adjust by the address to make it
8698 pcrel_offset. We use the address of the RELLO reloc
8699 which follows this one. */
8700 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8701 + fixP
->fx_next
->fx_where
);
8706 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8707 if (target_big_endian
)
8709 md_number_to_chars (buf
, value
, 2);
8712 case BFD_RELOC_PCREL_LO16
:
8713 /* The addend for this is tricky if it is internal, so we just
8714 do everything here rather than in bfd_install_relocation. */
8715 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8716 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8717 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8718 if (target_big_endian
)
8720 md_number_to_chars (buf
, value
, 2);
8724 /* This is handled like BFD_RELOC_32, but we output a sign
8725 extended value if we are only 32 bits. */
8727 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8729 if (8 <= sizeof (valueT
))
8730 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8737 w1
= w2
= fixP
->fx_where
;
8738 if (target_big_endian
)
8742 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8743 if ((value
& 0x80000000) != 0)
8747 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8753 /* If we are deleting this reloc entry, we must fill in the
8754 value now. This can happen if we have a .word which is not
8755 resolved when it appears but is later defined. We also need
8756 to fill in the value if this is an embedded PIC switch table
8759 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8760 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8765 /* If we are deleting this reloc entry, we must fill in the
8767 assert (fixP
->fx_size
== 2);
8769 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8773 case BFD_RELOC_LO16
:
8774 /* When handling an embedded PIC switch statement, we can wind
8775 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8778 if (value
< -0x8000 || value
> 0x7fff)
8779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8780 "relocation overflow");
8781 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8782 if (target_big_endian
)
8784 md_number_to_chars (buf
, value
, 2);
8788 case BFD_RELOC_16_PCREL_S2
:
8790 * We need to save the bits in the instruction since fixup_segment()
8791 * might be deleting the relocation entry (i.e., a branch within
8792 * the current segment).
8794 if ((value
& 0x3) != 0)
8795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8796 "Branch to odd address (%lx)", value
);
8799 /* update old instruction data */
8800 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8801 if (target_big_endian
)
8802 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8804 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8806 if (value
>= -0x8000 && value
< 0x8000)
8807 insn
|= value
& 0xffff;
8810 /* The branch offset is too large. If this is an
8811 unconditional branch, and we are not generating PIC code,
8812 we can convert it to an absolute jump instruction. */
8813 if (mips_pic
== NO_PIC
8815 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8816 && (fixP
->fx_frag
->fr_address
8817 < text_section
->vma
+ text_section
->_raw_size
)
8818 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8819 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8820 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8822 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8823 insn
= 0x0c000000; /* jal */
8825 insn
= 0x08000000; /* j */
8826 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8828 fixP
->fx_addsy
= section_symbol (text_section
);
8829 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8833 /* FIXME. It would be possible in principle to handle
8834 conditional branches which overflow. They could be
8835 transformed into a branch around a jump. This would
8836 require setting up variant frags for each different
8837 branch type. The native MIPS assembler attempts to
8838 handle these cases, but it appears to do it
8840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8841 "Relocation overflow");
8845 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8860 const struct mips_opcode
*p
;
8861 int treg
, sreg
, dreg
, shamt
;
8866 for (i
= 0; i
< NUMOPCODES
; ++i
)
8868 p
= &mips_opcodes
[i
];
8869 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8871 printf ("%08lx %s\t", oc
, p
->name
);
8872 treg
= (oc
>> 16) & 0x1f;
8873 sreg
= (oc
>> 21) & 0x1f;
8874 dreg
= (oc
>> 11) & 0x1f;
8875 shamt
= (oc
>> 6) & 0x1f;
8877 for (args
= p
->args
;; ++args
)
8888 printf ("%c", *args
);
8892 assert (treg
== sreg
);
8893 printf ("$%d,$%d", treg
, sreg
);
8898 printf ("$%d", dreg
);
8903 printf ("$%d", treg
);
8907 printf ("0x%x", treg
);
8912 printf ("$%d", sreg
);
8916 printf ("0x%08lx", oc
& 0x1ffffff);
8928 printf ("$%d", shamt
);
8939 printf ("%08lx UNDEFINED\n", oc
);
8950 name
= input_line_pointer
;
8951 c
= get_symbol_end ();
8952 p
= (symbolS
*) symbol_find_or_make (name
);
8953 *input_line_pointer
= c
;
8957 /* Align the current frag to a given power of two. The MIPS assembler
8958 also automatically adjusts any preceding label. */
8961 mips_align (to
, fill
, label
)
8966 mips_emit_delays (false);
8967 frag_align (to
, fill
, 0);
8968 record_alignment (now_seg
, to
);
8971 assert (S_GET_SEGMENT (label
) == now_seg
);
8972 label
->sy_frag
= frag_now
;
8973 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8977 /* Align to a given power of two. .align 0 turns off the automatic
8978 alignment used by the data creating pseudo-ops. */
8985 register long temp_fill
;
8986 long max_alignment
= 15;
8990 o Note that the assembler pulls down any immediately preceeding label
8991 to the aligned address.
8992 o It's not documented but auto alignment is reinstated by
8993 a .align pseudo instruction.
8994 o Note also that after auto alignment is turned off the mips assembler
8995 issues an error on attempt to assemble an improperly aligned data item.
9000 temp
= get_absolute_expression ();
9001 if (temp
> max_alignment
)
9002 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9005 as_warn ("Alignment negative: 0 assumed.");
9008 if (*input_line_pointer
== ',')
9010 input_line_pointer
++;
9011 temp_fill
= get_absolute_expression ();
9018 mips_align (temp
, (int) temp_fill
,
9019 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9026 demand_empty_rest_of_line ();
9030 mips_flush_pending_output ()
9032 mips_emit_delays (false);
9033 mips_clear_insn_labels ();
9042 /* When generating embedded PIC code, we only use the .text, .lit8,
9043 .sdata and .sbss sections. We change the .data and .rdata
9044 pseudo-ops to use .sdata. */
9045 if (mips_pic
== EMBEDDED_PIC
9046 && (sec
== 'd' || sec
== 'r'))
9049 mips_emit_delays (false);
9059 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9060 demand_empty_rest_of_line ();
9064 if (USE_GLOBAL_POINTER_OPT
)
9066 seg
= subseg_new (RDATA_SECTION_NAME
,
9067 (subsegT
) get_absolute_expression ());
9068 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9070 bfd_set_section_flags (stdoutput
, seg
,
9076 if (strcmp (TARGET_OS
, "elf") != 0)
9077 bfd_set_section_alignment (stdoutput
, seg
, 4);
9079 demand_empty_rest_of_line ();
9083 as_bad ("No read only data section in this object file format");
9084 demand_empty_rest_of_line ();
9090 if (USE_GLOBAL_POINTER_OPT
)
9092 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9093 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9095 bfd_set_section_flags (stdoutput
, seg
,
9096 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9098 if (strcmp (TARGET_OS
, "elf") != 0)
9099 bfd_set_section_alignment (stdoutput
, seg
, 4);
9101 demand_empty_rest_of_line ();
9106 as_bad ("Global pointers not supported; recompile -G 0");
9107 demand_empty_rest_of_line ();
9116 mips_enable_auto_align ()
9127 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9128 mips_emit_delays (false);
9129 if (log_size
> 0 && auto_align
)
9130 mips_align (log_size
, 0, label
);
9131 mips_clear_insn_labels ();
9132 cons (1 << log_size
);
9141 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9143 mips_emit_delays (false);
9147 mips_align (3, 0, label
);
9149 mips_align (2, 0, label
);
9151 mips_clear_insn_labels ();
9156 /* Handle .globl. We need to override it because on Irix 5 you are
9159 where foo is an undefined symbol, to mean that foo should be
9160 considered to be the address of a function. */
9171 name
= input_line_pointer
;
9172 c
= get_symbol_end ();
9173 symbolP
= symbol_find_or_make (name
);
9174 *input_line_pointer
= c
;
9177 /* On Irix 5, every global symbol that is not explicitly labelled as
9178 being a function is apparently labelled as being an object. */
9181 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9186 secname
= input_line_pointer
;
9187 c
= get_symbol_end ();
9188 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9190 as_bad ("%s: no such section", secname
);
9191 *input_line_pointer
= c
;
9193 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9194 flag
= BSF_FUNCTION
;
9197 symbolP
->bsym
->flags
|= flag
;
9199 S_SET_EXTERNAL (symbolP
);
9200 demand_empty_rest_of_line ();
9210 opt
= input_line_pointer
;
9211 c
= get_symbol_end ();
9215 /* FIXME: What does this mean? */
9217 else if (strncmp (opt
, "pic", 3) == 0)
9225 mips_pic
= SVR4_PIC
;
9227 as_bad (".option pic%d not supported", i
);
9229 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9231 if (g_switch_seen
&& g_switch_value
!= 0)
9232 as_warn ("-G may not be used with SVR4 PIC code");
9234 bfd_set_gp_size (stdoutput
, 0);
9238 as_warn ("Unrecognized option \"%s\"", opt
);
9240 *input_line_pointer
= c
;
9241 demand_empty_rest_of_line ();
9248 char *name
= input_line_pointer
, ch
;
9250 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9251 input_line_pointer
++;
9252 ch
= *input_line_pointer
;
9253 *input_line_pointer
= '\0';
9255 if (strcmp (name
, "reorder") == 0)
9257 if (mips_noreorder
&& prev_nop_frag
!= NULL
)
9259 /* If we still have pending nops, we can discard them. The
9260 usual nop handling will insert any that are still
9262 prev_nop_frag
->fr_fix
-= prev_nop_frag_holds
* (mips16
? 2 : 4);
9263 prev_nop_frag
= NULL
;
9267 else if (strcmp (name
, "noreorder") == 0)
9269 mips_emit_delays (true);
9271 mips_any_noreorder
= 1;
9273 else if (strcmp (name
, "at") == 0)
9277 else if (strcmp (name
, "noat") == 0)
9281 else if (strcmp (name
, "macro") == 0)
9283 mips_warn_about_macros
= 0;
9285 else if (strcmp (name
, "nomacro") == 0)
9287 if (mips_noreorder
== 0)
9288 as_bad ("`noreorder' must be set before `nomacro'");
9289 mips_warn_about_macros
= 1;
9291 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9295 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9299 else if (strcmp (name
, "bopt") == 0)
9303 else if (strcmp (name
, "nobopt") == 0)
9307 else if (strcmp (name
, "mips16") == 0
9308 || strcmp (name
, "MIPS-16") == 0)
9310 else if (strcmp (name
, "nomips16") == 0
9311 || strcmp (name
, "noMIPS-16") == 0)
9313 else if (strncmp (name
, "mips", 4) == 0)
9317 /* Permit the user to change the ISA on the fly. Needless to
9318 say, misuse can cause serious problems. */
9319 isa
= atoi (name
+ 4);
9321 mips_isa
= file_mips_isa
;
9322 else if (isa
< 1 || isa
> 4)
9323 as_bad ("unknown ISA level");
9327 else if (strcmp (name
, "autoextend") == 0)
9328 mips16_autoextend
= 1;
9329 else if (strcmp (name
, "noautoextend") == 0)
9330 mips16_autoextend
= 0;
9333 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9335 *input_line_pointer
= ch
;
9336 demand_empty_rest_of_line ();
9339 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9340 .option pic2. It means to generate SVR4 PIC calls. */
9346 mips_pic
= SVR4_PIC
;
9347 if (USE_GLOBAL_POINTER_OPT
)
9349 if (g_switch_seen
&& g_switch_value
!= 0)
9350 as_warn ("-G may not be used with SVR4 PIC code");
9353 bfd_set_gp_size (stdoutput
, 0);
9354 demand_empty_rest_of_line ();
9357 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9358 PIC code. It sets the $gp register for the function based on the
9359 function address, which is in the register named in the argument.
9360 This uses a relocation against _gp_disp, which is handled specially
9361 by the linker. The result is:
9362 lui $gp,%hi(_gp_disp)
9363 addiu $gp,$gp,%lo(_gp_disp)
9364 addu $gp,$gp,.cpload argument
9365 The .cpload argument is normally $25 == $t9. */
9374 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9375 if (mips_pic
!= SVR4_PIC
)
9381 /* .cpload should be a in .set noreorder section. */
9382 if (mips_noreorder
== 0)
9383 as_warn (".cpload not in noreorder section");
9386 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9387 ex
.X_op_symbol
= NULL
;
9388 ex
.X_add_number
= 0;
9390 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9391 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9393 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9394 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9395 (int) BFD_RELOC_LO16
);
9397 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9398 GP
, GP
, tc_get_register (0));
9400 demand_empty_rest_of_line ();
9403 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9404 offset from $sp. The offset is remembered, and after making a PIC
9405 call $gp is restored from that location. */
9408 s_cprestore (ignore
)
9414 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9415 if (mips_pic
!= SVR4_PIC
)
9421 mips_cprestore_offset
= get_absolute_expression ();
9423 ex
.X_op
= O_constant
;
9424 ex
.X_add_symbol
= NULL
;
9425 ex
.X_op_symbol
= NULL
;
9426 ex
.X_add_number
= mips_cprestore_offset
;
9428 macro_build ((char *) NULL
, &icnt
, &ex
,
9429 mips_isa
< 3 ? "sw" : "sd",
9430 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9432 demand_empty_rest_of_line ();
9435 /* Handle the .gpword pseudo-op. This is used when generating PIC
9436 code. It generates a 32 bit GP relative reloc. */
9446 /* When not generating PIC code, this is treated as .word. */
9447 if (mips_pic
!= SVR4_PIC
)
9453 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9454 mips_emit_delays (true);
9456 mips_align (2, 0, label
);
9457 mips_clear_insn_labels ();
9461 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9463 as_bad ("Unsupported use of .gpword");
9464 ignore_rest_of_line ();
9468 md_number_to_chars (p
, (valueT
) 0, 4);
9469 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9470 BFD_RELOC_MIPS_GPREL32
);
9472 demand_empty_rest_of_line ();
9475 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9476 tables in SVR4 PIC code. */
9485 /* This is ignored when not generating SVR4 PIC code. */
9486 if (mips_pic
!= SVR4_PIC
)
9492 /* Add $gp to the register named as an argument. */
9493 reg
= tc_get_register (0);
9494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9495 mips_isa
< 3 ? "addu" : "daddu",
9496 "d,v,t", reg
, reg
, GP
);
9498 demand_empty_rest_of_line ();
9501 /* Handle the .insn pseudo-op. This marks instruction labels in
9502 mips16 mode. This permits the linker to handle them specially,
9503 such as generating jalx instructions when needed. We also make
9504 them odd for the duration of the assembly, in order to generate the
9505 right sort of code. We will make them even in the adjust_symtab
9506 routine, while leaving them marked. This is convenient for the
9507 debugger and the disassembler. The linker knows to make them odd
9516 struct insn_label_list
*l
;
9518 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
9521 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9522 S_SET_OTHER (l
->label
, STO_MIPS16
);
9524 ++l
->label
->sy_value
.X_add_number
;
9527 mips_clear_insn_labels ();
9530 demand_empty_rest_of_line ();
9533 /* Parse a register string into a number. Called from the ECOFF code
9534 to parse .frame. The argument is non-zero if this is the frame
9535 register, so that we can record it in mips_frame_reg. */
9538 tc_get_register (frame
)
9544 if (*input_line_pointer
++ != '$')
9546 as_warn ("expected `$'");
9549 else if (isdigit ((unsigned char) *input_line_pointer
))
9551 reg
= get_absolute_expression ();
9552 if (reg
< 0 || reg
>= 32)
9554 as_warn ("Bad register number");
9560 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9562 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9564 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9566 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9570 as_warn ("Unrecognized register name");
9573 input_line_pointer
+= 2;
9576 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9581 md_section_align (seg
, addr
)
9585 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9588 /* We don't need to align ELF sections to the full alignment.
9589 However, Irix 5 may prefer that we align them at least to a 16
9590 byte boundary. We don't bother to align the sections if we are
9591 targeted for an embedded system. */
9592 if (strcmp (TARGET_OS
, "elf") == 0)
9598 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9601 /* Utility routine, called from above as well. If called while the
9602 input file is still being read, it's only an approximation. (For
9603 example, a symbol may later become defined which appeared to be
9604 undefined earlier.) */
9607 nopic_need_relax (sym
)
9613 if (USE_GLOBAL_POINTER_OPT
)
9615 const char *symname
;
9618 /* Find out whether this symbol can be referenced off the GP
9619 register. It can be if it is smaller than the -G size or if
9620 it is in the .sdata or .sbss section. Certain symbols can
9621 not be referenced off the GP, although it appears as though
9623 symname
= S_GET_NAME (sym
);
9624 if (symname
!= (const char *) NULL
9625 && (strcmp (symname
, "eprol") == 0
9626 || strcmp (symname
, "etext") == 0
9627 || strcmp (symname
, "_gp") == 0
9628 || strcmp (symname
, "edata") == 0
9629 || strcmp (symname
, "_fbss") == 0
9630 || strcmp (symname
, "_fdata") == 0
9631 || strcmp (symname
, "_ftext") == 0
9632 || strcmp (symname
, "end") == 0
9633 || strcmp (symname
, "_gp_disp") == 0))
9635 else if (! S_IS_DEFINED (sym
)
9637 #ifndef NO_ECOFF_DEBUGGING
9638 || (sym
->ecoff_extern_size
!= 0
9639 && sym
->ecoff_extern_size
<= g_switch_value
)
9641 || (S_GET_VALUE (sym
) != 0
9642 && S_GET_VALUE (sym
) <= g_switch_value
)))
9646 const char *segname
;
9648 segname
= segment_name (S_GET_SEGMENT (sym
));
9649 assert (strcmp (segname
, ".lit8") != 0
9650 && strcmp (segname
, ".lit4") != 0);
9651 change
= (strcmp (segname
, ".sdata") != 0
9652 && strcmp (segname
, ".sbss") != 0);
9657 /* We are not optimizing for the GP register. */
9661 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9662 extended opcode. SEC is the section the frag is in. */
9665 mips16_extended_frag (fragp
, sec
, stretch
)
9671 register const struct mips16_immed_operand
*op
;
9673 int mintiny
, maxtiny
;
9676 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9678 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9681 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9682 op
= mips16_immed_operands
;
9683 while (op
->type
!= type
)
9686 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9691 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9694 maxtiny
= 1 << op
->nbits
;
9699 maxtiny
= (1 << op
->nbits
) - 1;
9704 mintiny
= - (1 << (op
->nbits
- 1));
9705 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9708 /* We can't call S_GET_VALUE here, because we don't want to lock in
9709 a particular frag address. */
9710 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9712 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9713 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9714 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9716 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9717 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9720 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9721 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9722 + fragp
->fr_symbol
->sy_value
.X_add_number
9723 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9724 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9733 /* We won't have the section when we are called from
9734 mips_relax_frag. However, we will always have been called
9735 from md_estimate_size_before_relax first. If this is a
9736 branch to a different section, we mark it as such. If SEC is
9737 NULL, and the frag is not marked, then it must be a branch to
9738 the same section. */
9741 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9749 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9751 /* FIXME: We should support this, and let the linker
9752 catch branches and loads that are out of range. */
9753 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9754 "unsupported PC relative reference to different section");
9760 /* In this case, we know for sure that the symbol fragment is in
9761 the same section. If the fr_address of the symbol fragment
9762 is greater then the address of this fragment we want to add
9763 in STRETCH in order to get a better estimate of the address.
9764 This particularly matters because of the shift bits. */
9766 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9770 /* Adjust stretch for any alignment frag. FIXME: This
9771 doesn't handle the fr_subtype field, which specifies a
9772 maximum number of bytes to skip when doing an alignment. */
9773 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9776 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9779 stretch
= - ((- stretch
)
9780 & ~ ((1 << (int) f
->fr_offset
) - 1));
9782 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9790 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9792 /* The base address rules are complicated. The base address of
9793 a branch is the following instruction. The base address of a
9794 PC relative load or add is the instruction itself, but if it
9795 is in a delay slot (in which case it can not be extended) use
9796 the address of the instruction whose delay slot it is in. */
9797 if (type
== 'p' || type
== 'q')
9801 /* If we are currently assuming that this frag should be
9802 extended, then, the current address is two bytes
9804 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9807 /* Ignore the low bit in the target, since it will be set
9808 for a text label. */
9812 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9814 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9817 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9819 /* Branch offsets have an implicit 0 in the lowest bit. */
9820 if (type
== 'p' || type
== 'q')
9823 /* If any of the shifted bits are set, we must use an extended
9824 opcode. If the address depends on the size of this
9825 instruction, this can lead to a loop, so we arrange to always
9826 use an extended opcode. We only check this when we are in
9827 the main relaxation loop, when SEC is NULL. */
9828 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9831 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9835 /* If we are about to mark a frag as extended because the value
9836 is precisely maxtiny + 1, then there is a chance of an
9837 infinite loop as in the following code:
9842 In this case when the la is extended, foo is 0x3fc bytes
9843 away, so the la can be shrunk, but then foo is 0x400 away, so
9844 the la must be extended. To avoid this loop, we mark the
9845 frag as extended if it was small, and is about to become
9846 extended with a value of maxtiny + 1. */
9847 if (val
== ((maxtiny
+ 1) << op
->shift
)
9848 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9852 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9856 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9857 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9859 if ((val
& ((1 << op
->shift
) - 1)) != 0
9860 || val
< (mintiny
<< op
->shift
)
9861 || val
> (maxtiny
<< op
->shift
))
9867 /* Estimate the size of a frag before relaxing. Unless this is the
9868 mips16, we are not really relaxing here, and the final size is
9869 encoded in the subtype information. For the mips16, we have to
9870 decide whether we are using an extended opcode or not. */
9874 md_estimate_size_before_relax (fragp
, segtype
)
9880 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9882 if (mips16_extended_frag (fragp
, segtype
, 0))
9884 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9889 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9894 if (mips_pic
== NO_PIC
)
9896 change
= nopic_need_relax (fragp
->fr_symbol
);
9898 else if (mips_pic
== SVR4_PIC
)
9900 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9902 /* This must duplicate the test in adjust_reloc_syms. */
9903 change
= (symsec
!= &bfd_und_section
9904 && symsec
!= &bfd_abs_section
9905 && ! bfd_is_com_section (symsec
));
9912 /* Record the offset to the first reloc in the fr_opcode field.
9913 This lets md_convert_frag and tc_gen_reloc know that the code
9914 must be expanded. */
9915 fragp
->fr_opcode
= (fragp
->fr_literal
9917 - RELAX_OLD (fragp
->fr_subtype
)
9918 + RELAX_RELOC1 (fragp
->fr_subtype
));
9919 /* FIXME: This really needs as_warn_where. */
9920 if (RELAX_WARN (fragp
->fr_subtype
))
9921 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9927 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9930 /* This is called to see whether a reloc against a defined symbol
9931 should be converted into a reloc against a section. Don't adjust
9932 MIPS16 jump relocations, so we don't have to worry about the format
9933 of the offset in the .o file. Don't adjust relocations against
9934 mips16 symbols, so that the linker can find them if it needs to set
9938 mips_fix_adjustable (fixp
)
9941 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9943 if (fixp
->fx_addsy
== NULL
)
9946 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9947 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9953 /* Translate internal representation of relocation info to BFD target
9957 tc_gen_reloc (section
, fixp
)
9961 static arelent
*retval
[4];
9963 bfd_reloc_code_real_type code
;
9965 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9968 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9969 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9971 if (mips_pic
== EMBEDDED_PIC
9972 && SWITCH_TABLE (fixp
))
9974 /* For a switch table entry we use a special reloc. The addend
9975 is actually the difference between the reloc address and the
9977 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9978 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9979 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9980 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9982 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9984 /* We use a special addend for an internal RELLO reloc. */
9985 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9986 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9988 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9990 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9992 assert (fixp
->fx_next
!= NULL
9993 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9994 /* We use a special addend for an internal RELHI reloc. The
9995 reloc is relative to the RELLO; adjust the addend
9997 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9998 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9999 + fixp
->fx_next
->fx_where
10000 - S_GET_VALUE (fixp
->fx_subsy
));
10002 reloc
->addend
= (fixp
->fx_addnumber
10003 + fixp
->fx_next
->fx_frag
->fr_address
10004 + fixp
->fx_next
->fx_where
);
10006 else if (fixp
->fx_pcrel
== 0)
10007 reloc
->addend
= fixp
->fx_addnumber
;
10010 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10011 /* A gruesome hack which is a result of the gruesome gas reloc
10013 reloc
->addend
= reloc
->address
;
10015 reloc
->addend
= -reloc
->address
;
10018 /* If this is a variant frag, we may need to adjust the existing
10019 reloc and generate a new one. */
10020 if (fixp
->fx_frag
->fr_opcode
!= NULL
10021 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10022 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10023 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10024 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10025 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10026 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10027 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10031 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10033 /* If this is not the last reloc in this frag, then we have two
10034 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10035 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10036 the second one handle all of them. */
10037 if (fixp
->fx_next
!= NULL
10038 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10040 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10041 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10042 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10043 && (fixp
->fx_next
->fx_r_type
10044 == BFD_RELOC_MIPS_GOT_LO16
))
10045 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10046 && (fixp
->fx_next
->fx_r_type
10047 == BFD_RELOC_MIPS_CALL_LO16
)));
10052 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10053 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10054 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10056 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10057 reloc2
->address
= (reloc
->address
10058 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10059 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10060 reloc2
->addend
= fixp
->fx_addnumber
;
10061 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10062 assert (reloc2
->howto
!= NULL
);
10064 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10068 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10071 reloc3
->address
+= 4;
10074 if (mips_pic
== NO_PIC
)
10076 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10077 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10079 else if (mips_pic
== SVR4_PIC
)
10081 switch (fixp
->fx_r_type
)
10085 case BFD_RELOC_MIPS_GOT16
:
10087 case BFD_RELOC_MIPS_CALL16
:
10088 case BFD_RELOC_MIPS_GOT_LO16
:
10089 case BFD_RELOC_MIPS_CALL_LO16
:
10090 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10098 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10099 fixup_segment converted a non-PC relative reloc into a PC
10100 relative reloc. In such a case, we need to convert the reloc
10102 code
= fixp
->fx_r_type
;
10103 if (fixp
->fx_pcrel
)
10108 code
= BFD_RELOC_8_PCREL
;
10111 code
= BFD_RELOC_16_PCREL
;
10114 code
= BFD_RELOC_32_PCREL
;
10117 code
= BFD_RELOC_64_PCREL
;
10119 case BFD_RELOC_8_PCREL
:
10120 case BFD_RELOC_16_PCREL
:
10121 case BFD_RELOC_32_PCREL
:
10122 case BFD_RELOC_64_PCREL
:
10123 case BFD_RELOC_16_PCREL_S2
:
10124 case BFD_RELOC_PCREL_HI16_S
:
10125 case BFD_RELOC_PCREL_LO16
:
10128 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10129 "Cannot make %s relocation PC relative",
10130 bfd_get_reloc_code_name (code
));
10134 /* To support a PC relative reloc when generating embedded PIC code
10135 for ECOFF, we use a Cygnus extension. We check for that here to
10136 make sure that we don't let such a reloc escape normally. */
10137 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10138 && code
== BFD_RELOC_16_PCREL_S2
10139 && mips_pic
!= EMBEDDED_PIC
)
10140 reloc
->howto
= NULL
;
10142 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10144 if (reloc
->howto
== NULL
)
10146 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10147 "Can not represent %s relocation in this object file format",
10148 bfd_get_reloc_code_name (code
));
10155 /* Relax a machine dependent frag. This returns the amount by which
10156 the current size of the frag should change. */
10159 mips_relax_frag (fragp
, stretch
)
10163 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10166 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10168 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10170 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10175 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10177 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10184 /* Convert a machine dependent frag. */
10187 md_convert_frag (abfd
, asec
, fragp
)
10195 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10198 register const struct mips16_immed_operand
*op
;
10199 boolean small
, ext
;
10202 unsigned long insn
;
10203 boolean use_extend
;
10204 unsigned short extend
;
10206 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10207 op
= mips16_immed_operands
;
10208 while (op
->type
!= type
)
10211 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10222 resolve_symbol_value (fragp
->fr_symbol
);
10223 val
= S_GET_VALUE (fragp
->fr_symbol
);
10228 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10230 /* The rules for the base address of a PC relative reloc are
10231 complicated; see mips16_extended_frag. */
10232 if (type
== 'p' || type
== 'q')
10237 /* Ignore the low bit in the target, since it will be
10238 set for a text label. */
10239 if ((val
& 1) != 0)
10242 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10244 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10247 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10250 /* Make sure the section winds up with the alignment we have
10253 record_alignment (asec
, op
->shift
);
10257 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10258 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10259 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10260 "extended instruction in delay slot");
10262 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10264 if (target_big_endian
)
10265 insn
= bfd_getb16 (buf
);
10267 insn
= bfd_getl16 (buf
);
10269 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10270 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10271 small
, ext
, &insn
, &use_extend
, &extend
);
10275 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10276 fragp
->fr_fix
+= 2;
10280 md_number_to_chars (buf
, insn
, 2);
10281 fragp
->fr_fix
+= 2;
10286 if (fragp
->fr_opcode
== NULL
)
10289 old
= RELAX_OLD (fragp
->fr_subtype
);
10290 new = RELAX_NEW (fragp
->fr_subtype
);
10291 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10294 memcpy (fixptr
- old
, fixptr
, new);
10296 fragp
->fr_fix
+= new - old
;
10302 /* This function is called after the relocs have been generated.
10303 We've been storing mips16 text labels as odd. Here we convert them
10304 back to even for the convenience of the debugger. */
10307 mips_frob_file_after_relocs ()
10310 unsigned int count
, i
;
10312 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10315 syms
= bfd_get_outsymbols (stdoutput
);
10316 count
= bfd_get_symcount (stdoutput
);
10317 for (i
= 0; i
< count
; i
++, syms
++)
10319 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10320 && ((*syms
)->value
& 1) != 0)
10322 (*syms
)->value
&= ~1;
10323 /* If the symbol has an odd size, it was probably computed
10324 incorrectly, so adjust that as well. */
10325 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10326 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10333 /* This function is called whenever a label is defined. It is used
10334 when handling branch delays; if a branch has a label, we assume we
10335 can not move it. */
10338 mips_define_label (sym
)
10341 struct insn_label_list
*l
;
10343 if (free_insn_labels
== NULL
)
10344 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10347 l
= free_insn_labels
;
10348 free_insn_labels
= l
->next
;
10352 l
->next
= insn_labels
;
10356 /* Decide whether a label is local. This is called by LOCAL_LABEL.
10357 In order to work with gcc when using mips-tfile, we must keep all
10358 local labels. However, in other cases, we want to discard them,
10359 since they are useless. */
10362 mips_local_label (name
)
10365 #ifndef NO_ECOFF_DEBUGGING
10366 if (ECOFF_DEBUGGING
10368 && ! ecoff_debugging_seen
)
10370 /* We were called with -g, but we didn't see any debugging
10371 information. That may mean that gcc is smuggling debugging
10372 information through to mips-tfile, in which case we must
10373 generate all local labels. */
10378 /* Here it's OK to discard local labels. */
10380 return name
[0] == '$';
10383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10385 /* Some special processing for a MIPS ELF file. */
10388 mips_elf_final_processing ()
10390 /* Write out the register information. */
10395 s
.ri_gprmask
= mips_gprmask
;
10396 s
.ri_cprmask
[0] = mips_cprmask
[0];
10397 s
.ri_cprmask
[1] = mips_cprmask
[1];
10398 s
.ri_cprmask
[2] = mips_cprmask
[2];
10399 s
.ri_cprmask
[3] = mips_cprmask
[3];
10400 /* The gp_value field is set by the MIPS ELF backend. */
10402 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10403 ((Elf32_External_RegInfo
*)
10404 mips_regmask_frag
));
10408 Elf64_Internal_RegInfo s
;
10410 s
.ri_gprmask
= mips_gprmask
;
10412 s
.ri_cprmask
[0] = mips_cprmask
[0];
10413 s
.ri_cprmask
[1] = mips_cprmask
[1];
10414 s
.ri_cprmask
[2] = mips_cprmask
[2];
10415 s
.ri_cprmask
[3] = mips_cprmask
[3];
10416 /* The gp_value field is set by the MIPS ELF backend. */
10418 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10419 ((Elf64_External_RegInfo
*)
10420 mips_regmask_frag
));
10423 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10424 sort of BFD interface for this. */
10425 if (mips_any_noreorder
)
10426 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10427 if (mips_pic
!= NO_PIC
)
10428 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10431 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10433 /* These functions should really be defined by the object file format,
10434 since they are related to debugging information. However, this
10435 code has to work for the a.out format, which does not define them,
10436 so we provide simple versions here. These don't actually generate
10437 any debugging information, but they do simple checking and someday
10438 somebody may make them useful. */
10442 struct loc
*loc_next
;
10443 unsigned long loc_fileno
;
10444 unsigned long loc_lineno
;
10445 unsigned long loc_offset
;
10446 unsigned short loc_delta
;
10447 unsigned short loc_count
;
10454 typedef struct proc
10456 struct proc
*proc_next
;
10457 struct symbol
*proc_isym
;
10458 struct symbol
*proc_end
;
10459 unsigned long proc_reg_mask
;
10460 unsigned long proc_reg_offset
;
10461 unsigned long proc_fpreg_mask
;
10462 unsigned long proc_fpreg_offset
;
10463 unsigned long proc_frameoffset
;
10464 unsigned long proc_framereg
;
10465 unsigned long proc_pcreg
;
10467 struct file
*proc_file
;
10472 typedef struct file
10474 struct file
*file_next
;
10475 unsigned long file_fileno
;
10476 struct symbol
*file_symbol
;
10477 struct symbol
*file_end
;
10478 struct proc
*file_proc
;
10483 static struct obstack proc_frags
;
10484 static procS
*proc_lastP
;
10485 static procS
*proc_rootP
;
10486 static int numprocs
;
10491 obstack_begin (&proc_frags
, 0x2000);
10497 /* check for premature end, nesting errors, etc */
10498 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10499 as_warn ("missing `.end' at end of assembly");
10508 if (*input_line_pointer
== '-')
10510 ++input_line_pointer
;
10513 if (!isdigit (*input_line_pointer
))
10514 as_bad ("Expected simple number.");
10515 if (input_line_pointer
[0] == '0')
10517 if (input_line_pointer
[1] == 'x')
10519 input_line_pointer
+= 2;
10520 while (isxdigit (*input_line_pointer
))
10523 val
|= hex_value (*input_line_pointer
++);
10525 return negative
? -val
: val
;
10529 ++input_line_pointer
;
10530 while (isdigit (*input_line_pointer
))
10533 val
|= *input_line_pointer
++ - '0';
10535 return negative
? -val
: val
;
10538 if (!isdigit (*input_line_pointer
))
10540 printf (" *input_line_pointer == '%c' 0x%02x\n",
10541 *input_line_pointer
, *input_line_pointer
);
10542 as_warn ("Invalid number");
10545 while (isdigit (*input_line_pointer
))
10548 val
+= *input_line_pointer
++ - '0';
10550 return negative
? -val
: val
;
10553 /* The .file directive; just like the usual .file directive, but there
10554 is an initial number which is the ECOFF file index. */
10562 line
= get_number ();
10567 /* The .end directive. */
10575 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10578 demand_empty_rest_of_line ();
10582 if (now_seg
!= text_section
)
10583 as_warn (".end not in text section");
10586 as_warn (".end and no .ent seen yet.");
10592 assert (S_GET_NAME (p
));
10593 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10594 as_warn (".end symbol does not match .ent symbol.");
10597 proc_lastP
->proc_end
= (symbolS
*) 1;
10600 /* The .aent and .ent directives. */
10610 symbolP
= get_symbol ();
10611 if (*input_line_pointer
== ',')
10612 input_line_pointer
++;
10613 SKIP_WHITESPACE ();
10614 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10615 number
= get_number ();
10616 if (now_seg
!= text_section
)
10617 as_warn (".ent or .aent not in text section.");
10619 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10620 as_warn ("missing `.end'");
10624 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10625 procP
->proc_isym
= symbolP
;
10626 procP
->proc_reg_mask
= 0;
10627 procP
->proc_reg_offset
= 0;
10628 procP
->proc_fpreg_mask
= 0;
10629 procP
->proc_fpreg_offset
= 0;
10630 procP
->proc_frameoffset
= 0;
10631 procP
->proc_framereg
= 0;
10632 procP
->proc_pcreg
= 0;
10633 procP
->proc_end
= NULL
;
10634 procP
->proc_next
= NULL
;
10636 proc_lastP
->proc_next
= procP
;
10638 proc_rootP
= procP
;
10639 proc_lastP
= procP
;
10642 demand_empty_rest_of_line ();
10645 /* The .frame directive. */
10658 frame_reg
= tc_get_register (1);
10659 if (*input_line_pointer
== ',')
10660 input_line_pointer
++;
10661 frame_off
= get_absolute_expression ();
10662 if (*input_line_pointer
== ',')
10663 input_line_pointer
++;
10664 pcreg
= tc_get_register (0);
10666 /* bob third eye */
10667 assert (proc_rootP
);
10668 proc_rootP
->proc_framereg
= frame_reg
;
10669 proc_rootP
->proc_frameoffset
= frame_off
;
10670 proc_rootP
->proc_pcreg
= pcreg
;
10671 /* bob macho .frame */
10673 /* We don't have to write out a frame stab for unoptimized code. */
10674 if (!(frame_reg
== FP
&& frame_off
== 0))
10677 as_warn ("No .ent for .frame to use.");
10678 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10679 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10680 S_SET_TYPE (symP
, N_RMASK
);
10681 S_SET_OTHER (symP
, 0);
10682 S_SET_DESC (symP
, 0);
10683 symP
->sy_forward
= proc_lastP
->proc_isym
;
10684 /* bob perhaps I should have used pseudo set */
10686 demand_empty_rest_of_line ();
10690 /* The .fmask and .mask directives. */
10697 char str
[100], *strP
;
10703 mask
= get_number ();
10704 if (*input_line_pointer
== ',')
10705 input_line_pointer
++;
10706 off
= get_absolute_expression ();
10708 /* bob only for coff */
10709 assert (proc_rootP
);
10710 if (reg_type
== 'F')
10712 proc_rootP
->proc_fpreg_mask
= mask
;
10713 proc_rootP
->proc_fpreg_offset
= off
;
10717 proc_rootP
->proc_reg_mask
= mask
;
10718 proc_rootP
->proc_reg_offset
= off
;
10721 /* bob macho .mask + .fmask */
10723 /* We don't have to write out a mask stab if no saved regs. */
10727 as_warn ("No .ent for .mask to use.");
10729 for (i
= 0; i
< 32; i
++)
10733 sprintf (strP
, "%c%d,", reg_type
, i
);
10734 strP
+= strlen (strP
);
10738 sprintf (strP
, ";%d,", off
);
10739 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10740 S_SET_TYPE (symP
, N_RMASK
);
10741 S_SET_OTHER (symP
, 0);
10742 S_SET_DESC (symP
, 0);
10743 symP
->sy_forward
= proc_lastP
->proc_isym
;
10744 /* bob perhaps I should have used pseudo set */
10749 /* The .loc directive. */
10760 assert (now_seg
== text_section
);
10762 lineno
= get_number ();
10763 addroff
= frag_now_fix ();
10765 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10766 S_SET_TYPE (symbolP
, N_SLINE
);
10767 S_SET_OTHER (symbolP
, 0);
10768 S_SET_DESC (symbolP
, lineno
);
10769 symbolP
->sy_segment
= now_seg
;