1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 static char *insn_error
;
635 static int auto_align
= 1;
637 /* When outputting SVR4 PIC code, the assembler needs to know the
638 offset in the stack frame from which to restore the $gp register.
639 This is set by the .cprestore pseudo-op, and saved in this
641 static offsetT mips_cprestore_offset
= -1;
643 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
644 more optimizations, it can use a register value instead of a memory-saved
645 offset and even an other register than $gp as global pointer. */
646 static offsetT mips_cpreturn_offset
= -1;
647 static int mips_cpreturn_register
= -1;
648 static int mips_gp_register
= GP
;
649 static int mips_gprel_offset
= 0;
651 /* Whether mips_cprestore_offset has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_cprestore_valid
= 0;
655 /* This is the register which holds the stack frame, as set by the
656 .frame pseudo-op. This is needed to implement .cprestore. */
657 static int mips_frame_reg
= SP
;
659 /* Whether mips_frame_reg has been set in the current function
660 (or whether it has already been warned about, if not). */
661 static int mips_frame_reg_valid
= 0;
663 /* To output NOP instructions correctly, we need to keep information
664 about the previous two instructions. */
666 /* Whether we are optimizing. The default value of 2 means to remove
667 unneeded NOPs and swap branch instructions when possible. A value
668 of 1 means to not swap branches. A value of 0 means to always
670 static int mips_optimize
= 2;
672 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
673 equivalent to seeing no -g option at all. */
674 static int mips_debug
= 0;
676 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
677 #define MAX_VR4130_NOPS 4
679 /* The maximum number of NOPs needed to fill delay slots. */
680 #define MAX_DELAY_NOPS 2
682 /* The maximum number of NOPs needed for any purpose. */
685 /* A list of previous instructions, with index 0 being the most recent.
686 We need to look back MAX_NOPS instructions when filling delay slots
687 or working around processor errata. We need to look back one
688 instruction further if we're thinking about using history[0] to
689 fill a branch delay slot. */
690 static struct mips_cl_insn history
[1 + MAX_NOPS
];
692 /* Arrays of operands for each instruction. */
693 #define MAX_OPERANDS 6
694 struct mips_operand_array
{
695 const struct mips_operand
*operand
[MAX_OPERANDS
];
697 static struct mips_operand_array
*mips_operands
;
698 static struct mips_operand_array
*mips16_operands
;
699 static struct mips_operand_array
*micromips_operands
;
701 /* Nop instructions used by emit_nop. */
702 static struct mips_cl_insn nop_insn
;
703 static struct mips_cl_insn mips16_nop_insn
;
704 static struct mips_cl_insn micromips_nop16_insn
;
705 static struct mips_cl_insn micromips_nop32_insn
;
707 /* The appropriate nop for the current mode. */
708 #define NOP_INSN (mips_opts.mips16 \
710 : (mips_opts.micromips \
711 ? (mips_opts.insn32 \
712 ? µmips_nop32_insn \
713 : µmips_nop16_insn) \
716 /* The size of NOP_INSN in bytes. */
717 #define NOP_INSN_SIZE ((mips_opts.mips16 \
718 || (mips_opts.micromips && !mips_opts.insn32)) \
721 /* If this is set, it points to a frag holding nop instructions which
722 were inserted before the start of a noreorder section. If those
723 nops turn out to be unnecessary, the size of the frag can be
725 static fragS
*prev_nop_frag
;
727 /* The number of nop instructions we created in prev_nop_frag. */
728 static int prev_nop_frag_holds
;
730 /* The number of nop instructions that we know we need in
732 static int prev_nop_frag_required
;
734 /* The number of instructions we've seen since prev_nop_frag. */
735 static int prev_nop_frag_since
;
737 /* Relocations against symbols are sometimes done in two parts, with a HI
738 relocation and a LO relocation. Each relocation has only 16 bits of
739 space to store an addend. This means that in order for the linker to
740 handle carries correctly, it must be able to locate both the HI and
741 the LO relocation. This means that the relocations must appear in
742 order in the relocation table.
744 In order to implement this, we keep track of each unmatched HI
745 relocation. We then sort them so that they immediately precede the
746 corresponding LO relocation. */
751 struct mips_hi_fixup
*next
;
754 /* The section this fixup is in. */
758 /* The list of unmatched HI relocs. */
760 static struct mips_hi_fixup
*mips_hi_fixup_list
;
762 /* The frag containing the last explicit relocation operator.
763 Null if explicit relocations have not been used. */
765 static fragS
*prev_reloc_op_frag
;
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map
[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map microMIPS register numbers to normal MIPS register numbers. */
776 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
778 /* The microMIPS registers with type h. */
779 static const unsigned int micromips_to_32_reg_h_map1
[] =
781 5, 5, 6, 4, 4, 4, 4, 4
783 static const unsigned int micromips_to_32_reg_h_map2
[] =
785 6, 7, 7, 21, 22, 5, 6, 7
788 /* The microMIPS registers with type m. */
789 static const unsigned int micromips_to_32_reg_m_map
[] =
791 0, 17, 2, 3, 16, 18, 19, 20
794 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
796 /* Classifies the kind of instructions we're interested in when
797 implementing -mfix-vr4120. */
798 enum fix_vr4120_class
806 NUM_FIX_VR4120_CLASSES
809 /* ...likewise -mfix-loongson2f-jump. */
810 static bfd_boolean mips_fix_loongson2f_jump
;
812 /* ...likewise -mfix-loongson2f-nop. */
813 static bfd_boolean mips_fix_loongson2f_nop
;
815 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
816 static bfd_boolean mips_fix_loongson2f
;
818 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
819 there must be at least one other instruction between an instruction
820 of type X and an instruction of type Y. */
821 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
823 /* True if -mfix-vr4120 is in force. */
824 static int mips_fix_vr4120
;
826 /* ...likewise -mfix-vr4130. */
827 static int mips_fix_vr4130
;
829 /* ...likewise -mfix-24k. */
830 static int mips_fix_24k
;
832 /* ...likewise -mfix-cn63xxp1 */
833 static bfd_boolean mips_fix_cn63xxp1
;
835 /* We don't relax branches by default, since this causes us to expand
836 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
837 fail to compute the offset before expanding the macro to the most
838 efficient expansion. */
840 static int mips_relax_branch
;
842 /* The expansion of many macros depends on the type of symbol that
843 they refer to. For example, when generating position-dependent code,
844 a macro that refers to a symbol may have two different expansions,
845 one which uses GP-relative addresses and one which uses absolute
846 addresses. When generating SVR4-style PIC, a macro may have
847 different expansions for local and global symbols.
849 We handle these situations by generating both sequences and putting
850 them in variant frags. In position-dependent code, the first sequence
851 will be the GP-relative one and the second sequence will be the
852 absolute one. In SVR4 PIC, the first sequence will be for global
853 symbols and the second will be for local symbols.
855 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
856 SECOND are the lengths of the two sequences in bytes. These fields
857 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
858 the subtype has the following flags:
861 Set if it has been decided that we should use the second
862 sequence instead of the first.
865 Set in the first variant frag if the macro's second implementation
866 is longer than its first. This refers to the macro as a whole,
867 not an individual relaxation.
870 Set in the first variant frag if the macro appeared in a .set nomacro
871 block and if one alternative requires a warning but the other does not.
874 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
877 RELAX_DELAY_SLOT_16BIT
878 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
881 RELAX_DELAY_SLOT_SIZE_FIRST
882 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
883 the macro is of the wrong size for the branch delay slot.
885 RELAX_DELAY_SLOT_SIZE_SECOND
886 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
887 the macro is of the wrong size for the branch delay slot.
889 The frag's "opcode" points to the first fixup for relaxable code.
891 Relaxable macros are generated using a sequence such as:
893 relax_start (SYMBOL);
894 ... generate first expansion ...
896 ... generate second expansion ...
899 The code and fixups for the unwanted alternative are discarded
900 by md_convert_frag. */
901 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
903 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
904 #define RELAX_SECOND(X) ((X) & 0xff)
905 #define RELAX_USE_SECOND 0x10000
906 #define RELAX_SECOND_LONGER 0x20000
907 #define RELAX_NOMACRO 0x40000
908 #define RELAX_DELAY_SLOT 0x80000
909 #define RELAX_DELAY_SLOT_16BIT 0x100000
910 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
911 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
913 /* Branch without likely bit. If label is out of range, we turn:
915 beq reg1, reg2, label
925 with the following opcode replacements:
932 bltzal <-> bgezal (with jal label instead of j label)
934 Even though keeping the delay slot instruction in the delay slot of
935 the branch would be more efficient, it would be very tricky to do
936 correctly, because we'd have to introduce a variable frag *after*
937 the delay slot instruction, and expand that instead. Let's do it
938 the easy way for now, even if the branch-not-taken case now costs
939 one additional instruction. Out-of-range branches are not supposed
940 to be common, anyway.
942 Branch likely. If label is out of range, we turn:
944 beql reg1, reg2, label
945 delay slot (annulled if branch not taken)
954 delay slot (executed only if branch taken)
957 It would be possible to generate a shorter sequence by losing the
958 likely bit, generating something like:
963 delay slot (executed only if branch taken)
975 bltzall -> bgezal (with jal label instead of j label)
976 bgezall -> bltzal (ditto)
979 but it's not clear that it would actually improve performance. */
980 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
984 | ((toofar) ? 0x20 : 0) \
985 | ((link) ? 0x40 : 0) \
986 | ((likely) ? 0x80 : 0) \
987 | ((uncond) ? 0x100 : 0)))
988 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
989 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
990 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
991 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
992 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
993 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
995 /* For mips16 code, we use an entirely different form of relaxation.
996 mips16 supports two versions of most instructions which take
997 immediate values: a small one which takes some small value, and a
998 larger one which takes a 16 bit value. Since branches also follow
999 this pattern, relaxing these values is required.
1001 We can assemble both mips16 and normal MIPS code in a single
1002 object. Therefore, we need to support this type of relaxation at
1003 the same time that we support the relaxation described above. We
1004 use the high bit of the subtype field to distinguish these cases.
1006 The information we store for this type of relaxation is the
1007 argument code found in the opcode file for this relocation, whether
1008 the user explicitly requested a small or extended form, and whether
1009 the relocation is in a jump or jal delay slot. That tells us the
1010 size of the value, and how it should be stored. We also store
1011 whether the fragment is considered to be extended or not. We also
1012 store whether this is known to be a branch to a different section,
1013 whether we have tried to relax this frag yet, and whether we have
1014 ever extended a PC relative fragment because of a shift count. */
1015 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1018 | ((small) ? 0x100 : 0) \
1019 | ((ext) ? 0x200 : 0) \
1020 | ((dslot) ? 0x400 : 0) \
1021 | ((jal_dslot) ? 0x800 : 0))
1022 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1023 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1024 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1025 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1026 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1027 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1028 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1029 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1030 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1031 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1032 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1033 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1035 /* For microMIPS code, we use relaxation similar to one we use for
1036 MIPS16 code. Some instructions that take immediate values support
1037 two encodings: a small one which takes some small value, and a
1038 larger one which takes a 16 bit value. As some branches also follow
1039 this pattern, relaxing these values is required.
1041 We can assemble both microMIPS and normal MIPS code in a single
1042 object. Therefore, we need to support this type of relaxation at
1043 the same time that we support the relaxation described above. We
1044 use one of the high bits of the subtype field to distinguish these
1047 The information we store for this type of relaxation is the argument
1048 code found in the opcode file for this relocation, the register
1049 selected as the assembler temporary, whether the branch is
1050 unconditional, whether it is compact, whether it stores the link
1051 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1052 branches to a sequence of instructions is enabled, and whether the
1053 displacement of a branch is too large to fit as an immediate argument
1054 of a 16-bit and a 32-bit branch, respectively. */
1055 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1056 relax32, toofar16, toofar32) \
1059 | (((at) & 0x1f) << 8) \
1060 | ((uncond) ? 0x2000 : 0) \
1061 | ((compact) ? 0x4000 : 0) \
1062 | ((link) ? 0x8000 : 0) \
1063 | ((relax32) ? 0x10000 : 0) \
1064 | ((toofar16) ? 0x20000 : 0) \
1065 | ((toofar32) ? 0x40000 : 0))
1066 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1067 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1068 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1069 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1070 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1071 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1072 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1074 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1075 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1076 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1077 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1078 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1079 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1081 /* Sign-extend 16-bit value X. */
1082 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1084 /* Is the given value a sign-extended 32-bit value? */
1085 #define IS_SEXT_32BIT_NUM(x) \
1086 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1087 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1089 /* Is the given value a sign-extended 16-bit value? */
1090 #define IS_SEXT_16BIT_NUM(x) \
1091 (((x) &~ (offsetT) 0x7fff) == 0 \
1092 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1094 /* Is the given value a sign-extended 12-bit value? */
1095 #define IS_SEXT_12BIT_NUM(x) \
1096 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1098 /* Is the given value a sign-extended 9-bit value? */
1099 #define IS_SEXT_9BIT_NUM(x) \
1100 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1102 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1103 #define IS_ZEXT_32BIT_NUM(x) \
1104 (((x) &~ (offsetT) 0xffffffff) == 0 \
1105 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1107 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1109 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1110 (((STRUCT) >> (SHIFT)) & (MASK))
1112 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1113 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1115 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1116 : EXTRACT_BITS ((INSN).insn_opcode, \
1117 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1118 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1119 EXTRACT_BITS ((INSN).insn_opcode, \
1120 MIPS16OP_MASK_##FIELD, \
1121 MIPS16OP_SH_##FIELD)
1123 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1124 #define MIPS16_EXTEND (0xf000U << 16)
1126 /* Whether or not we are emitting a branch-likely macro. */
1127 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1129 /* Global variables used when generating relaxable macros. See the
1130 comment above RELAX_ENCODE for more details about how relaxation
1133 /* 0 if we're not emitting a relaxable macro.
1134 1 if we're emitting the first of the two relaxation alternatives.
1135 2 if we're emitting the second alternative. */
1138 /* The first relaxable fixup in the current frag. (In other words,
1139 the first fixup that refers to relaxable code.) */
1142 /* sizes[0] says how many bytes of the first alternative are stored in
1143 the current frag. Likewise sizes[1] for the second alternative. */
1144 unsigned int sizes
[2];
1146 /* The symbol on which the choice of sequence depends. */
1150 /* Global variables used to decide whether a macro needs a warning. */
1152 /* True if the macro is in a branch delay slot. */
1153 bfd_boolean delay_slot_p
;
1155 /* Set to the length in bytes required if the macro is in a delay slot
1156 that requires a specific length of instruction, otherwise zero. */
1157 unsigned int delay_slot_length
;
1159 /* For relaxable macros, sizes[0] is the length of the first alternative
1160 in bytes and sizes[1] is the length of the second alternative.
1161 For non-relaxable macros, both elements give the length of the
1163 unsigned int sizes
[2];
1165 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1166 instruction of the first alternative in bytes and first_insn_sizes[1]
1167 is the length of the first instruction of the second alternative.
1168 For non-relaxable macros, both elements give the length of the first
1169 instruction in bytes.
1171 Set to zero if we haven't yet seen the first instruction. */
1172 unsigned int first_insn_sizes
[2];
1174 /* For relaxable macros, insns[0] is the number of instructions for the
1175 first alternative and insns[1] is the number of instructions for the
1178 For non-relaxable macros, both elements give the number of
1179 instructions for the macro. */
1180 unsigned int insns
[2];
1182 /* The first variant frag for this macro. */
1184 } mips_macro_warning
;
1186 /* Prototypes for static functions. */
1188 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1190 static void append_insn
1191 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1192 bfd_boolean expansionp
);
1193 static void mips_no_prev_insn (void);
1194 static void macro_build (expressionS
*, const char *, const char *, ...);
1195 static void mips16_macro_build
1196 (expressionS
*, const char *, const char *, va_list *);
1197 static void load_register (int, expressionS
*, int);
1198 static void macro_start (void);
1199 static void macro_end (void);
1200 static void macro (struct mips_cl_insn
*ip
, char *str
);
1201 static void mips16_macro (struct mips_cl_insn
* ip
);
1202 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1203 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1204 static void mips16_immed
1205 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1206 unsigned int, unsigned long *);
1207 static size_t my_getSmallExpression
1208 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1209 static void my_getExpression (expressionS
*, char *);
1210 static void s_align (int);
1211 static void s_change_sec (int);
1212 static void s_change_section (int);
1213 static void s_cons (int);
1214 static void s_float_cons (int);
1215 static void s_mips_globl (int);
1216 static void s_option (int);
1217 static void s_mipsset (int);
1218 static void s_abicalls (int);
1219 static void s_cpload (int);
1220 static void s_cpsetup (int);
1221 static void s_cplocal (int);
1222 static void s_cprestore (int);
1223 static void s_cpreturn (int);
1224 static void s_dtprelword (int);
1225 static void s_dtpreldword (int);
1226 static void s_tprelword (int);
1227 static void s_tpreldword (int);
1228 static void s_gpvalue (int);
1229 static void s_gpword (int);
1230 static void s_gpdword (int);
1231 static void s_ehword (int);
1232 static void s_cpadd (int);
1233 static void s_insn (int);
1234 static void s_nan (int);
1235 static void md_obj_begin (void);
1236 static void md_obj_end (void);
1237 static void s_mips_ent (int);
1238 static void s_mips_end (int);
1239 static void s_mips_frame (int);
1240 static void s_mips_mask (int reg_type
);
1241 static void s_mips_stab (int);
1242 static void s_mips_weakext (int);
1243 static void s_mips_file (int);
1244 static void s_mips_loc (int);
1245 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1246 static int relaxed_branch_length (fragS
*, asection
*, int);
1247 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1248 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1250 /* Table and functions used to map between CPU/ISA names, and
1251 ISA levels, and CPU numbers. */
1253 struct mips_cpu_info
1255 const char *name
; /* CPU or ISA name. */
1256 int flags
; /* MIPS_CPU_* flags. */
1257 int ase
; /* Set of ASEs implemented by the CPU. */
1258 int isa
; /* ISA level. */
1259 int cpu
; /* CPU number (default CPU if ISA). */
1262 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1264 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1265 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1266 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1268 /* Command-line options. */
1269 const char *md_shortopts
= "O::g::G:";
1273 OPTION_MARCH
= OPTION_MD_BASE
,
1297 OPTION_NO_SMARTMIPS
,
1303 OPTION_NO_MICROMIPS
,
1306 OPTION_COMPAT_ARCH_BASE
,
1315 OPTION_M7000_HILO_FIX
,
1316 OPTION_MNO_7000_HILO_FIX
,
1319 OPTION_FIX_LOONGSON2F_JUMP
,
1320 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1321 OPTION_FIX_LOONGSON2F_NOP
,
1322 OPTION_NO_FIX_LOONGSON2F_NOP
,
1324 OPTION_NO_FIX_VR4120
,
1326 OPTION_NO_FIX_VR4130
,
1327 OPTION_FIX_CN63XXP1
,
1328 OPTION_NO_FIX_CN63XXP1
,
1335 OPTION_CONSTRUCT_FLOATS
,
1336 OPTION_NO_CONSTRUCT_FLOATS
,
1339 OPTION_RELAX_BRANCH
,
1340 OPTION_NO_RELAX_BRANCH
,
1349 OPTION_SINGLE_FLOAT
,
1350 OPTION_DOUBLE_FLOAT
,
1363 OPTION_MVXWORKS_PIC
,
1368 struct option md_longopts
[] =
1370 /* Options which specify architecture. */
1371 {"march", required_argument
, NULL
, OPTION_MARCH
},
1372 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1373 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1374 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1375 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1376 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1377 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1378 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1379 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1380 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1381 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1382 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1384 /* Options which specify Application Specific Extensions (ASEs). */
1385 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1386 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1387 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1388 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1389 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1390 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1391 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1392 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1393 {"mmt", no_argument
, NULL
, OPTION_MT
},
1394 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1395 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1396 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1397 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1398 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1399 {"meva", no_argument
, NULL
, OPTION_EVA
},
1400 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1401 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1402 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1403 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1404 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1405 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1406 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1408 /* Old-style architecture options. Don't add more of these. */
1409 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1410 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1411 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1412 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1413 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1414 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1415 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1416 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1418 /* Options which enable bug fixes. */
1419 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1420 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1421 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1422 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1423 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1424 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1425 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1426 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1427 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1428 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1429 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1430 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1431 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1432 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1433 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1435 /* Miscellaneous options. */
1436 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1437 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1438 {"break", no_argument
, NULL
, OPTION_BREAK
},
1439 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1440 {"EB", no_argument
, NULL
, OPTION_EB
},
1441 {"EL", no_argument
, NULL
, OPTION_EL
},
1442 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1443 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1444 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1445 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1446 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1447 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1448 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1449 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1450 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1451 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1452 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1453 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1454 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1455 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1456 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1457 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1458 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1459 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1461 /* Strictly speaking this next option is ELF specific,
1462 but we allow it for other ports as well in order to
1463 make testing easier. */
1464 {"32", no_argument
, NULL
, OPTION_32
},
1466 /* ELF-specific options. */
1467 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1468 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1469 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1470 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1471 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1472 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1473 {"n32", no_argument
, NULL
, OPTION_N32
},
1474 {"64", no_argument
, NULL
, OPTION_64
},
1475 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1476 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1477 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1478 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1479 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1480 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1482 {NULL
, no_argument
, NULL
, 0}
1484 size_t md_longopts_size
= sizeof (md_longopts
);
1486 /* Information about either an Application Specific Extension or an
1487 optional architecture feature that, for simplicity, we treat in the
1488 same way as an ASE. */
1491 /* The name of the ASE, used in both the command-line and .set options. */
1494 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1495 and 64-bit architectures, the flags here refer to the subset that
1496 is available on both. */
1499 /* The ASE_* flag used for instructions that are available on 64-bit
1500 architectures but that are not included in FLAGS. */
1501 unsigned int flags64
;
1503 /* The command-line options that turn the ASE on and off. */
1507 /* The minimum required architecture revisions for MIPS32, MIPS64,
1508 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1511 int micromips32_rev
;
1512 int micromips64_rev
;
1515 /* A table of all supported ASEs. */
1516 static const struct mips_ase mips_ases
[] = {
1517 { "dsp", ASE_DSP
, ASE_DSP64
,
1518 OPTION_DSP
, OPTION_NO_DSP
,
1521 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1522 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1525 { "eva", ASE_EVA
, 0,
1526 OPTION_EVA
, OPTION_NO_EVA
,
1529 { "mcu", ASE_MCU
, 0,
1530 OPTION_MCU
, OPTION_NO_MCU
,
1533 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1534 { "mdmx", ASE_MDMX
, 0,
1535 OPTION_MDMX
, OPTION_NO_MDMX
,
1538 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1539 { "mips3d", ASE_MIPS3D
, 0,
1540 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1544 OPTION_MT
, OPTION_NO_MT
,
1547 { "smartmips", ASE_SMARTMIPS
, 0,
1548 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1551 { "virt", ASE_VIRT
, ASE_VIRT64
,
1552 OPTION_VIRT
, OPTION_NO_VIRT
,
1556 /* The set of ASEs that require -mfp64. */
1557 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1559 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1560 static const unsigned int mips_ase_groups
[] = {
1566 The following pseudo-ops from the Kane and Heinrich MIPS book
1567 should be defined here, but are currently unsupported: .alias,
1568 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1570 The following pseudo-ops from the Kane and Heinrich MIPS book are
1571 specific to the type of debugging information being generated, and
1572 should be defined by the object format: .aent, .begin, .bend,
1573 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1576 The following pseudo-ops from the Kane and Heinrich MIPS book are
1577 not MIPS CPU specific, but are also not specific to the object file
1578 format. This file is probably the best place to define them, but
1579 they are not currently supported: .asm0, .endr, .lab, .struct. */
1581 static const pseudo_typeS mips_pseudo_table
[] =
1583 /* MIPS specific pseudo-ops. */
1584 {"option", s_option
, 0},
1585 {"set", s_mipsset
, 0},
1586 {"rdata", s_change_sec
, 'r'},
1587 {"sdata", s_change_sec
, 's'},
1588 {"livereg", s_ignore
, 0},
1589 {"abicalls", s_abicalls
, 0},
1590 {"cpload", s_cpload
, 0},
1591 {"cpsetup", s_cpsetup
, 0},
1592 {"cplocal", s_cplocal
, 0},
1593 {"cprestore", s_cprestore
, 0},
1594 {"cpreturn", s_cpreturn
, 0},
1595 {"dtprelword", s_dtprelword
, 0},
1596 {"dtpreldword", s_dtpreldword
, 0},
1597 {"tprelword", s_tprelword
, 0},
1598 {"tpreldword", s_tpreldword
, 0},
1599 {"gpvalue", s_gpvalue
, 0},
1600 {"gpword", s_gpword
, 0},
1601 {"gpdword", s_gpdword
, 0},
1602 {"ehword", s_ehword
, 0},
1603 {"cpadd", s_cpadd
, 0},
1604 {"insn", s_insn
, 0},
1607 /* Relatively generic pseudo-ops that happen to be used on MIPS
1609 {"asciiz", stringer
, 8 + 1},
1610 {"bss", s_change_sec
, 'b'},
1612 {"half", s_cons
, 1},
1613 {"dword", s_cons
, 3},
1614 {"weakext", s_mips_weakext
, 0},
1615 {"origin", s_org
, 0},
1616 {"repeat", s_rept
, 0},
1618 /* For MIPS this is non-standard, but we define it for consistency. */
1619 {"sbss", s_change_sec
, 'B'},
1621 /* These pseudo-ops are defined in read.c, but must be overridden
1622 here for one reason or another. */
1623 {"align", s_align
, 0},
1624 {"byte", s_cons
, 0},
1625 {"data", s_change_sec
, 'd'},
1626 {"double", s_float_cons
, 'd'},
1627 {"float", s_float_cons
, 'f'},
1628 {"globl", s_mips_globl
, 0},
1629 {"global", s_mips_globl
, 0},
1630 {"hword", s_cons
, 1},
1632 {"long", s_cons
, 2},
1633 {"octa", s_cons
, 4},
1634 {"quad", s_cons
, 3},
1635 {"section", s_change_section
, 0},
1636 {"short", s_cons
, 1},
1637 {"single", s_float_cons
, 'f'},
1638 {"stabd", s_mips_stab
, 'd'},
1639 {"stabn", s_mips_stab
, 'n'},
1640 {"stabs", s_mips_stab
, 's'},
1641 {"text", s_change_sec
, 't'},
1642 {"word", s_cons
, 2},
1644 { "extern", ecoff_directive_extern
, 0},
1649 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1651 /* These pseudo-ops should be defined by the object file format.
1652 However, a.out doesn't support them, so we have versions here. */
1653 {"aent", s_mips_ent
, 1},
1654 {"bgnb", s_ignore
, 0},
1655 {"end", s_mips_end
, 0},
1656 {"endb", s_ignore
, 0},
1657 {"ent", s_mips_ent
, 0},
1658 {"file", s_mips_file
, 0},
1659 {"fmask", s_mips_mask
, 'F'},
1660 {"frame", s_mips_frame
, 0},
1661 {"loc", s_mips_loc
, 0},
1662 {"mask", s_mips_mask
, 'R'},
1663 {"verstamp", s_ignore
, 0},
1667 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1668 purpose of the `.dc.a' internal pseudo-op. */
1671 mips_address_bytes (void)
1673 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1676 extern void pop_insert (const pseudo_typeS
*);
1679 mips_pop_insert (void)
1681 pop_insert (mips_pseudo_table
);
1682 if (! ECOFF_DEBUGGING
)
1683 pop_insert (mips_nonecoff_pseudo_table
);
1686 /* Symbols labelling the current insn. */
1688 struct insn_label_list
1690 struct insn_label_list
*next
;
1694 static struct insn_label_list
*free_insn_labels
;
1695 #define label_list tc_segment_info_data.labels
1697 static void mips_clear_insn_labels (void);
1698 static void mips_mark_labels (void);
1699 static void mips_compressed_mark_labels (void);
1702 mips_clear_insn_labels (void)
1704 register struct insn_label_list
**pl
;
1705 segment_info_type
*si
;
1709 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1712 si
= seg_info (now_seg
);
1713 *pl
= si
->label_list
;
1714 si
->label_list
= NULL
;
1718 /* Mark instruction labels in MIPS16/microMIPS mode. */
1721 mips_mark_labels (void)
1723 if (HAVE_CODE_COMPRESSION
)
1724 mips_compressed_mark_labels ();
1727 static char *expr_end
;
1729 /* Expressions which appear in macro instructions. These are set by
1730 mips_ip and read by macro. */
1732 static expressionS imm_expr
;
1733 static expressionS imm2_expr
;
1735 /* The relocatable field in an instruction and the relocs associated
1736 with it. These variables are used for instructions like LUI and
1737 JAL as well as true offsets. They are also used for address
1738 operands in macros. */
1740 static expressionS offset_expr
;
1741 static bfd_reloc_code_real_type offset_reloc
[3]
1742 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1744 /* This is set to the resulting size of the instruction to be produced
1745 by mips16_ip if an explicit extension is used or by mips_ip if an
1746 explicit size is supplied. */
1748 static unsigned int forced_insn_length
;
1750 /* True if we are assembling an instruction. All dot symbols defined during
1751 this time should be treated as code labels. */
1753 static bfd_boolean mips_assembling_insn
;
1755 /* The pdr segment for per procedure frame/regmask info. Not used for
1758 static segT pdr_seg
;
1760 /* The default target format to use. */
1762 #if defined (TE_FreeBSD)
1763 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1764 #elif defined (TE_TMIPS)
1765 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1767 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1771 mips_target_format (void)
1773 switch (OUTPUT_FLAVOR
)
1775 case bfd_target_elf_flavour
:
1777 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1778 return (target_big_endian
1779 ? "elf32-bigmips-vxworks"
1780 : "elf32-littlemips-vxworks");
1782 return (target_big_endian
1783 ? (HAVE_64BIT_OBJECTS
1784 ? ELF_TARGET ("elf64-", "big")
1786 ? ELF_TARGET ("elf32-n", "big")
1787 : ELF_TARGET ("elf32-", "big")))
1788 : (HAVE_64BIT_OBJECTS
1789 ? ELF_TARGET ("elf64-", "little")
1791 ? ELF_TARGET ("elf32-n", "little")
1792 : ELF_TARGET ("elf32-", "little"))));
1799 /* Return the ISA revision that is currently in use, or 0 if we are
1800 generating code for MIPS V or below. */
1805 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1808 /* microMIPS implies revision 2 or above. */
1809 if (mips_opts
.micromips
)
1812 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1818 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1821 mips_ase_mask (unsigned int flags
)
1825 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1826 if (flags
& mips_ase_groups
[i
])
1827 flags
|= mips_ase_groups
[i
];
1831 /* Check whether the current ISA supports ASE. Issue a warning if
1835 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1839 static unsigned int warned_isa
;
1840 static unsigned int warned_fp32
;
1842 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1843 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1845 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1846 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1847 && (warned_isa
& ase
->flags
) != ase
->flags
)
1849 warned_isa
|= ase
->flags
;
1850 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1851 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1853 as_warn (_("The %d-bit %s architecture does not support the"
1854 " `%s' extension"), size
, base
, ase
->name
);
1856 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1857 ase
->name
, base
, size
, min_rev
);
1859 if ((ase
->flags
& FP64_ASES
)
1861 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1863 warned_fp32
|= ase
->flags
;
1864 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1868 /* Check all enabled ASEs to see whether they are supported by the
1869 chosen architecture. */
1872 mips_check_isa_supports_ases (void)
1874 unsigned int i
, mask
;
1876 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1878 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1879 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1880 mips_check_isa_supports_ase (&mips_ases
[i
]);
1884 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1885 that were affected. */
1888 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1892 mask
= mips_ase_mask (ase
->flags
);
1893 mips_opts
.ase
&= ~mask
;
1895 mips_opts
.ase
|= ase
->flags
;
1899 /* Return the ASE called NAME, or null if none. */
1901 static const struct mips_ase
*
1902 mips_lookup_ase (const char *name
)
1906 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1907 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1908 return &mips_ases
[i
];
1912 /* Return the length of a microMIPS instruction in bytes. If bits of
1913 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1914 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1915 major opcode) will require further modifications to the opcode
1918 static inline unsigned int
1919 micromips_insn_length (const struct mips_opcode
*mo
)
1921 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1924 /* Return the length of MIPS16 instruction OPCODE. */
1926 static inline unsigned int
1927 mips16_opcode_length (unsigned long opcode
)
1929 return (opcode
>> 16) == 0 ? 2 : 4;
1932 /* Return the length of instruction INSN. */
1934 static inline unsigned int
1935 insn_length (const struct mips_cl_insn
*insn
)
1937 if (mips_opts
.micromips
)
1938 return micromips_insn_length (insn
->insn_mo
);
1939 else if (mips_opts
.mips16
)
1940 return mips16_opcode_length (insn
->insn_opcode
);
1945 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1948 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1953 insn
->insn_opcode
= mo
->match
;
1956 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1957 insn
->fixp
[i
] = NULL
;
1958 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1959 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1960 insn
->mips16_absolute_jump_p
= 0;
1961 insn
->complete_p
= 0;
1962 insn
->cleared_p
= 0;
1965 /* Get a list of all the operands in INSN. */
1967 static const struct mips_operand_array
*
1968 insn_operands (const struct mips_cl_insn
*insn
)
1970 if (insn
->insn_mo
>= &mips_opcodes
[0]
1971 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
1972 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
1974 if (insn
->insn_mo
>= &mips16_opcodes
[0]
1975 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
1976 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
1978 if (insn
->insn_mo
>= µmips_opcodes
[0]
1979 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
1980 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
1985 /* Get a description of operand OPNO of INSN. */
1987 static const struct mips_operand
*
1988 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
1990 const struct mips_operand_array
*operands
;
1992 operands
= insn_operands (insn
);
1993 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
1995 return operands
->operand
[opno
];
1998 /* Install UVAL as the value of OPERAND in INSN. */
2001 insn_insert_operand (struct mips_cl_insn
*insn
,
2002 const struct mips_operand
*operand
, unsigned int uval
)
2004 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2007 /* Extract the value of OPERAND from INSN. */
2009 static inline unsigned
2010 insn_extract_operand (const struct mips_cl_insn
*insn
,
2011 const struct mips_operand
*operand
)
2013 return mips_extract_operand (operand
, insn
->insn_opcode
);
2016 /* Record the current MIPS16/microMIPS mode in now_seg. */
2019 mips_record_compressed_mode (void)
2021 segment_info_type
*si
;
2023 si
= seg_info (now_seg
);
2024 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2025 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2026 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2027 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2030 /* Read a standard MIPS instruction from BUF. */
2032 static unsigned long
2033 read_insn (char *buf
)
2035 if (target_big_endian
)
2036 return bfd_getb32 ((bfd_byte
*) buf
);
2038 return bfd_getl32 ((bfd_byte
*) buf
);
2041 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2045 write_insn (char *buf
, unsigned int insn
)
2047 md_number_to_chars (buf
, insn
, 4);
2051 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2052 has length LENGTH. */
2054 static unsigned long
2055 read_compressed_insn (char *buf
, unsigned int length
)
2061 for (i
= 0; i
< length
; i
+= 2)
2064 if (target_big_endian
)
2065 insn
|= bfd_getb16 ((char *) buf
);
2067 insn
|= bfd_getl16 ((char *) buf
);
2073 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2074 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2077 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2081 for (i
= 0; i
< length
; i
+= 2)
2082 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2083 return buf
+ length
;
2086 /* Install INSN at the location specified by its "frag" and "where" fields. */
2089 install_insn (const struct mips_cl_insn
*insn
)
2091 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2092 if (HAVE_CODE_COMPRESSION
)
2093 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2095 write_insn (f
, insn
->insn_opcode
);
2096 mips_record_compressed_mode ();
2099 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2100 and install the opcode in the new location. */
2103 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2108 insn
->where
= where
;
2109 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2110 if (insn
->fixp
[i
] != NULL
)
2112 insn
->fixp
[i
]->fx_frag
= frag
;
2113 insn
->fixp
[i
]->fx_where
= where
;
2115 install_insn (insn
);
2118 /* Add INSN to the end of the output. */
2121 add_fixed_insn (struct mips_cl_insn
*insn
)
2123 char *f
= frag_more (insn_length (insn
));
2124 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2127 /* Start a variant frag and move INSN to the start of the variant part,
2128 marking it as fixed. The other arguments are as for frag_var. */
2131 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2132 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2134 frag_grow (max_chars
);
2135 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2137 frag_var (rs_machine_dependent
, max_chars
, var
,
2138 subtype
, symbol
, offset
, NULL
);
2141 /* Insert N copies of INSN into the history buffer, starting at
2142 position FIRST. Neither FIRST nor N need to be clipped. */
2145 insert_into_history (unsigned int first
, unsigned int n
,
2146 const struct mips_cl_insn
*insn
)
2148 if (mips_relax
.sequence
!= 2)
2152 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2154 history
[i
] = history
[i
- n
];
2160 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2161 the idea is to make it obvious at a glance that each errata is
2165 init_vr4120_conflicts (void)
2167 #define CONFLICT(FIRST, SECOND) \
2168 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2170 /* Errata 21 - [D]DIV[U] after [D]MACC */
2171 CONFLICT (MACC
, DIV
);
2172 CONFLICT (DMACC
, DIV
);
2174 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2175 CONFLICT (DMULT
, DMULT
);
2176 CONFLICT (DMULT
, DMACC
);
2177 CONFLICT (DMACC
, DMULT
);
2178 CONFLICT (DMACC
, DMACC
);
2180 /* Errata 24 - MT{LO,HI} after [D]MACC */
2181 CONFLICT (MACC
, MTHILO
);
2182 CONFLICT (DMACC
, MTHILO
);
2184 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2185 instruction is executed immediately after a MACC or DMACC
2186 instruction, the result of [either instruction] is incorrect." */
2187 CONFLICT (MACC
, MULT
);
2188 CONFLICT (MACC
, DMULT
);
2189 CONFLICT (DMACC
, MULT
);
2190 CONFLICT (DMACC
, DMULT
);
2192 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2193 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2194 DDIV or DDIVU instruction, the result of the MACC or
2195 DMACC instruction is incorrect.". */
2196 CONFLICT (DMULT
, MACC
);
2197 CONFLICT (DMULT
, DMACC
);
2198 CONFLICT (DIV
, MACC
);
2199 CONFLICT (DIV
, DMACC
);
2209 #define RNUM_MASK 0x00000ff
2210 #define RTYPE_MASK 0x0efff00
2211 #define RTYPE_NUM 0x0000100
2212 #define RTYPE_FPU 0x0000200
2213 #define RTYPE_FCC 0x0000400
2214 #define RTYPE_VEC 0x0000800
2215 #define RTYPE_GP 0x0001000
2216 #define RTYPE_CP0 0x0002000
2217 #define RTYPE_PC 0x0004000
2218 #define RTYPE_ACC 0x0008000
2219 #define RTYPE_CCC 0x0010000
2220 #define RTYPE_VI 0x0020000
2221 #define RTYPE_VF 0x0040000
2222 #define RTYPE_R5900_I 0x0080000
2223 #define RTYPE_R5900_Q 0x0100000
2224 #define RTYPE_R5900_R 0x0200000
2225 #define RTYPE_R5900_ACC 0x0400000
2226 #define RWARN 0x8000000
2228 #define GENERIC_REGISTER_NUMBERS \
2229 {"$0", RTYPE_NUM | 0}, \
2230 {"$1", RTYPE_NUM | 1}, \
2231 {"$2", RTYPE_NUM | 2}, \
2232 {"$3", RTYPE_NUM | 3}, \
2233 {"$4", RTYPE_NUM | 4}, \
2234 {"$5", RTYPE_NUM | 5}, \
2235 {"$6", RTYPE_NUM | 6}, \
2236 {"$7", RTYPE_NUM | 7}, \
2237 {"$8", RTYPE_NUM | 8}, \
2238 {"$9", RTYPE_NUM | 9}, \
2239 {"$10", RTYPE_NUM | 10}, \
2240 {"$11", RTYPE_NUM | 11}, \
2241 {"$12", RTYPE_NUM | 12}, \
2242 {"$13", RTYPE_NUM | 13}, \
2243 {"$14", RTYPE_NUM | 14}, \
2244 {"$15", RTYPE_NUM | 15}, \
2245 {"$16", RTYPE_NUM | 16}, \
2246 {"$17", RTYPE_NUM | 17}, \
2247 {"$18", RTYPE_NUM | 18}, \
2248 {"$19", RTYPE_NUM | 19}, \
2249 {"$20", RTYPE_NUM | 20}, \
2250 {"$21", RTYPE_NUM | 21}, \
2251 {"$22", RTYPE_NUM | 22}, \
2252 {"$23", RTYPE_NUM | 23}, \
2253 {"$24", RTYPE_NUM | 24}, \
2254 {"$25", RTYPE_NUM | 25}, \
2255 {"$26", RTYPE_NUM | 26}, \
2256 {"$27", RTYPE_NUM | 27}, \
2257 {"$28", RTYPE_NUM | 28}, \
2258 {"$29", RTYPE_NUM | 29}, \
2259 {"$30", RTYPE_NUM | 30}, \
2260 {"$31", RTYPE_NUM | 31}
2262 #define FPU_REGISTER_NAMES \
2263 {"$f0", RTYPE_FPU | 0}, \
2264 {"$f1", RTYPE_FPU | 1}, \
2265 {"$f2", RTYPE_FPU | 2}, \
2266 {"$f3", RTYPE_FPU | 3}, \
2267 {"$f4", RTYPE_FPU | 4}, \
2268 {"$f5", RTYPE_FPU | 5}, \
2269 {"$f6", RTYPE_FPU | 6}, \
2270 {"$f7", RTYPE_FPU | 7}, \
2271 {"$f8", RTYPE_FPU | 8}, \
2272 {"$f9", RTYPE_FPU | 9}, \
2273 {"$f10", RTYPE_FPU | 10}, \
2274 {"$f11", RTYPE_FPU | 11}, \
2275 {"$f12", RTYPE_FPU | 12}, \
2276 {"$f13", RTYPE_FPU | 13}, \
2277 {"$f14", RTYPE_FPU | 14}, \
2278 {"$f15", RTYPE_FPU | 15}, \
2279 {"$f16", RTYPE_FPU | 16}, \
2280 {"$f17", RTYPE_FPU | 17}, \
2281 {"$f18", RTYPE_FPU | 18}, \
2282 {"$f19", RTYPE_FPU | 19}, \
2283 {"$f20", RTYPE_FPU | 20}, \
2284 {"$f21", RTYPE_FPU | 21}, \
2285 {"$f22", RTYPE_FPU | 22}, \
2286 {"$f23", RTYPE_FPU | 23}, \
2287 {"$f24", RTYPE_FPU | 24}, \
2288 {"$f25", RTYPE_FPU | 25}, \
2289 {"$f26", RTYPE_FPU | 26}, \
2290 {"$f27", RTYPE_FPU | 27}, \
2291 {"$f28", RTYPE_FPU | 28}, \
2292 {"$f29", RTYPE_FPU | 29}, \
2293 {"$f30", RTYPE_FPU | 30}, \
2294 {"$f31", RTYPE_FPU | 31}
2296 #define FPU_CONDITION_CODE_NAMES \
2297 {"$fcc0", RTYPE_FCC | 0}, \
2298 {"$fcc1", RTYPE_FCC | 1}, \
2299 {"$fcc2", RTYPE_FCC | 2}, \
2300 {"$fcc3", RTYPE_FCC | 3}, \
2301 {"$fcc4", RTYPE_FCC | 4}, \
2302 {"$fcc5", RTYPE_FCC | 5}, \
2303 {"$fcc6", RTYPE_FCC | 6}, \
2304 {"$fcc7", RTYPE_FCC | 7}
2306 #define COPROC_CONDITION_CODE_NAMES \
2307 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2308 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2309 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2310 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2311 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2312 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2313 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2314 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2316 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2317 {"$a4", RTYPE_GP | 8}, \
2318 {"$a5", RTYPE_GP | 9}, \
2319 {"$a6", RTYPE_GP | 10}, \
2320 {"$a7", RTYPE_GP | 11}, \
2321 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2322 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2323 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2324 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2325 {"$t0", RTYPE_GP | 12}, \
2326 {"$t1", RTYPE_GP | 13}, \
2327 {"$t2", RTYPE_GP | 14}, \
2328 {"$t3", RTYPE_GP | 15}
2330 #define O32_SYMBOLIC_REGISTER_NAMES \
2331 {"$t0", RTYPE_GP | 8}, \
2332 {"$t1", RTYPE_GP | 9}, \
2333 {"$t2", RTYPE_GP | 10}, \
2334 {"$t3", RTYPE_GP | 11}, \
2335 {"$t4", RTYPE_GP | 12}, \
2336 {"$t5", RTYPE_GP | 13}, \
2337 {"$t6", RTYPE_GP | 14}, \
2338 {"$t7", RTYPE_GP | 15}, \
2339 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2340 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2341 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2342 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2344 /* Remaining symbolic register names */
2345 #define SYMBOLIC_REGISTER_NAMES \
2346 {"$zero", RTYPE_GP | 0}, \
2347 {"$at", RTYPE_GP | 1}, \
2348 {"$AT", RTYPE_GP | 1}, \
2349 {"$v0", RTYPE_GP | 2}, \
2350 {"$v1", RTYPE_GP | 3}, \
2351 {"$a0", RTYPE_GP | 4}, \
2352 {"$a1", RTYPE_GP | 5}, \
2353 {"$a2", RTYPE_GP | 6}, \
2354 {"$a3", RTYPE_GP | 7}, \
2355 {"$s0", RTYPE_GP | 16}, \
2356 {"$s1", RTYPE_GP | 17}, \
2357 {"$s2", RTYPE_GP | 18}, \
2358 {"$s3", RTYPE_GP | 19}, \
2359 {"$s4", RTYPE_GP | 20}, \
2360 {"$s5", RTYPE_GP | 21}, \
2361 {"$s6", RTYPE_GP | 22}, \
2362 {"$s7", RTYPE_GP | 23}, \
2363 {"$t8", RTYPE_GP | 24}, \
2364 {"$t9", RTYPE_GP | 25}, \
2365 {"$k0", RTYPE_GP | 26}, \
2366 {"$kt0", RTYPE_GP | 26}, \
2367 {"$k1", RTYPE_GP | 27}, \
2368 {"$kt1", RTYPE_GP | 27}, \
2369 {"$gp", RTYPE_GP | 28}, \
2370 {"$sp", RTYPE_GP | 29}, \
2371 {"$s8", RTYPE_GP | 30}, \
2372 {"$fp", RTYPE_GP | 30}, \
2373 {"$ra", RTYPE_GP | 31}
2375 #define MIPS16_SPECIAL_REGISTER_NAMES \
2376 {"$pc", RTYPE_PC | 0}
2378 #define MDMX_VECTOR_REGISTER_NAMES \
2379 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2380 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2381 {"$v2", RTYPE_VEC | 2}, \
2382 {"$v3", RTYPE_VEC | 3}, \
2383 {"$v4", RTYPE_VEC | 4}, \
2384 {"$v5", RTYPE_VEC | 5}, \
2385 {"$v6", RTYPE_VEC | 6}, \
2386 {"$v7", RTYPE_VEC | 7}, \
2387 {"$v8", RTYPE_VEC | 8}, \
2388 {"$v9", RTYPE_VEC | 9}, \
2389 {"$v10", RTYPE_VEC | 10}, \
2390 {"$v11", RTYPE_VEC | 11}, \
2391 {"$v12", RTYPE_VEC | 12}, \
2392 {"$v13", RTYPE_VEC | 13}, \
2393 {"$v14", RTYPE_VEC | 14}, \
2394 {"$v15", RTYPE_VEC | 15}, \
2395 {"$v16", RTYPE_VEC | 16}, \
2396 {"$v17", RTYPE_VEC | 17}, \
2397 {"$v18", RTYPE_VEC | 18}, \
2398 {"$v19", RTYPE_VEC | 19}, \
2399 {"$v20", RTYPE_VEC | 20}, \
2400 {"$v21", RTYPE_VEC | 21}, \
2401 {"$v22", RTYPE_VEC | 22}, \
2402 {"$v23", RTYPE_VEC | 23}, \
2403 {"$v24", RTYPE_VEC | 24}, \
2404 {"$v25", RTYPE_VEC | 25}, \
2405 {"$v26", RTYPE_VEC | 26}, \
2406 {"$v27", RTYPE_VEC | 27}, \
2407 {"$v28", RTYPE_VEC | 28}, \
2408 {"$v29", RTYPE_VEC | 29}, \
2409 {"$v30", RTYPE_VEC | 30}, \
2410 {"$v31", RTYPE_VEC | 31}
2412 #define R5900_I_NAMES \
2413 {"$I", RTYPE_R5900_I | 0}
2415 #define R5900_Q_NAMES \
2416 {"$Q", RTYPE_R5900_Q | 0}
2418 #define R5900_R_NAMES \
2419 {"$R", RTYPE_R5900_R | 0}
2421 #define R5900_ACC_NAMES \
2422 {"$ACC", RTYPE_R5900_ACC | 0 }
2424 #define MIPS_DSP_ACCUMULATOR_NAMES \
2425 {"$ac0", RTYPE_ACC | 0}, \
2426 {"$ac1", RTYPE_ACC | 1}, \
2427 {"$ac2", RTYPE_ACC | 2}, \
2428 {"$ac3", RTYPE_ACC | 3}
2430 static const struct regname reg_names
[] = {
2431 GENERIC_REGISTER_NUMBERS
,
2433 FPU_CONDITION_CODE_NAMES
,
2434 COPROC_CONDITION_CODE_NAMES
,
2436 /* The $txx registers depends on the abi,
2437 these will be added later into the symbol table from
2438 one of the tables below once mips_abi is set after
2439 parsing of arguments from the command line. */
2440 SYMBOLIC_REGISTER_NAMES
,
2442 MIPS16_SPECIAL_REGISTER_NAMES
,
2443 MDMX_VECTOR_REGISTER_NAMES
,
2448 MIPS_DSP_ACCUMULATOR_NAMES
,
2452 static const struct regname reg_names_o32
[] = {
2453 O32_SYMBOLIC_REGISTER_NAMES
,
2457 static const struct regname reg_names_n32n64
[] = {
2458 N32N64_SYMBOLIC_REGISTER_NAMES
,
2462 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2463 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2464 of these register symbols, return the associated vector register,
2465 otherwise return SYMVAL itself. */
2468 mips_prefer_vec_regno (unsigned int symval
)
2470 if ((symval
& -2) == (RTYPE_GP
| 2))
2471 return RTYPE_VEC
| (symval
& 1);
2475 /* Return true if string [S, E) is a valid register name, storing its
2476 symbol value in *SYMVAL_PTR if so. */
2479 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2484 /* Terminate name. */
2488 /* Look up the name. */
2489 symbol
= symbol_find (s
);
2492 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2495 *symval_ptr
= S_GET_VALUE (symbol
);
2499 /* Return true if the string at *SPTR is a valid register name. Allow it
2500 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2503 When returning true, move *SPTR past the register, store the
2504 register's symbol value in *SYMVAL_PTR and the channel mask in
2505 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2506 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2507 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2510 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2511 unsigned int *channels_ptr
)
2515 unsigned int channels
, symval
, bit
;
2517 /* Find end of name. */
2519 if (is_name_beginner (*e
))
2521 while (is_part_of_name (*e
))
2525 if (!mips_parse_register_1 (s
, e
, &symval
))
2530 /* Eat characters from the end of the string that are valid
2531 channel suffixes. The preceding register must be $ACC or
2532 end with a digit, so there is no ambiguity. */
2535 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2536 if (m
> s
&& m
[-1] == *q
)
2543 || !mips_parse_register_1 (s
, m
, &symval
)
2544 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2549 *symval_ptr
= symval
;
2551 *channels_ptr
= channels
;
2555 /* Check if SPTR points at a valid register specifier according to TYPES.
2556 If so, then return 1, advance S to consume the specifier and store
2557 the register's number in REGNOP, otherwise return 0. */
2560 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2564 if (mips_parse_register (s
, ®no
, NULL
))
2566 if (types
& RTYPE_VEC
)
2567 regno
= mips_prefer_vec_regno (regno
);
2576 as_warn (_("Unrecognized register name `%s'"), *s
);
2581 return regno
<= RNUM_MASK
;
2584 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2585 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2588 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2593 for (i
= 0; i
< 4; i
++)
2594 if (*s
== "xyzw"[i
])
2596 *channels
|= 1 << (3 - i
);
2602 /* Token types for parsed operand lists. */
2603 enum mips_operand_token_type
{
2604 /* A plain register, e.g. $f2. */
2607 /* A 4-bit XYZW channel mask. */
2610 /* An element of a vector, e.g. $v0[1]. */
2613 /* A continuous range of registers, e.g. $s0-$s4. */
2616 /* A (possibly relocated) expression. */
2619 /* A floating-point value. */
2622 /* A single character. This can be '(', ')' or ',', but '(' only appears
2626 /* A doubled character, either "--" or "++". */
2629 /* The end of the operand list. */
2633 /* A parsed operand token. */
2634 struct mips_operand_token
2636 /* The type of token. */
2637 enum mips_operand_token_type type
;
2640 /* The register symbol value for an OT_REG. */
2643 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2644 unsigned int channels
;
2646 /* The register symbol value and index for an OT_REG_ELEMENT. */
2652 /* The two register symbol values involved in an OT_REG_RANGE. */
2654 unsigned int regno1
;
2655 unsigned int regno2
;
2658 /* The value of an OT_INTEGER. The value is represented as an
2659 expression and the relocation operators that were applied to
2660 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2661 relocation operators were used. */
2664 bfd_reloc_code_real_type relocs
[3];
2667 /* The binary data for an OT_FLOAT constant, and the number of bytes
2670 unsigned char data
[8];
2674 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2679 /* An obstack used to construct lists of mips_operand_tokens. */
2680 static struct obstack mips_operand_tokens
;
2682 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2685 mips_add_token (struct mips_operand_token
*token
,
2686 enum mips_operand_token_type type
)
2689 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2692 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2693 and OT_REG tokens for them if so, and return a pointer to the first
2694 unconsumed character. Return null otherwise. */
2697 mips_parse_base_start (char *s
)
2699 struct mips_operand_token token
;
2700 unsigned int regno
, channels
;
2701 bfd_boolean decrement_p
;
2707 SKIP_SPACE_TABS (s
);
2709 /* Only match "--" as part of a base expression. In other contexts "--X"
2710 is a double negative. */
2711 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2715 SKIP_SPACE_TABS (s
);
2718 /* Allow a channel specifier because that leads to better error messages
2719 than treating something like "$vf0x++" as an expression. */
2720 if (!mips_parse_register (&s
, ®no
, &channels
))
2724 mips_add_token (&token
, OT_CHAR
);
2729 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2732 token
.u
.regno
= regno
;
2733 mips_add_token (&token
, OT_REG
);
2737 token
.u
.channels
= channels
;
2738 mips_add_token (&token
, OT_CHANNELS
);
2741 /* For consistency, only match "++" as part of base expressions too. */
2742 SKIP_SPACE_TABS (s
);
2743 if (s
[0] == '+' && s
[1] == '+')
2747 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2753 /* Parse one or more tokens from S. Return a pointer to the first
2754 unconsumed character on success. Return null if an error was found
2755 and store the error text in insn_error. FLOAT_FORMAT is as for
2756 mips_parse_arguments. */
2759 mips_parse_argument_token (char *s
, char float_format
)
2761 char *end
, *save_in
, *err
;
2762 unsigned int regno1
, regno2
, channels
;
2763 struct mips_operand_token token
;
2765 /* First look for "($reg", since we want to treat that as an
2766 OT_CHAR and OT_REG rather than an expression. */
2767 end
= mips_parse_base_start (s
);
2771 /* Handle other characters that end up as OT_CHARs. */
2772 if (*s
== ')' || *s
== ',')
2775 mips_add_token (&token
, OT_CHAR
);
2780 /* Handle tokens that start with a register. */
2781 if (mips_parse_register (&s
, ®no1
, &channels
))
2785 /* A register and a VU0 channel suffix. */
2786 token
.u
.regno
= regno1
;
2787 mips_add_token (&token
, OT_REG
);
2789 token
.u
.channels
= channels
;
2790 mips_add_token (&token
, OT_CHANNELS
);
2794 SKIP_SPACE_TABS (s
);
2797 /* A register range. */
2799 SKIP_SPACE_TABS (s
);
2800 if (!mips_parse_register (&s
, ®no2
, NULL
))
2802 insn_error
= _("Invalid register range");
2806 token
.u
.reg_range
.regno1
= regno1
;
2807 token
.u
.reg_range
.regno2
= regno2
;
2808 mips_add_token (&token
, OT_REG_RANGE
);
2813 /* A vector element. */
2814 expressionS element
;
2817 SKIP_SPACE_TABS (s
);
2818 my_getExpression (&element
, s
);
2819 if (element
.X_op
!= O_constant
)
2821 insn_error
= _("Vector element must be constant");
2825 SKIP_SPACE_TABS (s
);
2828 insn_error
= _("Missing `]'");
2833 token
.u
.reg_element
.regno
= regno1
;
2834 token
.u
.reg_element
.index
= element
.X_add_number
;
2835 mips_add_token (&token
, OT_REG_ELEMENT
);
2839 /* Looks like just a plain register. */
2840 token
.u
.regno
= regno1
;
2841 mips_add_token (&token
, OT_REG
);
2847 /* First try to treat expressions as floats. */
2848 save_in
= input_line_pointer
;
2849 input_line_pointer
= s
;
2850 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2851 &token
.u
.flt
.length
);
2852 end
= input_line_pointer
;
2853 input_line_pointer
= save_in
;
2861 mips_add_token (&token
, OT_FLOAT
);
2866 /* Treat everything else as an integer expression. */
2867 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
2868 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
2869 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
2870 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
2872 mips_add_token (&token
, OT_INTEGER
);
2876 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
2877 if expressions should be treated as 32-bit floating-point constants,
2878 'd' if they should be treated as 64-bit floating-point constants,
2879 or 0 if they should be treated as integer expressions (the usual case).
2881 Return a list of tokens on success, otherwise return 0. The caller
2882 must obstack_free the list after use. */
2884 static struct mips_operand_token
*
2885 mips_parse_arguments (char *s
, char float_format
)
2887 struct mips_operand_token token
;
2889 SKIP_SPACE_TABS (s
);
2892 s
= mips_parse_argument_token (s
, float_format
);
2895 obstack_free (&mips_operand_tokens
,
2896 obstack_finish (&mips_operand_tokens
));
2899 SKIP_SPACE_TABS (s
);
2901 mips_add_token (&token
, OT_END
);
2902 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
2905 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2906 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2909 is_opcode_valid (const struct mips_opcode
*mo
)
2911 int isa
= mips_opts
.isa
;
2912 int ase
= mips_opts
.ase
;
2916 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2917 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2918 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2919 ase
|= mips_ases
[i
].flags64
;
2921 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2924 /* Check whether the instruction or macro requires single-precision or
2925 double-precision floating-point support. Note that this information is
2926 stored differently in the opcode table for insns and macros. */
2927 if (mo
->pinfo
== INSN_MACRO
)
2929 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2930 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2934 fp_s
= mo
->pinfo
& FP_S
;
2935 fp_d
= mo
->pinfo
& FP_D
;
2938 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2941 if (fp_s
&& mips_opts
.soft_float
)
2947 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2948 selected ISA and architecture. */
2951 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2953 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2956 /* Return TRUE if the size of the microMIPS opcode MO matches one
2957 explicitly requested. Always TRUE in the standard MIPS mode. */
2960 is_size_valid (const struct mips_opcode
*mo
)
2962 if (!mips_opts
.micromips
)
2965 if (mips_opts
.insn32
)
2967 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2969 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2972 if (!forced_insn_length
)
2974 if (mo
->pinfo
== INSN_MACRO
)
2976 return forced_insn_length
== micromips_insn_length (mo
);
2979 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2980 of the preceding instruction. Always TRUE in the standard MIPS mode.
2982 We don't accept macros in 16-bit delay slots to avoid a case where
2983 a macro expansion fails because it relies on a preceding 32-bit real
2984 instruction to have matched and does not handle the operands correctly.
2985 The only macros that may expand to 16-bit instructions are JAL that
2986 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2987 and BGT (that likewise cannot be placed in a delay slot) that decay to
2988 a NOP. In all these cases the macros precede any corresponding real
2989 instruction definitions in the opcode table, so they will match in the
2990 second pass where the size of the delay slot is ignored and therefore
2991 produce correct code. */
2994 is_delay_slot_valid (const struct mips_opcode
*mo
)
2996 if (!mips_opts
.micromips
)
2999 if (mo
->pinfo
== INSN_MACRO
)
3000 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3001 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3002 && micromips_insn_length (mo
) != 4)
3004 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3005 && micromips_insn_length (mo
) != 2)
3011 /* For consistency checking, verify that all bits of OPCODE are specified
3012 either by the match/mask part of the instruction definition, or by the
3013 operand list. Also build up a list of operands in OPERANDS.
3015 INSN_BITS says which bits of the instruction are significant.
3016 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3017 provides the mips_operand description of each operand. DECODE_OPERAND
3018 is null for MIPS16 instructions. */
3021 validate_mips_insn (const struct mips_opcode
*opcode
,
3022 unsigned long insn_bits
,
3023 const struct mips_operand
*(*decode_operand
) (const char *),
3024 struct mips_operand_array
*operands
)
3027 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3028 const struct mips_operand
*operand
;
3030 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3031 if ((mask
& opcode
->match
) != opcode
->match
)
3033 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3034 opcode
->name
, opcode
->args
);
3039 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3040 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3041 for (s
= opcode
->args
; *s
; ++s
)
3054 if (!decode_operand
)
3055 operand
= decode_mips16_operand (*s
, FALSE
);
3057 operand
= decode_operand (s
);
3058 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3060 as_bad (_("internal: unknown operand type: %s %s"),
3061 opcode
->name
, opcode
->args
);
3064 gas_assert (opno
< MAX_OPERANDS
);
3065 operands
->operand
[opno
] = operand
;
3066 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3068 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3069 if (operand
->type
== OP_MDMX_IMM_REG
)
3070 /* Bit 5 is the format selector (OB vs QH). The opcode table
3071 has separate entries for each format. */
3072 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3073 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3074 used_bits
&= ~(mask
& 0x700);
3076 /* Skip prefix characters. */
3077 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3082 doubled
= used_bits
& mask
& insn_bits
;
3085 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3086 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3090 undefined
= ~used_bits
& insn_bits
;
3091 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3093 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3094 undefined
, opcode
->name
, opcode
->args
);
3097 used_bits
&= ~insn_bits
;
3100 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3101 used_bits
, opcode
->name
, opcode
->args
);
3107 /* The MIPS16 version of validate_mips_insn. */
3110 validate_mips16_insn (const struct mips_opcode
*opcode
,
3111 struct mips_operand_array
*operands
)
3113 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3115 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3116 instruction. Use TMP to describe the full instruction. */
3117 struct mips_opcode tmp
;
3122 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3124 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3127 /* The microMIPS version of validate_mips_insn. */
3130 validate_micromips_insn (const struct mips_opcode
*opc
,
3131 struct mips_operand_array
*operands
)
3133 unsigned long insn_bits
;
3134 unsigned long major
;
3135 unsigned int length
;
3137 if (opc
->pinfo
== INSN_MACRO
)
3138 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3141 length
= micromips_insn_length (opc
);
3142 if (length
!= 2 && length
!= 4)
3144 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3145 "%s %s"), length
, opc
->name
, opc
->args
);
3148 major
= opc
->match
>> (10 + 8 * (length
- 2));
3149 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3150 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3152 as_bad (_("Internal error: bad microMIPS opcode "
3153 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3157 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3158 insn_bits
= 1 << 4 * length
;
3159 insn_bits
<<= 4 * length
;
3161 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3165 /* This function is called once, at assembler startup time. It should set up
3166 all the tables, etc. that the MD part of the assembler will need. */
3171 const char *retval
= NULL
;
3175 if (mips_pic
!= NO_PIC
)
3177 if (g_switch_seen
&& g_switch_value
!= 0)
3178 as_bad (_("-G may not be used in position-independent code"));
3182 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3183 as_warn (_("Could not set architecture and machine"));
3185 op_hash
= hash_new ();
3187 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3188 for (i
= 0; i
< NUMOPCODES
;)
3190 const char *name
= mips_opcodes
[i
].name
;
3192 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3195 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3196 mips_opcodes
[i
].name
, retval
);
3197 /* Probably a memory allocation problem? Give up now. */
3198 as_fatal (_("Broken assembler. No assembly attempted."));
3202 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3203 decode_mips_operand
, &mips_operands
[i
]))
3205 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3207 create_insn (&nop_insn
, mips_opcodes
+ i
);
3208 if (mips_fix_loongson2f_nop
)
3209 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3210 nop_insn
.fixed_p
= 1;
3214 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3217 mips16_op_hash
= hash_new ();
3218 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3219 bfd_mips16_num_opcodes
);
3222 while (i
< bfd_mips16_num_opcodes
)
3224 const char *name
= mips16_opcodes
[i
].name
;
3226 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3228 as_fatal (_("internal: can't hash `%s': %s"),
3229 mips16_opcodes
[i
].name
, retval
);
3232 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3234 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3236 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3237 mips16_nop_insn
.fixed_p
= 1;
3241 while (i
< bfd_mips16_num_opcodes
3242 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3245 micromips_op_hash
= hash_new ();
3246 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3247 bfd_micromips_num_opcodes
);
3250 while (i
< bfd_micromips_num_opcodes
)
3252 const char *name
= micromips_opcodes
[i
].name
;
3254 retval
= hash_insert (micromips_op_hash
, name
,
3255 (void *) µmips_opcodes
[i
]);
3257 as_fatal (_("internal: can't hash `%s': %s"),
3258 micromips_opcodes
[i
].name
, retval
);
3261 struct mips_cl_insn
*micromips_nop_insn
;
3263 if (!validate_micromips_insn (µmips_opcodes
[i
],
3264 µmips_operands
[i
]))
3267 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3269 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3270 micromips_nop_insn
= µmips_nop16_insn
;
3271 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3272 micromips_nop_insn
= µmips_nop32_insn
;
3276 if (micromips_nop_insn
->insn_mo
== NULL
3277 && strcmp (name
, "nop") == 0)
3279 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3280 micromips_nop_insn
->fixed_p
= 1;
3284 while (++i
< bfd_micromips_num_opcodes
3285 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3289 as_fatal (_("Broken assembler. No assembly attempted."));
3291 /* We add all the general register names to the symbol table. This
3292 helps us detect invalid uses of them. */
3293 for (i
= 0; reg_names
[i
].name
; i
++)
3294 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3295 reg_names
[i
].num
, /* & RNUM_MASK, */
3296 &zero_address_frag
));
3298 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3299 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3300 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3301 &zero_address_frag
));
3303 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3304 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3305 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3306 &zero_address_frag
));
3308 for (i
= 0; i
< 32; i
++)
3312 /* R5900 VU0 floating-point register. */
3313 regname
[sizeof (rename
) - 1] = 0;
3314 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3315 symbol_table_insert (symbol_new (regname
, reg_section
,
3316 RTYPE_VF
| i
, &zero_address_frag
));
3318 /* R5900 VU0 integer register. */
3319 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3320 symbol_table_insert (symbol_new (regname
, reg_section
,
3321 RTYPE_VI
| i
, &zero_address_frag
));
3325 obstack_init (&mips_operand_tokens
);
3327 mips_no_prev_insn ();
3330 mips_cprmask
[0] = 0;
3331 mips_cprmask
[1] = 0;
3332 mips_cprmask
[2] = 0;
3333 mips_cprmask
[3] = 0;
3335 /* set the default alignment for the text section (2**2) */
3336 record_alignment (text_section
, 2);
3338 bfd_set_gp_size (stdoutput
, g_switch_value
);
3340 /* On a native system other than VxWorks, sections must be aligned
3341 to 16 byte boundaries. When configured for an embedded ELF
3342 target, we don't bother. */
3343 if (strncmp (TARGET_OS
, "elf", 3) != 0
3344 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3346 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3347 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3348 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3351 /* Create a .reginfo section for register masks and a .mdebug
3352 section for debugging information. */
3360 subseg
= now_subseg
;
3362 /* The ABI says this section should be loaded so that the
3363 running program can access it. However, we don't load it
3364 if we are configured for an embedded target */
3365 flags
= SEC_READONLY
| SEC_DATA
;
3366 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3367 flags
|= SEC_ALLOC
| SEC_LOAD
;
3369 if (mips_abi
!= N64_ABI
)
3371 sec
= subseg_new (".reginfo", (subsegT
) 0);
3373 bfd_set_section_flags (stdoutput
, sec
, flags
);
3374 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3376 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3380 /* The 64-bit ABI uses a .MIPS.options section rather than
3381 .reginfo section. */
3382 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3383 bfd_set_section_flags (stdoutput
, sec
, flags
);
3384 bfd_set_section_alignment (stdoutput
, sec
, 3);
3386 /* Set up the option header. */
3388 Elf_Internal_Options opthdr
;
3391 opthdr
.kind
= ODK_REGINFO
;
3392 opthdr
.size
= (sizeof (Elf_External_Options
)
3393 + sizeof (Elf64_External_RegInfo
));
3396 f
= frag_more (sizeof (Elf_External_Options
));
3397 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3398 (Elf_External_Options
*) f
);
3400 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3404 if (ECOFF_DEBUGGING
)
3406 sec
= subseg_new (".mdebug", (subsegT
) 0);
3407 (void) bfd_set_section_flags (stdoutput
, sec
,
3408 SEC_HAS_CONTENTS
| SEC_READONLY
);
3409 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3411 else if (mips_flag_pdr
)
3413 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3414 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3415 SEC_READONLY
| SEC_RELOC
3417 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3420 subseg_set (seg
, subseg
);
3423 if (! ECOFF_DEBUGGING
)
3426 if (mips_fix_vr4120
)
3427 init_vr4120_conflicts ();
3433 mips_emit_delays ();
3434 if (! ECOFF_DEBUGGING
)
3439 md_assemble (char *str
)
3441 struct mips_cl_insn insn
;
3442 bfd_reloc_code_real_type unused_reloc
[3]
3443 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3445 imm_expr
.X_op
= O_absent
;
3446 imm2_expr
.X_op
= O_absent
;
3447 offset_expr
.X_op
= O_absent
;
3448 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3449 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3450 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3452 mips_mark_labels ();
3453 mips_assembling_insn
= TRUE
;
3455 if (mips_opts
.mips16
)
3456 mips16_ip (str
, &insn
);
3459 mips_ip (str
, &insn
);
3460 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3461 str
, insn
.insn_opcode
));
3465 as_bad ("%s `%s'", insn_error
, str
);
3466 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3469 if (mips_opts
.mips16
)
3470 mips16_macro (&insn
);
3477 if (offset_expr
.X_op
!= O_absent
)
3478 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3480 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3483 mips_assembling_insn
= FALSE
;
3486 /* Convenience functions for abstracting away the differences between
3487 MIPS16 and non-MIPS16 relocations. */
3489 static inline bfd_boolean
3490 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3494 case BFD_RELOC_MIPS16_JMP
:
3495 case BFD_RELOC_MIPS16_GPREL
:
3496 case BFD_RELOC_MIPS16_GOT16
:
3497 case BFD_RELOC_MIPS16_CALL16
:
3498 case BFD_RELOC_MIPS16_HI16_S
:
3499 case BFD_RELOC_MIPS16_HI16
:
3500 case BFD_RELOC_MIPS16_LO16
:
3508 static inline bfd_boolean
3509 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3513 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3514 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3515 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3516 case BFD_RELOC_MICROMIPS_GPREL16
:
3517 case BFD_RELOC_MICROMIPS_JMP
:
3518 case BFD_RELOC_MICROMIPS_HI16
:
3519 case BFD_RELOC_MICROMIPS_HI16_S
:
3520 case BFD_RELOC_MICROMIPS_LO16
:
3521 case BFD_RELOC_MICROMIPS_LITERAL
:
3522 case BFD_RELOC_MICROMIPS_GOT16
:
3523 case BFD_RELOC_MICROMIPS_CALL16
:
3524 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3525 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3526 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3527 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3528 case BFD_RELOC_MICROMIPS_SUB
:
3529 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3530 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3531 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3532 case BFD_RELOC_MICROMIPS_HIGHEST
:
3533 case BFD_RELOC_MICROMIPS_HIGHER
:
3534 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3535 case BFD_RELOC_MICROMIPS_JALR
:
3543 static inline bfd_boolean
3544 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3546 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3549 static inline bfd_boolean
3550 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3552 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3553 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3556 static inline bfd_boolean
3557 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3559 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3560 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3563 static inline bfd_boolean
3564 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3566 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3567 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3570 static inline bfd_boolean
3571 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3573 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3576 static inline bfd_boolean
3577 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3579 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3580 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3583 /* Return true if RELOC is a PC-relative relocation that does not have
3584 full address range. */
3586 static inline bfd_boolean
3587 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3591 case BFD_RELOC_16_PCREL_S2
:
3592 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3593 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3594 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3597 case BFD_RELOC_32_PCREL
:
3598 return HAVE_64BIT_ADDRESSES
;
3605 /* Return true if the given relocation might need a matching %lo().
3606 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3607 need a matching %lo() when applied to local symbols. */
3609 static inline bfd_boolean
3610 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3612 return (HAVE_IN_PLACE_ADDENDS
3613 && (hi16_reloc_p (reloc
)
3614 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3615 all GOT16 relocations evaluate to "G". */
3616 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3619 /* Return the type of %lo() reloc needed by RELOC, given that
3620 reloc_needs_lo_p. */
3622 static inline bfd_reloc_code_real_type
3623 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3625 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3626 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3630 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3633 static inline bfd_boolean
3634 fixup_has_matching_lo_p (fixS
*fixp
)
3636 return (fixp
->fx_next
!= NULL
3637 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3638 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3639 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3642 /* Move all labels in LABELS to the current insertion point. TEXT_P
3643 says whether the labels refer to text or data. */
3646 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3648 struct insn_label_list
*l
;
3651 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3653 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3654 symbol_set_frag (l
->label
, frag_now
);
3655 val
= (valueT
) frag_now_fix ();
3656 /* MIPS16/microMIPS text labels are stored as odd. */
3657 if (text_p
&& HAVE_CODE_COMPRESSION
)
3659 S_SET_VALUE (l
->label
, val
);
3663 /* Move all labels in insn_labels to the current insertion point
3664 and treat them as text labels. */
3667 mips_move_text_labels (void)
3669 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3673 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3675 bfd_boolean linkonce
= FALSE
;
3676 segT symseg
= S_GET_SEGMENT (sym
);
3678 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3680 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3682 /* The GNU toolchain uses an extension for ELF: a section
3683 beginning with the magic string .gnu.linkonce is a
3684 linkonce section. */
3685 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3686 sizeof ".gnu.linkonce" - 1) == 0)
3692 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3693 linker to handle them specially, such as generating jalx instructions
3694 when needed. We also make them odd for the duration of the assembly,
3695 in order to generate the right sort of code. We will make them even
3696 in the adjust_symtab routine, while leaving them marked. This is
3697 convenient for the debugger and the disassembler. The linker knows
3698 to make them odd again. */
3701 mips_compressed_mark_label (symbolS
*label
)
3703 gas_assert (HAVE_CODE_COMPRESSION
);
3705 if (mips_opts
.mips16
)
3706 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3708 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3709 if ((S_GET_VALUE (label
) & 1) == 0
3710 /* Don't adjust the address if the label is global or weak, or
3711 in a link-once section, since we'll be emitting symbol reloc
3712 references to it which will be patched up by the linker, and
3713 the final value of the symbol may or may not be MIPS16/microMIPS. */
3714 && !S_IS_WEAK (label
)
3715 && !S_IS_EXTERNAL (label
)
3716 && !s_is_linkonce (label
, now_seg
))
3717 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3720 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3723 mips_compressed_mark_labels (void)
3725 struct insn_label_list
*l
;
3727 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3728 mips_compressed_mark_label (l
->label
);
3731 /* End the current frag. Make it a variant frag and record the
3735 relax_close_frag (void)
3737 mips_macro_warning
.first_frag
= frag_now
;
3738 frag_var (rs_machine_dependent
, 0, 0,
3739 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3740 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3742 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3743 mips_relax
.first_fixup
= 0;
3746 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3747 See the comment above RELAX_ENCODE for more details. */
3750 relax_start (symbolS
*symbol
)
3752 gas_assert (mips_relax
.sequence
== 0);
3753 mips_relax
.sequence
= 1;
3754 mips_relax
.symbol
= symbol
;
3757 /* Start generating the second version of a relaxable sequence.
3758 See the comment above RELAX_ENCODE for more details. */
3763 gas_assert (mips_relax
.sequence
== 1);
3764 mips_relax
.sequence
= 2;
3767 /* End the current relaxable sequence. */
3772 gas_assert (mips_relax
.sequence
== 2);
3773 relax_close_frag ();
3774 mips_relax
.sequence
= 0;
3777 /* Return true if IP is a delayed branch or jump. */
3779 static inline bfd_boolean
3780 delayed_branch_p (const struct mips_cl_insn
*ip
)
3782 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3783 | INSN_COND_BRANCH_DELAY
3784 | INSN_COND_BRANCH_LIKELY
)) != 0;
3787 /* Return true if IP is a compact branch or jump. */
3789 static inline bfd_boolean
3790 compact_branch_p (const struct mips_cl_insn
*ip
)
3792 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3793 | INSN2_COND_BRANCH
)) != 0;
3796 /* Return true if IP is an unconditional branch or jump. */
3798 static inline bfd_boolean
3799 uncond_branch_p (const struct mips_cl_insn
*ip
)
3801 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3802 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3805 /* Return true if IP is a branch-likely instruction. */
3807 static inline bfd_boolean
3808 branch_likely_p (const struct mips_cl_insn
*ip
)
3810 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3813 /* Return the type of nop that should be used to fill the delay slot
3814 of delayed branch IP. */
3816 static struct mips_cl_insn
*
3817 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3819 if (mips_opts
.micromips
3820 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3821 return µmips_nop32_insn
;
3825 /* Return a mask that has bit N set if OPCODE reads the register(s)
3829 insn_read_mask (const struct mips_opcode
*opcode
)
3831 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3834 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3838 insn_write_mask (const struct mips_opcode
*opcode
)
3840 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3843 /* Return a mask of the registers specified by operand OPERAND of INSN.
3844 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3848 operand_reg_mask (const struct mips_cl_insn
*insn
,
3849 const struct mips_operand
*operand
,
3850 unsigned int type_mask
)
3852 unsigned int uval
, vsel
;
3854 switch (operand
->type
)
3861 case OP_ADDIUSP_INT
:
3862 case OP_ENTRY_EXIT_LIST
:
3863 case OP_REPEAT_DEST_REG
:
3864 case OP_REPEAT_PREV_REG
:
3867 case OP_VU0_MATCH_SUFFIX
:
3872 const struct mips_reg_operand
*reg_op
;
3874 reg_op
= (const struct mips_reg_operand
*) operand
;
3875 if (!(type_mask
& (1 << reg_op
->reg_type
)))
3877 uval
= insn_extract_operand (insn
, operand
);
3878 return 1 << mips_decode_reg_operand (reg_op
, uval
);
3883 const struct mips_reg_pair_operand
*pair_op
;
3885 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
3886 if (!(type_mask
& (1 << pair_op
->reg_type
)))
3888 uval
= insn_extract_operand (insn
, operand
);
3889 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
3892 case OP_CLO_CLZ_DEST
:
3893 if (!(type_mask
& (1 << OP_REG_GP
)))
3895 uval
= insn_extract_operand (insn
, operand
);
3896 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
3898 case OP_LWM_SWM_LIST
:
3901 case OP_SAVE_RESTORE_LIST
:
3904 case OP_MDMX_IMM_REG
:
3905 if (!(type_mask
& (1 << OP_REG_VEC
)))
3907 uval
= insn_extract_operand (insn
, operand
);
3909 if ((vsel
& 0x18) == 0x18)
3911 return 1 << (uval
& 31);
3916 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
3917 where bit N of OPNO_MASK is set if operand N should be included.
3918 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3922 insn_reg_mask (const struct mips_cl_insn
*insn
,
3923 unsigned int type_mask
, unsigned int opno_mask
)
3925 unsigned int opno
, reg_mask
;
3929 while (opno_mask
!= 0)
3932 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
3939 /* Return the mask of core registers that IP reads. */
3942 gpr_read_mask (const struct mips_cl_insn
*ip
)
3944 unsigned long pinfo
, pinfo2
;
3947 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
3948 pinfo
= ip
->insn_mo
->pinfo
;
3949 pinfo2
= ip
->insn_mo
->pinfo2
;
3950 if (pinfo
& INSN_UDI
)
3952 /* UDI instructions have traditionally been assumed to read RS
3954 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3955 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3957 if (pinfo
& INSN_READ_GPR_24
)
3959 if (pinfo2
& INSN2_READ_GPR_16
)
3961 if (pinfo2
& INSN2_READ_SP
)
3963 if (pinfo2
& INSN2_READ_GPR_31
)
3965 /* Don't include register 0. */
3969 /* Return the mask of core registers that IP writes. */
3972 gpr_write_mask (const struct mips_cl_insn
*ip
)
3974 unsigned long pinfo
, pinfo2
;
3977 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
3978 pinfo
= ip
->insn_mo
->pinfo
;
3979 pinfo2
= ip
->insn_mo
->pinfo2
;
3980 if (pinfo
& INSN_WRITE_GPR_24
)
3982 if (pinfo
& INSN_WRITE_GPR_31
)
3984 if (pinfo
& INSN_UDI
)
3985 /* UDI instructions have traditionally been assumed to write to RD. */
3986 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3987 if (pinfo2
& INSN2_WRITE_SP
)
3989 /* Don't include register 0. */
3993 /* Return the mask of floating-point registers that IP reads. */
3996 fpr_read_mask (const struct mips_cl_insn
*ip
)
3998 unsigned long pinfo
;
4001 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4002 insn_read_mask (ip
->insn_mo
));
4003 pinfo
= ip
->insn_mo
->pinfo
;
4004 /* Conservatively treat all operands to an FP_D instruction are doubles.
4005 (This is overly pessimistic for things like cvt.d.s.) */
4006 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4011 /* Return the mask of floating-point registers that IP writes. */
4014 fpr_write_mask (const struct mips_cl_insn
*ip
)
4016 unsigned long pinfo
;
4019 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4020 insn_write_mask (ip
->insn_mo
));
4021 pinfo
= ip
->insn_mo
->pinfo
;
4022 /* Conservatively treat all operands to an FP_D instruction are doubles.
4023 (This is overly pessimistic for things like cvt.s.d.) */
4024 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4029 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4030 Check whether that is allowed. */
4033 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4035 const char *s
= insn
->name
;
4037 if (insn
->pinfo
== INSN_MACRO
)
4038 /* Let a macro pass, we'll catch it later when it is expanded. */
4041 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4043 /* Allow odd registers for single-precision ops. */
4044 switch (insn
->pinfo
& (FP_S
| FP_D
))
4055 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4056 s
= strchr (insn
->name
, '.');
4057 if (s
!= NULL
&& opnum
== 2)
4058 s
= strchr (s
+ 1, '.');
4059 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4062 /* Single-precision coprocessor loads and moves are OK too. */
4063 if ((insn
->pinfo
& FP_S
)
4064 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4065 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4071 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4072 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4073 this operand is normally printed in hex or decimal. */
4076 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
4077 offsetT val
, int min_val
, int max_val
,
4078 bfd_boolean print_hex
)
4080 if (print_hex
&& val
>= 0)
4081 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4083 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4085 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4087 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4089 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4091 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4094 /* Report an invalid combination of position and size operands for a bitfield
4095 operation. POS and SIZE are the values that were given. */
4098 report_bad_field (offsetT pos
, offsetT size
)
4100 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4101 (unsigned long) pos
, (unsigned long) size
);
4104 /* Information about an instruction argument that we're trying to match. */
4105 struct mips_arg_info
4107 /* The instruction so far. */
4108 struct mips_cl_insn
*insn
;
4110 /* The first unconsumed operand token. */
4111 struct mips_operand_token
*token
;
4113 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4116 /* The 1-based argument number, for error reporting. This does not
4117 count elided optional registers, etc.. */
4120 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4121 unsigned int last_regno
;
4123 /* If the first operand was an OP_REG, this is the register that it
4124 specified, otherwise it is ILLEGAL_REG. */
4125 unsigned int dest_regno
;
4127 /* The value of the last OP_INT operand. Only used for OP_MSB,
4128 where it gives the lsb position. */
4129 unsigned int last_op_int
;
4131 /* If true, match routines should silently reject invalid arguments.
4132 If false, match routines can accept invalid arguments as long as
4133 they report an appropriate error. They still have the option of
4134 silently rejecting arguments, in which case a generic "Invalid operands"
4135 style of error will be used instead. */
4136 bfd_boolean soft_match
;
4138 /* If true, the OP_INT match routine should treat plain symbolic operands
4139 as if a relocation operator like %lo(...) had been used. This is only
4140 ever true if the operand can be relocated. */
4141 bfd_boolean allow_nonconst
;
4143 /* When true, the OP_INT match routine should allow unsigned N-bit
4144 arguments to be used where a signed N-bit operand is expected. */
4145 bfd_boolean lax_max
;
4147 /* True if a reference to the current AT register was seen. */
4148 bfd_boolean seen_at
;
4151 /* Try to match an OT_CHAR token for character CH. Consume the token
4152 and return true on success, otherwise return false. */
4155 match_char (struct mips_arg_info
*arg
, char ch
)
4157 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4167 /* Try to get an expression from the next tokens in ARG. Consume the
4168 tokens and return true on success, storing the expression value in
4169 VALUE and relocation types in R. */
4172 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4173 bfd_reloc_code_real_type
*r
)
4175 if (arg
->token
->type
== OT_INTEGER
)
4177 *value
= arg
->token
->u
.integer
.value
;
4178 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4183 /* Error-reporting is more consistent if we treat registers as O_register
4184 rather than rejecting them outright. "$1", "($1)" and "(($1))" are
4185 then handled in the same way. */
4186 if (arg
->token
->type
== OT_REG
)
4188 value
->X_add_number
= arg
->token
->u
.regno
;
4191 else if (arg
->token
[0].type
== OT_CHAR
4192 && arg
->token
[0].u
.ch
== '('
4193 && arg
->token
[1].type
== OT_REG
4194 && arg
->token
[2].type
== OT_CHAR
4195 && arg
->token
[2].u
.ch
== ')')
4197 value
->X_add_number
= arg
->token
[1].u
.regno
;
4203 value
->X_op
= O_register
;
4204 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4208 /* Try to get a constant expression from the next tokens in ARG. Consume
4209 the tokens and return return true on success, storing the constant value
4210 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4214 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
, offsetT fallback
)
4217 bfd_reloc_code_real_type r
[3];
4219 if (!match_expression (arg
, &ex
, r
))
4222 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4223 *value
= ex
.X_add_number
;
4226 if (arg
->soft_match
)
4228 as_bad (_("Operand %d of `%s' must be constant"),
4229 arg
->argnum
, arg
->insn
->insn_mo
->name
);
4235 /* Return the RTYPE_* flags for a register operand of type TYPE that
4236 appears in instruction OPCODE. */
4239 convert_reg_type (const struct mips_opcode
*opcode
,
4240 enum mips_reg_operand_type type
)
4245 return RTYPE_NUM
| RTYPE_GP
;
4248 /* Allow vector register names for MDMX if the instruction is a 64-bit
4249 FPR load, store or move (including moves to and from GPRs). */
4250 if ((mips_opts
.ase
& ASE_MDMX
)
4251 && (opcode
->pinfo
& FP_D
)
4252 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4253 | INSN_COPROC_MEMORY_DELAY
4254 | INSN_LOAD_COPROC_DELAY
4255 | INSN_LOAD_MEMORY_DELAY
4256 | INSN_STORE_MEMORY
)))
4257 return RTYPE_FPU
| RTYPE_VEC
;
4261 if (opcode
->pinfo
& (FP_D
| FP_S
))
4262 return RTYPE_CCC
| RTYPE_FCC
;
4266 if (opcode
->membership
& INSN_5400
)
4268 return RTYPE_FPU
| RTYPE_VEC
;
4274 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4275 return RTYPE_NUM
| RTYPE_CP0
;
4282 return RTYPE_NUM
| RTYPE_VI
;
4285 return RTYPE_NUM
| RTYPE_VF
;
4287 case OP_REG_R5900_I
:
4288 return RTYPE_R5900_I
;
4290 case OP_REG_R5900_Q
:
4291 return RTYPE_R5900_Q
;
4293 case OP_REG_R5900_R
:
4294 return RTYPE_R5900_R
;
4296 case OP_REG_R5900_ACC
:
4297 return RTYPE_R5900_ACC
;
4302 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4305 check_regno (struct mips_arg_info
*arg
,
4306 enum mips_reg_operand_type type
, unsigned int regno
)
4308 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4309 arg
->seen_at
= TRUE
;
4311 if (type
== OP_REG_FP
4314 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4315 as_warn (_("Float register should be even, was %d"), regno
);
4317 if (type
== OP_REG_CCC
)
4322 name
= arg
->insn
->insn_mo
->name
;
4323 length
= strlen (name
);
4324 if ((regno
& 1) != 0
4325 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4326 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4327 as_warn (_("Condition code register should be even for %s, was %d"),
4330 if ((regno
& 3) != 0
4331 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4332 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4337 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4338 a register of type TYPE. Return true on success, storing the register
4339 number in *REGNO and warning about any dubious uses. */
4342 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4343 unsigned int symval
, unsigned int *regno
)
4345 if (type
== OP_REG_VEC
)
4346 symval
= mips_prefer_vec_regno (symval
);
4347 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4350 *regno
= symval
& RNUM_MASK
;
4351 check_regno (arg
, type
, *regno
);
4355 /* Try to interpret the next token in ARG as a register of type TYPE.
4356 Consume the token and return true on success, storing the register
4357 number in *REGNO. Return false on failure. */
4360 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4361 unsigned int *regno
)
4363 if (arg
->token
->type
== OT_REG
4364 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4372 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4373 Consume the token and return true on success, storing the register numbers
4374 in *REGNO1 and *REGNO2. Return false on failure. */
4377 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4378 unsigned int *regno1
, unsigned int *regno2
)
4380 if (match_reg (arg
, type
, regno1
))
4385 if (arg
->token
->type
== OT_REG_RANGE
4386 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4387 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4388 && *regno1
<= *regno2
)
4396 /* OP_INT matcher. */
4399 match_int_operand (struct mips_arg_info
*arg
,
4400 const struct mips_operand
*operand_base
)
4402 const struct mips_int_operand
*operand
;
4404 int min_val
, max_val
, factor
;
4406 bfd_boolean print_hex
;
4408 operand
= (const struct mips_int_operand
*) operand_base
;
4409 factor
= 1 << operand
->shift
;
4410 min_val
= mips_int_operand_min (operand
);
4411 max_val
= mips_int_operand_max (operand
);
4413 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4415 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4416 /* Assume we have an elided offset. The later match will fail
4417 if this turns out to be wrong. */
4419 else if (operand_base
->lsb
== 0
4420 && operand_base
->size
== 16
4421 && operand
->shift
== 0
4422 && operand
->bias
== 0
4423 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4425 /* The operand can be relocated. */
4426 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4429 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4430 /* Relocation operators were used. Accept the arguent and
4431 leave the relocation value in offset_expr and offset_relocs
4432 for the caller to process. */
4435 if (offset_expr
.X_op
!= O_constant
)
4437 /* If non-constant operands are allowed then leave them for
4438 the caller to process, otherwise fail the match. */
4439 if (!arg
->allow_nonconst
)
4441 offset_reloc
[0] = BFD_RELOC_LO16
;
4445 /* Clear the global state; we're going to install the operand
4447 sval
= offset_expr
.X_add_number
;
4448 offset_expr
.X_op
= O_absent
;
4452 if (!match_const_int (arg
, &sval
, min_val
))
4456 arg
->last_op_int
= sval
;
4458 /* Check the range. If there's a problem, record the lowest acceptable
4459 value in arg->last_op_int in order to prevent an unhelpful error
4462 Bit counts have traditionally been printed in hex by the disassembler
4463 but printed as decimal in error messages. Only resort to hex if
4464 the operand is bigger than 6 bits. */
4465 print_hex
= operand
->print_hex
&& operand_base
->size
> 6;
4466 if (sval
< min_val
|| sval
> max_val
)
4468 if (arg
->soft_match
)
4470 report_bad_range (arg
->insn
, arg
->argnum
, sval
, min_val
, max_val
,
4472 arg
->last_op_int
= min_val
;
4474 else if (sval
% factor
)
4476 if (arg
->soft_match
)
4478 as_bad (print_hex
&& sval
>= 0
4479 ? _("Operand %d of `%s' must be a factor of %d, was 0x%lx.")
4480 : _("Operand %d of `%s' must be a factor of %d, was %ld."),
4481 arg
->argnum
, arg
->insn
->insn_mo
->name
, factor
,
4482 (unsigned long) sval
);
4483 arg
->last_op_int
= min_val
;
4486 uval
= (unsigned int) sval
>> operand
->shift
;
4487 uval
-= operand
->bias
;
4489 /* Handle -mfix-cn63xxp1. */
4491 && mips_fix_cn63xxp1
4492 && !mips_opts
.micromips
4493 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4508 /* The rest must be changed to 28. */
4513 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4517 /* OP_MAPPED_INT matcher. */
4520 match_mapped_int_operand (struct mips_arg_info
*arg
,
4521 const struct mips_operand
*operand_base
)
4523 const struct mips_mapped_int_operand
*operand
;
4524 unsigned int uval
, num_vals
;
4527 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4528 if (!match_const_int (arg
, &sval
, operand
->int_map
[0]))
4531 num_vals
= 1 << operand_base
->size
;
4532 for (uval
= 0; uval
< num_vals
; uval
++)
4533 if (operand
->int_map
[uval
] == sval
)
4535 if (uval
== num_vals
)
4538 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4542 /* OP_MSB matcher. */
4545 match_msb_operand (struct mips_arg_info
*arg
,
4546 const struct mips_operand
*operand_base
)
4548 const struct mips_msb_operand
*operand
;
4549 int min_val
, max_val
, max_high
;
4550 offsetT size
, sval
, high
;
4552 operand
= (const struct mips_msb_operand
*) operand_base
;
4553 min_val
= operand
->bias
;
4554 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4555 max_high
= operand
->opsize
;
4557 if (!match_const_int (arg
, &size
, 1))
4560 high
= size
+ arg
->last_op_int
;
4561 sval
= operand
->add_lsb
? high
: size
;
4563 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4565 if (arg
->soft_match
)
4567 report_bad_field (arg
->last_op_int
, size
);
4570 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4574 /* OP_REG matcher. */
4577 match_reg_operand (struct mips_arg_info
*arg
,
4578 const struct mips_operand
*operand_base
)
4580 const struct mips_reg_operand
*operand
;
4581 unsigned int regno
, uval
, num_vals
;
4583 operand
= (const struct mips_reg_operand
*) operand_base
;
4584 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4587 if (operand
->reg_map
)
4589 num_vals
= 1 << operand
->root
.size
;
4590 for (uval
= 0; uval
< num_vals
; uval
++)
4591 if (operand
->reg_map
[uval
] == regno
)
4593 if (num_vals
== uval
)
4599 arg
->last_regno
= regno
;
4600 if (arg
->opnum
== 1)
4601 arg
->dest_regno
= regno
;
4602 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4606 /* OP_REG_PAIR matcher. */
4609 match_reg_pair_operand (struct mips_arg_info
*arg
,
4610 const struct mips_operand
*operand_base
)
4612 const struct mips_reg_pair_operand
*operand
;
4613 unsigned int regno1
, regno2
, uval
, num_vals
;
4615 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4616 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4617 || !match_char (arg
, ',')
4618 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4621 num_vals
= 1 << operand_base
->size
;
4622 for (uval
= 0; uval
< num_vals
; uval
++)
4623 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4625 if (uval
== num_vals
)
4628 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4632 /* OP_PCREL matcher. The caller chooses the relocation type. */
4635 match_pcrel_operand (struct mips_arg_info
*arg
)
4637 bfd_reloc_code_real_type r
[3];
4639 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4642 /* OP_PERF_REG matcher. */
4645 match_perf_reg_operand (struct mips_arg_info
*arg
,
4646 const struct mips_operand
*operand
)
4650 if (!match_const_int (arg
, &sval
, 0))
4655 || (mips_opts
.arch
== CPU_R5900
4656 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4657 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4659 if (arg
->soft_match
)
4661 as_bad (_("Invalid performance register (%ld)"), (unsigned long) sval
);
4664 insn_insert_operand (arg
->insn
, operand
, sval
);
4668 /* OP_ADDIUSP matcher. */
4671 match_addiusp_operand (struct mips_arg_info
*arg
,
4672 const struct mips_operand
*operand
)
4677 if (!match_const_int (arg
, &sval
, -256))
4684 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4687 uval
= (unsigned int) sval
;
4688 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4689 insn_insert_operand (arg
->insn
, operand
, uval
);
4693 /* OP_CLO_CLZ_DEST matcher. */
4696 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4697 const struct mips_operand
*operand
)
4701 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4704 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4708 /* OP_LWM_SWM_LIST matcher. */
4711 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4712 const struct mips_operand
*operand
)
4714 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4715 struct mips_arg_info reset
;
4718 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4722 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4727 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4730 while (match_char (arg
, ',')
4731 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4734 if (operand
->size
== 2)
4736 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4742 and any permutations of these. */
4743 if ((reglist
& 0xfff1ffff) != 0x80010000)
4746 sregs
= (reglist
>> 17) & 7;
4751 /* The list must include at least one of ra and s0-sN,
4752 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4753 which are $23 and $30 respectively.) E.g.:
4761 and any permutations of these. */
4762 if ((reglist
& 0x3f00ffff) != 0)
4765 ra
= (reglist
>> 27) & 0x10;
4766 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4769 if ((sregs
& -sregs
) != sregs
)
4772 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4776 /* OP_ENTRY_EXIT_LIST matcher. */
4779 match_entry_exit_operand (struct mips_arg_info
*arg
,
4780 const struct mips_operand
*operand
)
4783 bfd_boolean is_exit
;
4785 /* The format is the same for both ENTRY and EXIT, but the constraints
4787 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4788 mask
= (is_exit
? 7 << 3 : 0);
4791 unsigned int regno1
, regno2
;
4792 bfd_boolean is_freg
;
4794 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4796 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4801 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4804 mask
|= (5 + regno2
) << 3;
4806 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4807 mask
|= (regno2
- 3) << 3;
4808 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4809 mask
|= (regno2
- 15) << 1;
4810 else if (regno1
== RA
&& regno2
== RA
)
4815 while (match_char (arg
, ','));
4817 insn_insert_operand (arg
->insn
, operand
, mask
);
4821 /* OP_SAVE_RESTORE_LIST matcher. */
4824 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4826 unsigned int opcode
, args
, statics
, sregs
;
4827 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4832 opcode
= arg
->insn
->insn_opcode
;
4834 num_frame_sizes
= 0;
4840 unsigned int regno1
, regno2
;
4842 if (arg
->token
->type
== OT_INTEGER
)
4844 /* Handle the frame size. */
4845 if (!match_const_int (arg
, &frame_size
, 0))
4847 num_frame_sizes
+= 1;
4851 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4854 while (regno1
<= regno2
)
4856 if (regno1
>= 4 && regno1
<= 7)
4858 if (num_frame_sizes
== 0)
4860 args
|= 1 << (regno1
- 4);
4862 /* statics $a0-$a3 */
4863 statics
|= 1 << (regno1
- 4);
4865 else if (regno1
>= 16 && regno1
<= 23)
4867 sregs
|= 1 << (regno1
- 16);
4868 else if (regno1
== 30)
4871 else if (regno1
== 31)
4872 /* Add $ra to insn. */
4882 while (match_char (arg
, ','));
4884 /* Encode args/statics combination. */
4887 else if (args
== 0xf)
4888 /* All $a0-$a3 are args. */
4889 opcode
|= MIPS16_ALL_ARGS
<< 16;
4890 else if (statics
== 0xf)
4891 /* All $a0-$a3 are statics. */
4892 opcode
|= MIPS16_ALL_STATICS
<< 16;
4895 /* Count arg registers. */
4905 /* Count static registers. */
4907 while (statics
& 0x8)
4909 statics
= (statics
<< 1) & 0xf;
4915 /* Encode args/statics. */
4916 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
4919 /* Encode $s0/$s1. */
4920 if (sregs
& (1 << 0)) /* $s0 */
4922 if (sregs
& (1 << 1)) /* $s1 */
4926 /* Encode $s2-$s8. */
4935 opcode
|= num_sregs
<< 24;
4937 /* Encode frame size. */
4938 if (num_frame_sizes
== 0)
4939 error
= _("Missing frame size");
4940 else if (num_frame_sizes
> 1)
4941 error
= _("Frame size specified twice");
4942 else if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
4943 error
= _("Invalid frame size");
4944 else if (frame_size
!= 128 || (opcode
>> 16) != 0)
4947 opcode
|= (((frame_size
& 0xf0) << 16)
4948 | (frame_size
& 0x0f));
4953 if (arg
->soft_match
)
4955 as_bad ("%s", error
);
4958 /* Finally build the instruction. */
4959 if ((opcode
>> 16) != 0 || frame_size
== 0)
4960 opcode
|= MIPS16_EXTEND
;
4961 arg
->insn
->insn_opcode
= opcode
;
4965 /* OP_MDMX_IMM_REG matcher. */
4968 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
4969 const struct mips_operand
*operand
)
4971 unsigned int regno
, uval
;
4973 const struct mips_opcode
*opcode
;
4975 /* The mips_opcode records whether this is an octobyte or quadhalf
4976 instruction. Start out with that bit in place. */
4977 opcode
= arg
->insn
->insn_mo
;
4978 uval
= mips_extract_operand (operand
, opcode
->match
);
4979 is_qh
= (uval
!= 0);
4981 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
4983 if ((opcode
->membership
& INSN_5400
)
4984 && strcmp (opcode
->name
, "rzu.ob") == 0)
4986 if (arg
->soft_match
)
4988 as_bad (_("Operand %d of `%s' must be an immediate"),
4989 arg
->argnum
, opcode
->name
);
4992 /* Check whether this is a vector register or a broadcast of
4993 a single element. */
4994 if (arg
->token
->type
== OT_REG_ELEMENT
)
4996 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
4999 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
5001 if (arg
->soft_match
)
5003 as_bad (_("Invalid element selector"));
5006 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
5010 /* A full vector. */
5011 if ((opcode
->membership
& INSN_5400
)
5012 && (strcmp (opcode
->name
, "sll.ob") == 0
5013 || strcmp (opcode
->name
, "srl.ob") == 0))
5015 if (arg
->soft_match
)
5017 as_bad (_("Operand %d of `%s' must be scalar"),
5018 arg
->argnum
, opcode
->name
);
5021 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5024 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5026 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5035 if (!match_const_int (arg
, &sval
, 0))
5037 if (sval
< 0 || sval
> 31)
5039 if (arg
->soft_match
)
5041 report_bad_range (arg
->insn
, arg
->argnum
, sval
, 0, 31, FALSE
);
5043 uval
|= (sval
& 31);
5045 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5047 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5049 insn_insert_operand (arg
->insn
, operand
, uval
);
5053 /* OP_PC matcher. */
5056 match_pc_operand (struct mips_arg_info
*arg
)
5058 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5066 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5067 register that we need to match. */
5070 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5074 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5077 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5078 the length of the value in bytes (4 for float, 8 for double) and
5079 USING_GPRS says whether the destination is a GPR rather than an FPR.
5081 Return the constant in IMM and OFFSET as follows:
5083 - If the constant should be loaded via memory, set IMM to O_absent and
5084 OFFSET to the memory address.
5086 - Otherwise, if the constant should be loaded into two 32-bit registers,
5087 set IMM to the O_constant to load into the high register and OFFSET
5088 to the corresponding value for the low register.
5090 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5092 These constants only appear as the last operand in an instruction,
5093 and every instruction that accepts them in any variant accepts them
5094 in all variants. This means we don't have to worry about backing out
5095 any changes if the instruction does not match. We just match
5096 unconditionally and report an error if the constant is invalid. */
5099 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5100 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5105 const char *newname
;
5106 unsigned char *data
;
5108 /* Where the constant is placed is based on how the MIPS assembler
5111 length == 4 && using_gprs -- immediate value only
5112 length == 8 && using_gprs -- .rdata or immediate value
5113 length == 4 && !using_gprs -- .lit4 or immediate value
5114 length == 8 && !using_gprs -- .lit8 or immediate value
5116 The .lit4 and .lit8 sections are only used if permitted by the
5118 if (arg
->token
->type
!= OT_FLOAT
)
5121 gas_assert (arg
->token
->u
.flt
.length
== length
);
5122 data
= arg
->token
->u
.flt
.data
;
5125 /* Handle 32-bit constants for which an immediate value is best. */
5128 || g_switch_value
< 4
5129 || (data
[0] == 0 && data
[1] == 0)
5130 || (data
[2] == 0 && data
[3] == 0)))
5132 imm
->X_op
= O_constant
;
5133 if (!target_big_endian
)
5134 imm
->X_add_number
= bfd_getl32 (data
);
5136 imm
->X_add_number
= bfd_getb32 (data
);
5137 offset
->X_op
= O_absent
;
5141 /* Handle 64-bit constants for which an immediate value is best. */
5143 && !mips_disable_float_construction
5144 /* Constants can only be constructed in GPRs and copied
5145 to FPRs if the GPRs are at least as wide as the FPRs.
5146 Force the constant into memory if we are using 64-bit FPRs
5147 but the GPRs are only 32 bits wide. */
5148 /* ??? No longer true with the addition of MTHC1, but this
5149 is legacy code... */
5150 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5151 && ((data
[0] == 0 && data
[1] == 0)
5152 || (data
[2] == 0 && data
[3] == 0))
5153 && ((data
[4] == 0 && data
[5] == 0)
5154 || (data
[6] == 0 && data
[7] == 0)))
5156 /* The value is simple enough to load with a couple of instructions.
5157 If using 32-bit registers, set IMM to the high order 32 bits and
5158 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5160 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5162 imm
->X_op
= O_constant
;
5163 offset
->X_op
= O_constant
;
5164 if (!target_big_endian
)
5166 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5167 offset
->X_add_number
= bfd_getl32 (data
);
5171 imm
->X_add_number
= bfd_getb32 (data
);
5172 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5174 if (offset
->X_add_number
== 0)
5175 offset
->X_op
= O_absent
;
5179 imm
->X_op
= O_constant
;
5180 if (!target_big_endian
)
5181 imm
->X_add_number
= bfd_getl64 (data
);
5183 imm
->X_add_number
= bfd_getb64 (data
);
5184 offset
->X_op
= O_absent
;
5189 /* Switch to the right section. */
5191 subseg
= now_subseg
;
5194 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5199 if (using_gprs
|| g_switch_value
< 8)
5200 newname
= RDATA_SECTION_NAME
;
5205 new_seg
= subseg_new (newname
, (subsegT
) 0);
5206 bfd_set_section_flags (stdoutput
, new_seg
,
5207 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5208 frag_align (length
== 4 ? 2 : 3, 0, 0);
5209 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5210 record_alignment (new_seg
, 4);
5212 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5214 as_bad (_("Can't use floating point insn in this section"));
5216 /* Set the argument to the current address in the section. */
5217 imm
->X_op
= O_absent
;
5218 offset
->X_op
= O_symbol
;
5219 offset
->X_add_symbol
= symbol_temp_new_now ();
5220 offset
->X_add_number
= 0;
5222 /* Put the floating point number into the section. */
5223 p
= frag_more (length
);
5224 memcpy (p
, data
, length
);
5226 /* Switch back to the original section. */
5227 subseg_set (seg
, subseg
);
5231 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5235 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5236 const struct mips_operand
*operand
,
5237 bfd_boolean match_p
)
5241 /* The operand can be an XYZW mask or a single 2-bit channel index
5242 (with X being 0). */
5243 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5245 /* The suffix can be omitted when it is already part of the opcode. */
5246 if (arg
->token
->type
!= OT_CHANNELS
)
5249 uval
= arg
->token
->u
.channels
;
5250 if (operand
->size
== 2)
5252 /* Check that a single bit is set and convert it into a 2-bit index. */
5253 if ((uval
& -uval
) != uval
)
5255 uval
= 4 - ffs (uval
);
5258 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5263 insn_insert_operand (arg
->insn
, operand
, uval
);
5267 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5268 of the argument text if the match is successful, otherwise return null. */
5271 match_operand (struct mips_arg_info
*arg
,
5272 const struct mips_operand
*operand
)
5274 switch (operand
->type
)
5277 return match_int_operand (arg
, operand
);
5280 return match_mapped_int_operand (arg
, operand
);
5283 return match_msb_operand (arg
, operand
);
5286 return match_reg_operand (arg
, operand
);
5289 return match_reg_pair_operand (arg
, operand
);
5292 return match_pcrel_operand (arg
);
5295 return match_perf_reg_operand (arg
, operand
);
5297 case OP_ADDIUSP_INT
:
5298 return match_addiusp_operand (arg
, operand
);
5300 case OP_CLO_CLZ_DEST
:
5301 return match_clo_clz_dest_operand (arg
, operand
);
5303 case OP_LWM_SWM_LIST
:
5304 return match_lwm_swm_list_operand (arg
, operand
);
5306 case OP_ENTRY_EXIT_LIST
:
5307 return match_entry_exit_operand (arg
, operand
);
5309 case OP_SAVE_RESTORE_LIST
:
5310 return match_save_restore_list_operand (arg
);
5312 case OP_MDMX_IMM_REG
:
5313 return match_mdmx_imm_reg_operand (arg
, operand
);
5315 case OP_REPEAT_DEST_REG
:
5316 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5318 case OP_REPEAT_PREV_REG
:
5319 return match_tied_reg_operand (arg
, arg
->last_regno
);
5322 return match_pc_operand (arg
);
5325 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5327 case OP_VU0_MATCH_SUFFIX
:
5328 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5333 /* ARG is the state after successfully matching an instruction.
5334 Issue any queued-up warnings. */
5337 check_completed_insn (struct mips_arg_info
*arg
)
5342 as_warn (_("Used $at without \".set noat\""));
5344 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5348 /* Return true if modifying general-purpose register REG needs a delay. */
5351 reg_needs_delay (unsigned int reg
)
5353 unsigned long prev_pinfo
;
5355 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5356 if (!mips_opts
.noreorder
5357 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5358 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5359 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5365 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5366 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5367 by VR4120 errata. */
5370 classify_vr4120_insn (const char *name
)
5372 if (strncmp (name
, "macc", 4) == 0)
5373 return FIX_VR4120_MACC
;
5374 if (strncmp (name
, "dmacc", 5) == 0)
5375 return FIX_VR4120_DMACC
;
5376 if (strncmp (name
, "mult", 4) == 0)
5377 return FIX_VR4120_MULT
;
5378 if (strncmp (name
, "dmult", 5) == 0)
5379 return FIX_VR4120_DMULT
;
5380 if (strstr (name
, "div"))
5381 return FIX_VR4120_DIV
;
5382 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5383 return FIX_VR4120_MTHILO
;
5384 return NUM_FIX_VR4120_CLASSES
;
5387 #define INSN_ERET 0x42000018
5388 #define INSN_DERET 0x4200001f
5390 /* Return the number of instructions that must separate INSN1 and INSN2,
5391 where INSN1 is the earlier instruction. Return the worst-case value
5392 for any INSN2 if INSN2 is null. */
5395 insns_between (const struct mips_cl_insn
*insn1
,
5396 const struct mips_cl_insn
*insn2
)
5398 unsigned long pinfo1
, pinfo2
;
5401 /* If INFO2 is null, pessimistically assume that all flags are set for
5402 the second instruction. */
5403 pinfo1
= insn1
->insn_mo
->pinfo
;
5404 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5406 /* For most targets, write-after-read dependencies on the HI and LO
5407 registers must be separated by at least two instructions. */
5408 if (!hilo_interlocks
)
5410 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5412 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5416 /* If we're working around r7000 errata, there must be two instructions
5417 between an mfhi or mflo and any instruction that uses the result. */
5418 if (mips_7000_hilo_fix
5419 && !mips_opts
.micromips
5420 && MF_HILO_INSN (pinfo1
)
5421 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5424 /* If we're working around 24K errata, one instruction is required
5425 if an ERET or DERET is followed by a branch instruction. */
5426 if (mips_fix_24k
&& !mips_opts
.micromips
)
5428 if (insn1
->insn_opcode
== INSN_ERET
5429 || insn1
->insn_opcode
== INSN_DERET
)
5432 || insn2
->insn_opcode
== INSN_ERET
5433 || insn2
->insn_opcode
== INSN_DERET
5434 || delayed_branch_p (insn2
))
5439 /* If working around VR4120 errata, check for combinations that need
5440 a single intervening instruction. */
5441 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5443 unsigned int class1
, class2
;
5445 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5446 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5450 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5451 if (vr4120_conflicts
[class1
] & (1 << class2
))
5456 if (!HAVE_CODE_COMPRESSION
)
5458 /* Check for GPR or coprocessor load delays. All such delays
5459 are on the RT register. */
5460 /* Itbl support may require additional care here. */
5461 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5462 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5464 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5468 /* Check for generic coprocessor hazards.
5470 This case is not handled very well. There is no special
5471 knowledge of CP0 handling, and the coprocessors other than
5472 the floating point unit are not distinguished at all. */
5473 /* Itbl support may require additional care here. FIXME!
5474 Need to modify this to include knowledge about
5475 user specified delays! */
5476 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5477 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5479 /* Handle cases where INSN1 writes to a known general coprocessor
5480 register. There must be a one instruction delay before INSN2
5481 if INSN2 reads that register, otherwise no delay is needed. */
5482 mask
= fpr_write_mask (insn1
);
5485 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5490 /* Read-after-write dependencies on the control registers
5491 require a two-instruction gap. */
5492 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5493 && (pinfo2
& INSN_READ_COND_CODE
))
5496 /* We don't know exactly what INSN1 does. If INSN2 is
5497 also a coprocessor instruction, assume there must be
5498 a one instruction gap. */
5499 if (pinfo2
& INSN_COP
)
5504 /* Check for read-after-write dependencies on the coprocessor
5505 control registers in cases where INSN1 does not need a general
5506 coprocessor delay. This means that INSN1 is a floating point
5507 comparison instruction. */
5508 /* Itbl support may require additional care here. */
5509 else if (!cop_interlocks
5510 && (pinfo1
& INSN_WRITE_COND_CODE
)
5511 && (pinfo2
& INSN_READ_COND_CODE
))
5518 /* Return the number of nops that would be needed to work around the
5519 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5520 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5521 that are contained within the first IGNORE instructions of HIST. */
5524 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5525 const struct mips_cl_insn
*insn
)
5530 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5531 are not affected by the errata. */
5533 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5534 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5535 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5538 /* Search for the first MFLO or MFHI. */
5539 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5540 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5542 /* Extract the destination register. */
5543 mask
= gpr_write_mask (&hist
[i
]);
5545 /* No nops are needed if INSN reads that register. */
5546 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5549 /* ...or if any of the intervening instructions do. */
5550 for (j
= 0; j
< i
; j
++)
5551 if (gpr_read_mask (&hist
[j
]) & mask
)
5555 return MAX_VR4130_NOPS
- i
;
5560 #define BASE_REG_EQ(INSN1, INSN2) \
5561 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5562 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5564 /* Return the minimum alignment for this store instruction. */
5567 fix_24k_align_to (const struct mips_opcode
*mo
)
5569 if (strcmp (mo
->name
, "sh") == 0)
5572 if (strcmp (mo
->name
, "swc1") == 0
5573 || strcmp (mo
->name
, "swc2") == 0
5574 || strcmp (mo
->name
, "sw") == 0
5575 || strcmp (mo
->name
, "sc") == 0
5576 || strcmp (mo
->name
, "s.s") == 0)
5579 if (strcmp (mo
->name
, "sdc1") == 0
5580 || strcmp (mo
->name
, "sdc2") == 0
5581 || strcmp (mo
->name
, "s.d") == 0)
5588 struct fix_24k_store_info
5590 /* Immediate offset, if any, for this store instruction. */
5592 /* Alignment required by this store instruction. */
5594 /* True for register offsets. */
5595 int register_offset
;
5598 /* Comparison function used by qsort. */
5601 fix_24k_sort (const void *a
, const void *b
)
5603 const struct fix_24k_store_info
*pos1
= a
;
5604 const struct fix_24k_store_info
*pos2
= b
;
5606 return (pos1
->off
- pos2
->off
);
5609 /* INSN is a store instruction. Try to record the store information
5610 in STINFO. Return false if the information isn't known. */
5613 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5614 const struct mips_cl_insn
*insn
)
5616 /* The instruction must have a known offset. */
5617 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5620 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5621 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5625 /* Return the number of nops that would be needed to work around the 24k
5626 "lost data on stores during refill" errata if instruction INSN
5627 immediately followed the 2 instructions described by HIST.
5628 Ignore hazards that are contained within the first IGNORE
5629 instructions of HIST.
5631 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5632 for the data cache refills and store data. The following describes
5633 the scenario where the store data could be lost.
5635 * A data cache miss, due to either a load or a store, causing fill
5636 data to be supplied by the memory subsystem
5637 * The first three doublewords of fill data are returned and written
5639 * A sequence of four stores occurs in consecutive cycles around the
5640 final doubleword of the fill:
5644 * Zero, One or more instructions
5647 The four stores A-D must be to different doublewords of the line that
5648 is being filled. The fourth instruction in the sequence above permits
5649 the fill of the final doubleword to be transferred from the FSB into
5650 the cache. In the sequence above, the stores may be either integer
5651 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5652 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5653 different doublewords on the line. If the floating point unit is
5654 running in 1:2 mode, it is not possible to create the sequence above
5655 using only floating point store instructions.
5657 In this case, the cache line being filled is incorrectly marked
5658 invalid, thereby losing the data from any store to the line that
5659 occurs between the original miss and the completion of the five
5660 cycle sequence shown above.
5662 The workarounds are:
5664 * Run the data cache in write-through mode.
5665 * Insert a non-store instruction between
5666 Store A and Store B or Store B and Store C. */
5669 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5670 const struct mips_cl_insn
*insn
)
5672 struct fix_24k_store_info pos
[3];
5673 int align
, i
, base_offset
;
5678 /* If the previous instruction wasn't a store, there's nothing to
5680 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5683 /* If the instructions after the previous one are unknown, we have
5684 to assume the worst. */
5688 /* Check whether we are dealing with three consecutive stores. */
5689 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5690 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5693 /* If we don't know the relationship between the store addresses,
5694 assume the worst. */
5695 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5696 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5699 if (!fix_24k_record_store_info (&pos
[0], insn
)
5700 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5701 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5704 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5706 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5707 X bytes and such that the base register + X is known to be aligned
5710 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5714 align
= pos
[0].align_to
;
5715 base_offset
= pos
[0].off
;
5716 for (i
= 1; i
< 3; i
++)
5717 if (align
< pos
[i
].align_to
)
5719 align
= pos
[i
].align_to
;
5720 base_offset
= pos
[i
].off
;
5722 for (i
= 0; i
< 3; i
++)
5723 pos
[i
].off
-= base_offset
;
5726 pos
[0].off
&= ~align
+ 1;
5727 pos
[1].off
&= ~align
+ 1;
5728 pos
[2].off
&= ~align
+ 1;
5730 /* If any two stores write to the same chunk, they also write to the
5731 same doubleword. The offsets are still sorted at this point. */
5732 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5735 /* A range of at least 9 bytes is needed for the stores to be in
5736 non-overlapping doublewords. */
5737 if (pos
[2].off
- pos
[0].off
<= 8)
5740 if (pos
[2].off
- pos
[1].off
>= 24
5741 || pos
[1].off
- pos
[0].off
>= 24
5742 || pos
[2].off
- pos
[0].off
>= 32)
5748 /* Return the number of nops that would be needed if instruction INSN
5749 immediately followed the MAX_NOPS instructions given by HIST,
5750 where HIST[0] is the most recent instruction. Ignore hazards
5751 between INSN and the first IGNORE instructions in HIST.
5753 If INSN is null, return the worse-case number of nops for any
5757 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5758 const struct mips_cl_insn
*insn
)
5760 int i
, nops
, tmp_nops
;
5763 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5765 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5766 if (tmp_nops
> nops
)
5770 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5772 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5773 if (tmp_nops
> nops
)
5777 if (mips_fix_24k
&& !mips_opts
.micromips
)
5779 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5780 if (tmp_nops
> nops
)
5787 /* The variable arguments provide NUM_INSNS extra instructions that
5788 might be added to HIST. Return the largest number of nops that
5789 would be needed after the extended sequence, ignoring hazards
5790 in the first IGNORE instructions. */
5793 nops_for_sequence (int num_insns
, int ignore
,
5794 const struct mips_cl_insn
*hist
, ...)
5797 struct mips_cl_insn buffer
[MAX_NOPS
];
5798 struct mips_cl_insn
*cursor
;
5801 va_start (args
, hist
);
5802 cursor
= buffer
+ num_insns
;
5803 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5804 while (cursor
> buffer
)
5805 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5807 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5812 /* Like nops_for_insn, but if INSN is a branch, take into account the
5813 worst-case delay for the branch target. */
5816 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5817 const struct mips_cl_insn
*insn
)
5821 nops
= nops_for_insn (ignore
, hist
, insn
);
5822 if (delayed_branch_p (insn
))
5824 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5825 hist
, insn
, get_delay_slot_nop (insn
));
5826 if (tmp_nops
> nops
)
5829 else if (compact_branch_p (insn
))
5831 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5832 if (tmp_nops
> nops
)
5838 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5841 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5843 gas_assert (!HAVE_CODE_COMPRESSION
);
5844 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5845 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5848 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5849 jr target pc &= 'hffff_ffff_cfff_ffff. */
5852 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5854 gas_assert (!HAVE_CODE_COMPRESSION
);
5855 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5856 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5857 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
5865 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
5866 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
5869 ep
.X_op
= O_constant
;
5870 ep
.X_add_number
= 0xcfff0000;
5871 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
5872 ep
.X_add_number
= 0xffff;
5873 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
5874 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
5879 fix_loongson2f (struct mips_cl_insn
* ip
)
5881 if (mips_fix_loongson2f_nop
)
5882 fix_loongson2f_nop (ip
);
5884 if (mips_fix_loongson2f_jump
)
5885 fix_loongson2f_jump (ip
);
5888 /* IP is a branch that has a delay slot, and we need to fill it
5889 automatically. Return true if we can do that by swapping IP
5890 with the previous instruction.
5891 ADDRESS_EXPR is an operand of the instruction to be used with
5895 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
5896 bfd_reloc_code_real_type
*reloc_type
)
5898 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
5899 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
5901 /* -O2 and above is required for this optimization. */
5902 if (mips_optimize
< 2)
5905 /* If we have seen .set volatile or .set nomove, don't optimize. */
5906 if (mips_opts
.nomove
)
5909 /* We can't swap if the previous instruction's position is fixed. */
5910 if (history
[0].fixed_p
)
5913 /* If the previous previous insn was in a .set noreorder, we can't
5914 swap. Actually, the MIPS assembler will swap in this situation.
5915 However, gcc configured -with-gnu-as will generate code like
5923 in which we can not swap the bne and INSN. If gcc is not configured
5924 -with-gnu-as, it does not output the .set pseudo-ops. */
5925 if (history
[1].noreorder_p
)
5928 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
5929 This means that the previous instruction was a 4-byte one anyhow. */
5930 if (mips_opts
.mips16
&& history
[0].fixp
[0])
5933 /* If the branch is itself the target of a branch, we can not swap.
5934 We cheat on this; all we check for is whether there is a label on
5935 this instruction. If there are any branches to anything other than
5936 a label, users must use .set noreorder. */
5937 if (seg_info (now_seg
)->label_list
)
5940 /* If the previous instruction is in a variant frag other than this
5941 branch's one, we cannot do the swap. This does not apply to
5942 MIPS16 code, which uses variant frags for different purposes. */
5943 if (!mips_opts
.mips16
5945 && history
[0].frag
->fr_type
== rs_machine_dependent
)
5948 /* We do not swap with instructions that cannot architecturally
5949 be placed in a branch delay slot, such as SYNC or ERET. We
5950 also refrain from swapping with a trap instruction, since it
5951 complicates trap handlers to have the trap instruction be in
5953 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5954 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
5957 /* Check for conflicts between the branch and the instructions
5958 before the candidate delay slot. */
5959 if (nops_for_insn (0, history
+ 1, ip
) > 0)
5962 /* Check for conflicts between the swapped sequence and the
5963 target of the branch. */
5964 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
5967 /* If the branch reads a register that the previous
5968 instruction sets, we can not swap. */
5969 gpr_read
= gpr_read_mask (ip
);
5970 prev_gpr_write
= gpr_write_mask (&history
[0]);
5971 if (gpr_read
& prev_gpr_write
)
5974 /* If the branch writes a register that the previous
5975 instruction sets, we can not swap. */
5976 gpr_write
= gpr_write_mask (ip
);
5977 if (gpr_write
& prev_gpr_write
)
5980 /* If the branch writes a register that the previous
5981 instruction reads, we can not swap. */
5982 prev_gpr_read
= gpr_read_mask (&history
[0]);
5983 if (gpr_write
& prev_gpr_read
)
5986 /* If one instruction sets a condition code and the
5987 other one uses a condition code, we can not swap. */
5988 pinfo
= ip
->insn_mo
->pinfo
;
5989 if ((pinfo
& INSN_READ_COND_CODE
)
5990 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
5992 if ((pinfo
& INSN_WRITE_COND_CODE
)
5993 && (prev_pinfo
& INSN_READ_COND_CODE
))
5996 /* If the previous instruction uses the PC, we can not swap. */
5997 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
5998 if (prev_pinfo2
& INSN2_READ_PC
)
6001 /* If the previous instruction has an incorrect size for a fixed
6002 branch delay slot in microMIPS mode, we cannot swap. */
6003 pinfo2
= ip
->insn_mo
->pinfo2
;
6004 if (mips_opts
.micromips
6005 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6006 && insn_length (history
) != 2)
6008 if (mips_opts
.micromips
6009 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6010 && insn_length (history
) != 4)
6013 /* On R5900 short loops need to be fixed by inserting a nop in
6014 the branch delay slots.
6015 A short loop can be terminated too early. */
6016 if (mips_opts
.arch
== CPU_R5900
6017 /* Check if instruction has a parameter, ignore "j $31". */
6018 && (address_expr
!= NULL
)
6019 /* Parameter must be 16 bit. */
6020 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6021 /* Branch to same segment. */
6022 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6023 /* Branch to same code fragment. */
6024 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6025 /* Can only calculate branch offset if value is known. */
6026 && symbol_constant_p(address_expr
->X_add_symbol
)
6027 /* Check if branch is really conditional. */
6028 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6029 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6030 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6033 /* Check if loop is shorter than 6 instructions including
6034 branch and delay slot. */
6035 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6042 /* When the loop includes branches or jumps,
6043 it is not a short loop. */
6044 for (i
= 0; i
< (distance
/ 4); i
++)
6046 if ((history
[i
].cleared_p
)
6047 || delayed_branch_p(&history
[i
]))
6055 /* Insert nop after branch to fix short loop. */
6064 /* Decide how we should add IP to the instruction stream.
6065 ADDRESS_EXPR is an operand of the instruction to be used with
6068 static enum append_method
6069 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6070 bfd_reloc_code_real_type
*reloc_type
)
6072 /* The relaxed version of a macro sequence must be inherently
6074 if (mips_relax
.sequence
== 2)
6077 /* We must not dabble with instructions in a ".set norerorder" block. */
6078 if (mips_opts
.noreorder
)
6081 /* Otherwise, it's our responsibility to fill branch delay slots. */
6082 if (delayed_branch_p (ip
))
6084 if (!branch_likely_p (ip
)
6085 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6088 if (mips_opts
.mips16
6089 && ISA_SUPPORTS_MIPS16E
6090 && gpr_read_mask (ip
) != 0)
6091 return APPEND_ADD_COMPACT
;
6093 return APPEND_ADD_WITH_NOP
;
6099 /* IP is a MIPS16 instruction whose opcode we have just changed.
6100 Point IP->insn_mo to the new opcode's definition. */
6103 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6105 const struct mips_opcode
*mo
, *end
;
6107 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6108 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6109 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6117 /* For microMIPS macros, we need to generate a local number label
6118 as the target of branches. */
6119 #define MICROMIPS_LABEL_CHAR '\037'
6120 static unsigned long micromips_target_label
;
6121 static char micromips_target_name
[32];
6124 micromips_label_name (void)
6126 char *p
= micromips_target_name
;
6127 char symbol_name_temporary
[24];
6135 l
= micromips_target_label
;
6136 #ifdef LOCAL_LABEL_PREFIX
6137 *p
++ = LOCAL_LABEL_PREFIX
;
6140 *p
++ = MICROMIPS_LABEL_CHAR
;
6143 symbol_name_temporary
[i
++] = l
% 10 + '0';
6148 *p
++ = symbol_name_temporary
[--i
];
6151 return micromips_target_name
;
6155 micromips_label_expr (expressionS
*label_expr
)
6157 label_expr
->X_op
= O_symbol
;
6158 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6159 label_expr
->X_add_number
= 0;
6163 micromips_label_inc (void)
6165 micromips_target_label
++;
6166 *micromips_target_name
= '\0';
6170 micromips_add_label (void)
6174 s
= colon (micromips_label_name ());
6175 micromips_label_inc ();
6176 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6179 /* If assembling microMIPS code, then return the microMIPS reloc
6180 corresponding to the requested one if any. Otherwise return
6181 the reloc unchanged. */
6183 static bfd_reloc_code_real_type
6184 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6186 static const bfd_reloc_code_real_type relocs
[][2] =
6188 /* Keep sorted incrementally by the left-hand key. */
6189 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6190 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6191 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6192 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6193 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6194 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6195 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6196 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6197 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6198 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6199 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6200 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6201 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6202 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6203 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6204 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6205 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6206 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6207 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6208 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6209 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6210 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6211 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6212 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6213 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6214 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6215 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6217 bfd_reloc_code_real_type r
;
6220 if (!mips_opts
.micromips
)
6222 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6228 return relocs
[i
][1];
6233 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6234 Return true on success, storing the resolved value in RESULT. */
6237 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6242 case BFD_RELOC_MIPS_HIGHEST
:
6243 case BFD_RELOC_MICROMIPS_HIGHEST
:
6244 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6247 case BFD_RELOC_MIPS_HIGHER
:
6248 case BFD_RELOC_MICROMIPS_HIGHER
:
6249 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6252 case BFD_RELOC_HI16_S
:
6253 case BFD_RELOC_MICROMIPS_HI16_S
:
6254 case BFD_RELOC_MIPS16_HI16_S
:
6255 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6258 case BFD_RELOC_HI16
:
6259 case BFD_RELOC_MICROMIPS_HI16
:
6260 case BFD_RELOC_MIPS16_HI16
:
6261 *result
= (operand
>> 16) & 0xffff;
6264 case BFD_RELOC_LO16
:
6265 case BFD_RELOC_MICROMIPS_LO16
:
6266 case BFD_RELOC_MIPS16_LO16
:
6267 *result
= operand
& 0xffff;
6270 case BFD_RELOC_UNUSED
:
6279 /* Output an instruction. IP is the instruction information.
6280 ADDRESS_EXPR is an operand of the instruction to be used with
6281 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6282 a macro expansion. */
6285 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6286 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6288 unsigned long prev_pinfo2
, pinfo
;
6289 bfd_boolean relaxed_branch
= FALSE
;
6290 enum append_method method
;
6291 bfd_boolean relax32
;
6294 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6295 fix_loongson2f (ip
);
6297 file_ase_mips16
|= mips_opts
.mips16
;
6298 file_ase_micromips
|= mips_opts
.micromips
;
6300 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6301 pinfo
= ip
->insn_mo
->pinfo
;
6303 if (mips_opts
.micromips
6305 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6306 && micromips_insn_length (ip
->insn_mo
) != 2)
6307 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6308 && micromips_insn_length (ip
->insn_mo
) != 4)))
6309 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6310 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6312 if (address_expr
== NULL
)
6314 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6315 && reloc_type
[1] == BFD_RELOC_UNUSED
6316 && reloc_type
[2] == BFD_RELOC_UNUSED
6317 && address_expr
->X_op
== O_constant
)
6319 switch (*reloc_type
)
6321 case BFD_RELOC_MIPS_JMP
:
6325 shift
= mips_opts
.micromips
? 1 : 2;
6326 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6327 as_bad (_("jump to misaligned address (0x%lx)"),
6328 (unsigned long) address_expr
->X_add_number
);
6329 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6335 case BFD_RELOC_MIPS16_JMP
:
6336 if ((address_expr
->X_add_number
& 3) != 0)
6337 as_bad (_("jump to misaligned address (0x%lx)"),
6338 (unsigned long) address_expr
->X_add_number
);
6340 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6341 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6342 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6346 case BFD_RELOC_16_PCREL_S2
:
6350 shift
= mips_opts
.micromips
? 1 : 2;
6351 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6352 as_bad (_("branch to misaligned address (0x%lx)"),
6353 (unsigned long) address_expr
->X_add_number
);
6354 if (!mips_relax_branch
)
6356 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6357 & ~((1 << (shift
+ 16)) - 1))
6358 as_bad (_("branch address range overflow (0x%lx)"),
6359 (unsigned long) address_expr
->X_add_number
);
6360 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6370 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6373 ip
->insn_opcode
|= value
& 0xffff;
6381 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6383 /* There are a lot of optimizations we could do that we don't.
6384 In particular, we do not, in general, reorder instructions.
6385 If you use gcc with optimization, it will reorder
6386 instructions and generally do much more optimization then we
6387 do here; repeating all that work in the assembler would only
6388 benefit hand written assembly code, and does not seem worth
6390 int nops
= (mips_optimize
== 0
6391 ? nops_for_insn (0, history
, NULL
)
6392 : nops_for_insn_or_target (0, history
, ip
));
6396 unsigned long old_frag_offset
;
6399 old_frag
= frag_now
;
6400 old_frag_offset
= frag_now_fix ();
6402 for (i
= 0; i
< nops
; i
++)
6403 add_fixed_insn (NOP_INSN
);
6404 insert_into_history (0, nops
, NOP_INSN
);
6408 listing_prev_line ();
6409 /* We may be at the start of a variant frag. In case we
6410 are, make sure there is enough space for the frag
6411 after the frags created by listing_prev_line. The
6412 argument to frag_grow here must be at least as large
6413 as the argument to all other calls to frag_grow in
6414 this file. We don't have to worry about being in the
6415 middle of a variant frag, because the variants insert
6416 all needed nop instructions themselves. */
6420 mips_move_text_labels ();
6422 #ifndef NO_ECOFF_DEBUGGING
6423 if (ECOFF_DEBUGGING
)
6424 ecoff_fix_loc (old_frag
, old_frag_offset
);
6428 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6432 /* Work out how many nops in prev_nop_frag are needed by IP,
6433 ignoring hazards generated by the first prev_nop_frag_since
6435 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6436 gas_assert (nops
<= prev_nop_frag_holds
);
6438 /* Enforce NOPS as a minimum. */
6439 if (nops
> prev_nop_frag_required
)
6440 prev_nop_frag_required
= nops
;
6442 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6444 /* Settle for the current number of nops. Update the history
6445 accordingly (for the benefit of any future .set reorder code). */
6446 prev_nop_frag
= NULL
;
6447 insert_into_history (prev_nop_frag_since
,
6448 prev_nop_frag_holds
, NOP_INSN
);
6452 /* Allow this instruction to replace one of the nops that was
6453 tentatively added to prev_nop_frag. */
6454 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6455 prev_nop_frag_holds
--;
6456 prev_nop_frag_since
++;
6460 method
= get_append_method (ip
, address_expr
, reloc_type
);
6461 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6463 dwarf2_emit_insn (0);
6464 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6465 so "move" the instruction address accordingly.
6467 Also, it doesn't seem appropriate for the assembler to reorder .loc
6468 entries. If this instruction is a branch that we are going to swap
6469 with the previous instruction, the two instructions should be
6470 treated as a unit, and the debug information for both instructions
6471 should refer to the start of the branch sequence. Using the
6472 current position is certainly wrong when swapping a 32-bit branch
6473 and a 16-bit delay slot, since the current position would then be
6474 in the middle of a branch. */
6475 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6477 relax32
= (mips_relax_branch
6478 /* Don't try branch relaxation within .set nomacro, or within
6479 .set noat if we use $at for PIC computations. If it turns
6480 out that the branch was out-of-range, we'll get an error. */
6481 && !mips_opts
.warn_about_macros
6482 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6483 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6484 as they have no complementing branches. */
6485 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6487 if (!HAVE_CODE_COMPRESSION
6490 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6491 && delayed_branch_p (ip
))
6493 relaxed_branch
= TRUE
;
6494 add_relaxed_insn (ip
, (relaxed_branch_length
6496 uncond_branch_p (ip
) ? -1
6497 : branch_likely_p (ip
) ? 1
6501 uncond_branch_p (ip
),
6502 branch_likely_p (ip
),
6503 pinfo
& INSN_WRITE_GPR_31
,
6505 address_expr
->X_add_symbol
,
6506 address_expr
->X_add_number
);
6507 *reloc_type
= BFD_RELOC_UNUSED
;
6509 else if (mips_opts
.micromips
6511 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6512 || *reloc_type
> BFD_RELOC_UNUSED
)
6513 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6514 /* Don't try branch relaxation when users specify
6515 16-bit/32-bit instructions. */
6516 && !forced_insn_length
)
6518 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6519 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6520 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6521 int compact
= compact_branch_p (ip
);
6522 int al
= pinfo
& INSN_WRITE_GPR_31
;
6525 gas_assert (address_expr
!= NULL
);
6526 gas_assert (!mips_relax
.sequence
);
6528 relaxed_branch
= TRUE
;
6529 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6530 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6531 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6533 address_expr
->X_add_symbol
,
6534 address_expr
->X_add_number
);
6535 *reloc_type
= BFD_RELOC_UNUSED
;
6537 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6539 /* We need to set up a variant frag. */
6540 gas_assert (address_expr
!= NULL
);
6541 add_relaxed_insn (ip
, 4, 0,
6543 (*reloc_type
- BFD_RELOC_UNUSED
,
6544 forced_insn_length
== 2, forced_insn_length
== 4,
6545 delayed_branch_p (&history
[0]),
6546 history
[0].mips16_absolute_jump_p
),
6547 make_expr_symbol (address_expr
), 0);
6549 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6551 if (!delayed_branch_p (ip
))
6552 /* Make sure there is enough room to swap this instruction with
6553 a following jump instruction. */
6555 add_fixed_insn (ip
);
6559 if (mips_opts
.mips16
6560 && mips_opts
.noreorder
6561 && delayed_branch_p (&history
[0]))
6562 as_warn (_("extended instruction in delay slot"));
6564 if (mips_relax
.sequence
)
6566 /* If we've reached the end of this frag, turn it into a variant
6567 frag and record the information for the instructions we've
6569 if (frag_room () < 4)
6570 relax_close_frag ();
6571 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6574 if (mips_relax
.sequence
!= 2)
6576 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6577 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6578 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6579 mips_macro_warning
.insns
[0]++;
6581 if (mips_relax
.sequence
!= 1)
6583 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6584 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6585 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6586 mips_macro_warning
.insns
[1]++;
6589 if (mips_opts
.mips16
)
6592 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6594 add_fixed_insn (ip
);
6597 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6599 bfd_reloc_code_real_type final_type
[3];
6600 reloc_howto_type
*howto0
;
6601 reloc_howto_type
*howto
;
6604 /* Perform any necessary conversion to microMIPS relocations
6605 and find out how many relocations there actually are. */
6606 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6607 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6609 /* In a compound relocation, it is the final (outermost)
6610 operator that determines the relocated field. */
6611 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6616 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6617 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6618 bfd_get_reloc_size (howto
),
6620 howto0
&& howto0
->pc_relative
,
6623 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6624 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6625 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6627 /* These relocations can have an addend that won't fit in
6628 4 octets for 64bit assembly. */
6630 && ! howto
->partial_inplace
6631 && (reloc_type
[0] == BFD_RELOC_16
6632 || reloc_type
[0] == BFD_RELOC_32
6633 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6634 || reloc_type
[0] == BFD_RELOC_GPREL16
6635 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6636 || reloc_type
[0] == BFD_RELOC_GPREL32
6637 || reloc_type
[0] == BFD_RELOC_64
6638 || reloc_type
[0] == BFD_RELOC_CTOR
6639 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6640 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6641 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6642 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6643 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6644 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6645 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6646 || hi16_reloc_p (reloc_type
[0])
6647 || lo16_reloc_p (reloc_type
[0])))
6648 ip
->fixp
[0]->fx_no_overflow
= 1;
6650 /* These relocations can have an addend that won't fit in 2 octets. */
6651 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6652 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6653 ip
->fixp
[0]->fx_no_overflow
= 1;
6655 if (mips_relax
.sequence
)
6657 if (mips_relax
.first_fixup
== 0)
6658 mips_relax
.first_fixup
= ip
->fixp
[0];
6660 else if (reloc_needs_lo_p (*reloc_type
))
6662 struct mips_hi_fixup
*hi_fixup
;
6664 /* Reuse the last entry if it already has a matching %lo. */
6665 hi_fixup
= mips_hi_fixup_list
;
6667 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6669 hi_fixup
= ((struct mips_hi_fixup
*)
6670 xmalloc (sizeof (struct mips_hi_fixup
)));
6671 hi_fixup
->next
= mips_hi_fixup_list
;
6672 mips_hi_fixup_list
= hi_fixup
;
6674 hi_fixup
->fixp
= ip
->fixp
[0];
6675 hi_fixup
->seg
= now_seg
;
6678 /* Add fixups for the second and third relocations, if given.
6679 Note that the ABI allows the second relocation to be
6680 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6681 moment we only use RSS_UNDEF, but we could add support
6682 for the others if it ever becomes necessary. */
6683 for (i
= 1; i
< 3; i
++)
6684 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6686 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6687 ip
->fixp
[0]->fx_size
, NULL
, 0,
6688 FALSE
, final_type
[i
]);
6690 /* Use fx_tcbit to mark compound relocs. */
6691 ip
->fixp
[0]->fx_tcbit
= 1;
6692 ip
->fixp
[i
]->fx_tcbit
= 1;
6697 /* Update the register mask information. */
6698 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6699 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6704 insert_into_history (0, 1, ip
);
6707 case APPEND_ADD_WITH_NOP
:
6709 struct mips_cl_insn
*nop
;
6711 insert_into_history (0, 1, ip
);
6712 nop
= get_delay_slot_nop (ip
);
6713 add_fixed_insn (nop
);
6714 insert_into_history (0, 1, nop
);
6715 if (mips_relax
.sequence
)
6716 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6720 case APPEND_ADD_COMPACT
:
6721 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6722 gas_assert (mips_opts
.mips16
);
6723 ip
->insn_opcode
|= 0x0080;
6724 find_altered_mips16_opcode (ip
);
6726 insert_into_history (0, 1, ip
);
6731 struct mips_cl_insn delay
= history
[0];
6732 if (mips_opts
.mips16
)
6734 know (delay
.frag
== ip
->frag
);
6735 move_insn (ip
, delay
.frag
, delay
.where
);
6736 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6738 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6740 /* Add the delay slot instruction to the end of the
6741 current frag and shrink the fixed part of the
6742 original frag. If the branch occupies the tail of
6743 the latter, move it backwards to cover the gap. */
6744 delay
.frag
->fr_fix
-= branch_disp
;
6745 if (delay
.frag
== ip
->frag
)
6746 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6747 add_fixed_insn (&delay
);
6751 move_insn (&delay
, ip
->frag
,
6752 ip
->where
- branch_disp
+ insn_length (ip
));
6753 move_insn (ip
, history
[0].frag
, history
[0].where
);
6757 insert_into_history (0, 1, &delay
);
6762 /* If we have just completed an unconditional branch, clear the history. */
6763 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6764 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6768 mips_no_prev_insn ();
6770 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6771 history
[i
].cleared_p
= 1;
6774 /* We need to emit a label at the end of branch-likely macros. */
6775 if (emit_branch_likely_macro
)
6777 emit_branch_likely_macro
= FALSE
;
6778 micromips_add_label ();
6781 /* We just output an insn, so the next one doesn't have a label. */
6782 mips_clear_insn_labels ();
6785 /* Forget that there was any previous instruction or label.
6786 When BRANCH is true, the branch history is also flushed. */
6789 mips_no_prev_insn (void)
6791 prev_nop_frag
= NULL
;
6792 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6793 mips_clear_insn_labels ();
6796 /* This function must be called before we emit something other than
6797 instructions. It is like mips_no_prev_insn except that it inserts
6798 any NOPS that might be needed by previous instructions. */
6801 mips_emit_delays (void)
6803 if (! mips_opts
.noreorder
)
6805 int nops
= nops_for_insn (0, history
, NULL
);
6809 add_fixed_insn (NOP_INSN
);
6810 mips_move_text_labels ();
6813 mips_no_prev_insn ();
6816 /* Start a (possibly nested) noreorder block. */
6819 start_noreorder (void)
6821 if (mips_opts
.noreorder
== 0)
6826 /* None of the instructions before the .set noreorder can be moved. */
6827 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6828 history
[i
].fixed_p
= 1;
6830 /* Insert any nops that might be needed between the .set noreorder
6831 block and the previous instructions. We will later remove any
6832 nops that turn out not to be needed. */
6833 nops
= nops_for_insn (0, history
, NULL
);
6836 if (mips_optimize
!= 0)
6838 /* Record the frag which holds the nop instructions, so
6839 that we can remove them if we don't need them. */
6840 frag_grow (nops
* NOP_INSN_SIZE
);
6841 prev_nop_frag
= frag_now
;
6842 prev_nop_frag_holds
= nops
;
6843 prev_nop_frag_required
= 0;
6844 prev_nop_frag_since
= 0;
6847 for (; nops
> 0; --nops
)
6848 add_fixed_insn (NOP_INSN
);
6850 /* Move on to a new frag, so that it is safe to simply
6851 decrease the size of prev_nop_frag. */
6852 frag_wane (frag_now
);
6854 mips_move_text_labels ();
6856 mips_mark_labels ();
6857 mips_clear_insn_labels ();
6859 mips_opts
.noreorder
++;
6860 mips_any_noreorder
= 1;
6863 /* End a nested noreorder block. */
6866 end_noreorder (void)
6868 mips_opts
.noreorder
--;
6869 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
6871 /* Commit to inserting prev_nop_frag_required nops and go back to
6872 handling nop insertion the .set reorder way. */
6873 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
6875 insert_into_history (prev_nop_frag_since
,
6876 prev_nop_frag_required
, NOP_INSN
);
6877 prev_nop_frag
= NULL
;
6881 /* Set up global variables for the start of a new macro. */
6886 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
6887 memset (&mips_macro_warning
.first_insn_sizes
, 0,
6888 sizeof (mips_macro_warning
.first_insn_sizes
));
6889 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
6890 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
6891 && delayed_branch_p (&history
[0]));
6892 switch (history
[0].insn_mo
->pinfo2
6893 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
6895 case INSN2_BRANCH_DELAY_32BIT
:
6896 mips_macro_warning
.delay_slot_length
= 4;
6898 case INSN2_BRANCH_DELAY_16BIT
:
6899 mips_macro_warning
.delay_slot_length
= 2;
6902 mips_macro_warning
.delay_slot_length
= 0;
6905 mips_macro_warning
.first_frag
= NULL
;
6908 /* Given that a macro is longer than one instruction or of the wrong size,
6909 return the appropriate warning for it. Return null if no warning is
6910 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
6911 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
6912 and RELAX_NOMACRO. */
6915 macro_warning (relax_substateT subtype
)
6917 if (subtype
& RELAX_DELAY_SLOT
)
6918 return _("Macro instruction expanded into multiple instructions"
6919 " in a branch delay slot");
6920 else if (subtype
& RELAX_NOMACRO
)
6921 return _("Macro instruction expanded into multiple instructions");
6922 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
6923 | RELAX_DELAY_SLOT_SIZE_SECOND
))
6924 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
6925 ? _("Macro instruction expanded into a wrong size instruction"
6926 " in a 16-bit branch delay slot")
6927 : _("Macro instruction expanded into a wrong size instruction"
6928 " in a 32-bit branch delay slot"));
6933 /* Finish up a macro. Emit warnings as appropriate. */
6938 /* Relaxation warning flags. */
6939 relax_substateT subtype
= 0;
6941 /* Check delay slot size requirements. */
6942 if (mips_macro_warning
.delay_slot_length
== 2)
6943 subtype
|= RELAX_DELAY_SLOT_16BIT
;
6944 if (mips_macro_warning
.delay_slot_length
!= 0)
6946 if (mips_macro_warning
.delay_slot_length
6947 != mips_macro_warning
.first_insn_sizes
[0])
6948 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
6949 if (mips_macro_warning
.delay_slot_length
6950 != mips_macro_warning
.first_insn_sizes
[1])
6951 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
6954 /* Check instruction count requirements. */
6955 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
6957 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
6958 subtype
|= RELAX_SECOND_LONGER
;
6959 if (mips_opts
.warn_about_macros
)
6960 subtype
|= RELAX_NOMACRO
;
6961 if (mips_macro_warning
.delay_slot_p
)
6962 subtype
|= RELAX_DELAY_SLOT
;
6965 /* If both alternatives fail to fill a delay slot correctly,
6966 emit the warning now. */
6967 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
6968 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
6973 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
6974 | RELAX_DELAY_SLOT_SIZE_FIRST
6975 | RELAX_DELAY_SLOT_SIZE_SECOND
);
6976 msg
= macro_warning (s
);
6978 as_warn ("%s", msg
);
6982 /* If both implementations are longer than 1 instruction, then emit the
6984 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
6989 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
6990 msg
= macro_warning (s
);
6992 as_warn ("%s", msg
);
6996 /* If any flags still set, then one implementation might need a warning
6997 and the other either will need one of a different kind or none at all.
6998 Pass any remaining flags over to relaxation. */
6999 if (mips_macro_warning
.first_frag
!= NULL
)
7000 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7003 /* Instruction operand formats used in macros that vary between
7004 standard MIPS and microMIPS code. */
7006 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7007 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7008 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7009 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7010 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7011 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7012 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7013 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7015 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7016 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7017 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7018 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7019 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7020 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7021 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7022 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7024 /* Read a macro's relocation codes from *ARGS and store them in *R.
7025 The first argument in *ARGS will be either the code for a single
7026 relocation or -1 followed by the three codes that make up a
7027 composite relocation. */
7030 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7034 next
= va_arg (*args
, int);
7036 r
[0] = (bfd_reloc_code_real_type
) next
;
7039 for (i
= 0; i
< 3; i
++)
7040 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7041 /* This function is only used for 16-bit relocation fields.
7042 To make the macro code simpler, treat an unrelocated value
7043 in the same way as BFD_RELOC_LO16. */
7044 if (r
[0] == BFD_RELOC_UNUSED
)
7045 r
[0] = BFD_RELOC_LO16
;
7049 /* Build an instruction created by a macro expansion. This is passed
7050 a pointer to the count of instructions created so far, an
7051 expression, the name of the instruction to build, an operand format
7052 string, and corresponding arguments. */
7055 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7057 const struct mips_opcode
*mo
= NULL
;
7058 bfd_reloc_code_real_type r
[3];
7059 const struct mips_opcode
*amo
;
7060 const struct mips_operand
*operand
;
7061 struct hash_control
*hash
;
7062 struct mips_cl_insn insn
;
7066 va_start (args
, fmt
);
7068 if (mips_opts
.mips16
)
7070 mips16_macro_build (ep
, name
, fmt
, &args
);
7075 r
[0] = BFD_RELOC_UNUSED
;
7076 r
[1] = BFD_RELOC_UNUSED
;
7077 r
[2] = BFD_RELOC_UNUSED
;
7078 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7079 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7081 gas_assert (strcmp (name
, amo
->name
) == 0);
7085 /* Search until we get a match for NAME. It is assumed here that
7086 macros will never generate MDMX, MIPS-3D, or MT instructions.
7087 We try to match an instruction that fulfils the branch delay
7088 slot instruction length requirement (if any) of the previous
7089 instruction. While doing this we record the first instruction
7090 seen that matches all the other conditions and use it anyway
7091 if the requirement cannot be met; we will issue an appropriate
7092 warning later on. */
7093 if (strcmp (fmt
, amo
->args
) == 0
7094 && amo
->pinfo
!= INSN_MACRO
7095 && is_opcode_valid (amo
)
7096 && is_size_valid (amo
))
7098 if (is_delay_slot_valid (amo
))
7108 gas_assert (amo
->name
);
7110 while (strcmp (name
, amo
->name
) == 0);
7113 create_insn (&insn
, mo
);
7126 macro_read_relocs (&args
, r
);
7127 gas_assert (*r
== BFD_RELOC_GPREL16
7128 || *r
== BFD_RELOC_MIPS_HIGHER
7129 || *r
== BFD_RELOC_HI16_S
7130 || *r
== BFD_RELOC_LO16
7131 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7135 macro_read_relocs (&args
, r
);
7139 macro_read_relocs (&args
, r
);
7140 gas_assert (ep
!= NULL
7141 && (ep
->X_op
== O_constant
7142 || (ep
->X_op
== O_symbol
7143 && (*r
== BFD_RELOC_MIPS_HIGHEST
7144 || *r
== BFD_RELOC_HI16_S
7145 || *r
== BFD_RELOC_HI16
7146 || *r
== BFD_RELOC_GPREL16
7147 || *r
== BFD_RELOC_MIPS_GOT_HI16
7148 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7152 gas_assert (ep
!= NULL
);
7155 * This allows macro() to pass an immediate expression for
7156 * creating short branches without creating a symbol.
7158 * We don't allow branch relaxation for these branches, as
7159 * they should only appear in ".set nomacro" anyway.
7161 if (ep
->X_op
== O_constant
)
7163 /* For microMIPS we always use relocations for branches.
7164 So we should not resolve immediate values. */
7165 gas_assert (!mips_opts
.micromips
);
7167 if ((ep
->X_add_number
& 3) != 0)
7168 as_bad (_("branch to misaligned address (0x%lx)"),
7169 (unsigned long) ep
->X_add_number
);
7170 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7171 as_bad (_("branch address range overflow (0x%lx)"),
7172 (unsigned long) ep
->X_add_number
);
7173 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7177 *r
= BFD_RELOC_16_PCREL_S2
;
7181 gas_assert (ep
!= NULL
);
7182 *r
= BFD_RELOC_MIPS_JMP
;
7186 operand
= (mips_opts
.micromips
7187 ? decode_micromips_operand (fmt
)
7188 : decode_mips_operand (fmt
));
7192 uval
= va_arg (args
, int);
7193 if (operand
->type
== OP_CLO_CLZ_DEST
)
7194 uval
|= (uval
<< 5);
7195 insn_insert_operand (&insn
, operand
, uval
);
7197 if (*fmt
== '+' || *fmt
== 'm')
7203 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7205 append_insn (&insn
, ep
, r
, TRUE
);
7209 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
7212 struct mips_opcode
*mo
;
7213 struct mips_cl_insn insn
;
7214 const struct mips_operand
*operand
;
7215 bfd_reloc_code_real_type r
[3]
7216 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
7218 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
7220 gas_assert (strcmp (name
, mo
->name
) == 0);
7222 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7225 gas_assert (mo
->name
);
7226 gas_assert (strcmp (name
, mo
->name
) == 0);
7229 create_insn (&insn
, mo
);
7267 gas_assert (ep
!= NULL
);
7269 if (ep
->X_op
!= O_constant
)
7270 *r
= (int) BFD_RELOC_UNUSED
+ c
;
7271 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
7273 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
7275 *r
= BFD_RELOC_UNUSED
;
7281 operand
= decode_mips16_operand (c
, FALSE
);
7285 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
7290 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7292 append_insn (&insn
, ep
, r
, TRUE
);
7296 * Sign-extend 32-bit mode constants that have bit 31 set and all
7297 * higher bits unset.
7300 normalize_constant_expr (expressionS
*ex
)
7302 if (ex
->X_op
== O_constant
7303 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7304 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7309 * Sign-extend 32-bit mode address offsets that have bit 31 set and
7310 * all higher bits unset.
7313 normalize_address_expr (expressionS
*ex
)
7315 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7316 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7317 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7318 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7323 * Generate a "jalr" instruction with a relocation hint to the called
7324 * function. This occurs in NewABI PIC code.
7327 macro_build_jalr (expressionS
*ep
, int cprestore
)
7329 static const bfd_reloc_code_real_type jalr_relocs
[2]
7330 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
7331 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
7335 if (MIPS_JALR_HINT_P (ep
))
7340 if (mips_opts
.micromips
)
7342 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
7343 ? "jalr" : "jalrs");
7344 if (MIPS_JALR_HINT_P (ep
)
7346 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
7347 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
7349 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
7352 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
7353 if (MIPS_JALR_HINT_P (ep
))
7354 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
7358 * Generate a "lui" instruction.
7361 macro_build_lui (expressionS
*ep
, int regnum
)
7363 gas_assert (! mips_opts
.mips16
);
7365 if (ep
->X_op
!= O_constant
)
7367 gas_assert (ep
->X_op
== O_symbol
);
7368 /* _gp_disp is a special case, used from s_cpload.
7369 __gnu_local_gp is used if mips_no_shared. */
7370 gas_assert (mips_pic
== NO_PIC
7372 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
7373 || (! mips_in_shared
7374 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
7375 "__gnu_local_gp") == 0));
7378 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
7381 /* Generate a sequence of instructions to do a load or store from a constant
7382 offset off of a base register (breg) into/from a target register (treg),
7383 using AT if necessary. */
7385 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
7386 int treg
, int breg
, int dbl
)
7388 gas_assert (ep
->X_op
== O_constant
);
7390 /* Sign-extending 32-bit constants makes their handling easier. */
7392 normalize_constant_expr (ep
);
7394 /* Right now, this routine can only handle signed 32-bit constants. */
7395 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
7396 as_warn (_("operand overflow"));
7398 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
7400 /* Signed 16-bit offset will fit in the op. Easy! */
7401 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7405 /* 32-bit offset, need multiple instructions and AT, like:
7406 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7407 addu $tempreg,$tempreg,$breg
7408 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7409 to handle the complete offset. */
7410 macro_build_lui (ep
, AT
);
7411 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7412 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7415 as_bad (_("Macro used $at after \".set noat\""));
7420 * Generates code to set the $at register to true (one)
7421 * if reg is less than the immediate expression.
7424 set_at (int reg
, int unsignedp
)
7426 if (imm_expr
.X_op
== O_constant
7427 && imm_expr
.X_add_number
>= -0x8000
7428 && imm_expr
.X_add_number
< 0x8000)
7429 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
7430 AT
, reg
, BFD_RELOC_LO16
);
7433 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7434 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
7438 /* Count the leading zeroes by performing a binary chop. This is a
7439 bulky bit of source, but performance is a LOT better for the
7440 majority of values than a simple loop to count the bits:
7441 for (lcnt = 0; (lcnt < 32); lcnt++)
7442 if ((v) & (1 << (31 - lcnt)))
7444 However it is not code size friendly, and the gain will drop a bit
7445 on certain cached systems.
7447 #define COUNT_TOP_ZEROES(v) \
7448 (((v) & ~0xffff) == 0 \
7449 ? ((v) & ~0xff) == 0 \
7450 ? ((v) & ~0xf) == 0 \
7451 ? ((v) & ~0x3) == 0 \
7452 ? ((v) & ~0x1) == 0 \
7457 : ((v) & ~0x7) == 0 \
7460 : ((v) & ~0x3f) == 0 \
7461 ? ((v) & ~0x1f) == 0 \
7464 : ((v) & ~0x7f) == 0 \
7467 : ((v) & ~0xfff) == 0 \
7468 ? ((v) & ~0x3ff) == 0 \
7469 ? ((v) & ~0x1ff) == 0 \
7472 : ((v) & ~0x7ff) == 0 \
7475 : ((v) & ~0x3fff) == 0 \
7476 ? ((v) & ~0x1fff) == 0 \
7479 : ((v) & ~0x7fff) == 0 \
7482 : ((v) & ~0xffffff) == 0 \
7483 ? ((v) & ~0xfffff) == 0 \
7484 ? ((v) & ~0x3ffff) == 0 \
7485 ? ((v) & ~0x1ffff) == 0 \
7488 : ((v) & ~0x7ffff) == 0 \
7491 : ((v) & ~0x3fffff) == 0 \
7492 ? ((v) & ~0x1fffff) == 0 \
7495 : ((v) & ~0x7fffff) == 0 \
7498 : ((v) & ~0xfffffff) == 0 \
7499 ? ((v) & ~0x3ffffff) == 0 \
7500 ? ((v) & ~0x1ffffff) == 0 \
7503 : ((v) & ~0x7ffffff) == 0 \
7506 : ((v) & ~0x3fffffff) == 0 \
7507 ? ((v) & ~0x1fffffff) == 0 \
7510 : ((v) & ~0x7fffffff) == 0 \
7515 * This routine generates the least number of instructions necessary to load
7516 * an absolute expression value into a register.
7519 load_register (int reg
, expressionS
*ep
, int dbl
)
7522 expressionS hi32
, lo32
;
7524 if (ep
->X_op
!= O_big
)
7526 gas_assert (ep
->X_op
== O_constant
);
7528 /* Sign-extending 32-bit constants makes their handling easier. */
7530 normalize_constant_expr (ep
);
7532 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
7534 /* We can handle 16 bit signed values with an addiu to
7535 $zero. No need to ever use daddiu here, since $zero and
7536 the result are always correct in 32 bit mode. */
7537 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7540 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
7542 /* We can handle 16 bit unsigned values with an ori to
7544 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7547 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
7549 /* 32 bit values require an lui. */
7550 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7551 if ((ep
->X_add_number
& 0xffff) != 0)
7552 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7557 /* The value is larger than 32 bits. */
7559 if (!dbl
|| HAVE_32BIT_GPRS
)
7563 sprintf_vma (value
, ep
->X_add_number
);
7564 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7565 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7569 if (ep
->X_op
!= O_big
)
7572 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7573 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
7574 hi32
.X_add_number
&= 0xffffffff;
7576 lo32
.X_add_number
&= 0xffffffff;
7580 gas_assert (ep
->X_add_number
> 2);
7581 if (ep
->X_add_number
== 3)
7582 generic_bignum
[3] = 0;
7583 else if (ep
->X_add_number
> 4)
7584 as_bad (_("Number larger than 64 bits"));
7585 lo32
.X_op
= O_constant
;
7586 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
7587 hi32
.X_op
= O_constant
;
7588 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
7591 if (hi32
.X_add_number
== 0)
7596 unsigned long hi
, lo
;
7598 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
7600 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
7602 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7605 if (lo32
.X_add_number
& 0x80000000)
7607 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7608 if (lo32
.X_add_number
& 0xffff)
7609 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
7614 /* Check for 16bit shifted constant. We know that hi32 is
7615 non-zero, so start the mask on the first bit of the hi32
7620 unsigned long himask
, lomask
;
7624 himask
= 0xffff >> (32 - shift
);
7625 lomask
= (0xffff << shift
) & 0xffffffff;
7629 himask
= 0xffff << (shift
- 32);
7632 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
7633 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
7637 tmp
.X_op
= O_constant
;
7639 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
7640 | (lo32
.X_add_number
>> shift
));
7642 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
7643 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
7644 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7645 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7650 while (shift
<= (64 - 16));
7652 /* Find the bit number of the lowest one bit, and store the
7653 shifted value in hi/lo. */
7654 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
7655 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
7659 while ((lo
& 1) == 0)
7664 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
7670 while ((hi
& 1) == 0)
7679 /* Optimize if the shifted value is a (power of 2) - 1. */
7680 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
7681 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
7683 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
7688 /* This instruction will set the register to be all
7690 tmp
.X_op
= O_constant
;
7691 tmp
.X_add_number
= (offsetT
) -1;
7692 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
7696 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
7697 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
7699 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
7700 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
7705 /* Sign extend hi32 before calling load_register, because we can
7706 generally get better code when we load a sign extended value. */
7707 if ((hi32
.X_add_number
& 0x80000000) != 0)
7708 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
7709 load_register (reg
, &hi32
, 0);
7712 if ((lo32
.X_add_number
& 0xffff0000) == 0)
7716 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
7724 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
7726 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
7727 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
7733 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
7737 mid16
.X_add_number
>>= 16;
7738 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7739 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7742 if ((lo32
.X_add_number
& 0xffff) != 0)
7743 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
7747 load_delay_nop (void)
7749 if (!gpr_interlocks
)
7750 macro_build (NULL
, "nop", "");
7753 /* Load an address into a register. */
7756 load_address (int reg
, expressionS
*ep
, int *used_at
)
7758 if (ep
->X_op
!= O_constant
7759 && ep
->X_op
!= O_symbol
)
7761 as_bad (_("expression too complex"));
7762 ep
->X_op
= O_constant
;
7765 if (ep
->X_op
== O_constant
)
7767 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
7771 if (mips_pic
== NO_PIC
)
7773 /* If this is a reference to a GP relative symbol, we want
7774 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
7776 lui $reg,<sym> (BFD_RELOC_HI16_S)
7777 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7778 If we have an addend, we always use the latter form.
7780 With 64bit address space and a usable $at we want
7781 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7782 lui $at,<sym> (BFD_RELOC_HI16_S)
7783 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7784 daddiu $at,<sym> (BFD_RELOC_LO16)
7788 If $at is already in use, we use a path which is suboptimal
7789 on superscalar processors.
7790 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7791 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
7793 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
7795 daddiu $reg,<sym> (BFD_RELOC_LO16)
7797 For GP relative symbols in 64bit address space we can use
7798 the same sequence as in 32bit address space. */
7799 if (HAVE_64BIT_SYMBOLS
)
7801 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7802 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7804 relax_start (ep
->X_add_symbol
);
7805 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7806 mips_gp_register
, BFD_RELOC_GPREL16
);
7810 if (*used_at
== 0 && mips_opts
.at
)
7812 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7813 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
7814 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7815 BFD_RELOC_MIPS_HIGHER
);
7816 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
7817 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
7818 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
7823 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
7824 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
7825 BFD_RELOC_MIPS_HIGHER
);
7826 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7827 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
7828 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
7829 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
7832 if (mips_relax
.sequence
)
7837 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
7838 && !nopic_need_relax (ep
->X_add_symbol
, 1))
7840 relax_start (ep
->X_add_symbol
);
7841 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
7842 mips_gp_register
, BFD_RELOC_GPREL16
);
7845 macro_build_lui (ep
, reg
);
7846 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
7847 reg
, reg
, BFD_RELOC_LO16
);
7848 if (mips_relax
.sequence
)
7852 else if (!mips_big_got
)
7856 /* If this is a reference to an external symbol, we want
7857 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7859 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7861 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7862 If there is a constant, it must be added in after.
7864 If we have NewABI, we want
7865 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7866 unless we're referencing a global symbol with a non-zero
7867 offset, in which case cst must be added separately. */
7870 if (ep
->X_add_number
)
7872 ex
.X_add_number
= ep
->X_add_number
;
7873 ep
->X_add_number
= 0;
7874 relax_start (ep
->X_add_symbol
);
7875 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7876 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7877 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7878 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7879 ex
.X_op
= O_constant
;
7880 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7881 reg
, reg
, BFD_RELOC_LO16
);
7882 ep
->X_add_number
= ex
.X_add_number
;
7885 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7886 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7887 if (mips_relax
.sequence
)
7892 ex
.X_add_number
= ep
->X_add_number
;
7893 ep
->X_add_number
= 0;
7894 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7895 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7897 relax_start (ep
->X_add_symbol
);
7899 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7903 if (ex
.X_add_number
!= 0)
7905 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7906 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7907 ex
.X_op
= O_constant
;
7908 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
7909 reg
, reg
, BFD_RELOC_LO16
);
7913 else if (mips_big_got
)
7917 /* This is the large GOT case. If this is a reference to an
7918 external symbol, we want
7919 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7921 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
7923 Otherwise, for a reference to a local symbol in old ABI, we want
7924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7926 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
7927 If there is a constant, it must be added in after.
7929 In the NewABI, for local symbols, with or without offsets, we want:
7930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7931 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7935 ex
.X_add_number
= ep
->X_add_number
;
7936 ep
->X_add_number
= 0;
7937 relax_start (ep
->X_add_symbol
);
7938 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7939 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7940 reg
, reg
, mips_gp_register
);
7941 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7942 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7943 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7944 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7945 else if (ex
.X_add_number
)
7947 ex
.X_op
= O_constant
;
7948 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7952 ep
->X_add_number
= ex
.X_add_number
;
7954 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7955 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
7956 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7957 BFD_RELOC_MIPS_GOT_OFST
);
7962 ex
.X_add_number
= ep
->X_add_number
;
7963 ep
->X_add_number
= 0;
7964 relax_start (ep
->X_add_symbol
);
7965 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
7966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7967 reg
, reg
, mips_gp_register
);
7968 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
7969 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
7971 if (reg_needs_delay (mips_gp_register
))
7973 /* We need a nop before loading from $gp. This special
7974 check is required because the lui which starts the main
7975 instruction stream does not refer to $gp, and so will not
7976 insert the nop which may be required. */
7977 macro_build (NULL
, "nop", "");
7979 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
7980 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7982 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7986 if (ex
.X_add_number
!= 0)
7988 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
7989 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7990 ex
.X_op
= O_constant
;
7991 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
7999 if (!mips_opts
.at
&& *used_at
== 1)
8000 as_bad (_("Macro used $at after \".set noat\""));
8003 /* Move the contents of register SOURCE into register DEST. */
8006 move_register (int dest
, int source
)
8008 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8009 instruction specifically requires a 32-bit one. */
8010 if (mips_opts
.micromips
8011 && !mips_opts
.insn32
8012 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8013 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8015 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8019 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8020 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8021 The two alternatives are:
8023 Global symbol Local sybmol
8024 ------------- ------------
8025 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8027 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8029 load_got_offset emits the first instruction and add_got_offset
8030 emits the second for a 16-bit offset or add_got_offset_hilo emits
8031 a sequence to add a 32-bit offset using a scratch register. */
8034 load_got_offset (int dest
, expressionS
*local
)
8039 global
.X_add_number
= 0;
8041 relax_start (local
->X_add_symbol
);
8042 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8043 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8045 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8046 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8051 add_got_offset (int dest
, expressionS
*local
)
8055 global
.X_op
= O_constant
;
8056 global
.X_op_symbol
= NULL
;
8057 global
.X_add_symbol
= NULL
;
8058 global
.X_add_number
= local
->X_add_number
;
8060 relax_start (local
->X_add_symbol
);
8061 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8062 dest
, dest
, BFD_RELOC_LO16
);
8064 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8069 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8072 int hold_mips_optimize
;
8074 global
.X_op
= O_constant
;
8075 global
.X_op_symbol
= NULL
;
8076 global
.X_add_symbol
= NULL
;
8077 global
.X_add_number
= local
->X_add_number
;
8079 relax_start (local
->X_add_symbol
);
8080 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8082 /* Set mips_optimize around the lui instruction to avoid
8083 inserting an unnecessary nop after the lw. */
8084 hold_mips_optimize
= mips_optimize
;
8086 macro_build_lui (&global
, tmp
);
8087 mips_optimize
= hold_mips_optimize
;
8088 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8091 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8094 /* Emit a sequence of instructions to emulate a branch likely operation.
8095 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8096 is its complementing branch with the original condition negated.
8097 CALL is set if the original branch specified the link operation.
8098 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8100 Code like this is produced in the noreorder mode:
8105 delay slot (executed only if branch taken)
8113 delay slot (executed only if branch taken)
8116 In the reorder mode the delay slot would be filled with a nop anyway,
8117 so code produced is simply:
8122 This function is used when producing code for the microMIPS ASE that
8123 does not implement branch likely instructions in hardware. */
8126 macro_build_branch_likely (const char *br
, const char *brneg
,
8127 int call
, expressionS
*ep
, const char *fmt
,
8128 unsigned int sreg
, unsigned int treg
)
8130 int noreorder
= mips_opts
.noreorder
;
8133 gas_assert (mips_opts
.micromips
);
8137 micromips_label_expr (&expr1
);
8138 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8139 macro_build (NULL
, "nop", "");
8140 macro_build (ep
, call
? "bal" : "b", "p");
8142 /* Set to true so that append_insn adds a label. */
8143 emit_branch_likely_macro
= TRUE
;
8147 macro_build (ep
, br
, fmt
, sreg
, treg
);
8148 macro_build (NULL
, "nop", "");
8153 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8154 the condition code tested. EP specifies the branch target. */
8157 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8184 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8187 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8188 the register tested. EP specifies the branch target. */
8191 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8193 const char *brneg
= NULL
;
8203 br
= mips_opts
.micromips
? "bgez" : "bgezl";
8207 gas_assert (mips_opts
.micromips
);
8208 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
8216 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8223 br
= mips_opts
.micromips
? "blez" : "blezl";
8230 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8234 gas_assert (mips_opts
.micromips
);
8235 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8242 if (mips_opts
.micromips
&& brneg
)
8243 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8245 macro_build (ep
, br
, "s,p", sreg
);
8248 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8249 TREG as the registers tested. EP specifies the branch target. */
8252 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8253 unsigned int sreg
, unsigned int treg
)
8255 const char *brneg
= NULL
;
8267 br
= mips_opts
.micromips
? "beq" : "beql";
8276 br
= mips_opts
.micromips
? "bne" : "bnel";
8282 if (mips_opts
.micromips
&& brneg
)
8283 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8285 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8288 /* Return the high part that should be loaded in order to make the low
8289 part of VALUE accessible using an offset of OFFBITS bits. */
8292 offset_high_part (offsetT value
, unsigned int offbits
)
8299 bias
= 1 << (offbits
- 1);
8300 low_mask
= bias
* 2 - 1;
8301 return (value
+ bias
) & ~low_mask
;
8304 /* Return true if the value stored in offset_expr and offset_reloc
8305 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8306 amount that the caller wants to add without inducing overflow
8307 and ALIGN is the known alignment of the value in bytes. */
8310 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
8314 /* Accept any relocation operator if overflow isn't a concern. */
8315 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8318 /* These relocations are guaranteed not to overflow in correct links. */
8319 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
8320 || gprel16_reloc_p (*offset_reloc
))
8323 if (offset_expr
.X_op
== O_constant
8324 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
8325 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
8332 * This routine implements the seemingly endless macro or synthesized
8333 * instructions and addressing modes in the mips assembly language. Many
8334 * of these macros are simple and are similar to each other. These could
8335 * probably be handled by some kind of table or grammar approach instead of
8336 * this verbose method. Others are not simple macros but are more like
8337 * optimizing code generation.
8338 * One interesting optimization is when several store macros appear
8339 * consecutively that would load AT with the upper half of the same address.
8340 * The ensuing load upper instructions are ommited. This implies some kind
8341 * of global optimization. We currently only optimize within a single macro.
8342 * For many of the load and store macros if the address is specified as a
8343 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8344 * first load register 'at' with zero and use it as the base register. The
8345 * mips assembler simply uses register $zero. Just one tiny optimization
8349 macro (struct mips_cl_insn
*ip
, char *str
)
8351 const struct mips_operand_array
*operands
;
8352 unsigned int breg
, i
;
8353 unsigned int tempreg
;
8356 expressionS label_expr
;
8371 bfd_boolean large_offset
;
8373 int hold_mips_optimize
;
8375 unsigned int op
[MAX_OPERANDS
];
8377 gas_assert (! mips_opts
.mips16
);
8379 operands
= insn_operands (ip
);
8380 for (i
= 0; i
< MAX_OPERANDS
; i
++)
8381 if (operands
->operand
[i
])
8382 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
8386 mask
= ip
->insn_mo
->mask
;
8388 label_expr
.X_op
= O_constant
;
8389 label_expr
.X_op_symbol
= NULL
;
8390 label_expr
.X_add_symbol
= NULL
;
8391 label_expr
.X_add_number
= 0;
8393 expr1
.X_op
= O_constant
;
8394 expr1
.X_op_symbol
= NULL
;
8395 expr1
.X_add_symbol
= NULL
;
8396 expr1
.X_add_number
= 1;
8412 if (mips_opts
.micromips
)
8413 micromips_label_expr (&label_expr
);
8415 label_expr
.X_add_number
= 8;
8416 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
8418 macro_build (NULL
, "nop", "");
8420 move_register (op
[0], op
[1]);
8421 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
8422 if (mips_opts
.micromips
)
8423 micromips_add_label ();
8440 if (!mips_opts
.micromips
)
8442 if (imm_expr
.X_op
== O_constant
8443 && imm_expr
.X_add_number
>= -0x200
8444 && imm_expr
.X_add_number
< 0x200)
8446 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], imm_expr
.X_add_number
);
8455 if (imm_expr
.X_op
== O_constant
8456 && imm_expr
.X_add_number
>= -0x8000
8457 && imm_expr
.X_add_number
< 0x8000)
8459 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
8464 load_register (AT
, &imm_expr
, dbl
);
8465 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
8484 if (imm_expr
.X_op
== O_constant
8485 && imm_expr
.X_add_number
>= 0
8486 && imm_expr
.X_add_number
< 0x10000)
8488 if (mask
!= M_NOR_I
)
8489 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
8492 macro_build (&imm_expr
, "ori", "t,r,i",
8493 op
[0], op
[1], BFD_RELOC_LO16
);
8494 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
8500 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8501 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
8505 switch (imm_expr
.X_add_number
)
8508 macro_build (NULL
, "nop", "");
8511 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
8515 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
8516 (int) imm_expr
.X_add_number
);
8519 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
8520 (unsigned long) imm_expr
.X_add_number
);
8529 gas_assert (mips_opts
.micromips
);
8530 macro_build_branch_ccl (mask
, &offset_expr
,
8531 EXTRACT_OPERAND (1, BCC
, *ip
));
8538 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8544 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
8549 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
8556 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
8557 else if (op
[0] == 0)
8558 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
8562 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
8563 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8564 &offset_expr
, AT
, ZERO
);
8574 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
8580 /* Check for > max integer. */
8581 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8584 /* Result is always false. */
8586 macro_build (NULL
, "nop", "");
8588 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
8591 if (imm_expr
.X_op
!= O_constant
)
8592 as_bad (_("Unsupported large constant"));
8593 ++imm_expr
.X_add_number
;
8597 if (mask
== M_BGEL_I
)
8599 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8601 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
8602 &offset_expr
, op
[0]);
8605 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8607 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
8608 &offset_expr
, op
[0]);
8611 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
8614 /* result is always true */
8615 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
8616 macro_build (&offset_expr
, "b", "p");
8621 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8622 &offset_expr
, AT
, ZERO
);
8630 else if (op
[0] == 0)
8631 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8632 &offset_expr
, ZERO
, op
[1]);
8636 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
8637 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8638 &offset_expr
, AT
, ZERO
);
8647 && imm_expr
.X_op
== O_constant
8648 && imm_expr
.X_add_number
== -1))
8650 if (imm_expr
.X_op
!= O_constant
)
8651 as_bad (_("Unsupported large constant"));
8652 ++imm_expr
.X_add_number
;
8656 if (mask
== M_BGEUL_I
)
8658 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8660 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8661 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8662 &offset_expr
, op
[0], ZERO
);
8667 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8668 &offset_expr
, AT
, ZERO
);
8676 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
8677 else if (op
[0] == 0)
8678 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
8682 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
8683 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8684 &offset_expr
, AT
, ZERO
);
8692 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8693 &offset_expr
, op
[0], ZERO
);
8694 else if (op
[0] == 0)
8699 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
8700 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8701 &offset_expr
, AT
, ZERO
);
8709 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
8710 else if (op
[0] == 0)
8711 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
8715 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
8716 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8717 &offset_expr
, AT
, ZERO
);
8724 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
8726 if (imm_expr
.X_op
!= O_constant
)
8727 as_bad (_("Unsupported large constant"));
8728 ++imm_expr
.X_add_number
;
8732 if (mask
== M_BLTL_I
)
8734 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8735 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
8736 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8737 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
8742 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8743 &offset_expr
, AT
, ZERO
);
8751 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8752 &offset_expr
, op
[0], ZERO
);
8753 else if (op
[0] == 0)
8758 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
8759 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8760 &offset_expr
, AT
, ZERO
);
8769 && imm_expr
.X_op
== O_constant
8770 && imm_expr
.X_add_number
== -1))
8772 if (imm_expr
.X_op
!= O_constant
)
8773 as_bad (_("Unsupported large constant"));
8774 ++imm_expr
.X_add_number
;
8778 if (mask
== M_BLTUL_I
)
8780 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
8782 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
8783 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
8784 &offset_expr
, op
[0], ZERO
);
8789 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8790 &offset_expr
, AT
, ZERO
);
8798 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
8799 else if (op
[0] == 0)
8800 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
8804 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
8805 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8806 &offset_expr
, AT
, ZERO
);
8815 else if (op
[0] == 0)
8816 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8817 &offset_expr
, ZERO
, op
[1]);
8821 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
8822 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
8823 &offset_expr
, AT
, ZERO
);
8829 /* Use unsigned arithmetic. */
8833 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8835 as_bad (_("Unsupported large constant"));
8840 pos
= imm_expr
.X_add_number
;
8841 size
= imm2_expr
.X_add_number
;
8846 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8849 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8851 report_bad_field (pos
, size
);
8855 if (size
<= 32 && pos
< 32)
8860 else if (size
<= 32)
8870 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
8877 /* Use unsigned arithmetic. */
8881 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
8883 as_bad (_("Unsupported large constant"));
8888 pos
= imm_expr
.X_add_number
;
8889 size
= imm2_expr
.X_add_number
;
8894 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
8897 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
8899 report_bad_field (pos
, size
);
8903 if (pos
< 32 && (pos
+ size
- 1) < 32)
8918 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
8919 (int) (pos
+ size
- 1));
8935 as_warn (_("Divide by zero."));
8937 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
8939 macro_build (NULL
, "break", BRK_FMT
, 7);
8946 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
8947 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
8951 if (mips_opts
.micromips
)
8952 micromips_label_expr (&label_expr
);
8954 label_expr
.X_add_number
= 8;
8955 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
8956 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
8957 macro_build (NULL
, "break", BRK_FMT
, 7);
8958 if (mips_opts
.micromips
)
8959 micromips_add_label ();
8961 expr1
.X_add_number
= -1;
8963 load_register (AT
, &expr1
, dbl
);
8964 if (mips_opts
.micromips
)
8965 micromips_label_expr (&label_expr
);
8967 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
8968 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
8971 expr1
.X_add_number
= 1;
8972 load_register (AT
, &expr1
, dbl
);
8973 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
8977 expr1
.X_add_number
= 0x80000000;
8978 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
8982 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
8983 /* We want to close the noreorder block as soon as possible, so
8984 that later insns are available for delay slot filling. */
8989 if (mips_opts
.micromips
)
8990 micromips_label_expr (&label_expr
);
8992 label_expr
.X_add_number
= 8;
8993 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
8994 macro_build (NULL
, "nop", "");
8996 /* We want to close the noreorder block as soon as possible, so
8997 that later insns are available for delay slot filling. */
9000 macro_build (NULL
, "break", BRK_FMT
, 6);
9002 if (mips_opts
.micromips
)
9003 micromips_add_label ();
9004 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9043 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9045 as_warn (_("Divide by zero."));
9047 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9049 macro_build (NULL
, "break", BRK_FMT
, 7);
9052 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9054 if (strcmp (s2
, "mflo") == 0)
9055 move_register (op
[0], op
[1]);
9057 move_register (op
[0], ZERO
);
9060 if (imm_expr
.X_op
== O_constant
9061 && imm_expr
.X_add_number
== -1
9062 && s
[strlen (s
) - 1] != 'u')
9064 if (strcmp (s2
, "mflo") == 0)
9065 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9067 move_register (op
[0], ZERO
);
9072 load_register (AT
, &imm_expr
, dbl
);
9073 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9074 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9096 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9097 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9098 /* We want to close the noreorder block as soon as possible, so
9099 that later insns are available for delay slot filling. */
9104 if (mips_opts
.micromips
)
9105 micromips_label_expr (&label_expr
);
9107 label_expr
.X_add_number
= 8;
9108 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9109 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9111 /* We want to close the noreorder block as soon as possible, so
9112 that later insns are available for delay slot filling. */
9114 macro_build (NULL
, "break", BRK_FMT
, 7);
9115 if (mips_opts
.micromips
)
9116 micromips_add_label ();
9118 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9130 /* Load the address of a symbol into a register. If breg is not
9131 zero, we then add a base register to it. */
9134 if (dbl
&& HAVE_32BIT_GPRS
)
9135 as_warn (_("dla used to load 32-bit register"));
9137 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9138 as_warn (_("la used to load 64-bit address"));
9140 if (small_offset_p (0, align
, 16))
9142 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9143 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9147 if (mips_opts
.at
&& (op
[0] == breg
))
9155 if (offset_expr
.X_op
!= O_symbol
9156 && offset_expr
.X_op
!= O_constant
)
9158 as_bad (_("Expression too complex"));
9159 offset_expr
.X_op
= O_constant
;
9162 if (offset_expr
.X_op
== O_constant
)
9163 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9164 else if (mips_pic
== NO_PIC
)
9166 /* If this is a reference to a GP relative symbol, we want
9167 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9169 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9170 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9171 If we have a constant, we need two instructions anyhow,
9172 so we may as well always use the latter form.
9174 With 64bit address space and a usable $at we want
9175 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9176 lui $at,<sym> (BFD_RELOC_HI16_S)
9177 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9178 daddiu $at,<sym> (BFD_RELOC_LO16)
9180 daddu $tempreg,$tempreg,$at
9182 If $at is already in use, we use a path which is suboptimal
9183 on superscalar processors.
9184 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9185 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9187 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9189 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9191 For GP relative symbols in 64bit address space we can use
9192 the same sequence as in 32bit address space. */
9193 if (HAVE_64BIT_SYMBOLS
)
9195 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9196 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9198 relax_start (offset_expr
.X_add_symbol
);
9199 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9200 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9204 if (used_at
== 0 && mips_opts
.at
)
9206 macro_build (&offset_expr
, "lui", LUI_FMT
,
9207 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9208 macro_build (&offset_expr
, "lui", LUI_FMT
,
9209 AT
, BFD_RELOC_HI16_S
);
9210 macro_build (&offset_expr
, "daddiu", "t,r,j",
9211 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9212 macro_build (&offset_expr
, "daddiu", "t,r,j",
9213 AT
, AT
, BFD_RELOC_LO16
);
9214 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9215 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9220 macro_build (&offset_expr
, "lui", LUI_FMT
,
9221 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9222 macro_build (&offset_expr
, "daddiu", "t,r,j",
9223 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9224 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9225 macro_build (&offset_expr
, "daddiu", "t,r,j",
9226 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9227 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9228 macro_build (&offset_expr
, "daddiu", "t,r,j",
9229 tempreg
, tempreg
, BFD_RELOC_LO16
);
9232 if (mips_relax
.sequence
)
9237 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9238 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9240 relax_start (offset_expr
.X_add_symbol
);
9241 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9242 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9245 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9246 as_bad (_("Offset too large"));
9247 macro_build_lui (&offset_expr
, tempreg
);
9248 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9249 tempreg
, tempreg
, BFD_RELOC_LO16
);
9250 if (mips_relax
.sequence
)
9254 else if (!mips_big_got
&& !HAVE_NEWABI
)
9256 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9258 /* If this is a reference to an external symbol, and there
9259 is no constant, we want
9260 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9261 or for lca or if tempreg is PIC_CALL_REG
9262 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9263 For a local symbol, we want
9264 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9266 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9268 If we have a small constant, and this is a reference to
9269 an external symbol, we want
9270 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9272 addiu $tempreg,$tempreg,<constant>
9273 For a local symbol, we want the same instruction
9274 sequence, but we output a BFD_RELOC_LO16 reloc on the
9277 If we have a large constant, and this is a reference to
9278 an external symbol, we want
9279 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9280 lui $at,<hiconstant>
9281 addiu $at,$at,<loconstant>
9282 addu $tempreg,$tempreg,$at
9283 For a local symbol, we want the same instruction
9284 sequence, but we output a BFD_RELOC_LO16 reloc on the
9288 if (offset_expr
.X_add_number
== 0)
9290 if (mips_pic
== SVR4_PIC
9292 && (call
|| tempreg
== PIC_CALL_REG
))
9293 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9295 relax_start (offset_expr
.X_add_symbol
);
9296 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9297 lw_reloc_type
, mips_gp_register
);
9300 /* We're going to put in an addu instruction using
9301 tempreg, so we may as well insert the nop right
9306 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9307 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9309 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9310 tempreg
, tempreg
, BFD_RELOC_LO16
);
9312 /* FIXME: If breg == 0, and the next instruction uses
9313 $tempreg, then if this variant case is used an extra
9314 nop will be generated. */
9316 else if (offset_expr
.X_add_number
>= -0x8000
9317 && offset_expr
.X_add_number
< 0x8000)
9319 load_got_offset (tempreg
, &offset_expr
);
9321 add_got_offset (tempreg
, &offset_expr
);
9325 expr1
.X_add_number
= offset_expr
.X_add_number
;
9326 offset_expr
.X_add_number
=
9327 SEXT_16BIT (offset_expr
.X_add_number
);
9328 load_got_offset (tempreg
, &offset_expr
);
9329 offset_expr
.X_add_number
= expr1
.X_add_number
;
9330 /* If we are going to add in a base register, and the
9331 target register and the base register are the same,
9332 then we are using AT as a temporary register. Since
9333 we want to load the constant into AT, we add our
9334 current AT (from the global offset table) and the
9335 register into the register now, and pretend we were
9336 not using a base register. */
9340 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9345 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
9349 else if (!mips_big_got
&& HAVE_NEWABI
)
9351 int add_breg_early
= 0;
9353 /* If this is a reference to an external, and there is no
9354 constant, or local symbol (*), with or without a
9356 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9357 or for lca or if tempreg is PIC_CALL_REG
9358 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9360 If we have a small constant, and this is a reference to
9361 an external symbol, we want
9362 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9363 addiu $tempreg,$tempreg,<constant>
9365 If we have a large constant, and this is a reference to
9366 an external symbol, we want
9367 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9368 lui $at,<hiconstant>
9369 addiu $at,$at,<loconstant>
9370 addu $tempreg,$tempreg,$at
9372 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9373 local symbols, even though it introduces an additional
9376 if (offset_expr
.X_add_number
)
9378 expr1
.X_add_number
= offset_expr
.X_add_number
;
9379 offset_expr
.X_add_number
= 0;
9381 relax_start (offset_expr
.X_add_symbol
);
9382 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9383 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9385 if (expr1
.X_add_number
>= -0x8000
9386 && expr1
.X_add_number
< 0x8000)
9388 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9389 tempreg
, tempreg
, BFD_RELOC_LO16
);
9391 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9395 /* If we are going to add in a base register, and the
9396 target register and the base register are the same,
9397 then we are using AT as a temporary register. Since
9398 we want to load the constant into AT, we add our
9399 current AT (from the global offset table) and the
9400 register into the register now, and pretend we were
9401 not using a base register. */
9406 gas_assert (tempreg
== AT
);
9407 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9413 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9414 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9420 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9423 offset_expr
.X_add_number
= expr1
.X_add_number
;
9425 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9426 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9429 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9430 op
[0], tempreg
, breg
);
9436 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
9438 relax_start (offset_expr
.X_add_symbol
);
9439 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9440 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
9442 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9443 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9448 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9449 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9452 else if (mips_big_got
&& !HAVE_NEWABI
)
9455 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9456 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9457 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9459 /* This is the large GOT case. If this is a reference to an
9460 external symbol, and there is no constant, we want
9461 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9462 addu $tempreg,$tempreg,$gp
9463 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9464 or for lca or if tempreg is PIC_CALL_REG
9465 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9466 addu $tempreg,$tempreg,$gp
9467 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9468 For a local symbol, we want
9469 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9471 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9473 If we have a small constant, and this is a reference to
9474 an external symbol, we want
9475 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9476 addu $tempreg,$tempreg,$gp
9477 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9479 addiu $tempreg,$tempreg,<constant>
9480 For a local symbol, we want
9481 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9483 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
9485 If we have a large constant, and this is a reference to
9486 an external symbol, we want
9487 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9488 addu $tempreg,$tempreg,$gp
9489 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9490 lui $at,<hiconstant>
9491 addiu $at,$at,<loconstant>
9492 addu $tempreg,$tempreg,$at
9493 For a local symbol, we want
9494 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9495 lui $at,<hiconstant>
9496 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
9497 addu $tempreg,$tempreg,$at
9500 expr1
.X_add_number
= offset_expr
.X_add_number
;
9501 offset_expr
.X_add_number
= 0;
9502 relax_start (offset_expr
.X_add_symbol
);
9503 gpdelay
= reg_needs_delay (mips_gp_register
);
9504 if (expr1
.X_add_number
== 0 && breg
== 0
9505 && (call
|| tempreg
== PIC_CALL_REG
))
9507 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9508 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9510 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9511 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9512 tempreg
, tempreg
, mips_gp_register
);
9513 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9514 tempreg
, lw_reloc_type
, tempreg
);
9515 if (expr1
.X_add_number
== 0)
9519 /* We're going to put in an addu instruction using
9520 tempreg, so we may as well insert the nop right
9525 else if (expr1
.X_add_number
>= -0x8000
9526 && expr1
.X_add_number
< 0x8000)
9529 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9530 tempreg
, tempreg
, BFD_RELOC_LO16
);
9536 /* If we are going to add in a base register, and the
9537 target register and the base register are the same,
9538 then we are using AT as a temporary register. Since
9539 we want to load the constant into AT, we add our
9540 current AT (from the global offset table) and the
9541 register into the register now, and pretend we were
9542 not using a base register. */
9547 gas_assert (tempreg
== AT
);
9549 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9554 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9555 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9559 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
9564 /* This is needed because this instruction uses $gp, but
9565 the first instruction on the main stream does not. */
9566 macro_build (NULL
, "nop", "");
9569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9570 local_reloc_type
, mips_gp_register
);
9571 if (expr1
.X_add_number
>= -0x8000
9572 && expr1
.X_add_number
< 0x8000)
9575 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9576 tempreg
, tempreg
, BFD_RELOC_LO16
);
9577 /* FIXME: If add_number is 0, and there was no base
9578 register, the external symbol case ended with a load,
9579 so if the symbol turns out to not be external, and
9580 the next instruction uses tempreg, an unnecessary nop
9581 will be inserted. */
9587 /* We must add in the base register now, as in the
9588 external symbol case. */
9589 gas_assert (tempreg
== AT
);
9591 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9594 /* We set breg to 0 because we have arranged to add
9595 it in in both cases. */
9599 macro_build_lui (&expr1
, AT
);
9600 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9601 AT
, AT
, BFD_RELOC_LO16
);
9602 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9603 tempreg
, tempreg
, AT
);
9608 else if (mips_big_got
&& HAVE_NEWABI
)
9610 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
9611 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
9612 int add_breg_early
= 0;
9614 /* This is the large GOT case. If this is a reference to an
9615 external symbol, and there is no constant, we want
9616 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9617 add $tempreg,$tempreg,$gp
9618 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9619 or for lca or if tempreg is PIC_CALL_REG
9620 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9621 add $tempreg,$tempreg,$gp
9622 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
9624 If we have a small constant, and this is a reference to
9625 an external symbol, we want
9626 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9627 add $tempreg,$tempreg,$gp
9628 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9629 addi $tempreg,$tempreg,<constant>
9631 If we have a large constant, and this is a reference to
9632 an external symbol, we want
9633 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9634 addu $tempreg,$tempreg,$gp
9635 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9636 lui $at,<hiconstant>
9637 addi $at,$at,<loconstant>
9638 add $tempreg,$tempreg,$at
9640 If we have NewABI, and we know it's a local symbol, we want
9641 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9642 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9643 otherwise we have to resort to GOT_HI16/GOT_LO16. */
9645 relax_start (offset_expr
.X_add_symbol
);
9647 expr1
.X_add_number
= offset_expr
.X_add_number
;
9648 offset_expr
.X_add_number
= 0;
9650 if (expr1
.X_add_number
== 0 && breg
== 0
9651 && (call
|| tempreg
== PIC_CALL_REG
))
9653 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
9654 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
9656 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
9657 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9658 tempreg
, tempreg
, mips_gp_register
);
9659 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9660 tempreg
, lw_reloc_type
, tempreg
);
9662 if (expr1
.X_add_number
== 0)
9664 else if (expr1
.X_add_number
>= -0x8000
9665 && expr1
.X_add_number
< 0x8000)
9667 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
9668 tempreg
, tempreg
, BFD_RELOC_LO16
);
9670 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
9674 /* If we are going to add in a base register, and the
9675 target register and the base register are the same,
9676 then we are using AT as a temporary register. Since
9677 we want to load the constant into AT, we add our
9678 current AT (from the global offset table) and the
9679 register into the register now, and pretend we were
9680 not using a base register. */
9685 gas_assert (tempreg
== AT
);
9686 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9692 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
9693 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
9698 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9701 offset_expr
.X_add_number
= expr1
.X_add_number
;
9702 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9703 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9704 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9705 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
9708 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9709 op
[0], tempreg
, breg
);
9719 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
9723 gas_assert (!mips_opts
.micromips
);
9724 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
9728 gas_assert (!mips_opts
.micromips
);
9729 macro_build (NULL
, "c2", "C", 0x02);
9733 gas_assert (!mips_opts
.micromips
);
9734 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
9738 gas_assert (!mips_opts
.micromips
);
9739 macro_build (NULL
, "c2", "C", 3);
9743 gas_assert (!mips_opts
.micromips
);
9744 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
9748 /* The j instruction may not be used in PIC code, since it
9749 requires an absolute address. We convert it to a b
9751 if (mips_pic
== NO_PIC
)
9752 macro_build (&offset_expr
, "j", "a");
9754 macro_build (&offset_expr
, "b", "p");
9757 /* The jal instructions must be handled as macros because when
9758 generating PIC code they expand to multi-instruction
9759 sequences. Normally they are simple instructions. */
9765 gas_assert (mips_opts
.micromips
);
9766 if (mips_opts
.insn32
)
9768 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9779 if (mips_pic
== NO_PIC
)
9781 s
= jals
? "jalrs" : "jalr";
9782 if (mips_opts
.micromips
9783 && !mips_opts
.insn32
9785 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9786 macro_build (NULL
, s
, "mj", op
[1]);
9788 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
9792 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
9793 && mips_cprestore_offset
>= 0);
9795 if (op
[1] != PIC_CALL_REG
)
9796 as_warn (_("MIPS PIC call to register other than $25"));
9798 s
= ((mips_opts
.micromips
9799 && !mips_opts
.insn32
9800 && (!mips_opts
.noreorder
|| cprestore
))
9801 ? "jalrs" : "jalr");
9802 if (mips_opts
.micromips
9803 && !mips_opts
.insn32
9805 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9806 macro_build (NULL
, s
, "mj", op
[1]);
9808 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
9809 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
9811 if (mips_cprestore_offset
< 0)
9812 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9815 if (!mips_frame_reg_valid
)
9817 as_warn (_("No .frame pseudo-op used in PIC code"));
9818 /* Quiet this warning. */
9819 mips_frame_reg_valid
= 1;
9821 if (!mips_cprestore_valid
)
9823 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9824 /* Quiet this warning. */
9825 mips_cprestore_valid
= 1;
9827 if (mips_opts
.noreorder
)
9828 macro_build (NULL
, "nop", "");
9829 expr1
.X_add_number
= mips_cprestore_offset
;
9830 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9833 HAVE_64BIT_ADDRESSES
);
9841 gas_assert (mips_opts
.micromips
);
9842 if (mips_opts
.insn32
)
9844 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
9850 if (mips_pic
== NO_PIC
)
9851 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
9852 else if (mips_pic
== SVR4_PIC
)
9854 /* If this is a reference to an external symbol, and we are
9855 using a small GOT, we want
9856 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9860 lw $gp,cprestore($sp)
9861 The cprestore value is set using the .cprestore
9862 pseudo-op. If we are using a big GOT, we want
9863 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
9865 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
9869 lw $gp,cprestore($sp)
9870 If the symbol is not external, we want
9871 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9873 addiu $25,$25,<sym> (BFD_RELOC_LO16)
9876 lw $gp,cprestore($sp)
9878 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
9879 sequences above, minus nops, unless the symbol is local,
9880 which enables us to use GOT_PAGE/GOT_OFST (big got) or
9886 relax_start (offset_expr
.X_add_symbol
);
9887 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9888 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9891 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9892 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
9898 relax_start (offset_expr
.X_add_symbol
);
9899 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9900 BFD_RELOC_MIPS_CALL_HI16
);
9901 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9902 PIC_CALL_REG
, mips_gp_register
);
9903 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9904 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9907 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9908 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
9910 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9911 PIC_CALL_REG
, PIC_CALL_REG
,
9912 BFD_RELOC_MIPS_GOT_OFST
);
9916 macro_build_jalr (&offset_expr
, 0);
9920 relax_start (offset_expr
.X_add_symbol
);
9923 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9924 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
9933 gpdelay
= reg_needs_delay (mips_gp_register
);
9934 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
9935 BFD_RELOC_MIPS_CALL_HI16
);
9936 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
9937 PIC_CALL_REG
, mips_gp_register
);
9938 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9939 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
9944 macro_build (NULL
, "nop", "");
9946 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9947 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
9950 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9951 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
9953 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
9955 if (mips_cprestore_offset
< 0)
9956 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9959 if (!mips_frame_reg_valid
)
9961 as_warn (_("No .frame pseudo-op used in PIC code"));
9962 /* Quiet this warning. */
9963 mips_frame_reg_valid
= 1;
9965 if (!mips_cprestore_valid
)
9967 as_warn (_("No .cprestore pseudo-op used in PIC code"));
9968 /* Quiet this warning. */
9969 mips_cprestore_valid
= 1;
9971 if (mips_opts
.noreorder
)
9972 macro_build (NULL
, "nop", "");
9973 expr1
.X_add_number
= mips_cprestore_offset
;
9974 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
9977 HAVE_64BIT_ADDRESSES
);
9981 else if (mips_pic
== VXWORKS_PIC
)
9982 as_bad (_("Non-PIC jump used in PIC library"));
10089 gas_assert (!mips_opts
.micromips
);
10092 /* Itbl support may require additional care here. */
10098 /* Itbl support may require additional care here. */
10104 offbits
= (mips_opts
.micromips
? 12 : 16);
10105 /* Itbl support may require additional care here. */
10109 gas_assert (!mips_opts
.micromips
);
10112 /* Itbl support may require additional care here. */
10118 offbits
= (mips_opts
.micromips
? 12 : 16);
10123 offbits
= (mips_opts
.micromips
? 12 : 16);
10128 /* Itbl support may require additional care here. */
10134 offbits
= (mips_opts
.micromips
? 12 : 16);
10135 /* Itbl support may require additional care here. */
10141 /* Itbl support may require additional care here. */
10147 /* Itbl support may require additional care here. */
10153 offbits
= (mips_opts
.micromips
? 12 : 16);
10158 offbits
= (mips_opts
.micromips
? 12 : 16);
10163 offbits
= (mips_opts
.micromips
? 12 : 16);
10168 offbits
= (mips_opts
.micromips
? 12 : 16);
10173 offbits
= (mips_opts
.micromips
? 12 : 16);
10176 gas_assert (mips_opts
.micromips
);
10183 gas_assert (mips_opts
.micromips
);
10190 gas_assert (mips_opts
.micromips
);
10196 gas_assert (mips_opts
.micromips
);
10203 /* We don't want to use $0 as tempreg. */
10204 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10207 tempreg
= op
[0] + lp
;
10223 gas_assert (!mips_opts
.micromips
);
10226 /* Itbl support may require additional care here. */
10232 /* Itbl support may require additional care here. */
10238 offbits
= (mips_opts
.micromips
? 12 : 16);
10239 /* Itbl support may require additional care here. */
10243 gas_assert (!mips_opts
.micromips
);
10246 /* Itbl support may require additional care here. */
10252 offbits
= (mips_opts
.micromips
? 12 : 16);
10257 offbits
= (mips_opts
.micromips
? 12 : 16);
10262 offbits
= (mips_opts
.micromips
? 12 : 16);
10267 offbits
= (mips_opts
.micromips
? 12 : 16);
10271 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10272 offbits
= (mips_opts
.micromips
? 12 : 16);
10281 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10282 offbits
= (mips_opts
.micromips
? 12 : 16);
10293 /* Itbl support may require additional care here. */
10298 offbits
= (mips_opts
.micromips
? 12 : 16);
10299 /* Itbl support may require additional care here. */
10305 /* Itbl support may require additional care here. */
10309 gas_assert (!mips_opts
.micromips
);
10312 /* Itbl support may require additional care here. */
10318 offbits
= (mips_opts
.micromips
? 12 : 16);
10323 offbits
= (mips_opts
.micromips
? 12 : 16);
10326 gas_assert (mips_opts
.micromips
);
10332 gas_assert (mips_opts
.micromips
);
10338 gas_assert (mips_opts
.micromips
);
10344 gas_assert (mips_opts
.micromips
);
10353 if (small_offset_p (0, align
, 16))
10355 /* The first case exists for M_LD_AB and M_SD_AB, which are
10356 macros for o32 but which should act like normal instructions
10359 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
10360 offset_reloc
[1], offset_reloc
[2], breg
);
10361 else if (small_offset_p (0, align
, offbits
))
10364 macro_build (NULL
, s
, fmt
, op
[0], breg
);
10366 macro_build (NULL
, s
, fmt
, op
[0],
10367 (int) offset_expr
.X_add_number
, breg
);
10373 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10374 tempreg
, breg
, -1, offset_reloc
[0],
10375 offset_reloc
[1], offset_reloc
[2]);
10377 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10379 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
10387 if (offset_expr
.X_op
!= O_constant
10388 && offset_expr
.X_op
!= O_symbol
)
10390 as_bad (_("Expression too complex"));
10391 offset_expr
.X_op
= O_constant
;
10394 if (HAVE_32BIT_ADDRESSES
10395 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10399 sprintf_vma (value
, offset_expr
.X_add_number
);
10400 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
10403 /* A constant expression in PIC code can be handled just as it
10404 is in non PIC code. */
10405 if (offset_expr
.X_op
== O_constant
)
10407 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
10408 offbits
== 0 ? 16 : offbits
);
10409 offset_expr
.X_add_number
-= expr1
.X_add_number
;
10411 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
10413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10414 tempreg
, tempreg
, breg
);
10417 if (offset_expr
.X_add_number
!= 0)
10418 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
10419 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
10420 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10422 else if (offbits
== 16)
10423 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10425 macro_build (NULL
, s
, fmt
, op
[0],
10426 (int) offset_expr
.X_add_number
, tempreg
);
10428 else if (offbits
!= 16)
10430 /* The offset field is too narrow to be used for a low-part
10431 relocation, so load the whole address into the auxillary
10433 load_address (tempreg
, &offset_expr
, &used_at
);
10435 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10436 tempreg
, tempreg
, breg
);
10438 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
10440 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
10442 else if (mips_pic
== NO_PIC
)
10444 /* If this is a reference to a GP relative symbol, and there
10445 is no base register, we want
10446 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
10447 Otherwise, if there is no base register, we want
10448 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10449 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10450 If we have a constant, we need two instructions anyhow,
10451 so we always use the latter form.
10453 If we have a base register, and this is a reference to a
10454 GP relative symbol, we want
10455 addu $tempreg,$breg,$gp
10456 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
10458 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10459 addu $tempreg,$tempreg,$breg
10460 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10461 With a constant we always use the latter case.
10463 With 64bit address space and no base register and $at usable,
10465 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10466 lui $at,<sym> (BFD_RELOC_HI16_S)
10467 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10470 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10471 If we have a base register, we want
10472 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10473 lui $at,<sym> (BFD_RELOC_HI16_S)
10474 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10478 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10480 Without $at we can't generate the optimal path for superscalar
10481 processors here since this would require two temporary registers.
10482 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10483 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10485 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10487 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10488 If we have a base register, we want
10489 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10490 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10492 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10494 daddu $tempreg,$tempreg,$breg
10495 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
10497 For GP relative symbols in 64bit address space we can use
10498 the same sequence as in 32bit address space. */
10499 if (HAVE_64BIT_SYMBOLS
)
10501 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10502 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10504 relax_start (offset_expr
.X_add_symbol
);
10507 macro_build (&offset_expr
, s
, fmt
, op
[0],
10508 BFD_RELOC_GPREL16
, mips_gp_register
);
10512 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10513 tempreg
, breg
, mips_gp_register
);
10514 macro_build (&offset_expr
, s
, fmt
, op
[0],
10515 BFD_RELOC_GPREL16
, tempreg
);
10520 if (used_at
== 0 && mips_opts
.at
)
10522 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10523 BFD_RELOC_MIPS_HIGHEST
);
10524 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
10526 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10527 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10529 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
10530 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10531 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10532 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
10538 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10539 BFD_RELOC_MIPS_HIGHEST
);
10540 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10541 tempreg
, BFD_RELOC_MIPS_HIGHER
);
10542 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10543 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
10544 tempreg
, BFD_RELOC_HI16_S
);
10545 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10547 macro_build (NULL
, "daddu", "d,v,t",
10548 tempreg
, tempreg
, breg
);
10549 macro_build (&offset_expr
, s
, fmt
, op
[0],
10550 BFD_RELOC_LO16
, tempreg
);
10553 if (mips_relax
.sequence
)
10560 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10561 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10563 relax_start (offset_expr
.X_add_symbol
);
10564 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
10568 macro_build_lui (&offset_expr
, tempreg
);
10569 macro_build (&offset_expr
, s
, fmt
, op
[0],
10570 BFD_RELOC_LO16
, tempreg
);
10571 if (mips_relax
.sequence
)
10576 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10577 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10579 relax_start (offset_expr
.X_add_symbol
);
10580 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10581 tempreg
, breg
, mips_gp_register
);
10582 macro_build (&offset_expr
, s
, fmt
, op
[0],
10583 BFD_RELOC_GPREL16
, tempreg
);
10586 macro_build_lui (&offset_expr
, tempreg
);
10587 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10588 tempreg
, tempreg
, breg
);
10589 macro_build (&offset_expr
, s
, fmt
, op
[0],
10590 BFD_RELOC_LO16
, tempreg
);
10591 if (mips_relax
.sequence
)
10595 else if (!mips_big_got
)
10597 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10599 /* If this is a reference to an external symbol, we want
10600 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10602 <op> op[0],0($tempreg)
10604 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10606 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10607 <op> op[0],0($tempreg)
10609 For NewABI, we want
10610 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10611 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
10613 If there is a base register, we add it to $tempreg before
10614 the <op>. If there is a constant, we stick it in the
10615 <op> instruction. We don't handle constants larger than
10616 16 bits, because we have no way to load the upper 16 bits
10617 (actually, we could handle them for the subset of cases
10618 in which we are not using $at). */
10619 gas_assert (offset_expr
.X_op
== O_symbol
);
10622 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10623 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10625 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10626 tempreg
, tempreg
, breg
);
10627 macro_build (&offset_expr
, s
, fmt
, op
[0],
10628 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10631 expr1
.X_add_number
= offset_expr
.X_add_number
;
10632 offset_expr
.X_add_number
= 0;
10633 if (expr1
.X_add_number
< -0x8000
10634 || expr1
.X_add_number
>= 0x8000)
10635 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10637 lw_reloc_type
, mips_gp_register
);
10639 relax_start (offset_expr
.X_add_symbol
);
10641 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10642 tempreg
, BFD_RELOC_LO16
);
10645 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10646 tempreg
, tempreg
, breg
);
10647 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10649 else if (mips_big_got
&& !HAVE_NEWABI
)
10653 /* If this is a reference to an external symbol, we want
10654 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10655 addu $tempreg,$tempreg,$gp
10656 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10657 <op> op[0],0($tempreg)
10659 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10661 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10662 <op> op[0],0($tempreg)
10663 If there is a base register, we add it to $tempreg before
10664 the <op>. If there is a constant, we stick it in the
10665 <op> instruction. We don't handle constants larger than
10666 16 bits, because we have no way to load the upper 16 bits
10667 (actually, we could handle them for the subset of cases
10668 in which we are not using $at). */
10669 gas_assert (offset_expr
.X_op
== O_symbol
);
10670 expr1
.X_add_number
= offset_expr
.X_add_number
;
10671 offset_expr
.X_add_number
= 0;
10672 if (expr1
.X_add_number
< -0x8000
10673 || expr1
.X_add_number
>= 0x8000)
10674 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10675 gpdelay
= reg_needs_delay (mips_gp_register
);
10676 relax_start (offset_expr
.X_add_symbol
);
10677 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10678 BFD_RELOC_MIPS_GOT_HI16
);
10679 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10681 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10682 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10685 macro_build (NULL
, "nop", "");
10686 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10687 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10689 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10690 tempreg
, BFD_RELOC_LO16
);
10694 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10695 tempreg
, tempreg
, breg
);
10696 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10698 else if (mips_big_got
&& HAVE_NEWABI
)
10700 /* If this is a reference to an external symbol, we want
10701 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10702 add $tempreg,$tempreg,$gp
10703 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10704 <op> op[0],<ofst>($tempreg)
10705 Otherwise, for local symbols, we want:
10706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10707 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
10708 gas_assert (offset_expr
.X_op
== O_symbol
);
10709 expr1
.X_add_number
= offset_expr
.X_add_number
;
10710 offset_expr
.X_add_number
= 0;
10711 if (expr1
.X_add_number
< -0x8000
10712 || expr1
.X_add_number
>= 0x8000)
10713 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10714 relax_start (offset_expr
.X_add_symbol
);
10715 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
10716 BFD_RELOC_MIPS_GOT_HI16
);
10717 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
10719 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10720 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
10722 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10723 tempreg
, tempreg
, breg
);
10724 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
10727 offset_expr
.X_add_number
= expr1
.X_add_number
;
10728 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10729 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10731 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10732 tempreg
, tempreg
, breg
);
10733 macro_build (&offset_expr
, s
, fmt
, op
[0],
10734 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
10743 gas_assert (mips_opts
.micromips
);
10744 gas_assert (mips_opts
.insn32
);
10745 start_noreorder ();
10746 macro_build (NULL
, "jr", "s", RA
);
10747 expr1
.X_add_number
= op
[0] << 2;
10748 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
10753 gas_assert (mips_opts
.micromips
);
10754 gas_assert (mips_opts
.insn32
);
10755 macro_build (NULL
, "jr", "s", op
[0]);
10756 if (mips_opts
.noreorder
)
10757 macro_build (NULL
, "nop", "");
10762 load_register (op
[0], &imm_expr
, 0);
10766 load_register (op
[0], &imm_expr
, 1);
10770 if (imm_expr
.X_op
== O_constant
)
10773 load_register (AT
, &imm_expr
, 0);
10774 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
10779 gas_assert (offset_expr
.X_op
== O_symbol
10780 && strcmp (segment_name (S_GET_SEGMENT
10781 (offset_expr
.X_add_symbol
)),
10783 && offset_expr
.X_add_number
== 0);
10784 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
10785 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
10790 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
10791 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
10792 order 32 bits of the value and the low order 32 bits are either
10793 zero or in OFFSET_EXPR. */
10794 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10796 if (HAVE_64BIT_GPRS
)
10797 load_register (op
[0], &imm_expr
, 1);
10802 if (target_big_endian
)
10814 load_register (hreg
, &imm_expr
, 0);
10817 if (offset_expr
.X_op
== O_absent
)
10818 move_register (lreg
, 0);
10821 gas_assert (offset_expr
.X_op
== O_constant
);
10822 load_register (lreg
, &offset_expr
, 0);
10829 /* We know that sym is in the .rdata section. First we get the
10830 upper 16 bits of the address. */
10831 if (mips_pic
== NO_PIC
)
10833 macro_build_lui (&offset_expr
, AT
);
10838 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10839 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10843 /* Now we load the register(s). */
10844 if (HAVE_64BIT_GPRS
)
10847 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
10848 BFD_RELOC_LO16
, AT
);
10853 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
10854 BFD_RELOC_LO16
, AT
);
10857 /* FIXME: How in the world do we deal with the possible
10859 offset_expr
.X_add_number
+= 4;
10860 macro_build (&offset_expr
, "lw", "t,o(b)",
10861 op
[0] + 1, BFD_RELOC_LO16
, AT
);
10867 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
10868 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
10869 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
10870 the value and the low order 32 bits are either zero or in
10872 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
10875 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
10876 if (HAVE_64BIT_FPRS
)
10878 gas_assert (HAVE_64BIT_GPRS
);
10879 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
10883 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
10884 if (offset_expr
.X_op
== O_absent
)
10885 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
10888 gas_assert (offset_expr
.X_op
== O_constant
);
10889 load_register (AT
, &offset_expr
, 0);
10890 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
10896 gas_assert (offset_expr
.X_op
== O_symbol
10897 && offset_expr
.X_add_number
== 0);
10898 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
10899 if (strcmp (s
, ".lit8") == 0)
10901 op
[2] = mips_gp_register
;
10902 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
10903 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10904 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10908 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
10910 if (mips_pic
!= NO_PIC
)
10911 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
10912 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10915 /* FIXME: This won't work for a 64 bit address. */
10916 macro_build_lui (&offset_expr
, AT
);
10920 offset_reloc
[0] = BFD_RELOC_LO16
;
10921 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10922 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10929 * The MIPS assembler seems to check for X_add_number not
10930 * being double aligned and generating:
10931 * lui at,%hi(foo+1)
10933 * addiu at,at,%lo(foo+1)
10936 * But, the resulting address is the same after relocation so why
10937 * generate the extra instruction?
10939 /* Itbl support may require additional care here. */
10942 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10951 gas_assert (!mips_opts
.micromips
);
10952 /* Itbl support may require additional care here. */
10955 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
10975 if (HAVE_64BIT_GPRS
)
10985 if (HAVE_64BIT_GPRS
)
10993 /* Even on a big endian machine $fn comes before $fn+1. We have
10994 to adjust when loading from memory. We set coproc if we must
10995 load $fn+1 first. */
10996 /* Itbl support may require additional care here. */
10997 if (!target_big_endian
)
11001 if (small_offset_p (0, align
, 16))
11004 if (!small_offset_p (4, align
, 16))
11006 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11007 -1, offset_reloc
[0], offset_reloc
[1],
11009 expr1
.X_add_number
= 0;
11013 offset_reloc
[0] = BFD_RELOC_LO16
;
11014 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11015 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11017 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11019 ep
->X_add_number
+= 4;
11020 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11021 offset_reloc
[1], offset_reloc
[2], breg
);
11022 ep
->X_add_number
-= 4;
11023 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11024 offset_reloc
[1], offset_reloc
[2], breg
);
11028 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11029 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11031 ep
->X_add_number
+= 4;
11032 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11033 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11039 if (offset_expr
.X_op
!= O_symbol
11040 && offset_expr
.X_op
!= O_constant
)
11042 as_bad (_("Expression too complex"));
11043 offset_expr
.X_op
= O_constant
;
11046 if (HAVE_32BIT_ADDRESSES
11047 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11051 sprintf_vma (value
, offset_expr
.X_add_number
);
11052 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11055 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11057 /* If this is a reference to a GP relative symbol, we want
11058 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11059 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11060 If we have a base register, we use this
11062 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11063 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11064 If this is not a GP relative symbol, we want
11065 lui $at,<sym> (BFD_RELOC_HI16_S)
11066 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11067 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11068 If there is a base register, we add it to $at after the
11069 lui instruction. If there is a constant, we always use
11071 if (offset_expr
.X_op
== O_symbol
11072 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11073 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11075 relax_start (offset_expr
.X_add_symbol
);
11078 tempreg
= mips_gp_register
;
11082 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11083 AT
, breg
, mips_gp_register
);
11088 /* Itbl support may require additional care here. */
11089 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11090 BFD_RELOC_GPREL16
, tempreg
);
11091 offset_expr
.X_add_number
+= 4;
11093 /* Set mips_optimize to 2 to avoid inserting an
11095 hold_mips_optimize
= mips_optimize
;
11097 /* Itbl support may require additional care here. */
11098 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11099 BFD_RELOC_GPREL16
, tempreg
);
11100 mips_optimize
= hold_mips_optimize
;
11104 offset_expr
.X_add_number
-= 4;
11107 if (offset_high_part (offset_expr
.X_add_number
, 16)
11108 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11110 load_address (AT
, &offset_expr
, &used_at
);
11111 offset_expr
.X_op
= O_constant
;
11112 offset_expr
.X_add_number
= 0;
11115 macro_build_lui (&offset_expr
, AT
);
11117 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11118 /* Itbl support may require additional care here. */
11119 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11120 BFD_RELOC_LO16
, AT
);
11121 /* FIXME: How do we handle overflow here? */
11122 offset_expr
.X_add_number
+= 4;
11123 /* Itbl support may require additional care here. */
11124 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11125 BFD_RELOC_LO16
, AT
);
11126 if (mips_relax
.sequence
)
11129 else if (!mips_big_got
)
11131 /* If this is a reference to an external symbol, we want
11132 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11135 <op> op[0]+1,4($at)
11137 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11139 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11140 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11141 If there is a base register we add it to $at before the
11142 lwc1 instructions. If there is a constant we include it
11143 in the lwc1 instructions. */
11145 expr1
.X_add_number
= offset_expr
.X_add_number
;
11146 if (expr1
.X_add_number
< -0x8000
11147 || expr1
.X_add_number
>= 0x8000 - 4)
11148 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11149 load_got_offset (AT
, &offset_expr
);
11152 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11154 /* Set mips_optimize to 2 to avoid inserting an undesired
11156 hold_mips_optimize
= mips_optimize
;
11159 /* Itbl support may require additional care here. */
11160 relax_start (offset_expr
.X_add_symbol
);
11161 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11162 BFD_RELOC_LO16
, AT
);
11163 expr1
.X_add_number
+= 4;
11164 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11165 BFD_RELOC_LO16
, AT
);
11167 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11168 BFD_RELOC_LO16
, AT
);
11169 offset_expr
.X_add_number
+= 4;
11170 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11171 BFD_RELOC_LO16
, AT
);
11174 mips_optimize
= hold_mips_optimize
;
11176 else if (mips_big_got
)
11180 /* If this is a reference to an external symbol, we want
11181 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11183 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11186 <op> op[0]+1,4($at)
11188 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11190 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11191 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11192 If there is a base register we add it to $at before the
11193 lwc1 instructions. If there is a constant we include it
11194 in the lwc1 instructions. */
11196 expr1
.X_add_number
= offset_expr
.X_add_number
;
11197 offset_expr
.X_add_number
= 0;
11198 if (expr1
.X_add_number
< -0x8000
11199 || expr1
.X_add_number
>= 0x8000 - 4)
11200 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11201 gpdelay
= reg_needs_delay (mips_gp_register
);
11202 relax_start (offset_expr
.X_add_symbol
);
11203 macro_build (&offset_expr
, "lui", LUI_FMT
,
11204 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11205 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11206 AT
, AT
, mips_gp_register
);
11207 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11208 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11211 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11212 /* Itbl support may require additional care here. */
11213 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11214 BFD_RELOC_LO16
, AT
);
11215 expr1
.X_add_number
+= 4;
11217 /* Set mips_optimize to 2 to avoid inserting an undesired
11219 hold_mips_optimize
= mips_optimize
;
11221 /* Itbl support may require additional care here. */
11222 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11223 BFD_RELOC_LO16
, AT
);
11224 mips_optimize
= hold_mips_optimize
;
11225 expr1
.X_add_number
-= 4;
11228 offset_expr
.X_add_number
= expr1
.X_add_number
;
11230 macro_build (NULL
, "nop", "");
11231 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11232 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11235 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11236 /* Itbl support may require additional care here. */
11237 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11238 BFD_RELOC_LO16
, AT
);
11239 offset_expr
.X_add_number
+= 4;
11241 /* Set mips_optimize to 2 to avoid inserting an undesired
11243 hold_mips_optimize
= mips_optimize
;
11245 /* Itbl support may require additional care here. */
11246 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11247 BFD_RELOC_LO16
, AT
);
11248 mips_optimize
= hold_mips_optimize
;
11267 /* New code added to support COPZ instructions.
11268 This code builds table entries out of the macros in mip_opcodes.
11269 R4000 uses interlocks to handle coproc delays.
11270 Other chips (like the R3000) require nops to be inserted for delays.
11272 FIXME: Currently, we require that the user handle delays.
11273 In order to fill delay slots for non-interlocked chips,
11274 we must have a way to specify delays based on the coprocessor.
11275 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11276 What are the side-effects of the cop instruction?
11277 What cache support might we have and what are its effects?
11278 Both coprocessor & memory require delays. how long???
11279 What registers are read/set/modified?
11281 If an itbl is provided to interpret cop instructions,
11282 this knowledge can be encoded in the itbl spec. */
11296 gas_assert (!mips_opts
.micromips
);
11297 /* For now we just do C (same as Cz). The parameter will be
11298 stored in insn_opcode by mips_ip. */
11299 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11303 move_register (op
[0], op
[1]);
11307 gas_assert (mips_opts
.micromips
);
11308 gas_assert (mips_opts
.insn32
);
11309 move_register (micromips_to_32_reg_h_map1
[op
[0]],
11310 micromips_to_32_reg_m_map
[op
[1]]);
11311 move_register (micromips_to_32_reg_h_map2
[op
[0]],
11312 micromips_to_32_reg_n_map
[op
[2]]);
11318 if (mips_opts
.arch
== CPU_R5900
)
11319 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
11323 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
11324 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11331 /* The MIPS assembler some times generates shifts and adds. I'm
11332 not trying to be that fancy. GCC should do this for us
11335 load_register (AT
, &imm_expr
, dbl
);
11336 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
11337 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11350 start_noreorder ();
11353 load_register (AT
, &imm_expr
, dbl
);
11354 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
11355 op
[1], imm
? AT
: op
[2]);
11356 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11357 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
11358 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11360 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
11363 if (mips_opts
.micromips
)
11364 micromips_label_expr (&label_expr
);
11366 label_expr
.X_add_number
= 8;
11367 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
11368 macro_build (NULL
, "nop", "");
11369 macro_build (NULL
, "break", BRK_FMT
, 6);
11370 if (mips_opts
.micromips
)
11371 micromips_add_label ();
11374 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11387 start_noreorder ();
11390 load_register (AT
, &imm_expr
, dbl
);
11391 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
11392 op
[1], imm
? AT
: op
[2]);
11393 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
11394 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
11396 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
11399 if (mips_opts
.micromips
)
11400 micromips_label_expr (&label_expr
);
11402 label_expr
.X_add_number
= 8;
11403 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
11404 macro_build (NULL
, "nop", "");
11405 macro_build (NULL
, "break", BRK_FMT
, 6);
11406 if (mips_opts
.micromips
)
11407 micromips_add_label ();
11413 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11415 if (op
[0] == op
[1])
11422 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
11423 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
11427 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
11428 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
11429 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
11430 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11434 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11436 if (op
[0] == op
[1])
11443 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
11444 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
11448 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
11449 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
11450 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
11451 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11460 if (imm_expr
.X_op
!= O_constant
)
11461 as_bad (_("Improper rotate count"));
11462 rot
= imm_expr
.X_add_number
& 0x3f;
11463 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11465 rot
= (64 - rot
) & 0x3f;
11467 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
11469 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
11474 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
11477 l
= (rot
< 0x20) ? "dsll" : "dsll32";
11478 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
11481 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
11482 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11483 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11491 if (imm_expr
.X_op
!= O_constant
)
11492 as_bad (_("Improper rotate count"));
11493 rot
= imm_expr
.X_add_number
& 0x1f;
11494 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11496 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
11497 (32 - rot
) & 0x1f);
11502 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
11506 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
11507 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11508 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11513 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11515 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
11519 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
11520 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
11521 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
11522 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11526 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11528 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
11532 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
11533 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
11534 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
11535 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11544 if (imm_expr
.X_op
!= O_constant
)
11545 as_bad (_("Improper rotate count"));
11546 rot
= imm_expr
.X_add_number
& 0x3f;
11547 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
11550 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
11552 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
11557 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
11560 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
11561 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
11564 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
11565 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11566 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11574 if (imm_expr
.X_op
!= O_constant
)
11575 as_bad (_("Improper rotate count"));
11576 rot
= imm_expr
.X_add_number
& 0x1f;
11577 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
11579 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
11584 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
11588 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
11589 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
11590 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
11596 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
11597 else if (op
[2] == 0)
11598 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11601 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
11602 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
11607 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11609 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11614 as_warn (_("Instruction %s: result is always false"),
11615 ip
->insn_mo
->name
);
11616 move_register (op
[0], 0);
11619 if (CPU_HAS_SEQ (mips_opts
.arch
)
11620 && -512 <= imm_expr
.X_add_number
11621 && imm_expr
.X_add_number
< 512)
11623 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
11624 (int) imm_expr
.X_add_number
);
11627 if (imm_expr
.X_op
== O_constant
11628 && imm_expr
.X_add_number
>= 0
11629 && imm_expr
.X_add_number
< 0x10000)
11630 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
11631 else if (imm_expr
.X_op
== O_constant
11632 && imm_expr
.X_add_number
> -0x8000
11633 && imm_expr
.X_add_number
< 0)
11635 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11636 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11637 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11639 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11642 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11643 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
11648 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11649 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
11652 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
11655 case M_SGE
: /* X >= Y <==> not (X < Y) */
11661 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
11662 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11665 case M_SGE_I
: /* X >= I <==> not (X < I) */
11667 if (imm_expr
.X_op
== O_constant
11668 && imm_expr
.X_add_number
>= -0x8000
11669 && imm_expr
.X_add_number
< 0x8000)
11670 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
11671 op
[0], op
[1], BFD_RELOC_LO16
);
11674 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11675 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
11679 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11682 case M_SGT
: /* X > Y <==> Y < X */
11688 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
11691 case M_SGT_I
: /* X > I <==> I < X */
11698 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11699 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
11702 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
11708 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
11709 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11712 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
11719 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11720 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
11721 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
11725 if (imm_expr
.X_op
== O_constant
11726 && imm_expr
.X_add_number
>= -0x8000
11727 && imm_expr
.X_add_number
< 0x8000)
11729 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
11734 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11735 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
11739 if (imm_expr
.X_op
== O_constant
11740 && imm_expr
.X_add_number
>= -0x8000
11741 && imm_expr
.X_add_number
< 0x8000)
11743 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
11748 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11749 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
11754 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
11755 else if (op
[2] == 0)
11756 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
11759 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
11760 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
11765 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
11767 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
11772 as_warn (_("Instruction %s: result is always true"),
11773 ip
->insn_mo
->name
);
11774 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
11775 op
[0], 0, BFD_RELOC_LO16
);
11778 if (CPU_HAS_SEQ (mips_opts
.arch
)
11779 && -512 <= imm_expr
.X_add_number
11780 && imm_expr
.X_add_number
< 512)
11782 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
11783 (int) imm_expr
.X_add_number
);
11786 if (imm_expr
.X_op
== O_constant
11787 && imm_expr
.X_add_number
>= 0
11788 && imm_expr
.X_add_number
< 0x10000)
11790 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
11793 else if (imm_expr
.X_op
== O_constant
11794 && imm_expr
.X_add_number
> -0x8000
11795 && imm_expr
.X_add_number
< 0)
11797 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11798 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
11799 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11801 else if (CPU_HAS_SEQ (mips_opts
.arch
))
11804 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11805 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
11810 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11811 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
11814 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
11829 if (!mips_opts
.micromips
)
11831 if (imm_expr
.X_op
== O_constant
11832 && imm_expr
.X_add_number
> -0x200
11833 && imm_expr
.X_add_number
<= 0x200)
11835 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], -imm_expr
.X_add_number
);
11844 if (imm_expr
.X_op
== O_constant
11845 && imm_expr
.X_add_number
> -0x8000
11846 && imm_expr
.X_add_number
<= 0x8000)
11848 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
11849 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
11854 load_register (AT
, &imm_expr
, dbl
);
11855 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
11877 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
11878 macro_build (NULL
, s
, "s,t", op
[0], AT
);
11883 gas_assert (!mips_opts
.micromips
);
11884 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
11888 * Is the double cfc1 instruction a bug in the mips assembler;
11889 * or is there a reason for it?
11891 start_noreorder ();
11892 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
11893 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
11894 macro_build (NULL
, "nop", "");
11895 expr1
.X_add_number
= 3;
11896 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
11897 expr1
.X_add_number
= 2;
11898 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
11899 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
11900 macro_build (NULL
, "nop", "");
11901 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
11903 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
11904 macro_build (NULL
, "nop", "");
11921 offbits
= (mips_opts
.micromips
? 12 : 16);
11927 offbits
= (mips_opts
.micromips
? 12 : 16);
11939 offbits
= (mips_opts
.micromips
? 12 : 16);
11946 offbits
= (mips_opts
.micromips
? 12 : 16);
11952 large_offset
= !small_offset_p (off
, align
, offbits
);
11954 expr1
.X_add_number
= 0;
11959 if (small_offset_p (0, align
, 16))
11960 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
11961 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11964 load_address (tempreg
, ep
, &used_at
);
11966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11967 tempreg
, tempreg
, breg
);
11969 offset_reloc
[0] = BFD_RELOC_LO16
;
11970 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11971 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11976 else if (!ust
&& op
[0] == breg
)
11987 if (!target_big_endian
)
11988 ep
->X_add_number
+= off
;
11990 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
11992 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
11993 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
11995 if (!target_big_endian
)
11996 ep
->X_add_number
-= off
;
11998 ep
->X_add_number
+= off
;
12000 macro_build (NULL
, s2
, "t,~(b)",
12001 tempreg
, (int) ep
->X_add_number
, breg
);
12003 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12004 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12006 /* If necessary, move the result in tempreg to the final destination. */
12007 if (!ust
&& op
[0] != tempreg
)
12009 /* Protect second load's delay slot. */
12011 move_register (op
[0], tempreg
);
12017 if (target_big_endian
== ust
)
12018 ep
->X_add_number
+= off
;
12019 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12020 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12021 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12023 /* For halfword transfers we need a temporary register to shuffle
12024 bytes. Unfortunately for M_USH_A we have none available before
12025 the next store as AT holds the base address. We deal with this
12026 case by clobbering TREG and then restoring it as with ULH. */
12027 tempreg
= ust
== large_offset
? op
[0] : AT
;
12029 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12031 if (target_big_endian
== ust
)
12032 ep
->X_add_number
-= off
;
12034 ep
->X_add_number
+= off
;
12035 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12036 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12038 /* For M_USH_A re-retrieve the LSB. */
12039 if (ust
&& large_offset
)
12041 if (target_big_endian
)
12042 ep
->X_add_number
+= off
;
12044 ep
->X_add_number
-= off
;
12045 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12046 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12048 /* For ULH and M_USH_A OR the LSB in. */
12049 if (!ust
|| large_offset
)
12051 tempreg
= !large_offset
? AT
: op
[0];
12052 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12053 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12058 /* FIXME: Check if this is one of the itbl macros, since they
12059 are added dynamically. */
12060 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
12063 if (!mips_opts
.at
&& used_at
)
12064 as_bad (_("Macro used $at after \".set noat\""));
12067 /* Implement macros in mips16 mode. */
12070 mips16_macro (struct mips_cl_insn
*ip
)
12072 const struct mips_operand_array
*operands
;
12077 const char *s
, *s2
, *s3
;
12078 unsigned int op
[MAX_OPERANDS
];
12081 mask
= ip
->insn_mo
->mask
;
12083 operands
= insn_operands (ip
);
12084 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12085 if (operands
->operand
[i
])
12086 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12090 expr1
.X_op
= O_constant
;
12091 expr1
.X_op_symbol
= NULL
;
12092 expr1
.X_add_symbol
= NULL
;
12093 expr1
.X_add_number
= 1;
12112 start_noreorder ();
12113 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12114 expr1
.X_add_number
= 2;
12115 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12116 macro_build (NULL
, "break", "6", 7);
12118 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12119 since that causes an overflow. We should do that as well,
12120 but I don't see how to do the comparisons without a temporary
12123 macro_build (NULL
, s
, "x", op
[0]);
12142 start_noreorder ();
12143 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12144 expr1
.X_add_number
= 2;
12145 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12146 macro_build (NULL
, "break", "6", 7);
12148 macro_build (NULL
, s2
, "x", op
[0]);
12154 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12155 macro_build (NULL
, "mflo", "x", op
[0]);
12163 if (imm_expr
.X_op
!= O_constant
)
12164 as_bad (_("Unsupported large constant"));
12165 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12166 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12170 if (imm_expr
.X_op
!= O_constant
)
12171 as_bad (_("Unsupported large constant"));
12172 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12173 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12177 if (imm_expr
.X_op
!= O_constant
)
12178 as_bad (_("Unsupported large constant"));
12179 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12180 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12202 goto do_reverse_branch
;
12206 goto do_reverse_branch
;
12218 goto do_reverse_branch
;
12229 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12230 macro_build (&offset_expr
, s2
, "p");
12257 goto do_addone_branch_i
;
12262 goto do_addone_branch_i
;
12277 goto do_addone_branch_i
;
12283 do_addone_branch_i
:
12284 if (imm_expr
.X_op
!= O_constant
)
12285 as_bad (_("Unsupported large constant"));
12286 ++imm_expr
.X_add_number
;
12289 macro_build (&imm_expr
, s
, s3
, op
[0]);
12290 macro_build (&offset_expr
, s2
, "p");
12294 expr1
.X_add_number
= 0;
12295 macro_build (&expr1
, "slti", "x,8", op
[1]);
12296 if (op
[0] != op
[1])
12297 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12298 expr1
.X_add_number
= 2;
12299 macro_build (&expr1
, "bteqz", "p");
12300 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12305 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12306 opcode bits in *OPCODE_EXTRA. */
12308 static struct mips_opcode
*
12309 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12310 ssize_t length
, unsigned int *opcode_extra
)
12312 char *name
, *dot
, *p
;
12313 unsigned int mask
, suffix
;
12315 struct mips_opcode
*insn
;
12317 /* Make a copy of the instruction so that we can fiddle with it. */
12318 name
= alloca (length
+ 1);
12319 memcpy (name
, start
, length
);
12320 name
[length
] = '\0';
12322 /* Look up the instruction as-is. */
12323 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12327 dot
= strchr (name
, '.');
12330 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12331 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
12332 if (*p
== 0 && mask
!= 0)
12335 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12337 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
12339 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
12345 if (mips_opts
.micromips
)
12347 /* See if there's an instruction size override suffix,
12348 either `16' or `32', at the end of the mnemonic proper,
12349 that defines the operation, i.e. before the first `.'
12350 character if any. Strip it and retry. */
12351 opend
= dot
!= NULL
? dot
- name
: length
;
12352 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
12354 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
12360 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
12361 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12364 forced_insn_length
= suffix
;
12373 /* Assemble an instruction into its binary format. If the instruction
12374 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12375 associated with "I", "+I" and "A" operands respectively. Otherwise
12376 store the value of the relocatable field (if any) in offset_expr.
12377 In both cases set offset_reloc to the relocation operators applied
12381 mips_ip (char *str
, struct mips_cl_insn
*ip
)
12383 bfd_boolean wrong_delay_slot_insns
= FALSE
;
12384 bfd_boolean need_delay_slot_ok
= TRUE
;
12385 struct mips_opcode
*firstinsn
= NULL
;
12386 const struct mips_opcode
*past
;
12387 struct hash_control
*hash
;
12390 struct mips_opcode
*first
, *insn
;
12393 const struct mips_operand
*operand
;
12394 struct mips_arg_info arg
;
12395 struct mips_operand_token
*tokens
;
12396 bfd_boolean optional_reg
;
12397 unsigned int opcode_extra
;
12401 if (mips_opts
.micromips
)
12403 hash
= micromips_op_hash
;
12404 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
12409 past
= &mips_opcodes
[NUMOPCODES
];
12411 forced_insn_length
= 0;
12415 /* We first try to match an instruction up to a space or to the end. */
12416 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
12419 first
= insn
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
12422 insn_error
= _("Unrecognized opcode");
12425 /* When no opcode suffix is specified, assume ".xyzw". */
12426 if ((insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
12427 opcode_extra
= 0xf << mips_vu0_channel_mask
.lsb
;
12429 if (strcmp (insn
->name
, "li.s") == 0)
12431 else if (strcmp (insn
->name
, "li.d") == 0)
12435 tokens
= mips_parse_arguments (str
+ end
, format
);
12439 /* For microMIPS instructions placed in a fixed-length branch delay slot
12440 we make up to two passes over the relevant fragment of the opcode
12441 table. First we try instructions that meet the delay slot's length
12442 requirement. If none matched, then we retry with the remaining ones
12443 and if one matches, then we use it and then issue an appropriate
12444 warning later on. */
12447 bfd_boolean delay_slot_ok
;
12448 bfd_boolean size_ok
;
12450 bfd_boolean more_alts
;
12452 gas_assert (strcmp (insn
->name
, first
->name
) == 0);
12454 ok
= is_opcode_valid (insn
);
12455 size_ok
= is_size_valid (insn
);
12456 delay_slot_ok
= is_delay_slot_valid (insn
);
12457 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
12460 wrong_delay_slot_insns
= TRUE
;
12462 more_alts
= (insn
+ 1 < past
12463 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12464 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
12466 static char buf
[256];
12473 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12475 gas_assert (firstinsn
);
12476 need_delay_slot_ok
= FALSE
;
12482 obstack_free (&mips_operand_tokens
, tokens
);
12487 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
12488 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12489 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12490 else if (mips_opts
.insn32
)
12491 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
12493 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
12494 8 * forced_insn_length
);
12500 imm_expr
.X_op
= O_absent
;
12501 imm2_expr
.X_op
= O_absent
;
12502 offset_expr
.X_op
= O_absent
;
12503 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12504 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12505 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12507 create_insn (ip
, insn
);
12508 ip
->insn_opcode
|= opcode_extra
;
12510 memset (&arg
, 0, sizeof (arg
));
12512 arg
.token
= tokens
;
12514 arg
.last_regno
= ILLEGAL_REG
;
12515 arg
.dest_regno
= ILLEGAL_REG
;
12516 arg
.soft_match
= (more_alts
12517 || (wrong_delay_slot_insns
&& need_delay_slot_ok
));
12518 for (args
= insn
->args
;; ++args
)
12520 if (arg
.token
->type
== OT_END
)
12522 /* Handle unary instructions in which only one operand is given.
12523 The source is then the same as the destination. */
12524 if (arg
.opnum
== 1 && *args
== ',')
12532 arg
.token
= tokens
;
12537 /* Treat elided base registers as $0. */
12538 if (strcmp (args
, "(b)") == 0)
12541 if (args
[0] == '+')
12546 /* The register suffix is optional. */
12551 /* Fail the match if there were too few operands. */
12555 /* Successful match. */
12556 if (arg
.dest_regno
== arg
.last_regno
12557 && strncmp (ip
->insn_mo
->name
, "jalr", 4) == 0)
12559 if (arg
.opnum
== 2)
12560 as_bad (_("Source and destination must be different"));
12561 else if (arg
.last_regno
== 31)
12562 as_bad (_("A destination register must be supplied"));
12564 check_completed_insn (&arg
);
12565 obstack_free (&mips_operand_tokens
, tokens
);
12569 /* Fail the match if the line has too many operands. */
12573 /* Handle characters that need to match exactly. */
12574 if (*args
== '(' || *args
== ')' || *args
== ',')
12576 if (match_char (&arg
, *args
))
12583 if (arg
.token
->type
== OT_DOUBLE_CHAR
12584 && arg
.token
->u
.ch
== *args
)
12592 /* Handle special macro operands. Work out the properties of
12595 arg
.lax_max
= FALSE
;
12596 optional_reg
= FALSE
;
12615 /* If these integer forms come last, there is no other
12616 form of the instruction that could match. Prefer to
12617 give detailed error messages where possible. */
12619 arg
.soft_match
= FALSE
;
12623 /* "+I" is like "I", except that imm2_expr is used. */
12624 if (match_const_int (&arg
, &imm2_expr
.X_add_number
, 0))
12625 imm2_expr
.X_op
= O_constant
;
12627 insn_error
= _("absolute expression required");
12628 if (HAVE_32BIT_GPRS
)
12629 normalize_constant_expr (&imm2_expr
);
12634 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12664 /* If these integer forms come last, there is no other
12665 form of the instruction that could match. Prefer to
12666 give detailed error messages where possible. */
12668 arg
.soft_match
= FALSE
;
12676 /* We have already matched a comma by this point, so the register
12677 is only optional if there is another operand to come. */
12678 gas_assert (arg
.opnum
== 2);
12679 optional_reg
= (args
[1] == ',');
12683 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
12684 imm_expr
.X_op
= O_constant
;
12686 insn_error
= _("absolute expression required");
12687 if (HAVE_32BIT_GPRS
)
12688 normalize_constant_expr (&imm_expr
);
12692 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
12694 /* Assume that the offset has been elided and that what
12695 we saw was a base register. The match will fail later
12696 if that assumption turns out to be wrong. */
12697 offset_expr
.X_op
= O_constant
;
12698 offset_expr
.X_add_number
= 0;
12700 else if (match_expression (&arg
, &offset_expr
, offset_reloc
))
12701 normalize_address_expr (&offset_expr
);
12703 insn_error
= _("absolute expression required");
12707 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12709 insn_error
= _("floating-point expression required");
12713 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12715 insn_error
= _("floating-point expression required");
12719 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12721 insn_error
= _("floating-point expression required");
12725 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
12727 insn_error
= _("floating-point expression required");
12730 /* ??? This is the traditional behavior, but is flaky if
12731 there are alternative versions of the same instruction
12732 for different subarchitectures. The next alternative
12733 might not be suitable. */
12735 /* For compatibility with older assemblers, we accept
12736 0x8000-0xffff as signed 16-bit numbers when only
12737 signed numbers are allowed. */
12738 arg
.lax_max
= !more_alts
;
12740 /* Only accept non-constant operands if this is the
12741 final alternative. Later alternatives might include
12742 a macro implementation. */
12743 arg
.allow_nonconst
= !more_alts
;
12747 /* There are no macro implementations for out-of-range values. */
12748 arg
.allow_nonconst
= TRUE
;
12752 /* There should always be a macro implementation. */
12753 arg
.allow_nonconst
= FALSE
;
12757 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
12761 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
12765 gas_assert (mips_opts
.micromips
);
12772 /* We have already matched a comma by this point,
12773 so the register is only optional if there is another
12774 operand to come. */
12775 gas_assert (arg
.opnum
== 2);
12776 optional_reg
= (args
[2] == ',');
12781 if (!forced_insn_length
)
12782 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
12784 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
12786 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
12792 operand
= (mips_opts
.micromips
12793 ? decode_micromips_operand (args
)
12794 : decode_mips_operand (args
));
12799 && (arg
.token
[0].type
!= OT_REG
12800 || arg
.token
[1].type
== OT_END
))
12802 /* Assume that the register has been elided and is the
12803 same as the first operand. */
12804 arg
.token
= tokens
;
12808 if (!match_operand (&arg
, operand
))
12811 /* Skip prefixes. */
12812 if (*args
== '+' || *args
== 'm')
12817 /* Args don't match. */
12818 insn_error
= _("Illegal operands");
12824 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
12826 gas_assert (firstinsn
);
12827 need_delay_slot_ok
= FALSE
;
12832 obstack_free (&mips_operand_tokens
, tokens
);
12837 /* As for mips_ip, but used when assembling MIPS16 code.
12838 Also set forced_insn_length to the resulting instruction size in
12839 bytes if the user explicitly requested a small or extended instruction. */
12842 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
12846 struct mips_opcode
*insn
;
12847 const struct mips_operand
*operand
;
12848 const struct mips_operand
*ext_operand
;
12849 struct mips_arg_info arg
;
12850 struct mips_operand_token
*tokens
;
12851 bfd_boolean optional_reg
;
12855 forced_insn_length
= 0;
12857 for (s
= str
; ISLOWER (*s
); ++s
)
12869 if (s
[1] == 't' && s
[2] == ' ')
12872 forced_insn_length
= 2;
12876 else if (s
[1] == 'e' && s
[2] == ' ')
12879 forced_insn_length
= 4;
12883 /* Fall through. */
12885 insn_error
= _("unknown opcode");
12889 if (mips_opts
.noautoextend
&& !forced_insn_length
)
12890 forced_insn_length
= 2;
12892 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
12894 insn_error
= _("unrecognized opcode");
12898 tokens
= mips_parse_arguments (s
, 0);
12905 bfd_boolean more_alts
;
12908 gas_assert (strcmp (insn
->name
, str
) == 0);
12910 ok
= is_opcode_valid_16 (insn
);
12911 more_alts
= (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
12912 && strcmp (insn
[0].name
, insn
[1].name
) == 0);
12924 static char buf
[100];
12926 _("Opcode not supported on this processor: %s (%s)"),
12927 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
12928 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12931 obstack_free (&mips_operand_tokens
, tokens
);
12936 create_insn (ip
, insn
);
12937 imm_expr
.X_op
= O_absent
;
12938 imm2_expr
.X_op
= O_absent
;
12939 offset_expr
.X_op
= O_absent
;
12940 offset_reloc
[0] = BFD_RELOC_UNUSED
;
12941 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12942 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12945 memset (&arg
, 0, sizeof (arg
));
12947 arg
.token
= tokens
;
12949 arg
.last_regno
= ILLEGAL_REG
;
12950 arg
.dest_regno
= ILLEGAL_REG
;
12951 arg
.soft_match
= more_alts
;
12953 for (args
= insn
->args
; 1; ++args
)
12957 if (arg
.token
->type
== OT_END
)
12961 /* Handle unary instructions in which only one operand is given.
12962 The source is then the same as the destination. */
12963 if (arg
.opnum
== 1 && *args
== ',')
12968 arg
.token
= tokens
;
12973 /* Fail the match if there were too few operands. */
12977 /* Successful match. Stuff the immediate value in now, if
12979 if (insn
->pinfo
== INSN_MACRO
)
12981 gas_assert (relax_char
== 0 || relax_char
== 'p');
12982 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
12984 else if (relax_char
12985 && offset_expr
.X_op
== O_constant
12986 && calculate_reloc (*offset_reloc
,
12987 offset_expr
.X_add_number
,
12990 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
12991 forced_insn_length
, &ip
->insn_opcode
);
12992 offset_expr
.X_op
= O_absent
;
12993 *offset_reloc
= BFD_RELOC_UNUSED
;
12995 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
12997 if (forced_insn_length
== 2)
12998 as_bad (_("invalid unextended operand value"));
12999 forced_insn_length
= 4;
13000 ip
->insn_opcode
|= MIPS16_EXTEND
;
13002 else if (relax_char
)
13003 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
13005 check_completed_insn (&arg
);
13006 obstack_free (&mips_operand_tokens
, tokens
);
13010 /* Fail the match if the line has too many operands. */
13014 /* Handle characters that need to match exactly. */
13015 if (*args
== '(' || *args
== ')' || *args
== ',')
13017 if (match_char (&arg
, *args
))
13023 optional_reg
= FALSE
;
13029 optional_reg
= (args
[1] == ',');
13041 if (match_const_int (&arg
, &imm_expr
.X_add_number
, 0))
13042 imm_expr
.X_op
= O_constant
;
13044 insn_error
= _("absolute expression required");
13045 if (HAVE_32BIT_GPRS
)
13046 normalize_constant_expr (&imm_expr
);
13051 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
13052 ip
->insn_opcode
<<= 16;
13056 operand
= decode_mips16_operand (c
, FALSE
);
13060 /* '6' is a special case. It is used for BREAK and SDBBP,
13061 whose operands are only meaningful to the software that decodes
13062 them. This means that there is no architectural reason why
13063 they cannot be prefixed by EXTEND, but in practice,
13064 exception handlers will only look at the instruction
13065 itself. We therefore allow '6' to be extended when
13066 disassembling but not when assembling. */
13067 if (operand
->type
!= OP_PCREL
&& c
!= '6')
13069 ext_operand
= decode_mips16_operand (c
, TRUE
);
13070 if (operand
!= ext_operand
)
13072 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
13074 offset_expr
.X_op
= O_constant
;
13075 offset_expr
.X_add_number
= 0;
13080 /* We need the OT_INTEGER check because some MIPS16
13081 immediate variants are listed before the register ones. */
13082 if (arg
.token
->type
!= OT_INTEGER
13083 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
13086 /* '8' is used for SLTI(U) and has traditionally not
13087 been allowed to take relocation operators. */
13088 if (offset_reloc
[0] != BFD_RELOC_UNUSED
13089 && (ext_operand
->size
!= 16 || c
== '8'))
13098 && (arg
.token
[0].type
!= OT_REG
13099 || arg
.token
[1].type
== OT_END
))
13101 /* Assume that the register has been elided and is the
13102 same as the first operand. */
13103 arg
.token
= tokens
;
13107 if (!match_operand (&arg
, operand
))
13112 /* Args don't match. */
13119 insn_error
= _("illegal operands");
13121 obstack_free (&mips_operand_tokens
, tokens
);
13126 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13127 NBITS is the number of significant bits in VAL. */
13129 static unsigned long
13130 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13135 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13138 else if (nbits
== 15)
13140 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13145 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13148 return (extval
<< 16) | val
;
13151 /* Like decode_mips16_operand, but require the operand to be defined and
13152 require it to be an integer. */
13154 static const struct mips_int_operand
*
13155 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13157 const struct mips_operand
*operand
;
13159 operand
= decode_mips16_operand (type
, extended_p
);
13160 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13162 return (const struct mips_int_operand
*) operand
;
13165 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13168 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13169 bfd_reloc_code_real_type reloc
, offsetT sval
)
13171 int min_val
, max_val
;
13173 min_val
= mips_int_operand_min (operand
);
13174 max_val
= mips_int_operand_max (operand
);
13175 if (reloc
!= BFD_RELOC_UNUSED
)
13178 sval
= SEXT_16BIT (sval
);
13183 return (sval
>= min_val
13185 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13188 /* Install immediate value VAL into MIPS16 instruction *INSN,
13189 extending it if necessary. The instruction in *INSN may
13190 already be extended.
13192 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13193 if none. In the former case, VAL is a 16-bit number with no
13194 defined signedness.
13196 TYPE is the type of the immediate field. USER_INSN_LENGTH
13197 is the length that the user requested, or 0 if none. */
13200 mips16_immed (char *file
, unsigned int line
, int type
,
13201 bfd_reloc_code_real_type reloc
, offsetT val
,
13202 unsigned int user_insn_length
, unsigned long *insn
)
13204 const struct mips_int_operand
*operand
;
13205 unsigned int uval
, length
;
13207 operand
= mips16_immed_operand (type
, FALSE
);
13208 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13210 /* We need an extended instruction. */
13211 if (user_insn_length
== 2)
13212 as_bad_where (file
, line
, _("invalid unextended operand value"));
13214 *insn
|= MIPS16_EXTEND
;
13216 else if (user_insn_length
== 4)
13218 /* The operand doesn't force an unextended instruction to be extended.
13219 Warn if the user wanted an extended instruction anyway. */
13220 *insn
|= MIPS16_EXTEND
;
13221 as_warn_where (file
, line
,
13222 _("extended operand requested but not required"));
13225 length
= mips16_opcode_length (*insn
);
13228 operand
= mips16_immed_operand (type
, TRUE
);
13229 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13230 as_bad_where (file
, line
,
13231 _("operand value out of range for instruction"));
13233 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13235 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13237 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13240 struct percent_op_match
13243 bfd_reloc_code_real_type reloc
;
13246 static const struct percent_op_match mips_percent_op
[] =
13248 {"%lo", BFD_RELOC_LO16
},
13249 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13250 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13251 {"%call16", BFD_RELOC_MIPS_CALL16
},
13252 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13253 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13254 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13255 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13256 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13257 {"%got", BFD_RELOC_MIPS_GOT16
},
13258 {"%gp_rel", BFD_RELOC_GPREL16
},
13259 {"%half", BFD_RELOC_16
},
13260 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13261 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13262 {"%neg", BFD_RELOC_MIPS_SUB
},
13263 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13264 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13265 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13266 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13267 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13268 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13269 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13270 {"%hi", BFD_RELOC_HI16_S
}
13273 static const struct percent_op_match mips16_percent_op
[] =
13275 {"%lo", BFD_RELOC_MIPS16_LO16
},
13276 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13277 {"%got", BFD_RELOC_MIPS16_GOT16
},
13278 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13279 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13280 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13281 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13282 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13283 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13284 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13285 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13286 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13290 /* Return true if *STR points to a relocation operator. When returning true,
13291 move *STR over the operator and store its relocation code in *RELOC.
13292 Leave both *STR and *RELOC alone when returning false. */
13295 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13297 const struct percent_op_match
*percent_op
;
13300 if (mips_opts
.mips16
)
13302 percent_op
= mips16_percent_op
;
13303 limit
= ARRAY_SIZE (mips16_percent_op
);
13307 percent_op
= mips_percent_op
;
13308 limit
= ARRAY_SIZE (mips_percent_op
);
13311 for (i
= 0; i
< limit
; i
++)
13312 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13314 int len
= strlen (percent_op
[i
].str
);
13316 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13319 *str
+= strlen (percent_op
[i
].str
);
13320 *reloc
= percent_op
[i
].reloc
;
13322 /* Check whether the output BFD supports this relocation.
13323 If not, issue an error and fall back on something safe. */
13324 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13326 as_bad (_("relocation %s isn't supported by the current ABI"),
13327 percent_op
[i
].str
);
13328 *reloc
= BFD_RELOC_UNUSED
;
13336 /* Parse string STR as a 16-bit relocatable operand. Store the
13337 expression in *EP and the relocations in the array starting
13338 at RELOC. Return the number of relocation operators used.
13340 On exit, EXPR_END points to the first character after the expression. */
13343 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13346 bfd_reloc_code_real_type reversed_reloc
[3];
13347 size_t reloc_index
, i
;
13348 int crux_depth
, str_depth
;
13351 /* Search for the start of the main expression, recoding relocations
13352 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13353 of the main expression and with CRUX_DEPTH containing the number
13354 of open brackets at that point. */
13361 crux_depth
= str_depth
;
13363 /* Skip over whitespace and brackets, keeping count of the number
13365 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13370 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13371 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13373 my_getExpression (ep
, crux
);
13376 /* Match every open bracket. */
13377 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13381 if (crux_depth
> 0)
13382 as_bad (_("unclosed '('"));
13386 if (reloc_index
!= 0)
13388 prev_reloc_op_frag
= frag_now
;
13389 for (i
= 0; i
< reloc_index
; i
++)
13390 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13393 return reloc_index
;
13397 my_getExpression (expressionS
*ep
, char *str
)
13401 save_in
= input_line_pointer
;
13402 input_line_pointer
= str
;
13404 expr_end
= input_line_pointer
;
13405 input_line_pointer
= save_in
;
13409 md_atof (int type
, char *litP
, int *sizeP
)
13411 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13415 md_number_to_chars (char *buf
, valueT val
, int n
)
13417 if (target_big_endian
)
13418 number_to_chars_bigendian (buf
, val
, n
);
13420 number_to_chars_littleendian (buf
, val
, n
);
13423 static int support_64bit_objects(void)
13425 const char **list
, **l
;
13428 list
= bfd_target_list ();
13429 for (l
= list
; *l
!= NULL
; l
++)
13430 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13431 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13433 yes
= (*l
!= NULL
);
13438 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13439 NEW_VALUE. Warn if another value was already specified. Note:
13440 we have to defer parsing the -march and -mtune arguments in order
13441 to handle 'from-abi' correctly, since the ABI might be specified
13442 in a later argument. */
13445 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13447 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13448 as_warn (_("A different %s was already specified, is now %s"),
13449 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13452 *string_ptr
= new_value
;
13456 md_parse_option (int c
, char *arg
)
13460 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13461 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13463 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13464 c
== mips_ases
[i
].option_on
);
13470 case OPTION_CONSTRUCT_FLOATS
:
13471 mips_disable_float_construction
= 0;
13474 case OPTION_NO_CONSTRUCT_FLOATS
:
13475 mips_disable_float_construction
= 1;
13487 target_big_endian
= 1;
13491 target_big_endian
= 0;
13497 else if (arg
[0] == '0')
13499 else if (arg
[0] == '1')
13509 mips_debug
= atoi (arg
);
13513 file_mips_isa
= ISA_MIPS1
;
13517 file_mips_isa
= ISA_MIPS2
;
13521 file_mips_isa
= ISA_MIPS3
;
13525 file_mips_isa
= ISA_MIPS4
;
13529 file_mips_isa
= ISA_MIPS5
;
13532 case OPTION_MIPS32
:
13533 file_mips_isa
= ISA_MIPS32
;
13536 case OPTION_MIPS32R2
:
13537 file_mips_isa
= ISA_MIPS32R2
;
13540 case OPTION_MIPS64R2
:
13541 file_mips_isa
= ISA_MIPS64R2
;
13544 case OPTION_MIPS64
:
13545 file_mips_isa
= ISA_MIPS64
;
13549 mips_set_option_string (&mips_tune_string
, arg
);
13553 mips_set_option_string (&mips_arch_string
, arg
);
13557 mips_set_option_string (&mips_arch_string
, "4650");
13558 mips_set_option_string (&mips_tune_string
, "4650");
13561 case OPTION_NO_M4650
:
13565 mips_set_option_string (&mips_arch_string
, "4010");
13566 mips_set_option_string (&mips_tune_string
, "4010");
13569 case OPTION_NO_M4010
:
13573 mips_set_option_string (&mips_arch_string
, "4100");
13574 mips_set_option_string (&mips_tune_string
, "4100");
13577 case OPTION_NO_M4100
:
13581 mips_set_option_string (&mips_arch_string
, "3900");
13582 mips_set_option_string (&mips_tune_string
, "3900");
13585 case OPTION_NO_M3900
:
13588 case OPTION_MICROMIPS
:
13589 if (mips_opts
.mips16
== 1)
13591 as_bad (_("-mmicromips cannot be used with -mips16"));
13594 mips_opts
.micromips
= 1;
13595 mips_no_prev_insn ();
13598 case OPTION_NO_MICROMIPS
:
13599 mips_opts
.micromips
= 0;
13600 mips_no_prev_insn ();
13603 case OPTION_MIPS16
:
13604 if (mips_opts
.micromips
== 1)
13606 as_bad (_("-mips16 cannot be used with -micromips"));
13609 mips_opts
.mips16
= 1;
13610 mips_no_prev_insn ();
13613 case OPTION_NO_MIPS16
:
13614 mips_opts
.mips16
= 0;
13615 mips_no_prev_insn ();
13618 case OPTION_FIX_24K
:
13622 case OPTION_NO_FIX_24K
:
13626 case OPTION_FIX_LOONGSON2F_JUMP
:
13627 mips_fix_loongson2f_jump
= TRUE
;
13630 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13631 mips_fix_loongson2f_jump
= FALSE
;
13634 case OPTION_FIX_LOONGSON2F_NOP
:
13635 mips_fix_loongson2f_nop
= TRUE
;
13638 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13639 mips_fix_loongson2f_nop
= FALSE
;
13642 case OPTION_FIX_VR4120
:
13643 mips_fix_vr4120
= 1;
13646 case OPTION_NO_FIX_VR4120
:
13647 mips_fix_vr4120
= 0;
13650 case OPTION_FIX_VR4130
:
13651 mips_fix_vr4130
= 1;
13654 case OPTION_NO_FIX_VR4130
:
13655 mips_fix_vr4130
= 0;
13658 case OPTION_FIX_CN63XXP1
:
13659 mips_fix_cn63xxp1
= TRUE
;
13662 case OPTION_NO_FIX_CN63XXP1
:
13663 mips_fix_cn63xxp1
= FALSE
;
13666 case OPTION_RELAX_BRANCH
:
13667 mips_relax_branch
= 1;
13670 case OPTION_NO_RELAX_BRANCH
:
13671 mips_relax_branch
= 0;
13674 case OPTION_INSN32
:
13675 mips_opts
.insn32
= TRUE
;
13678 case OPTION_NO_INSN32
:
13679 mips_opts
.insn32
= FALSE
;
13682 case OPTION_MSHARED
:
13683 mips_in_shared
= TRUE
;
13686 case OPTION_MNO_SHARED
:
13687 mips_in_shared
= FALSE
;
13690 case OPTION_MSYM32
:
13691 mips_opts
.sym32
= TRUE
;
13694 case OPTION_MNO_SYM32
:
13695 mips_opts
.sym32
= FALSE
;
13698 /* When generating ELF code, we permit -KPIC and -call_shared to
13699 select SVR4_PIC, and -non_shared to select no PIC. This is
13700 intended to be compatible with Irix 5. */
13701 case OPTION_CALL_SHARED
:
13702 mips_pic
= SVR4_PIC
;
13703 mips_abicalls
= TRUE
;
13706 case OPTION_CALL_NONPIC
:
13708 mips_abicalls
= TRUE
;
13711 case OPTION_NON_SHARED
:
13713 mips_abicalls
= FALSE
;
13716 /* The -xgot option tells the assembler to use 32 bit offsets
13717 when accessing the got in SVR4_PIC mode. It is for Irix
13724 g_switch_value
= atoi (arg
);
13728 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13731 mips_abi
= O32_ABI
;
13735 mips_abi
= N32_ABI
;
13739 mips_abi
= N64_ABI
;
13740 if (!support_64bit_objects())
13741 as_fatal (_("No compiled in support for 64 bit object file format"));
13745 file_mips_gp32
= 1;
13749 file_mips_gp32
= 0;
13753 file_mips_fp32
= 1;
13757 file_mips_fp32
= 0;
13760 case OPTION_SINGLE_FLOAT
:
13761 file_mips_single_float
= 1;
13764 case OPTION_DOUBLE_FLOAT
:
13765 file_mips_single_float
= 0;
13768 case OPTION_SOFT_FLOAT
:
13769 file_mips_soft_float
= 1;
13772 case OPTION_HARD_FLOAT
:
13773 file_mips_soft_float
= 0;
13777 if (strcmp (arg
, "32") == 0)
13778 mips_abi
= O32_ABI
;
13779 else if (strcmp (arg
, "o64") == 0)
13780 mips_abi
= O64_ABI
;
13781 else if (strcmp (arg
, "n32") == 0)
13782 mips_abi
= N32_ABI
;
13783 else if (strcmp (arg
, "64") == 0)
13785 mips_abi
= N64_ABI
;
13786 if (! support_64bit_objects())
13787 as_fatal (_("No compiled in support for 64 bit object file "
13790 else if (strcmp (arg
, "eabi") == 0)
13791 mips_abi
= EABI_ABI
;
13794 as_fatal (_("invalid abi -mabi=%s"), arg
);
13799 case OPTION_M7000_HILO_FIX
:
13800 mips_7000_hilo_fix
= TRUE
;
13803 case OPTION_MNO_7000_HILO_FIX
:
13804 mips_7000_hilo_fix
= FALSE
;
13807 case OPTION_MDEBUG
:
13808 mips_flag_mdebug
= TRUE
;
13811 case OPTION_NO_MDEBUG
:
13812 mips_flag_mdebug
= FALSE
;
13816 mips_flag_pdr
= TRUE
;
13819 case OPTION_NO_PDR
:
13820 mips_flag_pdr
= FALSE
;
13823 case OPTION_MVXWORKS_PIC
:
13824 mips_pic
= VXWORKS_PIC
;
13828 if (strcmp (arg
, "2008") == 0)
13829 mips_flag_nan2008
= TRUE
;
13830 else if (strcmp (arg
, "legacy") == 0)
13831 mips_flag_nan2008
= FALSE
;
13834 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13843 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13848 /* Set up globals to generate code for the ISA or processor
13849 described by INFO. */
13852 mips_set_architecture (const struct mips_cpu_info
*info
)
13856 file_mips_arch
= info
->cpu
;
13857 mips_opts
.arch
= info
->cpu
;
13858 mips_opts
.isa
= info
->isa
;
13863 /* Likewise for tuning. */
13866 mips_set_tune (const struct mips_cpu_info
*info
)
13869 mips_tune
= info
->cpu
;
13874 mips_after_parse_args (void)
13876 const struct mips_cpu_info
*arch_info
= 0;
13877 const struct mips_cpu_info
*tune_info
= 0;
13879 /* GP relative stuff not working for PE */
13880 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13882 if (g_switch_seen
&& g_switch_value
!= 0)
13883 as_bad (_("-G not supported in this configuration."));
13884 g_switch_value
= 0;
13887 if (mips_abi
== NO_ABI
)
13888 mips_abi
= MIPS_DEFAULT_ABI
;
13890 /* The following code determines the architecture and register size.
13891 Similar code was added to GCC 3.3 (see override_options() in
13892 config/mips/mips.c). The GAS and GCC code should be kept in sync
13893 as much as possible. */
13895 if (mips_arch_string
!= 0)
13896 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13898 if (file_mips_isa
!= ISA_UNKNOWN
)
13900 /* Handle -mipsN. At this point, file_mips_isa contains the
13901 ISA level specified by -mipsN, while arch_info->isa contains
13902 the -march selection (if any). */
13903 if (arch_info
!= 0)
13905 /* -march takes precedence over -mipsN, since it is more descriptive.
13906 There's no harm in specifying both as long as the ISA levels
13908 if (file_mips_isa
!= arch_info
->isa
)
13909 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13910 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13911 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13914 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13917 if (arch_info
== 0)
13919 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13920 gas_assert (arch_info
);
13923 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13924 as_bad (_("-march=%s is not compatible with the selected ABI"),
13927 mips_set_architecture (arch_info
);
13929 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13930 if (mips_tune_string
!= 0)
13931 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13933 if (tune_info
== 0)
13934 mips_set_tune (arch_info
);
13936 mips_set_tune (tune_info
);
13938 if (file_mips_gp32
>= 0)
13940 /* The user specified the size of the integer registers. Make sure
13941 it agrees with the ABI and ISA. */
13942 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
13943 as_bad (_("-mgp64 used with a 32-bit processor"));
13944 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
13945 as_bad (_("-mgp32 used with a 64-bit ABI"));
13946 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
13947 as_bad (_("-mgp64 used with a 32-bit ABI"));
13951 /* Infer the integer register size from the ABI and processor.
13952 Restrict ourselves to 32-bit registers if that's all the
13953 processor has, or if the ABI cannot handle 64-bit registers. */
13954 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
13955 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
13958 switch (file_mips_fp32
)
13962 /* No user specified float register size.
13963 ??? GAS treats single-float processors as though they had 64-bit
13964 float registers (although it complains when double-precision
13965 instructions are used). As things stand, saying they have 32-bit
13966 registers would lead to spurious "register must be even" messages.
13967 So here we assume float registers are never smaller than the
13969 if (file_mips_gp32
== 0)
13970 /* 64-bit integer registers implies 64-bit float registers. */
13971 file_mips_fp32
= 0;
13972 else if ((mips_opts
.ase
& FP64_ASES
)
13973 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13974 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
13975 file_mips_fp32
= 0;
13977 /* 32-bit float registers. */
13978 file_mips_fp32
= 1;
13981 /* The user specified the size of the float registers. Check if it
13982 agrees with the ABI and ISA. */
13984 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
13985 as_bad (_("-mfp64 used with a 32-bit fpu"));
13986 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
13987 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
13988 as_warn (_("-mfp64 used with a 32-bit ABI"));
13991 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13992 as_warn (_("-mfp32 used with a 64-bit ABI"));
13996 /* End of GCC-shared inference code. */
13998 /* This flag is set when we have a 64-bit capable CPU but use only
13999 32-bit wide registers. Note that EABI does not use it. */
14000 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14001 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
14002 || mips_abi
== O32_ABI
))
14003 mips_32bitmode
= 1;
14005 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14006 as_bad (_("trap exception not supported at ISA 1"));
14008 /* If the selected architecture includes support for ASEs, enable
14009 generation of code for them. */
14010 if (mips_opts
.mips16
== -1)
14011 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
14012 if (mips_opts
.micromips
== -1)
14013 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
14015 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14016 ASEs from being selected implicitly. */
14017 if (file_mips_fp32
== 1)
14018 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
14020 /* If the user didn't explicitly select or deselect a particular ASE,
14021 use the default setting for the CPU. */
14022 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
14024 file_mips_isa
= mips_opts
.isa
;
14025 file_ase
= mips_opts
.ase
;
14026 mips_opts
.gp32
= file_mips_gp32
;
14027 mips_opts
.fp32
= file_mips_fp32
;
14028 mips_opts
.soft_float
= file_mips_soft_float
;
14029 mips_opts
.single_float
= file_mips_single_float
;
14031 mips_check_isa_supports_ases ();
14033 if (mips_flag_mdebug
< 0)
14034 mips_flag_mdebug
= 0;
14038 mips_init_after_args (void)
14040 /* initialize opcodes */
14041 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14042 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14046 md_pcrel_from (fixS
*fixP
)
14048 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14049 switch (fixP
->fx_r_type
)
14051 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14052 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14053 /* Return the address of the delay slot. */
14056 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14057 case BFD_RELOC_MICROMIPS_JMP
:
14058 case BFD_RELOC_16_PCREL_S2
:
14059 case BFD_RELOC_MIPS_JMP
:
14060 /* Return the address of the delay slot. */
14063 case BFD_RELOC_32_PCREL
:
14067 /* We have no relocation type for PC relative MIPS16 instructions. */
14068 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
14069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14070 _("PC relative MIPS16 instruction references a different section"));
14075 /* This is called before the symbol table is processed. In order to
14076 work with gcc when using mips-tfile, we must keep all local labels.
14077 However, in other cases, we want to discard them. If we were
14078 called with -g, but we didn't see any debugging information, it may
14079 mean that gcc is smuggling debugging information through to
14080 mips-tfile, in which case we must generate all local labels. */
14083 mips_frob_file_before_adjust (void)
14085 #ifndef NO_ECOFF_DEBUGGING
14086 if (ECOFF_DEBUGGING
14088 && ! ecoff_debugging_seen
)
14089 flag_keep_locals
= 1;
14093 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14094 the corresponding LO16 reloc. This is called before md_apply_fix and
14095 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14096 relocation operators.
14098 For our purposes, a %lo() expression matches a %got() or %hi()
14101 (a) it refers to the same symbol; and
14102 (b) the offset applied in the %lo() expression is no lower than
14103 the offset applied in the %got() or %hi().
14105 (b) allows us to cope with code like:
14108 lh $4,%lo(foo+2)($4)
14110 ...which is legal on RELA targets, and has a well-defined behaviour
14111 if the user knows that adding 2 to "foo" will not induce a carry to
14114 When several %lo()s match a particular %got() or %hi(), we use the
14115 following rules to distinguish them:
14117 (1) %lo()s with smaller offsets are a better match than %lo()s with
14120 (2) %lo()s with no matching %got() or %hi() are better than those
14121 that already have a matching %got() or %hi().
14123 (3) later %lo()s are better than earlier %lo()s.
14125 These rules are applied in order.
14127 (1) means, among other things, that %lo()s with identical offsets are
14128 chosen if they exist.
14130 (2) means that we won't associate several high-part relocations with
14131 the same low-part relocation unless there's no alternative. Having
14132 several high parts for the same low part is a GNU extension; this rule
14133 allows careful users to avoid it.
14135 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14136 with the last high-part relocation being at the front of the list.
14137 It therefore makes sense to choose the last matching low-part
14138 relocation, all other things being equal. It's also easier
14139 to code that way. */
14142 mips_frob_file (void)
14144 struct mips_hi_fixup
*l
;
14145 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14147 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14149 segment_info_type
*seginfo
;
14150 bfd_boolean matched_lo_p
;
14151 fixS
**hi_pos
, **lo_pos
, **pos
;
14153 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14155 /* If a GOT16 relocation turns out to be against a global symbol,
14156 there isn't supposed to be a matching LO. Ignore %gots against
14157 constants; we'll report an error for those later. */
14158 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14159 && !(l
->fixp
->fx_addsy
14160 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14163 /* Check quickly whether the next fixup happens to be a matching %lo. */
14164 if (fixup_has_matching_lo_p (l
->fixp
))
14167 seginfo
= seg_info (l
->seg
);
14169 /* Set HI_POS to the position of this relocation in the chain.
14170 Set LO_POS to the position of the chosen low-part relocation.
14171 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14172 relocation that matches an immediately-preceding high-part
14176 matched_lo_p
= FALSE
;
14177 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14179 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14181 if (*pos
== l
->fixp
)
14184 if ((*pos
)->fx_r_type
== looking_for_rtype
14185 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14186 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14188 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14190 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14193 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14194 && fixup_has_matching_lo_p (*pos
));
14197 /* If we found a match, remove the high-part relocation from its
14198 current position and insert it before the low-part relocation.
14199 Make the offsets match so that fixup_has_matching_lo_p()
14202 We don't warn about unmatched high-part relocations since some
14203 versions of gcc have been known to emit dead "lui ...%hi(...)"
14205 if (lo_pos
!= NULL
)
14207 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14208 if (l
->fixp
->fx_next
!= *lo_pos
)
14210 *hi_pos
= l
->fixp
->fx_next
;
14211 l
->fixp
->fx_next
= *lo_pos
;
14219 mips_force_relocation (fixS
*fixp
)
14221 if (generic_force_reloc (fixp
))
14224 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14225 so that the linker relaxation can update targets. */
14226 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14227 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14228 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14234 /* Read the instruction associated with RELOC from BUF. */
14236 static unsigned int
14237 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14239 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14240 return read_compressed_insn (buf
, 4);
14242 return read_insn (buf
);
14245 /* Write instruction INSN to BUF, given that it has been relocated
14249 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14250 unsigned long insn
)
14252 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14253 write_compressed_insn (buf
, insn
, 4);
14255 write_insn (buf
, insn
);
14258 /* Apply a fixup to the object file. */
14261 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14264 unsigned long insn
;
14265 reloc_howto_type
*howto
;
14267 /* We ignore generic BFD relocations we don't know about. */
14268 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14272 gas_assert (fixP
->fx_size
== 2
14273 || fixP
->fx_size
== 4
14274 || fixP
->fx_r_type
== BFD_RELOC_16
14275 || fixP
->fx_r_type
== BFD_RELOC_64
14276 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14277 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14278 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14279 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14280 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14281 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14283 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14285 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14286 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14287 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14288 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14289 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14291 /* Don't treat parts of a composite relocation as done. There are two
14294 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14295 should nevertheless be emitted if the first part is.
14297 (2) In normal usage, composite relocations are never assembly-time
14298 constants. The easiest way of dealing with the pathological
14299 exceptions is to generate a relocation against STN_UNDEF and
14300 leave everything up to the linker. */
14301 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14304 switch (fixP
->fx_r_type
)
14306 case BFD_RELOC_MIPS_TLS_GD
:
14307 case BFD_RELOC_MIPS_TLS_LDM
:
14308 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14309 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14310 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14311 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14312 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14313 case BFD_RELOC_MIPS_TLS_TPREL32
:
14314 case BFD_RELOC_MIPS_TLS_TPREL64
:
14315 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14316 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14317 case BFD_RELOC_MICROMIPS_TLS_GD
:
14318 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14319 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14320 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14321 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14322 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14323 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14324 case BFD_RELOC_MIPS16_TLS_GD
:
14325 case BFD_RELOC_MIPS16_TLS_LDM
:
14326 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14327 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14328 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14329 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14330 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14331 if (!fixP
->fx_addsy
)
14333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14334 _("TLS relocation against a constant"));
14337 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14340 case BFD_RELOC_MIPS_JMP
:
14341 case BFD_RELOC_MIPS_SHIFT5
:
14342 case BFD_RELOC_MIPS_SHIFT6
:
14343 case BFD_RELOC_MIPS_GOT_DISP
:
14344 case BFD_RELOC_MIPS_GOT_PAGE
:
14345 case BFD_RELOC_MIPS_GOT_OFST
:
14346 case BFD_RELOC_MIPS_SUB
:
14347 case BFD_RELOC_MIPS_INSERT_A
:
14348 case BFD_RELOC_MIPS_INSERT_B
:
14349 case BFD_RELOC_MIPS_DELETE
:
14350 case BFD_RELOC_MIPS_HIGHEST
:
14351 case BFD_RELOC_MIPS_HIGHER
:
14352 case BFD_RELOC_MIPS_SCN_DISP
:
14353 case BFD_RELOC_MIPS_REL16
:
14354 case BFD_RELOC_MIPS_RELGOT
:
14355 case BFD_RELOC_MIPS_JALR
:
14356 case BFD_RELOC_HI16
:
14357 case BFD_RELOC_HI16_S
:
14358 case BFD_RELOC_LO16
:
14359 case BFD_RELOC_GPREL16
:
14360 case BFD_RELOC_MIPS_LITERAL
:
14361 case BFD_RELOC_MIPS_CALL16
:
14362 case BFD_RELOC_MIPS_GOT16
:
14363 case BFD_RELOC_GPREL32
:
14364 case BFD_RELOC_MIPS_GOT_HI16
:
14365 case BFD_RELOC_MIPS_GOT_LO16
:
14366 case BFD_RELOC_MIPS_CALL_HI16
:
14367 case BFD_RELOC_MIPS_CALL_LO16
:
14368 case BFD_RELOC_MIPS16_GPREL
:
14369 case BFD_RELOC_MIPS16_GOT16
:
14370 case BFD_RELOC_MIPS16_CALL16
:
14371 case BFD_RELOC_MIPS16_HI16
:
14372 case BFD_RELOC_MIPS16_HI16_S
:
14373 case BFD_RELOC_MIPS16_LO16
:
14374 case BFD_RELOC_MIPS16_JMP
:
14375 case BFD_RELOC_MICROMIPS_JMP
:
14376 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14377 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14378 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14379 case BFD_RELOC_MICROMIPS_SUB
:
14380 case BFD_RELOC_MICROMIPS_HIGHEST
:
14381 case BFD_RELOC_MICROMIPS_HIGHER
:
14382 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14383 case BFD_RELOC_MICROMIPS_JALR
:
14384 case BFD_RELOC_MICROMIPS_HI16
:
14385 case BFD_RELOC_MICROMIPS_HI16_S
:
14386 case BFD_RELOC_MICROMIPS_LO16
:
14387 case BFD_RELOC_MICROMIPS_GPREL16
:
14388 case BFD_RELOC_MICROMIPS_LITERAL
:
14389 case BFD_RELOC_MICROMIPS_CALL16
:
14390 case BFD_RELOC_MICROMIPS_GOT16
:
14391 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14392 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14393 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14394 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14395 case BFD_RELOC_MIPS_EH
:
14400 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14402 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14403 if (mips16_reloc_p (fixP
->fx_r_type
))
14404 insn
|= mips16_immed_extend (value
, 16);
14406 insn
|= (value
& 0xffff);
14407 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14411 _("Unsupported constant in relocation"));
14416 /* This is handled like BFD_RELOC_32, but we output a sign
14417 extended value if we are only 32 bits. */
14420 if (8 <= sizeof (valueT
))
14421 md_number_to_chars (buf
, *valP
, 8);
14426 if ((*valP
& 0x80000000) != 0)
14430 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14431 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14436 case BFD_RELOC_RVA
:
14438 case BFD_RELOC_32_PCREL
:
14440 /* If we are deleting this reloc entry, we must fill in the
14441 value now. This can happen if we have a .word which is not
14442 resolved when it appears but is later defined. */
14444 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14447 case BFD_RELOC_16_PCREL_S2
:
14448 if ((*valP
& 0x3) != 0)
14449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14450 _("Branch to misaligned address (%lx)"), (long) *valP
);
14452 /* We need to save the bits in the instruction since fixup_segment()
14453 might be deleting the relocation entry (i.e., a branch within
14454 the current segment). */
14455 if (! fixP
->fx_done
)
14458 /* Update old instruction data. */
14459 insn
= read_insn (buf
);
14461 if (*valP
+ 0x20000 <= 0x3ffff)
14463 insn
|= (*valP
>> 2) & 0xffff;
14464 write_insn (buf
, insn
);
14466 else if (mips_pic
== NO_PIC
14468 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14469 && (fixP
->fx_frag
->fr_address
14470 < text_section
->vma
+ bfd_get_section_size (text_section
))
14471 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14472 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14473 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14475 /* The branch offset is too large. If this is an
14476 unconditional branch, and we are not generating PIC code,
14477 we can convert it to an absolute jump instruction. */
14478 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14479 insn
= 0x0c000000; /* jal */
14481 insn
= 0x08000000; /* j */
14482 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14484 fixP
->fx_addsy
= section_symbol (text_section
);
14485 *valP
+= md_pcrel_from (fixP
);
14486 write_insn (buf
, insn
);
14490 /* If we got here, we have branch-relaxation disabled,
14491 and there's nothing we can do to fix this instruction
14492 without turning it into a longer sequence. */
14493 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14494 _("Branch out of range"));
14498 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14499 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14500 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14501 /* We adjust the offset back to even. */
14502 if ((*valP
& 0x1) != 0)
14505 if (! fixP
->fx_done
)
14508 /* Should never visit here, because we keep the relocation. */
14512 case BFD_RELOC_VTABLE_INHERIT
:
14515 && !S_IS_DEFINED (fixP
->fx_addsy
)
14516 && !S_IS_WEAK (fixP
->fx_addsy
))
14517 S_SET_WEAK (fixP
->fx_addsy
);
14520 case BFD_RELOC_VTABLE_ENTRY
:
14528 /* Remember value for tc_gen_reloc. */
14529 fixP
->fx_addnumber
= *valP
;
14539 name
= input_line_pointer
;
14540 c
= get_symbol_end ();
14541 p
= (symbolS
*) symbol_find_or_make (name
);
14542 *input_line_pointer
= c
;
14546 /* Align the current frag to a given power of two. If a particular
14547 fill byte should be used, FILL points to an integer that contains
14548 that byte, otherwise FILL is null.
14550 This function used to have the comment:
14552 The MIPS assembler also automatically adjusts any preceding label.
14554 The implementation therefore applied the adjustment to a maximum of
14555 one label. However, other label adjustments are applied to batches
14556 of labels, and adjusting just one caused problems when new labels
14557 were added for the sake of debugging or unwind information.
14558 We therefore adjust all preceding labels (given as LABELS) instead. */
14561 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14563 mips_emit_delays ();
14564 mips_record_compressed_mode ();
14565 if (fill
== NULL
&& subseg_text_p (now_seg
))
14566 frag_align_code (to
, 0);
14568 frag_align (to
, fill
? *fill
: 0, 0);
14569 record_alignment (now_seg
, to
);
14570 mips_move_labels (labels
, FALSE
);
14573 /* Align to a given power of two. .align 0 turns off the automatic
14574 alignment used by the data creating pseudo-ops. */
14577 s_align (int x ATTRIBUTE_UNUSED
)
14579 int temp
, fill_value
, *fill_ptr
;
14580 long max_alignment
= 28;
14582 /* o Note that the assembler pulls down any immediately preceding label
14583 to the aligned address.
14584 o It's not documented but auto alignment is reinstated by
14585 a .align pseudo instruction.
14586 o Note also that after auto alignment is turned off the mips assembler
14587 issues an error on attempt to assemble an improperly aligned data item.
14590 temp
= get_absolute_expression ();
14591 if (temp
> max_alignment
)
14592 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14595 as_warn (_("Alignment negative: 0 assumed."));
14598 if (*input_line_pointer
== ',')
14600 ++input_line_pointer
;
14601 fill_value
= get_absolute_expression ();
14602 fill_ptr
= &fill_value
;
14608 segment_info_type
*si
= seg_info (now_seg
);
14609 struct insn_label_list
*l
= si
->label_list
;
14610 /* Auto alignment should be switched on by next section change. */
14612 mips_align (temp
, fill_ptr
, l
);
14619 demand_empty_rest_of_line ();
14623 s_change_sec (int sec
)
14627 /* The ELF backend needs to know that we are changing sections, so
14628 that .previous works correctly. We could do something like check
14629 for an obj_section_change_hook macro, but that might be confusing
14630 as it would not be appropriate to use it in the section changing
14631 functions in read.c, since obj-elf.c intercepts those. FIXME:
14632 This should be cleaner, somehow. */
14633 obj_elf_section_change_hook ();
14635 mips_emit_delays ();
14646 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14647 demand_empty_rest_of_line ();
14651 seg
= subseg_new (RDATA_SECTION_NAME
,
14652 (subsegT
) get_absolute_expression ());
14653 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14654 | SEC_READONLY
| SEC_RELOC
14656 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14657 record_alignment (seg
, 4);
14658 demand_empty_rest_of_line ();
14662 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14663 bfd_set_section_flags (stdoutput
, seg
,
14664 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14665 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14666 record_alignment (seg
, 4);
14667 demand_empty_rest_of_line ();
14671 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14672 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14673 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14674 record_alignment (seg
, 4);
14675 demand_empty_rest_of_line ();
14683 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14685 char *section_name
;
14690 int section_entry_size
;
14691 int section_alignment
;
14693 section_name
= input_line_pointer
;
14694 c
= get_symbol_end ();
14696 next_c
= *(input_line_pointer
+ 1);
14698 /* Do we have .section Name<,"flags">? */
14699 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14701 /* just after name is now '\0'. */
14702 *input_line_pointer
= c
;
14703 input_line_pointer
= section_name
;
14704 obj_elf_section (ignore
);
14707 input_line_pointer
++;
14709 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14711 section_type
= get_absolute_expression ();
14714 if (*input_line_pointer
++ == ',')
14715 section_flag
= get_absolute_expression ();
14718 if (*input_line_pointer
++ == ',')
14719 section_entry_size
= get_absolute_expression ();
14721 section_entry_size
= 0;
14722 if (*input_line_pointer
++ == ',')
14723 section_alignment
= get_absolute_expression ();
14725 section_alignment
= 0;
14726 /* FIXME: really ignore? */
14727 (void) section_alignment
;
14729 section_name
= xstrdup (section_name
);
14731 /* When using the generic form of .section (as implemented by obj-elf.c),
14732 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14733 traditionally had to fall back on the more common @progbits instead.
14735 There's nothing really harmful in this, since bfd will correct
14736 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14737 means that, for backwards compatibility, the special_section entries
14738 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14740 Even so, we shouldn't force users of the MIPS .section syntax to
14741 incorrectly label the sections as SHT_PROGBITS. The best compromise
14742 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14743 generic type-checking code. */
14744 if (section_type
== SHT_MIPS_DWARF
)
14745 section_type
= SHT_PROGBITS
;
14747 obj_elf_change_section (section_name
, section_type
, section_flag
,
14748 section_entry_size
, 0, 0, 0);
14750 if (now_seg
->name
!= section_name
)
14751 free (section_name
);
14755 mips_enable_auto_align (void)
14761 s_cons (int log_size
)
14763 segment_info_type
*si
= seg_info (now_seg
);
14764 struct insn_label_list
*l
= si
->label_list
;
14766 mips_emit_delays ();
14767 if (log_size
> 0 && auto_align
)
14768 mips_align (log_size
, 0, l
);
14769 cons (1 << log_size
);
14770 mips_clear_insn_labels ();
14774 s_float_cons (int type
)
14776 segment_info_type
*si
= seg_info (now_seg
);
14777 struct insn_label_list
*l
= si
->label_list
;
14779 mips_emit_delays ();
14784 mips_align (3, 0, l
);
14786 mips_align (2, 0, l
);
14790 mips_clear_insn_labels ();
14793 /* Handle .globl. We need to override it because on Irix 5 you are
14796 where foo is an undefined symbol, to mean that foo should be
14797 considered to be the address of a function. */
14800 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14809 name
= input_line_pointer
;
14810 c
= get_symbol_end ();
14811 symbolP
= symbol_find_or_make (name
);
14812 S_SET_EXTERNAL (symbolP
);
14814 *input_line_pointer
= c
;
14815 SKIP_WHITESPACE ();
14817 /* On Irix 5, every global symbol that is not explicitly labelled as
14818 being a function is apparently labelled as being an object. */
14821 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14822 && (*input_line_pointer
!= ','))
14827 secname
= input_line_pointer
;
14828 c
= get_symbol_end ();
14829 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14831 as_bad (_("%s: no such section"), secname
);
14832 *input_line_pointer
= c
;
14834 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14835 flag
= BSF_FUNCTION
;
14838 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14840 c
= *input_line_pointer
;
14843 input_line_pointer
++;
14844 SKIP_WHITESPACE ();
14845 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14851 demand_empty_rest_of_line ();
14855 s_option (int x ATTRIBUTE_UNUSED
)
14860 opt
= input_line_pointer
;
14861 c
= get_symbol_end ();
14865 /* FIXME: What does this mean? */
14867 else if (strncmp (opt
, "pic", 3) == 0)
14871 i
= atoi (opt
+ 3);
14876 mips_pic
= SVR4_PIC
;
14877 mips_abicalls
= TRUE
;
14880 as_bad (_(".option pic%d not supported"), i
);
14882 if (mips_pic
== SVR4_PIC
)
14884 if (g_switch_seen
&& g_switch_value
!= 0)
14885 as_warn (_("-G may not be used with SVR4 PIC code"));
14886 g_switch_value
= 0;
14887 bfd_set_gp_size (stdoutput
, 0);
14891 as_warn (_("Unrecognized option \"%s\""), opt
);
14893 *input_line_pointer
= c
;
14894 demand_empty_rest_of_line ();
14897 /* This structure is used to hold a stack of .set values. */
14899 struct mips_option_stack
14901 struct mips_option_stack
*next
;
14902 struct mips_set_options options
;
14905 static struct mips_option_stack
*mips_opts_stack
;
14907 /* Handle the .set pseudo-op. */
14910 s_mipsset (int x ATTRIBUTE_UNUSED
)
14912 char *name
= input_line_pointer
, ch
;
14913 const struct mips_ase
*ase
;
14915 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14916 ++input_line_pointer
;
14917 ch
= *input_line_pointer
;
14918 *input_line_pointer
= '\0';
14920 if (strcmp (name
, "reorder") == 0)
14922 if (mips_opts
.noreorder
)
14925 else if (strcmp (name
, "noreorder") == 0)
14927 if (!mips_opts
.noreorder
)
14928 start_noreorder ();
14930 else if (strncmp (name
, "at=", 3) == 0)
14932 char *s
= name
+ 3;
14934 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14935 as_bad (_("Unrecognized register name `%s'"), s
);
14937 else if (strcmp (name
, "at") == 0)
14939 mips_opts
.at
= ATREG
;
14941 else if (strcmp (name
, "noat") == 0)
14943 mips_opts
.at
= ZERO
;
14945 else if (strcmp (name
, "macro") == 0)
14947 mips_opts
.warn_about_macros
= 0;
14949 else if (strcmp (name
, "nomacro") == 0)
14951 if (mips_opts
.noreorder
== 0)
14952 as_bad (_("`noreorder' must be set before `nomacro'"));
14953 mips_opts
.warn_about_macros
= 1;
14955 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
14957 mips_opts
.nomove
= 0;
14959 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
14961 mips_opts
.nomove
= 1;
14963 else if (strcmp (name
, "bopt") == 0)
14965 mips_opts
.nobopt
= 0;
14967 else if (strcmp (name
, "nobopt") == 0)
14969 mips_opts
.nobopt
= 1;
14971 else if (strcmp (name
, "gp=default") == 0)
14972 mips_opts
.gp32
= file_mips_gp32
;
14973 else if (strcmp (name
, "gp=32") == 0)
14974 mips_opts
.gp32
= 1;
14975 else if (strcmp (name
, "gp=64") == 0)
14977 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14978 as_warn (_("%s isa does not support 64-bit registers"),
14979 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14980 mips_opts
.gp32
= 0;
14982 else if (strcmp (name
, "fp=default") == 0)
14983 mips_opts
.fp32
= file_mips_fp32
;
14984 else if (strcmp (name
, "fp=32") == 0)
14985 mips_opts
.fp32
= 1;
14986 else if (strcmp (name
, "fp=64") == 0)
14988 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14989 as_warn (_("%s isa does not support 64-bit floating point registers"),
14990 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14991 mips_opts
.fp32
= 0;
14993 else if (strcmp (name
, "softfloat") == 0)
14994 mips_opts
.soft_float
= 1;
14995 else if (strcmp (name
, "hardfloat") == 0)
14996 mips_opts
.soft_float
= 0;
14997 else if (strcmp (name
, "singlefloat") == 0)
14998 mips_opts
.single_float
= 1;
14999 else if (strcmp (name
, "doublefloat") == 0)
15000 mips_opts
.single_float
= 0;
15001 else if (strcmp (name
, "mips16") == 0
15002 || strcmp (name
, "MIPS-16") == 0)
15004 if (mips_opts
.micromips
== 1)
15005 as_fatal (_("`mips16' cannot be used with `micromips'"));
15006 mips_opts
.mips16
= 1;
15008 else if (strcmp (name
, "nomips16") == 0
15009 || strcmp (name
, "noMIPS-16") == 0)
15010 mips_opts
.mips16
= 0;
15011 else if (strcmp (name
, "micromips") == 0)
15013 if (mips_opts
.mips16
== 1)
15014 as_fatal (_("`micromips' cannot be used with `mips16'"));
15015 mips_opts
.micromips
= 1;
15017 else if (strcmp (name
, "nomicromips") == 0)
15018 mips_opts
.micromips
= 0;
15019 else if (name
[0] == 'n'
15021 && (ase
= mips_lookup_ase (name
+ 2)))
15022 mips_set_ase (ase
, FALSE
);
15023 else if ((ase
= mips_lookup_ase (name
)))
15024 mips_set_ase (ase
, TRUE
);
15025 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15029 /* Permit the user to change the ISA and architecture on the fly.
15030 Needless to say, misuse can cause serious problems. */
15031 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15034 mips_opts
.isa
= file_mips_isa
;
15035 mips_opts
.arch
= file_mips_arch
;
15037 else if (strncmp (name
, "arch=", 5) == 0)
15039 const struct mips_cpu_info
*p
;
15041 p
= mips_parse_cpu("internal use", name
+ 5);
15043 as_bad (_("unknown architecture %s"), name
+ 5);
15046 mips_opts
.arch
= p
->cpu
;
15047 mips_opts
.isa
= p
->isa
;
15050 else if (strncmp (name
, "mips", 4) == 0)
15052 const struct mips_cpu_info
*p
;
15054 p
= mips_parse_cpu("internal use", name
);
15056 as_bad (_("unknown ISA level %s"), name
+ 4);
15059 mips_opts
.arch
= p
->cpu
;
15060 mips_opts
.isa
= p
->isa
;
15064 as_bad (_("unknown ISA or architecture %s"), name
);
15066 switch (mips_opts
.isa
)
15074 mips_opts
.gp32
= 1;
15075 mips_opts
.fp32
= 1;
15082 mips_opts
.gp32
= 0;
15083 if (mips_opts
.arch
== CPU_R5900
)
15085 mips_opts
.fp32
= 1;
15089 mips_opts
.fp32
= 0;
15093 as_bad (_("unknown ISA level %s"), name
+ 4);
15098 mips_opts
.gp32
= file_mips_gp32
;
15099 mips_opts
.fp32
= file_mips_fp32
;
15102 else if (strcmp (name
, "autoextend") == 0)
15103 mips_opts
.noautoextend
= 0;
15104 else if (strcmp (name
, "noautoextend") == 0)
15105 mips_opts
.noautoextend
= 1;
15106 else if (strcmp (name
, "insn32") == 0)
15107 mips_opts
.insn32
= TRUE
;
15108 else if (strcmp (name
, "noinsn32") == 0)
15109 mips_opts
.insn32
= FALSE
;
15110 else if (strcmp (name
, "push") == 0)
15112 struct mips_option_stack
*s
;
15114 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15115 s
->next
= mips_opts_stack
;
15116 s
->options
= mips_opts
;
15117 mips_opts_stack
= s
;
15119 else if (strcmp (name
, "pop") == 0)
15121 struct mips_option_stack
*s
;
15123 s
= mips_opts_stack
;
15125 as_bad (_(".set pop with no .set push"));
15128 /* If we're changing the reorder mode we need to handle
15129 delay slots correctly. */
15130 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15131 start_noreorder ();
15132 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15135 mips_opts
= s
->options
;
15136 mips_opts_stack
= s
->next
;
15140 else if (strcmp (name
, "sym32") == 0)
15141 mips_opts
.sym32
= TRUE
;
15142 else if (strcmp (name
, "nosym32") == 0)
15143 mips_opts
.sym32
= FALSE
;
15144 else if (strchr (name
, ','))
15146 /* Generic ".set" directive; use the generic handler. */
15147 *input_line_pointer
= ch
;
15148 input_line_pointer
= name
;
15154 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
15156 mips_check_isa_supports_ases ();
15157 *input_line_pointer
= ch
;
15158 demand_empty_rest_of_line ();
15161 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15162 .option pic2. It means to generate SVR4 PIC calls. */
15165 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15167 mips_pic
= SVR4_PIC
;
15168 mips_abicalls
= TRUE
;
15170 if (g_switch_seen
&& g_switch_value
!= 0)
15171 as_warn (_("-G may not be used with SVR4 PIC code"));
15172 g_switch_value
= 0;
15174 bfd_set_gp_size (stdoutput
, 0);
15175 demand_empty_rest_of_line ();
15178 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15179 PIC code. It sets the $gp register for the function based on the
15180 function address, which is in the register named in the argument.
15181 This uses a relocation against _gp_disp, which is handled specially
15182 by the linker. The result is:
15183 lui $gp,%hi(_gp_disp)
15184 addiu $gp,$gp,%lo(_gp_disp)
15185 addu $gp,$gp,.cpload argument
15186 The .cpload argument is normally $25 == $t9.
15188 The -mno-shared option changes this to:
15189 lui $gp,%hi(__gnu_local_gp)
15190 addiu $gp,$gp,%lo(__gnu_local_gp)
15191 and the argument is ignored. This saves an instruction, but the
15192 resulting code is not position independent; it uses an absolute
15193 address for __gnu_local_gp. Thus code assembled with -mno-shared
15194 can go into an ordinary executable, but not into a shared library. */
15197 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15203 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15204 .cpload is ignored. */
15205 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15211 if (mips_opts
.mips16
)
15213 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15214 ignore_rest_of_line ();
15218 /* .cpload should be in a .set noreorder section. */
15219 if (mips_opts
.noreorder
== 0)
15220 as_warn (_(".cpload not in noreorder section"));
15222 reg
= tc_get_register (0);
15224 /* If we need to produce a 64-bit address, we are better off using
15225 the default instruction sequence. */
15226 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15228 ex
.X_op
= O_symbol
;
15229 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15231 ex
.X_op_symbol
= NULL
;
15232 ex
.X_add_number
= 0;
15234 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15235 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15237 mips_mark_labels ();
15238 mips_assembling_insn
= TRUE
;
15241 macro_build_lui (&ex
, mips_gp_register
);
15242 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15243 mips_gp_register
, BFD_RELOC_LO16
);
15245 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15246 mips_gp_register
, reg
);
15249 mips_assembling_insn
= FALSE
;
15250 demand_empty_rest_of_line ();
15253 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15254 .cpsetup $reg1, offset|$reg2, label
15256 If offset is given, this results in:
15257 sd $gp, offset($sp)
15258 lui $gp, %hi(%neg(%gp_rel(label)))
15259 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15260 daddu $gp, $gp, $reg1
15262 If $reg2 is given, this results in:
15263 daddu $reg2, $gp, $0
15264 lui $gp, %hi(%neg(%gp_rel(label)))
15265 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15266 daddu $gp, $gp, $reg1
15267 $reg1 is normally $25 == $t9.
15269 The -mno-shared option replaces the last three instructions with
15271 addiu $gp,$gp,%lo(_gp) */
15274 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15276 expressionS ex_off
;
15277 expressionS ex_sym
;
15280 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15281 We also need NewABI support. */
15282 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15288 if (mips_opts
.mips16
)
15290 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15291 ignore_rest_of_line ();
15295 reg1
= tc_get_register (0);
15296 SKIP_WHITESPACE ();
15297 if (*input_line_pointer
!= ',')
15299 as_bad (_("missing argument separator ',' for .cpsetup"));
15303 ++input_line_pointer
;
15304 SKIP_WHITESPACE ();
15305 if (*input_line_pointer
== '$')
15307 mips_cpreturn_register
= tc_get_register (0);
15308 mips_cpreturn_offset
= -1;
15312 mips_cpreturn_offset
= get_absolute_expression ();
15313 mips_cpreturn_register
= -1;
15315 SKIP_WHITESPACE ();
15316 if (*input_line_pointer
!= ',')
15318 as_bad (_("missing argument separator ',' for .cpsetup"));
15322 ++input_line_pointer
;
15323 SKIP_WHITESPACE ();
15324 expression (&ex_sym
);
15326 mips_mark_labels ();
15327 mips_assembling_insn
= TRUE
;
15330 if (mips_cpreturn_register
== -1)
15332 ex_off
.X_op
= O_constant
;
15333 ex_off
.X_add_symbol
= NULL
;
15334 ex_off
.X_op_symbol
= NULL
;
15335 ex_off
.X_add_number
= mips_cpreturn_offset
;
15337 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15338 BFD_RELOC_LO16
, SP
);
15341 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15342 mips_gp_register
, 0);
15344 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15346 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15347 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15350 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15351 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15352 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15354 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15355 mips_gp_register
, reg1
);
15361 ex
.X_op
= O_symbol
;
15362 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15363 ex
.X_op_symbol
= NULL
;
15364 ex
.X_add_number
= 0;
15366 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15367 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15369 macro_build_lui (&ex
, mips_gp_register
);
15370 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15371 mips_gp_register
, BFD_RELOC_LO16
);
15376 mips_assembling_insn
= FALSE
;
15377 demand_empty_rest_of_line ();
15381 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15383 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15384 .cplocal is ignored. */
15385 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15391 if (mips_opts
.mips16
)
15393 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15394 ignore_rest_of_line ();
15398 mips_gp_register
= tc_get_register (0);
15399 demand_empty_rest_of_line ();
15402 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15403 offset from $sp. The offset is remembered, and after making a PIC
15404 call $gp is restored from that location. */
15407 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15411 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15412 .cprestore is ignored. */
15413 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15419 if (mips_opts
.mips16
)
15421 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15422 ignore_rest_of_line ();
15426 mips_cprestore_offset
= get_absolute_expression ();
15427 mips_cprestore_valid
= 1;
15429 ex
.X_op
= O_constant
;
15430 ex
.X_add_symbol
= NULL
;
15431 ex
.X_op_symbol
= NULL
;
15432 ex
.X_add_number
= mips_cprestore_offset
;
15434 mips_mark_labels ();
15435 mips_assembling_insn
= TRUE
;
15438 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15439 SP
, HAVE_64BIT_ADDRESSES
);
15442 mips_assembling_insn
= FALSE
;
15443 demand_empty_rest_of_line ();
15446 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15447 was given in the preceding .cpsetup, it results in:
15448 ld $gp, offset($sp)
15450 If a register $reg2 was given there, it results in:
15451 daddu $gp, $reg2, $0 */
15454 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15458 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15459 We also need NewABI support. */
15460 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15466 if (mips_opts
.mips16
)
15468 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15469 ignore_rest_of_line ();
15473 mips_mark_labels ();
15474 mips_assembling_insn
= TRUE
;
15477 if (mips_cpreturn_register
== -1)
15479 ex
.X_op
= O_constant
;
15480 ex
.X_add_symbol
= NULL
;
15481 ex
.X_op_symbol
= NULL
;
15482 ex
.X_add_number
= mips_cpreturn_offset
;
15484 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15487 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15488 mips_cpreturn_register
, 0);
15491 mips_assembling_insn
= FALSE
;
15492 demand_empty_rest_of_line ();
15495 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15496 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15497 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15498 debug information or MIPS16 TLS. */
15501 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15502 bfd_reloc_code_real_type rtype
)
15509 if (ex
.X_op
!= O_symbol
)
15511 as_bad (_("Unsupported use of %s"), dirstr
);
15512 ignore_rest_of_line ();
15515 p
= frag_more (bytes
);
15516 md_number_to_chars (p
, 0, bytes
);
15517 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15518 demand_empty_rest_of_line ();
15519 mips_clear_insn_labels ();
15522 /* Handle .dtprelword. */
15525 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15527 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15530 /* Handle .dtpreldword. */
15533 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15535 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15538 /* Handle .tprelword. */
15541 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15543 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15546 /* Handle .tpreldword. */
15549 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15551 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15554 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15555 code. It sets the offset to use in gp_rel relocations. */
15558 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15560 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15561 We also need NewABI support. */
15562 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15568 mips_gprel_offset
= get_absolute_expression ();
15570 demand_empty_rest_of_line ();
15573 /* Handle the .gpword pseudo-op. This is used when generating PIC
15574 code. It generates a 32 bit GP relative reloc. */
15577 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15579 segment_info_type
*si
;
15580 struct insn_label_list
*l
;
15584 /* When not generating PIC code, this is treated as .word. */
15585 if (mips_pic
!= SVR4_PIC
)
15591 si
= seg_info (now_seg
);
15592 l
= si
->label_list
;
15593 mips_emit_delays ();
15595 mips_align (2, 0, l
);
15598 mips_clear_insn_labels ();
15600 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15602 as_bad (_("Unsupported use of .gpword"));
15603 ignore_rest_of_line ();
15607 md_number_to_chars (p
, 0, 4);
15608 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15609 BFD_RELOC_GPREL32
);
15611 demand_empty_rest_of_line ();
15615 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15617 segment_info_type
*si
;
15618 struct insn_label_list
*l
;
15622 /* When not generating PIC code, this is treated as .dword. */
15623 if (mips_pic
!= SVR4_PIC
)
15629 si
= seg_info (now_seg
);
15630 l
= si
->label_list
;
15631 mips_emit_delays ();
15633 mips_align (3, 0, l
);
15636 mips_clear_insn_labels ();
15638 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15640 as_bad (_("Unsupported use of .gpdword"));
15641 ignore_rest_of_line ();
15645 md_number_to_chars (p
, 0, 8);
15646 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15647 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15649 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15650 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15651 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15653 demand_empty_rest_of_line ();
15656 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15657 tables. It generates a R_MIPS_EH reloc. */
15660 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15665 mips_emit_delays ();
15668 mips_clear_insn_labels ();
15670 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15672 as_bad (_("Unsupported use of .ehword"));
15673 ignore_rest_of_line ();
15677 md_number_to_chars (p
, 0, 4);
15678 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15679 BFD_RELOC_MIPS_EH
);
15681 demand_empty_rest_of_line ();
15684 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15685 tables in SVR4 PIC code. */
15688 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15692 /* This is ignored when not generating SVR4 PIC code. */
15693 if (mips_pic
!= SVR4_PIC
)
15699 mips_mark_labels ();
15700 mips_assembling_insn
= TRUE
;
15702 /* Add $gp to the register named as an argument. */
15704 reg
= tc_get_register (0);
15705 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15708 mips_assembling_insn
= FALSE
;
15709 demand_empty_rest_of_line ();
15712 /* Handle the .insn pseudo-op. This marks instruction labels in
15713 mips16/micromips mode. This permits the linker to handle them specially,
15714 such as generating jalx instructions when needed. We also make
15715 them odd for the duration of the assembly, in order to generate the
15716 right sort of code. We will make them even in the adjust_symtab
15717 routine, while leaving them marked. This is convenient for the
15718 debugger and the disassembler. The linker knows to make them odd
15722 s_insn (int ignore ATTRIBUTE_UNUSED
)
15724 mips_mark_labels ();
15726 demand_empty_rest_of_line ();
15729 /* Handle the .nan pseudo-op. */
15732 s_nan (int ignore ATTRIBUTE_UNUSED
)
15734 static const char str_legacy
[] = "legacy";
15735 static const char str_2008
[] = "2008";
15738 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15740 if (i
== sizeof (str_2008
) - 1
15741 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15742 mips_flag_nan2008
= TRUE
;
15743 else if (i
== sizeof (str_legacy
) - 1
15744 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15745 mips_flag_nan2008
= FALSE
;
15747 as_bad (_("Bad .nan directive"));
15749 input_line_pointer
+= i
;
15750 demand_empty_rest_of_line ();
15753 /* Handle a .stab[snd] directive. Ideally these directives would be
15754 implemented in a transparent way, so that removing them would not
15755 have any effect on the generated instructions. However, s_stab
15756 internally changes the section, so in practice we need to decide
15757 now whether the preceding label marks compressed code. We do not
15758 support changing the compression mode of a label after a .stab*
15759 directive, such as in:
15765 so the current mode wins. */
15768 s_mips_stab (int type
)
15770 mips_mark_labels ();
15774 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15777 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15784 name
= input_line_pointer
;
15785 c
= get_symbol_end ();
15786 symbolP
= symbol_find_or_make (name
);
15787 S_SET_WEAK (symbolP
);
15788 *input_line_pointer
= c
;
15790 SKIP_WHITESPACE ();
15792 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15794 if (S_IS_DEFINED (symbolP
))
15796 as_bad (_("ignoring attempt to redefine symbol %s"),
15797 S_GET_NAME (symbolP
));
15798 ignore_rest_of_line ();
15802 if (*input_line_pointer
== ',')
15804 ++input_line_pointer
;
15805 SKIP_WHITESPACE ();
15809 if (exp
.X_op
!= O_symbol
)
15811 as_bad (_("bad .weakext directive"));
15812 ignore_rest_of_line ();
15815 symbol_set_value_expression (symbolP
, &exp
);
15818 demand_empty_rest_of_line ();
15821 /* Parse a register string into a number. Called from the ECOFF code
15822 to parse .frame. The argument is non-zero if this is the frame
15823 register, so that we can record it in mips_frame_reg. */
15826 tc_get_register (int frame
)
15830 SKIP_WHITESPACE ();
15831 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15835 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15836 mips_frame_reg_valid
= 1;
15837 mips_cprestore_valid
= 0;
15843 md_section_align (asection
*seg
, valueT addr
)
15845 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15847 /* We don't need to align ELF sections to the full alignment.
15848 However, Irix 5 may prefer that we align them at least to a 16
15849 byte boundary. We don't bother to align the sections if we
15850 are targeted for an embedded system. */
15851 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15856 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15859 /* Utility routine, called from above as well. If called while the
15860 input file is still being read, it's only an approximation. (For
15861 example, a symbol may later become defined which appeared to be
15862 undefined earlier.) */
15865 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15870 if (g_switch_value
> 0)
15872 const char *symname
;
15875 /* Find out whether this symbol can be referenced off the $gp
15876 register. It can be if it is smaller than the -G size or if
15877 it is in the .sdata or .sbss section. Certain symbols can
15878 not be referenced off the $gp, although it appears as though
15880 symname
= S_GET_NAME (sym
);
15881 if (symname
!= (const char *) NULL
15882 && (strcmp (symname
, "eprol") == 0
15883 || strcmp (symname
, "etext") == 0
15884 || strcmp (symname
, "_gp") == 0
15885 || strcmp (symname
, "edata") == 0
15886 || strcmp (symname
, "_fbss") == 0
15887 || strcmp (symname
, "_fdata") == 0
15888 || strcmp (symname
, "_ftext") == 0
15889 || strcmp (symname
, "end") == 0
15890 || strcmp (symname
, "_gp_disp") == 0))
15892 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15894 #ifndef NO_ECOFF_DEBUGGING
15895 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15896 && (symbol_get_obj (sym
)->ecoff_extern_size
15897 <= g_switch_value
))
15899 /* We must defer this decision until after the whole
15900 file has been read, since there might be a .extern
15901 after the first use of this symbol. */
15902 || (before_relaxing
15903 #ifndef NO_ECOFF_DEBUGGING
15904 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15906 && S_GET_VALUE (sym
) == 0)
15907 || (S_GET_VALUE (sym
) != 0
15908 && S_GET_VALUE (sym
) <= g_switch_value
)))
15912 const char *segname
;
15914 segname
= segment_name (S_GET_SEGMENT (sym
));
15915 gas_assert (strcmp (segname
, ".lit8") != 0
15916 && strcmp (segname
, ".lit4") != 0);
15917 change
= (strcmp (segname
, ".sdata") != 0
15918 && strcmp (segname
, ".sbss") != 0
15919 && strncmp (segname
, ".sdata.", 7) != 0
15920 && strncmp (segname
, ".sbss.", 6) != 0
15921 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15922 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15927 /* We are not optimizing for the $gp register. */
15932 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15935 pic_need_relax (symbolS
*sym
, asection
*segtype
)
15939 /* Handle the case of a symbol equated to another symbol. */
15940 while (symbol_equated_reloc_p (sym
))
15944 /* It's possible to get a loop here in a badly written program. */
15945 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
15951 if (symbol_section_p (sym
))
15954 symsec
= S_GET_SEGMENT (sym
);
15956 /* This must duplicate the test in adjust_reloc_syms. */
15957 return (!bfd_is_und_section (symsec
)
15958 && !bfd_is_abs_section (symsec
)
15959 && !bfd_is_com_section (symsec
)
15960 && !s_is_linkonce (sym
, segtype
)
15961 /* A global or weak symbol is treated as external. */
15962 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
15966 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
15967 extended opcode. SEC is the section the frag is in. */
15970 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
15973 const struct mips_int_operand
*operand
;
15978 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
15980 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
15983 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
15984 operand
= mips16_immed_operand (type
, FALSE
);
15986 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
15987 val
= S_GET_VALUE (fragp
->fr_symbol
);
15988 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
15990 if (operand
->root
.type
== OP_PCREL
)
15992 const struct mips_pcrel_operand
*pcrel_op
;
15996 /* We won't have the section when we are called from
15997 mips_relax_frag. However, we will always have been called
15998 from md_estimate_size_before_relax first. If this is a
15999 branch to a different section, we mark it as such. If SEC is
16000 NULL, and the frag is not marked, then it must be a branch to
16001 the same section. */
16002 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16005 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16010 /* Must have been called from md_estimate_size_before_relax. */
16013 fragp
->fr_subtype
=
16014 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16016 /* FIXME: We should support this, and let the linker
16017 catch branches and loads that are out of range. */
16018 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16019 _("unsupported PC relative reference to different section"));
16023 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16024 /* Assume non-extended on the first relaxation pass.
16025 The address we have calculated will be bogus if this is
16026 a forward branch to another frag, as the forward frag
16027 will have fr_address == 0. */
16031 /* In this case, we know for sure that the symbol fragment is in
16032 the same section. If the relax_marker of the symbol fragment
16033 differs from the relax_marker of this fragment, we have not
16034 yet adjusted the symbol fragment fr_address. We want to add
16035 in STRETCH in order to get a better estimate of the address.
16036 This particularly matters because of the shift bits. */
16038 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16042 /* Adjust stretch for any alignment frag. Note that if have
16043 been expanding the earlier code, the symbol may be
16044 defined in what appears to be an earlier frag. FIXME:
16045 This doesn't handle the fr_subtype field, which specifies
16046 a maximum number of bytes to skip when doing an
16048 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16050 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16053 stretch
= - ((- stretch
)
16054 & ~ ((1 << (int) f
->fr_offset
) - 1));
16056 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16065 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16067 /* The base address rules are complicated. The base address of
16068 a branch is the following instruction. The base address of a
16069 PC relative load or add is the instruction itself, but if it
16070 is in a delay slot (in which case it can not be extended) use
16071 the address of the instruction whose delay slot it is in. */
16072 if (pcrel_op
->include_isa_bit
)
16076 /* If we are currently assuming that this frag should be
16077 extended, then, the current address is two bytes
16079 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16082 /* Ignore the low bit in the target, since it will be set
16083 for a text label. */
16086 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16088 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16091 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16093 /* If any of the shifted bits are set, we must use an extended
16094 opcode. If the address depends on the size of this
16095 instruction, this can lead to a loop, so we arrange to always
16096 use an extended opcode. We only check this when we are in
16097 the main relaxation loop, when SEC is NULL. */
16098 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16100 fragp
->fr_subtype
=
16101 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16105 /* If we are about to mark a frag as extended because the value
16106 is precisely the next value above maxtiny, then there is a
16107 chance of an infinite loop as in the following code:
16112 In this case when the la is extended, foo is 0x3fc bytes
16113 away, so the la can be shrunk, but then foo is 0x400 away, so
16114 the la must be extended. To avoid this loop, we mark the
16115 frag as extended if it was small, and is about to become
16116 extended with the next value above maxtiny. */
16117 maxtiny
= mips_int_operand_max (operand
);
16118 if (val
== maxtiny
+ (1 << operand
->shift
)
16119 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16122 fragp
->fr_subtype
=
16123 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16127 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16128 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16130 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16133 /* Compute the length of a branch sequence, and adjust the
16134 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16135 worst-case length is computed, with UPDATE being used to indicate
16136 whether an unconditional (-1), branch-likely (+1) or regular (0)
16137 branch is to be computed. */
16139 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16141 bfd_boolean toofar
;
16145 && S_IS_DEFINED (fragp
->fr_symbol
)
16146 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16151 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16153 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16157 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16160 /* If the symbol is not defined or it's in a different segment,
16161 assume the user knows what's going on and emit a short
16167 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16169 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16170 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16171 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16172 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16178 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16181 if (mips_pic
!= NO_PIC
)
16183 /* Additional space for PIC loading of target address. */
16185 if (mips_opts
.isa
== ISA_MIPS1
)
16186 /* Additional space for $at-stabilizing nop. */
16190 /* If branch is conditional. */
16191 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16198 /* Compute the length of a branch sequence, and adjust the
16199 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16200 worst-case length is computed, with UPDATE being used to indicate
16201 whether an unconditional (-1), or regular (0) branch is to be
16205 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16207 bfd_boolean toofar
;
16211 && S_IS_DEFINED (fragp
->fr_symbol
)
16212 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16217 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16218 /* Ignore the low bit in the target, since it will be set
16219 for a text label. */
16220 if ((val
& 1) != 0)
16223 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16227 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16230 /* If the symbol is not defined or it's in a different segment,
16231 assume the user knows what's going on and emit a short
16237 if (fragp
&& update
16238 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16239 fragp
->fr_subtype
= (toofar
16240 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16241 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16246 bfd_boolean compact_known
= fragp
!= NULL
;
16247 bfd_boolean compact
= FALSE
;
16248 bfd_boolean uncond
;
16251 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16253 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16255 uncond
= update
< 0;
16257 /* If label is out of range, we turn branch <br>:
16259 <br> label # 4 bytes
16265 nop # 2 bytes if compact && !PIC
16268 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16271 /* If assembling PIC code, we further turn:
16277 lw/ld at, %got(label)(gp) # 4 bytes
16278 d/addiu at, %lo(label) # 4 bytes
16281 if (mips_pic
!= NO_PIC
)
16284 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16286 <brneg> 0f # 4 bytes
16287 nop # 2 bytes if !compact
16290 length
+= (compact_known
&& compact
) ? 4 : 6;
16296 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16297 bit accordingly. */
16300 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16302 bfd_boolean toofar
;
16305 && S_IS_DEFINED (fragp
->fr_symbol
)
16306 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16312 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16313 /* Ignore the low bit in the target, since it will be set
16314 for a text label. */
16315 if ((val
& 1) != 0)
16318 /* Assume this is a 2-byte branch. */
16319 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16321 /* We try to avoid the infinite loop by not adding 2 more bytes for
16326 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16328 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16329 else if (type
== 'E')
16330 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16335 /* If the symbol is not defined or it's in a different segment,
16336 we emit a normal 32-bit branch. */
16339 if (fragp
&& update
16340 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16342 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16343 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16351 /* Estimate the size of a frag before relaxing. Unless this is the
16352 mips16, we are not really relaxing here, and the final size is
16353 encoded in the subtype information. For the mips16, we have to
16354 decide whether we are using an extended opcode or not. */
16357 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16361 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16364 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16366 return fragp
->fr_var
;
16369 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16370 /* We don't want to modify the EXTENDED bit here; it might get us
16371 into infinite loops. We change it only in mips_relax_frag(). */
16372 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16374 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16378 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16379 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16380 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16381 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16382 fragp
->fr_var
= length
;
16387 if (mips_pic
== NO_PIC
)
16388 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16389 else if (mips_pic
== SVR4_PIC
)
16390 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16391 else if (mips_pic
== VXWORKS_PIC
)
16392 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16399 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16400 return -RELAX_FIRST (fragp
->fr_subtype
);
16403 return -RELAX_SECOND (fragp
->fr_subtype
);
16406 /* This is called to see whether a reloc against a defined symbol
16407 should be converted into a reloc against a section. */
16410 mips_fix_adjustable (fixS
*fixp
)
16412 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16413 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16416 if (fixp
->fx_addsy
== NULL
)
16419 /* If symbol SYM is in a mergeable section, relocations of the form
16420 SYM + 0 can usually be made section-relative. The mergeable data
16421 is then identified by the section offset rather than by the symbol.
16423 However, if we're generating REL LO16 relocations, the offset is split
16424 between the LO16 and parterning high part relocation. The linker will
16425 need to recalculate the complete offset in order to correctly identify
16428 The linker has traditionally not looked for the parterning high part
16429 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16430 placed anywhere. Rather than break backwards compatibility by changing
16431 this, it seems better not to force the issue, and instead keep the
16432 original symbol. This will work with either linker behavior. */
16433 if ((lo16_reloc_p (fixp
->fx_r_type
)
16434 || reloc_needs_lo_p (fixp
->fx_r_type
))
16435 && HAVE_IN_PLACE_ADDENDS
16436 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16439 /* There is no place to store an in-place offset for JALR relocations.
16440 Likewise an in-range offset of limited PC-relative relocations may
16441 overflow the in-place relocatable field if recalculated against the
16442 start address of the symbol's containing section. */
16443 if (HAVE_IN_PLACE_ADDENDS
16444 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16445 || jalr_reloc_p (fixp
->fx_r_type
)))
16448 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16449 to a floating-point stub. The same is true for non-R_MIPS16_26
16450 relocations against MIPS16 functions; in this case, the stub becomes
16451 the function's canonical address.
16453 Floating-point stubs are stored in unique .mips16.call.* or
16454 .mips16.fn.* sections. If a stub T for function F is in section S,
16455 the first relocation in section S must be against F; this is how the
16456 linker determines the target function. All relocations that might
16457 resolve to T must also be against F. We therefore have the following
16458 restrictions, which are given in an intentionally-redundant way:
16460 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16463 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16464 if that stub might be used.
16466 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16469 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16470 that stub might be used.
16472 There is a further restriction:
16474 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16475 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16476 targets with in-place addends; the relocation field cannot
16477 encode the low bit.
16479 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16480 against a MIPS16 symbol. We deal with (5) by by not reducing any
16481 such relocations on REL targets.
16483 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16484 relocation against some symbol R, no relocation against R may be
16485 reduced. (Note that this deals with (2) as well as (1) because
16486 relocations against global symbols will never be reduced on ELF
16487 targets.) This approach is a little simpler than trying to detect
16488 stub sections, and gives the "all or nothing" per-symbol consistency
16489 that we have for MIPS16 symbols. */
16490 if (fixp
->fx_subsy
== NULL
16491 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16492 || *symbol_get_tc (fixp
->fx_addsy
)
16493 || (HAVE_IN_PLACE_ADDENDS
16494 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16495 && jmp_reloc_p (fixp
->fx_r_type
))))
16501 /* Translate internal representation of relocation info to BFD target
16505 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16507 static arelent
*retval
[4];
16509 bfd_reloc_code_real_type code
;
16511 memset (retval
, 0, sizeof(retval
));
16512 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16513 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16514 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16515 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16517 if (fixp
->fx_pcrel
)
16519 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16520 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16521 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16522 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16523 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16525 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16526 Relocations want only the symbol offset. */
16527 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16530 reloc
->addend
= fixp
->fx_addnumber
;
16532 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16533 entry to be used in the relocation's section offset. */
16534 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16536 reloc
->address
= reloc
->addend
;
16540 code
= fixp
->fx_r_type
;
16542 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16543 if (reloc
->howto
== NULL
)
16545 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16546 _("Can not represent %s relocation in this object file format"),
16547 bfd_get_reloc_code_name (code
));
16554 /* Relax a machine dependent frag. This returns the amount by which
16555 the current size of the frag should change. */
16558 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16560 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16562 offsetT old_var
= fragp
->fr_var
;
16564 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16566 return fragp
->fr_var
- old_var
;
16569 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16571 offsetT old_var
= fragp
->fr_var
;
16572 offsetT new_var
= 4;
16574 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16575 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16576 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16577 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16578 fragp
->fr_var
= new_var
;
16580 return new_var
- old_var
;
16583 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16586 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16588 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16590 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16595 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16597 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16604 /* Convert a machine dependent frag. */
16607 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16609 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16612 unsigned long insn
;
16616 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16617 insn
= read_insn (buf
);
16619 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16621 /* We generate a fixup instead of applying it right now
16622 because, if there are linker relaxations, we're going to
16623 need the relocations. */
16624 exp
.X_op
= O_symbol
;
16625 exp
.X_add_symbol
= fragp
->fr_symbol
;
16626 exp
.X_add_number
= fragp
->fr_offset
;
16628 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16629 BFD_RELOC_16_PCREL_S2
);
16630 fixp
->fx_file
= fragp
->fr_file
;
16631 fixp
->fx_line
= fragp
->fr_line
;
16633 buf
= write_insn (buf
, insn
);
16639 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16640 _("Relaxed out-of-range branch into a jump"));
16642 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16645 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16647 /* Reverse the branch. */
16648 switch ((insn
>> 28) & 0xf)
16651 /* bc[0-3][tf]l? instructions can have the condition
16652 reversed by tweaking a single TF bit, and their
16653 opcodes all have 0x4???????. */
16654 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16655 insn
^= 0x00010000;
16659 /* bltz 0x04000000 bgez 0x04010000
16660 bltzal 0x04100000 bgezal 0x04110000 */
16661 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16662 insn
^= 0x00010000;
16666 /* beq 0x10000000 bne 0x14000000
16667 blez 0x18000000 bgtz 0x1c000000 */
16668 insn
^= 0x04000000;
16676 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16678 /* Clear the and-link bit. */
16679 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16681 /* bltzal 0x04100000 bgezal 0x04110000
16682 bltzall 0x04120000 bgezall 0x04130000 */
16683 insn
&= ~0x00100000;
16686 /* Branch over the branch (if the branch was likely) or the
16687 full jump (not likely case). Compute the offset from the
16688 current instruction to branch to. */
16689 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16693 /* How many bytes in instructions we've already emitted? */
16694 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16695 /* How many bytes in instructions from here to the end? */
16696 i
= fragp
->fr_var
- i
;
16698 /* Convert to instruction count. */
16700 /* Branch counts from the next instruction. */
16703 /* Branch over the jump. */
16704 buf
= write_insn (buf
, insn
);
16707 buf
= write_insn (buf
, 0);
16709 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16711 /* beql $0, $0, 2f */
16713 /* Compute the PC offset from the current instruction to
16714 the end of the variable frag. */
16715 /* How many bytes in instructions we've already emitted? */
16716 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16717 /* How many bytes in instructions from here to the end? */
16718 i
= fragp
->fr_var
- i
;
16719 /* Convert to instruction count. */
16721 /* Don't decrement i, because we want to branch over the
16725 buf
= write_insn (buf
, insn
);
16726 buf
= write_insn (buf
, 0);
16730 if (mips_pic
== NO_PIC
)
16733 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16734 ? 0x0c000000 : 0x08000000);
16735 exp
.X_op
= O_symbol
;
16736 exp
.X_add_symbol
= fragp
->fr_symbol
;
16737 exp
.X_add_number
= fragp
->fr_offset
;
16739 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16740 FALSE
, BFD_RELOC_MIPS_JMP
);
16741 fixp
->fx_file
= fragp
->fr_file
;
16742 fixp
->fx_line
= fragp
->fr_line
;
16744 buf
= write_insn (buf
, insn
);
16748 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16750 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16751 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16752 insn
|= at
<< OP_SH_RT
;
16753 exp
.X_op
= O_symbol
;
16754 exp
.X_add_symbol
= fragp
->fr_symbol
;
16755 exp
.X_add_number
= fragp
->fr_offset
;
16757 if (fragp
->fr_offset
)
16759 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16760 exp
.X_add_number
= 0;
16763 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16764 FALSE
, BFD_RELOC_MIPS_GOT16
);
16765 fixp
->fx_file
= fragp
->fr_file
;
16766 fixp
->fx_line
= fragp
->fr_line
;
16768 buf
= write_insn (buf
, insn
);
16770 if (mips_opts
.isa
== ISA_MIPS1
)
16772 buf
= write_insn (buf
, 0);
16774 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16775 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16776 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16778 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16779 FALSE
, BFD_RELOC_LO16
);
16780 fixp
->fx_file
= fragp
->fr_file
;
16781 fixp
->fx_line
= fragp
->fr_line
;
16783 buf
= write_insn (buf
, insn
);
16786 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16790 insn
|= at
<< OP_SH_RS
;
16792 buf
= write_insn (buf
, insn
);
16796 fragp
->fr_fix
+= fragp
->fr_var
;
16797 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16801 /* Relax microMIPS branches. */
16802 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16804 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16805 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16806 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16807 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16808 bfd_boolean short_ds
;
16809 unsigned long insn
;
16813 exp
.X_op
= O_symbol
;
16814 exp
.X_add_symbol
= fragp
->fr_symbol
;
16815 exp
.X_add_number
= fragp
->fr_offset
;
16817 fragp
->fr_fix
+= fragp
->fr_var
;
16819 /* Handle 16-bit branches that fit or are forced to fit. */
16820 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16822 /* We generate a fixup instead of applying it right now,
16823 because if there is linker relaxation, we're going to
16824 need the relocations. */
16826 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16827 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16828 else if (type
== 'E')
16829 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16830 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16834 fixp
->fx_file
= fragp
->fr_file
;
16835 fixp
->fx_line
= fragp
->fr_line
;
16837 /* These relocations can have an addend that won't fit in
16839 fixp
->fx_no_overflow
= 1;
16844 /* Handle 32-bit branches that fit or are forced to fit. */
16845 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16846 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16848 /* We generate a fixup instead of applying it right now,
16849 because if there is linker relaxation, we're going to
16850 need the relocations. */
16851 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16852 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16853 fixp
->fx_file
= fragp
->fr_file
;
16854 fixp
->fx_line
= fragp
->fr_line
;
16860 /* Relax 16-bit branches to 32-bit branches. */
16863 insn
= read_compressed_insn (buf
, 2);
16865 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16866 insn
= 0x94000000; /* beq */
16867 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16869 unsigned long regno
;
16871 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16872 regno
= micromips_to_32_reg_d_map
[regno
];
16873 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16874 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16879 /* Nothing else to do, just write it out. */
16880 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16881 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16883 buf
= write_compressed_insn (buf
, insn
, 4);
16884 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16889 insn
= read_compressed_insn (buf
, 4);
16891 /* Relax 32-bit branches to a sequence of instructions. */
16892 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16893 _("Relaxed out-of-range branch into a jump"));
16895 /* Set the short-delay-slot bit. */
16896 short_ds
= al
&& (insn
& 0x02000000) != 0;
16898 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16902 /* Reverse the branch. */
16903 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16904 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16905 insn
^= 0x20000000;
16906 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16907 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16908 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16909 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16910 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16911 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16912 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16913 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16914 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16915 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16916 insn
^= 0x00400000;
16917 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16918 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16919 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16920 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16921 insn
^= 0x00200000;
16927 /* Clear the and-link and short-delay-slot bits. */
16928 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16930 /* bltzal 0x40200000 bgezal 0x40600000 */
16931 /* bltzals 0x42200000 bgezals 0x42600000 */
16932 insn
&= ~0x02200000;
16935 /* Make a label at the end for use with the branch. */
16936 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
16937 micromips_label_inc ();
16938 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
16941 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
16942 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16943 fixp
->fx_file
= fragp
->fr_file
;
16944 fixp
->fx_line
= fragp
->fr_line
;
16946 /* Branch over the jump. */
16947 buf
= write_compressed_insn (buf
, insn
, 4);
16950 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16953 if (mips_pic
== NO_PIC
)
16955 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
16957 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
16958 insn
= al
? jal
: 0xd4000000;
16960 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16961 BFD_RELOC_MICROMIPS_JMP
);
16962 fixp
->fx_file
= fragp
->fr_file
;
16963 fixp
->fx_line
= fragp
->fr_line
;
16965 buf
= write_compressed_insn (buf
, insn
, 4);
16968 buf
= write_compressed_insn (buf
, 0x0c00, 2);
16972 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
16973 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
16974 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
16976 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
16977 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
16978 insn
|= at
<< MICROMIPSOP_SH_RT
;
16980 if (exp
.X_add_number
)
16982 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16983 exp
.X_add_number
= 0;
16986 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16987 BFD_RELOC_MICROMIPS_GOT16
);
16988 fixp
->fx_file
= fragp
->fr_file
;
16989 fixp
->fx_line
= fragp
->fr_line
;
16991 buf
= write_compressed_insn (buf
, insn
, 4);
16993 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
16994 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
16995 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
16997 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
16998 BFD_RELOC_MICROMIPS_LO16
);
16999 fixp
->fx_file
= fragp
->fr_file
;
17000 fixp
->fx_line
= fragp
->fr_line
;
17002 buf
= write_compressed_insn (buf
, insn
, 4);
17004 /* jr/jrc/jalr/jalrs $at */
17005 insn
= al
? jalr
: jr
;
17006 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17008 buf
= write_compressed_insn (buf
, insn
, 2);
17011 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17015 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17018 const struct mips_int_operand
*operand
;
17021 unsigned int user_length
, length
;
17022 unsigned long insn
;
17025 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17026 operand
= mips16_immed_operand (type
, FALSE
);
17028 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17029 val
= resolve_symbol_value (fragp
->fr_symbol
);
17030 if (operand
->root
.type
== OP_PCREL
)
17032 const struct mips_pcrel_operand
*pcrel_op
;
17035 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17036 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17038 /* The rules for the base address of a PC relative reloc are
17039 complicated; see mips16_extended_frag. */
17040 if (pcrel_op
->include_isa_bit
)
17045 /* Ignore the low bit in the target, since it will be
17046 set for a text label. */
17049 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17051 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17054 addr
&= -(1 << pcrel_op
->align_log2
);
17057 /* Make sure the section winds up with the alignment we have
17059 if (operand
->shift
> 0)
17060 record_alignment (asec
, operand
->shift
);
17064 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17065 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17066 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17067 _("extended instruction in delay slot"));
17069 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17071 insn
= read_compressed_insn (buf
, 2);
17073 insn
|= MIPS16_EXTEND
;
17075 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17077 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17082 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17083 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17085 length
= (ext
? 4 : 2);
17086 gas_assert (mips16_opcode_length (insn
) == length
);
17087 write_compressed_insn (buf
, insn
, length
);
17088 fragp
->fr_fix
+= length
;
17092 relax_substateT subtype
= fragp
->fr_subtype
;
17093 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17094 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17098 first
= RELAX_FIRST (subtype
);
17099 second
= RELAX_SECOND (subtype
);
17100 fixp
= (fixS
*) fragp
->fr_opcode
;
17102 /* If the delay slot chosen does not match the size of the instruction,
17103 then emit a warning. */
17104 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17105 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17110 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17111 | RELAX_DELAY_SLOT_SIZE_FIRST
17112 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17113 msg
= macro_warning (s
);
17115 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17119 /* Possibly emit a warning if we've chosen the longer option. */
17120 if (use_second
== second_longer
)
17126 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17127 msg
= macro_warning (s
);
17129 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17133 /* Go through all the fixups for the first sequence. Disable them
17134 (by marking them as done) if we're going to use the second
17135 sequence instead. */
17137 && fixp
->fx_frag
== fragp
17138 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17140 if (subtype
& RELAX_USE_SECOND
)
17142 fixp
= fixp
->fx_next
;
17145 /* Go through the fixups for the second sequence. Disable them if
17146 we're going to use the first sequence, otherwise adjust their
17147 addresses to account for the relaxation. */
17148 while (fixp
&& fixp
->fx_frag
== fragp
)
17150 if (subtype
& RELAX_USE_SECOND
)
17151 fixp
->fx_where
-= first
;
17154 fixp
= fixp
->fx_next
;
17157 /* Now modify the frag contents. */
17158 if (subtype
& RELAX_USE_SECOND
)
17162 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17163 memmove (start
, start
+ first
, second
);
17164 fragp
->fr_fix
-= first
;
17167 fragp
->fr_fix
-= second
;
17171 /* This function is called after the relocs have been generated.
17172 We've been storing mips16 text labels as odd. Here we convert them
17173 back to even for the convenience of the debugger. */
17176 mips_frob_file_after_relocs (void)
17179 unsigned int count
, i
;
17181 syms
= bfd_get_outsymbols (stdoutput
);
17182 count
= bfd_get_symcount (stdoutput
);
17183 for (i
= 0; i
< count
; i
++, syms
++)
17184 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17185 && ((*syms
)->value
& 1) != 0)
17187 (*syms
)->value
&= ~1;
17188 /* If the symbol has an odd size, it was probably computed
17189 incorrectly, so adjust that as well. */
17190 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17191 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17195 /* This function is called whenever a label is defined, including fake
17196 labels instantiated off the dot special symbol. It is used when
17197 handling branch delays; if a branch has a label, we assume we cannot
17198 move it. This also bumps the value of the symbol by 1 in compressed
17202 mips_record_label (symbolS
*sym
)
17204 segment_info_type
*si
= seg_info (now_seg
);
17205 struct insn_label_list
*l
;
17207 if (free_insn_labels
== NULL
)
17208 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17211 l
= free_insn_labels
;
17212 free_insn_labels
= l
->next
;
17216 l
->next
= si
->label_list
;
17217 si
->label_list
= l
;
17220 /* This function is called as tc_frob_label() whenever a label is defined
17221 and adds a DWARF-2 record we only want for true labels. */
17224 mips_define_label (symbolS
*sym
)
17226 mips_record_label (sym
);
17227 dwarf2_emit_label (sym
);
17230 /* This function is called by tc_new_dot_label whenever a new dot symbol
17234 mips_add_dot_label (symbolS
*sym
)
17236 mips_record_label (sym
);
17237 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17238 mips_compressed_mark_label (sym
);
17241 /* Some special processing for a MIPS ELF file. */
17244 mips_elf_final_processing (void)
17246 /* Write out the register information. */
17247 if (mips_abi
!= N64_ABI
)
17251 s
.ri_gprmask
= mips_gprmask
;
17252 s
.ri_cprmask
[0] = mips_cprmask
[0];
17253 s
.ri_cprmask
[1] = mips_cprmask
[1];
17254 s
.ri_cprmask
[2] = mips_cprmask
[2];
17255 s
.ri_cprmask
[3] = mips_cprmask
[3];
17256 /* The gp_value field is set by the MIPS ELF backend. */
17258 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17259 ((Elf32_External_RegInfo
*)
17260 mips_regmask_frag
));
17264 Elf64_Internal_RegInfo s
;
17266 s
.ri_gprmask
= mips_gprmask
;
17268 s
.ri_cprmask
[0] = mips_cprmask
[0];
17269 s
.ri_cprmask
[1] = mips_cprmask
[1];
17270 s
.ri_cprmask
[2] = mips_cprmask
[2];
17271 s
.ri_cprmask
[3] = mips_cprmask
[3];
17272 /* The gp_value field is set by the MIPS ELF backend. */
17274 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17275 ((Elf64_External_RegInfo
*)
17276 mips_regmask_frag
));
17279 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17280 sort of BFD interface for this. */
17281 if (mips_any_noreorder
)
17282 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17283 if (mips_pic
!= NO_PIC
)
17285 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17286 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17289 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17291 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17292 defined at present; this might need to change in future. */
17293 if (file_ase_mips16
)
17294 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17295 if (file_ase_micromips
)
17296 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17297 if (file_ase
& ASE_MDMX
)
17298 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17300 /* Set the MIPS ELF ABI flags. */
17301 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17302 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17303 else if (mips_abi
== O64_ABI
)
17304 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17305 else if (mips_abi
== EABI_ABI
)
17307 if (!file_mips_gp32
)
17308 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17310 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17312 else if (mips_abi
== N32_ABI
)
17313 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17315 /* Nothing to do for N64_ABI. */
17317 if (mips_32bitmode
)
17318 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17320 if (mips_flag_nan2008
)
17321 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17323 #if 0 /* XXX FIXME */
17324 /* 32 bit code with 64 bit FP registers. */
17325 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17326 elf_elfheader (stdoutput
)->e_flags
|= ???;
17330 typedef struct proc
{
17332 symbolS
*func_end_sym
;
17333 unsigned long reg_mask
;
17334 unsigned long reg_offset
;
17335 unsigned long fpreg_mask
;
17336 unsigned long fpreg_offset
;
17337 unsigned long frame_offset
;
17338 unsigned long frame_reg
;
17339 unsigned long pc_reg
;
17342 static procS cur_proc
;
17343 static procS
*cur_proc_ptr
;
17344 static int numprocs
;
17346 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17347 as "2", and a normal nop as "0". */
17349 #define NOP_OPCODE_MIPS 0
17350 #define NOP_OPCODE_MIPS16 1
17351 #define NOP_OPCODE_MICROMIPS 2
17354 mips_nop_opcode (void)
17356 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17357 return NOP_OPCODE_MICROMIPS
;
17358 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17359 return NOP_OPCODE_MIPS16
;
17361 return NOP_OPCODE_MIPS
;
17364 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17365 32-bit microMIPS NOPs here (if applicable). */
17368 mips_handle_align (fragS
*fragp
)
17372 int bytes
, size
, excess
;
17375 if (fragp
->fr_type
!= rs_align_code
)
17378 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17380 switch (nop_opcode
)
17382 case NOP_OPCODE_MICROMIPS
:
17383 opcode
= micromips_nop32_insn
.insn_opcode
;
17386 case NOP_OPCODE_MIPS16
:
17387 opcode
= mips16_nop_insn
.insn_opcode
;
17390 case NOP_OPCODE_MIPS
:
17392 opcode
= nop_insn
.insn_opcode
;
17397 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17398 excess
= bytes
% size
;
17400 /* Handle the leading part if we're not inserting a whole number of
17401 instructions, and make it the end of the fixed part of the frag.
17402 Try to fit in a short microMIPS NOP if applicable and possible,
17403 and use zeroes otherwise. */
17404 gas_assert (excess
< 4);
17405 fragp
->fr_fix
+= excess
;
17410 /* Fall through. */
17412 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17414 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17418 /* Fall through. */
17421 /* Fall through. */
17426 md_number_to_chars (p
, opcode
, size
);
17427 fragp
->fr_var
= size
;
17431 md_obj_begin (void)
17438 /* Check for premature end, nesting errors, etc. */
17440 as_warn (_("missing .end at end of assembly"));
17449 if (*input_line_pointer
== '-')
17451 ++input_line_pointer
;
17454 if (!ISDIGIT (*input_line_pointer
))
17455 as_bad (_("expected simple number"));
17456 if (input_line_pointer
[0] == '0')
17458 if (input_line_pointer
[1] == 'x')
17460 input_line_pointer
+= 2;
17461 while (ISXDIGIT (*input_line_pointer
))
17464 val
|= hex_value (*input_line_pointer
++);
17466 return negative
? -val
: val
;
17470 ++input_line_pointer
;
17471 while (ISDIGIT (*input_line_pointer
))
17474 val
|= *input_line_pointer
++ - '0';
17476 return negative
? -val
: val
;
17479 if (!ISDIGIT (*input_line_pointer
))
17481 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17482 *input_line_pointer
, *input_line_pointer
);
17483 as_warn (_("invalid number"));
17486 while (ISDIGIT (*input_line_pointer
))
17489 val
+= *input_line_pointer
++ - '0';
17491 return negative
? -val
: val
;
17494 /* The .file directive; just like the usual .file directive, but there
17495 is an initial number which is the ECOFF file index. In the non-ECOFF
17496 case .file implies DWARF-2. */
17499 s_mips_file (int x ATTRIBUTE_UNUSED
)
17501 static int first_file_directive
= 0;
17503 if (ECOFF_DEBUGGING
)
17512 filename
= dwarf2_directive_file (0);
17514 /* Versions of GCC up to 3.1 start files with a ".file"
17515 directive even for stabs output. Make sure that this
17516 ".file" is handled. Note that you need a version of GCC
17517 after 3.1 in order to support DWARF-2 on MIPS. */
17518 if (filename
!= NULL
&& ! first_file_directive
)
17520 (void) new_logical_line (filename
, -1);
17521 s_app_file_string (filename
, 0);
17523 first_file_directive
= 1;
17527 /* The .loc directive, implying DWARF-2. */
17530 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17532 if (!ECOFF_DEBUGGING
)
17533 dwarf2_directive_loc (0);
17536 /* The .end directive. */
17539 s_mips_end (int x ATTRIBUTE_UNUSED
)
17543 /* Following functions need their own .frame and .cprestore directives. */
17544 mips_frame_reg_valid
= 0;
17545 mips_cprestore_valid
= 0;
17547 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17550 demand_empty_rest_of_line ();
17555 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17556 as_warn (_(".end not in text section"));
17560 as_warn (_(".end directive without a preceding .ent directive."));
17561 demand_empty_rest_of_line ();
17567 gas_assert (S_GET_NAME (p
));
17568 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17569 as_warn (_(".end symbol does not match .ent symbol."));
17571 if (debug_type
== DEBUG_STABS
)
17572 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17576 as_warn (_(".end directive missing or unknown symbol"));
17578 /* Create an expression to calculate the size of the function. */
17579 if (p
&& cur_proc_ptr
)
17581 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17582 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17585 exp
->X_op
= O_subtract
;
17586 exp
->X_add_symbol
= symbol_temp_new_now ();
17587 exp
->X_op_symbol
= p
;
17588 exp
->X_add_number
= 0;
17590 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17593 /* Generate a .pdr section. */
17594 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17596 segT saved_seg
= now_seg
;
17597 subsegT saved_subseg
= now_subseg
;
17601 #ifdef md_flush_pending_output
17602 md_flush_pending_output ();
17605 gas_assert (pdr_seg
);
17606 subseg_set (pdr_seg
, 0);
17608 /* Write the symbol. */
17609 exp
.X_op
= O_symbol
;
17610 exp
.X_add_symbol
= p
;
17611 exp
.X_add_number
= 0;
17612 emit_expr (&exp
, 4);
17614 fragp
= frag_more (7 * 4);
17616 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17617 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17618 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17619 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17620 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17621 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17622 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17624 subseg_set (saved_seg
, saved_subseg
);
17627 cur_proc_ptr
= NULL
;
17630 /* The .aent and .ent directives. */
17633 s_mips_ent (int aent
)
17637 symbolP
= get_symbol ();
17638 if (*input_line_pointer
== ',')
17639 ++input_line_pointer
;
17640 SKIP_WHITESPACE ();
17641 if (ISDIGIT (*input_line_pointer
)
17642 || *input_line_pointer
== '-')
17645 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17646 as_warn (_(".ent or .aent not in text section."));
17648 if (!aent
&& cur_proc_ptr
)
17649 as_warn (_("missing .end"));
17653 /* This function needs its own .frame and .cprestore directives. */
17654 mips_frame_reg_valid
= 0;
17655 mips_cprestore_valid
= 0;
17657 cur_proc_ptr
= &cur_proc
;
17658 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17660 cur_proc_ptr
->func_sym
= symbolP
;
17664 if (debug_type
== DEBUG_STABS
)
17665 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17666 S_GET_NAME (symbolP
));
17669 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17671 demand_empty_rest_of_line ();
17674 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17675 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17676 s_mips_frame is used so that we can set the PDR information correctly.
17677 We can't use the ecoff routines because they make reference to the ecoff
17678 symbol table (in the mdebug section). */
17681 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17683 if (ECOFF_DEBUGGING
)
17689 if (cur_proc_ptr
== (procS
*) NULL
)
17691 as_warn (_(".frame outside of .ent"));
17692 demand_empty_rest_of_line ();
17696 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17698 SKIP_WHITESPACE ();
17699 if (*input_line_pointer
++ != ','
17700 || get_absolute_expression_and_terminator (&val
) != ',')
17702 as_warn (_("Bad .frame directive"));
17703 --input_line_pointer
;
17704 demand_empty_rest_of_line ();
17708 cur_proc_ptr
->frame_offset
= val
;
17709 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17711 demand_empty_rest_of_line ();
17715 /* The .fmask and .mask directives. If the mdebug section is present
17716 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17717 embedded targets, s_mips_mask is used so that we can set the PDR
17718 information correctly. We can't use the ecoff routines because they
17719 make reference to the ecoff symbol table (in the mdebug section). */
17722 s_mips_mask (int reg_type
)
17724 if (ECOFF_DEBUGGING
)
17725 s_ignore (reg_type
);
17730 if (cur_proc_ptr
== (procS
*) NULL
)
17732 as_warn (_(".mask/.fmask outside of .ent"));
17733 demand_empty_rest_of_line ();
17737 if (get_absolute_expression_and_terminator (&mask
) != ',')
17739 as_warn (_("Bad .mask/.fmask directive"));
17740 --input_line_pointer
;
17741 demand_empty_rest_of_line ();
17745 off
= get_absolute_expression ();
17747 if (reg_type
== 'F')
17749 cur_proc_ptr
->fpreg_mask
= mask
;
17750 cur_proc_ptr
->fpreg_offset
= off
;
17754 cur_proc_ptr
->reg_mask
= mask
;
17755 cur_proc_ptr
->reg_offset
= off
;
17758 demand_empty_rest_of_line ();
17762 /* A table describing all the processors gas knows about. Names are
17763 matched in the order listed.
17765 To ease comparison, please keep this table in the same order as
17766 gcc's mips_cpu_info_table[]. */
17767 static const struct mips_cpu_info mips_cpu_info_table
[] =
17769 /* Entries for generic ISAs */
17770 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17771 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17772 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17773 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17774 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17775 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17776 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17777 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17778 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17781 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17782 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17783 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17786 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17789 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17790 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17791 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17792 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17793 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17794 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17795 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17796 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17797 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17798 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17799 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17800 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17801 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17802 /* ST Microelectronics Loongson 2E and 2F cores */
17803 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17804 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17807 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17808 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17809 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17810 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17811 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17812 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17813 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17814 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17815 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17816 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17817 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17818 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17819 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17820 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17821 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17824 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17825 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17826 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17827 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17829 /* MIPS 32 Release 2 */
17830 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17831 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17832 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17833 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17834 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17835 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17836 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17837 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17838 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17839 ISA_MIPS32R2
, CPU_MIPS32R2
},
17840 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17841 ISA_MIPS32R2
, CPU_MIPS32R2
},
17842 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17843 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17844 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17845 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17846 /* Deprecated forms of the above. */
17847 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17848 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17849 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17850 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17851 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17852 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17853 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17854 /* Deprecated forms of the above. */
17855 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17856 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17857 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17858 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17859 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17860 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17861 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17862 /* Deprecated forms of the above. */
17863 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17864 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17865 /* 34Kn is a 34kc without DSP. */
17866 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17867 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17868 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17869 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17870 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17871 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17872 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17873 /* Deprecated forms of the above. */
17874 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17875 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17876 /* 1004K cores are multiprocessor versions of the 34K. */
17877 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17878 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17879 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17880 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17883 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17884 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17885 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17886 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17888 /* Broadcom SB-1 CPU core */
17889 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17890 /* Broadcom SB-1A CPU core */
17891 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17893 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17895 /* MIPS 64 Release 2 */
17897 /* Cavium Networks Octeon CPU core */
17898 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17899 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17900 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17903 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17906 XLP is mostly like XLR, with the prominent exception that it is
17907 MIPS64R2 rather than MIPS64. */
17908 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17911 { NULL
, 0, 0, 0, 0 }
17915 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17916 with a final "000" replaced by "k". Ignore case.
17918 Note: this function is shared between GCC and GAS. */
17921 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17923 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17924 given
++, canonical
++;
17926 return ((*given
== 0 && *canonical
== 0)
17927 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17931 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17932 CPU name. We've traditionally allowed a lot of variation here.
17934 Note: this function is shared between GCC and GAS. */
17937 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
17939 /* First see if the name matches exactly, or with a final "000"
17940 turned into "k". */
17941 if (mips_strict_matching_cpu_name_p (canonical
, given
))
17944 /* If not, try comparing based on numerical designation alone.
17945 See if GIVEN is an unadorned number, or 'r' followed by a number. */
17946 if (TOLOWER (*given
) == 'r')
17948 if (!ISDIGIT (*given
))
17951 /* Skip over some well-known prefixes in the canonical name,
17952 hoping to find a number there too. */
17953 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
17955 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
17957 else if (TOLOWER (canonical
[0]) == 'r')
17960 return mips_strict_matching_cpu_name_p (canonical
, given
);
17964 /* Parse an option that takes the name of a processor as its argument.
17965 OPTION is the name of the option and CPU_STRING is the argument.
17966 Return the corresponding processor enumeration if the CPU_STRING is
17967 recognized, otherwise report an error and return null.
17969 A similar function exists in GCC. */
17971 static const struct mips_cpu_info
*
17972 mips_parse_cpu (const char *option
, const char *cpu_string
)
17974 const struct mips_cpu_info
*p
;
17976 /* 'from-abi' selects the most compatible architecture for the given
17977 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
17978 EABIs, we have to decide whether we're using the 32-bit or 64-bit
17979 version. Look first at the -mgp options, if given, otherwise base
17980 the choice on MIPS_DEFAULT_64BIT.
17982 Treat NO_ABI like the EABIs. One reason to do this is that the
17983 plain 'mips' and 'mips64' configs have 'from-abi' as their default
17984 architecture. This code picks MIPS I for 'mips' and MIPS III for
17985 'mips64', just as we did in the days before 'from-abi'. */
17986 if (strcasecmp (cpu_string
, "from-abi") == 0)
17988 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
17989 return mips_cpu_info_from_isa (ISA_MIPS1
);
17991 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
17992 return mips_cpu_info_from_isa (ISA_MIPS3
);
17994 if (file_mips_gp32
>= 0)
17995 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
17997 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18002 /* 'default' has traditionally been a no-op. Probably not very useful. */
18003 if (strcasecmp (cpu_string
, "default") == 0)
18006 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18007 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18010 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
18014 /* Return the canonical processor information for ISA (a member of the
18015 ISA_MIPS* enumeration). */
18017 static const struct mips_cpu_info
*
18018 mips_cpu_info_from_isa (int isa
)
18022 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18023 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18024 && isa
== mips_cpu_info_table
[i
].isa
)
18025 return (&mips_cpu_info_table
[i
]);
18030 static const struct mips_cpu_info
*
18031 mips_cpu_info_from_arch (int arch
)
18035 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18036 if (arch
== mips_cpu_info_table
[i
].cpu
)
18037 return (&mips_cpu_info_table
[i
]);
18043 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18047 fprintf (stream
, "%24s", "");
18052 fprintf (stream
, ", ");
18056 if (*col_p
+ strlen (string
) > 72)
18058 fprintf (stream
, "\n%24s", "");
18062 fprintf (stream
, "%s", string
);
18063 *col_p
+= strlen (string
);
18069 md_show_usage (FILE *stream
)
18074 fprintf (stream
, _("\
18076 -EB generate big endian output\n\
18077 -EL generate little endian output\n\
18078 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18079 -G NUM allow referencing objects up to NUM bytes\n\
18080 implicitly with the gp register [default 8]\n"));
18081 fprintf (stream
, _("\
18082 -mips1 generate MIPS ISA I instructions\n\
18083 -mips2 generate MIPS ISA II instructions\n\
18084 -mips3 generate MIPS ISA III instructions\n\
18085 -mips4 generate MIPS ISA IV instructions\n\
18086 -mips5 generate MIPS ISA V instructions\n\
18087 -mips32 generate MIPS32 ISA instructions\n\
18088 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18089 -mips64 generate MIPS64 ISA instructions\n\
18090 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18091 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18095 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18096 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18097 show (stream
, "from-abi", &column
, &first
);
18098 fputc ('\n', stream
);
18100 fprintf (stream
, _("\
18101 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18102 -no-mCPU don't generate code specific to CPU.\n\
18103 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18107 show (stream
, "3900", &column
, &first
);
18108 show (stream
, "4010", &column
, &first
);
18109 show (stream
, "4100", &column
, &first
);
18110 show (stream
, "4650", &column
, &first
);
18111 fputc ('\n', stream
);
18113 fprintf (stream
, _("\
18114 -mips16 generate mips16 instructions\n\
18115 -no-mips16 do not generate mips16 instructions\n"));
18116 fprintf (stream
, _("\
18117 -mmicromips generate microMIPS instructions\n\
18118 -mno-micromips do not generate microMIPS instructions\n"));
18119 fprintf (stream
, _("\
18120 -msmartmips generate smartmips instructions\n\
18121 -mno-smartmips do not generate smartmips instructions\n"));
18122 fprintf (stream
, _("\
18123 -mdsp generate DSP instructions\n\
18124 -mno-dsp do not generate DSP instructions\n"));
18125 fprintf (stream
, _("\
18126 -mdspr2 generate DSP R2 instructions\n\
18127 -mno-dspr2 do not generate DSP R2 instructions\n"));
18128 fprintf (stream
, _("\
18129 -mmt generate MT instructions\n\
18130 -mno-mt do not generate MT instructions\n"));
18131 fprintf (stream
, _("\
18132 -mmcu generate MCU instructions\n\
18133 -mno-mcu do not generate MCU instructions\n"));
18134 fprintf (stream
, _("\
18135 -mvirt generate Virtualization instructions\n\
18136 -mno-virt do not generate Virtualization instructions\n"));
18137 fprintf (stream
, _("\
18138 -minsn32 only generate 32-bit microMIPS instructions\n\
18139 -mno-insn32 generate all microMIPS instructions\n"));
18140 fprintf (stream
, _("\
18141 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18142 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18143 -mfix-vr4120 work around certain VR4120 errata\n\
18144 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18145 -mfix-24k insert a nop after ERET and DERET instructions\n\
18146 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18147 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18148 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18149 -msym32 assume all symbols have 32-bit values\n\
18150 -O0 remove unneeded NOPs, do not swap branches\n\
18151 -O remove unneeded NOPs and swap branches\n\
18152 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18153 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18154 fprintf (stream
, _("\
18155 -mhard-float allow floating-point instructions\n\
18156 -msoft-float do not allow floating-point instructions\n\
18157 -msingle-float only allow 32-bit floating-point operations\n\
18158 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18159 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18160 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18161 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18165 show (stream
, "legacy", &column
, &first
);
18166 show (stream
, "2008", &column
, &first
);
18168 fputc ('\n', stream
);
18170 fprintf (stream
, _("\
18171 -KPIC, -call_shared generate SVR4 position independent code\n\
18172 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18173 -mvxworks-pic generate VxWorks position independent code\n\
18174 -non_shared do not generate code that can operate with DSOs\n\
18175 -xgot assume a 32 bit GOT\n\
18176 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18177 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18178 position dependent (non shared) code\n\
18179 -mabi=ABI create ABI conformant object file for:\n"));
18183 show (stream
, "32", &column
, &first
);
18184 show (stream
, "o64", &column
, &first
);
18185 show (stream
, "n32", &column
, &first
);
18186 show (stream
, "64", &column
, &first
);
18187 show (stream
, "eabi", &column
, &first
);
18189 fputc ('\n', stream
);
18191 fprintf (stream
, _("\
18192 -32 create o32 ABI object file (default)\n\
18193 -n32 create n32 ABI object file\n\
18194 -64 create 64 ABI object file\n"));
18199 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18201 if (HAVE_64BIT_SYMBOLS
)
18202 return dwarf2_format_64bit_irix
;
18204 return dwarf2_format_32bit
;
18209 mips_dwarf2_addr_size (void)
18211 if (HAVE_64BIT_OBJECTS
)
18217 /* Standard calling conventions leave the CFA at SP on entry. */
18219 mips_cfi_frame_initial_instructions (void)
18221 cfi_add_CFA_def_cfa_register (SP
);
18225 tc_mips_regname_to_dw2regnum (char *regname
)
18227 unsigned int regnum
= -1;
18230 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))