1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The frag that contains the instruction. */
147 /* The offset into FRAG of the first instruction byte. */
150 /* The relocs associated with the instruction, if any. */
153 /* True if this entry cannot be moved from its current position. */
154 unsigned int fixed_p
: 1;
156 /* True if this instruction occurred in a .set noreorder block. */
157 unsigned int noreorder_p
: 1;
159 /* True for mips16 instructions that jump to an absolute address. */
160 unsigned int mips16_absolute_jump_p
: 1;
162 /* True if this instruction is complete. */
163 unsigned int complete_p
: 1;
165 /* True if this instruction is cleared from history by unconditional
167 unsigned int cleared_p
: 1;
170 /* The ABI to use. */
181 /* MIPS ABI we are using for this output file. */
182 static enum mips_abi_level mips_abi
= NO_ABI
;
184 /* Whether or not we have code that can call pic code. */
185 int mips_abicalls
= FALSE
;
187 /* Whether or not we have code which can be put into a shared
189 static bfd_boolean mips_in_shared
= TRUE
;
191 /* This is the set of options which may be modified by the .set
192 pseudo-op. We use a struct so that .set push and .set pop are more
195 struct mips_set_options
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
198 if it has not been initialized. Changed by `.set mipsN', and the
199 -mipsN command line option, and the default CPU. */
201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
202 <asename>', by command line options, and based on the default
205 /* Whether we are assembling for the mips16 processor. 0 if we are
206 not, 1 if we are, and -1 if the value has not been initialized.
207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
208 -nomips16 command line options, and the default CPU. */
210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
211 1 if we are, and -1 if the value has not been initialized. Changed
212 by `.set micromips' and `.set nomicromips', and the -mmicromips
213 and -mno-micromips command line options, and the default CPU. */
215 /* Non-zero if we should not reorder instructions. Changed by `.set
216 reorder' and `.set noreorder'. */
218 /* Non-zero if we should not permit the register designated "assembler
219 temporary" to be used in instructions. The value is the register
220 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
223 /* Non-zero if we should warn when a macro instruction expands into
224 more than one machine instruction. Changed by `.set nomacro' and
226 int warn_about_macros
;
227 /* Non-zero if we should not move instructions. Changed by `.set
228 move', `.set volatile', `.set nomove', and `.set novolatile'. */
230 /* Non-zero if we should not optimize branches by moving the target
231 of the branch into the delay slot. Actually, we don't perform
232 this optimization anyhow. Changed by `.set bopt' and `.set
235 /* Non-zero if we should not autoextend mips16 instructions.
236 Changed by `.set autoextend' and `.set noautoextend'. */
238 /* True if we should only emit 32-bit microMIPS instructions.
239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
240 and -mno-insn32 command line options. */
242 /* Restrict general purpose registers and floating point registers
243 to 32 bit. This is initially determined when -mgp32 or -mfp32
244 is passed but can changed if the assembler code uses .set mipsN. */
247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
248 command line option, and the default CPU. */
250 /* True if ".set sym32" is in effect. */
252 /* True if floating-point operations are not allowed. Changed by .set
253 softfloat or .set hardfloat, by command line options -msoft-float or
254 -mhard-float. The default is false. */
255 bfd_boolean soft_float
;
257 /* True if only single-precision floating-point operations are allowed.
258 Changed by .set singlefloat or .set doublefloat, command-line options
259 -msingle-float or -mdouble-float. The default is false. */
260 bfd_boolean single_float
;
262 /* 1 if single-precision operations on odd-numbered registers are
267 /* Specifies whether module level options have been checked yet. */
268 static bfd_boolean file_mips_opts_checked
= FALSE
;
270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
271 value has not been initialized. Changed by `.nan legacy' and
272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
273 options, and the default CPU. */
274 static int mips_nan2008
= -1;
276 /* This is the struct we use to hold the module level set of options.
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
278 fp fields to -1 to indicate that they have not been initialized. */
280 static struct mips_set_options file_mips_opts
=
282 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
283 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
286 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
289 /* This is similar to file_mips_opts, but for the current set of options. */
291 static struct mips_set_options mips_opts
=
293 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
294 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
297 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1
300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
301 static unsigned int file_ase_explicit
;
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask
;
307 unsigned long mips_cprmask
[4];
309 /* True if any MIPS16 code was produced. */
310 static int file_ase_mips16
;
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
321 /* True if any microMIPS code was produced. */
322 static int file_ase_micromips
;
324 /* True if we want to create R_MIPS_JALR for jalr $25. */
326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
329 because there's no place for any addend, the only acceptable
330 expression is a bare symbol. */
331 #define MIPS_JALR_HINT_P(EXPR) \
332 (!HAVE_IN_PLACE_ADDENDS \
333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
336 /* The argument of the -march= flag. The architecture we are assembling. */
337 static const char *mips_arch_string
;
339 /* The argument of the -mtune= flag. The architecture for which we
341 static int mips_tune
= CPU_UNKNOWN
;
342 static const char *mips_tune_string
;
344 /* True when generating 32-bit code for a 64-bit processor. */
345 static int mips_32bitmode
= 0;
347 /* True if the given ABI requires 32-bit registers. */
348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
350 /* Likewise 64-bit registers. */
351 #define ABI_NEEDS_64BIT_REGS(ABI) \
353 || (ABI) == N64_ABI \
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
393 || (mips_opts.micromips \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
408 || (mips_opts.ase & ASE_SMARTMIPS) \
409 || mips_opts.micromips \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (CPU) == CPU_R5900) \
425 && (CPU) != CPU_LOONGSON_3A)
427 /* Return true if ISA supports move to/from high part of a 64-bit
428 floating-point register. */
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
469 /* True if relocations are stored in-place. */
470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
472 /* The ABI-derived address size. */
473 #define HAVE_64BIT_ADDRESSES \
474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
477 /* The size of symbolic constants (i.e., expressions of the form
478 "SYMBOL" or "SYMBOL + OFFSET"). */
479 #define HAVE_32BIT_SYMBOLS \
480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
483 /* Addresses are loaded in different ways, depending on the address size
484 in use. The n32 ABI Documentation also mandates the use of additions
485 with overflow checking, but existing implementations don't follow it. */
486 #define ADDRESS_ADD_INSN \
487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
489 #define ADDRESS_ADDI_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
492 #define ADDRESS_LOAD_INSN \
493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
495 #define ADDRESS_STORE_INSN \
496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
498 /* Return true if the given CPU supports the MIPS16 ASE. */
499 #define CPU_HAS_MIPS16(cpu) \
500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
503 /* Return true if the given CPU supports the microMIPS ASE. */
504 #define CPU_HAS_MICROMIPS(cpu) 0
506 /* True if CPU has a dror instruction. */
507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
509 /* True if CPU has a ror instruction. */
510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
512 /* True if CPU is in the Octeon family */
513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
516 /* True if CPU has seq/sne and seqi/snei instructions. */
517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
519 /* True, if CPU has support for ldc1 and sdc1. */
520 #define CPU_HAS_LDC1_SDC1(CPU) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
523 /* True if mflo and mfhi can be immediately followed by instructions
524 which write to the HI and LO registers.
526 According to MIPS specifications, MIPS ISAs I, II, and III need
527 (at least) two instructions between the reads of HI/LO and
528 instructions which write them, and later ISAs do not. Contradicting
529 the MIPS specifications, some MIPS IV processor user manuals (e.g.
530 the UM for the NEC Vr5000) document needing the instructions between
531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
532 MIPS64 and later ISAs to have the interlocks, plus any specific
533 earlier-ISA CPUs for which CPU documentation declares that the
534 instructions are really interlocked. */
535 #define hilo_interlocks \
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
546 || mips_opts.arch == CPU_R4010 \
547 || mips_opts.arch == CPU_R5900 \
548 || mips_opts.arch == CPU_R10000 \
549 || mips_opts.arch == CPU_R12000 \
550 || mips_opts.arch == CPU_R14000 \
551 || mips_opts.arch == CPU_R16000 \
552 || mips_opts.arch == CPU_RM7000 \
553 || mips_opts.arch == CPU_VR5500 \
554 || mips_opts.micromips \
557 /* Whether the processor uses hardware interlocks to protect reads
558 from the GPRs after they are loaded from memory, and thus does not
559 require nops to be inserted. This applies to instructions marked
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
561 level I and microMIPS mode instructions are always interlocked. */
562 #define gpr_interlocks \
563 (mips_opts.isa != ISA_MIPS1 \
564 || mips_opts.arch == CPU_R3900 \
565 || mips_opts.arch == CPU_R5900 \
566 || mips_opts.micromips \
569 /* Whether the processor uses hardware interlocks to avoid delays
570 required by coprocessor instructions, and thus does not require
571 nops to be inserted. This applies to instructions marked
572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
573 instructions marked INSN_WRITE_COND_CODE and ones marked
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
575 levels I, II, and III and microMIPS mode instructions are always
577 /* Itbl support may require additional care here. */
578 #define cop_interlocks \
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
582 || mips_opts.arch == CPU_R4300 \
583 || mips_opts.micromips \
586 /* Whether the processor uses hardware interlocks to protect reads
587 from coprocessor registers after they are loaded from memory, and
588 thus does not require nops to be inserted. This applies to
589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
590 requires at MIPS ISA level I and microMIPS mode instructions are
591 always interlocked. */
592 #define cop_mem_interlocks \
593 (mips_opts.isa != ISA_MIPS1 \
594 || mips_opts.micromips \
597 /* Is this a mfhi or mflo instruction? */
598 #define MF_HILO_INSN(PINFO) \
599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
602 has been selected. This implies, in particular, that addresses of text
603 labels have their LSB set. */
604 #define HAVE_CODE_COMPRESSION \
605 ((mips_opts.mips16 | mips_opts.micromips) != 0)
607 /* The minimum and maximum signed values that can be stored in a GPR. */
608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
609 #define GPR_SMIN (-GPR_SMAX - 1)
611 /* MIPS PIC level. */
613 enum mips_pic_level mips_pic
;
615 /* 1 if we should generate 32 bit offsets from the $gp register in
616 SVR4_PIC mode. Currently has no meaning in other modes. */
617 static int mips_big_got
= 0;
619 /* 1 if trap instructions should used for overflow rather than break
621 static int mips_trap
= 0;
623 /* 1 if double width floating point constants should not be constructed
624 by assembling two single width halves into two single width floating
625 point registers which just happen to alias the double width destination
626 register. On some architectures this aliasing can be disabled by a bit
627 in the status register, and the setting of this bit cannot be determined
628 automatically at assemble time. */
629 static int mips_disable_float_construction
;
631 /* Non-zero if any .set noreorder directives were used. */
633 static int mips_any_noreorder
;
635 /* Non-zero if nops should be inserted when the register referenced in
636 an mfhi/mflo instruction is read in the next two instructions. */
637 static int mips_7000_hilo_fix
;
639 /* The size of objects in the small data section. */
640 static unsigned int g_switch_value
= 8;
641 /* Whether the -G option was used. */
642 static int g_switch_seen
= 0;
647 /* If we can determine in advance that GP optimization won't be
648 possible, we can skip the relaxation stuff that tries to produce
649 GP-relative references. This makes delay slot optimization work
652 This function can only provide a guess, but it seems to work for
653 gcc output. It needs to guess right for gcc, otherwise gcc
654 will put what it thinks is a GP-relative instruction in a branch
657 I don't know if a fix is needed for the SVR4_PIC mode. I've only
658 fixed it for the non-PIC mode. KR 95/04/07 */
659 static int nopic_need_relax (symbolS
*, int);
661 /* handle of the OPCODE hash table */
662 static struct hash_control
*op_hash
= NULL
;
664 /* The opcode hash table we use for the mips16. */
665 static struct hash_control
*mips16_op_hash
= NULL
;
667 /* The opcode hash table we use for the microMIPS ASE. */
668 static struct hash_control
*micromips_op_hash
= NULL
;
670 /* This array holds the chars that always start a comment. If the
671 pre-processor is disabled, these aren't very useful */
672 const char comment_chars
[] = "#";
674 /* This array holds the chars that only start a comment at the beginning of
675 a line. If the line seems to have the form '# 123 filename'
676 .line and .file directives will appear in the pre-processed output */
677 /* Note that input_file.c hand checks for '#' at the beginning of the
678 first line of the input file. This is because the compiler outputs
679 #NO_APP at the beginning of its output. */
680 /* Also note that C style comments are always supported. */
681 const char line_comment_chars
[] = "#";
683 /* This array holds machine specific line separator characters. */
684 const char line_separator_chars
[] = ";";
686 /* Chars that can be used to separate mant from exp in floating point nums */
687 const char EXP_CHARS
[] = "eE";
689 /* Chars that mean this number is a floating point constant */
692 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
695 changed in read.c . Ideally it shouldn't have to know about it at all,
696 but nothing is ideal around here.
699 /* Types of printf format used for instruction-related error messages.
700 "I" means int ("%d") and "S" means string ("%s"). */
701 enum mips_insn_error_format
{
707 /* Information about an error that was found while assembling the current
709 struct mips_insn_error
{
710 /* We sometimes need to match an instruction against more than one
711 opcode table entry. Errors found during this matching are reported
712 against a particular syntactic argument rather than against the
713 instruction as a whole. We grade these messages so that errors
714 against argument N have a greater priority than an error against
715 any argument < N, since the former implies that arguments up to N
716 were acceptable and that the opcode entry was therefore a closer match.
717 If several matches report an error against the same argument,
718 we only use that error if it is the same in all cases.
720 min_argnum is the minimum argument number for which an error message
721 should be accepted. It is 0 if MSG is against the instruction as
725 /* The printf()-style message, including its format and arguments. */
726 enum mips_insn_error_format format
;
734 /* The error that should be reported for the current instruction. */
735 static struct mips_insn_error insn_error
;
737 static int auto_align
= 1;
739 /* When outputting SVR4 PIC code, the assembler needs to know the
740 offset in the stack frame from which to restore the $gp register.
741 This is set by the .cprestore pseudo-op, and saved in this
743 static offsetT mips_cprestore_offset
= -1;
745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
746 more optimizations, it can use a register value instead of a memory-saved
747 offset and even an other register than $gp as global pointer. */
748 static offsetT mips_cpreturn_offset
= -1;
749 static int mips_cpreturn_register
= -1;
750 static int mips_gp_register
= GP
;
751 static int mips_gprel_offset
= 0;
753 /* Whether mips_cprestore_offset has been set in the current function
754 (or whether it has already been warned about, if not). */
755 static int mips_cprestore_valid
= 0;
757 /* This is the register which holds the stack frame, as set by the
758 .frame pseudo-op. This is needed to implement .cprestore. */
759 static int mips_frame_reg
= SP
;
761 /* Whether mips_frame_reg has been set in the current function
762 (or whether it has already been warned about, if not). */
763 static int mips_frame_reg_valid
= 0;
765 /* To output NOP instructions correctly, we need to keep information
766 about the previous two instructions. */
768 /* Whether we are optimizing. The default value of 2 means to remove
769 unneeded NOPs and swap branch instructions when possible. A value
770 of 1 means to not swap branches. A value of 0 means to always
772 static int mips_optimize
= 2;
774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
775 equivalent to seeing no -g option at all. */
776 static int mips_debug
= 0;
778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
779 #define MAX_VR4130_NOPS 4
781 /* The maximum number of NOPs needed to fill delay slots. */
782 #define MAX_DELAY_NOPS 2
784 /* The maximum number of NOPs needed for any purpose. */
787 /* A list of previous instructions, with index 0 being the most recent.
788 We need to look back MAX_NOPS instructions when filling delay slots
789 or working around processor errata. We need to look back one
790 instruction further if we're thinking about using history[0] to
791 fill a branch delay slot. */
792 static struct mips_cl_insn history
[1 + MAX_NOPS
];
794 /* Arrays of operands for each instruction. */
795 #define MAX_OPERANDS 6
796 struct mips_operand_array
{
797 const struct mips_operand
*operand
[MAX_OPERANDS
];
799 static struct mips_operand_array
*mips_operands
;
800 static struct mips_operand_array
*mips16_operands
;
801 static struct mips_operand_array
*micromips_operands
;
803 /* Nop instructions used by emit_nop. */
804 static struct mips_cl_insn nop_insn
;
805 static struct mips_cl_insn mips16_nop_insn
;
806 static struct mips_cl_insn micromips_nop16_insn
;
807 static struct mips_cl_insn micromips_nop32_insn
;
809 /* The appropriate nop for the current mode. */
810 #define NOP_INSN (mips_opts.mips16 \
812 : (mips_opts.micromips \
813 ? (mips_opts.insn32 \
814 ? µmips_nop32_insn \
815 : µmips_nop16_insn) \
818 /* The size of NOP_INSN in bytes. */
819 #define NOP_INSN_SIZE ((mips_opts.mips16 \
820 || (mips_opts.micromips && !mips_opts.insn32)) \
823 /* If this is set, it points to a frag holding nop instructions which
824 were inserted before the start of a noreorder section. If those
825 nops turn out to be unnecessary, the size of the frag can be
827 static fragS
*prev_nop_frag
;
829 /* The number of nop instructions we created in prev_nop_frag. */
830 static int prev_nop_frag_holds
;
832 /* The number of nop instructions that we know we need in
834 static int prev_nop_frag_required
;
836 /* The number of instructions we've seen since prev_nop_frag. */
837 static int prev_nop_frag_since
;
839 /* Relocations against symbols are sometimes done in two parts, with a HI
840 relocation and a LO relocation. Each relocation has only 16 bits of
841 space to store an addend. This means that in order for the linker to
842 handle carries correctly, it must be able to locate both the HI and
843 the LO relocation. This means that the relocations must appear in
844 order in the relocation table.
846 In order to implement this, we keep track of each unmatched HI
847 relocation. We then sort them so that they immediately precede the
848 corresponding LO relocation. */
853 struct mips_hi_fixup
*next
;
856 /* The section this fixup is in. */
860 /* The list of unmatched HI relocs. */
862 static struct mips_hi_fixup
*mips_hi_fixup_list
;
864 /* The frag containing the last explicit relocation operator.
865 Null if explicit relocations have not been used. */
867 static fragS
*prev_reloc_op_frag
;
869 /* Map mips16 register numbers to normal MIPS register numbers. */
871 static const unsigned int mips16_to_32_reg_map
[] =
873 16, 17, 2, 3, 4, 5, 6, 7
876 /* Map microMIPS register numbers to normal MIPS register numbers. */
878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
880 /* The microMIPS registers with type h. */
881 static const unsigned int micromips_to_32_reg_h_map1
[] =
883 5, 5, 6, 4, 4, 4, 4, 4
885 static const unsigned int micromips_to_32_reg_h_map2
[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 /* The microMIPS registers with type m. */
891 static const unsigned int micromips_to_32_reg_m_map
[] =
893 0, 17, 2, 3, 16, 18, 19, 20
896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
898 /* Classifies the kind of instructions we're interested in when
899 implementing -mfix-vr4120. */
900 enum fix_vr4120_class
908 NUM_FIX_VR4120_CLASSES
911 /* ...likewise -mfix-loongson2f-jump. */
912 static bfd_boolean mips_fix_loongson2f_jump
;
914 /* ...likewise -mfix-loongson2f-nop. */
915 static bfd_boolean mips_fix_loongson2f_nop
;
917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
918 static bfd_boolean mips_fix_loongson2f
;
920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
921 there must be at least one other instruction between an instruction
922 of type X and an instruction of type Y. */
923 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
925 /* True if -mfix-vr4120 is in force. */
926 static int mips_fix_vr4120
;
928 /* ...likewise -mfix-vr4130. */
929 static int mips_fix_vr4130
;
931 /* ...likewise -mfix-24k. */
932 static int mips_fix_24k
;
934 /* ...likewise -mfix-rm7000 */
935 static int mips_fix_rm7000
;
937 /* ...likewise -mfix-cn63xxp1 */
938 static bfd_boolean mips_fix_cn63xxp1
;
940 /* We don't relax branches by default, since this causes us to expand
941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
942 fail to compute the offset before expanding the macro to the most
943 efficient expansion. */
945 static int mips_relax_branch
;
947 /* TRUE if checks are suppressed for invalid branches between ISA modes.
948 Needed for broken assembly produced by some GCC versions and some
949 sloppy code out there, where branches to data labels are present. */
950 static bfd_boolean mips_ignore_branch_isa
;
952 /* The expansion of many macros depends on the type of symbol that
953 they refer to. For example, when generating position-dependent code,
954 a macro that refers to a symbol may have two different expansions,
955 one which uses GP-relative addresses and one which uses absolute
956 addresses. When generating SVR4-style PIC, a macro may have
957 different expansions for local and global symbols.
959 We handle these situations by generating both sequences and putting
960 them in variant frags. In position-dependent code, the first sequence
961 will be the GP-relative one and the second sequence will be the
962 absolute one. In SVR4 PIC, the first sequence will be for global
963 symbols and the second will be for local symbols.
965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
966 SECOND are the lengths of the two sequences in bytes. These fields
967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
968 the subtype has the following flags:
971 Set if generating PIC code.
974 Set if it has been decided that we should use the second
975 sequence instead of the first.
978 Set in the first variant frag if the macro's second implementation
979 is longer than its first. This refers to the macro as a whole,
980 not an individual relaxation.
983 Set in the first variant frag if the macro appeared in a .set nomacro
984 block and if one alternative requires a warning but the other does not.
987 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
990 RELAX_DELAY_SLOT_16BIT
991 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
994 RELAX_DELAY_SLOT_SIZE_FIRST
995 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
996 the macro is of the wrong size for the branch delay slot.
998 RELAX_DELAY_SLOT_SIZE_SECOND
999 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1000 the macro is of the wrong size for the branch delay slot.
1002 The frag's "opcode" points to the first fixup for relaxable code.
1004 Relaxable macros are generated using a sequence such as:
1006 relax_start (SYMBOL);
1007 ... generate first expansion ...
1009 ... generate second expansion ...
1012 The code and fixups for the unwanted alternative are discarded
1013 by md_convert_frag. */
1014 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1015 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1017 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1018 #define RELAX_SECOND(X) ((X) & 0xff)
1019 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1020 #define RELAX_USE_SECOND 0x20000
1021 #define RELAX_SECOND_LONGER 0x40000
1022 #define RELAX_NOMACRO 0x80000
1023 #define RELAX_DELAY_SLOT 0x100000
1024 #define RELAX_DELAY_SLOT_16BIT 0x200000
1025 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1026 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1028 /* Branch without likely bit. If label is out of range, we turn:
1030 beq reg1, reg2, label
1040 with the following opcode replacements:
1047 bltzal <-> bgezal (with jal label instead of j label)
1049 Even though keeping the delay slot instruction in the delay slot of
1050 the branch would be more efficient, it would be very tricky to do
1051 correctly, because we'd have to introduce a variable frag *after*
1052 the delay slot instruction, and expand that instead. Let's do it
1053 the easy way for now, even if the branch-not-taken case now costs
1054 one additional instruction. Out-of-range branches are not supposed
1055 to be common, anyway.
1057 Branch likely. If label is out of range, we turn:
1059 beql reg1, reg2, label
1060 delay slot (annulled if branch not taken)
1069 delay slot (executed only if branch taken)
1072 It would be possible to generate a shorter sequence by losing the
1073 likely bit, generating something like:
1078 delay slot (executed only if branch taken)
1090 bltzall -> bgezal (with jal label instead of j label)
1091 bgezall -> bltzal (ditto)
1094 but it's not clear that it would actually improve performance. */
1095 #define RELAX_BRANCH_ENCODE(at, pic, \
1096 uncond, likely, link, toofar) \
1097 ((relax_substateT) \
1100 | ((pic) ? 0x20 : 0) \
1101 | ((toofar) ? 0x40 : 0) \
1102 | ((link) ? 0x80 : 0) \
1103 | ((likely) ? 0x100 : 0) \
1104 | ((uncond) ? 0x200 : 0)))
1105 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1106 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1107 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1108 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1109 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1110 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1111 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1113 /* For mips16 code, we use an entirely different form of relaxation.
1114 mips16 supports two versions of most instructions which take
1115 immediate values: a small one which takes some small value, and a
1116 larger one which takes a 16 bit value. Since branches also follow
1117 this pattern, relaxing these values is required.
1119 We can assemble both mips16 and normal MIPS code in a single
1120 object. Therefore, we need to support this type of relaxation at
1121 the same time that we support the relaxation described above. We
1122 use the high bit of the subtype field to distinguish these cases.
1124 The information we store for this type of relaxation is the
1125 argument code found in the opcode file for this relocation, whether
1126 the user explicitly requested a small or extended form, and whether
1127 the relocation is in a jump or jal delay slot. That tells us the
1128 size of the value, and how it should be stored. We also store
1129 whether the fragment is considered to be extended or not. We also
1130 store whether this is known to be a branch to a different section,
1131 whether we have tried to relax this frag yet, and whether we have
1132 ever extended a PC relative fragment because of a shift count. */
1133 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1136 | ((small) ? 0x100 : 0) \
1137 | ((ext) ? 0x200 : 0) \
1138 | ((dslot) ? 0x400 : 0) \
1139 | ((jal_dslot) ? 0x800 : 0))
1140 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1141 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1142 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1143 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1144 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1145 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1146 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1147 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1148 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1149 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x2000) != 0)
1150 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x2000)
1151 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x2000)
1153 /* For microMIPS code, we use relaxation similar to one we use for
1154 MIPS16 code. Some instructions that take immediate values support
1155 two encodings: a small one which takes some small value, and a
1156 larger one which takes a 16 bit value. As some branches also follow
1157 this pattern, relaxing these values is required.
1159 We can assemble both microMIPS and normal MIPS code in a single
1160 object. Therefore, we need to support this type of relaxation at
1161 the same time that we support the relaxation described above. We
1162 use one of the high bits of the subtype field to distinguish these
1165 The information we store for this type of relaxation is the argument
1166 code found in the opcode file for this relocation, the register
1167 selected as the assembler temporary, whether in the 32-bit
1168 instruction mode, whether the branch is unconditional, whether it is
1169 compact, whether there is no delay-slot instruction available to fill
1170 in, whether it stores the link address implicitly in $ra, whether
1171 relaxation of out-of-range 32-bit branches to a sequence of
1172 instructions is enabled, and whether the displacement of a branch is
1173 too large to fit as an immediate argument of a 16-bit and a 32-bit
1174 branch, respectively. */
1175 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1176 uncond, compact, link, nods, \
1177 relax32, toofar16, toofar32) \
1180 | (((at) & 0x1f) << 8) \
1181 | ((insn32) ? 0x2000 : 0) \
1182 | ((pic) ? 0x4000 : 0) \
1183 | ((uncond) ? 0x8000 : 0) \
1184 | ((compact) ? 0x10000 : 0) \
1185 | ((link) ? 0x20000 : 0) \
1186 | ((nods) ? 0x40000 : 0) \
1187 | ((relax32) ? 0x80000 : 0) \
1188 | ((toofar16) ? 0x100000 : 0) \
1189 | ((toofar32) ? 0x200000 : 0))
1190 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1191 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1192 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1193 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1194 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1195 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1196 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1197 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1198 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1199 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1201 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1202 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1203 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1204 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1205 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1206 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1208 /* Sign-extend 16-bit value X. */
1209 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1211 /* Is the given value a sign-extended 32-bit value? */
1212 #define IS_SEXT_32BIT_NUM(x) \
1213 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1214 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1216 /* Is the given value a sign-extended 16-bit value? */
1217 #define IS_SEXT_16BIT_NUM(x) \
1218 (((x) &~ (offsetT) 0x7fff) == 0 \
1219 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1221 /* Is the given value a sign-extended 12-bit value? */
1222 #define IS_SEXT_12BIT_NUM(x) \
1223 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1225 /* Is the given value a sign-extended 9-bit value? */
1226 #define IS_SEXT_9BIT_NUM(x) \
1227 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1229 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1230 #define IS_ZEXT_32BIT_NUM(x) \
1231 (((x) &~ (offsetT) 0xffffffff) == 0 \
1232 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1234 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1236 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1237 (((STRUCT) >> (SHIFT)) & (MASK))
1239 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1240 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1242 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1243 : EXTRACT_BITS ((INSN).insn_opcode, \
1244 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1245 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1246 EXTRACT_BITS ((INSN).insn_opcode, \
1247 MIPS16OP_MASK_##FIELD, \
1248 MIPS16OP_SH_##FIELD)
1250 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1251 #define MIPS16_EXTEND (0xf000U << 16)
1253 /* Whether or not we are emitting a branch-likely macro. */
1254 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1256 /* Global variables used when generating relaxable macros. See the
1257 comment above RELAX_ENCODE for more details about how relaxation
1260 /* 0 if we're not emitting a relaxable macro.
1261 1 if we're emitting the first of the two relaxation alternatives.
1262 2 if we're emitting the second alternative. */
1265 /* The first relaxable fixup in the current frag. (In other words,
1266 the first fixup that refers to relaxable code.) */
1269 /* sizes[0] says how many bytes of the first alternative are stored in
1270 the current frag. Likewise sizes[1] for the second alternative. */
1271 unsigned int sizes
[2];
1273 /* The symbol on which the choice of sequence depends. */
1277 /* Global variables used to decide whether a macro needs a warning. */
1279 /* True if the macro is in a branch delay slot. */
1280 bfd_boolean delay_slot_p
;
1282 /* Set to the length in bytes required if the macro is in a delay slot
1283 that requires a specific length of instruction, otherwise zero. */
1284 unsigned int delay_slot_length
;
1286 /* For relaxable macros, sizes[0] is the length of the first alternative
1287 in bytes and sizes[1] is the length of the second alternative.
1288 For non-relaxable macros, both elements give the length of the
1290 unsigned int sizes
[2];
1292 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1293 instruction of the first alternative in bytes and first_insn_sizes[1]
1294 is the length of the first instruction of the second alternative.
1295 For non-relaxable macros, both elements give the length of the first
1296 instruction in bytes.
1298 Set to zero if we haven't yet seen the first instruction. */
1299 unsigned int first_insn_sizes
[2];
1301 /* For relaxable macros, insns[0] is the number of instructions for the
1302 first alternative and insns[1] is the number of instructions for the
1305 For non-relaxable macros, both elements give the number of
1306 instructions for the macro. */
1307 unsigned int insns
[2];
1309 /* The first variant frag for this macro. */
1311 } mips_macro_warning
;
1313 /* Prototypes for static functions. */
1315 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1317 static void append_insn
1318 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1319 bfd_boolean expansionp
);
1320 static void mips_no_prev_insn (void);
1321 static void macro_build (expressionS
*, const char *, const char *, ...);
1322 static void mips16_macro_build
1323 (expressionS
*, const char *, const char *, va_list *);
1324 static void load_register (int, expressionS
*, int);
1325 static void macro_start (void);
1326 static void macro_end (void);
1327 static void macro (struct mips_cl_insn
*ip
, char *str
);
1328 static void mips16_macro (struct mips_cl_insn
* ip
);
1329 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1330 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1331 static void mips16_immed
1332 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1333 unsigned int, unsigned long *);
1334 static size_t my_getSmallExpression
1335 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1336 static void my_getExpression (expressionS
*, char *);
1337 static void s_align (int);
1338 static void s_change_sec (int);
1339 static void s_change_section (int);
1340 static void s_cons (int);
1341 static void s_float_cons (int);
1342 static void s_mips_globl (int);
1343 static void s_option (int);
1344 static void s_mipsset (int);
1345 static void s_abicalls (int);
1346 static void s_cpload (int);
1347 static void s_cpsetup (int);
1348 static void s_cplocal (int);
1349 static void s_cprestore (int);
1350 static void s_cpreturn (int);
1351 static void s_dtprelword (int);
1352 static void s_dtpreldword (int);
1353 static void s_tprelword (int);
1354 static void s_tpreldword (int);
1355 static void s_gpvalue (int);
1356 static void s_gpword (int);
1357 static void s_gpdword (int);
1358 static void s_ehword (int);
1359 static void s_cpadd (int);
1360 static void s_insn (int);
1361 static void s_nan (int);
1362 static void s_module (int);
1363 static void s_mips_ent (int);
1364 static void s_mips_end (int);
1365 static void s_mips_frame (int);
1366 static void s_mips_mask (int reg_type
);
1367 static void s_mips_stab (int);
1368 static void s_mips_weakext (int);
1369 static void s_mips_file (int);
1370 static void s_mips_loc (int);
1371 static bfd_boolean
pic_need_relax (symbolS
*);
1372 static int relaxed_branch_length (fragS
*, asection
*, int);
1373 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1374 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1375 static void file_mips_check_options (void);
1377 /* Table and functions used to map between CPU/ISA names, and
1378 ISA levels, and CPU numbers. */
1380 struct mips_cpu_info
1382 const char *name
; /* CPU or ISA name. */
1383 int flags
; /* MIPS_CPU_* flags. */
1384 int ase
; /* Set of ASEs implemented by the CPU. */
1385 int isa
; /* ISA level. */
1386 int cpu
; /* CPU number (default CPU if ISA). */
1389 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1391 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1392 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1393 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1395 /* Command-line options. */
1396 const char *md_shortopts
= "O::g::G:";
1400 OPTION_MARCH
= OPTION_MD_BASE
,
1432 OPTION_NO_SMARTMIPS
,
1442 OPTION_NO_MICROMIPS
,
1445 OPTION_COMPAT_ARCH_BASE
,
1454 OPTION_M7000_HILO_FIX
,
1455 OPTION_MNO_7000_HILO_FIX
,
1459 OPTION_NO_FIX_RM7000
,
1460 OPTION_FIX_LOONGSON2F_JUMP
,
1461 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1462 OPTION_FIX_LOONGSON2F_NOP
,
1463 OPTION_NO_FIX_LOONGSON2F_NOP
,
1465 OPTION_NO_FIX_VR4120
,
1467 OPTION_NO_FIX_VR4130
,
1468 OPTION_FIX_CN63XXP1
,
1469 OPTION_NO_FIX_CN63XXP1
,
1476 OPTION_CONSTRUCT_FLOATS
,
1477 OPTION_NO_CONSTRUCT_FLOATS
,
1481 OPTION_RELAX_BRANCH
,
1482 OPTION_NO_RELAX_BRANCH
,
1483 OPTION_IGNORE_BRANCH_ISA
,
1484 OPTION_NO_IGNORE_BRANCH_ISA
,
1493 OPTION_SINGLE_FLOAT
,
1494 OPTION_DOUBLE_FLOAT
,
1507 OPTION_MVXWORKS_PIC
,
1510 OPTION_NO_ODD_SPREG
,
1514 struct option md_longopts
[] =
1516 /* Options which specify architecture. */
1517 {"march", required_argument
, NULL
, OPTION_MARCH
},
1518 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1519 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1520 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1521 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1522 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1523 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1524 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1525 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1526 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1527 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1528 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1529 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1530 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1531 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1532 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1533 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1534 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1536 /* Options which specify Application Specific Extensions (ASEs). */
1537 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1538 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1539 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1540 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1541 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1542 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1543 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1544 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1545 {"mmt", no_argument
, NULL
, OPTION_MT
},
1546 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1547 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1548 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1549 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1550 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1551 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1552 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1553 {"meva", no_argument
, NULL
, OPTION_EVA
},
1554 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1555 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1556 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1557 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1558 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1559 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1560 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1561 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1562 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1563 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1564 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1566 /* Old-style architecture options. Don't add more of these. */
1567 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1568 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1569 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1570 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1571 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1572 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1573 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1574 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1576 /* Options which enable bug fixes. */
1577 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1578 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1579 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1580 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1581 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1582 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1583 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1584 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1585 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1586 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1587 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1588 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1589 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1590 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1591 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1592 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1593 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1595 /* Miscellaneous options. */
1596 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1597 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1598 {"break", no_argument
, NULL
, OPTION_BREAK
},
1599 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1600 {"EB", no_argument
, NULL
, OPTION_EB
},
1601 {"EL", no_argument
, NULL
, OPTION_EL
},
1602 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1603 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1604 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1605 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1606 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1607 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1608 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1609 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1610 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1611 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1612 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1613 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1614 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1615 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1616 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1617 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1618 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1619 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1620 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1621 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1622 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1623 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1624 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1626 /* Strictly speaking this next option is ELF specific,
1627 but we allow it for other ports as well in order to
1628 make testing easier. */
1629 {"32", no_argument
, NULL
, OPTION_32
},
1631 /* ELF-specific options. */
1632 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1633 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1634 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1635 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1636 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1637 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1638 {"n32", no_argument
, NULL
, OPTION_N32
},
1639 {"64", no_argument
, NULL
, OPTION_64
},
1640 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1641 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1642 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1643 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1644 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1645 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1647 {NULL
, no_argument
, NULL
, 0}
1649 size_t md_longopts_size
= sizeof (md_longopts
);
1651 /* Information about either an Application Specific Extension or an
1652 optional architecture feature that, for simplicity, we treat in the
1653 same way as an ASE. */
1656 /* The name of the ASE, used in both the command-line and .set options. */
1659 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1660 and 64-bit architectures, the flags here refer to the subset that
1661 is available on both. */
1664 /* The ASE_* flag used for instructions that are available on 64-bit
1665 architectures but that are not included in FLAGS. */
1666 unsigned int flags64
;
1668 /* The command-line options that turn the ASE on and off. */
1672 /* The minimum required architecture revisions for MIPS32, MIPS64,
1673 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1676 int micromips32_rev
;
1677 int micromips64_rev
;
1679 /* The architecture where the ASE was removed or -1 if the extension has not
1684 /* A table of all supported ASEs. */
1685 static const struct mips_ase mips_ases
[] = {
1686 { "dsp", ASE_DSP
, ASE_DSP64
,
1687 OPTION_DSP
, OPTION_NO_DSP
,
1691 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1692 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1696 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1697 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1701 { "eva", ASE_EVA
, 0,
1702 OPTION_EVA
, OPTION_NO_EVA
,
1706 { "mcu", ASE_MCU
, 0,
1707 OPTION_MCU
, OPTION_NO_MCU
,
1711 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1712 { "mdmx", ASE_MDMX
, 0,
1713 OPTION_MDMX
, OPTION_NO_MDMX
,
1717 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1718 { "mips3d", ASE_MIPS3D
, 0,
1719 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1724 OPTION_MT
, OPTION_NO_MT
,
1728 { "smartmips", ASE_SMARTMIPS
, 0,
1729 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1733 { "virt", ASE_VIRT
, ASE_VIRT64
,
1734 OPTION_VIRT
, OPTION_NO_VIRT
,
1738 { "msa", ASE_MSA
, ASE_MSA64
,
1739 OPTION_MSA
, OPTION_NO_MSA
,
1743 { "xpa", ASE_XPA
, 0,
1744 OPTION_XPA
, OPTION_NO_XPA
,
1749 /* The set of ASEs that require -mfp64. */
1750 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1752 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1753 static const unsigned int mips_ase_groups
[] = {
1754 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
1759 The following pseudo-ops from the Kane and Heinrich MIPS book
1760 should be defined here, but are currently unsupported: .alias,
1761 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1763 The following pseudo-ops from the Kane and Heinrich MIPS book are
1764 specific to the type of debugging information being generated, and
1765 should be defined by the object format: .aent, .begin, .bend,
1766 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1769 The following pseudo-ops from the Kane and Heinrich MIPS book are
1770 not MIPS CPU specific, but are also not specific to the object file
1771 format. This file is probably the best place to define them, but
1772 they are not currently supported: .asm0, .endr, .lab, .struct. */
1774 static const pseudo_typeS mips_pseudo_table
[] =
1776 /* MIPS specific pseudo-ops. */
1777 {"option", s_option
, 0},
1778 {"set", s_mipsset
, 0},
1779 {"rdata", s_change_sec
, 'r'},
1780 {"sdata", s_change_sec
, 's'},
1781 {"livereg", s_ignore
, 0},
1782 {"abicalls", s_abicalls
, 0},
1783 {"cpload", s_cpload
, 0},
1784 {"cpsetup", s_cpsetup
, 0},
1785 {"cplocal", s_cplocal
, 0},
1786 {"cprestore", s_cprestore
, 0},
1787 {"cpreturn", s_cpreturn
, 0},
1788 {"dtprelword", s_dtprelword
, 0},
1789 {"dtpreldword", s_dtpreldword
, 0},
1790 {"tprelword", s_tprelword
, 0},
1791 {"tpreldword", s_tpreldword
, 0},
1792 {"gpvalue", s_gpvalue
, 0},
1793 {"gpword", s_gpword
, 0},
1794 {"gpdword", s_gpdword
, 0},
1795 {"ehword", s_ehword
, 0},
1796 {"cpadd", s_cpadd
, 0},
1797 {"insn", s_insn
, 0},
1799 {"module", s_module
, 0},
1801 /* Relatively generic pseudo-ops that happen to be used on MIPS
1803 {"asciiz", stringer
, 8 + 1},
1804 {"bss", s_change_sec
, 'b'},
1806 {"half", s_cons
, 1},
1807 {"dword", s_cons
, 3},
1808 {"weakext", s_mips_weakext
, 0},
1809 {"origin", s_org
, 0},
1810 {"repeat", s_rept
, 0},
1812 /* For MIPS this is non-standard, but we define it for consistency. */
1813 {"sbss", s_change_sec
, 'B'},
1815 /* These pseudo-ops are defined in read.c, but must be overridden
1816 here for one reason or another. */
1817 {"align", s_align
, 0},
1818 {"byte", s_cons
, 0},
1819 {"data", s_change_sec
, 'd'},
1820 {"double", s_float_cons
, 'd'},
1821 {"float", s_float_cons
, 'f'},
1822 {"globl", s_mips_globl
, 0},
1823 {"global", s_mips_globl
, 0},
1824 {"hword", s_cons
, 1},
1826 {"long", s_cons
, 2},
1827 {"octa", s_cons
, 4},
1828 {"quad", s_cons
, 3},
1829 {"section", s_change_section
, 0},
1830 {"short", s_cons
, 1},
1831 {"single", s_float_cons
, 'f'},
1832 {"stabd", s_mips_stab
, 'd'},
1833 {"stabn", s_mips_stab
, 'n'},
1834 {"stabs", s_mips_stab
, 's'},
1835 {"text", s_change_sec
, 't'},
1836 {"word", s_cons
, 2},
1838 { "extern", ecoff_directive_extern
, 0},
1843 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1845 /* These pseudo-ops should be defined by the object file format.
1846 However, a.out doesn't support them, so we have versions here. */
1847 {"aent", s_mips_ent
, 1},
1848 {"bgnb", s_ignore
, 0},
1849 {"end", s_mips_end
, 0},
1850 {"endb", s_ignore
, 0},
1851 {"ent", s_mips_ent
, 0},
1852 {"file", s_mips_file
, 0},
1853 {"fmask", s_mips_mask
, 'F'},
1854 {"frame", s_mips_frame
, 0},
1855 {"loc", s_mips_loc
, 0},
1856 {"mask", s_mips_mask
, 'R'},
1857 {"verstamp", s_ignore
, 0},
1861 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1862 purpose of the `.dc.a' internal pseudo-op. */
1865 mips_address_bytes (void)
1867 file_mips_check_options ();
1868 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1871 extern void pop_insert (const pseudo_typeS
*);
1874 mips_pop_insert (void)
1876 pop_insert (mips_pseudo_table
);
1877 if (! ECOFF_DEBUGGING
)
1878 pop_insert (mips_nonecoff_pseudo_table
);
1881 /* Symbols labelling the current insn. */
1883 struct insn_label_list
1885 struct insn_label_list
*next
;
1889 static struct insn_label_list
*free_insn_labels
;
1890 #define label_list tc_segment_info_data.labels
1892 static void mips_clear_insn_labels (void);
1893 static void mips_mark_labels (void);
1894 static void mips_compressed_mark_labels (void);
1897 mips_clear_insn_labels (void)
1899 struct insn_label_list
**pl
;
1900 segment_info_type
*si
;
1904 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1907 si
= seg_info (now_seg
);
1908 *pl
= si
->label_list
;
1909 si
->label_list
= NULL
;
1913 /* Mark instruction labels in MIPS16/microMIPS mode. */
1916 mips_mark_labels (void)
1918 if (HAVE_CODE_COMPRESSION
)
1919 mips_compressed_mark_labels ();
1922 static char *expr_end
;
1924 /* An expression in a macro instruction. This is set by mips_ip and
1925 mips16_ip and when populated is always an O_constant. */
1927 static expressionS imm_expr
;
1929 /* The relocatable field in an instruction and the relocs associated
1930 with it. These variables are used for instructions like LUI and
1931 JAL as well as true offsets. They are also used for address
1932 operands in macros. */
1934 static expressionS offset_expr
;
1935 static bfd_reloc_code_real_type offset_reloc
[3]
1936 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1938 /* This is set to the resulting size of the instruction to be produced
1939 by mips16_ip if an explicit extension is used or by mips_ip if an
1940 explicit size is supplied. */
1942 static unsigned int forced_insn_length
;
1944 /* True if we are assembling an instruction. All dot symbols defined during
1945 this time should be treated as code labels. */
1947 static bfd_boolean mips_assembling_insn
;
1949 /* The pdr segment for per procedure frame/regmask info. Not used for
1952 static segT pdr_seg
;
1954 /* The default target format to use. */
1956 #if defined (TE_FreeBSD)
1957 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1958 #elif defined (TE_TMIPS)
1959 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1961 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1965 mips_target_format (void)
1967 switch (OUTPUT_FLAVOR
)
1969 case bfd_target_elf_flavour
:
1971 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1972 return (target_big_endian
1973 ? "elf32-bigmips-vxworks"
1974 : "elf32-littlemips-vxworks");
1976 return (target_big_endian
1977 ? (HAVE_64BIT_OBJECTS
1978 ? ELF_TARGET ("elf64-", "big")
1980 ? ELF_TARGET ("elf32-n", "big")
1981 : ELF_TARGET ("elf32-", "big")))
1982 : (HAVE_64BIT_OBJECTS
1983 ? ELF_TARGET ("elf64-", "little")
1985 ? ELF_TARGET ("elf32-n", "little")
1986 : ELF_TARGET ("elf32-", "little"))));
1993 /* Return the ISA revision that is currently in use, or 0 if we are
1994 generating code for MIPS V or below. */
1999 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2002 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2005 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2008 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2011 /* microMIPS implies revision 2 or above. */
2012 if (mips_opts
.micromips
)
2015 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2021 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2024 mips_ase_mask (unsigned int flags
)
2028 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2029 if (flags
& mips_ase_groups
[i
])
2030 flags
|= mips_ase_groups
[i
];
2034 /* Check whether the current ISA supports ASE. Issue a warning if
2038 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2042 static unsigned int warned_isa
;
2043 static unsigned int warned_fp32
;
2045 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2046 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2048 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2049 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2050 && (warned_isa
& ase
->flags
) != ase
->flags
)
2052 warned_isa
|= ase
->flags
;
2053 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2054 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2056 as_warn (_("the %d-bit %s architecture does not support the"
2057 " `%s' extension"), size
, base
, ase
->name
);
2059 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2060 ase
->name
, base
, size
, min_rev
);
2062 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2063 && (warned_isa
& ase
->flags
) != ase
->flags
)
2065 warned_isa
|= ase
->flags
;
2066 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2067 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2068 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2069 ase
->name
, base
, size
, ase
->rem_rev
);
2072 if ((ase
->flags
& FP64_ASES
)
2073 && mips_opts
.fp
!= 64
2074 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2076 warned_fp32
|= ase
->flags
;
2077 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2081 /* Check all enabled ASEs to see whether they are supported by the
2082 chosen architecture. */
2085 mips_check_isa_supports_ases (void)
2087 unsigned int i
, mask
;
2089 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2091 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2092 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2093 mips_check_isa_supports_ase (&mips_ases
[i
]);
2097 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2098 that were affected. */
2101 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2102 bfd_boolean enabled_p
)
2106 mask
= mips_ase_mask (ase
->flags
);
2109 opts
->ase
|= ase
->flags
;
2113 /* Return the ASE called NAME, or null if none. */
2115 static const struct mips_ase
*
2116 mips_lookup_ase (const char *name
)
2120 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2121 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2122 return &mips_ases
[i
];
2126 /* Return the length of a microMIPS instruction in bytes. If bits of
2127 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2128 otherwise it is a 32-bit instruction. */
2130 static inline unsigned int
2131 micromips_insn_length (const struct mips_opcode
*mo
)
2133 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2136 /* Return the length of MIPS16 instruction OPCODE. */
2138 static inline unsigned int
2139 mips16_opcode_length (unsigned long opcode
)
2141 return (opcode
>> 16) == 0 ? 2 : 4;
2144 /* Return the length of instruction INSN. */
2146 static inline unsigned int
2147 insn_length (const struct mips_cl_insn
*insn
)
2149 if (mips_opts
.micromips
)
2150 return micromips_insn_length (insn
->insn_mo
);
2151 else if (mips_opts
.mips16
)
2152 return mips16_opcode_length (insn
->insn_opcode
);
2157 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2160 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2165 insn
->insn_opcode
= mo
->match
;
2168 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2169 insn
->fixp
[i
] = NULL
;
2170 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2171 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2172 insn
->mips16_absolute_jump_p
= 0;
2173 insn
->complete_p
= 0;
2174 insn
->cleared_p
= 0;
2177 /* Get a list of all the operands in INSN. */
2179 static const struct mips_operand_array
*
2180 insn_operands (const struct mips_cl_insn
*insn
)
2182 if (insn
->insn_mo
>= &mips_opcodes
[0]
2183 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2184 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2186 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2187 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2188 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2190 if (insn
->insn_mo
>= µmips_opcodes
[0]
2191 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2192 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2197 /* Get a description of operand OPNO of INSN. */
2199 static const struct mips_operand
*
2200 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2202 const struct mips_operand_array
*operands
;
2204 operands
= insn_operands (insn
);
2205 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2207 return operands
->operand
[opno
];
2210 /* Install UVAL as the value of OPERAND in INSN. */
2213 insn_insert_operand (struct mips_cl_insn
*insn
,
2214 const struct mips_operand
*operand
, unsigned int uval
)
2216 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2219 /* Extract the value of OPERAND from INSN. */
2221 static inline unsigned
2222 insn_extract_operand (const struct mips_cl_insn
*insn
,
2223 const struct mips_operand
*operand
)
2225 return mips_extract_operand (operand
, insn
->insn_opcode
);
2228 /* Record the current MIPS16/microMIPS mode in now_seg. */
2231 mips_record_compressed_mode (void)
2233 segment_info_type
*si
;
2235 si
= seg_info (now_seg
);
2236 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2237 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2238 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2239 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2242 /* Read a standard MIPS instruction from BUF. */
2244 static unsigned long
2245 read_insn (char *buf
)
2247 if (target_big_endian
)
2248 return bfd_getb32 ((bfd_byte
*) buf
);
2250 return bfd_getl32 ((bfd_byte
*) buf
);
2253 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2257 write_insn (char *buf
, unsigned int insn
)
2259 md_number_to_chars (buf
, insn
, 4);
2263 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2264 has length LENGTH. */
2266 static unsigned long
2267 read_compressed_insn (char *buf
, unsigned int length
)
2273 for (i
= 0; i
< length
; i
+= 2)
2276 if (target_big_endian
)
2277 insn
|= bfd_getb16 ((char *) buf
);
2279 insn
|= bfd_getl16 ((char *) buf
);
2285 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2286 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2289 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2293 for (i
= 0; i
< length
; i
+= 2)
2294 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2295 return buf
+ length
;
2298 /* Install INSN at the location specified by its "frag" and "where" fields. */
2301 install_insn (const struct mips_cl_insn
*insn
)
2303 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2304 if (HAVE_CODE_COMPRESSION
)
2305 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2307 write_insn (f
, insn
->insn_opcode
);
2308 mips_record_compressed_mode ();
2311 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2312 and install the opcode in the new location. */
2315 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2320 insn
->where
= where
;
2321 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2322 if (insn
->fixp
[i
] != NULL
)
2324 insn
->fixp
[i
]->fx_frag
= frag
;
2325 insn
->fixp
[i
]->fx_where
= where
;
2327 install_insn (insn
);
2330 /* Add INSN to the end of the output. */
2333 add_fixed_insn (struct mips_cl_insn
*insn
)
2335 char *f
= frag_more (insn_length (insn
));
2336 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2339 /* Start a variant frag and move INSN to the start of the variant part,
2340 marking it as fixed. The other arguments are as for frag_var. */
2343 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2344 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2346 frag_grow (max_chars
);
2347 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2349 frag_var (rs_machine_dependent
, max_chars
, var
,
2350 subtype
, symbol
, offset
, NULL
);
2353 /* Insert N copies of INSN into the history buffer, starting at
2354 position FIRST. Neither FIRST nor N need to be clipped. */
2357 insert_into_history (unsigned int first
, unsigned int n
,
2358 const struct mips_cl_insn
*insn
)
2360 if (mips_relax
.sequence
!= 2)
2364 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2366 history
[i
] = history
[i
- n
];
2372 /* Clear the error in insn_error. */
2375 clear_insn_error (void)
2377 memset (&insn_error
, 0, sizeof (insn_error
));
2380 /* Possibly record error message MSG for the current instruction.
2381 If the error is about a particular argument, ARGNUM is the 1-based
2382 number of that argument, otherwise it is 0. FORMAT is the format
2383 of MSG. Return true if MSG was used, false if the current message
2387 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2392 /* Give priority to errors against specific arguments, and to
2393 the first whole-instruction message. */
2399 /* Keep insn_error if it is against a later argument. */
2400 if (argnum
< insn_error
.min_argnum
)
2403 /* If both errors are against the same argument but are different,
2404 give up on reporting a specific error for this argument.
2405 See the comment about mips_insn_error for details. */
2406 if (argnum
== insn_error
.min_argnum
2408 && strcmp (insn_error
.msg
, msg
) != 0)
2411 insn_error
.min_argnum
+= 1;
2415 insn_error
.min_argnum
= argnum
;
2416 insn_error
.format
= format
;
2417 insn_error
.msg
= msg
;
2421 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2422 as for set_insn_error_format. */
2425 set_insn_error (int argnum
, const char *msg
)
2427 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2430 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2431 as for set_insn_error_format. */
2434 set_insn_error_i (int argnum
, const char *msg
, int i
)
2436 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2440 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2441 are as for set_insn_error_format. */
2444 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2446 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2448 insn_error
.u
.ss
[0] = s1
;
2449 insn_error
.u
.ss
[1] = s2
;
2453 /* Report the error in insn_error, which is against assembly code STR. */
2456 report_insn_error (const char *str
)
2458 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2460 switch (insn_error
.format
)
2467 as_bad (msg
, insn_error
.u
.i
, str
);
2471 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2475 free ((char *) msg
);
2478 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2479 the idea is to make it obvious at a glance that each errata is
2483 init_vr4120_conflicts (void)
2485 #define CONFLICT(FIRST, SECOND) \
2486 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2488 /* Errata 21 - [D]DIV[U] after [D]MACC */
2489 CONFLICT (MACC
, DIV
);
2490 CONFLICT (DMACC
, DIV
);
2492 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2493 CONFLICT (DMULT
, DMULT
);
2494 CONFLICT (DMULT
, DMACC
);
2495 CONFLICT (DMACC
, DMULT
);
2496 CONFLICT (DMACC
, DMACC
);
2498 /* Errata 24 - MT{LO,HI} after [D]MACC */
2499 CONFLICT (MACC
, MTHILO
);
2500 CONFLICT (DMACC
, MTHILO
);
2502 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2503 instruction is executed immediately after a MACC or DMACC
2504 instruction, the result of [either instruction] is incorrect." */
2505 CONFLICT (MACC
, MULT
);
2506 CONFLICT (MACC
, DMULT
);
2507 CONFLICT (DMACC
, MULT
);
2508 CONFLICT (DMACC
, DMULT
);
2510 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2511 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2512 DDIV or DDIVU instruction, the result of the MACC or
2513 DMACC instruction is incorrect.". */
2514 CONFLICT (DMULT
, MACC
);
2515 CONFLICT (DMULT
, DMACC
);
2516 CONFLICT (DIV
, MACC
);
2517 CONFLICT (DIV
, DMACC
);
2527 #define RNUM_MASK 0x00000ff
2528 #define RTYPE_MASK 0x0ffff00
2529 #define RTYPE_NUM 0x0000100
2530 #define RTYPE_FPU 0x0000200
2531 #define RTYPE_FCC 0x0000400
2532 #define RTYPE_VEC 0x0000800
2533 #define RTYPE_GP 0x0001000
2534 #define RTYPE_CP0 0x0002000
2535 #define RTYPE_PC 0x0004000
2536 #define RTYPE_ACC 0x0008000
2537 #define RTYPE_CCC 0x0010000
2538 #define RTYPE_VI 0x0020000
2539 #define RTYPE_VF 0x0040000
2540 #define RTYPE_R5900_I 0x0080000
2541 #define RTYPE_R5900_Q 0x0100000
2542 #define RTYPE_R5900_R 0x0200000
2543 #define RTYPE_R5900_ACC 0x0400000
2544 #define RTYPE_MSA 0x0800000
2545 #define RWARN 0x8000000
2547 #define GENERIC_REGISTER_NUMBERS \
2548 {"$0", RTYPE_NUM | 0}, \
2549 {"$1", RTYPE_NUM | 1}, \
2550 {"$2", RTYPE_NUM | 2}, \
2551 {"$3", RTYPE_NUM | 3}, \
2552 {"$4", RTYPE_NUM | 4}, \
2553 {"$5", RTYPE_NUM | 5}, \
2554 {"$6", RTYPE_NUM | 6}, \
2555 {"$7", RTYPE_NUM | 7}, \
2556 {"$8", RTYPE_NUM | 8}, \
2557 {"$9", RTYPE_NUM | 9}, \
2558 {"$10", RTYPE_NUM | 10}, \
2559 {"$11", RTYPE_NUM | 11}, \
2560 {"$12", RTYPE_NUM | 12}, \
2561 {"$13", RTYPE_NUM | 13}, \
2562 {"$14", RTYPE_NUM | 14}, \
2563 {"$15", RTYPE_NUM | 15}, \
2564 {"$16", RTYPE_NUM | 16}, \
2565 {"$17", RTYPE_NUM | 17}, \
2566 {"$18", RTYPE_NUM | 18}, \
2567 {"$19", RTYPE_NUM | 19}, \
2568 {"$20", RTYPE_NUM | 20}, \
2569 {"$21", RTYPE_NUM | 21}, \
2570 {"$22", RTYPE_NUM | 22}, \
2571 {"$23", RTYPE_NUM | 23}, \
2572 {"$24", RTYPE_NUM | 24}, \
2573 {"$25", RTYPE_NUM | 25}, \
2574 {"$26", RTYPE_NUM | 26}, \
2575 {"$27", RTYPE_NUM | 27}, \
2576 {"$28", RTYPE_NUM | 28}, \
2577 {"$29", RTYPE_NUM | 29}, \
2578 {"$30", RTYPE_NUM | 30}, \
2579 {"$31", RTYPE_NUM | 31}
2581 #define FPU_REGISTER_NAMES \
2582 {"$f0", RTYPE_FPU | 0}, \
2583 {"$f1", RTYPE_FPU | 1}, \
2584 {"$f2", RTYPE_FPU | 2}, \
2585 {"$f3", RTYPE_FPU | 3}, \
2586 {"$f4", RTYPE_FPU | 4}, \
2587 {"$f5", RTYPE_FPU | 5}, \
2588 {"$f6", RTYPE_FPU | 6}, \
2589 {"$f7", RTYPE_FPU | 7}, \
2590 {"$f8", RTYPE_FPU | 8}, \
2591 {"$f9", RTYPE_FPU | 9}, \
2592 {"$f10", RTYPE_FPU | 10}, \
2593 {"$f11", RTYPE_FPU | 11}, \
2594 {"$f12", RTYPE_FPU | 12}, \
2595 {"$f13", RTYPE_FPU | 13}, \
2596 {"$f14", RTYPE_FPU | 14}, \
2597 {"$f15", RTYPE_FPU | 15}, \
2598 {"$f16", RTYPE_FPU | 16}, \
2599 {"$f17", RTYPE_FPU | 17}, \
2600 {"$f18", RTYPE_FPU | 18}, \
2601 {"$f19", RTYPE_FPU | 19}, \
2602 {"$f20", RTYPE_FPU | 20}, \
2603 {"$f21", RTYPE_FPU | 21}, \
2604 {"$f22", RTYPE_FPU | 22}, \
2605 {"$f23", RTYPE_FPU | 23}, \
2606 {"$f24", RTYPE_FPU | 24}, \
2607 {"$f25", RTYPE_FPU | 25}, \
2608 {"$f26", RTYPE_FPU | 26}, \
2609 {"$f27", RTYPE_FPU | 27}, \
2610 {"$f28", RTYPE_FPU | 28}, \
2611 {"$f29", RTYPE_FPU | 29}, \
2612 {"$f30", RTYPE_FPU | 30}, \
2613 {"$f31", RTYPE_FPU | 31}
2615 #define FPU_CONDITION_CODE_NAMES \
2616 {"$fcc0", RTYPE_FCC | 0}, \
2617 {"$fcc1", RTYPE_FCC | 1}, \
2618 {"$fcc2", RTYPE_FCC | 2}, \
2619 {"$fcc3", RTYPE_FCC | 3}, \
2620 {"$fcc4", RTYPE_FCC | 4}, \
2621 {"$fcc5", RTYPE_FCC | 5}, \
2622 {"$fcc6", RTYPE_FCC | 6}, \
2623 {"$fcc7", RTYPE_FCC | 7}
2625 #define COPROC_CONDITION_CODE_NAMES \
2626 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2627 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2628 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2629 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2630 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2631 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2632 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2633 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2635 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2636 {"$a4", RTYPE_GP | 8}, \
2637 {"$a5", RTYPE_GP | 9}, \
2638 {"$a6", RTYPE_GP | 10}, \
2639 {"$a7", RTYPE_GP | 11}, \
2640 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2641 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2642 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2643 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2644 {"$t0", RTYPE_GP | 12}, \
2645 {"$t1", RTYPE_GP | 13}, \
2646 {"$t2", RTYPE_GP | 14}, \
2647 {"$t3", RTYPE_GP | 15}
2649 #define O32_SYMBOLIC_REGISTER_NAMES \
2650 {"$t0", RTYPE_GP | 8}, \
2651 {"$t1", RTYPE_GP | 9}, \
2652 {"$t2", RTYPE_GP | 10}, \
2653 {"$t3", RTYPE_GP | 11}, \
2654 {"$t4", RTYPE_GP | 12}, \
2655 {"$t5", RTYPE_GP | 13}, \
2656 {"$t6", RTYPE_GP | 14}, \
2657 {"$t7", RTYPE_GP | 15}, \
2658 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2659 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2660 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2661 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2663 /* Remaining symbolic register names */
2664 #define SYMBOLIC_REGISTER_NAMES \
2665 {"$zero", RTYPE_GP | 0}, \
2666 {"$at", RTYPE_GP | 1}, \
2667 {"$AT", RTYPE_GP | 1}, \
2668 {"$v0", RTYPE_GP | 2}, \
2669 {"$v1", RTYPE_GP | 3}, \
2670 {"$a0", RTYPE_GP | 4}, \
2671 {"$a1", RTYPE_GP | 5}, \
2672 {"$a2", RTYPE_GP | 6}, \
2673 {"$a3", RTYPE_GP | 7}, \
2674 {"$s0", RTYPE_GP | 16}, \
2675 {"$s1", RTYPE_GP | 17}, \
2676 {"$s2", RTYPE_GP | 18}, \
2677 {"$s3", RTYPE_GP | 19}, \
2678 {"$s4", RTYPE_GP | 20}, \
2679 {"$s5", RTYPE_GP | 21}, \
2680 {"$s6", RTYPE_GP | 22}, \
2681 {"$s7", RTYPE_GP | 23}, \
2682 {"$t8", RTYPE_GP | 24}, \
2683 {"$t9", RTYPE_GP | 25}, \
2684 {"$k0", RTYPE_GP | 26}, \
2685 {"$kt0", RTYPE_GP | 26}, \
2686 {"$k1", RTYPE_GP | 27}, \
2687 {"$kt1", RTYPE_GP | 27}, \
2688 {"$gp", RTYPE_GP | 28}, \
2689 {"$sp", RTYPE_GP | 29}, \
2690 {"$s8", RTYPE_GP | 30}, \
2691 {"$fp", RTYPE_GP | 30}, \
2692 {"$ra", RTYPE_GP | 31}
2694 #define MIPS16_SPECIAL_REGISTER_NAMES \
2695 {"$pc", RTYPE_PC | 0}
2697 #define MDMX_VECTOR_REGISTER_NAMES \
2698 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2699 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2700 {"$v2", RTYPE_VEC | 2}, \
2701 {"$v3", RTYPE_VEC | 3}, \
2702 {"$v4", RTYPE_VEC | 4}, \
2703 {"$v5", RTYPE_VEC | 5}, \
2704 {"$v6", RTYPE_VEC | 6}, \
2705 {"$v7", RTYPE_VEC | 7}, \
2706 {"$v8", RTYPE_VEC | 8}, \
2707 {"$v9", RTYPE_VEC | 9}, \
2708 {"$v10", RTYPE_VEC | 10}, \
2709 {"$v11", RTYPE_VEC | 11}, \
2710 {"$v12", RTYPE_VEC | 12}, \
2711 {"$v13", RTYPE_VEC | 13}, \
2712 {"$v14", RTYPE_VEC | 14}, \
2713 {"$v15", RTYPE_VEC | 15}, \
2714 {"$v16", RTYPE_VEC | 16}, \
2715 {"$v17", RTYPE_VEC | 17}, \
2716 {"$v18", RTYPE_VEC | 18}, \
2717 {"$v19", RTYPE_VEC | 19}, \
2718 {"$v20", RTYPE_VEC | 20}, \
2719 {"$v21", RTYPE_VEC | 21}, \
2720 {"$v22", RTYPE_VEC | 22}, \
2721 {"$v23", RTYPE_VEC | 23}, \
2722 {"$v24", RTYPE_VEC | 24}, \
2723 {"$v25", RTYPE_VEC | 25}, \
2724 {"$v26", RTYPE_VEC | 26}, \
2725 {"$v27", RTYPE_VEC | 27}, \
2726 {"$v28", RTYPE_VEC | 28}, \
2727 {"$v29", RTYPE_VEC | 29}, \
2728 {"$v30", RTYPE_VEC | 30}, \
2729 {"$v31", RTYPE_VEC | 31}
2731 #define R5900_I_NAMES \
2732 {"$I", RTYPE_R5900_I | 0}
2734 #define R5900_Q_NAMES \
2735 {"$Q", RTYPE_R5900_Q | 0}
2737 #define R5900_R_NAMES \
2738 {"$R", RTYPE_R5900_R | 0}
2740 #define R5900_ACC_NAMES \
2741 {"$ACC", RTYPE_R5900_ACC | 0 }
2743 #define MIPS_DSP_ACCUMULATOR_NAMES \
2744 {"$ac0", RTYPE_ACC | 0}, \
2745 {"$ac1", RTYPE_ACC | 1}, \
2746 {"$ac2", RTYPE_ACC | 2}, \
2747 {"$ac3", RTYPE_ACC | 3}
2749 static const struct regname reg_names
[] = {
2750 GENERIC_REGISTER_NUMBERS
,
2752 FPU_CONDITION_CODE_NAMES
,
2753 COPROC_CONDITION_CODE_NAMES
,
2755 /* The $txx registers depends on the abi,
2756 these will be added later into the symbol table from
2757 one of the tables below once mips_abi is set after
2758 parsing of arguments from the command line. */
2759 SYMBOLIC_REGISTER_NAMES
,
2761 MIPS16_SPECIAL_REGISTER_NAMES
,
2762 MDMX_VECTOR_REGISTER_NAMES
,
2767 MIPS_DSP_ACCUMULATOR_NAMES
,
2771 static const struct regname reg_names_o32
[] = {
2772 O32_SYMBOLIC_REGISTER_NAMES
,
2776 static const struct regname reg_names_n32n64
[] = {
2777 N32N64_SYMBOLIC_REGISTER_NAMES
,
2781 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2782 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2783 of these register symbols, return the associated vector register,
2784 otherwise return SYMVAL itself. */
2787 mips_prefer_vec_regno (unsigned int symval
)
2789 if ((symval
& -2) == (RTYPE_GP
| 2))
2790 return RTYPE_VEC
| (symval
& 1);
2794 /* Return true if string [S, E) is a valid register name, storing its
2795 symbol value in *SYMVAL_PTR if so. */
2798 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2803 /* Terminate name. */
2807 /* Look up the name. */
2808 symbol
= symbol_find (s
);
2811 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2814 *symval_ptr
= S_GET_VALUE (symbol
);
2818 /* Return true if the string at *SPTR is a valid register name. Allow it
2819 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2822 When returning true, move *SPTR past the register, store the
2823 register's symbol value in *SYMVAL_PTR and the channel mask in
2824 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2825 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2826 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2829 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2830 unsigned int *channels_ptr
)
2834 unsigned int channels
, symval
, bit
;
2836 /* Find end of name. */
2838 if (is_name_beginner (*e
))
2840 while (is_part_of_name (*e
))
2844 if (!mips_parse_register_1 (s
, e
, &symval
))
2849 /* Eat characters from the end of the string that are valid
2850 channel suffixes. The preceding register must be $ACC or
2851 end with a digit, so there is no ambiguity. */
2854 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2855 if (m
> s
&& m
[-1] == *q
)
2862 || !mips_parse_register_1 (s
, m
, &symval
)
2863 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2868 *symval_ptr
= symval
;
2870 *channels_ptr
= channels
;
2874 /* Check if SPTR points at a valid register specifier according to TYPES.
2875 If so, then return 1, advance S to consume the specifier and store
2876 the register's number in REGNOP, otherwise return 0. */
2879 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2883 if (mips_parse_register (s
, ®no
, NULL
))
2885 if (types
& RTYPE_VEC
)
2886 regno
= mips_prefer_vec_regno (regno
);
2895 as_warn (_("unrecognized register name `%s'"), *s
);
2900 return regno
<= RNUM_MASK
;
2903 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2904 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2907 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2912 for (i
= 0; i
< 4; i
++)
2913 if (*s
== "xyzw"[i
])
2915 *channels
|= 1 << (3 - i
);
2921 /* Token types for parsed operand lists. */
2922 enum mips_operand_token_type
{
2923 /* A plain register, e.g. $f2. */
2926 /* A 4-bit XYZW channel mask. */
2929 /* A constant vector index, e.g. [1]. */
2932 /* A register vector index, e.g. [$2]. */
2935 /* A continuous range of registers, e.g. $s0-$s4. */
2938 /* A (possibly relocated) expression. */
2941 /* A floating-point value. */
2944 /* A single character. This can be '(', ')' or ',', but '(' only appears
2948 /* A doubled character, either "--" or "++". */
2951 /* The end of the operand list. */
2955 /* A parsed operand token. */
2956 struct mips_operand_token
2958 /* The type of token. */
2959 enum mips_operand_token_type type
;
2962 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2965 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2966 unsigned int channels
;
2968 /* The integer value of an OT_INTEGER_INDEX. */
2971 /* The two register symbol values involved in an OT_REG_RANGE. */
2973 unsigned int regno1
;
2974 unsigned int regno2
;
2977 /* The value of an OT_INTEGER. The value is represented as an
2978 expression and the relocation operators that were applied to
2979 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2980 relocation operators were used. */
2983 bfd_reloc_code_real_type relocs
[3];
2986 /* The binary data for an OT_FLOAT constant, and the number of bytes
2989 unsigned char data
[8];
2993 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2998 /* An obstack used to construct lists of mips_operand_tokens. */
2999 static struct obstack mips_operand_tokens
;
3001 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3004 mips_add_token (struct mips_operand_token
*token
,
3005 enum mips_operand_token_type type
)
3008 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3011 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3012 and OT_REG tokens for them if so, and return a pointer to the first
3013 unconsumed character. Return null otherwise. */
3016 mips_parse_base_start (char *s
)
3018 struct mips_operand_token token
;
3019 unsigned int regno
, channels
;
3020 bfd_boolean decrement_p
;
3026 SKIP_SPACE_TABS (s
);
3028 /* Only match "--" as part of a base expression. In other contexts "--X"
3029 is a double negative. */
3030 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3034 SKIP_SPACE_TABS (s
);
3037 /* Allow a channel specifier because that leads to better error messages
3038 than treating something like "$vf0x++" as an expression. */
3039 if (!mips_parse_register (&s
, ®no
, &channels
))
3043 mips_add_token (&token
, OT_CHAR
);
3048 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3051 token
.u
.regno
= regno
;
3052 mips_add_token (&token
, OT_REG
);
3056 token
.u
.channels
= channels
;
3057 mips_add_token (&token
, OT_CHANNELS
);
3060 /* For consistency, only match "++" as part of base expressions too. */
3061 SKIP_SPACE_TABS (s
);
3062 if (s
[0] == '+' && s
[1] == '+')
3066 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3072 /* Parse one or more tokens from S. Return a pointer to the first
3073 unconsumed character on success. Return null if an error was found
3074 and store the error text in insn_error. FLOAT_FORMAT is as for
3075 mips_parse_arguments. */
3078 mips_parse_argument_token (char *s
, char float_format
)
3080 char *end
, *save_in
;
3082 unsigned int regno1
, regno2
, channels
;
3083 struct mips_operand_token token
;
3085 /* First look for "($reg", since we want to treat that as an
3086 OT_CHAR and OT_REG rather than an expression. */
3087 end
= mips_parse_base_start (s
);
3091 /* Handle other characters that end up as OT_CHARs. */
3092 if (*s
== ')' || *s
== ',')
3095 mips_add_token (&token
, OT_CHAR
);
3100 /* Handle tokens that start with a register. */
3101 if (mips_parse_register (&s
, ®no1
, &channels
))
3105 /* A register and a VU0 channel suffix. */
3106 token
.u
.regno
= regno1
;
3107 mips_add_token (&token
, OT_REG
);
3109 token
.u
.channels
= channels
;
3110 mips_add_token (&token
, OT_CHANNELS
);
3114 SKIP_SPACE_TABS (s
);
3117 /* A register range. */
3119 SKIP_SPACE_TABS (s
);
3120 if (!mips_parse_register (&s
, ®no2
, NULL
))
3122 set_insn_error (0, _("invalid register range"));
3126 token
.u
.reg_range
.regno1
= regno1
;
3127 token
.u
.reg_range
.regno2
= regno2
;
3128 mips_add_token (&token
, OT_REG_RANGE
);
3132 /* Add the register itself. */
3133 token
.u
.regno
= regno1
;
3134 mips_add_token (&token
, OT_REG
);
3136 /* Check for a vector index. */
3140 SKIP_SPACE_TABS (s
);
3141 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3142 mips_add_token (&token
, OT_REG_INDEX
);
3145 expressionS element
;
3147 my_getExpression (&element
, s
);
3148 if (element
.X_op
!= O_constant
)
3150 set_insn_error (0, _("vector element must be constant"));
3154 token
.u
.index
= element
.X_add_number
;
3155 mips_add_token (&token
, OT_INTEGER_INDEX
);
3157 SKIP_SPACE_TABS (s
);
3160 set_insn_error (0, _("missing `]'"));
3170 /* First try to treat expressions as floats. */
3171 save_in
= input_line_pointer
;
3172 input_line_pointer
= s
;
3173 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3174 &token
.u
.flt
.length
);
3175 end
= input_line_pointer
;
3176 input_line_pointer
= save_in
;
3179 set_insn_error (0, err
);
3184 mips_add_token (&token
, OT_FLOAT
);
3189 /* Treat everything else as an integer expression. */
3190 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3191 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3192 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3193 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3195 mips_add_token (&token
, OT_INTEGER
);
3199 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3200 if expressions should be treated as 32-bit floating-point constants,
3201 'd' if they should be treated as 64-bit floating-point constants,
3202 or 0 if they should be treated as integer expressions (the usual case).
3204 Return a list of tokens on success, otherwise return 0. The caller
3205 must obstack_free the list after use. */
3207 static struct mips_operand_token
*
3208 mips_parse_arguments (char *s
, char float_format
)
3210 struct mips_operand_token token
;
3212 SKIP_SPACE_TABS (s
);
3215 s
= mips_parse_argument_token (s
, float_format
);
3218 obstack_free (&mips_operand_tokens
,
3219 obstack_finish (&mips_operand_tokens
));
3222 SKIP_SPACE_TABS (s
);
3224 mips_add_token (&token
, OT_END
);
3225 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3228 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3229 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3232 is_opcode_valid (const struct mips_opcode
*mo
)
3234 int isa
= mips_opts
.isa
;
3235 int ase
= mips_opts
.ase
;
3239 if (ISA_HAS_64BIT_REGS (isa
))
3240 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3241 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3242 ase
|= mips_ases
[i
].flags64
;
3244 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3247 /* Check whether the instruction or macro requires single-precision or
3248 double-precision floating-point support. Note that this information is
3249 stored differently in the opcode table for insns and macros. */
3250 if (mo
->pinfo
== INSN_MACRO
)
3252 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3253 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3257 fp_s
= mo
->pinfo
& FP_S
;
3258 fp_d
= mo
->pinfo
& FP_D
;
3261 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3264 if (fp_s
&& mips_opts
.soft_float
)
3270 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3271 selected ISA and architecture. */
3274 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3276 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3279 /* Return TRUE if the size of the microMIPS opcode MO matches one
3280 explicitly requested. Always TRUE in the standard MIPS mode.
3281 Use is_size_valid_16 for MIPS16 opcodes. */
3284 is_size_valid (const struct mips_opcode
*mo
)
3286 if (!mips_opts
.micromips
)
3289 if (mips_opts
.insn32
)
3291 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3293 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3296 if (!forced_insn_length
)
3298 if (mo
->pinfo
== INSN_MACRO
)
3300 return forced_insn_length
== micromips_insn_length (mo
);
3303 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3304 explicitly requested. */
3307 is_size_valid_16 (const struct mips_opcode
*mo
)
3309 if (!forced_insn_length
)
3311 if (mo
->pinfo
== INSN_MACRO
)
3313 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3315 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3320 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3321 of the preceding instruction. Always TRUE in the standard MIPS mode.
3323 We don't accept macros in 16-bit delay slots to avoid a case where
3324 a macro expansion fails because it relies on a preceding 32-bit real
3325 instruction to have matched and does not handle the operands correctly.
3326 The only macros that may expand to 16-bit instructions are JAL that
3327 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3328 and BGT (that likewise cannot be placed in a delay slot) that decay to
3329 a NOP. In all these cases the macros precede any corresponding real
3330 instruction definitions in the opcode table, so they will match in the
3331 second pass where the size of the delay slot is ignored and therefore
3332 produce correct code. */
3335 is_delay_slot_valid (const struct mips_opcode
*mo
)
3337 if (!mips_opts
.micromips
)
3340 if (mo
->pinfo
== INSN_MACRO
)
3341 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3342 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3343 && micromips_insn_length (mo
) != 4)
3345 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3346 && micromips_insn_length (mo
) != 2)
3352 /* For consistency checking, verify that all bits of OPCODE are specified
3353 either by the match/mask part of the instruction definition, or by the
3354 operand list. Also build up a list of operands in OPERANDS.
3356 INSN_BITS says which bits of the instruction are significant.
3357 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3358 provides the mips_operand description of each operand. DECODE_OPERAND
3359 is null for MIPS16 instructions. */
3362 validate_mips_insn (const struct mips_opcode
*opcode
,
3363 unsigned long insn_bits
,
3364 const struct mips_operand
*(*decode_operand
) (const char *),
3365 struct mips_operand_array
*operands
)
3368 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3369 const struct mips_operand
*operand
;
3371 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3372 if ((mask
& opcode
->match
) != opcode
->match
)
3374 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3375 opcode
->name
, opcode
->args
);
3380 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3381 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3382 for (s
= opcode
->args
; *s
; ++s
)
3395 if (!decode_operand
)
3396 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3398 operand
= decode_operand (s
);
3399 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3401 as_bad (_("internal: unknown operand type: %s %s"),
3402 opcode
->name
, opcode
->args
);
3405 gas_assert (opno
< MAX_OPERANDS
);
3406 operands
->operand
[opno
] = operand
;
3407 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3409 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3410 if (operand
->type
== OP_MDMX_IMM_REG
)
3411 /* Bit 5 is the format selector (OB vs QH). The opcode table
3412 has separate entries for each format. */
3413 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3414 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3415 used_bits
&= ~(mask
& 0x700);
3417 /* Skip prefix characters. */
3418 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3423 doubled
= used_bits
& mask
& insn_bits
;
3426 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3427 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3431 undefined
= ~used_bits
& insn_bits
;
3432 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3434 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3435 undefined
, opcode
->name
, opcode
->args
);
3438 used_bits
&= ~insn_bits
;
3441 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3442 used_bits
, opcode
->name
, opcode
->args
);
3448 /* The MIPS16 version of validate_mips_insn. */
3451 validate_mips16_insn (const struct mips_opcode
*opcode
,
3452 struct mips_operand_array
*operands
)
3454 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3456 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3459 /* The microMIPS version of validate_mips_insn. */
3462 validate_micromips_insn (const struct mips_opcode
*opc
,
3463 struct mips_operand_array
*operands
)
3465 unsigned long insn_bits
;
3466 unsigned long major
;
3467 unsigned int length
;
3469 if (opc
->pinfo
== INSN_MACRO
)
3470 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3473 length
= micromips_insn_length (opc
);
3474 if (length
!= 2 && length
!= 4)
3476 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3477 "%s %s"), length
, opc
->name
, opc
->args
);
3480 major
= opc
->match
>> (10 + 8 * (length
- 2));
3481 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3482 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3484 as_bad (_("internal error: bad microMIPS opcode "
3485 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3489 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3490 insn_bits
= 1 << 4 * length
;
3491 insn_bits
<<= 4 * length
;
3493 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3497 /* This function is called once, at assembler startup time. It should set up
3498 all the tables, etc. that the MD part of the assembler will need. */
3503 const char *retval
= NULL
;
3507 if (mips_pic
!= NO_PIC
)
3509 if (g_switch_seen
&& g_switch_value
!= 0)
3510 as_bad (_("-G may not be used in position-independent code"));
3513 else if (mips_abicalls
)
3515 if (g_switch_seen
&& g_switch_value
!= 0)
3516 as_bad (_("-G may not be used with abicalls"));
3520 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3521 as_warn (_("could not set architecture and machine"));
3523 op_hash
= hash_new ();
3525 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3526 for (i
= 0; i
< NUMOPCODES
;)
3528 const char *name
= mips_opcodes
[i
].name
;
3530 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3533 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3534 mips_opcodes
[i
].name
, retval
);
3535 /* Probably a memory allocation problem? Give up now. */
3536 as_fatal (_("broken assembler, no assembly attempted"));
3540 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3541 decode_mips_operand
, &mips_operands
[i
]))
3543 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3545 create_insn (&nop_insn
, mips_opcodes
+ i
);
3546 if (mips_fix_loongson2f_nop
)
3547 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3548 nop_insn
.fixed_p
= 1;
3552 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3555 mips16_op_hash
= hash_new ();
3556 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3557 bfd_mips16_num_opcodes
);
3560 while (i
< bfd_mips16_num_opcodes
)
3562 const char *name
= mips16_opcodes
[i
].name
;
3564 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3566 as_fatal (_("internal: can't hash `%s': %s"),
3567 mips16_opcodes
[i
].name
, retval
);
3570 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3572 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3574 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3575 mips16_nop_insn
.fixed_p
= 1;
3579 while (i
< bfd_mips16_num_opcodes
3580 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3583 micromips_op_hash
= hash_new ();
3584 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3585 bfd_micromips_num_opcodes
);
3588 while (i
< bfd_micromips_num_opcodes
)
3590 const char *name
= micromips_opcodes
[i
].name
;
3592 retval
= hash_insert (micromips_op_hash
, name
,
3593 (void *) µmips_opcodes
[i
]);
3595 as_fatal (_("internal: can't hash `%s': %s"),
3596 micromips_opcodes
[i
].name
, retval
);
3599 struct mips_cl_insn
*micromips_nop_insn
;
3601 if (!validate_micromips_insn (µmips_opcodes
[i
],
3602 µmips_operands
[i
]))
3605 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3607 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3608 micromips_nop_insn
= µmips_nop16_insn
;
3609 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3610 micromips_nop_insn
= µmips_nop32_insn
;
3614 if (micromips_nop_insn
->insn_mo
== NULL
3615 && strcmp (name
, "nop") == 0)
3617 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3618 micromips_nop_insn
->fixed_p
= 1;
3622 while (++i
< bfd_micromips_num_opcodes
3623 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3627 as_fatal (_("broken assembler, no assembly attempted"));
3629 /* We add all the general register names to the symbol table. This
3630 helps us detect invalid uses of them. */
3631 for (i
= 0; reg_names
[i
].name
; i
++)
3632 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3633 reg_names
[i
].num
, /* & RNUM_MASK, */
3634 &zero_address_frag
));
3636 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3637 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3638 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3639 &zero_address_frag
));
3641 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3642 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3643 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3644 &zero_address_frag
));
3646 for (i
= 0; i
< 32; i
++)
3650 /* R5900 VU0 floating-point register. */
3651 sprintf (regname
, "$vf%d", i
);
3652 symbol_table_insert (symbol_new (regname
, reg_section
,
3653 RTYPE_VF
| i
, &zero_address_frag
));
3655 /* R5900 VU0 integer register. */
3656 sprintf (regname
, "$vi%d", i
);
3657 symbol_table_insert (symbol_new (regname
, reg_section
,
3658 RTYPE_VI
| i
, &zero_address_frag
));
3661 sprintf (regname
, "$w%d", i
);
3662 symbol_table_insert (symbol_new (regname
, reg_section
,
3663 RTYPE_MSA
| i
, &zero_address_frag
));
3666 obstack_init (&mips_operand_tokens
);
3668 mips_no_prev_insn ();
3671 mips_cprmask
[0] = 0;
3672 mips_cprmask
[1] = 0;
3673 mips_cprmask
[2] = 0;
3674 mips_cprmask
[3] = 0;
3676 /* set the default alignment for the text section (2**2) */
3677 record_alignment (text_section
, 2);
3679 bfd_set_gp_size (stdoutput
, g_switch_value
);
3681 /* On a native system other than VxWorks, sections must be aligned
3682 to 16 byte boundaries. When configured for an embedded ELF
3683 target, we don't bother. */
3684 if (strncmp (TARGET_OS
, "elf", 3) != 0
3685 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3687 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3688 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3689 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3692 /* Create a .reginfo section for register masks and a .mdebug
3693 section for debugging information. */
3701 subseg
= now_subseg
;
3703 /* The ABI says this section should be loaded so that the
3704 running program can access it. However, we don't load it
3705 if we are configured for an embedded target */
3706 flags
= SEC_READONLY
| SEC_DATA
;
3707 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3708 flags
|= SEC_ALLOC
| SEC_LOAD
;
3710 if (mips_abi
!= N64_ABI
)
3712 sec
= subseg_new (".reginfo", (subsegT
) 0);
3714 bfd_set_section_flags (stdoutput
, sec
, flags
);
3715 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3717 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3721 /* The 64-bit ABI uses a .MIPS.options section rather than
3722 .reginfo section. */
3723 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3724 bfd_set_section_flags (stdoutput
, sec
, flags
);
3725 bfd_set_section_alignment (stdoutput
, sec
, 3);
3727 /* Set up the option header. */
3729 Elf_Internal_Options opthdr
;
3732 opthdr
.kind
= ODK_REGINFO
;
3733 opthdr
.size
= (sizeof (Elf_External_Options
)
3734 + sizeof (Elf64_External_RegInfo
));
3737 f
= frag_more (sizeof (Elf_External_Options
));
3738 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3739 (Elf_External_Options
*) f
);
3741 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3745 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3746 bfd_set_section_flags (stdoutput
, sec
,
3747 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3748 bfd_set_section_alignment (stdoutput
, sec
, 3);
3749 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3751 if (ECOFF_DEBUGGING
)
3753 sec
= subseg_new (".mdebug", (subsegT
) 0);
3754 (void) bfd_set_section_flags (stdoutput
, sec
,
3755 SEC_HAS_CONTENTS
| SEC_READONLY
);
3756 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3758 else if (mips_flag_pdr
)
3760 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3761 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3762 SEC_READONLY
| SEC_RELOC
3764 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3767 subseg_set (seg
, subseg
);
3770 if (mips_fix_vr4120
)
3771 init_vr4120_conflicts ();
3775 fpabi_incompatible_with (int fpabi
, const char *what
)
3777 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3778 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3782 fpabi_requires (int fpabi
, const char *what
)
3784 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3785 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3788 /* Check -mabi and register sizes against the specified FP ABI. */
3790 check_fpabi (int fpabi
)
3794 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3795 if (file_mips_opts
.soft_float
)
3796 fpabi_incompatible_with (fpabi
, "softfloat");
3797 else if (file_mips_opts
.single_float
)
3798 fpabi_incompatible_with (fpabi
, "singlefloat");
3799 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3800 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3801 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3802 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3805 case Val_GNU_MIPS_ABI_FP_XX
:
3806 if (mips_abi
!= O32_ABI
)
3807 fpabi_requires (fpabi
, "-mabi=32");
3808 else if (file_mips_opts
.soft_float
)
3809 fpabi_incompatible_with (fpabi
, "softfloat");
3810 else if (file_mips_opts
.single_float
)
3811 fpabi_incompatible_with (fpabi
, "singlefloat");
3812 else if (file_mips_opts
.fp
!= 0)
3813 fpabi_requires (fpabi
, "fp=xx");
3816 case Val_GNU_MIPS_ABI_FP_64A
:
3817 case Val_GNU_MIPS_ABI_FP_64
:
3818 if (mips_abi
!= O32_ABI
)
3819 fpabi_requires (fpabi
, "-mabi=32");
3820 else if (file_mips_opts
.soft_float
)
3821 fpabi_incompatible_with (fpabi
, "softfloat");
3822 else if (file_mips_opts
.single_float
)
3823 fpabi_incompatible_with (fpabi
, "singlefloat");
3824 else if (file_mips_opts
.fp
!= 64)
3825 fpabi_requires (fpabi
, "fp=64");
3826 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3827 fpabi_incompatible_with (fpabi
, "nooddspreg");
3828 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3829 fpabi_requires (fpabi
, "nooddspreg");
3832 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3833 if (file_mips_opts
.soft_float
)
3834 fpabi_incompatible_with (fpabi
, "softfloat");
3835 else if (!file_mips_opts
.single_float
)
3836 fpabi_requires (fpabi
, "singlefloat");
3839 case Val_GNU_MIPS_ABI_FP_SOFT
:
3840 if (!file_mips_opts
.soft_float
)
3841 fpabi_requires (fpabi
, "softfloat");
3844 case Val_GNU_MIPS_ABI_FP_OLD_64
:
3845 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
3846 Tag_GNU_MIPS_ABI_FP
, fpabi
);
3849 case Val_GNU_MIPS_ABI_FP_NAN2008
:
3850 /* Silently ignore compatibility value. */
3854 as_warn (_(".gnu_attribute %d,%d is not a recognized"
3855 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
3860 /* Perform consistency checks on the current options. */
3863 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
3865 /* Check the size of integer registers agrees with the ABI and ISA. */
3866 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
3867 as_bad (_("`gp=64' used with a 32-bit processor"));
3869 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3870 as_bad (_("`gp=32' used with a 64-bit ABI"));
3872 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
3873 as_bad (_("`gp=64' used with a 32-bit ABI"));
3875 /* Check the size of the float registers agrees with the ABI and ISA. */
3879 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
3880 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
3881 else if (opts
->single_float
== 1)
3882 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
3885 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
3886 as_bad (_("`fp=64' used with a 32-bit fpu"));
3888 && ABI_NEEDS_32BIT_REGS (mips_abi
)
3889 && !ISA_HAS_MXHC1 (opts
->isa
))
3890 as_warn (_("`fp=64' used with a 32-bit ABI"));
3894 && ABI_NEEDS_64BIT_REGS (mips_abi
))
3895 as_warn (_("`fp=32' used with a 64-bit ABI"));
3896 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
3897 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
3900 as_bad (_("Unknown size of floating point registers"));
3904 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
3905 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
3907 if (opts
->micromips
== 1 && opts
->mips16
== 1)
3908 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
3909 else if (ISA_IS_R6 (opts
->isa
)
3910 && (opts
->micromips
== 1
3911 || opts
->mips16
== 1))
3912 as_fatal (_("`%s' cannot be used with `%s'"),
3913 opts
->micromips
? "micromips" : "mips16",
3914 mips_cpu_info_from_isa (opts
->isa
)->name
);
3916 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
3917 as_fatal (_("branch relaxation is not supported in `%s'"),
3918 mips_cpu_info_from_isa (opts
->isa
)->name
);
3921 /* Perform consistency checks on the module level options exactly once.
3922 This is a deferred check that happens:
3923 at the first .set directive
3924 or, at the first pseudo op that generates code (inc .dc.a)
3925 or, at the first instruction
3929 file_mips_check_options (void)
3931 const struct mips_cpu_info
*arch_info
= 0;
3933 if (file_mips_opts_checked
)
3936 /* The following code determines the register size.
3937 Similar code was added to GCC 3.3 (see override_options() in
3938 config/mips/mips.c). The GAS and GCC code should be kept in sync
3939 as much as possible. */
3941 if (file_mips_opts
.gp
< 0)
3943 /* Infer the integer register size from the ABI and processor.
3944 Restrict ourselves to 32-bit registers if that's all the
3945 processor has, or if the ABI cannot handle 64-bit registers. */
3946 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
3947 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
3951 if (file_mips_opts
.fp
< 0)
3953 /* No user specified float register size.
3954 ??? GAS treats single-float processors as though they had 64-bit
3955 float registers (although it complains when double-precision
3956 instructions are used). As things stand, saying they have 32-bit
3957 registers would lead to spurious "register must be even" messages.
3958 So here we assume float registers are never smaller than the
3960 if (file_mips_opts
.gp
== 64)
3961 /* 64-bit integer registers implies 64-bit float registers. */
3962 file_mips_opts
.fp
= 64;
3963 else if ((file_mips_opts
.ase
& FP64_ASES
)
3964 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
3965 /* Handle ASEs that require 64-bit float registers, if possible. */
3966 file_mips_opts
.fp
= 64;
3967 else if (ISA_IS_R6 (mips_opts
.isa
))
3968 /* R6 implies 64-bit float registers. */
3969 file_mips_opts
.fp
= 64;
3971 /* 32-bit float registers. */
3972 file_mips_opts
.fp
= 32;
3975 arch_info
= mips_cpu_info_from_arch (file_mips_opts
.arch
);
3977 /* Disable operations on odd-numbered floating-point registers by default
3978 when using the FPXX ABI. */
3979 if (file_mips_opts
.oddspreg
< 0)
3981 if (file_mips_opts
.fp
== 0)
3982 file_mips_opts
.oddspreg
= 0;
3984 file_mips_opts
.oddspreg
= 1;
3987 /* End of GCC-shared inference code. */
3989 /* This flag is set when we have a 64-bit capable CPU but use only
3990 32-bit wide registers. Note that EABI does not use it. */
3991 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
3992 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
3993 || mips_abi
== O32_ABI
))
3996 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
3997 as_bad (_("trap exception not supported at ISA 1"));
3999 /* If the selected architecture includes support for ASEs, enable
4000 generation of code for them. */
4001 if (file_mips_opts
.mips16
== -1)
4002 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4003 if (file_mips_opts
.micromips
== -1)
4004 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4007 if (mips_nan2008
== -1)
4008 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4009 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4010 as_fatal (_("`%s' does not support legacy NaN"),
4011 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4013 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4014 being selected implicitly. */
4015 if (file_mips_opts
.fp
!= 64)
4016 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4018 /* If the user didn't explicitly select or deselect a particular ASE,
4019 use the default setting for the CPU. */
4020 file_mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
4022 /* Set up the current options. These may change throughout assembly. */
4023 mips_opts
= file_mips_opts
;
4025 mips_check_isa_supports_ases ();
4026 mips_check_options (&file_mips_opts
, TRUE
);
4027 file_mips_opts_checked
= TRUE
;
4029 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4030 as_warn (_("could not set architecture and machine"));
4034 md_assemble (char *str
)
4036 struct mips_cl_insn insn
;
4037 bfd_reloc_code_real_type unused_reloc
[3]
4038 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4040 file_mips_check_options ();
4042 imm_expr
.X_op
= O_absent
;
4043 offset_expr
.X_op
= O_absent
;
4044 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4045 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4046 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4048 mips_mark_labels ();
4049 mips_assembling_insn
= TRUE
;
4050 clear_insn_error ();
4052 if (mips_opts
.mips16
)
4053 mips16_ip (str
, &insn
);
4056 mips_ip (str
, &insn
);
4057 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4058 str
, insn
.insn_opcode
));
4062 report_insn_error (str
);
4063 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4066 if (mips_opts
.mips16
)
4067 mips16_macro (&insn
);
4074 if (offset_expr
.X_op
!= O_absent
)
4075 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4077 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4080 mips_assembling_insn
= FALSE
;
4083 /* Convenience functions for abstracting away the differences between
4084 MIPS16 and non-MIPS16 relocations. */
4086 static inline bfd_boolean
4087 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4091 case BFD_RELOC_MIPS16_JMP
:
4092 case BFD_RELOC_MIPS16_GPREL
:
4093 case BFD_RELOC_MIPS16_GOT16
:
4094 case BFD_RELOC_MIPS16_CALL16
:
4095 case BFD_RELOC_MIPS16_HI16_S
:
4096 case BFD_RELOC_MIPS16_HI16
:
4097 case BFD_RELOC_MIPS16_LO16
:
4098 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4106 static inline bfd_boolean
4107 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4111 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4112 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4113 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4114 case BFD_RELOC_MICROMIPS_GPREL16
:
4115 case BFD_RELOC_MICROMIPS_JMP
:
4116 case BFD_RELOC_MICROMIPS_HI16
:
4117 case BFD_RELOC_MICROMIPS_HI16_S
:
4118 case BFD_RELOC_MICROMIPS_LO16
:
4119 case BFD_RELOC_MICROMIPS_LITERAL
:
4120 case BFD_RELOC_MICROMIPS_GOT16
:
4121 case BFD_RELOC_MICROMIPS_CALL16
:
4122 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4123 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4124 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4125 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4126 case BFD_RELOC_MICROMIPS_SUB
:
4127 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4128 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4129 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4130 case BFD_RELOC_MICROMIPS_HIGHEST
:
4131 case BFD_RELOC_MICROMIPS_HIGHER
:
4132 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4133 case BFD_RELOC_MICROMIPS_JALR
:
4141 static inline bfd_boolean
4142 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4144 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4147 static inline bfd_boolean
4148 b_reloc_p (bfd_reloc_code_real_type reloc
)
4150 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4151 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4152 || reloc
== BFD_RELOC_16_PCREL_S2
4153 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4154 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4155 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4156 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4159 static inline bfd_boolean
4160 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4162 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4163 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4166 static inline bfd_boolean
4167 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4169 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4170 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4173 static inline bfd_boolean
4174 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4176 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4177 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4180 static inline bfd_boolean
4181 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4183 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4186 static inline bfd_boolean
4187 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4189 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4190 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4193 /* Return true if RELOC is a PC-relative relocation that does not have
4194 full address range. */
4196 static inline bfd_boolean
4197 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4201 case BFD_RELOC_16_PCREL_S2
:
4202 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4203 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4204 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4205 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4206 case BFD_RELOC_MIPS_21_PCREL_S2
:
4207 case BFD_RELOC_MIPS_26_PCREL_S2
:
4208 case BFD_RELOC_MIPS_18_PCREL_S3
:
4209 case BFD_RELOC_MIPS_19_PCREL_S2
:
4212 case BFD_RELOC_32_PCREL
:
4213 case BFD_RELOC_HI16_S_PCREL
:
4214 case BFD_RELOC_LO16_PCREL
:
4215 return HAVE_64BIT_ADDRESSES
;
4222 /* Return true if the given relocation might need a matching %lo().
4223 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4224 need a matching %lo() when applied to local symbols. */
4226 static inline bfd_boolean
4227 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4229 return (HAVE_IN_PLACE_ADDENDS
4230 && (hi16_reloc_p (reloc
)
4231 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4232 all GOT16 relocations evaluate to "G". */
4233 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4236 /* Return the type of %lo() reloc needed by RELOC, given that
4237 reloc_needs_lo_p. */
4239 static inline bfd_reloc_code_real_type
4240 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4242 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4243 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4247 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4250 static inline bfd_boolean
4251 fixup_has_matching_lo_p (fixS
*fixp
)
4253 return (fixp
->fx_next
!= NULL
4254 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4255 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4256 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4259 /* Move all labels in LABELS to the current insertion point. TEXT_P
4260 says whether the labels refer to text or data. */
4263 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4265 struct insn_label_list
*l
;
4268 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4270 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4271 symbol_set_frag (l
->label
, frag_now
);
4272 val
= (valueT
) frag_now_fix ();
4273 /* MIPS16/microMIPS text labels are stored as odd. */
4274 if (text_p
&& HAVE_CODE_COMPRESSION
)
4276 S_SET_VALUE (l
->label
, val
);
4280 /* Move all labels in insn_labels to the current insertion point
4281 and treat them as text labels. */
4284 mips_move_text_labels (void)
4286 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4289 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4292 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4294 bfd_boolean linkonce
= FALSE
;
4295 segT symseg
= S_GET_SEGMENT (sym
);
4297 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4299 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
4301 /* The GNU toolchain uses an extension for ELF: a section
4302 beginning with the magic string .gnu.linkonce is a
4303 linkonce section. */
4304 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4305 sizeof ".gnu.linkonce" - 1) == 0)
4311 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4312 linker to handle them specially, such as generating jalx instructions
4313 when needed. We also make them odd for the duration of the assembly,
4314 in order to generate the right sort of code. We will make them even
4315 in the adjust_symtab routine, while leaving them marked. This is
4316 convenient for the debugger and the disassembler. The linker knows
4317 to make them odd again. */
4320 mips_compressed_mark_label (symbolS
*label
)
4322 gas_assert (HAVE_CODE_COMPRESSION
);
4324 if (mips_opts
.mips16
)
4325 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4327 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4328 if ((S_GET_VALUE (label
) & 1) == 0
4329 /* Don't adjust the address if the label is global or weak, or
4330 in a link-once section, since we'll be emitting symbol reloc
4331 references to it which will be patched up by the linker, and
4332 the final value of the symbol may or may not be MIPS16/microMIPS. */
4333 && !S_IS_WEAK (label
)
4334 && !S_IS_EXTERNAL (label
)
4335 && !s_is_linkonce (label
, now_seg
))
4336 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4339 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4342 mips_compressed_mark_labels (void)
4344 struct insn_label_list
*l
;
4346 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4347 mips_compressed_mark_label (l
->label
);
4350 /* End the current frag. Make it a variant frag and record the
4354 relax_close_frag (void)
4356 mips_macro_warning
.first_frag
= frag_now
;
4357 frag_var (rs_machine_dependent
, 0, 0,
4358 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4359 mips_pic
!= NO_PIC
),
4360 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4362 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4363 mips_relax
.first_fixup
= 0;
4366 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4367 See the comment above RELAX_ENCODE for more details. */
4370 relax_start (symbolS
*symbol
)
4372 gas_assert (mips_relax
.sequence
== 0);
4373 mips_relax
.sequence
= 1;
4374 mips_relax
.symbol
= symbol
;
4377 /* Start generating the second version of a relaxable sequence.
4378 See the comment above RELAX_ENCODE for more details. */
4383 gas_assert (mips_relax
.sequence
== 1);
4384 mips_relax
.sequence
= 2;
4387 /* End the current relaxable sequence. */
4392 gas_assert (mips_relax
.sequence
== 2);
4393 relax_close_frag ();
4394 mips_relax
.sequence
= 0;
4397 /* Return true if IP is a delayed branch or jump. */
4399 static inline bfd_boolean
4400 delayed_branch_p (const struct mips_cl_insn
*ip
)
4402 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4403 | INSN_COND_BRANCH_DELAY
4404 | INSN_COND_BRANCH_LIKELY
)) != 0;
4407 /* Return true if IP is a compact branch or jump. */
4409 static inline bfd_boolean
4410 compact_branch_p (const struct mips_cl_insn
*ip
)
4412 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4413 | INSN2_COND_BRANCH
)) != 0;
4416 /* Return true if IP is an unconditional branch or jump. */
4418 static inline bfd_boolean
4419 uncond_branch_p (const struct mips_cl_insn
*ip
)
4421 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4422 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4425 /* Return true if IP is a branch-likely instruction. */
4427 static inline bfd_boolean
4428 branch_likely_p (const struct mips_cl_insn
*ip
)
4430 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4433 /* Return the type of nop that should be used to fill the delay slot
4434 of delayed branch IP. */
4436 static struct mips_cl_insn
*
4437 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4439 if (mips_opts
.micromips
4440 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4441 return µmips_nop32_insn
;
4445 /* Return a mask that has bit N set if OPCODE reads the register(s)
4449 insn_read_mask (const struct mips_opcode
*opcode
)
4451 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4454 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4458 insn_write_mask (const struct mips_opcode
*opcode
)
4460 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4463 /* Return a mask of the registers specified by operand OPERAND of INSN.
4464 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4468 operand_reg_mask (const struct mips_cl_insn
*insn
,
4469 const struct mips_operand
*operand
,
4470 unsigned int type_mask
)
4472 unsigned int uval
, vsel
;
4474 switch (operand
->type
)
4481 case OP_ADDIUSP_INT
:
4482 case OP_ENTRY_EXIT_LIST
:
4483 case OP_REPEAT_DEST_REG
:
4484 case OP_REPEAT_PREV_REG
:
4487 case OP_VU0_MATCH_SUFFIX
:
4492 case OP_OPTIONAL_REG
:
4494 const struct mips_reg_operand
*reg_op
;
4496 reg_op
= (const struct mips_reg_operand
*) operand
;
4497 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4499 uval
= insn_extract_operand (insn
, operand
);
4500 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4505 const struct mips_reg_pair_operand
*pair_op
;
4507 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4508 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4510 uval
= insn_extract_operand (insn
, operand
);
4511 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4514 case OP_CLO_CLZ_DEST
:
4515 if (!(type_mask
& (1 << OP_REG_GP
)))
4517 uval
= insn_extract_operand (insn
, operand
);
4518 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4521 if (!(type_mask
& (1 << OP_REG_GP
)))
4523 uval
= insn_extract_operand (insn
, operand
);
4524 gas_assert ((uval
& 31) == (uval
>> 5));
4525 return 1 << (uval
& 31);
4528 case OP_NON_ZERO_REG
:
4529 if (!(type_mask
& (1 << OP_REG_GP
)))
4531 uval
= insn_extract_operand (insn
, operand
);
4532 return 1 << (uval
& 31);
4534 case OP_LWM_SWM_LIST
:
4537 case OP_SAVE_RESTORE_LIST
:
4540 case OP_MDMX_IMM_REG
:
4541 if (!(type_mask
& (1 << OP_REG_VEC
)))
4543 uval
= insn_extract_operand (insn
, operand
);
4545 if ((vsel
& 0x18) == 0x18)
4547 return 1 << (uval
& 31);
4550 if (!(type_mask
& (1 << OP_REG_GP
)))
4552 return 1 << insn_extract_operand (insn
, operand
);
4557 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4558 where bit N of OPNO_MASK is set if operand N should be included.
4559 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4563 insn_reg_mask (const struct mips_cl_insn
*insn
,
4564 unsigned int type_mask
, unsigned int opno_mask
)
4566 unsigned int opno
, reg_mask
;
4570 while (opno_mask
!= 0)
4573 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4580 /* Return the mask of core registers that IP reads. */
4583 gpr_read_mask (const struct mips_cl_insn
*ip
)
4585 unsigned long pinfo
, pinfo2
;
4588 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4589 pinfo
= ip
->insn_mo
->pinfo
;
4590 pinfo2
= ip
->insn_mo
->pinfo2
;
4591 if (pinfo
& INSN_UDI
)
4593 /* UDI instructions have traditionally been assumed to read RS
4595 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4596 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4598 if (pinfo
& INSN_READ_GPR_24
)
4600 if (pinfo2
& INSN2_READ_GPR_16
)
4602 if (pinfo2
& INSN2_READ_SP
)
4604 if (pinfo2
& INSN2_READ_GPR_31
)
4606 /* Don't include register 0. */
4610 /* Return the mask of core registers that IP writes. */
4613 gpr_write_mask (const struct mips_cl_insn
*ip
)
4615 unsigned long pinfo
, pinfo2
;
4618 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4619 pinfo
= ip
->insn_mo
->pinfo
;
4620 pinfo2
= ip
->insn_mo
->pinfo2
;
4621 if (pinfo
& INSN_WRITE_GPR_24
)
4623 if (pinfo
& INSN_WRITE_GPR_31
)
4625 if (pinfo
& INSN_UDI
)
4626 /* UDI instructions have traditionally been assumed to write to RD. */
4627 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4628 if (pinfo2
& INSN2_WRITE_SP
)
4630 /* Don't include register 0. */
4634 /* Return the mask of floating-point registers that IP reads. */
4637 fpr_read_mask (const struct mips_cl_insn
*ip
)
4639 unsigned long pinfo
;
4642 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4643 | (1 << OP_REG_MSA
)),
4644 insn_read_mask (ip
->insn_mo
));
4645 pinfo
= ip
->insn_mo
->pinfo
;
4646 /* Conservatively treat all operands to an FP_D instruction are doubles.
4647 (This is overly pessimistic for things like cvt.d.s.) */
4648 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4653 /* Return the mask of floating-point registers that IP writes. */
4656 fpr_write_mask (const struct mips_cl_insn
*ip
)
4658 unsigned long pinfo
;
4661 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4662 | (1 << OP_REG_MSA
)),
4663 insn_write_mask (ip
->insn_mo
));
4664 pinfo
= ip
->insn_mo
->pinfo
;
4665 /* Conservatively treat all operands to an FP_D instruction are doubles.
4666 (This is overly pessimistic for things like cvt.s.d.) */
4667 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4672 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4673 Check whether that is allowed. */
4676 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4678 const char *s
= insn
->name
;
4679 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4681 && mips_opts
.oddspreg
;
4683 if (insn
->pinfo
== INSN_MACRO
)
4684 /* Let a macro pass, we'll catch it later when it is expanded. */
4687 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4688 otherwise it depends on oddspreg. */
4689 if ((insn
->pinfo
& FP_S
)
4690 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4691 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4692 return FPR_SIZE
== 32 || oddspreg
;
4694 /* Allow odd registers for single-precision ops and double-precision if the
4695 floating-point registers are 64-bit wide. */
4696 switch (insn
->pinfo
& (FP_S
| FP_D
))
4702 return FPR_SIZE
== 64;
4707 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4708 s
= strchr (insn
->name
, '.');
4709 if (s
!= NULL
&& opnum
== 2)
4710 s
= strchr (s
+ 1, '.');
4711 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4714 return FPR_SIZE
== 64;
4717 /* Information about an instruction argument that we're trying to match. */
4718 struct mips_arg_info
4720 /* The instruction so far. */
4721 struct mips_cl_insn
*insn
;
4723 /* The first unconsumed operand token. */
4724 struct mips_operand_token
*token
;
4726 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4729 /* The 1-based argument number, for error reporting. This does not
4730 count elided optional registers, etc.. */
4733 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4734 unsigned int last_regno
;
4736 /* If the first operand was an OP_REG, this is the register that it
4737 specified, otherwise it is ILLEGAL_REG. */
4738 unsigned int dest_regno
;
4740 /* The value of the last OP_INT operand. Only used for OP_MSB,
4741 where it gives the lsb position. */
4742 unsigned int last_op_int
;
4744 /* If true, match routines should assume that no later instruction
4745 alternative matches and should therefore be as accommodating as
4746 possible. Match routines should not report errors if something
4747 is only invalid for !LAX_MATCH. */
4748 bfd_boolean lax_match
;
4750 /* True if a reference to the current AT register was seen. */
4751 bfd_boolean seen_at
;
4754 /* Record that the argument is out of range. */
4757 match_out_of_range (struct mips_arg_info
*arg
)
4759 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4762 /* Record that the argument isn't constant but needs to be. */
4765 match_not_constant (struct mips_arg_info
*arg
)
4767 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4771 /* Try to match an OT_CHAR token for character CH. Consume the token
4772 and return true on success, otherwise return false. */
4775 match_char (struct mips_arg_info
*arg
, char ch
)
4777 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4787 /* Try to get an expression from the next tokens in ARG. Consume the
4788 tokens and return true on success, storing the expression value in
4789 VALUE and relocation types in R. */
4792 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4793 bfd_reloc_code_real_type
*r
)
4795 /* If the next token is a '(' that was parsed as being part of a base
4796 expression, assume we have an elided offset. The later match will fail
4797 if this turns out to be wrong. */
4798 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4800 value
->X_op
= O_constant
;
4801 value
->X_add_number
= 0;
4802 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4806 /* Reject register-based expressions such as "0+$2" and "(($2))".
4807 For plain registers the default error seems more appropriate. */
4808 if (arg
->token
->type
== OT_INTEGER
4809 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4811 set_insn_error (arg
->argnum
, _("register value used as expression"));
4815 if (arg
->token
->type
== OT_INTEGER
)
4817 *value
= arg
->token
->u
.integer
.value
;
4818 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4824 (arg
->argnum
, _("operand %d must be an immediate expression"),
4829 /* Try to get a constant expression from the next tokens in ARG. Consume
4830 the tokens and return return true on success, storing the constant value
4831 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4835 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4838 bfd_reloc_code_real_type r
[3];
4840 if (!match_expression (arg
, &ex
, r
))
4843 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4844 *value
= ex
.X_add_number
;
4847 match_not_constant (arg
);
4853 /* Return the RTYPE_* flags for a register operand of type TYPE that
4854 appears in instruction OPCODE. */
4857 convert_reg_type (const struct mips_opcode
*opcode
,
4858 enum mips_reg_operand_type type
)
4863 return RTYPE_NUM
| RTYPE_GP
;
4866 /* Allow vector register names for MDMX if the instruction is a 64-bit
4867 FPR load, store or move (including moves to and from GPRs). */
4868 if ((mips_opts
.ase
& ASE_MDMX
)
4869 && (opcode
->pinfo
& FP_D
)
4870 && (opcode
->pinfo
& (INSN_COPROC_MOVE
4871 | INSN_COPROC_MEMORY_DELAY
4874 | INSN_STORE_MEMORY
)))
4875 return RTYPE_FPU
| RTYPE_VEC
;
4879 if (opcode
->pinfo
& (FP_D
| FP_S
))
4880 return RTYPE_CCC
| RTYPE_FCC
;
4884 if (opcode
->membership
& INSN_5400
)
4886 return RTYPE_FPU
| RTYPE_VEC
;
4892 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4893 return RTYPE_NUM
| RTYPE_CP0
;
4900 return RTYPE_NUM
| RTYPE_VI
;
4903 return RTYPE_NUM
| RTYPE_VF
;
4905 case OP_REG_R5900_I
:
4906 return RTYPE_R5900_I
;
4908 case OP_REG_R5900_Q
:
4909 return RTYPE_R5900_Q
;
4911 case OP_REG_R5900_R
:
4912 return RTYPE_R5900_R
;
4914 case OP_REG_R5900_ACC
:
4915 return RTYPE_R5900_ACC
;
4920 case OP_REG_MSA_CTRL
:
4926 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4929 check_regno (struct mips_arg_info
*arg
,
4930 enum mips_reg_operand_type type
, unsigned int regno
)
4932 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4933 arg
->seen_at
= TRUE
;
4935 if (type
== OP_REG_FP
4937 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4939 /* This was a warning prior to introducing O32 FPXX and FP64 support
4940 so maintain a warning for FP32 but raise an error for the new
4943 as_warn (_("float register should be even, was %d"), regno
);
4945 as_bad (_("float register should be even, was %d"), regno
);
4948 if (type
== OP_REG_CCC
)
4953 name
= arg
->insn
->insn_mo
->name
;
4954 length
= strlen (name
);
4955 if ((regno
& 1) != 0
4956 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4957 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4958 as_warn (_("condition code register should be even for %s, was %d"),
4961 if ((regno
& 3) != 0
4962 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4963 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4968 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4969 a register of type TYPE. Return true on success, storing the register
4970 number in *REGNO and warning about any dubious uses. */
4973 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4974 unsigned int symval
, unsigned int *regno
)
4976 if (type
== OP_REG_VEC
)
4977 symval
= mips_prefer_vec_regno (symval
);
4978 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4981 *regno
= symval
& RNUM_MASK
;
4982 check_regno (arg
, type
, *regno
);
4986 /* Try to interpret the next token in ARG as a register of type TYPE.
4987 Consume the token and return true on success, storing the register
4988 number in *REGNO. Return false on failure. */
4991 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4992 unsigned int *regno
)
4994 if (arg
->token
->type
== OT_REG
4995 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5003 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5004 Consume the token and return true on success, storing the register numbers
5005 in *REGNO1 and *REGNO2. Return false on failure. */
5008 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5009 unsigned int *regno1
, unsigned int *regno2
)
5011 if (match_reg (arg
, type
, regno1
))
5016 if (arg
->token
->type
== OT_REG_RANGE
5017 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5018 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5019 && *regno1
<= *regno2
)
5027 /* OP_INT matcher. */
5030 match_int_operand (struct mips_arg_info
*arg
,
5031 const struct mips_operand
*operand_base
)
5033 const struct mips_int_operand
*operand
;
5035 int min_val
, max_val
, factor
;
5038 operand
= (const struct mips_int_operand
*) operand_base
;
5039 factor
= 1 << operand
->shift
;
5040 min_val
= mips_int_operand_min (operand
);
5041 max_val
= mips_int_operand_max (operand
);
5043 if (operand_base
->lsb
== 0
5044 && operand_base
->size
== 16
5045 && operand
->shift
== 0
5046 && operand
->bias
== 0
5047 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5049 /* The operand can be relocated. */
5050 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5053 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5054 /* Relocation operators were used. Accept the argument and
5055 leave the relocation value in offset_expr and offset_relocs
5056 for the caller to process. */
5059 if (offset_expr
.X_op
!= O_constant
)
5061 /* Accept non-constant operands if no later alternative matches,
5062 leaving it for the caller to process. */
5063 if (!arg
->lax_match
)
5065 offset_reloc
[0] = BFD_RELOC_LO16
;
5069 /* Clear the global state; we're going to install the operand
5071 sval
= offset_expr
.X_add_number
;
5072 offset_expr
.X_op
= O_absent
;
5074 /* For compatibility with older assemblers, we accept
5075 0x8000-0xffff as signed 16-bit numbers when only
5076 signed numbers are allowed. */
5079 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5080 if (!arg
->lax_match
&& sval
<= max_val
)
5086 if (!match_const_int (arg
, &sval
))
5090 arg
->last_op_int
= sval
;
5092 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5094 match_out_of_range (arg
);
5098 uval
= (unsigned int) sval
>> operand
->shift
;
5099 uval
-= operand
->bias
;
5101 /* Handle -mfix-cn63xxp1. */
5103 && mips_fix_cn63xxp1
5104 && !mips_opts
.micromips
5105 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5120 /* The rest must be changed to 28. */
5125 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5129 /* OP_MAPPED_INT matcher. */
5132 match_mapped_int_operand (struct mips_arg_info
*arg
,
5133 const struct mips_operand
*operand_base
)
5135 const struct mips_mapped_int_operand
*operand
;
5136 unsigned int uval
, num_vals
;
5139 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5140 if (!match_const_int (arg
, &sval
))
5143 num_vals
= 1 << operand_base
->size
;
5144 for (uval
= 0; uval
< num_vals
; uval
++)
5145 if (operand
->int_map
[uval
] == sval
)
5147 if (uval
== num_vals
)
5149 match_out_of_range (arg
);
5153 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5157 /* OP_MSB matcher. */
5160 match_msb_operand (struct mips_arg_info
*arg
,
5161 const struct mips_operand
*operand_base
)
5163 const struct mips_msb_operand
*operand
;
5164 int min_val
, max_val
, max_high
;
5165 offsetT size
, sval
, high
;
5167 operand
= (const struct mips_msb_operand
*) operand_base
;
5168 min_val
= operand
->bias
;
5169 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5170 max_high
= operand
->opsize
;
5172 if (!match_const_int (arg
, &size
))
5175 high
= size
+ arg
->last_op_int
;
5176 sval
= operand
->add_lsb
? high
: size
;
5178 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5180 match_out_of_range (arg
);
5183 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5187 /* OP_REG matcher. */
5190 match_reg_operand (struct mips_arg_info
*arg
,
5191 const struct mips_operand
*operand_base
)
5193 const struct mips_reg_operand
*operand
;
5194 unsigned int regno
, uval
, num_vals
;
5196 operand
= (const struct mips_reg_operand
*) operand_base
;
5197 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5200 if (operand
->reg_map
)
5202 num_vals
= 1 << operand
->root
.size
;
5203 for (uval
= 0; uval
< num_vals
; uval
++)
5204 if (operand
->reg_map
[uval
] == regno
)
5206 if (num_vals
== uval
)
5212 arg
->last_regno
= regno
;
5213 if (arg
->opnum
== 1)
5214 arg
->dest_regno
= regno
;
5215 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5219 /* OP_REG_PAIR matcher. */
5222 match_reg_pair_operand (struct mips_arg_info
*arg
,
5223 const struct mips_operand
*operand_base
)
5225 const struct mips_reg_pair_operand
*operand
;
5226 unsigned int regno1
, regno2
, uval
, num_vals
;
5228 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5229 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5230 || !match_char (arg
, ',')
5231 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5234 num_vals
= 1 << operand_base
->size
;
5235 for (uval
= 0; uval
< num_vals
; uval
++)
5236 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5238 if (uval
== num_vals
)
5241 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5245 /* OP_PCREL matcher. The caller chooses the relocation type. */
5248 match_pcrel_operand (struct mips_arg_info
*arg
)
5250 bfd_reloc_code_real_type r
[3];
5252 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5255 /* OP_PERF_REG matcher. */
5258 match_perf_reg_operand (struct mips_arg_info
*arg
,
5259 const struct mips_operand
*operand
)
5263 if (!match_const_int (arg
, &sval
))
5268 || (mips_opts
.arch
== CPU_R5900
5269 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5270 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5272 set_insn_error (arg
->argnum
, _("invalid performance register"));
5276 insn_insert_operand (arg
->insn
, operand
, sval
);
5280 /* OP_ADDIUSP matcher. */
5283 match_addiusp_operand (struct mips_arg_info
*arg
,
5284 const struct mips_operand
*operand
)
5289 if (!match_const_int (arg
, &sval
))
5294 match_out_of_range (arg
);
5299 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5301 match_out_of_range (arg
);
5305 uval
= (unsigned int) sval
;
5306 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5307 insn_insert_operand (arg
->insn
, operand
, uval
);
5311 /* OP_CLO_CLZ_DEST matcher. */
5314 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5315 const struct mips_operand
*operand
)
5319 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5322 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5326 /* OP_CHECK_PREV matcher. */
5329 match_check_prev_operand (struct mips_arg_info
*arg
,
5330 const struct mips_operand
*operand_base
)
5332 const struct mips_check_prev_operand
*operand
;
5335 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5337 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5340 if (!operand
->zero_ok
&& regno
== 0)
5343 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5344 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5345 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5347 arg
->last_regno
= regno
;
5348 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5355 /* OP_SAME_RS_RT matcher. */
5358 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5359 const struct mips_operand
*operand
)
5363 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5368 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5372 arg
->last_regno
= regno
;
5374 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5378 /* OP_LWM_SWM_LIST matcher. */
5381 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5382 const struct mips_operand
*operand
)
5384 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5385 struct mips_arg_info reset
;
5388 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5392 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5397 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5400 while (match_char (arg
, ',')
5401 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5404 if (operand
->size
== 2)
5406 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5412 and any permutations of these. */
5413 if ((reglist
& 0xfff1ffff) != 0x80010000)
5416 sregs
= (reglist
>> 17) & 7;
5421 /* The list must include at least one of ra and s0-sN,
5422 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5423 which are $23 and $30 respectively.) E.g.:
5431 and any permutations of these. */
5432 if ((reglist
& 0x3f00ffff) != 0)
5435 ra
= (reglist
>> 27) & 0x10;
5436 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5439 if ((sregs
& -sregs
) != sregs
)
5442 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5446 /* OP_ENTRY_EXIT_LIST matcher. */
5449 match_entry_exit_operand (struct mips_arg_info
*arg
,
5450 const struct mips_operand
*operand
)
5453 bfd_boolean is_exit
;
5455 /* The format is the same for both ENTRY and EXIT, but the constraints
5457 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5458 mask
= (is_exit
? 7 << 3 : 0);
5461 unsigned int regno1
, regno2
;
5462 bfd_boolean is_freg
;
5464 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5466 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5471 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5474 mask
|= (5 + regno2
) << 3;
5476 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5477 mask
|= (regno2
- 3) << 3;
5478 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5479 mask
|= (regno2
- 15) << 1;
5480 else if (regno1
== RA
&& regno2
== RA
)
5485 while (match_char (arg
, ','));
5487 insn_insert_operand (arg
->insn
, operand
, mask
);
5491 /* OP_SAVE_RESTORE_LIST matcher. */
5494 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5496 unsigned int opcode
, args
, statics
, sregs
;
5497 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5500 opcode
= arg
->insn
->insn_opcode
;
5502 num_frame_sizes
= 0;
5508 unsigned int regno1
, regno2
;
5510 if (arg
->token
->type
== OT_INTEGER
)
5512 /* Handle the frame size. */
5513 if (!match_const_int (arg
, &frame_size
))
5515 num_frame_sizes
+= 1;
5519 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5522 while (regno1
<= regno2
)
5524 if (regno1
>= 4 && regno1
<= 7)
5526 if (num_frame_sizes
== 0)
5528 args
|= 1 << (regno1
- 4);
5530 /* statics $a0-$a3 */
5531 statics
|= 1 << (regno1
- 4);
5533 else if (regno1
>= 16 && regno1
<= 23)
5535 sregs
|= 1 << (regno1
- 16);
5536 else if (regno1
== 30)
5539 else if (regno1
== 31)
5540 /* Add $ra to insn. */
5550 while (match_char (arg
, ','));
5552 /* Encode args/statics combination. */
5555 else if (args
== 0xf)
5556 /* All $a0-$a3 are args. */
5557 opcode
|= MIPS16_ALL_ARGS
<< 16;
5558 else if (statics
== 0xf)
5559 /* All $a0-$a3 are statics. */
5560 opcode
|= MIPS16_ALL_STATICS
<< 16;
5563 /* Count arg registers. */
5573 /* Count static registers. */
5575 while (statics
& 0x8)
5577 statics
= (statics
<< 1) & 0xf;
5583 /* Encode args/statics. */
5584 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5587 /* Encode $s0/$s1. */
5588 if (sregs
& (1 << 0)) /* $s0 */
5590 if (sregs
& (1 << 1)) /* $s1 */
5594 /* Encode $s2-$s8. */
5603 opcode
|= num_sregs
<< 24;
5605 /* Encode frame size. */
5606 if (num_frame_sizes
== 0)
5608 set_insn_error (arg
->argnum
, _("missing frame size"));
5611 if (num_frame_sizes
> 1)
5613 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5616 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5618 set_insn_error (arg
->argnum
, _("invalid frame size"));
5621 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5624 opcode
|= (((frame_size
& 0xf0) << 16)
5625 | (frame_size
& 0x0f));
5628 /* Finally build the instruction. */
5629 if ((opcode
>> 16) != 0 || frame_size
== 0)
5630 opcode
|= MIPS16_EXTEND
;
5631 arg
->insn
->insn_opcode
= opcode
;
5635 /* OP_MDMX_IMM_REG matcher. */
5638 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5639 const struct mips_operand
*operand
)
5641 unsigned int regno
, uval
;
5643 const struct mips_opcode
*opcode
;
5645 /* The mips_opcode records whether this is an octobyte or quadhalf
5646 instruction. Start out with that bit in place. */
5647 opcode
= arg
->insn
->insn_mo
;
5648 uval
= mips_extract_operand (operand
, opcode
->match
);
5649 is_qh
= (uval
!= 0);
5651 if (arg
->token
->type
== OT_REG
)
5653 if ((opcode
->membership
& INSN_5400
)
5654 && strcmp (opcode
->name
, "rzu.ob") == 0)
5656 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5661 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5665 /* Check whether this is a vector register or a broadcast of
5666 a single element. */
5667 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5669 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5671 set_insn_error (arg
->argnum
, _("invalid element selector"));
5674 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5679 /* A full vector. */
5680 if ((opcode
->membership
& INSN_5400
)
5681 && (strcmp (opcode
->name
, "sll.ob") == 0
5682 || strcmp (opcode
->name
, "srl.ob") == 0))
5684 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5690 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5692 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5700 if (!match_const_int (arg
, &sval
))
5702 if (sval
< 0 || sval
> 31)
5704 match_out_of_range (arg
);
5707 uval
|= (sval
& 31);
5709 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5711 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5713 insn_insert_operand (arg
->insn
, operand
, uval
);
5717 /* OP_IMM_INDEX matcher. */
5720 match_imm_index_operand (struct mips_arg_info
*arg
,
5721 const struct mips_operand
*operand
)
5723 unsigned int max_val
;
5725 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5728 max_val
= (1 << operand
->size
) - 1;
5729 if (arg
->token
->u
.index
> max_val
)
5731 match_out_of_range (arg
);
5734 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5739 /* OP_REG_INDEX matcher. */
5742 match_reg_index_operand (struct mips_arg_info
*arg
,
5743 const struct mips_operand
*operand
)
5747 if (arg
->token
->type
!= OT_REG_INDEX
)
5750 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5753 insn_insert_operand (arg
->insn
, operand
, regno
);
5758 /* OP_PC matcher. */
5761 match_pc_operand (struct mips_arg_info
*arg
)
5763 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5771 /* OP_NON_ZERO_REG matcher. */
5774 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
5775 const struct mips_operand
*operand
)
5779 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5785 arg
->last_regno
= regno
;
5786 insn_insert_operand (arg
->insn
, operand
, regno
);
5790 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5791 register that we need to match. */
5794 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5798 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5801 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5802 the length of the value in bytes (4 for float, 8 for double) and
5803 USING_GPRS says whether the destination is a GPR rather than an FPR.
5805 Return the constant in IMM and OFFSET as follows:
5807 - If the constant should be loaded via memory, set IMM to O_absent and
5808 OFFSET to the memory address.
5810 - Otherwise, if the constant should be loaded into two 32-bit registers,
5811 set IMM to the O_constant to load into the high register and OFFSET
5812 to the corresponding value for the low register.
5814 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5816 These constants only appear as the last operand in an instruction,
5817 and every instruction that accepts them in any variant accepts them
5818 in all variants. This means we don't have to worry about backing out
5819 any changes if the instruction does not match. We just match
5820 unconditionally and report an error if the constant is invalid. */
5823 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5824 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5829 const char *newname
;
5830 unsigned char *data
;
5832 /* Where the constant is placed is based on how the MIPS assembler
5835 length == 4 && using_gprs -- immediate value only
5836 length == 8 && using_gprs -- .rdata or immediate value
5837 length == 4 && !using_gprs -- .lit4 or immediate value
5838 length == 8 && !using_gprs -- .lit8 or immediate value
5840 The .lit4 and .lit8 sections are only used if permitted by the
5842 if (arg
->token
->type
!= OT_FLOAT
)
5844 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5848 gas_assert (arg
->token
->u
.flt
.length
== length
);
5849 data
= arg
->token
->u
.flt
.data
;
5852 /* Handle 32-bit constants for which an immediate value is best. */
5855 || g_switch_value
< 4
5856 || (data
[0] == 0 && data
[1] == 0)
5857 || (data
[2] == 0 && data
[3] == 0)))
5859 imm
->X_op
= O_constant
;
5860 if (!target_big_endian
)
5861 imm
->X_add_number
= bfd_getl32 (data
);
5863 imm
->X_add_number
= bfd_getb32 (data
);
5864 offset
->X_op
= O_absent
;
5868 /* Handle 64-bit constants for which an immediate value is best. */
5870 && !mips_disable_float_construction
5871 /* Constants can only be constructed in GPRs and copied to FPRs if the
5872 GPRs are at least as wide as the FPRs or MTHC1 is available.
5873 Unlike most tests for 32-bit floating-point registers this check
5874 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
5875 permit 64-bit moves without MXHC1.
5876 Force the constant into memory otherwise. */
5879 || ISA_HAS_MXHC1 (mips_opts
.isa
)
5881 && ((data
[0] == 0 && data
[1] == 0)
5882 || (data
[2] == 0 && data
[3] == 0))
5883 && ((data
[4] == 0 && data
[5] == 0)
5884 || (data
[6] == 0 && data
[7] == 0)))
5886 /* The value is simple enough to load with a couple of instructions.
5887 If using 32-bit registers, set IMM to the high order 32 bits and
5888 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5890 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
5892 imm
->X_op
= O_constant
;
5893 offset
->X_op
= O_constant
;
5894 if (!target_big_endian
)
5896 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5897 offset
->X_add_number
= bfd_getl32 (data
);
5901 imm
->X_add_number
= bfd_getb32 (data
);
5902 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5904 if (offset
->X_add_number
== 0)
5905 offset
->X_op
= O_absent
;
5909 imm
->X_op
= O_constant
;
5910 if (!target_big_endian
)
5911 imm
->X_add_number
= bfd_getl64 (data
);
5913 imm
->X_add_number
= bfd_getb64 (data
);
5914 offset
->X_op
= O_absent
;
5919 /* Switch to the right section. */
5921 subseg
= now_subseg
;
5924 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5929 if (using_gprs
|| g_switch_value
< 8)
5930 newname
= RDATA_SECTION_NAME
;
5935 new_seg
= subseg_new (newname
, (subsegT
) 0);
5936 bfd_set_section_flags (stdoutput
, new_seg
,
5937 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5938 frag_align (length
== 4 ? 2 : 3, 0, 0);
5939 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5940 record_alignment (new_seg
, 4);
5942 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5944 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5946 /* Set the argument to the current address in the section. */
5947 imm
->X_op
= O_absent
;
5948 offset
->X_op
= O_symbol
;
5949 offset
->X_add_symbol
= symbol_temp_new_now ();
5950 offset
->X_add_number
= 0;
5952 /* Put the floating point number into the section. */
5953 p
= frag_more (length
);
5954 memcpy (p
, data
, length
);
5956 /* Switch back to the original section. */
5957 subseg_set (seg
, subseg
);
5961 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5965 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5966 const struct mips_operand
*operand
,
5967 bfd_boolean match_p
)
5971 /* The operand can be an XYZW mask or a single 2-bit channel index
5972 (with X being 0). */
5973 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5975 /* The suffix can be omitted when it is already part of the opcode. */
5976 if (arg
->token
->type
!= OT_CHANNELS
)
5979 uval
= arg
->token
->u
.channels
;
5980 if (operand
->size
== 2)
5982 /* Check that a single bit is set and convert it into a 2-bit index. */
5983 if ((uval
& -uval
) != uval
)
5985 uval
= 4 - ffs (uval
);
5988 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5993 insn_insert_operand (arg
->insn
, operand
, uval
);
5997 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5998 of the argument text if the match is successful, otherwise return null. */
6001 match_operand (struct mips_arg_info
*arg
,
6002 const struct mips_operand
*operand
)
6004 switch (operand
->type
)
6007 return match_int_operand (arg
, operand
);
6010 return match_mapped_int_operand (arg
, operand
);
6013 return match_msb_operand (arg
, operand
);
6016 case OP_OPTIONAL_REG
:
6017 return match_reg_operand (arg
, operand
);
6020 return match_reg_pair_operand (arg
, operand
);
6023 return match_pcrel_operand (arg
);
6026 return match_perf_reg_operand (arg
, operand
);
6028 case OP_ADDIUSP_INT
:
6029 return match_addiusp_operand (arg
, operand
);
6031 case OP_CLO_CLZ_DEST
:
6032 return match_clo_clz_dest_operand (arg
, operand
);
6034 case OP_LWM_SWM_LIST
:
6035 return match_lwm_swm_list_operand (arg
, operand
);
6037 case OP_ENTRY_EXIT_LIST
:
6038 return match_entry_exit_operand (arg
, operand
);
6040 case OP_SAVE_RESTORE_LIST
:
6041 return match_save_restore_list_operand (arg
);
6043 case OP_MDMX_IMM_REG
:
6044 return match_mdmx_imm_reg_operand (arg
, operand
);
6046 case OP_REPEAT_DEST_REG
:
6047 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6049 case OP_REPEAT_PREV_REG
:
6050 return match_tied_reg_operand (arg
, arg
->last_regno
);
6053 return match_pc_operand (arg
);
6056 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6058 case OP_VU0_MATCH_SUFFIX
:
6059 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6062 return match_imm_index_operand (arg
, operand
);
6065 return match_reg_index_operand (arg
, operand
);
6068 return match_same_rs_rt_operand (arg
, operand
);
6071 return match_check_prev_operand (arg
, operand
);
6073 case OP_NON_ZERO_REG
:
6074 return match_non_zero_reg_operand (arg
, operand
);
6079 /* ARG is the state after successfully matching an instruction.
6080 Issue any queued-up warnings. */
6083 check_completed_insn (struct mips_arg_info
*arg
)
6088 as_warn (_("used $at without \".set noat\""));
6090 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6094 /* Return true if modifying general-purpose register REG needs a delay. */
6097 reg_needs_delay (unsigned int reg
)
6099 unsigned long prev_pinfo
;
6101 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6102 if (!mips_opts
.noreorder
6103 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6104 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6105 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6111 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6112 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6113 by VR4120 errata. */
6116 classify_vr4120_insn (const char *name
)
6118 if (strncmp (name
, "macc", 4) == 0)
6119 return FIX_VR4120_MACC
;
6120 if (strncmp (name
, "dmacc", 5) == 0)
6121 return FIX_VR4120_DMACC
;
6122 if (strncmp (name
, "mult", 4) == 0)
6123 return FIX_VR4120_MULT
;
6124 if (strncmp (name
, "dmult", 5) == 0)
6125 return FIX_VR4120_DMULT
;
6126 if (strstr (name
, "div"))
6127 return FIX_VR4120_DIV
;
6128 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6129 return FIX_VR4120_MTHILO
;
6130 return NUM_FIX_VR4120_CLASSES
;
6133 #define INSN_ERET 0x42000018
6134 #define INSN_DERET 0x4200001f
6135 #define INSN_DMULT 0x1c
6136 #define INSN_DMULTU 0x1d
6138 /* Return the number of instructions that must separate INSN1 and INSN2,
6139 where INSN1 is the earlier instruction. Return the worst-case value
6140 for any INSN2 if INSN2 is null. */
6143 insns_between (const struct mips_cl_insn
*insn1
,
6144 const struct mips_cl_insn
*insn2
)
6146 unsigned long pinfo1
, pinfo2
;
6149 /* If INFO2 is null, pessimistically assume that all flags are set for
6150 the second instruction. */
6151 pinfo1
= insn1
->insn_mo
->pinfo
;
6152 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6154 /* For most targets, write-after-read dependencies on the HI and LO
6155 registers must be separated by at least two instructions. */
6156 if (!hilo_interlocks
)
6158 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6160 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6164 /* If we're working around r7000 errata, there must be two instructions
6165 between an mfhi or mflo and any instruction that uses the result. */
6166 if (mips_7000_hilo_fix
6167 && !mips_opts
.micromips
6168 && MF_HILO_INSN (pinfo1
)
6169 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6172 /* If we're working around 24K errata, one instruction is required
6173 if an ERET or DERET is followed by a branch instruction. */
6174 if (mips_fix_24k
&& !mips_opts
.micromips
)
6176 if (insn1
->insn_opcode
== INSN_ERET
6177 || insn1
->insn_opcode
== INSN_DERET
)
6180 || insn2
->insn_opcode
== INSN_ERET
6181 || insn2
->insn_opcode
== INSN_DERET
6182 || delayed_branch_p (insn2
))
6187 /* If we're working around PMC RM7000 errata, there must be three
6188 nops between a dmult and a load instruction. */
6189 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6191 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6192 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6194 if (pinfo2
& INSN_LOAD_MEMORY
)
6199 /* If working around VR4120 errata, check for combinations that need
6200 a single intervening instruction. */
6201 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6203 unsigned int class1
, class2
;
6205 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6206 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6210 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6211 if (vr4120_conflicts
[class1
] & (1 << class2
))
6216 if (!HAVE_CODE_COMPRESSION
)
6218 /* Check for GPR or coprocessor load delays. All such delays
6219 are on the RT register. */
6220 /* Itbl support may require additional care here. */
6221 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6222 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6224 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6228 /* Check for generic coprocessor hazards.
6230 This case is not handled very well. There is no special
6231 knowledge of CP0 handling, and the coprocessors other than
6232 the floating point unit are not distinguished at all. */
6233 /* Itbl support may require additional care here. FIXME!
6234 Need to modify this to include knowledge about
6235 user specified delays! */
6236 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6237 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6239 /* Handle cases where INSN1 writes to a known general coprocessor
6240 register. There must be a one instruction delay before INSN2
6241 if INSN2 reads that register, otherwise no delay is needed. */
6242 mask
= fpr_write_mask (insn1
);
6245 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6250 /* Read-after-write dependencies on the control registers
6251 require a two-instruction gap. */
6252 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6253 && (pinfo2
& INSN_READ_COND_CODE
))
6256 /* We don't know exactly what INSN1 does. If INSN2 is
6257 also a coprocessor instruction, assume there must be
6258 a one instruction gap. */
6259 if (pinfo2
& INSN_COP
)
6264 /* Check for read-after-write dependencies on the coprocessor
6265 control registers in cases where INSN1 does not need a general
6266 coprocessor delay. This means that INSN1 is a floating point
6267 comparison instruction. */
6268 /* Itbl support may require additional care here. */
6269 else if (!cop_interlocks
6270 && (pinfo1
& INSN_WRITE_COND_CODE
)
6271 && (pinfo2
& INSN_READ_COND_CODE
))
6275 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6276 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6278 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6279 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6280 || (insn2
&& delayed_branch_p (insn2
))))
6286 /* Return the number of nops that would be needed to work around the
6287 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6288 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6289 that are contained within the first IGNORE instructions of HIST. */
6292 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6293 const struct mips_cl_insn
*insn
)
6298 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6299 are not affected by the errata. */
6301 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6302 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6303 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6306 /* Search for the first MFLO or MFHI. */
6307 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6308 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6310 /* Extract the destination register. */
6311 mask
= gpr_write_mask (&hist
[i
]);
6313 /* No nops are needed if INSN reads that register. */
6314 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6317 /* ...or if any of the intervening instructions do. */
6318 for (j
= 0; j
< i
; j
++)
6319 if (gpr_read_mask (&hist
[j
]) & mask
)
6323 return MAX_VR4130_NOPS
- i
;
6328 #define BASE_REG_EQ(INSN1, INSN2) \
6329 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6330 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6332 /* Return the minimum alignment for this store instruction. */
6335 fix_24k_align_to (const struct mips_opcode
*mo
)
6337 if (strcmp (mo
->name
, "sh") == 0)
6340 if (strcmp (mo
->name
, "swc1") == 0
6341 || strcmp (mo
->name
, "swc2") == 0
6342 || strcmp (mo
->name
, "sw") == 0
6343 || strcmp (mo
->name
, "sc") == 0
6344 || strcmp (mo
->name
, "s.s") == 0)
6347 if (strcmp (mo
->name
, "sdc1") == 0
6348 || strcmp (mo
->name
, "sdc2") == 0
6349 || strcmp (mo
->name
, "s.d") == 0)
6356 struct fix_24k_store_info
6358 /* Immediate offset, if any, for this store instruction. */
6360 /* Alignment required by this store instruction. */
6362 /* True for register offsets. */
6363 int register_offset
;
6366 /* Comparison function used by qsort. */
6369 fix_24k_sort (const void *a
, const void *b
)
6371 const struct fix_24k_store_info
*pos1
= a
;
6372 const struct fix_24k_store_info
*pos2
= b
;
6374 return (pos1
->off
- pos2
->off
);
6377 /* INSN is a store instruction. Try to record the store information
6378 in STINFO. Return false if the information isn't known. */
6381 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6382 const struct mips_cl_insn
*insn
)
6384 /* The instruction must have a known offset. */
6385 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6388 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6389 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6393 /* Return the number of nops that would be needed to work around the 24k
6394 "lost data on stores during refill" errata if instruction INSN
6395 immediately followed the 2 instructions described by HIST.
6396 Ignore hazards that are contained within the first IGNORE
6397 instructions of HIST.
6399 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6400 for the data cache refills and store data. The following describes
6401 the scenario where the store data could be lost.
6403 * A data cache miss, due to either a load or a store, causing fill
6404 data to be supplied by the memory subsystem
6405 * The first three doublewords of fill data are returned and written
6407 * A sequence of four stores occurs in consecutive cycles around the
6408 final doubleword of the fill:
6412 * Zero, One or more instructions
6415 The four stores A-D must be to different doublewords of the line that
6416 is being filled. The fourth instruction in the sequence above permits
6417 the fill of the final doubleword to be transferred from the FSB into
6418 the cache. In the sequence above, the stores may be either integer
6419 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6420 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6421 different doublewords on the line. If the floating point unit is
6422 running in 1:2 mode, it is not possible to create the sequence above
6423 using only floating point store instructions.
6425 In this case, the cache line being filled is incorrectly marked
6426 invalid, thereby losing the data from any store to the line that
6427 occurs between the original miss and the completion of the five
6428 cycle sequence shown above.
6430 The workarounds are:
6432 * Run the data cache in write-through mode.
6433 * Insert a non-store instruction between
6434 Store A and Store B or Store B and Store C. */
6437 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6438 const struct mips_cl_insn
*insn
)
6440 struct fix_24k_store_info pos
[3];
6441 int align
, i
, base_offset
;
6446 /* If the previous instruction wasn't a store, there's nothing to
6448 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6451 /* If the instructions after the previous one are unknown, we have
6452 to assume the worst. */
6456 /* Check whether we are dealing with three consecutive stores. */
6457 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6458 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6461 /* If we don't know the relationship between the store addresses,
6462 assume the worst. */
6463 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6464 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6467 if (!fix_24k_record_store_info (&pos
[0], insn
)
6468 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6469 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6472 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6474 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6475 X bytes and such that the base register + X is known to be aligned
6478 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6482 align
= pos
[0].align_to
;
6483 base_offset
= pos
[0].off
;
6484 for (i
= 1; i
< 3; i
++)
6485 if (align
< pos
[i
].align_to
)
6487 align
= pos
[i
].align_to
;
6488 base_offset
= pos
[i
].off
;
6490 for (i
= 0; i
< 3; i
++)
6491 pos
[i
].off
-= base_offset
;
6494 pos
[0].off
&= ~align
+ 1;
6495 pos
[1].off
&= ~align
+ 1;
6496 pos
[2].off
&= ~align
+ 1;
6498 /* If any two stores write to the same chunk, they also write to the
6499 same doubleword. The offsets are still sorted at this point. */
6500 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6503 /* A range of at least 9 bytes is needed for the stores to be in
6504 non-overlapping doublewords. */
6505 if (pos
[2].off
- pos
[0].off
<= 8)
6508 if (pos
[2].off
- pos
[1].off
>= 24
6509 || pos
[1].off
- pos
[0].off
>= 24
6510 || pos
[2].off
- pos
[0].off
>= 32)
6516 /* Return the number of nops that would be needed if instruction INSN
6517 immediately followed the MAX_NOPS instructions given by HIST,
6518 where HIST[0] is the most recent instruction. Ignore hazards
6519 between INSN and the first IGNORE instructions in HIST.
6521 If INSN is null, return the worse-case number of nops for any
6525 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6526 const struct mips_cl_insn
*insn
)
6528 int i
, nops
, tmp_nops
;
6531 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6533 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6534 if (tmp_nops
> nops
)
6538 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6540 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6541 if (tmp_nops
> nops
)
6545 if (mips_fix_24k
&& !mips_opts
.micromips
)
6547 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6548 if (tmp_nops
> nops
)
6555 /* The variable arguments provide NUM_INSNS extra instructions that
6556 might be added to HIST. Return the largest number of nops that
6557 would be needed after the extended sequence, ignoring hazards
6558 in the first IGNORE instructions. */
6561 nops_for_sequence (int num_insns
, int ignore
,
6562 const struct mips_cl_insn
*hist
, ...)
6565 struct mips_cl_insn buffer
[MAX_NOPS
];
6566 struct mips_cl_insn
*cursor
;
6569 va_start (args
, hist
);
6570 cursor
= buffer
+ num_insns
;
6571 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6572 while (cursor
> buffer
)
6573 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6575 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6580 /* Like nops_for_insn, but if INSN is a branch, take into account the
6581 worst-case delay for the branch target. */
6584 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6585 const struct mips_cl_insn
*insn
)
6589 nops
= nops_for_insn (ignore
, hist
, insn
);
6590 if (delayed_branch_p (insn
))
6592 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6593 hist
, insn
, get_delay_slot_nop (insn
));
6594 if (tmp_nops
> nops
)
6597 else if (compact_branch_p (insn
))
6599 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6600 if (tmp_nops
> nops
)
6606 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6609 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6611 gas_assert (!HAVE_CODE_COMPRESSION
);
6612 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6613 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6616 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6617 jr target pc &= 'hffff_ffff_cfff_ffff. */
6620 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6622 gas_assert (!HAVE_CODE_COMPRESSION
);
6623 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6624 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6625 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6633 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6634 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6637 ep
.X_op
= O_constant
;
6638 ep
.X_add_number
= 0xcfff0000;
6639 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6640 ep
.X_add_number
= 0xffff;
6641 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6642 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6647 fix_loongson2f (struct mips_cl_insn
* ip
)
6649 if (mips_fix_loongson2f_nop
)
6650 fix_loongson2f_nop (ip
);
6652 if (mips_fix_loongson2f_jump
)
6653 fix_loongson2f_jump (ip
);
6656 /* IP is a branch that has a delay slot, and we need to fill it
6657 automatically. Return true if we can do that by swapping IP
6658 with the previous instruction.
6659 ADDRESS_EXPR is an operand of the instruction to be used with
6663 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6664 bfd_reloc_code_real_type
*reloc_type
)
6666 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6667 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6668 unsigned int fpr_read
, prev_fpr_write
;
6670 /* -O2 and above is required for this optimization. */
6671 if (mips_optimize
< 2)
6674 /* If we have seen .set volatile or .set nomove, don't optimize. */
6675 if (mips_opts
.nomove
)
6678 /* We can't swap if the previous instruction's position is fixed. */
6679 if (history
[0].fixed_p
)
6682 /* If the previous previous insn was in a .set noreorder, we can't
6683 swap. Actually, the MIPS assembler will swap in this situation.
6684 However, gcc configured -with-gnu-as will generate code like
6692 in which we can not swap the bne and INSN. If gcc is not configured
6693 -with-gnu-as, it does not output the .set pseudo-ops. */
6694 if (history
[1].noreorder_p
)
6697 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6698 This means that the previous instruction was a 4-byte one anyhow. */
6699 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6702 /* If the branch is itself the target of a branch, we can not swap.
6703 We cheat on this; all we check for is whether there is a label on
6704 this instruction. If there are any branches to anything other than
6705 a label, users must use .set noreorder. */
6706 if (seg_info (now_seg
)->label_list
)
6709 /* If the previous instruction is in a variant frag other than this
6710 branch's one, we cannot do the swap. This does not apply to
6711 MIPS16 code, which uses variant frags for different purposes. */
6712 if (!mips_opts
.mips16
6714 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6717 /* We do not swap with instructions that cannot architecturally
6718 be placed in a branch delay slot, such as SYNC or ERET. We
6719 also refrain from swapping with a trap instruction, since it
6720 complicates trap handlers to have the trap instruction be in
6722 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6723 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6726 /* Check for conflicts between the branch and the instructions
6727 before the candidate delay slot. */
6728 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6731 /* Check for conflicts between the swapped sequence and the
6732 target of the branch. */
6733 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6736 /* If the branch reads a register that the previous
6737 instruction sets, we can not swap. */
6738 gpr_read
= gpr_read_mask (ip
);
6739 prev_gpr_write
= gpr_write_mask (&history
[0]);
6740 if (gpr_read
& prev_gpr_write
)
6743 fpr_read
= fpr_read_mask (ip
);
6744 prev_fpr_write
= fpr_write_mask (&history
[0]);
6745 if (fpr_read
& prev_fpr_write
)
6748 /* If the branch writes a register that the previous
6749 instruction sets, we can not swap. */
6750 gpr_write
= gpr_write_mask (ip
);
6751 if (gpr_write
& prev_gpr_write
)
6754 /* If the branch writes a register that the previous
6755 instruction reads, we can not swap. */
6756 prev_gpr_read
= gpr_read_mask (&history
[0]);
6757 if (gpr_write
& prev_gpr_read
)
6760 /* If one instruction sets a condition code and the
6761 other one uses a condition code, we can not swap. */
6762 pinfo
= ip
->insn_mo
->pinfo
;
6763 if ((pinfo
& INSN_READ_COND_CODE
)
6764 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6766 if ((pinfo
& INSN_WRITE_COND_CODE
)
6767 && (prev_pinfo
& INSN_READ_COND_CODE
))
6770 /* If the previous instruction uses the PC, we can not swap. */
6771 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6772 if (prev_pinfo2
& INSN2_READ_PC
)
6775 /* If the previous instruction has an incorrect size for a fixed
6776 branch delay slot in microMIPS mode, we cannot swap. */
6777 pinfo2
= ip
->insn_mo
->pinfo2
;
6778 if (mips_opts
.micromips
6779 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6780 && insn_length (history
) != 2)
6782 if (mips_opts
.micromips
6783 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6784 && insn_length (history
) != 4)
6787 /* On R5900 short loops need to be fixed by inserting a nop in
6788 the branch delay slots.
6789 A short loop can be terminated too early. */
6790 if (mips_opts
.arch
== CPU_R5900
6791 /* Check if instruction has a parameter, ignore "j $31". */
6792 && (address_expr
!= NULL
)
6793 /* Parameter must be 16 bit. */
6794 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6795 /* Branch to same segment. */
6796 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
6797 /* Branch to same code fragment. */
6798 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
6799 /* Can only calculate branch offset if value is known. */
6800 && symbol_constant_p (address_expr
->X_add_symbol
)
6801 /* Check if branch is really conditional. */
6802 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6803 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6804 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6807 /* Check if loop is shorter than 6 instructions including
6808 branch and delay slot. */
6809 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
6816 /* When the loop includes branches or jumps,
6817 it is not a short loop. */
6818 for (i
= 0; i
< (distance
/ 4); i
++)
6820 if ((history
[i
].cleared_p
)
6821 || delayed_branch_p (&history
[i
]))
6829 /* Insert nop after branch to fix short loop. */
6838 /* Decide how we should add IP to the instruction stream.
6839 ADDRESS_EXPR is an operand of the instruction to be used with
6842 static enum append_method
6843 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6844 bfd_reloc_code_real_type
*reloc_type
)
6846 /* The relaxed version of a macro sequence must be inherently
6848 if (mips_relax
.sequence
== 2)
6851 /* We must not dabble with instructions in a ".set noreorder" block. */
6852 if (mips_opts
.noreorder
)
6855 /* Otherwise, it's our responsibility to fill branch delay slots. */
6856 if (delayed_branch_p (ip
))
6858 if (!branch_likely_p (ip
)
6859 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6862 if (mips_opts
.mips16
6863 && ISA_SUPPORTS_MIPS16E
6864 && gpr_read_mask (ip
) != 0)
6865 return APPEND_ADD_COMPACT
;
6867 if (mips_opts
.micromips
6868 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
6869 || (!forced_insn_length
6870 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
6871 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
6872 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
6873 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
6874 return APPEND_ADD_COMPACT
;
6876 return APPEND_ADD_WITH_NOP
;
6882 /* IP is an instruction whose opcode we have just changed, END points
6883 to the end of the opcode table processed. Point IP->insn_mo to the
6884 new opcode's definition. */
6887 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
6889 const struct mips_opcode
*mo
;
6891 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6892 if (mo
->pinfo
!= INSN_MACRO
6893 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6901 /* IP is a MIPS16 instruction whose opcode we have just changed.
6902 Point IP->insn_mo to the new opcode's definition. */
6905 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6907 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
6910 /* IP is a microMIPS instruction whose opcode we have just changed.
6911 Point IP->insn_mo to the new opcode's definition. */
6914 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
6916 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
6919 /* For microMIPS macros, we need to generate a local number label
6920 as the target of branches. */
6921 #define MICROMIPS_LABEL_CHAR '\037'
6922 static unsigned long micromips_target_label
;
6923 static char micromips_target_name
[32];
6926 micromips_label_name (void)
6928 char *p
= micromips_target_name
;
6929 char symbol_name_temporary
[24];
6937 l
= micromips_target_label
;
6938 #ifdef LOCAL_LABEL_PREFIX
6939 *p
++ = LOCAL_LABEL_PREFIX
;
6942 *p
++ = MICROMIPS_LABEL_CHAR
;
6945 symbol_name_temporary
[i
++] = l
% 10 + '0';
6950 *p
++ = symbol_name_temporary
[--i
];
6953 return micromips_target_name
;
6957 micromips_label_expr (expressionS
*label_expr
)
6959 label_expr
->X_op
= O_symbol
;
6960 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6961 label_expr
->X_add_number
= 0;
6965 micromips_label_inc (void)
6967 micromips_target_label
++;
6968 *micromips_target_name
= '\0';
6972 micromips_add_label (void)
6976 s
= colon (micromips_label_name ());
6977 micromips_label_inc ();
6978 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6981 /* If assembling microMIPS code, then return the microMIPS reloc
6982 corresponding to the requested one if any. Otherwise return
6983 the reloc unchanged. */
6985 static bfd_reloc_code_real_type
6986 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6988 static const bfd_reloc_code_real_type relocs
[][2] =
6990 /* Keep sorted incrementally by the left-hand key. */
6991 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6992 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6993 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6994 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6995 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6996 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6997 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6998 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6999 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7000 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7001 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7002 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7003 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7004 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7005 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7006 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7007 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7008 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7009 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7010 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7011 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7012 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7013 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7014 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7015 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7016 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7017 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7019 bfd_reloc_code_real_type r
;
7022 if (!mips_opts
.micromips
)
7024 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7030 return relocs
[i
][1];
7035 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7036 Return true on success, storing the resolved value in RESULT. */
7039 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7044 case BFD_RELOC_MIPS_HIGHEST
:
7045 case BFD_RELOC_MICROMIPS_HIGHEST
:
7046 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7049 case BFD_RELOC_MIPS_HIGHER
:
7050 case BFD_RELOC_MICROMIPS_HIGHER
:
7051 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7054 case BFD_RELOC_HI16_S
:
7055 case BFD_RELOC_HI16_S_PCREL
:
7056 case BFD_RELOC_MICROMIPS_HI16_S
:
7057 case BFD_RELOC_MIPS16_HI16_S
:
7058 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7061 case BFD_RELOC_HI16
:
7062 case BFD_RELOC_MICROMIPS_HI16
:
7063 case BFD_RELOC_MIPS16_HI16
:
7064 *result
= (operand
>> 16) & 0xffff;
7067 case BFD_RELOC_LO16
:
7068 case BFD_RELOC_LO16_PCREL
:
7069 case BFD_RELOC_MICROMIPS_LO16
:
7070 case BFD_RELOC_MIPS16_LO16
:
7071 *result
= operand
& 0xffff;
7074 case BFD_RELOC_UNUSED
:
7083 /* Output an instruction. IP is the instruction information.
7084 ADDRESS_EXPR is an operand of the instruction to be used with
7085 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7086 a macro expansion. */
7089 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7090 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7092 unsigned long prev_pinfo2
, pinfo
;
7093 bfd_boolean relaxed_branch
= FALSE
;
7094 enum append_method method
;
7095 bfd_boolean relax32
;
7098 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7099 fix_loongson2f (ip
);
7101 file_ase_mips16
|= mips_opts
.mips16
;
7102 file_ase_micromips
|= mips_opts
.micromips
;
7104 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7105 pinfo
= ip
->insn_mo
->pinfo
;
7107 /* Don't raise alarm about `nods' frags as they'll fill in the right
7108 kind of nop in relaxation if required. */
7109 if (mips_opts
.micromips
7111 && !(history
[0].frag
7112 && history
[0].frag
->fr_type
== rs_machine_dependent
7113 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7114 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7115 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7116 && micromips_insn_length (ip
->insn_mo
) != 2)
7117 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7118 && micromips_insn_length (ip
->insn_mo
) != 4)))
7119 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7120 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7122 if (address_expr
== NULL
)
7124 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7125 && reloc_type
[1] == BFD_RELOC_UNUSED
7126 && reloc_type
[2] == BFD_RELOC_UNUSED
7127 && address_expr
->X_op
== O_constant
)
7129 switch (*reloc_type
)
7131 case BFD_RELOC_MIPS_JMP
:
7135 /* Shift is 2, unusually, for microMIPS JALX. */
7136 shift
= (mips_opts
.micromips
7137 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7138 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7139 as_bad (_("jump to misaligned address (0x%lx)"),
7140 (unsigned long) address_expr
->X_add_number
);
7141 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7147 case BFD_RELOC_MIPS16_JMP
:
7148 if ((address_expr
->X_add_number
& 3) != 0)
7149 as_bad (_("jump to misaligned address (0x%lx)"),
7150 (unsigned long) address_expr
->X_add_number
);
7152 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7153 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7154 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7158 case BFD_RELOC_16_PCREL_S2
:
7162 shift
= mips_opts
.micromips
? 1 : 2;
7163 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7164 as_bad (_("branch to misaligned address (0x%lx)"),
7165 (unsigned long) address_expr
->X_add_number
);
7166 if (!mips_relax_branch
)
7168 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7169 & ~((1 << (shift
+ 16)) - 1))
7170 as_bad (_("branch address range overflow (0x%lx)"),
7171 (unsigned long) address_expr
->X_add_number
);
7172 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7178 case BFD_RELOC_MIPS_21_PCREL_S2
:
7183 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7184 as_bad (_("branch to misaligned address (0x%lx)"),
7185 (unsigned long) address_expr
->X_add_number
);
7186 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7187 & ~((1 << (shift
+ 21)) - 1))
7188 as_bad (_("branch address range overflow (0x%lx)"),
7189 (unsigned long) address_expr
->X_add_number
);
7190 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7195 case BFD_RELOC_MIPS_26_PCREL_S2
:
7200 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7201 as_bad (_("branch to misaligned address (0x%lx)"),
7202 (unsigned long) address_expr
->X_add_number
);
7203 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7204 & ~((1 << (shift
+ 26)) - 1))
7205 as_bad (_("branch address range overflow (0x%lx)"),
7206 (unsigned long) address_expr
->X_add_number
);
7207 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7216 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7219 ip
->insn_opcode
|= value
& 0xffff;
7227 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7229 /* There are a lot of optimizations we could do that we don't.
7230 In particular, we do not, in general, reorder instructions.
7231 If you use gcc with optimization, it will reorder
7232 instructions and generally do much more optimization then we
7233 do here; repeating all that work in the assembler would only
7234 benefit hand written assembly code, and does not seem worth
7236 int nops
= (mips_optimize
== 0
7237 ? nops_for_insn (0, history
, NULL
)
7238 : nops_for_insn_or_target (0, history
, ip
));
7242 unsigned long old_frag_offset
;
7245 old_frag
= frag_now
;
7246 old_frag_offset
= frag_now_fix ();
7248 for (i
= 0; i
< nops
; i
++)
7249 add_fixed_insn (NOP_INSN
);
7250 insert_into_history (0, nops
, NOP_INSN
);
7254 listing_prev_line ();
7255 /* We may be at the start of a variant frag. In case we
7256 are, make sure there is enough space for the frag
7257 after the frags created by listing_prev_line. The
7258 argument to frag_grow here must be at least as large
7259 as the argument to all other calls to frag_grow in
7260 this file. We don't have to worry about being in the
7261 middle of a variant frag, because the variants insert
7262 all needed nop instructions themselves. */
7266 mips_move_text_labels ();
7268 #ifndef NO_ECOFF_DEBUGGING
7269 if (ECOFF_DEBUGGING
)
7270 ecoff_fix_loc (old_frag
, old_frag_offset
);
7274 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7278 /* Work out how many nops in prev_nop_frag are needed by IP,
7279 ignoring hazards generated by the first prev_nop_frag_since
7281 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7282 gas_assert (nops
<= prev_nop_frag_holds
);
7284 /* Enforce NOPS as a minimum. */
7285 if (nops
> prev_nop_frag_required
)
7286 prev_nop_frag_required
= nops
;
7288 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7290 /* Settle for the current number of nops. Update the history
7291 accordingly (for the benefit of any future .set reorder code). */
7292 prev_nop_frag
= NULL
;
7293 insert_into_history (prev_nop_frag_since
,
7294 prev_nop_frag_holds
, NOP_INSN
);
7298 /* Allow this instruction to replace one of the nops that was
7299 tentatively added to prev_nop_frag. */
7300 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7301 prev_nop_frag_holds
--;
7302 prev_nop_frag_since
++;
7306 method
= get_append_method (ip
, address_expr
, reloc_type
);
7307 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7309 dwarf2_emit_insn (0);
7310 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7311 so "move" the instruction address accordingly.
7313 Also, it doesn't seem appropriate for the assembler to reorder .loc
7314 entries. If this instruction is a branch that we are going to swap
7315 with the previous instruction, the two instructions should be
7316 treated as a unit, and the debug information for both instructions
7317 should refer to the start of the branch sequence. Using the
7318 current position is certainly wrong when swapping a 32-bit branch
7319 and a 16-bit delay slot, since the current position would then be
7320 in the middle of a branch. */
7321 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7323 relax32
= (mips_relax_branch
7324 /* Don't try branch relaxation within .set nomacro, or within
7325 .set noat if we use $at for PIC computations. If it turns
7326 out that the branch was out-of-range, we'll get an error. */
7327 && !mips_opts
.warn_about_macros
7328 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7329 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7330 as they have no complementing branches. */
7331 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7333 if (!HAVE_CODE_COMPRESSION
7336 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7337 && delayed_branch_p (ip
))
7339 relaxed_branch
= TRUE
;
7340 add_relaxed_insn (ip
, (relaxed_branch_length
7342 uncond_branch_p (ip
) ? -1
7343 : branch_likely_p (ip
) ? 1
7346 (AT
, mips_pic
!= NO_PIC
,
7347 uncond_branch_p (ip
),
7348 branch_likely_p (ip
),
7349 pinfo
& INSN_WRITE_GPR_31
,
7351 address_expr
->X_add_symbol
,
7352 address_expr
->X_add_number
);
7353 *reloc_type
= BFD_RELOC_UNUSED
;
7355 else if (mips_opts
.micromips
7357 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7358 || *reloc_type
> BFD_RELOC_UNUSED
)
7359 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7360 /* Don't try branch relaxation when users specify
7361 16-bit/32-bit instructions. */
7362 && !forced_insn_length
)
7364 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7365 && *reloc_type
> BFD_RELOC_UNUSED
);
7366 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7367 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7368 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7369 int nods
= method
== APPEND_ADD_WITH_NOP
;
7370 int al
= pinfo
& INSN_WRITE_GPR_31
;
7371 int length32
= nods
? 8 : 4;
7373 gas_assert (address_expr
!= NULL
);
7374 gas_assert (!mips_relax
.sequence
);
7376 relaxed_branch
= TRUE
;
7378 method
= APPEND_ADD
;
7380 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7381 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7382 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7384 uncond
, compact
, al
, nods
,
7386 address_expr
->X_add_symbol
,
7387 address_expr
->X_add_number
);
7388 *reloc_type
= BFD_RELOC_UNUSED
;
7390 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7392 bfd_boolean require_unextended
;
7393 bfd_boolean require_extended
;
7397 if (forced_insn_length
!= 0)
7399 require_unextended
= forced_insn_length
== 2;
7400 require_extended
= forced_insn_length
== 4;
7404 require_unextended
= (mips_opts
.noautoextend
7405 && !mips_opcode_32bit_p (ip
->insn_mo
));
7406 require_extended
= 0;
7409 /* We need to set up a variant frag. */
7410 gas_assert (address_expr
!= NULL
);
7411 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7412 symbol created by `make_expr_symbol' may not get a necessary
7413 external relocation produced. */
7414 if (address_expr
->X_op
== O_symbol
)
7416 symbol
= address_expr
->X_add_symbol
;
7417 offset
= address_expr
->X_add_number
;
7421 symbol
= make_expr_symbol (address_expr
);
7424 add_relaxed_insn (ip
, 4, 0,
7426 (*reloc_type
- BFD_RELOC_UNUSED
,
7427 require_unextended
, require_extended
,
7428 delayed_branch_p (&history
[0]),
7429 history
[0].mips16_absolute_jump_p
),
7432 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7434 if (!delayed_branch_p (ip
))
7435 /* Make sure there is enough room to swap this instruction with
7436 a following jump instruction. */
7438 add_fixed_insn (ip
);
7442 if (mips_opts
.mips16
7443 && mips_opts
.noreorder
7444 && delayed_branch_p (&history
[0]))
7445 as_warn (_("extended instruction in delay slot"));
7447 if (mips_relax
.sequence
)
7449 /* If we've reached the end of this frag, turn it into a variant
7450 frag and record the information for the instructions we've
7452 if (frag_room () < 4)
7453 relax_close_frag ();
7454 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7457 if (mips_relax
.sequence
!= 2)
7459 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7460 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7461 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7462 mips_macro_warning
.insns
[0]++;
7464 if (mips_relax
.sequence
!= 1)
7466 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7467 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7468 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7469 mips_macro_warning
.insns
[1]++;
7472 if (mips_opts
.mips16
)
7475 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7477 add_fixed_insn (ip
);
7480 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7482 bfd_reloc_code_real_type final_type
[3];
7483 reloc_howto_type
*howto0
;
7484 reloc_howto_type
*howto
;
7487 /* Perform any necessary conversion to microMIPS relocations
7488 and find out how many relocations there actually are. */
7489 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7490 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7492 /* In a compound relocation, it is the final (outermost)
7493 operator that determines the relocated field. */
7494 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7499 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7500 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7501 bfd_get_reloc_size (howto
),
7503 howto0
&& howto0
->pc_relative
,
7505 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7506 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7508 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7509 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7510 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7512 /* These relocations can have an addend that won't fit in
7513 4 octets for 64bit assembly. */
7515 && ! howto
->partial_inplace
7516 && (reloc_type
[0] == BFD_RELOC_16
7517 || reloc_type
[0] == BFD_RELOC_32
7518 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7519 || reloc_type
[0] == BFD_RELOC_GPREL16
7520 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7521 || reloc_type
[0] == BFD_RELOC_GPREL32
7522 || reloc_type
[0] == BFD_RELOC_64
7523 || reloc_type
[0] == BFD_RELOC_CTOR
7524 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7525 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7526 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7527 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7528 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7529 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7530 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7531 || hi16_reloc_p (reloc_type
[0])
7532 || lo16_reloc_p (reloc_type
[0])))
7533 ip
->fixp
[0]->fx_no_overflow
= 1;
7535 /* These relocations can have an addend that won't fit in 2 octets. */
7536 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7537 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7538 ip
->fixp
[0]->fx_no_overflow
= 1;
7540 if (mips_relax
.sequence
)
7542 if (mips_relax
.first_fixup
== 0)
7543 mips_relax
.first_fixup
= ip
->fixp
[0];
7545 else if (reloc_needs_lo_p (*reloc_type
))
7547 struct mips_hi_fixup
*hi_fixup
;
7549 /* Reuse the last entry if it already has a matching %lo. */
7550 hi_fixup
= mips_hi_fixup_list
;
7552 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7554 hi_fixup
= XNEW (struct mips_hi_fixup
);
7555 hi_fixup
->next
= mips_hi_fixup_list
;
7556 mips_hi_fixup_list
= hi_fixup
;
7558 hi_fixup
->fixp
= ip
->fixp
[0];
7559 hi_fixup
->seg
= now_seg
;
7562 /* Add fixups for the second and third relocations, if given.
7563 Note that the ABI allows the second relocation to be
7564 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7565 moment we only use RSS_UNDEF, but we could add support
7566 for the others if it ever becomes necessary. */
7567 for (i
= 1; i
< 3; i
++)
7568 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7570 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7571 ip
->fixp
[0]->fx_size
, NULL
, 0,
7572 FALSE
, final_type
[i
]);
7574 /* Use fx_tcbit to mark compound relocs. */
7575 ip
->fixp
[0]->fx_tcbit
= 1;
7576 ip
->fixp
[i
]->fx_tcbit
= 1;
7580 /* Update the register mask information. */
7581 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7582 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7587 insert_into_history (0, 1, ip
);
7590 case APPEND_ADD_WITH_NOP
:
7592 struct mips_cl_insn
*nop
;
7594 insert_into_history (0, 1, ip
);
7595 nop
= get_delay_slot_nop (ip
);
7596 add_fixed_insn (nop
);
7597 insert_into_history (0, 1, nop
);
7598 if (mips_relax
.sequence
)
7599 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7603 case APPEND_ADD_COMPACT
:
7604 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7605 if (mips_opts
.mips16
)
7607 ip
->insn_opcode
|= 0x0080;
7608 find_altered_mips16_opcode (ip
);
7610 /* Convert microMIPS instructions. */
7611 else if (mips_opts
.micromips
)
7614 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7615 ip
->insn_opcode
|= 0x0020;
7617 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7618 ip
->insn_opcode
= 0x40e00000;
7619 /* beqz16->beqzc, bnez16->bnezc */
7620 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7622 unsigned long regno
;
7624 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7625 regno
&= MICROMIPSOP_MASK_MD
;
7626 regno
= micromips_to_32_reg_d_map
[regno
];
7627 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7628 | (regno
<< MICROMIPSOP_SH_RS
)
7629 | 0x40a00000) ^ 0x00400000;
7631 /* beqz->beqzc, bnez->bnezc */
7632 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
7633 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
7634 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7635 | 0x40a00000) ^ 0x00400000;
7636 /* beq $0->beqzc, bne $0->bnezc */
7637 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
7638 ip
->insn_opcode
= (((ip
->insn_opcode
>>
7639 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
7640 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
7641 | ((ip
->insn_opcode
>> 7) & 0x00400000)
7642 | 0x40a00000) ^ 0x00400000;
7645 find_altered_micromips_opcode (ip
);
7650 insert_into_history (0, 1, ip
);
7655 struct mips_cl_insn delay
= history
[0];
7657 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
7659 /* Add the delay slot instruction to the end of the
7660 current frag and shrink the fixed part of the
7661 original frag. If the branch occupies the tail of
7662 the latter, move it backwards to cover the gap. */
7663 delay
.frag
->fr_fix
-= branch_disp
;
7664 if (delay
.frag
== ip
->frag
)
7665 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
7666 add_fixed_insn (&delay
);
7670 /* If this is not a relaxed branch and we are in the
7671 same frag, then just swap the instructions. */
7672 move_insn (ip
, delay
.frag
, delay
.where
);
7673 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
7677 insert_into_history (0, 1, &delay
);
7682 /* If we have just completed an unconditional branch, clear the history. */
7683 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7684 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7688 mips_no_prev_insn ();
7690 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7691 history
[i
].cleared_p
= 1;
7694 /* We need to emit a label at the end of branch-likely macros. */
7695 if (emit_branch_likely_macro
)
7697 emit_branch_likely_macro
= FALSE
;
7698 micromips_add_label ();
7701 /* We just output an insn, so the next one doesn't have a label. */
7702 mips_clear_insn_labels ();
7705 /* Forget that there was any previous instruction or label.
7706 When BRANCH is true, the branch history is also flushed. */
7709 mips_no_prev_insn (void)
7711 prev_nop_frag
= NULL
;
7712 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7713 mips_clear_insn_labels ();
7716 /* This function must be called before we emit something other than
7717 instructions. It is like mips_no_prev_insn except that it inserts
7718 any NOPS that might be needed by previous instructions. */
7721 mips_emit_delays (void)
7723 if (! mips_opts
.noreorder
)
7725 int nops
= nops_for_insn (0, history
, NULL
);
7729 add_fixed_insn (NOP_INSN
);
7730 mips_move_text_labels ();
7733 mips_no_prev_insn ();
7736 /* Start a (possibly nested) noreorder block. */
7739 start_noreorder (void)
7741 if (mips_opts
.noreorder
== 0)
7746 /* None of the instructions before the .set noreorder can be moved. */
7747 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7748 history
[i
].fixed_p
= 1;
7750 /* Insert any nops that might be needed between the .set noreorder
7751 block and the previous instructions. We will later remove any
7752 nops that turn out not to be needed. */
7753 nops
= nops_for_insn (0, history
, NULL
);
7756 if (mips_optimize
!= 0)
7758 /* Record the frag which holds the nop instructions, so
7759 that we can remove them if we don't need them. */
7760 frag_grow (nops
* NOP_INSN_SIZE
);
7761 prev_nop_frag
= frag_now
;
7762 prev_nop_frag_holds
= nops
;
7763 prev_nop_frag_required
= 0;
7764 prev_nop_frag_since
= 0;
7767 for (; nops
> 0; --nops
)
7768 add_fixed_insn (NOP_INSN
);
7770 /* Move on to a new frag, so that it is safe to simply
7771 decrease the size of prev_nop_frag. */
7772 frag_wane (frag_now
);
7774 mips_move_text_labels ();
7776 mips_mark_labels ();
7777 mips_clear_insn_labels ();
7779 mips_opts
.noreorder
++;
7780 mips_any_noreorder
= 1;
7783 /* End a nested noreorder block. */
7786 end_noreorder (void)
7788 mips_opts
.noreorder
--;
7789 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7791 /* Commit to inserting prev_nop_frag_required nops and go back to
7792 handling nop insertion the .set reorder way. */
7793 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7795 insert_into_history (prev_nop_frag_since
,
7796 prev_nop_frag_required
, NOP_INSN
);
7797 prev_nop_frag
= NULL
;
7801 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7802 higher bits unset. */
7805 normalize_constant_expr (expressionS
*ex
)
7807 if (ex
->X_op
== O_constant
7808 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7809 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7813 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7814 all higher bits unset. */
7817 normalize_address_expr (expressionS
*ex
)
7819 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7820 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7821 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7822 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7826 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7827 Return true if the match was successful.
7829 OPCODE_EXTRA is a value that should be ORed into the opcode
7830 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7831 there are more alternatives after OPCODE and SOFT_MATCH is
7832 as for mips_arg_info. */
7835 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7836 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7837 bfd_boolean lax_match
, bfd_boolean complete_p
)
7840 struct mips_arg_info arg
;
7841 const struct mips_operand
*operand
;
7844 imm_expr
.X_op
= O_absent
;
7845 offset_expr
.X_op
= O_absent
;
7846 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7847 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7848 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7850 create_insn (insn
, opcode
);
7851 /* When no opcode suffix is specified, assume ".xyzw". */
7852 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7853 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7855 insn
->insn_opcode
|= opcode_extra
;
7856 memset (&arg
, 0, sizeof (arg
));
7860 arg
.last_regno
= ILLEGAL_REG
;
7861 arg
.dest_regno
= ILLEGAL_REG
;
7862 arg
.lax_match
= lax_match
;
7863 for (args
= opcode
->args
;; ++args
)
7865 if (arg
.token
->type
== OT_END
)
7867 /* Handle unary instructions in which only one operand is given.
7868 The source is then the same as the destination. */
7869 if (arg
.opnum
== 1 && *args
== ',')
7871 operand
= (mips_opts
.micromips
7872 ? decode_micromips_operand (args
+ 1)
7873 : decode_mips_operand (args
+ 1));
7874 if (operand
&& mips_optional_operand_p (operand
))
7882 /* Treat elided base registers as $0. */
7883 if (strcmp (args
, "(b)") == 0)
7891 /* The register suffix is optional. */
7896 /* Fail the match if there were too few operands. */
7900 /* Successful match. */
7903 clear_insn_error ();
7904 if (arg
.dest_regno
== arg
.last_regno
7905 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7909 (0, _("source and destination must be different"));
7910 else if (arg
.last_regno
== 31)
7912 (0, _("a destination register must be supplied"));
7914 else if (arg
.last_regno
== 31
7915 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7916 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7917 set_insn_error (0, _("the source register must not be $31"));
7918 check_completed_insn (&arg
);
7922 /* Fail the match if the line has too many operands. */
7926 /* Handle characters that need to match exactly. */
7927 if (*args
== '(' || *args
== ')' || *args
== ',')
7929 if (match_char (&arg
, *args
))
7936 if (arg
.token
->type
== OT_DOUBLE_CHAR
7937 && arg
.token
->u
.ch
== *args
)
7945 /* Handle special macro operands. Work out the properties of
7954 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
7958 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
7967 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7971 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
7975 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
7981 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7983 imm_expr
.X_op
= O_constant
;
7985 normalize_constant_expr (&imm_expr
);
7989 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7991 /* Assume that the offset has been elided and that what
7992 we saw was a base register. The match will fail later
7993 if that assumption turns out to be wrong. */
7994 offset_expr
.X_op
= O_constant
;
7995 offset_expr
.X_add_number
= 0;
7999 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8001 normalize_address_expr (&offset_expr
);
8006 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8012 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8018 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8024 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8030 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8034 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8038 gas_assert (mips_opts
.micromips
);
8044 if (!forced_insn_length
)
8045 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8047 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8049 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8055 operand
= (mips_opts
.micromips
8056 ? decode_micromips_operand (args
)
8057 : decode_mips_operand (args
));
8061 /* Skip prefixes. */
8062 if (*args
== '+' || *args
== 'm' || *args
== '-')
8065 if (mips_optional_operand_p (operand
)
8067 && (arg
.token
[0].type
!= OT_REG
8068 || arg
.token
[1].type
== OT_END
))
8070 /* Assume that the register has been elided and is the
8071 same as the first operand. */
8076 if (!match_operand (&arg
, operand
))
8081 /* Like match_insn, but for MIPS16. */
8084 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8085 struct mips_operand_token
*tokens
)
8088 const struct mips_operand
*operand
;
8089 const struct mips_operand
*ext_operand
;
8090 int required_insn_length
;
8091 struct mips_arg_info arg
;
8094 if (forced_insn_length
)
8095 required_insn_length
= forced_insn_length
;
8096 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8097 required_insn_length
= 2;
8099 required_insn_length
= 0;
8101 create_insn (insn
, opcode
);
8102 imm_expr
.X_op
= O_absent
;
8103 offset_expr
.X_op
= O_absent
;
8104 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8105 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8106 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8109 memset (&arg
, 0, sizeof (arg
));
8113 arg
.last_regno
= ILLEGAL_REG
;
8114 arg
.dest_regno
= ILLEGAL_REG
;
8116 for (args
= opcode
->args
;; ++args
)
8120 if (arg
.token
->type
== OT_END
)
8124 /* Handle unary instructions in which only one operand is given.
8125 The source is then the same as the destination. */
8126 if (arg
.opnum
== 1 && *args
== ',')
8128 operand
= decode_mips16_operand (args
[1], FALSE
);
8129 if (operand
&& mips_optional_operand_p (operand
))
8137 /* Fail the match if there were too few operands. */
8141 /* Successful match. Stuff the immediate value in now, if
8143 clear_insn_error ();
8144 if (opcode
->pinfo
== INSN_MACRO
)
8146 gas_assert (relax_char
== 0 || relax_char
== 'p');
8147 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8150 && offset_expr
.X_op
== O_constant
8151 && calculate_reloc (*offset_reloc
,
8152 offset_expr
.X_add_number
,
8155 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8156 required_insn_length
, &insn
->insn_opcode
);
8157 offset_expr
.X_op
= O_absent
;
8158 *offset_reloc
= BFD_RELOC_UNUSED
;
8160 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8162 if (required_insn_length
== 2)
8163 set_insn_error (0, _("invalid unextended operand value"));
8166 forced_insn_length
= 4;
8167 insn
->insn_opcode
|= MIPS16_EXTEND
;
8170 else if (relax_char
)
8171 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8173 check_completed_insn (&arg
);
8177 /* Fail the match if the line has too many operands. */
8181 /* Handle characters that need to match exactly. */
8182 if (*args
== '(' || *args
== ')' || *args
== ',')
8184 if (match_char (&arg
, *args
))
8202 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8204 imm_expr
.X_op
= O_constant
;
8206 normalize_constant_expr (&imm_expr
);
8211 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8215 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8219 if (operand
->type
!= OP_PCREL
)
8221 ext_operand
= decode_mips16_operand (c
, TRUE
);
8222 if (operand
!= ext_operand
)
8224 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8226 offset_expr
.X_op
= O_constant
;
8227 offset_expr
.X_add_number
= 0;
8232 /* We need the OT_INTEGER check because some MIPS16
8233 immediate variants are listed before the register ones. */
8234 if (arg
.token
->type
!= OT_INTEGER
8235 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
8238 /* '8' is used for SLTI(U) and has traditionally not
8239 been allowed to take relocation operators. */
8240 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8241 && (ext_operand
->size
!= 16 || c
== '8'))
8249 if (mips_optional_operand_p (operand
)
8251 && (arg
.token
[0].type
!= OT_REG
8252 || arg
.token
[1].type
== OT_END
))
8254 /* Assume that the register has been elided and is the
8255 same as the first operand. */
8260 if (!match_operand (&arg
, operand
))
8265 /* Record that the current instruction is invalid for the current ISA. */
8268 match_invalid_for_isa (void)
8271 (0, _("opcode not supported on this processor: %s (%s)"),
8272 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8273 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8276 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8277 Return true if a definite match or failure was found, storing any match
8278 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8279 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8280 tried and failed to match under normal conditions and now want to try a
8281 more relaxed match. */
8284 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8285 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8286 int opcode_extra
, bfd_boolean lax_match
)
8288 const struct mips_opcode
*opcode
;
8289 const struct mips_opcode
*invalid_delay_slot
;
8290 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8292 /* Search for a match, ignoring alternatives that don't satisfy the
8293 current ISA or forced_length. */
8294 invalid_delay_slot
= 0;
8295 seen_valid_for_isa
= FALSE
;
8296 seen_valid_for_size
= FALSE
;
8300 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8301 if (is_opcode_valid (opcode
))
8303 seen_valid_for_isa
= TRUE
;
8304 if (is_size_valid (opcode
))
8306 bfd_boolean delay_slot_ok
;
8308 seen_valid_for_size
= TRUE
;
8309 delay_slot_ok
= is_delay_slot_valid (opcode
);
8310 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8311 lax_match
, delay_slot_ok
))
8315 if (!invalid_delay_slot
)
8316 invalid_delay_slot
= opcode
;
8325 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8327 /* If the only matches we found had the wrong length for the delay slot,
8328 pick the first such match. We'll issue an appropriate warning later. */
8329 if (invalid_delay_slot
)
8331 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8337 /* Handle the case where we didn't try to match an instruction because
8338 all the alternatives were incompatible with the current ISA. */
8339 if (!seen_valid_for_isa
)
8341 match_invalid_for_isa ();
8345 /* Handle the case where we didn't try to match an instruction because
8346 all the alternatives were of the wrong size. */
8347 if (!seen_valid_for_size
)
8349 if (mips_opts
.insn32
)
8350 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8353 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8354 8 * forced_insn_length
);
8361 /* Like match_insns, but for MIPS16. */
8364 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8365 struct mips_operand_token
*tokens
)
8367 const struct mips_opcode
*opcode
;
8368 bfd_boolean seen_valid_for_isa
;
8369 bfd_boolean seen_valid_for_size
;
8371 /* Search for a match, ignoring alternatives that don't satisfy the
8372 current ISA. There are no separate entries for extended forms so
8373 we deal with forced_length later. */
8374 seen_valid_for_isa
= FALSE
;
8375 seen_valid_for_size
= FALSE
;
8379 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8380 if (is_opcode_valid_16 (opcode
))
8382 seen_valid_for_isa
= TRUE
;
8383 if (is_size_valid_16 (opcode
))
8385 seen_valid_for_size
= TRUE
;
8386 if (match_mips16_insn (insn
, opcode
, tokens
))
8392 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8393 && strcmp (opcode
->name
, first
->name
) == 0);
8395 /* Handle the case where we didn't try to match an instruction because
8396 all the alternatives were incompatible with the current ISA. */
8397 if (!seen_valid_for_isa
)
8399 match_invalid_for_isa ();
8403 /* Handle the case where we didn't try to match an instruction because
8404 all the alternatives were of the wrong size. */
8405 if (!seen_valid_for_size
)
8407 if (forced_insn_length
== 2)
8409 (0, _("unrecognized unextended version of MIPS16 opcode"));
8412 (0, _("unrecognized extended version of MIPS16 opcode"));
8419 /* Set up global variables for the start of a new macro. */
8424 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8425 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8426 sizeof (mips_macro_warning
.first_insn_sizes
));
8427 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8428 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8429 && delayed_branch_p (&history
[0]));
8431 && history
[0].frag
->fr_type
== rs_machine_dependent
8432 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8433 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8434 mips_macro_warning
.delay_slot_length
= 0;
8436 switch (history
[0].insn_mo
->pinfo2
8437 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8439 case INSN2_BRANCH_DELAY_32BIT
:
8440 mips_macro_warning
.delay_slot_length
= 4;
8442 case INSN2_BRANCH_DELAY_16BIT
:
8443 mips_macro_warning
.delay_slot_length
= 2;
8446 mips_macro_warning
.delay_slot_length
= 0;
8449 mips_macro_warning
.first_frag
= NULL
;
8452 /* Given that a macro is longer than one instruction or of the wrong size,
8453 return the appropriate warning for it. Return null if no warning is
8454 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8455 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8456 and RELAX_NOMACRO. */
8459 macro_warning (relax_substateT subtype
)
8461 if (subtype
& RELAX_DELAY_SLOT
)
8462 return _("macro instruction expanded into multiple instructions"
8463 " in a branch delay slot");
8464 else if (subtype
& RELAX_NOMACRO
)
8465 return _("macro instruction expanded into multiple instructions");
8466 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8467 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8468 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8469 ? _("macro instruction expanded into a wrong size instruction"
8470 " in a 16-bit branch delay slot")
8471 : _("macro instruction expanded into a wrong size instruction"
8472 " in a 32-bit branch delay slot"));
8477 /* Finish up a macro. Emit warnings as appropriate. */
8482 /* Relaxation warning flags. */
8483 relax_substateT subtype
= 0;
8485 /* Check delay slot size requirements. */
8486 if (mips_macro_warning
.delay_slot_length
== 2)
8487 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8488 if (mips_macro_warning
.delay_slot_length
!= 0)
8490 if (mips_macro_warning
.delay_slot_length
8491 != mips_macro_warning
.first_insn_sizes
[0])
8492 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8493 if (mips_macro_warning
.delay_slot_length
8494 != mips_macro_warning
.first_insn_sizes
[1])
8495 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8498 /* Check instruction count requirements. */
8499 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8501 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8502 subtype
|= RELAX_SECOND_LONGER
;
8503 if (mips_opts
.warn_about_macros
)
8504 subtype
|= RELAX_NOMACRO
;
8505 if (mips_macro_warning
.delay_slot_p
)
8506 subtype
|= RELAX_DELAY_SLOT
;
8509 /* If both alternatives fail to fill a delay slot correctly,
8510 emit the warning now. */
8511 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8512 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8517 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8518 | RELAX_DELAY_SLOT_SIZE_FIRST
8519 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8520 msg
= macro_warning (s
);
8522 as_warn ("%s", msg
);
8526 /* If both implementations are longer than 1 instruction, then emit the
8528 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8533 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8534 msg
= macro_warning (s
);
8536 as_warn ("%s", msg
);
8540 /* If any flags still set, then one implementation might need a warning
8541 and the other either will need one of a different kind or none at all.
8542 Pass any remaining flags over to relaxation. */
8543 if (mips_macro_warning
.first_frag
!= NULL
)
8544 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8547 /* Instruction operand formats used in macros that vary between
8548 standard MIPS and microMIPS code. */
8550 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8551 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8552 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8553 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8554 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8555 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8556 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8557 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8559 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8560 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8561 : cop12_fmt[mips_opts.micromips])
8562 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8563 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8564 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8565 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8566 : mem12_fmt[mips_opts.micromips])
8567 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8568 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8569 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8571 /* Read a macro's relocation codes from *ARGS and store them in *R.
8572 The first argument in *ARGS will be either the code for a single
8573 relocation or -1 followed by the three codes that make up a
8574 composite relocation. */
8577 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8581 next
= va_arg (*args
, int);
8583 r
[0] = (bfd_reloc_code_real_type
) next
;
8586 for (i
= 0; i
< 3; i
++)
8587 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8588 /* This function is only used for 16-bit relocation fields.
8589 To make the macro code simpler, treat an unrelocated value
8590 in the same way as BFD_RELOC_LO16. */
8591 if (r
[0] == BFD_RELOC_UNUSED
)
8592 r
[0] = BFD_RELOC_LO16
;
8596 /* Build an instruction created by a macro expansion. This is passed
8597 a pointer to the count of instructions created so far, an
8598 expression, the name of the instruction to build, an operand format
8599 string, and corresponding arguments. */
8602 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8604 const struct mips_opcode
*mo
= NULL
;
8605 bfd_reloc_code_real_type r
[3];
8606 const struct mips_opcode
*amo
;
8607 const struct mips_operand
*operand
;
8608 struct hash_control
*hash
;
8609 struct mips_cl_insn insn
;
8613 va_start (args
, fmt
);
8615 if (mips_opts
.mips16
)
8617 mips16_macro_build (ep
, name
, fmt
, &args
);
8622 r
[0] = BFD_RELOC_UNUSED
;
8623 r
[1] = BFD_RELOC_UNUSED
;
8624 r
[2] = BFD_RELOC_UNUSED
;
8625 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
8626 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
8628 gas_assert (strcmp (name
, amo
->name
) == 0);
8632 /* Search until we get a match for NAME. It is assumed here that
8633 macros will never generate MDMX, MIPS-3D, or MT instructions.
8634 We try to match an instruction that fulfills the branch delay
8635 slot instruction length requirement (if any) of the previous
8636 instruction. While doing this we record the first instruction
8637 seen that matches all the other conditions and use it anyway
8638 if the requirement cannot be met; we will issue an appropriate
8639 warning later on. */
8640 if (strcmp (fmt
, amo
->args
) == 0
8641 && amo
->pinfo
!= INSN_MACRO
8642 && is_opcode_valid (amo
)
8643 && is_size_valid (amo
))
8645 if (is_delay_slot_valid (amo
))
8655 gas_assert (amo
->name
);
8657 while (strcmp (name
, amo
->name
) == 0);
8660 create_insn (&insn
, mo
);
8673 macro_read_relocs (&args
, r
);
8674 gas_assert (*r
== BFD_RELOC_GPREL16
8675 || *r
== BFD_RELOC_MIPS_HIGHER
8676 || *r
== BFD_RELOC_HI16_S
8677 || *r
== BFD_RELOC_LO16
8678 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
8682 macro_read_relocs (&args
, r
);
8686 macro_read_relocs (&args
, r
);
8687 gas_assert (ep
!= NULL
8688 && (ep
->X_op
== O_constant
8689 || (ep
->X_op
== O_symbol
8690 && (*r
== BFD_RELOC_MIPS_HIGHEST
8691 || *r
== BFD_RELOC_HI16_S
8692 || *r
== BFD_RELOC_HI16
8693 || *r
== BFD_RELOC_GPREL16
8694 || *r
== BFD_RELOC_MIPS_GOT_HI16
8695 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
8699 gas_assert (ep
!= NULL
);
8702 * This allows macro() to pass an immediate expression for
8703 * creating short branches without creating a symbol.
8705 * We don't allow branch relaxation for these branches, as
8706 * they should only appear in ".set nomacro" anyway.
8708 if (ep
->X_op
== O_constant
)
8710 /* For microMIPS we always use relocations for branches.
8711 So we should not resolve immediate values. */
8712 gas_assert (!mips_opts
.micromips
);
8714 if ((ep
->X_add_number
& 3) != 0)
8715 as_bad (_("branch to misaligned address (0x%lx)"),
8716 (unsigned long) ep
->X_add_number
);
8717 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
8718 as_bad (_("branch address range overflow (0x%lx)"),
8719 (unsigned long) ep
->X_add_number
);
8720 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8724 *r
= BFD_RELOC_16_PCREL_S2
;
8728 gas_assert (ep
!= NULL
);
8729 *r
= BFD_RELOC_MIPS_JMP
;
8733 operand
= (mips_opts
.micromips
8734 ? decode_micromips_operand (fmt
)
8735 : decode_mips_operand (fmt
));
8739 uval
= va_arg (args
, int);
8740 if (operand
->type
== OP_CLO_CLZ_DEST
)
8741 uval
|= (uval
<< 5);
8742 insn_insert_operand (&insn
, operand
, uval
);
8744 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
8750 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8752 append_insn (&insn
, ep
, r
, TRUE
);
8756 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8759 struct mips_opcode
*mo
;
8760 struct mips_cl_insn insn
;
8761 const struct mips_operand
*operand
;
8762 bfd_reloc_code_real_type r
[3]
8763 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8765 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8767 gas_assert (strcmp (name
, mo
->name
) == 0);
8769 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8772 gas_assert (mo
->name
);
8773 gas_assert (strcmp (name
, mo
->name
) == 0);
8776 create_insn (&insn
, mo
);
8813 gas_assert (ep
!= NULL
);
8815 if (ep
->X_op
!= O_constant
)
8816 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8817 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8819 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8821 *r
= BFD_RELOC_UNUSED
;
8827 operand
= decode_mips16_operand (c
, FALSE
);
8831 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8836 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8838 append_insn (&insn
, ep
, r
, TRUE
);
8842 * Generate a "jalr" instruction with a relocation hint to the called
8843 * function. This occurs in NewABI PIC code.
8846 macro_build_jalr (expressionS
*ep
, int cprestore
)
8848 static const bfd_reloc_code_real_type jalr_relocs
[2]
8849 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8850 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8854 if (MIPS_JALR_HINT_P (ep
))
8859 if (mips_opts
.micromips
)
8861 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8862 ? "jalr" : "jalrs");
8863 if (MIPS_JALR_HINT_P (ep
)
8865 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8866 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8868 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8871 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8872 if (MIPS_JALR_HINT_P (ep
))
8873 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8877 * Generate a "lui" instruction.
8880 macro_build_lui (expressionS
*ep
, int regnum
)
8882 gas_assert (! mips_opts
.mips16
);
8884 if (ep
->X_op
!= O_constant
)
8886 gas_assert (ep
->X_op
== O_symbol
);
8887 /* _gp_disp is a special case, used from s_cpload.
8888 __gnu_local_gp is used if mips_no_shared. */
8889 gas_assert (mips_pic
== NO_PIC
8891 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8892 || (! mips_in_shared
8893 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8894 "__gnu_local_gp") == 0));
8897 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8900 /* Generate a sequence of instructions to do a load or store from a constant
8901 offset off of a base register (breg) into/from a target register (treg),
8902 using AT if necessary. */
8904 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8905 int treg
, int breg
, int dbl
)
8907 gas_assert (ep
->X_op
== O_constant
);
8909 /* Sign-extending 32-bit constants makes their handling easier. */
8911 normalize_constant_expr (ep
);
8913 /* Right now, this routine can only handle signed 32-bit constants. */
8914 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8915 as_warn (_("operand overflow"));
8917 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8919 /* Signed 16-bit offset will fit in the op. Easy! */
8920 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8924 /* 32-bit offset, need multiple instructions and AT, like:
8925 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8926 addu $tempreg,$tempreg,$breg
8927 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8928 to handle the complete offset. */
8929 macro_build_lui (ep
, AT
);
8930 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8931 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8934 as_bad (_("macro used $at after \".set noat\""));
8939 * Generates code to set the $at register to true (one)
8940 * if reg is less than the immediate expression.
8943 set_at (int reg
, int unsignedp
)
8945 if (imm_expr
.X_add_number
>= -0x8000
8946 && imm_expr
.X_add_number
< 0x8000)
8947 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8948 AT
, reg
, BFD_RELOC_LO16
);
8951 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
8952 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8956 /* Count the leading zeroes by performing a binary chop. This is a
8957 bulky bit of source, but performance is a LOT better for the
8958 majority of values than a simple loop to count the bits:
8959 for (lcnt = 0; (lcnt < 32); lcnt++)
8960 if ((v) & (1 << (31 - lcnt)))
8962 However it is not code size friendly, and the gain will drop a bit
8963 on certain cached systems.
8965 #define COUNT_TOP_ZEROES(v) \
8966 (((v) & ~0xffff) == 0 \
8967 ? ((v) & ~0xff) == 0 \
8968 ? ((v) & ~0xf) == 0 \
8969 ? ((v) & ~0x3) == 0 \
8970 ? ((v) & ~0x1) == 0 \
8975 : ((v) & ~0x7) == 0 \
8978 : ((v) & ~0x3f) == 0 \
8979 ? ((v) & ~0x1f) == 0 \
8982 : ((v) & ~0x7f) == 0 \
8985 : ((v) & ~0xfff) == 0 \
8986 ? ((v) & ~0x3ff) == 0 \
8987 ? ((v) & ~0x1ff) == 0 \
8990 : ((v) & ~0x7ff) == 0 \
8993 : ((v) & ~0x3fff) == 0 \
8994 ? ((v) & ~0x1fff) == 0 \
8997 : ((v) & ~0x7fff) == 0 \
9000 : ((v) & ~0xffffff) == 0 \
9001 ? ((v) & ~0xfffff) == 0 \
9002 ? ((v) & ~0x3ffff) == 0 \
9003 ? ((v) & ~0x1ffff) == 0 \
9006 : ((v) & ~0x7ffff) == 0 \
9009 : ((v) & ~0x3fffff) == 0 \
9010 ? ((v) & ~0x1fffff) == 0 \
9013 : ((v) & ~0x7fffff) == 0 \
9016 : ((v) & ~0xfffffff) == 0 \
9017 ? ((v) & ~0x3ffffff) == 0 \
9018 ? ((v) & ~0x1ffffff) == 0 \
9021 : ((v) & ~0x7ffffff) == 0 \
9024 : ((v) & ~0x3fffffff) == 0 \
9025 ? ((v) & ~0x1fffffff) == 0 \
9028 : ((v) & ~0x7fffffff) == 0 \
9033 * This routine generates the least number of instructions necessary to load
9034 * an absolute expression value into a register.
9037 load_register (int reg
, expressionS
*ep
, int dbl
)
9040 expressionS hi32
, lo32
;
9042 if (ep
->X_op
!= O_big
)
9044 gas_assert (ep
->X_op
== O_constant
);
9046 /* Sign-extending 32-bit constants makes their handling easier. */
9048 normalize_constant_expr (ep
);
9050 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9052 /* We can handle 16 bit signed values with an addiu to
9053 $zero. No need to ever use daddiu here, since $zero and
9054 the result are always correct in 32 bit mode. */
9055 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9058 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9060 /* We can handle 16 bit unsigned values with an ori to
9062 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9065 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9067 /* 32 bit values require an lui. */
9068 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9069 if ((ep
->X_add_number
& 0xffff) != 0)
9070 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9075 /* The value is larger than 32 bits. */
9077 if (!dbl
|| GPR_SIZE
== 32)
9081 sprintf_vma (value
, ep
->X_add_number
);
9082 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9083 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9087 if (ep
->X_op
!= O_big
)
9090 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9091 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9092 hi32
.X_add_number
&= 0xffffffff;
9094 lo32
.X_add_number
&= 0xffffffff;
9098 gas_assert (ep
->X_add_number
> 2);
9099 if (ep
->X_add_number
== 3)
9100 generic_bignum
[3] = 0;
9101 else if (ep
->X_add_number
> 4)
9102 as_bad (_("number larger than 64 bits"));
9103 lo32
.X_op
= O_constant
;
9104 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9105 hi32
.X_op
= O_constant
;
9106 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9109 if (hi32
.X_add_number
== 0)
9114 unsigned long hi
, lo
;
9116 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9118 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9120 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9123 if (lo32
.X_add_number
& 0x80000000)
9125 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9126 if (lo32
.X_add_number
& 0xffff)
9127 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9132 /* Check for 16bit shifted constant. We know that hi32 is
9133 non-zero, so start the mask on the first bit of the hi32
9138 unsigned long himask
, lomask
;
9142 himask
= 0xffff >> (32 - shift
);
9143 lomask
= (0xffff << shift
) & 0xffffffff;
9147 himask
= 0xffff << (shift
- 32);
9150 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9151 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9155 tmp
.X_op
= O_constant
;
9157 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9158 | (lo32
.X_add_number
>> shift
));
9160 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9161 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9162 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9163 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9168 while (shift
<= (64 - 16));
9170 /* Find the bit number of the lowest one bit, and store the
9171 shifted value in hi/lo. */
9172 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9173 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9177 while ((lo
& 1) == 0)
9182 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9188 while ((hi
& 1) == 0)
9197 /* Optimize if the shifted value is a (power of 2) - 1. */
9198 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9199 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9201 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9206 /* This instruction will set the register to be all
9208 tmp
.X_op
= O_constant
;
9209 tmp
.X_add_number
= (offsetT
) -1;
9210 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9214 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9215 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9217 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9218 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9223 /* Sign extend hi32 before calling load_register, because we can
9224 generally get better code when we load a sign extended value. */
9225 if ((hi32
.X_add_number
& 0x80000000) != 0)
9226 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9227 load_register (reg
, &hi32
, 0);
9230 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9234 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9242 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9244 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9245 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9251 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9255 mid16
.X_add_number
>>= 16;
9256 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9257 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9260 if ((lo32
.X_add_number
& 0xffff) != 0)
9261 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9265 load_delay_nop (void)
9267 if (!gpr_interlocks
)
9268 macro_build (NULL
, "nop", "");
9271 /* Load an address into a register. */
9274 load_address (int reg
, expressionS
*ep
, int *used_at
)
9276 if (ep
->X_op
!= O_constant
9277 && ep
->X_op
!= O_symbol
)
9279 as_bad (_("expression too complex"));
9280 ep
->X_op
= O_constant
;
9283 if (ep
->X_op
== O_constant
)
9285 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9289 if (mips_pic
== NO_PIC
)
9291 /* If this is a reference to a GP relative symbol, we want
9292 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9294 lui $reg,<sym> (BFD_RELOC_HI16_S)
9295 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9296 If we have an addend, we always use the latter form.
9298 With 64bit address space and a usable $at we want
9299 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9300 lui $at,<sym> (BFD_RELOC_HI16_S)
9301 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9302 daddiu $at,<sym> (BFD_RELOC_LO16)
9306 If $at is already in use, we use a path which is suboptimal
9307 on superscalar processors.
9308 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9309 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9311 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9313 daddiu $reg,<sym> (BFD_RELOC_LO16)
9315 For GP relative symbols in 64bit address space we can use
9316 the same sequence as in 32bit address space. */
9317 if (HAVE_64BIT_SYMBOLS
)
9319 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9320 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9322 relax_start (ep
->X_add_symbol
);
9323 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9324 mips_gp_register
, BFD_RELOC_GPREL16
);
9328 if (*used_at
== 0 && mips_opts
.at
)
9330 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9331 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9332 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9333 BFD_RELOC_MIPS_HIGHER
);
9334 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9335 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9336 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9341 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9342 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9343 BFD_RELOC_MIPS_HIGHER
);
9344 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9345 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9346 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9347 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9350 if (mips_relax
.sequence
)
9355 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9356 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9358 relax_start (ep
->X_add_symbol
);
9359 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9360 mips_gp_register
, BFD_RELOC_GPREL16
);
9363 macro_build_lui (ep
, reg
);
9364 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9365 reg
, reg
, BFD_RELOC_LO16
);
9366 if (mips_relax
.sequence
)
9370 else if (!mips_big_got
)
9374 /* If this is a reference to an external symbol, we want
9375 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9377 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9379 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9380 If there is a constant, it must be added in after.
9382 If we have NewABI, we want
9383 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9384 unless we're referencing a global symbol with a non-zero
9385 offset, in which case cst must be added separately. */
9388 if (ep
->X_add_number
)
9390 ex
.X_add_number
= ep
->X_add_number
;
9391 ep
->X_add_number
= 0;
9392 relax_start (ep
->X_add_symbol
);
9393 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9394 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9395 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9396 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9397 ex
.X_op
= O_constant
;
9398 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9399 reg
, reg
, BFD_RELOC_LO16
);
9400 ep
->X_add_number
= ex
.X_add_number
;
9403 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9404 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9405 if (mips_relax
.sequence
)
9410 ex
.X_add_number
= ep
->X_add_number
;
9411 ep
->X_add_number
= 0;
9412 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9413 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9415 relax_start (ep
->X_add_symbol
);
9417 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9421 if (ex
.X_add_number
!= 0)
9423 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9424 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9425 ex
.X_op
= O_constant
;
9426 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9427 reg
, reg
, BFD_RELOC_LO16
);
9431 else if (mips_big_got
)
9435 /* This is the large GOT case. If this is a reference to an
9436 external symbol, we want
9437 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9439 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9441 Otherwise, for a reference to a local symbol in old ABI, we want
9442 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9444 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9445 If there is a constant, it must be added in after.
9447 In the NewABI, for local symbols, with or without offsets, we want:
9448 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9449 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9453 ex
.X_add_number
= ep
->X_add_number
;
9454 ep
->X_add_number
= 0;
9455 relax_start (ep
->X_add_symbol
);
9456 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9457 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9458 reg
, reg
, mips_gp_register
);
9459 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9460 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9461 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9462 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9463 else if (ex
.X_add_number
)
9465 ex
.X_op
= O_constant
;
9466 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9470 ep
->X_add_number
= ex
.X_add_number
;
9472 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9473 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9474 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9475 BFD_RELOC_MIPS_GOT_OFST
);
9480 ex
.X_add_number
= ep
->X_add_number
;
9481 ep
->X_add_number
= 0;
9482 relax_start (ep
->X_add_symbol
);
9483 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9484 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9485 reg
, reg
, mips_gp_register
);
9486 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9487 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9489 if (reg_needs_delay (mips_gp_register
))
9491 /* We need a nop before loading from $gp. This special
9492 check is required because the lui which starts the main
9493 instruction stream does not refer to $gp, and so will not
9494 insert the nop which may be required. */
9495 macro_build (NULL
, "nop", "");
9497 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9498 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9500 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9504 if (ex
.X_add_number
!= 0)
9506 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9507 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9508 ex
.X_op
= O_constant
;
9509 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9517 if (!mips_opts
.at
&& *used_at
== 1)
9518 as_bad (_("macro used $at after \".set noat\""));
9521 /* Move the contents of register SOURCE into register DEST. */
9524 move_register (int dest
, int source
)
9526 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9527 instruction specifically requires a 32-bit one. */
9528 if (mips_opts
.micromips
9529 && !mips_opts
.insn32
9530 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9531 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9533 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9536 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9537 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9538 The two alternatives are:
9540 Global symbol Local symbol
9541 ------------- ------------
9542 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9544 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9546 load_got_offset emits the first instruction and add_got_offset
9547 emits the second for a 16-bit offset or add_got_offset_hilo emits
9548 a sequence to add a 32-bit offset using a scratch register. */
9551 load_got_offset (int dest
, expressionS
*local
)
9556 global
.X_add_number
= 0;
9558 relax_start (local
->X_add_symbol
);
9559 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9560 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9562 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9563 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9568 add_got_offset (int dest
, expressionS
*local
)
9572 global
.X_op
= O_constant
;
9573 global
.X_op_symbol
= NULL
;
9574 global
.X_add_symbol
= NULL
;
9575 global
.X_add_number
= local
->X_add_number
;
9577 relax_start (local
->X_add_symbol
);
9578 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9579 dest
, dest
, BFD_RELOC_LO16
);
9581 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9586 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9589 int hold_mips_optimize
;
9591 global
.X_op
= O_constant
;
9592 global
.X_op_symbol
= NULL
;
9593 global
.X_add_symbol
= NULL
;
9594 global
.X_add_number
= local
->X_add_number
;
9596 relax_start (local
->X_add_symbol
);
9597 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
9599 /* Set mips_optimize around the lui instruction to avoid
9600 inserting an unnecessary nop after the lw. */
9601 hold_mips_optimize
= mips_optimize
;
9603 macro_build_lui (&global
, tmp
);
9604 mips_optimize
= hold_mips_optimize
;
9605 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
9608 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
9611 /* Emit a sequence of instructions to emulate a branch likely operation.
9612 BR is an ordinary branch corresponding to one to be emulated. BRNEG
9613 is its complementing branch with the original condition negated.
9614 CALL is set if the original branch specified the link operation.
9615 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
9617 Code like this is produced in the noreorder mode:
9622 delay slot (executed only if branch taken)
9630 delay slot (executed only if branch taken)
9633 In the reorder mode the delay slot would be filled with a nop anyway,
9634 so code produced is simply:
9639 This function is used when producing code for the microMIPS ASE that
9640 does not implement branch likely instructions in hardware. */
9643 macro_build_branch_likely (const char *br
, const char *brneg
,
9644 int call
, expressionS
*ep
, const char *fmt
,
9645 unsigned int sreg
, unsigned int treg
)
9647 int noreorder
= mips_opts
.noreorder
;
9650 gas_assert (mips_opts
.micromips
);
9654 micromips_label_expr (&expr1
);
9655 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
9656 macro_build (NULL
, "nop", "");
9657 macro_build (ep
, call
? "bal" : "b", "p");
9659 /* Set to true so that append_insn adds a label. */
9660 emit_branch_likely_macro
= TRUE
;
9664 macro_build (ep
, br
, fmt
, sreg
, treg
);
9665 macro_build (NULL
, "nop", "");
9670 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
9671 the condition code tested. EP specifies the branch target. */
9674 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
9701 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
9704 /* Emit a two-argument branch macro specified by TYPE, using SREG as
9705 the register tested. EP specifies the branch target. */
9708 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
9710 const char *brneg
= NULL
;
9720 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9724 gas_assert (mips_opts
.micromips
);
9725 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9733 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9740 br
= mips_opts
.micromips
? "blez" : "blezl";
9747 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9751 gas_assert (mips_opts
.micromips
);
9752 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9759 if (mips_opts
.micromips
&& brneg
)
9760 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9762 macro_build (ep
, br
, "s,p", sreg
);
9765 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9766 TREG as the registers tested. EP specifies the branch target. */
9769 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9770 unsigned int sreg
, unsigned int treg
)
9772 const char *brneg
= NULL
;
9784 br
= mips_opts
.micromips
? "beq" : "beql";
9793 br
= mips_opts
.micromips
? "bne" : "bnel";
9799 if (mips_opts
.micromips
&& brneg
)
9800 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9802 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9805 /* Return the high part that should be loaded in order to make the low
9806 part of VALUE accessible using an offset of OFFBITS bits. */
9809 offset_high_part (offsetT value
, unsigned int offbits
)
9816 bias
= 1 << (offbits
- 1);
9817 low_mask
= bias
* 2 - 1;
9818 return (value
+ bias
) & ~low_mask
;
9821 /* Return true if the value stored in offset_expr and offset_reloc
9822 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9823 amount that the caller wants to add without inducing overflow
9824 and ALIGN is the known alignment of the value in bytes. */
9827 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9831 /* Accept any relocation operator if overflow isn't a concern. */
9832 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9835 /* These relocations are guaranteed not to overflow in correct links. */
9836 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9837 || gprel16_reloc_p (*offset_reloc
))
9840 if (offset_expr
.X_op
== O_constant
9841 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9842 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9849 * This routine implements the seemingly endless macro or synthesized
9850 * instructions and addressing modes in the mips assembly language. Many
9851 * of these macros are simple and are similar to each other. These could
9852 * probably be handled by some kind of table or grammar approach instead of
9853 * this verbose method. Others are not simple macros but are more like
9854 * optimizing code generation.
9855 * One interesting optimization is when several store macros appear
9856 * consecutively that would load AT with the upper half of the same address.
9857 * The ensuing load upper instructions are omitted. This implies some kind
9858 * of global optimization. We currently only optimize within a single macro.
9859 * For many of the load and store macros if the address is specified as a
9860 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9861 * first load register 'at' with zero and use it as the base register. The
9862 * mips assembler simply uses register $zero. Just one tiny optimization
9866 macro (struct mips_cl_insn
*ip
, char *str
)
9868 const struct mips_operand_array
*operands
;
9869 unsigned int breg
, i
;
9870 unsigned int tempreg
;
9873 expressionS label_expr
;
9888 bfd_boolean large_offset
;
9890 int hold_mips_optimize
;
9892 unsigned int op
[MAX_OPERANDS
];
9894 gas_assert (! mips_opts
.mips16
);
9896 operands
= insn_operands (ip
);
9897 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9898 if (operands
->operand
[i
])
9899 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9903 mask
= ip
->insn_mo
->mask
;
9905 label_expr
.X_op
= O_constant
;
9906 label_expr
.X_op_symbol
= NULL
;
9907 label_expr
.X_add_symbol
= NULL
;
9908 label_expr
.X_add_number
= 0;
9910 expr1
.X_op
= O_constant
;
9911 expr1
.X_op_symbol
= NULL
;
9912 expr1
.X_add_symbol
= NULL
;
9913 expr1
.X_add_number
= 1;
9930 if (mips_opts
.micromips
)
9931 micromips_label_expr (&label_expr
);
9933 label_expr
.X_add_number
= 8;
9934 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9936 macro_build (NULL
, "nop", "");
9938 move_register (op
[0], op
[1]);
9939 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9940 if (mips_opts
.micromips
)
9941 micromips_add_label ();
9958 if (!mips_opts
.micromips
)
9960 if (imm_expr
.X_add_number
>= -0x200
9961 && imm_expr
.X_add_number
< 0x200)
9963 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9964 (int) imm_expr
.X_add_number
);
9973 if (imm_expr
.X_add_number
>= -0x8000
9974 && imm_expr
.X_add_number
< 0x8000)
9976 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9981 load_register (AT
, &imm_expr
, dbl
);
9982 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10001 if (imm_expr
.X_add_number
>= 0
10002 && imm_expr
.X_add_number
< 0x10000)
10004 if (mask
!= M_NOR_I
)
10005 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10008 macro_build (&imm_expr
, "ori", "t,r,i",
10009 op
[0], op
[1], BFD_RELOC_LO16
);
10010 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10016 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10017 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10021 switch (imm_expr
.X_add_number
)
10024 macro_build (NULL
, "nop", "");
10027 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10031 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10032 (int) imm_expr
.X_add_number
);
10035 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10036 (unsigned long) imm_expr
.X_add_number
);
10045 gas_assert (mips_opts
.micromips
);
10046 macro_build_branch_ccl (mask
, &offset_expr
,
10047 EXTRACT_OPERAND (1, BCC
, *ip
));
10054 if (imm_expr
.X_add_number
== 0)
10060 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10062 /* Fall through. */
10065 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10070 /* Fall through. */
10073 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10074 else if (op
[0] == 0)
10075 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10079 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10080 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10081 &offset_expr
, AT
, ZERO
);
10091 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10096 /* Fall through. */
10098 /* Check for > max integer. */
10099 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10102 /* Result is always false. */
10104 macro_build (NULL
, "nop", "");
10106 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10109 ++imm_expr
.X_add_number
;
10113 if (mask
== M_BGEL_I
)
10115 if (imm_expr
.X_add_number
== 0)
10117 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10118 &offset_expr
, op
[0]);
10121 if (imm_expr
.X_add_number
== 1)
10123 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10124 &offset_expr
, op
[0]);
10127 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10130 /* result is always true */
10131 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10132 macro_build (&offset_expr
, "b", "p");
10137 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10138 &offset_expr
, AT
, ZERO
);
10143 /* Fall through. */
10147 else if (op
[0] == 0)
10148 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10149 &offset_expr
, ZERO
, op
[1]);
10153 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10154 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10155 &offset_expr
, AT
, ZERO
);
10161 /* Fall through. */
10165 && imm_expr
.X_add_number
== -1))
10167 ++imm_expr
.X_add_number
;
10171 if (mask
== M_BGEUL_I
)
10173 if (imm_expr
.X_add_number
== 0)
10175 else if (imm_expr
.X_add_number
== 1)
10176 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10177 &offset_expr
, op
[0], ZERO
);
10182 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10183 &offset_expr
, AT
, ZERO
);
10189 /* Fall through. */
10192 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10193 else if (op
[0] == 0)
10194 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10198 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10199 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10200 &offset_expr
, AT
, ZERO
);
10206 /* Fall through. */
10209 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10210 &offset_expr
, op
[0], ZERO
);
10211 else if (op
[0] == 0)
10216 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10217 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10218 &offset_expr
, AT
, ZERO
);
10224 /* Fall through. */
10227 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10228 else if (op
[0] == 0)
10229 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10233 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10234 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10235 &offset_expr
, AT
, ZERO
);
10241 /* Fall through. */
10243 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10245 ++imm_expr
.X_add_number
;
10249 if (mask
== M_BLTL_I
)
10251 if (imm_expr
.X_add_number
== 0)
10252 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10253 else if (imm_expr
.X_add_number
== 1)
10254 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10259 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10260 &offset_expr
, AT
, ZERO
);
10266 /* Fall through. */
10269 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10270 &offset_expr
, op
[0], ZERO
);
10271 else if (op
[0] == 0)
10276 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10277 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10278 &offset_expr
, AT
, ZERO
);
10284 /* Fall through. */
10288 && imm_expr
.X_add_number
== -1))
10290 ++imm_expr
.X_add_number
;
10294 if (mask
== M_BLTUL_I
)
10296 if (imm_expr
.X_add_number
== 0)
10298 else if (imm_expr
.X_add_number
== 1)
10299 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10300 &offset_expr
, op
[0], ZERO
);
10305 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10306 &offset_expr
, AT
, ZERO
);
10312 /* Fall through. */
10315 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10316 else if (op
[0] == 0)
10317 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10321 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10322 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10323 &offset_expr
, AT
, ZERO
);
10329 /* Fall through. */
10333 else if (op
[0] == 0)
10334 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10335 &offset_expr
, ZERO
, op
[1]);
10339 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10340 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10341 &offset_expr
, AT
, ZERO
);
10347 /* Fall through. */
10353 /* Fall through. */
10359 as_warn (_("divide by zero"));
10361 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10363 macro_build (NULL
, "break", BRK_FMT
, 7);
10367 start_noreorder ();
10370 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10371 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10375 if (mips_opts
.micromips
)
10376 micromips_label_expr (&label_expr
);
10378 label_expr
.X_add_number
= 8;
10379 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10380 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10381 macro_build (NULL
, "break", BRK_FMT
, 7);
10382 if (mips_opts
.micromips
)
10383 micromips_add_label ();
10385 expr1
.X_add_number
= -1;
10387 load_register (AT
, &expr1
, dbl
);
10388 if (mips_opts
.micromips
)
10389 micromips_label_expr (&label_expr
);
10391 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10392 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10395 expr1
.X_add_number
= 1;
10396 load_register (AT
, &expr1
, dbl
);
10397 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10401 expr1
.X_add_number
= 0x80000000;
10402 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10406 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10407 /* We want to close the noreorder block as soon as possible, so
10408 that later insns are available for delay slot filling. */
10413 if (mips_opts
.micromips
)
10414 micromips_label_expr (&label_expr
);
10416 label_expr
.X_add_number
= 8;
10417 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10418 macro_build (NULL
, "nop", "");
10420 /* We want to close the noreorder block as soon as possible, so
10421 that later insns are available for delay slot filling. */
10424 macro_build (NULL
, "break", BRK_FMT
, 6);
10426 if (mips_opts
.micromips
)
10427 micromips_add_label ();
10428 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10467 if (imm_expr
.X_add_number
== 0)
10469 as_warn (_("divide by zero"));
10471 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10473 macro_build (NULL
, "break", BRK_FMT
, 7);
10476 if (imm_expr
.X_add_number
== 1)
10478 if (strcmp (s2
, "mflo") == 0)
10479 move_register (op
[0], op
[1]);
10481 move_register (op
[0], ZERO
);
10484 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10486 if (strcmp (s2
, "mflo") == 0)
10487 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10489 move_register (op
[0], ZERO
);
10494 load_register (AT
, &imm_expr
, dbl
);
10495 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10496 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10515 start_noreorder ();
10518 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10519 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10520 /* We want to close the noreorder block as soon as possible, so
10521 that later insns are available for delay slot filling. */
10526 if (mips_opts
.micromips
)
10527 micromips_label_expr (&label_expr
);
10529 label_expr
.X_add_number
= 8;
10530 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10531 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10533 /* We want to close the noreorder block as soon as possible, so
10534 that later insns are available for delay slot filling. */
10536 macro_build (NULL
, "break", BRK_FMT
, 7);
10537 if (mips_opts
.micromips
)
10538 micromips_add_label ();
10540 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10545 /* Fall through. */
10551 /* Fall through. */
10554 /* Load the address of a symbol into a register. If breg is not
10555 zero, we then add a base register to it. */
10558 if (dbl
&& GPR_SIZE
== 32)
10559 as_warn (_("dla used to load 32-bit register; recommend using la "
10562 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10563 as_warn (_("la used to load 64-bit address; recommend using dla "
10566 if (small_offset_p (0, align
, 16))
10568 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10569 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10573 if (mips_opts
.at
&& (op
[0] == breg
))
10581 if (offset_expr
.X_op
!= O_symbol
10582 && offset_expr
.X_op
!= O_constant
)
10584 as_bad (_("expression too complex"));
10585 offset_expr
.X_op
= O_constant
;
10588 if (offset_expr
.X_op
== O_constant
)
10589 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10590 else if (mips_pic
== NO_PIC
)
10592 /* If this is a reference to a GP relative symbol, we want
10593 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
10595 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
10596 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10597 If we have a constant, we need two instructions anyhow,
10598 so we may as well always use the latter form.
10600 With 64bit address space and a usable $at we want
10601 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10602 lui $at,<sym> (BFD_RELOC_HI16_S)
10603 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10604 daddiu $at,<sym> (BFD_RELOC_LO16)
10606 daddu $tempreg,$tempreg,$at
10608 If $at is already in use, we use a path which is suboptimal
10609 on superscalar processors.
10610 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
10611 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
10613 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
10615 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
10617 For GP relative symbols in 64bit address space we can use
10618 the same sequence as in 32bit address space. */
10619 if (HAVE_64BIT_SYMBOLS
)
10621 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10622 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10624 relax_start (offset_expr
.X_add_symbol
);
10625 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10626 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10630 if (used_at
== 0 && mips_opts
.at
)
10632 macro_build (&offset_expr
, "lui", LUI_FMT
,
10633 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10634 macro_build (&offset_expr
, "lui", LUI_FMT
,
10635 AT
, BFD_RELOC_HI16_S
);
10636 macro_build (&offset_expr
, "daddiu", "t,r,j",
10637 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10638 macro_build (&offset_expr
, "daddiu", "t,r,j",
10639 AT
, AT
, BFD_RELOC_LO16
);
10640 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
10641 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
10646 macro_build (&offset_expr
, "lui", LUI_FMT
,
10647 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
10648 macro_build (&offset_expr
, "daddiu", "t,r,j",
10649 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
10650 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10651 macro_build (&offset_expr
, "daddiu", "t,r,j",
10652 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
10653 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
10654 macro_build (&offset_expr
, "daddiu", "t,r,j",
10655 tempreg
, tempreg
, BFD_RELOC_LO16
);
10658 if (mips_relax
.sequence
)
10663 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
10664 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
10666 relax_start (offset_expr
.X_add_symbol
);
10667 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10668 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
10671 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
10672 as_bad (_("offset too large"));
10673 macro_build_lui (&offset_expr
, tempreg
);
10674 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10675 tempreg
, tempreg
, BFD_RELOC_LO16
);
10676 if (mips_relax
.sequence
)
10680 else if (!mips_big_got
&& !HAVE_NEWABI
)
10682 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10684 /* If this is a reference to an external symbol, and there
10685 is no constant, we want
10686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10687 or for lca or if tempreg is PIC_CALL_REG
10688 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10689 For a local symbol, we want
10690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10692 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10694 If we have a small constant, and this is a reference to
10695 an external symbol, we want
10696 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10698 addiu $tempreg,$tempreg,<constant>
10699 For a local symbol, we want the same instruction
10700 sequence, but we output a BFD_RELOC_LO16 reloc on the
10703 If we have a large constant, and this is a reference to
10704 an external symbol, we want
10705 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10706 lui $at,<hiconstant>
10707 addiu $at,$at,<loconstant>
10708 addu $tempreg,$tempreg,$at
10709 For a local symbol, we want the same instruction
10710 sequence, but we output a BFD_RELOC_LO16 reloc on the
10714 if (offset_expr
.X_add_number
== 0)
10716 if (mips_pic
== SVR4_PIC
10718 && (call
|| tempreg
== PIC_CALL_REG
))
10719 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
10721 relax_start (offset_expr
.X_add_symbol
);
10722 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10723 lw_reloc_type
, mips_gp_register
);
10726 /* We're going to put in an addu instruction using
10727 tempreg, so we may as well insert the nop right
10732 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10733 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10735 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10736 tempreg
, tempreg
, BFD_RELOC_LO16
);
10738 /* FIXME: If breg == 0, and the next instruction uses
10739 $tempreg, then if this variant case is used an extra
10740 nop will be generated. */
10742 else if (offset_expr
.X_add_number
>= -0x8000
10743 && offset_expr
.X_add_number
< 0x8000)
10745 load_got_offset (tempreg
, &offset_expr
);
10747 add_got_offset (tempreg
, &offset_expr
);
10751 expr1
.X_add_number
= offset_expr
.X_add_number
;
10752 offset_expr
.X_add_number
=
10753 SEXT_16BIT (offset_expr
.X_add_number
);
10754 load_got_offset (tempreg
, &offset_expr
);
10755 offset_expr
.X_add_number
= expr1
.X_add_number
;
10756 /* If we are going to add in a base register, and the
10757 target register and the base register are the same,
10758 then we are using AT as a temporary register. Since
10759 we want to load the constant into AT, we add our
10760 current AT (from the global offset table) and the
10761 register into the register now, and pretend we were
10762 not using a base register. */
10766 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10771 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10775 else if (!mips_big_got
&& HAVE_NEWABI
)
10777 int add_breg_early
= 0;
10779 /* If this is a reference to an external, and there is no
10780 constant, or local symbol (*), with or without a
10782 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10783 or for lca or if tempreg is PIC_CALL_REG
10784 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10786 If we have a small constant, and this is a reference to
10787 an external symbol, we want
10788 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10789 addiu $tempreg,$tempreg,<constant>
10791 If we have a large constant, and this is a reference to
10792 an external symbol, we want
10793 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10794 lui $at,<hiconstant>
10795 addiu $at,$at,<loconstant>
10796 addu $tempreg,$tempreg,$at
10798 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10799 local symbols, even though it introduces an additional
10802 if (offset_expr
.X_add_number
)
10804 expr1
.X_add_number
= offset_expr
.X_add_number
;
10805 offset_expr
.X_add_number
= 0;
10807 relax_start (offset_expr
.X_add_symbol
);
10808 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10809 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10811 if (expr1
.X_add_number
>= -0x8000
10812 && expr1
.X_add_number
< 0x8000)
10814 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10815 tempreg
, tempreg
, BFD_RELOC_LO16
);
10817 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10821 /* If we are going to add in a base register, and the
10822 target register and the base register are the same,
10823 then we are using AT as a temporary register. Since
10824 we want to load the constant into AT, we add our
10825 current AT (from the global offset table) and the
10826 register into the register now, and pretend we were
10827 not using a base register. */
10832 gas_assert (tempreg
== AT
);
10833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10836 add_breg_early
= 1;
10839 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10840 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10846 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10849 offset_expr
.X_add_number
= expr1
.X_add_number
;
10851 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10852 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10853 if (add_breg_early
)
10855 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10856 op
[0], tempreg
, breg
);
10862 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10864 relax_start (offset_expr
.X_add_symbol
);
10865 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10866 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10868 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10869 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10874 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10875 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10878 else if (mips_big_got
&& !HAVE_NEWABI
)
10881 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10882 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10883 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10885 /* This is the large GOT case. If this is a reference to an
10886 external symbol, and there is no constant, we want
10887 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10888 addu $tempreg,$tempreg,$gp
10889 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10890 or for lca or if tempreg is PIC_CALL_REG
10891 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10892 addu $tempreg,$tempreg,$gp
10893 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10894 For a local symbol, we want
10895 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10897 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10899 If we have a small constant, and this is a reference to
10900 an external symbol, we want
10901 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10902 addu $tempreg,$tempreg,$gp
10903 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10905 addiu $tempreg,$tempreg,<constant>
10906 For a local symbol, we want
10907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10909 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10911 If we have a large constant, and this is a reference to
10912 an external symbol, we want
10913 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10914 addu $tempreg,$tempreg,$gp
10915 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10916 lui $at,<hiconstant>
10917 addiu $at,$at,<loconstant>
10918 addu $tempreg,$tempreg,$at
10919 For a local symbol, we want
10920 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10921 lui $at,<hiconstant>
10922 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10923 addu $tempreg,$tempreg,$at
10926 expr1
.X_add_number
= offset_expr
.X_add_number
;
10927 offset_expr
.X_add_number
= 0;
10928 relax_start (offset_expr
.X_add_symbol
);
10929 gpdelay
= reg_needs_delay (mips_gp_register
);
10930 if (expr1
.X_add_number
== 0 && breg
== 0
10931 && (call
|| tempreg
== PIC_CALL_REG
))
10933 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10934 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10936 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10938 tempreg
, tempreg
, mips_gp_register
);
10939 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10940 tempreg
, lw_reloc_type
, tempreg
);
10941 if (expr1
.X_add_number
== 0)
10945 /* We're going to put in an addu instruction using
10946 tempreg, so we may as well insert the nop right
10951 else if (expr1
.X_add_number
>= -0x8000
10952 && expr1
.X_add_number
< 0x8000)
10955 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10956 tempreg
, tempreg
, BFD_RELOC_LO16
);
10962 /* If we are going to add in a base register, and the
10963 target register and the base register are the same,
10964 then we are using AT as a temporary register. Since
10965 we want to load the constant into AT, we add our
10966 current AT (from the global offset table) and the
10967 register into the register now, and pretend we were
10968 not using a base register. */
10973 gas_assert (tempreg
== AT
);
10975 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10980 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10981 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10985 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10990 /* This is needed because this instruction uses $gp, but
10991 the first instruction on the main stream does not. */
10992 macro_build (NULL
, "nop", "");
10995 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10996 local_reloc_type
, mips_gp_register
);
10997 if (expr1
.X_add_number
>= -0x8000
10998 && expr1
.X_add_number
< 0x8000)
11001 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11002 tempreg
, tempreg
, BFD_RELOC_LO16
);
11003 /* FIXME: If add_number is 0, and there was no base
11004 register, the external symbol case ended with a load,
11005 so if the symbol turns out to not be external, and
11006 the next instruction uses tempreg, an unnecessary nop
11007 will be inserted. */
11013 /* We must add in the base register now, as in the
11014 external symbol case. */
11015 gas_assert (tempreg
== AT
);
11017 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11020 /* We set breg to 0 because we have arranged to add
11021 it in in both cases. */
11025 macro_build_lui (&expr1
, AT
);
11026 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11027 AT
, AT
, BFD_RELOC_LO16
);
11028 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11029 tempreg
, tempreg
, AT
);
11034 else if (mips_big_got
&& HAVE_NEWABI
)
11036 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11037 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11038 int add_breg_early
= 0;
11040 /* This is the large GOT case. If this is a reference to an
11041 external symbol, and there is no constant, we want
11042 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11043 add $tempreg,$tempreg,$gp
11044 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11045 or for lca or if tempreg is PIC_CALL_REG
11046 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11047 add $tempreg,$tempreg,$gp
11048 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11050 If we have a small constant, and this is a reference to
11051 an external symbol, we want
11052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11053 add $tempreg,$tempreg,$gp
11054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11055 addi $tempreg,$tempreg,<constant>
11057 If we have a large constant, and this is a reference to
11058 an external symbol, we want
11059 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11060 addu $tempreg,$tempreg,$gp
11061 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11062 lui $at,<hiconstant>
11063 addi $at,$at,<loconstant>
11064 add $tempreg,$tempreg,$at
11066 If we have NewABI, and we know it's a local symbol, we want
11067 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11068 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11069 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11071 relax_start (offset_expr
.X_add_symbol
);
11073 expr1
.X_add_number
= offset_expr
.X_add_number
;
11074 offset_expr
.X_add_number
= 0;
11076 if (expr1
.X_add_number
== 0 && breg
== 0
11077 && (call
|| tempreg
== PIC_CALL_REG
))
11079 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11080 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11082 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11083 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11084 tempreg
, tempreg
, mips_gp_register
);
11085 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11086 tempreg
, lw_reloc_type
, tempreg
);
11088 if (expr1
.X_add_number
== 0)
11090 else if (expr1
.X_add_number
>= -0x8000
11091 && expr1
.X_add_number
< 0x8000)
11093 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11094 tempreg
, tempreg
, BFD_RELOC_LO16
);
11096 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11100 /* If we are going to add in a base register, and the
11101 target register and the base register are the same,
11102 then we are using AT as a temporary register. Since
11103 we want to load the constant into AT, we add our
11104 current AT (from the global offset table) and the
11105 register into the register now, and pretend we were
11106 not using a base register. */
11111 gas_assert (tempreg
== AT
);
11112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11115 add_breg_early
= 1;
11118 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11119 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11124 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11127 offset_expr
.X_add_number
= expr1
.X_add_number
;
11128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11129 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11130 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11131 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11132 if (add_breg_early
)
11134 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11135 op
[0], tempreg
, breg
);
11145 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11149 gas_assert (!mips_opts
.micromips
);
11150 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11154 gas_assert (!mips_opts
.micromips
);
11155 macro_build (NULL
, "c2", "C", 0x02);
11159 gas_assert (!mips_opts
.micromips
);
11160 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11164 gas_assert (!mips_opts
.micromips
);
11165 macro_build (NULL
, "c2", "C", 3);
11169 gas_assert (!mips_opts
.micromips
);
11170 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11174 /* The j instruction may not be used in PIC code, since it
11175 requires an absolute address. We convert it to a b
11177 if (mips_pic
== NO_PIC
)
11178 macro_build (&offset_expr
, "j", "a");
11180 macro_build (&offset_expr
, "b", "p");
11183 /* The jal instructions must be handled as macros because when
11184 generating PIC code they expand to multi-instruction
11185 sequences. Normally they are simple instructions. */
11189 /* Fall through. */
11191 gas_assert (mips_opts
.micromips
);
11192 if (mips_opts
.insn32
)
11194 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11202 /* Fall through. */
11205 if (mips_pic
== NO_PIC
)
11207 s
= jals
? "jalrs" : "jalr";
11208 if (mips_opts
.micromips
11209 && !mips_opts
.insn32
11211 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11212 macro_build (NULL
, s
, "mj", op
[1]);
11214 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11218 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11219 && mips_cprestore_offset
>= 0);
11221 if (op
[1] != PIC_CALL_REG
)
11222 as_warn (_("MIPS PIC call to register other than $25"));
11224 s
= ((mips_opts
.micromips
11225 && !mips_opts
.insn32
11226 && (!mips_opts
.noreorder
|| cprestore
))
11227 ? "jalrs" : "jalr");
11228 if (mips_opts
.micromips
11229 && !mips_opts
.insn32
11231 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11232 macro_build (NULL
, s
, "mj", op
[1]);
11234 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11235 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11237 if (mips_cprestore_offset
< 0)
11238 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11241 if (!mips_frame_reg_valid
)
11243 as_warn (_("no .frame pseudo-op used in PIC code"));
11244 /* Quiet this warning. */
11245 mips_frame_reg_valid
= 1;
11247 if (!mips_cprestore_valid
)
11249 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11250 /* Quiet this warning. */
11251 mips_cprestore_valid
= 1;
11253 if (mips_opts
.noreorder
)
11254 macro_build (NULL
, "nop", "");
11255 expr1
.X_add_number
= mips_cprestore_offset
;
11256 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11259 HAVE_64BIT_ADDRESSES
);
11267 gas_assert (mips_opts
.micromips
);
11268 if (mips_opts
.insn32
)
11270 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11274 /* Fall through. */
11276 if (mips_pic
== NO_PIC
)
11277 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11278 else if (mips_pic
== SVR4_PIC
)
11280 /* If this is a reference to an external symbol, and we are
11281 using a small GOT, we want
11282 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11286 lw $gp,cprestore($sp)
11287 The cprestore value is set using the .cprestore
11288 pseudo-op. If we are using a big GOT, we want
11289 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11291 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11295 lw $gp,cprestore($sp)
11296 If the symbol is not external, we want
11297 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11299 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11302 lw $gp,cprestore($sp)
11304 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11305 sequences above, minus nops, unless the symbol is local,
11306 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11312 relax_start (offset_expr
.X_add_symbol
);
11313 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11314 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11317 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11318 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11324 relax_start (offset_expr
.X_add_symbol
);
11325 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11326 BFD_RELOC_MIPS_CALL_HI16
);
11327 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11328 PIC_CALL_REG
, mips_gp_register
);
11329 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11330 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11333 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11334 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11336 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11337 PIC_CALL_REG
, PIC_CALL_REG
,
11338 BFD_RELOC_MIPS_GOT_OFST
);
11342 macro_build_jalr (&offset_expr
, 0);
11346 relax_start (offset_expr
.X_add_symbol
);
11349 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11350 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11359 gpdelay
= reg_needs_delay (mips_gp_register
);
11360 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11361 BFD_RELOC_MIPS_CALL_HI16
);
11362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11363 PIC_CALL_REG
, mips_gp_register
);
11364 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11365 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11370 macro_build (NULL
, "nop", "");
11372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11373 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11376 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11377 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11379 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11381 if (mips_cprestore_offset
< 0)
11382 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11385 if (!mips_frame_reg_valid
)
11387 as_warn (_("no .frame pseudo-op used in PIC code"));
11388 /* Quiet this warning. */
11389 mips_frame_reg_valid
= 1;
11391 if (!mips_cprestore_valid
)
11393 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11394 /* Quiet this warning. */
11395 mips_cprestore_valid
= 1;
11397 if (mips_opts
.noreorder
)
11398 macro_build (NULL
, "nop", "");
11399 expr1
.X_add_number
= mips_cprestore_offset
;
11400 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11403 HAVE_64BIT_ADDRESSES
);
11407 else if (mips_pic
== VXWORKS_PIC
)
11408 as_bad (_("non-PIC jump used in PIC library"));
11515 gas_assert (!mips_opts
.micromips
);
11518 /* Itbl support may require additional care here. */
11524 /* Itbl support may require additional care here. */
11530 offbits
= (mips_opts
.micromips
? 12
11531 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11533 /* Itbl support may require additional care here. */
11537 gas_assert (!mips_opts
.micromips
);
11540 /* Itbl support may require additional care here. */
11546 offbits
= (mips_opts
.micromips
? 12 : 16);
11551 offbits
= (mips_opts
.micromips
? 12 : 16);
11556 /* Itbl support may require additional care here. */
11562 offbits
= (mips_opts
.micromips
? 12
11563 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11565 /* Itbl support may require additional care here. */
11571 /* Itbl support may require additional care here. */
11577 /* Itbl support may require additional care here. */
11583 offbits
= (mips_opts
.micromips
? 12 : 16);
11588 offbits
= (mips_opts
.micromips
? 12 : 16);
11593 offbits
= (mips_opts
.micromips
? 12
11594 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11600 offbits
= (mips_opts
.micromips
? 12
11601 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11607 offbits
= (mips_opts
.micromips
? 12 : 16);
11610 gas_assert (mips_opts
.micromips
);
11617 gas_assert (mips_opts
.micromips
);
11624 gas_assert (mips_opts
.micromips
);
11630 gas_assert (mips_opts
.micromips
);
11637 /* We don't want to use $0 as tempreg. */
11638 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
11641 tempreg
= op
[0] + lp
;
11657 gas_assert (!mips_opts
.micromips
);
11660 /* Itbl support may require additional care here. */
11666 /* Itbl support may require additional care here. */
11672 offbits
= (mips_opts
.micromips
? 12
11673 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11675 /* Itbl support may require additional care here. */
11679 gas_assert (!mips_opts
.micromips
);
11682 /* Itbl support may require additional care here. */
11688 offbits
= (mips_opts
.micromips
? 12 : 16);
11693 offbits
= (mips_opts
.micromips
? 12 : 16);
11698 offbits
= (mips_opts
.micromips
? 12
11699 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11705 offbits
= (mips_opts
.micromips
? 12
11706 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11711 fmt
= (mips_opts
.micromips
? "k,~(b)"
11712 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11714 offbits
= (mips_opts
.micromips
? 12
11715 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11725 fmt
= (mips_opts
.micromips
? "k,~(b)"
11726 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
11728 offbits
= (mips_opts
.micromips
? 12
11729 : ISA_IS_R6 (mips_opts
.isa
) ? 9
11741 /* Itbl support may require additional care here. */
11746 offbits
= (mips_opts
.micromips
? 12
11747 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11749 /* Itbl support may require additional care here. */
11755 /* Itbl support may require additional care here. */
11759 gas_assert (!mips_opts
.micromips
);
11762 /* Itbl support may require additional care here. */
11768 offbits
= (mips_opts
.micromips
? 12 : 16);
11773 offbits
= (mips_opts
.micromips
? 12 : 16);
11776 gas_assert (mips_opts
.micromips
);
11782 gas_assert (mips_opts
.micromips
);
11788 gas_assert (mips_opts
.micromips
);
11794 gas_assert (mips_opts
.micromips
);
11803 if (small_offset_p (0, align
, 16))
11805 /* The first case exists for M_LD_AB and M_SD_AB, which are
11806 macros for o32 but which should act like normal instructions
11809 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11810 offset_reloc
[1], offset_reloc
[2], breg
);
11811 else if (small_offset_p (0, align
, offbits
))
11814 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11816 macro_build (NULL
, s
, fmt
, op
[0],
11817 (int) offset_expr
.X_add_number
, breg
);
11823 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11824 tempreg
, breg
, -1, offset_reloc
[0],
11825 offset_reloc
[1], offset_reloc
[2]);
11827 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11829 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11837 if (offset_expr
.X_op
!= O_constant
11838 && offset_expr
.X_op
!= O_symbol
)
11840 as_bad (_("expression too complex"));
11841 offset_expr
.X_op
= O_constant
;
11844 if (HAVE_32BIT_ADDRESSES
11845 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11849 sprintf_vma (value
, offset_expr
.X_add_number
);
11850 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11853 /* A constant expression in PIC code can be handled just as it
11854 is in non PIC code. */
11855 if (offset_expr
.X_op
== O_constant
)
11857 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11858 offbits
== 0 ? 16 : offbits
);
11859 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11861 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11864 tempreg
, tempreg
, breg
);
11867 if (offset_expr
.X_add_number
!= 0)
11868 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11869 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11870 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11872 else if (offbits
== 16)
11873 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11875 macro_build (NULL
, s
, fmt
, op
[0],
11876 (int) offset_expr
.X_add_number
, tempreg
);
11878 else if (offbits
!= 16)
11880 /* The offset field is too narrow to be used for a low-part
11881 relocation, so load the whole address into the auxiliary
11883 load_address (tempreg
, &offset_expr
, &used_at
);
11885 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11886 tempreg
, tempreg
, breg
);
11888 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11890 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11892 else if (mips_pic
== NO_PIC
)
11894 /* If this is a reference to a GP relative symbol, and there
11895 is no base register, we want
11896 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11897 Otherwise, if there is no base register, we want
11898 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11899 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11900 If we have a constant, we need two instructions anyhow,
11901 so we always use the latter form.
11903 If we have a base register, and this is a reference to a
11904 GP relative symbol, we want
11905 addu $tempreg,$breg,$gp
11906 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11908 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11909 addu $tempreg,$tempreg,$breg
11910 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11911 With a constant we always use the latter case.
11913 With 64bit address space and no base register and $at usable,
11915 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11916 lui $at,<sym> (BFD_RELOC_HI16_S)
11917 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11920 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11921 If we have a base register, we want
11922 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11923 lui $at,<sym> (BFD_RELOC_HI16_S)
11924 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11928 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11930 Without $at we can't generate the optimal path for superscalar
11931 processors here since this would require two temporary registers.
11932 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11933 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11935 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11937 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11938 If we have a base register, we want
11939 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11940 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11942 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11944 daddu $tempreg,$tempreg,$breg
11945 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11947 For GP relative symbols in 64bit address space we can use
11948 the same sequence as in 32bit address space. */
11949 if (HAVE_64BIT_SYMBOLS
)
11951 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11952 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11954 relax_start (offset_expr
.X_add_symbol
);
11957 macro_build (&offset_expr
, s
, fmt
, op
[0],
11958 BFD_RELOC_GPREL16
, mips_gp_register
);
11962 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11963 tempreg
, breg
, mips_gp_register
);
11964 macro_build (&offset_expr
, s
, fmt
, op
[0],
11965 BFD_RELOC_GPREL16
, tempreg
);
11970 if (used_at
== 0 && mips_opts
.at
)
11972 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11973 BFD_RELOC_MIPS_HIGHEST
);
11974 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11976 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11977 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11979 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11980 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11981 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11982 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11988 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11989 BFD_RELOC_MIPS_HIGHEST
);
11990 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11991 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11992 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11993 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11994 tempreg
, BFD_RELOC_HI16_S
);
11995 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11997 macro_build (NULL
, "daddu", "d,v,t",
11998 tempreg
, tempreg
, breg
);
11999 macro_build (&offset_expr
, s
, fmt
, op
[0],
12000 BFD_RELOC_LO16
, tempreg
);
12003 if (mips_relax
.sequence
)
12010 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12011 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12013 relax_start (offset_expr
.X_add_symbol
);
12014 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12018 macro_build_lui (&offset_expr
, tempreg
);
12019 macro_build (&offset_expr
, s
, fmt
, op
[0],
12020 BFD_RELOC_LO16
, tempreg
);
12021 if (mips_relax
.sequence
)
12026 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12027 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12029 relax_start (offset_expr
.X_add_symbol
);
12030 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12031 tempreg
, breg
, mips_gp_register
);
12032 macro_build (&offset_expr
, s
, fmt
, op
[0],
12033 BFD_RELOC_GPREL16
, tempreg
);
12036 macro_build_lui (&offset_expr
, tempreg
);
12037 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12038 tempreg
, tempreg
, breg
);
12039 macro_build (&offset_expr
, s
, fmt
, op
[0],
12040 BFD_RELOC_LO16
, tempreg
);
12041 if (mips_relax
.sequence
)
12045 else if (!mips_big_got
)
12047 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12049 /* If this is a reference to an external symbol, we want
12050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12052 <op> op[0],0($tempreg)
12054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12056 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12057 <op> op[0],0($tempreg)
12059 For NewABI, we want
12060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12061 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12063 If there is a base register, we add it to $tempreg before
12064 the <op>. If there is a constant, we stick it in the
12065 <op> instruction. We don't handle constants larger than
12066 16 bits, because we have no way to load the upper 16 bits
12067 (actually, we could handle them for the subset of cases
12068 in which we are not using $at). */
12069 gas_assert (offset_expr
.X_op
== O_symbol
);
12072 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12073 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12075 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12076 tempreg
, tempreg
, breg
);
12077 macro_build (&offset_expr
, s
, fmt
, op
[0],
12078 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12081 expr1
.X_add_number
= offset_expr
.X_add_number
;
12082 offset_expr
.X_add_number
= 0;
12083 if (expr1
.X_add_number
< -0x8000
12084 || expr1
.X_add_number
>= 0x8000)
12085 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12086 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12087 lw_reloc_type
, mips_gp_register
);
12089 relax_start (offset_expr
.X_add_symbol
);
12091 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12092 tempreg
, BFD_RELOC_LO16
);
12095 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12096 tempreg
, tempreg
, breg
);
12097 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12099 else if (mips_big_got
&& !HAVE_NEWABI
)
12103 /* If this is a reference to an external symbol, we want
12104 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12105 addu $tempreg,$tempreg,$gp
12106 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12107 <op> op[0],0($tempreg)
12109 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12111 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12112 <op> op[0],0($tempreg)
12113 If there is a base register, we add it to $tempreg before
12114 the <op>. If there is a constant, we stick it in the
12115 <op> instruction. We don't handle constants larger than
12116 16 bits, because we have no way to load the upper 16 bits
12117 (actually, we could handle them for the subset of cases
12118 in which we are not using $at). */
12119 gas_assert (offset_expr
.X_op
== O_symbol
);
12120 expr1
.X_add_number
= offset_expr
.X_add_number
;
12121 offset_expr
.X_add_number
= 0;
12122 if (expr1
.X_add_number
< -0x8000
12123 || expr1
.X_add_number
>= 0x8000)
12124 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12125 gpdelay
= reg_needs_delay (mips_gp_register
);
12126 relax_start (offset_expr
.X_add_symbol
);
12127 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12128 BFD_RELOC_MIPS_GOT_HI16
);
12129 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12131 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12132 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12135 macro_build (NULL
, "nop", "");
12136 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12137 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12139 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12140 tempreg
, BFD_RELOC_LO16
);
12144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12145 tempreg
, tempreg
, breg
);
12146 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12148 else if (mips_big_got
&& HAVE_NEWABI
)
12150 /* If this is a reference to an external symbol, we want
12151 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12152 add $tempreg,$tempreg,$gp
12153 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12154 <op> op[0],<ofst>($tempreg)
12155 Otherwise, for local symbols, we want:
12156 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12157 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12158 gas_assert (offset_expr
.X_op
== O_symbol
);
12159 expr1
.X_add_number
= offset_expr
.X_add_number
;
12160 offset_expr
.X_add_number
= 0;
12161 if (expr1
.X_add_number
< -0x8000
12162 || expr1
.X_add_number
>= 0x8000)
12163 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12164 relax_start (offset_expr
.X_add_symbol
);
12165 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12166 BFD_RELOC_MIPS_GOT_HI16
);
12167 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12169 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12170 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12172 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12173 tempreg
, tempreg
, breg
);
12174 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12177 offset_expr
.X_add_number
= expr1
.X_add_number
;
12178 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12179 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12181 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12182 tempreg
, tempreg
, breg
);
12183 macro_build (&offset_expr
, s
, fmt
, op
[0],
12184 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12193 gas_assert (mips_opts
.micromips
);
12194 gas_assert (mips_opts
.insn32
);
12195 start_noreorder ();
12196 macro_build (NULL
, "jr", "s", RA
);
12197 expr1
.X_add_number
= op
[0] << 2;
12198 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12203 gas_assert (mips_opts
.micromips
);
12204 gas_assert (mips_opts
.insn32
);
12205 macro_build (NULL
, "jr", "s", op
[0]);
12206 if (mips_opts
.noreorder
)
12207 macro_build (NULL
, "nop", "");
12212 load_register (op
[0], &imm_expr
, 0);
12216 load_register (op
[0], &imm_expr
, 1);
12220 if (imm_expr
.X_op
== O_constant
)
12223 load_register (AT
, &imm_expr
, 0);
12224 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12229 gas_assert (imm_expr
.X_op
== O_absent
12230 && offset_expr
.X_op
== O_symbol
12231 && strcmp (segment_name (S_GET_SEGMENT
12232 (offset_expr
.X_add_symbol
)),
12234 && offset_expr
.X_add_number
== 0);
12235 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12236 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12241 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12242 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12243 order 32 bits of the value and the low order 32 bits are either
12244 zero or in OFFSET_EXPR. */
12245 if (imm_expr
.X_op
== O_constant
)
12247 if (GPR_SIZE
== 64)
12248 load_register (op
[0], &imm_expr
, 1);
12253 if (target_big_endian
)
12265 load_register (hreg
, &imm_expr
, 0);
12268 if (offset_expr
.X_op
== O_absent
)
12269 move_register (lreg
, 0);
12272 gas_assert (offset_expr
.X_op
== O_constant
);
12273 load_register (lreg
, &offset_expr
, 0);
12279 gas_assert (imm_expr
.X_op
== O_absent
);
12281 /* We know that sym is in the .rdata section. First we get the
12282 upper 16 bits of the address. */
12283 if (mips_pic
== NO_PIC
)
12285 macro_build_lui (&offset_expr
, AT
);
12290 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12291 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12295 /* Now we load the register(s). */
12296 if (GPR_SIZE
== 64)
12299 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12300 BFD_RELOC_LO16
, AT
);
12305 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12306 BFD_RELOC_LO16
, AT
);
12309 /* FIXME: How in the world do we deal with the possible
12311 offset_expr
.X_add_number
+= 4;
12312 macro_build (&offset_expr
, "lw", "t,o(b)",
12313 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12319 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12320 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12321 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12322 the value and the low order 32 bits are either zero or in
12324 if (imm_expr
.X_op
== O_constant
)
12327 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12328 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12329 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
12332 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12333 macro_build (NULL
, "mthc1", "t,G", AT
, op
[0]);
12334 else if (FPR_SIZE
!= 32)
12335 as_bad (_("Unable to generate `%s' compliant code "
12337 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12339 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
12340 if (offset_expr
.X_op
== O_absent
)
12341 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12344 gas_assert (offset_expr
.X_op
== O_constant
);
12345 load_register (AT
, &offset_expr
, 0);
12346 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12352 gas_assert (imm_expr
.X_op
== O_absent
12353 && offset_expr
.X_op
== O_symbol
12354 && offset_expr
.X_add_number
== 0);
12355 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12356 if (strcmp (s
, ".lit8") == 0)
12358 op
[2] = mips_gp_register
;
12359 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12360 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12361 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12365 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12367 if (mips_pic
!= NO_PIC
)
12368 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12369 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12372 /* FIXME: This won't work for a 64 bit address. */
12373 macro_build_lui (&offset_expr
, AT
);
12377 offset_reloc
[0] = BFD_RELOC_LO16
;
12378 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12379 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12386 * The MIPS assembler seems to check for X_add_number not
12387 * being double aligned and generating:
12388 * lui at,%hi(foo+1)
12390 * addiu at,at,%lo(foo+1)
12393 * But, the resulting address is the same after relocation so why
12394 * generate the extra instruction?
12396 /* Itbl support may require additional care here. */
12399 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12408 gas_assert (!mips_opts
.micromips
);
12409 /* Itbl support may require additional care here. */
12412 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12432 if (GPR_SIZE
== 64)
12442 if (GPR_SIZE
== 64)
12450 /* Even on a big endian machine $fn comes before $fn+1. We have
12451 to adjust when loading from memory. We set coproc if we must
12452 load $fn+1 first. */
12453 /* Itbl support may require additional care here. */
12454 if (!target_big_endian
)
12458 if (small_offset_p (0, align
, 16))
12461 if (!small_offset_p (4, align
, 16))
12463 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12464 -1, offset_reloc
[0], offset_reloc
[1],
12466 expr1
.X_add_number
= 0;
12470 offset_reloc
[0] = BFD_RELOC_LO16
;
12471 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12472 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12474 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12476 ep
->X_add_number
+= 4;
12477 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12478 offset_reloc
[1], offset_reloc
[2], breg
);
12479 ep
->X_add_number
-= 4;
12480 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12481 offset_reloc
[1], offset_reloc
[2], breg
);
12485 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12486 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12488 ep
->X_add_number
+= 4;
12489 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12490 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12496 if (offset_expr
.X_op
!= O_symbol
12497 && offset_expr
.X_op
!= O_constant
)
12499 as_bad (_("expression too complex"));
12500 offset_expr
.X_op
= O_constant
;
12503 if (HAVE_32BIT_ADDRESSES
12504 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12508 sprintf_vma (value
, offset_expr
.X_add_number
);
12509 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12512 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12514 /* If this is a reference to a GP relative symbol, we want
12515 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12516 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12517 If we have a base register, we use this
12519 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12520 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12521 If this is not a GP relative symbol, we want
12522 lui $at,<sym> (BFD_RELOC_HI16_S)
12523 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12524 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12525 If there is a base register, we add it to $at after the
12526 lui instruction. If there is a constant, we always use
12528 if (offset_expr
.X_op
== O_symbol
12529 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12530 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12532 relax_start (offset_expr
.X_add_symbol
);
12535 tempreg
= mips_gp_register
;
12539 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12540 AT
, breg
, mips_gp_register
);
12545 /* Itbl support may require additional care here. */
12546 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12547 BFD_RELOC_GPREL16
, tempreg
);
12548 offset_expr
.X_add_number
+= 4;
12550 /* Set mips_optimize to 2 to avoid inserting an
12552 hold_mips_optimize
= mips_optimize
;
12554 /* Itbl support may require additional care here. */
12555 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12556 BFD_RELOC_GPREL16
, tempreg
);
12557 mips_optimize
= hold_mips_optimize
;
12561 offset_expr
.X_add_number
-= 4;
12564 if (offset_high_part (offset_expr
.X_add_number
, 16)
12565 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
12567 load_address (AT
, &offset_expr
, &used_at
);
12568 offset_expr
.X_op
= O_constant
;
12569 offset_expr
.X_add_number
= 0;
12572 macro_build_lui (&offset_expr
, AT
);
12574 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12575 /* Itbl support may require additional care here. */
12576 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12577 BFD_RELOC_LO16
, AT
);
12578 /* FIXME: How do we handle overflow here? */
12579 offset_expr
.X_add_number
+= 4;
12580 /* Itbl support may require additional care here. */
12581 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12582 BFD_RELOC_LO16
, AT
);
12583 if (mips_relax
.sequence
)
12586 else if (!mips_big_got
)
12588 /* If this is a reference to an external symbol, we want
12589 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12592 <op> op[0]+1,4($at)
12594 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12596 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12597 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12598 If there is a base register we add it to $at before the
12599 lwc1 instructions. If there is a constant we include it
12600 in the lwc1 instructions. */
12602 expr1
.X_add_number
= offset_expr
.X_add_number
;
12603 if (expr1
.X_add_number
< -0x8000
12604 || expr1
.X_add_number
>= 0x8000 - 4)
12605 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12606 load_got_offset (AT
, &offset_expr
);
12609 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12611 /* Set mips_optimize to 2 to avoid inserting an undesired
12613 hold_mips_optimize
= mips_optimize
;
12616 /* Itbl support may require additional care here. */
12617 relax_start (offset_expr
.X_add_symbol
);
12618 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12619 BFD_RELOC_LO16
, AT
);
12620 expr1
.X_add_number
+= 4;
12621 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12622 BFD_RELOC_LO16
, AT
);
12624 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12625 BFD_RELOC_LO16
, AT
);
12626 offset_expr
.X_add_number
+= 4;
12627 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12628 BFD_RELOC_LO16
, AT
);
12631 mips_optimize
= hold_mips_optimize
;
12633 else if (mips_big_got
)
12637 /* If this is a reference to an external symbol, we want
12638 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12640 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
12643 <op> op[0]+1,4($at)
12645 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12647 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12648 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12649 If there is a base register we add it to $at before the
12650 lwc1 instructions. If there is a constant we include it
12651 in the lwc1 instructions. */
12653 expr1
.X_add_number
= offset_expr
.X_add_number
;
12654 offset_expr
.X_add_number
= 0;
12655 if (expr1
.X_add_number
< -0x8000
12656 || expr1
.X_add_number
>= 0x8000 - 4)
12657 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12658 gpdelay
= reg_needs_delay (mips_gp_register
);
12659 relax_start (offset_expr
.X_add_symbol
);
12660 macro_build (&offset_expr
, "lui", LUI_FMT
,
12661 AT
, BFD_RELOC_MIPS_GOT_HI16
);
12662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12663 AT
, AT
, mips_gp_register
);
12664 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
12665 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
12668 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12669 /* Itbl support may require additional care here. */
12670 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12671 BFD_RELOC_LO16
, AT
);
12672 expr1
.X_add_number
+= 4;
12674 /* Set mips_optimize to 2 to avoid inserting an undesired
12676 hold_mips_optimize
= mips_optimize
;
12678 /* Itbl support may require additional care here. */
12679 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12680 BFD_RELOC_LO16
, AT
);
12681 mips_optimize
= hold_mips_optimize
;
12682 expr1
.X_add_number
-= 4;
12685 offset_expr
.X_add_number
= expr1
.X_add_number
;
12687 macro_build (NULL
, "nop", "");
12688 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12689 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12692 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
12693 /* Itbl support may require additional care here. */
12694 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
12695 BFD_RELOC_LO16
, AT
);
12696 offset_expr
.X_add_number
+= 4;
12698 /* Set mips_optimize to 2 to avoid inserting an undesired
12700 hold_mips_optimize
= mips_optimize
;
12702 /* Itbl support may require additional care here. */
12703 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
12704 BFD_RELOC_LO16
, AT
);
12705 mips_optimize
= hold_mips_optimize
;
12719 gas_assert (!mips_opts
.micromips
);
12724 /* New code added to support COPZ instructions.
12725 This code builds table entries out of the macros in mip_opcodes.
12726 R4000 uses interlocks to handle coproc delays.
12727 Other chips (like the R3000) require nops to be inserted for delays.
12729 FIXME: Currently, we require that the user handle delays.
12730 In order to fill delay slots for non-interlocked chips,
12731 we must have a way to specify delays based on the coprocessor.
12732 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
12733 What are the side-effects of the cop instruction?
12734 What cache support might we have and what are its effects?
12735 Both coprocessor & memory require delays. how long???
12736 What registers are read/set/modified?
12738 If an itbl is provided to interpret cop instructions,
12739 this knowledge can be encoded in the itbl spec. */
12753 gas_assert (!mips_opts
.micromips
);
12754 /* For now we just do C (same as Cz). The parameter will be
12755 stored in insn_opcode by mips_ip. */
12756 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
12760 move_register (op
[0], op
[1]);
12764 gas_assert (mips_opts
.micromips
);
12765 gas_assert (mips_opts
.insn32
);
12766 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12767 micromips_to_32_reg_m_map
[op
[1]]);
12768 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12769 micromips_to_32_reg_n_map
[op
[2]]);
12774 /* Fall through. */
12776 if (mips_opts
.arch
== CPU_R5900
)
12777 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12781 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12782 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12788 /* Fall through. */
12790 /* The MIPS assembler some times generates shifts and adds. I'm
12791 not trying to be that fancy. GCC should do this for us
12794 load_register (AT
, &imm_expr
, dbl
);
12795 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12796 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12801 /* Fall through. */
12808 /* Fall through. */
12811 start_noreorder ();
12814 load_register (AT
, &imm_expr
, dbl
);
12815 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12816 op
[1], imm
? AT
: op
[2]);
12817 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12818 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12819 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12821 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12824 if (mips_opts
.micromips
)
12825 micromips_label_expr (&label_expr
);
12827 label_expr
.X_add_number
= 8;
12828 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12829 macro_build (NULL
, "nop", "");
12830 macro_build (NULL
, "break", BRK_FMT
, 6);
12831 if (mips_opts
.micromips
)
12832 micromips_add_label ();
12835 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12840 /* Fall through. */
12847 /* Fall through. */
12850 start_noreorder ();
12853 load_register (AT
, &imm_expr
, dbl
);
12854 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12855 op
[1], imm
? AT
: op
[2]);
12856 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12857 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12859 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12862 if (mips_opts
.micromips
)
12863 micromips_label_expr (&label_expr
);
12865 label_expr
.X_add_number
= 8;
12866 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12867 macro_build (NULL
, "nop", "");
12868 macro_build (NULL
, "break", BRK_FMT
, 6);
12869 if (mips_opts
.micromips
)
12870 micromips_add_label ();
12876 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12878 if (op
[0] == op
[1])
12885 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12886 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12890 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12891 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12892 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12893 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12897 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12899 if (op
[0] == op
[1])
12906 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12907 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12911 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12912 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12913 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12914 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12923 rot
= imm_expr
.X_add_number
& 0x3f;
12924 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12926 rot
= (64 - rot
) & 0x3f;
12928 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12930 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12935 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12938 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12939 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12942 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12943 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12944 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12952 rot
= imm_expr
.X_add_number
& 0x1f;
12953 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12955 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12956 (32 - rot
) & 0x1f);
12961 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12965 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12966 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12967 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12972 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12974 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12978 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12979 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12980 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12981 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12985 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12987 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12991 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12992 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12993 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12994 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13003 rot
= imm_expr
.X_add_number
& 0x3f;
13004 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13007 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13009 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13014 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13017 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13018 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13021 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13022 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13023 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13031 rot
= imm_expr
.X_add_number
& 0x1f;
13032 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13034 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13039 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13043 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13044 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13045 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13051 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13052 else if (op
[2] == 0)
13053 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13056 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13057 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13062 if (imm_expr
.X_add_number
== 0)
13064 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13069 as_warn (_("instruction %s: result is always false"),
13070 ip
->insn_mo
->name
);
13071 move_register (op
[0], 0);
13074 if (CPU_HAS_SEQ (mips_opts
.arch
)
13075 && -512 <= imm_expr
.X_add_number
13076 && imm_expr
.X_add_number
< 512)
13078 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13079 (int) imm_expr
.X_add_number
);
13082 if (imm_expr
.X_add_number
>= 0
13083 && imm_expr
.X_add_number
< 0x10000)
13084 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13085 else if (imm_expr
.X_add_number
> -0x8000
13086 && imm_expr
.X_add_number
< 0)
13088 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13089 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13090 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13092 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13095 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13096 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13101 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13102 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13105 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13108 case M_SGE
: /* X >= Y <==> not (X < Y) */
13114 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13115 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13118 case M_SGE_I
: /* X >= I <==> not (X < I) */
13120 if (imm_expr
.X_add_number
>= -0x8000
13121 && imm_expr
.X_add_number
< 0x8000)
13122 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13123 op
[0], op
[1], BFD_RELOC_LO16
);
13126 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13127 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13131 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13134 case M_SGT
: /* X > Y <==> Y < X */
13140 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13143 case M_SGT_I
: /* X > I <==> I < X */
13150 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13151 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13154 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
13160 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13161 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13164 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13171 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13172 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13173 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13177 if (imm_expr
.X_add_number
>= -0x8000
13178 && imm_expr
.X_add_number
< 0x8000)
13180 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13185 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13186 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13190 if (imm_expr
.X_add_number
>= -0x8000
13191 && imm_expr
.X_add_number
< 0x8000)
13193 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13198 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13199 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13204 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13205 else if (op
[2] == 0)
13206 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13209 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13210 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13215 if (imm_expr
.X_add_number
== 0)
13217 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13222 as_warn (_("instruction %s: result is always true"),
13223 ip
->insn_mo
->name
);
13224 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13225 op
[0], 0, BFD_RELOC_LO16
);
13228 if (CPU_HAS_SEQ (mips_opts
.arch
)
13229 && -512 <= imm_expr
.X_add_number
13230 && imm_expr
.X_add_number
< 512)
13232 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13233 (int) imm_expr
.X_add_number
);
13236 if (imm_expr
.X_add_number
>= 0
13237 && imm_expr
.X_add_number
< 0x10000)
13239 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13242 else if (imm_expr
.X_add_number
> -0x8000
13243 && imm_expr
.X_add_number
< 0)
13245 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13246 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13247 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13249 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13252 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13253 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13258 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13259 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13262 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13277 if (!mips_opts
.micromips
)
13279 if (imm_expr
.X_add_number
> -0x200
13280 && imm_expr
.X_add_number
<= 0x200)
13282 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13283 (int) -imm_expr
.X_add_number
);
13292 if (imm_expr
.X_add_number
> -0x8000
13293 && imm_expr
.X_add_number
<= 0x8000)
13295 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13296 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13301 load_register (AT
, &imm_expr
, dbl
);
13302 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13324 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13325 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13330 gas_assert (!mips_opts
.micromips
);
13331 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13335 * Is the double cfc1 instruction a bug in the mips assembler;
13336 * or is there a reason for it?
13338 start_noreorder ();
13339 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13340 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13341 macro_build (NULL
, "nop", "");
13342 expr1
.X_add_number
= 3;
13343 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13344 expr1
.X_add_number
= 2;
13345 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13346 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13347 macro_build (NULL
, "nop", "");
13348 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13350 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13351 macro_build (NULL
, "nop", "");
13368 offbits
= (mips_opts
.micromips
? 12 : 16);
13374 offbits
= (mips_opts
.micromips
? 12 : 16);
13386 offbits
= (mips_opts
.micromips
? 12 : 16);
13393 offbits
= (mips_opts
.micromips
? 12 : 16);
13399 large_offset
= !small_offset_p (off
, align
, offbits
);
13401 expr1
.X_add_number
= 0;
13406 if (small_offset_p (0, align
, 16))
13407 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13408 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13411 load_address (tempreg
, ep
, &used_at
);
13413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13414 tempreg
, tempreg
, breg
);
13416 offset_reloc
[0] = BFD_RELOC_LO16
;
13417 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13418 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13423 else if (!ust
&& op
[0] == breg
)
13434 if (!target_big_endian
)
13435 ep
->X_add_number
+= off
;
13437 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13439 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13440 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13442 if (!target_big_endian
)
13443 ep
->X_add_number
-= off
;
13445 ep
->X_add_number
+= off
;
13447 macro_build (NULL
, s2
, "t,~(b)",
13448 tempreg
, (int) ep
->X_add_number
, breg
);
13450 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13451 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13453 /* If necessary, move the result in tempreg to the final destination. */
13454 if (!ust
&& op
[0] != tempreg
)
13456 /* Protect second load's delay slot. */
13458 move_register (op
[0], tempreg
);
13464 if (target_big_endian
== ust
)
13465 ep
->X_add_number
+= off
;
13466 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13467 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13468 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13470 /* For halfword transfers we need a temporary register to shuffle
13471 bytes. Unfortunately for M_USH_A we have none available before
13472 the next store as AT holds the base address. We deal with this
13473 case by clobbering TREG and then restoring it as with ULH. */
13474 tempreg
= ust
== large_offset
? op
[0] : AT
;
13476 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13478 if (target_big_endian
== ust
)
13479 ep
->X_add_number
-= off
;
13481 ep
->X_add_number
+= off
;
13482 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13483 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13485 /* For M_USH_A re-retrieve the LSB. */
13486 if (ust
&& large_offset
)
13488 if (target_big_endian
)
13489 ep
->X_add_number
+= off
;
13491 ep
->X_add_number
-= off
;
13492 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13493 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13495 /* For ULH and M_USH_A OR the LSB in. */
13496 if (!ust
|| large_offset
)
13498 tempreg
= !large_offset
? AT
: op
[0];
13499 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13500 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13505 /* FIXME: Check if this is one of the itbl macros, since they
13506 are added dynamically. */
13507 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13510 if (!mips_opts
.at
&& used_at
)
13511 as_bad (_("macro used $at after \".set noat\""));
13514 /* Implement macros in mips16 mode. */
13517 mips16_macro (struct mips_cl_insn
*ip
)
13519 const struct mips_operand_array
*operands
;
13524 const char *s
, *s2
, *s3
;
13525 unsigned int op
[MAX_OPERANDS
];
13528 mask
= ip
->insn_mo
->mask
;
13530 operands
= insn_operands (ip
);
13531 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13532 if (operands
->operand
[i
])
13533 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
13537 expr1
.X_op
= O_constant
;
13538 expr1
.X_op_symbol
= NULL
;
13539 expr1
.X_add_symbol
= NULL
;
13540 expr1
.X_add_number
= 1;
13551 /* Fall through. */
13557 /* Fall through. */
13561 start_noreorder ();
13562 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
13563 expr1
.X_add_number
= 2;
13564 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13565 macro_build (NULL
, "break", "6", 7);
13567 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
13568 since that causes an overflow. We should do that as well,
13569 but I don't see how to do the comparisons without a temporary
13572 macro_build (NULL
, s
, "x", op
[0]);
13591 start_noreorder ();
13592 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
13593 expr1
.X_add_number
= 2;
13594 macro_build (&expr1
, "bnez", "x,p", op
[2]);
13595 macro_build (NULL
, "break", "6", 7);
13597 macro_build (NULL
, s2
, "x", op
[0]);
13602 /* Fall through. */
13604 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
13605 macro_build (NULL
, "mflo", "x", op
[0]);
13613 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13614 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
13618 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13619 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
13623 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13624 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
13646 goto do_reverse_branch
;
13650 goto do_reverse_branch
;
13662 goto do_reverse_branch
;
13673 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
13674 macro_build (&offset_expr
, s2
, "p");
13701 goto do_addone_branch_i
;
13706 goto do_addone_branch_i
;
13721 goto do_addone_branch_i
;
13727 do_addone_branch_i
:
13728 ++imm_expr
.X_add_number
;
13731 macro_build (&imm_expr
, s
, s3
, op
[0]);
13732 macro_build (&offset_expr
, s2
, "p");
13736 expr1
.X_add_number
= 0;
13737 macro_build (&expr1
, "slti", "x,8", op
[1]);
13738 if (op
[0] != op
[1])
13739 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
13740 expr1
.X_add_number
= 2;
13741 macro_build (&expr1
, "bteqz", "p");
13742 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
13747 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
13748 opcode bits in *OPCODE_EXTRA. */
13750 static struct mips_opcode
*
13751 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13752 ssize_t length
, unsigned int *opcode_extra
)
13754 char *name
, *dot
, *p
;
13755 unsigned int mask
, suffix
;
13757 struct mips_opcode
*insn
;
13759 /* Make a copy of the instruction so that we can fiddle with it. */
13760 name
= xstrndup (start
, length
);
13762 /* Look up the instruction as-is. */
13763 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13767 dot
= strchr (name
, '.');
13770 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13771 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13772 if (*p
== 0 && mask
!= 0)
13775 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13777 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13779 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13785 if (mips_opts
.micromips
)
13787 /* See if there's an instruction size override suffix,
13788 either `16' or `32', at the end of the mnemonic proper,
13789 that defines the operation, i.e. before the first `.'
13790 character if any. Strip it and retry. */
13791 opend
= dot
!= NULL
? dot
- name
: length
;
13792 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13794 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13800 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13801 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13804 forced_insn_length
= suffix
;
13816 /* Assemble an instruction into its binary format. If the instruction
13817 is a macro, set imm_expr and offset_expr to the values associated
13818 with "I" and "A" operands respectively. Otherwise store the value
13819 of the relocatable field (if any) in offset_expr. In both cases
13820 set offset_reloc to the relocation operators applied to offset_expr. */
13823 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13825 const struct mips_opcode
*first
, *past
;
13826 struct hash_control
*hash
;
13829 struct mips_operand_token
*tokens
;
13830 unsigned int opcode_extra
;
13832 if (mips_opts
.micromips
)
13834 hash
= micromips_op_hash
;
13835 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13840 past
= &mips_opcodes
[NUMOPCODES
];
13842 forced_insn_length
= 0;
13845 /* We first try to match an instruction up to a space or to the end. */
13846 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13849 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13852 set_insn_error (0, _("unrecognized opcode"));
13856 if (strcmp (first
->name
, "li.s") == 0)
13858 else if (strcmp (first
->name
, "li.d") == 0)
13862 tokens
= mips_parse_arguments (str
+ end
, format
);
13866 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13867 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13868 set_insn_error (0, _("invalid operands"));
13870 obstack_free (&mips_operand_tokens
, tokens
);
13873 /* As for mips_ip, but used when assembling MIPS16 code.
13874 Also set forced_insn_length to the resulting instruction size in
13875 bytes if the user explicitly requested a small or extended instruction. */
13878 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13881 struct mips_opcode
*first
;
13882 struct mips_operand_token
*tokens
;
13885 for (s
= str
; ISLOWER (*s
); ++s
)
13907 else if (*s
== 'e')
13914 else if (*s
++ == ' ')
13916 /* Fall through. */
13918 set_insn_error (0, _("unrecognized opcode"));
13921 forced_insn_length
= l
;
13924 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13929 set_insn_error (0, _("unrecognized opcode"));
13933 tokens
= mips_parse_arguments (s
, 0);
13937 if (!match_mips16_insns (insn
, first
, tokens
))
13938 set_insn_error (0, _("invalid operands"));
13940 obstack_free (&mips_operand_tokens
, tokens
);
13943 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13944 NBITS is the number of significant bits in VAL. */
13946 static unsigned long
13947 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13952 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13955 else if (nbits
== 15)
13957 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13962 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13965 return (extval
<< 16) | val
;
13968 /* Like decode_mips16_operand, but require the operand to be defined and
13969 require it to be an integer. */
13971 static const struct mips_int_operand
*
13972 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13974 const struct mips_operand
*operand
;
13976 operand
= decode_mips16_operand (type
, extended_p
);
13977 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13979 return (const struct mips_int_operand
*) operand
;
13982 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13985 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13986 bfd_reloc_code_real_type reloc
, offsetT sval
)
13988 int min_val
, max_val
;
13990 min_val
= mips_int_operand_min (operand
);
13991 max_val
= mips_int_operand_max (operand
);
13992 if (reloc
!= BFD_RELOC_UNUSED
)
13995 sval
= SEXT_16BIT (sval
);
14000 return (sval
>= min_val
14002 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14005 /* Install immediate value VAL into MIPS16 instruction *INSN,
14006 extending it if necessary. The instruction in *INSN may
14007 already be extended.
14009 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14010 if none. In the former case, VAL is a 16-bit number with no
14011 defined signedness.
14013 TYPE is the type of the immediate field. USER_INSN_LENGTH
14014 is the length that the user requested, or 0 if none. */
14017 mips16_immed (const char *file
, unsigned int line
, int type
,
14018 bfd_reloc_code_real_type reloc
, offsetT val
,
14019 unsigned int user_insn_length
, unsigned long *insn
)
14021 const struct mips_int_operand
*operand
;
14022 unsigned int uval
, length
;
14024 operand
= mips16_immed_operand (type
, FALSE
);
14025 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14027 /* We need an extended instruction. */
14028 if (user_insn_length
== 2)
14029 as_bad_where (file
, line
, _("invalid unextended operand value"));
14031 *insn
|= MIPS16_EXTEND
;
14033 else if (user_insn_length
== 4)
14035 /* The operand doesn't force an unextended instruction to be extended.
14036 Warn if the user wanted an extended instruction anyway. */
14037 *insn
|= MIPS16_EXTEND
;
14038 as_warn_where (file
, line
,
14039 _("extended operand requested but not required"));
14042 length
= mips16_opcode_length (*insn
);
14045 operand
= mips16_immed_operand (type
, TRUE
);
14046 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14047 as_bad_where (file
, line
,
14048 _("operand value out of range for instruction"));
14050 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14051 if (length
== 2 || operand
->root
.lsb
!= 0)
14052 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14054 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14057 struct percent_op_match
14060 bfd_reloc_code_real_type reloc
;
14063 static const struct percent_op_match mips_percent_op
[] =
14065 {"%lo", BFD_RELOC_LO16
},
14066 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14067 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14068 {"%call16", BFD_RELOC_MIPS_CALL16
},
14069 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14070 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14071 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14072 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14073 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14074 {"%got", BFD_RELOC_MIPS_GOT16
},
14075 {"%gp_rel", BFD_RELOC_GPREL16
},
14076 {"%half", BFD_RELOC_16
},
14077 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14078 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14079 {"%neg", BFD_RELOC_MIPS_SUB
},
14080 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14081 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14082 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14083 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14084 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14085 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14086 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14087 {"%hi", BFD_RELOC_HI16_S
},
14088 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14089 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14092 static const struct percent_op_match mips16_percent_op
[] =
14094 {"%lo", BFD_RELOC_MIPS16_LO16
},
14095 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14096 {"%got", BFD_RELOC_MIPS16_GOT16
},
14097 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14098 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14099 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14100 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14101 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14102 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14103 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14104 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14105 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14109 /* Return true if *STR points to a relocation operator. When returning true,
14110 move *STR over the operator and store its relocation code in *RELOC.
14111 Leave both *STR and *RELOC alone when returning false. */
14114 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14116 const struct percent_op_match
*percent_op
;
14119 if (mips_opts
.mips16
)
14121 percent_op
= mips16_percent_op
;
14122 limit
= ARRAY_SIZE (mips16_percent_op
);
14126 percent_op
= mips_percent_op
;
14127 limit
= ARRAY_SIZE (mips_percent_op
);
14130 for (i
= 0; i
< limit
; i
++)
14131 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14133 int len
= strlen (percent_op
[i
].str
);
14135 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14138 *str
+= strlen (percent_op
[i
].str
);
14139 *reloc
= percent_op
[i
].reloc
;
14141 /* Check whether the output BFD supports this relocation.
14142 If not, issue an error and fall back on something safe. */
14143 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14145 as_bad (_("relocation %s isn't supported by the current ABI"),
14146 percent_op
[i
].str
);
14147 *reloc
= BFD_RELOC_UNUSED
;
14155 /* Parse string STR as a 16-bit relocatable operand. Store the
14156 expression in *EP and the relocations in the array starting
14157 at RELOC. Return the number of relocation operators used.
14159 On exit, EXPR_END points to the first character after the expression. */
14162 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14165 bfd_reloc_code_real_type reversed_reloc
[3];
14166 size_t reloc_index
, i
;
14167 int crux_depth
, str_depth
;
14170 /* Search for the start of the main expression, recoding relocations
14171 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14172 of the main expression and with CRUX_DEPTH containing the number
14173 of open brackets at that point. */
14180 crux_depth
= str_depth
;
14182 /* Skip over whitespace and brackets, keeping count of the number
14184 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14189 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14190 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14192 my_getExpression (ep
, crux
);
14195 /* Match every open bracket. */
14196 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14200 if (crux_depth
> 0)
14201 as_bad (_("unclosed '('"));
14205 if (reloc_index
!= 0)
14207 prev_reloc_op_frag
= frag_now
;
14208 for (i
= 0; i
< reloc_index
; i
++)
14209 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14212 return reloc_index
;
14216 my_getExpression (expressionS
*ep
, char *str
)
14220 save_in
= input_line_pointer
;
14221 input_line_pointer
= str
;
14223 expr_end
= input_line_pointer
;
14224 input_line_pointer
= save_in
;
14228 md_atof (int type
, char *litP
, int *sizeP
)
14230 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14234 md_number_to_chars (char *buf
, valueT val
, int n
)
14236 if (target_big_endian
)
14237 number_to_chars_bigendian (buf
, val
, n
);
14239 number_to_chars_littleendian (buf
, val
, n
);
14242 static int support_64bit_objects(void)
14244 const char **list
, **l
;
14247 list
= bfd_target_list ();
14248 for (l
= list
; *l
!= NULL
; l
++)
14249 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14250 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14252 yes
= (*l
!= NULL
);
14257 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14258 NEW_VALUE. Warn if another value was already specified. Note:
14259 we have to defer parsing the -march and -mtune arguments in order
14260 to handle 'from-abi' correctly, since the ABI might be specified
14261 in a later argument. */
14264 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14266 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14267 as_warn (_("a different %s was already specified, is now %s"),
14268 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14271 *string_ptr
= new_value
;
14275 md_parse_option (int c
, const char *arg
)
14279 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14280 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14282 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14283 c
== mips_ases
[i
].option_on
);
14289 case OPTION_CONSTRUCT_FLOATS
:
14290 mips_disable_float_construction
= 0;
14293 case OPTION_NO_CONSTRUCT_FLOATS
:
14294 mips_disable_float_construction
= 1;
14306 target_big_endian
= 1;
14310 target_big_endian
= 0;
14316 else if (arg
[0] == '0')
14318 else if (arg
[0] == '1')
14328 mips_debug
= atoi (arg
);
14332 file_mips_opts
.isa
= ISA_MIPS1
;
14336 file_mips_opts
.isa
= ISA_MIPS2
;
14340 file_mips_opts
.isa
= ISA_MIPS3
;
14344 file_mips_opts
.isa
= ISA_MIPS4
;
14348 file_mips_opts
.isa
= ISA_MIPS5
;
14351 case OPTION_MIPS32
:
14352 file_mips_opts
.isa
= ISA_MIPS32
;
14355 case OPTION_MIPS32R2
:
14356 file_mips_opts
.isa
= ISA_MIPS32R2
;
14359 case OPTION_MIPS32R3
:
14360 file_mips_opts
.isa
= ISA_MIPS32R3
;
14363 case OPTION_MIPS32R5
:
14364 file_mips_opts
.isa
= ISA_MIPS32R5
;
14367 case OPTION_MIPS32R6
:
14368 file_mips_opts
.isa
= ISA_MIPS32R6
;
14371 case OPTION_MIPS64R2
:
14372 file_mips_opts
.isa
= ISA_MIPS64R2
;
14375 case OPTION_MIPS64R3
:
14376 file_mips_opts
.isa
= ISA_MIPS64R3
;
14379 case OPTION_MIPS64R5
:
14380 file_mips_opts
.isa
= ISA_MIPS64R5
;
14383 case OPTION_MIPS64R6
:
14384 file_mips_opts
.isa
= ISA_MIPS64R6
;
14387 case OPTION_MIPS64
:
14388 file_mips_opts
.isa
= ISA_MIPS64
;
14392 mips_set_option_string (&mips_tune_string
, arg
);
14396 mips_set_option_string (&mips_arch_string
, arg
);
14400 mips_set_option_string (&mips_arch_string
, "4650");
14401 mips_set_option_string (&mips_tune_string
, "4650");
14404 case OPTION_NO_M4650
:
14408 mips_set_option_string (&mips_arch_string
, "4010");
14409 mips_set_option_string (&mips_tune_string
, "4010");
14412 case OPTION_NO_M4010
:
14416 mips_set_option_string (&mips_arch_string
, "4100");
14417 mips_set_option_string (&mips_tune_string
, "4100");
14420 case OPTION_NO_M4100
:
14424 mips_set_option_string (&mips_arch_string
, "3900");
14425 mips_set_option_string (&mips_tune_string
, "3900");
14428 case OPTION_NO_M3900
:
14431 case OPTION_MICROMIPS
:
14432 if (file_mips_opts
.mips16
== 1)
14434 as_bad (_("-mmicromips cannot be used with -mips16"));
14437 file_mips_opts
.micromips
= 1;
14438 mips_no_prev_insn ();
14441 case OPTION_NO_MICROMIPS
:
14442 file_mips_opts
.micromips
= 0;
14443 mips_no_prev_insn ();
14446 case OPTION_MIPS16
:
14447 if (file_mips_opts
.micromips
== 1)
14449 as_bad (_("-mips16 cannot be used with -micromips"));
14452 file_mips_opts
.mips16
= 1;
14453 mips_no_prev_insn ();
14456 case OPTION_NO_MIPS16
:
14457 file_mips_opts
.mips16
= 0;
14458 mips_no_prev_insn ();
14461 case OPTION_FIX_24K
:
14465 case OPTION_NO_FIX_24K
:
14469 case OPTION_FIX_RM7000
:
14470 mips_fix_rm7000
= 1;
14473 case OPTION_NO_FIX_RM7000
:
14474 mips_fix_rm7000
= 0;
14477 case OPTION_FIX_LOONGSON2F_JUMP
:
14478 mips_fix_loongson2f_jump
= TRUE
;
14481 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14482 mips_fix_loongson2f_jump
= FALSE
;
14485 case OPTION_FIX_LOONGSON2F_NOP
:
14486 mips_fix_loongson2f_nop
= TRUE
;
14489 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14490 mips_fix_loongson2f_nop
= FALSE
;
14493 case OPTION_FIX_VR4120
:
14494 mips_fix_vr4120
= 1;
14497 case OPTION_NO_FIX_VR4120
:
14498 mips_fix_vr4120
= 0;
14501 case OPTION_FIX_VR4130
:
14502 mips_fix_vr4130
= 1;
14505 case OPTION_NO_FIX_VR4130
:
14506 mips_fix_vr4130
= 0;
14509 case OPTION_FIX_CN63XXP1
:
14510 mips_fix_cn63xxp1
= TRUE
;
14513 case OPTION_NO_FIX_CN63XXP1
:
14514 mips_fix_cn63xxp1
= FALSE
;
14517 case OPTION_RELAX_BRANCH
:
14518 mips_relax_branch
= 1;
14521 case OPTION_NO_RELAX_BRANCH
:
14522 mips_relax_branch
= 0;
14525 case OPTION_IGNORE_BRANCH_ISA
:
14526 mips_ignore_branch_isa
= TRUE
;
14529 case OPTION_NO_IGNORE_BRANCH_ISA
:
14530 mips_ignore_branch_isa
= FALSE
;
14533 case OPTION_INSN32
:
14534 file_mips_opts
.insn32
= TRUE
;
14537 case OPTION_NO_INSN32
:
14538 file_mips_opts
.insn32
= FALSE
;
14541 case OPTION_MSHARED
:
14542 mips_in_shared
= TRUE
;
14545 case OPTION_MNO_SHARED
:
14546 mips_in_shared
= FALSE
;
14549 case OPTION_MSYM32
:
14550 file_mips_opts
.sym32
= TRUE
;
14553 case OPTION_MNO_SYM32
:
14554 file_mips_opts
.sym32
= FALSE
;
14557 /* When generating ELF code, we permit -KPIC and -call_shared to
14558 select SVR4_PIC, and -non_shared to select no PIC. This is
14559 intended to be compatible with Irix 5. */
14560 case OPTION_CALL_SHARED
:
14561 mips_pic
= SVR4_PIC
;
14562 mips_abicalls
= TRUE
;
14565 case OPTION_CALL_NONPIC
:
14567 mips_abicalls
= TRUE
;
14570 case OPTION_NON_SHARED
:
14572 mips_abicalls
= FALSE
;
14575 /* The -xgot option tells the assembler to use 32 bit offsets
14576 when accessing the got in SVR4_PIC mode. It is for Irix
14583 g_switch_value
= atoi (arg
);
14587 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14590 mips_abi
= O32_ABI
;
14594 mips_abi
= N32_ABI
;
14598 mips_abi
= N64_ABI
;
14599 if (!support_64bit_objects())
14600 as_fatal (_("no compiled in support for 64 bit object file format"));
14604 file_mips_opts
.gp
= 32;
14608 file_mips_opts
.gp
= 64;
14612 file_mips_opts
.fp
= 32;
14616 file_mips_opts
.fp
= 0;
14620 file_mips_opts
.fp
= 64;
14623 case OPTION_ODD_SPREG
:
14624 file_mips_opts
.oddspreg
= 1;
14627 case OPTION_NO_ODD_SPREG
:
14628 file_mips_opts
.oddspreg
= 0;
14631 case OPTION_SINGLE_FLOAT
:
14632 file_mips_opts
.single_float
= 1;
14635 case OPTION_DOUBLE_FLOAT
:
14636 file_mips_opts
.single_float
= 0;
14639 case OPTION_SOFT_FLOAT
:
14640 file_mips_opts
.soft_float
= 1;
14643 case OPTION_HARD_FLOAT
:
14644 file_mips_opts
.soft_float
= 0;
14648 if (strcmp (arg
, "32") == 0)
14649 mips_abi
= O32_ABI
;
14650 else if (strcmp (arg
, "o64") == 0)
14651 mips_abi
= O64_ABI
;
14652 else if (strcmp (arg
, "n32") == 0)
14653 mips_abi
= N32_ABI
;
14654 else if (strcmp (arg
, "64") == 0)
14656 mips_abi
= N64_ABI
;
14657 if (! support_64bit_objects())
14658 as_fatal (_("no compiled in support for 64 bit object file "
14661 else if (strcmp (arg
, "eabi") == 0)
14662 mips_abi
= EABI_ABI
;
14665 as_fatal (_("invalid abi -mabi=%s"), arg
);
14670 case OPTION_M7000_HILO_FIX
:
14671 mips_7000_hilo_fix
= TRUE
;
14674 case OPTION_MNO_7000_HILO_FIX
:
14675 mips_7000_hilo_fix
= FALSE
;
14678 case OPTION_MDEBUG
:
14679 mips_flag_mdebug
= TRUE
;
14682 case OPTION_NO_MDEBUG
:
14683 mips_flag_mdebug
= FALSE
;
14687 mips_flag_pdr
= TRUE
;
14690 case OPTION_NO_PDR
:
14691 mips_flag_pdr
= FALSE
;
14694 case OPTION_MVXWORKS_PIC
:
14695 mips_pic
= VXWORKS_PIC
;
14699 if (strcmp (arg
, "2008") == 0)
14701 else if (strcmp (arg
, "legacy") == 0)
14705 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
14714 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
14719 /* Set up globals to tune for the ISA or processor described by INFO. */
14722 mips_set_tune (const struct mips_cpu_info
*info
)
14725 mips_tune
= info
->cpu
;
14730 mips_after_parse_args (void)
14732 const struct mips_cpu_info
*arch_info
= 0;
14733 const struct mips_cpu_info
*tune_info
= 0;
14735 /* GP relative stuff not working for PE */
14736 if (strncmp (TARGET_OS
, "pe", 2) == 0)
14738 if (g_switch_seen
&& g_switch_value
!= 0)
14739 as_bad (_("-G not supported in this configuration"));
14740 g_switch_value
= 0;
14743 if (mips_abi
== NO_ABI
)
14744 mips_abi
= MIPS_DEFAULT_ABI
;
14746 /* The following code determines the architecture.
14747 Similar code was added to GCC 3.3 (see override_options() in
14748 config/mips/mips.c). The GAS and GCC code should be kept in sync
14749 as much as possible. */
14751 if (mips_arch_string
!= 0)
14752 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
14754 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
14756 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14757 ISA level specified by -mipsN, while arch_info->isa contains
14758 the -march selection (if any). */
14759 if (arch_info
!= 0)
14761 /* -march takes precedence over -mipsN, since it is more descriptive.
14762 There's no harm in specifying both as long as the ISA levels
14764 if (file_mips_opts
.isa
!= arch_info
->isa
)
14765 as_bad (_("-%s conflicts with the other architecture options,"
14766 " which imply -%s"),
14767 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
14768 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
14771 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
14774 if (arch_info
== 0)
14776 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
14777 gas_assert (arch_info
);
14780 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
14781 as_bad (_("-march=%s is not compatible with the selected ABI"),
14784 file_mips_opts
.arch
= arch_info
->cpu
;
14785 file_mips_opts
.isa
= arch_info
->isa
;
14787 /* Set up initial mips_opts state. */
14788 mips_opts
= file_mips_opts
;
14790 /* The register size inference code is now placed in
14791 file_mips_check_options. */
14793 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
14795 if (mips_tune_string
!= 0)
14796 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
14798 if (tune_info
== 0)
14799 mips_set_tune (arch_info
);
14801 mips_set_tune (tune_info
);
14803 if (mips_flag_mdebug
< 0)
14804 mips_flag_mdebug
= 0;
14808 mips_init_after_args (void)
14810 /* initialize opcodes */
14811 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14812 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14816 md_pcrel_from (fixS
*fixP
)
14818 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14819 switch (fixP
->fx_r_type
)
14821 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14822 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14823 /* Return the address of the delay slot. */
14826 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14827 case BFD_RELOC_MICROMIPS_JMP
:
14828 case BFD_RELOC_MIPS16_16_PCREL_S1
:
14829 case BFD_RELOC_16_PCREL_S2
:
14830 case BFD_RELOC_MIPS_21_PCREL_S2
:
14831 case BFD_RELOC_MIPS_26_PCREL_S2
:
14832 case BFD_RELOC_MIPS_JMP
:
14833 /* Return the address of the delay slot. */
14836 case BFD_RELOC_MIPS_18_PCREL_S3
:
14837 /* Return the aligned address of the doubleword containing
14838 the instruction. */
14846 /* This is called before the symbol table is processed. In order to
14847 work with gcc when using mips-tfile, we must keep all local labels.
14848 However, in other cases, we want to discard them. If we were
14849 called with -g, but we didn't see any debugging information, it may
14850 mean that gcc is smuggling debugging information through to
14851 mips-tfile, in which case we must generate all local labels. */
14854 mips_frob_file_before_adjust (void)
14856 #ifndef NO_ECOFF_DEBUGGING
14857 if (ECOFF_DEBUGGING
14859 && ! ecoff_debugging_seen
)
14860 flag_keep_locals
= 1;
14864 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14865 the corresponding LO16 reloc. This is called before md_apply_fix and
14866 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14867 relocation operators.
14869 For our purposes, a %lo() expression matches a %got() or %hi()
14872 (a) it refers to the same symbol; and
14873 (b) the offset applied in the %lo() expression is no lower than
14874 the offset applied in the %got() or %hi().
14876 (b) allows us to cope with code like:
14879 lh $4,%lo(foo+2)($4)
14881 ...which is legal on RELA targets, and has a well-defined behaviour
14882 if the user knows that adding 2 to "foo" will not induce a carry to
14885 When several %lo()s match a particular %got() or %hi(), we use the
14886 following rules to distinguish them:
14888 (1) %lo()s with smaller offsets are a better match than %lo()s with
14891 (2) %lo()s with no matching %got() or %hi() are better than those
14892 that already have a matching %got() or %hi().
14894 (3) later %lo()s are better than earlier %lo()s.
14896 These rules are applied in order.
14898 (1) means, among other things, that %lo()s with identical offsets are
14899 chosen if they exist.
14901 (2) means that we won't associate several high-part relocations with
14902 the same low-part relocation unless there's no alternative. Having
14903 several high parts for the same low part is a GNU extension; this rule
14904 allows careful users to avoid it.
14906 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14907 with the last high-part relocation being at the front of the list.
14908 It therefore makes sense to choose the last matching low-part
14909 relocation, all other things being equal. It's also easier
14910 to code that way. */
14913 mips_frob_file (void)
14915 struct mips_hi_fixup
*l
;
14916 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14918 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14920 segment_info_type
*seginfo
;
14921 bfd_boolean matched_lo_p
;
14922 fixS
**hi_pos
, **lo_pos
, **pos
;
14924 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14926 /* If a GOT16 relocation turns out to be against a global symbol,
14927 there isn't supposed to be a matching LO. Ignore %gots against
14928 constants; we'll report an error for those later. */
14929 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14930 && !(l
->fixp
->fx_addsy
14931 && pic_need_relax (l
->fixp
->fx_addsy
)))
14934 /* Check quickly whether the next fixup happens to be a matching %lo. */
14935 if (fixup_has_matching_lo_p (l
->fixp
))
14938 seginfo
= seg_info (l
->seg
);
14940 /* Set HI_POS to the position of this relocation in the chain.
14941 Set LO_POS to the position of the chosen low-part relocation.
14942 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14943 relocation that matches an immediately-preceding high-part
14947 matched_lo_p
= FALSE
;
14948 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14950 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14952 if (*pos
== l
->fixp
)
14955 if ((*pos
)->fx_r_type
== looking_for_rtype
14956 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14957 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14959 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14961 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14964 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14965 && fixup_has_matching_lo_p (*pos
));
14968 /* If we found a match, remove the high-part relocation from its
14969 current position and insert it before the low-part relocation.
14970 Make the offsets match so that fixup_has_matching_lo_p()
14973 We don't warn about unmatched high-part relocations since some
14974 versions of gcc have been known to emit dead "lui ...%hi(...)"
14976 if (lo_pos
!= NULL
)
14978 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14979 if (l
->fixp
->fx_next
!= *lo_pos
)
14981 *hi_pos
= l
->fixp
->fx_next
;
14982 l
->fixp
->fx_next
= *lo_pos
;
14990 mips_force_relocation (fixS
*fixp
)
14992 if (generic_force_reloc (fixp
))
14995 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14996 so that the linker relaxation can update targets. */
14997 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14998 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14999 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15002 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15003 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15004 microMIPS symbols so that we can do cross-mode branch diagnostics
15005 and BAL to JALX conversion by the linker. */
15006 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15007 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15008 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15010 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15013 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15014 if (ISA_IS_R6 (file_mips_opts
.isa
)
15015 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15016 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15017 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15018 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15019 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15020 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15021 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15027 /* Implement TC_FORCE_RELOCATION_ABS. */
15030 mips_force_relocation_abs (fixS
*fixp
)
15032 if (generic_force_reloc (fixp
))
15035 /* These relocations do not have enough bits in the in-place addend
15036 to hold an arbitrary absolute section's offset. */
15037 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15043 /* Read the instruction associated with RELOC from BUF. */
15045 static unsigned int
15046 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15048 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15049 return read_compressed_insn (buf
, 4);
15051 return read_insn (buf
);
15054 /* Write instruction INSN to BUF, given that it has been relocated
15058 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15059 unsigned long insn
)
15061 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15062 write_compressed_insn (buf
, insn
, 4);
15064 write_insn (buf
, insn
);
15067 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15068 to a symbol in another ISA mode, which cannot be converted to JALX. */
15071 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15073 unsigned long opcode
;
15077 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15080 other
= S_GET_OTHER (fixP
->fx_addsy
);
15081 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15082 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15083 switch (fixP
->fx_r_type
)
15085 case BFD_RELOC_MIPS_JMP
:
15086 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15087 case BFD_RELOC_MICROMIPS_JMP
:
15088 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15094 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15095 jump to a symbol in the same ISA mode. */
15098 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15100 unsigned long opcode
;
15104 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15107 other
= S_GET_OTHER (fixP
->fx_addsy
);
15108 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15109 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15110 switch (fixP
->fx_r_type
)
15112 case BFD_RELOC_MIPS_JMP
:
15113 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15114 case BFD_RELOC_MIPS16_JMP
:
15115 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15116 case BFD_RELOC_MICROMIPS_JMP
:
15117 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15123 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15124 to a symbol whose value plus addend is not aligned according to the
15125 ultimate (after linker relaxation) jump instruction's immediate field
15126 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15127 regular MIPS code, to (1 << 2). */
15130 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15132 bfd_boolean micro_to_mips_p
;
15136 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15139 other
= S_GET_OTHER (fixP
->fx_addsy
);
15140 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15141 val
+= fixP
->fx_offset
;
15142 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15143 && !ELF_ST_IS_MICROMIPS (other
));
15144 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15145 != ELF_ST_IS_COMPRESSED (other
));
15148 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15149 to a symbol whose annotation indicates another ISA mode. For absolute
15150 symbols check the ISA bit instead.
15152 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15153 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15154 MIPS symbols and associated with BAL instructions as these instructions
15155 may be be converted to JALX by the linker. */
15158 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15160 bfd_boolean absolute_p
;
15161 unsigned long opcode
;
15167 if (mips_ignore_branch_isa
)
15170 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15173 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15174 absolute_p
= bfd_is_abs_section (symsec
);
15176 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15177 other
= S_GET_OTHER (fixP
->fx_addsy
);
15179 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15180 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15181 switch (fixP
->fx_r_type
)
15183 case BFD_RELOC_16_PCREL_S2
:
15184 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15185 && opcode
!= 0x0411);
15186 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15187 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15188 && opcode
!= 0x4060);
15189 case BFD_RELOC_MIPS_21_PCREL_S2
:
15190 case BFD_RELOC_MIPS_26_PCREL_S2
:
15191 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15192 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15193 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15194 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15195 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15196 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15202 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15203 branch instruction pointed to by FIXP is not aligned according to the
15204 branch instruction's immediate field requirement. We need the addend
15205 to preserve the ISA bit and also the sum must not have bit 2 set. We
15206 must explicitly OR in the ISA bit from symbol annotation as the bit
15207 won't be set in the symbol's value then. */
15210 fix_bad_misaligned_branch_p (fixS
*fixP
)
15212 bfd_boolean absolute_p
;
15219 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15222 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15223 absolute_p
= bfd_is_abs_section (symsec
);
15225 val
= S_GET_VALUE (fixP
->fx_addsy
);
15226 other
= S_GET_OTHER (fixP
->fx_addsy
);
15227 off
= fixP
->fx_offset
;
15229 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15230 val
|= ELF_ST_IS_COMPRESSED (other
);
15232 return (val
& 0x3) != isa_bit
;
15235 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15236 and its calculated value VAL. */
15239 fix_validate_branch (fixS
*fixP
, valueT val
)
15241 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15243 _("branch to misaligned address (0x%lx)"),
15244 (long) (val
+ md_pcrel_from (fixP
)));
15245 else if (fix_bad_cross_mode_branch_p (fixP
))
15246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15247 _("branch to a symbol in another ISA mode"));
15248 else if (fix_bad_misaligned_branch_p (fixP
))
15249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15250 _("branch to misaligned address (0x%lx)"),
15251 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15252 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15254 _("cannot encode misaligned addend "
15255 "in the relocatable field (0x%lx)"),
15256 (long) fixP
->fx_offset
);
15259 /* Apply a fixup to the object file. */
15262 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15265 unsigned long insn
;
15266 reloc_howto_type
*howto
;
15268 if (fixP
->fx_pcrel
)
15269 switch (fixP
->fx_r_type
)
15271 case BFD_RELOC_16_PCREL_S2
:
15272 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15273 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15274 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15275 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15276 case BFD_RELOC_32_PCREL
:
15277 case BFD_RELOC_MIPS_21_PCREL_S2
:
15278 case BFD_RELOC_MIPS_26_PCREL_S2
:
15279 case BFD_RELOC_MIPS_18_PCREL_S3
:
15280 case BFD_RELOC_MIPS_19_PCREL_S2
:
15281 case BFD_RELOC_HI16_S_PCREL
:
15282 case BFD_RELOC_LO16_PCREL
:
15286 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15290 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15291 _("PC-relative reference to a different section"));
15295 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15296 that have no MIPS ELF equivalent. */
15297 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15299 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15304 gas_assert (fixP
->fx_size
== 2
15305 || fixP
->fx_size
== 4
15306 || fixP
->fx_r_type
== BFD_RELOC_8
15307 || fixP
->fx_r_type
== BFD_RELOC_16
15308 || fixP
->fx_r_type
== BFD_RELOC_64
15309 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15310 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15311 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15312 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15313 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15314 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15315 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15317 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15319 /* Don't treat parts of a composite relocation as done. There are two
15322 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15323 should nevertheless be emitted if the first part is.
15325 (2) In normal usage, composite relocations are never assembly-time
15326 constants. The easiest way of dealing with the pathological
15327 exceptions is to generate a relocation against STN_UNDEF and
15328 leave everything up to the linker. */
15329 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15332 switch (fixP
->fx_r_type
)
15334 case BFD_RELOC_MIPS_TLS_GD
:
15335 case BFD_RELOC_MIPS_TLS_LDM
:
15336 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15337 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15338 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15339 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15340 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15341 case BFD_RELOC_MIPS_TLS_TPREL32
:
15342 case BFD_RELOC_MIPS_TLS_TPREL64
:
15343 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15344 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15345 case BFD_RELOC_MICROMIPS_TLS_GD
:
15346 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15347 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15348 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15349 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15350 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15351 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15352 case BFD_RELOC_MIPS16_TLS_GD
:
15353 case BFD_RELOC_MIPS16_TLS_LDM
:
15354 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15355 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15356 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15357 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15358 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15359 if (fixP
->fx_addsy
)
15360 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15363 _("TLS relocation against a constant"));
15366 case BFD_RELOC_MIPS_JMP
:
15367 case BFD_RELOC_MIPS16_JMP
:
15368 case BFD_RELOC_MICROMIPS_JMP
:
15372 gas_assert (!fixP
->fx_done
);
15374 /* Shift is 2, unusually, for microMIPS JALX. */
15375 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15376 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15381 if (fix_bad_cross_mode_jump_p (fixP
))
15382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15383 _("jump to a symbol in another ISA mode"));
15384 else if (fix_bad_same_mode_jalx_p (fixP
))
15385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15386 _("JALX to a symbol in the same ISA mode"));
15387 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15389 _("jump to misaligned address (0x%lx)"),
15390 (long) (S_GET_VALUE (fixP
->fx_addsy
)
15391 + fixP
->fx_offset
));
15392 else if (HAVE_IN_PLACE_ADDENDS
15393 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15395 _("cannot encode misaligned addend "
15396 "in the relocatable field (0x%lx)"),
15397 (long) fixP
->fx_offset
);
15399 /* Fall through. */
15401 case BFD_RELOC_MIPS_SHIFT5
:
15402 case BFD_RELOC_MIPS_SHIFT6
:
15403 case BFD_RELOC_MIPS_GOT_DISP
:
15404 case BFD_RELOC_MIPS_GOT_PAGE
:
15405 case BFD_RELOC_MIPS_GOT_OFST
:
15406 case BFD_RELOC_MIPS_SUB
:
15407 case BFD_RELOC_MIPS_INSERT_A
:
15408 case BFD_RELOC_MIPS_INSERT_B
:
15409 case BFD_RELOC_MIPS_DELETE
:
15410 case BFD_RELOC_MIPS_HIGHEST
:
15411 case BFD_RELOC_MIPS_HIGHER
:
15412 case BFD_RELOC_MIPS_SCN_DISP
:
15413 case BFD_RELOC_MIPS_REL16
:
15414 case BFD_RELOC_MIPS_RELGOT
:
15415 case BFD_RELOC_MIPS_JALR
:
15416 case BFD_RELOC_HI16
:
15417 case BFD_RELOC_HI16_S
:
15418 case BFD_RELOC_LO16
:
15419 case BFD_RELOC_GPREL16
:
15420 case BFD_RELOC_MIPS_LITERAL
:
15421 case BFD_RELOC_MIPS_CALL16
:
15422 case BFD_RELOC_MIPS_GOT16
:
15423 case BFD_RELOC_GPREL32
:
15424 case BFD_RELOC_MIPS_GOT_HI16
:
15425 case BFD_RELOC_MIPS_GOT_LO16
:
15426 case BFD_RELOC_MIPS_CALL_HI16
:
15427 case BFD_RELOC_MIPS_CALL_LO16
:
15428 case BFD_RELOC_HI16_S_PCREL
:
15429 case BFD_RELOC_LO16_PCREL
:
15430 case BFD_RELOC_MIPS16_GPREL
:
15431 case BFD_RELOC_MIPS16_GOT16
:
15432 case BFD_RELOC_MIPS16_CALL16
:
15433 case BFD_RELOC_MIPS16_HI16
:
15434 case BFD_RELOC_MIPS16_HI16_S
:
15435 case BFD_RELOC_MIPS16_LO16
:
15436 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15437 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15438 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15439 case BFD_RELOC_MICROMIPS_SUB
:
15440 case BFD_RELOC_MICROMIPS_HIGHEST
:
15441 case BFD_RELOC_MICROMIPS_HIGHER
:
15442 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15443 case BFD_RELOC_MICROMIPS_JALR
:
15444 case BFD_RELOC_MICROMIPS_HI16
:
15445 case BFD_RELOC_MICROMIPS_HI16_S
:
15446 case BFD_RELOC_MICROMIPS_LO16
:
15447 case BFD_RELOC_MICROMIPS_GPREL16
:
15448 case BFD_RELOC_MICROMIPS_LITERAL
:
15449 case BFD_RELOC_MICROMIPS_CALL16
:
15450 case BFD_RELOC_MICROMIPS_GOT16
:
15451 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15452 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15453 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15454 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15455 case BFD_RELOC_MIPS_EH
:
15460 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15462 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15463 if (mips16_reloc_p (fixP
->fx_r_type
))
15464 insn
|= mips16_immed_extend (value
, 16);
15466 insn
|= (value
& 0xffff);
15467 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15470 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15471 _("unsupported constant in relocation"));
15476 /* This is handled like BFD_RELOC_32, but we output a sign
15477 extended value if we are only 32 bits. */
15480 if (8 <= sizeof (valueT
))
15481 md_number_to_chars (buf
, *valP
, 8);
15486 if ((*valP
& 0x80000000) != 0)
15490 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15491 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15496 case BFD_RELOC_RVA
:
15498 case BFD_RELOC_32_PCREL
:
15501 /* If we are deleting this reloc entry, we must fill in the
15502 value now. This can happen if we have a .word which is not
15503 resolved when it appears but is later defined. */
15505 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15508 case BFD_RELOC_MIPS_21_PCREL_S2
:
15509 fix_validate_branch (fixP
, *valP
);
15510 if (!fixP
->fx_done
)
15513 if (*valP
+ 0x400000 <= 0x7fffff)
15515 insn
= read_insn (buf
);
15516 insn
|= (*valP
>> 2) & 0x1fffff;
15517 write_insn (buf
, insn
);
15520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15521 _("branch out of range"));
15524 case BFD_RELOC_MIPS_26_PCREL_S2
:
15525 fix_validate_branch (fixP
, *valP
);
15526 if (!fixP
->fx_done
)
15529 if (*valP
+ 0x8000000 <= 0xfffffff)
15531 insn
= read_insn (buf
);
15532 insn
|= (*valP
>> 2) & 0x3ffffff;
15533 write_insn (buf
, insn
);
15536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15537 _("branch out of range"));
15540 case BFD_RELOC_MIPS_18_PCREL_S3
:
15541 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
15542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15543 _("PC-relative access using misaligned symbol (%lx)"),
15544 (long) S_GET_VALUE (fixP
->fx_addsy
));
15545 if ((fixP
->fx_offset
& 0x7) != 0)
15546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15547 _("PC-relative access using misaligned offset (%lx)"),
15548 (long) fixP
->fx_offset
);
15549 if (!fixP
->fx_done
)
15552 if (*valP
+ 0x100000 <= 0x1fffff)
15554 insn
= read_insn (buf
);
15555 insn
|= (*valP
>> 3) & 0x3ffff;
15556 write_insn (buf
, insn
);
15559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15560 _("PC-relative access out of range"));
15563 case BFD_RELOC_MIPS_19_PCREL_S2
:
15564 if ((*valP
& 0x3) != 0)
15565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15566 _("PC-relative access to misaligned address (%lx)"),
15568 if (!fixP
->fx_done
)
15571 if (*valP
+ 0x100000 <= 0x1fffff)
15573 insn
= read_insn (buf
);
15574 insn
|= (*valP
>> 2) & 0x7ffff;
15575 write_insn (buf
, insn
);
15578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15579 _("PC-relative access out of range"));
15582 case BFD_RELOC_16_PCREL_S2
:
15583 fix_validate_branch (fixP
, *valP
);
15585 /* We need to save the bits in the instruction since fixup_segment()
15586 might be deleting the relocation entry (i.e., a branch within
15587 the current segment). */
15588 if (! fixP
->fx_done
)
15591 /* Update old instruction data. */
15592 insn
= read_insn (buf
);
15594 if (*valP
+ 0x20000 <= 0x3ffff)
15596 insn
|= (*valP
>> 2) & 0xffff;
15597 write_insn (buf
, insn
);
15599 else if (fixP
->fx_tcbit2
15601 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15602 && (fixP
->fx_frag
->fr_address
15603 < text_section
->vma
+ bfd_get_section_size (text_section
))
15604 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15605 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15606 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15608 /* The branch offset is too large. If this is an
15609 unconditional branch, and we are not generating PIC code,
15610 we can convert it to an absolute jump instruction. */
15611 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
15612 insn
= 0x0c000000; /* jal */
15614 insn
= 0x08000000; /* j */
15615 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
15617 fixP
->fx_addsy
= section_symbol (text_section
);
15618 *valP
+= md_pcrel_from (fixP
);
15619 write_insn (buf
, insn
);
15623 /* If we got here, we have branch-relaxation disabled,
15624 and there's nothing we can do to fix this instruction
15625 without turning it into a longer sequence. */
15626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15627 _("branch out of range"));
15631 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15632 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15633 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15634 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15635 gas_assert (!fixP
->fx_done
);
15636 if (fix_bad_cross_mode_branch_p (fixP
))
15637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15638 _("branch to a symbol in another ISA mode"));
15639 else if (fixP
->fx_addsy
15640 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
15641 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
15642 && (fixP
->fx_offset
& 0x1) != 0)
15643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15644 _("branch to misaligned address (0x%lx)"),
15645 (long) (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
));
15646 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
15647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15648 _("cannot encode misaligned addend "
15649 "in the relocatable field (0x%lx)"),
15650 (long) fixP
->fx_offset
);
15653 case BFD_RELOC_VTABLE_INHERIT
:
15656 && !S_IS_DEFINED (fixP
->fx_addsy
)
15657 && !S_IS_WEAK (fixP
->fx_addsy
))
15658 S_SET_WEAK (fixP
->fx_addsy
);
15661 case BFD_RELOC_NONE
:
15662 case BFD_RELOC_VTABLE_ENTRY
:
15670 /* Remember value for tc_gen_reloc. */
15671 fixP
->fx_addnumber
= *valP
;
15681 c
= get_symbol_name (&name
);
15682 p
= (symbolS
*) symbol_find_or_make (name
);
15683 (void) restore_line_pointer (c
);
15687 /* Align the current frag to a given power of two. If a particular
15688 fill byte should be used, FILL points to an integer that contains
15689 that byte, otherwise FILL is null.
15691 This function used to have the comment:
15693 The MIPS assembler also automatically adjusts any preceding label.
15695 The implementation therefore applied the adjustment to a maximum of
15696 one label. However, other label adjustments are applied to batches
15697 of labels, and adjusting just one caused problems when new labels
15698 were added for the sake of debugging or unwind information.
15699 We therefore adjust all preceding labels (given as LABELS) instead. */
15702 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
15704 mips_emit_delays ();
15705 mips_record_compressed_mode ();
15706 if (fill
== NULL
&& subseg_text_p (now_seg
))
15707 frag_align_code (to
, 0);
15709 frag_align (to
, fill
? *fill
: 0, 0);
15710 record_alignment (now_seg
, to
);
15711 mips_move_labels (labels
, FALSE
);
15714 /* Align to a given power of two. .align 0 turns off the automatic
15715 alignment used by the data creating pseudo-ops. */
15718 s_align (int x ATTRIBUTE_UNUSED
)
15720 int temp
, fill_value
, *fill_ptr
;
15721 long max_alignment
= 28;
15723 /* o Note that the assembler pulls down any immediately preceding label
15724 to the aligned address.
15725 o It's not documented but auto alignment is reinstated by
15726 a .align pseudo instruction.
15727 o Note also that after auto alignment is turned off the mips assembler
15728 issues an error on attempt to assemble an improperly aligned data item.
15731 temp
= get_absolute_expression ();
15732 if (temp
> max_alignment
)
15733 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
15736 as_warn (_("alignment negative, 0 assumed"));
15739 if (*input_line_pointer
== ',')
15741 ++input_line_pointer
;
15742 fill_value
= get_absolute_expression ();
15743 fill_ptr
= &fill_value
;
15749 segment_info_type
*si
= seg_info (now_seg
);
15750 struct insn_label_list
*l
= si
->label_list
;
15751 /* Auto alignment should be switched on by next section change. */
15753 mips_align (temp
, fill_ptr
, l
);
15760 demand_empty_rest_of_line ();
15764 s_change_sec (int sec
)
15768 /* The ELF backend needs to know that we are changing sections, so
15769 that .previous works correctly. We could do something like check
15770 for an obj_section_change_hook macro, but that might be confusing
15771 as it would not be appropriate to use it in the section changing
15772 functions in read.c, since obj-elf.c intercepts those. FIXME:
15773 This should be cleaner, somehow. */
15774 obj_elf_section_change_hook ();
15776 mips_emit_delays ();
15787 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
15788 demand_empty_rest_of_line ();
15792 seg
= subseg_new (RDATA_SECTION_NAME
,
15793 (subsegT
) get_absolute_expression ());
15794 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
15795 | SEC_READONLY
| SEC_RELOC
15797 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15798 record_alignment (seg
, 4);
15799 demand_empty_rest_of_line ();
15803 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
15804 bfd_set_section_flags (stdoutput
, seg
,
15805 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
15806 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15807 record_alignment (seg
, 4);
15808 demand_empty_rest_of_line ();
15812 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
15813 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
15814 if (strncmp (TARGET_OS
, "elf", 3) != 0)
15815 record_alignment (seg
, 4);
15816 demand_empty_rest_of_line ();
15824 s_change_section (int ignore ATTRIBUTE_UNUSED
)
15827 char *section_name
;
15832 int section_entry_size
;
15833 int section_alignment
;
15835 saved_ilp
= input_line_pointer
;
15836 endc
= get_symbol_name (§ion_name
);
15837 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
15839 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
15841 /* Do we have .section Name<,"flags">? */
15842 if (c
!= ',' || (c
== ',' && next_c
== '"'))
15844 /* Just after name is now '\0'. */
15845 (void) restore_line_pointer (endc
);
15846 input_line_pointer
= saved_ilp
;
15847 obj_elf_section (ignore
);
15851 section_name
= xstrdup (section_name
);
15852 c
= restore_line_pointer (endc
);
15854 input_line_pointer
++;
15856 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15858 section_type
= get_absolute_expression ();
15862 if (*input_line_pointer
++ == ',')
15863 section_flag
= get_absolute_expression ();
15867 if (*input_line_pointer
++ == ',')
15868 section_entry_size
= get_absolute_expression ();
15870 section_entry_size
= 0;
15872 if (*input_line_pointer
++ == ',')
15873 section_alignment
= get_absolute_expression ();
15875 section_alignment
= 0;
15877 /* FIXME: really ignore? */
15878 (void) section_alignment
;
15880 /* When using the generic form of .section (as implemented by obj-elf.c),
15881 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15882 traditionally had to fall back on the more common @progbits instead.
15884 There's nothing really harmful in this, since bfd will correct
15885 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15886 means that, for backwards compatibility, the special_section entries
15887 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15889 Even so, we shouldn't force users of the MIPS .section syntax to
15890 incorrectly label the sections as SHT_PROGBITS. The best compromise
15891 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15892 generic type-checking code. */
15893 if (section_type
== SHT_MIPS_DWARF
)
15894 section_type
= SHT_PROGBITS
;
15896 obj_elf_change_section (section_name
, section_type
, 0, section_flag
,
15897 section_entry_size
, 0, 0, 0);
15899 if (now_seg
->name
!= section_name
)
15900 free (section_name
);
15904 mips_enable_auto_align (void)
15910 s_cons (int log_size
)
15912 segment_info_type
*si
= seg_info (now_seg
);
15913 struct insn_label_list
*l
= si
->label_list
;
15915 mips_emit_delays ();
15916 if (log_size
> 0 && auto_align
)
15917 mips_align (log_size
, 0, l
);
15918 cons (1 << log_size
);
15919 mips_clear_insn_labels ();
15923 s_float_cons (int type
)
15925 segment_info_type
*si
= seg_info (now_seg
);
15926 struct insn_label_list
*l
= si
->label_list
;
15928 mips_emit_delays ();
15933 mips_align (3, 0, l
);
15935 mips_align (2, 0, l
);
15939 mips_clear_insn_labels ();
15942 /* Handle .globl. We need to override it because on Irix 5 you are
15945 where foo is an undefined symbol, to mean that foo should be
15946 considered to be the address of a function. */
15949 s_mips_globl (int x ATTRIBUTE_UNUSED
)
15958 c
= get_symbol_name (&name
);
15959 symbolP
= symbol_find_or_make (name
);
15960 S_SET_EXTERNAL (symbolP
);
15962 *input_line_pointer
= c
;
15963 SKIP_WHITESPACE_AFTER_NAME ();
15965 /* On Irix 5, every global symbol that is not explicitly labelled as
15966 being a function is apparently labelled as being an object. */
15969 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
15970 && (*input_line_pointer
!= ','))
15975 c
= get_symbol_name (&secname
);
15976 sec
= bfd_get_section_by_name (stdoutput
, secname
);
15978 as_bad (_("%s: no such section"), secname
);
15979 (void) restore_line_pointer (c
);
15981 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
15982 flag
= BSF_FUNCTION
;
15985 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
15987 c
= *input_line_pointer
;
15990 input_line_pointer
++;
15991 SKIP_WHITESPACE ();
15992 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
15998 demand_empty_rest_of_line ();
16002 s_option (int x ATTRIBUTE_UNUSED
)
16007 c
= get_symbol_name (&opt
);
16011 /* FIXME: What does this mean? */
16013 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16017 i
= atoi (opt
+ 3);
16018 if (i
!= 0 && i
!= 2)
16019 as_bad (_(".option pic%d not supported"), i
);
16020 else if (mips_pic
== VXWORKS_PIC
)
16021 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16026 mips_pic
= SVR4_PIC
;
16027 mips_abicalls
= TRUE
;
16030 if (mips_pic
== SVR4_PIC
)
16032 if (g_switch_seen
&& g_switch_value
!= 0)
16033 as_warn (_("-G may not be used with SVR4 PIC code"));
16034 g_switch_value
= 0;
16035 bfd_set_gp_size (stdoutput
, 0);
16039 as_warn (_("unrecognized option \"%s\""), opt
);
16041 (void) restore_line_pointer (c
);
16042 demand_empty_rest_of_line ();
16045 /* This structure is used to hold a stack of .set values. */
16047 struct mips_option_stack
16049 struct mips_option_stack
*next
;
16050 struct mips_set_options options
;
16053 static struct mips_option_stack
*mips_opts_stack
;
16055 /* Return status for .set/.module option handling. */
16057 enum code_option_type
16059 /* Unrecognized option. */
16060 OPTION_TYPE_BAD
= -1,
16062 /* Ordinary option. */
16063 OPTION_TYPE_NORMAL
,
16065 /* ISA changing option. */
16069 /* Handle common .set/.module options. Return status indicating option
16072 static enum code_option_type
16073 parse_code_option (char * name
)
16075 bfd_boolean isa_set
= FALSE
;
16076 const struct mips_ase
*ase
;
16078 if (strncmp (name
, "at=", 3) == 0)
16080 char *s
= name
+ 3;
16082 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16083 as_bad (_("unrecognized register name `%s'"), s
);
16085 else if (strcmp (name
, "at") == 0)
16086 mips_opts
.at
= ATREG
;
16087 else if (strcmp (name
, "noat") == 0)
16088 mips_opts
.at
= ZERO
;
16089 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16090 mips_opts
.nomove
= 0;
16091 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16092 mips_opts
.nomove
= 1;
16093 else if (strcmp (name
, "bopt") == 0)
16094 mips_opts
.nobopt
= 0;
16095 else if (strcmp (name
, "nobopt") == 0)
16096 mips_opts
.nobopt
= 1;
16097 else if (strcmp (name
, "gp=32") == 0)
16099 else if (strcmp (name
, "gp=64") == 0)
16101 else if (strcmp (name
, "fp=32") == 0)
16103 else if (strcmp (name
, "fp=xx") == 0)
16105 else if (strcmp (name
, "fp=64") == 0)
16107 else if (strcmp (name
, "softfloat") == 0)
16108 mips_opts
.soft_float
= 1;
16109 else if (strcmp (name
, "hardfloat") == 0)
16110 mips_opts
.soft_float
= 0;
16111 else if (strcmp (name
, "singlefloat") == 0)
16112 mips_opts
.single_float
= 1;
16113 else if (strcmp (name
, "doublefloat") == 0)
16114 mips_opts
.single_float
= 0;
16115 else if (strcmp (name
, "nooddspreg") == 0)
16116 mips_opts
.oddspreg
= 0;
16117 else if (strcmp (name
, "oddspreg") == 0)
16118 mips_opts
.oddspreg
= 1;
16119 else if (strcmp (name
, "mips16") == 0
16120 || strcmp (name
, "MIPS-16") == 0)
16121 mips_opts
.mips16
= 1;
16122 else if (strcmp (name
, "nomips16") == 0
16123 || strcmp (name
, "noMIPS-16") == 0)
16124 mips_opts
.mips16
= 0;
16125 else if (strcmp (name
, "micromips") == 0)
16126 mips_opts
.micromips
= 1;
16127 else if (strcmp (name
, "nomicromips") == 0)
16128 mips_opts
.micromips
= 0;
16129 else if (name
[0] == 'n'
16131 && (ase
= mips_lookup_ase (name
+ 2)))
16132 mips_set_ase (ase
, &mips_opts
, FALSE
);
16133 else if ((ase
= mips_lookup_ase (name
)))
16134 mips_set_ase (ase
, &mips_opts
, TRUE
);
16135 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16137 /* Permit the user to change the ISA and architecture on the fly.
16138 Needless to say, misuse can cause serious problems. */
16139 if (strncmp (name
, "arch=", 5) == 0)
16141 const struct mips_cpu_info
*p
;
16143 p
= mips_parse_cpu ("internal use", name
+ 5);
16145 as_bad (_("unknown architecture %s"), name
+ 5);
16148 mips_opts
.arch
= p
->cpu
;
16149 mips_opts
.isa
= p
->isa
;
16153 else if (strncmp (name
, "mips", 4) == 0)
16155 const struct mips_cpu_info
*p
;
16157 p
= mips_parse_cpu ("internal use", name
);
16159 as_bad (_("unknown ISA level %s"), name
+ 4);
16162 mips_opts
.arch
= p
->cpu
;
16163 mips_opts
.isa
= p
->isa
;
16168 as_bad (_("unknown ISA or architecture %s"), name
);
16170 else if (strcmp (name
, "autoextend") == 0)
16171 mips_opts
.noautoextend
= 0;
16172 else if (strcmp (name
, "noautoextend") == 0)
16173 mips_opts
.noautoextend
= 1;
16174 else if (strcmp (name
, "insn32") == 0)
16175 mips_opts
.insn32
= TRUE
;
16176 else if (strcmp (name
, "noinsn32") == 0)
16177 mips_opts
.insn32
= FALSE
;
16178 else if (strcmp (name
, "sym32") == 0)
16179 mips_opts
.sym32
= TRUE
;
16180 else if (strcmp (name
, "nosym32") == 0)
16181 mips_opts
.sym32
= FALSE
;
16183 return OPTION_TYPE_BAD
;
16185 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16188 /* Handle the .set pseudo-op. */
16191 s_mipsset (int x ATTRIBUTE_UNUSED
)
16193 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16194 char *name
= input_line_pointer
, ch
;
16196 file_mips_check_options ();
16198 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16199 ++input_line_pointer
;
16200 ch
= *input_line_pointer
;
16201 *input_line_pointer
= '\0';
16203 if (strchr (name
, ','))
16205 /* Generic ".set" directive; use the generic handler. */
16206 *input_line_pointer
= ch
;
16207 input_line_pointer
= name
;
16212 if (strcmp (name
, "reorder") == 0)
16214 if (mips_opts
.noreorder
)
16217 else if (strcmp (name
, "noreorder") == 0)
16219 if (!mips_opts
.noreorder
)
16220 start_noreorder ();
16222 else if (strcmp (name
, "macro") == 0)
16223 mips_opts
.warn_about_macros
= 0;
16224 else if (strcmp (name
, "nomacro") == 0)
16226 if (mips_opts
.noreorder
== 0)
16227 as_bad (_("`noreorder' must be set before `nomacro'"));
16228 mips_opts
.warn_about_macros
= 1;
16230 else if (strcmp (name
, "gp=default") == 0)
16231 mips_opts
.gp
= file_mips_opts
.gp
;
16232 else if (strcmp (name
, "fp=default") == 0)
16233 mips_opts
.fp
= file_mips_opts
.fp
;
16234 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16236 mips_opts
.isa
= file_mips_opts
.isa
;
16237 mips_opts
.arch
= file_mips_opts
.arch
;
16238 mips_opts
.gp
= file_mips_opts
.gp
;
16239 mips_opts
.fp
= file_mips_opts
.fp
;
16241 else if (strcmp (name
, "push") == 0)
16243 struct mips_option_stack
*s
;
16245 s
= XNEW (struct mips_option_stack
);
16246 s
->next
= mips_opts_stack
;
16247 s
->options
= mips_opts
;
16248 mips_opts_stack
= s
;
16250 else if (strcmp (name
, "pop") == 0)
16252 struct mips_option_stack
*s
;
16254 s
= mips_opts_stack
;
16256 as_bad (_(".set pop with no .set push"));
16259 /* If we're changing the reorder mode we need to handle
16260 delay slots correctly. */
16261 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16262 start_noreorder ();
16263 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16266 mips_opts
= s
->options
;
16267 mips_opts_stack
= s
->next
;
16273 type
= parse_code_option (name
);
16274 if (type
== OPTION_TYPE_BAD
)
16275 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16278 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16279 registers based on what is supported by the arch/cpu. */
16280 if (type
== OPTION_TYPE_ISA
)
16282 switch (mips_opts
.isa
)
16287 /* MIPS I cannot support FPXX. */
16289 /* fall-through. */
16296 if (mips_opts
.fp
!= 0)
16312 if (mips_opts
.fp
!= 0)
16314 if (mips_opts
.arch
== CPU_R5900
)
16321 as_bad (_("unknown ISA level %s"), name
+ 4);
16326 mips_check_options (&mips_opts
, FALSE
);
16328 mips_check_isa_supports_ases ();
16329 *input_line_pointer
= ch
;
16330 demand_empty_rest_of_line ();
16333 /* Handle the .module pseudo-op. */
16336 s_module (int ignore ATTRIBUTE_UNUSED
)
16338 char *name
= input_line_pointer
, ch
;
16340 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16341 ++input_line_pointer
;
16342 ch
= *input_line_pointer
;
16343 *input_line_pointer
= '\0';
16345 if (!file_mips_opts_checked
)
16347 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16348 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16350 /* Update module level settings from mips_opts. */
16351 file_mips_opts
= mips_opts
;
16354 as_bad (_(".module is not permitted after generating code"));
16356 *input_line_pointer
= ch
;
16357 demand_empty_rest_of_line ();
16360 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16361 .option pic2. It means to generate SVR4 PIC calls. */
16364 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16366 mips_pic
= SVR4_PIC
;
16367 mips_abicalls
= TRUE
;
16369 if (g_switch_seen
&& g_switch_value
!= 0)
16370 as_warn (_("-G may not be used with SVR4 PIC code"));
16371 g_switch_value
= 0;
16373 bfd_set_gp_size (stdoutput
, 0);
16374 demand_empty_rest_of_line ();
16377 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16378 PIC code. It sets the $gp register for the function based on the
16379 function address, which is in the register named in the argument.
16380 This uses a relocation against _gp_disp, which is handled specially
16381 by the linker. The result is:
16382 lui $gp,%hi(_gp_disp)
16383 addiu $gp,$gp,%lo(_gp_disp)
16384 addu $gp,$gp,.cpload argument
16385 The .cpload argument is normally $25 == $t9.
16387 The -mno-shared option changes this to:
16388 lui $gp,%hi(__gnu_local_gp)
16389 addiu $gp,$gp,%lo(__gnu_local_gp)
16390 and the argument is ignored. This saves an instruction, but the
16391 resulting code is not position independent; it uses an absolute
16392 address for __gnu_local_gp. Thus code assembled with -mno-shared
16393 can go into an ordinary executable, but not into a shared library. */
16396 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16402 file_mips_check_options ();
16404 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16405 .cpload is ignored. */
16406 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16412 if (mips_opts
.mips16
)
16414 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16415 ignore_rest_of_line ();
16419 /* .cpload should be in a .set noreorder section. */
16420 if (mips_opts
.noreorder
== 0)
16421 as_warn (_(".cpload not in noreorder section"));
16423 reg
= tc_get_register (0);
16425 /* If we need to produce a 64-bit address, we are better off using
16426 the default instruction sequence. */
16427 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16429 ex
.X_op
= O_symbol
;
16430 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16432 ex
.X_op_symbol
= NULL
;
16433 ex
.X_add_number
= 0;
16435 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16436 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16438 mips_mark_labels ();
16439 mips_assembling_insn
= TRUE
;
16442 macro_build_lui (&ex
, mips_gp_register
);
16443 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16444 mips_gp_register
, BFD_RELOC_LO16
);
16446 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16447 mips_gp_register
, reg
);
16450 mips_assembling_insn
= FALSE
;
16451 demand_empty_rest_of_line ();
16454 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16455 .cpsetup $reg1, offset|$reg2, label
16457 If offset is given, this results in:
16458 sd $gp, offset($sp)
16459 lui $gp, %hi(%neg(%gp_rel(label)))
16460 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16461 daddu $gp, $gp, $reg1
16463 If $reg2 is given, this results in:
16465 lui $gp, %hi(%neg(%gp_rel(label)))
16466 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16467 daddu $gp, $gp, $reg1
16468 $reg1 is normally $25 == $t9.
16470 The -mno-shared option replaces the last three instructions with
16472 addiu $gp,$gp,%lo(_gp) */
16475 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16477 expressionS ex_off
;
16478 expressionS ex_sym
;
16481 file_mips_check_options ();
16483 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16484 We also need NewABI support. */
16485 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16491 if (mips_opts
.mips16
)
16493 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16494 ignore_rest_of_line ();
16498 reg1
= tc_get_register (0);
16499 SKIP_WHITESPACE ();
16500 if (*input_line_pointer
!= ',')
16502 as_bad (_("missing argument separator ',' for .cpsetup"));
16506 ++input_line_pointer
;
16507 SKIP_WHITESPACE ();
16508 if (*input_line_pointer
== '$')
16510 mips_cpreturn_register
= tc_get_register (0);
16511 mips_cpreturn_offset
= -1;
16515 mips_cpreturn_offset
= get_absolute_expression ();
16516 mips_cpreturn_register
= -1;
16518 SKIP_WHITESPACE ();
16519 if (*input_line_pointer
!= ',')
16521 as_bad (_("missing argument separator ',' for .cpsetup"));
16525 ++input_line_pointer
;
16526 SKIP_WHITESPACE ();
16527 expression (&ex_sym
);
16529 mips_mark_labels ();
16530 mips_assembling_insn
= TRUE
;
16533 if (mips_cpreturn_register
== -1)
16535 ex_off
.X_op
= O_constant
;
16536 ex_off
.X_add_symbol
= NULL
;
16537 ex_off
.X_op_symbol
= NULL
;
16538 ex_off
.X_add_number
= mips_cpreturn_offset
;
16540 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16541 BFD_RELOC_LO16
, SP
);
16544 move_register (mips_cpreturn_register
, mips_gp_register
);
16546 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16548 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16549 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16552 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16553 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16554 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16556 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16557 mips_gp_register
, reg1
);
16563 ex
.X_op
= O_symbol
;
16564 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16565 ex
.X_op_symbol
= NULL
;
16566 ex
.X_add_number
= 0;
16568 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16569 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16571 macro_build_lui (&ex
, mips_gp_register
);
16572 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16573 mips_gp_register
, BFD_RELOC_LO16
);
16578 mips_assembling_insn
= FALSE
;
16579 demand_empty_rest_of_line ();
16583 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16585 file_mips_check_options ();
16587 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16588 .cplocal is ignored. */
16589 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16595 if (mips_opts
.mips16
)
16597 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16598 ignore_rest_of_line ();
16602 mips_gp_register
= tc_get_register (0);
16603 demand_empty_rest_of_line ();
16606 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16607 offset from $sp. The offset is remembered, and after making a PIC
16608 call $gp is restored from that location. */
16611 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16615 file_mips_check_options ();
16617 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16618 .cprestore is ignored. */
16619 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16625 if (mips_opts
.mips16
)
16627 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16628 ignore_rest_of_line ();
16632 mips_cprestore_offset
= get_absolute_expression ();
16633 mips_cprestore_valid
= 1;
16635 ex
.X_op
= O_constant
;
16636 ex
.X_add_symbol
= NULL
;
16637 ex
.X_op_symbol
= NULL
;
16638 ex
.X_add_number
= mips_cprestore_offset
;
16640 mips_mark_labels ();
16641 mips_assembling_insn
= TRUE
;
16644 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16645 SP
, HAVE_64BIT_ADDRESSES
);
16648 mips_assembling_insn
= FALSE
;
16649 demand_empty_rest_of_line ();
16652 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16653 was given in the preceding .cpsetup, it results in:
16654 ld $gp, offset($sp)
16656 If a register $reg2 was given there, it results in:
16657 or $gp, $reg2, $0 */
16660 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16664 file_mips_check_options ();
16666 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16667 We also need NewABI support. */
16668 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16674 if (mips_opts
.mips16
)
16676 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16677 ignore_rest_of_line ();
16681 mips_mark_labels ();
16682 mips_assembling_insn
= TRUE
;
16685 if (mips_cpreturn_register
== -1)
16687 ex
.X_op
= O_constant
;
16688 ex
.X_add_symbol
= NULL
;
16689 ex
.X_op_symbol
= NULL
;
16690 ex
.X_add_number
= mips_cpreturn_offset
;
16692 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
16695 move_register (mips_gp_register
, mips_cpreturn_register
);
16699 mips_assembling_insn
= FALSE
;
16700 demand_empty_rest_of_line ();
16703 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16704 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16705 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16706 debug information or MIPS16 TLS. */
16709 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
16710 bfd_reloc_code_real_type rtype
)
16717 if (ex
.X_op
!= O_symbol
)
16719 as_bad (_("unsupported use of %s"), dirstr
);
16720 ignore_rest_of_line ();
16723 p
= frag_more (bytes
);
16724 md_number_to_chars (p
, 0, bytes
);
16725 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
16726 demand_empty_rest_of_line ();
16727 mips_clear_insn_labels ();
16730 /* Handle .dtprelword. */
16733 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
16735 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
16738 /* Handle .dtpreldword. */
16741 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
16743 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
16746 /* Handle .tprelword. */
16749 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
16751 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
16754 /* Handle .tpreldword. */
16757 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
16759 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
16762 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16763 code. It sets the offset to use in gp_rel relocations. */
16766 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
16768 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16769 We also need NewABI support. */
16770 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16776 mips_gprel_offset
= get_absolute_expression ();
16778 demand_empty_rest_of_line ();
16781 /* Handle the .gpword pseudo-op. This is used when generating PIC
16782 code. It generates a 32 bit GP relative reloc. */
16785 s_gpword (int ignore ATTRIBUTE_UNUSED
)
16787 segment_info_type
*si
;
16788 struct insn_label_list
*l
;
16792 /* When not generating PIC code, this is treated as .word. */
16793 if (mips_pic
!= SVR4_PIC
)
16799 si
= seg_info (now_seg
);
16800 l
= si
->label_list
;
16801 mips_emit_delays ();
16803 mips_align (2, 0, l
);
16806 mips_clear_insn_labels ();
16808 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16810 as_bad (_("unsupported use of .gpword"));
16811 ignore_rest_of_line ();
16815 md_number_to_chars (p
, 0, 4);
16816 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16817 BFD_RELOC_GPREL32
);
16819 demand_empty_rest_of_line ();
16823 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
16825 segment_info_type
*si
;
16826 struct insn_label_list
*l
;
16830 /* When not generating PIC code, this is treated as .dword. */
16831 if (mips_pic
!= SVR4_PIC
)
16837 si
= seg_info (now_seg
);
16838 l
= si
->label_list
;
16839 mips_emit_delays ();
16841 mips_align (3, 0, l
);
16844 mips_clear_insn_labels ();
16846 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16848 as_bad (_("unsupported use of .gpdword"));
16849 ignore_rest_of_line ();
16853 md_number_to_chars (p
, 0, 8);
16854 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16855 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
16857 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16858 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
16859 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
16861 demand_empty_rest_of_line ();
16864 /* Handle the .ehword pseudo-op. This is used when generating unwinding
16865 tables. It generates a R_MIPS_EH reloc. */
16868 s_ehword (int ignore ATTRIBUTE_UNUSED
)
16873 mips_emit_delays ();
16876 mips_clear_insn_labels ();
16878 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
16880 as_bad (_("unsupported use of .ehword"));
16881 ignore_rest_of_line ();
16885 md_number_to_chars (p
, 0, 4);
16886 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
16887 BFD_RELOC_32_PCREL
);
16889 demand_empty_rest_of_line ();
16892 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16893 tables in SVR4 PIC code. */
16896 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
16900 file_mips_check_options ();
16902 /* This is ignored when not generating SVR4 PIC code. */
16903 if (mips_pic
!= SVR4_PIC
)
16909 mips_mark_labels ();
16910 mips_assembling_insn
= TRUE
;
16912 /* Add $gp to the register named as an argument. */
16914 reg
= tc_get_register (0);
16915 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
16918 mips_assembling_insn
= FALSE
;
16919 demand_empty_rest_of_line ();
16922 /* Handle the .insn pseudo-op. This marks instruction labels in
16923 mips16/micromips mode. This permits the linker to handle them specially,
16924 such as generating jalx instructions when needed. We also make
16925 them odd for the duration of the assembly, in order to generate the
16926 right sort of code. We will make them even in the adjust_symtab
16927 routine, while leaving them marked. This is convenient for the
16928 debugger and the disassembler. The linker knows to make them odd
16932 s_insn (int ignore ATTRIBUTE_UNUSED
)
16934 file_mips_check_options ();
16935 file_ase_mips16
|= mips_opts
.mips16
;
16936 file_ase_micromips
|= mips_opts
.micromips
;
16938 mips_mark_labels ();
16940 demand_empty_rest_of_line ();
16943 /* Handle the .nan pseudo-op. */
16946 s_nan (int ignore ATTRIBUTE_UNUSED
)
16948 static const char str_legacy
[] = "legacy";
16949 static const char str_2008
[] = "2008";
16952 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
16954 if (i
== sizeof (str_2008
) - 1
16955 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
16957 else if (i
== sizeof (str_legacy
) - 1
16958 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
16960 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
16963 as_bad (_("`%s' does not support legacy NaN"),
16964 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
16967 as_bad (_("bad .nan directive"));
16969 input_line_pointer
+= i
;
16970 demand_empty_rest_of_line ();
16973 /* Handle a .stab[snd] directive. Ideally these directives would be
16974 implemented in a transparent way, so that removing them would not
16975 have any effect on the generated instructions. However, s_stab
16976 internally changes the section, so in practice we need to decide
16977 now whether the preceding label marks compressed code. We do not
16978 support changing the compression mode of a label after a .stab*
16979 directive, such as in:
16985 so the current mode wins. */
16988 s_mips_stab (int type
)
16990 mips_mark_labels ();
16994 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16997 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17004 c
= get_symbol_name (&name
);
17005 symbolP
= symbol_find_or_make (name
);
17006 S_SET_WEAK (symbolP
);
17007 *input_line_pointer
= c
;
17009 SKIP_WHITESPACE_AFTER_NAME ();
17011 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17013 if (S_IS_DEFINED (symbolP
))
17015 as_bad (_("ignoring attempt to redefine symbol %s"),
17016 S_GET_NAME (symbolP
));
17017 ignore_rest_of_line ();
17021 if (*input_line_pointer
== ',')
17023 ++input_line_pointer
;
17024 SKIP_WHITESPACE ();
17028 if (exp
.X_op
!= O_symbol
)
17030 as_bad (_("bad .weakext directive"));
17031 ignore_rest_of_line ();
17034 symbol_set_value_expression (symbolP
, &exp
);
17037 demand_empty_rest_of_line ();
17040 /* Parse a register string into a number. Called from the ECOFF code
17041 to parse .frame. The argument is non-zero if this is the frame
17042 register, so that we can record it in mips_frame_reg. */
17045 tc_get_register (int frame
)
17049 SKIP_WHITESPACE ();
17050 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17054 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17055 mips_frame_reg_valid
= 1;
17056 mips_cprestore_valid
= 0;
17062 md_section_align (asection
*seg
, valueT addr
)
17064 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17066 /* We don't need to align ELF sections to the full alignment.
17067 However, Irix 5 may prefer that we align them at least to a 16
17068 byte boundary. We don't bother to align the sections if we
17069 are targeted for an embedded system. */
17070 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17075 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17078 /* Utility routine, called from above as well. If called while the
17079 input file is still being read, it's only an approximation. (For
17080 example, a symbol may later become defined which appeared to be
17081 undefined earlier.) */
17084 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17089 if (g_switch_value
> 0)
17091 const char *symname
;
17094 /* Find out whether this symbol can be referenced off the $gp
17095 register. It can be if it is smaller than the -G size or if
17096 it is in the .sdata or .sbss section. Certain symbols can
17097 not be referenced off the $gp, although it appears as though
17099 symname
= S_GET_NAME (sym
);
17100 if (symname
!= (const char *) NULL
17101 && (strcmp (symname
, "eprol") == 0
17102 || strcmp (symname
, "etext") == 0
17103 || strcmp (symname
, "_gp") == 0
17104 || strcmp (symname
, "edata") == 0
17105 || strcmp (symname
, "_fbss") == 0
17106 || strcmp (symname
, "_fdata") == 0
17107 || strcmp (symname
, "_ftext") == 0
17108 || strcmp (symname
, "end") == 0
17109 || strcmp (symname
, "_gp_disp") == 0))
17111 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17113 #ifndef NO_ECOFF_DEBUGGING
17114 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17115 && (symbol_get_obj (sym
)->ecoff_extern_size
17116 <= g_switch_value
))
17118 /* We must defer this decision until after the whole
17119 file has been read, since there might be a .extern
17120 after the first use of this symbol. */
17121 || (before_relaxing
17122 #ifndef NO_ECOFF_DEBUGGING
17123 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17125 && S_GET_VALUE (sym
) == 0)
17126 || (S_GET_VALUE (sym
) != 0
17127 && S_GET_VALUE (sym
) <= g_switch_value
)))
17131 const char *segname
;
17133 segname
= segment_name (S_GET_SEGMENT (sym
));
17134 gas_assert (strcmp (segname
, ".lit8") != 0
17135 && strcmp (segname
, ".lit4") != 0);
17136 change
= (strcmp (segname
, ".sdata") != 0
17137 && strcmp (segname
, ".sbss") != 0
17138 && strncmp (segname
, ".sdata.", 7) != 0
17139 && strncmp (segname
, ".sbss.", 6) != 0
17140 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17141 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17146 /* We are not optimizing for the $gp register. */
17151 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17154 pic_need_relax (symbolS
*sym
)
17158 /* Handle the case of a symbol equated to another symbol. */
17159 while (symbol_equated_reloc_p (sym
))
17163 /* It's possible to get a loop here in a badly written program. */
17164 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17170 if (symbol_section_p (sym
))
17173 symsec
= S_GET_SEGMENT (sym
);
17175 /* This must duplicate the test in adjust_reloc_syms. */
17176 return (!bfd_is_und_section (symsec
)
17177 && !bfd_is_abs_section (symsec
)
17178 && !bfd_is_com_section (symsec
)
17179 /* A global or weak symbol is treated as external. */
17180 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17183 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17184 convert a section-relative value VAL to the equivalent PC-relative
17188 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17189 offsetT val
, long stretch
)
17194 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17196 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17198 /* If the relax_marker of the symbol fragment differs from the
17199 relax_marker of this fragment, we have not yet adjusted the
17200 symbol fragment fr_address. We want to add in STRETCH in
17201 order to get a better estimate of the address. This
17202 particularly matters because of the shift bits. */
17203 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17207 /* Adjust stretch for any alignment frag. Note that if have
17208 been expanding the earlier code, the symbol may be
17209 defined in what appears to be an earlier frag. FIXME:
17210 This doesn't handle the fr_subtype field, which specifies
17211 a maximum number of bytes to skip when doing an
17213 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17215 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17218 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17220 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17229 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17231 /* The base address rules are complicated. The base address of
17232 a branch is the following instruction. The base address of a
17233 PC relative load or add is the instruction itself, but if it
17234 is in a delay slot (in which case it can not be extended) use
17235 the address of the instruction whose delay slot it is in. */
17236 if (pcrel_op
->include_isa_bit
)
17240 /* If we are currently assuming that this frag should be
17241 extended, then the current address is two bytes higher. */
17242 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17245 /* Ignore the low bit in the target, since it will be set
17246 for a text label. */
17249 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17251 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17254 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17259 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17260 extended opcode. SEC is the section the frag is in. */
17263 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17265 const struct mips_int_operand
*operand
;
17270 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17272 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17275 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17276 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17277 operand
= mips16_immed_operand (type
, FALSE
);
17278 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17279 || (operand
->root
.type
== OP_PCREL
17281 : !bfd_is_abs_section (symsec
)))
17284 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17286 if (operand
->root
.type
== OP_PCREL
)
17288 const struct mips_pcrel_operand
*pcrel_op
;
17291 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17294 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17295 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17297 /* If any of the shifted bits are set, we must use an extended
17298 opcode. If the address depends on the size of this
17299 instruction, this can lead to a loop, so we arrange to always
17300 use an extended opcode. */
17301 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17303 fragp
->fr_subtype
=
17304 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17308 /* If we are about to mark a frag as extended because the value
17309 is precisely the next value above maxtiny, then there is a
17310 chance of an infinite loop as in the following code:
17315 In this case when the la is extended, foo is 0x3fc bytes
17316 away, so the la can be shrunk, but then foo is 0x400 away, so
17317 the la must be extended. To avoid this loop, we mark the
17318 frag as extended if it was small, and is about to become
17319 extended with the next value above maxtiny. */
17320 maxtiny
= mips_int_operand_max (operand
);
17321 if (val
== maxtiny
+ (1 << operand
->shift
)
17322 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17324 fragp
->fr_subtype
=
17325 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17330 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17333 /* Compute the length of a branch sequence, and adjust the
17334 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17335 worst-case length is computed, with UPDATE being used to indicate
17336 whether an unconditional (-1), branch-likely (+1) or regular (0)
17337 branch is to be computed. */
17339 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17341 bfd_boolean toofar
;
17345 && S_IS_DEFINED (fragp
->fr_symbol
)
17346 && !S_IS_WEAK (fragp
->fr_symbol
)
17347 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17352 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17354 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17358 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17361 /* If the symbol is not defined or it's in a different segment,
17362 we emit the long sequence. */
17365 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17367 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17368 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17369 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17370 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17371 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17377 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17380 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17382 /* Additional space for PIC loading of target address. */
17384 if (mips_opts
.isa
== ISA_MIPS1
)
17385 /* Additional space for $at-stabilizing nop. */
17389 /* If branch is conditional. */
17390 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17397 /* Get a FRAG's branch instruction delay slot size, either from the
17398 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17399 or SHORT_INSN_SIZE otherwise. */
17402 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17404 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17407 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17409 return short_insn_size
;
17412 /* Compute the length of a branch sequence, and adjust the
17413 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17414 worst-case length is computed, with UPDATE being used to indicate
17415 whether an unconditional (-1), or regular (0) branch is to be
17419 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17421 bfd_boolean insn32
= TRUE
;
17422 bfd_boolean nods
= TRUE
;
17423 bfd_boolean pic
= TRUE
;
17424 bfd_boolean al
= TRUE
;
17425 int short_insn_size
;
17426 bfd_boolean toofar
;
17431 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
17432 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
17433 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
17434 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
17436 short_insn_size
= insn32
? 4 : 2;
17439 && S_IS_DEFINED (fragp
->fr_symbol
)
17440 && !S_IS_WEAK (fragp
->fr_symbol
)
17441 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17446 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17447 /* Ignore the low bit in the target, since it will be set
17448 for a text label. */
17449 if ((val
& 1) != 0)
17452 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17456 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17459 /* If the symbol is not defined or it's in a different segment,
17460 we emit the long sequence. */
17463 if (fragp
&& update
17464 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17465 fragp
->fr_subtype
= (toofar
17466 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17467 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17472 bfd_boolean compact_known
= fragp
!= NULL
;
17473 bfd_boolean compact
= FALSE
;
17474 bfd_boolean uncond
;
17478 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17479 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17482 uncond
= update
< 0;
17484 /* If label is out of range, we turn branch <br>:
17486 <br> label # 4 bytes
17493 # compact && (!PIC || insn32)
17496 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
17497 length
+= short_insn_size
;
17499 /* If assembling PIC code, we further turn:
17505 lw/ld at, %got(label)(gp) # 4 bytes
17506 d/addiu at, %lo(label) # 4 bytes
17507 jr/c at # 2/4 bytes
17510 length
+= 4 + short_insn_size
;
17512 /* Add an extra nop if the jump has no compact form and we need
17513 to fill the delay slot. */
17514 if ((!pic
|| al
) && nods
)
17516 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
17517 : short_insn_size
);
17519 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17521 <brneg> 0f # 4 bytes
17522 nop # 2/4 bytes if !compact
17525 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
17529 /* Add an extra nop to fill the delay slot. */
17530 gas_assert (fragp
);
17531 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
17537 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17538 bit accordingly. */
17541 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17543 bfd_boolean toofar
;
17546 && S_IS_DEFINED (fragp
->fr_symbol
)
17547 && !S_IS_WEAK (fragp
->fr_symbol
)
17548 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17554 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17555 /* Ignore the low bit in the target, since it will be set
17556 for a text label. */
17557 if ((val
& 1) != 0)
17560 /* Assume this is a 2-byte branch. */
17561 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17563 /* We try to avoid the infinite loop by not adding 2 more bytes for
17568 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17570 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17571 else if (type
== 'E')
17572 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17577 /* If the symbol is not defined or it's in a different segment,
17578 we emit a normal 32-bit branch. */
17581 if (fragp
&& update
17582 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17584 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17585 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17593 /* Estimate the size of a frag before relaxing. Unless this is the
17594 mips16, we are not really relaxing here, and the final size is
17595 encoded in the subtype information. For the mips16, we have to
17596 decide whether we are using an extended opcode or not. */
17599 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17603 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17606 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17608 return fragp
->fr_var
;
17611 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17612 /* We don't want to modify the EXTENDED bit here; it might get us
17613 into infinite loops. We change it only in mips_relax_frag(). */
17614 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17616 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17620 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17621 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17622 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17623 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17624 fragp
->fr_var
= length
;
17629 if (mips_pic
== VXWORKS_PIC
)
17630 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17632 else if (RELAX_PIC (fragp
->fr_subtype
))
17633 change
= pic_need_relax (fragp
->fr_symbol
);
17635 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17639 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17640 return -RELAX_FIRST (fragp
->fr_subtype
);
17643 return -RELAX_SECOND (fragp
->fr_subtype
);
17646 /* This is called to see whether a reloc against a defined symbol
17647 should be converted into a reloc against a section. */
17650 mips_fix_adjustable (fixS
*fixp
)
17652 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17653 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17656 if (fixp
->fx_addsy
== NULL
)
17659 /* Allow relocs used for EH tables. */
17660 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
17663 /* If symbol SYM is in a mergeable section, relocations of the form
17664 SYM + 0 can usually be made section-relative. The mergeable data
17665 is then identified by the section offset rather than by the symbol.
17667 However, if we're generating REL LO16 relocations, the offset is split
17668 between the LO16 and partnering high part relocation. The linker will
17669 need to recalculate the complete offset in order to correctly identify
17672 The linker has traditionally not looked for the partnering high part
17673 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17674 placed anywhere. Rather than break backwards compatibility by changing
17675 this, it seems better not to force the issue, and instead keep the
17676 original symbol. This will work with either linker behavior. */
17677 if ((lo16_reloc_p (fixp
->fx_r_type
)
17678 || reloc_needs_lo_p (fixp
->fx_r_type
))
17679 && HAVE_IN_PLACE_ADDENDS
17680 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17683 /* There is no place to store an in-place offset for JALR relocations. */
17684 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
17687 /* Likewise an in-range offset of limited PC-relative relocations may
17688 overflow the in-place relocatable field if recalculated against the
17689 start address of the symbol's containing section.
17691 Also, PC relative relocations for MIPS R6 need to be symbol rather than
17692 section relative to allow linker relaxations to be performed later on. */
17693 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17694 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
17697 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17698 to a floating-point stub. The same is true for non-R_MIPS16_26
17699 relocations against MIPS16 functions; in this case, the stub becomes
17700 the function's canonical address.
17702 Floating-point stubs are stored in unique .mips16.call.* or
17703 .mips16.fn.* sections. If a stub T for function F is in section S,
17704 the first relocation in section S must be against F; this is how the
17705 linker determines the target function. All relocations that might
17706 resolve to T must also be against F. We therefore have the following
17707 restrictions, which are given in an intentionally-redundant way:
17709 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17712 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17713 if that stub might be used.
17715 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17718 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17719 that stub might be used.
17721 There is a further restriction:
17723 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17724 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
17725 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
17726 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
17727 against MIPS16 or microMIPS symbols because we need to keep the
17728 MIPS16 or microMIPS symbol for the purpose of mode mismatch
17729 detection and JAL or BAL to JALX instruction conversion in the
17732 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17733 against a MIPS16 symbol. We deal with (5) by additionally leaving
17734 alone any jump and branch relocations against a microMIPS symbol.
17736 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17737 relocation against some symbol R, no relocation against R may be
17738 reduced. (Note that this deals with (2) as well as (1) because
17739 relocations against global symbols will never be reduced on ELF
17740 targets.) This approach is a little simpler than trying to detect
17741 stub sections, and gives the "all or nothing" per-symbol consistency
17742 that we have for MIPS16 symbols. */
17743 if (fixp
->fx_subsy
== NULL
17744 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
17745 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
17746 && (jmp_reloc_p (fixp
->fx_r_type
)
17747 || b_reloc_p (fixp
->fx_r_type
)))
17748 || *symbol_get_tc (fixp
->fx_addsy
)))
17754 /* Translate internal representation of relocation info to BFD target
17758 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
17760 static arelent
*retval
[4];
17762 bfd_reloc_code_real_type code
;
17764 memset (retval
, 0, sizeof(retval
));
17765 reloc
= retval
[0] = XCNEW (arelent
);
17766 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
17767 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
17768 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
17770 if (fixp
->fx_pcrel
)
17772 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
17773 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
17774 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
17775 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
17776 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
17777 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
17778 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
17779 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
17780 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
17781 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
17782 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
17783 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
17785 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17786 Relocations want only the symbol offset. */
17787 switch (fixp
->fx_r_type
)
17789 case BFD_RELOC_MIPS_18_PCREL_S3
:
17790 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
17793 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
17797 else if (HAVE_IN_PLACE_ADDENDS
17798 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
17799 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
17800 + fixp
->fx_where
, 4) >> 26) == 0x3c)
17802 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
17803 addend accordingly. */
17804 reloc
->addend
= fixp
->fx_addnumber
>> 1;
17807 reloc
->addend
= fixp
->fx_addnumber
;
17809 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17810 entry to be used in the relocation's section offset. */
17811 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17813 reloc
->address
= reloc
->addend
;
17817 code
= fixp
->fx_r_type
;
17819 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
17820 if (reloc
->howto
== NULL
)
17822 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
17823 _("cannot represent %s relocation in this object file"
17825 bfd_get_reloc_code_name (code
));
17832 /* Relax a machine dependent frag. This returns the amount by which
17833 the current size of the frag should change. */
17836 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17838 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17840 offsetT old_var
= fragp
->fr_var
;
17842 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
17844 return fragp
->fr_var
- old_var
;
17847 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17849 offsetT old_var
= fragp
->fr_var
;
17850 offsetT new_var
= 4;
17852 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17853 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
17854 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17855 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
17856 fragp
->fr_var
= new_var
;
17858 return new_var
- old_var
;
17861 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
17864 if (mips16_extended_frag (fragp
, sec
, stretch
))
17866 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17868 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
17873 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17875 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
17882 /* Convert a machine dependent frag. */
17885 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
17887 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17890 unsigned long insn
;
17894 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17895 insn
= read_insn (buf
);
17897 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17899 /* We generate a fixup instead of applying it right now
17900 because, if there are linker relaxations, we're going to
17901 need the relocations. */
17902 exp
.X_op
= O_symbol
;
17903 exp
.X_add_symbol
= fragp
->fr_symbol
;
17904 exp
.X_add_number
= fragp
->fr_offset
;
17906 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
17907 BFD_RELOC_16_PCREL_S2
);
17908 fixp
->fx_file
= fragp
->fr_file
;
17909 fixp
->fx_line
= fragp
->fr_line
;
17911 buf
= write_insn (buf
, insn
);
17917 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17918 _("relaxed out-of-range branch into a jump"));
17920 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
17923 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17925 /* Reverse the branch. */
17926 switch ((insn
>> 28) & 0xf)
17929 if ((insn
& 0xff000000) == 0x47000000
17930 || (insn
& 0xff600000) == 0x45600000)
17932 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
17933 reversed by tweaking bit 23. */
17934 insn
^= 0x00800000;
17938 /* bc[0-3][tf]l? instructions can have the condition
17939 reversed by tweaking a single TF bit, and their
17940 opcodes all have 0x4???????. */
17941 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
17942 insn
^= 0x00010000;
17947 /* bltz 0x04000000 bgez 0x04010000
17948 bltzal 0x04100000 bgezal 0x04110000 */
17949 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
17950 insn
^= 0x00010000;
17954 /* beq 0x10000000 bne 0x14000000
17955 blez 0x18000000 bgtz 0x1c000000 */
17956 insn
^= 0x04000000;
17964 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
17966 /* Clear the and-link bit. */
17967 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
17969 /* bltzal 0x04100000 bgezal 0x04110000
17970 bltzall 0x04120000 bgezall 0x04130000 */
17971 insn
&= ~0x00100000;
17974 /* Branch over the branch (if the branch was likely) or the
17975 full jump (not likely case). Compute the offset from the
17976 current instruction to branch to. */
17977 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17981 /* How many bytes in instructions we've already emitted? */
17982 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
17983 /* How many bytes in instructions from here to the end? */
17984 i
= fragp
->fr_var
- i
;
17986 /* Convert to instruction count. */
17988 /* Branch counts from the next instruction. */
17991 /* Branch over the jump. */
17992 buf
= write_insn (buf
, insn
);
17995 buf
= write_insn (buf
, 0);
17997 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
17999 /* beql $0, $0, 2f */
18001 /* Compute the PC offset from the current instruction to
18002 the end of the variable frag. */
18003 /* How many bytes in instructions we've already emitted? */
18004 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18005 /* How many bytes in instructions from here to the end? */
18006 i
= fragp
->fr_var
- i
;
18007 /* Convert to instruction count. */
18009 /* Don't decrement i, because we want to branch over the
18013 buf
= write_insn (buf
, insn
);
18014 buf
= write_insn (buf
, 0);
18018 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18021 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18022 ? 0x0c000000 : 0x08000000);
18023 exp
.X_op
= O_symbol
;
18024 exp
.X_add_symbol
= fragp
->fr_symbol
;
18025 exp
.X_add_number
= fragp
->fr_offset
;
18027 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18028 FALSE
, BFD_RELOC_MIPS_JMP
);
18029 fixp
->fx_file
= fragp
->fr_file
;
18030 fixp
->fx_line
= fragp
->fr_line
;
18032 buf
= write_insn (buf
, insn
);
18036 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18038 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18039 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18040 insn
|= at
<< OP_SH_RT
;
18041 exp
.X_op
= O_symbol
;
18042 exp
.X_add_symbol
= fragp
->fr_symbol
;
18043 exp
.X_add_number
= fragp
->fr_offset
;
18045 if (fragp
->fr_offset
)
18047 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18048 exp
.X_add_number
= 0;
18051 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18052 FALSE
, BFD_RELOC_MIPS_GOT16
);
18053 fixp
->fx_file
= fragp
->fr_file
;
18054 fixp
->fx_line
= fragp
->fr_line
;
18056 buf
= write_insn (buf
, insn
);
18058 if (mips_opts
.isa
== ISA_MIPS1
)
18060 buf
= write_insn (buf
, 0);
18062 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18063 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18064 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18066 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18067 FALSE
, BFD_RELOC_LO16
);
18068 fixp
->fx_file
= fragp
->fr_file
;
18069 fixp
->fx_line
= fragp
->fr_line
;
18071 buf
= write_insn (buf
, insn
);
18074 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18078 insn
|= at
<< OP_SH_RS
;
18080 buf
= write_insn (buf
, insn
);
18084 fragp
->fr_fix
+= fragp
->fr_var
;
18085 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18089 /* Relax microMIPS branches. */
18090 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18092 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18093 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18094 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18095 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18096 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18097 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18098 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18099 bfd_boolean short_ds
;
18100 unsigned long insn
;
18104 exp
.X_op
= O_symbol
;
18105 exp
.X_add_symbol
= fragp
->fr_symbol
;
18106 exp
.X_add_number
= fragp
->fr_offset
;
18108 fragp
->fr_fix
+= fragp
->fr_var
;
18110 /* Handle 16-bit branches that fit or are forced to fit. */
18111 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18113 /* We generate a fixup instead of applying it right now,
18114 because if there is linker relaxation, we're going to
18115 need the relocations. */
18117 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18118 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18119 else if (type
== 'E')
18120 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18121 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18125 fixp
->fx_file
= fragp
->fr_file
;
18126 fixp
->fx_line
= fragp
->fr_line
;
18128 /* These relocations can have an addend that won't fit in
18130 fixp
->fx_no_overflow
= 1;
18135 /* Handle 32-bit branches that fit or are forced to fit. */
18136 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18137 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18139 /* We generate a fixup instead of applying it right now,
18140 because if there is linker relaxation, we're going to
18141 need the relocations. */
18142 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18143 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18144 fixp
->fx_file
= fragp
->fr_file
;
18145 fixp
->fx_line
= fragp
->fr_line
;
18149 insn
= read_compressed_insn (buf
, 4);
18154 /* Check the short-delay-slot bit. */
18155 if (!al
|| (insn
& 0x02000000) != 0)
18156 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18158 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18161 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18166 /* Relax 16-bit branches to 32-bit branches. */
18169 insn
= read_compressed_insn (buf
, 2);
18171 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18172 insn
= 0x94000000; /* beq */
18173 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18175 unsigned long regno
;
18177 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18178 regno
= micromips_to_32_reg_d_map
[regno
];
18179 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18180 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18185 /* Nothing else to do, just write it out. */
18186 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18187 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18189 buf
= write_compressed_insn (buf
, insn
, 4);
18191 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18192 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18197 insn
= read_compressed_insn (buf
, 4);
18199 /* Relax 32-bit branches to a sequence of instructions. */
18200 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18201 _("relaxed out-of-range branch into a jump"));
18203 /* Set the short-delay-slot bit. */
18204 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18206 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18210 /* Reverse the branch. */
18211 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18212 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18213 insn
^= 0x20000000;
18214 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18215 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18216 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18217 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18218 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18219 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18220 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18221 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18222 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18223 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18224 insn
^= 0x00400000;
18225 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18226 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18227 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18228 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18229 insn
^= 0x00200000;
18230 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18232 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18234 insn
^= 0x00800000;
18240 /* Clear the and-link and short-delay-slot bits. */
18241 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18243 /* bltzal 0x40200000 bgezal 0x40600000 */
18244 /* bltzals 0x42200000 bgezals 0x42600000 */
18245 insn
&= ~0x02200000;
18248 /* Make a label at the end for use with the branch. */
18249 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18250 micromips_label_inc ();
18251 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18254 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18255 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18256 fixp
->fx_file
= fragp
->fr_file
;
18257 fixp
->fx_line
= fragp
->fr_line
;
18259 /* Branch over the jump. */
18260 buf
= write_compressed_insn (buf
, insn
, 4);
18266 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18268 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18274 unsigned long jal
= (short_ds
|| nods
18275 ? 0x74000000 : 0xf4000000); /* jal/s */
18277 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18278 insn
= al
? jal
: 0xd4000000;
18280 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18281 BFD_RELOC_MICROMIPS_JMP
);
18282 fixp
->fx_file
= fragp
->fr_file
;
18283 fixp
->fx_line
= fragp
->fr_line
;
18285 buf
= write_compressed_insn (buf
, insn
, 4);
18287 if (compact
|| nods
)
18291 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18293 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18298 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18300 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18301 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18302 insn
|= at
<< MICROMIPSOP_SH_RT
;
18304 if (exp
.X_add_number
)
18306 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18307 exp
.X_add_number
= 0;
18310 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18311 BFD_RELOC_MICROMIPS_GOT16
);
18312 fixp
->fx_file
= fragp
->fr_file
;
18313 fixp
->fx_line
= fragp
->fr_line
;
18315 buf
= write_compressed_insn (buf
, insn
, 4);
18317 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18318 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18319 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18321 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18322 BFD_RELOC_MICROMIPS_LO16
);
18323 fixp
->fx_file
= fragp
->fr_file
;
18324 fixp
->fx_line
= fragp
->fr_line
;
18326 buf
= write_compressed_insn (buf
, insn
, 4);
18331 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18332 insn
|= at
<< MICROMIPSOP_SH_RS
;
18334 buf
= write_compressed_insn (buf
, insn
, 4);
18336 if (compact
|| nods
)
18338 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18342 /* jr/jrc/jalr/jalrs $at */
18343 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18344 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18346 insn
= al
? jalr
: jr
;
18347 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18349 buf
= write_compressed_insn (buf
, insn
, 2);
18354 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18356 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18361 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18365 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18368 const struct mips_int_operand
*operand
;
18371 unsigned int user_length
, length
;
18372 bfd_boolean need_reloc
;
18373 unsigned long insn
;
18377 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18378 operand
= mips16_immed_operand (type
, FALSE
);
18380 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18381 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18383 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18384 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18385 || (operand
->root
.type
== OP_PCREL
18387 : !bfd_is_abs_section (symsec
)));
18389 if (operand
->root
.type
== OP_PCREL
)
18391 const struct mips_pcrel_operand
*pcrel_op
;
18393 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
18395 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
18397 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
18398 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18399 _("branch to a symbol in another ISA mode"));
18400 else if ((fragp
->fr_offset
& 0x1) != 0)
18401 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18402 _("branch to misaligned address (0x%lx)"),
18406 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
18408 /* Make sure the section winds up with the alignment we have
18410 if (operand
->shift
> 0)
18411 record_alignment (asec
, operand
->shift
);
18415 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18416 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18417 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18418 _("extended instruction in delay slot"));
18420 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18422 insn
= read_compressed_insn (buf
, 2);
18424 insn
|= MIPS16_EXTEND
;
18426 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18428 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18435 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
18443 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
18446 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18447 _("unsupported relocation"));
18450 if (reloc
== BFD_RELOC_NONE
)
18454 exp
.X_op
= O_symbol
;
18455 exp
.X_add_symbol
= fragp
->fr_symbol
;
18456 exp
.X_add_number
= fragp
->fr_offset
;
18458 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18461 fixp
->fx_file
= fragp
->fr_file
;
18462 fixp
->fx_line
= fragp
->fr_line
;
18465 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
18466 _("invalid unextended operand value"));
18469 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18470 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18472 length
= (ext
? 4 : 2);
18473 gas_assert (mips16_opcode_length (insn
) == length
);
18474 write_compressed_insn (buf
, insn
, length
);
18475 fragp
->fr_fix
+= length
;
18479 relax_substateT subtype
= fragp
->fr_subtype
;
18480 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18481 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18485 first
= RELAX_FIRST (subtype
);
18486 second
= RELAX_SECOND (subtype
);
18487 fixp
= (fixS
*) fragp
->fr_opcode
;
18489 /* If the delay slot chosen does not match the size of the instruction,
18490 then emit a warning. */
18491 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18492 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18497 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18498 | RELAX_DELAY_SLOT_SIZE_FIRST
18499 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18500 msg
= macro_warning (s
);
18502 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18506 /* Possibly emit a warning if we've chosen the longer option. */
18507 if (use_second
== second_longer
)
18513 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18514 msg
= macro_warning (s
);
18516 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18520 /* Go through all the fixups for the first sequence. Disable them
18521 (by marking them as done) if we're going to use the second
18522 sequence instead. */
18524 && fixp
->fx_frag
== fragp
18525 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18527 if (subtype
& RELAX_USE_SECOND
)
18529 fixp
= fixp
->fx_next
;
18532 /* Go through the fixups for the second sequence. Disable them if
18533 we're going to use the first sequence, otherwise adjust their
18534 addresses to account for the relaxation. */
18535 while (fixp
&& fixp
->fx_frag
== fragp
)
18537 if (subtype
& RELAX_USE_SECOND
)
18538 fixp
->fx_where
-= first
;
18541 fixp
= fixp
->fx_next
;
18544 /* Now modify the frag contents. */
18545 if (subtype
& RELAX_USE_SECOND
)
18549 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18550 memmove (start
, start
+ first
, second
);
18551 fragp
->fr_fix
-= first
;
18554 fragp
->fr_fix
-= second
;
18558 /* This function is called after the relocs have been generated.
18559 We've been storing mips16 text labels as odd. Here we convert them
18560 back to even for the convenience of the debugger. */
18563 mips_frob_file_after_relocs (void)
18566 unsigned int count
, i
;
18568 syms
= bfd_get_outsymbols (stdoutput
);
18569 count
= bfd_get_symcount (stdoutput
);
18570 for (i
= 0; i
< count
; i
++, syms
++)
18571 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18572 && ((*syms
)->value
& 1) != 0)
18574 (*syms
)->value
&= ~1;
18575 /* If the symbol has an odd size, it was probably computed
18576 incorrectly, so adjust that as well. */
18577 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18578 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18582 /* This function is called whenever a label is defined, including fake
18583 labels instantiated off the dot special symbol. It is used when
18584 handling branch delays; if a branch has a label, we assume we cannot
18585 move it. This also bumps the value of the symbol by 1 in compressed
18589 mips_record_label (symbolS
*sym
)
18591 segment_info_type
*si
= seg_info (now_seg
);
18592 struct insn_label_list
*l
;
18594 if (free_insn_labels
== NULL
)
18595 l
= XNEW (struct insn_label_list
);
18598 l
= free_insn_labels
;
18599 free_insn_labels
= l
->next
;
18603 l
->next
= si
->label_list
;
18604 si
->label_list
= l
;
18607 /* This function is called as tc_frob_label() whenever a label is defined
18608 and adds a DWARF-2 record we only want for true labels. */
18611 mips_define_label (symbolS
*sym
)
18613 mips_record_label (sym
);
18614 dwarf2_emit_label (sym
);
18617 /* This function is called by tc_new_dot_label whenever a new dot symbol
18621 mips_add_dot_label (symbolS
*sym
)
18623 mips_record_label (sym
);
18624 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18625 mips_compressed_mark_label (sym
);
18628 /* Converting ASE flags from internal to .MIPS.abiflags values. */
18629 static unsigned int
18630 mips_convert_ase_flags (int ase
)
18632 unsigned int ext_ases
= 0;
18635 ext_ases
|= AFL_ASE_DSP
;
18636 if (ase
& ASE_DSPR2
)
18637 ext_ases
|= AFL_ASE_DSPR2
;
18638 if (ase
& ASE_DSPR3
)
18639 ext_ases
|= AFL_ASE_DSPR3
;
18641 ext_ases
|= AFL_ASE_EVA
;
18643 ext_ases
|= AFL_ASE_MCU
;
18644 if (ase
& ASE_MDMX
)
18645 ext_ases
|= AFL_ASE_MDMX
;
18646 if (ase
& ASE_MIPS3D
)
18647 ext_ases
|= AFL_ASE_MIPS3D
;
18649 ext_ases
|= AFL_ASE_MT
;
18650 if (ase
& ASE_SMARTMIPS
)
18651 ext_ases
|= AFL_ASE_SMARTMIPS
;
18652 if (ase
& ASE_VIRT
)
18653 ext_ases
|= AFL_ASE_VIRT
;
18655 ext_ases
|= AFL_ASE_MSA
;
18657 ext_ases
|= AFL_ASE_XPA
;
18661 /* Some special processing for a MIPS ELF file. */
18664 mips_elf_final_processing (void)
18667 Elf_Internal_ABIFlags_v0 flags
;
18671 switch (file_mips_opts
.isa
)
18674 flags
.isa_level
= 1;
18677 flags
.isa_level
= 2;
18680 flags
.isa_level
= 3;
18683 flags
.isa_level
= 4;
18686 flags
.isa_level
= 5;
18689 flags
.isa_level
= 32;
18693 flags
.isa_level
= 32;
18697 flags
.isa_level
= 32;
18701 flags
.isa_level
= 32;
18705 flags
.isa_level
= 32;
18709 flags
.isa_level
= 64;
18713 flags
.isa_level
= 64;
18717 flags
.isa_level
= 64;
18721 flags
.isa_level
= 64;
18725 flags
.isa_level
= 64;
18730 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
18731 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
18732 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
18733 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
18735 flags
.cpr2_size
= AFL_REG_NONE
;
18736 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18737 Tag_GNU_MIPS_ABI_FP
);
18738 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
18739 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
18740 if (file_ase_mips16
)
18741 flags
.ases
|= AFL_ASE_MIPS16
;
18742 if (file_ase_micromips
)
18743 flags
.ases
|= AFL_ASE_MICROMIPS
;
18745 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
18746 || file_mips_opts
.fp
== 64)
18747 && file_mips_opts
.oddspreg
)
18748 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
18751 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
18752 ((Elf_External_ABIFlags_v0
*)
18755 /* Write out the register information. */
18756 if (mips_abi
!= N64_ABI
)
18760 s
.ri_gprmask
= mips_gprmask
;
18761 s
.ri_cprmask
[0] = mips_cprmask
[0];
18762 s
.ri_cprmask
[1] = mips_cprmask
[1];
18763 s
.ri_cprmask
[2] = mips_cprmask
[2];
18764 s
.ri_cprmask
[3] = mips_cprmask
[3];
18765 /* The gp_value field is set by the MIPS ELF backend. */
18767 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18768 ((Elf32_External_RegInfo
*)
18769 mips_regmask_frag
));
18773 Elf64_Internal_RegInfo s
;
18775 s
.ri_gprmask
= mips_gprmask
;
18777 s
.ri_cprmask
[0] = mips_cprmask
[0];
18778 s
.ri_cprmask
[1] = mips_cprmask
[1];
18779 s
.ri_cprmask
[2] = mips_cprmask
[2];
18780 s
.ri_cprmask
[3] = mips_cprmask
[3];
18781 /* The gp_value field is set by the MIPS ELF backend. */
18783 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18784 ((Elf64_External_RegInfo
*)
18785 mips_regmask_frag
));
18788 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18789 sort of BFD interface for this. */
18790 if (mips_any_noreorder
)
18791 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18792 if (mips_pic
!= NO_PIC
)
18794 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18795 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18798 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18800 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18801 defined at present; this might need to change in future. */
18802 if (file_ase_mips16
)
18803 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18804 if (file_ase_micromips
)
18805 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18806 if (file_mips_opts
.ase
& ASE_MDMX
)
18807 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18809 /* Set the MIPS ELF ABI flags. */
18810 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18811 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18812 else if (mips_abi
== O64_ABI
)
18813 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18814 else if (mips_abi
== EABI_ABI
)
18816 if (file_mips_opts
.gp
== 64)
18817 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18819 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18821 else if (mips_abi
== N32_ABI
)
18822 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18824 /* Nothing to do for N64_ABI. */
18826 if (mips_32bitmode
)
18827 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18829 if (mips_nan2008
== 1)
18830 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
18832 /* 32 bit code with 64 bit FP registers. */
18833 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
18834 Tag_GNU_MIPS_ABI_FP
);
18835 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
18836 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
18839 typedef struct proc
{
18841 symbolS
*func_end_sym
;
18842 unsigned long reg_mask
;
18843 unsigned long reg_offset
;
18844 unsigned long fpreg_mask
;
18845 unsigned long fpreg_offset
;
18846 unsigned long frame_offset
;
18847 unsigned long frame_reg
;
18848 unsigned long pc_reg
;
18851 static procS cur_proc
;
18852 static procS
*cur_proc_ptr
;
18853 static int numprocs
;
18855 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18856 as "2", and a normal nop as "0". */
18858 #define NOP_OPCODE_MIPS 0
18859 #define NOP_OPCODE_MIPS16 1
18860 #define NOP_OPCODE_MICROMIPS 2
18863 mips_nop_opcode (void)
18865 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18866 return NOP_OPCODE_MICROMIPS
;
18867 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18868 return NOP_OPCODE_MIPS16
;
18870 return NOP_OPCODE_MIPS
;
18873 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18874 32-bit microMIPS NOPs here (if applicable). */
18877 mips_handle_align (fragS
*fragp
)
18881 int bytes
, size
, excess
;
18884 if (fragp
->fr_type
!= rs_align_code
)
18887 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18889 switch (nop_opcode
)
18891 case NOP_OPCODE_MICROMIPS
:
18892 opcode
= micromips_nop32_insn
.insn_opcode
;
18895 case NOP_OPCODE_MIPS16
:
18896 opcode
= mips16_nop_insn
.insn_opcode
;
18899 case NOP_OPCODE_MIPS
:
18901 opcode
= nop_insn
.insn_opcode
;
18906 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18907 excess
= bytes
% size
;
18909 /* Handle the leading part if we're not inserting a whole number of
18910 instructions, and make it the end of the fixed part of the frag.
18911 Try to fit in a short microMIPS NOP if applicable and possible,
18912 and use zeroes otherwise. */
18913 gas_assert (excess
< 4);
18914 fragp
->fr_fix
+= excess
;
18919 /* Fall through. */
18921 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18923 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18927 /* Fall through. */
18930 /* Fall through. */
18935 md_number_to_chars (p
, opcode
, size
);
18936 fragp
->fr_var
= size
;
18945 if (*input_line_pointer
== '-')
18947 ++input_line_pointer
;
18950 if (!ISDIGIT (*input_line_pointer
))
18951 as_bad (_("expected simple number"));
18952 if (input_line_pointer
[0] == '0')
18954 if (input_line_pointer
[1] == 'x')
18956 input_line_pointer
+= 2;
18957 while (ISXDIGIT (*input_line_pointer
))
18960 val
|= hex_value (*input_line_pointer
++);
18962 return negative
? -val
: val
;
18966 ++input_line_pointer
;
18967 while (ISDIGIT (*input_line_pointer
))
18970 val
|= *input_line_pointer
++ - '0';
18972 return negative
? -val
: val
;
18975 if (!ISDIGIT (*input_line_pointer
))
18977 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18978 *input_line_pointer
, *input_line_pointer
);
18979 as_warn (_("invalid number"));
18982 while (ISDIGIT (*input_line_pointer
))
18985 val
+= *input_line_pointer
++ - '0';
18987 return negative
? -val
: val
;
18990 /* The .file directive; just like the usual .file directive, but there
18991 is an initial number which is the ECOFF file index. In the non-ECOFF
18992 case .file implies DWARF-2. */
18995 s_mips_file (int x ATTRIBUTE_UNUSED
)
18997 static int first_file_directive
= 0;
18999 if (ECOFF_DEBUGGING
)
19008 filename
= dwarf2_directive_file (0);
19010 /* Versions of GCC up to 3.1 start files with a ".file"
19011 directive even for stabs output. Make sure that this
19012 ".file" is handled. Note that you need a version of GCC
19013 after 3.1 in order to support DWARF-2 on MIPS. */
19014 if (filename
!= NULL
&& ! first_file_directive
)
19016 (void) new_logical_line (filename
, -1);
19017 s_app_file_string (filename
, 0);
19019 first_file_directive
= 1;
19023 /* The .loc directive, implying DWARF-2. */
19026 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19028 if (!ECOFF_DEBUGGING
)
19029 dwarf2_directive_loc (0);
19032 /* The .end directive. */
19035 s_mips_end (int x ATTRIBUTE_UNUSED
)
19039 /* Following functions need their own .frame and .cprestore directives. */
19040 mips_frame_reg_valid
= 0;
19041 mips_cprestore_valid
= 0;
19043 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19046 demand_empty_rest_of_line ();
19051 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19052 as_warn (_(".end not in text section"));
19056 as_warn (_(".end directive without a preceding .ent directive"));
19057 demand_empty_rest_of_line ();
19063 gas_assert (S_GET_NAME (p
));
19064 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19065 as_warn (_(".end symbol does not match .ent symbol"));
19067 if (debug_type
== DEBUG_STABS
)
19068 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19072 as_warn (_(".end directive missing or unknown symbol"));
19074 /* Create an expression to calculate the size of the function. */
19075 if (p
&& cur_proc_ptr
)
19077 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19078 expressionS
*exp
= XNEW (expressionS
);
19081 exp
->X_op
= O_subtract
;
19082 exp
->X_add_symbol
= symbol_temp_new_now ();
19083 exp
->X_op_symbol
= p
;
19084 exp
->X_add_number
= 0;
19086 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19089 #ifdef md_flush_pending_output
19090 md_flush_pending_output ();
19093 /* Generate a .pdr section. */
19094 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19096 segT saved_seg
= now_seg
;
19097 subsegT saved_subseg
= now_subseg
;
19101 gas_assert (pdr_seg
);
19102 subseg_set (pdr_seg
, 0);
19104 /* Write the symbol. */
19105 exp
.X_op
= O_symbol
;
19106 exp
.X_add_symbol
= p
;
19107 exp
.X_add_number
= 0;
19108 emit_expr (&exp
, 4);
19110 fragp
= frag_more (7 * 4);
19112 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19113 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19114 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19115 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19116 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19117 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19118 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19120 subseg_set (saved_seg
, saved_subseg
);
19123 cur_proc_ptr
= NULL
;
19126 /* The .aent and .ent directives. */
19129 s_mips_ent (int aent
)
19133 symbolP
= get_symbol ();
19134 if (*input_line_pointer
== ',')
19135 ++input_line_pointer
;
19136 SKIP_WHITESPACE ();
19137 if (ISDIGIT (*input_line_pointer
)
19138 || *input_line_pointer
== '-')
19141 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19142 as_warn (_(".ent or .aent not in text section"));
19144 if (!aent
&& cur_proc_ptr
)
19145 as_warn (_("missing .end"));
19149 /* This function needs its own .frame and .cprestore directives. */
19150 mips_frame_reg_valid
= 0;
19151 mips_cprestore_valid
= 0;
19153 cur_proc_ptr
= &cur_proc
;
19154 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19156 cur_proc_ptr
->func_sym
= symbolP
;
19160 if (debug_type
== DEBUG_STABS
)
19161 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19162 S_GET_NAME (symbolP
));
19165 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19167 demand_empty_rest_of_line ();
19170 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19171 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19172 s_mips_frame is used so that we can set the PDR information correctly.
19173 We can't use the ecoff routines because they make reference to the ecoff
19174 symbol table (in the mdebug section). */
19177 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19179 if (ECOFF_DEBUGGING
)
19185 if (cur_proc_ptr
== (procS
*) NULL
)
19187 as_warn (_(".frame outside of .ent"));
19188 demand_empty_rest_of_line ();
19192 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19194 SKIP_WHITESPACE ();
19195 if (*input_line_pointer
++ != ','
19196 || get_absolute_expression_and_terminator (&val
) != ',')
19198 as_warn (_("bad .frame directive"));
19199 --input_line_pointer
;
19200 demand_empty_rest_of_line ();
19204 cur_proc_ptr
->frame_offset
= val
;
19205 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19207 demand_empty_rest_of_line ();
19211 /* The .fmask and .mask directives. If the mdebug section is present
19212 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19213 embedded targets, s_mips_mask is used so that we can set the PDR
19214 information correctly. We can't use the ecoff routines because they
19215 make reference to the ecoff symbol table (in the mdebug section). */
19218 s_mips_mask (int reg_type
)
19220 if (ECOFF_DEBUGGING
)
19221 s_ignore (reg_type
);
19226 if (cur_proc_ptr
== (procS
*) NULL
)
19228 as_warn (_(".mask/.fmask outside of .ent"));
19229 demand_empty_rest_of_line ();
19233 if (get_absolute_expression_and_terminator (&mask
) != ',')
19235 as_warn (_("bad .mask/.fmask directive"));
19236 --input_line_pointer
;
19237 demand_empty_rest_of_line ();
19241 off
= get_absolute_expression ();
19243 if (reg_type
== 'F')
19245 cur_proc_ptr
->fpreg_mask
= mask
;
19246 cur_proc_ptr
->fpreg_offset
= off
;
19250 cur_proc_ptr
->reg_mask
= mask
;
19251 cur_proc_ptr
->reg_offset
= off
;
19254 demand_empty_rest_of_line ();
19258 /* A table describing all the processors gas knows about. Names are
19259 matched in the order listed.
19261 To ease comparison, please keep this table in the same order as
19262 gcc's mips_cpu_info_table[]. */
19263 static const struct mips_cpu_info mips_cpu_info_table
[] =
19265 /* Entries for generic ISAs */
19266 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19267 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19268 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19269 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19270 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19271 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19272 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19273 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19274 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19275 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19276 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19277 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19278 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19279 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19280 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19283 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19284 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19285 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19288 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19291 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19292 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19293 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19294 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19295 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19296 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19297 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19298 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19299 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19300 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19301 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19302 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19303 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19304 /* ST Microelectronics Loongson 2E and 2F cores */
19305 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19306 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19309 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19310 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19311 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19312 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19313 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19314 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19315 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19316 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19317 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19318 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19319 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19320 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19321 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19322 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19323 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19326 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19327 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19328 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19329 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19331 /* MIPS 32 Release 2 */
19332 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19333 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19334 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19335 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19336 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19337 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19338 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19339 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19340 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19341 ISA_MIPS32R2
, CPU_MIPS32R2
},
19342 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19343 ISA_MIPS32R2
, CPU_MIPS32R2
},
19344 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19345 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19346 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19347 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19348 /* Deprecated forms of the above. */
19349 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19350 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19351 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19352 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19353 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19354 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19355 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19356 /* Deprecated forms of the above. */
19357 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19358 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19359 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19360 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19361 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19362 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19363 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19364 /* Deprecated forms of the above. */
19365 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19366 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19367 /* 34Kn is a 34kc without DSP. */
19368 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19369 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19370 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19371 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19372 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19373 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19374 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19375 /* Deprecated forms of the above. */
19376 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19377 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19378 /* 1004K cores are multiprocessor versions of the 34K. */
19379 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19380 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19381 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19382 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19383 /* interaptiv is the new name for 1004kf */
19384 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19386 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19387 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19388 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
19389 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
19392 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19393 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19394 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19395 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19397 /* Broadcom SB-1 CPU core */
19398 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19399 /* Broadcom SB-1A CPU core */
19400 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19402 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
19404 /* MIPS 64 Release 2 */
19406 /* Cavium Networks Octeon CPU core */
19407 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19408 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19409 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19410 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
19413 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19416 XLP is mostly like XLR, with the prominent exception that it is
19417 MIPS64R2 rather than MIPS64. */
19418 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19420 /* MIPS 64 Release 6 */
19421 { "i6400", 0, ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19422 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
19425 { NULL
, 0, 0, 0, 0 }
19429 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19430 with a final "000" replaced by "k". Ignore case.
19432 Note: this function is shared between GCC and GAS. */
19435 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19437 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19438 given
++, canonical
++;
19440 return ((*given
== 0 && *canonical
== 0)
19441 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19445 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19446 CPU name. We've traditionally allowed a lot of variation here.
19448 Note: this function is shared between GCC and GAS. */
19451 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19453 /* First see if the name matches exactly, or with a final "000"
19454 turned into "k". */
19455 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19458 /* If not, try comparing based on numerical designation alone.
19459 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19460 if (TOLOWER (*given
) == 'r')
19462 if (!ISDIGIT (*given
))
19465 /* Skip over some well-known prefixes in the canonical name,
19466 hoping to find a number there too. */
19467 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19469 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19471 else if (TOLOWER (canonical
[0]) == 'r')
19474 return mips_strict_matching_cpu_name_p (canonical
, given
);
19478 /* Parse an option that takes the name of a processor as its argument.
19479 OPTION is the name of the option and CPU_STRING is the argument.
19480 Return the corresponding processor enumeration if the CPU_STRING is
19481 recognized, otherwise report an error and return null.
19483 A similar function exists in GCC. */
19485 static const struct mips_cpu_info
*
19486 mips_parse_cpu (const char *option
, const char *cpu_string
)
19488 const struct mips_cpu_info
*p
;
19490 /* 'from-abi' selects the most compatible architecture for the given
19491 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19492 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19493 version. Look first at the -mgp options, if given, otherwise base
19494 the choice on MIPS_DEFAULT_64BIT.
19496 Treat NO_ABI like the EABIs. One reason to do this is that the
19497 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19498 architecture. This code picks MIPS I for 'mips' and MIPS III for
19499 'mips64', just as we did in the days before 'from-abi'. */
19500 if (strcasecmp (cpu_string
, "from-abi") == 0)
19502 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19503 return mips_cpu_info_from_isa (ISA_MIPS1
);
19505 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19506 return mips_cpu_info_from_isa (ISA_MIPS3
);
19508 if (file_mips_opts
.gp
>= 0)
19509 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
19510 ? ISA_MIPS1
: ISA_MIPS3
);
19512 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19517 /* 'default' has traditionally been a no-op. Probably not very useful. */
19518 if (strcasecmp (cpu_string
, "default") == 0)
19521 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19522 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19525 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
19529 /* Return the canonical processor information for ISA (a member of the
19530 ISA_MIPS* enumeration). */
19532 static const struct mips_cpu_info
*
19533 mips_cpu_info_from_isa (int isa
)
19537 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19538 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19539 && isa
== mips_cpu_info_table
[i
].isa
)
19540 return (&mips_cpu_info_table
[i
]);
19545 static const struct mips_cpu_info
*
19546 mips_cpu_info_from_arch (int arch
)
19550 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19551 if (arch
== mips_cpu_info_table
[i
].cpu
)
19552 return (&mips_cpu_info_table
[i
]);
19558 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19562 fprintf (stream
, "%24s", "");
19567 fprintf (stream
, ", ");
19571 if (*col_p
+ strlen (string
) > 72)
19573 fprintf (stream
, "\n%24s", "");
19577 fprintf (stream
, "%s", string
);
19578 *col_p
+= strlen (string
);
19584 md_show_usage (FILE *stream
)
19589 fprintf (stream
, _("\
19591 -EB generate big endian output\n\
19592 -EL generate little endian output\n\
19593 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19594 -G NUM allow referencing objects up to NUM bytes\n\
19595 implicitly with the gp register [default 8]\n"));
19596 fprintf (stream
, _("\
19597 -mips1 generate MIPS ISA I instructions\n\
19598 -mips2 generate MIPS ISA II instructions\n\
19599 -mips3 generate MIPS ISA III instructions\n\
19600 -mips4 generate MIPS ISA IV instructions\n\
19601 -mips5 generate MIPS ISA V instructions\n\
19602 -mips32 generate MIPS32 ISA instructions\n\
19603 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19604 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19605 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19606 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19607 -mips64 generate MIPS64 ISA instructions\n\
19608 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19609 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19610 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19611 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19612 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19616 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19617 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19618 show (stream
, "from-abi", &column
, &first
);
19619 fputc ('\n', stream
);
19621 fprintf (stream
, _("\
19622 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19623 -no-mCPU don't generate code specific to CPU.\n\
19624 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19628 show (stream
, "3900", &column
, &first
);
19629 show (stream
, "4010", &column
, &first
);
19630 show (stream
, "4100", &column
, &first
);
19631 show (stream
, "4650", &column
, &first
);
19632 fputc ('\n', stream
);
19634 fprintf (stream
, _("\
19635 -mips16 generate mips16 instructions\n\
19636 -no-mips16 do not generate mips16 instructions\n"));
19637 fprintf (stream
, _("\
19638 -mmicromips generate microMIPS instructions\n\
19639 -mno-micromips do not generate microMIPS instructions\n"));
19640 fprintf (stream
, _("\
19641 -msmartmips generate smartmips instructions\n\
19642 -mno-smartmips do not generate smartmips instructions\n"));
19643 fprintf (stream
, _("\
19644 -mdsp generate DSP instructions\n\
19645 -mno-dsp do not generate DSP instructions\n"));
19646 fprintf (stream
, _("\
19647 -mdspr2 generate DSP R2 instructions\n\
19648 -mno-dspr2 do not generate DSP R2 instructions\n"));
19649 fprintf (stream
, _("\
19650 -mdspr3 generate DSP R3 instructions\n\
19651 -mno-dspr3 do not generate DSP R3 instructions\n"));
19652 fprintf (stream
, _("\
19653 -mmt generate MT instructions\n\
19654 -mno-mt do not generate MT instructions\n"));
19655 fprintf (stream
, _("\
19656 -mmcu generate MCU instructions\n\
19657 -mno-mcu do not generate MCU instructions\n"));
19658 fprintf (stream
, _("\
19659 -mmsa generate MSA instructions\n\
19660 -mno-msa do not generate MSA instructions\n"));
19661 fprintf (stream
, _("\
19662 -mxpa generate eXtended Physical Address (XPA) instructions\n\
19663 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
19664 fprintf (stream
, _("\
19665 -mvirt generate Virtualization instructions\n\
19666 -mno-virt do not generate Virtualization instructions\n"));
19667 fprintf (stream
, _("\
19668 -minsn32 only generate 32-bit microMIPS instructions\n\
19669 -mno-insn32 generate all microMIPS instructions\n"));
19670 fprintf (stream
, _("\
19671 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19672 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19673 -mfix-vr4120 work around certain VR4120 errata\n\
19674 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19675 -mfix-24k insert a nop after ERET and DERET instructions\n\
19676 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19677 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19678 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19679 -msym32 assume all symbols have 32-bit values\n\
19680 -O0 remove unneeded NOPs, do not swap branches\n\
19681 -O remove unneeded NOPs and swap branches\n\
19682 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19683 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19684 fprintf (stream
, _("\
19685 -mhard-float allow floating-point instructions\n\
19686 -msoft-float do not allow floating-point instructions\n\
19687 -msingle-float only allow 32-bit floating-point operations\n\
19688 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19689 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19690 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19691 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
19692 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
19693 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19697 show (stream
, "legacy", &column
, &first
);
19698 show (stream
, "2008", &column
, &first
);
19700 fputc ('\n', stream
);
19702 fprintf (stream
, _("\
19703 -KPIC, -call_shared generate SVR4 position independent code\n\
19704 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19705 -mvxworks-pic generate VxWorks position independent code\n\
19706 -non_shared do not generate code that can operate with DSOs\n\
19707 -xgot assume a 32 bit GOT\n\
19708 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19709 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19710 position dependent (non shared) code\n\
19711 -mabi=ABI create ABI conformant object file for:\n"));
19715 show (stream
, "32", &column
, &first
);
19716 show (stream
, "o64", &column
, &first
);
19717 show (stream
, "n32", &column
, &first
);
19718 show (stream
, "64", &column
, &first
);
19719 show (stream
, "eabi", &column
, &first
);
19721 fputc ('\n', stream
);
19723 fprintf (stream
, _("\
19724 -32 create o32 ABI object file (default)\n\
19725 -n32 create n32 ABI object file\n\
19726 -64 create 64 ABI object file\n"));
19731 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19733 if (HAVE_64BIT_SYMBOLS
)
19734 return dwarf2_format_64bit_irix
;
19736 return dwarf2_format_32bit
;
19741 mips_dwarf2_addr_size (void)
19743 if (HAVE_64BIT_OBJECTS
)
19749 /* Standard calling conventions leave the CFA at SP on entry. */
19751 mips_cfi_frame_initial_instructions (void)
19753 cfi_add_CFA_def_cfa_register (SP
);
19757 tc_mips_regname_to_dw2regnum (char *regname
)
19759 unsigned int regnum
= -1;
19762 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
19768 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
19769 Given a symbolic attribute NAME, return the proper integer value.
19770 Returns -1 if the attribute is not known. */
19773 mips_convert_symbolic_attribute (const char *name
)
19775 static const struct
19780 attribute_table
[] =
19782 #define T(tag) {#tag, tag}
19783 T (Tag_GNU_MIPS_ABI_FP
),
19784 T (Tag_GNU_MIPS_ABI_MSA
),
19792 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
19793 if (streq (name
, attribute_table
[i
].name
))
19794 return attribute_table
[i
].tag
;
19802 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
19804 mips_emit_delays ();
19806 as_warn (_("missing .end at end of assembly"));
19808 /* Just in case no code was emitted, do the consistency check. */
19809 file_mips_check_options ();
19811 /* Set a floating-point ABI if the user did not. */
19812 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
19814 /* Perform consistency checks on the floating-point ABI. */
19815 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19816 Tag_GNU_MIPS_ABI_FP
);
19817 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
19818 check_fpabi (fpabi
);
19822 /* Soft-float gets precedence over single-float, the two options should
19823 not be used together so this should not matter. */
19824 if (file_mips_opts
.soft_float
== 1)
19825 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
19826 /* Single-float gets precedence over all double_float cases. */
19827 else if (file_mips_opts
.single_float
== 1)
19828 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
19831 switch (file_mips_opts
.fp
)
19834 if (file_mips_opts
.gp
== 32)
19835 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19838 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
19841 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
19842 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
19843 else if (file_mips_opts
.gp
== 32)
19844 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
19846 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
19851 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19852 Tag_GNU_MIPS_ABI_FP
, fpabi
);
19856 /* Returns the relocation type required for a particular CFI encoding. */
19858 bfd_reloc_code_real_type
19859 mips_cfi_reloc_for_encoding (int encoding
)
19861 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
19862 return BFD_RELOC_32_PCREL
;
19863 else return BFD_RELOC_NONE
;