1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_coff_flavour
:
123 case bfd_target_elf_flavour
:
125 /* This is traditional mips */
126 return (target_big_endian
127 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
129 return (target_big_endian
130 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
131 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
139 /* The name of the readonly data section. */
140 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
142 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
144 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
146 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
150 /* This is the set of options which may be modified by the .set
151 pseudo-op. We use a struct so that .set push and .set pop are more
154 struct mips_set_options
156 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
157 if it has not been initialized. Changed by `.set mipsN', and the
158 -mipsN command line option, and the default CPU. */
160 /* Whether we are assembling for the mips16 processor. 0 if we are
161 not, 1 if we are, and -1 if the value has not been initialized.
162 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
163 -nomips16 command line options, and the default CPU. */
165 /* Non-zero if we should not reorder instructions. Changed by `.set
166 reorder' and `.set noreorder'. */
168 /* Non-zero if we should not permit the $at ($1) register to be used
169 in instructions. Changed by `.set at' and `.set noat'. */
171 /* Non-zero if we should warn when a macro instruction expands into
172 more than one machine instruction. Changed by `.set nomacro' and
174 int warn_about_macros
;
175 /* Non-zero if we should not move instructions. Changed by `.set
176 move', `.set volatile', `.set nomove', and `.set novolatile'. */
178 /* Non-zero if we should not optimize branches by moving the target
179 of the branch into the delay slot. Actually, we don't perform
180 this optimization anyhow. Changed by `.set bopt' and `.set
183 /* Non-zero if we should not autoextend mips16 instructions.
184 Changed by `.set autoextend' and `.set noautoextend'. */
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa and mips16 fields to -1 to indicate that
190 they have not been initialized. */
192 static struct mips_set_options mips_opts
= { -1, -1, 0, 0, 0, 0, 0, 0 };
194 /* These variables are filled in with the masks of registers used.
195 The object format code reads them and puts them in the appropriate
197 unsigned long mips_gprmask
;
198 unsigned long mips_cprmask
[4];
200 /* MIPS ISA we are using for this output file. */
201 static int file_mips_isa
;
203 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
204 static int mips_cpu
= -1;
206 /* The argument of the -mabi= flag. */
207 static char* mips_abi_string
= 0;
209 /* Wether we should mark the file EABI64 or EABI32. */
210 static int mips_eabi64
= 0;
212 /* If they asked for mips1 or mips2 and a cpu that is
213 mips3 or greater, then mark the object file 32BITMODE. */
214 static int mips_32bitmode
= 0;
216 /* True if -mgp32 was passed. */
217 static int mips_gp32
= 0;
219 /* Some ISA's have delay slots for instructions which read or write
220 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
221 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
222 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
223 delay slot in this ISA. The uses of this macro assume that any
224 ISA that has delay slots for one of these, has them for all. They
225 also assume that ISAs which don't have delays for these insns, don't
226 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
227 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
233 /* Return true if ISA supports 64 bit gp register instructions. */
234 #define ISA_HAS_64BIT_REGS(ISA) ( \
239 /* Whether the processor uses hardware interlocks to protect
240 reads from the HI and LO registers, and thus does not
241 require nops to be inserted.
243 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
244 -mcpu=FOO schedules for FOO, but still produces code that meets the
245 requirements of MIPS ISA I. For example, it won't generate any
246 FOO-specific instructions, and it will still assume that any
247 scheduling hazards described in MIPS ISA I are there, even if FOO
248 has interlocks. -mFOO gives GCC permission to generate code that
249 will only run on a FOO; it will generate FOO-specific instructions,
250 and assume interlocks provided by a FOO.
252 However, GAS currently doesn't make this distinction; before Jan 28
253 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
254 assumptions. The GCC driver passes these flags through to GAS, so
255 if GAS actually does anything that doesn't meet MIPS ISA I with
256 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
258 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
259 which seems senseless --- why generate code which will only run on
260 a FOO, but schedule for something else?
262 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
264 -- Jim Blandy <jimb@cygnus.com> */
266 #define hilo_interlocks (mips_cpu == CPU_R4010 \
269 /* Whether the processor uses hardware interlocks to protect reads
270 from the GPRs, and thus does not require nops to be inserted. */
271 #define gpr_interlocks \
272 (mips_opts.isa != 1 \
273 || mips_cpu == CPU_R3900)
275 /* As with other "interlocks" this is used by hardware that has FP
276 (co-processor) interlocks. */
277 /* Itbl support may require additional care here. */
278 #define cop_interlocks (mips_cpu == CPU_R4300 \
281 /* Is this a mfhi or mflo instruction? */
282 #define MF_HILO_INSN(PINFO) \
283 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
285 /* MIPS PIC level. */
289 /* Do not generate PIC code. */
292 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
293 not sure what it is supposed to do. */
296 /* Generate PIC code as in the SVR4 MIPS ABI. */
299 /* Generate PIC code without using a global offset table: the data
300 segment has a maximum size of 64K, all data references are off
301 the $gp register, and all text references are PC relative. This
302 is used on some embedded systems. */
306 static enum mips_pic_level mips_pic
;
308 /* 1 if we should generate 32 bit offsets from the GP register in
309 SVR4_PIC mode. Currently has no meaning in other modes. */
310 static int mips_big_got
;
312 /* 1 if trap instructions should used for overflow rather than break
314 static int mips_trap
;
316 /* 1 if double width floating point constants should not be constructed
317 by a assembling two single width halves into two single width floating
318 point registers which just happen to alias the double width destination
319 register. On some architectures this aliasing can be disabled by a bit
320 in the status register, and the setting of this bit cannot be determined
321 automatically at assemble time. */
322 static int mips_disable_float_construction
;
324 /* Non-zero if any .set noreorder directives were used. */
326 static int mips_any_noreorder
;
328 /* Non-zero if nops should be inserted when the register referenced in
329 an mfhi/mflo instruction is read in the next two instructions. */
330 static int mips_7000_hilo_fix
;
332 /* The size of the small data section. */
333 static unsigned int g_switch_value
= 8;
334 /* Whether the -G option was used. */
335 static int g_switch_seen
= 0;
340 /* If we can determine in advance that GP optimization won't be
341 possible, we can skip the relaxation stuff that tries to produce
342 GP-relative references. This makes delay slot optimization work
345 This function can only provide a guess, but it seems to work for
346 gcc output. It needs to guess right for gcc, otherwise gcc
347 will put what it thinks is a GP-relative instruction in a branch
350 I don't know if a fix is needed for the SVR4_PIC mode. I've only
351 fixed it for the non-PIC mode. KR 95/04/07 */
352 static int nopic_need_relax
PARAMS ((symbolS
*, int));
354 /* handle of the OPCODE hash table */
355 static struct hash_control
*op_hash
= NULL
;
357 /* The opcode hash table we use for the mips16. */
358 static struct hash_control
*mips16_op_hash
= NULL
;
360 /* This array holds the chars that always start a comment. If the
361 pre-processor is disabled, these aren't very useful */
362 const char comment_chars
[] = "#";
364 /* This array holds the chars that only start a comment at the beginning of
365 a line. If the line seems to have the form '# 123 filename'
366 .line and .file directives will appear in the pre-processed output */
367 /* Note that input_file.c hand checks for '#' at the beginning of the
368 first line of the input file. This is because the compiler outputs
369 #NO_APP at the beginning of its output. */
370 /* Also note that C style comments are always supported. */
371 const char line_comment_chars
[] = "#";
373 /* This array holds machine specific line separator characters. */
374 const char line_separator_chars
[] = ";";
376 /* Chars that can be used to separate mant from exp in floating point nums */
377 const char EXP_CHARS
[] = "eE";
379 /* Chars that mean this number is a floating point constant */
382 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
384 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
385 changed in read.c . Ideally it shouldn't have to know about it at all,
386 but nothing is ideal around here.
389 static char *insn_error
;
391 static int auto_align
= 1;
393 /* When outputting SVR4 PIC code, the assembler needs to know the
394 offset in the stack frame from which to restore the $gp register.
395 This is set by the .cprestore pseudo-op, and saved in this
397 static offsetT mips_cprestore_offset
= -1;
399 /* This is the register which holds the stack frame, as set by the
400 .frame pseudo-op. This is needed to implement .cprestore. */
401 static int mips_frame_reg
= SP
;
403 /* To output NOP instructions correctly, we need to keep information
404 about the previous two instructions. */
406 /* Whether we are optimizing. The default value of 2 means to remove
407 unneeded NOPs and swap branch instructions when possible. A value
408 of 1 means to not swap branches. A value of 0 means to always
410 static int mips_optimize
= 2;
412 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
413 equivalent to seeing no -g option at all. */
414 static int mips_debug
= 0;
416 /* The previous instruction. */
417 static struct mips_cl_insn prev_insn
;
419 /* The instruction before prev_insn. */
420 static struct mips_cl_insn prev_prev_insn
;
422 /* If we don't want information for prev_insn or prev_prev_insn, we
423 point the insn_mo field at this dummy integer. */
424 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
426 /* Non-zero if prev_insn is valid. */
427 static int prev_insn_valid
;
429 /* The frag for the previous instruction. */
430 static struct frag
*prev_insn_frag
;
432 /* The offset into prev_insn_frag for the previous instruction. */
433 static long prev_insn_where
;
435 /* The reloc type for the previous instruction, if any. */
436 static bfd_reloc_code_real_type prev_insn_reloc_type
;
438 /* The reloc for the previous instruction, if any. */
439 static fixS
*prev_insn_fixp
;
441 /* Non-zero if the previous instruction was in a delay slot. */
442 static int prev_insn_is_delay_slot
;
444 /* Non-zero if the previous instruction was in a .set noreorder. */
445 static int prev_insn_unreordered
;
447 /* Non-zero if the previous instruction uses an extend opcode (if
449 static int prev_insn_extended
;
451 /* Non-zero if the previous previous instruction was in a .set
453 static int prev_prev_insn_unreordered
;
455 /* If this is set, it points to a frag holding nop instructions which
456 were inserted before the start of a noreorder section. If those
457 nops turn out to be unnecessary, the size of the frag can be
459 static fragS
*prev_nop_frag
;
461 /* The number of nop instructions we created in prev_nop_frag. */
462 static int prev_nop_frag_holds
;
464 /* The number of nop instructions that we know we need in
466 static int prev_nop_frag_required
;
468 /* The number of instructions we've seen since prev_nop_frag. */
469 static int prev_nop_frag_since
;
471 /* For ECOFF and ELF, relocations against symbols are done in two
472 parts, with a HI relocation and a LO relocation. Each relocation
473 has only 16 bits of space to store an addend. This means that in
474 order for the linker to handle carries correctly, it must be able
475 to locate both the HI and the LO relocation. This means that the
476 relocations must appear in order in the relocation table.
478 In order to implement this, we keep track of each unmatched HI
479 relocation. We then sort them so that they immediately precede the
480 corresponding LO relocation. */
485 struct mips_hi_fixup
*next
;
488 /* The section this fixup is in. */
492 /* The list of unmatched HI relocs. */
494 static struct mips_hi_fixup
*mips_hi_fixup_list
;
496 /* Map normal MIPS register numbers to mips16 register numbers. */
498 #define X ILLEGAL_REG
499 static const int mips32_to_16_reg_map
[] =
501 X
, X
, 2, 3, 4, 5, 6, 7,
502 X
, X
, X
, X
, X
, X
, X
, X
,
503 0, 1, X
, X
, X
, X
, X
, X
,
504 X
, X
, X
, X
, X
, X
, X
, X
508 /* Map mips16 register numbers to normal MIPS register numbers. */
510 static const unsigned int mips16_to_32_reg_map
[] =
512 16, 17, 2, 3, 4, 5, 6, 7
515 /* Since the MIPS does not have multiple forms of PC relative
516 instructions, we do not have to do relaxing as is done on other
517 platforms. However, we do have to handle GP relative addressing
518 correctly, which turns out to be a similar problem.
520 Every macro that refers to a symbol can occur in (at least) two
521 forms, one with GP relative addressing and one without. For
522 example, loading a global variable into a register generally uses
523 a macro instruction like this:
525 If i can be addressed off the GP register (this is true if it is in
526 the .sbss or .sdata section, or if it is known to be smaller than
527 the -G argument) this will generate the following instruction:
529 This instruction will use a GPREL reloc. If i can not be addressed
530 off the GP register, the following instruction sequence will be used:
533 In this case the first instruction will have a HI16 reloc, and the
534 second reloc will have a LO16 reloc. Both relocs will be against
537 The issue here is that we may not know whether i is GP addressable
538 until after we see the instruction that uses it. Therefore, we
539 want to be able to choose the final instruction sequence only at
540 the end of the assembly. This is similar to the way other
541 platforms choose the size of a PC relative instruction only at the
544 When generating position independent code we do not use GP
545 addressing in quite the same way, but the issue still arises as
546 external symbols and local symbols must be handled differently.
548 We handle these issues by actually generating both possible
549 instruction sequences. The longer one is put in a frag_var with
550 type rs_machine_dependent. We encode what to do with the frag in
551 the subtype field. We encode (1) the number of existing bytes to
552 replace, (2) the number of new bytes to use, (3) the offset from
553 the start of the existing bytes to the first reloc we must generate
554 (that is, the offset is applied from the start of the existing
555 bytes after they are replaced by the new bytes, if any), (4) the
556 offset from the start of the existing bytes to the second reloc,
557 (5) whether a third reloc is needed (the third reloc is always four
558 bytes after the second reloc), and (6) whether to warn if this
559 variant is used (this is sometimes needed if .set nomacro or .set
560 noat is in effect). All these numbers are reasonably small.
562 Generating two instruction sequences must be handled carefully to
563 ensure that delay slots are handled correctly. Fortunately, there
564 are a limited number of cases. When the second instruction
565 sequence is generated, append_insn is directed to maintain the
566 existing delay slot information, so it continues to apply to any
567 code after the second instruction sequence. This means that the
568 second instruction sequence must not impose any requirements not
569 required by the first instruction sequence.
571 These variant frags are then handled in functions called by the
572 machine independent code. md_estimate_size_before_relax returns
573 the final size of the frag. md_convert_frag sets up the final form
574 of the frag. tc_gen_reloc adjust the first reloc and adds a second
576 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
580 | (((reloc1) + 64) << 9) \
581 | (((reloc2) + 64) << 2) \
582 | ((reloc3) ? (1 << 1) : 0) \
584 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
585 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
586 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
587 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
588 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
589 #define RELAX_WARN(i) ((i) & 1)
591 /* For mips16 code, we use an entirely different form of relaxation.
592 mips16 supports two versions of most instructions which take
593 immediate values: a small one which takes some small value, and a
594 larger one which takes a 16 bit value. Since branches also follow
595 this pattern, relaxing these values is required.
597 We can assemble both mips16 and normal MIPS code in a single
598 object. Therefore, we need to support this type of relaxation at
599 the same time that we support the relaxation described above. We
600 use the high bit of the subtype field to distinguish these cases.
602 The information we store for this type of relaxation is the
603 argument code found in the opcode file for this relocation, whether
604 the user explicitly requested a small or extended form, and whether
605 the relocation is in a jump or jal delay slot. That tells us the
606 size of the value, and how it should be stored. We also store
607 whether the fragment is considered to be extended or not. We also
608 store whether this is known to be a branch to a different section,
609 whether we have tried to relax this frag yet, and whether we have
610 ever extended a PC relative fragment because of a shift count. */
611 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
614 | ((small) ? 0x100 : 0) \
615 | ((ext) ? 0x200 : 0) \
616 | ((dslot) ? 0x400 : 0) \
617 | ((jal_dslot) ? 0x800 : 0))
618 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
619 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
620 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
621 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
622 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
623 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
624 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
625 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
626 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
627 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
628 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
629 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
631 /* Prototypes for static functions. */
634 #define internalError() \
635 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
637 #define internalError() as_fatal (_("MIPS internal Error"));
640 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
642 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
643 unsigned int reg
, enum mips_regclass
class));
644 static int reg_needs_delay
PARAMS ((unsigned int));
645 static void mips16_mark_labels
PARAMS ((void));
646 static void append_insn
PARAMS ((char *place
,
647 struct mips_cl_insn
* ip
,
649 bfd_reloc_code_real_type r
,
651 static void mips_no_prev_insn
PARAMS ((int));
652 static void mips_emit_delays
PARAMS ((boolean
));
654 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
655 const char *name
, const char *fmt
,
658 static void macro_build ();
660 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
661 const char *, const char *,
663 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
664 expressionS
* ep
, int regnum
));
665 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
666 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
668 static void load_register
PARAMS ((int *, int, expressionS
*, int));
669 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
670 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
671 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
672 #ifdef LOSING_COMPILER
673 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
675 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
676 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
677 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
678 boolean
, boolean
, unsigned long *,
679 boolean
*, unsigned short *));
680 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
681 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
682 static symbolS
*get_symbol
PARAMS ((void));
683 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
684 static void s_align
PARAMS ((int));
685 static void s_change_sec
PARAMS ((int));
686 static void s_cons
PARAMS ((int));
687 static void s_float_cons
PARAMS ((int));
688 static void s_mips_globl
PARAMS ((int));
689 static void s_option
PARAMS ((int));
690 static void s_mipsset
PARAMS ((int));
691 static void s_abicalls
PARAMS ((int));
692 static void s_cpload
PARAMS ((int));
693 static void s_cprestore
PARAMS ((int));
694 static void s_gpword
PARAMS ((int));
695 static void s_cpadd
PARAMS ((int));
696 static void s_insn
PARAMS ((int));
697 static void md_obj_begin
PARAMS ((void));
698 static void md_obj_end
PARAMS ((void));
699 static long get_number
PARAMS ((void));
700 static void s_mips_ent
PARAMS ((int));
701 static void s_mips_end
PARAMS ((int));
702 static void s_mips_frame
PARAMS ((int));
703 static void s_mips_mask
PARAMS ((int));
704 static void s_mips_stab
PARAMS ((int));
705 static void s_mips_weakext
PARAMS ((int));
706 static void s_file
PARAMS ((int));
707 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
708 static char *mips_cpu_to_str
PARAMS ((int));
710 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
714 The following pseudo-ops from the Kane and Heinrich MIPS book
715 should be defined here, but are currently unsupported: .alias,
716 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
718 The following pseudo-ops from the Kane and Heinrich MIPS book are
719 specific to the type of debugging information being generated, and
720 should be defined by the object format: .aent, .begin, .bend,
721 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
724 The following pseudo-ops from the Kane and Heinrich MIPS book are
725 not MIPS CPU specific, but are also not specific to the object file
726 format. This file is probably the best place to define them, but
727 they are not currently supported: .asm0, .endr, .lab, .repeat,
730 static const pseudo_typeS mips_pseudo_table
[] =
732 /* MIPS specific pseudo-ops. */
733 {"option", s_option
, 0},
734 {"set", s_mipsset
, 0},
735 {"rdata", s_change_sec
, 'r'},
736 {"sdata", s_change_sec
, 's'},
737 {"livereg", s_ignore
, 0},
738 {"abicalls", s_abicalls
, 0},
739 {"cpload", s_cpload
, 0},
740 {"cprestore", s_cprestore
, 0},
741 {"gpword", s_gpword
, 0},
742 {"cpadd", s_cpadd
, 0},
745 /* Relatively generic pseudo-ops that happen to be used on MIPS
747 {"asciiz", stringer
, 1},
748 {"bss", s_change_sec
, 'b'},
751 {"dword", s_cons
, 3},
752 {"weakext", s_mips_weakext
, 0},
754 /* These pseudo-ops are defined in read.c, but must be overridden
755 here for one reason or another. */
756 {"align", s_align
, 0},
758 {"data", s_change_sec
, 'd'},
759 {"double", s_float_cons
, 'd'},
760 {"float", s_float_cons
, 'f'},
761 {"globl", s_mips_globl
, 0},
762 {"global", s_mips_globl
, 0},
763 {"hword", s_cons
, 1},
768 {"short", s_cons
, 1},
769 {"single", s_float_cons
, 'f'},
770 {"stabn", s_mips_stab
, 'n'},
771 {"text", s_change_sec
, 't'},
776 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
777 /* These pseudo-ops should be defined by the object file format.
778 However, a.out doesn't support them, so we have versions here. */
779 {"aent", s_mips_ent
, 1},
780 {"bgnb", s_ignore
, 0},
781 {"end", s_mips_end
, 0},
782 {"endb", s_ignore
, 0},
783 {"ent", s_mips_ent
, 0},
785 {"fmask", s_mips_mask
, 'F'},
786 {"frame", s_mips_frame
, 0},
787 {"loc", s_ignore
, 0},
788 {"mask", s_mips_mask
, 'R'},
789 {"verstamp", s_ignore
, 0},
793 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
798 pop_insert (mips_pseudo_table
);
799 if (! ECOFF_DEBUGGING
)
800 pop_insert (mips_nonecoff_pseudo_table
);
803 /* Symbols labelling the current insn. */
805 struct insn_label_list
807 struct insn_label_list
*next
;
811 static struct insn_label_list
*insn_labels
;
812 static struct insn_label_list
*free_insn_labels
;
814 static void mips_clear_insn_labels
PARAMS ((void));
817 mips_clear_insn_labels ()
819 register struct insn_label_list
**pl
;
821 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
827 static char *expr_end
;
829 /* Expressions which appear in instructions. These are set by
832 static expressionS imm_expr
;
833 static expressionS offset_expr
;
835 /* Relocs associated with imm_expr and offset_expr. */
837 static bfd_reloc_code_real_type imm_reloc
;
838 static bfd_reloc_code_real_type offset_reloc
;
840 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
842 static boolean imm_unmatched_hi
;
844 /* These are set by mips16_ip if an explicit extension is used. */
846 static boolean mips16_small
, mips16_ext
;
848 #ifdef MIPS_STABS_ELF
849 /* The pdr segment for per procedure frame/regmask info */
855 mips_cpu_to_str (cpu
)
861 case CPU_R2000
: return "R2000";
862 case CPU_R3000
: return "R3000";
863 case CPU_R3900
: return "R3900";
864 case CPU_R4000
: return "R4000";
865 case CPU_R4010
: return "R4010";
866 case CPU_VR4100
: return "VR4100";
867 case CPU_R4111
: return "R4111";
868 case CPU_R4300
: return "R4300";
869 case CPU_R4400
: return "R4400";
870 case CPU_R4600
: return "R4600";
871 case CPU_R4650
: return "R4650";
872 case CPU_R5000
: return "R5000";
873 case CPU_R6000
: return "R6000";
874 case CPU_R8000
: return "R8000";
875 case CPU_R10000
: return "R10000";
876 case CPU_4K
: return "4K";
878 sprintf (s
, "%d", cpu
);
883 /* This function is called once, at assembler startup time. It should
884 set up all the tables, etc. that the MD part of the assembler will need. */
890 register const char *retval
= NULL
;
895 int mips_isa_from_cpu
;
897 /* GP relative stuff not working for PE */
898 if (strncmp (TARGET_OS
, "pe", 2) == 0
899 && g_switch_value
!= 0)
902 as_bad (_("-G not supported in this configuration."));
907 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
909 a
= xmalloc (sizeof TARGET_CPU
);
910 strcpy (a
, TARGET_CPU
);
911 a
[(sizeof TARGET_CPU
) - 3] = '\0';
917 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
918 just the generic 'mips', in which case set mips_cpu based
919 on the given ISA, if any. */
921 if (strcmp (cpu
, "mips") == 0)
923 if (mips_opts
.isa
< 0)
924 mips_cpu
= CPU_R3000
;
926 else if (mips_opts
.isa
== 2)
927 mips_cpu
= CPU_R6000
;
929 else if (mips_opts
.isa
== 3)
930 mips_cpu
= CPU_R4000
;
932 else if (mips_opts
.isa
== 4)
933 mips_cpu
= CPU_R8000
;
936 mips_cpu
= CPU_R3000
;
939 else if (strcmp (cpu
, "r3900") == 0
940 || strcmp (cpu
, "mipstx39") == 0
942 mips_cpu
= CPU_R3900
;
944 else if (strcmp (cpu
, "r6000") == 0
945 || strcmp (cpu
, "mips2") == 0)
946 mips_cpu
= CPU_R6000
;
948 else if (strcmp (cpu
, "mips64") == 0
949 || strcmp (cpu
, "r4000") == 0
950 || strcmp (cpu
, "mips3") == 0)
951 mips_cpu
= CPU_R4000
;
953 else if (strcmp (cpu
, "r4400") == 0)
954 mips_cpu
= CPU_R4400
;
956 else if (strcmp (cpu
, "mips64orion") == 0
957 || strcmp (cpu
, "r4600") == 0)
958 mips_cpu
= CPU_R4600
;
960 else if (strcmp (cpu
, "r4650") == 0)
961 mips_cpu
= CPU_R4650
;
963 else if (strcmp (cpu
, "mips64vr4300") == 0)
964 mips_cpu
= CPU_R4300
;
966 else if (strcmp (cpu
, "mips64vr4111") == 0)
967 mips_cpu
= CPU_R4111
;
969 else if (strcmp (cpu
, "mips64vr4100") == 0)
970 mips_cpu
= CPU_VR4100
;
972 else if (strcmp (cpu
, "r4010") == 0)
973 mips_cpu
= CPU_R4010
;
975 else if (strcmp (cpu
, "4Kc") == 0
976 || strcmp (cpu
, "4Kp") == 0
977 || strcmp (cpu
, "4Km") == 0)
980 else if (strcmp (cpu
, "r5000") == 0
981 || strcmp (cpu
, "mips64vr5000") == 0)
982 mips_cpu
= CPU_R5000
;
984 else if (strcmp (cpu
, "r8000") == 0
985 || strcmp (cpu
, "mips4") == 0)
986 mips_cpu
= CPU_R8000
;
988 else if (strcmp (cpu
, "r10000") == 0)
989 mips_cpu
= CPU_R10000
;
991 else if (strcmp (cpu
, "mips16") == 0)
992 mips_cpu
= 0; /* FIXME */
995 mips_cpu
= CPU_R3000
;
998 if (mips_cpu
== CPU_R3000
999 || mips_cpu
== CPU_R3900
)
1000 mips_isa_from_cpu
= 1;
1002 else if (mips_cpu
== CPU_R6000
1003 || mips_cpu
== CPU_R4010
)
1004 mips_isa_from_cpu
= 2;
1006 else if (mips_cpu
== CPU_R4000
1007 || mips_cpu
== CPU_VR4100
1008 || mips_cpu
== CPU_R4111
1009 || mips_cpu
== CPU_R4400
1010 || mips_cpu
== CPU_R4300
1011 || mips_cpu
== CPU_R4600
1012 || mips_cpu
== CPU_R4650
)
1013 mips_isa_from_cpu
= 3;
1015 else if (mips_cpu
== CPU_R5000
1016 || mips_cpu
== CPU_R8000
1017 || mips_cpu
== CPU_R10000
)
1018 mips_isa_from_cpu
= 4;
1021 mips_isa_from_cpu
= -1;
1023 if (mips_opts
.isa
== -1)
1025 if (mips_isa_from_cpu
!= -1)
1026 mips_opts
.isa
= mips_isa_from_cpu
;
1031 if (mips_opts
.mips16
< 0)
1033 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1034 mips_opts
.mips16
= 1;
1036 mips_opts
.mips16
= 0;
1039 /* End of TARGET_CPU processing, get rid of malloced memory
1048 if (mips_opts
.isa
== 1 && mips_trap
)
1049 as_bad (_("trap exception not supported at ISA 1"));
1051 /* Set the EABI kind based on the ISA before the user gets
1052 to change the ISA with directives. This isn't really
1053 the best, but then neither is basing the abi on the isa. */
1054 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1056 && 0 == strcmp (mips_abi_string
,"eabi"))
1059 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1061 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1063 /* If they asked for mips1 or mips2 and a cpu that is
1064 mips3 or greater, then mark the object file 32BITMODE. */
1065 if (mips_isa_from_cpu
!= -1
1066 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1067 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1072 switch (mips_opts
.isa
)
1075 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R3000
);
1078 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R6000
);
1081 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R4000
);
1084 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, CPU_R8000
);
1090 as_warn (_("Could not set architecture and machine"));
1092 file_mips_isa
= mips_opts
.isa
;
1094 op_hash
= hash_new ();
1096 for (i
= 0; i
< NUMOPCODES
;)
1098 const char *name
= mips_opcodes
[i
].name
;
1100 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1103 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1104 mips_opcodes
[i
].name
, retval
);
1105 /* Probably a memory allocation problem? Give up now. */
1106 as_fatal (_("Broken assembler. No assembly attempted."));
1110 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1112 if (!validate_mips_insn (&mips_opcodes
[i
]))
1117 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1120 mips16_op_hash
= hash_new ();
1123 while (i
< bfd_mips16_num_opcodes
)
1125 const char *name
= mips16_opcodes
[i
].name
;
1127 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1129 as_fatal (_("internal: can't hash `%s': %s"),
1130 mips16_opcodes
[i
].name
, retval
);
1133 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1134 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1135 != mips16_opcodes
[i
].match
))
1137 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1138 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1143 while (i
< bfd_mips16_num_opcodes
1144 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1148 as_fatal (_("Broken assembler. No assembly attempted."));
1150 /* We add all the general register names to the symbol table. This
1151 helps us detect invalid uses of them. */
1152 for (i
= 0; i
< 32; i
++)
1156 sprintf (buf
, "$%d", i
);
1157 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1158 &zero_address_frag
));
1160 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1161 &zero_address_frag
));
1162 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1163 &zero_address_frag
));
1164 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1165 &zero_address_frag
));
1166 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1167 &zero_address_frag
));
1168 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1169 &zero_address_frag
));
1170 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1171 &zero_address_frag
));
1172 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1173 &zero_address_frag
));
1175 mips_no_prev_insn (false);
1178 mips_cprmask
[0] = 0;
1179 mips_cprmask
[1] = 0;
1180 mips_cprmask
[2] = 0;
1181 mips_cprmask
[3] = 0;
1183 /* set the default alignment for the text section (2**2) */
1184 record_alignment (text_section
, 2);
1186 if (USE_GLOBAL_POINTER_OPT
)
1187 bfd_set_gp_size (stdoutput
, g_switch_value
);
1189 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1191 /* On a native system, sections must be aligned to 16 byte
1192 boundaries. When configured for an embedded ELF target, we
1194 if (strcmp (TARGET_OS
, "elf") != 0)
1196 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1197 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1198 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1201 /* Create a .reginfo section for register masks and a .mdebug
1202 section for debugging information. */
1210 subseg
= now_subseg
;
1212 /* The ABI says this section should be loaded so that the
1213 running program can access it. However, we don't load it
1214 if we are configured for an embedded target */
1215 flags
= SEC_READONLY
| SEC_DATA
;
1216 if (strcmp (TARGET_OS
, "elf") != 0)
1217 flags
|= SEC_ALLOC
| SEC_LOAD
;
1221 sec
= subseg_new (".reginfo", (subsegT
) 0);
1223 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1224 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1227 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1232 /* The 64-bit ABI uses a .MIPS.options section rather than
1233 .reginfo section. */
1234 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1235 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1236 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1239 /* Set up the option header. */
1241 Elf_Internal_Options opthdr
;
1244 opthdr
.kind
= ODK_REGINFO
;
1245 opthdr
.size
= (sizeof (Elf_External_Options
)
1246 + sizeof (Elf64_External_RegInfo
));
1249 f
= frag_more (sizeof (Elf_External_Options
));
1250 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1251 (Elf_External_Options
*) f
);
1253 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1258 if (ECOFF_DEBUGGING
)
1260 sec
= subseg_new (".mdebug", (subsegT
) 0);
1261 (void) bfd_set_section_flags (stdoutput
, sec
,
1262 SEC_HAS_CONTENTS
| SEC_READONLY
);
1263 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1266 #ifdef MIPS_STABS_ELF
1267 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1268 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1269 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1270 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1273 subseg_set (seg
, subseg
);
1277 if (! ECOFF_DEBUGGING
)
1284 if (! ECOFF_DEBUGGING
)
1292 struct mips_cl_insn insn
;
1294 imm_expr
.X_op
= O_absent
;
1295 imm_reloc
= BFD_RELOC_UNUSED
;
1296 imm_unmatched_hi
= false;
1297 offset_expr
.X_op
= O_absent
;
1298 offset_reloc
= BFD_RELOC_UNUSED
;
1300 if (mips_opts
.mips16
)
1301 mips16_ip (str
, &insn
);
1304 mips_ip (str
, &insn
);
1305 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1306 str
, insn
.insn_opcode
));
1311 as_bad ("%s `%s'", insn_error
, str
);
1315 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1317 if (mips_opts
.mips16
)
1318 mips16_macro (&insn
);
1324 if (imm_expr
.X_op
!= O_absent
)
1325 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1327 else if (offset_expr
.X_op
!= O_absent
)
1328 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1330 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1334 /* See whether instruction IP reads register REG. CLASS is the type
1338 insn_uses_reg (ip
, reg
, class)
1339 struct mips_cl_insn
*ip
;
1341 enum mips_regclass
class;
1343 if (class == MIPS16_REG
)
1345 assert (mips_opts
.mips16
);
1346 reg
= mips16_to_32_reg_map
[reg
];
1347 class = MIPS_GR_REG
;
1350 /* Don't report on general register 0, since it never changes. */
1351 if (class == MIPS_GR_REG
&& reg
== 0)
1354 if (class == MIPS_FP_REG
)
1356 assert (! mips_opts
.mips16
);
1357 /* If we are called with either $f0 or $f1, we must check $f0.
1358 This is not optimal, because it will introduce an unnecessary
1359 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1360 need to distinguish reading both $f0 and $f1 or just one of
1361 them. Note that we don't have to check the other way,
1362 because there is no instruction that sets both $f0 and $f1
1363 and requires a delay. */
1364 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1365 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1366 == (reg
&~ (unsigned) 1)))
1368 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1369 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1370 == (reg
&~ (unsigned) 1)))
1373 else if (! mips_opts
.mips16
)
1375 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1376 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1378 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1379 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1384 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1385 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1386 & MIPS16OP_MASK_RX
)]
1389 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1390 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1391 & MIPS16OP_MASK_RY
)]
1394 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1395 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1396 & MIPS16OP_MASK_MOVE32Z
)]
1399 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1401 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1403 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1405 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1406 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1407 & MIPS16OP_MASK_REGR32
) == reg
)
1414 /* This function returns true if modifying a register requires a
1418 reg_needs_delay (reg
)
1421 unsigned long prev_pinfo
;
1423 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1424 if (! mips_opts
.noreorder
1425 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1426 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1427 || (! gpr_interlocks
1428 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1430 /* A load from a coprocessor or from memory. All load
1431 delays delay the use of general register rt for one
1432 instruction on the r3000. The r6000 and r4000 use
1434 /* Itbl support may require additional care here. */
1435 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1436 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1443 /* Mark instruction labels in mips16 mode. This permits the linker to
1444 handle them specially, such as generating jalx instructions when
1445 needed. We also make them odd for the duration of the assembly, in
1446 order to generate the right sort of code. We will make them even
1447 in the adjust_symtab routine, while leaving them marked. This is
1448 convenient for the debugger and the disassembler. The linker knows
1449 to make them odd again. */
1452 mips16_mark_labels ()
1454 if (mips_opts
.mips16
)
1456 struct insn_label_list
*l
;
1458 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1461 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1462 S_SET_OTHER (l
->label
, STO_MIPS16
);
1464 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1465 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1470 /* Output an instruction. PLACE is where to put the instruction; if
1471 it is NULL, this uses frag_more to get room. IP is the instruction
1472 information. ADDRESS_EXPR is an operand of the instruction to be
1473 used with RELOC_TYPE. */
1476 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1478 struct mips_cl_insn
*ip
;
1479 expressionS
*address_expr
;
1480 bfd_reloc_code_real_type reloc_type
;
1481 boolean unmatched_hi
;
1483 register unsigned long prev_pinfo
, pinfo
;
1488 /* Mark instruction labels in mips16 mode. */
1489 if (mips_opts
.mips16
)
1490 mips16_mark_labels ();
1492 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1493 pinfo
= ip
->insn_mo
->pinfo
;
1495 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1499 /* If the previous insn required any delay slots, see if we need
1500 to insert a NOP or two. There are eight kinds of possible
1501 hazards, of which an instruction can have at most one type.
1502 (1) a load from memory delay
1503 (2) a load from a coprocessor delay
1504 (3) an unconditional branch delay
1505 (4) a conditional branch delay
1506 (5) a move to coprocessor register delay
1507 (6) a load coprocessor register from memory delay
1508 (7) a coprocessor condition code delay
1509 (8) a HI/LO special register delay
1511 There are a lot of optimizations we could do that we don't.
1512 In particular, we do not, in general, reorder instructions.
1513 If you use gcc with optimization, it will reorder
1514 instructions and generally do much more optimization then we
1515 do here; repeating all that work in the assembler would only
1516 benefit hand written assembly code, and does not seem worth
1519 /* This is how a NOP is emitted. */
1520 #define emit_nop() \
1522 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1523 : md_number_to_chars (frag_more (4), 0, 4))
1525 /* The previous insn might require a delay slot, depending upon
1526 the contents of the current insn. */
1527 if (! mips_opts
.mips16
1528 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1529 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1530 && ! cop_interlocks
)
1531 || (! gpr_interlocks
1532 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1534 /* A load from a coprocessor or from memory. All load
1535 delays delay the use of general register rt for one
1536 instruction on the r3000. The r6000 and r4000 use
1538 /* Itbl support may require additional care here. */
1539 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1540 if (mips_optimize
== 0
1541 || insn_uses_reg (ip
,
1542 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1547 else if (! mips_opts
.mips16
1548 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1549 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1550 && ! cop_interlocks
)
1551 || (mips_opts
.isa
== 1
1552 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1554 /* A generic coprocessor delay. The previous instruction
1555 modified a coprocessor general or control register. If
1556 it modified a control register, we need to avoid any
1557 coprocessor instruction (this is probably not always
1558 required, but it sometimes is). If it modified a general
1559 register, we avoid using that register.
1561 On the r6000 and r4000 loading a coprocessor register
1562 from memory is interlocked, and does not require a delay.
1564 This case is not handled very well. There is no special
1565 knowledge of CP0 handling, and the coprocessors other
1566 than the floating point unit are not distinguished at
1568 /* Itbl support may require additional care here. FIXME!
1569 Need to modify this to include knowledge about
1570 user specified delays! */
1571 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1573 if (mips_optimize
== 0
1574 || insn_uses_reg (ip
,
1575 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1580 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1582 if (mips_optimize
== 0
1583 || insn_uses_reg (ip
,
1584 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1591 /* We don't know exactly what the previous instruction
1592 does. If the current instruction uses a coprocessor
1593 register, we must insert a NOP. If previous
1594 instruction may set the condition codes, and the
1595 current instruction uses them, we must insert two
1597 /* Itbl support may require additional care here. */
1598 if (mips_optimize
== 0
1599 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1600 && (pinfo
& INSN_READ_COND_CODE
)))
1602 else if (pinfo
& INSN_COP
)
1606 else if (! mips_opts
.mips16
1607 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1608 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1609 && ! cop_interlocks
)
1611 /* The previous instruction sets the coprocessor condition
1612 codes, but does not require a general coprocessor delay
1613 (this means it is a floating point comparison
1614 instruction). If this instruction uses the condition
1615 codes, we need to insert a single NOP. */
1616 /* Itbl support may require additional care here. */
1617 if (mips_optimize
== 0
1618 || (pinfo
& INSN_READ_COND_CODE
))
1622 /* If we're fixing up mfhi/mflo for the r7000 and the
1623 previous insn was an mfhi/mflo and the current insn
1624 reads the register that the mfhi/mflo wrote to, then
1627 else if (mips_7000_hilo_fix
1628 && MF_HILO_INSN (prev_pinfo
)
1629 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1637 /* If we're fixing up mfhi/mflo for the r7000 and the
1638 2nd previous insn was an mfhi/mflo and the current insn
1639 reads the register that the mfhi/mflo wrote to, then
1642 else if (mips_7000_hilo_fix
1643 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1644 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1652 else if (prev_pinfo
& INSN_READ_LO
)
1654 /* The previous instruction reads the LO register; if the
1655 current instruction writes to the LO register, we must
1656 insert two NOPS. Some newer processors have interlocks.
1657 Also the tx39's multiply instructions can be exectuted
1658 immediatly after a read from HI/LO (without the delay),
1659 though the tx39's divide insns still do require the
1661 if (! (hilo_interlocks
1662 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1663 && (mips_optimize
== 0
1664 || (pinfo
& INSN_WRITE_LO
)))
1666 /* Most mips16 branch insns don't have a delay slot.
1667 If a read from LO is immediately followed by a branch
1668 to a write to LO we have a read followed by a write
1669 less than 2 insns away. We assume the target of
1670 a branch might be a write to LO, and insert a nop
1671 between a read and an immediately following branch. */
1672 else if (mips_opts
.mips16
1673 && (mips_optimize
== 0
1674 || (pinfo
& MIPS16_INSN_BRANCH
)))
1677 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1679 /* The previous instruction reads the HI register; if the
1680 current instruction writes to the HI register, we must
1681 insert a NOP. Some newer processors have interlocks.
1682 Also the note tx39's multiply above. */
1683 if (! (hilo_interlocks
1684 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1685 && (mips_optimize
== 0
1686 || (pinfo
& INSN_WRITE_HI
)))
1688 /* Most mips16 branch insns don't have a delay slot.
1689 If a read from HI is immediately followed by a branch
1690 to a write to HI we have a read followed by a write
1691 less than 2 insns away. We assume the target of
1692 a branch might be a write to HI, and insert a nop
1693 between a read and an immediately following branch. */
1694 else if (mips_opts
.mips16
1695 && (mips_optimize
== 0
1696 || (pinfo
& MIPS16_INSN_BRANCH
)))
1700 /* If the previous instruction was in a noreorder section, then
1701 we don't want to insert the nop after all. */
1702 /* Itbl support may require additional care here. */
1703 if (prev_insn_unreordered
)
1706 /* There are two cases which require two intervening
1707 instructions: 1) setting the condition codes using a move to
1708 coprocessor instruction which requires a general coprocessor
1709 delay and then reading the condition codes 2) reading the HI
1710 or LO register and then writing to it (except on processors
1711 which have interlocks). If we are not already emitting a NOP
1712 instruction, we must check for these cases compared to the
1713 instruction previous to the previous instruction. */
1714 if ((! mips_opts
.mips16
1715 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1716 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1717 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1718 && (pinfo
& INSN_READ_COND_CODE
)
1719 && ! cop_interlocks
)
1720 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1721 && (pinfo
& INSN_WRITE_LO
)
1722 && ! (hilo_interlocks
1723 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1724 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1725 && (pinfo
& INSN_WRITE_HI
)
1726 && ! (hilo_interlocks
1727 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1732 if (prev_prev_insn_unreordered
)
1735 if (prev_prev_nop
&& nops
== 0)
1738 /* If we are being given a nop instruction, don't bother with
1739 one of the nops we would otherwise output. This will only
1740 happen when a nop instruction is used with mips_optimize set
1743 && ! mips_opts
.noreorder
1744 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1747 /* Now emit the right number of NOP instructions. */
1748 if (nops
> 0 && ! mips_opts
.noreorder
)
1751 unsigned long old_frag_offset
;
1753 struct insn_label_list
*l
;
1755 old_frag
= frag_now
;
1756 old_frag_offset
= frag_now_fix ();
1758 for (i
= 0; i
< nops
; i
++)
1763 listing_prev_line ();
1764 /* We may be at the start of a variant frag. In case we
1765 are, make sure there is enough space for the frag
1766 after the frags created by listing_prev_line. The
1767 argument to frag_grow here must be at least as large
1768 as the argument to all other calls to frag_grow in
1769 this file. We don't have to worry about being in the
1770 middle of a variant frag, because the variants insert
1771 all needed nop instructions themselves. */
1775 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1777 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1778 symbol_set_frag (l
->label
, frag_now
);
1779 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1780 /* mips16 text labels are stored as odd. */
1781 if (mips_opts
.mips16
)
1782 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1785 #ifndef NO_ECOFF_DEBUGGING
1786 if (ECOFF_DEBUGGING
)
1787 ecoff_fix_loc (old_frag
, old_frag_offset
);
1790 else if (prev_nop_frag
!= NULL
)
1792 /* We have a frag holding nops we may be able to remove. If
1793 we don't need any nops, we can decrease the size of
1794 prev_nop_frag by the size of one instruction. If we do
1795 need some nops, we count them in prev_nops_required. */
1796 if (prev_nop_frag_since
== 0)
1800 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1801 --prev_nop_frag_holds
;
1804 prev_nop_frag_required
+= nops
;
1808 if (prev_prev_nop
== 0)
1810 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1811 --prev_nop_frag_holds
;
1814 ++prev_nop_frag_required
;
1817 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1818 prev_nop_frag
= NULL
;
1820 ++prev_nop_frag_since
;
1822 /* Sanity check: by the time we reach the second instruction
1823 after prev_nop_frag, we should have used up all the nops
1824 one way or another. */
1825 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1829 if (reloc_type
> BFD_RELOC_UNUSED
)
1831 /* We need to set up a variant frag. */
1832 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1833 f
= frag_var (rs_machine_dependent
, 4, 0,
1834 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1835 mips16_small
, mips16_ext
,
1837 & INSN_UNCOND_BRANCH_DELAY
),
1838 (prev_insn_reloc_type
1839 == BFD_RELOC_MIPS16_JMP
)),
1840 make_expr_symbol (address_expr
), (offsetT
) 0,
1843 else if (place
!= NULL
)
1845 else if (mips_opts
.mips16
1847 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1849 /* Make sure there is enough room to swap this instruction with
1850 a following jump instruction. */
1856 if (mips_opts
.mips16
1857 && mips_opts
.noreorder
1858 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1859 as_warn (_("extended instruction in delay slot"));
1865 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1867 if (address_expr
->X_op
== O_constant
)
1872 ip
->insn_opcode
|= address_expr
->X_add_number
;
1875 case BFD_RELOC_LO16
:
1876 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1879 case BFD_RELOC_MIPS_JMP
:
1880 if ((address_expr
->X_add_number
& 3) != 0)
1881 as_bad (_("jump to misaligned address (0x%lx)"),
1882 (unsigned long) address_expr
->X_add_number
);
1883 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1886 case BFD_RELOC_MIPS16_JMP
:
1887 if ((address_expr
->X_add_number
& 3) != 0)
1888 as_bad (_("jump to misaligned address (0x%lx)"),
1889 (unsigned long) address_expr
->X_add_number
);
1891 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1892 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1893 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1896 case BFD_RELOC_16_PCREL_S2
:
1906 /* Don't generate a reloc if we are writing into a variant
1910 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1912 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1916 struct mips_hi_fixup
*hi_fixup
;
1918 assert (reloc_type
== BFD_RELOC_HI16_S
);
1919 hi_fixup
= ((struct mips_hi_fixup
*)
1920 xmalloc (sizeof (struct mips_hi_fixup
)));
1921 hi_fixup
->fixp
= fixp
;
1922 hi_fixup
->seg
= now_seg
;
1923 hi_fixup
->next
= mips_hi_fixup_list
;
1924 mips_hi_fixup_list
= hi_fixup
;
1930 if (! mips_opts
.mips16
)
1931 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1932 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1934 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1935 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1941 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1944 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1947 /* Update the register mask information. */
1948 if (! mips_opts
.mips16
)
1950 if (pinfo
& INSN_WRITE_GPR_D
)
1951 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1952 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1953 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1954 if (pinfo
& INSN_READ_GPR_S
)
1955 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1956 if (pinfo
& INSN_WRITE_GPR_31
)
1957 mips_gprmask
|= 1 << 31;
1958 if (pinfo
& INSN_WRITE_FPR_D
)
1959 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1960 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1961 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1962 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1963 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1964 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1965 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1966 if (pinfo
& INSN_COP
)
1968 /* We don't keep enough information to sort these cases out.
1969 The itbl support does keep this information however, although
1970 we currently don't support itbl fprmats as part of the cop
1971 instruction. May want to add this support in the future. */
1973 /* Never set the bit for $0, which is always zero. */
1974 mips_gprmask
&=~ 1 << 0;
1978 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1979 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1980 & MIPS16OP_MASK_RX
);
1981 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1982 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1983 & MIPS16OP_MASK_RY
);
1984 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1985 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1986 & MIPS16OP_MASK_RZ
);
1987 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1988 mips_gprmask
|= 1 << TREG
;
1989 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1990 mips_gprmask
|= 1 << SP
;
1991 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1992 mips_gprmask
|= 1 << RA
;
1993 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1994 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1995 if (pinfo
& MIPS16_INSN_READ_Z
)
1996 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1997 & MIPS16OP_MASK_MOVE32Z
);
1998 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1999 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2000 & MIPS16OP_MASK_REGR32
);
2003 if (place
== NULL
&& ! mips_opts
.noreorder
)
2005 /* Filling the branch delay slot is more complex. We try to
2006 switch the branch with the previous instruction, which we can
2007 do if the previous instruction does not set up a condition
2008 that the branch tests and if the branch is not itself the
2009 target of any branch. */
2010 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2011 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2013 if (mips_optimize
< 2
2014 /* If we have seen .set volatile or .set nomove, don't
2016 || mips_opts
.nomove
!= 0
2017 /* If we had to emit any NOP instructions, then we
2018 already know we can not swap. */
2020 /* If we don't even know the previous insn, we can not
2022 || ! prev_insn_valid
2023 /* If the previous insn is already in a branch delay
2024 slot, then we can not swap. */
2025 || prev_insn_is_delay_slot
2026 /* If the previous previous insn was in a .set
2027 noreorder, we can't swap. Actually, the MIPS
2028 assembler will swap in this situation. However, gcc
2029 configured -with-gnu-as will generate code like
2035 in which we can not swap the bne and INSN. If gcc is
2036 not configured -with-gnu-as, it does not output the
2037 .set pseudo-ops. We don't have to check
2038 prev_insn_unreordered, because prev_insn_valid will
2039 be 0 in that case. We don't want to use
2040 prev_prev_insn_valid, because we do want to be able
2041 to swap at the start of a function. */
2042 || prev_prev_insn_unreordered
2043 /* If the branch is itself the target of a branch, we
2044 can not swap. We cheat on this; all we check for is
2045 whether there is a label on this instruction. If
2046 there are any branches to anything other than a
2047 label, users must use .set noreorder. */
2048 || insn_labels
!= NULL
2049 /* If the previous instruction is in a variant frag, we
2050 can not do the swap. This does not apply to the
2051 mips16, which uses variant frags for different
2053 || (! mips_opts
.mips16
2054 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2055 /* If the branch reads the condition codes, we don't
2056 even try to swap, because in the sequence
2061 we can not swap, and I don't feel like handling that
2063 || (! mips_opts
.mips16
2064 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2065 && (pinfo
& INSN_READ_COND_CODE
))
2066 /* We can not swap with an instruction that requires a
2067 delay slot, becase the target of the branch might
2068 interfere with that instruction. */
2069 || (! mips_opts
.mips16
2070 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2072 /* Itbl support may require additional care here. */
2073 & (INSN_LOAD_COPROC_DELAY
2074 | INSN_COPROC_MOVE_DELAY
2075 | INSN_WRITE_COND_CODE
)))
2076 || (! (hilo_interlocks
2077 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2081 || (! mips_opts
.mips16
2083 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2084 || (! mips_opts
.mips16
2085 && mips_opts
.isa
== 1
2086 /* Itbl support may require additional care here. */
2087 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2088 /* We can not swap with a branch instruction. */
2090 & (INSN_UNCOND_BRANCH_DELAY
2091 | INSN_COND_BRANCH_DELAY
2092 | INSN_COND_BRANCH_LIKELY
))
2093 /* We do not swap with a trap instruction, since it
2094 complicates trap handlers to have the trap
2095 instruction be in a delay slot. */
2096 || (prev_pinfo
& INSN_TRAP
)
2097 /* If the branch reads a register that the previous
2098 instruction sets, we can not swap. */
2099 || (! mips_opts
.mips16
2100 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2101 && insn_uses_reg (ip
,
2102 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2105 || (! mips_opts
.mips16
2106 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2107 && insn_uses_reg (ip
,
2108 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2111 || (mips_opts
.mips16
2112 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2113 && insn_uses_reg (ip
,
2114 ((prev_insn
.insn_opcode
2116 & MIPS16OP_MASK_RX
),
2118 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2119 && insn_uses_reg (ip
,
2120 ((prev_insn
.insn_opcode
2122 & MIPS16OP_MASK_RY
),
2124 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2125 && insn_uses_reg (ip
,
2126 ((prev_insn
.insn_opcode
2128 & MIPS16OP_MASK_RZ
),
2130 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2131 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2132 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2133 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2134 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2135 && insn_uses_reg (ip
,
2136 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2139 /* If the branch writes a register that the previous
2140 instruction sets, we can not swap (we know that
2141 branches write only to RD or to $31). */
2142 || (! mips_opts
.mips16
2143 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2144 && (((pinfo
& INSN_WRITE_GPR_D
)
2145 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2146 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2147 || ((pinfo
& INSN_WRITE_GPR_31
)
2148 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2151 || (! mips_opts
.mips16
2152 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2153 && (((pinfo
& INSN_WRITE_GPR_D
)
2154 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2155 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2156 || ((pinfo
& INSN_WRITE_GPR_31
)
2157 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2160 || (mips_opts
.mips16
2161 && (pinfo
& MIPS16_INSN_WRITE_31
)
2162 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2163 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2164 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2166 /* If the branch writes a register that the previous
2167 instruction reads, we can not swap (we know that
2168 branches only write to RD or to $31). */
2169 || (! mips_opts
.mips16
2170 && (pinfo
& INSN_WRITE_GPR_D
)
2171 && insn_uses_reg (&prev_insn
,
2172 ((ip
->insn_opcode
>> OP_SH_RD
)
2175 || (! mips_opts
.mips16
2176 && (pinfo
& INSN_WRITE_GPR_31
)
2177 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2178 || (mips_opts
.mips16
2179 && (pinfo
& MIPS16_INSN_WRITE_31
)
2180 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2181 /* If we are generating embedded PIC code, the branch
2182 might be expanded into a sequence which uses $at, so
2183 we can't swap with an instruction which reads it. */
2184 || (mips_pic
== EMBEDDED_PIC
2185 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2186 /* If the previous previous instruction has a load
2187 delay, and sets a register that the branch reads, we
2189 || (! mips_opts
.mips16
2190 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2191 /* Itbl support may require additional care here. */
2192 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2193 || (! gpr_interlocks
2194 && (prev_prev_insn
.insn_mo
->pinfo
2195 & INSN_LOAD_MEMORY_DELAY
)))
2196 && insn_uses_reg (ip
,
2197 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2200 /* If one instruction sets a condition code and the
2201 other one uses a condition code, we can not swap. */
2202 || ((pinfo
& INSN_READ_COND_CODE
)
2203 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2204 || ((pinfo
& INSN_WRITE_COND_CODE
)
2205 && (prev_pinfo
& INSN_READ_COND_CODE
))
2206 /* If the previous instruction uses the PC, we can not
2208 || (mips_opts
.mips16
2209 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2210 /* If the previous instruction was extended, we can not
2212 || (mips_opts
.mips16
&& prev_insn_extended
)
2213 /* If the previous instruction had a fixup in mips16
2214 mode, we can not swap. This normally means that the
2215 previous instruction was a 4 byte branch anyhow. */
2216 || (mips_opts
.mips16
&& prev_insn_fixp
)
2217 /* If the previous instruction is a sync, sync.l, or
2218 sync.p, we can not swap. */
2219 || (prev_pinfo
& INSN_SYNC
))
2221 /* We could do even better for unconditional branches to
2222 portions of this object file; we could pick up the
2223 instruction at the destination, put it in the delay
2224 slot, and bump the destination address. */
2226 /* Update the previous insn information. */
2227 prev_prev_insn
= *ip
;
2228 prev_insn
.insn_mo
= &dummy_opcode
;
2232 /* It looks like we can actually do the swap. */
2233 if (! mips_opts
.mips16
)
2238 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2239 memcpy (temp
, prev_f
, 4);
2240 memcpy (prev_f
, f
, 4);
2241 memcpy (f
, temp
, 4);
2244 prev_insn_fixp
->fx_frag
= frag_now
;
2245 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2249 fixp
->fx_frag
= prev_insn_frag
;
2250 fixp
->fx_where
= prev_insn_where
;
2258 assert (prev_insn_fixp
== NULL
);
2259 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2260 memcpy (temp
, prev_f
, 2);
2261 memcpy (prev_f
, f
, 2);
2262 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2264 assert (reloc_type
== BFD_RELOC_UNUSED
);
2265 memcpy (f
, temp
, 2);
2269 memcpy (f
, f
+ 2, 2);
2270 memcpy (f
+ 2, temp
, 2);
2274 fixp
->fx_frag
= prev_insn_frag
;
2275 fixp
->fx_where
= prev_insn_where
;
2279 /* Update the previous insn information; leave prev_insn
2281 prev_prev_insn
= *ip
;
2283 prev_insn_is_delay_slot
= 1;
2285 /* If that was an unconditional branch, forget the previous
2286 insn information. */
2287 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2289 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2290 prev_insn
.insn_mo
= &dummy_opcode
;
2293 prev_insn_fixp
= NULL
;
2294 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2295 prev_insn_extended
= 0;
2297 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2299 /* We don't yet optimize a branch likely. What we should do
2300 is look at the target, copy the instruction found there
2301 into the delay slot, and increment the branch to jump to
2302 the next instruction. */
2304 /* Update the previous insn information. */
2305 prev_prev_insn
= *ip
;
2306 prev_insn
.insn_mo
= &dummy_opcode
;
2307 prev_insn_fixp
= NULL
;
2308 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2309 prev_insn_extended
= 0;
2313 /* Update the previous insn information. */
2315 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2317 prev_prev_insn
= prev_insn
;
2320 /* Any time we see a branch, we always fill the delay slot
2321 immediately; since this insn is not a branch, we know it
2322 is not in a delay slot. */
2323 prev_insn_is_delay_slot
= 0;
2325 prev_insn_fixp
= fixp
;
2326 prev_insn_reloc_type
= reloc_type
;
2327 if (mips_opts
.mips16
)
2328 prev_insn_extended
= (ip
->use_extend
2329 || reloc_type
> BFD_RELOC_UNUSED
);
2332 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2333 prev_insn_unreordered
= 0;
2334 prev_insn_frag
= frag_now
;
2335 prev_insn_where
= f
- frag_now
->fr_literal
;
2336 prev_insn_valid
= 1;
2338 else if (place
== NULL
)
2340 /* We need to record a bit of information even when we are not
2341 reordering, in order to determine the base address for mips16
2342 PC relative relocs. */
2343 prev_prev_insn
= prev_insn
;
2345 prev_insn_reloc_type
= reloc_type
;
2346 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2347 prev_insn_unreordered
= 1;
2350 /* We just output an insn, so the next one doesn't have a label. */
2351 mips_clear_insn_labels ();
2353 /* We must ensure that a fixup associated with an unmatched %hi
2354 reloc does not become a variant frag. Otherwise, the
2355 rearrangement of %hi relocs in frob_file may confuse
2359 frag_wane (frag_now
);
2364 /* This function forgets that there was any previous instruction or
2365 label. If PRESERVE is non-zero, it remembers enough information to
2366 know whether nops are needed before a noreorder section. */
2369 mips_no_prev_insn (preserve
)
2374 prev_insn
.insn_mo
= &dummy_opcode
;
2375 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2376 prev_nop_frag
= NULL
;
2377 prev_nop_frag_holds
= 0;
2378 prev_nop_frag_required
= 0;
2379 prev_nop_frag_since
= 0;
2381 prev_insn_valid
= 0;
2382 prev_insn_is_delay_slot
= 0;
2383 prev_insn_unreordered
= 0;
2384 prev_insn_extended
= 0;
2385 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2386 prev_prev_insn_unreordered
= 0;
2387 mips_clear_insn_labels ();
2390 /* This function must be called whenever we turn on noreorder or emit
2391 something other than instructions. It inserts any NOPS which might
2392 be needed by the previous instruction, and clears the information
2393 kept for the previous instructions. The INSNS parameter is true if
2394 instructions are to follow. */
2397 mips_emit_delays (insns
)
2400 if (! mips_opts
.noreorder
)
2405 if ((! mips_opts
.mips16
2406 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2407 && (! cop_interlocks
2408 && (prev_insn
.insn_mo
->pinfo
2409 & (INSN_LOAD_COPROC_DELAY
2410 | INSN_COPROC_MOVE_DELAY
2411 | INSN_WRITE_COND_CODE
))))
2412 || (! hilo_interlocks
2413 && (prev_insn
.insn_mo
->pinfo
2416 || (! mips_opts
.mips16
2418 && (prev_insn
.insn_mo
->pinfo
2419 & INSN_LOAD_MEMORY_DELAY
))
2420 || (! mips_opts
.mips16
2421 && mips_opts
.isa
== 1
2422 && (prev_insn
.insn_mo
->pinfo
2423 & INSN_COPROC_MEMORY_DELAY
)))
2425 /* Itbl support may require additional care here. */
2427 if ((! mips_opts
.mips16
2428 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2429 && (! cop_interlocks
2430 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2431 || (! hilo_interlocks
2432 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2433 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2436 if (prev_insn_unreordered
)
2439 else if ((! mips_opts
.mips16
2440 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2441 && (! cop_interlocks
2442 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2443 || (! hilo_interlocks
2444 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2445 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2447 /* Itbl support may require additional care here. */
2448 if (! prev_prev_insn_unreordered
)
2454 struct insn_label_list
*l
;
2458 /* Record the frag which holds the nop instructions, so
2459 that we can remove them if we don't need them. */
2460 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2461 prev_nop_frag
= frag_now
;
2462 prev_nop_frag_holds
= nops
;
2463 prev_nop_frag_required
= 0;
2464 prev_nop_frag_since
= 0;
2467 for (; nops
> 0; --nops
)
2472 /* Move on to a new frag, so that it is safe to simply
2473 decrease the size of prev_nop_frag. */
2474 frag_wane (frag_now
);
2478 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2480 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2481 symbol_set_frag (l
->label
, frag_now
);
2482 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2483 /* mips16 text labels are stored as odd. */
2484 if (mips_opts
.mips16
)
2485 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2490 /* Mark instruction labels in mips16 mode. */
2491 if (mips_opts
.mips16
&& insns
)
2492 mips16_mark_labels ();
2494 mips_no_prev_insn (insns
);
2497 /* Build an instruction created by a macro expansion. This is passed
2498 a pointer to the count of instructions created so far, an
2499 expression, the name of the instruction to build, an operand format
2500 string, and corresponding arguments. */
2504 macro_build (char *place
,
2512 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2521 struct mips_cl_insn insn
;
2522 bfd_reloc_code_real_type r
;
2526 va_start (args
, fmt
);
2532 * If the macro is about to expand into a second instruction,
2533 * print a warning if needed. We need to pass ip as a parameter
2534 * to generate a better warning message here...
2536 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2537 as_warn (_("Macro instruction expanded into multiple instructions"));
2540 *counter
+= 1; /* bump instruction counter */
2542 if (mips_opts
.mips16
)
2544 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2549 r
= BFD_RELOC_UNUSED
;
2550 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2551 assert (insn
.insn_mo
);
2552 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2554 /* Search until we get a match for NAME. */
2557 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2558 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2559 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2561 && (mips_cpu
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2565 assert (insn
.insn_mo
->name
);
2566 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2569 insn
.insn_opcode
= insn
.insn_mo
->match
;
2585 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2591 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2596 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2601 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2608 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2612 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2616 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2620 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2627 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2633 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2634 assert (r
== BFD_RELOC_MIPS_GPREL
2635 || r
== BFD_RELOC_MIPS_LITERAL
2636 || r
== BFD_RELOC_LO16
2637 || r
== BFD_RELOC_MIPS_GOT16
2638 || r
== BFD_RELOC_MIPS_CALL16
2639 || r
== BFD_RELOC_MIPS_GOT_LO16
2640 || r
== BFD_RELOC_MIPS_CALL_LO16
2641 || (ep
->X_op
== O_subtract
2642 && r
== BFD_RELOC_PCREL_LO16
));
2646 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2648 && (ep
->X_op
== O_constant
2649 || (ep
->X_op
== O_symbol
2650 && (r
== BFD_RELOC_HI16_S
2651 || r
== BFD_RELOC_HI16
2652 || r
== BFD_RELOC_MIPS_GOT_HI16
2653 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2654 || (ep
->X_op
== O_subtract
2655 && r
== BFD_RELOC_PCREL_HI16_S
)));
2656 if (ep
->X_op
== O_constant
)
2658 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2660 r
= BFD_RELOC_UNUSED
;
2665 assert (ep
!= NULL
);
2667 * This allows macro() to pass an immediate expression for
2668 * creating short branches without creating a symbol.
2669 * Note that the expression still might come from the assembly
2670 * input, in which case the value is not checked for range nor
2671 * is a relocation entry generated (yuck).
2673 if (ep
->X_op
== O_constant
)
2675 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2679 r
= BFD_RELOC_16_PCREL_S2
;
2683 assert (ep
!= NULL
);
2684 r
= BFD_RELOC_MIPS_JMP
;
2688 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2697 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2699 append_insn (place
, &insn
, ep
, r
, false);
2703 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2705 int *counter ATTRIBUTE_UNUSED
;
2711 struct mips_cl_insn insn
;
2712 bfd_reloc_code_real_type r
;
2714 r
= BFD_RELOC_UNUSED
;
2715 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2716 assert (insn
.insn_mo
);
2717 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2719 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2720 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2723 assert (insn
.insn_mo
->name
);
2724 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2727 insn
.insn_opcode
= insn
.insn_mo
->match
;
2728 insn
.use_extend
= false;
2747 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2752 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2756 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2760 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2770 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2777 regno
= va_arg (args
, int);
2778 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2779 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2800 assert (ep
!= NULL
);
2802 if (ep
->X_op
!= O_constant
)
2803 r
= BFD_RELOC_UNUSED
+ c
;
2806 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2807 false, false, &insn
.insn_opcode
,
2808 &insn
.use_extend
, &insn
.extend
);
2810 r
= BFD_RELOC_UNUSED
;
2816 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2823 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2825 append_insn (place
, &insn
, ep
, r
, false);
2829 * Generate a "lui" instruction.
2832 macro_build_lui (place
, counter
, ep
, regnum
)
2838 expressionS high_expr
;
2839 struct mips_cl_insn insn
;
2840 bfd_reloc_code_real_type r
;
2841 CONST
char *name
= "lui";
2842 CONST
char *fmt
= "t,u";
2844 assert (! mips_opts
.mips16
);
2850 high_expr
.X_op
= O_constant
;
2851 high_expr
.X_add_number
= ep
->X_add_number
;
2854 if (high_expr
.X_op
== O_constant
)
2856 /* we can compute the instruction now without a relocation entry */
2857 if (high_expr
.X_add_number
& 0x8000)
2858 high_expr
.X_add_number
+= 0x10000;
2859 high_expr
.X_add_number
=
2860 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2861 r
= BFD_RELOC_UNUSED
;
2865 assert (ep
->X_op
== O_symbol
);
2866 /* _gp_disp is a special case, used from s_cpload. */
2867 assert (mips_pic
== NO_PIC
2868 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2869 r
= BFD_RELOC_HI16_S
;
2873 * If the macro is about to expand into a second instruction,
2874 * print a warning if needed. We need to pass ip as a parameter
2875 * to generate a better warning message here...
2877 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2878 as_warn (_("Macro instruction expanded into multiple instructions"));
2881 *counter
+= 1; /* bump instruction counter */
2883 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2884 assert (insn
.insn_mo
);
2885 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2886 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2888 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2889 if (r
== BFD_RELOC_UNUSED
)
2891 insn
.insn_opcode
|= high_expr
.X_add_number
;
2892 append_insn (place
, &insn
, NULL
, r
, false);
2895 append_insn (place
, &insn
, &high_expr
, r
, false);
2899 * Generates code to set the $at register to true (one)
2900 * if reg is less than the immediate expression.
2903 set_at (counter
, reg
, unsignedp
)
2908 if (imm_expr
.X_op
== O_constant
2909 && imm_expr
.X_add_number
>= -0x8000
2910 && imm_expr
.X_add_number
< 0x8000)
2911 macro_build ((char *) NULL
, counter
, &imm_expr
,
2912 unsignedp
? "sltiu" : "slti",
2913 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2916 load_register (counter
, AT
, &imm_expr
, 0);
2917 macro_build ((char *) NULL
, counter
, NULL
,
2918 unsignedp
? "sltu" : "slt",
2919 "d,v,t", AT
, reg
, AT
);
2923 /* Warn if an expression is not a constant. */
2926 check_absolute_expr (ip
, ex
)
2927 struct mips_cl_insn
*ip
;
2930 if (ex
->X_op
== O_big
)
2931 as_bad (_("unsupported large constant"));
2932 else if (ex
->X_op
!= O_constant
)
2933 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2936 /* Count the leading zeroes by performing a binary chop. This is a
2937 bulky bit of source, but performance is a LOT better for the
2938 majority of values than a simple loop to count the bits:
2939 for (lcnt = 0; (lcnt < 32); lcnt++)
2940 if ((v) & (1 << (31 - lcnt)))
2942 However it is not code size friendly, and the gain will drop a bit
2943 on certain cached systems.
2945 #define COUNT_TOP_ZEROES(v) \
2946 (((v) & ~0xffff) == 0 \
2947 ? ((v) & ~0xff) == 0 \
2948 ? ((v) & ~0xf) == 0 \
2949 ? ((v) & ~0x3) == 0 \
2950 ? ((v) & ~0x1) == 0 \
2955 : ((v) & ~0x7) == 0 \
2958 : ((v) & ~0x3f) == 0 \
2959 ? ((v) & ~0x1f) == 0 \
2962 : ((v) & ~0x7f) == 0 \
2965 : ((v) & ~0xfff) == 0 \
2966 ? ((v) & ~0x3ff) == 0 \
2967 ? ((v) & ~0x1ff) == 0 \
2970 : ((v) & ~0x7ff) == 0 \
2973 : ((v) & ~0x3fff) == 0 \
2974 ? ((v) & ~0x1fff) == 0 \
2977 : ((v) & ~0x7fff) == 0 \
2980 : ((v) & ~0xffffff) == 0 \
2981 ? ((v) & ~0xfffff) == 0 \
2982 ? ((v) & ~0x3ffff) == 0 \
2983 ? ((v) & ~0x1ffff) == 0 \
2986 : ((v) & ~0x7ffff) == 0 \
2989 : ((v) & ~0x3fffff) == 0 \
2990 ? ((v) & ~0x1fffff) == 0 \
2993 : ((v) & ~0x7fffff) == 0 \
2996 : ((v) & ~0xfffffff) == 0 \
2997 ? ((v) & ~0x3ffffff) == 0 \
2998 ? ((v) & ~0x1ffffff) == 0 \
3001 : ((v) & ~0x7ffffff) == 0 \
3004 : ((v) & ~0x3fffffff) == 0 \
3005 ? ((v) & ~0x1fffffff) == 0 \
3008 : ((v) & ~0x7fffffff) == 0 \
3013 * This routine generates the least number of instructions neccessary to load
3014 * an absolute expression value into a register.
3017 load_register (counter
, reg
, ep
, dbl
)
3024 expressionS hi32
, lo32
;
3026 if (ep
->X_op
!= O_big
)
3028 assert (ep
->X_op
== O_constant
);
3029 if (ep
->X_add_number
< 0x8000
3030 && (ep
->X_add_number
>= 0
3031 || (ep
->X_add_number
>= -0x8000
3034 || sizeof (ep
->X_add_number
) > 4))))
3036 /* We can handle 16 bit signed values with an addiu to
3037 $zero. No need to ever use daddiu here, since $zero and
3038 the result are always correct in 32 bit mode. */
3039 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3040 (int) BFD_RELOC_LO16
);
3043 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3045 /* We can handle 16 bit unsigned values with an ori to
3047 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3048 (int) BFD_RELOC_LO16
);
3051 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3052 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3053 == ~ (offsetT
) 0x7fffffff))
3056 || sizeof (ep
->X_add_number
) > 4
3057 || (ep
->X_add_number
& 0x80000000) == 0))
3058 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3059 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3060 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3062 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3063 == ~ (offsetT
) 0xffffffff)))
3065 /* 32 bit values require an lui. */
3066 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3067 (int) BFD_RELOC_HI16
);
3068 if ((ep
->X_add_number
& 0xffff) != 0)
3069 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3070 (int) BFD_RELOC_LO16
);
3075 /* The value is larger than 32 bits. */
3077 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3079 as_bad (_("Number larger than 32 bits"));
3080 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3081 (int) BFD_RELOC_LO16
);
3085 if (ep
->X_op
!= O_big
)
3088 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3089 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3090 hi32
.X_add_number
&= 0xffffffff;
3092 lo32
.X_add_number
&= 0xffffffff;
3096 assert (ep
->X_add_number
> 2);
3097 if (ep
->X_add_number
== 3)
3098 generic_bignum
[3] = 0;
3099 else if (ep
->X_add_number
> 4)
3100 as_bad (_("Number larger than 64 bits"));
3101 lo32
.X_op
= O_constant
;
3102 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3103 hi32
.X_op
= O_constant
;
3104 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3107 if (hi32
.X_add_number
== 0)
3112 unsigned long hi
, lo
;
3114 if (hi32
.X_add_number
== 0xffffffff)
3116 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3118 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3119 reg
, 0, (int) BFD_RELOC_LO16
);
3122 if (lo32
.X_add_number
& 0x80000000)
3124 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3125 (int) BFD_RELOC_HI16
);
3126 if (lo32
.X_add_number
& 0xffff)
3127 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3128 reg
, reg
, (int) BFD_RELOC_LO16
);
3133 /* Check for 16bit shifted constant. We know that hi32 is
3134 non-zero, so start the mask on the first bit of the hi32
3139 unsigned long himask
, lomask
;
3143 himask
= 0xffff >> (32 - shift
);
3144 lomask
= (0xffff << shift
) & 0xffffffff;
3148 himask
= 0xffff << (shift
- 32);
3151 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3152 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3156 tmp
.X_op
= O_constant
;
3158 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3159 | (lo32
.X_add_number
>> shift
));
3161 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3162 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3163 (int) BFD_RELOC_LO16
);
3164 macro_build ((char *) NULL
, counter
, NULL
,
3165 (shift
>= 32) ? "dsll32" : "dsll",
3167 (shift
>= 32) ? shift
- 32 : shift
);
3171 } while (shift
<= (64 - 16));
3173 /* Find the bit number of the lowest one bit, and store the
3174 shifted value in hi/lo. */
3175 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3176 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3180 while ((lo
& 1) == 0)
3185 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3191 while ((hi
& 1) == 0)
3200 /* Optimize if the shifted value is a (power of 2) - 1. */
3201 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3202 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3204 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3209 /* This instruction will set the register to be all
3211 tmp
.X_op
= O_constant
;
3212 tmp
.X_add_number
= (offsetT
) -1;
3213 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3214 reg
, 0, (int) BFD_RELOC_LO16
);
3218 macro_build ((char *) NULL
, counter
, NULL
,
3219 (bit
>= 32) ? "dsll32" : "dsll",
3221 (bit
>= 32) ? bit
- 32 : bit
);
3223 macro_build ((char *) NULL
, counter
, NULL
,
3224 (shift
>= 32) ? "dsrl32" : "dsrl",
3226 (shift
>= 32) ? shift
- 32 : shift
);
3231 /* Sign extend hi32 before calling load_register, because we can
3232 generally get better code when we load a sign extended value. */
3233 if ((hi32
.X_add_number
& 0x80000000) != 0)
3234 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3235 load_register (counter
, reg
, &hi32
, 0);
3238 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3242 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3251 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3253 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3254 (int) BFD_RELOC_HI16
);
3255 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3262 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3267 mid16
.X_add_number
>>= 16;
3268 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3269 freg
, (int) BFD_RELOC_LO16
);
3270 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3274 if ((lo32
.X_add_number
& 0xffff) != 0)
3275 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3276 (int) BFD_RELOC_LO16
);
3279 /* Load an address into a register. */
3282 load_address (counter
, reg
, ep
)
3289 if (ep
->X_op
!= O_constant
3290 && ep
->X_op
!= O_symbol
)
3292 as_bad (_("expression too complex"));
3293 ep
->X_op
= O_constant
;
3296 if (ep
->X_op
== O_constant
)
3298 load_register (counter
, reg
, ep
, 0);
3302 if (mips_pic
== NO_PIC
)
3304 /* If this is a reference to a GP relative symbol, we want
3305 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3307 lui $reg,<sym> (BFD_RELOC_HI16_S)
3308 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3309 If we have an addend, we always use the latter form. */
3310 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3311 || nopic_need_relax (ep
->X_add_symbol
, 1))
3316 macro_build ((char *) NULL
, counter
, ep
,
3317 ((bfd_arch_bits_per_address (stdoutput
) == 32
3318 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3319 ? "addiu" : "daddiu"),
3320 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3321 p
= frag_var (rs_machine_dependent
, 8, 0,
3322 RELAX_ENCODE (4, 8, 0, 4, 0,
3323 mips_opts
.warn_about_macros
),
3324 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3326 macro_build_lui (p
, counter
, ep
, reg
);
3329 macro_build (p
, counter
, ep
,
3330 ((bfd_arch_bits_per_address (stdoutput
) == 32
3331 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3332 ? "addiu" : "daddiu"),
3333 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3335 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3339 /* If this is a reference to an external symbol, we want
3340 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3342 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3344 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3345 If there is a constant, it must be added in after. */
3346 ex
.X_add_number
= ep
->X_add_number
;
3347 ep
->X_add_number
= 0;
3349 macro_build ((char *) NULL
, counter
, ep
,
3350 ((bfd_arch_bits_per_address (stdoutput
) == 32
3351 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3353 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3354 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3355 p
= frag_var (rs_machine_dependent
, 4, 0,
3356 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3357 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3358 macro_build (p
, counter
, ep
,
3359 ((bfd_arch_bits_per_address (stdoutput
) == 32
3360 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3361 ? "addiu" : "daddiu"),
3362 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3363 if (ex
.X_add_number
!= 0)
3365 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3366 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3367 ex
.X_op
= O_constant
;
3368 macro_build ((char *) NULL
, counter
, &ex
,
3369 ((bfd_arch_bits_per_address (stdoutput
) == 32
3370 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3371 ? "addiu" : "daddiu"),
3372 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3375 else if (mips_pic
== SVR4_PIC
)
3380 /* This is the large GOT case. If this is a reference to an
3381 external symbol, we want
3382 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3384 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3385 Otherwise, for a reference to a local symbol, we want
3386 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3388 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3389 If there is a constant, it must be added in after. */
3390 ex
.X_add_number
= ep
->X_add_number
;
3391 ep
->X_add_number
= 0;
3392 if (reg_needs_delay (GP
))
3397 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3398 (int) BFD_RELOC_MIPS_GOT_HI16
);
3399 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3400 ((bfd_arch_bits_per_address (stdoutput
) == 32
3401 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3402 ? "addu" : "daddu"),
3403 "d,v,t", reg
, reg
, GP
);
3404 macro_build ((char *) NULL
, counter
, ep
,
3405 ((bfd_arch_bits_per_address (stdoutput
) == 32
3406 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3408 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3409 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3410 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3411 mips_opts
.warn_about_macros
),
3412 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3415 /* We need a nop before loading from $gp. This special
3416 check is required because the lui which starts the main
3417 instruction stream does not refer to $gp, and so will not
3418 insert the nop which may be required. */
3419 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3422 macro_build (p
, counter
, ep
,
3423 ((bfd_arch_bits_per_address (stdoutput
) == 32
3424 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3426 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3428 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3430 macro_build (p
, counter
, ep
,
3431 ((bfd_arch_bits_per_address (stdoutput
) == 32
3432 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3433 ? "addiu" : "daddiu"),
3434 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3435 if (ex
.X_add_number
!= 0)
3437 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3438 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3439 ex
.X_op
= O_constant
;
3440 macro_build ((char *) NULL
, counter
, &ex
,
3441 ((bfd_arch_bits_per_address (stdoutput
) == 32
3442 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3443 ? "addiu" : "daddiu"),
3444 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3447 else if (mips_pic
== EMBEDDED_PIC
)
3450 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3452 macro_build ((char *) NULL
, counter
, ep
,
3453 ((bfd_arch_bits_per_address (stdoutput
) == 32
3454 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3455 ? "addiu" : "daddiu"),
3456 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3464 * This routine implements the seemingly endless macro or synthesized
3465 * instructions and addressing modes in the mips assembly language. Many
3466 * of these macros are simple and are similar to each other. These could
3467 * probably be handled by some kind of table or grammer aproach instead of
3468 * this verbose method. Others are not simple macros but are more like
3469 * optimizing code generation.
3470 * One interesting optimization is when several store macros appear
3471 * consecutivly that would load AT with the upper half of the same address.
3472 * The ensuing load upper instructions are ommited. This implies some kind
3473 * of global optimization. We currently only optimize within a single macro.
3474 * For many of the load and store macros if the address is specified as a
3475 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3476 * first load register 'at' with zero and use it as the base register. The
3477 * mips assembler simply uses register $zero. Just one tiny optimization
3482 struct mips_cl_insn
*ip
;
3484 register int treg
, sreg
, dreg
, breg
;
3500 bfd_reloc_code_real_type r
;
3502 int hold_mips_optimize
;
3504 assert (! mips_opts
.mips16
);
3506 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3507 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3508 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3509 mask
= ip
->insn_mo
->mask
;
3511 expr1
.X_op
= O_constant
;
3512 expr1
.X_op_symbol
= NULL
;
3513 expr1
.X_add_symbol
= NULL
;
3514 expr1
.X_add_number
= 1;
3526 mips_emit_delays (true);
3527 ++mips_opts
.noreorder
;
3528 mips_any_noreorder
= 1;
3530 expr1
.X_add_number
= 8;
3531 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3533 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3535 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3536 macro_build ((char *) NULL
, &icnt
, NULL
,
3537 dbl
? "dsub" : "sub",
3538 "d,v,t", dreg
, 0, sreg
);
3540 --mips_opts
.noreorder
;
3561 if (imm_expr
.X_op
== O_constant
3562 && imm_expr
.X_add_number
>= -0x8000
3563 && imm_expr
.X_add_number
< 0x8000)
3565 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3566 (int) BFD_RELOC_LO16
);
3569 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3570 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3589 if (imm_expr
.X_op
== O_constant
3590 && imm_expr
.X_add_number
>= 0
3591 && imm_expr
.X_add_number
< 0x10000)
3593 if (mask
!= M_NOR_I
)
3594 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3595 sreg
, (int) BFD_RELOC_LO16
);
3598 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3599 treg
, sreg
, (int) BFD_RELOC_LO16
);
3600 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3606 load_register (&icnt
, AT
, &imm_expr
, 0);
3607 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3624 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3626 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3630 load_register (&icnt
, AT
, &imm_expr
, 0);
3631 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3640 likely
? "bgezl" : "bgez",
3646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3647 likely
? "blezl" : "blez",
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3653 likely
? "beql" : "beq",
3660 /* check for > max integer */
3661 maxnum
= 0x7fffffff;
3662 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3669 if (imm_expr
.X_op
== O_constant
3670 && imm_expr
.X_add_number
>= maxnum
3671 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3674 /* result is always false */
3677 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3678 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3682 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3683 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3688 if (imm_expr
.X_op
!= O_constant
)
3689 as_bad (_("Unsupported large constant"));
3690 imm_expr
.X_add_number
++;
3694 if (mask
== M_BGEL_I
)
3696 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3698 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3699 likely
? "bgezl" : "bgez",
3703 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3706 likely
? "bgtzl" : "bgtz",
3710 maxnum
= 0x7fffffff;
3711 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3718 maxnum
= - maxnum
- 1;
3719 if (imm_expr
.X_op
== O_constant
3720 && imm_expr
.X_add_number
<= maxnum
3721 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3724 /* result is always true */
3725 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3729 set_at (&icnt
, sreg
, 0);
3730 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3731 likely
? "beql" : "beq",
3742 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3743 likely
? "beql" : "beq",
3747 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3749 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3750 likely
? "beql" : "beq",
3758 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3759 && imm_expr
.X_op
== O_constant
3760 && imm_expr
.X_add_number
== 0xffffffff))
3762 if (imm_expr
.X_op
!= O_constant
)
3763 as_bad (_("Unsupported large constant"));
3764 imm_expr
.X_add_number
++;
3768 if (mask
== M_BGEUL_I
)
3770 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3772 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3775 likely
? "bnel" : "bne",
3779 set_at (&icnt
, sreg
, 1);
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "beql" : "beq",
3790 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3791 likely
? "bgtzl" : "bgtz",
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3798 likely
? "bltzl" : "bltz",
3802 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 likely
? "bnel" : "bne",
3813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3814 likely
? "bnel" : "bne",
3820 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3822 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3823 likely
? "bnel" : "bne",
3832 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3833 likely
? "blezl" : "blez",
3839 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3840 likely
? "bgezl" : "bgez",
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3846 likely
? "beql" : "beq",
3853 maxnum
= 0x7fffffff;
3854 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3861 if (imm_expr
.X_op
== O_constant
3862 && imm_expr
.X_add_number
>= maxnum
3863 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3865 if (imm_expr
.X_op
!= O_constant
)
3866 as_bad (_("Unsupported large constant"));
3867 imm_expr
.X_add_number
++;
3871 if (mask
== M_BLTL_I
)
3873 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3875 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3876 likely
? "bltzl" : "bltz",
3880 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3882 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3883 likely
? "blezl" : "blez",
3887 set_at (&icnt
, sreg
, 0);
3888 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3889 likely
? "bnel" : "bne",
3898 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3899 likely
? "beql" : "beq",
3905 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3907 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3908 likely
? "beql" : "beq",
3916 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3917 && imm_expr
.X_op
== O_constant
3918 && imm_expr
.X_add_number
== 0xffffffff))
3920 if (imm_expr
.X_op
!= O_constant
)
3921 as_bad (_("Unsupported large constant"));
3922 imm_expr
.X_add_number
++;
3926 if (mask
== M_BLTUL_I
)
3928 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3930 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3933 likely
? "beql" : "beq",
3937 set_at (&icnt
, sreg
, 1);
3938 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3939 likely
? "bnel" : "bne",
3948 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3949 likely
? "bltzl" : "bltz",
3955 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3956 likely
? "bgtzl" : "bgtz",
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3961 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3962 likely
? "bnel" : "bne",
3973 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3974 likely
? "bnel" : "bne",
3978 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3980 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3981 likely
? "bnel" : "bne",
3997 as_warn (_("Divide by zero."));
3999 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4001 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4005 mips_emit_delays (true);
4006 ++mips_opts
.noreorder
;
4007 mips_any_noreorder
= 1;
4010 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4011 macro_build ((char *) NULL
, &icnt
, NULL
,
4012 dbl
? "ddiv" : "div",
4013 "z,s,t", sreg
, treg
);
4017 expr1
.X_add_number
= 8;
4018 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4019 macro_build ((char *) NULL
, &icnt
, NULL
,
4020 dbl
? "ddiv" : "div",
4021 "z,s,t", sreg
, treg
);
4022 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4024 expr1
.X_add_number
= -1;
4025 macro_build ((char *) NULL
, &icnt
, &expr1
,
4026 dbl
? "daddiu" : "addiu",
4027 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4028 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4029 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4032 expr1
.X_add_number
= 1;
4033 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4034 (int) BFD_RELOC_LO16
);
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4040 expr1
.X_add_number
= 0x80000000;
4041 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4042 (int) BFD_RELOC_HI16
);
4046 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4047 /* We want to close the noreorder block as soon as possible, so
4048 that later insns are available for delay slot filling. */
4049 --mips_opts
.noreorder
;
4053 expr1
.X_add_number
= 8;
4054 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4055 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4057 /* We want to close the noreorder block as soon as possible, so
4058 that later insns are available for delay slot filling. */
4059 --mips_opts
.noreorder
;
4061 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4063 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4102 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4104 as_warn (_("Divide by zero."));
4106 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4108 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4111 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4113 if (strcmp (s2
, "mflo") == 0)
4114 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4117 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4120 if (imm_expr
.X_op
== O_constant
4121 && imm_expr
.X_add_number
== -1
4122 && s
[strlen (s
) - 1] != 'u')
4124 if (strcmp (s2
, "mflo") == 0)
4127 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4130 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4134 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4138 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4139 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4140 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4159 mips_emit_delays (true);
4160 ++mips_opts
.noreorder
;
4161 mips_any_noreorder
= 1;
4164 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4165 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4166 /* We want to close the noreorder block as soon as possible, so
4167 that later insns are available for delay slot filling. */
4168 --mips_opts
.noreorder
;
4172 expr1
.X_add_number
= 8;
4173 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4174 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4176 /* We want to close the noreorder block as soon as possible, so
4177 that later insns are available for delay slot filling. */
4178 --mips_opts
.noreorder
;
4179 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4181 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4187 /* Load the address of a symbol into a register. If breg is not
4188 zero, we then add a base register to it. */
4190 /* When generating embedded PIC code, we permit expressions of
4193 where bar is an address in the current section. These are used
4194 when getting the addresses of functions. We don't permit
4195 X_add_number to be non-zero, because if the symbol is
4196 external the relaxing code needs to know that any addend is
4197 purely the offset to X_op_symbol. */
4198 if (mips_pic
== EMBEDDED_PIC
4199 && offset_expr
.X_op
== O_subtract
4200 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4201 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4202 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4204 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4208 && (offset_expr
.X_add_number
== 0
4209 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4212 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4213 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4214 ((bfd_arch_bits_per_address (stdoutput
) == 32
4215 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4216 ? "addiu" : "daddiu"),
4217 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4221 if (offset_expr
.X_op
!= O_symbol
4222 && offset_expr
.X_op
!= O_constant
)
4224 as_bad (_("expression too complex"));
4225 offset_expr
.X_op
= O_constant
;
4239 if (offset_expr
.X_op
== O_constant
)
4240 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4241 else if (mips_pic
== NO_PIC
)
4243 /* If this is a reference to an GP relative symbol, we want
4244 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4246 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4247 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4248 If we have a constant, we need two instructions anyhow,
4249 so we may as well always use the latter form. */
4250 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4251 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4256 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4257 ((bfd_arch_bits_per_address (stdoutput
) == 32
4258 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4259 ? "addiu" : "daddiu"),
4260 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4261 p
= frag_var (rs_machine_dependent
, 8, 0,
4262 RELAX_ENCODE (4, 8, 0, 4, 0,
4263 mips_opts
.warn_about_macros
),
4264 offset_expr
.X_add_symbol
, (offsetT
) 0,
4267 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4270 macro_build (p
, &icnt
, &offset_expr
,
4271 ((bfd_arch_bits_per_address (stdoutput
) == 32
4272 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4273 ? "addiu" : "daddiu"),
4274 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4276 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4278 /* If this is a reference to an external symbol, and there
4279 is no constant, we want
4280 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4281 For a local symbol, we want
4282 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4284 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4286 If we have a small constant, and this is a reference to
4287 an external symbol, we want
4288 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4290 addiu $tempreg,$tempreg,<constant>
4291 For a local symbol, we want the same instruction
4292 sequence, but we output a BFD_RELOC_LO16 reloc on the
4295 If we have a large constant, and this is a reference to
4296 an external symbol, we want
4297 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4298 lui $at,<hiconstant>
4299 addiu $at,$at,<loconstant>
4300 addu $tempreg,$tempreg,$at
4301 For a local symbol, we want the same instruction
4302 sequence, but we output a BFD_RELOC_LO16 reloc on the
4303 addiu instruction. */
4304 expr1
.X_add_number
= offset_expr
.X_add_number
;
4305 offset_expr
.X_add_number
= 0;
4307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4309 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4310 if (expr1
.X_add_number
== 0)
4318 /* We're going to put in an addu instruction using
4319 tempreg, so we may as well insert the nop right
4321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4325 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4326 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4328 ? mips_opts
.warn_about_macros
4330 offset_expr
.X_add_symbol
, (offsetT
) 0,
4334 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4337 macro_build (p
, &icnt
, &expr1
,
4338 ((bfd_arch_bits_per_address (stdoutput
) == 32
4339 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4340 ? "addiu" : "daddiu"),
4341 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4342 /* FIXME: If breg == 0, and the next instruction uses
4343 $tempreg, then if this variant case is used an extra
4344 nop will be generated. */
4346 else if (expr1
.X_add_number
>= -0x8000
4347 && expr1
.X_add_number
< 0x8000)
4349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4351 macro_build ((char *) NULL
, &icnt
, &expr1
,
4352 ((bfd_arch_bits_per_address (stdoutput
) == 32
4353 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4354 ? "addiu" : "daddiu"),
4355 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4356 (void) frag_var (rs_machine_dependent
, 0, 0,
4357 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4358 offset_expr
.X_add_symbol
, (offsetT
) 0,
4365 /* If we are going to add in a base register, and the
4366 target register and the base register are the same,
4367 then we are using AT as a temporary register. Since
4368 we want to load the constant into AT, we add our
4369 current AT (from the global offset table) and the
4370 register into the register now, and pretend we were
4371 not using a base register. */
4376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4379 ((bfd_arch_bits_per_address (stdoutput
) == 32
4380 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4381 ? "addu" : "daddu"),
4382 "d,v,t", treg
, AT
, breg
);
4388 /* Set mips_optimize around the lui instruction to avoid
4389 inserting an unnecessary nop after the lw. */
4390 hold_mips_optimize
= mips_optimize
;
4392 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4393 mips_optimize
= hold_mips_optimize
;
4395 macro_build ((char *) NULL
, &icnt
, &expr1
,
4396 ((bfd_arch_bits_per_address (stdoutput
) == 32
4397 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4398 ? "addiu" : "daddiu"),
4399 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4401 ((bfd_arch_bits_per_address (stdoutput
) == 32
4402 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4403 ? "addu" : "daddu"),
4404 "d,v,t", tempreg
, tempreg
, AT
);
4405 (void) frag_var (rs_machine_dependent
, 0, 0,
4406 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4407 offset_expr
.X_add_symbol
, (offsetT
) 0,
4412 else if (mips_pic
== SVR4_PIC
)
4416 /* This is the large GOT case. If this is a reference to an
4417 external symbol, and there is no constant, we want
4418 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4419 addu $tempreg,$tempreg,$gp
4420 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4421 For a local symbol, we want
4422 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4424 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4426 If we have a small constant, and this is a reference to
4427 an external symbol, we want
4428 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4429 addu $tempreg,$tempreg,$gp
4430 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4432 addiu $tempreg,$tempreg,<constant>
4433 For a local symbol, we want
4434 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4436 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4438 If we have a large constant, and this is a reference to
4439 an external symbol, we want
4440 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4441 addu $tempreg,$tempreg,$gp
4442 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4443 lui $at,<hiconstant>
4444 addiu $at,$at,<loconstant>
4445 addu $tempreg,$tempreg,$at
4446 For a local symbol, we want
4447 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4448 lui $at,<hiconstant>
4449 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4450 addu $tempreg,$tempreg,$at
4452 expr1
.X_add_number
= offset_expr
.X_add_number
;
4453 offset_expr
.X_add_number
= 0;
4455 if (reg_needs_delay (GP
))
4459 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4460 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4461 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4462 ((bfd_arch_bits_per_address (stdoutput
) == 32
4463 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4464 ? "addu" : "daddu"),
4465 "d,v,t", tempreg
, tempreg
, GP
);
4466 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4468 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4470 if (expr1
.X_add_number
== 0)
4478 /* We're going to put in an addu instruction using
4479 tempreg, so we may as well insert the nop right
4481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4486 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4487 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4490 ? mips_opts
.warn_about_macros
4492 offset_expr
.X_add_symbol
, (offsetT
) 0,
4495 else if (expr1
.X_add_number
>= -0x8000
4496 && expr1
.X_add_number
< 0x8000)
4498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4500 macro_build ((char *) NULL
, &icnt
, &expr1
,
4501 ((bfd_arch_bits_per_address (stdoutput
) == 32
4502 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4503 ? "addiu" : "daddiu"),
4504 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4506 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4507 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4509 ? mips_opts
.warn_about_macros
4511 offset_expr
.X_add_symbol
, (offsetT
) 0,
4518 /* If we are going to add in a base register, and the
4519 target register and the base register are the same,
4520 then we are using AT as a temporary register. Since
4521 we want to load the constant into AT, we add our
4522 current AT (from the global offset table) and the
4523 register into the register now, and pretend we were
4524 not using a base register. */
4532 assert (tempreg
== AT
);
4533 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4536 ((bfd_arch_bits_per_address (stdoutput
) == 32
4537 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4538 ? "addu" : "daddu"),
4539 "d,v,t", treg
, AT
, breg
);
4544 /* Set mips_optimize around the lui instruction to avoid
4545 inserting an unnecessary nop after the lw. */
4546 hold_mips_optimize
= mips_optimize
;
4548 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4549 mips_optimize
= hold_mips_optimize
;
4551 macro_build ((char *) NULL
, &icnt
, &expr1
,
4552 ((bfd_arch_bits_per_address (stdoutput
) == 32
4553 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4554 ? "addiu" : "daddiu"),
4555 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4556 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4557 ((bfd_arch_bits_per_address (stdoutput
) == 32
4558 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4559 ? "addu" : "daddu"),
4560 "d,v,t", dreg
, dreg
, AT
);
4562 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4563 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4566 ? mips_opts
.warn_about_macros
4568 offset_expr
.X_add_symbol
, (offsetT
) 0,
4576 /* This is needed because this instruction uses $gp, but
4577 the first instruction on the main stream does not. */
4578 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4581 macro_build (p
, &icnt
, &offset_expr
,
4583 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4585 if (expr1
.X_add_number
>= -0x8000
4586 && expr1
.X_add_number
< 0x8000)
4588 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4590 macro_build (p
, &icnt
, &expr1
,
4591 ((bfd_arch_bits_per_address (stdoutput
) == 32
4592 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4593 ? "addiu" : "daddiu"),
4594 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4595 /* FIXME: If add_number is 0, and there was no base
4596 register, the external symbol case ended with a load,
4597 so if the symbol turns out to not be external, and
4598 the next instruction uses tempreg, an unnecessary nop
4599 will be inserted. */
4605 /* We must add in the base register now, as in the
4606 external symbol case. */
4607 assert (tempreg
== AT
);
4608 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4610 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4611 ((bfd_arch_bits_per_address (stdoutput
) == 32
4612 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4613 ? "addu" : "daddu"),
4614 "d,v,t", treg
, AT
, breg
);
4617 /* We set breg to 0 because we have arranged to add
4618 it in in both cases. */
4622 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4624 macro_build (p
, &icnt
, &expr1
,
4625 ((bfd_arch_bits_per_address (stdoutput
) == 32
4626 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4627 ? "addiu" : "daddiu"),
4628 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4630 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4631 ((bfd_arch_bits_per_address (stdoutput
) == 32
4632 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4633 ? "addu" : "daddu"),
4634 "d,v,t", tempreg
, tempreg
, AT
);
4638 else if (mips_pic
== EMBEDDED_PIC
)
4641 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4643 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4644 ((bfd_arch_bits_per_address (stdoutput
) == 32
4645 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4646 ? "addiu" : "daddiu"),
4647 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4654 ((bfd_arch_bits_per_address (stdoutput
) == 32
4655 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4656 ? "addu" : "daddu"),
4657 "d,v,t", treg
, tempreg
, breg
);
4665 /* The j instruction may not be used in PIC code, since it
4666 requires an absolute address. We convert it to a b
4668 if (mips_pic
== NO_PIC
)
4669 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4674 /* The jal instructions must be handled as macros because when
4675 generating PIC code they expand to multi-instruction
4676 sequences. Normally they are simple instructions. */
4681 if (mips_pic
== NO_PIC
4682 || mips_pic
== EMBEDDED_PIC
)
4683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4685 else if (mips_pic
== SVR4_PIC
)
4687 if (sreg
!= PIC_CALL_REG
)
4688 as_warn (_("MIPS PIC call to register other than $25"));
4690 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4692 if (mips_cprestore_offset
< 0)
4693 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4696 expr1
.X_add_number
= mips_cprestore_offset
;
4697 macro_build ((char *) NULL
, &icnt
, &expr1
,
4698 ((bfd_arch_bits_per_address (stdoutput
) == 32
4699 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4701 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4710 if (mips_pic
== NO_PIC
)
4711 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4712 else if (mips_pic
== SVR4_PIC
)
4714 /* If this is a reference to an external symbol, and we are
4715 using a small GOT, we want
4716 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4720 lw $gp,cprestore($sp)
4721 The cprestore value is set using the .cprestore
4722 pseudo-op. If we are using a big GOT, we want
4723 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4725 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4729 lw $gp,cprestore($sp)
4730 If the symbol is not external, we want
4731 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4733 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4736 lw $gp,cprestore($sp) */
4740 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4741 ((bfd_arch_bits_per_address (stdoutput
) == 32
4742 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4744 "t,o(b)", PIC_CALL_REG
,
4745 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4746 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4748 p
= frag_var (rs_machine_dependent
, 4, 0,
4749 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4750 offset_expr
.X_add_symbol
, (offsetT
) 0,
4757 if (reg_needs_delay (GP
))
4761 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4762 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4764 ((bfd_arch_bits_per_address (stdoutput
) == 32
4765 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4766 ? "addu" : "daddu"),
4767 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4768 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4769 ((bfd_arch_bits_per_address (stdoutput
) == 32
4770 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4772 "t,o(b)", PIC_CALL_REG
,
4773 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4776 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4777 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4779 offset_expr
.X_add_symbol
, (offsetT
) 0,
4783 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4786 macro_build (p
, &icnt
, &offset_expr
,
4787 ((bfd_arch_bits_per_address (stdoutput
) == 32
4788 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4790 "t,o(b)", PIC_CALL_REG
,
4791 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4793 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4796 macro_build (p
, &icnt
, &offset_expr
,
4797 ((bfd_arch_bits_per_address (stdoutput
) == 32
4798 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4799 ? "addiu" : "daddiu"),
4800 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4801 (int) BFD_RELOC_LO16
);
4802 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4803 "jalr", "s", PIC_CALL_REG
);
4804 if (mips_cprestore_offset
< 0)
4805 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4808 if (mips_opts
.noreorder
)
4809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4811 expr1
.X_add_number
= mips_cprestore_offset
;
4812 macro_build ((char *) NULL
, &icnt
, &expr1
,
4813 ((bfd_arch_bits_per_address (stdoutput
) == 32
4814 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4816 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4820 else if (mips_pic
== EMBEDDED_PIC
)
4822 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4823 /* The linker may expand the call to a longer sequence which
4824 uses $at, so we must break rather than return. */
4849 /* Itbl support may require additional care here. */
4854 /* Itbl support may require additional care here. */
4859 /* Itbl support may require additional care here. */
4864 /* Itbl support may require additional care here. */
4876 if (mips_cpu
== CPU_R4650
)
4878 as_bad (_("opcode not supported on this processor"));
4882 /* Itbl support may require additional care here. */
4887 /* Itbl support may require additional care here. */
4892 /* Itbl support may require additional care here. */
4912 if (breg
== treg
|| coproc
|| lr
)
4934 /* Itbl support may require additional care here. */
4939 /* Itbl support may require additional care here. */
4944 /* Itbl support may require additional care here. */
4949 /* Itbl support may require additional care here. */
4965 if (mips_cpu
== CPU_R4650
)
4967 as_bad (_("opcode not supported on this processor"));
4972 /* Itbl support may require additional care here. */
4976 /* Itbl support may require additional care here. */
4981 /* Itbl support may require additional care here. */
4993 /* Itbl support may require additional care here. */
4994 if (mask
== M_LWC1_AB
4995 || mask
== M_SWC1_AB
4996 || mask
== M_LDC1_AB
4997 || mask
== M_SDC1_AB
5006 if (offset_expr
.X_op
!= O_constant
5007 && offset_expr
.X_op
!= O_symbol
)
5009 as_bad (_("expression too complex"));
5010 offset_expr
.X_op
= O_constant
;
5013 /* A constant expression in PIC code can be handled just as it
5014 is in non PIC code. */
5015 if (mips_pic
== NO_PIC
5016 || offset_expr
.X_op
== O_constant
)
5018 /* If this is a reference to a GP relative symbol, and there
5019 is no base register, we want
5020 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5021 Otherwise, if there is no base register, we want
5022 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5023 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5024 If we have a constant, we need two instructions anyhow,
5025 so we always use the latter form.
5027 If we have a base register, and this is a reference to a
5028 GP relative symbol, we want
5029 addu $tempreg,$breg,$gp
5030 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5032 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5033 addu $tempreg,$tempreg,$breg
5034 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5035 With a constant we always use the latter case. */
5038 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5039 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5044 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5045 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5046 p
= frag_var (rs_machine_dependent
, 8, 0,
5047 RELAX_ENCODE (4, 8, 0, 4, 0,
5048 (mips_opts
.warn_about_macros
5050 && mips_opts
.noat
))),
5051 offset_expr
.X_add_symbol
, (offsetT
) 0,
5055 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5058 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5059 (int) BFD_RELOC_LO16
, tempreg
);
5063 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5064 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5069 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5070 ((bfd_arch_bits_per_address (stdoutput
) == 32
5071 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5072 ? "addu" : "daddu"),
5073 "d,v,t", tempreg
, breg
, GP
);
5074 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5075 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5076 p
= frag_var (rs_machine_dependent
, 12, 0,
5077 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5078 offset_expr
.X_add_symbol
, (offsetT
) 0,
5081 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5084 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5085 ((bfd_arch_bits_per_address (stdoutput
) == 32
5086 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5087 ? "addu" : "daddu"),
5088 "d,v,t", tempreg
, tempreg
, breg
);
5091 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5092 (int) BFD_RELOC_LO16
, tempreg
);
5095 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5097 /* If this is a reference to an external symbol, we want
5098 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5100 <op> $treg,0($tempreg)
5102 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5104 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5105 <op> $treg,0($tempreg)
5106 If there is a base register, we add it to $tempreg before
5107 the <op>. If there is a constant, we stick it in the
5108 <op> instruction. We don't handle constants larger than
5109 16 bits, because we have no way to load the upper 16 bits
5110 (actually, we could handle them for the subset of cases
5111 in which we are not using $at). */
5112 assert (offset_expr
.X_op
== O_symbol
);
5113 expr1
.X_add_number
= offset_expr
.X_add_number
;
5114 offset_expr
.X_add_number
= 0;
5115 if (expr1
.X_add_number
< -0x8000
5116 || expr1
.X_add_number
>= 0x8000)
5117 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5119 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5120 ((bfd_arch_bits_per_address (stdoutput
) == 32
5121 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5123 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5124 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5125 p
= frag_var (rs_machine_dependent
, 4, 0,
5126 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5127 offset_expr
.X_add_symbol
, (offsetT
) 0,
5129 macro_build (p
, &icnt
, &offset_expr
,
5130 ((bfd_arch_bits_per_address (stdoutput
) == 32
5131 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5132 ? "addiu" : "daddiu"),
5133 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5135 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5136 ((bfd_arch_bits_per_address (stdoutput
) == 32
5137 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5138 ? "addu" : "daddu"),
5139 "d,v,t", tempreg
, tempreg
, breg
);
5140 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5141 (int) BFD_RELOC_LO16
, tempreg
);
5143 else if (mips_pic
== SVR4_PIC
)
5147 /* If this is a reference to an external symbol, we want
5148 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5149 addu $tempreg,$tempreg,$gp
5150 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5151 <op> $treg,0($tempreg)
5153 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5155 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5156 <op> $treg,0($tempreg)
5157 If there is a base register, we add it to $tempreg before
5158 the <op>. If there is a constant, we stick it in the
5159 <op> instruction. We don't handle constants larger than
5160 16 bits, because we have no way to load the upper 16 bits
5161 (actually, we could handle them for the subset of cases
5162 in which we are not using $at). */
5163 assert (offset_expr
.X_op
== O_symbol
);
5164 expr1
.X_add_number
= offset_expr
.X_add_number
;
5165 offset_expr
.X_add_number
= 0;
5166 if (expr1
.X_add_number
< -0x8000
5167 || expr1
.X_add_number
>= 0x8000)
5168 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5169 if (reg_needs_delay (GP
))
5174 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5175 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5177 ((bfd_arch_bits_per_address (stdoutput
) == 32
5178 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5179 ? "addu" : "daddu"),
5180 "d,v,t", tempreg
, tempreg
, GP
);
5181 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5182 ((bfd_arch_bits_per_address (stdoutput
) == 32
5183 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5185 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5187 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5188 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5189 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5192 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5195 macro_build (p
, &icnt
, &offset_expr
,
5196 ((bfd_arch_bits_per_address (stdoutput
) == 32
5197 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5199 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5201 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5203 macro_build (p
, &icnt
, &offset_expr
,
5204 ((bfd_arch_bits_per_address (stdoutput
) == 32
5205 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5206 ? "addiu" : "daddiu"),
5207 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5209 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5210 ((bfd_arch_bits_per_address (stdoutput
) == 32
5211 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5212 ? "addu" : "daddu"),
5213 "d,v,t", tempreg
, tempreg
, breg
);
5214 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5215 (int) BFD_RELOC_LO16
, tempreg
);
5217 else if (mips_pic
== EMBEDDED_PIC
)
5219 /* If there is no base register, we want
5220 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5221 If there is a base register, we want
5222 addu $tempreg,$breg,$gp
5223 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5225 assert (offset_expr
.X_op
== O_symbol
);
5228 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5229 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5234 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5235 ((bfd_arch_bits_per_address (stdoutput
) == 32
5236 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5237 ? "addu" : "daddu"),
5238 "d,v,t", tempreg
, breg
, GP
);
5239 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5240 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5253 load_register (&icnt
, treg
, &imm_expr
, 0);
5257 load_register (&icnt
, treg
, &imm_expr
, 1);
5261 if (imm_expr
.X_op
== O_constant
)
5263 load_register (&icnt
, AT
, &imm_expr
, 0);
5264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5265 "mtc1", "t,G", AT
, treg
);
5270 assert (offset_expr
.X_op
== O_symbol
5271 && strcmp (segment_name (S_GET_SEGMENT
5272 (offset_expr
.X_add_symbol
)),
5274 && offset_expr
.X_add_number
== 0);
5275 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5276 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5281 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5282 the entire value, and in mips1 mode it is the high order 32
5283 bits of the value and the low order 32 bits are either zero
5284 or in offset_expr. */
5285 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5287 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5288 load_register (&icnt
, treg
, &imm_expr
, 1);
5293 if (target_big_endian
)
5305 load_register (&icnt
, hreg
, &imm_expr
, 0);
5308 if (offset_expr
.X_op
== O_absent
)
5309 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5313 assert (offset_expr
.X_op
== O_constant
);
5314 load_register (&icnt
, lreg
, &offset_expr
, 0);
5321 /* We know that sym is in the .rdata section. First we get the
5322 upper 16 bits of the address. */
5323 if (mips_pic
== NO_PIC
)
5325 /* FIXME: This won't work for a 64 bit address. */
5326 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5328 else if (mips_pic
== SVR4_PIC
)
5330 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5331 ((bfd_arch_bits_per_address (stdoutput
) == 32
5332 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5334 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5336 else if (mips_pic
== EMBEDDED_PIC
)
5338 /* For embedded PIC we pick up the entire address off $gp in
5339 a single instruction. */
5340 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5341 ((bfd_arch_bits_per_address (stdoutput
) == 32
5342 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5343 ? "addiu" : "daddiu"),
5344 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5345 offset_expr
.X_op
= O_constant
;
5346 offset_expr
.X_add_number
= 0;
5351 /* Now we load the register(s). */
5352 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5354 treg
, (int) BFD_RELOC_LO16
, AT
);
5357 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5358 treg
, (int) BFD_RELOC_LO16
, AT
);
5361 /* FIXME: How in the world do we deal with the possible
5363 offset_expr
.X_add_number
+= 4;
5364 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5365 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5369 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5370 does not become a variant frag. */
5371 frag_wane (frag_now
);
5377 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5378 the entire value, and in mips1 mode it is the high order 32
5379 bits of the value and the low order 32 bits are either zero
5380 or in offset_expr. */
5381 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5383 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5384 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5386 "dmtc1", "t,S", AT
, treg
);
5389 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5390 "mtc1", "t,G", AT
, treg
+ 1);
5391 if (offset_expr
.X_op
== O_absent
)
5392 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5393 "mtc1", "t,G", 0, treg
);
5396 assert (offset_expr
.X_op
== O_constant
);
5397 load_register (&icnt
, AT
, &offset_expr
, 0);
5398 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5399 "mtc1", "t,G", AT
, treg
);
5405 assert (offset_expr
.X_op
== O_symbol
5406 && offset_expr
.X_add_number
== 0);
5407 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5408 if (strcmp (s
, ".lit8") == 0)
5410 if (mips_opts
.isa
!= 1)
5412 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5413 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5417 r
= BFD_RELOC_MIPS_LITERAL
;
5422 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5423 if (mips_pic
== SVR4_PIC
)
5424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5425 ((bfd_arch_bits_per_address (stdoutput
) == 32
5426 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5428 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5431 /* FIXME: This won't work for a 64 bit address. */
5432 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5435 if (mips_opts
.isa
!= 1)
5437 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5438 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5440 /* To avoid confusion in tc_gen_reloc, we must ensure
5441 that this does not become a variant frag. */
5442 frag_wane (frag_now
);
5453 if (mips_cpu
== CPU_R4650
)
5455 as_bad (_("opcode not supported on this processor"));
5458 /* Even on a big endian machine $fn comes before $fn+1. We have
5459 to adjust when loading from memory. */
5462 assert (mips_opts
.isa
== 1);
5463 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5464 target_big_endian
? treg
+ 1 : treg
,
5466 /* FIXME: A possible overflow which I don't know how to deal
5468 offset_expr
.X_add_number
+= 4;
5469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5470 target_big_endian
? treg
: treg
+ 1,
5473 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5474 does not become a variant frag. */
5475 frag_wane (frag_now
);
5484 * The MIPS assembler seems to check for X_add_number not
5485 * being double aligned and generating:
5488 * addiu at,at,%lo(foo+1)
5491 * But, the resulting address is the same after relocation so why
5492 * generate the extra instruction?
5494 if (mips_cpu
== CPU_R4650
)
5496 as_bad (_("opcode not supported on this processor"));
5499 /* Itbl support may require additional care here. */
5501 if (mips_opts
.isa
!= 1)
5512 if (mips_cpu
== CPU_R4650
)
5514 as_bad (_("opcode not supported on this processor"));
5518 if (mips_opts
.isa
!= 1)
5526 /* Itbl support may require additional care here. */
5531 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5542 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5552 if (offset_expr
.X_op
!= O_symbol
5553 && offset_expr
.X_op
!= O_constant
)
5555 as_bad (_("expression too complex"));
5556 offset_expr
.X_op
= O_constant
;
5559 /* Even on a big endian machine $fn comes before $fn+1. We have
5560 to adjust when loading from memory. We set coproc if we must
5561 load $fn+1 first. */
5562 /* Itbl support may require additional care here. */
5563 if (! target_big_endian
)
5566 if (mips_pic
== NO_PIC
5567 || offset_expr
.X_op
== O_constant
)
5569 /* If this is a reference to a GP relative symbol, we want
5570 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5571 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5572 If we have a base register, we use this
5574 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5575 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5576 If this is not a GP relative symbol, we want
5577 lui $at,<sym> (BFD_RELOC_HI16_S)
5578 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5579 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5580 If there is a base register, we add it to $at after the
5581 lui instruction. If there is a constant, we always use
5583 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5584 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5604 ((bfd_arch_bits_per_address (stdoutput
) == 32
5605 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5606 ? "addu" : "daddu"),
5607 "d,v,t", AT
, breg
, GP
);
5613 /* Itbl support may require additional care here. */
5614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5615 coproc
? treg
+ 1 : treg
,
5616 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5617 offset_expr
.X_add_number
+= 4;
5619 /* Set mips_optimize to 2 to avoid inserting an
5621 hold_mips_optimize
= mips_optimize
;
5623 /* Itbl support may require additional care here. */
5624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5625 coproc
? treg
: treg
+ 1,
5626 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5627 mips_optimize
= hold_mips_optimize
;
5629 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5630 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5631 used_at
&& mips_opts
.noat
),
5632 offset_expr
.X_add_symbol
, (offsetT
) 0,
5635 /* We just generated two relocs. When tc_gen_reloc
5636 handles this case, it will skip the first reloc and
5637 handle the second. The second reloc already has an
5638 extra addend of 4, which we added above. We must
5639 subtract it out, and then subtract another 4 to make
5640 the first reloc come out right. The second reloc
5641 will come out right because we are going to add 4 to
5642 offset_expr when we build its instruction below.
5644 If we have a symbol, then we don't want to include
5645 the offset, because it will wind up being included
5646 when we generate the reloc. */
5648 if (offset_expr
.X_op
== O_constant
)
5649 offset_expr
.X_add_number
-= 8;
5652 offset_expr
.X_add_number
= -4;
5653 offset_expr
.X_op
= O_constant
;
5656 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5661 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5662 ((bfd_arch_bits_per_address (stdoutput
) == 32
5663 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5664 ? "addu" : "daddu"),
5665 "d,v,t", AT
, breg
, AT
);
5669 /* Itbl support may require additional care here. */
5670 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5671 coproc
? treg
+ 1 : treg
,
5672 (int) BFD_RELOC_LO16
, AT
);
5675 /* FIXME: How do we handle overflow here? */
5676 offset_expr
.X_add_number
+= 4;
5677 /* Itbl support may require additional care here. */
5678 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5679 coproc
? treg
: treg
+ 1,
5680 (int) BFD_RELOC_LO16
, AT
);
5682 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5686 /* If this is a reference to an external symbol, we want
5687 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5692 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5694 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5695 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5696 If there is a base register we add it to $at before the
5697 lwc1 instructions. If there is a constant we include it
5698 in the lwc1 instructions. */
5700 expr1
.X_add_number
= offset_expr
.X_add_number
;
5701 offset_expr
.X_add_number
= 0;
5702 if (expr1
.X_add_number
< -0x8000
5703 || expr1
.X_add_number
>= 0x8000 - 4)
5704 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5709 frag_grow (24 + off
);
5710 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5711 ((bfd_arch_bits_per_address (stdoutput
) == 32
5712 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5714 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5718 ((bfd_arch_bits_per_address (stdoutput
) == 32
5719 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5720 ? "addu" : "daddu"),
5721 "d,v,t", AT
, breg
, AT
);
5722 /* Itbl support may require additional care here. */
5723 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5724 coproc
? treg
+ 1 : treg
,
5725 (int) BFD_RELOC_LO16
, AT
);
5726 expr1
.X_add_number
+= 4;
5728 /* Set mips_optimize to 2 to avoid inserting an undesired
5730 hold_mips_optimize
= mips_optimize
;
5732 /* Itbl support may require additional care here. */
5733 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5734 coproc
? treg
: treg
+ 1,
5735 (int) BFD_RELOC_LO16
, AT
);
5736 mips_optimize
= hold_mips_optimize
;
5738 (void) frag_var (rs_machine_dependent
, 0, 0,
5739 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5740 offset_expr
.X_add_symbol
, (offsetT
) 0,
5743 else if (mips_pic
== SVR4_PIC
)
5747 /* If this is a reference to an external symbol, we want
5748 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5750 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5755 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5757 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5758 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5759 If there is a base register we add it to $at before the
5760 lwc1 instructions. If there is a constant we include it
5761 in the lwc1 instructions. */
5763 expr1
.X_add_number
= offset_expr
.X_add_number
;
5764 offset_expr
.X_add_number
= 0;
5765 if (expr1
.X_add_number
< -0x8000
5766 || expr1
.X_add_number
>= 0x8000 - 4)
5767 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5768 if (reg_needs_delay (GP
))
5777 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5778 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5779 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5780 ((bfd_arch_bits_per_address (stdoutput
) == 32
5781 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5782 ? "addu" : "daddu"),
5783 "d,v,t", AT
, AT
, GP
);
5784 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5785 ((bfd_arch_bits_per_address (stdoutput
) == 32
5786 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5788 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5789 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5792 ((bfd_arch_bits_per_address (stdoutput
) == 32
5793 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5794 ? "addu" : "daddu"),
5795 "d,v,t", AT
, breg
, AT
);
5796 /* Itbl support may require additional care here. */
5797 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5798 coproc
? treg
+ 1 : treg
,
5799 (int) BFD_RELOC_LO16
, AT
);
5800 expr1
.X_add_number
+= 4;
5802 /* Set mips_optimize to 2 to avoid inserting an undesired
5804 hold_mips_optimize
= mips_optimize
;
5806 /* Itbl support may require additional care here. */
5807 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5808 coproc
? treg
: treg
+ 1,
5809 (int) BFD_RELOC_LO16
, AT
);
5810 mips_optimize
= hold_mips_optimize
;
5811 expr1
.X_add_number
-= 4;
5813 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5814 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5815 8 + gpdel
+ off
, 1, 0),
5816 offset_expr
.X_add_symbol
, (offsetT
) 0,
5820 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5823 macro_build (p
, &icnt
, &offset_expr
,
5824 ((bfd_arch_bits_per_address (stdoutput
) == 32
5825 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5827 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5829 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5833 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5834 ((bfd_arch_bits_per_address (stdoutput
) == 32
5835 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5836 ? "addu" : "daddu"),
5837 "d,v,t", AT
, breg
, AT
);
5840 /* Itbl support may require additional care here. */
5841 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5842 coproc
? treg
+ 1 : treg
,
5843 (int) BFD_RELOC_LO16
, AT
);
5845 expr1
.X_add_number
+= 4;
5847 /* Set mips_optimize to 2 to avoid inserting an undesired
5849 hold_mips_optimize
= mips_optimize
;
5851 /* Itbl support may require additional care here. */
5852 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5853 coproc
? treg
: treg
+ 1,
5854 (int) BFD_RELOC_LO16
, AT
);
5855 mips_optimize
= hold_mips_optimize
;
5857 else if (mips_pic
== EMBEDDED_PIC
)
5859 /* If there is no base register, we use
5860 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5861 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5862 If we have a base register, we use
5864 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5865 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5875 ((bfd_arch_bits_per_address (stdoutput
) == 32
5876 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5877 ? "addu" : "daddu"),
5878 "d,v,t", AT
, breg
, GP
);
5883 /* Itbl support may require additional care here. */
5884 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5885 coproc
? treg
+ 1 : treg
,
5886 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5887 offset_expr
.X_add_number
+= 4;
5888 /* Itbl support may require additional care here. */
5889 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5890 coproc
? treg
: treg
+ 1,
5891 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5907 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5908 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5909 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5910 (int) BFD_RELOC_LO16
, breg
);
5911 offset_expr
.X_add_number
+= 4;
5912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5913 (int) BFD_RELOC_LO16
, breg
);
5916 /* New code added to support COPZ instructions.
5917 This code builds table entries out of the macros in mip_opcodes.
5918 R4000 uses interlocks to handle coproc delays.
5919 Other chips (like the R3000) require nops to be inserted for delays.
5921 FIXME: Currently, we require that the user handle delays.
5922 In order to fill delay slots for non-interlocked chips,
5923 we must have a way to specify delays based on the coprocessor.
5924 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5925 What are the side-effects of the cop instruction?
5926 What cache support might we have and what are its effects?
5927 Both coprocessor & memory require delays. how long???
5928 What registers are read/set/modified?
5930 If an itbl is provided to interpret cop instructions,
5931 this knowledge can be encoded in the itbl spec. */
5945 /* For now we just do C (same as Cz). The parameter will be
5946 stored in insn_opcode by mips_ip. */
5947 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5951 #ifdef LOSING_COMPILER
5953 /* Try and see if this is a new itbl instruction.
5954 This code builds table entries out of the macros in mip_opcodes.
5955 FIXME: For now we just assemble the expression and pass it's
5956 value along as a 32-bit immediate.
5957 We may want to have the assembler assemble this value,
5958 so that we gain the assembler's knowledge of delay slots,
5960 Would it be more efficient to use mask (id) here? */
5961 if (itbl_have_entries
5962 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5964 s
= ip
->insn_mo
->name
;
5966 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5967 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5974 as_warn (_("Macro used $at after \".set noat\""));
5979 struct mips_cl_insn
*ip
;
5981 register int treg
, sreg
, dreg
, breg
;
5997 bfd_reloc_code_real_type r
;
6000 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6001 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6002 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6003 mask
= ip
->insn_mo
->mask
;
6005 expr1
.X_op
= O_constant
;
6006 expr1
.X_op_symbol
= NULL
;
6007 expr1
.X_add_symbol
= NULL
;
6008 expr1
.X_add_number
= 1;
6012 #endif /* LOSING_COMPILER */
6017 macro_build ((char *) NULL
, &icnt
, NULL
,
6018 dbl
? "dmultu" : "multu",
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6026 /* The MIPS assembler some times generates shifts and adds. I'm
6027 not trying to be that fancy. GCC should do this for us
6029 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6030 macro_build ((char *) NULL
, &icnt
, NULL
,
6031 dbl
? "dmult" : "mult",
6033 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6046 mips_emit_delays (true);
6047 ++mips_opts
.noreorder
;
6048 mips_any_noreorder
= 1;
6050 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6051 macro_build ((char *) NULL
, &icnt
, NULL
,
6052 dbl
? "dmult" : "mult",
6053 "s,t", sreg
, imm
? AT
: treg
);
6054 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6055 macro_build ((char *) NULL
, &icnt
, NULL
,
6056 dbl
? "dsra32" : "sra",
6057 "d,w,<", dreg
, dreg
, 31);
6058 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6060 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6063 expr1
.X_add_number
= 8;
6064 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6068 --mips_opts
.noreorder
;
6069 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6082 mips_emit_delays (true);
6083 ++mips_opts
.noreorder
;
6084 mips_any_noreorder
= 1;
6086 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6087 macro_build ((char *) NULL
, &icnt
, NULL
,
6088 dbl
? "dmultu" : "multu",
6089 "s,t", sreg
, imm
? AT
: treg
);
6090 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6093 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6096 expr1
.X_add_number
= 8;
6097 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6098 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6099 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6101 --mips_opts
.noreorder
;
6105 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6106 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6107 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6109 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6113 if (imm_expr
.X_op
!= O_constant
)
6114 as_bad (_("rotate count too large"));
6115 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6116 (int) (imm_expr
.X_add_number
& 0x1f));
6117 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6118 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6119 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6123 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6124 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6125 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6127 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6131 if (imm_expr
.X_op
!= O_constant
)
6132 as_bad (_("rotate count too large"));
6133 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6134 (int) (imm_expr
.X_add_number
& 0x1f));
6135 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6136 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6137 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6141 if (mips_cpu
== CPU_R4650
)
6143 as_bad (_("opcode not supported on this processor"));
6146 assert (mips_opts
.isa
== 1);
6147 /* Even on a big endian machine $fn comes before $fn+1. We have
6148 to adjust when storing to memory. */
6149 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6150 target_big_endian
? treg
+ 1 : treg
,
6151 (int) BFD_RELOC_LO16
, breg
);
6152 offset_expr
.X_add_number
+= 4;
6153 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6154 target_big_endian
? treg
: treg
+ 1,
6155 (int) BFD_RELOC_LO16
, breg
);
6160 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6161 treg
, (int) BFD_RELOC_LO16
);
6163 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6164 sreg
, (int) BFD_RELOC_LO16
);
6167 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6169 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6170 dreg
, (int) BFD_RELOC_LO16
);
6175 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6177 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6178 sreg
, (int) BFD_RELOC_LO16
);
6183 as_warn (_("Instruction %s: result is always false"),
6185 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6188 if (imm_expr
.X_op
== O_constant
6189 && imm_expr
.X_add_number
>= 0
6190 && imm_expr
.X_add_number
< 0x10000)
6192 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6193 sreg
, (int) BFD_RELOC_LO16
);
6196 else if (imm_expr
.X_op
== O_constant
6197 && imm_expr
.X_add_number
> -0x8000
6198 && imm_expr
.X_add_number
< 0)
6200 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6201 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6202 ((bfd_arch_bits_per_address (stdoutput
) == 32
6203 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6204 ? "addiu" : "daddiu"),
6205 "t,r,j", dreg
, sreg
,
6206 (int) BFD_RELOC_LO16
);
6211 load_register (&icnt
, AT
, &imm_expr
, 0);
6212 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6216 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6217 (int) BFD_RELOC_LO16
);
6222 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6228 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6229 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6230 (int) BFD_RELOC_LO16
);
6233 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6235 if (imm_expr
.X_op
== O_constant
6236 && imm_expr
.X_add_number
>= -0x8000
6237 && imm_expr
.X_add_number
< 0x8000)
6239 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6240 mask
== M_SGE_I
? "slti" : "sltiu",
6241 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6246 load_register (&icnt
, AT
, &imm_expr
, 0);
6247 macro_build ((char *) NULL
, &icnt
, NULL
,
6248 mask
== M_SGE_I
? "slt" : "sltu",
6249 "d,v,t", dreg
, sreg
, AT
);
6252 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6253 (int) BFD_RELOC_LO16
);
6258 case M_SGT
: /* sreg > treg <==> treg < sreg */
6264 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6267 case M_SGT_I
: /* sreg > I <==> I < sreg */
6273 load_register (&icnt
, AT
, &imm_expr
, 0);
6274 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6277 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6283 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6284 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6285 (int) BFD_RELOC_LO16
);
6288 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6294 load_register (&icnt
, AT
, &imm_expr
, 0);
6295 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6296 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6297 (int) BFD_RELOC_LO16
);
6301 if (imm_expr
.X_op
== O_constant
6302 && imm_expr
.X_add_number
>= -0x8000
6303 && imm_expr
.X_add_number
< 0x8000)
6305 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6306 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6309 load_register (&icnt
, AT
, &imm_expr
, 0);
6310 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6314 if (imm_expr
.X_op
== O_constant
6315 && imm_expr
.X_add_number
>= -0x8000
6316 && imm_expr
.X_add_number
< 0x8000)
6318 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6319 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6322 load_register (&icnt
, AT
, &imm_expr
, 0);
6323 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6329 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6332 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6336 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6338 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6344 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6346 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6352 as_warn (_("Instruction %s: result is always true"),
6354 macro_build ((char *) NULL
, &icnt
, &expr1
,
6355 ((bfd_arch_bits_per_address (stdoutput
) == 32
6356 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6357 ? "addiu" : "daddiu"),
6358 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6361 if (imm_expr
.X_op
== O_constant
6362 && imm_expr
.X_add_number
>= 0
6363 && imm_expr
.X_add_number
< 0x10000)
6365 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6366 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6369 else if (imm_expr
.X_op
== O_constant
6370 && imm_expr
.X_add_number
> -0x8000
6371 && imm_expr
.X_add_number
< 0)
6373 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6374 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6375 ((bfd_arch_bits_per_address (stdoutput
) == 32
6376 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6377 ? "addiu" : "daddiu"),
6378 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6383 load_register (&icnt
, AT
, &imm_expr
, 0);
6384 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6388 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6396 if (imm_expr
.X_op
== O_constant
6397 && imm_expr
.X_add_number
> -0x8000
6398 && imm_expr
.X_add_number
<= 0x8000)
6400 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6401 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6402 dbl
? "daddi" : "addi",
6403 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6406 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6407 macro_build ((char *) NULL
, &icnt
, NULL
,
6408 dbl
? "dsub" : "sub",
6409 "d,v,t", dreg
, sreg
, AT
);
6415 if (imm_expr
.X_op
== O_constant
6416 && imm_expr
.X_add_number
> -0x8000
6417 && imm_expr
.X_add_number
<= 0x8000)
6419 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6420 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6421 dbl
? "daddiu" : "addiu",
6422 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6425 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6426 macro_build ((char *) NULL
, &icnt
, NULL
,
6427 dbl
? "dsubu" : "subu",
6428 "d,v,t", dreg
, sreg
, AT
);
6449 load_register (&icnt
, AT
, &imm_expr
, 0);
6450 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6455 assert (mips_opts
.isa
== 1);
6456 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6457 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6460 * Is the double cfc1 instruction a bug in the mips assembler;
6461 * or is there a reason for it?
6463 mips_emit_delays (true);
6464 ++mips_opts
.noreorder
;
6465 mips_any_noreorder
= 1;
6466 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6467 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6468 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6469 expr1
.X_add_number
= 3;
6470 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6471 (int) BFD_RELOC_LO16
);
6472 expr1
.X_add_number
= 2;
6473 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6474 (int) BFD_RELOC_LO16
);
6475 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6476 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6477 macro_build ((char *) NULL
, &icnt
, NULL
,
6478 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6479 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6480 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6481 --mips_opts
.noreorder
;
6490 if (offset_expr
.X_add_number
>= 0x7fff)
6491 as_bad (_("operand overflow"));
6492 /* avoid load delay */
6493 if (! target_big_endian
)
6494 offset_expr
.X_add_number
+= 1;
6495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6496 (int) BFD_RELOC_LO16
, breg
);
6497 if (! target_big_endian
)
6498 offset_expr
.X_add_number
-= 1;
6500 offset_expr
.X_add_number
+= 1;
6501 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6502 (int) BFD_RELOC_LO16
, breg
);
6503 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6504 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6517 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6518 as_bad (_("operand overflow"));
6519 if (! target_big_endian
)
6520 offset_expr
.X_add_number
+= off
;
6521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6522 (int) BFD_RELOC_LO16
, breg
);
6523 if (! target_big_endian
)
6524 offset_expr
.X_add_number
-= off
;
6526 offset_expr
.X_add_number
+= off
;
6527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6528 (int) BFD_RELOC_LO16
, breg
);
6541 load_address (&icnt
, AT
, &offset_expr
);
6543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6544 ((bfd_arch_bits_per_address (stdoutput
) == 32
6545 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6546 ? "addu" : "daddu"),
6547 "d,v,t", AT
, AT
, breg
);
6548 if (! target_big_endian
)
6549 expr1
.X_add_number
= off
;
6551 expr1
.X_add_number
= 0;
6552 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6553 (int) BFD_RELOC_LO16
, AT
);
6554 if (! target_big_endian
)
6555 expr1
.X_add_number
= 0;
6557 expr1
.X_add_number
= off
;
6558 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6559 (int) BFD_RELOC_LO16
, AT
);
6564 load_address (&icnt
, AT
, &offset_expr
);
6566 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6567 ((bfd_arch_bits_per_address (stdoutput
) == 32
6568 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6569 ? "addu" : "daddu"),
6570 "d,v,t", AT
, AT
, breg
);
6571 if (target_big_endian
)
6572 expr1
.X_add_number
= 0;
6573 macro_build ((char *) NULL
, &icnt
, &expr1
,
6574 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6575 (int) BFD_RELOC_LO16
, AT
);
6576 if (target_big_endian
)
6577 expr1
.X_add_number
= 1;
6579 expr1
.X_add_number
= 0;
6580 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6581 (int) BFD_RELOC_LO16
, AT
);
6582 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6584 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6589 if (offset_expr
.X_add_number
>= 0x7fff)
6590 as_bad (_("operand overflow"));
6591 if (target_big_endian
)
6592 offset_expr
.X_add_number
+= 1;
6593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6594 (int) BFD_RELOC_LO16
, breg
);
6595 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6596 if (target_big_endian
)
6597 offset_expr
.X_add_number
-= 1;
6599 offset_expr
.X_add_number
+= 1;
6600 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6601 (int) BFD_RELOC_LO16
, breg
);
6614 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6615 as_bad (_("operand overflow"));
6616 if (! target_big_endian
)
6617 offset_expr
.X_add_number
+= off
;
6618 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6619 (int) BFD_RELOC_LO16
, breg
);
6620 if (! target_big_endian
)
6621 offset_expr
.X_add_number
-= off
;
6623 offset_expr
.X_add_number
+= off
;
6624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6625 (int) BFD_RELOC_LO16
, breg
);
6638 load_address (&icnt
, AT
, &offset_expr
);
6640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6641 ((bfd_arch_bits_per_address (stdoutput
) == 32
6642 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6643 ? "addu" : "daddu"),
6644 "d,v,t", AT
, AT
, breg
);
6645 if (! target_big_endian
)
6646 expr1
.X_add_number
= off
;
6648 expr1
.X_add_number
= 0;
6649 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6650 (int) BFD_RELOC_LO16
, AT
);
6651 if (! target_big_endian
)
6652 expr1
.X_add_number
= 0;
6654 expr1
.X_add_number
= off
;
6655 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6656 (int) BFD_RELOC_LO16
, AT
);
6660 load_address (&icnt
, AT
, &offset_expr
);
6662 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6663 ((bfd_arch_bits_per_address (stdoutput
) == 32
6664 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6665 ? "addu" : "daddu"),
6666 "d,v,t", AT
, AT
, breg
);
6667 if (! target_big_endian
)
6668 expr1
.X_add_number
= 0;
6669 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6670 (int) BFD_RELOC_LO16
, AT
);
6671 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6673 if (! target_big_endian
)
6674 expr1
.X_add_number
= 1;
6676 expr1
.X_add_number
= 0;
6677 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6678 (int) BFD_RELOC_LO16
, AT
);
6679 if (! target_big_endian
)
6680 expr1
.X_add_number
= 0;
6682 expr1
.X_add_number
= 1;
6683 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6684 (int) BFD_RELOC_LO16
, AT
);
6685 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6687 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6692 /* FIXME: Check if this is one of the itbl macros, since they
6693 are added dynamically. */
6694 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6698 as_warn (_("Macro used $at after \".set noat\""));
6701 /* Implement macros in mips16 mode. */
6705 struct mips_cl_insn
*ip
;
6708 int xreg
, yreg
, zreg
, tmp
;
6712 const char *s
, *s2
, *s3
;
6714 mask
= ip
->insn_mo
->mask
;
6716 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6717 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6718 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6722 expr1
.X_op
= O_constant
;
6723 expr1
.X_op_symbol
= NULL
;
6724 expr1
.X_add_symbol
= NULL
;
6725 expr1
.X_add_number
= 1;
6744 mips_emit_delays (true);
6745 ++mips_opts
.noreorder
;
6746 mips_any_noreorder
= 1;
6747 macro_build ((char *) NULL
, &icnt
, NULL
,
6748 dbl
? "ddiv" : "div",
6749 "0,x,y", xreg
, yreg
);
6750 expr1
.X_add_number
= 2;
6751 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6752 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6754 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6755 since that causes an overflow. We should do that as well,
6756 but I don't see how to do the comparisons without a temporary
6758 --mips_opts
.noreorder
;
6759 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6778 mips_emit_delays (true);
6779 ++mips_opts
.noreorder
;
6780 mips_any_noreorder
= 1;
6781 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6782 expr1
.X_add_number
= 2;
6783 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6784 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6785 --mips_opts
.noreorder
;
6786 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6792 macro_build ((char *) NULL
, &icnt
, NULL
,
6793 dbl
? "dmultu" : "multu",
6795 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6803 if (imm_expr
.X_op
!= O_constant
)
6804 as_bad (_("Unsupported large constant"));
6805 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6806 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6807 dbl
? "daddiu" : "addiu",
6808 "y,x,4", yreg
, xreg
);
6812 if (imm_expr
.X_op
!= O_constant
)
6813 as_bad (_("Unsupported large constant"));
6814 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6815 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6820 if (imm_expr
.X_op
!= O_constant
)
6821 as_bad (_("Unsupported large constant"));
6822 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6823 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6846 goto do_reverse_branch
;
6850 goto do_reverse_branch
;
6862 goto do_reverse_branch
;
6873 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6902 goto do_addone_branch_i
;
6907 goto do_addone_branch_i
;
6922 goto do_addone_branch_i
;
6929 if (imm_expr
.X_op
!= O_constant
)
6930 as_bad (_("Unsupported large constant"));
6931 ++imm_expr
.X_add_number
;
6934 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6935 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6939 expr1
.X_add_number
= 0;
6940 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6942 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6943 "move", "y,X", xreg
, yreg
);
6944 expr1
.X_add_number
= 2;
6945 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6947 "neg", "x,w", xreg
, xreg
);
6951 /* For consistency checking, verify that all bits are specified either
6952 by the match/mask part of the instruction definition, or by the
6955 validate_mips_insn (opc
)
6956 const struct mips_opcode
*opc
;
6958 const char *p
= opc
->args
;
6960 unsigned long used_bits
= opc
->mask
;
6962 if ((used_bits
& opc
->match
) != opc
->match
)
6964 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6965 opc
->name
, opc
->args
);
6968 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6975 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6976 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6978 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6979 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6980 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6981 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6983 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6984 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6987 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6988 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6989 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6990 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6991 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6992 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6993 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6994 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6995 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6996 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6997 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6999 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7000 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7001 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7002 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7004 case 'm': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7005 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7006 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7007 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7008 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7009 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7010 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7011 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7012 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7013 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7016 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7018 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7019 c
, opc
->name
, opc
->args
);
7023 if (used_bits
!= 0xffffffff)
7025 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7026 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7032 /* This routine assembles an instruction into its binary format. As a
7033 side effect, it sets one of the global variables imm_reloc or
7034 offset_reloc to the type of relocation to do if one of the operands
7035 is an address expression. */
7040 struct mips_cl_insn
*ip
;
7045 struct mips_opcode
*insn
;
7048 unsigned int lastregno
= 0;
7051 int full_opcode_match
= 1;
7055 /* If the instruction contains a '.', we first try to match an instruction
7056 including the '.'. Then we try again without the '.'. */
7058 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7061 /* If we stopped on whitespace, then replace the whitespace with null for
7062 the call to hash_find. Save the character we replaced just in case we
7063 have to re-parse the instruction. */
7064 if (isspace ((unsigned char) *s
))
7070 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7072 /* If we didn't find the instruction in the opcode table, try again, but
7073 this time with just the instruction up to, but not including the
7077 /* Restore the character we overwrite above (if any). */
7081 /* Scan up to the first '.' or whitespace. */
7082 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7085 /* If we did not find a '.', then we can quit now. */
7088 insn_error
= "unrecognized opcode";
7092 /* Lookup the instruction in the hash table. */
7094 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7096 insn_error
= "unrecognized opcode";
7100 full_opcode_match
= 0;
7108 assert (strcmp (insn
->name
, str
) == 0);
7110 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7115 if (insn
->pinfo
!= INSN_MACRO
)
7117 if (mips_cpu
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7123 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7124 && strcmp (insn
->name
, insn
[1].name
) == 0)
7131 static char buf
[100];
7133 _("opcode not supported on this processor: %s (MIPS%d)"),
7134 mips_cpu_to_str (mips_cpu
), mips_opts
.isa
);
7142 ip
->insn_opcode
= insn
->match
;
7143 for (args
= insn
->args
;; ++args
)
7149 case '\0': /* end of args */
7162 ip
->insn_opcode
|= lastregno
<< 21;
7167 ip
->insn_opcode
|= lastregno
<< 16;
7171 ip
->insn_opcode
|= lastregno
<< 11;
7177 /* Handle optional base register.
7178 Either the base register is omitted or
7179 we must have a left paren. */
7180 /* This is dependent on the next operand specifier
7181 is a base register specification. */
7182 assert (args
[1] == 'b' || args
[1] == '5'
7183 || args
[1] == '-' || args
[1] == '4');
7187 case ')': /* these must match exactly */
7192 case '<': /* must be at least one digit */
7194 * According to the manual, if the shift amount is greater
7195 * than 31 or less than 0 the the shift amount should be
7196 * mod 32. In reality the mips assembler issues an error.
7197 * We issue a warning and mask out all but the low 5 bits.
7199 my_getExpression (&imm_expr
, s
);
7200 check_absolute_expr (ip
, &imm_expr
);
7201 if ((unsigned long) imm_expr
.X_add_number
> 31)
7203 as_warn (_("Improper shift amount (%ld)"),
7204 (long) imm_expr
.X_add_number
);
7205 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7207 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7208 imm_expr
.X_op
= O_absent
;
7212 case '>': /* shift amount minus 32 */
7213 my_getExpression (&imm_expr
, s
);
7214 check_absolute_expr (ip
, &imm_expr
);
7215 if ((unsigned long) imm_expr
.X_add_number
< 32
7216 || (unsigned long) imm_expr
.X_add_number
> 63)
7218 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7219 imm_expr
.X_op
= O_absent
;
7223 case 'k': /* cache code */
7224 case 'h': /* prefx code */
7225 my_getExpression (&imm_expr
, s
);
7226 check_absolute_expr (ip
, &imm_expr
);
7227 if ((unsigned long) imm_expr
.X_add_number
> 31)
7229 as_warn (_("Invalid value for `%s' (%lu)"),
7231 (unsigned long) imm_expr
.X_add_number
);
7232 imm_expr
.X_add_number
&= 0x1f;
7235 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7237 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7238 imm_expr
.X_op
= O_absent
;
7242 case 'c': /* break code */
7243 my_getExpression (&imm_expr
, s
);
7244 check_absolute_expr (ip
, &imm_expr
);
7245 if ((unsigned) imm_expr
.X_add_number
> 1023)
7247 as_warn (_("Illegal break code (%ld)"),
7248 (long) imm_expr
.X_add_number
);
7249 imm_expr
.X_add_number
&= 0x3ff;
7251 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7252 imm_expr
.X_op
= O_absent
;
7256 case 'q': /* lower break code */
7257 my_getExpression (&imm_expr
, s
);
7258 check_absolute_expr (ip
, &imm_expr
);
7259 if ((unsigned) imm_expr
.X_add_number
> 1023)
7261 as_warn (_("Illegal lower break code (%ld)"),
7262 (long) imm_expr
.X_add_number
);
7263 imm_expr
.X_add_number
&= 0x3ff;
7265 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7266 imm_expr
.X_op
= O_absent
;
7270 case 'm': /* Full 20 bit break code. */
7271 my_getExpression (&imm_expr
, s
);
7273 check_absolute_expr (ip
, &imm_expr
);
7275 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7277 as_warn (_("Illegal break code (%ld)"),
7278 (long) imm_expr
.X_add_number
);
7279 imm_expr
.X_add_number
&= 0xfffff;
7282 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7283 imm_expr
.X_op
= O_absent
;
7288 case 'B': /* syscall code */
7289 my_getExpression (&imm_expr
, s
);
7290 check_absolute_expr (ip
, &imm_expr
);
7291 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7292 as_warn (_("Illegal syscall code (%ld)"),
7293 (long) imm_expr
.X_add_number
);
7294 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7295 imm_expr
.X_op
= O_absent
;
7299 case 'C': /* Coprocessor code */
7300 my_getExpression (&imm_expr
, s
);
7301 check_absolute_expr (ip
, &imm_expr
);
7302 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7304 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7305 (long) imm_expr
.X_add_number
);
7306 imm_expr
.X_add_number
&= ((1<<25) - 1);
7308 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7309 imm_expr
.X_op
= O_absent
;
7313 case 'P': /* Performance register */
7314 my_getExpression (&imm_expr
, s
);
7315 check_absolute_expr (ip
, &imm_expr
);
7316 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7318 as_warn (_("Invalidate performance regster (%ld)"),
7319 (long) imm_expr
.X_add_number
);
7320 imm_expr
.X_add_number
&= 1;
7322 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7323 imm_expr
.X_op
= O_absent
;
7327 case 'b': /* base register */
7328 case 'd': /* destination register */
7329 case 's': /* source register */
7330 case 't': /* target register */
7331 case 'r': /* both target and source */
7332 case 'v': /* both dest and source */
7333 case 'w': /* both dest and target */
7334 case 'E': /* coprocessor target register */
7335 case 'G': /* coprocessor destination register */
7336 case 'x': /* ignore register name */
7337 case 'z': /* must be zero register */
7342 if (isdigit ((unsigned char) s
[1]))
7352 while (isdigit ((unsigned char) *s
));
7354 as_bad (_("Invalid register number (%d)"), regno
);
7356 else if (*args
== 'E' || *args
== 'G')
7360 if (s
[1] == 'f' && s
[2] == 'p')
7365 else if (s
[1] == 's' && s
[2] == 'p')
7370 else if (s
[1] == 'g' && s
[2] == 'p')
7375 else if (s
[1] == 'a' && s
[2] == 't')
7380 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7385 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7390 else if (itbl_have_entries
)
7395 p
= s
+ 1; /* advance past '$' */
7396 n
= itbl_get_field (&p
); /* n is name */
7398 /* See if this is a register defined in an
7400 if (itbl_get_reg_val (n
, &r
))
7402 /* Get_field advances to the start of
7403 the next field, so we need to back
7404 rack to the end of the last field. */
7408 s
= strchr (s
, '\0');
7421 as_warn (_("Used $at without \".set noat\""));
7427 if (c
== 'r' || c
== 'v' || c
== 'w')
7434 /* 'z' only matches $0. */
7435 if (c
== 'z' && regno
!= 0)
7438 /* Now that we have assembled one operand, we use the args string
7439 * to figure out where it goes in the instruction. */
7446 ip
->insn_opcode
|= regno
<< 21;
7450 ip
->insn_opcode
|= regno
<< 11;
7455 ip
->insn_opcode
|= regno
<< 16;
7458 /* This case exists because on the r3000 trunc
7459 expands into a macro which requires a gp
7460 register. On the r6000 or r4000 it is
7461 assembled into a single instruction which
7462 ignores the register. Thus the insn version
7463 is MIPS_ISA2 and uses 'x', and the macro
7464 version is MIPS_ISA1 and uses 't'. */
7467 /* This case is for the div instruction, which
7468 acts differently if the destination argument
7469 is $0. This only matches $0, and is checked
7470 outside the switch. */
7473 /* Itbl operand; not yet implemented. FIXME ?? */
7475 /* What about all other operands like 'i', which
7476 can be specified in the opcode table? */
7486 ip
->insn_opcode
|= lastregno
<< 21;
7489 ip
->insn_opcode
|= lastregno
<< 16;
7494 case 'D': /* floating point destination register */
7495 case 'S': /* floating point source register */
7496 case 'T': /* floating point target register */
7497 case 'R': /* floating point source register */
7501 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7511 while (isdigit ((unsigned char) *s
));
7514 as_bad (_("Invalid float register number (%d)"), regno
);
7516 if ((regno
& 1) != 0
7517 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7518 && ! (strcmp (str
, "mtc1") == 0
7519 || strcmp (str
, "mfc1") == 0
7520 || strcmp (str
, "lwc1") == 0
7521 || strcmp (str
, "swc1") == 0
7522 || strcmp (str
, "l.s") == 0
7523 || strcmp (str
, "s.s") == 0))
7524 as_warn (_("Float register should be even, was %d"),
7532 if (c
== 'V' || c
== 'W')
7542 ip
->insn_opcode
|= regno
<< 6;
7546 ip
->insn_opcode
|= regno
<< 11;
7550 ip
->insn_opcode
|= regno
<< 16;
7553 ip
->insn_opcode
|= regno
<< 21;
7563 ip
->insn_opcode
|= lastregno
<< 11;
7566 ip
->insn_opcode
|= lastregno
<< 16;
7572 my_getExpression (&imm_expr
, s
);
7573 if (imm_expr
.X_op
!= O_big
7574 && imm_expr
.X_op
!= O_constant
)
7575 insn_error
= _("absolute expression required");
7580 my_getExpression (&offset_expr
, s
);
7581 imm_reloc
= BFD_RELOC_32
;
7593 unsigned char temp
[8];
7595 unsigned int length
;
7600 /* These only appear as the last operand in an
7601 instruction, and every instruction that accepts
7602 them in any variant accepts them in all variants.
7603 This means we don't have to worry about backing out
7604 any changes if the instruction does not match.
7606 The difference between them is the size of the
7607 floating point constant and where it goes. For 'F'
7608 and 'L' the constant is 64 bits; for 'f' and 'l' it
7609 is 32 bits. Where the constant is placed is based
7610 on how the MIPS assembler does things:
7613 f -- immediate value
7616 The .lit4 and .lit8 sections are only used if
7617 permitted by the -G argument.
7619 When generating embedded PIC code, we use the
7620 .lit8 section but not the .lit4 section (we can do
7621 .lit4 inline easily; we need to put .lit8
7622 somewhere in the data segment, and using .lit8
7623 permits the linker to eventually combine identical
7626 f64
= *args
== 'F' || *args
== 'L';
7628 save_in
= input_line_pointer
;
7629 input_line_pointer
= s
;
7630 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7632 s
= input_line_pointer
;
7633 input_line_pointer
= save_in
;
7634 if (err
!= NULL
&& *err
!= '\0')
7636 as_bad (_("Bad floating point constant: %s"), err
);
7637 memset (temp
, '\0', sizeof temp
);
7638 length
= f64
? 8 : 4;
7641 assert (length
== (unsigned) (f64
? 8 : 4));
7645 && (! USE_GLOBAL_POINTER_OPT
7646 || mips_pic
== EMBEDDED_PIC
7647 || g_switch_value
< 4
7648 || (temp
[0] == 0 && temp
[1] == 0)
7649 || (temp
[2] == 0 && temp
[3] == 0))))
7651 imm_expr
.X_op
= O_constant
;
7652 if (! target_big_endian
)
7653 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7655 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7658 && ! mips_disable_float_construction
7659 && ((temp
[0] == 0 && temp
[1] == 0)
7660 || (temp
[2] == 0 && temp
[3] == 0))
7661 && ((temp
[4] == 0 && temp
[5] == 0)
7662 || (temp
[6] == 0 && temp
[7] == 0)))
7664 /* The value is simple enough to load with a
7665 couple of instructions. In mips1 mode, set
7666 imm_expr to the high order 32 bits and
7667 offset_expr to the low order 32 bits.
7668 Otherwise, set imm_expr to the entire 64 bit
7670 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7672 imm_expr
.X_op
= O_constant
;
7673 offset_expr
.X_op
= O_constant
;
7674 if (! target_big_endian
)
7676 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7677 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7681 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7682 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7684 if (offset_expr
.X_add_number
== 0)
7685 offset_expr
.X_op
= O_absent
;
7687 else if (sizeof (imm_expr
.X_add_number
) > 4)
7689 imm_expr
.X_op
= O_constant
;
7690 if (! target_big_endian
)
7691 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7693 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7697 imm_expr
.X_op
= O_big
;
7698 imm_expr
.X_add_number
= 4;
7699 if (! target_big_endian
)
7701 generic_bignum
[0] = bfd_getl16 (temp
);
7702 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7703 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7704 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7708 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7709 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7710 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7711 generic_bignum
[3] = bfd_getb16 (temp
);
7717 const char *newname
;
7720 /* Switch to the right section. */
7722 subseg
= now_subseg
;
7725 default: /* unused default case avoids warnings. */
7727 newname
= RDATA_SECTION_NAME
;
7728 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7729 || mips_pic
== EMBEDDED_PIC
)
7733 if (mips_pic
== EMBEDDED_PIC
)
7736 newname
= RDATA_SECTION_NAME
;
7739 assert (!USE_GLOBAL_POINTER_OPT
7740 || g_switch_value
>= 4);
7744 new_seg
= subseg_new (newname
, (subsegT
) 0);
7745 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7746 bfd_set_section_flags (stdoutput
, new_seg
,
7751 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7752 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7753 && strcmp (TARGET_OS
, "elf") != 0)
7754 record_alignment (new_seg
, 4);
7756 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7758 as_bad (_("Can't use floating point insn in this section"));
7760 /* Set the argument to the current address in the
7762 offset_expr
.X_op
= O_symbol
;
7763 offset_expr
.X_add_symbol
=
7764 symbol_new ("L0\001", now_seg
,
7765 (valueT
) frag_now_fix (), frag_now
);
7766 offset_expr
.X_add_number
= 0;
7768 /* Put the floating point number into the section. */
7769 p
= frag_more ((int) length
);
7770 memcpy (p
, temp
, length
);
7772 /* Switch back to the original section. */
7773 subseg_set (seg
, subseg
);
7778 case 'i': /* 16 bit unsigned immediate */
7779 case 'j': /* 16 bit signed immediate */
7780 imm_reloc
= BFD_RELOC_LO16
;
7781 c
= my_getSmallExpression (&imm_expr
, s
);
7786 if (imm_expr
.X_op
== O_constant
)
7787 imm_expr
.X_add_number
=
7788 (imm_expr
.X_add_number
>> 16) & 0xffff;
7791 imm_reloc
= BFD_RELOC_HI16_S
;
7792 imm_unmatched_hi
= true;
7795 imm_reloc
= BFD_RELOC_HI16
;
7797 else if (imm_expr
.X_op
== O_constant
)
7798 imm_expr
.X_add_number
&= 0xffff;
7802 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7803 || ((imm_expr
.X_add_number
< 0
7804 || imm_expr
.X_add_number
>= 0x10000)
7805 && imm_expr
.X_op
== O_constant
))
7807 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7808 !strcmp (insn
->name
, insn
[1].name
))
7810 if (imm_expr
.X_op
== O_constant
7811 || imm_expr
.X_op
== O_big
)
7812 as_bad (_("16 bit expression not in range 0..65535"));
7820 /* The upper bound should be 0x8000, but
7821 unfortunately the MIPS assembler accepts numbers
7822 from 0x8000 to 0xffff and sign extends them, and
7823 we want to be compatible. We only permit this
7824 extended range for an instruction which does not
7825 provide any further alternates, since those
7826 alternates may handle other cases. People should
7827 use the numbers they mean, rather than relying on
7828 a mysterious sign extension. */
7829 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7830 strcmp (insn
->name
, insn
[1].name
) == 0);
7835 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7836 || ((imm_expr
.X_add_number
< -0x8000
7837 || imm_expr
.X_add_number
>= max
)
7838 && imm_expr
.X_op
== O_constant
)
7840 && imm_expr
.X_add_number
< 0
7841 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7842 && imm_expr
.X_unsigned
7843 && sizeof (imm_expr
.X_add_number
) <= 4))
7847 if (imm_expr
.X_op
== O_constant
7848 || imm_expr
.X_op
== O_big
)
7849 as_bad (_("16 bit expression not in range -32768..32767"));
7855 case 'o': /* 16 bit offset */
7856 c
= my_getSmallExpression (&offset_expr
, s
);
7858 /* If this value won't fit into a 16 bit offset, then go
7859 find a macro that will generate the 32 bit offset
7860 code pattern. As a special hack, we accept the
7861 difference of two local symbols as a constant. This
7862 is required to suppose embedded PIC switches, which
7863 use an instruction which looks like
7864 lw $4,$L12-$LS12($4)
7865 The problem with handling this in a more general
7866 fashion is that the macro function doesn't expect to
7867 see anything which can be handled in a single
7868 constant instruction. */
7870 && (offset_expr
.X_op
!= O_constant
7871 || offset_expr
.X_add_number
>= 0x8000
7872 || offset_expr
.X_add_number
< -0x8000)
7873 && (mips_pic
!= EMBEDDED_PIC
7874 || offset_expr
.X_op
!= O_subtract
7875 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7879 if (c
== 'h' || c
== 'H')
7881 if (offset_expr
.X_op
!= O_constant
)
7883 offset_expr
.X_add_number
=
7884 (offset_expr
.X_add_number
>> 16) & 0xffff;
7886 offset_reloc
= BFD_RELOC_LO16
;
7890 case 'p': /* pc relative offset */
7891 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7892 my_getExpression (&offset_expr
, s
);
7896 case 'u': /* upper 16 bits */
7897 c
= my_getSmallExpression (&imm_expr
, s
);
7898 imm_reloc
= BFD_RELOC_LO16
;
7903 if (imm_expr
.X_op
== O_constant
)
7904 imm_expr
.X_add_number
=
7905 (imm_expr
.X_add_number
>> 16) & 0xffff;
7908 imm_reloc
= BFD_RELOC_HI16_S
;
7909 imm_unmatched_hi
= true;
7912 imm_reloc
= BFD_RELOC_HI16
;
7914 else if (imm_expr
.X_op
== O_constant
)
7915 imm_expr
.X_add_number
&= 0xffff;
7917 if (imm_expr
.X_op
== O_constant
7918 && (imm_expr
.X_add_number
< 0
7919 || imm_expr
.X_add_number
>= 0x10000))
7920 as_bad (_("lui expression not in range 0..65535"));
7924 case 'a': /* 26 bit address */
7925 my_getExpression (&offset_expr
, s
);
7927 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7930 case 'N': /* 3 bit branch condition code */
7931 case 'M': /* 3 bit compare condition code */
7932 if (strncmp (s
, "$fcc", 4) != 0)
7942 while (isdigit ((unsigned char) *s
));
7944 as_bad (_("invalid condition code register $fcc%d"), regno
);
7946 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7948 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7952 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7954 if (isdigit ((unsigned char) *s
))
7963 while (isdigit ((unsigned char) *s
));
7966 c
= 8; /* Invalid sel value. */
7969 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7970 ip
->insn_opcode
|= c
;
7974 as_bad (_("bad char = '%c'\n"), *args
);
7979 /* Args don't match. */
7980 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7981 !strcmp (insn
->name
, insn
[1].name
))
7987 insn_error
= _("illegal operands");
7992 /* This routine assembles an instruction into its binary format when
7993 assembling for the mips16. As a side effect, it sets one of the
7994 global variables imm_reloc or offset_reloc to the type of
7995 relocation to do if one of the operands is an address expression.
7996 It also sets mips16_small and mips16_ext if the user explicitly
7997 requested a small or extended instruction. */
8002 struct mips_cl_insn
*ip
;
8006 struct mips_opcode
*insn
;
8009 unsigned int lastregno
= 0;
8014 mips16_small
= false;
8017 for (s
= str
; islower ((unsigned char) *s
); ++s
)
8029 if (s
[1] == 't' && s
[2] == ' ')
8032 mips16_small
= true;
8036 else if (s
[1] == 'e' && s
[2] == ' ')
8045 insn_error
= _("unknown opcode");
8049 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8050 mips16_small
= true;
8052 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8054 insn_error
= _("unrecognized opcode");
8061 assert (strcmp (insn
->name
, str
) == 0);
8064 ip
->insn_opcode
= insn
->match
;
8065 ip
->use_extend
= false;
8066 imm_expr
.X_op
= O_absent
;
8067 imm_reloc
= BFD_RELOC_UNUSED
;
8068 offset_expr
.X_op
= O_absent
;
8069 offset_reloc
= BFD_RELOC_UNUSED
;
8070 for (args
= insn
->args
; 1; ++args
)
8077 /* In this switch statement we call break if we did not find
8078 a match, continue if we did find a match, or return if we
8087 /* Stuff the immediate value in now, if we can. */
8088 if (imm_expr
.X_op
== O_constant
8089 && imm_reloc
> BFD_RELOC_UNUSED
8090 && insn
->pinfo
!= INSN_MACRO
)
8092 mips16_immed ((char *) NULL
, 0,
8093 imm_reloc
- BFD_RELOC_UNUSED
,
8094 imm_expr
.X_add_number
, true, mips16_small
,
8095 mips16_ext
, &ip
->insn_opcode
,
8096 &ip
->use_extend
, &ip
->extend
);
8097 imm_expr
.X_op
= O_absent
;
8098 imm_reloc
= BFD_RELOC_UNUSED
;
8112 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8115 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8131 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8133 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8150 if (isdigit ((unsigned char) s
[1]))
8160 while (isdigit ((unsigned char) *s
));
8163 as_bad (_("invalid register number (%d)"), regno
);
8169 if (s
[1] == 'f' && s
[2] == 'p')
8174 else if (s
[1] == 's' && s
[2] == 'p')
8179 else if (s
[1] == 'g' && s
[2] == 'p')
8184 else if (s
[1] == 'a' && s
[2] == 't')
8189 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8194 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8207 if (c
== 'v' || c
== 'w')
8209 regno
= mips16_to_32_reg_map
[lastregno
];
8223 regno
= mips32_to_16_reg_map
[regno
];
8228 regno
= ILLEGAL_REG
;
8233 regno
= ILLEGAL_REG
;
8238 regno
= ILLEGAL_REG
;
8243 if (regno
== AT
&& ! mips_opts
.noat
)
8244 as_warn (_("used $at without \".set noat\""));
8251 if (regno
== ILLEGAL_REG
)
8258 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8262 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8265 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8268 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8274 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8277 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8278 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8288 if (strncmp (s
, "$pc", 3) == 0)
8312 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8314 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8315 and generate the appropriate reloc. If the text
8316 inside %gprel is not a symbol name with an
8317 optional offset, then we generate a normal reloc
8318 and will probably fail later. */
8319 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8320 if (imm_expr
.X_op
== O_symbol
)
8323 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8325 ip
->use_extend
= true;
8332 /* Just pick up a normal expression. */
8333 my_getExpression (&imm_expr
, s
);
8336 if (imm_expr
.X_op
== O_register
)
8338 /* What we thought was an expression turned out to
8341 if (s
[0] == '(' && args
[1] == '(')
8343 /* It looks like the expression was omitted
8344 before a register indirection, which means
8345 that the expression is implicitly zero. We
8346 still set up imm_expr, so that we handle
8347 explicit extensions correctly. */
8348 imm_expr
.X_op
= O_constant
;
8349 imm_expr
.X_add_number
= 0;
8350 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8357 /* We need to relax this instruction. */
8358 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8367 /* We use offset_reloc rather than imm_reloc for the PC
8368 relative operands. This lets macros with both
8369 immediate and address operands work correctly. */
8370 my_getExpression (&offset_expr
, s
);
8372 if (offset_expr
.X_op
== O_register
)
8375 /* We need to relax this instruction. */
8376 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8380 case '6': /* break code */
8381 my_getExpression (&imm_expr
, s
);
8382 check_absolute_expr (ip
, &imm_expr
);
8383 if ((unsigned long) imm_expr
.X_add_number
> 63)
8385 as_warn (_("Invalid value for `%s' (%lu)"),
8387 (unsigned long) imm_expr
.X_add_number
);
8388 imm_expr
.X_add_number
&= 0x3f;
8390 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8391 imm_expr
.X_op
= O_absent
;
8395 case 'a': /* 26 bit address */
8396 my_getExpression (&offset_expr
, s
);
8398 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8399 ip
->insn_opcode
<<= 16;
8402 case 'l': /* register list for entry macro */
8403 case 'L': /* register list for exit macro */
8413 int freg
, reg1
, reg2
;
8415 while (*s
== ' ' || *s
== ',')
8419 as_bad (_("can't parse register list"));
8431 while (isdigit ((unsigned char) *s
))
8453 as_bad (_("invalid register list"));
8458 while (isdigit ((unsigned char) *s
))
8465 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8470 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8475 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8476 mask
|= (reg2
- 3) << 3;
8477 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8478 mask
|= (reg2
- 15) << 1;
8479 else if (reg1
== 31 && reg2
== 31)
8483 as_bad (_("invalid register list"));
8487 /* The mask is filled in in the opcode table for the
8488 benefit of the disassembler. We remove it before
8489 applying the actual mask. */
8490 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8491 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8495 case 'e': /* extend code */
8496 my_getExpression (&imm_expr
, s
);
8497 check_absolute_expr (ip
, &imm_expr
);
8498 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8500 as_warn (_("Invalid value for `%s' (%lu)"),
8502 (unsigned long) imm_expr
.X_add_number
);
8503 imm_expr
.X_add_number
&= 0x7ff;
8505 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8506 imm_expr
.X_op
= O_absent
;
8516 /* Args don't match. */
8517 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8518 strcmp (insn
->name
, insn
[1].name
) == 0)
8525 insn_error
= _("illegal operands");
8531 /* This structure holds information we know about a mips16 immediate
8534 struct mips16_immed_operand
8536 /* The type code used in the argument string in the opcode table. */
8538 /* The number of bits in the short form of the opcode. */
8540 /* The number of bits in the extended form of the opcode. */
8542 /* The amount by which the short form is shifted when it is used;
8543 for example, the sw instruction has a shift count of 2. */
8545 /* The amount by which the short form is shifted when it is stored
8546 into the instruction code. */
8548 /* Non-zero if the short form is unsigned. */
8550 /* Non-zero if the extended form is unsigned. */
8552 /* Non-zero if the value is PC relative. */
8556 /* The mips16 immediate operand types. */
8558 static const struct mips16_immed_operand mips16_immed_operands
[] =
8560 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8561 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8562 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8563 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8564 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8565 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8566 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8567 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8568 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8569 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8570 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8571 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8572 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8573 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8574 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8575 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8576 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8577 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8578 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8579 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8580 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8583 #define MIPS16_NUM_IMMED \
8584 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8586 /* Handle a mips16 instruction with an immediate value. This or's the
8587 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8588 whether an extended value is needed; if one is needed, it sets
8589 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8590 If SMALL is true, an unextended opcode was explicitly requested.
8591 If EXT is true, an extended opcode was explicitly requested. If
8592 WARN is true, warn if EXT does not match reality. */
8595 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8604 unsigned long *insn
;
8605 boolean
*use_extend
;
8606 unsigned short *extend
;
8608 register const struct mips16_immed_operand
*op
;
8609 int mintiny
, maxtiny
;
8612 op
= mips16_immed_operands
;
8613 while (op
->type
!= type
)
8616 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8621 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8624 maxtiny
= 1 << op
->nbits
;
8629 maxtiny
= (1 << op
->nbits
) - 1;
8634 mintiny
= - (1 << (op
->nbits
- 1));
8635 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8638 /* Branch offsets have an implicit 0 in the lowest bit. */
8639 if (type
== 'p' || type
== 'q')
8642 if ((val
& ((1 << op
->shift
) - 1)) != 0
8643 || val
< (mintiny
<< op
->shift
)
8644 || val
> (maxtiny
<< op
->shift
))
8649 if (warn
&& ext
&& ! needext
)
8650 as_warn_where (file
, line
, _("extended operand requested but not required"));
8651 if (small
&& needext
)
8652 as_bad_where (file
, line
, _("invalid unextended operand value"));
8654 if (small
|| (! ext
&& ! needext
))
8658 *use_extend
= false;
8659 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8660 insnval
<<= op
->op_shift
;
8665 long minext
, maxext
;
8671 maxext
= (1 << op
->extbits
) - 1;
8675 minext
= - (1 << (op
->extbits
- 1));
8676 maxext
= (1 << (op
->extbits
- 1)) - 1;
8678 if (val
< minext
|| val
> maxext
)
8679 as_bad_where (file
, line
,
8680 _("operand value out of range for instruction"));
8683 if (op
->extbits
== 16)
8685 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8688 else if (op
->extbits
== 15)
8690 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8695 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8699 *extend
= (unsigned short) extval
;
8708 my_getSmallExpression (ep
, str
)
8719 ((str
[1] == 'h' && str
[2] == 'i')
8720 || (str
[1] == 'H' && str
[2] == 'I')
8721 || (str
[1] == 'l' && str
[2] == 'o'))
8733 * A small expression may be followed by a base register.
8734 * Scan to the end of this operand, and then back over a possible
8735 * base register. Then scan the small expression up to that
8736 * point. (Based on code in sparc.c...)
8738 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8740 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8742 if (isdigit ((unsigned char) sp
[-2]))
8744 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8746 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8752 else if (sp
- 5 >= str
8755 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8756 || (sp
[-3] == 's' && sp
[-2] == 'p')
8757 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8758 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8764 /* no expression means zero offset */
8767 /* %xx(reg) is an error */
8768 ep
->X_op
= O_absent
;
8773 ep
->X_op
= O_constant
;
8776 ep
->X_add_symbol
= NULL
;
8777 ep
->X_op_symbol
= NULL
;
8778 ep
->X_add_number
= 0;
8783 my_getExpression (ep
, str
);
8790 my_getExpression (ep
, str
);
8791 return c
; /* => %hi or %lo encountered */
8795 my_getExpression (ep
, str
)
8801 save_in
= input_line_pointer
;
8802 input_line_pointer
= str
;
8804 expr_end
= input_line_pointer
;
8805 input_line_pointer
= save_in
;
8807 /* If we are in mips16 mode, and this is an expression based on `.',
8808 then we bump the value of the symbol by 1 since that is how other
8809 text symbols are handled. We don't bother to handle complex
8810 expressions, just `.' plus or minus a constant. */
8811 if (mips_opts
.mips16
8812 && ep
->X_op
== O_symbol
8813 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8814 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8815 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8816 && symbol_constant_p (ep
->X_add_symbol
)
8817 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8818 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8821 /* Turn a string in input_line_pointer into a floating point constant
8822 of type TYPE, and store the appropriate bytes in *LITP. The number
8823 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8824 returned, or NULL on OK. */
8827 md_atof (type
, litP
, sizeP
)
8833 LITTLENUM_TYPE words
[4];
8849 return _("bad call to md_atof");
8852 t
= atof_ieee (input_line_pointer
, type
, words
);
8854 input_line_pointer
= t
;
8858 if (! target_big_endian
)
8860 for (i
= prec
- 1; i
>= 0; i
--)
8862 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8868 for (i
= 0; i
< prec
; i
++)
8870 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8879 md_number_to_chars (buf
, val
, n
)
8884 if (target_big_endian
)
8885 number_to_chars_bigendian (buf
, val
, n
);
8887 number_to_chars_littleendian (buf
, val
, n
);
8890 CONST
char *md_shortopts
= "O::g::G:";
8892 struct option md_longopts
[] =
8894 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8895 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8896 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8897 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8898 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8899 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8900 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8901 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8902 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8903 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8904 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8905 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8906 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8907 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8908 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8909 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8910 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8911 {"break", no_argument
, NULL
, OPTION_BREAK
},
8912 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8913 #define OPTION_EB (OPTION_MD_BASE + 9)
8914 {"EB", no_argument
, NULL
, OPTION_EB
},
8915 #define OPTION_EL (OPTION_MD_BASE + 10)
8916 {"EL", no_argument
, NULL
, OPTION_EL
},
8917 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8918 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8919 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8920 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8921 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8922 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8923 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8924 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8925 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8926 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8927 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8928 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8929 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8930 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8931 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8932 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8933 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8934 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8935 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8936 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8937 #define OPTION_MABI (OPTION_MD_BASE + 21)
8938 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8939 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8940 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8941 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8942 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8943 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8944 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8945 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8946 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8947 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8948 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8949 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8950 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8951 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8952 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8953 #define OPTION_NO_MIPS32 (OPTION_MD_BASE + 29)
8954 {"no-mips32", no_argument
, NULL
, OPTION_NO_MIPS32
},
8957 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8958 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8959 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8960 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8961 #define OPTION_32 (OPTION_ELF_BASE + 3)
8962 #define OPTION_64 (OPTION_ELF_BASE + 4)
8963 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8964 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8965 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8966 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8967 {"32", no_argument
, NULL
, OPTION_32
},
8968 {"64", no_argument
, NULL
, OPTION_64
},
8971 {NULL
, no_argument
, NULL
, 0}
8973 size_t md_longopts_size
= sizeof (md_longopts
);
8976 md_parse_option (c
, arg
)
8982 case OPTION_CONSTRUCT_FLOATS
:
8983 mips_disable_float_construction
= 0;
8986 case OPTION_NO_CONSTRUCT_FLOATS
:
8987 mips_disable_float_construction
= 1;
8999 target_big_endian
= 1;
9003 target_big_endian
= 0;
9007 if (arg
&& arg
[1] == '0')
9017 mips_debug
= atoi (arg
);
9018 /* When the MIPS assembler sees -g or -g2, it does not do
9019 optimizations which limit full symbolic debugging. We take
9020 that to be equivalent to -O0. */
9021 if (mips_debug
== 2)
9045 /* Identify the processor type */
9047 if (strcmp (p
, "default") == 0
9048 || strcmp (p
, "DEFAULT") == 0)
9054 /* We need to cope with the various "vr" prefixes for the 4300
9056 if (*p
== 'v' || *p
== 'V')
9062 if (*p
== 'r' || *p
== 'R')
9069 if (strcmp (p
, "10000") == 0
9070 || strcmp (p
, "10k") == 0
9071 || strcmp (p
, "10K") == 0)
9072 mips_cpu
= CPU_R10000
;
9076 if (strcmp (p
, "2000") == 0
9077 || strcmp (p
, "2k") == 0
9078 || strcmp (p
, "2K") == 0)
9079 mips_cpu
= CPU_R2000
;
9083 if (strcmp (p
, "3000") == 0
9084 || strcmp (p
, "3k") == 0
9085 || strcmp (p
, "3K") == 0)
9086 mips_cpu
= CPU_R3000
;
9087 else if (strcmp (p
, "3900") == 0)
9088 mips_cpu
= CPU_R3900
;
9092 if (strcmp (p
, "4000") == 0
9093 || strcmp (p
, "4k") == 0
9094 || strcmp (p
, "4K") == 0)
9095 mips_cpu
= CPU_R4000
;
9096 else if (strcmp (p
, "4100") == 0)
9097 mips_cpu
= CPU_VR4100
;
9098 else if (strcmp (p
, "4111") == 0)
9099 mips_cpu
= CPU_R4111
;
9100 else if (strcmp (p
, "4300") == 0)
9101 mips_cpu
= CPU_R4300
;
9102 else if (strcmp (p
, "4400") == 0)
9103 mips_cpu
= CPU_R4400
;
9104 else if (strcmp (p
, "4600") == 0)
9105 mips_cpu
= CPU_R4600
;
9106 else if (strcmp (p
, "4650") == 0)
9107 mips_cpu
= CPU_R4650
;
9108 else if (strcmp (p
, "4010") == 0)
9109 mips_cpu
= CPU_R4010
;
9110 else if (strcmp (p
, "4Kc") == 0
9111 || strcmp (p
, "4Kp") == 0
9112 || strcmp (p
, "4Km") == 0)
9113 mips_cpu
= CPU_MIPS32
;
9117 if (strcmp (p
, "5000") == 0
9118 || strcmp (p
, "5k") == 0
9119 || strcmp (p
, "5K") == 0)
9120 mips_cpu
= CPU_R5000
;
9124 if (strcmp (p
, "6000") == 0
9125 || strcmp (p
, "6k") == 0
9126 || strcmp (p
, "6K") == 0)
9127 mips_cpu
= CPU_R6000
;
9131 if (strcmp (p
, "8000") == 0
9132 || strcmp (p
, "8k") == 0
9133 || strcmp (p
, "8K") == 0)
9134 mips_cpu
= CPU_R8000
;
9138 if (strcmp (p
, "orion") == 0)
9139 mips_cpu
= CPU_R4600
;
9144 switch (atoi (p
+ 1))
9152 mips_cpu
= CPU_R5000
;
9160 && (mips_cpu
!= CPU_R4300
9161 && mips_cpu
!= CPU_VR4100
9162 && mips_cpu
!= CPU_R4111
9163 && mips_cpu
!= CPU_R5000
))
9165 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9171 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9179 mips_cpu
= CPU_R4650
;
9182 case OPTION_NO_M4650
:
9186 mips_cpu
= CPU_R4010
;
9189 case OPTION_NO_M4010
:
9193 mips_cpu
= CPU_VR4100
;
9196 case OPTION_NO_M4100
:
9200 mips_cpu
= CPU_MIPS32
;
9203 case OPTION_NO_MIPS32
:
9207 mips_cpu
= CPU_R3900
;
9210 case OPTION_NO_M3900
:
9214 mips_opts
.mips16
= 1;
9215 mips_no_prev_insn (false);
9218 case OPTION_NO_MIPS16
:
9219 mips_opts
.mips16
= 0;
9220 mips_no_prev_insn (false);
9223 case OPTION_MEMBEDDED_PIC
:
9224 mips_pic
= EMBEDDED_PIC
;
9225 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9227 as_bad (_("-G may not be used with embedded PIC code"));
9230 g_switch_value
= 0x7fffffff;
9233 /* When generating ELF code, we permit -KPIC and -call_shared to
9234 select SVR4_PIC, and -non_shared to select no PIC. This is
9235 intended to be compatible with Irix 5. */
9236 case OPTION_CALL_SHARED
:
9237 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9239 as_bad (_("-call_shared is supported only for ELF format"));
9242 mips_pic
= SVR4_PIC
;
9243 if (g_switch_seen
&& g_switch_value
!= 0)
9245 as_bad (_("-G may not be used with SVR4 PIC code"));
9251 case OPTION_NON_SHARED
:
9252 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9254 as_bad (_("-non_shared is supported only for ELF format"));
9260 /* The -xgot option tells the assembler to use 32 offsets when
9261 accessing the got in SVR4_PIC mode. It is for Irix
9268 if (! USE_GLOBAL_POINTER_OPT
)
9270 as_bad (_("-G is not supported for this configuration"));
9273 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9275 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9279 g_switch_value
= atoi (arg
);
9283 /* The -32 and -64 options tell the assembler to output the 32
9284 bit or the 64 bit MIPS ELF format. */
9291 const char **list
, **l
;
9293 list
= bfd_target_list ();
9294 for (l
= list
; *l
!= NULL
; l
++)
9295 if (strcmp (*l
, "elf64-bigmips") == 0
9296 || strcmp (*l
, "elf64-littlemips") == 0)
9299 as_fatal (_("No compiled in support for 64 bit object file format"));
9309 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9310 flag in object files because to do so would make it
9311 impossible to link with libraries compiled without "-gp32".
9312 This is unnecessarily restrictive.
9314 We could solve this problem by adding "-gp32" multilibs to
9315 gcc, but to set this flag before gcc is built with such
9316 multilibs will break too many systems. */
9318 /* mips_32bitmode = 1; */
9324 /* mips_32bitmode = 0; */
9328 if (strcmp (arg
,"32") == 0
9329 || strcmp (arg
,"n32") == 0
9330 || strcmp (arg
,"64") == 0
9331 || strcmp (arg
,"o64") == 0
9332 || strcmp (arg
,"eabi") == 0)
9333 mips_abi_string
= arg
;
9336 case OPTION_M7000_HILO_FIX
:
9337 mips_7000_hilo_fix
= true;
9340 case OPTION_NO_M7000_HILO_FIX
:
9341 mips_7000_hilo_fix
= false;
9352 show (stream
, string
, col_p
, first_p
)
9360 fprintf (stream
, "%24s", "");
9365 fprintf (stream
, ", ");
9369 if (*col_p
+ strlen (string
) > 72)
9371 fprintf (stream
, "\n%24s", "");
9375 fprintf (stream
, "%s", string
);
9376 *col_p
+= strlen (string
);
9382 md_show_usage (stream
)
9387 fprintf(stream
, _("\
9389 -membedded-pic generate embedded position independent code\n\
9390 -EB generate big endian output\n\
9391 -EL generate little endian output\n\
9392 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9393 -G NUM allow referencing objects up to NUM bytes\n\
9394 implicitly with the gp register [default 8]\n"));
9395 fprintf(stream
, _("\
9396 -mips1 generate MIPS ISA I instructions\n\
9397 -mips2 generate MIPS ISA II instructions\n\
9398 -mips3 generate MIPS ISA III instructions\n\
9399 -mips4 generate MIPS ISA IV instructions\n\
9400 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9404 show (stream
, "2000", &column
, &first
);
9405 show (stream
, "3000", &column
, &first
);
9406 show (stream
, "3900", &column
, &first
);
9407 show (stream
, "4000", &column
, &first
);
9408 show (stream
, "4010", &column
, &first
);
9409 show (stream
, "4100", &column
, &first
);
9410 show (stream
, "4111", &column
, &first
);
9411 show (stream
, "4300", &column
, &first
);
9412 show (stream
, "4400", &column
, &first
);
9413 show (stream
, "4600", &column
, &first
);
9414 show (stream
, "4650", &column
, &first
);
9415 show (stream
, "5000", &column
, &first
);
9416 show (stream
, "6000", &column
, &first
);
9417 show (stream
, "8000", &column
, &first
);
9418 show (stream
, "10000", &column
, &first
);
9419 show (stream
, "4Kc", &column
, &first
);
9420 show (stream
, "4Kp", &column
, &first
);
9421 show (stream
, "4Km", &column
, &first
);
9422 fputc ('\n', stream
);
9424 fprintf (stream
, _("\
9425 -mCPU equivalent to -mcpu=CPU.\n\
9426 -no-mCPU don't generate code specific to CPU.\n\
9427 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9431 show (stream
, "3900", &column
, &first
);
9432 show (stream
, "4010", &column
, &first
);
9433 show (stream
, "4100", &column
, &first
);
9434 show (stream
, "4650", &column
, &first
);
9435 fputc ('\n', stream
);
9437 fprintf (stream
, _("\
9438 -mips32 generate MIPS32 instructions\n"));
9440 fprintf(stream
, _("\
9441 -mips16 generate mips16 instructions\n\
9442 -no-mips16 do not generate mips16 instructions\n"));
9443 fprintf(stream
, _("\
9444 -O0 remove unneeded NOPs, do not swap branches\n\
9445 -O remove unneeded NOPs and swap branches\n\
9446 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9447 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9448 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9450 fprintf(stream
, _("\
9451 -KPIC, -call_shared generate SVR4 position independent code\n\
9452 -non_shared do not generate position independent code\n\
9453 -xgot assume a 32 bit GOT\n\
9454 -32 create 32 bit object file (default)\n\
9455 -64 create 64 bit object file\n"));
9460 mips_init_after_args ()
9462 /* initialize opcodes */
9463 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9464 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9468 md_pcrel_from (fixP
)
9471 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9472 && fixP
->fx_addsy
!= (symbolS
*) NULL
9473 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9475 /* This makes a branch to an undefined symbol be a branch to the
9476 current location. */
9480 /* return the address of the delay slot */
9481 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9484 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9485 reloc for a cons. We could use the definition there, except that
9486 we want to handle 64 bit relocs specially. */
9489 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9490 fragS
*frag ATTRIBUTE_UNUSED
;
9492 unsigned int nbytes
;
9496 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9498 if (nbytes
== 8 && ! mips_64
)
9500 if (target_big_endian
)
9506 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9507 as_bad (_("Unsupported reloc size %d"), nbytes
);
9509 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9512 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9515 /* This is called before the symbol table is processed. In order to
9516 work with gcc when using mips-tfile, we must keep all local labels.
9517 However, in other cases, we want to discard them. If we were
9518 called with -g, but we didn't see any debugging information, it may
9519 mean that gcc is smuggling debugging information through to
9520 mips-tfile, in which case we must generate all local labels. */
9523 mips_frob_file_before_adjust ()
9525 #ifndef NO_ECOFF_DEBUGGING
9528 && ! ecoff_debugging_seen
)
9529 flag_keep_locals
= 1;
9533 /* Sort any unmatched HI16_S relocs so that they immediately precede
9534 the corresponding LO reloc. This is called before md_apply_fix and
9535 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9536 explicit use of the %hi modifier. */
9541 struct mips_hi_fixup
*l
;
9543 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9545 segment_info_type
*seginfo
;
9548 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9550 /* Check quickly whether the next fixup happens to be a matching
9552 if (l
->fixp
->fx_next
!= NULL
9553 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9554 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9555 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9558 /* Look through the fixups for this segment for a matching %lo.
9559 When we find one, move the %hi just in front of it. We do
9560 this in two passes. In the first pass, we try to find a
9561 unique %lo. In the second pass, we permit multiple %hi
9562 relocs for a single %lo (this is a GNU extension). */
9563 seginfo
= seg_info (l
->seg
);
9564 for (pass
= 0; pass
< 2; pass
++)
9569 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9571 /* Check whether this is a %lo fixup which matches l->fixp. */
9572 if (f
->fx_r_type
== BFD_RELOC_LO16
9573 && f
->fx_addsy
== l
->fixp
->fx_addsy
9574 && f
->fx_offset
== l
->fixp
->fx_offset
9577 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9578 || prev
->fx_addsy
!= f
->fx_addsy
9579 || prev
->fx_offset
!= f
->fx_offset
))
9583 /* Move l->fixp before f. */
9584 for (pf
= &seginfo
->fix_root
;
9586 pf
= &(*pf
)->fx_next
)
9587 assert (*pf
!= NULL
);
9589 *pf
= l
->fixp
->fx_next
;
9591 l
->fixp
->fx_next
= f
;
9593 seginfo
->fix_root
= l
->fixp
;
9595 prev
->fx_next
= l
->fixp
;
9606 #if 0 /* GCC code motion plus incomplete dead code elimination
9607 can leave a %hi without a %lo. */
9609 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9610 _("Unmatched %%hi reloc"));
9616 /* When generating embedded PIC code we need to use a special
9617 relocation to represent the difference of two symbols in the .text
9618 section (switch tables use a difference of this sort). See
9619 include/coff/mips.h for details. This macro checks whether this
9620 fixup requires the special reloc. */
9621 #define SWITCH_TABLE(fixp) \
9622 ((fixp)->fx_r_type == BFD_RELOC_32 \
9623 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9624 && (fixp)->fx_addsy != NULL \
9625 && (fixp)->fx_subsy != NULL \
9626 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9627 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9629 /* When generating embedded PIC code we must keep all PC relative
9630 relocations, in case the linker has to relax a call. We also need
9631 to keep relocations for switch table entries. */
9635 mips_force_relocation (fixp
)
9638 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9639 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9642 return (mips_pic
== EMBEDDED_PIC
9644 || SWITCH_TABLE (fixp
)
9645 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9646 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9649 /* Apply a fixup to the object file. */
9652 md_apply_fix (fixP
, valueP
)
9659 assert (fixP
->fx_size
== 4
9660 || fixP
->fx_r_type
== BFD_RELOC_16
9661 || fixP
->fx_r_type
== BFD_RELOC_64
9662 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9663 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9667 /* If we aren't adjusting this fixup to be against the section
9668 symbol, we need to adjust the value. */
9670 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9672 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9673 || S_IS_WEAK (fixP
->fx_addsy
)
9674 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9675 && (((bfd_get_section_flags (stdoutput
,
9676 S_GET_SEGMENT (fixP
->fx_addsy
))
9677 & SEC_LINK_ONCE
) != 0)
9678 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9680 sizeof (".gnu.linkonce") - 1))))
9683 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9684 if (value
!= 0 && ! fixP
->fx_pcrel
)
9686 /* In this case, the bfd_install_relocation routine will
9687 incorrectly add the symbol value back in. We just want
9688 the addend to appear in the object file.
9689 FIXME: If this makes VALUE zero, we're toast. */
9690 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9694 /* This code was generated using trial and error and so is
9695 fragile and not trustworthy. If you change it, you should
9696 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9698 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9700 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9702 /* BFD's REL handling, for MIPS, is _very_ weird.
9703 This gives the right results, but it can't possibly
9704 be the way things are supposed to work. */
9705 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9706 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9707 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9712 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9714 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9717 switch (fixP
->fx_r_type
)
9719 case BFD_RELOC_MIPS_JMP
:
9720 case BFD_RELOC_HI16
:
9721 case BFD_RELOC_HI16_S
:
9722 case BFD_RELOC_MIPS_GPREL
:
9723 case BFD_RELOC_MIPS_LITERAL
:
9724 case BFD_RELOC_MIPS_CALL16
:
9725 case BFD_RELOC_MIPS_GOT16
:
9726 case BFD_RELOC_MIPS_GPREL32
:
9727 case BFD_RELOC_MIPS_GOT_HI16
:
9728 case BFD_RELOC_MIPS_GOT_LO16
:
9729 case BFD_RELOC_MIPS_CALL_HI16
:
9730 case BFD_RELOC_MIPS_CALL_LO16
:
9731 case BFD_RELOC_MIPS16_GPREL
:
9733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9734 _("Invalid PC relative reloc"));
9735 /* Nothing needed to do. The value comes from the reloc entry */
9738 case BFD_RELOC_MIPS16_JMP
:
9739 /* We currently always generate a reloc against a symbol, which
9740 means that we don't want an addend even if the symbol is
9742 fixP
->fx_addnumber
= 0;
9745 case BFD_RELOC_PCREL_HI16_S
:
9746 /* The addend for this is tricky if it is internal, so we just
9747 do everything here rather than in bfd_install_relocation. */
9748 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9753 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9755 /* For an external symbol adjust by the address to make it
9756 pcrel_offset. We use the address of the RELLO reloc
9757 which follows this one. */
9758 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9759 + fixP
->fx_next
->fx_where
);
9764 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9765 if (target_big_endian
)
9767 md_number_to_chars (buf
, value
, 2);
9770 case BFD_RELOC_PCREL_LO16
:
9771 /* The addend for this is tricky if it is internal, so we just
9772 do everything here rather than in bfd_install_relocation. */
9773 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9778 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9779 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9780 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9781 if (target_big_endian
)
9783 md_number_to_chars (buf
, value
, 2);
9787 /* This is handled like BFD_RELOC_32, but we output a sign
9788 extended value if we are only 32 bits. */
9790 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9792 if (8 <= sizeof (valueT
))
9793 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9800 w1
= w2
= fixP
->fx_where
;
9801 if (target_big_endian
)
9805 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9806 if ((value
& 0x80000000) != 0)
9810 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9817 /* If we are deleting this reloc entry, we must fill in the
9818 value now. This can happen if we have a .word which is not
9819 resolved when it appears but is later defined. We also need
9820 to fill in the value if this is an embedded PIC switch table
9823 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9824 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9829 /* If we are deleting this reloc entry, we must fill in the
9831 assert (fixP
->fx_size
== 2);
9833 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9837 case BFD_RELOC_LO16
:
9838 /* When handling an embedded PIC switch statement, we can wind
9839 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9842 if (value
< -0x8000 || value
> 0x7fff)
9843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9844 _("relocation overflow"));
9845 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9846 if (target_big_endian
)
9848 md_number_to_chars (buf
, value
, 2);
9852 case BFD_RELOC_16_PCREL_S2
:
9854 * We need to save the bits in the instruction since fixup_segment()
9855 * might be deleting the relocation entry (i.e., a branch within
9856 * the current segment).
9858 if ((value
& 0x3) != 0)
9859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9860 _("Branch to odd address (%lx)"), value
);
9862 if (!fixP
->fx_done
&& value
!= 0)
9864 /* If 'value' is zero, the remaining reloc code won't actually
9865 do the store, so it must be done here. This is probably
9868 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9872 /* update old instruction data */
9873 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9874 if (target_big_endian
)
9875 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9877 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9879 if (value
>= -0x8000 && value
< 0x8000)
9880 insn
|= value
& 0xffff;
9883 /* The branch offset is too large. If this is an
9884 unconditional branch, and we are not generating PIC code,
9885 we can convert it to an absolute jump instruction. */
9886 if (mips_pic
== NO_PIC
9888 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9889 && (fixP
->fx_frag
->fr_address
9890 < text_section
->vma
+ text_section
->_raw_size
)
9891 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9892 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9893 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9895 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9896 insn
= 0x0c000000; /* jal */
9898 insn
= 0x08000000; /* j */
9899 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9901 fixP
->fx_addsy
= section_symbol (text_section
);
9902 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9906 /* FIXME. It would be possible in principle to handle
9907 conditional branches which overflow. They could be
9908 transformed into a branch around a jump. This would
9909 require setting up variant frags for each different
9910 branch type. The native MIPS assembler attempts to
9911 handle these cases, but it appears to do it
9913 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9914 _("Branch out of range"));
9918 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9921 case BFD_RELOC_VTABLE_INHERIT
:
9924 && !S_IS_DEFINED (fixP
->fx_addsy
)
9925 && !S_IS_WEAK (fixP
->fx_addsy
))
9926 S_SET_WEAK (fixP
->fx_addsy
);
9929 case BFD_RELOC_VTABLE_ENTRY
:
9945 const struct mips_opcode
*p
;
9946 int treg
, sreg
, dreg
, shamt
;
9951 for (i
= 0; i
< NUMOPCODES
; ++i
)
9953 p
= &mips_opcodes
[i
];
9954 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9956 printf ("%08lx %s\t", oc
, p
->name
);
9957 treg
= (oc
>> 16) & 0x1f;
9958 sreg
= (oc
>> 21) & 0x1f;
9959 dreg
= (oc
>> 11) & 0x1f;
9960 shamt
= (oc
>> 6) & 0x1f;
9962 for (args
= p
->args
;; ++args
)
9973 printf ("%c", *args
);
9977 assert (treg
== sreg
);
9978 printf ("$%d,$%d", treg
, sreg
);
9983 printf ("$%d", dreg
);
9988 printf ("$%d", treg
);
9992 printf ("0x%x", treg
);
9997 printf ("$%d", sreg
);
10001 printf ("0x%08lx", oc
& 0x1ffffff);
10008 printf ("%d", imm
);
10013 printf ("$%d", shamt
);
10024 printf (_("%08lx UNDEFINED\n"), oc
);
10035 name
= input_line_pointer
;
10036 c
= get_symbol_end ();
10037 p
= (symbolS
*) symbol_find_or_make (name
);
10038 *input_line_pointer
= c
;
10042 /* Align the current frag to a given power of two. The MIPS assembler
10043 also automatically adjusts any preceding label. */
10046 mips_align (to
, fill
, label
)
10051 mips_emit_delays (false);
10052 frag_align (to
, fill
, 0);
10053 record_alignment (now_seg
, to
);
10056 assert (S_GET_SEGMENT (label
) == now_seg
);
10057 symbol_set_frag (label
, frag_now
);
10058 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10062 /* Align to a given power of two. .align 0 turns off the automatic
10063 alignment used by the data creating pseudo-ops. */
10067 int x ATTRIBUTE_UNUSED
;
10070 register long temp_fill
;
10071 long max_alignment
= 15;
10075 o Note that the assembler pulls down any immediately preceeding label
10076 to the aligned address.
10077 o It's not documented but auto alignment is reinstated by
10078 a .align pseudo instruction.
10079 o Note also that after auto alignment is turned off the mips assembler
10080 issues an error on attempt to assemble an improperly aligned data item.
10085 temp
= get_absolute_expression ();
10086 if (temp
> max_alignment
)
10087 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10090 as_warn (_("Alignment negative: 0 assumed."));
10093 if (*input_line_pointer
== ',')
10095 input_line_pointer
++;
10096 temp_fill
= get_absolute_expression ();
10103 mips_align (temp
, (int) temp_fill
,
10104 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10111 demand_empty_rest_of_line ();
10115 mips_flush_pending_output ()
10117 mips_emit_delays (false);
10118 mips_clear_insn_labels ();
10127 /* When generating embedded PIC code, we only use the .text, .lit8,
10128 .sdata and .sbss sections. We change the .data and .rdata
10129 pseudo-ops to use .sdata. */
10130 if (mips_pic
== EMBEDDED_PIC
10131 && (sec
== 'd' || sec
== 'r'))
10135 /* The ELF backend needs to know that we are changing sections, so
10136 that .previous works correctly. We could do something like check
10137 for a obj_section_change_hook macro, but that might be confusing
10138 as it would not be appropriate to use it in the section changing
10139 functions in read.c, since obj-elf.c intercepts those. FIXME:
10140 This should be cleaner, somehow. */
10141 obj_elf_section_change_hook ();
10144 mips_emit_delays (false);
10154 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10155 demand_empty_rest_of_line ();
10159 if (USE_GLOBAL_POINTER_OPT
)
10161 seg
= subseg_new (RDATA_SECTION_NAME
,
10162 (subsegT
) get_absolute_expression ());
10163 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10165 bfd_set_section_flags (stdoutput
, seg
,
10171 if (strcmp (TARGET_OS
, "elf") != 0)
10172 record_alignment (seg
, 4);
10174 demand_empty_rest_of_line ();
10178 as_bad (_("No read only data section in this object file format"));
10179 demand_empty_rest_of_line ();
10185 if (USE_GLOBAL_POINTER_OPT
)
10187 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10188 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10190 bfd_set_section_flags (stdoutput
, seg
,
10191 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10193 if (strcmp (TARGET_OS
, "elf") != 0)
10194 record_alignment (seg
, 4);
10196 demand_empty_rest_of_line ();
10201 as_bad (_("Global pointers not supported; recompile -G 0"));
10202 demand_empty_rest_of_line ();
10211 mips_enable_auto_align ()
10222 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10223 mips_emit_delays (false);
10224 if (log_size
> 0 && auto_align
)
10225 mips_align (log_size
, 0, label
);
10226 mips_clear_insn_labels ();
10227 cons (1 << log_size
);
10231 s_float_cons (type
)
10236 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10238 mips_emit_delays (false);
10243 mips_align (3, 0, label
);
10245 mips_align (2, 0, label
);
10248 mips_clear_insn_labels ();
10253 /* Handle .globl. We need to override it because on Irix 5 you are
10256 where foo is an undefined symbol, to mean that foo should be
10257 considered to be the address of a function. */
10261 int x ATTRIBUTE_UNUSED
;
10268 name
= input_line_pointer
;
10269 c
= get_symbol_end ();
10270 symbolP
= symbol_find_or_make (name
);
10271 *input_line_pointer
= c
;
10272 SKIP_WHITESPACE ();
10274 /* On Irix 5, every global symbol that is not explicitly labelled as
10275 being a function is apparently labelled as being an object. */
10278 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10283 secname
= input_line_pointer
;
10284 c
= get_symbol_end ();
10285 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10287 as_bad (_("%s: no such section"), secname
);
10288 *input_line_pointer
= c
;
10290 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10291 flag
= BSF_FUNCTION
;
10294 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10296 S_SET_EXTERNAL (symbolP
);
10297 demand_empty_rest_of_line ();
10302 int x ATTRIBUTE_UNUSED
;
10307 opt
= input_line_pointer
;
10308 c
= get_symbol_end ();
10312 /* FIXME: What does this mean? */
10314 else if (strncmp (opt
, "pic", 3) == 0)
10318 i
= atoi (opt
+ 3);
10322 mips_pic
= SVR4_PIC
;
10324 as_bad (_(".option pic%d not supported"), i
);
10326 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10328 if (g_switch_seen
&& g_switch_value
!= 0)
10329 as_warn (_("-G may not be used with SVR4 PIC code"));
10330 g_switch_value
= 0;
10331 bfd_set_gp_size (stdoutput
, 0);
10335 as_warn (_("Unrecognized option \"%s\""), opt
);
10337 *input_line_pointer
= c
;
10338 demand_empty_rest_of_line ();
10341 /* This structure is used to hold a stack of .set values. */
10343 struct mips_option_stack
10345 struct mips_option_stack
*next
;
10346 struct mips_set_options options
;
10349 static struct mips_option_stack
*mips_opts_stack
;
10351 /* Handle the .set pseudo-op. */
10355 int x ATTRIBUTE_UNUSED
;
10357 char *name
= input_line_pointer
, ch
;
10359 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10360 input_line_pointer
++;
10361 ch
= *input_line_pointer
;
10362 *input_line_pointer
= '\0';
10364 if (strcmp (name
, "reorder") == 0)
10366 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10368 /* If we still have pending nops, we can discard them. The
10369 usual nop handling will insert any that are still
10371 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10372 * (mips_opts
.mips16
? 2 : 4));
10373 prev_nop_frag
= NULL
;
10375 mips_opts
.noreorder
= 0;
10377 else if (strcmp (name
, "noreorder") == 0)
10379 mips_emit_delays (true);
10380 mips_opts
.noreorder
= 1;
10381 mips_any_noreorder
= 1;
10383 else if (strcmp (name
, "at") == 0)
10385 mips_opts
.noat
= 0;
10387 else if (strcmp (name
, "noat") == 0)
10389 mips_opts
.noat
= 1;
10391 else if (strcmp (name
, "macro") == 0)
10393 mips_opts
.warn_about_macros
= 0;
10395 else if (strcmp (name
, "nomacro") == 0)
10397 if (mips_opts
.noreorder
== 0)
10398 as_bad (_("`noreorder' must be set before `nomacro'"));
10399 mips_opts
.warn_about_macros
= 1;
10401 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10403 mips_opts
.nomove
= 0;
10405 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10407 mips_opts
.nomove
= 1;
10409 else if (strcmp (name
, "bopt") == 0)
10411 mips_opts
.nobopt
= 0;
10413 else if (strcmp (name
, "nobopt") == 0)
10415 mips_opts
.nobopt
= 1;
10417 else if (strcmp (name
, "mips16") == 0
10418 || strcmp (name
, "MIPS-16") == 0)
10419 mips_opts
.mips16
= 1;
10420 else if (strcmp (name
, "nomips16") == 0
10421 || strcmp (name
, "noMIPS-16") == 0)
10422 mips_opts
.mips16
= 0;
10423 else if (strncmp (name
, "mips", 4) == 0)
10427 /* Permit the user to change the ISA on the fly. Needless to
10428 say, misuse can cause serious problems. */
10429 isa
= atoi (name
+ 4);
10431 mips_opts
.isa
= file_mips_isa
;
10432 else if (isa
< 1 || isa
> 4)
10433 as_bad (_("unknown ISA level"));
10435 mips_opts
.isa
= isa
;
10437 else if (strcmp (name
, "autoextend") == 0)
10438 mips_opts
.noautoextend
= 0;
10439 else if (strcmp (name
, "noautoextend") == 0)
10440 mips_opts
.noautoextend
= 1;
10441 else if (strcmp (name
, "push") == 0)
10443 struct mips_option_stack
*s
;
10445 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10446 s
->next
= mips_opts_stack
;
10447 s
->options
= mips_opts
;
10448 mips_opts_stack
= s
;
10450 else if (strcmp (name
, "pop") == 0)
10452 struct mips_option_stack
*s
;
10454 s
= mips_opts_stack
;
10456 as_bad (_(".set pop with no .set push"));
10459 /* If we're changing the reorder mode we need to handle
10460 delay slots correctly. */
10461 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10462 mips_emit_delays (true);
10463 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10465 if (prev_nop_frag
!= NULL
)
10467 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10468 * (mips_opts
.mips16
? 2 : 4));
10469 prev_nop_frag
= NULL
;
10473 mips_opts
= s
->options
;
10474 mips_opts_stack
= s
->next
;
10480 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10482 *input_line_pointer
= ch
;
10483 demand_empty_rest_of_line ();
10486 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10487 .option pic2. It means to generate SVR4 PIC calls. */
10490 s_abicalls (ignore
)
10491 int ignore ATTRIBUTE_UNUSED
;
10493 mips_pic
= SVR4_PIC
;
10494 if (USE_GLOBAL_POINTER_OPT
)
10496 if (g_switch_seen
&& g_switch_value
!= 0)
10497 as_warn (_("-G may not be used with SVR4 PIC code"));
10498 g_switch_value
= 0;
10500 bfd_set_gp_size (stdoutput
, 0);
10501 demand_empty_rest_of_line ();
10504 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10505 PIC code. It sets the $gp register for the function based on the
10506 function address, which is in the register named in the argument.
10507 This uses a relocation against _gp_disp, which is handled specially
10508 by the linker. The result is:
10509 lui $gp,%hi(_gp_disp)
10510 addiu $gp,$gp,%lo(_gp_disp)
10511 addu $gp,$gp,.cpload argument
10512 The .cpload argument is normally $25 == $t9. */
10516 int ignore ATTRIBUTE_UNUSED
;
10521 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10522 if (mips_pic
!= SVR4_PIC
)
10528 /* .cpload should be a in .set noreorder section. */
10529 if (mips_opts
.noreorder
== 0)
10530 as_warn (_(".cpload not in noreorder section"));
10532 ex
.X_op
= O_symbol
;
10533 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10534 ex
.X_op_symbol
= NULL
;
10535 ex
.X_add_number
= 0;
10537 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10538 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10540 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10541 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10542 (int) BFD_RELOC_LO16
);
10544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10545 GP
, GP
, tc_get_register (0));
10547 demand_empty_rest_of_line ();
10550 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10551 offset from $sp. The offset is remembered, and after making a PIC
10552 call $gp is restored from that location. */
10555 s_cprestore (ignore
)
10556 int ignore ATTRIBUTE_UNUSED
;
10561 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10562 if (mips_pic
!= SVR4_PIC
)
10568 mips_cprestore_offset
= get_absolute_expression ();
10570 ex
.X_op
= O_constant
;
10571 ex
.X_add_symbol
= NULL
;
10572 ex
.X_op_symbol
= NULL
;
10573 ex
.X_add_number
= mips_cprestore_offset
;
10575 macro_build ((char *) NULL
, &icnt
, &ex
,
10576 ((bfd_arch_bits_per_address (stdoutput
) == 32
10577 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10579 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10581 demand_empty_rest_of_line ();
10584 /* Handle the .gpword pseudo-op. This is used when generating PIC
10585 code. It generates a 32 bit GP relative reloc. */
10589 int ignore ATTRIBUTE_UNUSED
;
10595 /* When not generating PIC code, this is treated as .word. */
10596 if (mips_pic
!= SVR4_PIC
)
10602 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10603 mips_emit_delays (true);
10605 mips_align (2, 0, label
);
10606 mips_clear_insn_labels ();
10610 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10612 as_bad (_("Unsupported use of .gpword"));
10613 ignore_rest_of_line ();
10617 md_number_to_chars (p
, (valueT
) 0, 4);
10618 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10619 BFD_RELOC_MIPS_GPREL32
);
10621 demand_empty_rest_of_line ();
10624 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10625 tables in SVR4 PIC code. */
10629 int ignore ATTRIBUTE_UNUSED
;
10634 /* This is ignored when not generating SVR4 PIC code. */
10635 if (mips_pic
!= SVR4_PIC
)
10641 /* Add $gp to the register named as an argument. */
10642 reg
= tc_get_register (0);
10643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10644 ((bfd_arch_bits_per_address (stdoutput
) == 32
10645 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10646 ? "addu" : "daddu"),
10647 "d,v,t", reg
, reg
, GP
);
10649 demand_empty_rest_of_line ();
10652 /* Handle the .insn pseudo-op. This marks instruction labels in
10653 mips16 mode. This permits the linker to handle them specially,
10654 such as generating jalx instructions when needed. We also make
10655 them odd for the duration of the assembly, in order to generate the
10656 right sort of code. We will make them even in the adjust_symtab
10657 routine, while leaving them marked. This is convenient for the
10658 debugger and the disassembler. The linker knows to make them odd
10663 int ignore ATTRIBUTE_UNUSED
;
10665 if (mips_opts
.mips16
)
10666 mips16_mark_labels ();
10668 demand_empty_rest_of_line ();
10671 /* Handle a .stabn directive. We need these in order to mark a label
10672 as being a mips16 text label correctly. Sometimes the compiler
10673 will emit a label, followed by a .stabn, and then switch sections.
10674 If the label and .stabn are in mips16 mode, then the label is
10675 really a mips16 text label. */
10681 if (type
== 'n' && mips_opts
.mips16
)
10682 mips16_mark_labels ();
10687 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10691 s_mips_weakext (ignore
)
10692 int ignore ATTRIBUTE_UNUSED
;
10699 name
= input_line_pointer
;
10700 c
= get_symbol_end ();
10701 symbolP
= symbol_find_or_make (name
);
10702 S_SET_WEAK (symbolP
);
10703 *input_line_pointer
= c
;
10705 SKIP_WHITESPACE ();
10707 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10709 if (S_IS_DEFINED (symbolP
))
10711 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10712 S_GET_NAME (symbolP
));
10713 ignore_rest_of_line ();
10717 if (*input_line_pointer
== ',')
10719 ++input_line_pointer
;
10720 SKIP_WHITESPACE ();
10724 if (exp
.X_op
!= O_symbol
)
10726 as_bad ("bad .weakext directive");
10727 ignore_rest_of_line();
10730 symbol_set_value_expression (symbolP
, &exp
);
10733 demand_empty_rest_of_line ();
10736 /* Parse a register string into a number. Called from the ECOFF code
10737 to parse .frame. The argument is non-zero if this is the frame
10738 register, so that we can record it in mips_frame_reg. */
10741 tc_get_register (frame
)
10746 SKIP_WHITESPACE ();
10747 if (*input_line_pointer
++ != '$')
10749 as_warn (_("expected `$'"));
10752 else if (isdigit ((unsigned char) *input_line_pointer
))
10754 reg
= get_absolute_expression ();
10755 if (reg
< 0 || reg
>= 32)
10757 as_warn (_("Bad register number"));
10763 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10765 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10767 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10769 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10773 as_warn (_("Unrecognized register name"));
10776 input_line_pointer
+= 2;
10779 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10784 md_section_align (seg
, addr
)
10788 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10791 /* We don't need to align ELF sections to the full alignment.
10792 However, Irix 5 may prefer that we align them at least to a 16
10793 byte boundary. We don't bother to align the sections if we are
10794 targeted for an embedded system. */
10795 if (strcmp (TARGET_OS
, "elf") == 0)
10801 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10804 /* Utility routine, called from above as well. If called while the
10805 input file is still being read, it's only an approximation. (For
10806 example, a symbol may later become defined which appeared to be
10807 undefined earlier.) */
10810 nopic_need_relax (sym
, before_relaxing
)
10812 int before_relaxing
;
10817 if (USE_GLOBAL_POINTER_OPT
)
10819 const char *symname
;
10822 /* Find out whether this symbol can be referenced off the GP
10823 register. It can be if it is smaller than the -G size or if
10824 it is in the .sdata or .sbss section. Certain symbols can
10825 not be referenced off the GP, although it appears as though
10827 symname
= S_GET_NAME (sym
);
10828 if (symname
!= (const char *) NULL
10829 && (strcmp (symname
, "eprol") == 0
10830 || strcmp (symname
, "etext") == 0
10831 || strcmp (symname
, "_gp") == 0
10832 || strcmp (symname
, "edata") == 0
10833 || strcmp (symname
, "_fbss") == 0
10834 || strcmp (symname
, "_fdata") == 0
10835 || strcmp (symname
, "_ftext") == 0
10836 || strcmp (symname
, "end") == 0
10837 || strcmp (symname
, "_gp_disp") == 0))
10839 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10841 #ifndef NO_ECOFF_DEBUGGING
10842 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10843 && (symbol_get_obj (sym
)->ecoff_extern_size
10844 <= g_switch_value
))
10846 /* We must defer this decision until after the whole
10847 file has been read, since there might be a .extern
10848 after the first use of this symbol. */
10849 || (before_relaxing
10850 #ifndef NO_ECOFF_DEBUGGING
10851 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10853 && S_GET_VALUE (sym
) == 0)
10854 || (S_GET_VALUE (sym
) != 0
10855 && S_GET_VALUE (sym
) <= g_switch_value
)))
10859 const char *segname
;
10861 segname
= segment_name (S_GET_SEGMENT (sym
));
10862 assert (strcmp (segname
, ".lit8") != 0
10863 && strcmp (segname
, ".lit4") != 0);
10864 change
= (strcmp (segname
, ".sdata") != 0
10865 && strcmp (segname
, ".sbss") != 0
10866 && strncmp (segname
, ".sdata.", 7) != 0
10867 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10872 /* We are not optimizing for the GP register. */
10876 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10877 extended opcode. SEC is the section the frag is in. */
10880 mips16_extended_frag (fragp
, sec
, stretch
)
10886 register const struct mips16_immed_operand
*op
;
10888 int mintiny
, maxtiny
;
10891 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10893 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10896 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10897 op
= mips16_immed_operands
;
10898 while (op
->type
!= type
)
10901 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10906 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10909 maxtiny
= 1 << op
->nbits
;
10914 maxtiny
= (1 << op
->nbits
) - 1;
10919 mintiny
= - (1 << (op
->nbits
- 1));
10920 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10923 /* We can't always call S_GET_VALUE here, because we don't want to
10924 lock in a particular frag address. */
10925 if (symbol_constant_p (fragp
->fr_symbol
))
10927 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10928 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10929 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10931 else if (symbol_equated_p (fragp
->fr_symbol
)
10932 && (symbol_constant_p
10933 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10937 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10938 val
= (S_GET_VALUE (eqsym
)
10939 + symbol_get_frag (eqsym
)->fr_address
10940 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10941 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10942 symsec
= S_GET_SEGMENT (eqsym
);
10951 /* We won't have the section when we are called from
10952 mips_relax_frag. However, we will always have been called
10953 from md_estimate_size_before_relax first. If this is a
10954 branch to a different section, we mark it as such. If SEC is
10955 NULL, and the frag is not marked, then it must be a branch to
10956 the same section. */
10959 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10966 fragp
->fr_subtype
=
10967 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10969 /* FIXME: We should support this, and let the linker
10970 catch branches and loads that are out of range. */
10971 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10972 _("unsupported PC relative reference to different section"));
10978 /* In this case, we know for sure that the symbol fragment is in
10979 the same section. If the fr_address of the symbol fragment
10980 is greater then the address of this fragment we want to add
10981 in STRETCH in order to get a better estimate of the address.
10982 This particularly matters because of the shift bits. */
10984 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10985 >= fragp
->fr_address
))
10989 /* Adjust stretch for any alignment frag. Note that if have
10990 been expanding the earlier code, the symbol may be
10991 defined in what appears to be an earlier frag. FIXME:
10992 This doesn't handle the fr_subtype field, which specifies
10993 a maximum number of bytes to skip when doing an
10996 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10999 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11002 stretch
= - ((- stretch
)
11003 & ~ ((1 << (int) f
->fr_offset
) - 1));
11005 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11014 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11016 /* The base address rules are complicated. The base address of
11017 a branch is the following instruction. The base address of a
11018 PC relative load or add is the instruction itself, but if it
11019 is in a delay slot (in which case it can not be extended) use
11020 the address of the instruction whose delay slot it is in. */
11021 if (type
== 'p' || type
== 'q')
11025 /* If we are currently assuming that this frag should be
11026 extended, then, the current address is two bytes
11028 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11031 /* Ignore the low bit in the target, since it will be set
11032 for a text label. */
11033 if ((val
& 1) != 0)
11036 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11038 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11041 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11043 /* Branch offsets have an implicit 0 in the lowest bit. */
11044 if (type
== 'p' || type
== 'q')
11047 /* If any of the shifted bits are set, we must use an extended
11048 opcode. If the address depends on the size of this
11049 instruction, this can lead to a loop, so we arrange to always
11050 use an extended opcode. We only check this when we are in
11051 the main relaxation loop, when SEC is NULL. */
11052 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11054 fragp
->fr_subtype
=
11055 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11059 /* If we are about to mark a frag as extended because the value
11060 is precisely maxtiny + 1, then there is a chance of an
11061 infinite loop as in the following code:
11066 In this case when the la is extended, foo is 0x3fc bytes
11067 away, so the la can be shrunk, but then foo is 0x400 away, so
11068 the la must be extended. To avoid this loop, we mark the
11069 frag as extended if it was small, and is about to become
11070 extended with a value of maxtiny + 1. */
11071 if (val
== ((maxtiny
+ 1) << op
->shift
)
11072 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11075 fragp
->fr_subtype
=
11076 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11080 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11081 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11083 if ((val
& ((1 << op
->shift
) - 1)) != 0
11084 || val
< (mintiny
<< op
->shift
)
11085 || val
> (maxtiny
<< op
->shift
))
11091 /* Estimate the size of a frag before relaxing. Unless this is the
11092 mips16, we are not really relaxing here, and the final size is
11093 encoded in the subtype information. For the mips16, we have to
11094 decide whether we are using an extended opcode or not. */
11098 md_estimate_size_before_relax (fragp
, segtype
)
11103 boolean linkonce
= false;
11105 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11107 if (mips16_extended_frag (fragp
, segtype
, 0))
11109 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11114 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11119 if (mips_pic
== NO_PIC
)
11121 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11123 else if (mips_pic
== SVR4_PIC
)
11128 sym
= fragp
->fr_symbol
;
11130 /* Handle the case of a symbol equated to another symbol. */
11131 while (symbol_equated_p (sym
)
11132 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11136 /* It's possible to get a loop here in a badly written
11138 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11144 symsec
= S_GET_SEGMENT (sym
);
11146 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11147 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11149 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11153 /* The GNU toolchain uses an extension for ELF: a section
11154 beginning with the magic string .gnu.linkonce is a linkonce
11156 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11157 sizeof ".gnu.linkonce" - 1) == 0)
11161 /* This must duplicate the test in adjust_reloc_syms. */
11162 change
= (symsec
!= &bfd_und_section
11163 && symsec
!= &bfd_abs_section
11164 && ! bfd_is_com_section (symsec
)
11167 /* A weak symbol is treated as external. */
11168 && ! S_IS_WEAK (sym
)
11177 /* Record the offset to the first reloc in the fr_opcode field.
11178 This lets md_convert_frag and tc_gen_reloc know that the code
11179 must be expanded. */
11180 fragp
->fr_opcode
= (fragp
->fr_literal
11182 - RELAX_OLD (fragp
->fr_subtype
)
11183 + RELAX_RELOC1 (fragp
->fr_subtype
));
11184 /* FIXME: This really needs as_warn_where. */
11185 if (RELAX_WARN (fragp
->fr_subtype
))
11186 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11192 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11195 /* This is called to see whether a reloc against a defined symbol
11196 should be converted into a reloc against a section. Don't adjust
11197 MIPS16 jump relocations, so we don't have to worry about the format
11198 of the offset in the .o file. Don't adjust relocations against
11199 mips16 symbols, so that the linker can find them if it needs to set
11203 mips_fix_adjustable (fixp
)
11206 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11208 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11209 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11211 if (fixp
->fx_addsy
== NULL
)
11214 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11215 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11216 && fixp
->fx_subsy
== NULL
)
11222 /* Translate internal representation of relocation info to BFD target
11226 tc_gen_reloc (section
, fixp
)
11227 asection
*section ATTRIBUTE_UNUSED
;
11230 static arelent
*retval
[4];
11232 bfd_reloc_code_real_type code
;
11234 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11237 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11238 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11239 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11241 if (mips_pic
== EMBEDDED_PIC
11242 && SWITCH_TABLE (fixp
))
11244 /* For a switch table entry we use a special reloc. The addend
11245 is actually the difference between the reloc address and the
11247 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11248 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11249 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11250 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11252 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11253 reloc
->addend
= fixp
->fx_addnumber
;
11254 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11256 /* We use a special addend for an internal RELLO reloc. */
11257 if (symbol_section_p (fixp
->fx_addsy
))
11258 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11260 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11262 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11264 assert (fixp
->fx_next
!= NULL
11265 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11266 /* We use a special addend for an internal RELHI reloc. The
11267 reloc is relative to the RELLO; adjust the addend
11269 if (symbol_section_p (fixp
->fx_addsy
))
11270 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11271 + fixp
->fx_next
->fx_where
11272 - S_GET_VALUE (fixp
->fx_subsy
));
11274 reloc
->addend
= (fixp
->fx_addnumber
11275 + fixp
->fx_next
->fx_frag
->fr_address
11276 + fixp
->fx_next
->fx_where
);
11280 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11281 /* A gruesome hack which is a result of the gruesome gas reloc
11283 reloc
->addend
= reloc
->address
;
11285 reloc
->addend
= -reloc
->address
;
11288 /* If this is a variant frag, we may need to adjust the existing
11289 reloc and generate a new one. */
11290 if (fixp
->fx_frag
->fr_opcode
!= NULL
11291 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11292 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11293 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11294 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11295 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11296 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11297 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11301 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11303 /* If this is not the last reloc in this frag, then we have two
11304 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11305 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11306 the second one handle all of them. */
11307 if (fixp
->fx_next
!= NULL
11308 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11310 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11311 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11312 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11313 && (fixp
->fx_next
->fx_r_type
11314 == BFD_RELOC_MIPS_GOT_LO16
))
11315 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11316 && (fixp
->fx_next
->fx_r_type
11317 == BFD_RELOC_MIPS_CALL_LO16
)));
11322 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11323 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11324 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11326 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11327 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11328 reloc2
->address
= (reloc
->address
11329 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11330 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11331 reloc2
->addend
= fixp
->fx_addnumber
;
11332 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11333 assert (reloc2
->howto
!= NULL
);
11335 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11339 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11342 reloc3
->address
+= 4;
11345 if (mips_pic
== NO_PIC
)
11347 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11348 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11350 else if (mips_pic
== SVR4_PIC
)
11352 switch (fixp
->fx_r_type
)
11356 case BFD_RELOC_MIPS_GOT16
:
11358 case BFD_RELOC_MIPS_CALL16
:
11359 case BFD_RELOC_MIPS_GOT_LO16
:
11360 case BFD_RELOC_MIPS_CALL_LO16
:
11361 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11369 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11370 to be used in the relocation's section offset. */
11371 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11373 reloc
->address
= reloc
->addend
;
11377 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11378 fixup_segment converted a non-PC relative reloc into a PC
11379 relative reloc. In such a case, we need to convert the reloc
11381 code
= fixp
->fx_r_type
;
11382 if (fixp
->fx_pcrel
)
11387 code
= BFD_RELOC_8_PCREL
;
11390 code
= BFD_RELOC_16_PCREL
;
11393 code
= BFD_RELOC_32_PCREL
;
11396 code
= BFD_RELOC_64_PCREL
;
11398 case BFD_RELOC_8_PCREL
:
11399 case BFD_RELOC_16_PCREL
:
11400 case BFD_RELOC_32_PCREL
:
11401 case BFD_RELOC_64_PCREL
:
11402 case BFD_RELOC_16_PCREL_S2
:
11403 case BFD_RELOC_PCREL_HI16_S
:
11404 case BFD_RELOC_PCREL_LO16
:
11407 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11408 _("Cannot make %s relocation PC relative"),
11409 bfd_get_reloc_code_name (code
));
11413 /* To support a PC relative reloc when generating embedded PIC code
11414 for ECOFF, we use a Cygnus extension. We check for that here to
11415 make sure that we don't let such a reloc escape normally. */
11416 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11417 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11418 && code
== BFD_RELOC_16_PCREL_S2
11419 && mips_pic
!= EMBEDDED_PIC
)
11420 reloc
->howto
= NULL
;
11422 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11424 if (reloc
->howto
== NULL
)
11426 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11427 _("Can not represent %s relocation in this object file format"),
11428 bfd_get_reloc_code_name (code
));
11435 /* Relax a machine dependent frag. This returns the amount by which
11436 the current size of the frag should change. */
11439 mips_relax_frag (fragp
, stretch
)
11443 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11446 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11448 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11450 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11455 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11457 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11464 /* Convert a machine dependent frag. */
11467 md_convert_frag (abfd
, asec
, fragp
)
11468 bfd
*abfd ATTRIBUTE_UNUSED
;
11475 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11478 register const struct mips16_immed_operand
*op
;
11479 boolean small
, ext
;
11482 unsigned long insn
;
11483 boolean use_extend
;
11484 unsigned short extend
;
11486 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11487 op
= mips16_immed_operands
;
11488 while (op
->type
!= type
)
11491 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11502 resolve_symbol_value (fragp
->fr_symbol
, 1);
11503 val
= S_GET_VALUE (fragp
->fr_symbol
);
11508 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11510 /* The rules for the base address of a PC relative reloc are
11511 complicated; see mips16_extended_frag. */
11512 if (type
== 'p' || type
== 'q')
11517 /* Ignore the low bit in the target, since it will be
11518 set for a text label. */
11519 if ((val
& 1) != 0)
11522 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11524 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11527 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11530 /* Make sure the section winds up with the alignment we have
11533 record_alignment (asec
, op
->shift
);
11537 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11538 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11539 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11540 _("extended instruction in delay slot"));
11542 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11544 if (target_big_endian
)
11545 insn
= bfd_getb16 (buf
);
11547 insn
= bfd_getl16 (buf
);
11549 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11550 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11551 small
, ext
, &insn
, &use_extend
, &extend
);
11555 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11556 fragp
->fr_fix
+= 2;
11560 md_number_to_chars (buf
, insn
, 2);
11561 fragp
->fr_fix
+= 2;
11566 if (fragp
->fr_opcode
== NULL
)
11569 old
= RELAX_OLD (fragp
->fr_subtype
);
11570 new = RELAX_NEW (fragp
->fr_subtype
);
11571 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11574 memcpy (fixptr
- old
, fixptr
, new);
11576 fragp
->fr_fix
+= new - old
;
11582 /* This function is called after the relocs have been generated.
11583 We've been storing mips16 text labels as odd. Here we convert them
11584 back to even for the convenience of the debugger. */
11587 mips_frob_file_after_relocs ()
11590 unsigned int count
, i
;
11592 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11595 syms
= bfd_get_outsymbols (stdoutput
);
11596 count
= bfd_get_symcount (stdoutput
);
11597 for (i
= 0; i
< count
; i
++, syms
++)
11599 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11600 && ((*syms
)->value
& 1) != 0)
11602 (*syms
)->value
&= ~1;
11603 /* If the symbol has an odd size, it was probably computed
11604 incorrectly, so adjust that as well. */
11605 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11606 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11613 /* This function is called whenever a label is defined. It is used
11614 when handling branch delays; if a branch has a label, we assume we
11615 can not move it. */
11618 mips_define_label (sym
)
11621 struct insn_label_list
*l
;
11623 if (free_insn_labels
== NULL
)
11624 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11627 l
= free_insn_labels
;
11628 free_insn_labels
= l
->next
;
11632 l
->next
= insn_labels
;
11636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11638 /* Some special processing for a MIPS ELF file. */
11641 mips_elf_final_processing ()
11643 /* Write out the register information. */
11648 s
.ri_gprmask
= mips_gprmask
;
11649 s
.ri_cprmask
[0] = mips_cprmask
[0];
11650 s
.ri_cprmask
[1] = mips_cprmask
[1];
11651 s
.ri_cprmask
[2] = mips_cprmask
[2];
11652 s
.ri_cprmask
[3] = mips_cprmask
[3];
11653 /* The gp_value field is set by the MIPS ELF backend. */
11655 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11656 ((Elf32_External_RegInfo
*)
11657 mips_regmask_frag
));
11661 Elf64_Internal_RegInfo s
;
11663 s
.ri_gprmask
= mips_gprmask
;
11665 s
.ri_cprmask
[0] = mips_cprmask
[0];
11666 s
.ri_cprmask
[1] = mips_cprmask
[1];
11667 s
.ri_cprmask
[2] = mips_cprmask
[2];
11668 s
.ri_cprmask
[3] = mips_cprmask
[3];
11669 /* The gp_value field is set by the MIPS ELF backend. */
11671 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11672 ((Elf64_External_RegInfo
*)
11673 mips_regmask_frag
));
11676 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11677 sort of BFD interface for this. */
11678 if (mips_any_noreorder
)
11679 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11680 if (mips_pic
!= NO_PIC
)
11681 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11683 /* Set the MIPS ELF ABI flags. */
11684 if (mips_abi_string
== 0)
11686 else if (strcmp (mips_abi_string
,"32") == 0)
11687 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11688 else if (strcmp (mips_abi_string
,"o64") == 0)
11689 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11690 else if (strcmp (mips_abi_string
,"eabi") == 0)
11693 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11695 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11698 if (mips_32bitmode
)
11699 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11702 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11704 typedef struct proc
11707 unsigned long reg_mask
;
11708 unsigned long reg_offset
;
11709 unsigned long fpreg_mask
;
11710 unsigned long fpreg_offset
;
11711 unsigned long frame_offset
;
11712 unsigned long frame_reg
;
11713 unsigned long pc_reg
;
11717 static procS cur_proc
;
11718 static procS
*cur_proc_ptr
;
11719 static int numprocs
;
11721 /* When we align code in the .text section of mips16, use the correct two
11722 byte nop pattern of 0x6500 (move $0,$0) */
11725 mips_do_align (n
, fill
, len
, max
)
11728 int len ATTRIBUTE_UNUSED
;
11732 && subseg_text_p (now_seg
)
11734 && mips_opts
.mips16
)
11736 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11737 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11739 frag_align (1, 0, 0);
11741 if (target_big_endian
)
11742 frag_align_pattern (n
, be_nop
, 2, max
);
11744 frag_align_pattern (n
, le_nop
, 2, max
);
11759 /* check for premature end, nesting errors, etc */
11761 as_warn (_("missing `.end' at end of assembly"));
11770 if (*input_line_pointer
== '-')
11772 ++input_line_pointer
;
11775 if (!isdigit ((unsigned char) *input_line_pointer
))
11776 as_bad (_("Expected simple number."));
11777 if (input_line_pointer
[0] == '0')
11779 if (input_line_pointer
[1] == 'x')
11781 input_line_pointer
+= 2;
11782 while (isxdigit ((unsigned char) *input_line_pointer
))
11785 val
|= hex_value (*input_line_pointer
++);
11787 return negative
? -val
: val
;
11791 ++input_line_pointer
;
11792 while (isdigit ((unsigned char) *input_line_pointer
))
11795 val
|= *input_line_pointer
++ - '0';
11797 return negative
? -val
: val
;
11800 if (!isdigit ((unsigned char) *input_line_pointer
))
11802 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11803 *input_line_pointer
, *input_line_pointer
);
11804 as_warn (_("Invalid number"));
11807 while (isdigit ((unsigned char) *input_line_pointer
))
11810 val
+= *input_line_pointer
++ - '0';
11812 return negative
? -val
: val
;
11815 /* The .file directive; just like the usual .file directive, but there
11816 is an initial number which is the ECOFF file index. */
11820 int x ATTRIBUTE_UNUSED
;
11824 line
= get_number ();
11828 /* The .end directive. */
11832 int x ATTRIBUTE_UNUSED
;
11837 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11840 demand_empty_rest_of_line ();
11845 #ifdef BFD_ASSEMBLER
11846 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11851 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11858 as_warn (_(".end not in text section"));
11862 as_warn (_(".end directive without a preceding .ent directive."));
11863 demand_empty_rest_of_line ();
11869 assert (S_GET_NAME (p
));
11870 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11871 as_warn (_(".end symbol does not match .ent symbol."));
11874 as_warn (_(".end directive missing or unknown symbol"));
11876 #ifdef MIPS_STABS_ELF
11878 segT saved_seg
= now_seg
;
11879 subsegT saved_subseg
= now_subseg
;
11880 fragS
*saved_frag
= frag_now
;
11886 dot
= frag_now_fix ();
11888 #ifdef md_flush_pending_output
11889 md_flush_pending_output ();
11893 subseg_set (pdr_seg
, 0);
11895 /* Write the symbol */
11896 exp
.X_op
= O_symbol
;
11897 exp
.X_add_symbol
= p
;
11898 exp
.X_add_number
= 0;
11899 emit_expr (&exp
, 4);
11901 fragp
= frag_more (7*4);
11903 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11904 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11905 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11906 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11907 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11908 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11909 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11911 subseg_set (saved_seg
, saved_subseg
);
11915 cur_proc_ptr
= NULL
;
11918 /* The .aent and .ent directives. */
11928 symbolP
= get_symbol ();
11929 if (*input_line_pointer
== ',')
11930 input_line_pointer
++;
11931 SKIP_WHITESPACE ();
11932 if (isdigit ((unsigned char) *input_line_pointer
)
11933 || *input_line_pointer
== '-')
11934 number
= get_number ();
11936 #ifdef BFD_ASSEMBLER
11937 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11942 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11949 as_warn (_(".ent or .aent not in text section."));
11951 if (!aent
&& cur_proc_ptr
)
11952 as_warn (_("missing `.end'"));
11956 cur_proc_ptr
= &cur_proc
;
11957 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11959 cur_proc_ptr
->isym
= symbolP
;
11961 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11966 demand_empty_rest_of_line ();
11969 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11970 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11971 s_mips_frame is used so that we can set the PDR information correctly.
11972 We can't use the ecoff routines because they make reference to the ecoff
11973 symbol table (in the mdebug section). */
11976 s_mips_frame (ignore
)
11979 #ifdef MIPS_STABS_ELF
11983 if (cur_proc_ptr
== (procS
*) NULL
)
11985 as_warn (_(".frame outside of .ent"));
11986 demand_empty_rest_of_line ();
11990 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11992 SKIP_WHITESPACE ();
11993 if (*input_line_pointer
++ != ','
11994 || get_absolute_expression_and_terminator (&val
) != ',')
11996 as_warn (_("Bad .frame directive"));
11997 --input_line_pointer
;
11998 demand_empty_rest_of_line ();
12002 cur_proc_ptr
->frame_offset
= val
;
12003 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12005 demand_empty_rest_of_line ();
12008 #endif /* MIPS_STABS_ELF */
12011 /* The .fmask and .mask directives. If the mdebug section is present
12012 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12013 embedded targets, s_mips_mask is used so that we can set the PDR
12014 information correctly. We can't use the ecoff routines because they
12015 make reference to the ecoff symbol table (in the mdebug section). */
12018 s_mips_mask (reg_type
)
12021 #ifdef MIPS_STABS_ELF
12024 if (cur_proc_ptr
== (procS
*) NULL
)
12026 as_warn (_(".mask/.fmask outside of .ent"));
12027 demand_empty_rest_of_line ();
12031 if (get_absolute_expression_and_terminator (&mask
) != ',')
12033 as_warn (_("Bad .mask/.fmask directive"));
12034 --input_line_pointer
;
12035 demand_empty_rest_of_line ();
12039 off
= get_absolute_expression ();
12041 if (reg_type
== 'F')
12043 cur_proc_ptr
->fpreg_mask
= mask
;
12044 cur_proc_ptr
->fpreg_offset
= off
;
12048 cur_proc_ptr
->reg_mask
= mask
;
12049 cur_proc_ptr
->reg_offset
= off
;
12052 demand_empty_rest_of_line ();
12054 s_ignore (reg_type
);
12055 #endif /* MIPS_STABS_ELF */
12058 /* The .loc directive. */
12069 assert (now_seg
== text_section
);
12071 lineno
= get_number ();
12072 addroff
= frag_now_fix ();
12074 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12075 S_SET_TYPE (symbolP
, N_SLINE
);
12076 S_SET_OTHER (symbolP
, 0);
12077 S_SET_DESC (symbolP
, lineno
);
12078 symbolP
->sy_segment
= now_seg
;