1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
27 #include "libiberty.h"
38 #include "opcode/mips.h"
44 static char *mips_regmask_frag
;
47 #define PIC_CALL_REG 25
55 extern int target_big_endian
;
57 /* The default target format to use. */
61 switch (OUTPUT_FLAVOR
)
63 case bfd_target_aout_flavour
:
64 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
65 case bfd_target_ecoff_flavour
:
66 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
67 case bfd_target_elf_flavour
:
68 return target_big_endian
? "elf32-bigmips" : "elf32-littlemips";
74 /* The name of the readonly data section. */
75 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
77 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
79 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
83 /* These variables are filled in with the masks of registers used.
84 The object format code reads them and puts them in the appropriate
86 unsigned long mips_gprmask
;
87 unsigned long mips_cprmask
[4];
89 /* MIPS ISA (Instruction Set Architecture) level (may be changed
90 temporarily using .set mipsN). */
91 static int mips_isa
= -1;
93 /* MIPS ISA we are using for this output file. */
94 static int file_mips_isa
;
96 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
97 static int mips_cpu
= -1;
99 /* Whether the 4650 instructions (mad/madu) are permitted. */
100 static int mips_4650
= -1;
102 /* MIPS PIC level. */
106 /* Do not generate PIC code. */
109 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
110 not sure what it is supposed to do. */
113 /* Generate PIC code as in the SVR4 MIPS ABI. */
116 /* Generate PIC code without using a global offset table: the data
117 segment has a maximum size of 64K, all data references are off
118 the $gp register, and all text references are PC relative. This
119 is used on some embedded systems. */
123 static enum mips_pic_level mips_pic
;
125 /* 1 if trap instructions should used for overflow rather than break
127 static int mips_trap
;
129 static int mips_warn_about_macros
;
130 static int mips_noreorder
;
131 static int mips_any_noreorder
;
132 static int mips_nomove
;
133 static int mips_noat
;
134 static int mips_nobopt
;
136 /* The size of the small data section. */
137 static int g_switch_value
= 8;
138 /* Whether the -G option was used. */
139 static int g_switch_seen
= 0;
144 /* If we can determine in advance that GP optimization won't be
145 possible, we can skip the relaxation stuff that tries to produce
146 GP-relative references. This makes delay slot optimization work
149 This function can only provide a guess, but it seems to work for
150 gcc output. If it guesses wrong, the only loss should be in
151 efficiency; it shouldn't introduce any bugs.
153 I don't know if a fix is needed for the SVR4_PIC mode. I've only
154 fixed it for the non-PIC mode. KR 95/04/07 */
155 static int nopic_need_relax
PARAMS ((symbolS
*));
157 /* handle of the OPCODE hash table */
158 static struct hash_control
*op_hash
= NULL
;
160 /* This array holds the chars that always start a comment. If the
161 pre-processor is disabled, these aren't very useful */
162 const char comment_chars
[] = "#";
164 /* This array holds the chars that only start a comment at the beginning of
165 a line. If the line seems to have the form '# 123 filename'
166 .line and .file directives will appear in the pre-processed output */
167 /* Note that input_file.c hand checks for '#' at the beginning of the
168 first line of the input file. This is because the compiler outputs
169 #NO_APP at the beginning of its output. */
170 /* Also note that C style comments are always supported. */
171 const char line_comment_chars
[] = "#";
173 /* This array holds machine specific line separator characters. */
174 const char line_separator_chars
[] = "";
176 /* Chars that can be used to separate mant from exp in floating point nums */
177 const char EXP_CHARS
[] = "eE";
179 /* Chars that mean this number is a floating point constant */
182 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
184 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
185 changed in read.c . Ideally it shouldn't have to know about it at all,
186 but nothing is ideal around here.
189 static char *insn_error
;
191 static int byte_order
= BYTE_ORDER
;
193 static int auto_align
= 1;
195 /* Symbol labelling the current insn. */
196 static symbolS
*insn_label
;
198 /* When outputting SVR4 PIC code, the assembler needs to know the
199 offset in the stack frame from which to restore the $gp register.
200 This is set by the .cprestore pseudo-op, and saved in this
202 static offsetT mips_cprestore_offset
= -1;
204 /* This is the register which holds the stack frame, as set by the
205 .frame pseudo-op. This is needed to implement .cprestore. */
206 static int mips_frame_reg
= SP
;
208 /* To output NOP instructions correctly, we need to keep information
209 about the previous two instructions. */
211 /* Whether we are optimizing. The default value of 2 means to remove
212 unneeded NOPs and swap branch instructions when possible. A value
213 of 1 means to not swap branches. A value of 0 means to always
215 static int mips_optimize
= 2;
217 /* The previous instruction. */
218 static struct mips_cl_insn prev_insn
;
220 /* The instruction before prev_insn. */
221 static struct mips_cl_insn prev_prev_insn
;
223 /* If we don't want information for prev_insn or prev_prev_insn, we
224 point the insn_mo field at this dummy integer. */
225 static const struct mips_opcode dummy_opcode
= { 0 };
227 /* Non-zero if prev_insn is valid. */
228 static int prev_insn_valid
;
230 /* The frag for the previous instruction. */
231 static struct frag
*prev_insn_frag
;
233 /* The offset into prev_insn_frag for the previous instruction. */
234 static long prev_insn_where
;
236 /* The reloc for the previous instruction, if any. */
237 static fixS
*prev_insn_fixp
;
239 /* Non-zero if the previous instruction was in a delay slot. */
240 static int prev_insn_is_delay_slot
;
242 /* Non-zero if the previous instruction was in a .set noreorder. */
243 static int prev_insn_unreordered
;
245 /* Non-zero if the previous previous instruction was in a .set
247 static int prev_prev_insn_unreordered
;
249 /* Since the MIPS does not have multiple forms of PC relative
250 instructions, we do not have to do relaxing as is done on other
251 platforms. However, we do have to handle GP relative addressing
252 correctly, which turns out to be a similar problem.
254 Every macro that refers to a symbol can occur in (at least) two
255 forms, one with GP relative addressing and one without. For
256 example, loading a global variable into a register generally uses
257 a macro instruction like this:
259 If i can be addressed off the GP register (this is true if it is in
260 the .sbss or .sdata section, or if it is known to be smaller than
261 the -G argument) this will generate the following instruction:
263 This instruction will use a GPREL reloc. If i can not be addressed
264 off the GP register, the following instruction sequence will be used:
267 In this case the first instruction will have a HI16 reloc, and the
268 second reloc will have a LO16 reloc. Both relocs will be against
271 The issue here is that we may not know whether i is GP addressable
272 until after we see the instruction that uses it. Therefore, we
273 want to be able to choose the final instruction sequence only at
274 the end of the assembly. This is similar to the way other
275 platforms choose the size of a PC relative instruction only at the
278 When generating position independent code we do not use GP
279 addressing in quite the same way, but the issue still arises as
280 external symbols and local symbols must be handled differently.
282 We handle these issues by actually generating both possible
283 instruction sequences. The longer one is put in a frag_var with
284 type rs_machine_dependent. We encode what to do with the frag in
285 the subtype field. We encode (1) the number of existing bytes to
286 replace, (2) the number of new bytes to use, (3) the offset from
287 the start of the existing bytes to the first reloc we must generate
288 (that is, the offset is applied from the start of the existing
289 bytes after they are replaced by the new bytes, if any), (4) the
290 offset from the start of the existing bytes to the second reloc,
291 (5) whether a third reloc is needed (the third reloc is always four
292 bytes after the second reloc), and (6) whether to warn if this
293 variant is used (this is sometimes needed if .set nomacro or .set
294 noat is in effect). All these numbers are reasonably small.
296 Generating two instruction sequences must be handled carefully to
297 ensure that delay slots are handled correctly. Fortunately, there
298 are a limited number of cases. When the second instruction
299 sequence is generated, append_insn is directed to maintain the
300 existing delay slot information, so it continues to apply to any
301 code after the second instruction sequence. This means that the
302 second instruction sequence must not impose any requirements not
303 required by the first instruction sequence.
305 These variant frags are then handled in functions called by the
306 machine independent code. md_estimate_size_before_relax returns
307 the final size of the frag. md_convert_frag sets up the final form
308 of the frag. tc_gen_reloc adjust the first reloc and adds a second
310 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
314 | (((reloc1) + 64) << 9) \
315 | (((reloc2) + 64) << 2) \
316 | ((reloc3) ? (1 << 1) : 0) \
318 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
319 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
320 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
321 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
322 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
323 #define RELAX_WARN(i) ((i) & 1)
325 /* Prototypes for static functions. */
328 #define internalError() \
329 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
331 #define internalError() as_fatal ("MIPS internal Error");
334 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
335 unsigned int reg
, int fpr
));
336 static void append_insn
PARAMS ((char *place
,
337 struct mips_cl_insn
* ip
,
339 bfd_reloc_code_real_type r
));
340 static void mips_no_prev_insn
PARAMS ((void));
341 static void mips_emit_delays
PARAMS ((void));
342 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
343 const char *name
, const char *fmt
,
345 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
346 expressionS
* ep
, int regnum
));
347 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
348 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
350 static void load_register
PARAMS ((int *, int, expressionS
*, int));
351 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
352 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
353 #ifdef LOSING_COMPILER
354 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
356 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
357 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
358 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
359 static symbolS
*get_symbol
PARAMS ((void));
360 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
361 static void s_align
PARAMS ((int));
362 static void s_stringer
PARAMS ((int));
363 static void s_change_sec
PARAMS ((int));
364 static void s_cons
PARAMS ((int));
365 static void s_err
PARAMS ((int));
366 static void s_extern
PARAMS ((int));
367 static void s_float_cons
PARAMS ((int));
368 static void s_mips_globl
PARAMS ((int));
369 static void s_option
PARAMS ((int));
370 static void s_mipsset
PARAMS ((int));
371 static void s_mips_space
PARAMS ((int));
372 static void s_abicalls
PARAMS ((int));
373 static void s_cpload
PARAMS ((int));
374 static void s_cprestore
PARAMS ((int));
375 static void s_gpword
PARAMS ((int));
376 static void s_cpadd
PARAMS ((int));
377 #ifndef ECOFF_DEBUGGING
378 static void md_obj_begin
PARAMS ((void));
379 static void md_obj_end
PARAMS ((void));
380 static long get_number
PARAMS ((void));
381 static void s_ent
PARAMS ((int));
382 static void s_mipsend
PARAMS ((int));
383 static void s_file
PARAMS ((int));
385 static void s_frame
PARAMS ((int));
386 static void s_loc
PARAMS ((int));
387 static void s_mask
PARAMS ((char));
391 static void s_elf_section
PARAMS ((int));
396 The following pseudo-ops from the Kane and Heinrich MIPS book
397 should be defined here, but are currently unsupported: .alias,
398 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
400 The following pseudo-ops from the Kane and Heinrich MIPS book are
401 specific to the type of debugging information being generated, and
402 should be defined by the object format: .aent, .begin, .bend,
403 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
406 The following pseudo-ops from the Kane and Heinrich MIPS book are
407 not MIPS CPU specific, but are also not specific to the object file
408 format. This file is probably the best place to define them, but
409 they are not currently supported: .asm0, .endr, .lab, .repeat,
410 .struct, .weakext. */
412 const pseudo_typeS md_pseudo_table
[] =
414 /* MIPS specific pseudo-ops. */
415 {"option", s_option
, 0},
416 {"set", s_mipsset
, 0},
417 {"rdata", s_change_sec
, 'r'},
418 {"sdata", s_change_sec
, 's'},
419 {"livereg", s_ignore
, 0},
420 { "abicalls", s_abicalls
, 0},
421 { "cpload", s_cpload
, 0},
422 { "cprestore", s_cprestore
, 0},
423 { "gpword", s_gpword
, 0},
424 { "cpadd", s_cpadd
, 0},
426 /* Relatively generic pseudo-ops that happen to be used on MIPS
428 {"asciiz", s_stringer
, 1},
429 {"bss", s_change_sec
, 'b'},
432 {"dword", s_cons
, 3},
434 /* These pseudo-ops are defined in read.c, but must be overridden
435 here for one reason or another. */
436 {"align", s_align
, 0},
437 {"ascii", s_stringer
, 0},
438 {"asciz", s_stringer
, 1},
440 {"data", s_change_sec
, 'd'},
441 {"double", s_float_cons
, 'd'},
442 {"extern", s_extern
, 0},
443 {"float", s_float_cons
, 'f'},
444 {"globl", s_mips_globl
, 0},
445 {"global", s_mips_globl
, 0},
446 {"hword", s_cons
, 1},
451 {"short", s_cons
, 1},
452 {"single", s_float_cons
, 'f'},
453 {"space", s_mips_space
, 0},
454 {"text", s_change_sec
, 't'},
457 #ifndef ECOFF_DEBUGGING
458 /* These pseudo-ops should be defined by the object file format.
459 However, a.out doesn't support them, so we have versions here. */
461 {"bgnb", s_ignore
, 0},
462 {"end", s_mipsend
, 0},
463 {"endb", s_ignore
, 0},
466 {"fmask", s_ignore
, 'F'},
467 {"frame", s_ignore
, 0},
468 {"loc", s_ignore
, 0},
469 {"mask", s_ignore
, 'R'},
470 {"verstamp", s_ignore
, 0},
474 /* We need to tweak the ELF ".section" pseudo-op a bit. */
475 {"section", s_elf_section
, 0},
477 /* Redirect additional ELF data allocation pseudo-ops. */
478 {"2byte", s_cons
, 2},
479 {"4byte", s_cons
, 4},
480 {"8byte", s_cons
, 8},
487 static char *expr_end
;
489 static expressionS imm_expr
;
490 static expressionS offset_expr
;
491 static bfd_reloc_code_real_type imm_reloc
;
492 static bfd_reloc_code_real_type offset_reloc
;
495 * This function is called once, at assembler startup time. It should
496 * set up all the tables, etc. that the MD part of the assembler will need.
502 register const char *retval
= NULL
;
503 register unsigned int i
= 0;
511 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
513 a
= xmalloc (sizeof TARGET_CPU
);
514 strcpy (a
, TARGET_CPU
);
515 a
[(sizeof TARGET_CPU
) - 3] = '\0';
519 if (strcmp (cpu
, "mips") == 0)
525 else if (strcmp (cpu
, "r6000") == 0
526 || strcmp (cpu
, "mips2") == 0)
532 else if (strcmp (cpu
, "mips64") == 0
533 || strcmp (cpu
, "r4000") == 0
534 || strcmp (cpu
, "mips3") == 0)
540 else if (strcmp (cpu
, "r4400") == 0)
546 else if (strcmp (cpu
, "mips64orion") == 0
547 || strcmp (cpu
, "r4600") == 0)
553 else if (strcmp (cpu
, "r4650") == 0)
561 else if (strcmp (cpu
, "r8000") == 0
562 || strcmp (cpu
, "mips4") == 0)
568 else if (strcmp (cpu
, "r10000") == 0)
588 if (mips_isa
< 2 && mips_trap
)
589 as_bad ("trap exception not supported at ISA 1");
594 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
597 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
600 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
603 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
607 as_warn ("Could not set architecture and machine");
609 file_mips_isa
= mips_isa
;
611 op_hash
= hash_new ();
613 for (i
= 0; i
< NUMOPCODES
;)
615 const char *name
= mips_opcodes
[i
].name
;
617 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
620 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
621 mips_opcodes
[i
].name
, retval
);
622 as_fatal ("Broken assembler. No assembly attempted.");
626 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
627 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
628 != mips_opcodes
[i
].match
))
630 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
631 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
632 as_fatal ("Broken assembler. No assembly attempted.");
636 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
639 mips_no_prev_insn ();
647 /* set the default alignment for the text section (2**2) */
648 record_alignment (text_section
, 2);
650 if (USE_GLOBAL_POINTER_OPT
)
651 bfd_set_gp_size (stdoutput
, g_switch_value
);
653 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
655 /* Sections must be aligned to 16 byte boundaries. */
656 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
657 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
658 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
660 /* Create a .reginfo section for register masks and a .mdebug
661 section for debugging information. */
669 sec
= subseg_new (".reginfo", (subsegT
) 0);
671 /* The ABI says this section should be loaded so that the
672 running program can access it. */
673 (void) bfd_set_section_flags (stdoutput
, sec
,
674 (SEC_ALLOC
| SEC_LOAD
675 | SEC_READONLY
| SEC_DATA
));
676 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
679 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
682 #ifdef ECOFF_DEBUGGING
683 sec
= subseg_new (".mdebug", (subsegT
) 0);
684 (void) bfd_set_section_flags (stdoutput
, sec
,
685 SEC_HAS_CONTENTS
| SEC_READONLY
);
686 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
689 subseg_set (seg
, subseg
);
693 #ifndef ECOFF_DEBUGGING
701 #ifndef ECOFF_DEBUGGING
710 struct mips_cl_insn insn
;
712 imm_expr
.X_op
= O_absent
;
713 offset_expr
.X_op
= O_absent
;
715 mips_ip (str
, &insn
);
718 as_bad ("%s `%s'", insn_error
, str
);
721 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
727 if (imm_expr
.X_op
!= O_absent
)
728 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
729 else if (offset_expr
.X_op
!= O_absent
)
730 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
732 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
736 /* See whether instruction IP reads register REG. If FPR is non-zero,
737 REG is a floating point register. */
740 insn_uses_reg (ip
, reg
, fpr
)
741 struct mips_cl_insn
*ip
;
745 /* Don't report on general register 0, since it never changes. */
746 if (! fpr
&& reg
== 0)
751 /* If we are called with either $f0 or $f1, we must check $f0.
752 This is not optimal, because it will introduce an unnecessary
753 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
754 need to distinguish reading both $f0 and $f1 or just one of
755 them. Note that we don't have to check the other way,
756 because there is no instruction that sets both $f0 and $f1
757 and requires a delay. */
758 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
759 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
760 == (reg
&~ (unsigned) 1)))
762 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
763 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
764 == (reg
&~ (unsigned) 1)))
769 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
770 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
772 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
773 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
780 /* Output an instruction. PLACE is where to put the instruction; if
781 it is NULL, this uses frag_more to get room. IP is the instruction
782 information. ADDRESS_EXPR is an operand of the instruction to be
783 used with RELOC_TYPE. */
786 append_insn (place
, ip
, address_expr
, reloc_type
)
788 struct mips_cl_insn
*ip
;
789 expressionS
*address_expr
;
790 bfd_reloc_code_real_type reloc_type
;
792 register unsigned long prev_pinfo
, pinfo
;
797 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
798 pinfo
= ip
->insn_mo
->pinfo
;
800 if (place
== NULL
&& ! mips_noreorder
)
802 /* If the previous insn required any delay slots, see if we need
803 to insert a NOP or two. There are eight kinds of possible
804 hazards, of which an instruction can have at most one type.
805 (1) a load from memory delay
806 (2) a load from a coprocessor delay
807 (3) an unconditional branch delay
808 (4) a conditional branch delay
809 (5) a move to coprocessor register delay
810 (6) a load coprocessor register from memory delay
811 (7) a coprocessor condition code delay
812 (8) a HI/LO special register delay
814 There are a lot of optimizations we could do that we don't.
815 In particular, we do not, in general, reorder instructions.
816 If you use gcc with optimization, it will reorder
817 instructions and generally do much more optimization then we
818 do here; repeating all that work in the assembler would only
819 benefit hand written assembly code, and does not seem worth
822 /* This is how a NOP is emitted. */
823 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
825 /* The previous insn might require a delay slot, depending upon
826 the contents of the current insn. */
828 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
830 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
832 /* A load from a coprocessor or from memory. All load
833 delays delay the use of general register rt for one
834 instruction on the r3000. The r6000 and r4000 use
836 know (prev_pinfo
& INSN_WRITE_GPR_T
);
837 if (mips_optimize
== 0
838 || insn_uses_reg (ip
,
839 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
844 else if (mips_isa
< 4
845 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
847 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
849 /* A generic coprocessor delay. The previous instruction
850 modified a coprocessor general or control register. If
851 it modified a control register, we need to avoid any
852 coprocessor instruction (this is probably not always
853 required, but it sometimes is). If it modified a general
854 register, we avoid using that register.
856 On the r6000 and r4000 loading a coprocessor register
857 from memory is interlocked, and does not require a delay.
859 This case is not handled very well. There is no special
860 knowledge of CP0 handling, and the coprocessors other
861 than the floating point unit are not distinguished at
863 if (prev_pinfo
& INSN_WRITE_FPR_T
)
865 if (mips_optimize
== 0
866 || insn_uses_reg (ip
,
867 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
872 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
874 if (mips_optimize
== 0
875 || insn_uses_reg (ip
,
876 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
883 /* We don't know exactly what the previous instruction
884 does. If the current instruction uses a coprocessor
885 register, we must insert a NOP. If previous
886 instruction may set the condition codes, and the
887 current instruction uses them, we must insert two
889 if (mips_optimize
== 0
890 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
891 && (pinfo
& INSN_READ_COND_CODE
)))
893 else if (pinfo
& INSN_COP
)
897 else if (mips_isa
< 4
898 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
900 /* The previous instruction sets the coprocessor condition
901 codes, but does not require a general coprocessor delay
902 (this means it is a floating point comparison
903 instruction). If this instruction uses the condition
904 codes, we need to insert a single NOP. */
905 if (mips_optimize
== 0
906 || (pinfo
& INSN_READ_COND_CODE
))
909 else if (prev_pinfo
& INSN_READ_LO
)
911 /* The previous instruction reads the LO register; if the
912 current instruction writes to the LO register, we must
913 insert two NOPS. The R4650 has interlocks. */
915 && (mips_optimize
== 0
916 || (pinfo
& INSN_WRITE_LO
)))
919 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
921 /* The previous instruction reads the HI register; if the
922 current instruction writes to the HI register, we must
923 insert a NOP. The R4650 has interlocks. */
925 && (mips_optimize
== 0
926 || (pinfo
& INSN_WRITE_HI
)))
930 /* There are two cases which require two intervening
931 instructions: 1) setting the condition codes using a move to
932 coprocessor instruction which requires a general coprocessor
933 delay and then reading the condition codes 2) reading the HI
934 or LO register and then writing to it (except on the R4650,
935 which has interlocks). If we are not already emitting a NOP
936 instruction, we must check for these cases compared to the
937 instruction previous to the previous instruction. */
940 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
941 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
942 && (pinfo
& INSN_READ_COND_CODE
))
943 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
944 && (pinfo
& INSN_WRITE_LO
)
946 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
947 && (pinfo
& INSN_WRITE_HI
)
951 /* If we are being given a nop instruction, don't bother with
952 one of the nops we would otherwise output. This will only
953 happen when a nop instruction is used with mips_optimize set
955 if (nops
> 0 && ip
->insn_opcode
== 0)
958 /* Now emit the right number of NOP instructions. */
963 for (i
= 0; i
< nops
; i
++)
967 listing_prev_line ();
968 /* We may be at the start of a variant frag. In case we
969 are, make sure there is enough space for the frag
970 after the frags created by listing_prev_line. The
971 argument to frag_grow here must be at least as large
972 as the argument to all other calls to frag_grow in
973 this file. We don't have to worry about being in the
974 middle of a variant frag, because the variants insert
975 all needed nop instructions themselves. */
978 if (insn_label
!= NULL
)
980 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
981 insn_label
->sy_frag
= frag_now
;
982 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
992 if (address_expr
!= NULL
)
994 if (address_expr
->X_op
== O_constant
)
999 ip
->insn_opcode
|= address_expr
->X_add_number
;
1002 case BFD_RELOC_LO16
:
1003 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1006 case BFD_RELOC_MIPS_JMP
:
1007 case BFD_RELOC_16_PCREL_S2
:
1016 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1018 /* Don't generate a reloc if we are writing into a variant
1021 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1023 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1028 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1030 /* Update the register mask information. */
1031 if (pinfo
& INSN_WRITE_GPR_D
)
1032 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1033 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1034 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1035 if (pinfo
& INSN_READ_GPR_S
)
1036 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1037 if (pinfo
& INSN_WRITE_GPR_31
)
1038 mips_gprmask
|= 1 << 31;
1039 if (pinfo
& INSN_WRITE_FPR_D
)
1040 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1041 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1042 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1043 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1044 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1045 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1046 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1047 if (pinfo
& INSN_COP
)
1049 /* We don't keep enough information to sort these cases out. */
1051 /* Never set the bit for $0, which is always zero. */
1052 mips_gprmask
&=~ 1 << 0;
1054 if (place
== NULL
&& ! mips_noreorder
)
1056 /* Filling the branch delay slot is more complex. We try to
1057 switch the branch with the previous instruction, which we can
1058 do if the previous instruction does not set up a condition
1059 that the branch tests and if the branch is not itself the
1060 target of any branch. */
1061 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1062 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1064 if (mips_optimize
< 2
1065 /* If we have seen .set volatile or .set nomove, don't
1068 /* If we had to emit any NOP instructions, then we
1069 already know we can not swap. */
1071 /* If we don't even know the previous insn, we can not
1073 || ! prev_insn_valid
1074 /* If the previous insn is already in a branch delay
1075 slot, then we can not swap. */
1076 || prev_insn_is_delay_slot
1077 /* If the previous previous insn was in a .set
1078 noreorder, we can't swap. Actually, the MIPS
1079 assembler will swap in this situation. However, gcc
1080 configured -with-gnu-as will generate code like
1086 in which we can not swap the bne and INSN. If gcc is
1087 not configured -with-gnu-as, it does not output the
1088 .set pseudo-ops. We don't have to check
1089 prev_insn_unreordered, because prev_insn_valid will
1090 be 0 in that case. We don't want to use
1091 prev_prev_insn_valid, because we do want to be able
1092 to swap at the start of a function. */
1093 || prev_prev_insn_unreordered
1094 /* If the branch is itself the target of a branch, we
1095 can not swap. We cheat on this; all we check for is
1096 whether there is a label on this instruction. If
1097 there are any branches to anything other than a
1098 label, users must use .set noreorder. */
1099 || insn_label
!= NULL
1100 /* If the previous instruction is in a variant frag, we
1101 can not do the swap. */
1102 || prev_insn_frag
->fr_type
== rs_machine_dependent
1103 /* If the branch reads the condition codes, we don't
1104 even try to swap, because in the sequence
1109 we can not swap, and I don't feel like handling that
1112 && (pinfo
& INSN_READ_COND_CODE
))
1113 /* We can not swap with an instruction that requires a
1114 delay slot, becase the target of the branch might
1115 interfere with that instruction. */
1118 & (INSN_LOAD_COPROC_DELAY
1119 | INSN_COPROC_MOVE_DELAY
1120 | INSN_WRITE_COND_CODE
)))
1127 & (INSN_LOAD_MEMORY_DELAY
1128 | INSN_COPROC_MEMORY_DELAY
)))
1129 /* We can not swap with a branch instruction. */
1131 & (INSN_UNCOND_BRANCH_DELAY
1132 | INSN_COND_BRANCH_DELAY
1133 | INSN_COND_BRANCH_LIKELY
))
1134 /* We do not swap with a trap instruction, since it
1135 complicates trap handlers to have the trap
1136 instruction be in a delay slot. */
1137 || (prev_pinfo
& INSN_TRAP
)
1138 /* If the branch reads a register that the previous
1139 instruction sets, we can not swap. */
1140 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1141 && insn_uses_reg (ip
,
1142 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1145 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1146 && insn_uses_reg (ip
,
1147 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1150 /* If the branch writes a register that the previous
1151 instruction sets, we can not swap (we know that
1152 branches write only to RD or to $31). */
1153 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1154 && (((pinfo
& INSN_WRITE_GPR_D
)
1155 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1156 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1157 || ((pinfo
& INSN_WRITE_GPR_31
)
1158 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1161 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1162 && (((pinfo
& INSN_WRITE_GPR_D
)
1163 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1164 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1165 || ((pinfo
& INSN_WRITE_GPR_31
)
1166 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1169 /* If the branch writes a register that the previous
1170 instruction reads, we can not swap (we know that
1171 branches only write to RD or to $31). */
1172 || ((pinfo
& INSN_WRITE_GPR_D
)
1173 && insn_uses_reg (&prev_insn
,
1174 ((ip
->insn_opcode
>> OP_SH_RD
)
1177 || ((pinfo
& INSN_WRITE_GPR_31
)
1178 && insn_uses_reg (&prev_insn
, 31, 0))
1179 /* If we are generating embedded PIC code, the branch
1180 might be expanded into a sequence which uses $at, so
1181 we can't swap with an instruction which reads it. */
1182 || (mips_pic
== EMBEDDED_PIC
1183 && insn_uses_reg (&prev_insn
, AT
, 0))
1184 /* If the previous previous instruction has a load
1185 delay, and sets a register that the branch reads, we
1188 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1190 && (prev_prev_insn
.insn_mo
->pinfo
1191 & INSN_LOAD_MEMORY_DELAY
)))
1192 && insn_uses_reg (ip
,
1193 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1197 /* We could do even better for unconditional branches to
1198 portions of this object file; we could pick up the
1199 instruction at the destination, put it in the delay
1200 slot, and bump the destination address. */
1202 /* Update the previous insn information. */
1203 prev_prev_insn
= *ip
;
1204 prev_insn
.insn_mo
= &dummy_opcode
;
1211 /* It looks like we can actually do the swap. */
1212 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1213 memcpy (temp
, prev_f
, 4);
1214 memcpy (prev_f
, f
, 4);
1215 memcpy (f
, temp
, 4);
1218 prev_insn_fixp
->fx_frag
= frag_now
;
1219 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1223 fixp
->fx_frag
= prev_insn_frag
;
1224 fixp
->fx_where
= prev_insn_where
;
1226 /* Update the previous insn information; leave prev_insn
1228 prev_prev_insn
= *ip
;
1230 prev_insn_is_delay_slot
= 1;
1232 /* If that was an unconditional branch, forget the previous
1233 insn information. */
1234 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1236 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1237 prev_insn
.insn_mo
= &dummy_opcode
;
1240 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1242 /* We don't yet optimize a branch likely. What we should do
1243 is look at the target, copy the instruction found there
1244 into the delay slot, and increment the branch to jump to
1245 the next instruction. */
1247 /* Update the previous insn information. */
1248 prev_prev_insn
= *ip
;
1249 prev_insn
.insn_mo
= &dummy_opcode
;
1253 /* Update the previous insn information. */
1255 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1257 prev_prev_insn
= prev_insn
;
1260 /* Any time we see a branch, we always fill the delay slot
1261 immediately; since this insn is not a branch, we know it
1262 is not in a delay slot. */
1263 prev_insn_is_delay_slot
= 0;
1266 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1267 prev_insn_unreordered
= 0;
1268 prev_insn_frag
= frag_now
;
1269 prev_insn_where
= f
- frag_now
->fr_literal
;
1270 prev_insn_fixp
= fixp
;
1271 prev_insn_valid
= 1;
1274 /* We just output an insn, so the next one doesn't have a label. */
1278 /* This function forgets that there was any previous instruction or
1282 mips_no_prev_insn ()
1284 prev_insn
.insn_mo
= &dummy_opcode
;
1285 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1286 prev_insn_valid
= 0;
1287 prev_insn_is_delay_slot
= 0;
1288 prev_insn_unreordered
= 0;
1289 prev_prev_insn_unreordered
= 0;
1293 /* This function must be called whenever we turn on noreorder or emit
1294 something other than instructions. It inserts any NOPS which might
1295 be needed by the previous instruction, and clears the information
1296 kept for the previous instructions. */
1301 if (! mips_noreorder
)
1307 && (prev_insn
.insn_mo
->pinfo
1308 & (INSN_LOAD_COPROC_DELAY
1309 | INSN_COPROC_MOVE_DELAY
1310 | INSN_WRITE_COND_CODE
)))
1312 && (prev_insn
.insn_mo
->pinfo
1316 && (prev_insn
.insn_mo
->pinfo
1317 & (INSN_LOAD_MEMORY_DELAY
1318 | INSN_COPROC_MEMORY_DELAY
))))
1322 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1324 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1325 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1328 else if ((mips_isa
< 4
1329 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1331 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1332 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1337 if (insn_label
!= NULL
)
1339 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1340 insn_label
->sy_frag
= frag_now
;
1341 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1346 mips_no_prev_insn ();
1349 /* Build an instruction created by a macro expansion. This is passed
1350 a pointer to the count of instructions created so far, an
1351 expression, the name of the instruction to build, an operand format
1352 string, and corresponding arguments. */
1356 macro_build (char *place
,
1364 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1373 struct mips_cl_insn insn
;
1374 bfd_reloc_code_real_type r
;
1378 va_start (args
, fmt
);
1384 * If the macro is about to expand into a second instruction,
1385 * print a warning if needed. We need to pass ip as a parameter
1386 * to generate a better warning message here...
1388 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1389 as_warn ("Macro instruction expanded into multiple instructions");
1392 *counter
+= 1; /* bump instruction counter */
1394 r
= BFD_RELOC_UNUSED
;
1395 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1396 assert (insn
.insn_mo
);
1397 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1399 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1400 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1403 assert (insn
.insn_mo
->name
);
1404 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1406 insn
.insn_opcode
= insn
.insn_mo
->match
;
1422 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1428 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1433 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1438 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1445 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1449 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1453 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1460 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1466 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1467 assert (r
== BFD_RELOC_MIPS_GPREL
1468 || r
== BFD_RELOC_MIPS_LITERAL
1469 || r
== BFD_RELOC_LO16
1470 || r
== BFD_RELOC_MIPS_GOT16
1471 || r
== BFD_RELOC_MIPS_CALL16
1472 || (ep
->X_op
== O_subtract
1473 && now_seg
== text_section
1474 && r
== BFD_RELOC_PCREL_LO16
));
1478 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1480 && (ep
->X_op
== O_constant
1481 || (ep
->X_op
== O_symbol
1482 && (r
== BFD_RELOC_HI16_S
1483 || r
== BFD_RELOC_HI16
))
1484 || (ep
->X_op
== O_subtract
1485 && now_seg
== text_section
1486 && r
== BFD_RELOC_PCREL_HI16_S
)));
1487 if (ep
->X_op
== O_constant
)
1489 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1491 r
= BFD_RELOC_UNUSED
;
1496 assert (ep
!= NULL
);
1498 * This allows macro() to pass an immediate expression for
1499 * creating short branches without creating a symbol.
1500 * Note that the expression still might come from the assembly
1501 * input, in which case the value is not checked for range nor
1502 * is a relocation entry generated (yuck).
1504 if (ep
->X_op
== O_constant
)
1506 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1510 r
= BFD_RELOC_16_PCREL_S2
;
1514 assert (ep
!= NULL
);
1515 r
= BFD_RELOC_MIPS_JMP
;
1524 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1526 append_insn (place
, &insn
, ep
, r
);
1530 * Generate a "lui" instruction.
1533 macro_build_lui (place
, counter
, ep
, regnum
)
1539 expressionS high_expr
;
1540 struct mips_cl_insn insn
;
1541 bfd_reloc_code_real_type r
;
1542 CONST
char *name
= "lui";
1543 CONST
char *fmt
= "t,u";
1549 high_expr
.X_op
= O_constant
;
1550 high_expr
.X_add_number
= 0;
1553 if (high_expr
.X_op
== O_constant
)
1555 /* we can compute the instruction now without a relocation entry */
1556 if (high_expr
.X_add_number
& 0x8000)
1557 high_expr
.X_add_number
+= 0x10000;
1558 high_expr
.X_add_number
=
1559 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1560 r
= BFD_RELOC_UNUSED
;
1564 assert (ep
->X_op
== O_symbol
);
1565 /* _gp_disp is a special case, used from s_cpload. */
1566 assert (mips_pic
== NO_PIC
1567 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1568 r
= BFD_RELOC_HI16_S
;
1572 * If the macro is about to expand into a second instruction,
1573 * print a warning if needed. We need to pass ip as a parameter
1574 * to generate a better warning message here...
1576 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1577 as_warn ("Macro instruction expanded into multiple instructions");
1580 *counter
+= 1; /* bump instruction counter */
1582 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1583 assert (insn
.insn_mo
);
1584 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1585 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1587 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1588 if (r
== BFD_RELOC_UNUSED
)
1590 insn
.insn_opcode
|= high_expr
.X_add_number
;
1591 append_insn (place
, &insn
, NULL
, r
);
1594 append_insn (place
, &insn
, &high_expr
, r
);
1598 * Generates code to set the $at register to true (one)
1599 * if reg is less than the immediate expression.
1602 set_at (counter
, reg
, unsignedp
)
1607 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1608 macro_build ((char *) NULL
, counter
, &imm_expr
,
1609 unsignedp
? "sltiu" : "slti",
1610 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1613 load_register (counter
, AT
, &imm_expr
, 0);
1614 macro_build ((char *) NULL
, counter
, NULL
,
1615 unsignedp
? "sltu" : "slt",
1616 "d,v,t", AT
, reg
, AT
);
1620 /* Warn if an expression is not a constant. */
1623 check_absolute_expr (ip
, ex
)
1624 struct mips_cl_insn
*ip
;
1627 if (ex
->X_op
!= O_constant
)
1628 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1632 * This routine generates the least number of instructions neccessary to load
1633 * an absolute expression value into a register.
1636 load_register (counter
, reg
, ep
, dbl
)
1643 expressionS hi32
, lo32
, tmp
;
1645 if (ep
->X_op
!= O_big
)
1647 assert (ep
->X_op
== O_constant
);
1648 if (ep
->X_add_number
< 0x8000
1649 && (ep
->X_add_number
>= 0
1650 || (ep
->X_add_number
>= -0x8000
1653 || sizeof (ep
->X_add_number
) > 4))))
1655 /* We can handle 16 bit signed values with an addiu to
1656 $zero. No need to ever use daddiu here, since $zero and
1657 the result are always correct in 32 bit mode. */
1658 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1659 (int) BFD_RELOC_LO16
);
1662 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1664 /* We can handle 16 bit unsigned values with an ori to
1666 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1667 (int) BFD_RELOC_LO16
);
1670 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1671 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1672 == ~ (offsetT
) 0x7fffffff))
1675 || sizeof (ep
->X_add_number
) > 4
1676 || (ep
->X_add_number
& 0x80000000) == 0))
1678 /* 32 bit values require an lui. */
1679 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1680 (int) BFD_RELOC_HI16
);
1681 if ((ep
->X_add_number
& 0xffff) != 0)
1682 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1683 (int) BFD_RELOC_LO16
);
1688 /* 32 bit value with high bit set being loaded into a 64 bit
1689 register. We can't use lui, because that would
1690 incorrectly set the 32 high bits. */
1691 generic_bignum
[3] = 0;
1692 generic_bignum
[2] = 0;
1693 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1694 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1696 tmp
.X_add_number
= 4;
1701 /* The value is larger than 32 bits. */
1705 as_bad ("Number larger than 32 bits");
1706 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1707 (int) BFD_RELOC_LO16
);
1711 if (ep
->X_op
!= O_big
)
1715 hi32
.X_add_number
>>= shift
;
1716 hi32
.X_add_number
&= 0xffffffff;
1717 if ((hi32
.X_add_number
& 0x80000000) != 0)
1718 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1720 lo32
.X_add_number
&= 0xffffffff;
1724 assert (ep
->X_add_number
> 2);
1725 if (ep
->X_add_number
== 3)
1726 generic_bignum
[3] = 0;
1727 else if (ep
->X_add_number
> 4)
1728 as_bad ("Number larger than 64 bits");
1729 lo32
.X_op
= O_constant
;
1730 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1731 hi32
.X_op
= O_constant
;
1732 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1735 if (hi32
.X_add_number
== 0)
1739 load_register (counter
, reg
, &hi32
, 0);
1742 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1746 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1757 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1762 mid16
.X_add_number
>>= 16;
1763 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1764 freg
, (int) BFD_RELOC_LO16
);
1765 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1769 if ((lo32
.X_add_number
& 0xffff) != 0)
1770 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1771 (int) BFD_RELOC_LO16
);
1774 /* Load an address into a register. */
1777 load_address (counter
, reg
, ep
)
1784 if (ep
->X_op
!= O_constant
1785 && ep
->X_op
!= O_symbol
)
1787 as_bad ("expression too complex");
1788 ep
->X_op
= O_constant
;
1791 if (ep
->X_op
== O_constant
)
1793 load_register (counter
, reg
, ep
, 0);
1797 if (mips_pic
== NO_PIC
)
1799 /* If this is a reference to a GP relative symbol, we want
1800 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1802 lui $reg,<sym> (BFD_RELOC_HI16_S)
1803 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1804 If we have an addend, we always use the latter form. */
1805 if (ep
->X_add_number
!= 0 || nopic_need_relax (ep
->X_add_symbol
))
1810 macro_build ((char *) NULL
, counter
, ep
,
1811 mips_isa
< 3 ? "addiu" : "daddiu",
1812 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1813 p
= frag_var (rs_machine_dependent
, 8, 0,
1814 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1815 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1817 macro_build_lui (p
, counter
, ep
, reg
);
1820 macro_build (p
, counter
, ep
,
1821 mips_isa
< 3 ? "addiu" : "daddiu",
1822 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1824 else if (mips_pic
== SVR4_PIC
)
1828 /* If this is a reference to an external symbol, we want
1829 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1831 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1833 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1834 If there is a constant, it must be added in after. */
1835 ex
.X_add_number
= ep
->X_add_number
;
1836 ep
->X_add_number
= 0;
1838 macro_build ((char *) NULL
, counter
, ep
,
1839 mips_isa
< 3 ? "lw" : "ld",
1840 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1841 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1842 p
= frag_var (rs_machine_dependent
, 4, 0,
1843 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1844 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1845 macro_build (p
, counter
, ep
,
1846 mips_isa
< 3 ? "addiu" : "daddiu",
1847 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1848 if (ex
.X_add_number
!= 0)
1850 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1851 as_bad ("PIC code offset overflow (max 16 signed bits)");
1852 ex
.X_op
= O_constant
;
1853 macro_build (p
, counter
, &ex
,
1854 mips_isa
< 3 ? "addiu" : "daddiu",
1855 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1858 else if (mips_pic
== EMBEDDED_PIC
)
1861 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1863 macro_build ((char *) NULL
, counter
, ep
,
1864 mips_isa
< 3 ? "addiu" : "daddiu",
1865 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1873 * This routine implements the seemingly endless macro or synthesized
1874 * instructions and addressing modes in the mips assembly language. Many
1875 * of these macros are simple and are similar to each other. These could
1876 * probably be handled by some kind of table or grammer aproach instead of
1877 * this verbose method. Others are not simple macros but are more like
1878 * optimizing code generation.
1879 * One interesting optimization is when several store macros appear
1880 * consecutivly that would load AT with the upper half of the same address.
1881 * The ensuing load upper instructions are ommited. This implies some kind
1882 * of global optimization. We currently only optimize within a single macro.
1883 * For many of the load and store macros if the address is specified as a
1884 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1885 * first load register 'at' with zero and use it as the base register. The
1886 * mips assembler simply uses register $zero. Just one tiny optimization
1891 struct mips_cl_insn
*ip
;
1893 register int treg
, sreg
, dreg
, breg
;
1908 bfd_reloc_code_real_type r
;
1910 int hold_mips_optimize
;
1912 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1913 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1914 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1915 mask
= ip
->insn_mo
->mask
;
1917 expr1
.X_op
= O_constant
;
1918 expr1
.X_op_symbol
= NULL
;
1919 expr1
.X_add_symbol
= NULL
;
1920 expr1
.X_add_number
= 1;
1932 mips_emit_delays ();
1934 mips_any_noreorder
= 1;
1936 expr1
.X_add_number
= 8;
1937 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1939 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1941 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1942 macro_build ((char *) NULL
, &icnt
, NULL
,
1943 dbl
? "dsub" : "sub",
1944 "d,v,t", dreg
, 0, sreg
);
1967 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1969 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1970 (int) BFD_RELOC_LO16
);
1973 load_register (&icnt
, AT
, &imm_expr
, dbl
);
1974 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1993 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1995 if (mask
!= M_NOR_I
)
1996 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1997 sreg
, (int) BFD_RELOC_LO16
);
2000 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2001 treg
, sreg
, (int) BFD_RELOC_LO16
);
2002 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2008 load_register (&icnt
, AT
, &imm_expr
, 0);
2009 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2026 if (imm_expr
.X_add_number
== 0)
2028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2032 load_register (&icnt
, AT
, &imm_expr
, 0);
2033 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2041 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2042 likely
? "bgezl" : "bgez",
2048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2049 likely
? "blezl" : "blez",
2053 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2054 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2055 likely
? "beql" : "beq",
2062 /* check for > max integer */
2063 maxnum
= 0x7fffffff;
2071 if (imm_expr
.X_add_number
>= maxnum
2072 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2075 /* result is always false */
2078 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2079 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2083 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2084 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2089 imm_expr
.X_add_number
++;
2093 if (mask
== M_BGEL_I
)
2095 if (imm_expr
.X_add_number
== 0)
2097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2098 likely
? "bgezl" : "bgez",
2102 if (imm_expr
.X_add_number
== 1)
2104 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2105 likely
? "bgtzl" : "bgtz",
2109 maxnum
= 0x7fffffff;
2117 maxnum
= - maxnum
- 1;
2118 if (imm_expr
.X_add_number
<= maxnum
2119 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2122 /* result is always true */
2123 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2124 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2127 set_at (&icnt
, sreg
, 0);
2128 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2129 likely
? "beql" : "beq",
2140 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2141 likely
? "beql" : "beq",
2145 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2147 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2148 likely
? "beql" : "beq",
2155 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2157 imm_expr
.X_add_number
++;
2161 if (mask
== M_BGEUL_I
)
2163 if (imm_expr
.X_add_number
== 0)
2165 if (imm_expr
.X_add_number
== 1)
2167 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2168 likely
? "bnel" : "bne",
2172 set_at (&icnt
, sreg
, 1);
2173 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2174 likely
? "beql" : "beq",
2183 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2184 likely
? "bgtzl" : "bgtz",
2190 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2191 likely
? "bltzl" : "bltz",
2195 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2196 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2197 likely
? "bnel" : "bne",
2206 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2207 likely
? "bnel" : "bne",
2213 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2215 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2216 likely
? "bnel" : "bne",
2225 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2226 likely
? "blezl" : "blez",
2232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2233 likely
? "bgezl" : "bgez",
2237 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2239 likely
? "beql" : "beq",
2246 maxnum
= 0x7fffffff;
2254 if (imm_expr
.X_add_number
>= maxnum
2255 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2257 imm_expr
.X_add_number
++;
2261 if (mask
== M_BLTL_I
)
2263 if (imm_expr
.X_add_number
== 0)
2265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2266 likely
? "bltzl" : "bltz",
2270 if (imm_expr
.X_add_number
== 1)
2272 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2273 likely
? "blezl" : "blez",
2277 set_at (&icnt
, sreg
, 0);
2278 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2279 likely
? "bnel" : "bne",
2288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2289 likely
? "beql" : "beq",
2295 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2297 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2298 likely
? "beql" : "beq",
2305 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2307 imm_expr
.X_add_number
++;
2311 if (mask
== M_BLTUL_I
)
2313 if (imm_expr
.X_add_number
== 0)
2315 if (imm_expr
.X_add_number
== 1)
2317 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2318 likely
? "beql" : "beq",
2322 set_at (&icnt
, sreg
, 1);
2323 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2324 likely
? "bnel" : "bne",
2333 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2334 likely
? "bltzl" : "bltz",
2340 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2341 likely
? "bgtzl" : "bgtz",
2345 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2346 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2347 likely
? "bnel" : "bne",
2358 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2359 likely
? "bnel" : "bne",
2363 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2365 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2366 likely
? "bnel" : "bne",
2382 as_warn ("Divide by zero.");
2384 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2386 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2390 mips_emit_delays ();
2392 mips_any_noreorder
= 1;
2393 macro_build ((char *) NULL
, &icnt
, NULL
,
2394 dbl
? "ddiv" : "div",
2395 "z,s,t", sreg
, treg
);
2397 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2400 expr1
.X_add_number
= 8;
2401 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2402 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2403 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2405 expr1
.X_add_number
= -1;
2406 macro_build ((char *) NULL
, &icnt
, &expr1
,
2407 dbl
? "daddiu" : "addiu",
2408 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2409 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2410 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2413 expr1
.X_add_number
= 1;
2414 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2415 (int) BFD_RELOC_LO16
);
2416 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2421 expr1
.X_add_number
= 0x80000000;
2422 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2423 (int) BFD_RELOC_HI16
);
2426 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2429 expr1
.X_add_number
= 8;
2430 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2431 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2432 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2435 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2474 if (imm_expr
.X_add_number
== 0)
2476 as_warn ("Divide by zero.");
2478 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2480 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2483 if (imm_expr
.X_add_number
== 1)
2485 if (strcmp (s2
, "mflo") == 0)
2486 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2489 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2492 if (imm_expr
.X_add_number
== -1
2493 && s
[strlen (s
) - 1] != 'u')
2495 if (strcmp (s2
, "mflo") == 0)
2498 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2501 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2505 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2509 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2510 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2511 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2530 mips_emit_delays ();
2532 mips_any_noreorder
= 1;
2533 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2535 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2538 expr1
.X_add_number
= 8;
2539 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2540 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2541 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2544 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2550 /* Load the address of a symbol into a register. If breg is not
2551 zero, we then add a base register to it. */
2553 /* When generating embedded PIC code, we permit expressions of
2556 where bar is an address in the .text section. These are used
2557 when getting the addresses of functions. We don't permit
2558 X_add_number to be non-zero, because if the symbol is
2559 external the relaxing code needs to know that any addend is
2560 purely the offset to X_op_symbol. */
2561 if (mips_pic
== EMBEDDED_PIC
2562 && offset_expr
.X_op
== O_subtract
2563 && now_seg
== text_section
2564 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2565 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2566 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2567 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2568 ->sy_value
.X_add_symbol
)
2571 && offset_expr
.X_add_number
== 0)
2573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2574 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2575 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2576 mips_isa
< 3 ? "addiu" : "daddiu",
2577 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2581 if (offset_expr
.X_op
!= O_symbol
2582 && offset_expr
.X_op
!= O_constant
)
2584 as_bad ("expression too complex");
2585 offset_expr
.X_op
= O_constant
;
2599 if (offset_expr
.X_op
== O_constant
)
2600 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2601 else if (mips_pic
== NO_PIC
)
2603 /* If this is a reference to an GP relative symbol, we want
2604 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2606 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2607 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2608 If we have a constant, we need two instructions anyhow,
2609 so we may as well always use the latter form. */
2610 if (offset_expr
.X_add_number
!= 0
2611 || nopic_need_relax (offset_expr
.X_add_symbol
))
2616 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2617 mips_isa
< 3 ? "addiu" : "daddiu",
2618 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2619 p
= frag_var (rs_machine_dependent
, 8, 0,
2620 RELAX_ENCODE (4, 8, 0, 4, 0,
2621 mips_warn_about_macros
),
2622 offset_expr
.X_add_symbol
, (long) 0,
2625 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2628 macro_build (p
, &icnt
, &offset_expr
,
2629 mips_isa
< 3 ? "addiu" : "daddiu",
2630 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2632 else if (mips_pic
== SVR4_PIC
)
2634 /* If this is a reference to an external symbol, and there
2635 is no constant, we want
2636 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2637 For a local symbol, we want
2638 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2640 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2642 If we have a small constant, and this is a reference to
2643 an external symbol, we want
2644 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2646 addiu $tempreg,$tempreg,<constant>
2647 For a local symbol, we want the same instruction
2648 sequence, but we output a BFD_RELOC_LO16 reloc on the
2651 If we have a large constant, and this is a reference to
2652 an external symbol, we want
2653 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2654 lui $at,<hiconstant>
2655 addiu $at,$at,<loconstant>
2656 addu $tempreg,$tempreg,$at
2657 For a local symbol, we want the same instruction
2658 sequence, but we output a BFD_RELOC_LO16 reloc on the
2659 addiu instruction. */
2660 expr1
.X_add_number
= offset_expr
.X_add_number
;
2661 offset_expr
.X_add_number
= 0;
2663 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2665 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2666 if (expr1
.X_add_number
== 0)
2674 /* We're going to put in an addu instruction using
2675 tempreg, so we may as well insert the nop right
2677 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2681 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2682 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2684 ? mips_warn_about_macros
2686 offset_expr
.X_add_symbol
, (long) 0,
2690 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2693 macro_build (p
, &icnt
, &expr1
,
2694 mips_isa
< 3 ? "addiu" : "daddiu",
2695 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2696 /* FIXME: If breg == 0, and the next instruction uses
2697 $tempreg, then if this variant case is used an extra
2698 nop will be generated. */
2700 else if (expr1
.X_add_number
>= -0x8000
2701 && expr1
.X_add_number
< 0x8000)
2703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2705 macro_build ((char *) NULL
, &icnt
, &expr1
,
2706 mips_isa
< 3 ? "addiu" : "daddiu",
2707 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2708 (void) frag_var (rs_machine_dependent
, 0, 0,
2709 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2710 offset_expr
.X_add_symbol
, (long) 0,
2717 /* If we are going to add in a base register, and the
2718 target register and the base register are the same,
2719 then we are using AT as a temporary register. Since
2720 we want to load the constant into AT, we add our
2721 current AT (from the global offset table) and the
2722 register into the register now, and pretend we were
2723 not using a base register. */
2728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2730 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2731 mips_isa
< 3 ? "addu" : "daddu",
2732 "d,v,t", treg
, AT
, breg
);
2738 /* Set mips_optimize around the lui instruction to avoid
2739 inserting an unnecessary nop after the lw. */
2740 hold_mips_optimize
= mips_optimize
;
2742 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2743 mips_optimize
= hold_mips_optimize
;
2745 macro_build ((char *) NULL
, &icnt
, &expr1
,
2746 mips_isa
< 3 ? "addiu" : "daddiu",
2747 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2748 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2749 mips_isa
< 3 ? "addu" : "daddu",
2750 "d,v,t", tempreg
, tempreg
, AT
);
2751 (void) frag_var (rs_machine_dependent
, 0, 0,
2752 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2753 offset_expr
.X_add_symbol
, (long) 0,
2758 else if (mips_pic
== EMBEDDED_PIC
)
2761 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2763 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2764 mips_isa
< 3 ? "addiu" : "daddiu",
2765 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2771 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2772 mips_isa
< 3 ? "addu" : "daddu",
2773 "d,v,t", treg
, tempreg
, breg
);
2781 /* The j instruction may not be used in PIC code, since it
2782 requires an absolute address. We convert it to a b
2784 if (mips_pic
== NO_PIC
)
2785 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2787 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2790 /* The jal instructions must be handled as macros because when
2791 generating PIC code they expand to multi-instruction
2792 sequences. Normally they are simple instructions. */
2797 if (mips_pic
== NO_PIC
2798 || mips_pic
== EMBEDDED_PIC
)
2799 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2801 else if (mips_pic
== SVR4_PIC
)
2803 if (sreg
!= PIC_CALL_REG
)
2804 as_warn ("MIPS PIC call to register other than $25");
2806 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2808 if (mips_cprestore_offset
< 0)
2809 as_warn ("No .cprestore pseudo-op used in PIC code");
2812 expr1
.X_add_number
= mips_cprestore_offset
;
2813 macro_build ((char *) NULL
, &icnt
, &expr1
,
2814 mips_isa
< 3 ? "lw" : "ld",
2815 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2824 if (mips_pic
== NO_PIC
)
2825 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2826 else if (mips_pic
== SVR4_PIC
)
2828 /* If this is a reference to an external symbol, we want
2829 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2833 lw $gp,cprestore($sp)
2834 The cprestore value is set using the .cprestore
2835 pseudo-op. If the symbol is not external, we want
2836 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2838 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2841 lw $gp,cprestore($sp)
2844 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2845 mips_isa
< 3 ? "lw" : "ld",
2846 "t,o(b)", PIC_CALL_REG
,
2847 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2848 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2849 p
= frag_var (rs_machine_dependent
, 4, 0,
2850 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2851 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2852 macro_build (p
, &icnt
, &offset_expr
,
2853 mips_isa
< 3 ? "addiu" : "daddiu",
2854 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2855 (int) BFD_RELOC_LO16
);
2856 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2857 "jalr", "s", PIC_CALL_REG
);
2858 if (mips_cprestore_offset
< 0)
2859 as_warn ("No .cprestore pseudo-op used in PIC code");
2863 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2865 expr1
.X_add_number
= mips_cprestore_offset
;
2866 macro_build ((char *) NULL
, &icnt
, &expr1
,
2867 mips_isa
< 3 ? "lw" : "ld",
2868 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2872 else if (mips_pic
== EMBEDDED_PIC
)
2874 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2875 /* The linker may expand the call to a longer sequence which
2876 uses $at, so we must break rather than return. */
2952 if (breg
== treg
|| coproc
|| lr
)
3021 if (mask
== M_LWC1_AB
3022 || mask
== M_SWC1_AB
3023 || mask
== M_LDC1_AB
3024 || mask
== M_SDC1_AB
3033 if (offset_expr
.X_op
!= O_constant
3034 && offset_expr
.X_op
!= O_symbol
)
3036 as_bad ("expression too complex");
3037 offset_expr
.X_op
= O_constant
;
3040 /* A constant expression in PIC code can be handled just as it
3041 is in non PIC code. */
3042 if (mips_pic
== NO_PIC
3043 || offset_expr
.X_op
== O_constant
)
3045 /* If this is a reference to a GP relative symbol, and there
3046 is no base register, we want
3047 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3048 Otherwise, if there is no base register, we want
3049 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3050 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3051 If we have a constant, we need two instructions anyhow,
3052 so we always use the latter form.
3054 If we have a base register, and this is a reference to a
3055 GP relative symbol, we want
3056 addu $tempreg,$breg,$gp
3057 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3059 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3060 addu $tempreg,$tempreg,$breg
3061 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3062 With a constant we always use the latter case. */
3065 if (offset_expr
.X_add_number
!= 0
3066 || nopic_need_relax (offset_expr
.X_add_symbol
))
3071 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3072 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3073 p
= frag_var (rs_machine_dependent
, 8, 0,
3074 RELAX_ENCODE (4, 8, 0, 4, 0,
3075 (mips_warn_about_macros
3076 || (used_at
&& mips_noat
))),
3077 offset_expr
.X_add_symbol
, (long) 0,
3081 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3084 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3085 (int) BFD_RELOC_LO16
, tempreg
);
3089 if (offset_expr
.X_add_number
!= 0
3090 || nopic_need_relax (offset_expr
.X_add_symbol
))
3095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3096 mips_isa
< 3 ? "addu" : "daddu",
3097 "d,v,t", tempreg
, breg
, GP
);
3098 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3099 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3100 p
= frag_var (rs_machine_dependent
, 12, 0,
3101 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3102 offset_expr
.X_add_symbol
, (long) 0,
3105 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3108 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3109 mips_isa
< 3 ? "addu" : "daddu",
3110 "d,v,t", tempreg
, tempreg
, breg
);
3113 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3114 (int) BFD_RELOC_LO16
, tempreg
);
3117 else if (mips_pic
== SVR4_PIC
)
3119 /* If this is a reference to an external symbol, we want
3120 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3122 <op> $treg,0($tempreg)
3124 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3126 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3127 <op> $treg,0($tempreg)
3128 If there is a base register, we add it to $tempreg before
3129 the <op>. If there is a constant, we stick it in the
3130 <op> instruction. We don't handle constants larger than
3131 16 bits, because we have no way to load the upper 16 bits
3132 (actually, we could handle them for the subset of cases
3133 in which we are not using $at). */
3134 assert (offset_expr
.X_op
== O_symbol
);
3135 expr1
.X_add_number
= offset_expr
.X_add_number
;
3136 offset_expr
.X_add_number
= 0;
3137 if (expr1
.X_add_number
< -0x8000
3138 || expr1
.X_add_number
>= 0x8000)
3139 as_bad ("PIC code offset overflow (max 16 signed bits)");
3141 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3142 mips_isa
< 3 ? "lw" : "ld",
3143 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3145 p
= frag_var (rs_machine_dependent
, 4, 0,
3146 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3147 offset_expr
.X_add_symbol
, (long) 0,
3149 macro_build (p
, &icnt
, &offset_expr
,
3150 mips_isa
< 3 ? "addiu" : "daddiu",
3151 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3153 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3154 mips_isa
< 3 ? "addu" : "daddu",
3155 "d,v,t", tempreg
, tempreg
, breg
);
3156 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3157 (int) BFD_RELOC_LO16
, tempreg
);
3159 else if (mips_pic
== EMBEDDED_PIC
)
3161 /* If there is no base register, we want
3162 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3163 If there is a base register, we want
3164 addu $tempreg,$breg,$gp
3165 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3167 assert (offset_expr
.X_op
== O_symbol
);
3170 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3171 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3177 mips_isa
< 3 ? "addu" : "daddu",
3178 "d,v,t", tempreg
, breg
, GP
);
3179 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3180 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3193 load_register (&icnt
, treg
, &imm_expr
, 0);
3197 load_register (&icnt
, treg
, &imm_expr
, 1);
3201 if (imm_expr
.X_op
== O_constant
)
3203 load_register (&icnt
, AT
, &imm_expr
, 0);
3204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3205 "mtc1", "t,G", AT
, treg
);
3210 assert (offset_expr
.X_op
== O_symbol
3211 && strcmp (segment_name (S_GET_SEGMENT
3212 (offset_expr
.X_add_symbol
)),
3214 && offset_expr
.X_add_number
== 0);
3215 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3216 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3221 /* We know that sym is in the .rdata section. First we get the
3222 upper 16 bits of the address. */
3223 if (mips_pic
== NO_PIC
)
3225 /* FIXME: This won't work for a 64 bit address. */
3226 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3228 else if (mips_pic
== SVR4_PIC
)
3230 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3231 mips_isa
< 3 ? "lw" : "ld",
3232 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3234 else if (mips_pic
== EMBEDDED_PIC
)
3236 /* For embedded PIC we pick up the entire address off $gp in
3237 a single instruction. */
3238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3239 mips_isa
< 3 ? "addiu" : "daddiu",
3240 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3241 offset_expr
.X_op
= O_constant
;
3242 offset_expr
.X_add_number
= 0;
3247 /* Now we load the register(s). */
3249 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3250 treg
, (int) BFD_RELOC_LO16
, AT
);
3253 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3254 treg
, (int) BFD_RELOC_LO16
, AT
);
3257 /* FIXME: How in the world do we deal with the possible
3259 offset_expr
.X_add_number
+= 4;
3260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3261 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3265 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3266 does not become a variant frag. */
3267 frag_wane (frag_now
);
3273 assert (offset_expr
.X_op
== O_symbol
3274 && offset_expr
.X_add_number
== 0);
3275 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3276 if (strcmp (s
, ".lit8") == 0)
3280 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3281 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3285 r
= BFD_RELOC_MIPS_LITERAL
;
3290 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3291 if (mips_pic
== SVR4_PIC
)
3292 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3293 mips_isa
< 3 ? "lw" : "ld",
3294 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3297 /* FIXME: This won't work for a 64 bit address. */
3298 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3303 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3304 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3306 /* To avoid confusion in tc_gen_reloc, we must ensure
3307 that this does not become a variant frag. */
3308 frag_wane (frag_now
);
3319 /* Even on a big endian machine $fn comes before $fn+1. We have
3320 to adjust when loading from memory. */
3323 assert (mips_isa
< 2);
3324 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3325 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3327 /* FIXME: A possible overflow which I don't know how to deal
3329 offset_expr
.X_add_number
+= 4;
3330 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3331 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3334 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3335 does not become a variant frag. */
3336 frag_wane (frag_now
);
3345 * The MIPS assembler seems to check for X_add_number not
3346 * being double aligned and generating:
3349 * addiu at,at,%lo(foo+1)
3352 * But, the resulting address is the same after relocation so why
3353 * generate the extra instruction?
3400 if (offset_expr
.X_op
!= O_symbol
3401 && offset_expr
.X_op
!= O_constant
)
3403 as_bad ("expression too complex");
3404 offset_expr
.X_op
= O_constant
;
3407 /* Even on a big endian machine $fn comes before $fn+1. We have
3408 to adjust when loading from memory. We set coproc if we must
3409 load $fn+1 first. */
3410 if (byte_order
== LITTLE_ENDIAN
)
3413 if (mips_pic
== NO_PIC
3414 || offset_expr
.X_op
== O_constant
)
3416 /* If this is a reference to a GP relative symbol, we want
3417 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3418 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3419 If we have a base register, we use this
3421 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3422 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3423 If this is not a GP relative symbol, we want
3424 lui $at,<sym> (BFD_RELOC_HI16_S)
3425 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3426 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3427 If there is a base register, we add it to $at after the
3428 lui instruction. If there is a constant, we always use
3430 if (offset_expr
.X_add_number
!= 0
3431 || nopic_need_relax (offset_expr
.X_add_symbol
))
3450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3451 mips_isa
< 3 ? "addu" : "daddu",
3452 "d,v,t", AT
, breg
, GP
);
3458 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3459 coproc
? treg
+ 1 : treg
,
3460 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3461 offset_expr
.X_add_number
+= 4;
3463 /* Set mips_optimize to 2 to avoid inserting an
3465 hold_mips_optimize
= mips_optimize
;
3467 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3468 coproc
? treg
: treg
+ 1,
3469 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3470 mips_optimize
= hold_mips_optimize
;
3472 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3473 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3474 used_at
&& mips_noat
),
3475 offset_expr
.X_add_symbol
, (long) 0,
3478 /* We just generated two relocs. When tc_gen_reloc
3479 handles this case, it will skip the first reloc and
3480 handle the second. The second reloc already has an
3481 extra addend of 4, which we added above. We must
3482 subtract it out, and then subtract another 4 to make
3483 the first reloc come out right. The second reloc
3484 will come out right because we are going to add 4 to
3485 offset_expr when we build its instruction below. */
3486 offset_expr
.X_add_number
-= 8;
3487 offset_expr
.X_op
= O_constant
;
3489 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3494 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3495 mips_isa
< 3 ? "addu" : "daddu",
3496 "d,v,t", AT
, breg
, AT
);
3500 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3501 coproc
? treg
+ 1 : treg
,
3502 (int) BFD_RELOC_LO16
, AT
);
3505 /* FIXME: How do we handle overflow here? */
3506 offset_expr
.X_add_number
+= 4;
3507 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3508 coproc
? treg
: treg
+ 1,
3509 (int) BFD_RELOC_LO16
, AT
);
3511 else if (mips_pic
== SVR4_PIC
)
3515 /* If this is a reference to an external symbol, we want
3516 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3521 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3523 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3524 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3525 If there is a base register we add it to $at before the
3526 lwc1 instructions. If there is a constant we include it
3527 in the lwc1 instructions. */
3529 expr1
.X_add_number
= offset_expr
.X_add_number
;
3530 offset_expr
.X_add_number
= 0;
3531 if (expr1
.X_add_number
< -0x8000
3532 || expr1
.X_add_number
>= 0x8000 - 4)
3533 as_bad ("PIC code offset overflow (max 16 signed bits)");
3538 frag_grow (24 + off
);
3539 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3540 mips_isa
< 3 ? "lw" : "ld",
3541 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3545 mips_isa
< 3 ? "addu" : "daddu",
3546 "d,v,t", AT
, breg
, AT
);
3547 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3548 coproc
? treg
+ 1 : treg
,
3549 (int) BFD_RELOC_LO16
, AT
);
3550 expr1
.X_add_number
+= 4;
3552 /* Set mips_optimize to 2 to avoid inserting an undesired
3554 hold_mips_optimize
= mips_optimize
;
3556 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3557 coproc
? treg
: treg
+ 1,
3558 (int) BFD_RELOC_LO16
, AT
);
3559 mips_optimize
= hold_mips_optimize
;
3561 (void) frag_var (rs_machine_dependent
, 0, 0,
3562 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3563 offset_expr
.X_add_symbol
, (long) 0,
3566 else if (mips_pic
== EMBEDDED_PIC
)
3568 /* If there is no base register, we use
3569 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3570 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3571 If we have a base register, we use
3573 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3574 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3583 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3584 mips_isa
< 3 ? "addu" : "daddu",
3585 "d,v,t", AT
, breg
, GP
);
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3591 coproc
? treg
+ 1 : treg
,
3592 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3593 offset_expr
.X_add_number
+= 4;
3594 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3595 coproc
? treg
: treg
+ 1,
3596 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3612 assert (mips_isa
< 3);
3613 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3614 (int) BFD_RELOC_LO16
, breg
);
3615 offset_expr
.X_add_number
+= 4;
3616 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3617 (int) BFD_RELOC_LO16
, breg
);
3619 #ifdef LOSING_COMPILER
3625 as_warn ("Macro used $at after \".set noat\"");
3630 struct mips_cl_insn
*ip
;
3632 register int treg
, sreg
, dreg
, breg
;
3647 bfd_reloc_code_real_type r
;
3650 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3651 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3652 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3653 mask
= ip
->insn_mo
->mask
;
3655 expr1
.X_op
= O_constant
;
3656 expr1
.X_op_symbol
= NULL
;
3657 expr1
.X_add_symbol
= NULL
;
3658 expr1
.X_add_number
= 1;
3662 #endif /* LOSING_COMPILER */
3667 macro_build ((char *) NULL
, &icnt
, NULL
,
3668 dbl
? "dmultu" : "multu",
3670 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3676 /* The MIPS assembler some times generates shifts and adds. I'm
3677 not trying to be that fancy. GCC should do this for us
3679 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3680 macro_build ((char *) NULL
, &icnt
, NULL
,
3681 dbl
? "dmult" : "mult",
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3689 mips_emit_delays ();
3691 mips_any_noreorder
= 1;
3692 macro_build ((char *) NULL
, &icnt
, NULL
,
3693 dbl
? "dmult" : "mult",
3695 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3696 macro_build ((char *) NULL
, &icnt
, NULL
,
3697 dbl
? "dsra32" : "sra",
3698 "d,w,<", dreg
, dreg
, 31);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3701 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3704 expr1
.X_add_number
= 8;
3705 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3706 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3707 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3710 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3716 mips_emit_delays ();
3718 mips_any_noreorder
= 1;
3719 macro_build ((char *) NULL
, &icnt
, NULL
,
3720 dbl
? "dmultu" : "multu",
3722 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3723 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3725 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3728 expr1
.X_add_number
= 8;
3729 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3730 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3731 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3737 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3738 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3739 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3741 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3745 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3746 imm_expr
.X_add_number
& 0x1f);
3747 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3748 (0 - imm_expr
.X_add_number
) & 0x1f);
3749 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3753 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3754 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3755 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3757 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3761 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3762 imm_expr
.X_add_number
& 0x1f);
3763 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3764 (0 - imm_expr
.X_add_number
) & 0x1f);
3765 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3769 assert (mips_isa
< 2);
3770 /* Even on a big endian machine $fn comes before $fn+1. We have
3771 to adjust when storing to memory. */
3772 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3773 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3774 (int) BFD_RELOC_LO16
, breg
);
3775 offset_expr
.X_add_number
+= 4;
3776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3777 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3778 (int) BFD_RELOC_LO16
, breg
);
3783 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3784 treg
, (int) BFD_RELOC_LO16
);
3786 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3787 sreg
, (int) BFD_RELOC_LO16
);
3790 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3792 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3793 dreg
, (int) BFD_RELOC_LO16
);
3798 if (imm_expr
.X_add_number
== 0)
3800 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3801 sreg
, (int) BFD_RELOC_LO16
);
3806 as_warn ("Instruction %s: result is always false",
3808 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3811 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3813 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3814 sreg
, (int) BFD_RELOC_LO16
);
3817 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3819 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3820 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3821 mips_isa
< 3 ? "addiu" : "daddiu",
3822 "t,r,j", dreg
, sreg
,
3823 (int) BFD_RELOC_LO16
);
3828 load_register (&icnt
, AT
, &imm_expr
, 0);
3829 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3833 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3834 (int) BFD_RELOC_LO16
);
3839 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3845 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3846 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3847 (int) BFD_RELOC_LO16
);
3850 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3852 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3854 macro_build ((char *) NULL
, &icnt
, &expr1
,
3855 mask
== M_SGE_I
? "slti" : "sltiu",
3856 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3861 load_register (&icnt
, AT
, &imm_expr
, 0);
3862 macro_build ((char *) NULL
, &icnt
, NULL
,
3863 mask
== M_SGE_I
? "slt" : "sltu",
3864 "d,v,t", dreg
, sreg
, AT
);
3867 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3868 (int) BFD_RELOC_LO16
);
3873 case M_SGT
: /* sreg > treg <==> treg < sreg */
3879 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3882 case M_SGT_I
: /* sreg > I <==> I < sreg */
3888 load_register (&icnt
, AT
, &imm_expr
, 0);
3889 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3892 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3898 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3899 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3900 (int) BFD_RELOC_LO16
);
3903 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3909 load_register (&icnt
, AT
, &imm_expr
, 0);
3910 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3911 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3912 (int) BFD_RELOC_LO16
);
3916 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3918 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3919 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3922 load_register (&icnt
, AT
, &imm_expr
, 0);
3923 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3927 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3929 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3930 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3933 load_register (&icnt
, AT
, &imm_expr
, 0);
3934 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3940 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3943 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3947 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3949 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3955 if (imm_expr
.X_add_number
== 0)
3957 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3963 as_warn ("Instruction %s: result is always true",
3965 macro_build ((char *) NULL
, &icnt
, &expr1
,
3966 mips_isa
< 3 ? "addiu" : "daddiu",
3967 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3970 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3972 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3973 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3976 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3978 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3979 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3980 mips_isa
< 3 ? "addiu" : "daddiu",
3981 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3986 load_register (&icnt
, AT
, &imm_expr
, 0);
3987 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3991 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3999 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4001 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4002 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4003 dbl
? "daddi" : "addi",
4004 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4007 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4008 macro_build ((char *) NULL
, &icnt
, NULL
,
4009 dbl
? "dsub" : "sub",
4010 "d,v,t", dreg
, sreg
, AT
);
4016 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4018 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4019 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4020 dbl
? "daddiu" : "addiu",
4021 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4024 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4025 macro_build ((char *) NULL
, &icnt
, NULL
,
4026 dbl
? "dsubu" : "subu",
4027 "d,v,t", dreg
, sreg
, AT
);
4048 load_register (&icnt
, AT
, &imm_expr
, 0);
4049 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4054 assert (mips_isa
< 2);
4055 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4056 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4059 * Is the double cfc1 instruction a bug in the mips assembler;
4060 * or is there a reason for it?
4062 mips_emit_delays ();
4064 mips_any_noreorder
= 1;
4065 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4067 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4068 expr1
.X_add_number
= 3;
4069 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4070 (int) BFD_RELOC_LO16
);
4071 expr1
.X_add_number
= 2;
4072 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4073 (int) BFD_RELOC_LO16
);
4074 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4075 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4076 macro_build ((char *) NULL
, &icnt
, NULL
,
4077 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4078 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4079 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4089 if (offset_expr
.X_add_number
>= 0x7fff)
4090 as_bad ("operand overflow");
4091 /* avoid load delay */
4092 if (byte_order
== LITTLE_ENDIAN
)
4093 offset_expr
.X_add_number
+= 1;
4094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4095 (int) BFD_RELOC_LO16
, breg
);
4096 if (byte_order
== LITTLE_ENDIAN
)
4097 offset_expr
.X_add_number
-= 1;
4099 offset_expr
.X_add_number
+= 1;
4100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4101 (int) BFD_RELOC_LO16
, breg
);
4102 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4116 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4117 as_bad ("operand overflow");
4118 if (byte_order
== LITTLE_ENDIAN
)
4119 offset_expr
.X_add_number
+= off
;
4120 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4121 (int) BFD_RELOC_LO16
, breg
);
4122 if (byte_order
== LITTLE_ENDIAN
)
4123 offset_expr
.X_add_number
-= off
;
4125 offset_expr
.X_add_number
+= off
;
4126 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4127 (int) BFD_RELOC_LO16
, breg
);
4140 load_address (&icnt
, AT
, &offset_expr
);
4141 if (byte_order
== LITTLE_ENDIAN
)
4142 expr1
.X_add_number
= off
;
4144 expr1
.X_add_number
= 0;
4145 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4146 (int) BFD_RELOC_LO16
, AT
);
4147 if (byte_order
== LITTLE_ENDIAN
)
4148 expr1
.X_add_number
= 0;
4150 expr1
.X_add_number
= off
;
4151 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4152 (int) BFD_RELOC_LO16
, AT
);
4157 load_address (&icnt
, AT
, &offset_expr
);
4158 if (byte_order
== BIG_ENDIAN
)
4159 expr1
.X_add_number
= 0;
4160 macro_build ((char *) NULL
, &icnt
, &expr1
,
4161 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4162 (int) BFD_RELOC_LO16
, AT
);
4163 if (byte_order
== BIG_ENDIAN
)
4164 expr1
.X_add_number
= 1;
4166 expr1
.X_add_number
= 0;
4167 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4168 (int) BFD_RELOC_LO16
, AT
);
4169 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4171 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4176 if (offset_expr
.X_add_number
>= 0x7fff)
4177 as_bad ("operand overflow");
4178 if (byte_order
== BIG_ENDIAN
)
4179 offset_expr
.X_add_number
+= 1;
4180 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4181 (int) BFD_RELOC_LO16
, breg
);
4182 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4183 if (byte_order
== BIG_ENDIAN
)
4184 offset_expr
.X_add_number
-= 1;
4186 offset_expr
.X_add_number
+= 1;
4187 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4188 (int) BFD_RELOC_LO16
, breg
);
4201 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4202 as_bad ("operand overflow");
4203 if (byte_order
== LITTLE_ENDIAN
)
4204 offset_expr
.X_add_number
+= off
;
4205 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4206 (int) BFD_RELOC_LO16
, breg
);
4207 if (byte_order
== LITTLE_ENDIAN
)
4208 offset_expr
.X_add_number
-= off
;
4210 offset_expr
.X_add_number
+= off
;
4211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4212 (int) BFD_RELOC_LO16
, breg
);
4225 load_address (&icnt
, AT
, &offset_expr
);
4226 if (byte_order
== LITTLE_ENDIAN
)
4227 expr1
.X_add_number
= off
;
4229 expr1
.X_add_number
= 0;
4230 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4231 (int) BFD_RELOC_LO16
, AT
);
4232 if (byte_order
== LITTLE_ENDIAN
)
4233 expr1
.X_add_number
= 0;
4235 expr1
.X_add_number
= off
;
4236 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4237 (int) BFD_RELOC_LO16
, AT
);
4241 load_address (&icnt
, AT
, &offset_expr
);
4242 if (byte_order
== LITTLE_ENDIAN
)
4243 expr1
.X_add_number
= 0;
4244 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4245 (int) BFD_RELOC_LO16
, AT
);
4246 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4248 if (byte_order
== LITTLE_ENDIAN
)
4249 expr1
.X_add_number
= 1;
4251 expr1
.X_add_number
= 0;
4252 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4253 (int) BFD_RELOC_LO16
, AT
);
4254 if (byte_order
== LITTLE_ENDIAN
)
4255 expr1
.X_add_number
= 0;
4257 expr1
.X_add_number
= 1;
4258 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4259 (int) BFD_RELOC_LO16
, AT
);
4260 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4262 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4267 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4271 as_warn ("Macro used $at after \".set noat\"");
4276 This routine assembles an instruction into its binary format. As a side
4277 effect it sets one of the global variables imm_reloc or offset_reloc to the
4278 type of relocation to do if one of the operands is an address expression.
4283 struct mips_cl_insn
*ip
;
4288 struct mips_opcode
*insn
;
4291 unsigned int lastregno
= 0;
4296 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4308 as_fatal ("Unknown opcode: `%s'", str
);
4310 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4312 as_warn ("`%s' not in hash table.", str
);
4313 insn_error
= "ERROR: Unrecognized opcode";
4321 assert (strcmp (insn
->name
, str
) == 0);
4323 if (insn
->pinfo
== INSN_MACRO
)
4324 insn_isa
= insn
->match
;
4325 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4327 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4329 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
4334 if (insn_isa
> mips_isa
4335 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4338 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4339 && strcmp (insn
->name
, insn
[1].name
) == 0)
4344 as_warn ("Instruction not supported on this processor");
4348 ip
->insn_opcode
= insn
->match
;
4349 for (args
= insn
->args
;; ++args
)
4355 case '\0': /* end of args */
4368 ip
->insn_opcode
|= lastregno
<< 21;
4373 ip
->insn_opcode
|= lastregno
<< 16;
4377 ip
->insn_opcode
|= lastregno
<< 11;
4383 /* handle optional base register.
4384 Either the base register is omitted or
4385 we must have a left paren. */
4386 /* this is dependent on the next operand specifier
4387 is a 'b' for base register */
4388 assert (args
[1] == 'b');
4392 case ')': /* these must match exactly */
4397 case '<': /* must be at least one digit */
4399 * According to the manual, if the shift amount is greater
4400 * than 31 or less than 0 the the shift amount should be
4401 * mod 32. In reality the mips assembler issues an error.
4402 * We issue a warning and mask out all but the low 5 bits.
4404 my_getExpression (&imm_expr
, s
);
4405 check_absolute_expr (ip
, &imm_expr
);
4406 if ((unsigned long) imm_expr
.X_add_number
> 31)
4408 as_warn ("Improper shift amount (%ld)",
4409 (long) imm_expr
.X_add_number
);
4410 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4412 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4413 imm_expr
.X_op
= O_absent
;
4417 case '>': /* shift amount minus 32 */
4418 my_getExpression (&imm_expr
, s
);
4419 check_absolute_expr (ip
, &imm_expr
);
4420 if ((unsigned long) imm_expr
.X_add_number
< 32
4421 || (unsigned long) imm_expr
.X_add_number
> 63)
4423 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4424 imm_expr
.X_op
= O_absent
;
4428 case 'k': /* cache code */
4429 case 'h': /* prefx code */
4430 my_getExpression (&imm_expr
, s
);
4431 check_absolute_expr (ip
, &imm_expr
);
4432 if ((unsigned long) imm_expr
.X_add_number
> 31)
4434 as_warn ("Invalid value for `%s' (%lu)",
4436 (unsigned long) imm_expr
.X_add_number
);
4437 imm_expr
.X_add_number
&= 0x1f;
4440 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4442 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
4443 imm_expr
.X_op
= O_absent
;
4447 case 'c': /* break code */
4448 my_getExpression (&imm_expr
, s
);
4449 check_absolute_expr (ip
, &imm_expr
);
4450 if ((unsigned) imm_expr
.X_add_number
> 1023)
4451 as_warn ("Illegal break code (%ld)",
4452 (long) imm_expr
.X_add_number
);
4453 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4454 imm_expr
.X_op
= O_absent
;
4458 case 'B': /* syscall code */
4459 my_getExpression (&imm_expr
, s
);
4460 check_absolute_expr (ip
, &imm_expr
);
4461 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4462 as_warn ("Illegal syscall code (%ld)",
4463 (long) imm_expr
.X_add_number
);
4464 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4465 imm_expr
.X_op
= O_absent
;
4469 case 'C': /* Coprocessor code */
4470 my_getExpression (&imm_expr
, s
);
4471 check_absolute_expr (ip
, &imm_expr
);
4472 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4474 as_warn ("Coproccesor code > 25 bits (%ld)",
4475 (long) imm_expr
.X_add_number
);
4476 imm_expr
.X_add_number
&= ((1<<25) - 1);
4478 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4479 imm_expr
.X_op
= O_absent
;
4483 case 'b': /* base register */
4484 case 'd': /* destination register */
4485 case 's': /* source register */
4486 case 't': /* target register */
4487 case 'r': /* both target and source */
4488 case 'v': /* both dest and source */
4489 case 'w': /* both dest and target */
4490 case 'E': /* coprocessor target register */
4491 case 'G': /* coprocessor destination register */
4492 case 'x': /* ignore register name */
4493 case 'z': /* must be zero register */
4507 while (isdigit (*s
));
4509 as_bad ("Invalid register number (%d)", regno
);
4511 else if (*args
== 'E' || *args
== 'G')
4515 if (s
[1] == 'f' && s
[2] == 'p')
4520 else if (s
[1] == 's' && s
[2] == 'p')
4525 else if (s
[1] == 'g' && s
[2] == 'p')
4530 else if (s
[1] == 'a' && s
[2] == 't')
4535 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
4540 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
4548 if (regno
== AT
&& ! mips_noat
)
4549 as_warn ("Used $at without \".set noat\"");
4555 if (c
== 'r' || c
== 'v' || c
== 'w')
4562 /* 'z' only matches $0. */
4563 if (c
== 'z' && regno
!= 0)
4571 ip
->insn_opcode
|= regno
<< 21;
4575 ip
->insn_opcode
|= regno
<< 11;
4580 ip
->insn_opcode
|= regno
<< 16;
4583 /* This case exists because on the r3000 trunc
4584 expands into a macro which requires a gp
4585 register. On the r6000 or r4000 it is
4586 assembled into a single instruction which
4587 ignores the register. Thus the insn version
4588 is MIPS_ISA2 and uses 'x', and the macro
4589 version is MIPS_ISA1 and uses 't'. */
4592 /* This case is for the div instruction, which
4593 acts differently if the destination argument
4594 is $0. This only matches $0, and is checked
4595 outside the switch. */
4606 ip
->insn_opcode
|= lastregno
<< 21;
4609 ip
->insn_opcode
|= lastregno
<< 16;
4614 case 'D': /* floating point destination register */
4615 case 'S': /* floating point source register */
4616 case 'T': /* floating point target register */
4617 case 'R': /* floating point source register */
4621 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4631 while (isdigit (*s
));
4634 as_bad ("Invalid float register number (%d)", regno
);
4636 if ((regno
& 1) != 0
4638 && ! (strcmp (str
, "mtc1") == 0 ||
4639 strcmp (str
, "mfc1") == 0 ||
4640 strcmp (str
, "lwc1") == 0 ||
4641 strcmp (str
, "swc1") == 0))
4642 as_warn ("Float register should be even, was %d",
4650 if (c
== 'V' || c
== 'W')
4660 ip
->insn_opcode
|= regno
<< 6;
4664 ip
->insn_opcode
|= regno
<< 11;
4668 ip
->insn_opcode
|= regno
<< 16;
4671 ip
->insn_opcode
|= regno
<< 21;
4680 ip
->insn_opcode
|= lastregno
<< 11;
4683 ip
->insn_opcode
|= lastregno
<< 16;
4689 my_getExpression (&imm_expr
, s
);
4690 if (imm_expr
.X_op
!= O_big
)
4691 check_absolute_expr (ip
, &imm_expr
);
4696 my_getExpression (&offset_expr
, s
);
4697 imm_reloc
= BFD_RELOC_32
;
4709 unsigned char temp
[8];
4711 unsigned int length
;
4716 /* These only appear as the last operand in an
4717 instruction, and every instruction that accepts
4718 them in any variant accepts them in all variants.
4719 This means we don't have to worry about backing out
4720 any changes if the instruction does not match.
4722 The difference between them is the size of the
4723 floating point constant and where it goes. For 'F'
4724 and 'L' the constant is 64 bits; for 'f' and 'l' it
4725 is 32 bits. Where the constant is placed is based
4726 on how the MIPS assembler does things:
4729 f -- immediate value
4732 The .lit4 and .lit8 sections are only used if
4733 permitted by the -G argument.
4735 When generating embedded PIC code, we use the
4736 .lit8 section but not the .lit4 section (we can do
4737 .lit4 inline easily; we need to put .lit8
4738 somewhere in the data segment, and using .lit8
4739 permits the linker to eventually combine identical
4742 f64
= *args
== 'F' || *args
== 'L';
4744 save_in
= input_line_pointer
;
4745 input_line_pointer
= s
;
4746 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4748 s
= input_line_pointer
;
4749 input_line_pointer
= save_in
;
4750 if (err
!= NULL
&& *err
!= '\0')
4752 as_bad ("Bad floating point constant: %s", err
);
4753 memset (temp
, '\0', sizeof temp
);
4754 length
= f64
? 8 : 4;
4757 assert (length
== (f64
? 8 : 4));
4761 && (! USE_GLOBAL_POINTER_OPT
4762 || mips_pic
== EMBEDDED_PIC
4763 || g_switch_value
< 4)
4766 imm_expr
.X_op
= O_constant
;
4767 if (byte_order
== LITTLE_ENDIAN
)
4768 imm_expr
.X_add_number
=
4769 (((((((int) temp
[3] << 8)
4774 imm_expr
.X_add_number
=
4775 (((((((int) temp
[0] << 8)
4782 const char *newname
;
4785 /* Switch to the right section. */
4787 subseg
= now_subseg
;
4790 default: /* unused default case avoids warnings. */
4792 newname
= RDATA_SECTION_NAME
;
4793 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
4797 newname
= RDATA_SECTION_NAME
;
4800 assert (!USE_GLOBAL_POINTER_OPT
4801 || g_switch_value
>= 4);
4805 new_seg
= subseg_new (newname
, (subsegT
) 0);
4806 frag_align (*args
== 'l' ? 2 : 3, 0);
4807 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4808 record_alignment (new_seg
, 4);
4810 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4812 as_bad ("Can't use floating point insn in this section");
4814 /* Set the argument to the current address in the
4816 offset_expr
.X_op
= O_symbol
;
4817 offset_expr
.X_add_symbol
=
4818 symbol_new ("L0\001", now_seg
,
4819 (valueT
) frag_now_fix (), frag_now
);
4820 offset_expr
.X_add_number
= 0;
4822 /* Put the floating point number into the section. */
4823 p
= frag_more ((int) length
);
4824 memcpy (p
, temp
, length
);
4826 /* Switch back to the original section. */
4827 subseg_set (seg
, subseg
);
4832 case 'i': /* 16 bit unsigned immediate */
4833 case 'j': /* 16 bit signed immediate */
4834 imm_reloc
= BFD_RELOC_LO16
;
4835 c
= my_getSmallExpression (&imm_expr
, s
);
4840 if (imm_expr
.X_op
== O_constant
)
4841 imm_expr
.X_add_number
=
4842 (imm_expr
.X_add_number
>> 16) & 0xffff;
4844 imm_reloc
= BFD_RELOC_HI16_S
;
4846 imm_reloc
= BFD_RELOC_HI16
;
4849 else if (imm_expr
.X_op
!= O_big
)
4850 check_absolute_expr (ip
, &imm_expr
);
4853 if (imm_expr
.X_op
== O_big
4854 || imm_expr
.X_add_number
< 0
4855 || imm_expr
.X_add_number
>= 0x10000)
4857 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4858 !strcmp (insn
->name
, insn
[1].name
))
4860 as_bad ("16 bit expression not in range 0..65535");
4868 /* The upper bound should be 0x8000, but
4869 unfortunately the MIPS assembler accepts numbers
4870 from 0x8000 to 0xffff and sign extends them, and
4871 we want to be compatible. We only permit this
4872 extended range for an instruction which does not
4873 provide any further alternates, since those
4874 alternates may handle other cases. People should
4875 use the numbers they mean, rather than relying on
4876 a mysterious sign extension. */
4877 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4878 strcmp (insn
->name
, insn
[1].name
) == 0);
4883 if (imm_expr
.X_op
== O_big
4884 || imm_expr
.X_add_number
< -0x8000
4885 || imm_expr
.X_add_number
>= max
4887 && imm_expr
.X_add_number
< 0
4889 && imm_expr
.X_unsigned
4890 && sizeof (imm_expr
.X_add_number
) <= 4))
4894 as_bad ("16 bit expression not in range -32768..32767");
4900 case 'o': /* 16 bit offset */
4901 c
= my_getSmallExpression (&offset_expr
, s
);
4903 /* If this value won't fit into a 16 bit offset, then go
4904 find a macro that will generate the 32 bit offset
4905 code pattern. As a special hack, we accept the
4906 difference of two local symbols as a constant. This
4907 is required to suppose embedded PIC switches, which
4908 use an instruction which looks like
4909 lw $4,$L12-$LS12($4)
4910 The problem with handling this in a more general
4911 fashion is that the macro function doesn't expect to
4912 see anything which can be handled in a single
4913 constant instruction. */
4915 && (offset_expr
.X_op
!= O_constant
4916 || offset_expr
.X_add_number
>= 0x8000
4917 || offset_expr
.X_add_number
< -0x8000)
4918 && (mips_pic
!= EMBEDDED_PIC
4919 || offset_expr
.X_op
!= O_subtract
4920 || now_seg
!= text_section
4921 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
4925 offset_reloc
= BFD_RELOC_LO16
;
4926 if (c
== 'h' || c
== 'H')
4928 assert (offset_expr
.X_op
== O_constant
);
4929 offset_expr
.X_add_number
=
4930 (offset_expr
.X_add_number
>> 16) & 0xffff;
4935 case 'p': /* pc relative offset */
4936 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4937 my_getExpression (&offset_expr
, s
);
4941 case 'u': /* upper 16 bits */
4942 c
= my_getSmallExpression (&imm_expr
, s
);
4943 if (imm_expr
.X_op
== O_constant
4944 && (imm_expr
.X_add_number
< 0
4945 || imm_expr
.X_add_number
>= 0x10000))
4946 as_bad ("lui expression not in range 0..65535");
4947 imm_reloc
= BFD_RELOC_LO16
;
4952 if (imm_expr
.X_op
== O_constant
)
4953 imm_expr
.X_add_number
=
4954 (imm_expr
.X_add_number
>> 16) & 0xffff;
4956 imm_reloc
= BFD_RELOC_HI16_S
;
4958 imm_reloc
= BFD_RELOC_HI16
;
4964 case 'a': /* 26 bit address */
4965 my_getExpression (&offset_expr
, s
);
4967 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4970 case 'N': /* 3 bit branch condition code */
4971 case 'M': /* 3 bit compare condition code */
4972 my_getExpression (&imm_expr
, s
);
4973 check_absolute_expr (ip
, &imm_expr
);
4974 if ((unsigned long) imm_expr
.X_add_number
> 7)
4976 as_warn ("Condition code > 7 (%ld)",
4977 (long) imm_expr
.X_add_number
);
4978 imm_expr
.X_add_number
&= 7;
4981 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
4983 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
4984 imm_expr
.X_op
= O_absent
;
4989 fprintf (stderr
, "bad char = '%c'\n", *args
);
4994 /* Args don't match. */
4995 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4996 !strcmp (insn
->name
, insn
[1].name
))
5002 insn_error
= "ERROR: Illegal operands";
5011 my_getSmallExpression (ep
, str
)
5022 ((str
[1] == 'h' && str
[2] == 'i')
5023 || (str
[1] == 'H' && str
[2] == 'I')
5024 || (str
[1] == 'l' && str
[2] == 'o'))
5036 * A small expression may be followed by a base register.
5037 * Scan to the end of this operand, and then back over a possible
5038 * base register. Then scan the small expression up to that
5039 * point. (Based on code in sparc.c...)
5041 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5043 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5045 if (isdigit (sp
[-2]))
5047 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5049 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5055 else if (sp
- 5 >= str
5058 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5059 || (sp
[-3] == 's' && sp
[-2] == 'p')
5060 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5061 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5067 /* no expression means zero offset */
5070 /* %xx(reg) is an error */
5071 ep
->X_op
= O_absent
;
5076 ep
->X_op
= O_constant
;
5079 ep
->X_add_symbol
= NULL
;
5080 ep
->X_op_symbol
= NULL
;
5081 ep
->X_add_number
= 0;
5086 my_getExpression (ep
, str
);
5093 my_getExpression (ep
, str
);
5094 return c
; /* => %hi or %lo encountered */
5098 my_getExpression (ep
, str
)
5104 save_in
= input_line_pointer
;
5105 input_line_pointer
= str
;
5107 expr_end
= input_line_pointer
;
5108 input_line_pointer
= save_in
;
5111 /* Turn a string in input_line_pointer into a floating point constant
5112 of type type, and store the appropriate bytes in *litP. The number
5113 of LITTLENUMS emitted is stored in *sizeP . An error message is
5114 returned, or NULL on OK. */
5117 md_atof (type
, litP
, sizeP
)
5123 LITTLENUM_TYPE words
[4];
5139 return "bad call to md_atof";
5142 t
= atof_ieee (input_line_pointer
, type
, words
);
5144 input_line_pointer
= t
;
5148 if (byte_order
== LITTLE_ENDIAN
)
5150 for (i
= prec
- 1; i
>= 0; i
--)
5152 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5158 for (i
= 0; i
< prec
; i
++)
5160 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5169 md_number_to_chars (buf
, val
, n
)
5177 number_to_chars_littleendian (buf
, val
, n
);
5181 number_to_chars_bigendian (buf
, val
, n
);
5189 CONST
char *md_shortopts
= "O::g::G:";
5191 struct option md_longopts
[] = {
5192 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5193 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5194 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5195 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5196 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5197 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5198 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5199 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5200 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5201 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5202 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5203 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5204 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5205 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5206 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5207 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5208 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5209 {"break", no_argument
, NULL
, OPTION_BREAK
},
5210 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5211 #define OPTION_EB (OPTION_MD_BASE + 11)
5212 {"EB", no_argument
, NULL
, OPTION_EB
},
5213 #define OPTION_EL (OPTION_MD_BASE + 12)
5214 {"EL", no_argument
, NULL
, OPTION_EL
},
5215 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5216 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5217 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5218 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5220 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5221 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5223 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5224 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5225 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5228 {NULL
, no_argument
, NULL
, 0}
5230 size_t md_longopts_size
= sizeof(md_longopts
);
5233 md_parse_option (c
, arg
)
5248 byte_order
= BIG_ENDIAN
;
5249 target_big_endian
= 1;
5253 byte_order
= LITTLE_ENDIAN
;
5254 target_big_endian
= 0;
5258 if (arg
&& arg
[1] == '0')
5265 if (arg
== NULL
|| arg
[1] == '2')
5297 /* Identify the processor type */
5299 if (strcmp (p
, "default") == 0
5300 || strcmp (p
, "DEFAULT") == 0)
5304 if (*p
== 'r' || *p
== 'R')
5311 if (strcmp (p
, "10000") == 0
5312 || strcmp (p
, "10k") == 0
5313 || strcmp (p
, "10K") == 0)
5318 if (strcmp (p
, "2000") == 0
5319 || strcmp (p
, "2k") == 0
5320 || strcmp (p
, "2K") == 0)
5325 if (strcmp (p
, "3000") == 0
5326 || strcmp (p
, "3k") == 0
5327 || strcmp (p
, "3K") == 0)
5332 if (strcmp (p
, "4000") == 0
5333 || strcmp (p
, "4k") == 0
5334 || strcmp (p
, "4K") == 0)
5336 else if (strcmp (p
, "4400") == 0)
5338 else if (strcmp (p
, "4600") == 0)
5340 else if (strcmp (p
, "4650") == 0)
5349 if (strcmp (p
, "6000") == 0
5350 || strcmp (p
, "6k") == 0
5351 || strcmp (p
, "6K") == 0)
5356 if (strcmp (p
, "8000") == 0
5357 || strcmp (p
, "8k") == 0
5358 || strcmp (p
, "8K") == 0)
5363 if (strcmp (p
, "orion") == 0)
5370 as_bad ("invalid architecture -mcpu=%s", arg
);
5381 case OPTION_NO_M4650
:
5385 case OPTION_MEMBEDDED_PIC
:
5386 mips_pic
= EMBEDDED_PIC
;
5387 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
5389 as_bad ("-G may not be used with embedded PIC code");
5392 g_switch_value
= 0x7fffffff;
5395 /* When generating ELF code, we permit -KPIC and -call_shared to
5396 select SVR4_PIC, and -non_shared to select no PIC. This is
5397 intended to be compatible with Irix 5. */
5398 case OPTION_CALL_SHARED
:
5399 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
5401 as_bad ("-call_shared is supported only for ELF format");
5404 mips_pic
= SVR4_PIC
;
5405 if (g_switch_seen
&& g_switch_value
!= 0)
5407 as_bad ("-G may not be used with SVR4 PIC code");
5413 case OPTION_NON_SHARED
:
5414 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
5416 as_bad ("-non_shared is supported only for ELF format");
5423 if (! USE_GLOBAL_POINTER_OPT
)
5425 as_bad ("-G is not supported for this configuration");
5428 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5430 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5434 g_switch_value
= atoi (arg
);
5446 md_show_usage (stream
)
5451 -membedded-pic generate embedded position independent code\n\
5452 -EB generate big endian output\n\
5453 -EL generate little endian output\n\
5454 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5455 -G NUM allow referencing objects up to NUM bytes\n\
5456 implicitly with the gp register [default 8]\n");
5458 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5459 -mips2, -mcpu=r6000 generate code for r6000\n\
5460 -mips3, -mcpu=r4000 generate code for r4000\n\
5461 -mips4, -mcpu=r8000 generate code for r8000\n\
5462 -m4650 permit -m4650 instructions\n\
5463 -no-m4650 do not permit -m4650 instructions\n\
5464 -O0 remove unneeded NOPs, do not swap branches\n\
5465 -O remove unneeded NOPs and swap branches\n\
5466 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5467 --break, --no-trap break exception on div by 0 and mult overflow\n");
5470 -KPIC, -call_shared generate SVR4 position independent code\n\
5471 -non_shared do not generate position independent code\n");
5476 md_pcrel_from (fixP
)
5479 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
5480 && fixP
->fx_addsy
!= (symbolS
*) NULL
5481 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5483 /* This makes a branch to an undefined symbol be a branch to the
5484 current location. */
5488 /* return the address of the delay slot */
5489 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5492 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5493 reloc for a cons. We could use the definition there, except that
5494 we want to handle 64 bit relocs specially. */
5497 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5500 unsigned int nbytes
;
5503 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5505 FIXME: There is no way to select anything but 32 bit mode right
5509 if (byte_order
== BIG_ENDIAN
)
5514 if (nbytes
!= 2 && nbytes
!= 4)
5515 as_bad ("Unsupported reloc size %d", nbytes
);
5517 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5518 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5521 /* When generating embedded PIC code we need to use a special
5522 relocation to represent the difference of two symbols in the .text
5523 section (switch tables use a difference of this sort). See
5524 include/coff/mips.h for details. This macro checks whether this
5525 fixup requires the special reloc. */
5526 #define SWITCH_TABLE(fixp) \
5527 ((fixp)->fx_r_type == BFD_RELOC_32 \
5528 && (fixp)->fx_addsy != NULL \
5529 && (fixp)->fx_subsy != NULL \
5530 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5531 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5533 /* When generating embedded PIC code we must keep all PC relative
5534 relocations, in case the linker has to relax a call. We also need
5535 to keep relocations for switch table entries. */
5539 mips_force_relocation (fixp
)
5542 return (mips_pic
== EMBEDDED_PIC
5544 || SWITCH_TABLE (fixp
)
5545 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5546 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5549 /* Apply a fixup to the object file. */
5552 md_apply_fix (fixP
, valueP
)
5559 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
5562 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5564 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5567 switch (fixP
->fx_r_type
)
5569 case BFD_RELOC_MIPS_JMP
:
5570 case BFD_RELOC_HI16
:
5571 case BFD_RELOC_HI16_S
:
5572 case BFD_RELOC_MIPS_GPREL
:
5573 case BFD_RELOC_MIPS_LITERAL
:
5574 case BFD_RELOC_MIPS_CALL16
:
5575 case BFD_RELOC_MIPS_GOT16
:
5576 case BFD_RELOC_MIPS_GPREL32
:
5578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5579 "Invalid PC relative reloc");
5580 /* Nothing needed to do. The value comes from the reloc entry */
5583 case BFD_RELOC_PCREL_HI16_S
:
5584 /* The addend for this is tricky if it is internal, so we just
5585 do everything here rather than in bfd_perform_relocation. */
5586 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5588 /* For an external symbol adjust by the address to make it
5589 pcrel_offset. We use the address of the RELLO reloc
5590 which follows this one. */
5591 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5592 + fixP
->fx_next
->fx_where
);
5597 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5598 if (byte_order
== BIG_ENDIAN
)
5600 md_number_to_chars (buf
, value
, 2);
5603 case BFD_RELOC_PCREL_LO16
:
5604 /* The addend for this is tricky if it is internal, so we just
5605 do everything here rather than in bfd_perform_relocation. */
5606 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5607 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5608 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5609 if (byte_order
== BIG_ENDIAN
)
5611 md_number_to_chars (buf
, value
, 2);
5615 /* If we are deleting this reloc entry, we must fill in the
5616 value now. This can happen if we have a .word which is not
5617 resolved when it appears but is later defined. We also need
5618 to fill in the value if this is an embedded PIC switch table
5621 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5622 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5627 /* If we are deleting this reloc entry, we must fill in the
5629 assert (fixP
->fx_size
== 2);
5631 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5635 case BFD_RELOC_LO16
:
5636 /* When handling an embedded PIC switch statement, we can wind
5637 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5640 if (value
< -0x8000 || value
> 0x7fff)
5641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5642 "relocation overflow");
5643 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5644 if (byte_order
== BIG_ENDIAN
)
5646 md_number_to_chars (buf
, value
, 2);
5650 case BFD_RELOC_16_PCREL_S2
:
5652 * We need to save the bits in the instruction since fixup_segment()
5653 * might be deleting the relocation entry (i.e., a branch within
5654 * the current segment).
5657 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
5658 "Branch to odd address (%lx)", value
);
5661 /* update old instruction data */
5662 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5666 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5670 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5678 if (value
>= -0x8000 && value
< 0x8000)
5679 insn
|= value
& 0xffff;
5682 /* The branch offset is too large. If this is an
5683 unconditional branch, and we are not generating PIC code,
5684 we can convert it to an absolute jump instruction. */
5685 if (mips_pic
== NO_PIC
5687 && fixP
->fx_frag
->fr_address
>= text_section
->vma
5688 && (fixP
->fx_frag
->fr_address
5689 < text_section
->vma
+ text_section
->_raw_size
)
5690 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
5691 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
5692 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
5694 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
5695 insn
= 0x0c000000; /* jal */
5697 insn
= 0x08000000; /* j */
5698 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
5700 fixP
->fx_addsy
= section_symbol (text_section
);
5701 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
5705 /* FIXME. It would be possible in principle to handle
5706 conditional branches which overflow. They could be
5707 transformed into a branch around a jump. This would
5708 require setting up variant frags for each different
5709 branch type. The native MIPS assembler attempts to
5710 handle these cases, but it appears to do it
5712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5713 "Relocation overflow");
5717 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5732 const struct mips_opcode
*p
;
5733 int treg
, sreg
, dreg
, shamt
;
5738 for (i
= 0; i
< NUMOPCODES
; ++i
)
5740 p
= &mips_opcodes
[i
];
5741 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5743 printf ("%08lx %s\t", oc
, p
->name
);
5744 treg
= (oc
>> 16) & 0x1f;
5745 sreg
= (oc
>> 21) & 0x1f;
5746 dreg
= (oc
>> 11) & 0x1f;
5747 shamt
= (oc
>> 6) & 0x1f;
5749 for (args
= p
->args
;; ++args
)
5760 printf ("%c", *args
);
5764 assert (treg
== sreg
);
5765 printf ("$%d,$%d", treg
, sreg
);
5770 printf ("$%d", dreg
);
5775 printf ("$%d", treg
);
5779 printf ("0x%x", treg
);
5784 printf ("$%d", sreg
);
5788 printf ("0x%08lx", oc
& 0x1ffffff);
5800 printf ("$%d", shamt
);
5811 printf ("%08lx UNDEFINED\n", oc
);
5822 name
= input_line_pointer
;
5823 c
= get_symbol_end ();
5824 p
= (symbolS
*) symbol_find_or_make (name
);
5825 *input_line_pointer
= c
;
5829 /* Align the current frag to a given power of two. The MIPS assembler
5830 also automatically adjusts any preceding label. */
5833 mips_align (to
, fill
, label
)
5838 mips_emit_delays ();
5839 frag_align (to
, fill
);
5840 record_alignment (now_seg
, to
);
5843 assert (S_GET_SEGMENT (label
) == now_seg
);
5844 label
->sy_frag
= frag_now
;
5845 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5849 /* Align to a given power of two. .align 0 turns off the automatic
5850 alignment used by the data creating pseudo-ops. */
5857 register long temp_fill
;
5858 long max_alignment
= 15;
5862 o Note that the assembler pulls down any immediately preceeding label
5863 to the aligned address.
5864 o It's not documented but auto alignment is reinstated by
5865 a .align pseudo instruction.
5866 o Note also that after auto alignment is turned off the mips assembler
5867 issues an error on attempt to assemble an improperly aligned data item.
5872 temp
= get_absolute_expression ();
5873 if (temp
> max_alignment
)
5874 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5877 as_warn ("Alignment negative: 0 assumed.");
5880 if (*input_line_pointer
== ',')
5882 input_line_pointer
++;
5883 temp_fill
= get_absolute_expression ();
5890 mips_align (temp
, (int) temp_fill
, insn_label
);
5897 demand_empty_rest_of_line ();
5900 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5901 that there was a previous instruction. */
5904 s_stringer (append_zero
)
5907 mips_emit_delays ();
5909 stringer (append_zero
);
5918 /* When generating embedded PIC code, we only use the .text, .lit8,
5919 .sdata and .sbss sections. We change the .data and .rdata
5920 pseudo-ops to use .sdata. */
5921 if (mips_pic
== EMBEDDED_PIC
5922 && (sec
== 'd' || sec
== 'r'))
5925 mips_emit_delays ();
5935 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5936 demand_empty_rest_of_line ();
5940 if (USE_GLOBAL_POINTER_OPT
)
5942 seg
= subseg_new (RDATA_SECTION_NAME
,
5943 (subsegT
) get_absolute_expression ());
5944 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5946 bfd_set_section_flags (stdoutput
, seg
,
5952 bfd_set_section_alignment (stdoutput
, seg
, 4);
5954 demand_empty_rest_of_line ();
5958 as_bad ("No read only data section in this object file format");
5959 demand_empty_rest_of_line ();
5965 if (USE_GLOBAL_POINTER_OPT
)
5967 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5968 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5970 bfd_set_section_flags (stdoutput
, seg
,
5971 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
5973 bfd_set_section_alignment (stdoutput
, seg
, 4);
5975 demand_empty_rest_of_line ();
5980 as_bad ("Global pointers not supported; recompile -G 0");
5981 demand_empty_rest_of_line ();
5991 /* Handle the ELF .section pseudo-op. This is a wrapper around
5998 mips_emit_delays ();
5999 obj_elf_section (x
);
6003 #endif /* OBJ_ELF */
6012 mips_emit_delays ();
6013 if (log_size
> 0 && auto_align
)
6014 mips_align (log_size
, 0, label
);
6016 cons (1 << log_size
);
6023 as_fatal ("Encountered `.err', aborting assembly");
6033 symbolP
= get_symbol ();
6034 if (*input_line_pointer
== ',')
6035 input_line_pointer
++;
6036 size
= get_absolute_expression ();
6037 S_SET_EXTERNAL (symbolP
);
6039 #ifdef ECOFF_DEBUGGING
6040 symbolP
->ecoff_extern_size
= size
;
6052 mips_emit_delays ();
6056 mips_align (3, 0, label
);
6058 mips_align (2, 0, label
);
6065 /* Handle .globl. We need to override it because on Irix 5 you are
6068 where foo is an undefined symbol, to mean that foo should be
6069 considered to be the address of a function. */
6079 name
= input_line_pointer
;
6080 c
= get_symbol_end ();
6081 symbolP
= symbol_find_or_make (name
);
6082 *input_line_pointer
= c
;
6084 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6089 secname
= input_line_pointer
;
6090 c
= get_symbol_end ();
6091 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6093 as_bad ("%s: no such section", secname
);
6094 *input_line_pointer
= c
;
6096 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6097 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
6100 S_SET_EXTERNAL (symbolP
);
6101 demand_empty_rest_of_line ();
6111 opt
= input_line_pointer
;
6112 c
= get_symbol_end ();
6116 /* FIXME: What does this mean? */
6118 else if (strncmp (opt
, "pic", 3) == 0)
6126 mips_pic
= SVR4_PIC
;
6128 as_bad (".option pic%d not supported", i
);
6130 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6132 if (g_switch_seen
&& g_switch_value
!= 0)
6133 as_warn ("-G may not be used with SVR4 PIC code");
6135 bfd_set_gp_size (stdoutput
, 0);
6139 as_warn ("Unrecognized option \"%s\"", opt
);
6141 *input_line_pointer
= c
;
6142 demand_empty_rest_of_line ();
6149 char *name
= input_line_pointer
, ch
;
6151 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6152 input_line_pointer
++;
6153 ch
= *input_line_pointer
;
6154 *input_line_pointer
= '\0';
6156 if (strcmp (name
, "reorder") == 0)
6160 prev_insn_unreordered
= 1;
6161 prev_prev_insn_unreordered
= 1;
6165 else if (strcmp (name
, "noreorder") == 0)
6167 mips_emit_delays ();
6169 mips_any_noreorder
= 1;
6171 else if (strcmp (name
, "at") == 0)
6175 else if (strcmp (name
, "noat") == 0)
6179 else if (strcmp (name
, "macro") == 0)
6181 mips_warn_about_macros
= 0;
6183 else if (strcmp (name
, "nomacro") == 0)
6185 if (mips_noreorder
== 0)
6186 as_bad ("`noreorder' must be set before `nomacro'");
6187 mips_warn_about_macros
= 1;
6189 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6193 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6197 else if (strcmp (name
, "bopt") == 0)
6201 else if (strcmp (name
, "nobopt") == 0)
6205 else if (strncmp (name
, "mips", 4) == 0)
6209 /* Permit the user to change the ISA on the fly. Needless to
6210 say, misuse can cause serious problems. */
6211 isa
= atoi (name
+ 4);
6213 mips_isa
= file_mips_isa
;
6214 else if (isa
< 1 || isa
> 4)
6215 as_bad ("unknown ISA level");
6221 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6223 *input_line_pointer
= ch
;
6224 demand_empty_rest_of_line ();
6227 /* The same as the usual .space directive, except that we have to
6228 forget about any previous instruction. */
6231 s_mips_space (param
)
6234 mips_emit_delays ();
6239 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6240 .option pic2. It means to generate SVR4 PIC calls. */
6246 mips_pic
= SVR4_PIC
;
6247 if (USE_GLOBAL_POINTER_OPT
)
6249 if (g_switch_seen
&& g_switch_value
!= 0)
6250 as_warn ("-G may not be used with SVR4 PIC code");
6253 bfd_set_gp_size (stdoutput
, 0);
6254 demand_empty_rest_of_line ();
6257 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6258 PIC code. It sets the $gp register for the function based on the
6259 function address, which is in the register named in the argument.
6260 This uses a relocation against _gp_disp, which is handled specially
6261 by the linker. The result is:
6262 lui $gp,%hi(_gp_disp)
6263 addiu $gp,$gp,%lo(_gp_disp)
6264 addu $gp,$gp,.cpload argument
6265 The .cpload argument is normally $25 == $t9. */
6274 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6275 if (mips_pic
!= SVR4_PIC
)
6281 /* .cpload should be a in .set noreorder section. */
6282 if (mips_noreorder
== 0)
6283 as_warn (".cpload not in noreorder section");
6286 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6287 ex
.X_op_symbol
= NULL
;
6288 ex
.X_add_number
= 0;
6290 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6291 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6292 (int) BFD_RELOC_LO16
);
6294 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6295 GP
, GP
, tc_get_register (0));
6297 demand_empty_rest_of_line ();
6300 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6301 offset from $sp. The offset is remembered, and after making a PIC
6302 call $gp is restored from that location. */
6305 s_cprestore (ignore
)
6311 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6312 if (mips_pic
!= SVR4_PIC
)
6318 mips_cprestore_offset
= get_absolute_expression ();
6320 ex
.X_op
= O_constant
;
6321 ex
.X_add_symbol
= NULL
;
6322 ex
.X_op_symbol
= NULL
;
6323 ex
.X_add_number
= mips_cprestore_offset
;
6325 macro_build ((char *) NULL
, &icnt
, &ex
,
6326 mips_isa
< 3 ? "sw" : "sd",
6327 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6329 demand_empty_rest_of_line ();
6332 /* Handle the .gpword pseudo-op. This is used when generating PIC
6333 code. It generates a 32 bit GP relative reloc. */
6343 /* When not generating PIC code, this is treated as .word. */
6344 if (mips_pic
!= SVR4_PIC
)
6351 mips_emit_delays ();
6353 mips_align (2, 0, label
);
6358 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6360 as_bad ("Unsupported use of .gpword");
6361 ignore_rest_of_line ();
6365 md_number_to_chars (p
, (valueT
) 0, 4);
6366 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6367 BFD_RELOC_MIPS_GPREL32
);
6369 demand_empty_rest_of_line ();
6372 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6373 tables in SVR4 PIC code. */
6382 /* This is ignored when not generating SVR4 PIC code. */
6383 if (mips_pic
!= SVR4_PIC
)
6389 /* Add $gp to the register named as an argument. */
6390 reg
= tc_get_register (0);
6391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6392 mips_isa
< 3 ? "addu" : "daddu",
6393 "d,v,t", reg
, reg
, GP
);
6395 demand_empty_rest_of_line ();
6398 /* Parse a register string into a number. Called from the ECOFF code
6399 to parse .frame. The argument is non-zero if this is the frame
6400 register, so that we can record it in mips_frame_reg. */
6403 tc_get_register (frame
)
6409 if (*input_line_pointer
++ != '$')
6411 as_warn ("expected `$'");
6414 else if (isdigit ((unsigned char) *input_line_pointer
))
6416 reg
= get_absolute_expression ();
6417 if (reg
< 0 || reg
>= 32)
6419 as_warn ("Bad register number");
6425 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6427 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6429 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6431 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6435 as_warn ("Unrecognized register name");
6438 input_line_pointer
+= 2;
6441 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6446 md_section_align (seg
, addr
)
6450 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6452 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6455 /* Estimate the size of a frag before relaxing. We are not really
6456 relaxing here, and the final size is encoded in the subtype
6459 /* Utility routine, called from above as well. If called while the
6460 input file is still being read, it's only an approximation. (For
6461 example, a symbol may later become defined which appeared to be
6462 undefined earlier.) */
6463 static int nopic_need_relax (sym
)
6469 if (USE_GLOBAL_POINTER_OPT
)
6471 const char *symname
;
6474 /* Find out whether this symbol can be referenced off the GP
6475 register. It can be if it is smaller than the -G size or if
6476 it is in the .sdata or .sbss section. Certain symbols can
6477 not be referenced off the GP, although it appears as though
6479 symname
= S_GET_NAME (sym
);
6480 if (symname
!= (const char *) NULL
6481 && (strcmp (symname
, "eprol") == 0
6482 || strcmp (symname
, "etext") == 0
6483 || strcmp (symname
, "_gp") == 0
6484 || strcmp (symname
, "edata") == 0
6485 || strcmp (symname
, "_fbss") == 0
6486 || strcmp (symname
, "_fdata") == 0
6487 || strcmp (symname
, "_ftext") == 0
6488 || strcmp (symname
, "end") == 0
6489 || strcmp (symname
, "_gp_disp") == 0))
6491 else if (! S_IS_DEFINED (sym
)
6492 && ((sym
->ecoff_extern_size
!= 0
6493 && sym
->ecoff_extern_size
<= g_switch_value
)
6494 || (S_GET_VALUE (sym
) != 0
6495 && S_GET_VALUE (sym
) <= g_switch_value
)))
6499 const char *segname
;
6501 segname
= segment_name (S_GET_SEGMENT (sym
));
6502 assert (strcmp (segname
, ".lit8") != 0
6503 && strcmp (segname
, ".lit4") != 0);
6504 change
= (strcmp (segname
, ".sdata") != 0
6505 && strcmp (segname
, ".sbss") != 0);
6510 /* We are not optimizing for the GP register. */
6516 md_estimate_size_before_relax (fragp
, segtype
)
6522 if (mips_pic
== NO_PIC
)
6524 change
= nopic_need_relax (fragp
->fr_symbol
);
6526 else if (mips_pic
== SVR4_PIC
)
6528 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6530 /* This must duplicate the test in adjust_reloc_syms. */
6531 change
= (symsec
!= &bfd_und_section
6532 && symsec
!= &bfd_abs_section
6533 && ! bfd_is_com_section (symsec
));
6540 /* Record the offset to the first reloc in the fr_opcode field.
6541 This lets md_convert_frag and tc_gen_reloc know that the code
6542 must be expanded. */
6543 fragp
->fr_opcode
= (fragp
->fr_literal
6545 - RELAX_OLD (fragp
->fr_subtype
)
6546 + RELAX_RELOC1 (fragp
->fr_subtype
));
6547 /* FIXME: This really needs as_warn_where. */
6548 if (RELAX_WARN (fragp
->fr_subtype
))
6549 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6555 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6558 /* Translate internal representation of relocation info to BFD target
6562 tc_gen_reloc (section
, fixp
)
6566 static arelent
*retval
[4];
6569 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6572 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6573 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6575 if (mips_pic
== EMBEDDED_PIC
6576 && SWITCH_TABLE (fixp
))
6578 /* For a switch table entry we use a special reloc. The addend
6579 is actually the difference between the reloc address and the
6581 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6582 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
6583 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6584 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6586 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6588 /* We use a special addend for an internal RELLO reloc. */
6589 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6590 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6592 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6594 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6596 assert (fixp
->fx_next
!= NULL
6597 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6598 /* We use a special addend for an internal RELHI reloc. The
6599 reloc is relative to the RELLO; adjust the addend
6601 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6602 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6603 + fixp
->fx_next
->fx_where
6604 - S_GET_VALUE (fixp
->fx_subsy
));
6606 reloc
->addend
= (fixp
->fx_addnumber
6607 + fixp
->fx_next
->fx_frag
->fr_address
6608 + fixp
->fx_next
->fx_where
);
6610 else if (fixp
->fx_pcrel
== 0)
6611 reloc
->addend
= fixp
->fx_addnumber
;
6614 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
6615 /* A gruesome hack which is a result of the gruesome gas reloc
6617 reloc
->addend
= reloc
->address
;
6619 reloc
->addend
= -reloc
->address
;
6622 /* If this is a variant frag, we may need to adjust the existing
6623 reloc and generate a new one. */
6624 if (fixp
->fx_frag
->fr_opcode
!= NULL
6625 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6626 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6627 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6631 /* If this is not the last reloc in this frag, then we have two
6632 GPREL relocs, both of which are being replaced. Let the
6633 second one handle all of them. */
6634 if (fixp
->fx_next
!= NULL
6635 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6637 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6638 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6643 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6644 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6645 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6647 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6648 reloc2
->address
= (reloc
->address
6649 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6650 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6651 reloc2
->addend
= fixp
->fx_addnumber
;
6652 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6653 assert (reloc2
->howto
!= NULL
);
6655 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6659 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6662 reloc3
->address
+= 4;
6665 if (mips_pic
== NO_PIC
)
6667 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6668 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6670 else if (mips_pic
== SVR4_PIC
)
6672 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6674 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6675 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6682 /* To support a PC relative reloc when generating embedded PIC code
6683 for ECOFF, we use a Cygnus extension. We check for that here to
6684 make sure that we don't let such a reloc escape normally. */
6685 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
6686 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6687 && mips_pic
!= EMBEDDED_PIC
)
6688 reloc
->howto
= NULL
;
6690 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6692 if (reloc
->howto
== NULL
)
6694 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6695 "Can not represent relocation in this object file format");
6702 /* Convert a machine dependent frag. */
6705 md_convert_frag (abfd
, asec
, fragp
)
6713 if (fragp
->fr_opcode
== NULL
)
6716 old
= RELAX_OLD (fragp
->fr_subtype
);
6717 new = RELAX_NEW (fragp
->fr_subtype
);
6718 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6721 memcpy (fixptr
- old
, fixptr
, new);
6723 fragp
->fr_fix
+= new - old
;
6726 /* This function is called whenever a label is defined. It is used
6727 when handling branch delays; if a branch has a label, we assume we
6731 mips_define_label (sym
)
6739 /* Some special processing for a MIPS ELF file. */
6742 mips_elf_final_processing ()
6746 /* Write out the .reginfo section. */
6747 s
.ri_gprmask
= mips_gprmask
;
6748 s
.ri_cprmask
[0] = mips_cprmask
[0];
6749 s
.ri_cprmask
[1] = mips_cprmask
[1];
6750 s
.ri_cprmask
[2] = mips_cprmask
[2];
6751 s
.ri_cprmask
[3] = mips_cprmask
[3];
6752 /* The gp_value field is set by the MIPS ELF backend. */
6754 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6755 ((Elf32_External_RegInfo
*)
6756 mips_regmask_frag
));
6758 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6759 sort of BFD interface for this. */
6760 if (mips_any_noreorder
)
6761 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6762 if (mips_pic
!= NO_PIC
)
6763 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6766 #endif /* OBJ_ELF */
6768 #ifndef ECOFF_DEBUGGING
6770 /* These functions should really be defined by the object file format,
6771 since they are related to debugging information. However, this
6772 code has to work for the a.out format, which does not define them,
6773 so we provide simple versions here. These don't actually generate
6774 any debugging information, but they do simple checking and someday
6775 somebody may make them useful. */
6779 struct loc
*loc_next
;
6780 unsigned long loc_fileno
;
6781 unsigned long loc_lineno
;
6782 unsigned long loc_offset
;
6783 unsigned short loc_delta
;
6784 unsigned short loc_count
;
6793 struct proc
*proc_next
;
6794 struct symbol
*proc_isym
;
6795 struct symbol
*proc_end
;
6796 unsigned long proc_reg_mask
;
6797 unsigned long proc_reg_offset
;
6798 unsigned long proc_fpreg_mask
;
6799 unsigned long proc_fpreg_offset
;
6800 unsigned long proc_frameoffset
;
6801 unsigned long proc_framereg
;
6802 unsigned long proc_pcreg
;
6804 struct file
*proc_file
;
6811 struct file
*file_next
;
6812 unsigned long file_fileno
;
6813 struct symbol
*file_symbol
;
6814 struct symbol
*file_end
;
6815 struct proc
*file_proc
;
6820 static struct obstack proc_frags
;
6821 static procS
*proc_lastP
;
6822 static procS
*proc_rootP
;
6823 static int numprocs
;
6828 obstack_begin (&proc_frags
, 0x2000);
6834 /* check for premature end, nesting errors, etc */
6835 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6836 as_warn ("missing `.end' at end of assembly");
6845 if (*input_line_pointer
== '-')
6847 ++input_line_pointer
;
6850 if (!isdigit (*input_line_pointer
))
6851 as_bad ("Expected simple number.");
6852 if (input_line_pointer
[0] == '0')
6854 if (input_line_pointer
[1] == 'x')
6856 input_line_pointer
+= 2;
6857 while (isxdigit (*input_line_pointer
))
6860 val
|= hex_value (*input_line_pointer
++);
6862 return negative
? -val
: val
;
6866 ++input_line_pointer
;
6867 while (isdigit (*input_line_pointer
))
6870 val
|= *input_line_pointer
++ - '0';
6872 return negative
? -val
: val
;
6875 if (!isdigit (*input_line_pointer
))
6877 printf (" *input_line_pointer == '%c' 0x%02x\n",
6878 *input_line_pointer
, *input_line_pointer
);
6879 as_warn ("Invalid number");
6882 while (isdigit (*input_line_pointer
))
6885 val
+= *input_line_pointer
++ - '0';
6887 return negative
? -val
: val
;
6890 /* The .file directive; just like the usual .file directive, but there
6891 is an initial number which is the ECOFF file index. */
6899 line
= get_number ();
6904 /* The .end directive. */
6912 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6915 demand_empty_rest_of_line ();
6919 if (now_seg
!= text_section
)
6920 as_warn (".end not in text section");
6923 as_warn (".end and no .ent seen yet.");
6929 assert (S_GET_NAME (p
));
6930 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6931 as_warn (".end symbol does not match .ent symbol.");
6934 proc_lastP
->proc_end
= (symbolS
*) 1;
6937 /* The .aent and .ent directives. */
6947 symbolP
= get_symbol ();
6948 if (*input_line_pointer
== ',')
6949 input_line_pointer
++;
6951 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6952 number
= get_number ();
6953 if (now_seg
!= text_section
)
6954 as_warn (".ent or .aent not in text section.");
6956 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6957 as_warn ("missing `.end'");
6961 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6962 procP
->proc_isym
= symbolP
;
6963 procP
->proc_reg_mask
= 0;
6964 procP
->proc_reg_offset
= 0;
6965 procP
->proc_fpreg_mask
= 0;
6966 procP
->proc_fpreg_offset
= 0;
6967 procP
->proc_frameoffset
= 0;
6968 procP
->proc_framereg
= 0;
6969 procP
->proc_pcreg
= 0;
6970 procP
->proc_end
= NULL
;
6971 procP
->proc_next
= NULL
;
6973 proc_lastP
->proc_next
= procP
;
6979 demand_empty_rest_of_line ();
6982 /* The .frame directive. */
6995 frame_reg
= tc_get_register (1);
6996 if (*input_line_pointer
== ',')
6997 input_line_pointer
++;
6998 frame_off
= get_absolute_expression ();
6999 if (*input_line_pointer
== ',')
7000 input_line_pointer
++;
7001 pcreg
= tc_get_register (0);
7004 assert (proc_rootP
);
7005 proc_rootP
->proc_framereg
= frame_reg
;
7006 proc_rootP
->proc_frameoffset
= frame_off
;
7007 proc_rootP
->proc_pcreg
= pcreg
;
7008 /* bob macho .frame */
7010 /* We don't have to write out a frame stab for unoptimized code. */
7011 if (!(frame_reg
== FP
&& frame_off
== 0))
7014 as_warn ("No .ent for .frame to use.");
7015 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7016 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7017 S_SET_TYPE (symP
, N_RMASK
);
7018 S_SET_OTHER (symP
, 0);
7019 S_SET_DESC (symP
, 0);
7020 symP
->sy_forward
= proc_lastP
->proc_isym
;
7021 /* bob perhaps I should have used pseudo set */
7023 demand_empty_rest_of_line ();
7027 /* The .fmask and .mask directives. */
7034 char str
[100], *strP
;
7040 mask
= get_number ();
7041 if (*input_line_pointer
== ',')
7042 input_line_pointer
++;
7043 off
= get_absolute_expression ();
7045 /* bob only for coff */
7046 assert (proc_rootP
);
7047 if (reg_type
== 'F')
7049 proc_rootP
->proc_fpreg_mask
= mask
;
7050 proc_rootP
->proc_fpreg_offset
= off
;
7054 proc_rootP
->proc_reg_mask
= mask
;
7055 proc_rootP
->proc_reg_offset
= off
;
7058 /* bob macho .mask + .fmask */
7060 /* We don't have to write out a mask stab if no saved regs. */
7064 as_warn ("No .ent for .mask to use.");
7066 for (i
= 0; i
< 32; i
++)
7070 sprintf (strP
, "%c%d,", reg_type
, i
);
7071 strP
+= strlen (strP
);
7075 sprintf (strP
, ";%d,", off
);
7076 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7077 S_SET_TYPE (symP
, N_RMASK
);
7078 S_SET_OTHER (symP
, 0);
7079 S_SET_DESC (symP
, 0);
7080 symP
->sy_forward
= proc_lastP
->proc_isym
;
7081 /* bob perhaps I should have used pseudo set */
7086 /* The .loc directive. */
7097 assert (now_seg
== text_section
);
7099 lineno
= get_number ();
7100 addroff
= frag_now_fix ();
7102 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7103 S_SET_TYPE (symbolP
, N_SLINE
);
7104 S_SET_OTHER (symbolP
, 0);
7105 S_SET_DESC (symbolP
, lineno
);
7106 symbolP
->sy_segment
= now_seg
;
7110 #endif /* ! defined (ECOFF_DEBUGGING) */