1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS32R3 \
312 || mips_opts.isa == ISA_MIPS32R5 \
313 || mips_opts.isa == ISA_MIPS64 \
314 || mips_opts.isa == ISA_MIPS64R2 \
315 || mips_opts.isa == ISA_MIPS64R3 \
316 || mips_opts.isa == ISA_MIPS64R5)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips
;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* The argument of the -march= flag. The architecture we are assembling. */
334 static int file_mips_arch
= CPU_UNKNOWN
;
335 static const char *mips_arch_string
;
337 /* The argument of the -mtune= flag. The architecture for which we
339 static int mips_tune
= CPU_UNKNOWN
;
340 static const char *mips_tune_string
;
342 /* True when generating 32-bit code for a 64-bit processor. */
343 static int mips_32bitmode
= 0;
345 /* True if the given ABI requires 32-bit registers. */
346 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
348 /* Likewise 64-bit registers. */
349 #define ABI_NEEDS_64BIT_REGS(ABI) \
351 || (ABI) == N64_ABI \
354 /* Return true if ISA supports 64 bit wide gp registers. */
355 #define ISA_HAS_64BIT_REGS(ISA) \
356 ((ISA) == ISA_MIPS3 \
357 || (ISA) == ISA_MIPS4 \
358 || (ISA) == ISA_MIPS5 \
359 || (ISA) == ISA_MIPS64 \
360 || (ISA) == ISA_MIPS64R2 \
361 || (ISA) == ISA_MIPS64R3 \
362 || (ISA) == ISA_MIPS64R5)
364 /* Return true if ISA supports 64 bit wide float registers. */
365 #define ISA_HAS_64BIT_FPRS(ISA) \
366 ((ISA) == ISA_MIPS3 \
367 || (ISA) == ISA_MIPS4 \
368 || (ISA) == ISA_MIPS5 \
369 || (ISA) == ISA_MIPS32R2 \
370 || (ISA) == ISA_MIPS32R3 \
371 || (ISA) == ISA_MIPS32R5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2 \
374 || (ISA) == ISA_MIPS64R3 \
375 || (ISA) == ISA_MIPS64R5 )
377 /* Return true if ISA supports 64-bit right rotate (dror et al.)
379 #define ISA_HAS_DROR(ISA) \
380 ((ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (mips_opts.micromips \
384 && ISA_HAS_64BIT_REGS (ISA)) \
387 /* Return true if ISA supports 32-bit right rotate (ror et al.)
389 #define ISA_HAS_ROR(ISA) \
390 ((ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS64R2 \
394 || (ISA) == ISA_MIPS64R3 \
395 || (ISA) == ISA_MIPS64R5 \
396 || (mips_opts.ase & ASE_SMARTMIPS) \
397 || mips_opts.micromips \
400 /* Return true if ISA supports single-precision floats in odd registers. */
401 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
402 ((ISA) == ISA_MIPS32 \
403 || (ISA) == ISA_MIPS32R2 \
404 || (ISA) == ISA_MIPS32R3 \
405 || (ISA) == ISA_MIPS32R5 \
406 || (ISA) == ISA_MIPS64 \
407 || (ISA) == ISA_MIPS64R2 \
408 || (ISA) == ISA_MIPS64R3 \
409 || (ISA) == ISA_MIPS64R5)
411 /* Return true if ISA supports move to/from high part of a 64-bit
412 floating-point register. */
413 #define ISA_HAS_MXHC1(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS64R2 \
418 || (ISA) == ISA_MIPS64R3 \
419 || (ISA) == ISA_MIPS64R5)
421 #define HAVE_32BIT_GPRS \
422 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
424 #define HAVE_32BIT_FPRS \
425 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
427 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
428 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
430 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
432 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
434 /* True if relocations are stored in-place. */
435 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
437 /* The ABI-derived address size. */
438 #define HAVE_64BIT_ADDRESSES \
439 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
440 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
442 /* The size of symbolic constants (i.e., expressions of the form
443 "SYMBOL" or "SYMBOL + OFFSET"). */
444 #define HAVE_32BIT_SYMBOLS \
445 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
446 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
448 /* Addresses are loaded in different ways, depending on the address size
449 in use. The n32 ABI Documentation also mandates the use of additions
450 with overflow checking, but existing implementations don't follow it. */
451 #define ADDRESS_ADD_INSN \
452 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
454 #define ADDRESS_ADDI_INSN \
455 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
457 #define ADDRESS_LOAD_INSN \
458 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
460 #define ADDRESS_STORE_INSN \
461 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
463 /* Return true if the given CPU supports the MIPS16 ASE. */
464 #define CPU_HAS_MIPS16(cpu) \
465 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
466 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
468 /* Return true if the given CPU supports the microMIPS ASE. */
469 #define CPU_HAS_MICROMIPS(cpu) 0
471 /* True if CPU has a dror instruction. */
472 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
474 /* True if CPU has a ror instruction. */
475 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
477 /* True if CPU is in the Octeon family */
478 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
480 /* True if CPU has seq/sne and seqi/snei instructions. */
481 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
483 /* True, if CPU has support for ldc1 and sdc1. */
484 #define CPU_HAS_LDC1_SDC1(CPU) \
485 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
487 /* True if mflo and mfhi can be immediately followed by instructions
488 which write to the HI and LO registers.
490 According to MIPS specifications, MIPS ISAs I, II, and III need
491 (at least) two instructions between the reads of HI/LO and
492 instructions which write them, and later ISAs do not. Contradicting
493 the MIPS specifications, some MIPS IV processor user manuals (e.g.
494 the UM for the NEC Vr5000) document needing the instructions between
495 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
496 MIPS64 and later ISAs to have the interlocks, plus any specific
497 earlier-ISA CPUs for which CPU documentation declares that the
498 instructions are really interlocked. */
499 #define hilo_interlocks \
500 (mips_opts.isa == ISA_MIPS32 \
501 || mips_opts.isa == ISA_MIPS32R2 \
502 || mips_opts.isa == ISA_MIPS32R3 \
503 || mips_opts.isa == ISA_MIPS32R5 \
504 || mips_opts.isa == ISA_MIPS64 \
505 || mips_opts.isa == ISA_MIPS64R2 \
506 || mips_opts.isa == ISA_MIPS64R3 \
507 || mips_opts.isa == ISA_MIPS64R5 \
508 || mips_opts.arch == CPU_R4010 \
509 || mips_opts.arch == CPU_R5900 \
510 || mips_opts.arch == CPU_R10000 \
511 || mips_opts.arch == CPU_R12000 \
512 || mips_opts.arch == CPU_R14000 \
513 || mips_opts.arch == CPU_R16000 \
514 || mips_opts.arch == CPU_RM7000 \
515 || mips_opts.arch == CPU_VR5500 \
516 || mips_opts.micromips \
519 /* Whether the processor uses hardware interlocks to protect reads
520 from the GPRs after they are loaded from memory, and thus does not
521 require nops to be inserted. This applies to instructions marked
522 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
523 level I and microMIPS mode instructions are always interlocked. */
524 #define gpr_interlocks \
525 (mips_opts.isa != ISA_MIPS1 \
526 || mips_opts.arch == CPU_R3900 \
527 || mips_opts.arch == CPU_R5900 \
528 || mips_opts.micromips \
531 /* Whether the processor uses hardware interlocks to avoid delays
532 required by coprocessor instructions, and thus does not require
533 nops to be inserted. This applies to instructions marked
534 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
535 between instructions marked INSN_WRITE_COND_CODE and ones marked
536 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
537 levels I, II, and III and microMIPS mode instructions are always
539 /* Itbl support may require additional care here. */
540 #define cop_interlocks \
541 ((mips_opts.isa != ISA_MIPS1 \
542 && mips_opts.isa != ISA_MIPS2 \
543 && mips_opts.isa != ISA_MIPS3) \
544 || mips_opts.arch == CPU_R4300 \
545 || mips_opts.micromips \
548 /* Whether the processor uses hardware interlocks to protect reads
549 from coprocessor registers after they are loaded from memory, and
550 thus does not require nops to be inserted. This applies to
551 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
552 requires at MIPS ISA level I and microMIPS mode instructions are
553 always interlocked. */
554 #define cop_mem_interlocks \
555 (mips_opts.isa != ISA_MIPS1 \
556 || mips_opts.micromips \
559 /* Is this a mfhi or mflo instruction? */
560 #define MF_HILO_INSN(PINFO) \
561 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
563 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
564 has been selected. This implies, in particular, that addresses of text
565 labels have their LSB set. */
566 #define HAVE_CODE_COMPRESSION \
567 ((mips_opts.mips16 | mips_opts.micromips) != 0)
569 /* The minimum and maximum signed values that can be stored in a GPR. */
570 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
571 #define GPR_SMIN (-GPR_SMAX - 1)
573 /* MIPS PIC level. */
575 enum mips_pic_level mips_pic
;
577 /* 1 if we should generate 32 bit offsets from the $gp register in
578 SVR4_PIC mode. Currently has no meaning in other modes. */
579 static int mips_big_got
= 0;
581 /* 1 if trap instructions should used for overflow rather than break
583 static int mips_trap
= 0;
585 /* 1 if double width floating point constants should not be constructed
586 by assembling two single width halves into two single width floating
587 point registers which just happen to alias the double width destination
588 register. On some architectures this aliasing can be disabled by a bit
589 in the status register, and the setting of this bit cannot be determined
590 automatically at assemble time. */
591 static int mips_disable_float_construction
;
593 /* Non-zero if any .set noreorder directives were used. */
595 static int mips_any_noreorder
;
597 /* Non-zero if nops should be inserted when the register referenced in
598 an mfhi/mflo instruction is read in the next two instructions. */
599 static int mips_7000_hilo_fix
;
601 /* The size of objects in the small data section. */
602 static unsigned int g_switch_value
= 8;
603 /* Whether the -G option was used. */
604 static int g_switch_seen
= 0;
609 /* If we can determine in advance that GP optimization won't be
610 possible, we can skip the relaxation stuff that tries to produce
611 GP-relative references. This makes delay slot optimization work
614 This function can only provide a guess, but it seems to work for
615 gcc output. It needs to guess right for gcc, otherwise gcc
616 will put what it thinks is a GP-relative instruction in a branch
619 I don't know if a fix is needed for the SVR4_PIC mode. I've only
620 fixed it for the non-PIC mode. KR 95/04/07 */
621 static int nopic_need_relax (symbolS
*, int);
623 /* handle of the OPCODE hash table */
624 static struct hash_control
*op_hash
= NULL
;
626 /* The opcode hash table we use for the mips16. */
627 static struct hash_control
*mips16_op_hash
= NULL
;
629 /* The opcode hash table we use for the microMIPS ASE. */
630 static struct hash_control
*micromips_op_hash
= NULL
;
632 /* This array holds the chars that always start a comment. If the
633 pre-processor is disabled, these aren't very useful */
634 const char comment_chars
[] = "#";
636 /* This array holds the chars that only start a comment at the beginning of
637 a line. If the line seems to have the form '# 123 filename'
638 .line and .file directives will appear in the pre-processed output */
639 /* Note that input_file.c hand checks for '#' at the beginning of the
640 first line of the input file. This is because the compiler outputs
641 #NO_APP at the beginning of its output. */
642 /* Also note that C style comments are always supported. */
643 const char line_comment_chars
[] = "#";
645 /* This array holds machine specific line separator characters. */
646 const char line_separator_chars
[] = ";";
648 /* Chars that can be used to separate mant from exp in floating point nums */
649 const char EXP_CHARS
[] = "eE";
651 /* Chars that mean this number is a floating point constant */
654 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
656 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
657 changed in read.c . Ideally it shouldn't have to know about it at all,
658 but nothing is ideal around here.
661 /* Types of printf format used for instruction-related error messages.
662 "I" means int ("%d") and "S" means string ("%s"). */
663 enum mips_insn_error_format
{
669 /* Information about an error that was found while assembling the current
671 struct mips_insn_error
{
672 /* We sometimes need to match an instruction against more than one
673 opcode table entry. Errors found during this matching are reported
674 against a particular syntactic argument rather than against the
675 instruction as a whole. We grade these messages so that errors
676 against argument N have a greater priority than an error against
677 any argument < N, since the former implies that arguments up to N
678 were acceptable and that the opcode entry was therefore a closer match.
679 If several matches report an error against the same argument,
680 we only use that error if it is the same in all cases.
682 min_argnum is the minimum argument number for which an error message
683 should be accepted. It is 0 if MSG is against the instruction as
687 /* The printf()-style message, including its format and arguments. */
688 enum mips_insn_error_format format
;
696 /* The error that should be reported for the current instruction. */
697 static struct mips_insn_error insn_error
;
699 static int auto_align
= 1;
701 /* When outputting SVR4 PIC code, the assembler needs to know the
702 offset in the stack frame from which to restore the $gp register.
703 This is set by the .cprestore pseudo-op, and saved in this
705 static offsetT mips_cprestore_offset
= -1;
707 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
708 more optimizations, it can use a register value instead of a memory-saved
709 offset and even an other register than $gp as global pointer. */
710 static offsetT mips_cpreturn_offset
= -1;
711 static int mips_cpreturn_register
= -1;
712 static int mips_gp_register
= GP
;
713 static int mips_gprel_offset
= 0;
715 /* Whether mips_cprestore_offset has been set in the current function
716 (or whether it has already been warned about, if not). */
717 static int mips_cprestore_valid
= 0;
719 /* This is the register which holds the stack frame, as set by the
720 .frame pseudo-op. This is needed to implement .cprestore. */
721 static int mips_frame_reg
= SP
;
723 /* Whether mips_frame_reg has been set in the current function
724 (or whether it has already been warned about, if not). */
725 static int mips_frame_reg_valid
= 0;
727 /* To output NOP instructions correctly, we need to keep information
728 about the previous two instructions. */
730 /* Whether we are optimizing. The default value of 2 means to remove
731 unneeded NOPs and swap branch instructions when possible. A value
732 of 1 means to not swap branches. A value of 0 means to always
734 static int mips_optimize
= 2;
736 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
737 equivalent to seeing no -g option at all. */
738 static int mips_debug
= 0;
740 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
741 #define MAX_VR4130_NOPS 4
743 /* The maximum number of NOPs needed to fill delay slots. */
744 #define MAX_DELAY_NOPS 2
746 /* The maximum number of NOPs needed for any purpose. */
749 /* A list of previous instructions, with index 0 being the most recent.
750 We need to look back MAX_NOPS instructions when filling delay slots
751 or working around processor errata. We need to look back one
752 instruction further if we're thinking about using history[0] to
753 fill a branch delay slot. */
754 static struct mips_cl_insn history
[1 + MAX_NOPS
];
756 /* Arrays of operands for each instruction. */
757 #define MAX_OPERANDS 6
758 struct mips_operand_array
{
759 const struct mips_operand
*operand
[MAX_OPERANDS
];
761 static struct mips_operand_array
*mips_operands
;
762 static struct mips_operand_array
*mips16_operands
;
763 static struct mips_operand_array
*micromips_operands
;
765 /* Nop instructions used by emit_nop. */
766 static struct mips_cl_insn nop_insn
;
767 static struct mips_cl_insn mips16_nop_insn
;
768 static struct mips_cl_insn micromips_nop16_insn
;
769 static struct mips_cl_insn micromips_nop32_insn
;
771 /* The appropriate nop for the current mode. */
772 #define NOP_INSN (mips_opts.mips16 \
774 : (mips_opts.micromips \
775 ? (mips_opts.insn32 \
776 ? µmips_nop32_insn \
777 : µmips_nop16_insn) \
780 /* The size of NOP_INSN in bytes. */
781 #define NOP_INSN_SIZE ((mips_opts.mips16 \
782 || (mips_opts.micromips && !mips_opts.insn32)) \
785 /* If this is set, it points to a frag holding nop instructions which
786 were inserted before the start of a noreorder section. If those
787 nops turn out to be unnecessary, the size of the frag can be
789 static fragS
*prev_nop_frag
;
791 /* The number of nop instructions we created in prev_nop_frag. */
792 static int prev_nop_frag_holds
;
794 /* The number of nop instructions that we know we need in
796 static int prev_nop_frag_required
;
798 /* The number of instructions we've seen since prev_nop_frag. */
799 static int prev_nop_frag_since
;
801 /* Relocations against symbols are sometimes done in two parts, with a HI
802 relocation and a LO relocation. Each relocation has only 16 bits of
803 space to store an addend. This means that in order for the linker to
804 handle carries correctly, it must be able to locate both the HI and
805 the LO relocation. This means that the relocations must appear in
806 order in the relocation table.
808 In order to implement this, we keep track of each unmatched HI
809 relocation. We then sort them so that they immediately precede the
810 corresponding LO relocation. */
815 struct mips_hi_fixup
*next
;
818 /* The section this fixup is in. */
822 /* The list of unmatched HI relocs. */
824 static struct mips_hi_fixup
*mips_hi_fixup_list
;
826 /* The frag containing the last explicit relocation operator.
827 Null if explicit relocations have not been used. */
829 static fragS
*prev_reloc_op_frag
;
831 /* Map mips16 register numbers to normal MIPS register numbers. */
833 static const unsigned int mips16_to_32_reg_map
[] =
835 16, 17, 2, 3, 4, 5, 6, 7
838 /* Map microMIPS register numbers to normal MIPS register numbers. */
840 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
842 /* The microMIPS registers with type h. */
843 static const unsigned int micromips_to_32_reg_h_map1
[] =
845 5, 5, 6, 4, 4, 4, 4, 4
847 static const unsigned int micromips_to_32_reg_h_map2
[] =
849 6, 7, 7, 21, 22, 5, 6, 7
852 /* The microMIPS registers with type m. */
853 static const unsigned int micromips_to_32_reg_m_map
[] =
855 0, 17, 2, 3, 16, 18, 19, 20
858 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
860 /* Classifies the kind of instructions we're interested in when
861 implementing -mfix-vr4120. */
862 enum fix_vr4120_class
870 NUM_FIX_VR4120_CLASSES
873 /* ...likewise -mfix-loongson2f-jump. */
874 static bfd_boolean mips_fix_loongson2f_jump
;
876 /* ...likewise -mfix-loongson2f-nop. */
877 static bfd_boolean mips_fix_loongson2f_nop
;
879 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
880 static bfd_boolean mips_fix_loongson2f
;
882 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
883 there must be at least one other instruction between an instruction
884 of type X and an instruction of type Y. */
885 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
887 /* True if -mfix-vr4120 is in force. */
888 static int mips_fix_vr4120
;
890 /* ...likewise -mfix-vr4130. */
891 static int mips_fix_vr4130
;
893 /* ...likewise -mfix-24k. */
894 static int mips_fix_24k
;
896 /* ...likewise -mfix-rm7000 */
897 static int mips_fix_rm7000
;
899 /* ...likewise -mfix-cn63xxp1 */
900 static bfd_boolean mips_fix_cn63xxp1
;
902 /* We don't relax branches by default, since this causes us to expand
903 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
904 fail to compute the offset before expanding the macro to the most
905 efficient expansion. */
907 static int mips_relax_branch
;
909 /* The expansion of many macros depends on the type of symbol that
910 they refer to. For example, when generating position-dependent code,
911 a macro that refers to a symbol may have two different expansions,
912 one which uses GP-relative addresses and one which uses absolute
913 addresses. When generating SVR4-style PIC, a macro may have
914 different expansions for local and global symbols.
916 We handle these situations by generating both sequences and putting
917 them in variant frags. In position-dependent code, the first sequence
918 will be the GP-relative one and the second sequence will be the
919 absolute one. In SVR4 PIC, the first sequence will be for global
920 symbols and the second will be for local symbols.
922 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
923 SECOND are the lengths of the two sequences in bytes. These fields
924 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
925 the subtype has the following flags:
928 Set if it has been decided that we should use the second
929 sequence instead of the first.
932 Set in the first variant frag if the macro's second implementation
933 is longer than its first. This refers to the macro as a whole,
934 not an individual relaxation.
937 Set in the first variant frag if the macro appeared in a .set nomacro
938 block and if one alternative requires a warning but the other does not.
941 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
944 RELAX_DELAY_SLOT_16BIT
945 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
948 RELAX_DELAY_SLOT_SIZE_FIRST
949 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
950 the macro is of the wrong size for the branch delay slot.
952 RELAX_DELAY_SLOT_SIZE_SECOND
953 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
954 the macro is of the wrong size for the branch delay slot.
956 The frag's "opcode" points to the first fixup for relaxable code.
958 Relaxable macros are generated using a sequence such as:
960 relax_start (SYMBOL);
961 ... generate first expansion ...
963 ... generate second expansion ...
966 The code and fixups for the unwanted alternative are discarded
967 by md_convert_frag. */
968 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
970 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
971 #define RELAX_SECOND(X) ((X) & 0xff)
972 #define RELAX_USE_SECOND 0x10000
973 #define RELAX_SECOND_LONGER 0x20000
974 #define RELAX_NOMACRO 0x40000
975 #define RELAX_DELAY_SLOT 0x80000
976 #define RELAX_DELAY_SLOT_16BIT 0x100000
977 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
978 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
980 /* Branch without likely bit. If label is out of range, we turn:
982 beq reg1, reg2, label
992 with the following opcode replacements:
999 bltzal <-> bgezal (with jal label instead of j label)
1001 Even though keeping the delay slot instruction in the delay slot of
1002 the branch would be more efficient, it would be very tricky to do
1003 correctly, because we'd have to introduce a variable frag *after*
1004 the delay slot instruction, and expand that instead. Let's do it
1005 the easy way for now, even if the branch-not-taken case now costs
1006 one additional instruction. Out-of-range branches are not supposed
1007 to be common, anyway.
1009 Branch likely. If label is out of range, we turn:
1011 beql reg1, reg2, label
1012 delay slot (annulled if branch not taken)
1021 delay slot (executed only if branch taken)
1024 It would be possible to generate a shorter sequence by losing the
1025 likely bit, generating something like:
1030 delay slot (executed only if branch taken)
1042 bltzall -> bgezal (with jal label instead of j label)
1043 bgezall -> bltzal (ditto)
1046 but it's not clear that it would actually improve performance. */
1047 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1048 ((relax_substateT) \
1051 | ((toofar) ? 0x20 : 0) \
1052 | ((link) ? 0x40 : 0) \
1053 | ((likely) ? 0x80 : 0) \
1054 | ((uncond) ? 0x100 : 0)))
1055 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1056 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1057 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1058 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1059 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1060 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1062 /* For mips16 code, we use an entirely different form of relaxation.
1063 mips16 supports two versions of most instructions which take
1064 immediate values: a small one which takes some small value, and a
1065 larger one which takes a 16 bit value. Since branches also follow
1066 this pattern, relaxing these values is required.
1068 We can assemble both mips16 and normal MIPS code in a single
1069 object. Therefore, we need to support this type of relaxation at
1070 the same time that we support the relaxation described above. We
1071 use the high bit of the subtype field to distinguish these cases.
1073 The information we store for this type of relaxation is the
1074 argument code found in the opcode file for this relocation, whether
1075 the user explicitly requested a small or extended form, and whether
1076 the relocation is in a jump or jal delay slot. That tells us the
1077 size of the value, and how it should be stored. We also store
1078 whether the fragment is considered to be extended or not. We also
1079 store whether this is known to be a branch to a different section,
1080 whether we have tried to relax this frag yet, and whether we have
1081 ever extended a PC relative fragment because of a shift count. */
1082 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1085 | ((small) ? 0x100 : 0) \
1086 | ((ext) ? 0x200 : 0) \
1087 | ((dslot) ? 0x400 : 0) \
1088 | ((jal_dslot) ? 0x800 : 0))
1089 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1090 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1091 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1092 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1093 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1094 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1095 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1096 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1097 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1098 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1099 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1100 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1102 /* For microMIPS code, we use relaxation similar to one we use for
1103 MIPS16 code. Some instructions that take immediate values support
1104 two encodings: a small one which takes some small value, and a
1105 larger one which takes a 16 bit value. As some branches also follow
1106 this pattern, relaxing these values is required.
1108 We can assemble both microMIPS and normal MIPS code in a single
1109 object. Therefore, we need to support this type of relaxation at
1110 the same time that we support the relaxation described above. We
1111 use one of the high bits of the subtype field to distinguish these
1114 The information we store for this type of relaxation is the argument
1115 code found in the opcode file for this relocation, the register
1116 selected as the assembler temporary, whether the branch is
1117 unconditional, whether it is compact, whether it stores the link
1118 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1119 branches to a sequence of instructions is enabled, and whether the
1120 displacement of a branch is too large to fit as an immediate argument
1121 of a 16-bit and a 32-bit branch, respectively. */
1122 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1123 relax32, toofar16, toofar32) \
1126 | (((at) & 0x1f) << 8) \
1127 | ((uncond) ? 0x2000 : 0) \
1128 | ((compact) ? 0x4000 : 0) \
1129 | ((link) ? 0x8000 : 0) \
1130 | ((relax32) ? 0x10000 : 0) \
1131 | ((toofar16) ? 0x20000 : 0) \
1132 | ((toofar32) ? 0x40000 : 0))
1133 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1134 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1135 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1136 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1137 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1138 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1139 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1141 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1142 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1143 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1144 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1145 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1146 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1148 /* Sign-extend 16-bit value X. */
1149 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1151 /* Is the given value a sign-extended 32-bit value? */
1152 #define IS_SEXT_32BIT_NUM(x) \
1153 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1154 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1156 /* Is the given value a sign-extended 16-bit value? */
1157 #define IS_SEXT_16BIT_NUM(x) \
1158 (((x) &~ (offsetT) 0x7fff) == 0 \
1159 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1161 /* Is the given value a sign-extended 12-bit value? */
1162 #define IS_SEXT_12BIT_NUM(x) \
1163 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1165 /* Is the given value a sign-extended 9-bit value? */
1166 #define IS_SEXT_9BIT_NUM(x) \
1167 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1169 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1170 #define IS_ZEXT_32BIT_NUM(x) \
1171 (((x) &~ (offsetT) 0xffffffff) == 0 \
1172 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1174 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1176 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1177 (((STRUCT) >> (SHIFT)) & (MASK))
1179 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1180 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1182 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1183 : EXTRACT_BITS ((INSN).insn_opcode, \
1184 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1185 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1186 EXTRACT_BITS ((INSN).insn_opcode, \
1187 MIPS16OP_MASK_##FIELD, \
1188 MIPS16OP_SH_##FIELD)
1190 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1191 #define MIPS16_EXTEND (0xf000U << 16)
1193 /* Whether or not we are emitting a branch-likely macro. */
1194 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1196 /* Global variables used when generating relaxable macros. See the
1197 comment above RELAX_ENCODE for more details about how relaxation
1200 /* 0 if we're not emitting a relaxable macro.
1201 1 if we're emitting the first of the two relaxation alternatives.
1202 2 if we're emitting the second alternative. */
1205 /* The first relaxable fixup in the current frag. (In other words,
1206 the first fixup that refers to relaxable code.) */
1209 /* sizes[0] says how many bytes of the first alternative are stored in
1210 the current frag. Likewise sizes[1] for the second alternative. */
1211 unsigned int sizes
[2];
1213 /* The symbol on which the choice of sequence depends. */
1217 /* Global variables used to decide whether a macro needs a warning. */
1219 /* True if the macro is in a branch delay slot. */
1220 bfd_boolean delay_slot_p
;
1222 /* Set to the length in bytes required if the macro is in a delay slot
1223 that requires a specific length of instruction, otherwise zero. */
1224 unsigned int delay_slot_length
;
1226 /* For relaxable macros, sizes[0] is the length of the first alternative
1227 in bytes and sizes[1] is the length of the second alternative.
1228 For non-relaxable macros, both elements give the length of the
1230 unsigned int sizes
[2];
1232 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1233 instruction of the first alternative in bytes and first_insn_sizes[1]
1234 is the length of the first instruction of the second alternative.
1235 For non-relaxable macros, both elements give the length of the first
1236 instruction in bytes.
1238 Set to zero if we haven't yet seen the first instruction. */
1239 unsigned int first_insn_sizes
[2];
1241 /* For relaxable macros, insns[0] is the number of instructions for the
1242 first alternative and insns[1] is the number of instructions for the
1245 For non-relaxable macros, both elements give the number of
1246 instructions for the macro. */
1247 unsigned int insns
[2];
1249 /* The first variant frag for this macro. */
1251 } mips_macro_warning
;
1253 /* Prototypes for static functions. */
1255 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1257 static void append_insn
1258 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1259 bfd_boolean expansionp
);
1260 static void mips_no_prev_insn (void);
1261 static void macro_build (expressionS
*, const char *, const char *, ...);
1262 static void mips16_macro_build
1263 (expressionS
*, const char *, const char *, va_list *);
1264 static void load_register (int, expressionS
*, int);
1265 static void macro_start (void);
1266 static void macro_end (void);
1267 static void macro (struct mips_cl_insn
*ip
, char *str
);
1268 static void mips16_macro (struct mips_cl_insn
* ip
);
1269 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1270 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1271 static void mips16_immed
1272 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1273 unsigned int, unsigned long *);
1274 static size_t my_getSmallExpression
1275 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1276 static void my_getExpression (expressionS
*, char *);
1277 static void s_align (int);
1278 static void s_change_sec (int);
1279 static void s_change_section (int);
1280 static void s_cons (int);
1281 static void s_float_cons (int);
1282 static void s_mips_globl (int);
1283 static void s_option (int);
1284 static void s_mipsset (int);
1285 static void s_abicalls (int);
1286 static void s_cpload (int);
1287 static void s_cpsetup (int);
1288 static void s_cplocal (int);
1289 static void s_cprestore (int);
1290 static void s_cpreturn (int);
1291 static void s_dtprelword (int);
1292 static void s_dtpreldword (int);
1293 static void s_tprelword (int);
1294 static void s_tpreldword (int);
1295 static void s_gpvalue (int);
1296 static void s_gpword (int);
1297 static void s_gpdword (int);
1298 static void s_ehword (int);
1299 static void s_cpadd (int);
1300 static void s_insn (int);
1301 static void s_nan (int);
1302 static void md_obj_begin (void);
1303 static void md_obj_end (void);
1304 static void s_mips_ent (int);
1305 static void s_mips_end (int);
1306 static void s_mips_frame (int);
1307 static void s_mips_mask (int reg_type
);
1308 static void s_mips_stab (int);
1309 static void s_mips_weakext (int);
1310 static void s_mips_file (int);
1311 static void s_mips_loc (int);
1312 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1313 static int relaxed_branch_length (fragS
*, asection
*, int);
1314 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1315 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1317 /* Table and functions used to map between CPU/ISA names, and
1318 ISA levels, and CPU numbers. */
1320 struct mips_cpu_info
1322 const char *name
; /* CPU or ISA name. */
1323 int flags
; /* MIPS_CPU_* flags. */
1324 int ase
; /* Set of ASEs implemented by the CPU. */
1325 int isa
; /* ISA level. */
1326 int cpu
; /* CPU number (default CPU if ISA). */
1329 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1331 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1332 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1333 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1335 /* Command-line options. */
1336 const char *md_shortopts
= "O::g::G:";
1340 OPTION_MARCH
= OPTION_MD_BASE
,
1370 OPTION_NO_SMARTMIPS
,
1378 OPTION_NO_MICROMIPS
,
1381 OPTION_COMPAT_ARCH_BASE
,
1390 OPTION_M7000_HILO_FIX
,
1391 OPTION_MNO_7000_HILO_FIX
,
1395 OPTION_NO_FIX_RM7000
,
1396 OPTION_FIX_LOONGSON2F_JUMP
,
1397 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1398 OPTION_FIX_LOONGSON2F_NOP
,
1399 OPTION_NO_FIX_LOONGSON2F_NOP
,
1401 OPTION_NO_FIX_VR4120
,
1403 OPTION_NO_FIX_VR4130
,
1404 OPTION_FIX_CN63XXP1
,
1405 OPTION_NO_FIX_CN63XXP1
,
1412 OPTION_CONSTRUCT_FLOATS
,
1413 OPTION_NO_CONSTRUCT_FLOATS
,
1416 OPTION_RELAX_BRANCH
,
1417 OPTION_NO_RELAX_BRANCH
,
1426 OPTION_SINGLE_FLOAT
,
1427 OPTION_DOUBLE_FLOAT
,
1440 OPTION_MVXWORKS_PIC
,
1445 struct option md_longopts
[] =
1447 /* Options which specify architecture. */
1448 {"march", required_argument
, NULL
, OPTION_MARCH
},
1449 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1450 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1451 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1452 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1453 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1454 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1455 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1456 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1457 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1458 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1459 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1460 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1461 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1462 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1463 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1465 /* Options which specify Application Specific Extensions (ASEs). */
1466 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1467 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1468 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1469 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1470 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1471 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1472 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1473 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1474 {"mmt", no_argument
, NULL
, OPTION_MT
},
1475 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1476 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1477 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1478 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1479 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1480 {"meva", no_argument
, NULL
, OPTION_EVA
},
1481 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1482 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1483 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1484 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1485 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1486 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1487 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1488 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1489 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1490 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1491 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1493 /* Old-style architecture options. Don't add more of these. */
1494 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1495 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1496 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1497 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1498 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1499 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1500 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1501 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1503 /* Options which enable bug fixes. */
1504 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1505 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1506 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1507 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1508 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1509 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1510 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1511 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1512 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1513 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1514 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1515 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1516 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1517 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1518 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1519 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1520 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1522 /* Miscellaneous options. */
1523 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1524 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1525 {"break", no_argument
, NULL
, OPTION_BREAK
},
1526 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1527 {"EB", no_argument
, NULL
, OPTION_EB
},
1528 {"EL", no_argument
, NULL
, OPTION_EL
},
1529 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1530 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1531 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1532 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1533 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1534 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1535 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1536 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1537 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1538 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1539 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1540 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1541 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1542 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1543 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1544 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1545 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1546 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1548 /* Strictly speaking this next option is ELF specific,
1549 but we allow it for other ports as well in order to
1550 make testing easier. */
1551 {"32", no_argument
, NULL
, OPTION_32
},
1553 /* ELF-specific options. */
1554 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1555 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1556 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1557 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1558 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1559 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1560 {"n32", no_argument
, NULL
, OPTION_N32
},
1561 {"64", no_argument
, NULL
, OPTION_64
},
1562 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1563 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1564 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1565 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1566 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1567 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1569 {NULL
, no_argument
, NULL
, 0}
1571 size_t md_longopts_size
= sizeof (md_longopts
);
1573 /* Information about either an Application Specific Extension or an
1574 optional architecture feature that, for simplicity, we treat in the
1575 same way as an ASE. */
1578 /* The name of the ASE, used in both the command-line and .set options. */
1581 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1582 and 64-bit architectures, the flags here refer to the subset that
1583 is available on both. */
1586 /* The ASE_* flag used for instructions that are available on 64-bit
1587 architectures but that are not included in FLAGS. */
1588 unsigned int flags64
;
1590 /* The command-line options that turn the ASE on and off. */
1594 /* The minimum required architecture revisions for MIPS32, MIPS64,
1595 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1598 int micromips32_rev
;
1599 int micromips64_rev
;
1602 /* A table of all supported ASEs. */
1603 static const struct mips_ase mips_ases
[] = {
1604 { "dsp", ASE_DSP
, ASE_DSP64
,
1605 OPTION_DSP
, OPTION_NO_DSP
,
1608 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1609 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1612 { "eva", ASE_EVA
, 0,
1613 OPTION_EVA
, OPTION_NO_EVA
,
1616 { "mcu", ASE_MCU
, 0,
1617 OPTION_MCU
, OPTION_NO_MCU
,
1620 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1621 { "mdmx", ASE_MDMX
, 0,
1622 OPTION_MDMX
, OPTION_NO_MDMX
,
1625 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1626 { "mips3d", ASE_MIPS3D
, 0,
1627 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1631 OPTION_MT
, OPTION_NO_MT
,
1634 { "smartmips", ASE_SMARTMIPS
, 0,
1635 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1638 { "virt", ASE_VIRT
, ASE_VIRT64
,
1639 OPTION_VIRT
, OPTION_NO_VIRT
,
1642 { "msa", ASE_MSA
, ASE_MSA64
,
1643 OPTION_MSA
, OPTION_NO_MSA
,
1646 { "xpa", ASE_XPA
, 0,
1647 OPTION_XPA
, OPTION_NO_XPA
,
1651 /* The set of ASEs that require -mfp64. */
1652 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1654 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1655 static const unsigned int mips_ase_groups
[] = {
1661 The following pseudo-ops from the Kane and Heinrich MIPS book
1662 should be defined here, but are currently unsupported: .alias,
1663 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1665 The following pseudo-ops from the Kane and Heinrich MIPS book are
1666 specific to the type of debugging information being generated, and
1667 should be defined by the object format: .aent, .begin, .bend,
1668 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1671 The following pseudo-ops from the Kane and Heinrich MIPS book are
1672 not MIPS CPU specific, but are also not specific to the object file
1673 format. This file is probably the best place to define them, but
1674 they are not currently supported: .asm0, .endr, .lab, .struct. */
1676 static const pseudo_typeS mips_pseudo_table
[] =
1678 /* MIPS specific pseudo-ops. */
1679 {"option", s_option
, 0},
1680 {"set", s_mipsset
, 0},
1681 {"rdata", s_change_sec
, 'r'},
1682 {"sdata", s_change_sec
, 's'},
1683 {"livereg", s_ignore
, 0},
1684 {"abicalls", s_abicalls
, 0},
1685 {"cpload", s_cpload
, 0},
1686 {"cpsetup", s_cpsetup
, 0},
1687 {"cplocal", s_cplocal
, 0},
1688 {"cprestore", s_cprestore
, 0},
1689 {"cpreturn", s_cpreturn
, 0},
1690 {"dtprelword", s_dtprelword
, 0},
1691 {"dtpreldword", s_dtpreldword
, 0},
1692 {"tprelword", s_tprelword
, 0},
1693 {"tpreldword", s_tpreldword
, 0},
1694 {"gpvalue", s_gpvalue
, 0},
1695 {"gpword", s_gpword
, 0},
1696 {"gpdword", s_gpdword
, 0},
1697 {"ehword", s_ehword
, 0},
1698 {"cpadd", s_cpadd
, 0},
1699 {"insn", s_insn
, 0},
1702 /* Relatively generic pseudo-ops that happen to be used on MIPS
1704 {"asciiz", stringer
, 8 + 1},
1705 {"bss", s_change_sec
, 'b'},
1707 {"half", s_cons
, 1},
1708 {"dword", s_cons
, 3},
1709 {"weakext", s_mips_weakext
, 0},
1710 {"origin", s_org
, 0},
1711 {"repeat", s_rept
, 0},
1713 /* For MIPS this is non-standard, but we define it for consistency. */
1714 {"sbss", s_change_sec
, 'B'},
1716 /* These pseudo-ops are defined in read.c, but must be overridden
1717 here for one reason or another. */
1718 {"align", s_align
, 0},
1719 {"byte", s_cons
, 0},
1720 {"data", s_change_sec
, 'd'},
1721 {"double", s_float_cons
, 'd'},
1722 {"float", s_float_cons
, 'f'},
1723 {"globl", s_mips_globl
, 0},
1724 {"global", s_mips_globl
, 0},
1725 {"hword", s_cons
, 1},
1727 {"long", s_cons
, 2},
1728 {"octa", s_cons
, 4},
1729 {"quad", s_cons
, 3},
1730 {"section", s_change_section
, 0},
1731 {"short", s_cons
, 1},
1732 {"single", s_float_cons
, 'f'},
1733 {"stabd", s_mips_stab
, 'd'},
1734 {"stabn", s_mips_stab
, 'n'},
1735 {"stabs", s_mips_stab
, 's'},
1736 {"text", s_change_sec
, 't'},
1737 {"word", s_cons
, 2},
1739 { "extern", ecoff_directive_extern
, 0},
1744 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1746 /* These pseudo-ops should be defined by the object file format.
1747 However, a.out doesn't support them, so we have versions here. */
1748 {"aent", s_mips_ent
, 1},
1749 {"bgnb", s_ignore
, 0},
1750 {"end", s_mips_end
, 0},
1751 {"endb", s_ignore
, 0},
1752 {"ent", s_mips_ent
, 0},
1753 {"file", s_mips_file
, 0},
1754 {"fmask", s_mips_mask
, 'F'},
1755 {"frame", s_mips_frame
, 0},
1756 {"loc", s_mips_loc
, 0},
1757 {"mask", s_mips_mask
, 'R'},
1758 {"verstamp", s_ignore
, 0},
1762 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1763 purpose of the `.dc.a' internal pseudo-op. */
1766 mips_address_bytes (void)
1768 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1771 extern void pop_insert (const pseudo_typeS
*);
1774 mips_pop_insert (void)
1776 pop_insert (mips_pseudo_table
);
1777 if (! ECOFF_DEBUGGING
)
1778 pop_insert (mips_nonecoff_pseudo_table
);
1781 /* Symbols labelling the current insn. */
1783 struct insn_label_list
1785 struct insn_label_list
*next
;
1789 static struct insn_label_list
*free_insn_labels
;
1790 #define label_list tc_segment_info_data.labels
1792 static void mips_clear_insn_labels (void);
1793 static void mips_mark_labels (void);
1794 static void mips_compressed_mark_labels (void);
1797 mips_clear_insn_labels (void)
1799 register struct insn_label_list
**pl
;
1800 segment_info_type
*si
;
1804 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1807 si
= seg_info (now_seg
);
1808 *pl
= si
->label_list
;
1809 si
->label_list
= NULL
;
1813 /* Mark instruction labels in MIPS16/microMIPS mode. */
1816 mips_mark_labels (void)
1818 if (HAVE_CODE_COMPRESSION
)
1819 mips_compressed_mark_labels ();
1822 static char *expr_end
;
1824 /* An expression in a macro instruction. This is set by mips_ip and
1825 mips16_ip and when populated is always an O_constant. */
1827 static expressionS imm_expr
;
1829 /* The relocatable field in an instruction and the relocs associated
1830 with it. These variables are used for instructions like LUI and
1831 JAL as well as true offsets. They are also used for address
1832 operands in macros. */
1834 static expressionS offset_expr
;
1835 static bfd_reloc_code_real_type offset_reloc
[3]
1836 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1838 /* This is set to the resulting size of the instruction to be produced
1839 by mips16_ip if an explicit extension is used or by mips_ip if an
1840 explicit size is supplied. */
1842 static unsigned int forced_insn_length
;
1844 /* True if we are assembling an instruction. All dot symbols defined during
1845 this time should be treated as code labels. */
1847 static bfd_boolean mips_assembling_insn
;
1849 /* The pdr segment for per procedure frame/regmask info. Not used for
1852 static segT pdr_seg
;
1854 /* The default target format to use. */
1856 #if defined (TE_FreeBSD)
1857 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1858 #elif defined (TE_TMIPS)
1859 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1861 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1865 mips_target_format (void)
1867 switch (OUTPUT_FLAVOR
)
1869 case bfd_target_elf_flavour
:
1871 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1872 return (target_big_endian
1873 ? "elf32-bigmips-vxworks"
1874 : "elf32-littlemips-vxworks");
1876 return (target_big_endian
1877 ? (HAVE_64BIT_OBJECTS
1878 ? ELF_TARGET ("elf64-", "big")
1880 ? ELF_TARGET ("elf32-n", "big")
1881 : ELF_TARGET ("elf32-", "big")))
1882 : (HAVE_64BIT_OBJECTS
1883 ? ELF_TARGET ("elf64-", "little")
1885 ? ELF_TARGET ("elf32-n", "little")
1886 : ELF_TARGET ("elf32-", "little"))));
1893 /* Return the ISA revision that is currently in use, or 0 if we are
1894 generating code for MIPS V or below. */
1899 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1902 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
1905 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
1908 /* microMIPS implies revision 2 or above. */
1909 if (mips_opts
.micromips
)
1912 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1918 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1921 mips_ase_mask (unsigned int flags
)
1925 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1926 if (flags
& mips_ase_groups
[i
])
1927 flags
|= mips_ase_groups
[i
];
1931 /* Check whether the current ISA supports ASE. Issue a warning if
1935 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1939 static unsigned int warned_isa
;
1940 static unsigned int warned_fp32
;
1942 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1943 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1945 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1946 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1947 && (warned_isa
& ase
->flags
) != ase
->flags
)
1949 warned_isa
|= ase
->flags
;
1950 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1951 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1953 as_warn (_("the %d-bit %s architecture does not support the"
1954 " `%s' extension"), size
, base
, ase
->name
);
1956 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
1957 ase
->name
, base
, size
, min_rev
);
1959 if ((ase
->flags
& FP64_ASES
)
1961 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1963 warned_fp32
|= ase
->flags
;
1964 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
1968 /* Check all enabled ASEs to see whether they are supported by the
1969 chosen architecture. */
1972 mips_check_isa_supports_ases (void)
1974 unsigned int i
, mask
;
1976 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1978 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1979 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1980 mips_check_isa_supports_ase (&mips_ases
[i
]);
1984 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1985 that were affected. */
1988 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1992 mask
= mips_ase_mask (ase
->flags
);
1993 mips_opts
.ase
&= ~mask
;
1995 mips_opts
.ase
|= ase
->flags
;
1999 /* Return the ASE called NAME, or null if none. */
2001 static const struct mips_ase
*
2002 mips_lookup_ase (const char *name
)
2006 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2007 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2008 return &mips_ases
[i
];
2012 /* Return the length of a microMIPS instruction in bytes. If bits of
2013 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2014 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2015 major opcode) will require further modifications to the opcode
2018 static inline unsigned int
2019 micromips_insn_length (const struct mips_opcode
*mo
)
2021 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2024 /* Return the length of MIPS16 instruction OPCODE. */
2026 static inline unsigned int
2027 mips16_opcode_length (unsigned long opcode
)
2029 return (opcode
>> 16) == 0 ? 2 : 4;
2032 /* Return the length of instruction INSN. */
2034 static inline unsigned int
2035 insn_length (const struct mips_cl_insn
*insn
)
2037 if (mips_opts
.micromips
)
2038 return micromips_insn_length (insn
->insn_mo
);
2039 else if (mips_opts
.mips16
)
2040 return mips16_opcode_length (insn
->insn_opcode
);
2045 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2048 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2053 insn
->insn_opcode
= mo
->match
;
2056 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2057 insn
->fixp
[i
] = NULL
;
2058 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2059 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2060 insn
->mips16_absolute_jump_p
= 0;
2061 insn
->complete_p
= 0;
2062 insn
->cleared_p
= 0;
2065 /* Get a list of all the operands in INSN. */
2067 static const struct mips_operand_array
*
2068 insn_operands (const struct mips_cl_insn
*insn
)
2070 if (insn
->insn_mo
>= &mips_opcodes
[0]
2071 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2072 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2074 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2075 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2076 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2078 if (insn
->insn_mo
>= µmips_opcodes
[0]
2079 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2080 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2085 /* Get a description of operand OPNO of INSN. */
2087 static const struct mips_operand
*
2088 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2090 const struct mips_operand_array
*operands
;
2092 operands
= insn_operands (insn
);
2093 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2095 return operands
->operand
[opno
];
2098 /* Install UVAL as the value of OPERAND in INSN. */
2101 insn_insert_operand (struct mips_cl_insn
*insn
,
2102 const struct mips_operand
*operand
, unsigned int uval
)
2104 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2107 /* Extract the value of OPERAND from INSN. */
2109 static inline unsigned
2110 insn_extract_operand (const struct mips_cl_insn
*insn
,
2111 const struct mips_operand
*operand
)
2113 return mips_extract_operand (operand
, insn
->insn_opcode
);
2116 /* Record the current MIPS16/microMIPS mode in now_seg. */
2119 mips_record_compressed_mode (void)
2121 segment_info_type
*si
;
2123 si
= seg_info (now_seg
);
2124 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2125 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2126 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2127 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2130 /* Read a standard MIPS instruction from BUF. */
2132 static unsigned long
2133 read_insn (char *buf
)
2135 if (target_big_endian
)
2136 return bfd_getb32 ((bfd_byte
*) buf
);
2138 return bfd_getl32 ((bfd_byte
*) buf
);
2141 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2145 write_insn (char *buf
, unsigned int insn
)
2147 md_number_to_chars (buf
, insn
, 4);
2151 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2152 has length LENGTH. */
2154 static unsigned long
2155 read_compressed_insn (char *buf
, unsigned int length
)
2161 for (i
= 0; i
< length
; i
+= 2)
2164 if (target_big_endian
)
2165 insn
|= bfd_getb16 ((char *) buf
);
2167 insn
|= bfd_getl16 ((char *) buf
);
2173 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2174 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2177 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2181 for (i
= 0; i
< length
; i
+= 2)
2182 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2183 return buf
+ length
;
2186 /* Install INSN at the location specified by its "frag" and "where" fields. */
2189 install_insn (const struct mips_cl_insn
*insn
)
2191 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2192 if (HAVE_CODE_COMPRESSION
)
2193 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2195 write_insn (f
, insn
->insn_opcode
);
2196 mips_record_compressed_mode ();
2199 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2200 and install the opcode in the new location. */
2203 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2208 insn
->where
= where
;
2209 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2210 if (insn
->fixp
[i
] != NULL
)
2212 insn
->fixp
[i
]->fx_frag
= frag
;
2213 insn
->fixp
[i
]->fx_where
= where
;
2215 install_insn (insn
);
2218 /* Add INSN to the end of the output. */
2221 add_fixed_insn (struct mips_cl_insn
*insn
)
2223 char *f
= frag_more (insn_length (insn
));
2224 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2227 /* Start a variant frag and move INSN to the start of the variant part,
2228 marking it as fixed. The other arguments are as for frag_var. */
2231 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2232 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2234 frag_grow (max_chars
);
2235 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2237 frag_var (rs_machine_dependent
, max_chars
, var
,
2238 subtype
, symbol
, offset
, NULL
);
2241 /* Insert N copies of INSN into the history buffer, starting at
2242 position FIRST. Neither FIRST nor N need to be clipped. */
2245 insert_into_history (unsigned int first
, unsigned int n
,
2246 const struct mips_cl_insn
*insn
)
2248 if (mips_relax
.sequence
!= 2)
2252 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2254 history
[i
] = history
[i
- n
];
2260 /* Clear the error in insn_error. */
2263 clear_insn_error (void)
2265 memset (&insn_error
, 0, sizeof (insn_error
));
2268 /* Possibly record error message MSG for the current instruction.
2269 If the error is about a particular argument, ARGNUM is the 1-based
2270 number of that argument, otherwise it is 0. FORMAT is the format
2271 of MSG. Return true if MSG was used, false if the current message
2275 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2280 /* Give priority to errors against specific arguments, and to
2281 the first whole-instruction message. */
2287 /* Keep insn_error if it is against a later argument. */
2288 if (argnum
< insn_error
.min_argnum
)
2291 /* If both errors are against the same argument but are different,
2292 give up on reporting a specific error for this argument.
2293 See the comment about mips_insn_error for details. */
2294 if (argnum
== insn_error
.min_argnum
2296 && strcmp (insn_error
.msg
, msg
) != 0)
2299 insn_error
.min_argnum
+= 1;
2303 insn_error
.min_argnum
= argnum
;
2304 insn_error
.format
= format
;
2305 insn_error
.msg
= msg
;
2309 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2310 as for set_insn_error_format. */
2313 set_insn_error (int argnum
, const char *msg
)
2315 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2318 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2319 as for set_insn_error_format. */
2322 set_insn_error_i (int argnum
, const char *msg
, int i
)
2324 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2328 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2329 are as for set_insn_error_format. */
2332 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2334 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2336 insn_error
.u
.ss
[0] = s1
;
2337 insn_error
.u
.ss
[1] = s2
;
2341 /* Report the error in insn_error, which is against assembly code STR. */
2344 report_insn_error (const char *str
)
2348 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2349 switch (insn_error
.format
)
2356 as_bad (msg
, insn_error
.u
.i
, str
);
2360 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2365 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2366 the idea is to make it obvious at a glance that each errata is
2370 init_vr4120_conflicts (void)
2372 #define CONFLICT(FIRST, SECOND) \
2373 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2375 /* Errata 21 - [D]DIV[U] after [D]MACC */
2376 CONFLICT (MACC
, DIV
);
2377 CONFLICT (DMACC
, DIV
);
2379 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2380 CONFLICT (DMULT
, DMULT
);
2381 CONFLICT (DMULT
, DMACC
);
2382 CONFLICT (DMACC
, DMULT
);
2383 CONFLICT (DMACC
, DMACC
);
2385 /* Errata 24 - MT{LO,HI} after [D]MACC */
2386 CONFLICT (MACC
, MTHILO
);
2387 CONFLICT (DMACC
, MTHILO
);
2389 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2390 instruction is executed immediately after a MACC or DMACC
2391 instruction, the result of [either instruction] is incorrect." */
2392 CONFLICT (MACC
, MULT
);
2393 CONFLICT (MACC
, DMULT
);
2394 CONFLICT (DMACC
, MULT
);
2395 CONFLICT (DMACC
, DMULT
);
2397 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2398 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2399 DDIV or DDIVU instruction, the result of the MACC or
2400 DMACC instruction is incorrect.". */
2401 CONFLICT (DMULT
, MACC
);
2402 CONFLICT (DMULT
, DMACC
);
2403 CONFLICT (DIV
, MACC
);
2404 CONFLICT (DIV
, DMACC
);
2414 #define RNUM_MASK 0x00000ff
2415 #define RTYPE_MASK 0x0ffff00
2416 #define RTYPE_NUM 0x0000100
2417 #define RTYPE_FPU 0x0000200
2418 #define RTYPE_FCC 0x0000400
2419 #define RTYPE_VEC 0x0000800
2420 #define RTYPE_GP 0x0001000
2421 #define RTYPE_CP0 0x0002000
2422 #define RTYPE_PC 0x0004000
2423 #define RTYPE_ACC 0x0008000
2424 #define RTYPE_CCC 0x0010000
2425 #define RTYPE_VI 0x0020000
2426 #define RTYPE_VF 0x0040000
2427 #define RTYPE_R5900_I 0x0080000
2428 #define RTYPE_R5900_Q 0x0100000
2429 #define RTYPE_R5900_R 0x0200000
2430 #define RTYPE_R5900_ACC 0x0400000
2431 #define RTYPE_MSA 0x0800000
2432 #define RWARN 0x8000000
2434 #define GENERIC_REGISTER_NUMBERS \
2435 {"$0", RTYPE_NUM | 0}, \
2436 {"$1", RTYPE_NUM | 1}, \
2437 {"$2", RTYPE_NUM | 2}, \
2438 {"$3", RTYPE_NUM | 3}, \
2439 {"$4", RTYPE_NUM | 4}, \
2440 {"$5", RTYPE_NUM | 5}, \
2441 {"$6", RTYPE_NUM | 6}, \
2442 {"$7", RTYPE_NUM | 7}, \
2443 {"$8", RTYPE_NUM | 8}, \
2444 {"$9", RTYPE_NUM | 9}, \
2445 {"$10", RTYPE_NUM | 10}, \
2446 {"$11", RTYPE_NUM | 11}, \
2447 {"$12", RTYPE_NUM | 12}, \
2448 {"$13", RTYPE_NUM | 13}, \
2449 {"$14", RTYPE_NUM | 14}, \
2450 {"$15", RTYPE_NUM | 15}, \
2451 {"$16", RTYPE_NUM | 16}, \
2452 {"$17", RTYPE_NUM | 17}, \
2453 {"$18", RTYPE_NUM | 18}, \
2454 {"$19", RTYPE_NUM | 19}, \
2455 {"$20", RTYPE_NUM | 20}, \
2456 {"$21", RTYPE_NUM | 21}, \
2457 {"$22", RTYPE_NUM | 22}, \
2458 {"$23", RTYPE_NUM | 23}, \
2459 {"$24", RTYPE_NUM | 24}, \
2460 {"$25", RTYPE_NUM | 25}, \
2461 {"$26", RTYPE_NUM | 26}, \
2462 {"$27", RTYPE_NUM | 27}, \
2463 {"$28", RTYPE_NUM | 28}, \
2464 {"$29", RTYPE_NUM | 29}, \
2465 {"$30", RTYPE_NUM | 30}, \
2466 {"$31", RTYPE_NUM | 31}
2468 #define FPU_REGISTER_NAMES \
2469 {"$f0", RTYPE_FPU | 0}, \
2470 {"$f1", RTYPE_FPU | 1}, \
2471 {"$f2", RTYPE_FPU | 2}, \
2472 {"$f3", RTYPE_FPU | 3}, \
2473 {"$f4", RTYPE_FPU | 4}, \
2474 {"$f5", RTYPE_FPU | 5}, \
2475 {"$f6", RTYPE_FPU | 6}, \
2476 {"$f7", RTYPE_FPU | 7}, \
2477 {"$f8", RTYPE_FPU | 8}, \
2478 {"$f9", RTYPE_FPU | 9}, \
2479 {"$f10", RTYPE_FPU | 10}, \
2480 {"$f11", RTYPE_FPU | 11}, \
2481 {"$f12", RTYPE_FPU | 12}, \
2482 {"$f13", RTYPE_FPU | 13}, \
2483 {"$f14", RTYPE_FPU | 14}, \
2484 {"$f15", RTYPE_FPU | 15}, \
2485 {"$f16", RTYPE_FPU | 16}, \
2486 {"$f17", RTYPE_FPU | 17}, \
2487 {"$f18", RTYPE_FPU | 18}, \
2488 {"$f19", RTYPE_FPU | 19}, \
2489 {"$f20", RTYPE_FPU | 20}, \
2490 {"$f21", RTYPE_FPU | 21}, \
2491 {"$f22", RTYPE_FPU | 22}, \
2492 {"$f23", RTYPE_FPU | 23}, \
2493 {"$f24", RTYPE_FPU | 24}, \
2494 {"$f25", RTYPE_FPU | 25}, \
2495 {"$f26", RTYPE_FPU | 26}, \
2496 {"$f27", RTYPE_FPU | 27}, \
2497 {"$f28", RTYPE_FPU | 28}, \
2498 {"$f29", RTYPE_FPU | 29}, \
2499 {"$f30", RTYPE_FPU | 30}, \
2500 {"$f31", RTYPE_FPU | 31}
2502 #define FPU_CONDITION_CODE_NAMES \
2503 {"$fcc0", RTYPE_FCC | 0}, \
2504 {"$fcc1", RTYPE_FCC | 1}, \
2505 {"$fcc2", RTYPE_FCC | 2}, \
2506 {"$fcc3", RTYPE_FCC | 3}, \
2507 {"$fcc4", RTYPE_FCC | 4}, \
2508 {"$fcc5", RTYPE_FCC | 5}, \
2509 {"$fcc6", RTYPE_FCC | 6}, \
2510 {"$fcc7", RTYPE_FCC | 7}
2512 #define COPROC_CONDITION_CODE_NAMES \
2513 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2514 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2515 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2516 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2517 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2518 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2519 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2520 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2522 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2523 {"$a4", RTYPE_GP | 8}, \
2524 {"$a5", RTYPE_GP | 9}, \
2525 {"$a6", RTYPE_GP | 10}, \
2526 {"$a7", RTYPE_GP | 11}, \
2527 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2528 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2529 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2530 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2531 {"$t0", RTYPE_GP | 12}, \
2532 {"$t1", RTYPE_GP | 13}, \
2533 {"$t2", RTYPE_GP | 14}, \
2534 {"$t3", RTYPE_GP | 15}
2536 #define O32_SYMBOLIC_REGISTER_NAMES \
2537 {"$t0", RTYPE_GP | 8}, \
2538 {"$t1", RTYPE_GP | 9}, \
2539 {"$t2", RTYPE_GP | 10}, \
2540 {"$t3", RTYPE_GP | 11}, \
2541 {"$t4", RTYPE_GP | 12}, \
2542 {"$t5", RTYPE_GP | 13}, \
2543 {"$t6", RTYPE_GP | 14}, \
2544 {"$t7", RTYPE_GP | 15}, \
2545 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2546 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2547 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2548 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2550 /* Remaining symbolic register names */
2551 #define SYMBOLIC_REGISTER_NAMES \
2552 {"$zero", RTYPE_GP | 0}, \
2553 {"$at", RTYPE_GP | 1}, \
2554 {"$AT", RTYPE_GP | 1}, \
2555 {"$v0", RTYPE_GP | 2}, \
2556 {"$v1", RTYPE_GP | 3}, \
2557 {"$a0", RTYPE_GP | 4}, \
2558 {"$a1", RTYPE_GP | 5}, \
2559 {"$a2", RTYPE_GP | 6}, \
2560 {"$a3", RTYPE_GP | 7}, \
2561 {"$s0", RTYPE_GP | 16}, \
2562 {"$s1", RTYPE_GP | 17}, \
2563 {"$s2", RTYPE_GP | 18}, \
2564 {"$s3", RTYPE_GP | 19}, \
2565 {"$s4", RTYPE_GP | 20}, \
2566 {"$s5", RTYPE_GP | 21}, \
2567 {"$s6", RTYPE_GP | 22}, \
2568 {"$s7", RTYPE_GP | 23}, \
2569 {"$t8", RTYPE_GP | 24}, \
2570 {"$t9", RTYPE_GP | 25}, \
2571 {"$k0", RTYPE_GP | 26}, \
2572 {"$kt0", RTYPE_GP | 26}, \
2573 {"$k1", RTYPE_GP | 27}, \
2574 {"$kt1", RTYPE_GP | 27}, \
2575 {"$gp", RTYPE_GP | 28}, \
2576 {"$sp", RTYPE_GP | 29}, \
2577 {"$s8", RTYPE_GP | 30}, \
2578 {"$fp", RTYPE_GP | 30}, \
2579 {"$ra", RTYPE_GP | 31}
2581 #define MIPS16_SPECIAL_REGISTER_NAMES \
2582 {"$pc", RTYPE_PC | 0}
2584 #define MDMX_VECTOR_REGISTER_NAMES \
2585 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2586 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2587 {"$v2", RTYPE_VEC | 2}, \
2588 {"$v3", RTYPE_VEC | 3}, \
2589 {"$v4", RTYPE_VEC | 4}, \
2590 {"$v5", RTYPE_VEC | 5}, \
2591 {"$v6", RTYPE_VEC | 6}, \
2592 {"$v7", RTYPE_VEC | 7}, \
2593 {"$v8", RTYPE_VEC | 8}, \
2594 {"$v9", RTYPE_VEC | 9}, \
2595 {"$v10", RTYPE_VEC | 10}, \
2596 {"$v11", RTYPE_VEC | 11}, \
2597 {"$v12", RTYPE_VEC | 12}, \
2598 {"$v13", RTYPE_VEC | 13}, \
2599 {"$v14", RTYPE_VEC | 14}, \
2600 {"$v15", RTYPE_VEC | 15}, \
2601 {"$v16", RTYPE_VEC | 16}, \
2602 {"$v17", RTYPE_VEC | 17}, \
2603 {"$v18", RTYPE_VEC | 18}, \
2604 {"$v19", RTYPE_VEC | 19}, \
2605 {"$v20", RTYPE_VEC | 20}, \
2606 {"$v21", RTYPE_VEC | 21}, \
2607 {"$v22", RTYPE_VEC | 22}, \
2608 {"$v23", RTYPE_VEC | 23}, \
2609 {"$v24", RTYPE_VEC | 24}, \
2610 {"$v25", RTYPE_VEC | 25}, \
2611 {"$v26", RTYPE_VEC | 26}, \
2612 {"$v27", RTYPE_VEC | 27}, \
2613 {"$v28", RTYPE_VEC | 28}, \
2614 {"$v29", RTYPE_VEC | 29}, \
2615 {"$v30", RTYPE_VEC | 30}, \
2616 {"$v31", RTYPE_VEC | 31}
2618 #define R5900_I_NAMES \
2619 {"$I", RTYPE_R5900_I | 0}
2621 #define R5900_Q_NAMES \
2622 {"$Q", RTYPE_R5900_Q | 0}
2624 #define R5900_R_NAMES \
2625 {"$R", RTYPE_R5900_R | 0}
2627 #define R5900_ACC_NAMES \
2628 {"$ACC", RTYPE_R5900_ACC | 0 }
2630 #define MIPS_DSP_ACCUMULATOR_NAMES \
2631 {"$ac0", RTYPE_ACC | 0}, \
2632 {"$ac1", RTYPE_ACC | 1}, \
2633 {"$ac2", RTYPE_ACC | 2}, \
2634 {"$ac3", RTYPE_ACC | 3}
2636 static const struct regname reg_names
[] = {
2637 GENERIC_REGISTER_NUMBERS
,
2639 FPU_CONDITION_CODE_NAMES
,
2640 COPROC_CONDITION_CODE_NAMES
,
2642 /* The $txx registers depends on the abi,
2643 these will be added later into the symbol table from
2644 one of the tables below once mips_abi is set after
2645 parsing of arguments from the command line. */
2646 SYMBOLIC_REGISTER_NAMES
,
2648 MIPS16_SPECIAL_REGISTER_NAMES
,
2649 MDMX_VECTOR_REGISTER_NAMES
,
2654 MIPS_DSP_ACCUMULATOR_NAMES
,
2658 static const struct regname reg_names_o32
[] = {
2659 O32_SYMBOLIC_REGISTER_NAMES
,
2663 static const struct regname reg_names_n32n64
[] = {
2664 N32N64_SYMBOLIC_REGISTER_NAMES
,
2668 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2669 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2670 of these register symbols, return the associated vector register,
2671 otherwise return SYMVAL itself. */
2674 mips_prefer_vec_regno (unsigned int symval
)
2676 if ((symval
& -2) == (RTYPE_GP
| 2))
2677 return RTYPE_VEC
| (symval
& 1);
2681 /* Return true if string [S, E) is a valid register name, storing its
2682 symbol value in *SYMVAL_PTR if so. */
2685 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2690 /* Terminate name. */
2694 /* Look up the name. */
2695 symbol
= symbol_find (s
);
2698 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2701 *symval_ptr
= S_GET_VALUE (symbol
);
2705 /* Return true if the string at *SPTR is a valid register name. Allow it
2706 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2709 When returning true, move *SPTR past the register, store the
2710 register's symbol value in *SYMVAL_PTR and the channel mask in
2711 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2712 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2713 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2716 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2717 unsigned int *channels_ptr
)
2721 unsigned int channels
, symval
, bit
;
2723 /* Find end of name. */
2725 if (is_name_beginner (*e
))
2727 while (is_part_of_name (*e
))
2731 if (!mips_parse_register_1 (s
, e
, &symval
))
2736 /* Eat characters from the end of the string that are valid
2737 channel suffixes. The preceding register must be $ACC or
2738 end with a digit, so there is no ambiguity. */
2741 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2742 if (m
> s
&& m
[-1] == *q
)
2749 || !mips_parse_register_1 (s
, m
, &symval
)
2750 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2755 *symval_ptr
= symval
;
2757 *channels_ptr
= channels
;
2761 /* Check if SPTR points at a valid register specifier according to TYPES.
2762 If so, then return 1, advance S to consume the specifier and store
2763 the register's number in REGNOP, otherwise return 0. */
2766 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2770 if (mips_parse_register (s
, ®no
, NULL
))
2772 if (types
& RTYPE_VEC
)
2773 regno
= mips_prefer_vec_regno (regno
);
2782 as_warn (_("unrecognized register name `%s'"), *s
);
2787 return regno
<= RNUM_MASK
;
2790 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2791 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2794 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2799 for (i
= 0; i
< 4; i
++)
2800 if (*s
== "xyzw"[i
])
2802 *channels
|= 1 << (3 - i
);
2808 /* Token types for parsed operand lists. */
2809 enum mips_operand_token_type
{
2810 /* A plain register, e.g. $f2. */
2813 /* A 4-bit XYZW channel mask. */
2816 /* A constant vector index, e.g. [1]. */
2819 /* A register vector index, e.g. [$2]. */
2822 /* A continuous range of registers, e.g. $s0-$s4. */
2825 /* A (possibly relocated) expression. */
2828 /* A floating-point value. */
2831 /* A single character. This can be '(', ')' or ',', but '(' only appears
2835 /* A doubled character, either "--" or "++". */
2838 /* The end of the operand list. */
2842 /* A parsed operand token. */
2843 struct mips_operand_token
2845 /* The type of token. */
2846 enum mips_operand_token_type type
;
2849 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
2852 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2853 unsigned int channels
;
2855 /* The integer value of an OT_INTEGER_INDEX. */
2858 /* The two register symbol values involved in an OT_REG_RANGE. */
2860 unsigned int regno1
;
2861 unsigned int regno2
;
2864 /* The value of an OT_INTEGER. The value is represented as an
2865 expression and the relocation operators that were applied to
2866 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2867 relocation operators were used. */
2870 bfd_reloc_code_real_type relocs
[3];
2873 /* The binary data for an OT_FLOAT constant, and the number of bytes
2876 unsigned char data
[8];
2880 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2885 /* An obstack used to construct lists of mips_operand_tokens. */
2886 static struct obstack mips_operand_tokens
;
2888 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2891 mips_add_token (struct mips_operand_token
*token
,
2892 enum mips_operand_token_type type
)
2895 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2898 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2899 and OT_REG tokens for them if so, and return a pointer to the first
2900 unconsumed character. Return null otherwise. */
2903 mips_parse_base_start (char *s
)
2905 struct mips_operand_token token
;
2906 unsigned int regno
, channels
;
2907 bfd_boolean decrement_p
;
2913 SKIP_SPACE_TABS (s
);
2915 /* Only match "--" as part of a base expression. In other contexts "--X"
2916 is a double negative. */
2917 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2921 SKIP_SPACE_TABS (s
);
2924 /* Allow a channel specifier because that leads to better error messages
2925 than treating something like "$vf0x++" as an expression. */
2926 if (!mips_parse_register (&s
, ®no
, &channels
))
2930 mips_add_token (&token
, OT_CHAR
);
2935 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2938 token
.u
.regno
= regno
;
2939 mips_add_token (&token
, OT_REG
);
2943 token
.u
.channels
= channels
;
2944 mips_add_token (&token
, OT_CHANNELS
);
2947 /* For consistency, only match "++" as part of base expressions too. */
2948 SKIP_SPACE_TABS (s
);
2949 if (s
[0] == '+' && s
[1] == '+')
2953 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2959 /* Parse one or more tokens from S. Return a pointer to the first
2960 unconsumed character on success. Return null if an error was found
2961 and store the error text in insn_error. FLOAT_FORMAT is as for
2962 mips_parse_arguments. */
2965 mips_parse_argument_token (char *s
, char float_format
)
2967 char *end
, *save_in
, *err
;
2968 unsigned int regno1
, regno2
, channels
;
2969 struct mips_operand_token token
;
2971 /* First look for "($reg", since we want to treat that as an
2972 OT_CHAR and OT_REG rather than an expression. */
2973 end
= mips_parse_base_start (s
);
2977 /* Handle other characters that end up as OT_CHARs. */
2978 if (*s
== ')' || *s
== ',')
2981 mips_add_token (&token
, OT_CHAR
);
2986 /* Handle tokens that start with a register. */
2987 if (mips_parse_register (&s
, ®no1
, &channels
))
2991 /* A register and a VU0 channel suffix. */
2992 token
.u
.regno
= regno1
;
2993 mips_add_token (&token
, OT_REG
);
2995 token
.u
.channels
= channels
;
2996 mips_add_token (&token
, OT_CHANNELS
);
3000 SKIP_SPACE_TABS (s
);
3003 /* A register range. */
3005 SKIP_SPACE_TABS (s
);
3006 if (!mips_parse_register (&s
, ®no2
, NULL
))
3008 set_insn_error (0, _("invalid register range"));
3012 token
.u
.reg_range
.regno1
= regno1
;
3013 token
.u
.reg_range
.regno2
= regno2
;
3014 mips_add_token (&token
, OT_REG_RANGE
);
3018 /* Add the register itself. */
3019 token
.u
.regno
= regno1
;
3020 mips_add_token (&token
, OT_REG
);
3022 /* Check for a vector index. */
3026 SKIP_SPACE_TABS (s
);
3027 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3028 mips_add_token (&token
, OT_REG_INDEX
);
3031 expressionS element
;
3033 my_getExpression (&element
, s
);
3034 if (element
.X_op
!= O_constant
)
3036 set_insn_error (0, _("vector element must be constant"));
3040 token
.u
.index
= element
.X_add_number
;
3041 mips_add_token (&token
, OT_INTEGER_INDEX
);
3043 SKIP_SPACE_TABS (s
);
3046 set_insn_error (0, _("missing `]'"));
3056 /* First try to treat expressions as floats. */
3057 save_in
= input_line_pointer
;
3058 input_line_pointer
= s
;
3059 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3060 &token
.u
.flt
.length
);
3061 end
= input_line_pointer
;
3062 input_line_pointer
= save_in
;
3065 set_insn_error (0, err
);
3070 mips_add_token (&token
, OT_FLOAT
);
3075 /* Treat everything else as an integer expression. */
3076 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3077 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3078 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3079 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3081 mips_add_token (&token
, OT_INTEGER
);
3085 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3086 if expressions should be treated as 32-bit floating-point constants,
3087 'd' if they should be treated as 64-bit floating-point constants,
3088 or 0 if they should be treated as integer expressions (the usual case).
3090 Return a list of tokens on success, otherwise return 0. The caller
3091 must obstack_free the list after use. */
3093 static struct mips_operand_token
*
3094 mips_parse_arguments (char *s
, char float_format
)
3096 struct mips_operand_token token
;
3098 SKIP_SPACE_TABS (s
);
3101 s
= mips_parse_argument_token (s
, float_format
);
3104 obstack_free (&mips_operand_tokens
,
3105 obstack_finish (&mips_operand_tokens
));
3108 SKIP_SPACE_TABS (s
);
3110 mips_add_token (&token
, OT_END
);
3111 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3114 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3115 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3118 is_opcode_valid (const struct mips_opcode
*mo
)
3120 int isa
= mips_opts
.isa
;
3121 int ase
= mips_opts
.ase
;
3125 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3126 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3127 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3128 ase
|= mips_ases
[i
].flags64
;
3130 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3133 /* Check whether the instruction or macro requires single-precision or
3134 double-precision floating-point support. Note that this information is
3135 stored differently in the opcode table for insns and macros. */
3136 if (mo
->pinfo
== INSN_MACRO
)
3138 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3139 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3143 fp_s
= mo
->pinfo
& FP_S
;
3144 fp_d
= mo
->pinfo
& FP_D
;
3147 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3150 if (fp_s
&& mips_opts
.soft_float
)
3156 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3157 selected ISA and architecture. */
3160 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3162 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3165 /* Return TRUE if the size of the microMIPS opcode MO matches one
3166 explicitly requested. Always TRUE in the standard MIPS mode. */
3169 is_size_valid (const struct mips_opcode
*mo
)
3171 if (!mips_opts
.micromips
)
3174 if (mips_opts
.insn32
)
3176 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3178 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3181 if (!forced_insn_length
)
3183 if (mo
->pinfo
== INSN_MACRO
)
3185 return forced_insn_length
== micromips_insn_length (mo
);
3188 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3189 of the preceding instruction. Always TRUE in the standard MIPS mode.
3191 We don't accept macros in 16-bit delay slots to avoid a case where
3192 a macro expansion fails because it relies on a preceding 32-bit real
3193 instruction to have matched and does not handle the operands correctly.
3194 The only macros that may expand to 16-bit instructions are JAL that
3195 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3196 and BGT (that likewise cannot be placed in a delay slot) that decay to
3197 a NOP. In all these cases the macros precede any corresponding real
3198 instruction definitions in the opcode table, so they will match in the
3199 second pass where the size of the delay slot is ignored and therefore
3200 produce correct code. */
3203 is_delay_slot_valid (const struct mips_opcode
*mo
)
3205 if (!mips_opts
.micromips
)
3208 if (mo
->pinfo
== INSN_MACRO
)
3209 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3210 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3211 && micromips_insn_length (mo
) != 4)
3213 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3214 && micromips_insn_length (mo
) != 2)
3220 /* For consistency checking, verify that all bits of OPCODE are specified
3221 either by the match/mask part of the instruction definition, or by the
3222 operand list. Also build up a list of operands in OPERANDS.
3224 INSN_BITS says which bits of the instruction are significant.
3225 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3226 provides the mips_operand description of each operand. DECODE_OPERAND
3227 is null for MIPS16 instructions. */
3230 validate_mips_insn (const struct mips_opcode
*opcode
,
3231 unsigned long insn_bits
,
3232 const struct mips_operand
*(*decode_operand
) (const char *),
3233 struct mips_operand_array
*operands
)
3236 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3237 const struct mips_operand
*operand
;
3239 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3240 if ((mask
& opcode
->match
) != opcode
->match
)
3242 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3243 opcode
->name
, opcode
->args
);
3248 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3249 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3250 for (s
= opcode
->args
; *s
; ++s
)
3263 if (!decode_operand
)
3264 operand
= decode_mips16_operand (*s
, FALSE
);
3266 operand
= decode_operand (s
);
3267 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3269 as_bad (_("internal: unknown operand type: %s %s"),
3270 opcode
->name
, opcode
->args
);
3273 gas_assert (opno
< MAX_OPERANDS
);
3274 operands
->operand
[opno
] = operand
;
3275 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3277 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3278 if (operand
->type
== OP_MDMX_IMM_REG
)
3279 /* Bit 5 is the format selector (OB vs QH). The opcode table
3280 has separate entries for each format. */
3281 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3282 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3283 used_bits
&= ~(mask
& 0x700);
3285 /* Skip prefix characters. */
3286 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3291 doubled
= used_bits
& mask
& insn_bits
;
3294 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3295 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3299 undefined
= ~used_bits
& insn_bits
;
3300 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3302 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3303 undefined
, opcode
->name
, opcode
->args
);
3306 used_bits
&= ~insn_bits
;
3309 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3310 used_bits
, opcode
->name
, opcode
->args
);
3316 /* The MIPS16 version of validate_mips_insn. */
3319 validate_mips16_insn (const struct mips_opcode
*opcode
,
3320 struct mips_operand_array
*operands
)
3322 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3324 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3325 instruction. Use TMP to describe the full instruction. */
3326 struct mips_opcode tmp
;
3331 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3333 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3336 /* The microMIPS version of validate_mips_insn. */
3339 validate_micromips_insn (const struct mips_opcode
*opc
,
3340 struct mips_operand_array
*operands
)
3342 unsigned long insn_bits
;
3343 unsigned long major
;
3344 unsigned int length
;
3346 if (opc
->pinfo
== INSN_MACRO
)
3347 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3350 length
= micromips_insn_length (opc
);
3351 if (length
!= 2 && length
!= 4)
3353 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3354 "%s %s"), length
, opc
->name
, opc
->args
);
3357 major
= opc
->match
>> (10 + 8 * (length
- 2));
3358 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3359 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3361 as_bad (_("internal error: bad microMIPS opcode "
3362 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3366 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3367 insn_bits
= 1 << 4 * length
;
3368 insn_bits
<<= 4 * length
;
3370 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3374 /* This function is called once, at assembler startup time. It should set up
3375 all the tables, etc. that the MD part of the assembler will need. */
3380 const char *retval
= NULL
;
3384 if (mips_pic
!= NO_PIC
)
3386 if (g_switch_seen
&& g_switch_value
!= 0)
3387 as_bad (_("-G may not be used in position-independent code"));
3391 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3392 as_warn (_("could not set architecture and machine"));
3394 op_hash
= hash_new ();
3396 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3397 for (i
= 0; i
< NUMOPCODES
;)
3399 const char *name
= mips_opcodes
[i
].name
;
3401 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3404 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3405 mips_opcodes
[i
].name
, retval
);
3406 /* Probably a memory allocation problem? Give up now. */
3407 as_fatal (_("broken assembler, no assembly attempted"));
3411 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3412 decode_mips_operand
, &mips_operands
[i
]))
3414 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3416 create_insn (&nop_insn
, mips_opcodes
+ i
);
3417 if (mips_fix_loongson2f_nop
)
3418 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3419 nop_insn
.fixed_p
= 1;
3423 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3426 mips16_op_hash
= hash_new ();
3427 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3428 bfd_mips16_num_opcodes
);
3431 while (i
< bfd_mips16_num_opcodes
)
3433 const char *name
= mips16_opcodes
[i
].name
;
3435 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3437 as_fatal (_("internal: can't hash `%s': %s"),
3438 mips16_opcodes
[i
].name
, retval
);
3441 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3443 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3445 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3446 mips16_nop_insn
.fixed_p
= 1;
3450 while (i
< bfd_mips16_num_opcodes
3451 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3454 micromips_op_hash
= hash_new ();
3455 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3456 bfd_micromips_num_opcodes
);
3459 while (i
< bfd_micromips_num_opcodes
)
3461 const char *name
= micromips_opcodes
[i
].name
;
3463 retval
= hash_insert (micromips_op_hash
, name
,
3464 (void *) µmips_opcodes
[i
]);
3466 as_fatal (_("internal: can't hash `%s': %s"),
3467 micromips_opcodes
[i
].name
, retval
);
3470 struct mips_cl_insn
*micromips_nop_insn
;
3472 if (!validate_micromips_insn (µmips_opcodes
[i
],
3473 µmips_operands
[i
]))
3476 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3478 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3479 micromips_nop_insn
= µmips_nop16_insn
;
3480 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3481 micromips_nop_insn
= µmips_nop32_insn
;
3485 if (micromips_nop_insn
->insn_mo
== NULL
3486 && strcmp (name
, "nop") == 0)
3488 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3489 micromips_nop_insn
->fixed_p
= 1;
3493 while (++i
< bfd_micromips_num_opcodes
3494 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3498 as_fatal (_("broken assembler, no assembly attempted"));
3500 /* We add all the general register names to the symbol table. This
3501 helps us detect invalid uses of them. */
3502 for (i
= 0; reg_names
[i
].name
; i
++)
3503 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3504 reg_names
[i
].num
, /* & RNUM_MASK, */
3505 &zero_address_frag
));
3507 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3508 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3509 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3510 &zero_address_frag
));
3512 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3513 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3514 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3515 &zero_address_frag
));
3517 for (i
= 0; i
< 32; i
++)
3521 /* R5900 VU0 floating-point register. */
3522 regname
[sizeof (rename
) - 1] = 0;
3523 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3524 symbol_table_insert (symbol_new (regname
, reg_section
,
3525 RTYPE_VF
| i
, &zero_address_frag
));
3527 /* R5900 VU0 integer register. */
3528 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3529 symbol_table_insert (symbol_new (regname
, reg_section
,
3530 RTYPE_VI
| i
, &zero_address_frag
));
3533 snprintf (regname
, sizeof (regname
) - 1, "$w%d", i
);
3534 symbol_table_insert (symbol_new (regname
, reg_section
,
3535 RTYPE_MSA
| i
, &zero_address_frag
));
3538 obstack_init (&mips_operand_tokens
);
3540 mips_no_prev_insn ();
3543 mips_cprmask
[0] = 0;
3544 mips_cprmask
[1] = 0;
3545 mips_cprmask
[2] = 0;
3546 mips_cprmask
[3] = 0;
3548 /* set the default alignment for the text section (2**2) */
3549 record_alignment (text_section
, 2);
3551 bfd_set_gp_size (stdoutput
, g_switch_value
);
3553 /* On a native system other than VxWorks, sections must be aligned
3554 to 16 byte boundaries. When configured for an embedded ELF
3555 target, we don't bother. */
3556 if (strncmp (TARGET_OS
, "elf", 3) != 0
3557 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3559 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3560 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3561 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3564 /* Create a .reginfo section for register masks and a .mdebug
3565 section for debugging information. */
3573 subseg
= now_subseg
;
3575 /* The ABI says this section should be loaded so that the
3576 running program can access it. However, we don't load it
3577 if we are configured for an embedded target */
3578 flags
= SEC_READONLY
| SEC_DATA
;
3579 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3580 flags
|= SEC_ALLOC
| SEC_LOAD
;
3582 if (mips_abi
!= N64_ABI
)
3584 sec
= subseg_new (".reginfo", (subsegT
) 0);
3586 bfd_set_section_flags (stdoutput
, sec
, flags
);
3587 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3589 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3593 /* The 64-bit ABI uses a .MIPS.options section rather than
3594 .reginfo section. */
3595 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3596 bfd_set_section_flags (stdoutput
, sec
, flags
);
3597 bfd_set_section_alignment (stdoutput
, sec
, 3);
3599 /* Set up the option header. */
3601 Elf_Internal_Options opthdr
;
3604 opthdr
.kind
= ODK_REGINFO
;
3605 opthdr
.size
= (sizeof (Elf_External_Options
)
3606 + sizeof (Elf64_External_RegInfo
));
3609 f
= frag_more (sizeof (Elf_External_Options
));
3610 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3611 (Elf_External_Options
*) f
);
3613 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3617 if (ECOFF_DEBUGGING
)
3619 sec
= subseg_new (".mdebug", (subsegT
) 0);
3620 (void) bfd_set_section_flags (stdoutput
, sec
,
3621 SEC_HAS_CONTENTS
| SEC_READONLY
);
3622 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3624 else if (mips_flag_pdr
)
3626 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3627 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3628 SEC_READONLY
| SEC_RELOC
3630 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3633 subseg_set (seg
, subseg
);
3636 if (! ECOFF_DEBUGGING
)
3639 if (mips_fix_vr4120
)
3640 init_vr4120_conflicts ();
3646 mips_emit_delays ();
3647 if (! ECOFF_DEBUGGING
)
3652 md_assemble (char *str
)
3654 struct mips_cl_insn insn
;
3655 bfd_reloc_code_real_type unused_reloc
[3]
3656 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3658 imm_expr
.X_op
= O_absent
;
3659 offset_expr
.X_op
= O_absent
;
3660 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3661 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3662 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3664 mips_mark_labels ();
3665 mips_assembling_insn
= TRUE
;
3666 clear_insn_error ();
3668 if (mips_opts
.mips16
)
3669 mips16_ip (str
, &insn
);
3672 mips_ip (str
, &insn
);
3673 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3674 str
, insn
.insn_opcode
));
3678 report_insn_error (str
);
3679 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3682 if (mips_opts
.mips16
)
3683 mips16_macro (&insn
);
3690 if (offset_expr
.X_op
!= O_absent
)
3691 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3693 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3696 mips_assembling_insn
= FALSE
;
3699 /* Convenience functions for abstracting away the differences between
3700 MIPS16 and non-MIPS16 relocations. */
3702 static inline bfd_boolean
3703 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3707 case BFD_RELOC_MIPS16_JMP
:
3708 case BFD_RELOC_MIPS16_GPREL
:
3709 case BFD_RELOC_MIPS16_GOT16
:
3710 case BFD_RELOC_MIPS16_CALL16
:
3711 case BFD_RELOC_MIPS16_HI16_S
:
3712 case BFD_RELOC_MIPS16_HI16
:
3713 case BFD_RELOC_MIPS16_LO16
:
3721 static inline bfd_boolean
3722 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3726 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3727 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3728 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3729 case BFD_RELOC_MICROMIPS_GPREL16
:
3730 case BFD_RELOC_MICROMIPS_JMP
:
3731 case BFD_RELOC_MICROMIPS_HI16
:
3732 case BFD_RELOC_MICROMIPS_HI16_S
:
3733 case BFD_RELOC_MICROMIPS_LO16
:
3734 case BFD_RELOC_MICROMIPS_LITERAL
:
3735 case BFD_RELOC_MICROMIPS_GOT16
:
3736 case BFD_RELOC_MICROMIPS_CALL16
:
3737 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3738 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3739 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3740 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3741 case BFD_RELOC_MICROMIPS_SUB
:
3742 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3743 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3744 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3745 case BFD_RELOC_MICROMIPS_HIGHEST
:
3746 case BFD_RELOC_MICROMIPS_HIGHER
:
3747 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3748 case BFD_RELOC_MICROMIPS_JALR
:
3756 static inline bfd_boolean
3757 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3759 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3762 static inline bfd_boolean
3763 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3765 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3766 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3769 static inline bfd_boolean
3770 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3772 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3773 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3776 static inline bfd_boolean
3777 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3779 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3780 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3783 static inline bfd_boolean
3784 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3786 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3789 static inline bfd_boolean
3790 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3792 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3793 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3796 /* Return true if RELOC is a PC-relative relocation that does not have
3797 full address range. */
3799 static inline bfd_boolean
3800 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3804 case BFD_RELOC_16_PCREL_S2
:
3805 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3806 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3807 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3810 case BFD_RELOC_32_PCREL
:
3811 return HAVE_64BIT_ADDRESSES
;
3818 /* Return true if the given relocation might need a matching %lo().
3819 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3820 need a matching %lo() when applied to local symbols. */
3822 static inline bfd_boolean
3823 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3825 return (HAVE_IN_PLACE_ADDENDS
3826 && (hi16_reloc_p (reloc
)
3827 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3828 all GOT16 relocations evaluate to "G". */
3829 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3832 /* Return the type of %lo() reloc needed by RELOC, given that
3833 reloc_needs_lo_p. */
3835 static inline bfd_reloc_code_real_type
3836 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3838 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3839 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3843 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3846 static inline bfd_boolean
3847 fixup_has_matching_lo_p (fixS
*fixp
)
3849 return (fixp
->fx_next
!= NULL
3850 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3851 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3852 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3855 /* Move all labels in LABELS to the current insertion point. TEXT_P
3856 says whether the labels refer to text or data. */
3859 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3861 struct insn_label_list
*l
;
3864 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3866 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3867 symbol_set_frag (l
->label
, frag_now
);
3868 val
= (valueT
) frag_now_fix ();
3869 /* MIPS16/microMIPS text labels are stored as odd. */
3870 if (text_p
&& HAVE_CODE_COMPRESSION
)
3872 S_SET_VALUE (l
->label
, val
);
3876 /* Move all labels in insn_labels to the current insertion point
3877 and treat them as text labels. */
3880 mips_move_text_labels (void)
3882 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3886 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3888 bfd_boolean linkonce
= FALSE
;
3889 segT symseg
= S_GET_SEGMENT (sym
);
3891 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3893 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3895 /* The GNU toolchain uses an extension for ELF: a section
3896 beginning with the magic string .gnu.linkonce is a
3897 linkonce section. */
3898 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3899 sizeof ".gnu.linkonce" - 1) == 0)
3905 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3906 linker to handle them specially, such as generating jalx instructions
3907 when needed. We also make them odd for the duration of the assembly,
3908 in order to generate the right sort of code. We will make them even
3909 in the adjust_symtab routine, while leaving them marked. This is
3910 convenient for the debugger and the disassembler. The linker knows
3911 to make them odd again. */
3914 mips_compressed_mark_label (symbolS
*label
)
3916 gas_assert (HAVE_CODE_COMPRESSION
);
3918 if (mips_opts
.mips16
)
3919 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3921 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3922 if ((S_GET_VALUE (label
) & 1) == 0
3923 /* Don't adjust the address if the label is global or weak, or
3924 in a link-once section, since we'll be emitting symbol reloc
3925 references to it which will be patched up by the linker, and
3926 the final value of the symbol may or may not be MIPS16/microMIPS. */
3927 && !S_IS_WEAK (label
)
3928 && !S_IS_EXTERNAL (label
)
3929 && !s_is_linkonce (label
, now_seg
))
3930 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3933 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3936 mips_compressed_mark_labels (void)
3938 struct insn_label_list
*l
;
3940 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3941 mips_compressed_mark_label (l
->label
);
3944 /* End the current frag. Make it a variant frag and record the
3948 relax_close_frag (void)
3950 mips_macro_warning
.first_frag
= frag_now
;
3951 frag_var (rs_machine_dependent
, 0, 0,
3952 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3953 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3955 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3956 mips_relax
.first_fixup
= 0;
3959 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3960 See the comment above RELAX_ENCODE for more details. */
3963 relax_start (symbolS
*symbol
)
3965 gas_assert (mips_relax
.sequence
== 0);
3966 mips_relax
.sequence
= 1;
3967 mips_relax
.symbol
= symbol
;
3970 /* Start generating the second version of a relaxable sequence.
3971 See the comment above RELAX_ENCODE for more details. */
3976 gas_assert (mips_relax
.sequence
== 1);
3977 mips_relax
.sequence
= 2;
3980 /* End the current relaxable sequence. */
3985 gas_assert (mips_relax
.sequence
== 2);
3986 relax_close_frag ();
3987 mips_relax
.sequence
= 0;
3990 /* Return true if IP is a delayed branch or jump. */
3992 static inline bfd_boolean
3993 delayed_branch_p (const struct mips_cl_insn
*ip
)
3995 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3996 | INSN_COND_BRANCH_DELAY
3997 | INSN_COND_BRANCH_LIKELY
)) != 0;
4000 /* Return true if IP is a compact branch or jump. */
4002 static inline bfd_boolean
4003 compact_branch_p (const struct mips_cl_insn
*ip
)
4005 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4006 | INSN2_COND_BRANCH
)) != 0;
4009 /* Return true if IP is an unconditional branch or jump. */
4011 static inline bfd_boolean
4012 uncond_branch_p (const struct mips_cl_insn
*ip
)
4014 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4015 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4018 /* Return true if IP is a branch-likely instruction. */
4020 static inline bfd_boolean
4021 branch_likely_p (const struct mips_cl_insn
*ip
)
4023 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4026 /* Return the type of nop that should be used to fill the delay slot
4027 of delayed branch IP. */
4029 static struct mips_cl_insn
*
4030 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4032 if (mips_opts
.micromips
4033 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4034 return µmips_nop32_insn
;
4038 /* Return a mask that has bit N set if OPCODE reads the register(s)
4042 insn_read_mask (const struct mips_opcode
*opcode
)
4044 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4047 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4051 insn_write_mask (const struct mips_opcode
*opcode
)
4053 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4056 /* Return a mask of the registers specified by operand OPERAND of INSN.
4057 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4061 operand_reg_mask (const struct mips_cl_insn
*insn
,
4062 const struct mips_operand
*operand
,
4063 unsigned int type_mask
)
4065 unsigned int uval
, vsel
;
4067 switch (operand
->type
)
4074 case OP_ADDIUSP_INT
:
4075 case OP_ENTRY_EXIT_LIST
:
4076 case OP_REPEAT_DEST_REG
:
4077 case OP_REPEAT_PREV_REG
:
4080 case OP_VU0_MATCH_SUFFIX
:
4085 case OP_OPTIONAL_REG
:
4087 const struct mips_reg_operand
*reg_op
;
4089 reg_op
= (const struct mips_reg_operand
*) operand
;
4090 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4092 uval
= insn_extract_operand (insn
, operand
);
4093 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4098 const struct mips_reg_pair_operand
*pair_op
;
4100 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4101 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4103 uval
= insn_extract_operand (insn
, operand
);
4104 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4107 case OP_CLO_CLZ_DEST
:
4108 if (!(type_mask
& (1 << OP_REG_GP
)))
4110 uval
= insn_extract_operand (insn
, operand
);
4111 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4113 case OP_LWM_SWM_LIST
:
4116 case OP_SAVE_RESTORE_LIST
:
4119 case OP_MDMX_IMM_REG
:
4120 if (!(type_mask
& (1 << OP_REG_VEC
)))
4122 uval
= insn_extract_operand (insn
, operand
);
4124 if ((vsel
& 0x18) == 0x18)
4126 return 1 << (uval
& 31);
4129 if (!(type_mask
& (1 << OP_REG_GP
)))
4131 return 1 << insn_extract_operand (insn
, operand
);
4136 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4137 where bit N of OPNO_MASK is set if operand N should be included.
4138 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4142 insn_reg_mask (const struct mips_cl_insn
*insn
,
4143 unsigned int type_mask
, unsigned int opno_mask
)
4145 unsigned int opno
, reg_mask
;
4149 while (opno_mask
!= 0)
4152 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4159 /* Return the mask of core registers that IP reads. */
4162 gpr_read_mask (const struct mips_cl_insn
*ip
)
4164 unsigned long pinfo
, pinfo2
;
4167 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4168 pinfo
= ip
->insn_mo
->pinfo
;
4169 pinfo2
= ip
->insn_mo
->pinfo2
;
4170 if (pinfo
& INSN_UDI
)
4172 /* UDI instructions have traditionally been assumed to read RS
4174 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4175 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4177 if (pinfo
& INSN_READ_GPR_24
)
4179 if (pinfo2
& INSN2_READ_GPR_16
)
4181 if (pinfo2
& INSN2_READ_SP
)
4183 if (pinfo2
& INSN2_READ_GPR_31
)
4185 /* Don't include register 0. */
4189 /* Return the mask of core registers that IP writes. */
4192 gpr_write_mask (const struct mips_cl_insn
*ip
)
4194 unsigned long pinfo
, pinfo2
;
4197 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4198 pinfo
= ip
->insn_mo
->pinfo
;
4199 pinfo2
= ip
->insn_mo
->pinfo2
;
4200 if (pinfo
& INSN_WRITE_GPR_24
)
4202 if (pinfo
& INSN_WRITE_GPR_31
)
4204 if (pinfo
& INSN_UDI
)
4205 /* UDI instructions have traditionally been assumed to write to RD. */
4206 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4207 if (pinfo2
& INSN2_WRITE_SP
)
4209 /* Don't include register 0. */
4213 /* Return the mask of floating-point registers that IP reads. */
4216 fpr_read_mask (const struct mips_cl_insn
*ip
)
4218 unsigned long pinfo
;
4221 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4222 | (1 << OP_REG_MSA
)),
4223 insn_read_mask (ip
->insn_mo
));
4224 pinfo
= ip
->insn_mo
->pinfo
;
4225 /* Conservatively treat all operands to an FP_D instruction are doubles.
4226 (This is overly pessimistic for things like cvt.d.s.) */
4227 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4232 /* Return the mask of floating-point registers that IP writes. */
4235 fpr_write_mask (const struct mips_cl_insn
*ip
)
4237 unsigned long pinfo
;
4240 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4241 | (1 << OP_REG_MSA
)),
4242 insn_write_mask (ip
->insn_mo
));
4243 pinfo
= ip
->insn_mo
->pinfo
;
4244 /* Conservatively treat all operands to an FP_D instruction are doubles.
4245 (This is overly pessimistic for things like cvt.s.d.) */
4246 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4251 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4252 Check whether that is allowed. */
4255 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4257 const char *s
= insn
->name
;
4259 if (insn
->pinfo
== INSN_MACRO
)
4260 /* Let a macro pass, we'll catch it later when it is expanded. */
4263 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4265 /* Allow odd registers for single-precision ops. */
4266 switch (insn
->pinfo
& (FP_S
| FP_D
))
4277 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4278 s
= strchr (insn
->name
, '.');
4279 if (s
!= NULL
&& opnum
== 2)
4280 s
= strchr (s
+ 1, '.');
4281 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4284 /* Single-precision coprocessor loads and moves are OK too. */
4285 if ((insn
->pinfo
& FP_S
)
4286 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4287 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4293 /* Information about an instruction argument that we're trying to match. */
4294 struct mips_arg_info
4296 /* The instruction so far. */
4297 struct mips_cl_insn
*insn
;
4299 /* The first unconsumed operand token. */
4300 struct mips_operand_token
*token
;
4302 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4305 /* The 1-based argument number, for error reporting. This does not
4306 count elided optional registers, etc.. */
4309 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4310 unsigned int last_regno
;
4312 /* If the first operand was an OP_REG, this is the register that it
4313 specified, otherwise it is ILLEGAL_REG. */
4314 unsigned int dest_regno
;
4316 /* The value of the last OP_INT operand. Only used for OP_MSB,
4317 where it gives the lsb position. */
4318 unsigned int last_op_int
;
4320 /* If true, match routines should assume that no later instruction
4321 alternative matches and should therefore be as accomodating as
4322 possible. Match routines should not report errors if something
4323 is only invalid for !LAX_MATCH. */
4324 bfd_boolean lax_match
;
4326 /* True if a reference to the current AT register was seen. */
4327 bfd_boolean seen_at
;
4330 /* Record that the argument is out of range. */
4333 match_out_of_range (struct mips_arg_info
*arg
)
4335 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4338 /* Record that the argument isn't constant but needs to be. */
4341 match_not_constant (struct mips_arg_info
*arg
)
4343 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4347 /* Try to match an OT_CHAR token for character CH. Consume the token
4348 and return true on success, otherwise return false. */
4351 match_char (struct mips_arg_info
*arg
, char ch
)
4353 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4363 /* Try to get an expression from the next tokens in ARG. Consume the
4364 tokens and return true on success, storing the expression value in
4365 VALUE and relocation types in R. */
4368 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4369 bfd_reloc_code_real_type
*r
)
4371 /* If the next token is a '(' that was parsed as being part of a base
4372 expression, assume we have an elided offset. The later match will fail
4373 if this turns out to be wrong. */
4374 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4376 value
->X_op
= O_constant
;
4377 value
->X_add_number
= 0;
4378 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4382 /* Reject register-based expressions such as "0+$2" and "(($2))".
4383 For plain registers the default error seems more appropriate. */
4384 if (arg
->token
->type
== OT_INTEGER
4385 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4387 set_insn_error (arg
->argnum
, _("register value used as expression"));
4391 if (arg
->token
->type
== OT_INTEGER
)
4393 *value
= arg
->token
->u
.integer
.value
;
4394 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4400 (arg
->argnum
, _("operand %d must be an immediate expression"),
4405 /* Try to get a constant expression from the next tokens in ARG. Consume
4406 the tokens and return return true on success, storing the constant value
4407 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4411 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4414 bfd_reloc_code_real_type r
[3];
4416 if (!match_expression (arg
, &ex
, r
))
4419 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4420 *value
= ex
.X_add_number
;
4423 match_not_constant (arg
);
4429 /* Return the RTYPE_* flags for a register operand of type TYPE that
4430 appears in instruction OPCODE. */
4433 convert_reg_type (const struct mips_opcode
*opcode
,
4434 enum mips_reg_operand_type type
)
4439 return RTYPE_NUM
| RTYPE_GP
;
4442 /* Allow vector register names for MDMX if the instruction is a 64-bit
4443 FPR load, store or move (including moves to and from GPRs). */
4444 if ((mips_opts
.ase
& ASE_MDMX
)
4445 && (opcode
->pinfo
& FP_D
)
4446 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4447 | INSN_COPROC_MEMORY_DELAY
4448 | INSN_LOAD_COPROC_DELAY
4450 | INSN_STORE_MEMORY
)))
4451 return RTYPE_FPU
| RTYPE_VEC
;
4455 if (opcode
->pinfo
& (FP_D
| FP_S
))
4456 return RTYPE_CCC
| RTYPE_FCC
;
4460 if (opcode
->membership
& INSN_5400
)
4462 return RTYPE_FPU
| RTYPE_VEC
;
4468 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4469 return RTYPE_NUM
| RTYPE_CP0
;
4476 return RTYPE_NUM
| RTYPE_VI
;
4479 return RTYPE_NUM
| RTYPE_VF
;
4481 case OP_REG_R5900_I
:
4482 return RTYPE_R5900_I
;
4484 case OP_REG_R5900_Q
:
4485 return RTYPE_R5900_Q
;
4487 case OP_REG_R5900_R
:
4488 return RTYPE_R5900_R
;
4490 case OP_REG_R5900_ACC
:
4491 return RTYPE_R5900_ACC
;
4496 case OP_REG_MSA_CTRL
:
4502 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4505 check_regno (struct mips_arg_info
*arg
,
4506 enum mips_reg_operand_type type
, unsigned int regno
)
4508 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4509 arg
->seen_at
= TRUE
;
4511 if (type
== OP_REG_FP
4514 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4515 as_warn (_("float register should be even, was %d"), regno
);
4517 if (type
== OP_REG_CCC
)
4522 name
= arg
->insn
->insn_mo
->name
;
4523 length
= strlen (name
);
4524 if ((regno
& 1) != 0
4525 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4526 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4527 as_warn (_("condition code register should be even for %s, was %d"),
4530 if ((regno
& 3) != 0
4531 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4532 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
4537 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4538 a register of type TYPE. Return true on success, storing the register
4539 number in *REGNO and warning about any dubious uses. */
4542 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4543 unsigned int symval
, unsigned int *regno
)
4545 if (type
== OP_REG_VEC
)
4546 symval
= mips_prefer_vec_regno (symval
);
4547 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4550 *regno
= symval
& RNUM_MASK
;
4551 check_regno (arg
, type
, *regno
);
4555 /* Try to interpret the next token in ARG as a register of type TYPE.
4556 Consume the token and return true on success, storing the register
4557 number in *REGNO. Return false on failure. */
4560 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4561 unsigned int *regno
)
4563 if (arg
->token
->type
== OT_REG
4564 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4572 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4573 Consume the token and return true on success, storing the register numbers
4574 in *REGNO1 and *REGNO2. Return false on failure. */
4577 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4578 unsigned int *regno1
, unsigned int *regno2
)
4580 if (match_reg (arg
, type
, regno1
))
4585 if (arg
->token
->type
== OT_REG_RANGE
4586 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4587 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4588 && *regno1
<= *regno2
)
4596 /* OP_INT matcher. */
4599 match_int_operand (struct mips_arg_info
*arg
,
4600 const struct mips_operand
*operand_base
)
4602 const struct mips_int_operand
*operand
;
4604 int min_val
, max_val
, factor
;
4607 operand
= (const struct mips_int_operand
*) operand_base
;
4608 factor
= 1 << operand
->shift
;
4609 min_val
= mips_int_operand_min (operand
);
4610 max_val
= mips_int_operand_max (operand
);
4612 if (operand_base
->lsb
== 0
4613 && operand_base
->size
== 16
4614 && operand
->shift
== 0
4615 && operand
->bias
== 0
4616 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4618 /* The operand can be relocated. */
4619 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4622 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4623 /* Relocation operators were used. Accept the arguent and
4624 leave the relocation value in offset_expr and offset_relocs
4625 for the caller to process. */
4628 if (offset_expr
.X_op
!= O_constant
)
4630 /* Accept non-constant operands if no later alternative matches,
4631 leaving it for the caller to process. */
4632 if (!arg
->lax_match
)
4634 offset_reloc
[0] = BFD_RELOC_LO16
;
4638 /* Clear the global state; we're going to install the operand
4640 sval
= offset_expr
.X_add_number
;
4641 offset_expr
.X_op
= O_absent
;
4643 /* For compatibility with older assemblers, we accept
4644 0x8000-0xffff as signed 16-bit numbers when only
4645 signed numbers are allowed. */
4648 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4649 if (!arg
->lax_match
&& sval
<= max_val
)
4655 if (!match_const_int (arg
, &sval
))
4659 arg
->last_op_int
= sval
;
4661 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
4663 match_out_of_range (arg
);
4667 uval
= (unsigned int) sval
>> operand
->shift
;
4668 uval
-= operand
->bias
;
4670 /* Handle -mfix-cn63xxp1. */
4672 && mips_fix_cn63xxp1
4673 && !mips_opts
.micromips
4674 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4689 /* The rest must be changed to 28. */
4694 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4698 /* OP_MAPPED_INT matcher. */
4701 match_mapped_int_operand (struct mips_arg_info
*arg
,
4702 const struct mips_operand
*operand_base
)
4704 const struct mips_mapped_int_operand
*operand
;
4705 unsigned int uval
, num_vals
;
4708 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4709 if (!match_const_int (arg
, &sval
))
4712 num_vals
= 1 << operand_base
->size
;
4713 for (uval
= 0; uval
< num_vals
; uval
++)
4714 if (operand
->int_map
[uval
] == sval
)
4716 if (uval
== num_vals
)
4718 match_out_of_range (arg
);
4722 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4726 /* OP_MSB matcher. */
4729 match_msb_operand (struct mips_arg_info
*arg
,
4730 const struct mips_operand
*operand_base
)
4732 const struct mips_msb_operand
*operand
;
4733 int min_val
, max_val
, max_high
;
4734 offsetT size
, sval
, high
;
4736 operand
= (const struct mips_msb_operand
*) operand_base
;
4737 min_val
= operand
->bias
;
4738 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4739 max_high
= operand
->opsize
;
4741 if (!match_const_int (arg
, &size
))
4744 high
= size
+ arg
->last_op_int
;
4745 sval
= operand
->add_lsb
? high
: size
;
4747 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4749 match_out_of_range (arg
);
4752 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4756 /* OP_REG matcher. */
4759 match_reg_operand (struct mips_arg_info
*arg
,
4760 const struct mips_operand
*operand_base
)
4762 const struct mips_reg_operand
*operand
;
4763 unsigned int regno
, uval
, num_vals
;
4765 operand
= (const struct mips_reg_operand
*) operand_base
;
4766 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4769 if (operand
->reg_map
)
4771 num_vals
= 1 << operand
->root
.size
;
4772 for (uval
= 0; uval
< num_vals
; uval
++)
4773 if (operand
->reg_map
[uval
] == regno
)
4775 if (num_vals
== uval
)
4781 arg
->last_regno
= regno
;
4782 if (arg
->opnum
== 1)
4783 arg
->dest_regno
= regno
;
4784 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4788 /* OP_REG_PAIR matcher. */
4791 match_reg_pair_operand (struct mips_arg_info
*arg
,
4792 const struct mips_operand
*operand_base
)
4794 const struct mips_reg_pair_operand
*operand
;
4795 unsigned int regno1
, regno2
, uval
, num_vals
;
4797 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4798 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4799 || !match_char (arg
, ',')
4800 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4803 num_vals
= 1 << operand_base
->size
;
4804 for (uval
= 0; uval
< num_vals
; uval
++)
4805 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4807 if (uval
== num_vals
)
4810 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4814 /* OP_PCREL matcher. The caller chooses the relocation type. */
4817 match_pcrel_operand (struct mips_arg_info
*arg
)
4819 bfd_reloc_code_real_type r
[3];
4821 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4824 /* OP_PERF_REG matcher. */
4827 match_perf_reg_operand (struct mips_arg_info
*arg
,
4828 const struct mips_operand
*operand
)
4832 if (!match_const_int (arg
, &sval
))
4837 || (mips_opts
.arch
== CPU_R5900
4838 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4839 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4841 set_insn_error (arg
->argnum
, _("invalid performance register"));
4845 insn_insert_operand (arg
->insn
, operand
, sval
);
4849 /* OP_ADDIUSP matcher. */
4852 match_addiusp_operand (struct mips_arg_info
*arg
,
4853 const struct mips_operand
*operand
)
4858 if (!match_const_int (arg
, &sval
))
4863 match_out_of_range (arg
);
4868 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4870 match_out_of_range (arg
);
4874 uval
= (unsigned int) sval
;
4875 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4876 insn_insert_operand (arg
->insn
, operand
, uval
);
4880 /* OP_CLO_CLZ_DEST matcher. */
4883 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4884 const struct mips_operand
*operand
)
4888 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4891 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4895 /* OP_LWM_SWM_LIST matcher. */
4898 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4899 const struct mips_operand
*operand
)
4901 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4902 struct mips_arg_info reset
;
4905 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4909 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4914 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4917 while (match_char (arg
, ',')
4918 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4921 if (operand
->size
== 2)
4923 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4929 and any permutations of these. */
4930 if ((reglist
& 0xfff1ffff) != 0x80010000)
4933 sregs
= (reglist
>> 17) & 7;
4938 /* The list must include at least one of ra and s0-sN,
4939 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4940 which are $23 and $30 respectively.) E.g.:
4948 and any permutations of these. */
4949 if ((reglist
& 0x3f00ffff) != 0)
4952 ra
= (reglist
>> 27) & 0x10;
4953 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4956 if ((sregs
& -sregs
) != sregs
)
4959 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4963 /* OP_ENTRY_EXIT_LIST matcher. */
4966 match_entry_exit_operand (struct mips_arg_info
*arg
,
4967 const struct mips_operand
*operand
)
4970 bfd_boolean is_exit
;
4972 /* The format is the same for both ENTRY and EXIT, but the constraints
4974 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4975 mask
= (is_exit
? 7 << 3 : 0);
4978 unsigned int regno1
, regno2
;
4979 bfd_boolean is_freg
;
4981 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4983 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4988 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4991 mask
|= (5 + regno2
) << 3;
4993 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4994 mask
|= (regno2
- 3) << 3;
4995 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4996 mask
|= (regno2
- 15) << 1;
4997 else if (regno1
== RA
&& regno2
== RA
)
5002 while (match_char (arg
, ','));
5004 insn_insert_operand (arg
->insn
, operand
, mask
);
5008 /* OP_SAVE_RESTORE_LIST matcher. */
5011 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5013 unsigned int opcode
, args
, statics
, sregs
;
5014 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5017 opcode
= arg
->insn
->insn_opcode
;
5019 num_frame_sizes
= 0;
5025 unsigned int regno1
, regno2
;
5027 if (arg
->token
->type
== OT_INTEGER
)
5029 /* Handle the frame size. */
5030 if (!match_const_int (arg
, &frame_size
))
5032 num_frame_sizes
+= 1;
5036 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5039 while (regno1
<= regno2
)
5041 if (regno1
>= 4 && regno1
<= 7)
5043 if (num_frame_sizes
== 0)
5045 args
|= 1 << (regno1
- 4);
5047 /* statics $a0-$a3 */
5048 statics
|= 1 << (regno1
- 4);
5050 else if (regno1
>= 16 && regno1
<= 23)
5052 sregs
|= 1 << (regno1
- 16);
5053 else if (regno1
== 30)
5056 else if (regno1
== 31)
5057 /* Add $ra to insn. */
5067 while (match_char (arg
, ','));
5069 /* Encode args/statics combination. */
5072 else if (args
== 0xf)
5073 /* All $a0-$a3 are args. */
5074 opcode
|= MIPS16_ALL_ARGS
<< 16;
5075 else if (statics
== 0xf)
5076 /* All $a0-$a3 are statics. */
5077 opcode
|= MIPS16_ALL_STATICS
<< 16;
5080 /* Count arg registers. */
5090 /* Count static registers. */
5092 while (statics
& 0x8)
5094 statics
= (statics
<< 1) & 0xf;
5100 /* Encode args/statics. */
5101 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5104 /* Encode $s0/$s1. */
5105 if (sregs
& (1 << 0)) /* $s0 */
5107 if (sregs
& (1 << 1)) /* $s1 */
5111 /* Encode $s2-$s8. */
5120 opcode
|= num_sregs
<< 24;
5122 /* Encode frame size. */
5123 if (num_frame_sizes
== 0)
5125 set_insn_error (arg
->argnum
, _("missing frame size"));
5128 if (num_frame_sizes
> 1)
5130 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5133 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5135 set_insn_error (arg
->argnum
, _("invalid frame size"));
5138 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5141 opcode
|= (((frame_size
& 0xf0) << 16)
5142 | (frame_size
& 0x0f));
5145 /* Finally build the instruction. */
5146 if ((opcode
>> 16) != 0 || frame_size
== 0)
5147 opcode
|= MIPS16_EXTEND
;
5148 arg
->insn
->insn_opcode
= opcode
;
5152 /* OP_MDMX_IMM_REG matcher. */
5155 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5156 const struct mips_operand
*operand
)
5158 unsigned int regno
, uval
;
5160 const struct mips_opcode
*opcode
;
5162 /* The mips_opcode records whether this is an octobyte or quadhalf
5163 instruction. Start out with that bit in place. */
5164 opcode
= arg
->insn
->insn_mo
;
5165 uval
= mips_extract_operand (operand
, opcode
->match
);
5166 is_qh
= (uval
!= 0);
5168 if (arg
->token
->type
== OT_REG
)
5170 if ((opcode
->membership
& INSN_5400
)
5171 && strcmp (opcode
->name
, "rzu.ob") == 0)
5173 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5178 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5182 /* Check whether this is a vector register or a broadcast of
5183 a single element. */
5184 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5186 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5188 set_insn_error (arg
->argnum
, _("invalid element selector"));
5191 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5196 /* A full vector. */
5197 if ((opcode
->membership
& INSN_5400
)
5198 && (strcmp (opcode
->name
, "sll.ob") == 0
5199 || strcmp (opcode
->name
, "srl.ob") == 0))
5201 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5207 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5209 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5217 if (!match_const_int (arg
, &sval
))
5219 if (sval
< 0 || sval
> 31)
5221 match_out_of_range (arg
);
5224 uval
|= (sval
& 31);
5226 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5228 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5230 insn_insert_operand (arg
->insn
, operand
, uval
);
5234 /* OP_IMM_INDEX matcher. */
5237 match_imm_index_operand (struct mips_arg_info
*arg
,
5238 const struct mips_operand
*operand
)
5240 unsigned int max_val
;
5242 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5245 max_val
= (1 << operand
->size
) - 1;
5246 if (arg
->token
->u
.index
> max_val
)
5248 match_out_of_range (arg
);
5251 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5256 /* OP_REG_INDEX matcher. */
5259 match_reg_index_operand (struct mips_arg_info
*arg
,
5260 const struct mips_operand
*operand
)
5264 if (arg
->token
->type
!= OT_REG_INDEX
)
5267 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5270 insn_insert_operand (arg
->insn
, operand
, regno
);
5275 /* OP_PC matcher. */
5278 match_pc_operand (struct mips_arg_info
*arg
)
5280 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5288 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5289 register that we need to match. */
5292 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5296 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5299 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5300 the length of the value in bytes (4 for float, 8 for double) and
5301 USING_GPRS says whether the destination is a GPR rather than an FPR.
5303 Return the constant in IMM and OFFSET as follows:
5305 - If the constant should be loaded via memory, set IMM to O_absent and
5306 OFFSET to the memory address.
5308 - Otherwise, if the constant should be loaded into two 32-bit registers,
5309 set IMM to the O_constant to load into the high register and OFFSET
5310 to the corresponding value for the low register.
5312 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5314 These constants only appear as the last operand in an instruction,
5315 and every instruction that accepts them in any variant accepts them
5316 in all variants. This means we don't have to worry about backing out
5317 any changes if the instruction does not match. We just match
5318 unconditionally and report an error if the constant is invalid. */
5321 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5322 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5327 const char *newname
;
5328 unsigned char *data
;
5330 /* Where the constant is placed is based on how the MIPS assembler
5333 length == 4 && using_gprs -- immediate value only
5334 length == 8 && using_gprs -- .rdata or immediate value
5335 length == 4 && !using_gprs -- .lit4 or immediate value
5336 length == 8 && !using_gprs -- .lit8 or immediate value
5338 The .lit4 and .lit8 sections are only used if permitted by the
5340 if (arg
->token
->type
!= OT_FLOAT
)
5342 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5346 gas_assert (arg
->token
->u
.flt
.length
== length
);
5347 data
= arg
->token
->u
.flt
.data
;
5350 /* Handle 32-bit constants for which an immediate value is best. */
5353 || g_switch_value
< 4
5354 || (data
[0] == 0 && data
[1] == 0)
5355 || (data
[2] == 0 && data
[3] == 0)))
5357 imm
->X_op
= O_constant
;
5358 if (!target_big_endian
)
5359 imm
->X_add_number
= bfd_getl32 (data
);
5361 imm
->X_add_number
= bfd_getb32 (data
);
5362 offset
->X_op
= O_absent
;
5366 /* Handle 64-bit constants for which an immediate value is best. */
5368 && !mips_disable_float_construction
5369 /* Constants can only be constructed in GPRs and copied
5370 to FPRs if the GPRs are at least as wide as the FPRs.
5371 Force the constant into memory if we are using 64-bit FPRs
5372 but the GPRs are only 32 bits wide. */
5373 /* ??? No longer true with the addition of MTHC1, but this
5374 is legacy code... */
5375 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5376 && ((data
[0] == 0 && data
[1] == 0)
5377 || (data
[2] == 0 && data
[3] == 0))
5378 && ((data
[4] == 0 && data
[5] == 0)
5379 || (data
[6] == 0 && data
[7] == 0)))
5381 /* The value is simple enough to load with a couple of instructions.
5382 If using 32-bit registers, set IMM to the high order 32 bits and
5383 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5385 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5387 imm
->X_op
= O_constant
;
5388 offset
->X_op
= O_constant
;
5389 if (!target_big_endian
)
5391 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5392 offset
->X_add_number
= bfd_getl32 (data
);
5396 imm
->X_add_number
= bfd_getb32 (data
);
5397 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5399 if (offset
->X_add_number
== 0)
5400 offset
->X_op
= O_absent
;
5404 imm
->X_op
= O_constant
;
5405 if (!target_big_endian
)
5406 imm
->X_add_number
= bfd_getl64 (data
);
5408 imm
->X_add_number
= bfd_getb64 (data
);
5409 offset
->X_op
= O_absent
;
5414 /* Switch to the right section. */
5416 subseg
= now_subseg
;
5419 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5424 if (using_gprs
|| g_switch_value
< 8)
5425 newname
= RDATA_SECTION_NAME
;
5430 new_seg
= subseg_new (newname
, (subsegT
) 0);
5431 bfd_set_section_flags (stdoutput
, new_seg
,
5432 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5433 frag_align (length
== 4 ? 2 : 3, 0, 0);
5434 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5435 record_alignment (new_seg
, 4);
5437 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5439 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
5441 /* Set the argument to the current address in the section. */
5442 imm
->X_op
= O_absent
;
5443 offset
->X_op
= O_symbol
;
5444 offset
->X_add_symbol
= symbol_temp_new_now ();
5445 offset
->X_add_number
= 0;
5447 /* Put the floating point number into the section. */
5448 p
= frag_more (length
);
5449 memcpy (p
, data
, length
);
5451 /* Switch back to the original section. */
5452 subseg_set (seg
, subseg
);
5456 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5460 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5461 const struct mips_operand
*operand
,
5462 bfd_boolean match_p
)
5466 /* The operand can be an XYZW mask or a single 2-bit channel index
5467 (with X being 0). */
5468 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5470 /* The suffix can be omitted when it is already part of the opcode. */
5471 if (arg
->token
->type
!= OT_CHANNELS
)
5474 uval
= arg
->token
->u
.channels
;
5475 if (operand
->size
== 2)
5477 /* Check that a single bit is set and convert it into a 2-bit index. */
5478 if ((uval
& -uval
) != uval
)
5480 uval
= 4 - ffs (uval
);
5483 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5488 insn_insert_operand (arg
->insn
, operand
, uval
);
5492 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5493 of the argument text if the match is successful, otherwise return null. */
5496 match_operand (struct mips_arg_info
*arg
,
5497 const struct mips_operand
*operand
)
5499 switch (operand
->type
)
5502 return match_int_operand (arg
, operand
);
5505 return match_mapped_int_operand (arg
, operand
);
5508 return match_msb_operand (arg
, operand
);
5511 case OP_OPTIONAL_REG
:
5512 return match_reg_operand (arg
, operand
);
5515 return match_reg_pair_operand (arg
, operand
);
5518 return match_pcrel_operand (arg
);
5521 return match_perf_reg_operand (arg
, operand
);
5523 case OP_ADDIUSP_INT
:
5524 return match_addiusp_operand (arg
, operand
);
5526 case OP_CLO_CLZ_DEST
:
5527 return match_clo_clz_dest_operand (arg
, operand
);
5529 case OP_LWM_SWM_LIST
:
5530 return match_lwm_swm_list_operand (arg
, operand
);
5532 case OP_ENTRY_EXIT_LIST
:
5533 return match_entry_exit_operand (arg
, operand
);
5535 case OP_SAVE_RESTORE_LIST
:
5536 return match_save_restore_list_operand (arg
);
5538 case OP_MDMX_IMM_REG
:
5539 return match_mdmx_imm_reg_operand (arg
, operand
);
5541 case OP_REPEAT_DEST_REG
:
5542 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5544 case OP_REPEAT_PREV_REG
:
5545 return match_tied_reg_operand (arg
, arg
->last_regno
);
5548 return match_pc_operand (arg
);
5551 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5553 case OP_VU0_MATCH_SUFFIX
:
5554 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5557 return match_imm_index_operand (arg
, operand
);
5560 return match_reg_index_operand (arg
, operand
);
5565 /* ARG is the state after successfully matching an instruction.
5566 Issue any queued-up warnings. */
5569 check_completed_insn (struct mips_arg_info
*arg
)
5574 as_warn (_("used $at without \".set noat\""));
5576 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
5580 /* Return true if modifying general-purpose register REG needs a delay. */
5583 reg_needs_delay (unsigned int reg
)
5585 unsigned long prev_pinfo
;
5587 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5588 if (!mips_opts
.noreorder
5589 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
5590 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5591 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5597 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5598 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5599 by VR4120 errata. */
5602 classify_vr4120_insn (const char *name
)
5604 if (strncmp (name
, "macc", 4) == 0)
5605 return FIX_VR4120_MACC
;
5606 if (strncmp (name
, "dmacc", 5) == 0)
5607 return FIX_VR4120_DMACC
;
5608 if (strncmp (name
, "mult", 4) == 0)
5609 return FIX_VR4120_MULT
;
5610 if (strncmp (name
, "dmult", 5) == 0)
5611 return FIX_VR4120_DMULT
;
5612 if (strstr (name
, "div"))
5613 return FIX_VR4120_DIV
;
5614 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5615 return FIX_VR4120_MTHILO
;
5616 return NUM_FIX_VR4120_CLASSES
;
5619 #define INSN_ERET 0x42000018
5620 #define INSN_DERET 0x4200001f
5621 #define INSN_DMULT 0x1c
5622 #define INSN_DMULTU 0x1d
5624 /* Return the number of instructions that must separate INSN1 and INSN2,
5625 where INSN1 is the earlier instruction. Return the worst-case value
5626 for any INSN2 if INSN2 is null. */
5629 insns_between (const struct mips_cl_insn
*insn1
,
5630 const struct mips_cl_insn
*insn2
)
5632 unsigned long pinfo1
, pinfo2
;
5635 /* If INFO2 is null, pessimistically assume that all flags are set for
5636 the second instruction. */
5637 pinfo1
= insn1
->insn_mo
->pinfo
;
5638 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5640 /* For most targets, write-after-read dependencies on the HI and LO
5641 registers must be separated by at least two instructions. */
5642 if (!hilo_interlocks
)
5644 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5646 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5650 /* If we're working around r7000 errata, there must be two instructions
5651 between an mfhi or mflo and any instruction that uses the result. */
5652 if (mips_7000_hilo_fix
5653 && !mips_opts
.micromips
5654 && MF_HILO_INSN (pinfo1
)
5655 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5658 /* If we're working around 24K errata, one instruction is required
5659 if an ERET or DERET is followed by a branch instruction. */
5660 if (mips_fix_24k
&& !mips_opts
.micromips
)
5662 if (insn1
->insn_opcode
== INSN_ERET
5663 || insn1
->insn_opcode
== INSN_DERET
)
5666 || insn2
->insn_opcode
== INSN_ERET
5667 || insn2
->insn_opcode
== INSN_DERET
5668 || delayed_branch_p (insn2
))
5673 /* If we're working around PMC RM7000 errata, there must be three
5674 nops between a dmult and a load instruction. */
5675 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
5677 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
5678 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
5680 if (pinfo2
& INSN_LOAD_MEMORY
)
5685 /* If working around VR4120 errata, check for combinations that need
5686 a single intervening instruction. */
5687 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5689 unsigned int class1
, class2
;
5691 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5692 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5696 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5697 if (vr4120_conflicts
[class1
] & (1 << class2
))
5702 if (!HAVE_CODE_COMPRESSION
)
5704 /* Check for GPR or coprocessor load delays. All such delays
5705 are on the RT register. */
5706 /* Itbl support may require additional care here. */
5707 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
5708 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5710 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5714 /* Check for generic coprocessor hazards.
5716 This case is not handled very well. There is no special
5717 knowledge of CP0 handling, and the coprocessors other than
5718 the floating point unit are not distinguished at all. */
5719 /* Itbl support may require additional care here. FIXME!
5720 Need to modify this to include knowledge about
5721 user specified delays! */
5722 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5723 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5725 /* Handle cases where INSN1 writes to a known general coprocessor
5726 register. There must be a one instruction delay before INSN2
5727 if INSN2 reads that register, otherwise no delay is needed. */
5728 mask
= fpr_write_mask (insn1
);
5731 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5736 /* Read-after-write dependencies on the control registers
5737 require a two-instruction gap. */
5738 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5739 && (pinfo2
& INSN_READ_COND_CODE
))
5742 /* We don't know exactly what INSN1 does. If INSN2 is
5743 also a coprocessor instruction, assume there must be
5744 a one instruction gap. */
5745 if (pinfo2
& INSN_COP
)
5750 /* Check for read-after-write dependencies on the coprocessor
5751 control registers in cases where INSN1 does not need a general
5752 coprocessor delay. This means that INSN1 is a floating point
5753 comparison instruction. */
5754 /* Itbl support may require additional care here. */
5755 else if (!cop_interlocks
5756 && (pinfo1
& INSN_WRITE_COND_CODE
)
5757 && (pinfo2
& INSN_READ_COND_CODE
))
5764 /* Return the number of nops that would be needed to work around the
5765 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5766 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5767 that are contained within the first IGNORE instructions of HIST. */
5770 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5771 const struct mips_cl_insn
*insn
)
5776 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5777 are not affected by the errata. */
5779 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5780 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5781 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5784 /* Search for the first MFLO or MFHI. */
5785 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5786 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5788 /* Extract the destination register. */
5789 mask
= gpr_write_mask (&hist
[i
]);
5791 /* No nops are needed if INSN reads that register. */
5792 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5795 /* ...or if any of the intervening instructions do. */
5796 for (j
= 0; j
< i
; j
++)
5797 if (gpr_read_mask (&hist
[j
]) & mask
)
5801 return MAX_VR4130_NOPS
- i
;
5806 #define BASE_REG_EQ(INSN1, INSN2) \
5807 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5808 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5810 /* Return the minimum alignment for this store instruction. */
5813 fix_24k_align_to (const struct mips_opcode
*mo
)
5815 if (strcmp (mo
->name
, "sh") == 0)
5818 if (strcmp (mo
->name
, "swc1") == 0
5819 || strcmp (mo
->name
, "swc2") == 0
5820 || strcmp (mo
->name
, "sw") == 0
5821 || strcmp (mo
->name
, "sc") == 0
5822 || strcmp (mo
->name
, "s.s") == 0)
5825 if (strcmp (mo
->name
, "sdc1") == 0
5826 || strcmp (mo
->name
, "sdc2") == 0
5827 || strcmp (mo
->name
, "s.d") == 0)
5834 struct fix_24k_store_info
5836 /* Immediate offset, if any, for this store instruction. */
5838 /* Alignment required by this store instruction. */
5840 /* True for register offsets. */
5841 int register_offset
;
5844 /* Comparison function used by qsort. */
5847 fix_24k_sort (const void *a
, const void *b
)
5849 const struct fix_24k_store_info
*pos1
= a
;
5850 const struct fix_24k_store_info
*pos2
= b
;
5852 return (pos1
->off
- pos2
->off
);
5855 /* INSN is a store instruction. Try to record the store information
5856 in STINFO. Return false if the information isn't known. */
5859 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5860 const struct mips_cl_insn
*insn
)
5862 /* The instruction must have a known offset. */
5863 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5866 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5867 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5871 /* Return the number of nops that would be needed to work around the 24k
5872 "lost data on stores during refill" errata if instruction INSN
5873 immediately followed the 2 instructions described by HIST.
5874 Ignore hazards that are contained within the first IGNORE
5875 instructions of HIST.
5877 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5878 for the data cache refills and store data. The following describes
5879 the scenario where the store data could be lost.
5881 * A data cache miss, due to either a load or a store, causing fill
5882 data to be supplied by the memory subsystem
5883 * The first three doublewords of fill data are returned and written
5885 * A sequence of four stores occurs in consecutive cycles around the
5886 final doubleword of the fill:
5890 * Zero, One or more instructions
5893 The four stores A-D must be to different doublewords of the line that
5894 is being filled. The fourth instruction in the sequence above permits
5895 the fill of the final doubleword to be transferred from the FSB into
5896 the cache. In the sequence above, the stores may be either integer
5897 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5898 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5899 different doublewords on the line. If the floating point unit is
5900 running in 1:2 mode, it is not possible to create the sequence above
5901 using only floating point store instructions.
5903 In this case, the cache line being filled is incorrectly marked
5904 invalid, thereby losing the data from any store to the line that
5905 occurs between the original miss and the completion of the five
5906 cycle sequence shown above.
5908 The workarounds are:
5910 * Run the data cache in write-through mode.
5911 * Insert a non-store instruction between
5912 Store A and Store B or Store B and Store C. */
5915 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5916 const struct mips_cl_insn
*insn
)
5918 struct fix_24k_store_info pos
[3];
5919 int align
, i
, base_offset
;
5924 /* If the previous instruction wasn't a store, there's nothing to
5926 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5929 /* If the instructions after the previous one are unknown, we have
5930 to assume the worst. */
5934 /* Check whether we are dealing with three consecutive stores. */
5935 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5936 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5939 /* If we don't know the relationship between the store addresses,
5940 assume the worst. */
5941 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5942 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5945 if (!fix_24k_record_store_info (&pos
[0], insn
)
5946 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5947 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5950 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5952 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5953 X bytes and such that the base register + X is known to be aligned
5956 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5960 align
= pos
[0].align_to
;
5961 base_offset
= pos
[0].off
;
5962 for (i
= 1; i
< 3; i
++)
5963 if (align
< pos
[i
].align_to
)
5965 align
= pos
[i
].align_to
;
5966 base_offset
= pos
[i
].off
;
5968 for (i
= 0; i
< 3; i
++)
5969 pos
[i
].off
-= base_offset
;
5972 pos
[0].off
&= ~align
+ 1;
5973 pos
[1].off
&= ~align
+ 1;
5974 pos
[2].off
&= ~align
+ 1;
5976 /* If any two stores write to the same chunk, they also write to the
5977 same doubleword. The offsets are still sorted at this point. */
5978 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5981 /* A range of at least 9 bytes is needed for the stores to be in
5982 non-overlapping doublewords. */
5983 if (pos
[2].off
- pos
[0].off
<= 8)
5986 if (pos
[2].off
- pos
[1].off
>= 24
5987 || pos
[1].off
- pos
[0].off
>= 24
5988 || pos
[2].off
- pos
[0].off
>= 32)
5994 /* Return the number of nops that would be needed if instruction INSN
5995 immediately followed the MAX_NOPS instructions given by HIST,
5996 where HIST[0] is the most recent instruction. Ignore hazards
5997 between INSN and the first IGNORE instructions in HIST.
5999 If INSN is null, return the worse-case number of nops for any
6003 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6004 const struct mips_cl_insn
*insn
)
6006 int i
, nops
, tmp_nops
;
6009 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6011 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6012 if (tmp_nops
> nops
)
6016 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6018 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6019 if (tmp_nops
> nops
)
6023 if (mips_fix_24k
&& !mips_opts
.micromips
)
6025 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6026 if (tmp_nops
> nops
)
6033 /* The variable arguments provide NUM_INSNS extra instructions that
6034 might be added to HIST. Return the largest number of nops that
6035 would be needed after the extended sequence, ignoring hazards
6036 in the first IGNORE instructions. */
6039 nops_for_sequence (int num_insns
, int ignore
,
6040 const struct mips_cl_insn
*hist
, ...)
6043 struct mips_cl_insn buffer
[MAX_NOPS
];
6044 struct mips_cl_insn
*cursor
;
6047 va_start (args
, hist
);
6048 cursor
= buffer
+ num_insns
;
6049 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6050 while (cursor
> buffer
)
6051 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6053 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6058 /* Like nops_for_insn, but if INSN is a branch, take into account the
6059 worst-case delay for the branch target. */
6062 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6063 const struct mips_cl_insn
*insn
)
6067 nops
= nops_for_insn (ignore
, hist
, insn
);
6068 if (delayed_branch_p (insn
))
6070 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6071 hist
, insn
, get_delay_slot_nop (insn
));
6072 if (tmp_nops
> nops
)
6075 else if (compact_branch_p (insn
))
6077 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6078 if (tmp_nops
> nops
)
6084 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6087 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6089 gas_assert (!HAVE_CODE_COMPRESSION
);
6090 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6091 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6094 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6095 jr target pc &= 'hffff_ffff_cfff_ffff. */
6098 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6100 gas_assert (!HAVE_CODE_COMPRESSION
);
6101 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6102 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6103 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6111 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6112 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6115 ep
.X_op
= O_constant
;
6116 ep
.X_add_number
= 0xcfff0000;
6117 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6118 ep
.X_add_number
= 0xffff;
6119 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6120 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6125 fix_loongson2f (struct mips_cl_insn
* ip
)
6127 if (mips_fix_loongson2f_nop
)
6128 fix_loongson2f_nop (ip
);
6130 if (mips_fix_loongson2f_jump
)
6131 fix_loongson2f_jump (ip
);
6134 /* IP is a branch that has a delay slot, and we need to fill it
6135 automatically. Return true if we can do that by swapping IP
6136 with the previous instruction.
6137 ADDRESS_EXPR is an operand of the instruction to be used with
6141 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6142 bfd_reloc_code_real_type
*reloc_type
)
6144 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6145 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6146 unsigned int fpr_read
, prev_fpr_write
;
6148 /* -O2 and above is required for this optimization. */
6149 if (mips_optimize
< 2)
6152 /* If we have seen .set volatile or .set nomove, don't optimize. */
6153 if (mips_opts
.nomove
)
6156 /* We can't swap if the previous instruction's position is fixed. */
6157 if (history
[0].fixed_p
)
6160 /* If the previous previous insn was in a .set noreorder, we can't
6161 swap. Actually, the MIPS assembler will swap in this situation.
6162 However, gcc configured -with-gnu-as will generate code like
6170 in which we can not swap the bne and INSN. If gcc is not configured
6171 -with-gnu-as, it does not output the .set pseudo-ops. */
6172 if (history
[1].noreorder_p
)
6175 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6176 This means that the previous instruction was a 4-byte one anyhow. */
6177 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6180 /* If the branch is itself the target of a branch, we can not swap.
6181 We cheat on this; all we check for is whether there is a label on
6182 this instruction. If there are any branches to anything other than
6183 a label, users must use .set noreorder. */
6184 if (seg_info (now_seg
)->label_list
)
6187 /* If the previous instruction is in a variant frag other than this
6188 branch's one, we cannot do the swap. This does not apply to
6189 MIPS16 code, which uses variant frags for different purposes. */
6190 if (!mips_opts
.mips16
6192 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6195 /* We do not swap with instructions that cannot architecturally
6196 be placed in a branch delay slot, such as SYNC or ERET. We
6197 also refrain from swapping with a trap instruction, since it
6198 complicates trap handlers to have the trap instruction be in
6200 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6201 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6204 /* Check for conflicts between the branch and the instructions
6205 before the candidate delay slot. */
6206 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6209 /* Check for conflicts between the swapped sequence and the
6210 target of the branch. */
6211 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6214 /* If the branch reads a register that the previous
6215 instruction sets, we can not swap. */
6216 gpr_read
= gpr_read_mask (ip
);
6217 prev_gpr_write
= gpr_write_mask (&history
[0]);
6218 if (gpr_read
& prev_gpr_write
)
6221 fpr_read
= fpr_read_mask (ip
);
6222 prev_fpr_write
= fpr_write_mask (&history
[0]);
6223 if (fpr_read
& prev_fpr_write
)
6226 /* If the branch writes a register that the previous
6227 instruction sets, we can not swap. */
6228 gpr_write
= gpr_write_mask (ip
);
6229 if (gpr_write
& prev_gpr_write
)
6232 /* If the branch writes a register that the previous
6233 instruction reads, we can not swap. */
6234 prev_gpr_read
= gpr_read_mask (&history
[0]);
6235 if (gpr_write
& prev_gpr_read
)
6238 /* If one instruction sets a condition code and the
6239 other one uses a condition code, we can not swap. */
6240 pinfo
= ip
->insn_mo
->pinfo
;
6241 if ((pinfo
& INSN_READ_COND_CODE
)
6242 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6244 if ((pinfo
& INSN_WRITE_COND_CODE
)
6245 && (prev_pinfo
& INSN_READ_COND_CODE
))
6248 /* If the previous instruction uses the PC, we can not swap. */
6249 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6250 if (prev_pinfo2
& INSN2_READ_PC
)
6253 /* If the previous instruction has an incorrect size for a fixed
6254 branch delay slot in microMIPS mode, we cannot swap. */
6255 pinfo2
= ip
->insn_mo
->pinfo2
;
6256 if (mips_opts
.micromips
6257 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6258 && insn_length (history
) != 2)
6260 if (mips_opts
.micromips
6261 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6262 && insn_length (history
) != 4)
6265 /* On R5900 short loops need to be fixed by inserting a nop in
6266 the branch delay slots.
6267 A short loop can be terminated too early. */
6268 if (mips_opts
.arch
== CPU_R5900
6269 /* Check if instruction has a parameter, ignore "j $31". */
6270 && (address_expr
!= NULL
)
6271 /* Parameter must be 16 bit. */
6272 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6273 /* Branch to same segment. */
6274 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6275 /* Branch to same code fragment. */
6276 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6277 /* Can only calculate branch offset if value is known. */
6278 && symbol_constant_p(address_expr
->X_add_symbol
)
6279 /* Check if branch is really conditional. */
6280 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6281 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6282 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6285 /* Check if loop is shorter than 6 instructions including
6286 branch and delay slot. */
6287 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6294 /* When the loop includes branches or jumps,
6295 it is not a short loop. */
6296 for (i
= 0; i
< (distance
/ 4); i
++)
6298 if ((history
[i
].cleared_p
)
6299 || delayed_branch_p(&history
[i
]))
6307 /* Insert nop after branch to fix short loop. */
6316 /* Decide how we should add IP to the instruction stream.
6317 ADDRESS_EXPR is an operand of the instruction to be used with
6320 static enum append_method
6321 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6322 bfd_reloc_code_real_type
*reloc_type
)
6324 /* The relaxed version of a macro sequence must be inherently
6326 if (mips_relax
.sequence
== 2)
6329 /* We must not dabble with instructions in a ".set norerorder" block. */
6330 if (mips_opts
.noreorder
)
6333 /* Otherwise, it's our responsibility to fill branch delay slots. */
6334 if (delayed_branch_p (ip
))
6336 if (!branch_likely_p (ip
)
6337 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6340 if (mips_opts
.mips16
6341 && ISA_SUPPORTS_MIPS16E
6342 && gpr_read_mask (ip
) != 0)
6343 return APPEND_ADD_COMPACT
;
6345 return APPEND_ADD_WITH_NOP
;
6351 /* IP is a MIPS16 instruction whose opcode we have just changed.
6352 Point IP->insn_mo to the new opcode's definition. */
6355 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6357 const struct mips_opcode
*mo
, *end
;
6359 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6360 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6361 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6369 /* For microMIPS macros, we need to generate a local number label
6370 as the target of branches. */
6371 #define MICROMIPS_LABEL_CHAR '\037'
6372 static unsigned long micromips_target_label
;
6373 static char micromips_target_name
[32];
6376 micromips_label_name (void)
6378 char *p
= micromips_target_name
;
6379 char symbol_name_temporary
[24];
6387 l
= micromips_target_label
;
6388 #ifdef LOCAL_LABEL_PREFIX
6389 *p
++ = LOCAL_LABEL_PREFIX
;
6392 *p
++ = MICROMIPS_LABEL_CHAR
;
6395 symbol_name_temporary
[i
++] = l
% 10 + '0';
6400 *p
++ = symbol_name_temporary
[--i
];
6403 return micromips_target_name
;
6407 micromips_label_expr (expressionS
*label_expr
)
6409 label_expr
->X_op
= O_symbol
;
6410 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6411 label_expr
->X_add_number
= 0;
6415 micromips_label_inc (void)
6417 micromips_target_label
++;
6418 *micromips_target_name
= '\0';
6422 micromips_add_label (void)
6426 s
= colon (micromips_label_name ());
6427 micromips_label_inc ();
6428 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6431 /* If assembling microMIPS code, then return the microMIPS reloc
6432 corresponding to the requested one if any. Otherwise return
6433 the reloc unchanged. */
6435 static bfd_reloc_code_real_type
6436 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6438 static const bfd_reloc_code_real_type relocs
[][2] =
6440 /* Keep sorted incrementally by the left-hand key. */
6441 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6442 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6443 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6444 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6445 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6446 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6447 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6448 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6449 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6450 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6451 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6452 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6453 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6454 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6455 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6456 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6457 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6458 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6459 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6460 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6461 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6462 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6463 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6464 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6465 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6466 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6467 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6469 bfd_reloc_code_real_type r
;
6472 if (!mips_opts
.micromips
)
6474 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6480 return relocs
[i
][1];
6485 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6486 Return true on success, storing the resolved value in RESULT. */
6489 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6494 case BFD_RELOC_MIPS_HIGHEST
:
6495 case BFD_RELOC_MICROMIPS_HIGHEST
:
6496 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6499 case BFD_RELOC_MIPS_HIGHER
:
6500 case BFD_RELOC_MICROMIPS_HIGHER
:
6501 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6504 case BFD_RELOC_HI16_S
:
6505 case BFD_RELOC_MICROMIPS_HI16_S
:
6506 case BFD_RELOC_MIPS16_HI16_S
:
6507 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6510 case BFD_RELOC_HI16
:
6511 case BFD_RELOC_MICROMIPS_HI16
:
6512 case BFD_RELOC_MIPS16_HI16
:
6513 *result
= (operand
>> 16) & 0xffff;
6516 case BFD_RELOC_LO16
:
6517 case BFD_RELOC_MICROMIPS_LO16
:
6518 case BFD_RELOC_MIPS16_LO16
:
6519 *result
= operand
& 0xffff;
6522 case BFD_RELOC_UNUSED
:
6531 /* Output an instruction. IP is the instruction information.
6532 ADDRESS_EXPR is an operand of the instruction to be used with
6533 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6534 a macro expansion. */
6537 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6538 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6540 unsigned long prev_pinfo2
, pinfo
;
6541 bfd_boolean relaxed_branch
= FALSE
;
6542 enum append_method method
;
6543 bfd_boolean relax32
;
6546 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6547 fix_loongson2f (ip
);
6549 file_ase_mips16
|= mips_opts
.mips16
;
6550 file_ase_micromips
|= mips_opts
.micromips
;
6552 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6553 pinfo
= ip
->insn_mo
->pinfo
;
6555 if (mips_opts
.micromips
6557 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6558 && micromips_insn_length (ip
->insn_mo
) != 2)
6559 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6560 && micromips_insn_length (ip
->insn_mo
) != 4)))
6561 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
6562 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6564 if (address_expr
== NULL
)
6566 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6567 && reloc_type
[1] == BFD_RELOC_UNUSED
6568 && reloc_type
[2] == BFD_RELOC_UNUSED
6569 && address_expr
->X_op
== O_constant
)
6571 switch (*reloc_type
)
6573 case BFD_RELOC_MIPS_JMP
:
6577 shift
= mips_opts
.micromips
? 1 : 2;
6578 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6579 as_bad (_("jump to misaligned address (0x%lx)"),
6580 (unsigned long) address_expr
->X_add_number
);
6581 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6587 case BFD_RELOC_MIPS16_JMP
:
6588 if ((address_expr
->X_add_number
& 3) != 0)
6589 as_bad (_("jump to misaligned address (0x%lx)"),
6590 (unsigned long) address_expr
->X_add_number
);
6592 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6593 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6594 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6598 case BFD_RELOC_16_PCREL_S2
:
6602 shift
= mips_opts
.micromips
? 1 : 2;
6603 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6604 as_bad (_("branch to misaligned address (0x%lx)"),
6605 (unsigned long) address_expr
->X_add_number
);
6606 if (!mips_relax_branch
)
6608 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6609 & ~((1 << (shift
+ 16)) - 1))
6610 as_bad (_("branch address range overflow (0x%lx)"),
6611 (unsigned long) address_expr
->X_add_number
);
6612 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6622 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6625 ip
->insn_opcode
|= value
& 0xffff;
6633 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6635 /* There are a lot of optimizations we could do that we don't.
6636 In particular, we do not, in general, reorder instructions.
6637 If you use gcc with optimization, it will reorder
6638 instructions and generally do much more optimization then we
6639 do here; repeating all that work in the assembler would only
6640 benefit hand written assembly code, and does not seem worth
6642 int nops
= (mips_optimize
== 0
6643 ? nops_for_insn (0, history
, NULL
)
6644 : nops_for_insn_or_target (0, history
, ip
));
6648 unsigned long old_frag_offset
;
6651 old_frag
= frag_now
;
6652 old_frag_offset
= frag_now_fix ();
6654 for (i
= 0; i
< nops
; i
++)
6655 add_fixed_insn (NOP_INSN
);
6656 insert_into_history (0, nops
, NOP_INSN
);
6660 listing_prev_line ();
6661 /* We may be at the start of a variant frag. In case we
6662 are, make sure there is enough space for the frag
6663 after the frags created by listing_prev_line. The
6664 argument to frag_grow here must be at least as large
6665 as the argument to all other calls to frag_grow in
6666 this file. We don't have to worry about being in the
6667 middle of a variant frag, because the variants insert
6668 all needed nop instructions themselves. */
6672 mips_move_text_labels ();
6674 #ifndef NO_ECOFF_DEBUGGING
6675 if (ECOFF_DEBUGGING
)
6676 ecoff_fix_loc (old_frag
, old_frag_offset
);
6680 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6684 /* Work out how many nops in prev_nop_frag are needed by IP,
6685 ignoring hazards generated by the first prev_nop_frag_since
6687 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6688 gas_assert (nops
<= prev_nop_frag_holds
);
6690 /* Enforce NOPS as a minimum. */
6691 if (nops
> prev_nop_frag_required
)
6692 prev_nop_frag_required
= nops
;
6694 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6696 /* Settle for the current number of nops. Update the history
6697 accordingly (for the benefit of any future .set reorder code). */
6698 prev_nop_frag
= NULL
;
6699 insert_into_history (prev_nop_frag_since
,
6700 prev_nop_frag_holds
, NOP_INSN
);
6704 /* Allow this instruction to replace one of the nops that was
6705 tentatively added to prev_nop_frag. */
6706 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6707 prev_nop_frag_holds
--;
6708 prev_nop_frag_since
++;
6712 method
= get_append_method (ip
, address_expr
, reloc_type
);
6713 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6715 dwarf2_emit_insn (0);
6716 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6717 so "move" the instruction address accordingly.
6719 Also, it doesn't seem appropriate for the assembler to reorder .loc
6720 entries. If this instruction is a branch that we are going to swap
6721 with the previous instruction, the two instructions should be
6722 treated as a unit, and the debug information for both instructions
6723 should refer to the start of the branch sequence. Using the
6724 current position is certainly wrong when swapping a 32-bit branch
6725 and a 16-bit delay slot, since the current position would then be
6726 in the middle of a branch. */
6727 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6729 relax32
= (mips_relax_branch
6730 /* Don't try branch relaxation within .set nomacro, or within
6731 .set noat if we use $at for PIC computations. If it turns
6732 out that the branch was out-of-range, we'll get an error. */
6733 && !mips_opts
.warn_about_macros
6734 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6735 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6736 as they have no complementing branches. */
6737 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6739 if (!HAVE_CODE_COMPRESSION
6742 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6743 && delayed_branch_p (ip
))
6745 relaxed_branch
= TRUE
;
6746 add_relaxed_insn (ip
, (relaxed_branch_length
6748 uncond_branch_p (ip
) ? -1
6749 : branch_likely_p (ip
) ? 1
6753 uncond_branch_p (ip
),
6754 branch_likely_p (ip
),
6755 pinfo
& INSN_WRITE_GPR_31
,
6757 address_expr
->X_add_symbol
,
6758 address_expr
->X_add_number
);
6759 *reloc_type
= BFD_RELOC_UNUSED
;
6761 else if (mips_opts
.micromips
6763 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6764 || *reloc_type
> BFD_RELOC_UNUSED
)
6765 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6766 /* Don't try branch relaxation when users specify
6767 16-bit/32-bit instructions. */
6768 && !forced_insn_length
)
6770 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6771 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6772 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6773 int compact
= compact_branch_p (ip
);
6774 int al
= pinfo
& INSN_WRITE_GPR_31
;
6777 gas_assert (address_expr
!= NULL
);
6778 gas_assert (!mips_relax
.sequence
);
6780 relaxed_branch
= TRUE
;
6781 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6782 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6783 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6785 address_expr
->X_add_symbol
,
6786 address_expr
->X_add_number
);
6787 *reloc_type
= BFD_RELOC_UNUSED
;
6789 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6791 /* We need to set up a variant frag. */
6792 gas_assert (address_expr
!= NULL
);
6793 add_relaxed_insn (ip
, 4, 0,
6795 (*reloc_type
- BFD_RELOC_UNUSED
,
6796 forced_insn_length
== 2, forced_insn_length
== 4,
6797 delayed_branch_p (&history
[0]),
6798 history
[0].mips16_absolute_jump_p
),
6799 make_expr_symbol (address_expr
), 0);
6801 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6803 if (!delayed_branch_p (ip
))
6804 /* Make sure there is enough room to swap this instruction with
6805 a following jump instruction. */
6807 add_fixed_insn (ip
);
6811 if (mips_opts
.mips16
6812 && mips_opts
.noreorder
6813 && delayed_branch_p (&history
[0]))
6814 as_warn (_("extended instruction in delay slot"));
6816 if (mips_relax
.sequence
)
6818 /* If we've reached the end of this frag, turn it into a variant
6819 frag and record the information for the instructions we've
6821 if (frag_room () < 4)
6822 relax_close_frag ();
6823 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6826 if (mips_relax
.sequence
!= 2)
6828 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6829 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6830 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6831 mips_macro_warning
.insns
[0]++;
6833 if (mips_relax
.sequence
!= 1)
6835 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6836 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6837 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6838 mips_macro_warning
.insns
[1]++;
6841 if (mips_opts
.mips16
)
6844 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6846 add_fixed_insn (ip
);
6849 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6851 bfd_reloc_code_real_type final_type
[3];
6852 reloc_howto_type
*howto0
;
6853 reloc_howto_type
*howto
;
6856 /* Perform any necessary conversion to microMIPS relocations
6857 and find out how many relocations there actually are. */
6858 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6859 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6861 /* In a compound relocation, it is the final (outermost)
6862 operator that determines the relocated field. */
6863 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6868 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6869 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6870 bfd_get_reloc_size (howto
),
6872 howto0
&& howto0
->pc_relative
,
6875 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6876 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6877 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6879 /* These relocations can have an addend that won't fit in
6880 4 octets for 64bit assembly. */
6882 && ! howto
->partial_inplace
6883 && (reloc_type
[0] == BFD_RELOC_16
6884 || reloc_type
[0] == BFD_RELOC_32
6885 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6886 || reloc_type
[0] == BFD_RELOC_GPREL16
6887 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6888 || reloc_type
[0] == BFD_RELOC_GPREL32
6889 || reloc_type
[0] == BFD_RELOC_64
6890 || reloc_type
[0] == BFD_RELOC_CTOR
6891 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6892 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6893 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6894 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6895 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6896 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6897 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6898 || hi16_reloc_p (reloc_type
[0])
6899 || lo16_reloc_p (reloc_type
[0])))
6900 ip
->fixp
[0]->fx_no_overflow
= 1;
6902 /* These relocations can have an addend that won't fit in 2 octets. */
6903 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6904 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6905 ip
->fixp
[0]->fx_no_overflow
= 1;
6907 if (mips_relax
.sequence
)
6909 if (mips_relax
.first_fixup
== 0)
6910 mips_relax
.first_fixup
= ip
->fixp
[0];
6912 else if (reloc_needs_lo_p (*reloc_type
))
6914 struct mips_hi_fixup
*hi_fixup
;
6916 /* Reuse the last entry if it already has a matching %lo. */
6917 hi_fixup
= mips_hi_fixup_list
;
6919 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6921 hi_fixup
= ((struct mips_hi_fixup
*)
6922 xmalloc (sizeof (struct mips_hi_fixup
)));
6923 hi_fixup
->next
= mips_hi_fixup_list
;
6924 mips_hi_fixup_list
= hi_fixup
;
6926 hi_fixup
->fixp
= ip
->fixp
[0];
6927 hi_fixup
->seg
= now_seg
;
6930 /* Add fixups for the second and third relocations, if given.
6931 Note that the ABI allows the second relocation to be
6932 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6933 moment we only use RSS_UNDEF, but we could add support
6934 for the others if it ever becomes necessary. */
6935 for (i
= 1; i
< 3; i
++)
6936 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6938 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6939 ip
->fixp
[0]->fx_size
, NULL
, 0,
6940 FALSE
, final_type
[i
]);
6942 /* Use fx_tcbit to mark compound relocs. */
6943 ip
->fixp
[0]->fx_tcbit
= 1;
6944 ip
->fixp
[i
]->fx_tcbit
= 1;
6949 /* Update the register mask information. */
6950 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6951 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6956 insert_into_history (0, 1, ip
);
6959 case APPEND_ADD_WITH_NOP
:
6961 struct mips_cl_insn
*nop
;
6963 insert_into_history (0, 1, ip
);
6964 nop
= get_delay_slot_nop (ip
);
6965 add_fixed_insn (nop
);
6966 insert_into_history (0, 1, nop
);
6967 if (mips_relax
.sequence
)
6968 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6972 case APPEND_ADD_COMPACT
:
6973 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6974 gas_assert (mips_opts
.mips16
);
6975 ip
->insn_opcode
|= 0x0080;
6976 find_altered_mips16_opcode (ip
);
6978 insert_into_history (0, 1, ip
);
6983 struct mips_cl_insn delay
= history
[0];
6984 if (mips_opts
.mips16
)
6986 know (delay
.frag
== ip
->frag
);
6987 move_insn (ip
, delay
.frag
, delay
.where
);
6988 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6990 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6992 /* Add the delay slot instruction to the end of the
6993 current frag and shrink the fixed part of the
6994 original frag. If the branch occupies the tail of
6995 the latter, move it backwards to cover the gap. */
6996 delay
.frag
->fr_fix
-= branch_disp
;
6997 if (delay
.frag
== ip
->frag
)
6998 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6999 add_fixed_insn (&delay
);
7003 move_insn (&delay
, ip
->frag
,
7004 ip
->where
- branch_disp
+ insn_length (ip
));
7005 move_insn (ip
, history
[0].frag
, history
[0].where
);
7009 insert_into_history (0, 1, &delay
);
7014 /* If we have just completed an unconditional branch, clear the history. */
7015 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
7016 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
7020 mips_no_prev_insn ();
7022 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7023 history
[i
].cleared_p
= 1;
7026 /* We need to emit a label at the end of branch-likely macros. */
7027 if (emit_branch_likely_macro
)
7029 emit_branch_likely_macro
= FALSE
;
7030 micromips_add_label ();
7033 /* We just output an insn, so the next one doesn't have a label. */
7034 mips_clear_insn_labels ();
7037 /* Forget that there was any previous instruction or label.
7038 When BRANCH is true, the branch history is also flushed. */
7041 mips_no_prev_insn (void)
7043 prev_nop_frag
= NULL
;
7044 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
7045 mips_clear_insn_labels ();
7048 /* This function must be called before we emit something other than
7049 instructions. It is like mips_no_prev_insn except that it inserts
7050 any NOPS that might be needed by previous instructions. */
7053 mips_emit_delays (void)
7055 if (! mips_opts
.noreorder
)
7057 int nops
= nops_for_insn (0, history
, NULL
);
7061 add_fixed_insn (NOP_INSN
);
7062 mips_move_text_labels ();
7065 mips_no_prev_insn ();
7068 /* Start a (possibly nested) noreorder block. */
7071 start_noreorder (void)
7073 if (mips_opts
.noreorder
== 0)
7078 /* None of the instructions before the .set noreorder can be moved. */
7079 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
7080 history
[i
].fixed_p
= 1;
7082 /* Insert any nops that might be needed between the .set noreorder
7083 block and the previous instructions. We will later remove any
7084 nops that turn out not to be needed. */
7085 nops
= nops_for_insn (0, history
, NULL
);
7088 if (mips_optimize
!= 0)
7090 /* Record the frag which holds the nop instructions, so
7091 that we can remove them if we don't need them. */
7092 frag_grow (nops
* NOP_INSN_SIZE
);
7093 prev_nop_frag
= frag_now
;
7094 prev_nop_frag_holds
= nops
;
7095 prev_nop_frag_required
= 0;
7096 prev_nop_frag_since
= 0;
7099 for (; nops
> 0; --nops
)
7100 add_fixed_insn (NOP_INSN
);
7102 /* Move on to a new frag, so that it is safe to simply
7103 decrease the size of prev_nop_frag. */
7104 frag_wane (frag_now
);
7106 mips_move_text_labels ();
7108 mips_mark_labels ();
7109 mips_clear_insn_labels ();
7111 mips_opts
.noreorder
++;
7112 mips_any_noreorder
= 1;
7115 /* End a nested noreorder block. */
7118 end_noreorder (void)
7120 mips_opts
.noreorder
--;
7121 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7123 /* Commit to inserting prev_nop_frag_required nops and go back to
7124 handling nop insertion the .set reorder way. */
7125 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7127 insert_into_history (prev_nop_frag_since
,
7128 prev_nop_frag_required
, NOP_INSN
);
7129 prev_nop_frag
= NULL
;
7133 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7134 higher bits unset. */
7137 normalize_constant_expr (expressionS
*ex
)
7139 if (ex
->X_op
== O_constant
7140 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7141 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7145 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7146 all higher bits unset. */
7149 normalize_address_expr (expressionS
*ex
)
7151 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7152 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7153 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7154 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7158 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7159 Return true if the match was successful.
7161 OPCODE_EXTRA is a value that should be ORed into the opcode
7162 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7163 there are more alternatives after OPCODE and SOFT_MATCH is
7164 as for mips_arg_info. */
7167 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7168 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7169 bfd_boolean lax_match
, bfd_boolean complete_p
)
7172 struct mips_arg_info arg
;
7173 const struct mips_operand
*operand
;
7176 imm_expr
.X_op
= O_absent
;
7177 offset_expr
.X_op
= O_absent
;
7178 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7179 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7180 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7182 create_insn (insn
, opcode
);
7183 /* When no opcode suffix is specified, assume ".xyzw". */
7184 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7185 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7187 insn
->insn_opcode
|= opcode_extra
;
7188 memset (&arg
, 0, sizeof (arg
));
7192 arg
.last_regno
= ILLEGAL_REG
;
7193 arg
.dest_regno
= ILLEGAL_REG
;
7194 arg
.lax_match
= lax_match
;
7195 for (args
= opcode
->args
;; ++args
)
7197 if (arg
.token
->type
== OT_END
)
7199 /* Handle unary instructions in which only one operand is given.
7200 The source is then the same as the destination. */
7201 if (arg
.opnum
== 1 && *args
== ',')
7203 operand
= (mips_opts
.micromips
7204 ? decode_micromips_operand (args
+ 1)
7205 : decode_mips_operand (args
+ 1));
7206 if (operand
&& mips_optional_operand_p (operand
))
7214 /* Treat elided base registers as $0. */
7215 if (strcmp (args
, "(b)") == 0)
7223 /* The register suffix is optional. */
7228 /* Fail the match if there were too few operands. */
7232 /* Successful match. */
7235 clear_insn_error ();
7236 if (arg
.dest_regno
== arg
.last_regno
7237 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7241 (0, _("source and destination must be different"));
7242 else if (arg
.last_regno
== 31)
7244 (0, _("a destination register must be supplied"));
7246 else if (arg
.last_regno
== 31
7247 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
7248 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
7249 set_insn_error (0, _("the source register must not be $31"));
7250 check_completed_insn (&arg
);
7254 /* Fail the match if the line has too many operands. */
7258 /* Handle characters that need to match exactly. */
7259 if (*args
== '(' || *args
== ')' || *args
== ',')
7261 if (match_char (&arg
, *args
))
7268 if (arg
.token
->type
== OT_DOUBLE_CHAR
7269 && arg
.token
->u
.ch
== *args
)
7277 /* Handle special macro operands. Work out the properties of
7286 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7292 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7294 imm_expr
.X_op
= O_constant
;
7295 if (HAVE_32BIT_GPRS
)
7296 normalize_constant_expr (&imm_expr
);
7300 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7302 /* Assume that the offset has been elided and that what
7303 we saw was a base register. The match will fail later
7304 if that assumption turns out to be wrong. */
7305 offset_expr
.X_op
= O_constant
;
7306 offset_expr
.X_add_number
= 0;
7310 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7312 normalize_address_expr (&offset_expr
);
7317 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7323 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7329 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7335 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7341 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7345 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7349 gas_assert (mips_opts
.micromips
);
7355 if (!forced_insn_length
)
7356 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7358 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7360 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7366 operand
= (mips_opts
.micromips
7367 ? decode_micromips_operand (args
)
7368 : decode_mips_operand (args
));
7372 /* Skip prefixes. */
7373 if (*args
== '+' || *args
== 'm')
7376 if (mips_optional_operand_p (operand
)
7378 && (arg
.token
[0].type
!= OT_REG
7379 || arg
.token
[1].type
== OT_END
))
7381 /* Assume that the register has been elided and is the
7382 same as the first operand. */
7387 if (!match_operand (&arg
, operand
))
7392 /* Like match_insn, but for MIPS16. */
7395 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7396 struct mips_operand_token
*tokens
)
7399 const struct mips_operand
*operand
;
7400 const struct mips_operand
*ext_operand
;
7401 struct mips_arg_info arg
;
7404 create_insn (insn
, opcode
);
7405 imm_expr
.X_op
= O_absent
;
7406 offset_expr
.X_op
= O_absent
;
7407 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7408 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7409 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7412 memset (&arg
, 0, sizeof (arg
));
7416 arg
.last_regno
= ILLEGAL_REG
;
7417 arg
.dest_regno
= ILLEGAL_REG
;
7419 for (args
= opcode
->args
;; ++args
)
7423 if (arg
.token
->type
== OT_END
)
7427 /* Handle unary instructions in which only one operand is given.
7428 The source is then the same as the destination. */
7429 if (arg
.opnum
== 1 && *args
== ',')
7431 operand
= decode_mips16_operand (args
[1], FALSE
);
7432 if (operand
&& mips_optional_operand_p (operand
))
7440 /* Fail the match if there were too few operands. */
7444 /* Successful match. Stuff the immediate value in now, if
7446 clear_insn_error ();
7447 if (opcode
->pinfo
== INSN_MACRO
)
7449 gas_assert (relax_char
== 0 || relax_char
== 'p');
7450 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7453 && offset_expr
.X_op
== O_constant
7454 && calculate_reloc (*offset_reloc
,
7455 offset_expr
.X_add_number
,
7458 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7459 forced_insn_length
, &insn
->insn_opcode
);
7460 offset_expr
.X_op
= O_absent
;
7461 *offset_reloc
= BFD_RELOC_UNUSED
;
7463 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7465 if (forced_insn_length
== 2)
7466 set_insn_error (0, _("invalid unextended operand value"));
7467 forced_insn_length
= 4;
7468 insn
->insn_opcode
|= MIPS16_EXTEND
;
7470 else if (relax_char
)
7471 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7473 check_completed_insn (&arg
);
7477 /* Fail the match if the line has too many operands. */
7481 /* Handle characters that need to match exactly. */
7482 if (*args
== '(' || *args
== ')' || *args
== ',')
7484 if (match_char (&arg
, *args
))
7502 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7504 imm_expr
.X_op
= O_constant
;
7505 if (HAVE_32BIT_GPRS
)
7506 normalize_constant_expr (&imm_expr
);
7511 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7512 insn
->insn_opcode
<<= 16;
7516 operand
= decode_mips16_operand (c
, FALSE
);
7520 /* '6' is a special case. It is used for BREAK and SDBBP,
7521 whose operands are only meaningful to the software that decodes
7522 them. This means that there is no architectural reason why
7523 they cannot be prefixed by EXTEND, but in practice,
7524 exception handlers will only look at the instruction
7525 itself. We therefore allow '6' to be extended when
7526 disassembling but not when assembling. */
7527 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7529 ext_operand
= decode_mips16_operand (c
, TRUE
);
7530 if (operand
!= ext_operand
)
7532 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7534 offset_expr
.X_op
= O_constant
;
7535 offset_expr
.X_add_number
= 0;
7540 /* We need the OT_INTEGER check because some MIPS16
7541 immediate variants are listed before the register ones. */
7542 if (arg
.token
->type
!= OT_INTEGER
7543 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7546 /* '8' is used for SLTI(U) and has traditionally not
7547 been allowed to take relocation operators. */
7548 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7549 && (ext_operand
->size
!= 16 || c
== '8'))
7557 if (mips_optional_operand_p (operand
)
7559 && (arg
.token
[0].type
!= OT_REG
7560 || arg
.token
[1].type
== OT_END
))
7562 /* Assume that the register has been elided and is the
7563 same as the first operand. */
7568 if (!match_operand (&arg
, operand
))
7573 /* Record that the current instruction is invalid for the current ISA. */
7576 match_invalid_for_isa (void)
7579 (0, _("opcode not supported on this processor: %s (%s)"),
7580 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7581 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7584 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7585 Return true if a definite match or failure was found, storing any match
7586 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7587 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7588 tried and failed to match under normal conditions and now want to try a
7589 more relaxed match. */
7592 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7593 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
7594 int opcode_extra
, bfd_boolean lax_match
)
7596 const struct mips_opcode
*opcode
;
7597 const struct mips_opcode
*invalid_delay_slot
;
7598 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
7600 /* Search for a match, ignoring alternatives that don't satisfy the
7601 current ISA or forced_length. */
7602 invalid_delay_slot
= 0;
7603 seen_valid_for_isa
= FALSE
;
7604 seen_valid_for_size
= FALSE
;
7608 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7609 if (is_opcode_valid (opcode
))
7611 seen_valid_for_isa
= TRUE
;
7612 if (is_size_valid (opcode
))
7614 bfd_boolean delay_slot_ok
;
7616 seen_valid_for_size
= TRUE
;
7617 delay_slot_ok
= is_delay_slot_valid (opcode
);
7618 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
7619 lax_match
, delay_slot_ok
))
7623 if (!invalid_delay_slot
)
7624 invalid_delay_slot
= opcode
;
7633 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
7635 /* If the only matches we found had the wrong length for the delay slot,
7636 pick the first such match. We'll issue an appropriate warning later. */
7637 if (invalid_delay_slot
)
7639 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
7645 /* Handle the case where we didn't try to match an instruction because
7646 all the alternatives were incompatible with the current ISA. */
7647 if (!seen_valid_for_isa
)
7649 match_invalid_for_isa ();
7653 /* Handle the case where we didn't try to match an instruction because
7654 all the alternatives were of the wrong size. */
7655 if (!seen_valid_for_size
)
7657 if (mips_opts
.insn32
)
7658 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
7661 (0, _("unrecognized %d-bit version of microMIPS opcode"),
7662 8 * forced_insn_length
);
7669 /* Like match_insns, but for MIPS16. */
7672 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7673 struct mips_operand_token
*tokens
)
7675 const struct mips_opcode
*opcode
;
7676 bfd_boolean seen_valid_for_isa
;
7678 /* Search for a match, ignoring alternatives that don't satisfy the
7679 current ISA. There are no separate entries for extended forms so
7680 we deal with forced_length later. */
7681 seen_valid_for_isa
= FALSE
;
7685 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7686 if (is_opcode_valid_16 (opcode
))
7688 seen_valid_for_isa
= TRUE
;
7689 if (match_mips16_insn (insn
, opcode
, tokens
))
7694 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
7695 && strcmp (opcode
->name
, first
->name
) == 0);
7697 /* Handle the case where we didn't try to match an instruction because
7698 all the alternatives were incompatible with the current ISA. */
7699 if (!seen_valid_for_isa
)
7701 match_invalid_for_isa ();
7708 /* Set up global variables for the start of a new macro. */
7713 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7714 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7715 sizeof (mips_macro_warning
.first_insn_sizes
));
7716 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7717 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7718 && delayed_branch_p (&history
[0]));
7719 switch (history
[0].insn_mo
->pinfo2
7720 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7722 case INSN2_BRANCH_DELAY_32BIT
:
7723 mips_macro_warning
.delay_slot_length
= 4;
7725 case INSN2_BRANCH_DELAY_16BIT
:
7726 mips_macro_warning
.delay_slot_length
= 2;
7729 mips_macro_warning
.delay_slot_length
= 0;
7732 mips_macro_warning
.first_frag
= NULL
;
7735 /* Given that a macro is longer than one instruction or of the wrong size,
7736 return the appropriate warning for it. Return null if no warning is
7737 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7738 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7739 and RELAX_NOMACRO. */
7742 macro_warning (relax_substateT subtype
)
7744 if (subtype
& RELAX_DELAY_SLOT
)
7745 return _("macro instruction expanded into multiple instructions"
7746 " in a branch delay slot");
7747 else if (subtype
& RELAX_NOMACRO
)
7748 return _("macro instruction expanded into multiple instructions");
7749 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7750 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7751 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7752 ? _("macro instruction expanded into a wrong size instruction"
7753 " in a 16-bit branch delay slot")
7754 : _("macro instruction expanded into a wrong size instruction"
7755 " in a 32-bit branch delay slot"));
7760 /* Finish up a macro. Emit warnings as appropriate. */
7765 /* Relaxation warning flags. */
7766 relax_substateT subtype
= 0;
7768 /* Check delay slot size requirements. */
7769 if (mips_macro_warning
.delay_slot_length
== 2)
7770 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7771 if (mips_macro_warning
.delay_slot_length
!= 0)
7773 if (mips_macro_warning
.delay_slot_length
7774 != mips_macro_warning
.first_insn_sizes
[0])
7775 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7776 if (mips_macro_warning
.delay_slot_length
7777 != mips_macro_warning
.first_insn_sizes
[1])
7778 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7781 /* Check instruction count requirements. */
7782 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7784 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7785 subtype
|= RELAX_SECOND_LONGER
;
7786 if (mips_opts
.warn_about_macros
)
7787 subtype
|= RELAX_NOMACRO
;
7788 if (mips_macro_warning
.delay_slot_p
)
7789 subtype
|= RELAX_DELAY_SLOT
;
7792 /* If both alternatives fail to fill a delay slot correctly,
7793 emit the warning now. */
7794 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7795 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7800 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7801 | RELAX_DELAY_SLOT_SIZE_FIRST
7802 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7803 msg
= macro_warning (s
);
7805 as_warn ("%s", msg
);
7809 /* If both implementations are longer than 1 instruction, then emit the
7811 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7816 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7817 msg
= macro_warning (s
);
7819 as_warn ("%s", msg
);
7823 /* If any flags still set, then one implementation might need a warning
7824 and the other either will need one of a different kind or none at all.
7825 Pass any remaining flags over to relaxation. */
7826 if (mips_macro_warning
.first_frag
!= NULL
)
7827 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7830 /* Instruction operand formats used in macros that vary between
7831 standard MIPS and microMIPS code. */
7833 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7834 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7835 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7836 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7837 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7838 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7839 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7840 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7842 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7843 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7844 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7845 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7846 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7847 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7848 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7849 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7851 /* Read a macro's relocation codes from *ARGS and store them in *R.
7852 The first argument in *ARGS will be either the code for a single
7853 relocation or -1 followed by the three codes that make up a
7854 composite relocation. */
7857 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7861 next
= va_arg (*args
, int);
7863 r
[0] = (bfd_reloc_code_real_type
) next
;
7866 for (i
= 0; i
< 3; i
++)
7867 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7868 /* This function is only used for 16-bit relocation fields.
7869 To make the macro code simpler, treat an unrelocated value
7870 in the same way as BFD_RELOC_LO16. */
7871 if (r
[0] == BFD_RELOC_UNUSED
)
7872 r
[0] = BFD_RELOC_LO16
;
7876 /* Build an instruction created by a macro expansion. This is passed
7877 a pointer to the count of instructions created so far, an
7878 expression, the name of the instruction to build, an operand format
7879 string, and corresponding arguments. */
7882 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7884 const struct mips_opcode
*mo
= NULL
;
7885 bfd_reloc_code_real_type r
[3];
7886 const struct mips_opcode
*amo
;
7887 const struct mips_operand
*operand
;
7888 struct hash_control
*hash
;
7889 struct mips_cl_insn insn
;
7893 va_start (args
, fmt
);
7895 if (mips_opts
.mips16
)
7897 mips16_macro_build (ep
, name
, fmt
, &args
);
7902 r
[0] = BFD_RELOC_UNUSED
;
7903 r
[1] = BFD_RELOC_UNUSED
;
7904 r
[2] = BFD_RELOC_UNUSED
;
7905 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7906 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7908 gas_assert (strcmp (name
, amo
->name
) == 0);
7912 /* Search until we get a match for NAME. It is assumed here that
7913 macros will never generate MDMX, MIPS-3D, or MT instructions.
7914 We try to match an instruction that fulfils the branch delay
7915 slot instruction length requirement (if any) of the previous
7916 instruction. While doing this we record the first instruction
7917 seen that matches all the other conditions and use it anyway
7918 if the requirement cannot be met; we will issue an appropriate
7919 warning later on. */
7920 if (strcmp (fmt
, amo
->args
) == 0
7921 && amo
->pinfo
!= INSN_MACRO
7922 && is_opcode_valid (amo
)
7923 && is_size_valid (amo
))
7925 if (is_delay_slot_valid (amo
))
7935 gas_assert (amo
->name
);
7937 while (strcmp (name
, amo
->name
) == 0);
7940 create_insn (&insn
, mo
);
7953 macro_read_relocs (&args
, r
);
7954 gas_assert (*r
== BFD_RELOC_GPREL16
7955 || *r
== BFD_RELOC_MIPS_HIGHER
7956 || *r
== BFD_RELOC_HI16_S
7957 || *r
== BFD_RELOC_LO16
7958 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7962 macro_read_relocs (&args
, r
);
7966 macro_read_relocs (&args
, r
);
7967 gas_assert (ep
!= NULL
7968 && (ep
->X_op
== O_constant
7969 || (ep
->X_op
== O_symbol
7970 && (*r
== BFD_RELOC_MIPS_HIGHEST
7971 || *r
== BFD_RELOC_HI16_S
7972 || *r
== BFD_RELOC_HI16
7973 || *r
== BFD_RELOC_GPREL16
7974 || *r
== BFD_RELOC_MIPS_GOT_HI16
7975 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7979 gas_assert (ep
!= NULL
);
7982 * This allows macro() to pass an immediate expression for
7983 * creating short branches without creating a symbol.
7985 * We don't allow branch relaxation for these branches, as
7986 * they should only appear in ".set nomacro" anyway.
7988 if (ep
->X_op
== O_constant
)
7990 /* For microMIPS we always use relocations for branches.
7991 So we should not resolve immediate values. */
7992 gas_assert (!mips_opts
.micromips
);
7994 if ((ep
->X_add_number
& 3) != 0)
7995 as_bad (_("branch to misaligned address (0x%lx)"),
7996 (unsigned long) ep
->X_add_number
);
7997 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7998 as_bad (_("branch address range overflow (0x%lx)"),
7999 (unsigned long) ep
->X_add_number
);
8000 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
8004 *r
= BFD_RELOC_16_PCREL_S2
;
8008 gas_assert (ep
!= NULL
);
8009 *r
= BFD_RELOC_MIPS_JMP
;
8013 operand
= (mips_opts
.micromips
8014 ? decode_micromips_operand (fmt
)
8015 : decode_mips_operand (fmt
));
8019 uval
= va_arg (args
, int);
8020 if (operand
->type
== OP_CLO_CLZ_DEST
)
8021 uval
|= (uval
<< 5);
8022 insn_insert_operand (&insn
, operand
, uval
);
8024 if (*fmt
== '+' || *fmt
== 'm')
8030 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8032 append_insn (&insn
, ep
, r
, TRUE
);
8036 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
8039 struct mips_opcode
*mo
;
8040 struct mips_cl_insn insn
;
8041 const struct mips_operand
*operand
;
8042 bfd_reloc_code_real_type r
[3]
8043 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
8045 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
8047 gas_assert (strcmp (name
, mo
->name
) == 0);
8049 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
8052 gas_assert (mo
->name
);
8053 gas_assert (strcmp (name
, mo
->name
) == 0);
8056 create_insn (&insn
, mo
);
8094 gas_assert (ep
!= NULL
);
8096 if (ep
->X_op
!= O_constant
)
8097 *r
= (int) BFD_RELOC_UNUSED
+ c
;
8098 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
8100 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
8102 *r
= BFD_RELOC_UNUSED
;
8108 operand
= decode_mips16_operand (c
, FALSE
);
8112 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8117 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8119 append_insn (&insn
, ep
, r
, TRUE
);
8123 * Generate a "jalr" instruction with a relocation hint to the called
8124 * function. This occurs in NewABI PIC code.
8127 macro_build_jalr (expressionS
*ep
, int cprestore
)
8129 static const bfd_reloc_code_real_type jalr_relocs
[2]
8130 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8131 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8135 if (MIPS_JALR_HINT_P (ep
))
8140 if (mips_opts
.micromips
)
8142 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8143 ? "jalr" : "jalrs");
8144 if (MIPS_JALR_HINT_P (ep
)
8146 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8147 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8149 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8152 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8153 if (MIPS_JALR_HINT_P (ep
))
8154 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8158 * Generate a "lui" instruction.
8161 macro_build_lui (expressionS
*ep
, int regnum
)
8163 gas_assert (! mips_opts
.mips16
);
8165 if (ep
->X_op
!= O_constant
)
8167 gas_assert (ep
->X_op
== O_symbol
);
8168 /* _gp_disp is a special case, used from s_cpload.
8169 __gnu_local_gp is used if mips_no_shared. */
8170 gas_assert (mips_pic
== NO_PIC
8172 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8173 || (! mips_in_shared
8174 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8175 "__gnu_local_gp") == 0));
8178 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8181 /* Generate a sequence of instructions to do a load or store from a constant
8182 offset off of a base register (breg) into/from a target register (treg),
8183 using AT if necessary. */
8185 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8186 int treg
, int breg
, int dbl
)
8188 gas_assert (ep
->X_op
== O_constant
);
8190 /* Sign-extending 32-bit constants makes their handling easier. */
8192 normalize_constant_expr (ep
);
8194 /* Right now, this routine can only handle signed 32-bit constants. */
8195 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8196 as_warn (_("operand overflow"));
8198 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8200 /* Signed 16-bit offset will fit in the op. Easy! */
8201 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8205 /* 32-bit offset, need multiple instructions and AT, like:
8206 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8207 addu $tempreg,$tempreg,$breg
8208 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8209 to handle the complete offset. */
8210 macro_build_lui (ep
, AT
);
8211 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8212 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8215 as_bad (_("macro used $at after \".set noat\""));
8220 * Generates code to set the $at register to true (one)
8221 * if reg is less than the immediate expression.
8224 set_at (int reg
, int unsignedp
)
8226 if (imm_expr
.X_add_number
>= -0x8000
8227 && imm_expr
.X_add_number
< 0x8000)
8228 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8229 AT
, reg
, BFD_RELOC_LO16
);
8232 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8233 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8237 /* Count the leading zeroes by performing a binary chop. This is a
8238 bulky bit of source, but performance is a LOT better for the
8239 majority of values than a simple loop to count the bits:
8240 for (lcnt = 0; (lcnt < 32); lcnt++)
8241 if ((v) & (1 << (31 - lcnt)))
8243 However it is not code size friendly, and the gain will drop a bit
8244 on certain cached systems.
8246 #define COUNT_TOP_ZEROES(v) \
8247 (((v) & ~0xffff) == 0 \
8248 ? ((v) & ~0xff) == 0 \
8249 ? ((v) & ~0xf) == 0 \
8250 ? ((v) & ~0x3) == 0 \
8251 ? ((v) & ~0x1) == 0 \
8256 : ((v) & ~0x7) == 0 \
8259 : ((v) & ~0x3f) == 0 \
8260 ? ((v) & ~0x1f) == 0 \
8263 : ((v) & ~0x7f) == 0 \
8266 : ((v) & ~0xfff) == 0 \
8267 ? ((v) & ~0x3ff) == 0 \
8268 ? ((v) & ~0x1ff) == 0 \
8271 : ((v) & ~0x7ff) == 0 \
8274 : ((v) & ~0x3fff) == 0 \
8275 ? ((v) & ~0x1fff) == 0 \
8278 : ((v) & ~0x7fff) == 0 \
8281 : ((v) & ~0xffffff) == 0 \
8282 ? ((v) & ~0xfffff) == 0 \
8283 ? ((v) & ~0x3ffff) == 0 \
8284 ? ((v) & ~0x1ffff) == 0 \
8287 : ((v) & ~0x7ffff) == 0 \
8290 : ((v) & ~0x3fffff) == 0 \
8291 ? ((v) & ~0x1fffff) == 0 \
8294 : ((v) & ~0x7fffff) == 0 \
8297 : ((v) & ~0xfffffff) == 0 \
8298 ? ((v) & ~0x3ffffff) == 0 \
8299 ? ((v) & ~0x1ffffff) == 0 \
8302 : ((v) & ~0x7ffffff) == 0 \
8305 : ((v) & ~0x3fffffff) == 0 \
8306 ? ((v) & ~0x1fffffff) == 0 \
8309 : ((v) & ~0x7fffffff) == 0 \
8314 * This routine generates the least number of instructions necessary to load
8315 * an absolute expression value into a register.
8318 load_register (int reg
, expressionS
*ep
, int dbl
)
8321 expressionS hi32
, lo32
;
8323 if (ep
->X_op
!= O_big
)
8325 gas_assert (ep
->X_op
== O_constant
);
8327 /* Sign-extending 32-bit constants makes their handling easier. */
8329 normalize_constant_expr (ep
);
8331 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8333 /* We can handle 16 bit signed values with an addiu to
8334 $zero. No need to ever use daddiu here, since $zero and
8335 the result are always correct in 32 bit mode. */
8336 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8339 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8341 /* We can handle 16 bit unsigned values with an ori to
8343 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8346 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8348 /* 32 bit values require an lui. */
8349 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8350 if ((ep
->X_add_number
& 0xffff) != 0)
8351 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8356 /* The value is larger than 32 bits. */
8358 if (!dbl
|| HAVE_32BIT_GPRS
)
8362 sprintf_vma (value
, ep
->X_add_number
);
8363 as_bad (_("number (0x%s) larger than 32 bits"), value
);
8364 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8368 if (ep
->X_op
!= O_big
)
8371 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8372 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8373 hi32
.X_add_number
&= 0xffffffff;
8375 lo32
.X_add_number
&= 0xffffffff;
8379 gas_assert (ep
->X_add_number
> 2);
8380 if (ep
->X_add_number
== 3)
8381 generic_bignum
[3] = 0;
8382 else if (ep
->X_add_number
> 4)
8383 as_bad (_("number larger than 64 bits"));
8384 lo32
.X_op
= O_constant
;
8385 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8386 hi32
.X_op
= O_constant
;
8387 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8390 if (hi32
.X_add_number
== 0)
8395 unsigned long hi
, lo
;
8397 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8399 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8401 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8404 if (lo32
.X_add_number
& 0x80000000)
8406 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8407 if (lo32
.X_add_number
& 0xffff)
8408 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8413 /* Check for 16bit shifted constant. We know that hi32 is
8414 non-zero, so start the mask on the first bit of the hi32
8419 unsigned long himask
, lomask
;
8423 himask
= 0xffff >> (32 - shift
);
8424 lomask
= (0xffff << shift
) & 0xffffffff;
8428 himask
= 0xffff << (shift
- 32);
8431 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8432 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8436 tmp
.X_op
= O_constant
;
8438 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8439 | (lo32
.X_add_number
>> shift
));
8441 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8442 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8443 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8444 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8449 while (shift
<= (64 - 16));
8451 /* Find the bit number of the lowest one bit, and store the
8452 shifted value in hi/lo. */
8453 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8454 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8458 while ((lo
& 1) == 0)
8463 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8469 while ((hi
& 1) == 0)
8478 /* Optimize if the shifted value is a (power of 2) - 1. */
8479 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8480 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8482 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8487 /* This instruction will set the register to be all
8489 tmp
.X_op
= O_constant
;
8490 tmp
.X_add_number
= (offsetT
) -1;
8491 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8495 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8496 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8498 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8499 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8504 /* Sign extend hi32 before calling load_register, because we can
8505 generally get better code when we load a sign extended value. */
8506 if ((hi32
.X_add_number
& 0x80000000) != 0)
8507 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8508 load_register (reg
, &hi32
, 0);
8511 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8515 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8523 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8525 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8526 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8532 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8536 mid16
.X_add_number
>>= 16;
8537 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8538 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8541 if ((lo32
.X_add_number
& 0xffff) != 0)
8542 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8546 load_delay_nop (void)
8548 if (!gpr_interlocks
)
8549 macro_build (NULL
, "nop", "");
8552 /* Load an address into a register. */
8555 load_address (int reg
, expressionS
*ep
, int *used_at
)
8557 if (ep
->X_op
!= O_constant
8558 && ep
->X_op
!= O_symbol
)
8560 as_bad (_("expression too complex"));
8561 ep
->X_op
= O_constant
;
8564 if (ep
->X_op
== O_constant
)
8566 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8570 if (mips_pic
== NO_PIC
)
8572 /* If this is a reference to a GP relative symbol, we want
8573 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8575 lui $reg,<sym> (BFD_RELOC_HI16_S)
8576 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8577 If we have an addend, we always use the latter form.
8579 With 64bit address space and a usable $at we want
8580 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8581 lui $at,<sym> (BFD_RELOC_HI16_S)
8582 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8583 daddiu $at,<sym> (BFD_RELOC_LO16)
8587 If $at is already in use, we use a path which is suboptimal
8588 on superscalar processors.
8589 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8590 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8592 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8594 daddiu $reg,<sym> (BFD_RELOC_LO16)
8596 For GP relative symbols in 64bit address space we can use
8597 the same sequence as in 32bit address space. */
8598 if (HAVE_64BIT_SYMBOLS
)
8600 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8601 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8603 relax_start (ep
->X_add_symbol
);
8604 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8605 mips_gp_register
, BFD_RELOC_GPREL16
);
8609 if (*used_at
== 0 && mips_opts
.at
)
8611 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8612 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8613 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8614 BFD_RELOC_MIPS_HIGHER
);
8615 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8616 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8617 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8622 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8623 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8624 BFD_RELOC_MIPS_HIGHER
);
8625 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8626 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8627 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8628 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8631 if (mips_relax
.sequence
)
8636 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8637 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8639 relax_start (ep
->X_add_symbol
);
8640 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8641 mips_gp_register
, BFD_RELOC_GPREL16
);
8644 macro_build_lui (ep
, reg
);
8645 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8646 reg
, reg
, BFD_RELOC_LO16
);
8647 if (mips_relax
.sequence
)
8651 else if (!mips_big_got
)
8655 /* If this is a reference to an external symbol, we want
8656 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8658 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8660 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8661 If there is a constant, it must be added in after.
8663 If we have NewABI, we want
8664 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8665 unless we're referencing a global symbol with a non-zero
8666 offset, in which case cst must be added separately. */
8669 if (ep
->X_add_number
)
8671 ex
.X_add_number
= ep
->X_add_number
;
8672 ep
->X_add_number
= 0;
8673 relax_start (ep
->X_add_symbol
);
8674 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8675 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8676 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8677 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8678 ex
.X_op
= O_constant
;
8679 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8680 reg
, reg
, BFD_RELOC_LO16
);
8681 ep
->X_add_number
= ex
.X_add_number
;
8684 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8685 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8686 if (mips_relax
.sequence
)
8691 ex
.X_add_number
= ep
->X_add_number
;
8692 ep
->X_add_number
= 0;
8693 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8694 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8696 relax_start (ep
->X_add_symbol
);
8698 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8702 if (ex
.X_add_number
!= 0)
8704 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8705 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8706 ex
.X_op
= O_constant
;
8707 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8708 reg
, reg
, BFD_RELOC_LO16
);
8712 else if (mips_big_got
)
8716 /* This is the large GOT case. If this is a reference to an
8717 external symbol, we want
8718 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8720 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8722 Otherwise, for a reference to a local symbol in old ABI, we want
8723 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8725 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8726 If there is a constant, it must be added in after.
8728 In the NewABI, for local symbols, with or without offsets, we want:
8729 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8730 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8734 ex
.X_add_number
= ep
->X_add_number
;
8735 ep
->X_add_number
= 0;
8736 relax_start (ep
->X_add_symbol
);
8737 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8738 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8739 reg
, reg
, mips_gp_register
);
8740 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8741 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8742 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8743 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8744 else if (ex
.X_add_number
)
8746 ex
.X_op
= O_constant
;
8747 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8751 ep
->X_add_number
= ex
.X_add_number
;
8753 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8754 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8755 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8756 BFD_RELOC_MIPS_GOT_OFST
);
8761 ex
.X_add_number
= ep
->X_add_number
;
8762 ep
->X_add_number
= 0;
8763 relax_start (ep
->X_add_symbol
);
8764 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8765 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8766 reg
, reg
, mips_gp_register
);
8767 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8768 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8770 if (reg_needs_delay (mips_gp_register
))
8772 /* We need a nop before loading from $gp. This special
8773 check is required because the lui which starts the main
8774 instruction stream does not refer to $gp, and so will not
8775 insert the nop which may be required. */
8776 macro_build (NULL
, "nop", "");
8778 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8779 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8781 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8785 if (ex
.X_add_number
!= 0)
8787 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8788 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8789 ex
.X_op
= O_constant
;
8790 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8798 if (!mips_opts
.at
&& *used_at
== 1)
8799 as_bad (_("macro used $at after \".set noat\""));
8802 /* Move the contents of register SOURCE into register DEST. */
8805 move_register (int dest
, int source
)
8807 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8808 instruction specifically requires a 32-bit one. */
8809 if (mips_opts
.micromips
8810 && !mips_opts
.insn32
8811 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8812 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8814 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8818 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8819 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8820 The two alternatives are:
8822 Global symbol Local sybmol
8823 ------------- ------------
8824 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8826 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8828 load_got_offset emits the first instruction and add_got_offset
8829 emits the second for a 16-bit offset or add_got_offset_hilo emits
8830 a sequence to add a 32-bit offset using a scratch register. */
8833 load_got_offset (int dest
, expressionS
*local
)
8838 global
.X_add_number
= 0;
8840 relax_start (local
->X_add_symbol
);
8841 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8842 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8844 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8845 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8850 add_got_offset (int dest
, expressionS
*local
)
8854 global
.X_op
= O_constant
;
8855 global
.X_op_symbol
= NULL
;
8856 global
.X_add_symbol
= NULL
;
8857 global
.X_add_number
= local
->X_add_number
;
8859 relax_start (local
->X_add_symbol
);
8860 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8861 dest
, dest
, BFD_RELOC_LO16
);
8863 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8868 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8871 int hold_mips_optimize
;
8873 global
.X_op
= O_constant
;
8874 global
.X_op_symbol
= NULL
;
8875 global
.X_add_symbol
= NULL
;
8876 global
.X_add_number
= local
->X_add_number
;
8878 relax_start (local
->X_add_symbol
);
8879 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8881 /* Set mips_optimize around the lui instruction to avoid
8882 inserting an unnecessary nop after the lw. */
8883 hold_mips_optimize
= mips_optimize
;
8885 macro_build_lui (&global
, tmp
);
8886 mips_optimize
= hold_mips_optimize
;
8887 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8893 /* Emit a sequence of instructions to emulate a branch likely operation.
8894 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8895 is its complementing branch with the original condition negated.
8896 CALL is set if the original branch specified the link operation.
8897 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8899 Code like this is produced in the noreorder mode:
8904 delay slot (executed only if branch taken)
8912 delay slot (executed only if branch taken)
8915 In the reorder mode the delay slot would be filled with a nop anyway,
8916 so code produced is simply:
8921 This function is used when producing code for the microMIPS ASE that
8922 does not implement branch likely instructions in hardware. */
8925 macro_build_branch_likely (const char *br
, const char *brneg
,
8926 int call
, expressionS
*ep
, const char *fmt
,
8927 unsigned int sreg
, unsigned int treg
)
8929 int noreorder
= mips_opts
.noreorder
;
8932 gas_assert (mips_opts
.micromips
);
8936 micromips_label_expr (&expr1
);
8937 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8938 macro_build (NULL
, "nop", "");
8939 macro_build (ep
, call
? "bal" : "b", "p");
8941 /* Set to true so that append_insn adds a label. */
8942 emit_branch_likely_macro
= TRUE
;
8946 macro_build (ep
, br
, fmt
, sreg
, treg
);
8947 macro_build (NULL
, "nop", "");
8952 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8953 the condition code tested. EP specifies the branch target. */
8956 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8983 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8986 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8987 the register tested. EP specifies the branch target. */
8990 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8992 const char *brneg
= NULL
;
9002 br
= mips_opts
.micromips
? "bgez" : "bgezl";
9006 gas_assert (mips_opts
.micromips
);
9007 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
9015 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
9022 br
= mips_opts
.micromips
? "blez" : "blezl";
9029 br
= mips_opts
.micromips
? "bltz" : "bltzl";
9033 gas_assert (mips_opts
.micromips
);
9034 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
9041 if (mips_opts
.micromips
&& brneg
)
9042 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
9044 macro_build (ep
, br
, "s,p", sreg
);
9047 /* Emit a three-argument branch macro specified by TYPE, using SREG and
9048 TREG as the registers tested. EP specifies the branch target. */
9051 macro_build_branch_rsrt (int type
, expressionS
*ep
,
9052 unsigned int sreg
, unsigned int treg
)
9054 const char *brneg
= NULL
;
9066 br
= mips_opts
.micromips
? "beq" : "beql";
9075 br
= mips_opts
.micromips
? "bne" : "bnel";
9081 if (mips_opts
.micromips
&& brneg
)
9082 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
9084 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
9087 /* Return the high part that should be loaded in order to make the low
9088 part of VALUE accessible using an offset of OFFBITS bits. */
9091 offset_high_part (offsetT value
, unsigned int offbits
)
9098 bias
= 1 << (offbits
- 1);
9099 low_mask
= bias
* 2 - 1;
9100 return (value
+ bias
) & ~low_mask
;
9103 /* Return true if the value stored in offset_expr and offset_reloc
9104 fits into a signed offset of OFFBITS bits. RANGE is the maximum
9105 amount that the caller wants to add without inducing overflow
9106 and ALIGN is the known alignment of the value in bytes. */
9109 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9113 /* Accept any relocation operator if overflow isn't a concern. */
9114 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9117 /* These relocations are guaranteed not to overflow in correct links. */
9118 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9119 || gprel16_reloc_p (*offset_reloc
))
9122 if (offset_expr
.X_op
== O_constant
9123 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9124 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9131 * This routine implements the seemingly endless macro or synthesized
9132 * instructions and addressing modes in the mips assembly language. Many
9133 * of these macros are simple and are similar to each other. These could
9134 * probably be handled by some kind of table or grammar approach instead of
9135 * this verbose method. Others are not simple macros but are more like
9136 * optimizing code generation.
9137 * One interesting optimization is when several store macros appear
9138 * consecutively that would load AT with the upper half of the same address.
9139 * The ensuing load upper instructions are ommited. This implies some kind
9140 * of global optimization. We currently only optimize within a single macro.
9141 * For many of the load and store macros if the address is specified as a
9142 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9143 * first load register 'at' with zero and use it as the base register. The
9144 * mips assembler simply uses register $zero. Just one tiny optimization
9148 macro (struct mips_cl_insn
*ip
, char *str
)
9150 const struct mips_operand_array
*operands
;
9151 unsigned int breg
, i
;
9152 unsigned int tempreg
;
9155 expressionS label_expr
;
9170 bfd_boolean large_offset
;
9172 int hold_mips_optimize
;
9174 unsigned int op
[MAX_OPERANDS
];
9176 gas_assert (! mips_opts
.mips16
);
9178 operands
= insn_operands (ip
);
9179 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9180 if (operands
->operand
[i
])
9181 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9185 mask
= ip
->insn_mo
->mask
;
9187 label_expr
.X_op
= O_constant
;
9188 label_expr
.X_op_symbol
= NULL
;
9189 label_expr
.X_add_symbol
= NULL
;
9190 label_expr
.X_add_number
= 0;
9192 expr1
.X_op
= O_constant
;
9193 expr1
.X_op_symbol
= NULL
;
9194 expr1
.X_add_symbol
= NULL
;
9195 expr1
.X_add_number
= 1;
9211 if (mips_opts
.micromips
)
9212 micromips_label_expr (&label_expr
);
9214 label_expr
.X_add_number
= 8;
9215 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9217 macro_build (NULL
, "nop", "");
9219 move_register (op
[0], op
[1]);
9220 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9221 if (mips_opts
.micromips
)
9222 micromips_add_label ();
9239 if (!mips_opts
.micromips
)
9241 if (imm_expr
.X_add_number
>= -0x200
9242 && imm_expr
.X_add_number
< 0x200)
9244 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
9245 (int) imm_expr
.X_add_number
);
9254 if (imm_expr
.X_add_number
>= -0x8000
9255 && imm_expr
.X_add_number
< 0x8000)
9257 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9262 load_register (AT
, &imm_expr
, dbl
);
9263 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9282 if (imm_expr
.X_add_number
>= 0
9283 && imm_expr
.X_add_number
< 0x10000)
9285 if (mask
!= M_NOR_I
)
9286 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9289 macro_build (&imm_expr
, "ori", "t,r,i",
9290 op
[0], op
[1], BFD_RELOC_LO16
);
9291 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9297 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9298 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9302 switch (imm_expr
.X_add_number
)
9305 macro_build (NULL
, "nop", "");
9308 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9312 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9313 (int) imm_expr
.X_add_number
);
9316 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9317 (unsigned long) imm_expr
.X_add_number
);
9326 gas_assert (mips_opts
.micromips
);
9327 macro_build_branch_ccl (mask
, &offset_expr
,
9328 EXTRACT_OPERAND (1, BCC
, *ip
));
9335 if (imm_expr
.X_add_number
== 0)
9341 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9346 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9353 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9354 else if (op
[0] == 0)
9355 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9359 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9360 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9361 &offset_expr
, AT
, ZERO
);
9371 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9377 /* Check for > max integer. */
9378 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9381 /* Result is always false. */
9383 macro_build (NULL
, "nop", "");
9385 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9388 ++imm_expr
.X_add_number
;
9392 if (mask
== M_BGEL_I
)
9394 if (imm_expr
.X_add_number
== 0)
9396 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9397 &offset_expr
, op
[0]);
9400 if (imm_expr
.X_add_number
== 1)
9402 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9403 &offset_expr
, op
[0]);
9406 if (imm_expr
.X_add_number
<= GPR_SMIN
)
9409 /* result is always true */
9410 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
9411 macro_build (&offset_expr
, "b", "p");
9416 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9417 &offset_expr
, AT
, ZERO
);
9425 else if (op
[0] == 0)
9426 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9427 &offset_expr
, ZERO
, op
[1]);
9431 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9432 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9433 &offset_expr
, AT
, ZERO
);
9442 && imm_expr
.X_add_number
== -1))
9444 ++imm_expr
.X_add_number
;
9448 if (mask
== M_BGEUL_I
)
9450 if (imm_expr
.X_add_number
== 0)
9452 else if (imm_expr
.X_add_number
== 1)
9453 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9454 &offset_expr
, op
[0], ZERO
);
9459 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9460 &offset_expr
, AT
, ZERO
);
9468 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9469 else if (op
[0] == 0)
9470 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9474 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9475 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9476 &offset_expr
, AT
, ZERO
);
9484 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9485 &offset_expr
, op
[0], ZERO
);
9486 else if (op
[0] == 0)
9491 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9492 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9493 &offset_expr
, AT
, ZERO
);
9501 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9502 else if (op
[0] == 0)
9503 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9507 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9508 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9509 &offset_expr
, AT
, ZERO
);
9516 if (imm_expr
.X_add_number
>= GPR_SMAX
)
9518 ++imm_expr
.X_add_number
;
9522 if (mask
== M_BLTL_I
)
9524 if (imm_expr
.X_add_number
== 0)
9525 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9526 else if (imm_expr
.X_add_number
== 1)
9527 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9532 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9533 &offset_expr
, AT
, ZERO
);
9541 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9542 &offset_expr
, op
[0], ZERO
);
9543 else if (op
[0] == 0)
9548 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9549 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9550 &offset_expr
, AT
, ZERO
);
9559 && imm_expr
.X_add_number
== -1))
9561 ++imm_expr
.X_add_number
;
9565 if (mask
== M_BLTUL_I
)
9567 if (imm_expr
.X_add_number
== 0)
9569 else if (imm_expr
.X_add_number
== 1)
9570 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9571 &offset_expr
, op
[0], ZERO
);
9576 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9577 &offset_expr
, AT
, ZERO
);
9585 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9586 else if (op
[0] == 0)
9587 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9591 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9592 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9593 &offset_expr
, AT
, ZERO
);
9602 else if (op
[0] == 0)
9603 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9604 &offset_expr
, ZERO
, op
[1]);
9608 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9609 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9610 &offset_expr
, AT
, ZERO
);
9626 as_warn (_("divide by zero"));
9628 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9630 macro_build (NULL
, "break", BRK_FMT
, 7);
9637 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9638 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9642 if (mips_opts
.micromips
)
9643 micromips_label_expr (&label_expr
);
9645 label_expr
.X_add_number
= 8;
9646 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9647 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9648 macro_build (NULL
, "break", BRK_FMT
, 7);
9649 if (mips_opts
.micromips
)
9650 micromips_add_label ();
9652 expr1
.X_add_number
= -1;
9654 load_register (AT
, &expr1
, dbl
);
9655 if (mips_opts
.micromips
)
9656 micromips_label_expr (&label_expr
);
9658 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9659 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9662 expr1
.X_add_number
= 1;
9663 load_register (AT
, &expr1
, dbl
);
9664 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9668 expr1
.X_add_number
= 0x80000000;
9669 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9673 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9674 /* We want to close the noreorder block as soon as possible, so
9675 that later insns are available for delay slot filling. */
9680 if (mips_opts
.micromips
)
9681 micromips_label_expr (&label_expr
);
9683 label_expr
.X_add_number
= 8;
9684 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9685 macro_build (NULL
, "nop", "");
9687 /* We want to close the noreorder block as soon as possible, so
9688 that later insns are available for delay slot filling. */
9691 macro_build (NULL
, "break", BRK_FMT
, 6);
9693 if (mips_opts
.micromips
)
9694 micromips_add_label ();
9695 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9734 if (imm_expr
.X_add_number
== 0)
9736 as_warn (_("divide by zero"));
9738 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9740 macro_build (NULL
, "break", BRK_FMT
, 7);
9743 if (imm_expr
.X_add_number
== 1)
9745 if (strcmp (s2
, "mflo") == 0)
9746 move_register (op
[0], op
[1]);
9748 move_register (op
[0], ZERO
);
9751 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
9753 if (strcmp (s2
, "mflo") == 0)
9754 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9756 move_register (op
[0], ZERO
);
9761 load_register (AT
, &imm_expr
, dbl
);
9762 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9763 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9785 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9786 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9787 /* We want to close the noreorder block as soon as possible, so
9788 that later insns are available for delay slot filling. */
9793 if (mips_opts
.micromips
)
9794 micromips_label_expr (&label_expr
);
9796 label_expr
.X_add_number
= 8;
9797 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9798 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9800 /* We want to close the noreorder block as soon as possible, so
9801 that later insns are available for delay slot filling. */
9803 macro_build (NULL
, "break", BRK_FMT
, 7);
9804 if (mips_opts
.micromips
)
9805 micromips_add_label ();
9807 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9819 /* Load the address of a symbol into a register. If breg is not
9820 zero, we then add a base register to it. */
9823 if (dbl
&& HAVE_32BIT_GPRS
)
9824 as_warn (_("dla used to load 32-bit register"));
9826 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9827 as_warn (_("la used to load 64-bit address"));
9829 if (small_offset_p (0, align
, 16))
9831 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9832 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9836 if (mips_opts
.at
&& (op
[0] == breg
))
9844 if (offset_expr
.X_op
!= O_symbol
9845 && offset_expr
.X_op
!= O_constant
)
9847 as_bad (_("expression too complex"));
9848 offset_expr
.X_op
= O_constant
;
9851 if (offset_expr
.X_op
== O_constant
)
9852 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9853 else if (mips_pic
== NO_PIC
)
9855 /* If this is a reference to a GP relative symbol, we want
9856 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9858 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9859 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9860 If we have a constant, we need two instructions anyhow,
9861 so we may as well always use the latter form.
9863 With 64bit address space and a usable $at we want
9864 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9865 lui $at,<sym> (BFD_RELOC_HI16_S)
9866 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9867 daddiu $at,<sym> (BFD_RELOC_LO16)
9869 daddu $tempreg,$tempreg,$at
9871 If $at is already in use, we use a path which is suboptimal
9872 on superscalar processors.
9873 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9874 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9876 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9878 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9880 For GP relative symbols in 64bit address space we can use
9881 the same sequence as in 32bit address space. */
9882 if (HAVE_64BIT_SYMBOLS
)
9884 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9885 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9887 relax_start (offset_expr
.X_add_symbol
);
9888 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9889 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9893 if (used_at
== 0 && mips_opts
.at
)
9895 macro_build (&offset_expr
, "lui", LUI_FMT
,
9896 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9897 macro_build (&offset_expr
, "lui", LUI_FMT
,
9898 AT
, BFD_RELOC_HI16_S
);
9899 macro_build (&offset_expr
, "daddiu", "t,r,j",
9900 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9901 macro_build (&offset_expr
, "daddiu", "t,r,j",
9902 AT
, AT
, BFD_RELOC_LO16
);
9903 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9904 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9909 macro_build (&offset_expr
, "lui", LUI_FMT
,
9910 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9911 macro_build (&offset_expr
, "daddiu", "t,r,j",
9912 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9913 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9914 macro_build (&offset_expr
, "daddiu", "t,r,j",
9915 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9916 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9917 macro_build (&offset_expr
, "daddiu", "t,r,j",
9918 tempreg
, tempreg
, BFD_RELOC_LO16
);
9921 if (mips_relax
.sequence
)
9926 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9927 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9929 relax_start (offset_expr
.X_add_symbol
);
9930 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9931 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9934 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9935 as_bad (_("offset too large"));
9936 macro_build_lui (&offset_expr
, tempreg
);
9937 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9938 tempreg
, tempreg
, BFD_RELOC_LO16
);
9939 if (mips_relax
.sequence
)
9943 else if (!mips_big_got
&& !HAVE_NEWABI
)
9945 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9947 /* If this is a reference to an external symbol, and there
9948 is no constant, we want
9949 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9950 or for lca or if tempreg is PIC_CALL_REG
9951 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9952 For a local symbol, we want
9953 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9955 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9957 If we have a small constant, and this is a reference to
9958 an external symbol, we want
9959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9961 addiu $tempreg,$tempreg,<constant>
9962 For a local symbol, we want the same instruction
9963 sequence, but we output a BFD_RELOC_LO16 reloc on the
9966 If we have a large constant, and this is a reference to
9967 an external symbol, we want
9968 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9969 lui $at,<hiconstant>
9970 addiu $at,$at,<loconstant>
9971 addu $tempreg,$tempreg,$at
9972 For a local symbol, we want the same instruction
9973 sequence, but we output a BFD_RELOC_LO16 reloc on the
9977 if (offset_expr
.X_add_number
== 0)
9979 if (mips_pic
== SVR4_PIC
9981 && (call
|| tempreg
== PIC_CALL_REG
))
9982 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9984 relax_start (offset_expr
.X_add_symbol
);
9985 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9986 lw_reloc_type
, mips_gp_register
);
9989 /* We're going to put in an addu instruction using
9990 tempreg, so we may as well insert the nop right
9995 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9996 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9998 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9999 tempreg
, tempreg
, BFD_RELOC_LO16
);
10001 /* FIXME: If breg == 0, and the next instruction uses
10002 $tempreg, then if this variant case is used an extra
10003 nop will be generated. */
10005 else if (offset_expr
.X_add_number
>= -0x8000
10006 && offset_expr
.X_add_number
< 0x8000)
10008 load_got_offset (tempreg
, &offset_expr
);
10010 add_got_offset (tempreg
, &offset_expr
);
10014 expr1
.X_add_number
= offset_expr
.X_add_number
;
10015 offset_expr
.X_add_number
=
10016 SEXT_16BIT (offset_expr
.X_add_number
);
10017 load_got_offset (tempreg
, &offset_expr
);
10018 offset_expr
.X_add_number
= expr1
.X_add_number
;
10019 /* If we are going to add in a base register, and the
10020 target register and the base register are the same,
10021 then we are using AT as a temporary register. Since
10022 we want to load the constant into AT, we add our
10023 current AT (from the global offset table) and the
10024 register into the register now, and pretend we were
10025 not using a base register. */
10029 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10034 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10038 else if (!mips_big_got
&& HAVE_NEWABI
)
10040 int add_breg_early
= 0;
10042 /* If this is a reference to an external, and there is no
10043 constant, or local symbol (*), with or without a
10045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10046 or for lca or if tempreg is PIC_CALL_REG
10047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10049 If we have a small constant, and this is a reference to
10050 an external symbol, we want
10051 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10052 addiu $tempreg,$tempreg,<constant>
10054 If we have a large constant, and this is a reference to
10055 an external symbol, we want
10056 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10057 lui $at,<hiconstant>
10058 addiu $at,$at,<loconstant>
10059 addu $tempreg,$tempreg,$at
10061 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10062 local symbols, even though it introduces an additional
10065 if (offset_expr
.X_add_number
)
10067 expr1
.X_add_number
= offset_expr
.X_add_number
;
10068 offset_expr
.X_add_number
= 0;
10070 relax_start (offset_expr
.X_add_symbol
);
10071 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10072 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10074 if (expr1
.X_add_number
>= -0x8000
10075 && expr1
.X_add_number
< 0x8000)
10077 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10078 tempreg
, tempreg
, BFD_RELOC_LO16
);
10080 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10084 /* If we are going to add in a base register, and the
10085 target register and the base register are the same,
10086 then we are using AT as a temporary register. Since
10087 we want to load the constant into AT, we add our
10088 current AT (from the global offset table) and the
10089 register into the register now, and pretend we were
10090 not using a base register. */
10095 gas_assert (tempreg
== AT
);
10096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10099 add_breg_early
= 1;
10102 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10109 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10112 offset_expr
.X_add_number
= expr1
.X_add_number
;
10114 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10115 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10116 if (add_breg_early
)
10118 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10119 op
[0], tempreg
, breg
);
10125 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10127 relax_start (offset_expr
.X_add_symbol
);
10128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10129 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10131 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10132 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10137 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10138 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10141 else if (mips_big_got
&& !HAVE_NEWABI
)
10144 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10145 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10146 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10148 /* This is the large GOT case. If this is a reference to an
10149 external symbol, and there is no constant, we want
10150 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10151 addu $tempreg,$tempreg,$gp
10152 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10153 or for lca or if tempreg is PIC_CALL_REG
10154 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10155 addu $tempreg,$tempreg,$gp
10156 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10157 For a local symbol, we want
10158 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10160 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10162 If we have a small constant, and this is a reference to
10163 an external symbol, we want
10164 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10165 addu $tempreg,$tempreg,$gp
10166 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10168 addiu $tempreg,$tempreg,<constant>
10169 For a local symbol, we want
10170 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10172 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10174 If we have a large constant, and this is a reference to
10175 an external symbol, we want
10176 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10177 addu $tempreg,$tempreg,$gp
10178 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10179 lui $at,<hiconstant>
10180 addiu $at,$at,<loconstant>
10181 addu $tempreg,$tempreg,$at
10182 For a local symbol, we want
10183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10184 lui $at,<hiconstant>
10185 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10186 addu $tempreg,$tempreg,$at
10189 expr1
.X_add_number
= offset_expr
.X_add_number
;
10190 offset_expr
.X_add_number
= 0;
10191 relax_start (offset_expr
.X_add_symbol
);
10192 gpdelay
= reg_needs_delay (mips_gp_register
);
10193 if (expr1
.X_add_number
== 0 && breg
== 0
10194 && (call
|| tempreg
== PIC_CALL_REG
))
10196 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10197 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10199 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10200 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10201 tempreg
, tempreg
, mips_gp_register
);
10202 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10203 tempreg
, lw_reloc_type
, tempreg
);
10204 if (expr1
.X_add_number
== 0)
10208 /* We're going to put in an addu instruction using
10209 tempreg, so we may as well insert the nop right
10214 else if (expr1
.X_add_number
>= -0x8000
10215 && expr1
.X_add_number
< 0x8000)
10218 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10219 tempreg
, tempreg
, BFD_RELOC_LO16
);
10225 /* If we are going to add in a base register, and the
10226 target register and the base register are the same,
10227 then we are using AT as a temporary register. Since
10228 we want to load the constant into AT, we add our
10229 current AT (from the global offset table) and the
10230 register into the register now, and pretend we were
10231 not using a base register. */
10236 gas_assert (tempreg
== AT
);
10238 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10243 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10244 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10248 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10253 /* This is needed because this instruction uses $gp, but
10254 the first instruction on the main stream does not. */
10255 macro_build (NULL
, "nop", "");
10258 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10259 local_reloc_type
, mips_gp_register
);
10260 if (expr1
.X_add_number
>= -0x8000
10261 && expr1
.X_add_number
< 0x8000)
10264 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10265 tempreg
, tempreg
, BFD_RELOC_LO16
);
10266 /* FIXME: If add_number is 0, and there was no base
10267 register, the external symbol case ended with a load,
10268 so if the symbol turns out to not be external, and
10269 the next instruction uses tempreg, an unnecessary nop
10270 will be inserted. */
10276 /* We must add in the base register now, as in the
10277 external symbol case. */
10278 gas_assert (tempreg
== AT
);
10280 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10283 /* We set breg to 0 because we have arranged to add
10284 it in in both cases. */
10288 macro_build_lui (&expr1
, AT
);
10289 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10290 AT
, AT
, BFD_RELOC_LO16
);
10291 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10292 tempreg
, tempreg
, AT
);
10297 else if (mips_big_got
&& HAVE_NEWABI
)
10299 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10300 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10301 int add_breg_early
= 0;
10303 /* This is the large GOT case. If this is a reference to an
10304 external symbol, and there is no constant, we want
10305 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10306 add $tempreg,$tempreg,$gp
10307 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10308 or for lca or if tempreg is PIC_CALL_REG
10309 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10310 add $tempreg,$tempreg,$gp
10311 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10313 If we have a small constant, and this is a reference to
10314 an external symbol, we want
10315 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10316 add $tempreg,$tempreg,$gp
10317 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10318 addi $tempreg,$tempreg,<constant>
10320 If we have a large constant, and this is a reference to
10321 an external symbol, we want
10322 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10323 addu $tempreg,$tempreg,$gp
10324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10325 lui $at,<hiconstant>
10326 addi $at,$at,<loconstant>
10327 add $tempreg,$tempreg,$at
10329 If we have NewABI, and we know it's a local symbol, we want
10330 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10331 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10332 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10334 relax_start (offset_expr
.X_add_symbol
);
10336 expr1
.X_add_number
= offset_expr
.X_add_number
;
10337 offset_expr
.X_add_number
= 0;
10339 if (expr1
.X_add_number
== 0 && breg
== 0
10340 && (call
|| tempreg
== PIC_CALL_REG
))
10342 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10343 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10345 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10346 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10347 tempreg
, tempreg
, mips_gp_register
);
10348 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10349 tempreg
, lw_reloc_type
, tempreg
);
10351 if (expr1
.X_add_number
== 0)
10353 else if (expr1
.X_add_number
>= -0x8000
10354 && expr1
.X_add_number
< 0x8000)
10356 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10357 tempreg
, tempreg
, BFD_RELOC_LO16
);
10359 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10363 /* If we are going to add in a base register, and the
10364 target register and the base register are the same,
10365 then we are using AT as a temporary register. Since
10366 we want to load the constant into AT, we add our
10367 current AT (from the global offset table) and the
10368 register into the register now, and pretend we were
10369 not using a base register. */
10374 gas_assert (tempreg
== AT
);
10375 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10378 add_breg_early
= 1;
10381 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10387 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10390 offset_expr
.X_add_number
= expr1
.X_add_number
;
10391 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10392 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10393 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10394 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10395 if (add_breg_early
)
10397 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10398 op
[0], tempreg
, breg
);
10408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10412 gas_assert (!mips_opts
.micromips
);
10413 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10417 gas_assert (!mips_opts
.micromips
);
10418 macro_build (NULL
, "c2", "C", 0x02);
10422 gas_assert (!mips_opts
.micromips
);
10423 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10427 gas_assert (!mips_opts
.micromips
);
10428 macro_build (NULL
, "c2", "C", 3);
10432 gas_assert (!mips_opts
.micromips
);
10433 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10437 /* The j instruction may not be used in PIC code, since it
10438 requires an absolute address. We convert it to a b
10440 if (mips_pic
== NO_PIC
)
10441 macro_build (&offset_expr
, "j", "a");
10443 macro_build (&offset_expr
, "b", "p");
10446 /* The jal instructions must be handled as macros because when
10447 generating PIC code they expand to multi-instruction
10448 sequences. Normally they are simple instructions. */
10452 /* Fall through. */
10454 gas_assert (mips_opts
.micromips
);
10455 if (mips_opts
.insn32
)
10457 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10465 /* Fall through. */
10468 if (mips_pic
== NO_PIC
)
10470 s
= jals
? "jalrs" : "jalr";
10471 if (mips_opts
.micromips
10472 && !mips_opts
.insn32
10474 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10475 macro_build (NULL
, s
, "mj", op
[1]);
10477 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10481 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10482 && mips_cprestore_offset
>= 0);
10484 if (op
[1] != PIC_CALL_REG
)
10485 as_warn (_("MIPS PIC call to register other than $25"));
10487 s
= ((mips_opts
.micromips
10488 && !mips_opts
.insn32
10489 && (!mips_opts
.noreorder
|| cprestore
))
10490 ? "jalrs" : "jalr");
10491 if (mips_opts
.micromips
10492 && !mips_opts
.insn32
10494 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10495 macro_build (NULL
, s
, "mj", op
[1]);
10497 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10498 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10500 if (mips_cprestore_offset
< 0)
10501 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10504 if (!mips_frame_reg_valid
)
10506 as_warn (_("no .frame pseudo-op used in PIC code"));
10507 /* Quiet this warning. */
10508 mips_frame_reg_valid
= 1;
10510 if (!mips_cprestore_valid
)
10512 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10513 /* Quiet this warning. */
10514 mips_cprestore_valid
= 1;
10516 if (mips_opts
.noreorder
)
10517 macro_build (NULL
, "nop", "");
10518 expr1
.X_add_number
= mips_cprestore_offset
;
10519 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10522 HAVE_64BIT_ADDRESSES
);
10530 gas_assert (mips_opts
.micromips
);
10531 if (mips_opts
.insn32
)
10533 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
10537 /* Fall through. */
10539 if (mips_pic
== NO_PIC
)
10540 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10541 else if (mips_pic
== SVR4_PIC
)
10543 /* If this is a reference to an external symbol, and we are
10544 using a small GOT, we want
10545 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10549 lw $gp,cprestore($sp)
10550 The cprestore value is set using the .cprestore
10551 pseudo-op. If we are using a big GOT, we want
10552 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10554 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10558 lw $gp,cprestore($sp)
10559 If the symbol is not external, we want
10560 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10562 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10565 lw $gp,cprestore($sp)
10567 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10568 sequences above, minus nops, unless the symbol is local,
10569 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10575 relax_start (offset_expr
.X_add_symbol
);
10576 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10577 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10580 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10581 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10587 relax_start (offset_expr
.X_add_symbol
);
10588 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10589 BFD_RELOC_MIPS_CALL_HI16
);
10590 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10591 PIC_CALL_REG
, mips_gp_register
);
10592 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10593 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10596 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10597 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10599 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10600 PIC_CALL_REG
, PIC_CALL_REG
,
10601 BFD_RELOC_MIPS_GOT_OFST
);
10605 macro_build_jalr (&offset_expr
, 0);
10609 relax_start (offset_expr
.X_add_symbol
);
10612 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10613 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10622 gpdelay
= reg_needs_delay (mips_gp_register
);
10623 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10624 BFD_RELOC_MIPS_CALL_HI16
);
10625 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10626 PIC_CALL_REG
, mips_gp_register
);
10627 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10628 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10633 macro_build (NULL
, "nop", "");
10635 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10636 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10639 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10640 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10642 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10644 if (mips_cprestore_offset
< 0)
10645 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10648 if (!mips_frame_reg_valid
)
10650 as_warn (_("no .frame pseudo-op used in PIC code"));
10651 /* Quiet this warning. */
10652 mips_frame_reg_valid
= 1;
10654 if (!mips_cprestore_valid
)
10656 as_warn (_("no .cprestore pseudo-op used in PIC code"));
10657 /* Quiet this warning. */
10658 mips_cprestore_valid
= 1;
10660 if (mips_opts
.noreorder
)
10661 macro_build (NULL
, "nop", "");
10662 expr1
.X_add_number
= mips_cprestore_offset
;
10663 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10666 HAVE_64BIT_ADDRESSES
);
10670 else if (mips_pic
== VXWORKS_PIC
)
10671 as_bad (_("non-PIC jump used in PIC library"));
10778 gas_assert (!mips_opts
.micromips
);
10781 /* Itbl support may require additional care here. */
10787 /* Itbl support may require additional care here. */
10793 offbits
= (mips_opts
.micromips
? 12 : 16);
10794 /* Itbl support may require additional care here. */
10798 gas_assert (!mips_opts
.micromips
);
10801 /* Itbl support may require additional care here. */
10807 offbits
= (mips_opts
.micromips
? 12 : 16);
10812 offbits
= (mips_opts
.micromips
? 12 : 16);
10817 /* Itbl support may require additional care here. */
10823 offbits
= (mips_opts
.micromips
? 12 : 16);
10824 /* Itbl support may require additional care here. */
10830 /* Itbl support may require additional care here. */
10836 /* Itbl support may require additional care here. */
10842 offbits
= (mips_opts
.micromips
? 12 : 16);
10847 offbits
= (mips_opts
.micromips
? 12 : 16);
10852 offbits
= (mips_opts
.micromips
? 12 : 16);
10857 offbits
= (mips_opts
.micromips
? 12 : 16);
10862 offbits
= (mips_opts
.micromips
? 12 : 16);
10865 gas_assert (mips_opts
.micromips
);
10872 gas_assert (mips_opts
.micromips
);
10879 gas_assert (mips_opts
.micromips
);
10885 gas_assert (mips_opts
.micromips
);
10892 /* We don't want to use $0 as tempreg. */
10893 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10896 tempreg
= op
[0] + lp
;
10912 gas_assert (!mips_opts
.micromips
);
10915 /* Itbl support may require additional care here. */
10921 /* Itbl support may require additional care here. */
10927 offbits
= (mips_opts
.micromips
? 12 : 16);
10928 /* Itbl support may require additional care here. */
10932 gas_assert (!mips_opts
.micromips
);
10935 /* Itbl support may require additional care here. */
10941 offbits
= (mips_opts
.micromips
? 12 : 16);
10946 offbits
= (mips_opts
.micromips
? 12 : 16);
10951 offbits
= (mips_opts
.micromips
? 12 : 16);
10956 offbits
= (mips_opts
.micromips
? 12 : 16);
10960 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10961 offbits
= (mips_opts
.micromips
? 12 : 16);
10970 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10971 offbits
= (mips_opts
.micromips
? 12 : 16);
10982 /* Itbl support may require additional care here. */
10987 offbits
= (mips_opts
.micromips
? 12 : 16);
10988 /* Itbl support may require additional care here. */
10994 /* Itbl support may require additional care here. */
10998 gas_assert (!mips_opts
.micromips
);
11001 /* Itbl support may require additional care here. */
11007 offbits
= (mips_opts
.micromips
? 12 : 16);
11012 offbits
= (mips_opts
.micromips
? 12 : 16);
11015 gas_assert (mips_opts
.micromips
);
11021 gas_assert (mips_opts
.micromips
);
11027 gas_assert (mips_opts
.micromips
);
11033 gas_assert (mips_opts
.micromips
);
11042 if (small_offset_p (0, align
, 16))
11044 /* The first case exists for M_LD_AB and M_SD_AB, which are
11045 macros for o32 but which should act like normal instructions
11048 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11049 offset_reloc
[1], offset_reloc
[2], breg
);
11050 else if (small_offset_p (0, align
, offbits
))
11053 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11055 macro_build (NULL
, s
, fmt
, op
[0],
11056 (int) offset_expr
.X_add_number
, breg
);
11062 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11063 tempreg
, breg
, -1, offset_reloc
[0],
11064 offset_reloc
[1], offset_reloc
[2]);
11066 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11068 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11076 if (offset_expr
.X_op
!= O_constant
11077 && offset_expr
.X_op
!= O_symbol
)
11079 as_bad (_("expression too complex"));
11080 offset_expr
.X_op
= O_constant
;
11083 if (HAVE_32BIT_ADDRESSES
11084 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11088 sprintf_vma (value
, offset_expr
.X_add_number
);
11089 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11092 /* A constant expression in PIC code can be handled just as it
11093 is in non PIC code. */
11094 if (offset_expr
.X_op
== O_constant
)
11096 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11097 offbits
== 0 ? 16 : offbits
);
11098 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11100 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11102 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11103 tempreg
, tempreg
, breg
);
11106 if (offset_expr
.X_add_number
!= 0)
11107 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11108 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11109 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11111 else if (offbits
== 16)
11112 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11114 macro_build (NULL
, s
, fmt
, op
[0],
11115 (int) offset_expr
.X_add_number
, tempreg
);
11117 else if (offbits
!= 16)
11119 /* The offset field is too narrow to be used for a low-part
11120 relocation, so load the whole address into the auxillary
11122 load_address (tempreg
, &offset_expr
, &used_at
);
11124 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11125 tempreg
, tempreg
, breg
);
11127 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11129 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11131 else if (mips_pic
== NO_PIC
)
11133 /* If this is a reference to a GP relative symbol, and there
11134 is no base register, we want
11135 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11136 Otherwise, if there is no base register, we want
11137 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11138 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11139 If we have a constant, we need two instructions anyhow,
11140 so we always use the latter form.
11142 If we have a base register, and this is a reference to a
11143 GP relative symbol, we want
11144 addu $tempreg,$breg,$gp
11145 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11147 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11148 addu $tempreg,$tempreg,$breg
11149 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11150 With a constant we always use the latter case.
11152 With 64bit address space and no base register and $at usable,
11154 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11155 lui $at,<sym> (BFD_RELOC_HI16_S)
11156 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11159 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11160 If we have a base register, we want
11161 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11162 lui $at,<sym> (BFD_RELOC_HI16_S)
11163 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11167 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11169 Without $at we can't generate the optimal path for superscalar
11170 processors here since this would require two temporary registers.
11171 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11172 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11174 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11176 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11177 If we have a base register, we want
11178 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11179 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11181 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11183 daddu $tempreg,$tempreg,$breg
11184 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11186 For GP relative symbols in 64bit address space we can use
11187 the same sequence as in 32bit address space. */
11188 if (HAVE_64BIT_SYMBOLS
)
11190 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11191 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11193 relax_start (offset_expr
.X_add_symbol
);
11196 macro_build (&offset_expr
, s
, fmt
, op
[0],
11197 BFD_RELOC_GPREL16
, mips_gp_register
);
11201 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11202 tempreg
, breg
, mips_gp_register
);
11203 macro_build (&offset_expr
, s
, fmt
, op
[0],
11204 BFD_RELOC_GPREL16
, tempreg
);
11209 if (used_at
== 0 && mips_opts
.at
)
11211 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11212 BFD_RELOC_MIPS_HIGHEST
);
11213 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11215 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11216 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11218 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11219 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11220 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11221 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11227 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11228 BFD_RELOC_MIPS_HIGHEST
);
11229 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11230 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11231 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11232 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11233 tempreg
, BFD_RELOC_HI16_S
);
11234 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11236 macro_build (NULL
, "daddu", "d,v,t",
11237 tempreg
, tempreg
, breg
);
11238 macro_build (&offset_expr
, s
, fmt
, op
[0],
11239 BFD_RELOC_LO16
, tempreg
);
11242 if (mips_relax
.sequence
)
11249 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11250 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11252 relax_start (offset_expr
.X_add_symbol
);
11253 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11257 macro_build_lui (&offset_expr
, tempreg
);
11258 macro_build (&offset_expr
, s
, fmt
, op
[0],
11259 BFD_RELOC_LO16
, tempreg
);
11260 if (mips_relax
.sequence
)
11265 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11266 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11268 relax_start (offset_expr
.X_add_symbol
);
11269 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11270 tempreg
, breg
, mips_gp_register
);
11271 macro_build (&offset_expr
, s
, fmt
, op
[0],
11272 BFD_RELOC_GPREL16
, tempreg
);
11275 macro_build_lui (&offset_expr
, tempreg
);
11276 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11277 tempreg
, tempreg
, breg
);
11278 macro_build (&offset_expr
, s
, fmt
, op
[0],
11279 BFD_RELOC_LO16
, tempreg
);
11280 if (mips_relax
.sequence
)
11284 else if (!mips_big_got
)
11286 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11288 /* If this is a reference to an external symbol, we want
11289 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11291 <op> op[0],0($tempreg)
11293 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11295 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11296 <op> op[0],0($tempreg)
11298 For NewABI, we want
11299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11300 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11302 If there is a base register, we add it to $tempreg before
11303 the <op>. If there is a constant, we stick it in the
11304 <op> instruction. We don't handle constants larger than
11305 16 bits, because we have no way to load the upper 16 bits
11306 (actually, we could handle them for the subset of cases
11307 in which we are not using $at). */
11308 gas_assert (offset_expr
.X_op
== O_symbol
);
11311 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11312 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11314 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11315 tempreg
, tempreg
, breg
);
11316 macro_build (&offset_expr
, s
, fmt
, op
[0],
11317 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11320 expr1
.X_add_number
= offset_expr
.X_add_number
;
11321 offset_expr
.X_add_number
= 0;
11322 if (expr1
.X_add_number
< -0x8000
11323 || expr1
.X_add_number
>= 0x8000)
11324 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11325 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11326 lw_reloc_type
, mips_gp_register
);
11328 relax_start (offset_expr
.X_add_symbol
);
11330 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11331 tempreg
, BFD_RELOC_LO16
);
11334 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11335 tempreg
, tempreg
, breg
);
11336 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11338 else if (mips_big_got
&& !HAVE_NEWABI
)
11342 /* If this is a reference to an external symbol, we want
11343 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11344 addu $tempreg,$tempreg,$gp
11345 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11346 <op> op[0],0($tempreg)
11348 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11350 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11351 <op> op[0],0($tempreg)
11352 If there is a base register, we add it to $tempreg before
11353 the <op>. If there is a constant, we stick it in the
11354 <op> instruction. We don't handle constants larger than
11355 16 bits, because we have no way to load the upper 16 bits
11356 (actually, we could handle them for the subset of cases
11357 in which we are not using $at). */
11358 gas_assert (offset_expr
.X_op
== O_symbol
);
11359 expr1
.X_add_number
= offset_expr
.X_add_number
;
11360 offset_expr
.X_add_number
= 0;
11361 if (expr1
.X_add_number
< -0x8000
11362 || expr1
.X_add_number
>= 0x8000)
11363 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11364 gpdelay
= reg_needs_delay (mips_gp_register
);
11365 relax_start (offset_expr
.X_add_symbol
);
11366 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11367 BFD_RELOC_MIPS_GOT_HI16
);
11368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11370 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11371 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11374 macro_build (NULL
, "nop", "");
11375 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11376 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11378 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11379 tempreg
, BFD_RELOC_LO16
);
11383 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11384 tempreg
, tempreg
, breg
);
11385 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11387 else if (mips_big_got
&& HAVE_NEWABI
)
11389 /* If this is a reference to an external symbol, we want
11390 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11391 add $tempreg,$tempreg,$gp
11392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11393 <op> op[0],<ofst>($tempreg)
11394 Otherwise, for local symbols, we want:
11395 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11396 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11397 gas_assert (offset_expr
.X_op
== O_symbol
);
11398 expr1
.X_add_number
= offset_expr
.X_add_number
;
11399 offset_expr
.X_add_number
= 0;
11400 if (expr1
.X_add_number
< -0x8000
11401 || expr1
.X_add_number
>= 0x8000)
11402 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11403 relax_start (offset_expr
.X_add_symbol
);
11404 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11405 BFD_RELOC_MIPS_GOT_HI16
);
11406 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11408 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11409 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11411 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11412 tempreg
, tempreg
, breg
);
11413 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11416 offset_expr
.X_add_number
= expr1
.X_add_number
;
11417 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11418 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11420 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11421 tempreg
, tempreg
, breg
);
11422 macro_build (&offset_expr
, s
, fmt
, op
[0],
11423 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11432 gas_assert (mips_opts
.micromips
);
11433 gas_assert (mips_opts
.insn32
);
11434 start_noreorder ();
11435 macro_build (NULL
, "jr", "s", RA
);
11436 expr1
.X_add_number
= op
[0] << 2;
11437 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11442 gas_assert (mips_opts
.micromips
);
11443 gas_assert (mips_opts
.insn32
);
11444 macro_build (NULL
, "jr", "s", op
[0]);
11445 if (mips_opts
.noreorder
)
11446 macro_build (NULL
, "nop", "");
11451 load_register (op
[0], &imm_expr
, 0);
11455 load_register (op
[0], &imm_expr
, 1);
11459 if (imm_expr
.X_op
== O_constant
)
11462 load_register (AT
, &imm_expr
, 0);
11463 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11468 gas_assert (imm_expr
.X_op
== O_absent
11469 && offset_expr
.X_op
== O_symbol
11470 && strcmp (segment_name (S_GET_SEGMENT
11471 (offset_expr
.X_add_symbol
)),
11473 && offset_expr
.X_add_number
== 0);
11474 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11475 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11480 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11481 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11482 order 32 bits of the value and the low order 32 bits are either
11483 zero or in OFFSET_EXPR. */
11484 if (imm_expr
.X_op
== O_constant
)
11486 if (HAVE_64BIT_GPRS
)
11487 load_register (op
[0], &imm_expr
, 1);
11492 if (target_big_endian
)
11504 load_register (hreg
, &imm_expr
, 0);
11507 if (offset_expr
.X_op
== O_absent
)
11508 move_register (lreg
, 0);
11511 gas_assert (offset_expr
.X_op
== O_constant
);
11512 load_register (lreg
, &offset_expr
, 0);
11518 gas_assert (imm_expr
.X_op
== O_absent
);
11520 /* We know that sym is in the .rdata section. First we get the
11521 upper 16 bits of the address. */
11522 if (mips_pic
== NO_PIC
)
11524 macro_build_lui (&offset_expr
, AT
);
11529 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11530 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11534 /* Now we load the register(s). */
11535 if (HAVE_64BIT_GPRS
)
11538 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11539 BFD_RELOC_LO16
, AT
);
11544 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11545 BFD_RELOC_LO16
, AT
);
11548 /* FIXME: How in the world do we deal with the possible
11550 offset_expr
.X_add_number
+= 4;
11551 macro_build (&offset_expr
, "lw", "t,o(b)",
11552 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11558 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11559 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11560 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11561 the value and the low order 32 bits are either zero or in
11563 if (imm_expr
.X_op
== O_constant
)
11566 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11567 if (HAVE_64BIT_FPRS
)
11569 gas_assert (HAVE_64BIT_GPRS
);
11570 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11574 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11575 if (offset_expr
.X_op
== O_absent
)
11576 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11579 gas_assert (offset_expr
.X_op
== O_constant
);
11580 load_register (AT
, &offset_expr
, 0);
11581 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11587 gas_assert (imm_expr
.X_op
== O_absent
11588 && offset_expr
.X_op
== O_symbol
11589 && offset_expr
.X_add_number
== 0);
11590 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11591 if (strcmp (s
, ".lit8") == 0)
11593 op
[2] = mips_gp_register
;
11594 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11595 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11596 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11600 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11602 if (mips_pic
!= NO_PIC
)
11603 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11604 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11607 /* FIXME: This won't work for a 64 bit address. */
11608 macro_build_lui (&offset_expr
, AT
);
11612 offset_reloc
[0] = BFD_RELOC_LO16
;
11613 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11614 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11621 * The MIPS assembler seems to check for X_add_number not
11622 * being double aligned and generating:
11623 * lui at,%hi(foo+1)
11625 * addiu at,at,%lo(foo+1)
11628 * But, the resulting address is the same after relocation so why
11629 * generate the extra instruction?
11631 /* Itbl support may require additional care here. */
11634 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11643 gas_assert (!mips_opts
.micromips
);
11644 /* Itbl support may require additional care here. */
11647 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11667 if (HAVE_64BIT_GPRS
)
11677 if (HAVE_64BIT_GPRS
)
11685 /* Even on a big endian machine $fn comes before $fn+1. We have
11686 to adjust when loading from memory. We set coproc if we must
11687 load $fn+1 first. */
11688 /* Itbl support may require additional care here. */
11689 if (!target_big_endian
)
11693 if (small_offset_p (0, align
, 16))
11696 if (!small_offset_p (4, align
, 16))
11698 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11699 -1, offset_reloc
[0], offset_reloc
[1],
11701 expr1
.X_add_number
= 0;
11705 offset_reloc
[0] = BFD_RELOC_LO16
;
11706 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11707 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11709 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11711 ep
->X_add_number
+= 4;
11712 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11713 offset_reloc
[1], offset_reloc
[2], breg
);
11714 ep
->X_add_number
-= 4;
11715 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11716 offset_reloc
[1], offset_reloc
[2], breg
);
11720 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11721 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11723 ep
->X_add_number
+= 4;
11724 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11725 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11731 if (offset_expr
.X_op
!= O_symbol
11732 && offset_expr
.X_op
!= O_constant
)
11734 as_bad (_("expression too complex"));
11735 offset_expr
.X_op
= O_constant
;
11738 if (HAVE_32BIT_ADDRESSES
11739 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11743 sprintf_vma (value
, offset_expr
.X_add_number
);
11744 as_bad (_("number (0x%s) larger than 32 bits"), value
);
11747 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11749 /* If this is a reference to a GP relative symbol, we want
11750 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11751 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11752 If we have a base register, we use this
11754 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11755 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11756 If this is not a GP relative symbol, we want
11757 lui $at,<sym> (BFD_RELOC_HI16_S)
11758 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11759 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11760 If there is a base register, we add it to $at after the
11761 lui instruction. If there is a constant, we always use
11763 if (offset_expr
.X_op
== O_symbol
11764 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11765 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11767 relax_start (offset_expr
.X_add_symbol
);
11770 tempreg
= mips_gp_register
;
11774 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11775 AT
, breg
, mips_gp_register
);
11780 /* Itbl support may require additional care here. */
11781 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11782 BFD_RELOC_GPREL16
, tempreg
);
11783 offset_expr
.X_add_number
+= 4;
11785 /* Set mips_optimize to 2 to avoid inserting an
11787 hold_mips_optimize
= mips_optimize
;
11789 /* Itbl support may require additional care here. */
11790 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11791 BFD_RELOC_GPREL16
, tempreg
);
11792 mips_optimize
= hold_mips_optimize
;
11796 offset_expr
.X_add_number
-= 4;
11799 if (offset_high_part (offset_expr
.X_add_number
, 16)
11800 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11802 load_address (AT
, &offset_expr
, &used_at
);
11803 offset_expr
.X_op
= O_constant
;
11804 offset_expr
.X_add_number
= 0;
11807 macro_build_lui (&offset_expr
, AT
);
11809 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11810 /* Itbl support may require additional care here. */
11811 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11812 BFD_RELOC_LO16
, AT
);
11813 /* FIXME: How do we handle overflow here? */
11814 offset_expr
.X_add_number
+= 4;
11815 /* Itbl support may require additional care here. */
11816 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11817 BFD_RELOC_LO16
, AT
);
11818 if (mips_relax
.sequence
)
11821 else if (!mips_big_got
)
11823 /* If this is a reference to an external symbol, we want
11824 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11827 <op> op[0]+1,4($at)
11829 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11831 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11832 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11833 If there is a base register we add it to $at before the
11834 lwc1 instructions. If there is a constant we include it
11835 in the lwc1 instructions. */
11837 expr1
.X_add_number
= offset_expr
.X_add_number
;
11838 if (expr1
.X_add_number
< -0x8000
11839 || expr1
.X_add_number
>= 0x8000 - 4)
11840 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11841 load_got_offset (AT
, &offset_expr
);
11844 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11846 /* Set mips_optimize to 2 to avoid inserting an undesired
11848 hold_mips_optimize
= mips_optimize
;
11851 /* Itbl support may require additional care here. */
11852 relax_start (offset_expr
.X_add_symbol
);
11853 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11854 BFD_RELOC_LO16
, AT
);
11855 expr1
.X_add_number
+= 4;
11856 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11857 BFD_RELOC_LO16
, AT
);
11859 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11860 BFD_RELOC_LO16
, AT
);
11861 offset_expr
.X_add_number
+= 4;
11862 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11863 BFD_RELOC_LO16
, AT
);
11866 mips_optimize
= hold_mips_optimize
;
11868 else if (mips_big_got
)
11872 /* If this is a reference to an external symbol, we want
11873 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11875 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11878 <op> op[0]+1,4($at)
11880 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11882 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11883 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11884 If there is a base register we add it to $at before the
11885 lwc1 instructions. If there is a constant we include it
11886 in the lwc1 instructions. */
11888 expr1
.X_add_number
= offset_expr
.X_add_number
;
11889 offset_expr
.X_add_number
= 0;
11890 if (expr1
.X_add_number
< -0x8000
11891 || expr1
.X_add_number
>= 0x8000 - 4)
11892 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11893 gpdelay
= reg_needs_delay (mips_gp_register
);
11894 relax_start (offset_expr
.X_add_symbol
);
11895 macro_build (&offset_expr
, "lui", LUI_FMT
,
11896 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11897 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11898 AT
, AT
, mips_gp_register
);
11899 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11900 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11904 /* Itbl support may require additional care here. */
11905 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11906 BFD_RELOC_LO16
, AT
);
11907 expr1
.X_add_number
+= 4;
11909 /* Set mips_optimize to 2 to avoid inserting an undesired
11911 hold_mips_optimize
= mips_optimize
;
11913 /* Itbl support may require additional care here. */
11914 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11915 BFD_RELOC_LO16
, AT
);
11916 mips_optimize
= hold_mips_optimize
;
11917 expr1
.X_add_number
-= 4;
11920 offset_expr
.X_add_number
= expr1
.X_add_number
;
11922 macro_build (NULL
, "nop", "");
11923 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11924 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11927 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11928 /* Itbl support may require additional care here. */
11929 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11930 BFD_RELOC_LO16
, AT
);
11931 offset_expr
.X_add_number
+= 4;
11933 /* Set mips_optimize to 2 to avoid inserting an undesired
11935 hold_mips_optimize
= mips_optimize
;
11937 /* Itbl support may require additional care here. */
11938 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11939 BFD_RELOC_LO16
, AT
);
11940 mips_optimize
= hold_mips_optimize
;
11959 /* New code added to support COPZ instructions.
11960 This code builds table entries out of the macros in mip_opcodes.
11961 R4000 uses interlocks to handle coproc delays.
11962 Other chips (like the R3000) require nops to be inserted for delays.
11964 FIXME: Currently, we require that the user handle delays.
11965 In order to fill delay slots for non-interlocked chips,
11966 we must have a way to specify delays based on the coprocessor.
11967 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11968 What are the side-effects of the cop instruction?
11969 What cache support might we have and what are its effects?
11970 Both coprocessor & memory require delays. how long???
11971 What registers are read/set/modified?
11973 If an itbl is provided to interpret cop instructions,
11974 this knowledge can be encoded in the itbl spec. */
11988 gas_assert (!mips_opts
.micromips
);
11989 /* For now we just do C (same as Cz). The parameter will be
11990 stored in insn_opcode by mips_ip. */
11991 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11995 move_register (op
[0], op
[1]);
11999 gas_assert (mips_opts
.micromips
);
12000 gas_assert (mips_opts
.insn32
);
12001 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12002 micromips_to_32_reg_m_map
[op
[1]]);
12003 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12004 micromips_to_32_reg_n_map
[op
[2]]);
12010 if (mips_opts
.arch
== CPU_R5900
)
12011 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12015 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12016 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12023 /* The MIPS assembler some times generates shifts and adds. I'm
12024 not trying to be that fancy. GCC should do this for us
12027 load_register (AT
, &imm_expr
, dbl
);
12028 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12029 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12042 start_noreorder ();
12045 load_register (AT
, &imm_expr
, dbl
);
12046 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12047 op
[1], imm
? AT
: op
[2]);
12048 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12049 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12050 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12052 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12055 if (mips_opts
.micromips
)
12056 micromips_label_expr (&label_expr
);
12058 label_expr
.X_add_number
= 8;
12059 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12060 macro_build (NULL
, "nop", "");
12061 macro_build (NULL
, "break", BRK_FMT
, 6);
12062 if (mips_opts
.micromips
)
12063 micromips_add_label ();
12066 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12079 start_noreorder ();
12082 load_register (AT
, &imm_expr
, dbl
);
12083 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12084 op
[1], imm
? AT
: op
[2]);
12085 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12086 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12088 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12091 if (mips_opts
.micromips
)
12092 micromips_label_expr (&label_expr
);
12094 label_expr
.X_add_number
= 8;
12095 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12096 macro_build (NULL
, "nop", "");
12097 macro_build (NULL
, "break", BRK_FMT
, 6);
12098 if (mips_opts
.micromips
)
12099 micromips_add_label ();
12105 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12107 if (op
[0] == op
[1])
12114 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12115 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12119 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12120 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12121 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12122 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12126 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12128 if (op
[0] == op
[1])
12135 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12136 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12140 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12141 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12142 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12143 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12152 rot
= imm_expr
.X_add_number
& 0x3f;
12153 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12155 rot
= (64 - rot
) & 0x3f;
12157 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12159 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12164 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12167 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12168 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12171 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12172 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12173 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12181 rot
= imm_expr
.X_add_number
& 0x1f;
12182 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12184 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12185 (32 - rot
) & 0x1f);
12190 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12194 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12195 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12196 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12201 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12203 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12207 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12208 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12209 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12210 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12214 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12216 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12220 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12221 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12222 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12223 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12232 rot
= imm_expr
.X_add_number
& 0x3f;
12233 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12236 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12238 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12243 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12246 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12247 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12250 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12251 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12252 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12260 rot
= imm_expr
.X_add_number
& 0x1f;
12261 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12263 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12268 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12272 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12273 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12274 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12280 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12281 else if (op
[2] == 0)
12282 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12285 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12286 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12291 if (imm_expr
.X_add_number
== 0)
12293 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12298 as_warn (_("instruction %s: result is always false"),
12299 ip
->insn_mo
->name
);
12300 move_register (op
[0], 0);
12303 if (CPU_HAS_SEQ (mips_opts
.arch
)
12304 && -512 <= imm_expr
.X_add_number
12305 && imm_expr
.X_add_number
< 512)
12307 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12308 (int) imm_expr
.X_add_number
);
12311 if (imm_expr
.X_add_number
>= 0
12312 && imm_expr
.X_add_number
< 0x10000)
12313 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12314 else if (imm_expr
.X_add_number
> -0x8000
12315 && imm_expr
.X_add_number
< 0)
12317 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12318 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12319 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12321 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12324 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12325 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12330 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12331 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12334 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12337 case M_SGE
: /* X >= Y <==> not (X < Y) */
12343 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12344 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12347 case M_SGE_I
: /* X >= I <==> not (X < I) */
12349 if (imm_expr
.X_add_number
>= -0x8000
12350 && imm_expr
.X_add_number
< 0x8000)
12351 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12352 op
[0], op
[1], BFD_RELOC_LO16
);
12355 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12356 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12360 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12363 case M_SGT
: /* X > Y <==> Y < X */
12369 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12372 case M_SGT_I
: /* X > I <==> I < X */
12379 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12380 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12383 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12389 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12390 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12393 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12400 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12401 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12402 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12406 if (imm_expr
.X_add_number
>= -0x8000
12407 && imm_expr
.X_add_number
< 0x8000)
12409 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12414 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12415 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12419 if (imm_expr
.X_add_number
>= -0x8000
12420 && imm_expr
.X_add_number
< 0x8000)
12422 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12427 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12428 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12433 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12434 else if (op
[2] == 0)
12435 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12438 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12439 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12444 if (imm_expr
.X_add_number
== 0)
12446 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12451 as_warn (_("instruction %s: result is always true"),
12452 ip
->insn_mo
->name
);
12453 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12454 op
[0], 0, BFD_RELOC_LO16
);
12457 if (CPU_HAS_SEQ (mips_opts
.arch
)
12458 && -512 <= imm_expr
.X_add_number
12459 && imm_expr
.X_add_number
< 512)
12461 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12462 (int) imm_expr
.X_add_number
);
12465 if (imm_expr
.X_add_number
>= 0
12466 && imm_expr
.X_add_number
< 0x10000)
12468 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12471 else if (imm_expr
.X_add_number
> -0x8000
12472 && imm_expr
.X_add_number
< 0)
12474 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12475 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12476 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12478 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12481 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12482 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12487 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12488 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12491 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12506 if (!mips_opts
.micromips
)
12508 if (imm_expr
.X_add_number
> -0x200
12509 && imm_expr
.X_add_number
<= 0x200)
12511 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
12512 (int) -imm_expr
.X_add_number
);
12521 if (imm_expr
.X_add_number
> -0x8000
12522 && imm_expr
.X_add_number
<= 0x8000)
12524 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12525 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12530 load_register (AT
, &imm_expr
, dbl
);
12531 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12553 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12554 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12559 gas_assert (!mips_opts
.micromips
);
12560 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12564 * Is the double cfc1 instruction a bug in the mips assembler;
12565 * or is there a reason for it?
12567 start_noreorder ();
12568 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12569 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12570 macro_build (NULL
, "nop", "");
12571 expr1
.X_add_number
= 3;
12572 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12573 expr1
.X_add_number
= 2;
12574 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12575 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12576 macro_build (NULL
, "nop", "");
12577 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12579 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12580 macro_build (NULL
, "nop", "");
12597 offbits
= (mips_opts
.micromips
? 12 : 16);
12603 offbits
= (mips_opts
.micromips
? 12 : 16);
12615 offbits
= (mips_opts
.micromips
? 12 : 16);
12622 offbits
= (mips_opts
.micromips
? 12 : 16);
12628 large_offset
= !small_offset_p (off
, align
, offbits
);
12630 expr1
.X_add_number
= 0;
12635 if (small_offset_p (0, align
, 16))
12636 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12637 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12640 load_address (tempreg
, ep
, &used_at
);
12642 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12643 tempreg
, tempreg
, breg
);
12645 offset_reloc
[0] = BFD_RELOC_LO16
;
12646 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12647 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12652 else if (!ust
&& op
[0] == breg
)
12663 if (!target_big_endian
)
12664 ep
->X_add_number
+= off
;
12666 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12668 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12669 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12671 if (!target_big_endian
)
12672 ep
->X_add_number
-= off
;
12674 ep
->X_add_number
+= off
;
12676 macro_build (NULL
, s2
, "t,~(b)",
12677 tempreg
, (int) ep
->X_add_number
, breg
);
12679 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12680 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12682 /* If necessary, move the result in tempreg to the final destination. */
12683 if (!ust
&& op
[0] != tempreg
)
12685 /* Protect second load's delay slot. */
12687 move_register (op
[0], tempreg
);
12693 if (target_big_endian
== ust
)
12694 ep
->X_add_number
+= off
;
12695 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12696 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12697 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12699 /* For halfword transfers we need a temporary register to shuffle
12700 bytes. Unfortunately for M_USH_A we have none available before
12701 the next store as AT holds the base address. We deal with this
12702 case by clobbering TREG and then restoring it as with ULH. */
12703 tempreg
= ust
== large_offset
? op
[0] : AT
;
12705 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12707 if (target_big_endian
== ust
)
12708 ep
->X_add_number
-= off
;
12710 ep
->X_add_number
+= off
;
12711 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12712 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12714 /* For M_USH_A re-retrieve the LSB. */
12715 if (ust
&& large_offset
)
12717 if (target_big_endian
)
12718 ep
->X_add_number
+= off
;
12720 ep
->X_add_number
-= off
;
12721 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12722 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12724 /* For ULH and M_USH_A OR the LSB in. */
12725 if (!ust
|| large_offset
)
12727 tempreg
= !large_offset
? AT
: op
[0];
12728 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12729 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12734 /* FIXME: Check if this is one of the itbl macros, since they
12735 are added dynamically. */
12736 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
12739 if (!mips_opts
.at
&& used_at
)
12740 as_bad (_("macro used $at after \".set noat\""));
12743 /* Implement macros in mips16 mode. */
12746 mips16_macro (struct mips_cl_insn
*ip
)
12748 const struct mips_operand_array
*operands
;
12753 const char *s
, *s2
, *s3
;
12754 unsigned int op
[MAX_OPERANDS
];
12757 mask
= ip
->insn_mo
->mask
;
12759 operands
= insn_operands (ip
);
12760 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12761 if (operands
->operand
[i
])
12762 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12766 expr1
.X_op
= O_constant
;
12767 expr1
.X_op_symbol
= NULL
;
12768 expr1
.X_add_symbol
= NULL
;
12769 expr1
.X_add_number
= 1;
12788 start_noreorder ();
12789 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12790 expr1
.X_add_number
= 2;
12791 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12792 macro_build (NULL
, "break", "6", 7);
12794 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12795 since that causes an overflow. We should do that as well,
12796 but I don't see how to do the comparisons without a temporary
12799 macro_build (NULL
, s
, "x", op
[0]);
12818 start_noreorder ();
12819 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12820 expr1
.X_add_number
= 2;
12821 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12822 macro_build (NULL
, "break", "6", 7);
12824 macro_build (NULL
, s2
, "x", op
[0]);
12830 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12831 macro_build (NULL
, "mflo", "x", op
[0]);
12839 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12840 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12844 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12845 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12849 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12850 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12872 goto do_reverse_branch
;
12876 goto do_reverse_branch
;
12888 goto do_reverse_branch
;
12899 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12900 macro_build (&offset_expr
, s2
, "p");
12927 goto do_addone_branch_i
;
12932 goto do_addone_branch_i
;
12947 goto do_addone_branch_i
;
12953 do_addone_branch_i
:
12954 ++imm_expr
.X_add_number
;
12957 macro_build (&imm_expr
, s
, s3
, op
[0]);
12958 macro_build (&offset_expr
, s2
, "p");
12962 expr1
.X_add_number
= 0;
12963 macro_build (&expr1
, "slti", "x,8", op
[1]);
12964 if (op
[0] != op
[1])
12965 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12966 expr1
.X_add_number
= 2;
12967 macro_build (&expr1
, "bteqz", "p");
12968 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12973 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12974 opcode bits in *OPCODE_EXTRA. */
12976 static struct mips_opcode
*
12977 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
12978 ssize_t length
, unsigned int *opcode_extra
)
12980 char *name
, *dot
, *p
;
12981 unsigned int mask
, suffix
;
12983 struct mips_opcode
*insn
;
12985 /* Make a copy of the instruction so that we can fiddle with it. */
12986 name
= alloca (length
+ 1);
12987 memcpy (name
, start
, length
);
12988 name
[length
] = '\0';
12990 /* Look up the instruction as-is. */
12991 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
12995 dot
= strchr (name
, '.');
12998 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12999 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13000 if (*p
== 0 && mask
!= 0)
13003 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13005 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13007 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13013 if (mips_opts
.micromips
)
13015 /* See if there's an instruction size override suffix,
13016 either `16' or `32', at the end of the mnemonic proper,
13017 that defines the operation, i.e. before the first `.'
13018 character if any. Strip it and retry. */
13019 opend
= dot
!= NULL
? dot
- name
: length
;
13020 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13022 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13028 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13029 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13032 forced_insn_length
= suffix
;
13041 /* Assemble an instruction into its binary format. If the instruction
13042 is a macro, set imm_expr and offset_expr to the values associated
13043 with "I" and "A" operands respectively. Otherwise store the value
13044 of the relocatable field (if any) in offset_expr. In both cases
13045 set offset_reloc to the relocation operators applied to offset_expr. */
13048 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13050 const struct mips_opcode
*first
, *past
;
13051 struct hash_control
*hash
;
13054 struct mips_operand_token
*tokens
;
13055 unsigned int opcode_extra
;
13057 if (mips_opts
.micromips
)
13059 hash
= micromips_op_hash
;
13060 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13065 past
= &mips_opcodes
[NUMOPCODES
];
13067 forced_insn_length
= 0;
13070 /* We first try to match an instruction up to a space or to the end. */
13071 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13074 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13077 set_insn_error (0, _("unrecognized opcode"));
13081 if (strcmp (first
->name
, "li.s") == 0)
13083 else if (strcmp (first
->name
, "li.d") == 0)
13087 tokens
= mips_parse_arguments (str
+ end
, format
);
13091 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13092 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13093 set_insn_error (0, _("invalid operands"));
13095 obstack_free (&mips_operand_tokens
, tokens
);
13098 /* As for mips_ip, but used when assembling MIPS16 code.
13099 Also set forced_insn_length to the resulting instruction size in
13100 bytes if the user explicitly requested a small or extended instruction. */
13103 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13106 struct mips_opcode
*first
;
13107 struct mips_operand_token
*tokens
;
13109 forced_insn_length
= 0;
13111 for (s
= str
; ISLOWER (*s
); ++s
)
13125 if (s
[1] == 't' && s
[2] == ' ')
13127 forced_insn_length
= 2;
13131 else if (s
[1] == 'e' && s
[2] == ' ')
13133 forced_insn_length
= 4;
13137 /* Fall through. */
13139 set_insn_error (0, _("unrecognized opcode"));
13143 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13144 forced_insn_length
= 2;
13147 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13152 set_insn_error (0, _("unrecognized opcode"));
13156 tokens
= mips_parse_arguments (s
, 0);
13160 if (!match_mips16_insns (insn
, first
, tokens
))
13161 set_insn_error (0, _("invalid operands"));
13163 obstack_free (&mips_operand_tokens
, tokens
);
13166 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13167 NBITS is the number of significant bits in VAL. */
13169 static unsigned long
13170 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13175 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13178 else if (nbits
== 15)
13180 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13185 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13188 return (extval
<< 16) | val
;
13191 /* Like decode_mips16_operand, but require the operand to be defined and
13192 require it to be an integer. */
13194 static const struct mips_int_operand
*
13195 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13197 const struct mips_operand
*operand
;
13199 operand
= decode_mips16_operand (type
, extended_p
);
13200 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13202 return (const struct mips_int_operand
*) operand
;
13205 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13208 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13209 bfd_reloc_code_real_type reloc
, offsetT sval
)
13211 int min_val
, max_val
;
13213 min_val
= mips_int_operand_min (operand
);
13214 max_val
= mips_int_operand_max (operand
);
13215 if (reloc
!= BFD_RELOC_UNUSED
)
13218 sval
= SEXT_16BIT (sval
);
13223 return (sval
>= min_val
13225 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13228 /* Install immediate value VAL into MIPS16 instruction *INSN,
13229 extending it if necessary. The instruction in *INSN may
13230 already be extended.
13232 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13233 if none. In the former case, VAL is a 16-bit number with no
13234 defined signedness.
13236 TYPE is the type of the immediate field. USER_INSN_LENGTH
13237 is the length that the user requested, or 0 if none. */
13240 mips16_immed (char *file
, unsigned int line
, int type
,
13241 bfd_reloc_code_real_type reloc
, offsetT val
,
13242 unsigned int user_insn_length
, unsigned long *insn
)
13244 const struct mips_int_operand
*operand
;
13245 unsigned int uval
, length
;
13247 operand
= mips16_immed_operand (type
, FALSE
);
13248 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13250 /* We need an extended instruction. */
13251 if (user_insn_length
== 2)
13252 as_bad_where (file
, line
, _("invalid unextended operand value"));
13254 *insn
|= MIPS16_EXTEND
;
13256 else if (user_insn_length
== 4)
13258 /* The operand doesn't force an unextended instruction to be extended.
13259 Warn if the user wanted an extended instruction anyway. */
13260 *insn
|= MIPS16_EXTEND
;
13261 as_warn_where (file
, line
,
13262 _("extended operand requested but not required"));
13265 length
= mips16_opcode_length (*insn
);
13268 operand
= mips16_immed_operand (type
, TRUE
);
13269 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13270 as_bad_where (file
, line
,
13271 _("operand value out of range for instruction"));
13273 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13275 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13277 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13280 struct percent_op_match
13283 bfd_reloc_code_real_type reloc
;
13286 static const struct percent_op_match mips_percent_op
[] =
13288 {"%lo", BFD_RELOC_LO16
},
13289 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13290 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13291 {"%call16", BFD_RELOC_MIPS_CALL16
},
13292 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13293 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13294 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13295 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13296 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13297 {"%got", BFD_RELOC_MIPS_GOT16
},
13298 {"%gp_rel", BFD_RELOC_GPREL16
},
13299 {"%half", BFD_RELOC_16
},
13300 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13301 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13302 {"%neg", BFD_RELOC_MIPS_SUB
},
13303 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13304 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13305 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13306 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13307 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13308 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13309 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13310 {"%hi", BFD_RELOC_HI16_S
}
13313 static const struct percent_op_match mips16_percent_op
[] =
13315 {"%lo", BFD_RELOC_MIPS16_LO16
},
13316 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13317 {"%got", BFD_RELOC_MIPS16_GOT16
},
13318 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13319 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13320 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13321 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13322 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13323 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13324 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13325 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13326 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13330 /* Return true if *STR points to a relocation operator. When returning true,
13331 move *STR over the operator and store its relocation code in *RELOC.
13332 Leave both *STR and *RELOC alone when returning false. */
13335 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13337 const struct percent_op_match
*percent_op
;
13340 if (mips_opts
.mips16
)
13342 percent_op
= mips16_percent_op
;
13343 limit
= ARRAY_SIZE (mips16_percent_op
);
13347 percent_op
= mips_percent_op
;
13348 limit
= ARRAY_SIZE (mips_percent_op
);
13351 for (i
= 0; i
< limit
; i
++)
13352 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13354 int len
= strlen (percent_op
[i
].str
);
13356 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13359 *str
+= strlen (percent_op
[i
].str
);
13360 *reloc
= percent_op
[i
].reloc
;
13362 /* Check whether the output BFD supports this relocation.
13363 If not, issue an error and fall back on something safe. */
13364 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13366 as_bad (_("relocation %s isn't supported by the current ABI"),
13367 percent_op
[i
].str
);
13368 *reloc
= BFD_RELOC_UNUSED
;
13376 /* Parse string STR as a 16-bit relocatable operand. Store the
13377 expression in *EP and the relocations in the array starting
13378 at RELOC. Return the number of relocation operators used.
13380 On exit, EXPR_END points to the first character after the expression. */
13383 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13386 bfd_reloc_code_real_type reversed_reloc
[3];
13387 size_t reloc_index
, i
;
13388 int crux_depth
, str_depth
;
13391 /* Search for the start of the main expression, recoding relocations
13392 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13393 of the main expression and with CRUX_DEPTH containing the number
13394 of open brackets at that point. */
13401 crux_depth
= str_depth
;
13403 /* Skip over whitespace and brackets, keeping count of the number
13405 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13410 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13411 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13413 my_getExpression (ep
, crux
);
13416 /* Match every open bracket. */
13417 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13421 if (crux_depth
> 0)
13422 as_bad (_("unclosed '('"));
13426 if (reloc_index
!= 0)
13428 prev_reloc_op_frag
= frag_now
;
13429 for (i
= 0; i
< reloc_index
; i
++)
13430 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13433 return reloc_index
;
13437 my_getExpression (expressionS
*ep
, char *str
)
13441 save_in
= input_line_pointer
;
13442 input_line_pointer
= str
;
13444 expr_end
= input_line_pointer
;
13445 input_line_pointer
= save_in
;
13449 md_atof (int type
, char *litP
, int *sizeP
)
13451 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13455 md_number_to_chars (char *buf
, valueT val
, int n
)
13457 if (target_big_endian
)
13458 number_to_chars_bigendian (buf
, val
, n
);
13460 number_to_chars_littleendian (buf
, val
, n
);
13463 static int support_64bit_objects(void)
13465 const char **list
, **l
;
13468 list
= bfd_target_list ();
13469 for (l
= list
; *l
!= NULL
; l
++)
13470 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13471 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13473 yes
= (*l
!= NULL
);
13478 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13479 NEW_VALUE. Warn if another value was already specified. Note:
13480 we have to defer parsing the -march and -mtune arguments in order
13481 to handle 'from-abi' correctly, since the ABI might be specified
13482 in a later argument. */
13485 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13487 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13488 as_warn (_("a different %s was already specified, is now %s"),
13489 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13492 *string_ptr
= new_value
;
13496 md_parse_option (int c
, char *arg
)
13500 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13501 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13503 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13504 c
== mips_ases
[i
].option_on
);
13510 case OPTION_CONSTRUCT_FLOATS
:
13511 mips_disable_float_construction
= 0;
13514 case OPTION_NO_CONSTRUCT_FLOATS
:
13515 mips_disable_float_construction
= 1;
13527 target_big_endian
= 1;
13531 target_big_endian
= 0;
13537 else if (arg
[0] == '0')
13539 else if (arg
[0] == '1')
13549 mips_debug
= atoi (arg
);
13553 file_mips_isa
= ISA_MIPS1
;
13557 file_mips_isa
= ISA_MIPS2
;
13561 file_mips_isa
= ISA_MIPS3
;
13565 file_mips_isa
= ISA_MIPS4
;
13569 file_mips_isa
= ISA_MIPS5
;
13572 case OPTION_MIPS32
:
13573 file_mips_isa
= ISA_MIPS32
;
13576 case OPTION_MIPS32R2
:
13577 file_mips_isa
= ISA_MIPS32R2
;
13580 case OPTION_MIPS32R3
:
13581 file_mips_isa
= ISA_MIPS32R3
;
13584 case OPTION_MIPS32R5
:
13585 file_mips_isa
= ISA_MIPS32R5
;
13588 case OPTION_MIPS64R2
:
13589 file_mips_isa
= ISA_MIPS64R2
;
13592 case OPTION_MIPS64R3
:
13593 file_mips_isa
= ISA_MIPS64R3
;
13596 case OPTION_MIPS64R5
:
13597 file_mips_isa
= ISA_MIPS64R5
;
13600 case OPTION_MIPS64
:
13601 file_mips_isa
= ISA_MIPS64
;
13605 mips_set_option_string (&mips_tune_string
, arg
);
13609 mips_set_option_string (&mips_arch_string
, arg
);
13613 mips_set_option_string (&mips_arch_string
, "4650");
13614 mips_set_option_string (&mips_tune_string
, "4650");
13617 case OPTION_NO_M4650
:
13621 mips_set_option_string (&mips_arch_string
, "4010");
13622 mips_set_option_string (&mips_tune_string
, "4010");
13625 case OPTION_NO_M4010
:
13629 mips_set_option_string (&mips_arch_string
, "4100");
13630 mips_set_option_string (&mips_tune_string
, "4100");
13633 case OPTION_NO_M4100
:
13637 mips_set_option_string (&mips_arch_string
, "3900");
13638 mips_set_option_string (&mips_tune_string
, "3900");
13641 case OPTION_NO_M3900
:
13644 case OPTION_MICROMIPS
:
13645 if (mips_opts
.mips16
== 1)
13647 as_bad (_("-mmicromips cannot be used with -mips16"));
13650 mips_opts
.micromips
= 1;
13651 mips_no_prev_insn ();
13654 case OPTION_NO_MICROMIPS
:
13655 mips_opts
.micromips
= 0;
13656 mips_no_prev_insn ();
13659 case OPTION_MIPS16
:
13660 if (mips_opts
.micromips
== 1)
13662 as_bad (_("-mips16 cannot be used with -micromips"));
13665 mips_opts
.mips16
= 1;
13666 mips_no_prev_insn ();
13669 case OPTION_NO_MIPS16
:
13670 mips_opts
.mips16
= 0;
13671 mips_no_prev_insn ();
13674 case OPTION_FIX_24K
:
13678 case OPTION_NO_FIX_24K
:
13682 case OPTION_FIX_RM7000
:
13683 mips_fix_rm7000
= 1;
13686 case OPTION_NO_FIX_RM7000
:
13687 mips_fix_rm7000
= 0;
13690 case OPTION_FIX_LOONGSON2F_JUMP
:
13691 mips_fix_loongson2f_jump
= TRUE
;
13694 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13695 mips_fix_loongson2f_jump
= FALSE
;
13698 case OPTION_FIX_LOONGSON2F_NOP
:
13699 mips_fix_loongson2f_nop
= TRUE
;
13702 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13703 mips_fix_loongson2f_nop
= FALSE
;
13706 case OPTION_FIX_VR4120
:
13707 mips_fix_vr4120
= 1;
13710 case OPTION_NO_FIX_VR4120
:
13711 mips_fix_vr4120
= 0;
13714 case OPTION_FIX_VR4130
:
13715 mips_fix_vr4130
= 1;
13718 case OPTION_NO_FIX_VR4130
:
13719 mips_fix_vr4130
= 0;
13722 case OPTION_FIX_CN63XXP1
:
13723 mips_fix_cn63xxp1
= TRUE
;
13726 case OPTION_NO_FIX_CN63XXP1
:
13727 mips_fix_cn63xxp1
= FALSE
;
13730 case OPTION_RELAX_BRANCH
:
13731 mips_relax_branch
= 1;
13734 case OPTION_NO_RELAX_BRANCH
:
13735 mips_relax_branch
= 0;
13738 case OPTION_INSN32
:
13739 mips_opts
.insn32
= TRUE
;
13742 case OPTION_NO_INSN32
:
13743 mips_opts
.insn32
= FALSE
;
13746 case OPTION_MSHARED
:
13747 mips_in_shared
= TRUE
;
13750 case OPTION_MNO_SHARED
:
13751 mips_in_shared
= FALSE
;
13754 case OPTION_MSYM32
:
13755 mips_opts
.sym32
= TRUE
;
13758 case OPTION_MNO_SYM32
:
13759 mips_opts
.sym32
= FALSE
;
13762 /* When generating ELF code, we permit -KPIC and -call_shared to
13763 select SVR4_PIC, and -non_shared to select no PIC. This is
13764 intended to be compatible with Irix 5. */
13765 case OPTION_CALL_SHARED
:
13766 mips_pic
= SVR4_PIC
;
13767 mips_abicalls
= TRUE
;
13770 case OPTION_CALL_NONPIC
:
13772 mips_abicalls
= TRUE
;
13775 case OPTION_NON_SHARED
:
13777 mips_abicalls
= FALSE
;
13780 /* The -xgot option tells the assembler to use 32 bit offsets
13781 when accessing the got in SVR4_PIC mode. It is for Irix
13788 g_switch_value
= atoi (arg
);
13792 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13795 mips_abi
= O32_ABI
;
13799 mips_abi
= N32_ABI
;
13803 mips_abi
= N64_ABI
;
13804 if (!support_64bit_objects())
13805 as_fatal (_("no compiled in support for 64 bit object file format"));
13809 file_mips_gp32
= 1;
13813 file_mips_gp32
= 0;
13817 file_mips_fp32
= 1;
13821 file_mips_fp32
= 0;
13824 case OPTION_SINGLE_FLOAT
:
13825 file_mips_single_float
= 1;
13828 case OPTION_DOUBLE_FLOAT
:
13829 file_mips_single_float
= 0;
13832 case OPTION_SOFT_FLOAT
:
13833 file_mips_soft_float
= 1;
13836 case OPTION_HARD_FLOAT
:
13837 file_mips_soft_float
= 0;
13841 if (strcmp (arg
, "32") == 0)
13842 mips_abi
= O32_ABI
;
13843 else if (strcmp (arg
, "o64") == 0)
13844 mips_abi
= O64_ABI
;
13845 else if (strcmp (arg
, "n32") == 0)
13846 mips_abi
= N32_ABI
;
13847 else if (strcmp (arg
, "64") == 0)
13849 mips_abi
= N64_ABI
;
13850 if (! support_64bit_objects())
13851 as_fatal (_("no compiled in support for 64 bit object file "
13854 else if (strcmp (arg
, "eabi") == 0)
13855 mips_abi
= EABI_ABI
;
13858 as_fatal (_("invalid abi -mabi=%s"), arg
);
13863 case OPTION_M7000_HILO_FIX
:
13864 mips_7000_hilo_fix
= TRUE
;
13867 case OPTION_MNO_7000_HILO_FIX
:
13868 mips_7000_hilo_fix
= FALSE
;
13871 case OPTION_MDEBUG
:
13872 mips_flag_mdebug
= TRUE
;
13875 case OPTION_NO_MDEBUG
:
13876 mips_flag_mdebug
= FALSE
;
13880 mips_flag_pdr
= TRUE
;
13883 case OPTION_NO_PDR
:
13884 mips_flag_pdr
= FALSE
;
13887 case OPTION_MVXWORKS_PIC
:
13888 mips_pic
= VXWORKS_PIC
;
13892 if (strcmp (arg
, "2008") == 0)
13893 mips_flag_nan2008
= TRUE
;
13894 else if (strcmp (arg
, "legacy") == 0)
13895 mips_flag_nan2008
= FALSE
;
13898 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
13907 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13912 /* Set up globals to generate code for the ISA or processor
13913 described by INFO. */
13916 mips_set_architecture (const struct mips_cpu_info
*info
)
13920 file_mips_arch
= info
->cpu
;
13921 mips_opts
.arch
= info
->cpu
;
13922 mips_opts
.isa
= info
->isa
;
13927 /* Likewise for tuning. */
13930 mips_set_tune (const struct mips_cpu_info
*info
)
13933 mips_tune
= info
->cpu
;
13938 mips_after_parse_args (void)
13940 const struct mips_cpu_info
*arch_info
= 0;
13941 const struct mips_cpu_info
*tune_info
= 0;
13943 /* GP relative stuff not working for PE */
13944 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13946 if (g_switch_seen
&& g_switch_value
!= 0)
13947 as_bad (_("-G not supported in this configuration"));
13948 g_switch_value
= 0;
13951 if (mips_abi
== NO_ABI
)
13952 mips_abi
= MIPS_DEFAULT_ABI
;
13954 /* The following code determines the architecture and register size.
13955 Similar code was added to GCC 3.3 (see override_options() in
13956 config/mips/mips.c). The GAS and GCC code should be kept in sync
13957 as much as possible. */
13959 if (mips_arch_string
!= 0)
13960 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13962 if (file_mips_isa
!= ISA_UNKNOWN
)
13964 /* Handle -mipsN. At this point, file_mips_isa contains the
13965 ISA level specified by -mipsN, while arch_info->isa contains
13966 the -march selection (if any). */
13967 if (arch_info
!= 0)
13969 /* -march takes precedence over -mipsN, since it is more descriptive.
13970 There's no harm in specifying both as long as the ISA levels
13972 if (file_mips_isa
!= arch_info
->isa
)
13973 as_bad (_("-%s conflicts with the other architecture options,"
13974 " which imply -%s"),
13975 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13976 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13979 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13982 if (arch_info
== 0)
13984 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13985 gas_assert (arch_info
);
13988 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13989 as_bad (_("-march=%s is not compatible with the selected ABI"),
13992 mips_set_architecture (arch_info
);
13994 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13995 if (mips_tune_string
!= 0)
13996 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13998 if (tune_info
== 0)
13999 mips_set_tune (arch_info
);
14001 mips_set_tune (tune_info
);
14003 if (file_mips_gp32
>= 0)
14005 /* The user specified the size of the integer registers. Make sure
14006 it agrees with the ABI and ISA. */
14007 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14008 as_bad (_("-mgp64 used with a 32-bit processor"));
14009 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
14010 as_bad (_("-mgp32 used with a 64-bit ABI"));
14011 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
14012 as_bad (_("-mgp64 used with a 32-bit ABI"));
14016 /* Infer the integer register size from the ABI and processor.
14017 Restrict ourselves to 32-bit registers if that's all the
14018 processor has, or if the ABI cannot handle 64-bit registers. */
14019 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
14020 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
14023 switch (file_mips_fp32
)
14027 /* No user specified float register size.
14028 ??? GAS treats single-float processors as though they had 64-bit
14029 float registers (although it complains when double-precision
14030 instructions are used). As things stand, saying they have 32-bit
14031 registers would lead to spurious "register must be even" messages.
14032 So here we assume float registers are never smaller than the
14034 if (file_mips_gp32
== 0)
14035 /* 64-bit integer registers implies 64-bit float registers. */
14036 file_mips_fp32
= 0;
14037 else if ((mips_opts
.ase
& FP64_ASES
)
14038 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14039 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14040 file_mips_fp32
= 0;
14042 /* 32-bit float registers. */
14043 file_mips_fp32
= 1;
14046 /* The user specified the size of the float registers. Check if it
14047 agrees with the ABI and ISA. */
14049 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14050 as_bad (_("-mfp64 used with a 32-bit fpu"));
14051 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
14052 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
14053 as_warn (_("-mfp64 used with a 32-bit ABI"));
14056 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14057 as_warn (_("-mfp32 used with a 64-bit ABI"));
14061 /* End of GCC-shared inference code. */
14063 /* This flag is set when we have a 64-bit capable CPU but use only
14064 32-bit wide registers. Note that EABI does not use it. */
14065 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14066 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
14067 || mips_abi
== O32_ABI
))
14068 mips_32bitmode
= 1;
14070 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14071 as_bad (_("trap exception not supported at ISA 1"));
14073 /* If the selected architecture includes support for ASEs, enable
14074 generation of code for them. */
14075 if (mips_opts
.mips16
== -1)
14076 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
14077 if (mips_opts
.micromips
== -1)
14078 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
14080 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14081 ASEs from being selected implicitly. */
14082 if (file_mips_fp32
== 1)
14083 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
14085 /* If the user didn't explicitly select or deselect a particular ASE,
14086 use the default setting for the CPU. */
14087 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
14089 file_mips_isa
= mips_opts
.isa
;
14090 file_ase
= mips_opts
.ase
;
14091 mips_opts
.gp32
= file_mips_gp32
;
14092 mips_opts
.fp32
= file_mips_fp32
;
14093 mips_opts
.soft_float
= file_mips_soft_float
;
14094 mips_opts
.single_float
= file_mips_single_float
;
14096 mips_check_isa_supports_ases ();
14098 if (mips_flag_mdebug
< 0)
14099 mips_flag_mdebug
= 0;
14103 mips_init_after_args (void)
14105 /* initialize opcodes */
14106 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14107 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14111 md_pcrel_from (fixS
*fixP
)
14113 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14114 switch (fixP
->fx_r_type
)
14116 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14117 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14118 /* Return the address of the delay slot. */
14121 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14122 case BFD_RELOC_MICROMIPS_JMP
:
14123 case BFD_RELOC_16_PCREL_S2
:
14124 case BFD_RELOC_MIPS_JMP
:
14125 /* Return the address of the delay slot. */
14133 /* This is called before the symbol table is processed. In order to
14134 work with gcc when using mips-tfile, we must keep all local labels.
14135 However, in other cases, we want to discard them. If we were
14136 called with -g, but we didn't see any debugging information, it may
14137 mean that gcc is smuggling debugging information through to
14138 mips-tfile, in which case we must generate all local labels. */
14141 mips_frob_file_before_adjust (void)
14143 #ifndef NO_ECOFF_DEBUGGING
14144 if (ECOFF_DEBUGGING
14146 && ! ecoff_debugging_seen
)
14147 flag_keep_locals
= 1;
14151 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14152 the corresponding LO16 reloc. This is called before md_apply_fix and
14153 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14154 relocation operators.
14156 For our purposes, a %lo() expression matches a %got() or %hi()
14159 (a) it refers to the same symbol; and
14160 (b) the offset applied in the %lo() expression is no lower than
14161 the offset applied in the %got() or %hi().
14163 (b) allows us to cope with code like:
14166 lh $4,%lo(foo+2)($4)
14168 ...which is legal on RELA targets, and has a well-defined behaviour
14169 if the user knows that adding 2 to "foo" will not induce a carry to
14172 When several %lo()s match a particular %got() or %hi(), we use the
14173 following rules to distinguish them:
14175 (1) %lo()s with smaller offsets are a better match than %lo()s with
14178 (2) %lo()s with no matching %got() or %hi() are better than those
14179 that already have a matching %got() or %hi().
14181 (3) later %lo()s are better than earlier %lo()s.
14183 These rules are applied in order.
14185 (1) means, among other things, that %lo()s with identical offsets are
14186 chosen if they exist.
14188 (2) means that we won't associate several high-part relocations with
14189 the same low-part relocation unless there's no alternative. Having
14190 several high parts for the same low part is a GNU extension; this rule
14191 allows careful users to avoid it.
14193 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14194 with the last high-part relocation being at the front of the list.
14195 It therefore makes sense to choose the last matching low-part
14196 relocation, all other things being equal. It's also easier
14197 to code that way. */
14200 mips_frob_file (void)
14202 struct mips_hi_fixup
*l
;
14203 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14205 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14207 segment_info_type
*seginfo
;
14208 bfd_boolean matched_lo_p
;
14209 fixS
**hi_pos
, **lo_pos
, **pos
;
14211 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14213 /* If a GOT16 relocation turns out to be against a global symbol,
14214 there isn't supposed to be a matching LO. Ignore %gots against
14215 constants; we'll report an error for those later. */
14216 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14217 && !(l
->fixp
->fx_addsy
14218 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14221 /* Check quickly whether the next fixup happens to be a matching %lo. */
14222 if (fixup_has_matching_lo_p (l
->fixp
))
14225 seginfo
= seg_info (l
->seg
);
14227 /* Set HI_POS to the position of this relocation in the chain.
14228 Set LO_POS to the position of the chosen low-part relocation.
14229 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14230 relocation that matches an immediately-preceding high-part
14234 matched_lo_p
= FALSE
;
14235 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14237 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14239 if (*pos
== l
->fixp
)
14242 if ((*pos
)->fx_r_type
== looking_for_rtype
14243 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14244 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14246 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14248 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14251 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14252 && fixup_has_matching_lo_p (*pos
));
14255 /* If we found a match, remove the high-part relocation from its
14256 current position and insert it before the low-part relocation.
14257 Make the offsets match so that fixup_has_matching_lo_p()
14260 We don't warn about unmatched high-part relocations since some
14261 versions of gcc have been known to emit dead "lui ...%hi(...)"
14263 if (lo_pos
!= NULL
)
14265 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14266 if (l
->fixp
->fx_next
!= *lo_pos
)
14268 *hi_pos
= l
->fixp
->fx_next
;
14269 l
->fixp
->fx_next
= *lo_pos
;
14277 mips_force_relocation (fixS
*fixp
)
14279 if (generic_force_reloc (fixp
))
14282 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14283 so that the linker relaxation can update targets. */
14284 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14285 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14286 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14292 /* Read the instruction associated with RELOC from BUF. */
14294 static unsigned int
14295 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14297 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14298 return read_compressed_insn (buf
, 4);
14300 return read_insn (buf
);
14303 /* Write instruction INSN to BUF, given that it has been relocated
14307 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14308 unsigned long insn
)
14310 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14311 write_compressed_insn (buf
, insn
, 4);
14313 write_insn (buf
, insn
);
14316 /* Apply a fixup to the object file. */
14319 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14322 unsigned long insn
;
14323 reloc_howto_type
*howto
;
14325 if (fixP
->fx_pcrel
)
14326 switch (fixP
->fx_r_type
)
14328 case BFD_RELOC_16_PCREL_S2
:
14329 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14330 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14331 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14332 case BFD_RELOC_32_PCREL
:
14336 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
14340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14341 _("PC-relative reference to a different section"));
14345 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
14346 that have no MIPS ELF equivalent. */
14347 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
14349 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14354 gas_assert (fixP
->fx_size
== 2
14355 || fixP
->fx_size
== 4
14356 || fixP
->fx_r_type
== BFD_RELOC_8
14357 || fixP
->fx_r_type
== BFD_RELOC_16
14358 || fixP
->fx_r_type
== BFD_RELOC_64
14359 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14360 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14361 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14362 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14363 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14364 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14366 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14368 /* Don't treat parts of a composite relocation as done. There are two
14371 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14372 should nevertheless be emitted if the first part is.
14374 (2) In normal usage, composite relocations are never assembly-time
14375 constants. The easiest way of dealing with the pathological
14376 exceptions is to generate a relocation against STN_UNDEF and
14377 leave everything up to the linker. */
14378 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14381 switch (fixP
->fx_r_type
)
14383 case BFD_RELOC_MIPS_TLS_GD
:
14384 case BFD_RELOC_MIPS_TLS_LDM
:
14385 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14386 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14387 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14388 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14389 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14390 case BFD_RELOC_MIPS_TLS_TPREL32
:
14391 case BFD_RELOC_MIPS_TLS_TPREL64
:
14392 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14393 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14394 case BFD_RELOC_MICROMIPS_TLS_GD
:
14395 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14396 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14397 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14398 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14399 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14400 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14401 case BFD_RELOC_MIPS16_TLS_GD
:
14402 case BFD_RELOC_MIPS16_TLS_LDM
:
14403 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14404 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14405 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14406 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14407 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14408 if (!fixP
->fx_addsy
)
14410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14411 _("TLS relocation against a constant"));
14414 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14417 case BFD_RELOC_MIPS_JMP
:
14418 case BFD_RELOC_MIPS_SHIFT5
:
14419 case BFD_RELOC_MIPS_SHIFT6
:
14420 case BFD_RELOC_MIPS_GOT_DISP
:
14421 case BFD_RELOC_MIPS_GOT_PAGE
:
14422 case BFD_RELOC_MIPS_GOT_OFST
:
14423 case BFD_RELOC_MIPS_SUB
:
14424 case BFD_RELOC_MIPS_INSERT_A
:
14425 case BFD_RELOC_MIPS_INSERT_B
:
14426 case BFD_RELOC_MIPS_DELETE
:
14427 case BFD_RELOC_MIPS_HIGHEST
:
14428 case BFD_RELOC_MIPS_HIGHER
:
14429 case BFD_RELOC_MIPS_SCN_DISP
:
14430 case BFD_RELOC_MIPS_REL16
:
14431 case BFD_RELOC_MIPS_RELGOT
:
14432 case BFD_RELOC_MIPS_JALR
:
14433 case BFD_RELOC_HI16
:
14434 case BFD_RELOC_HI16_S
:
14435 case BFD_RELOC_LO16
:
14436 case BFD_RELOC_GPREL16
:
14437 case BFD_RELOC_MIPS_LITERAL
:
14438 case BFD_RELOC_MIPS_CALL16
:
14439 case BFD_RELOC_MIPS_GOT16
:
14440 case BFD_RELOC_GPREL32
:
14441 case BFD_RELOC_MIPS_GOT_HI16
:
14442 case BFD_RELOC_MIPS_GOT_LO16
:
14443 case BFD_RELOC_MIPS_CALL_HI16
:
14444 case BFD_RELOC_MIPS_CALL_LO16
:
14445 case BFD_RELOC_MIPS16_GPREL
:
14446 case BFD_RELOC_MIPS16_GOT16
:
14447 case BFD_RELOC_MIPS16_CALL16
:
14448 case BFD_RELOC_MIPS16_HI16
:
14449 case BFD_RELOC_MIPS16_HI16_S
:
14450 case BFD_RELOC_MIPS16_LO16
:
14451 case BFD_RELOC_MIPS16_JMP
:
14452 case BFD_RELOC_MICROMIPS_JMP
:
14453 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14454 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14455 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14456 case BFD_RELOC_MICROMIPS_SUB
:
14457 case BFD_RELOC_MICROMIPS_HIGHEST
:
14458 case BFD_RELOC_MICROMIPS_HIGHER
:
14459 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14460 case BFD_RELOC_MICROMIPS_JALR
:
14461 case BFD_RELOC_MICROMIPS_HI16
:
14462 case BFD_RELOC_MICROMIPS_HI16_S
:
14463 case BFD_RELOC_MICROMIPS_LO16
:
14464 case BFD_RELOC_MICROMIPS_GPREL16
:
14465 case BFD_RELOC_MICROMIPS_LITERAL
:
14466 case BFD_RELOC_MICROMIPS_CALL16
:
14467 case BFD_RELOC_MICROMIPS_GOT16
:
14468 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14469 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14470 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14471 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14472 case BFD_RELOC_MIPS_EH
:
14477 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14479 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14480 if (mips16_reloc_p (fixP
->fx_r_type
))
14481 insn
|= mips16_immed_extend (value
, 16);
14483 insn
|= (value
& 0xffff);
14484 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14488 _("unsupported constant in relocation"));
14493 /* This is handled like BFD_RELOC_32, but we output a sign
14494 extended value if we are only 32 bits. */
14497 if (8 <= sizeof (valueT
))
14498 md_number_to_chars (buf
, *valP
, 8);
14503 if ((*valP
& 0x80000000) != 0)
14507 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14508 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14513 case BFD_RELOC_RVA
:
14515 case BFD_RELOC_32_PCREL
:
14518 /* If we are deleting this reloc entry, we must fill in the
14519 value now. This can happen if we have a .word which is not
14520 resolved when it appears but is later defined. */
14522 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14525 case BFD_RELOC_16_PCREL_S2
:
14526 if ((*valP
& 0x3) != 0)
14527 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14528 _("branch to misaligned address (%lx)"), (long) *valP
);
14530 /* We need to save the bits in the instruction since fixup_segment()
14531 might be deleting the relocation entry (i.e., a branch within
14532 the current segment). */
14533 if (! fixP
->fx_done
)
14536 /* Update old instruction data. */
14537 insn
= read_insn (buf
);
14539 if (*valP
+ 0x20000 <= 0x3ffff)
14541 insn
|= (*valP
>> 2) & 0xffff;
14542 write_insn (buf
, insn
);
14544 else if (mips_pic
== NO_PIC
14546 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14547 && (fixP
->fx_frag
->fr_address
14548 < text_section
->vma
+ bfd_get_section_size (text_section
))
14549 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14550 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14551 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14553 /* The branch offset is too large. If this is an
14554 unconditional branch, and we are not generating PIC code,
14555 we can convert it to an absolute jump instruction. */
14556 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14557 insn
= 0x0c000000; /* jal */
14559 insn
= 0x08000000; /* j */
14560 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14562 fixP
->fx_addsy
= section_symbol (text_section
);
14563 *valP
+= md_pcrel_from (fixP
);
14564 write_insn (buf
, insn
);
14568 /* If we got here, we have branch-relaxation disabled,
14569 and there's nothing we can do to fix this instruction
14570 without turning it into a longer sequence. */
14571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14572 _("branch out of range"));
14576 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14577 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14578 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14579 /* We adjust the offset back to even. */
14580 if ((*valP
& 0x1) != 0)
14583 if (! fixP
->fx_done
)
14586 /* Should never visit here, because we keep the relocation. */
14590 case BFD_RELOC_VTABLE_INHERIT
:
14593 && !S_IS_DEFINED (fixP
->fx_addsy
)
14594 && !S_IS_WEAK (fixP
->fx_addsy
))
14595 S_SET_WEAK (fixP
->fx_addsy
);
14598 case BFD_RELOC_VTABLE_ENTRY
:
14606 /* Remember value for tc_gen_reloc. */
14607 fixP
->fx_addnumber
= *valP
;
14617 name
= input_line_pointer
;
14618 c
= get_symbol_end ();
14619 p
= (symbolS
*) symbol_find_or_make (name
);
14620 *input_line_pointer
= c
;
14624 /* Align the current frag to a given power of two. If a particular
14625 fill byte should be used, FILL points to an integer that contains
14626 that byte, otherwise FILL is null.
14628 This function used to have the comment:
14630 The MIPS assembler also automatically adjusts any preceding label.
14632 The implementation therefore applied the adjustment to a maximum of
14633 one label. However, other label adjustments are applied to batches
14634 of labels, and adjusting just one caused problems when new labels
14635 were added for the sake of debugging or unwind information.
14636 We therefore adjust all preceding labels (given as LABELS) instead. */
14639 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14641 mips_emit_delays ();
14642 mips_record_compressed_mode ();
14643 if (fill
== NULL
&& subseg_text_p (now_seg
))
14644 frag_align_code (to
, 0);
14646 frag_align (to
, fill
? *fill
: 0, 0);
14647 record_alignment (now_seg
, to
);
14648 mips_move_labels (labels
, FALSE
);
14651 /* Align to a given power of two. .align 0 turns off the automatic
14652 alignment used by the data creating pseudo-ops. */
14655 s_align (int x ATTRIBUTE_UNUSED
)
14657 int temp
, fill_value
, *fill_ptr
;
14658 long max_alignment
= 28;
14660 /* o Note that the assembler pulls down any immediately preceding label
14661 to the aligned address.
14662 o It's not documented but auto alignment is reinstated by
14663 a .align pseudo instruction.
14664 o Note also that after auto alignment is turned off the mips assembler
14665 issues an error on attempt to assemble an improperly aligned data item.
14668 temp
= get_absolute_expression ();
14669 if (temp
> max_alignment
)
14670 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
14673 as_warn (_("alignment negative, 0 assumed"));
14676 if (*input_line_pointer
== ',')
14678 ++input_line_pointer
;
14679 fill_value
= get_absolute_expression ();
14680 fill_ptr
= &fill_value
;
14686 segment_info_type
*si
= seg_info (now_seg
);
14687 struct insn_label_list
*l
= si
->label_list
;
14688 /* Auto alignment should be switched on by next section change. */
14690 mips_align (temp
, fill_ptr
, l
);
14697 demand_empty_rest_of_line ();
14701 s_change_sec (int sec
)
14705 /* The ELF backend needs to know that we are changing sections, so
14706 that .previous works correctly. We could do something like check
14707 for an obj_section_change_hook macro, but that might be confusing
14708 as it would not be appropriate to use it in the section changing
14709 functions in read.c, since obj-elf.c intercepts those. FIXME:
14710 This should be cleaner, somehow. */
14711 obj_elf_section_change_hook ();
14713 mips_emit_delays ();
14724 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14725 demand_empty_rest_of_line ();
14729 seg
= subseg_new (RDATA_SECTION_NAME
,
14730 (subsegT
) get_absolute_expression ());
14731 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14732 | SEC_READONLY
| SEC_RELOC
14734 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14735 record_alignment (seg
, 4);
14736 demand_empty_rest_of_line ();
14740 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14741 bfd_set_section_flags (stdoutput
, seg
,
14742 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14743 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14744 record_alignment (seg
, 4);
14745 demand_empty_rest_of_line ();
14749 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14750 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14751 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14752 record_alignment (seg
, 4);
14753 demand_empty_rest_of_line ();
14761 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14763 char *section_name
;
14768 int section_entry_size
;
14769 int section_alignment
;
14771 section_name
= input_line_pointer
;
14772 c
= get_symbol_end ();
14774 next_c
= *(input_line_pointer
+ 1);
14776 /* Do we have .section Name<,"flags">? */
14777 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14779 /* just after name is now '\0'. */
14780 *input_line_pointer
= c
;
14781 input_line_pointer
= section_name
;
14782 obj_elf_section (ignore
);
14785 input_line_pointer
++;
14787 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14789 section_type
= get_absolute_expression ();
14792 if (*input_line_pointer
++ == ',')
14793 section_flag
= get_absolute_expression ();
14796 if (*input_line_pointer
++ == ',')
14797 section_entry_size
= get_absolute_expression ();
14799 section_entry_size
= 0;
14800 if (*input_line_pointer
++ == ',')
14801 section_alignment
= get_absolute_expression ();
14803 section_alignment
= 0;
14804 /* FIXME: really ignore? */
14805 (void) section_alignment
;
14807 section_name
= xstrdup (section_name
);
14809 /* When using the generic form of .section (as implemented by obj-elf.c),
14810 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14811 traditionally had to fall back on the more common @progbits instead.
14813 There's nothing really harmful in this, since bfd will correct
14814 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14815 means that, for backwards compatibility, the special_section entries
14816 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14818 Even so, we shouldn't force users of the MIPS .section syntax to
14819 incorrectly label the sections as SHT_PROGBITS. The best compromise
14820 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14821 generic type-checking code. */
14822 if (section_type
== SHT_MIPS_DWARF
)
14823 section_type
= SHT_PROGBITS
;
14825 obj_elf_change_section (section_name
, section_type
, section_flag
,
14826 section_entry_size
, 0, 0, 0);
14828 if (now_seg
->name
!= section_name
)
14829 free (section_name
);
14833 mips_enable_auto_align (void)
14839 s_cons (int log_size
)
14841 segment_info_type
*si
= seg_info (now_seg
);
14842 struct insn_label_list
*l
= si
->label_list
;
14844 mips_emit_delays ();
14845 if (log_size
> 0 && auto_align
)
14846 mips_align (log_size
, 0, l
);
14847 cons (1 << log_size
);
14848 mips_clear_insn_labels ();
14852 s_float_cons (int type
)
14854 segment_info_type
*si
= seg_info (now_seg
);
14855 struct insn_label_list
*l
= si
->label_list
;
14857 mips_emit_delays ();
14862 mips_align (3, 0, l
);
14864 mips_align (2, 0, l
);
14868 mips_clear_insn_labels ();
14871 /* Handle .globl. We need to override it because on Irix 5 you are
14874 where foo is an undefined symbol, to mean that foo should be
14875 considered to be the address of a function. */
14878 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14887 name
= input_line_pointer
;
14888 c
= get_symbol_end ();
14889 symbolP
= symbol_find_or_make (name
);
14890 S_SET_EXTERNAL (symbolP
);
14892 *input_line_pointer
= c
;
14893 SKIP_WHITESPACE ();
14895 /* On Irix 5, every global symbol that is not explicitly labelled as
14896 being a function is apparently labelled as being an object. */
14899 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14900 && (*input_line_pointer
!= ','))
14905 secname
= input_line_pointer
;
14906 c
= get_symbol_end ();
14907 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14909 as_bad (_("%s: no such section"), secname
);
14910 *input_line_pointer
= c
;
14912 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14913 flag
= BSF_FUNCTION
;
14916 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14918 c
= *input_line_pointer
;
14921 input_line_pointer
++;
14922 SKIP_WHITESPACE ();
14923 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14929 demand_empty_rest_of_line ();
14933 s_option (int x ATTRIBUTE_UNUSED
)
14938 opt
= input_line_pointer
;
14939 c
= get_symbol_end ();
14943 /* FIXME: What does this mean? */
14945 else if (strncmp (opt
, "pic", 3) == 0)
14949 i
= atoi (opt
+ 3);
14954 mips_pic
= SVR4_PIC
;
14955 mips_abicalls
= TRUE
;
14958 as_bad (_(".option pic%d not supported"), i
);
14960 if (mips_pic
== SVR4_PIC
)
14962 if (g_switch_seen
&& g_switch_value
!= 0)
14963 as_warn (_("-G may not be used with SVR4 PIC code"));
14964 g_switch_value
= 0;
14965 bfd_set_gp_size (stdoutput
, 0);
14969 as_warn (_("unrecognized option \"%s\""), opt
);
14971 *input_line_pointer
= c
;
14972 demand_empty_rest_of_line ();
14975 /* This structure is used to hold a stack of .set values. */
14977 struct mips_option_stack
14979 struct mips_option_stack
*next
;
14980 struct mips_set_options options
;
14983 static struct mips_option_stack
*mips_opts_stack
;
14985 /* Handle the .set pseudo-op. */
14988 s_mipsset (int x ATTRIBUTE_UNUSED
)
14990 char *name
= input_line_pointer
, ch
;
14991 const struct mips_ase
*ase
;
14993 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14994 ++input_line_pointer
;
14995 ch
= *input_line_pointer
;
14996 *input_line_pointer
= '\0';
14998 if (strcmp (name
, "reorder") == 0)
15000 if (mips_opts
.noreorder
)
15003 else if (strcmp (name
, "noreorder") == 0)
15005 if (!mips_opts
.noreorder
)
15006 start_noreorder ();
15008 else if (strncmp (name
, "at=", 3) == 0)
15010 char *s
= name
+ 3;
15012 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
15013 as_bad (_("unrecognized register name `%s'"), s
);
15015 else if (strcmp (name
, "at") == 0)
15017 mips_opts
.at
= ATREG
;
15019 else if (strcmp (name
, "noat") == 0)
15021 mips_opts
.at
= ZERO
;
15023 else if (strcmp (name
, "macro") == 0)
15025 mips_opts
.warn_about_macros
= 0;
15027 else if (strcmp (name
, "nomacro") == 0)
15029 if (mips_opts
.noreorder
== 0)
15030 as_bad (_("`noreorder' must be set before `nomacro'"));
15031 mips_opts
.warn_about_macros
= 1;
15033 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15035 mips_opts
.nomove
= 0;
15037 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15039 mips_opts
.nomove
= 1;
15041 else if (strcmp (name
, "bopt") == 0)
15043 mips_opts
.nobopt
= 0;
15045 else if (strcmp (name
, "nobopt") == 0)
15047 mips_opts
.nobopt
= 1;
15049 else if (strcmp (name
, "gp=default") == 0)
15050 mips_opts
.gp32
= file_mips_gp32
;
15051 else if (strcmp (name
, "gp=32") == 0)
15052 mips_opts
.gp32
= 1;
15053 else if (strcmp (name
, "gp=64") == 0)
15055 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15056 as_warn (_("%s isa does not support 64-bit registers"),
15057 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15058 mips_opts
.gp32
= 0;
15060 else if (strcmp (name
, "fp=default") == 0)
15061 mips_opts
.fp32
= file_mips_fp32
;
15062 else if (strcmp (name
, "fp=32") == 0)
15063 mips_opts
.fp32
= 1;
15064 else if (strcmp (name
, "fp=64") == 0)
15066 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15067 as_warn (_("%s isa does not support 64-bit floating point registers"),
15068 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15069 mips_opts
.fp32
= 0;
15071 else if (strcmp (name
, "softfloat") == 0)
15072 mips_opts
.soft_float
= 1;
15073 else if (strcmp (name
, "hardfloat") == 0)
15074 mips_opts
.soft_float
= 0;
15075 else if (strcmp (name
, "singlefloat") == 0)
15076 mips_opts
.single_float
= 1;
15077 else if (strcmp (name
, "doublefloat") == 0)
15078 mips_opts
.single_float
= 0;
15079 else if (strcmp (name
, "mips16") == 0
15080 || strcmp (name
, "MIPS-16") == 0)
15082 if (mips_opts
.micromips
== 1)
15083 as_fatal (_("`mips16' cannot be used with `micromips'"));
15084 mips_opts
.mips16
= 1;
15086 else if (strcmp (name
, "nomips16") == 0
15087 || strcmp (name
, "noMIPS-16") == 0)
15088 mips_opts
.mips16
= 0;
15089 else if (strcmp (name
, "micromips") == 0)
15091 if (mips_opts
.mips16
== 1)
15092 as_fatal (_("`micromips' cannot be used with `mips16'"));
15093 mips_opts
.micromips
= 1;
15095 else if (strcmp (name
, "nomicromips") == 0)
15096 mips_opts
.micromips
= 0;
15097 else if (name
[0] == 'n'
15099 && (ase
= mips_lookup_ase (name
+ 2)))
15100 mips_set_ase (ase
, FALSE
);
15101 else if ((ase
= mips_lookup_ase (name
)))
15102 mips_set_ase (ase
, TRUE
);
15103 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15107 /* Permit the user to change the ISA and architecture on the fly.
15108 Needless to say, misuse can cause serious problems. */
15109 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15112 mips_opts
.isa
= file_mips_isa
;
15113 mips_opts
.arch
= file_mips_arch
;
15115 else if (strncmp (name
, "arch=", 5) == 0)
15117 const struct mips_cpu_info
*p
;
15119 p
= mips_parse_cpu("internal use", name
+ 5);
15121 as_bad (_("unknown architecture %s"), name
+ 5);
15124 mips_opts
.arch
= p
->cpu
;
15125 mips_opts
.isa
= p
->isa
;
15128 else if (strncmp (name
, "mips", 4) == 0)
15130 const struct mips_cpu_info
*p
;
15132 p
= mips_parse_cpu("internal use", name
);
15134 as_bad (_("unknown ISA level %s"), name
+ 4);
15137 mips_opts
.arch
= p
->cpu
;
15138 mips_opts
.isa
= p
->isa
;
15142 as_bad (_("unknown ISA or architecture %s"), name
);
15144 switch (mips_opts
.isa
)
15154 mips_opts
.gp32
= 1;
15155 mips_opts
.fp32
= 1;
15164 mips_opts
.gp32
= 0;
15165 if (mips_opts
.arch
== CPU_R5900
)
15167 mips_opts
.fp32
= 1;
15171 mips_opts
.fp32
= 0;
15175 as_bad (_("unknown ISA level %s"), name
+ 4);
15180 mips_opts
.gp32
= file_mips_gp32
;
15181 mips_opts
.fp32
= file_mips_fp32
;
15184 else if (strcmp (name
, "autoextend") == 0)
15185 mips_opts
.noautoextend
= 0;
15186 else if (strcmp (name
, "noautoextend") == 0)
15187 mips_opts
.noautoextend
= 1;
15188 else if (strcmp (name
, "insn32") == 0)
15189 mips_opts
.insn32
= TRUE
;
15190 else if (strcmp (name
, "noinsn32") == 0)
15191 mips_opts
.insn32
= FALSE
;
15192 else if (strcmp (name
, "push") == 0)
15194 struct mips_option_stack
*s
;
15196 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15197 s
->next
= mips_opts_stack
;
15198 s
->options
= mips_opts
;
15199 mips_opts_stack
= s
;
15201 else if (strcmp (name
, "pop") == 0)
15203 struct mips_option_stack
*s
;
15205 s
= mips_opts_stack
;
15207 as_bad (_(".set pop with no .set push"));
15210 /* If we're changing the reorder mode we need to handle
15211 delay slots correctly. */
15212 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15213 start_noreorder ();
15214 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15217 mips_opts
= s
->options
;
15218 mips_opts_stack
= s
->next
;
15222 else if (strcmp (name
, "sym32") == 0)
15223 mips_opts
.sym32
= TRUE
;
15224 else if (strcmp (name
, "nosym32") == 0)
15225 mips_opts
.sym32
= FALSE
;
15226 else if (strchr (name
, ','))
15228 /* Generic ".set" directive; use the generic handler. */
15229 *input_line_pointer
= ch
;
15230 input_line_pointer
= name
;
15236 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
15238 mips_check_isa_supports_ases ();
15239 *input_line_pointer
= ch
;
15240 demand_empty_rest_of_line ();
15243 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15244 .option pic2. It means to generate SVR4 PIC calls. */
15247 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15249 mips_pic
= SVR4_PIC
;
15250 mips_abicalls
= TRUE
;
15252 if (g_switch_seen
&& g_switch_value
!= 0)
15253 as_warn (_("-G may not be used with SVR4 PIC code"));
15254 g_switch_value
= 0;
15256 bfd_set_gp_size (stdoutput
, 0);
15257 demand_empty_rest_of_line ();
15260 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15261 PIC code. It sets the $gp register for the function based on the
15262 function address, which is in the register named in the argument.
15263 This uses a relocation against _gp_disp, which is handled specially
15264 by the linker. The result is:
15265 lui $gp,%hi(_gp_disp)
15266 addiu $gp,$gp,%lo(_gp_disp)
15267 addu $gp,$gp,.cpload argument
15268 The .cpload argument is normally $25 == $t9.
15270 The -mno-shared option changes this to:
15271 lui $gp,%hi(__gnu_local_gp)
15272 addiu $gp,$gp,%lo(__gnu_local_gp)
15273 and the argument is ignored. This saves an instruction, but the
15274 resulting code is not position independent; it uses an absolute
15275 address for __gnu_local_gp. Thus code assembled with -mno-shared
15276 can go into an ordinary executable, but not into a shared library. */
15279 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15285 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15286 .cpload is ignored. */
15287 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15293 if (mips_opts
.mips16
)
15295 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15296 ignore_rest_of_line ();
15300 /* .cpload should be in a .set noreorder section. */
15301 if (mips_opts
.noreorder
== 0)
15302 as_warn (_(".cpload not in noreorder section"));
15304 reg
= tc_get_register (0);
15306 /* If we need to produce a 64-bit address, we are better off using
15307 the default instruction sequence. */
15308 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15310 ex
.X_op
= O_symbol
;
15311 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15313 ex
.X_op_symbol
= NULL
;
15314 ex
.X_add_number
= 0;
15316 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15317 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15319 mips_mark_labels ();
15320 mips_assembling_insn
= TRUE
;
15323 macro_build_lui (&ex
, mips_gp_register
);
15324 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15325 mips_gp_register
, BFD_RELOC_LO16
);
15327 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15328 mips_gp_register
, reg
);
15331 mips_assembling_insn
= FALSE
;
15332 demand_empty_rest_of_line ();
15335 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15336 .cpsetup $reg1, offset|$reg2, label
15338 If offset is given, this results in:
15339 sd $gp, offset($sp)
15340 lui $gp, %hi(%neg(%gp_rel(label)))
15341 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15342 daddu $gp, $gp, $reg1
15344 If $reg2 is given, this results in:
15345 daddu $reg2, $gp, $0
15346 lui $gp, %hi(%neg(%gp_rel(label)))
15347 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15348 daddu $gp, $gp, $reg1
15349 $reg1 is normally $25 == $t9.
15351 The -mno-shared option replaces the last three instructions with
15353 addiu $gp,$gp,%lo(_gp) */
15356 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15358 expressionS ex_off
;
15359 expressionS ex_sym
;
15362 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15363 We also need NewABI support. */
15364 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15370 if (mips_opts
.mips16
)
15372 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15373 ignore_rest_of_line ();
15377 reg1
= tc_get_register (0);
15378 SKIP_WHITESPACE ();
15379 if (*input_line_pointer
!= ',')
15381 as_bad (_("missing argument separator ',' for .cpsetup"));
15385 ++input_line_pointer
;
15386 SKIP_WHITESPACE ();
15387 if (*input_line_pointer
== '$')
15389 mips_cpreturn_register
= tc_get_register (0);
15390 mips_cpreturn_offset
= -1;
15394 mips_cpreturn_offset
= get_absolute_expression ();
15395 mips_cpreturn_register
= -1;
15397 SKIP_WHITESPACE ();
15398 if (*input_line_pointer
!= ',')
15400 as_bad (_("missing argument separator ',' for .cpsetup"));
15404 ++input_line_pointer
;
15405 SKIP_WHITESPACE ();
15406 expression (&ex_sym
);
15408 mips_mark_labels ();
15409 mips_assembling_insn
= TRUE
;
15412 if (mips_cpreturn_register
== -1)
15414 ex_off
.X_op
= O_constant
;
15415 ex_off
.X_add_symbol
= NULL
;
15416 ex_off
.X_op_symbol
= NULL
;
15417 ex_off
.X_add_number
= mips_cpreturn_offset
;
15419 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15420 BFD_RELOC_LO16
, SP
);
15423 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15424 mips_gp_register
, 0);
15426 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15428 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15429 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15432 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15433 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15434 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15436 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15437 mips_gp_register
, reg1
);
15443 ex
.X_op
= O_symbol
;
15444 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15445 ex
.X_op_symbol
= NULL
;
15446 ex
.X_add_number
= 0;
15448 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15449 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15451 macro_build_lui (&ex
, mips_gp_register
);
15452 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15453 mips_gp_register
, BFD_RELOC_LO16
);
15458 mips_assembling_insn
= FALSE
;
15459 demand_empty_rest_of_line ();
15463 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15465 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15466 .cplocal is ignored. */
15467 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15473 if (mips_opts
.mips16
)
15475 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15476 ignore_rest_of_line ();
15480 mips_gp_register
= tc_get_register (0);
15481 demand_empty_rest_of_line ();
15484 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15485 offset from $sp. The offset is remembered, and after making a PIC
15486 call $gp is restored from that location. */
15489 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15493 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15494 .cprestore is ignored. */
15495 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15501 if (mips_opts
.mips16
)
15503 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15504 ignore_rest_of_line ();
15508 mips_cprestore_offset
= get_absolute_expression ();
15509 mips_cprestore_valid
= 1;
15511 ex
.X_op
= O_constant
;
15512 ex
.X_add_symbol
= NULL
;
15513 ex
.X_op_symbol
= NULL
;
15514 ex
.X_add_number
= mips_cprestore_offset
;
15516 mips_mark_labels ();
15517 mips_assembling_insn
= TRUE
;
15520 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15521 SP
, HAVE_64BIT_ADDRESSES
);
15524 mips_assembling_insn
= FALSE
;
15525 demand_empty_rest_of_line ();
15528 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15529 was given in the preceding .cpsetup, it results in:
15530 ld $gp, offset($sp)
15532 If a register $reg2 was given there, it results in:
15533 daddu $gp, $reg2, $0 */
15536 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15540 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15541 We also need NewABI support. */
15542 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15548 if (mips_opts
.mips16
)
15550 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15551 ignore_rest_of_line ();
15555 mips_mark_labels ();
15556 mips_assembling_insn
= TRUE
;
15559 if (mips_cpreturn_register
== -1)
15561 ex
.X_op
= O_constant
;
15562 ex
.X_add_symbol
= NULL
;
15563 ex
.X_op_symbol
= NULL
;
15564 ex
.X_add_number
= mips_cpreturn_offset
;
15566 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15569 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15570 mips_cpreturn_register
, 0);
15573 mips_assembling_insn
= FALSE
;
15574 demand_empty_rest_of_line ();
15577 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15578 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15579 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15580 debug information or MIPS16 TLS. */
15583 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15584 bfd_reloc_code_real_type rtype
)
15591 if (ex
.X_op
!= O_symbol
)
15593 as_bad (_("unsupported use of %s"), dirstr
);
15594 ignore_rest_of_line ();
15597 p
= frag_more (bytes
);
15598 md_number_to_chars (p
, 0, bytes
);
15599 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15600 demand_empty_rest_of_line ();
15601 mips_clear_insn_labels ();
15604 /* Handle .dtprelword. */
15607 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15609 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15612 /* Handle .dtpreldword. */
15615 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15617 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15620 /* Handle .tprelword. */
15623 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15625 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15628 /* Handle .tpreldword. */
15631 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15633 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15636 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15637 code. It sets the offset to use in gp_rel relocations. */
15640 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15642 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15643 We also need NewABI support. */
15644 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15650 mips_gprel_offset
= get_absolute_expression ();
15652 demand_empty_rest_of_line ();
15655 /* Handle the .gpword pseudo-op. This is used when generating PIC
15656 code. It generates a 32 bit GP relative reloc. */
15659 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15661 segment_info_type
*si
;
15662 struct insn_label_list
*l
;
15666 /* When not generating PIC code, this is treated as .word. */
15667 if (mips_pic
!= SVR4_PIC
)
15673 si
= seg_info (now_seg
);
15674 l
= si
->label_list
;
15675 mips_emit_delays ();
15677 mips_align (2, 0, l
);
15680 mips_clear_insn_labels ();
15682 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15684 as_bad (_("unsupported use of .gpword"));
15685 ignore_rest_of_line ();
15689 md_number_to_chars (p
, 0, 4);
15690 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15691 BFD_RELOC_GPREL32
);
15693 demand_empty_rest_of_line ();
15697 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15699 segment_info_type
*si
;
15700 struct insn_label_list
*l
;
15704 /* When not generating PIC code, this is treated as .dword. */
15705 if (mips_pic
!= SVR4_PIC
)
15711 si
= seg_info (now_seg
);
15712 l
= si
->label_list
;
15713 mips_emit_delays ();
15715 mips_align (3, 0, l
);
15718 mips_clear_insn_labels ();
15720 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15722 as_bad (_("unsupported use of .gpdword"));
15723 ignore_rest_of_line ();
15727 md_number_to_chars (p
, 0, 8);
15728 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15729 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15731 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15732 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15733 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15735 demand_empty_rest_of_line ();
15738 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15739 tables. It generates a R_MIPS_EH reloc. */
15742 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15747 mips_emit_delays ();
15750 mips_clear_insn_labels ();
15752 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15754 as_bad (_("unsupported use of .ehword"));
15755 ignore_rest_of_line ();
15759 md_number_to_chars (p
, 0, 4);
15760 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15761 BFD_RELOC_MIPS_EH
);
15763 demand_empty_rest_of_line ();
15766 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15767 tables in SVR4 PIC code. */
15770 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15774 /* This is ignored when not generating SVR4 PIC code. */
15775 if (mips_pic
!= SVR4_PIC
)
15781 mips_mark_labels ();
15782 mips_assembling_insn
= TRUE
;
15784 /* Add $gp to the register named as an argument. */
15786 reg
= tc_get_register (0);
15787 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15790 mips_assembling_insn
= FALSE
;
15791 demand_empty_rest_of_line ();
15794 /* Handle the .insn pseudo-op. This marks instruction labels in
15795 mips16/micromips mode. This permits the linker to handle them specially,
15796 such as generating jalx instructions when needed. We also make
15797 them odd for the duration of the assembly, in order to generate the
15798 right sort of code. We will make them even in the adjust_symtab
15799 routine, while leaving them marked. This is convenient for the
15800 debugger and the disassembler. The linker knows to make them odd
15804 s_insn (int ignore ATTRIBUTE_UNUSED
)
15806 mips_mark_labels ();
15808 demand_empty_rest_of_line ();
15811 /* Handle the .nan pseudo-op. */
15814 s_nan (int ignore ATTRIBUTE_UNUSED
)
15816 static const char str_legacy
[] = "legacy";
15817 static const char str_2008
[] = "2008";
15820 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15822 if (i
== sizeof (str_2008
) - 1
15823 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15824 mips_flag_nan2008
= TRUE
;
15825 else if (i
== sizeof (str_legacy
) - 1
15826 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15827 mips_flag_nan2008
= FALSE
;
15829 as_bad (_("bad .nan directive"));
15831 input_line_pointer
+= i
;
15832 demand_empty_rest_of_line ();
15835 /* Handle a .stab[snd] directive. Ideally these directives would be
15836 implemented in a transparent way, so that removing them would not
15837 have any effect on the generated instructions. However, s_stab
15838 internally changes the section, so in practice we need to decide
15839 now whether the preceding label marks compressed code. We do not
15840 support changing the compression mode of a label after a .stab*
15841 directive, such as in:
15847 so the current mode wins. */
15850 s_mips_stab (int type
)
15852 mips_mark_labels ();
15856 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15859 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15866 name
= input_line_pointer
;
15867 c
= get_symbol_end ();
15868 symbolP
= symbol_find_or_make (name
);
15869 S_SET_WEAK (symbolP
);
15870 *input_line_pointer
= c
;
15872 SKIP_WHITESPACE ();
15874 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15876 if (S_IS_DEFINED (symbolP
))
15878 as_bad (_("ignoring attempt to redefine symbol %s"),
15879 S_GET_NAME (symbolP
));
15880 ignore_rest_of_line ();
15884 if (*input_line_pointer
== ',')
15886 ++input_line_pointer
;
15887 SKIP_WHITESPACE ();
15891 if (exp
.X_op
!= O_symbol
)
15893 as_bad (_("bad .weakext directive"));
15894 ignore_rest_of_line ();
15897 symbol_set_value_expression (symbolP
, &exp
);
15900 demand_empty_rest_of_line ();
15903 /* Parse a register string into a number. Called from the ECOFF code
15904 to parse .frame. The argument is non-zero if this is the frame
15905 register, so that we can record it in mips_frame_reg. */
15908 tc_get_register (int frame
)
15912 SKIP_WHITESPACE ();
15913 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15917 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15918 mips_frame_reg_valid
= 1;
15919 mips_cprestore_valid
= 0;
15925 md_section_align (asection
*seg
, valueT addr
)
15927 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15929 /* We don't need to align ELF sections to the full alignment.
15930 However, Irix 5 may prefer that we align them at least to a 16
15931 byte boundary. We don't bother to align the sections if we
15932 are targeted for an embedded system. */
15933 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15938 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15941 /* Utility routine, called from above as well. If called while the
15942 input file is still being read, it's only an approximation. (For
15943 example, a symbol may later become defined which appeared to be
15944 undefined earlier.) */
15947 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15952 if (g_switch_value
> 0)
15954 const char *symname
;
15957 /* Find out whether this symbol can be referenced off the $gp
15958 register. It can be if it is smaller than the -G size or if
15959 it is in the .sdata or .sbss section. Certain symbols can
15960 not be referenced off the $gp, although it appears as though
15962 symname
= S_GET_NAME (sym
);
15963 if (symname
!= (const char *) NULL
15964 && (strcmp (symname
, "eprol") == 0
15965 || strcmp (symname
, "etext") == 0
15966 || strcmp (symname
, "_gp") == 0
15967 || strcmp (symname
, "edata") == 0
15968 || strcmp (symname
, "_fbss") == 0
15969 || strcmp (symname
, "_fdata") == 0
15970 || strcmp (symname
, "_ftext") == 0
15971 || strcmp (symname
, "end") == 0
15972 || strcmp (symname
, "_gp_disp") == 0))
15974 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15976 #ifndef NO_ECOFF_DEBUGGING
15977 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15978 && (symbol_get_obj (sym
)->ecoff_extern_size
15979 <= g_switch_value
))
15981 /* We must defer this decision until after the whole
15982 file has been read, since there might be a .extern
15983 after the first use of this symbol. */
15984 || (before_relaxing
15985 #ifndef NO_ECOFF_DEBUGGING
15986 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15988 && S_GET_VALUE (sym
) == 0)
15989 || (S_GET_VALUE (sym
) != 0
15990 && S_GET_VALUE (sym
) <= g_switch_value
)))
15994 const char *segname
;
15996 segname
= segment_name (S_GET_SEGMENT (sym
));
15997 gas_assert (strcmp (segname
, ".lit8") != 0
15998 && strcmp (segname
, ".lit4") != 0);
15999 change
= (strcmp (segname
, ".sdata") != 0
16000 && strcmp (segname
, ".sbss") != 0
16001 && strncmp (segname
, ".sdata.", 7) != 0
16002 && strncmp (segname
, ".sbss.", 6) != 0
16003 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
16004 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
16009 /* We are not optimizing for the $gp register. */
16014 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16017 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16021 /* Handle the case of a symbol equated to another symbol. */
16022 while (symbol_equated_reloc_p (sym
))
16026 /* It's possible to get a loop here in a badly written program. */
16027 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16033 if (symbol_section_p (sym
))
16036 symsec
= S_GET_SEGMENT (sym
);
16038 /* This must duplicate the test in adjust_reloc_syms. */
16039 return (!bfd_is_und_section (symsec
)
16040 && !bfd_is_abs_section (symsec
)
16041 && !bfd_is_com_section (symsec
)
16042 && !s_is_linkonce (sym
, segtype
)
16043 /* A global or weak symbol is treated as external. */
16044 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16048 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16049 extended opcode. SEC is the section the frag is in. */
16052 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16055 const struct mips_int_operand
*operand
;
16060 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16062 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16065 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16066 operand
= mips16_immed_operand (type
, FALSE
);
16068 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16069 val
= S_GET_VALUE (fragp
->fr_symbol
);
16070 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16072 if (operand
->root
.type
== OP_PCREL
)
16074 const struct mips_pcrel_operand
*pcrel_op
;
16078 /* We won't have the section when we are called from
16079 mips_relax_frag. However, we will always have been called
16080 from md_estimate_size_before_relax first. If this is a
16081 branch to a different section, we mark it as such. If SEC is
16082 NULL, and the frag is not marked, then it must be a branch to
16083 the same section. */
16084 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16087 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16092 /* Must have been called from md_estimate_size_before_relax. */
16095 fragp
->fr_subtype
=
16096 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16098 /* FIXME: We should support this, and let the linker
16099 catch branches and loads that are out of range. */
16100 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16101 _("unsupported PC relative reference to different section"));
16105 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16106 /* Assume non-extended on the first relaxation pass.
16107 The address we have calculated will be bogus if this is
16108 a forward branch to another frag, as the forward frag
16109 will have fr_address == 0. */
16113 /* In this case, we know for sure that the symbol fragment is in
16114 the same section. If the relax_marker of the symbol fragment
16115 differs from the relax_marker of this fragment, we have not
16116 yet adjusted the symbol fragment fr_address. We want to add
16117 in STRETCH in order to get a better estimate of the address.
16118 This particularly matters because of the shift bits. */
16120 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16124 /* Adjust stretch for any alignment frag. Note that if have
16125 been expanding the earlier code, the symbol may be
16126 defined in what appears to be an earlier frag. FIXME:
16127 This doesn't handle the fr_subtype field, which specifies
16128 a maximum number of bytes to skip when doing an
16130 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16132 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16135 stretch
= - ((- stretch
)
16136 & ~ ((1 << (int) f
->fr_offset
) - 1));
16138 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16147 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16149 /* The base address rules are complicated. The base address of
16150 a branch is the following instruction. The base address of a
16151 PC relative load or add is the instruction itself, but if it
16152 is in a delay slot (in which case it can not be extended) use
16153 the address of the instruction whose delay slot it is in. */
16154 if (pcrel_op
->include_isa_bit
)
16158 /* If we are currently assuming that this frag should be
16159 extended, then, the current address is two bytes
16161 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16164 /* Ignore the low bit in the target, since it will be set
16165 for a text label. */
16168 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16170 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16173 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16175 /* If any of the shifted bits are set, we must use an extended
16176 opcode. If the address depends on the size of this
16177 instruction, this can lead to a loop, so we arrange to always
16178 use an extended opcode. We only check this when we are in
16179 the main relaxation loop, when SEC is NULL. */
16180 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16182 fragp
->fr_subtype
=
16183 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16187 /* If we are about to mark a frag as extended because the value
16188 is precisely the next value above maxtiny, then there is a
16189 chance of an infinite loop as in the following code:
16194 In this case when the la is extended, foo is 0x3fc bytes
16195 away, so the la can be shrunk, but then foo is 0x400 away, so
16196 the la must be extended. To avoid this loop, we mark the
16197 frag as extended if it was small, and is about to become
16198 extended with the next value above maxtiny. */
16199 maxtiny
= mips_int_operand_max (operand
);
16200 if (val
== maxtiny
+ (1 << operand
->shift
)
16201 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16204 fragp
->fr_subtype
=
16205 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16209 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16210 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16212 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16215 /* Compute the length of a branch sequence, and adjust the
16216 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16217 worst-case length is computed, with UPDATE being used to indicate
16218 whether an unconditional (-1), branch-likely (+1) or regular (0)
16219 branch is to be computed. */
16221 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16223 bfd_boolean toofar
;
16227 && S_IS_DEFINED (fragp
->fr_symbol
)
16228 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16233 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16235 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16239 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16242 /* If the symbol is not defined or it's in a different segment,
16243 assume the user knows what's going on and emit a short
16249 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16251 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16252 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16253 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16254 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16260 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16263 if (mips_pic
!= NO_PIC
)
16265 /* Additional space for PIC loading of target address. */
16267 if (mips_opts
.isa
== ISA_MIPS1
)
16268 /* Additional space for $at-stabilizing nop. */
16272 /* If branch is conditional. */
16273 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16280 /* Compute the length of a branch sequence, and adjust the
16281 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16282 worst-case length is computed, with UPDATE being used to indicate
16283 whether an unconditional (-1), or regular (0) branch is to be
16287 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16289 bfd_boolean toofar
;
16293 && S_IS_DEFINED (fragp
->fr_symbol
)
16294 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16299 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16300 /* Ignore the low bit in the target, since it will be set
16301 for a text label. */
16302 if ((val
& 1) != 0)
16305 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16309 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16312 /* If the symbol is not defined or it's in a different segment,
16313 assume the user knows what's going on and emit a short
16319 if (fragp
&& update
16320 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16321 fragp
->fr_subtype
= (toofar
16322 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16323 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16328 bfd_boolean compact_known
= fragp
!= NULL
;
16329 bfd_boolean compact
= FALSE
;
16330 bfd_boolean uncond
;
16333 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16335 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16337 uncond
= update
< 0;
16339 /* If label is out of range, we turn branch <br>:
16341 <br> label # 4 bytes
16347 nop # 2 bytes if compact && !PIC
16350 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16353 /* If assembling PIC code, we further turn:
16359 lw/ld at, %got(label)(gp) # 4 bytes
16360 d/addiu at, %lo(label) # 4 bytes
16363 if (mips_pic
!= NO_PIC
)
16366 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16368 <brneg> 0f # 4 bytes
16369 nop # 2 bytes if !compact
16372 length
+= (compact_known
&& compact
) ? 4 : 6;
16378 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16379 bit accordingly. */
16382 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16384 bfd_boolean toofar
;
16387 && S_IS_DEFINED (fragp
->fr_symbol
)
16388 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16394 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16395 /* Ignore the low bit in the target, since it will be set
16396 for a text label. */
16397 if ((val
& 1) != 0)
16400 /* Assume this is a 2-byte branch. */
16401 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16403 /* We try to avoid the infinite loop by not adding 2 more bytes for
16408 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16410 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16411 else if (type
== 'E')
16412 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16417 /* If the symbol is not defined or it's in a different segment,
16418 we emit a normal 32-bit branch. */
16421 if (fragp
&& update
16422 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16424 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16425 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16433 /* Estimate the size of a frag before relaxing. Unless this is the
16434 mips16, we are not really relaxing here, and the final size is
16435 encoded in the subtype information. For the mips16, we have to
16436 decide whether we are using an extended opcode or not. */
16439 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16443 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16446 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16448 return fragp
->fr_var
;
16451 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16452 /* We don't want to modify the EXTENDED bit here; it might get us
16453 into infinite loops. We change it only in mips_relax_frag(). */
16454 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16456 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16460 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16461 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16462 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16463 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16464 fragp
->fr_var
= length
;
16469 if (mips_pic
== NO_PIC
)
16470 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16471 else if (mips_pic
== SVR4_PIC
)
16472 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16473 else if (mips_pic
== VXWORKS_PIC
)
16474 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16481 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16482 return -RELAX_FIRST (fragp
->fr_subtype
);
16485 return -RELAX_SECOND (fragp
->fr_subtype
);
16488 /* This is called to see whether a reloc against a defined symbol
16489 should be converted into a reloc against a section. */
16492 mips_fix_adjustable (fixS
*fixp
)
16494 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16495 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16498 if (fixp
->fx_addsy
== NULL
)
16501 /* If symbol SYM is in a mergeable section, relocations of the form
16502 SYM + 0 can usually be made section-relative. The mergeable data
16503 is then identified by the section offset rather than by the symbol.
16505 However, if we're generating REL LO16 relocations, the offset is split
16506 between the LO16 and parterning high part relocation. The linker will
16507 need to recalculate the complete offset in order to correctly identify
16510 The linker has traditionally not looked for the parterning high part
16511 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16512 placed anywhere. Rather than break backwards compatibility by changing
16513 this, it seems better not to force the issue, and instead keep the
16514 original symbol. This will work with either linker behavior. */
16515 if ((lo16_reloc_p (fixp
->fx_r_type
)
16516 || reloc_needs_lo_p (fixp
->fx_r_type
))
16517 && HAVE_IN_PLACE_ADDENDS
16518 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16521 /* There is no place to store an in-place offset for JALR relocations.
16522 Likewise an in-range offset of limited PC-relative relocations may
16523 overflow the in-place relocatable field if recalculated against the
16524 start address of the symbol's containing section. */
16525 if (HAVE_IN_PLACE_ADDENDS
16526 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16527 || jalr_reloc_p (fixp
->fx_r_type
)))
16530 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16531 to a floating-point stub. The same is true for non-R_MIPS16_26
16532 relocations against MIPS16 functions; in this case, the stub becomes
16533 the function's canonical address.
16535 Floating-point stubs are stored in unique .mips16.call.* or
16536 .mips16.fn.* sections. If a stub T for function F is in section S,
16537 the first relocation in section S must be against F; this is how the
16538 linker determines the target function. All relocations that might
16539 resolve to T must also be against F. We therefore have the following
16540 restrictions, which are given in an intentionally-redundant way:
16542 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16545 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16546 if that stub might be used.
16548 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16551 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16552 that stub might be used.
16554 There is a further restriction:
16556 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16557 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16558 targets with in-place addends; the relocation field cannot
16559 encode the low bit.
16561 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16562 against a MIPS16 symbol. We deal with (5) by by not reducing any
16563 such relocations on REL targets.
16565 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16566 relocation against some symbol R, no relocation against R may be
16567 reduced. (Note that this deals with (2) as well as (1) because
16568 relocations against global symbols will never be reduced on ELF
16569 targets.) This approach is a little simpler than trying to detect
16570 stub sections, and gives the "all or nothing" per-symbol consistency
16571 that we have for MIPS16 symbols. */
16572 if (fixp
->fx_subsy
== NULL
16573 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16574 || *symbol_get_tc (fixp
->fx_addsy
)
16575 || (HAVE_IN_PLACE_ADDENDS
16576 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16577 && jmp_reloc_p (fixp
->fx_r_type
))))
16583 /* Translate internal representation of relocation info to BFD target
16587 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16589 static arelent
*retval
[4];
16591 bfd_reloc_code_real_type code
;
16593 memset (retval
, 0, sizeof(retval
));
16594 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16595 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16596 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16597 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16599 if (fixp
->fx_pcrel
)
16601 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16602 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16603 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16604 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16605 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16607 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16608 Relocations want only the symbol offset. */
16609 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16612 reloc
->addend
= fixp
->fx_addnumber
;
16614 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16615 entry to be used in the relocation's section offset. */
16616 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16618 reloc
->address
= reloc
->addend
;
16622 code
= fixp
->fx_r_type
;
16624 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16625 if (reloc
->howto
== NULL
)
16627 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16628 _("cannot represent %s relocation in this object file"
16630 bfd_get_reloc_code_name (code
));
16637 /* Relax a machine dependent frag. This returns the amount by which
16638 the current size of the frag should change. */
16641 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16643 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16645 offsetT old_var
= fragp
->fr_var
;
16647 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16649 return fragp
->fr_var
- old_var
;
16652 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16654 offsetT old_var
= fragp
->fr_var
;
16655 offsetT new_var
= 4;
16657 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16658 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16659 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16660 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16661 fragp
->fr_var
= new_var
;
16663 return new_var
- old_var
;
16666 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16669 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16671 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16673 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16678 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16680 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16687 /* Convert a machine dependent frag. */
16690 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16692 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16695 unsigned long insn
;
16699 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16700 insn
= read_insn (buf
);
16702 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16704 /* We generate a fixup instead of applying it right now
16705 because, if there are linker relaxations, we're going to
16706 need the relocations. */
16707 exp
.X_op
= O_symbol
;
16708 exp
.X_add_symbol
= fragp
->fr_symbol
;
16709 exp
.X_add_number
= fragp
->fr_offset
;
16711 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16712 BFD_RELOC_16_PCREL_S2
);
16713 fixp
->fx_file
= fragp
->fr_file
;
16714 fixp
->fx_line
= fragp
->fr_line
;
16716 buf
= write_insn (buf
, insn
);
16722 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16723 _("relaxed out-of-range branch into a jump"));
16725 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16728 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16730 /* Reverse the branch. */
16731 switch ((insn
>> 28) & 0xf)
16734 if ((insn
& 0xff000000) == 0x47000000
16735 || (insn
& 0xff600000) == 0x45600000)
16737 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
16738 reversed by tweaking bit 23. */
16739 insn
^= 0x00800000;
16743 /* bc[0-3][tf]l? instructions can have the condition
16744 reversed by tweaking a single TF bit, and their
16745 opcodes all have 0x4???????. */
16746 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16747 insn
^= 0x00010000;
16752 /* bltz 0x04000000 bgez 0x04010000
16753 bltzal 0x04100000 bgezal 0x04110000 */
16754 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16755 insn
^= 0x00010000;
16759 /* beq 0x10000000 bne 0x14000000
16760 blez 0x18000000 bgtz 0x1c000000 */
16761 insn
^= 0x04000000;
16769 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16771 /* Clear the and-link bit. */
16772 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16774 /* bltzal 0x04100000 bgezal 0x04110000
16775 bltzall 0x04120000 bgezall 0x04130000 */
16776 insn
&= ~0x00100000;
16779 /* Branch over the branch (if the branch was likely) or the
16780 full jump (not likely case). Compute the offset from the
16781 current instruction to branch to. */
16782 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16786 /* How many bytes in instructions we've already emitted? */
16787 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16788 /* How many bytes in instructions from here to the end? */
16789 i
= fragp
->fr_var
- i
;
16791 /* Convert to instruction count. */
16793 /* Branch counts from the next instruction. */
16796 /* Branch over the jump. */
16797 buf
= write_insn (buf
, insn
);
16800 buf
= write_insn (buf
, 0);
16802 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16804 /* beql $0, $0, 2f */
16806 /* Compute the PC offset from the current instruction to
16807 the end of the variable frag. */
16808 /* How many bytes in instructions we've already emitted? */
16809 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16810 /* How many bytes in instructions from here to the end? */
16811 i
= fragp
->fr_var
- i
;
16812 /* Convert to instruction count. */
16814 /* Don't decrement i, because we want to branch over the
16818 buf
= write_insn (buf
, insn
);
16819 buf
= write_insn (buf
, 0);
16823 if (mips_pic
== NO_PIC
)
16826 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16827 ? 0x0c000000 : 0x08000000);
16828 exp
.X_op
= O_symbol
;
16829 exp
.X_add_symbol
= fragp
->fr_symbol
;
16830 exp
.X_add_number
= fragp
->fr_offset
;
16832 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16833 FALSE
, BFD_RELOC_MIPS_JMP
);
16834 fixp
->fx_file
= fragp
->fr_file
;
16835 fixp
->fx_line
= fragp
->fr_line
;
16837 buf
= write_insn (buf
, insn
);
16841 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16843 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16844 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16845 insn
|= at
<< OP_SH_RT
;
16846 exp
.X_op
= O_symbol
;
16847 exp
.X_add_symbol
= fragp
->fr_symbol
;
16848 exp
.X_add_number
= fragp
->fr_offset
;
16850 if (fragp
->fr_offset
)
16852 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16853 exp
.X_add_number
= 0;
16856 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16857 FALSE
, BFD_RELOC_MIPS_GOT16
);
16858 fixp
->fx_file
= fragp
->fr_file
;
16859 fixp
->fx_line
= fragp
->fr_line
;
16861 buf
= write_insn (buf
, insn
);
16863 if (mips_opts
.isa
== ISA_MIPS1
)
16865 buf
= write_insn (buf
, 0);
16867 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16868 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16869 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16871 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16872 FALSE
, BFD_RELOC_LO16
);
16873 fixp
->fx_file
= fragp
->fr_file
;
16874 fixp
->fx_line
= fragp
->fr_line
;
16876 buf
= write_insn (buf
, insn
);
16879 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16883 insn
|= at
<< OP_SH_RS
;
16885 buf
= write_insn (buf
, insn
);
16889 fragp
->fr_fix
+= fragp
->fr_var
;
16890 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16894 /* Relax microMIPS branches. */
16895 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16897 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16898 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16899 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16900 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16901 bfd_boolean short_ds
;
16902 unsigned long insn
;
16906 exp
.X_op
= O_symbol
;
16907 exp
.X_add_symbol
= fragp
->fr_symbol
;
16908 exp
.X_add_number
= fragp
->fr_offset
;
16910 fragp
->fr_fix
+= fragp
->fr_var
;
16912 /* Handle 16-bit branches that fit or are forced to fit. */
16913 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16915 /* We generate a fixup instead of applying it right now,
16916 because if there is linker relaxation, we're going to
16917 need the relocations. */
16919 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16920 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16921 else if (type
== 'E')
16922 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16923 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16927 fixp
->fx_file
= fragp
->fr_file
;
16928 fixp
->fx_line
= fragp
->fr_line
;
16930 /* These relocations can have an addend that won't fit in
16932 fixp
->fx_no_overflow
= 1;
16937 /* Handle 32-bit branches that fit or are forced to fit. */
16938 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16939 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16941 /* We generate a fixup instead of applying it right now,
16942 because if there is linker relaxation, we're going to
16943 need the relocations. */
16944 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16945 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16946 fixp
->fx_file
= fragp
->fr_file
;
16947 fixp
->fx_line
= fragp
->fr_line
;
16953 /* Relax 16-bit branches to 32-bit branches. */
16956 insn
= read_compressed_insn (buf
, 2);
16958 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16959 insn
= 0x94000000; /* beq */
16960 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16962 unsigned long regno
;
16964 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16965 regno
= micromips_to_32_reg_d_map
[regno
];
16966 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16967 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16972 /* Nothing else to do, just write it out. */
16973 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16974 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16976 buf
= write_compressed_insn (buf
, insn
, 4);
16977 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16982 insn
= read_compressed_insn (buf
, 4);
16984 /* Relax 32-bit branches to a sequence of instructions. */
16985 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16986 _("relaxed out-of-range branch into a jump"));
16988 /* Set the short-delay-slot bit. */
16989 short_ds
= al
&& (insn
& 0x02000000) != 0;
16991 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16995 /* Reverse the branch. */
16996 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16997 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16998 insn
^= 0x20000000;
16999 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
17000 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
17001 || (insn
& 0xffe00000) == 0x40800000 /* blez */
17002 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
17003 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
17004 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
17005 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
17006 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
17007 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
17008 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
17009 insn
^= 0x00400000;
17010 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
17011 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
17012 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
17013 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
17014 insn
^= 0x00200000;
17015 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
17017 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
17019 insn
^= 0x00800000;
17025 /* Clear the and-link and short-delay-slot bits. */
17026 gas_assert ((insn
& 0xfda00000) == 0x40200000);
17028 /* bltzal 0x40200000 bgezal 0x40600000 */
17029 /* bltzals 0x42200000 bgezals 0x42600000 */
17030 insn
&= ~0x02200000;
17033 /* Make a label at the end for use with the branch. */
17034 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17035 micromips_label_inc ();
17036 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17039 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17040 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17041 fixp
->fx_file
= fragp
->fr_file
;
17042 fixp
->fx_line
= fragp
->fr_line
;
17044 /* Branch over the jump. */
17045 buf
= write_compressed_insn (buf
, insn
, 4);
17048 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17051 if (mips_pic
== NO_PIC
)
17053 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17055 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17056 insn
= al
? jal
: 0xd4000000;
17058 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17059 BFD_RELOC_MICROMIPS_JMP
);
17060 fixp
->fx_file
= fragp
->fr_file
;
17061 fixp
->fx_line
= fragp
->fr_line
;
17063 buf
= write_compressed_insn (buf
, insn
, 4);
17066 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17070 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17071 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17072 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17074 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17075 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17076 insn
|= at
<< MICROMIPSOP_SH_RT
;
17078 if (exp
.X_add_number
)
17080 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17081 exp
.X_add_number
= 0;
17084 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17085 BFD_RELOC_MICROMIPS_GOT16
);
17086 fixp
->fx_file
= fragp
->fr_file
;
17087 fixp
->fx_line
= fragp
->fr_line
;
17089 buf
= write_compressed_insn (buf
, insn
, 4);
17091 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17092 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17093 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17095 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17096 BFD_RELOC_MICROMIPS_LO16
);
17097 fixp
->fx_file
= fragp
->fr_file
;
17098 fixp
->fx_line
= fragp
->fr_line
;
17100 buf
= write_compressed_insn (buf
, insn
, 4);
17102 /* jr/jrc/jalr/jalrs $at */
17103 insn
= al
? jalr
: jr
;
17104 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17106 buf
= write_compressed_insn (buf
, insn
, 2);
17109 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17113 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17116 const struct mips_int_operand
*operand
;
17119 unsigned int user_length
, length
;
17120 unsigned long insn
;
17123 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17124 operand
= mips16_immed_operand (type
, FALSE
);
17126 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17127 val
= resolve_symbol_value (fragp
->fr_symbol
);
17128 if (operand
->root
.type
== OP_PCREL
)
17130 const struct mips_pcrel_operand
*pcrel_op
;
17133 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17134 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17136 /* The rules for the base address of a PC relative reloc are
17137 complicated; see mips16_extended_frag. */
17138 if (pcrel_op
->include_isa_bit
)
17143 /* Ignore the low bit in the target, since it will be
17144 set for a text label. */
17147 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17149 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17152 addr
&= -(1 << pcrel_op
->align_log2
);
17155 /* Make sure the section winds up with the alignment we have
17157 if (operand
->shift
> 0)
17158 record_alignment (asec
, operand
->shift
);
17162 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17163 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17164 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17165 _("extended instruction in delay slot"));
17167 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17169 insn
= read_compressed_insn (buf
, 2);
17171 insn
|= MIPS16_EXTEND
;
17173 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17175 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17180 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17181 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17183 length
= (ext
? 4 : 2);
17184 gas_assert (mips16_opcode_length (insn
) == length
);
17185 write_compressed_insn (buf
, insn
, length
);
17186 fragp
->fr_fix
+= length
;
17190 relax_substateT subtype
= fragp
->fr_subtype
;
17191 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17192 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17196 first
= RELAX_FIRST (subtype
);
17197 second
= RELAX_SECOND (subtype
);
17198 fixp
= (fixS
*) fragp
->fr_opcode
;
17200 /* If the delay slot chosen does not match the size of the instruction,
17201 then emit a warning. */
17202 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17203 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17208 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17209 | RELAX_DELAY_SLOT_SIZE_FIRST
17210 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17211 msg
= macro_warning (s
);
17213 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17217 /* Possibly emit a warning if we've chosen the longer option. */
17218 if (use_second
== second_longer
)
17224 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17225 msg
= macro_warning (s
);
17227 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17231 /* Go through all the fixups for the first sequence. Disable them
17232 (by marking them as done) if we're going to use the second
17233 sequence instead. */
17235 && fixp
->fx_frag
== fragp
17236 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17238 if (subtype
& RELAX_USE_SECOND
)
17240 fixp
= fixp
->fx_next
;
17243 /* Go through the fixups for the second sequence. Disable them if
17244 we're going to use the first sequence, otherwise adjust their
17245 addresses to account for the relaxation. */
17246 while (fixp
&& fixp
->fx_frag
== fragp
)
17248 if (subtype
& RELAX_USE_SECOND
)
17249 fixp
->fx_where
-= first
;
17252 fixp
= fixp
->fx_next
;
17255 /* Now modify the frag contents. */
17256 if (subtype
& RELAX_USE_SECOND
)
17260 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17261 memmove (start
, start
+ first
, second
);
17262 fragp
->fr_fix
-= first
;
17265 fragp
->fr_fix
-= second
;
17269 /* This function is called after the relocs have been generated.
17270 We've been storing mips16 text labels as odd. Here we convert them
17271 back to even for the convenience of the debugger. */
17274 mips_frob_file_after_relocs (void)
17277 unsigned int count
, i
;
17279 syms
= bfd_get_outsymbols (stdoutput
);
17280 count
= bfd_get_symcount (stdoutput
);
17281 for (i
= 0; i
< count
; i
++, syms
++)
17282 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17283 && ((*syms
)->value
& 1) != 0)
17285 (*syms
)->value
&= ~1;
17286 /* If the symbol has an odd size, it was probably computed
17287 incorrectly, so adjust that as well. */
17288 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17289 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17293 /* This function is called whenever a label is defined, including fake
17294 labels instantiated off the dot special symbol. It is used when
17295 handling branch delays; if a branch has a label, we assume we cannot
17296 move it. This also bumps the value of the symbol by 1 in compressed
17300 mips_record_label (symbolS
*sym
)
17302 segment_info_type
*si
= seg_info (now_seg
);
17303 struct insn_label_list
*l
;
17305 if (free_insn_labels
== NULL
)
17306 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17309 l
= free_insn_labels
;
17310 free_insn_labels
= l
->next
;
17314 l
->next
= si
->label_list
;
17315 si
->label_list
= l
;
17318 /* This function is called as tc_frob_label() whenever a label is defined
17319 and adds a DWARF-2 record we only want for true labels. */
17322 mips_define_label (symbolS
*sym
)
17324 mips_record_label (sym
);
17325 dwarf2_emit_label (sym
);
17328 /* This function is called by tc_new_dot_label whenever a new dot symbol
17332 mips_add_dot_label (symbolS
*sym
)
17334 mips_record_label (sym
);
17335 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17336 mips_compressed_mark_label (sym
);
17339 /* Some special processing for a MIPS ELF file. */
17342 mips_elf_final_processing (void)
17344 /* Write out the register information. */
17345 if (mips_abi
!= N64_ABI
)
17349 s
.ri_gprmask
= mips_gprmask
;
17350 s
.ri_cprmask
[0] = mips_cprmask
[0];
17351 s
.ri_cprmask
[1] = mips_cprmask
[1];
17352 s
.ri_cprmask
[2] = mips_cprmask
[2];
17353 s
.ri_cprmask
[3] = mips_cprmask
[3];
17354 /* The gp_value field is set by the MIPS ELF backend. */
17356 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17357 ((Elf32_External_RegInfo
*)
17358 mips_regmask_frag
));
17362 Elf64_Internal_RegInfo s
;
17364 s
.ri_gprmask
= mips_gprmask
;
17366 s
.ri_cprmask
[0] = mips_cprmask
[0];
17367 s
.ri_cprmask
[1] = mips_cprmask
[1];
17368 s
.ri_cprmask
[2] = mips_cprmask
[2];
17369 s
.ri_cprmask
[3] = mips_cprmask
[3];
17370 /* The gp_value field is set by the MIPS ELF backend. */
17372 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17373 ((Elf64_External_RegInfo
*)
17374 mips_regmask_frag
));
17377 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17378 sort of BFD interface for this. */
17379 if (mips_any_noreorder
)
17380 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17381 if (mips_pic
!= NO_PIC
)
17383 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17384 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17387 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17389 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17390 defined at present; this might need to change in future. */
17391 if (file_ase_mips16
)
17392 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17393 if (file_ase_micromips
)
17394 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17395 if (file_ase
& ASE_MDMX
)
17396 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17398 /* Set the MIPS ELF ABI flags. */
17399 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17400 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17401 else if (mips_abi
== O64_ABI
)
17402 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17403 else if (mips_abi
== EABI_ABI
)
17405 if (!file_mips_gp32
)
17406 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17408 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17410 else if (mips_abi
== N32_ABI
)
17411 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17413 /* Nothing to do for N64_ABI. */
17415 if (mips_32bitmode
)
17416 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17418 if (mips_flag_nan2008
)
17419 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17421 /* 32 bit code with 64 bit FP registers. */
17422 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17423 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
17426 typedef struct proc
{
17428 symbolS
*func_end_sym
;
17429 unsigned long reg_mask
;
17430 unsigned long reg_offset
;
17431 unsigned long fpreg_mask
;
17432 unsigned long fpreg_offset
;
17433 unsigned long frame_offset
;
17434 unsigned long frame_reg
;
17435 unsigned long pc_reg
;
17438 static procS cur_proc
;
17439 static procS
*cur_proc_ptr
;
17440 static int numprocs
;
17442 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17443 as "2", and a normal nop as "0". */
17445 #define NOP_OPCODE_MIPS 0
17446 #define NOP_OPCODE_MIPS16 1
17447 #define NOP_OPCODE_MICROMIPS 2
17450 mips_nop_opcode (void)
17452 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17453 return NOP_OPCODE_MICROMIPS
;
17454 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17455 return NOP_OPCODE_MIPS16
;
17457 return NOP_OPCODE_MIPS
;
17460 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17461 32-bit microMIPS NOPs here (if applicable). */
17464 mips_handle_align (fragS
*fragp
)
17468 int bytes
, size
, excess
;
17471 if (fragp
->fr_type
!= rs_align_code
)
17474 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17476 switch (nop_opcode
)
17478 case NOP_OPCODE_MICROMIPS
:
17479 opcode
= micromips_nop32_insn
.insn_opcode
;
17482 case NOP_OPCODE_MIPS16
:
17483 opcode
= mips16_nop_insn
.insn_opcode
;
17486 case NOP_OPCODE_MIPS
:
17488 opcode
= nop_insn
.insn_opcode
;
17493 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17494 excess
= bytes
% size
;
17496 /* Handle the leading part if we're not inserting a whole number of
17497 instructions, and make it the end of the fixed part of the frag.
17498 Try to fit in a short microMIPS NOP if applicable and possible,
17499 and use zeroes otherwise. */
17500 gas_assert (excess
< 4);
17501 fragp
->fr_fix
+= excess
;
17506 /* Fall through. */
17508 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17510 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17514 /* Fall through. */
17517 /* Fall through. */
17522 md_number_to_chars (p
, opcode
, size
);
17523 fragp
->fr_var
= size
;
17527 md_obj_begin (void)
17534 /* Check for premature end, nesting errors, etc. */
17536 as_warn (_("missing .end at end of assembly"));
17545 if (*input_line_pointer
== '-')
17547 ++input_line_pointer
;
17550 if (!ISDIGIT (*input_line_pointer
))
17551 as_bad (_("expected simple number"));
17552 if (input_line_pointer
[0] == '0')
17554 if (input_line_pointer
[1] == 'x')
17556 input_line_pointer
+= 2;
17557 while (ISXDIGIT (*input_line_pointer
))
17560 val
|= hex_value (*input_line_pointer
++);
17562 return negative
? -val
: val
;
17566 ++input_line_pointer
;
17567 while (ISDIGIT (*input_line_pointer
))
17570 val
|= *input_line_pointer
++ - '0';
17572 return negative
? -val
: val
;
17575 if (!ISDIGIT (*input_line_pointer
))
17577 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17578 *input_line_pointer
, *input_line_pointer
);
17579 as_warn (_("invalid number"));
17582 while (ISDIGIT (*input_line_pointer
))
17585 val
+= *input_line_pointer
++ - '0';
17587 return negative
? -val
: val
;
17590 /* The .file directive; just like the usual .file directive, but there
17591 is an initial number which is the ECOFF file index. In the non-ECOFF
17592 case .file implies DWARF-2. */
17595 s_mips_file (int x ATTRIBUTE_UNUSED
)
17597 static int first_file_directive
= 0;
17599 if (ECOFF_DEBUGGING
)
17608 filename
= dwarf2_directive_file (0);
17610 /* Versions of GCC up to 3.1 start files with a ".file"
17611 directive even for stabs output. Make sure that this
17612 ".file" is handled. Note that you need a version of GCC
17613 after 3.1 in order to support DWARF-2 on MIPS. */
17614 if (filename
!= NULL
&& ! first_file_directive
)
17616 (void) new_logical_line (filename
, -1);
17617 s_app_file_string (filename
, 0);
17619 first_file_directive
= 1;
17623 /* The .loc directive, implying DWARF-2. */
17626 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17628 if (!ECOFF_DEBUGGING
)
17629 dwarf2_directive_loc (0);
17632 /* The .end directive. */
17635 s_mips_end (int x ATTRIBUTE_UNUSED
)
17639 /* Following functions need their own .frame and .cprestore directives. */
17640 mips_frame_reg_valid
= 0;
17641 mips_cprestore_valid
= 0;
17643 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17646 demand_empty_rest_of_line ();
17651 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17652 as_warn (_(".end not in text section"));
17656 as_warn (_(".end directive without a preceding .ent directive"));
17657 demand_empty_rest_of_line ();
17663 gas_assert (S_GET_NAME (p
));
17664 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17665 as_warn (_(".end symbol does not match .ent symbol"));
17667 if (debug_type
== DEBUG_STABS
)
17668 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17672 as_warn (_(".end directive missing or unknown symbol"));
17674 /* Create an expression to calculate the size of the function. */
17675 if (p
&& cur_proc_ptr
)
17677 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17678 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17681 exp
->X_op
= O_subtract
;
17682 exp
->X_add_symbol
= symbol_temp_new_now ();
17683 exp
->X_op_symbol
= p
;
17684 exp
->X_add_number
= 0;
17686 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17689 /* Generate a .pdr section. */
17690 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17692 segT saved_seg
= now_seg
;
17693 subsegT saved_subseg
= now_subseg
;
17697 #ifdef md_flush_pending_output
17698 md_flush_pending_output ();
17701 gas_assert (pdr_seg
);
17702 subseg_set (pdr_seg
, 0);
17704 /* Write the symbol. */
17705 exp
.X_op
= O_symbol
;
17706 exp
.X_add_symbol
= p
;
17707 exp
.X_add_number
= 0;
17708 emit_expr (&exp
, 4);
17710 fragp
= frag_more (7 * 4);
17712 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17713 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17714 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17715 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17716 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17717 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17718 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17720 subseg_set (saved_seg
, saved_subseg
);
17723 cur_proc_ptr
= NULL
;
17726 /* The .aent and .ent directives. */
17729 s_mips_ent (int aent
)
17733 symbolP
= get_symbol ();
17734 if (*input_line_pointer
== ',')
17735 ++input_line_pointer
;
17736 SKIP_WHITESPACE ();
17737 if (ISDIGIT (*input_line_pointer
)
17738 || *input_line_pointer
== '-')
17741 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17742 as_warn (_(".ent or .aent not in text section"));
17744 if (!aent
&& cur_proc_ptr
)
17745 as_warn (_("missing .end"));
17749 /* This function needs its own .frame and .cprestore directives. */
17750 mips_frame_reg_valid
= 0;
17751 mips_cprestore_valid
= 0;
17753 cur_proc_ptr
= &cur_proc
;
17754 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17756 cur_proc_ptr
->func_sym
= symbolP
;
17760 if (debug_type
== DEBUG_STABS
)
17761 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17762 S_GET_NAME (symbolP
));
17765 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17767 demand_empty_rest_of_line ();
17770 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17771 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17772 s_mips_frame is used so that we can set the PDR information correctly.
17773 We can't use the ecoff routines because they make reference to the ecoff
17774 symbol table (in the mdebug section). */
17777 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17779 if (ECOFF_DEBUGGING
)
17785 if (cur_proc_ptr
== (procS
*) NULL
)
17787 as_warn (_(".frame outside of .ent"));
17788 demand_empty_rest_of_line ();
17792 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17794 SKIP_WHITESPACE ();
17795 if (*input_line_pointer
++ != ','
17796 || get_absolute_expression_and_terminator (&val
) != ',')
17798 as_warn (_("bad .frame directive"));
17799 --input_line_pointer
;
17800 demand_empty_rest_of_line ();
17804 cur_proc_ptr
->frame_offset
= val
;
17805 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17807 demand_empty_rest_of_line ();
17811 /* The .fmask and .mask directives. If the mdebug section is present
17812 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17813 embedded targets, s_mips_mask is used so that we can set the PDR
17814 information correctly. We can't use the ecoff routines because they
17815 make reference to the ecoff symbol table (in the mdebug section). */
17818 s_mips_mask (int reg_type
)
17820 if (ECOFF_DEBUGGING
)
17821 s_ignore (reg_type
);
17826 if (cur_proc_ptr
== (procS
*) NULL
)
17828 as_warn (_(".mask/.fmask outside of .ent"));
17829 demand_empty_rest_of_line ();
17833 if (get_absolute_expression_and_terminator (&mask
) != ',')
17835 as_warn (_("bad .mask/.fmask directive"));
17836 --input_line_pointer
;
17837 demand_empty_rest_of_line ();
17841 off
= get_absolute_expression ();
17843 if (reg_type
== 'F')
17845 cur_proc_ptr
->fpreg_mask
= mask
;
17846 cur_proc_ptr
->fpreg_offset
= off
;
17850 cur_proc_ptr
->reg_mask
= mask
;
17851 cur_proc_ptr
->reg_offset
= off
;
17854 demand_empty_rest_of_line ();
17858 /* A table describing all the processors gas knows about. Names are
17859 matched in the order listed.
17861 To ease comparison, please keep this table in the same order as
17862 gcc's mips_cpu_info_table[]. */
17863 static const struct mips_cpu_info mips_cpu_info_table
[] =
17865 /* Entries for generic ISAs */
17866 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17867 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17868 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17869 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17870 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17871 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17872 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17873 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
17874 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
17875 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17876 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17877 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
17878 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
17881 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17882 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17883 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17886 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17889 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17890 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17891 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17892 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17893 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17894 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17895 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17896 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17897 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17898 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17899 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17900 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17901 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17902 /* ST Microelectronics Loongson 2E and 2F cores */
17903 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17904 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17907 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17908 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17909 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17910 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17911 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17912 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17913 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17914 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17915 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17916 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17917 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17918 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17919 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17920 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17921 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17924 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17925 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17926 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17927 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17929 /* MIPS 32 Release 2 */
17930 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17931 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17932 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17933 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17934 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17935 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17936 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17937 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17938 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17939 ISA_MIPS32R2
, CPU_MIPS32R2
},
17940 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17941 ISA_MIPS32R2
, CPU_MIPS32R2
},
17942 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17943 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17944 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17945 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17946 /* Deprecated forms of the above. */
17947 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17948 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17949 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17950 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17951 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17952 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17953 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17954 /* Deprecated forms of the above. */
17955 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17956 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17957 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17958 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17959 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17960 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17961 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17962 /* Deprecated forms of the above. */
17963 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17964 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17965 /* 34Kn is a 34kc without DSP. */
17966 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17967 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17968 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17969 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17970 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17971 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17972 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17973 /* Deprecated forms of the above. */
17974 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17975 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17976 /* 1004K cores are multiprocessor versions of the 34K. */
17977 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17978 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17979 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17980 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17981 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
17982 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
17985 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17986 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17987 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17988 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17990 /* Broadcom SB-1 CPU core */
17991 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17992 /* Broadcom SB-1A CPU core */
17993 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17995 { "loongson3a", 0, 0, ISA_MIPS64R2
, CPU_LOONGSON_3A
},
17997 /* MIPS 64 Release 2 */
17999 /* Cavium Networks Octeon CPU core */
18000 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
18001 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
18002 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
18005 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
18008 XLP is mostly like XLR, with the prominent exception that it is
18009 MIPS64R2 rather than MIPS64. */
18010 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
18013 { NULL
, 0, 0, 0, 0 }
18017 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
18018 with a final "000" replaced by "k". Ignore case.
18020 Note: this function is shared between GCC and GAS. */
18023 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
18025 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
18026 given
++, canonical
++;
18028 return ((*given
== 0 && *canonical
== 0)
18029 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
18033 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
18034 CPU name. We've traditionally allowed a lot of variation here.
18036 Note: this function is shared between GCC and GAS. */
18039 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18041 /* First see if the name matches exactly, or with a final "000"
18042 turned into "k". */
18043 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18046 /* If not, try comparing based on numerical designation alone.
18047 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18048 if (TOLOWER (*given
) == 'r')
18050 if (!ISDIGIT (*given
))
18053 /* Skip over some well-known prefixes in the canonical name,
18054 hoping to find a number there too. */
18055 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18057 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18059 else if (TOLOWER (canonical
[0]) == 'r')
18062 return mips_strict_matching_cpu_name_p (canonical
, given
);
18066 /* Parse an option that takes the name of a processor as its argument.
18067 OPTION is the name of the option and CPU_STRING is the argument.
18068 Return the corresponding processor enumeration if the CPU_STRING is
18069 recognized, otherwise report an error and return null.
18071 A similar function exists in GCC. */
18073 static const struct mips_cpu_info
*
18074 mips_parse_cpu (const char *option
, const char *cpu_string
)
18076 const struct mips_cpu_info
*p
;
18078 /* 'from-abi' selects the most compatible architecture for the given
18079 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18080 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18081 version. Look first at the -mgp options, if given, otherwise base
18082 the choice on MIPS_DEFAULT_64BIT.
18084 Treat NO_ABI like the EABIs. One reason to do this is that the
18085 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18086 architecture. This code picks MIPS I for 'mips' and MIPS III for
18087 'mips64', just as we did in the days before 'from-abi'. */
18088 if (strcasecmp (cpu_string
, "from-abi") == 0)
18090 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18091 return mips_cpu_info_from_isa (ISA_MIPS1
);
18093 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18094 return mips_cpu_info_from_isa (ISA_MIPS3
);
18096 if (file_mips_gp32
>= 0)
18097 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
18099 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18104 /* 'default' has traditionally been a no-op. Probably not very useful. */
18105 if (strcasecmp (cpu_string
, "default") == 0)
18108 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18109 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18112 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
18116 /* Return the canonical processor information for ISA (a member of the
18117 ISA_MIPS* enumeration). */
18119 static const struct mips_cpu_info
*
18120 mips_cpu_info_from_isa (int isa
)
18124 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18125 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18126 && isa
== mips_cpu_info_table
[i
].isa
)
18127 return (&mips_cpu_info_table
[i
]);
18132 static const struct mips_cpu_info
*
18133 mips_cpu_info_from_arch (int arch
)
18137 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18138 if (arch
== mips_cpu_info_table
[i
].cpu
)
18139 return (&mips_cpu_info_table
[i
]);
18145 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18149 fprintf (stream
, "%24s", "");
18154 fprintf (stream
, ", ");
18158 if (*col_p
+ strlen (string
) > 72)
18160 fprintf (stream
, "\n%24s", "");
18164 fprintf (stream
, "%s", string
);
18165 *col_p
+= strlen (string
);
18171 md_show_usage (FILE *stream
)
18176 fprintf (stream
, _("\
18178 -EB generate big endian output\n\
18179 -EL generate little endian output\n\
18180 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18181 -G NUM allow referencing objects up to NUM bytes\n\
18182 implicitly with the gp register [default 8]\n"));
18183 fprintf (stream
, _("\
18184 -mips1 generate MIPS ISA I instructions\n\
18185 -mips2 generate MIPS ISA II instructions\n\
18186 -mips3 generate MIPS ISA III instructions\n\
18187 -mips4 generate MIPS ISA IV instructions\n\
18188 -mips5 generate MIPS ISA V instructions\n\
18189 -mips32 generate MIPS32 ISA instructions\n\
18190 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18191 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
18192 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
18193 -mips64 generate MIPS64 ISA instructions\n\
18194 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18195 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
18196 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
18197 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18201 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18202 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18203 show (stream
, "from-abi", &column
, &first
);
18204 fputc ('\n', stream
);
18206 fprintf (stream
, _("\
18207 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18208 -no-mCPU don't generate code specific to CPU.\n\
18209 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18213 show (stream
, "3900", &column
, &first
);
18214 show (stream
, "4010", &column
, &first
);
18215 show (stream
, "4100", &column
, &first
);
18216 show (stream
, "4650", &column
, &first
);
18217 fputc ('\n', stream
);
18219 fprintf (stream
, _("\
18220 -mips16 generate mips16 instructions\n\
18221 -no-mips16 do not generate mips16 instructions\n"));
18222 fprintf (stream
, _("\
18223 -mmicromips generate microMIPS instructions\n\
18224 -mno-micromips do not generate microMIPS instructions\n"));
18225 fprintf (stream
, _("\
18226 -msmartmips generate smartmips instructions\n\
18227 -mno-smartmips do not generate smartmips instructions\n"));
18228 fprintf (stream
, _("\
18229 -mdsp generate DSP instructions\n\
18230 -mno-dsp do not generate DSP instructions\n"));
18231 fprintf (stream
, _("\
18232 -mdspr2 generate DSP R2 instructions\n\
18233 -mno-dspr2 do not generate DSP R2 instructions\n"));
18234 fprintf (stream
, _("\
18235 -mmt generate MT instructions\n\
18236 -mno-mt do not generate MT instructions\n"));
18237 fprintf (stream
, _("\
18238 -mmcu generate MCU instructions\n\
18239 -mno-mcu do not generate MCU instructions\n"));
18240 fprintf (stream
, _("\
18241 -mmsa generate MSA instructions\n\
18242 -mno-msa do not generate MSA instructions\n"));
18243 fprintf (stream
, _("\
18244 -mxpa generate eXtended Physical Address (XPA) instructions\n\
18245 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
18246 fprintf (stream
, _("\
18247 -mvirt generate Virtualization instructions\n\
18248 -mno-virt do not generate Virtualization instructions\n"));
18249 fprintf (stream
, _("\
18250 -minsn32 only generate 32-bit microMIPS instructions\n\
18251 -mno-insn32 generate all microMIPS instructions\n"));
18252 fprintf (stream
, _("\
18253 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18254 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18255 -mfix-vr4120 work around certain VR4120 errata\n\
18256 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18257 -mfix-24k insert a nop after ERET and DERET instructions\n\
18258 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18259 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18260 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18261 -msym32 assume all symbols have 32-bit values\n\
18262 -O0 remove unneeded NOPs, do not swap branches\n\
18263 -O remove unneeded NOPs and swap branches\n\
18264 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18265 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18266 fprintf (stream
, _("\
18267 -mhard-float allow floating-point instructions\n\
18268 -msoft-float do not allow floating-point instructions\n\
18269 -msingle-float only allow 32-bit floating-point operations\n\
18270 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18271 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18272 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18273 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18277 show (stream
, "legacy", &column
, &first
);
18278 show (stream
, "2008", &column
, &first
);
18280 fputc ('\n', stream
);
18282 fprintf (stream
, _("\
18283 -KPIC, -call_shared generate SVR4 position independent code\n\
18284 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18285 -mvxworks-pic generate VxWorks position independent code\n\
18286 -non_shared do not generate code that can operate with DSOs\n\
18287 -xgot assume a 32 bit GOT\n\
18288 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18289 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18290 position dependent (non shared) code\n\
18291 -mabi=ABI create ABI conformant object file for:\n"));
18295 show (stream
, "32", &column
, &first
);
18296 show (stream
, "o64", &column
, &first
);
18297 show (stream
, "n32", &column
, &first
);
18298 show (stream
, "64", &column
, &first
);
18299 show (stream
, "eabi", &column
, &first
);
18301 fputc ('\n', stream
);
18303 fprintf (stream
, _("\
18304 -32 create o32 ABI object file (default)\n\
18305 -n32 create n32 ABI object file\n\
18306 -64 create 64 ABI object file\n"));
18311 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18313 if (HAVE_64BIT_SYMBOLS
)
18314 return dwarf2_format_64bit_irix
;
18316 return dwarf2_format_32bit
;
18321 mips_dwarf2_addr_size (void)
18323 if (HAVE_64BIT_OBJECTS
)
18329 /* Standard calling conventions leave the CFA at SP on entry. */
18331 mips_cfi_frame_initial_instructions (void)
18333 cfi_add_CFA_def_cfa_register (SP
);
18337 tc_mips_regname_to_dw2regnum (char *regname
)
18339 unsigned int regnum
= -1;
18342 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
18348 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
18349 Given a symbolic attribute NAME, return the proper integer value.
18350 Returns -1 if the attribute is not known. */
18353 mips_convert_symbolic_attribute (const char *name
)
18355 static const struct
18360 attribute_table
[] =
18362 #define T(tag) {#tag, tag}
18363 T (Tag_GNU_MIPS_ABI_FP
),
18364 T (Tag_GNU_MIPS_ABI_MSA
),
18372 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
18373 if (streq (name
, attribute_table
[i
].name
))
18374 return attribute_table
[i
].tag
;