1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* start-sanitize-r5900 */
152 /* Whether Toshiba r5900 instructions are permitted. */
153 static int mips_5900
= -1;
154 /* end-sanitize-r5900 */
156 /* Whether the processor uses hardware interlocks, and thus does not
157 require nops to be inserted. */
158 static int interlocks
= -1;
160 /* As with "interlocks" this is used by hardware that has FP
161 (co-processor) interlocks. */
162 static int cop_interlocks
= -1;
164 /* MIPS PIC level. */
168 /* Do not generate PIC code. */
171 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
172 not sure what it is supposed to do. */
175 /* Generate PIC code as in the SVR4 MIPS ABI. */
178 /* Generate PIC code without using a global offset table: the data
179 segment has a maximum size of 64K, all data references are off
180 the $gp register, and all text references are PC relative. This
181 is used on some embedded systems. */
185 static enum mips_pic_level mips_pic
;
187 /* 1 if we should generate 32 bit offsets from the GP register in
188 SVR4_PIC mode. Currently has no meaning in other modes. */
189 static int mips_big_got
;
191 /* 1 if trap instructions should used for overflow rather than break
193 static int mips_trap
;
195 /* 1 if we should autoextend mips16 instructions. */
196 static int mips16_autoextend
= 1;
198 static int mips_warn_about_macros
;
199 static int mips_noreorder
;
200 static int mips_any_noreorder
;
201 static int mips_nomove
;
202 static int mips_noat
;
203 static int mips_nobopt
;
205 /* The size of the small data section. */
206 static int g_switch_value
= 8;
207 /* Whether the -G option was used. */
208 static int g_switch_seen
= 0;
213 /* If we can determine in advance that GP optimization won't be
214 possible, we can skip the relaxation stuff that tries to produce
215 GP-relative references. This makes delay slot optimization work
218 This function can only provide a guess, but it seems to work for
219 gcc output. If it guesses wrong, the only loss should be in
220 efficiency; it shouldn't introduce any bugs.
222 I don't know if a fix is needed for the SVR4_PIC mode. I've only
223 fixed it for the non-PIC mode. KR 95/04/07 */
224 static int nopic_need_relax
PARAMS ((symbolS
*));
226 /* handle of the OPCODE hash table */
227 static struct hash_control
*op_hash
= NULL
;
229 /* The opcode hash table we use for the mips16. */
230 static struct hash_control
*mips16_op_hash
= NULL
;
232 /* This array holds the chars that always start a comment. If the
233 pre-processor is disabled, these aren't very useful */
234 const char comment_chars
[] = "#";
236 /* This array holds the chars that only start a comment at the beginning of
237 a line. If the line seems to have the form '# 123 filename'
238 .line and .file directives will appear in the pre-processed output */
239 /* Note that input_file.c hand checks for '#' at the beginning of the
240 first line of the input file. This is because the compiler outputs
241 #NO_APP at the beginning of its output. */
242 /* Also note that C style comments are always supported. */
243 const char line_comment_chars
[] = "#";
245 /* This array holds machine specific line separator characters. */
246 const char line_separator_chars
[] = "";
248 /* Chars that can be used to separate mant from exp in floating point nums */
249 const char EXP_CHARS
[] = "eE";
251 /* Chars that mean this number is a floating point constant */
254 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
256 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
257 changed in read.c . Ideally it shouldn't have to know about it at all,
258 but nothing is ideal around here.
261 static char *insn_error
;
263 static int auto_align
= 1;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc type for the previous instruction, if any. */
308 static bfd_reloc_code_real_type prev_insn_reloc_type
;
310 /* The reloc for the previous instruction, if any. */
311 static fixS
*prev_insn_fixp
;
313 /* Non-zero if the previous instruction was in a delay slot. */
314 static int prev_insn_is_delay_slot
;
316 /* Non-zero if the previous instruction was in a .set noreorder. */
317 static int prev_insn_unreordered
;
319 /* Non-zero if the previous instruction uses an extend opcode (if
321 static int prev_insn_extended
;
323 /* Non-zero if the previous previous instruction was in a .set
325 static int prev_prev_insn_unreordered
;
327 /* If this is set, it points to a frag holding nop instructions which
328 were inserted before the start of a noreorder section. If those
329 nops turn out to be unnecessary, the size of the frag can be
331 static fragS
*prev_nop_frag
;
333 /* The number of nop instructions we created in prev_nop_frag. */
334 static int prev_nop_frag_holds
;
336 /* The number of nop instructions that we know we need in
338 static int prev_nop_frag_required
;
340 /* The number of instructions we've seen since prev_nop_frag. */
341 static int prev_nop_frag_since
;
343 /* For ECOFF and ELF, relocations against symbols are done in two
344 parts, with a HI relocation and a LO relocation. Each relocation
345 has only 16 bits of space to store an addend. This means that in
346 order for the linker to handle carries correctly, it must be able
347 to locate both the HI and the LO relocation. This means that the
348 relocations must appear in order in the relocation table.
350 In order to implement this, we keep track of each unmatched HI
351 relocation. We then sort them so that they immediately precede the
352 corresponding LO relocation. */
357 struct mips_hi_fixup
*next
;
360 /* The section this fixup is in. */
364 /* The list of unmatched HI relocs. */
366 static struct mips_hi_fixup
*mips_hi_fixup_list
;
368 /* Map normal MIPS register numbers to mips16 register numbers. */
370 #define X ILLEGAL_REG
371 static const int mips32_to_16_reg_map
[] =
373 X
, X
, 2, 3, 4, 5, 6, 7,
374 X
, X
, X
, X
, X
, X
, X
, X
,
375 0, 1, X
, X
, X
, X
, X
, X
,
376 X
, X
, X
, X
, X
, X
, X
, X
380 /* Map mips16 register numbers to normal MIPS register numbers. */
382 static const int mips16_to_32_reg_map
[] =
384 16, 17, 2, 3, 4, 5, 6, 7
387 /* Since the MIPS does not have multiple forms of PC relative
388 instructions, we do not have to do relaxing as is done on other
389 platforms. However, we do have to handle GP relative addressing
390 correctly, which turns out to be a similar problem.
392 Every macro that refers to a symbol can occur in (at least) two
393 forms, one with GP relative addressing and one without. For
394 example, loading a global variable into a register generally uses
395 a macro instruction like this:
397 If i can be addressed off the GP register (this is true if it is in
398 the .sbss or .sdata section, or if it is known to be smaller than
399 the -G argument) this will generate the following instruction:
401 This instruction will use a GPREL reloc. If i can not be addressed
402 off the GP register, the following instruction sequence will be used:
405 In this case the first instruction will have a HI16 reloc, and the
406 second reloc will have a LO16 reloc. Both relocs will be against
409 The issue here is that we may not know whether i is GP addressable
410 until after we see the instruction that uses it. Therefore, we
411 want to be able to choose the final instruction sequence only at
412 the end of the assembly. This is similar to the way other
413 platforms choose the size of a PC relative instruction only at the
416 When generating position independent code we do not use GP
417 addressing in quite the same way, but the issue still arises as
418 external symbols and local symbols must be handled differently.
420 We handle these issues by actually generating both possible
421 instruction sequences. The longer one is put in a frag_var with
422 type rs_machine_dependent. We encode what to do with the frag in
423 the subtype field. We encode (1) the number of existing bytes to
424 replace, (2) the number of new bytes to use, (3) the offset from
425 the start of the existing bytes to the first reloc we must generate
426 (that is, the offset is applied from the start of the existing
427 bytes after they are replaced by the new bytes, if any), (4) the
428 offset from the start of the existing bytes to the second reloc,
429 (5) whether a third reloc is needed (the third reloc is always four
430 bytes after the second reloc), and (6) whether to warn if this
431 variant is used (this is sometimes needed if .set nomacro or .set
432 noat is in effect). All these numbers are reasonably small.
434 Generating two instruction sequences must be handled carefully to
435 ensure that delay slots are handled correctly. Fortunately, there
436 are a limited number of cases. When the second instruction
437 sequence is generated, append_insn is directed to maintain the
438 existing delay slot information, so it continues to apply to any
439 code after the second instruction sequence. This means that the
440 second instruction sequence must not impose any requirements not
441 required by the first instruction sequence.
443 These variant frags are then handled in functions called by the
444 machine independent code. md_estimate_size_before_relax returns
445 the final size of the frag. md_convert_frag sets up the final form
446 of the frag. tc_gen_reloc adjust the first reloc and adds a second
448 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
452 | (((reloc1) + 64) << 9) \
453 | (((reloc2) + 64) << 2) \
454 | ((reloc3) ? (1 << 1) : 0) \
456 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
457 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
458 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
459 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
460 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
461 #define RELAX_WARN(i) ((i) & 1)
463 /* For mips16 code, we use an entirely different form of relaxation.
464 mips16 supports two versions of most instructions which take
465 immediate values: a small one which takes some small value, and a
466 larger one which takes a 16 bit value. Since branches also follow
467 this pattern, relaxing these values is required.
469 We can assemble both mips16 and normal MIPS code in a single
470 object. Therefore, we need to support this type of relaxation at
471 the same time that we support the relaxation described above. We
472 use the high bit of the subtype field to distinguish these cases.
474 The information we store for this type of relaxation is the
475 argument code found in the opcode file for this relocation, whether
476 the user explicitly requested a small or extended form, and whether
477 the relocation is in a jump or jal delay slot. That tells us the
478 size of the value, and how it should be stored. We also store
479 whether the fragment is considered to be extended or not. We also
480 store whether this is known to be a branch to a different section,
481 whether we have tried to relax this frag yet, and whether we have
482 ever extended a PC relative fragment because of a shift count. */
483 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
486 | ((small) ? 0x100 : 0) \
487 | ((ext) ? 0x200 : 0) \
488 | ((dslot) ? 0x400 : 0) \
489 | ((jal_dslot) ? 0x800 : 0))
490 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
491 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
492 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
493 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
494 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
495 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
496 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
497 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
498 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
499 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
500 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
501 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
503 /* Prototypes for static functions. */
506 #define internalError() \
507 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
509 #define internalError() as_fatal ("MIPS internal Error");
512 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
514 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
515 unsigned int reg
, enum mips_regclass
class));
516 static int reg_needs_delay
PARAMS ((int));
517 static void append_insn
PARAMS ((char *place
,
518 struct mips_cl_insn
* ip
,
520 bfd_reloc_code_real_type r
,
522 static void mips_no_prev_insn
PARAMS ((int));
523 static void mips_emit_delays
PARAMS ((boolean
));
525 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
526 const char *name
, const char *fmt
,
529 static void macro_build ();
531 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
532 const char *, const char *,
534 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
535 expressionS
* ep
, int regnum
));
536 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
537 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
539 static void load_register
PARAMS ((int *, int, expressionS
*, int));
540 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
541 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
542 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
543 #ifdef LOSING_COMPILER
544 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
546 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
547 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
548 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
549 boolean
, boolean
, unsigned long *,
550 boolean
*, unsigned short *));
551 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
552 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
553 static symbolS
*get_symbol
PARAMS ((void));
554 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
555 static void s_align
PARAMS ((int));
556 static void s_change_sec
PARAMS ((int));
557 static void s_cons
PARAMS ((int));
558 static void s_float_cons
PARAMS ((int));
559 static void s_mips_globl
PARAMS ((int));
560 static void s_option
PARAMS ((int));
561 static void s_mipsset
PARAMS ((int));
562 static void s_abicalls
PARAMS ((int));
563 static void s_cpload
PARAMS ((int));
564 static void s_cprestore
PARAMS ((int));
565 static void s_gpword
PARAMS ((int));
566 static void s_cpadd
PARAMS ((int));
567 static void s_insn
PARAMS ((int));
568 static void md_obj_begin
PARAMS ((void));
569 static void md_obj_end
PARAMS ((void));
570 static long get_number
PARAMS ((void));
571 static void s_ent
PARAMS ((int));
572 static void s_mipsend
PARAMS ((int));
573 static void s_file
PARAMS ((int));
574 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
578 The following pseudo-ops from the Kane and Heinrich MIPS book
579 should be defined here, but are currently unsupported: .alias,
580 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
582 The following pseudo-ops from the Kane and Heinrich MIPS book are
583 specific to the type of debugging information being generated, and
584 should be defined by the object format: .aent, .begin, .bend,
585 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
588 The following pseudo-ops from the Kane and Heinrich MIPS book are
589 not MIPS CPU specific, but are also not specific to the object file
590 format. This file is probably the best place to define them, but
591 they are not currently supported: .asm0, .endr, .lab, .repeat,
592 .struct, .weakext. */
594 static const pseudo_typeS mips_pseudo_table
[] =
596 /* MIPS specific pseudo-ops. */
597 {"option", s_option
, 0},
598 {"set", s_mipsset
, 0},
599 {"rdata", s_change_sec
, 'r'},
600 {"sdata", s_change_sec
, 's'},
601 {"livereg", s_ignore
, 0},
602 {"abicalls", s_abicalls
, 0},
603 {"cpload", s_cpload
, 0},
604 {"cprestore", s_cprestore
, 0},
605 {"gpword", s_gpword
, 0},
606 {"cpadd", s_cpadd
, 0},
609 /* Relatively generic pseudo-ops that happen to be used on MIPS
611 {"asciiz", stringer
, 1},
612 {"bss", s_change_sec
, 'b'},
615 {"dword", s_cons
, 3},
617 /* These pseudo-ops are defined in read.c, but must be overridden
618 here for one reason or another. */
619 {"align", s_align
, 0},
621 {"data", s_change_sec
, 'd'},
622 {"double", s_float_cons
, 'd'},
623 {"float", s_float_cons
, 'f'},
624 {"globl", s_mips_globl
, 0},
625 {"global", s_mips_globl
, 0},
626 {"hword", s_cons
, 1},
631 {"short", s_cons
, 1},
632 {"single", s_float_cons
, 'f'},
633 {"text", s_change_sec
, 't'},
638 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
639 /* These pseudo-ops should be defined by the object file format.
640 However, a.out doesn't support them, so we have versions here. */
642 {"bgnb", s_ignore
, 0},
643 {"end", s_mipsend
, 0},
644 {"endb", s_ignore
, 0},
647 {"fmask", s_ignore
, 'F'},
648 {"frame", s_ignore
, 0},
649 {"loc", s_ignore
, 0},
650 {"mask", s_ignore
, 'R'},
651 {"verstamp", s_ignore
, 0},
655 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
660 pop_insert (mips_pseudo_table
);
661 if (! ECOFF_DEBUGGING
)
662 pop_insert (mips_nonecoff_pseudo_table
);
665 /* Symbols labelling the current insn. */
667 struct insn_label_list
669 struct insn_label_list
*next
;
673 static struct insn_label_list
*insn_labels
;
674 static struct insn_label_list
*free_insn_labels
;
676 static void mips_clear_insn_labels
PARAMS ((void));
679 mips_clear_insn_labels ()
681 register struct insn_label_list
**pl
;
683 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
689 static char *expr_end
;
691 /* Expressions which appear in instructions. These are set by
694 static expressionS imm_expr
;
695 static expressionS offset_expr
;
697 /* Relocs associated with imm_expr and offset_expr. */
699 static bfd_reloc_code_real_type imm_reloc
;
700 static bfd_reloc_code_real_type offset_reloc
;
702 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
704 static boolean imm_unmatched_hi
;
706 /* These are set by mips16_ip if an explicit extension is used. */
708 static boolean mips16_small
, mips16_ext
;
711 * This function is called once, at assembler startup time. It should
712 * set up all the tables, etc. that the MD part of the assembler will need.
718 register const char *retval
= NULL
;
719 register unsigned int i
= 0;
727 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
729 a
= xmalloc (sizeof TARGET_CPU
);
730 strcpy (a
, TARGET_CPU
);
731 a
[(sizeof TARGET_CPU
) - 3] = '\0';
735 if (strcmp (cpu
, "mips") == 0)
741 else if (strcmp (cpu
, "r6000") == 0
742 || strcmp (cpu
, "mips2") == 0)
748 else if (strcmp (cpu
, "mips64") == 0
749 || strcmp (cpu
, "r4000") == 0
750 || strcmp (cpu
, "mips3") == 0)
756 else if (strcmp (cpu
, "r4400") == 0)
762 else if (strcmp (cpu
, "mips64orion") == 0
763 || strcmp (cpu
, "r4600") == 0)
769 else if (strcmp (cpu
, "r4650") == 0)
777 else if (strcmp (cpu
, "mips64vr4300") == 0)
783 else if (strcmp (cpu
, "mips64vr4100") == 0)
791 else if (strcmp (cpu
, "r4010") == 0)
799 else if (strcmp (cpu
, "r5000") == 0
800 || strcmp (cpu
, "mips64vr5000") == 0)
806 /* start-sanitize-r5900 */
807 else if (strcmp (cpu
, "r5900") == 0
808 || strcmp (cpu
, "mips64vr5900") == 0
809 || strcmp (cpu
, "mips64vr5900el") == 0)
817 /* end-sanitize-r5900 */
818 else if (strcmp (cpu
, "r8000") == 0
819 || strcmp (cpu
, "mips4") == 0)
825 else if (strcmp (cpu
, "r10000") == 0)
831 else if (strcmp (cpu
, "mips16") == 0)
835 mips_cpu
= 0; /* FIXME */
850 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
865 /* start-sanitize-r5900 */
868 /* end-sanitize-r5900 */
870 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
875 if (mips_cpu
== 4300)
880 if (mips_isa
< 2 && mips_trap
)
881 as_bad ("trap exception not supported at ISA 1");
886 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
889 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
892 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
895 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
899 as_warn ("Could not set architecture and machine");
901 file_mips_isa
= mips_isa
;
903 op_hash
= hash_new ();
905 for (i
= 0; i
< NUMOPCODES
;)
907 const char *name
= mips_opcodes
[i
].name
;
909 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
912 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
913 mips_opcodes
[i
].name
, retval
);
914 as_fatal ("Broken assembler. No assembly attempted.");
918 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
919 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
920 != mips_opcodes
[i
].match
))
922 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
923 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
924 as_fatal ("Broken assembler. No assembly attempted.");
928 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
931 mips16_op_hash
= hash_new ();
934 while (i
< bfd_mips16_num_opcodes
)
936 const char *name
= mips16_opcodes
[i
].name
;
938 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
940 as_fatal ("internal error: can't hash `%s': %s\n",
941 mips16_opcodes
[i
].name
, retval
);
944 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
945 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
946 != mips16_opcodes
[i
].match
))
947 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
948 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
951 while (i
< bfd_mips16_num_opcodes
952 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
955 /* We add all the general register names to the symbol table. This
956 helps us detect invalid uses of them. */
957 for (i
= 0; i
< 32; i
++)
961 sprintf (buf
, "$%d", i
);
962 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
963 &zero_address_frag
));
965 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
966 &zero_address_frag
));
967 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
968 &zero_address_frag
));
969 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
970 &zero_address_frag
));
971 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
972 &zero_address_frag
));
973 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
974 &zero_address_frag
));
975 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
976 &zero_address_frag
));
977 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
978 &zero_address_frag
));
980 mips_no_prev_insn (false);
988 /* set the default alignment for the text section (2**2) */
989 record_alignment (text_section
, 2);
991 if (USE_GLOBAL_POINTER_OPT
)
992 bfd_set_gp_size (stdoutput
, g_switch_value
);
994 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
996 /* On a native system, sections must be aligned to 16 byte
997 boundaries. When configured for an embedded ELF target, we
999 if (strcmp (TARGET_OS
, "elf") != 0)
1001 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1002 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1003 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1006 /* Create a .reginfo section for register masks and a .mdebug
1007 section for debugging information. */
1015 subseg
= now_subseg
;
1017 /* The ABI says this section should be loaded so that the
1018 running program can access it. However, we don't load it
1019 if we are configured for an embedded target */
1020 flags
= SEC_READONLY
| SEC_DATA
;
1021 if (strcmp (TARGET_OS
, "elf") != 0)
1022 flags
|= SEC_ALLOC
| SEC_LOAD
;
1026 sec
= subseg_new (".reginfo", (subsegT
) 0);
1029 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1030 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1033 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1038 /* The 64-bit ABI uses a .MIPS.options section rather than
1039 .reginfo section. */
1040 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1041 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1042 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1045 /* Set up the option header. */
1047 Elf_Internal_Options opthdr
;
1050 opthdr
.kind
= ODK_REGINFO
;
1051 opthdr
.size
= (sizeof (Elf_External_Options
)
1052 + sizeof (Elf64_External_RegInfo
));
1055 f
= frag_more (sizeof (Elf_External_Options
));
1056 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1057 (Elf_External_Options
*) f
);
1059 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1064 if (ECOFF_DEBUGGING
)
1066 sec
= subseg_new (".mdebug", (subsegT
) 0);
1067 (void) bfd_set_section_flags (stdoutput
, sec
,
1068 SEC_HAS_CONTENTS
| SEC_READONLY
);
1069 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1072 subseg_set (seg
, subseg
);
1076 if (! ECOFF_DEBUGGING
)
1083 if (! ECOFF_DEBUGGING
)
1091 struct mips_cl_insn insn
;
1093 imm_expr
.X_op
= O_absent
;
1094 imm_reloc
= BFD_RELOC_UNUSED
;
1095 imm_unmatched_hi
= false;
1096 offset_expr
.X_op
= O_absent
;
1097 offset_reloc
= BFD_RELOC_UNUSED
;
1100 mips16_ip (str
, &insn
);
1102 mips_ip (str
, &insn
);
1106 as_bad ("%s `%s'", insn_error
, str
);
1110 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1113 mips16_macro (&insn
);
1119 if (imm_expr
.X_op
!= O_absent
)
1120 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1122 else if (offset_expr
.X_op
!= O_absent
)
1123 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1125 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1129 /* See whether instruction IP reads register REG. CLASS is the type
1133 insn_uses_reg (ip
, reg
, class)
1134 struct mips_cl_insn
*ip
;
1136 enum mips_regclass
class;
1138 if (class == MIPS16_REG
)
1141 reg
= mips16_to_32_reg_map
[reg
];
1142 class = MIPS_GR_REG
;
1145 /* Don't report on general register 0, since it never changes. */
1146 if (class == MIPS_GR_REG
&& reg
== 0)
1149 if (class == MIPS_FP_REG
)
1152 /* If we are called with either $f0 or $f1, we must check $f0.
1153 This is not optimal, because it will introduce an unnecessary
1154 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1155 need to distinguish reading both $f0 and $f1 or just one of
1156 them. Note that we don't have to check the other way,
1157 because there is no instruction that sets both $f0 and $f1
1158 and requires a delay. */
1159 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1160 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1161 == (reg
&~ (unsigned) 1)))
1163 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1164 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1165 == (reg
&~ (unsigned) 1)))
1170 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1171 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1173 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1174 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1179 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1180 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1182 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1183 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1185 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1186 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1187 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1189 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1191 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1193 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1195 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1196 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1197 & MIPS16OP_MASK_REGR32
) == reg
)
1204 /* This function returns true if modifying a register requires a
1208 reg_needs_delay (reg
)
1211 unsigned long prev_pinfo
;
1213 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1214 if (! mips_noreorder
1216 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1218 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1220 /* A load from a coprocessor or from memory. All load
1221 delays delay the use of general register rt for one
1222 instruction on the r3000. The r6000 and r4000 use
1224 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1225 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1232 /* Output an instruction. PLACE is where to put the instruction; if
1233 it is NULL, this uses frag_more to get room. IP is the instruction
1234 information. ADDRESS_EXPR is an operand of the instruction to be
1235 used with RELOC_TYPE. */
1238 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1240 struct mips_cl_insn
*ip
;
1241 expressionS
*address_expr
;
1242 bfd_reloc_code_real_type reloc_type
;
1243 boolean unmatched_hi
;
1245 register unsigned long prev_pinfo
, pinfo
;
1250 /* Mark instruction labels in mips16 mode. This permits the linker
1251 to handle them specially, such as generating jalx instructions
1252 when needed. We also make them odd for the duration of the
1253 assembly, in order to generate the right sort of code. We will
1254 make them even in the adjust_symtab routine, while leaving them
1255 marked. This is convenient for the debugger and the
1256 disassembler. The linker knows to make them odd again. */
1259 struct insn_label_list
*l
;
1261 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1264 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1265 S_SET_OTHER (l
->label
, STO_MIPS16
);
1267 ++l
->label
->sy_value
.X_add_number
;
1271 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1272 pinfo
= ip
->insn_mo
->pinfo
;
1274 if (place
== NULL
&& (! mips_noreorder
|| prev_nop_frag
!= NULL
))
1278 /* If the previous insn required any delay slots, see if we need
1279 to insert a NOP or two. There are eight kinds of possible
1280 hazards, of which an instruction can have at most one type.
1281 (1) a load from memory delay
1282 (2) a load from a coprocessor delay
1283 (3) an unconditional branch delay
1284 (4) a conditional branch delay
1285 (5) a move to coprocessor register delay
1286 (6) a load coprocessor register from memory delay
1287 (7) a coprocessor condition code delay
1288 (8) a HI/LO special register delay
1290 There are a lot of optimizations we could do that we don't.
1291 In particular, we do not, in general, reorder instructions.
1292 If you use gcc with optimization, it will reorder
1293 instructions and generally do much more optimization then we
1294 do here; repeating all that work in the assembler would only
1295 benefit hand written assembly code, and does not seem worth
1298 /* This is how a NOP is emitted. */
1299 #define emit_nop() \
1301 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1302 : md_number_to_chars (frag_more (4), 0, 4))
1304 /* The previous insn might require a delay slot, depending upon
1305 the contents of the current insn. */
1308 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1309 && ! cop_interlocks
)
1311 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1313 /* A load from a coprocessor or from memory. All load
1314 delays delay the use of general register rt for one
1315 instruction on the r3000. The r6000 and r4000 use
1317 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1318 if (mips_optimize
== 0
1319 || insn_uses_reg (ip
,
1320 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1327 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1328 && ! cop_interlocks
)
1330 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1332 /* A generic coprocessor delay. The previous instruction
1333 modified a coprocessor general or control register. If
1334 it modified a control register, we need to avoid any
1335 coprocessor instruction (this is probably not always
1336 required, but it sometimes is). If it modified a general
1337 register, we avoid using that register.
1339 On the r6000 and r4000 loading a coprocessor register
1340 from memory is interlocked, and does not require a delay.
1342 This case is not handled very well. There is no special
1343 knowledge of CP0 handling, and the coprocessors other
1344 than the floating point unit are not distinguished at
1346 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1348 if (mips_optimize
== 0
1349 || insn_uses_reg (ip
,
1350 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1355 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1357 if (mips_optimize
== 0
1358 || insn_uses_reg (ip
,
1359 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1366 /* We don't know exactly what the previous instruction
1367 does. If the current instruction uses a coprocessor
1368 register, we must insert a NOP. If previous
1369 instruction may set the condition codes, and the
1370 current instruction uses them, we must insert two
1372 if (mips_optimize
== 0
1373 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1374 && (pinfo
& INSN_READ_COND_CODE
)))
1376 else if (pinfo
& INSN_COP
)
1382 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1383 && ! cop_interlocks
)
1385 /* The previous instruction sets the coprocessor condition
1386 codes, but does not require a general coprocessor delay
1387 (this means it is a floating point comparison
1388 instruction). If this instruction uses the condition
1389 codes, we need to insert a single NOP. */
1390 if (mips_optimize
== 0
1391 || (pinfo
& INSN_READ_COND_CODE
))
1394 else if (prev_pinfo
& INSN_READ_LO
)
1396 /* The previous instruction reads the LO register; if the
1397 current instruction writes to the LO register, we must
1398 insert two NOPS. Some newer processors have interlocks. */
1400 && (mips_optimize
== 0
1401 || (pinfo
& INSN_WRITE_LO
)))
1404 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1406 /* The previous instruction reads the HI register; if the
1407 current instruction writes to the HI register, we must
1408 insert a NOP. Some newer processors have interlocks. */
1410 && (mips_optimize
== 0
1411 || (pinfo
& INSN_WRITE_HI
)))
1415 /* If the previous instruction was in a noreorder section, then
1416 we don't want to insert the nop after all. */
1417 if (prev_insn_unreordered
)
1420 /* There are two cases which require two intervening
1421 instructions: 1) setting the condition codes using a move to
1422 coprocessor instruction which requires a general coprocessor
1423 delay and then reading the condition codes 2) reading the HI
1424 or LO register and then writing to it (except on processors
1425 which have interlocks). If we are not already emitting a NOP
1426 instruction, we must check for these cases compared to the
1427 instruction previous to the previous instruction. */
1430 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1431 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1432 && (pinfo
& INSN_READ_COND_CODE
)
1433 && ! cop_interlocks
)
1434 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1435 && (pinfo
& INSN_WRITE_LO
)
1437 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1438 && (pinfo
& INSN_WRITE_HI
)
1444 if (prev_prev_insn_unreordered
)
1447 if (prev_prev_nop
&& nops
== 0)
1450 /* If we are being given a nop instruction, don't bother with
1451 one of the nops we would otherwise output. This will only
1452 happen when a nop instruction is used with mips_optimize set
1456 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1459 /* Now emit the right number of NOP instructions. */
1460 if (nops
> 0 && ! mips_noreorder
)
1463 unsigned long old_frag_offset
;
1465 struct insn_label_list
*l
;
1467 old_frag
= frag_now
;
1468 old_frag_offset
= frag_now_fix ();
1470 for (i
= 0; i
< nops
; i
++)
1475 listing_prev_line ();
1476 /* We may be at the start of a variant frag. In case we
1477 are, make sure there is enough space for the frag
1478 after the frags created by listing_prev_line. The
1479 argument to frag_grow here must be at least as large
1480 as the argument to all other calls to frag_grow in
1481 this file. We don't have to worry about being in the
1482 middle of a variant frag, because the variants insert
1483 all needed nop instructions themselves. */
1487 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1489 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1490 l
->label
->sy_frag
= frag_now
;
1491 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1492 /* mips16 text labels are stored as odd. */
1494 ++l
->label
->sy_value
.X_add_number
;
1497 #ifndef NO_ECOFF_DEBUGGING
1498 if (ECOFF_DEBUGGING
)
1499 ecoff_fix_loc (old_frag
, old_frag_offset
);
1502 else if (prev_nop_frag
!= NULL
)
1504 /* We have a frag holding nops we may be able to remove. If
1505 we don't need any nops, we can decrease the size of
1506 prev_nop_frag by the size of one instruction. If we do
1507 need some nops, we count them in prev_nops_required. */
1508 if (prev_nop_frag_since
== 0)
1512 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1513 --prev_nop_frag_holds
;
1516 prev_nop_frag_required
+= nops
;
1520 if (prev_prev_nop
== 0)
1522 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1523 --prev_nop_frag_holds
;
1526 ++prev_nop_frag_required
;
1529 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1530 prev_nop_frag
= NULL
;
1532 ++prev_nop_frag_since
;
1534 /* Sanity check: by the time we reach the second instruction
1535 after prev_nop_frag, we should have used up all the nops
1536 one way or another. */
1537 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1541 if (reloc_type
> BFD_RELOC_UNUSED
)
1543 /* We need to set up a variant frag. */
1544 assert (mips16
&& address_expr
!= NULL
);
1545 f
= frag_var (rs_machine_dependent
, 4, 0,
1546 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1547 mips16_small
, mips16_ext
,
1549 & INSN_UNCOND_BRANCH_DELAY
),
1550 (prev_insn_reloc_type
1551 == BFD_RELOC_MIPS16_JMP
)),
1552 make_expr_symbol (address_expr
), (long) 0,
1555 else if (place
!= NULL
)
1557 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1559 /* Make sure there is enough room to swap this instruction with
1560 a following jump instruction. */
1568 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1569 as_warn ("extended instruction in delay slot");
1575 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1577 if (address_expr
->X_op
== O_constant
)
1582 ip
->insn_opcode
|= address_expr
->X_add_number
;
1585 case BFD_RELOC_LO16
:
1586 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1589 case BFD_RELOC_MIPS_JMP
:
1590 if ((address_expr
->X_add_number
& 3) != 0)
1591 as_bad ("jump to misaligned address (0x%lx)",
1592 (unsigned long) address_expr
->X_add_number
);
1593 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1596 case BFD_RELOC_MIPS16_JMP
:
1597 if ((address_expr
->X_add_number
& 3) != 0)
1598 as_bad ("jump to misaligned address (0x%lx)",
1599 (unsigned long) address_expr
->X_add_number
);
1601 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1602 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1603 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1606 case BFD_RELOC_16_PCREL_S2
:
1616 /* Don't generate a reloc if we are writing into a variant
1620 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1622 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1626 struct mips_hi_fixup
*hi_fixup
;
1628 assert (reloc_type
== BFD_RELOC_HI16_S
);
1629 hi_fixup
= ((struct mips_hi_fixup
*)
1630 xmalloc (sizeof (struct mips_hi_fixup
)));
1631 hi_fixup
->fixp
= fixp
;
1632 hi_fixup
->seg
= now_seg
;
1633 hi_fixup
->next
= mips_hi_fixup_list
;
1634 mips_hi_fixup_list
= hi_fixup
;
1641 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1642 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1644 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1645 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1651 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1654 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1657 /* Update the register mask information. */
1660 if (pinfo
& INSN_WRITE_GPR_D
)
1661 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1662 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1663 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1664 if (pinfo
& INSN_READ_GPR_S
)
1665 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1666 if (pinfo
& INSN_WRITE_GPR_31
)
1667 mips_gprmask
|= 1 << 31;
1668 if (pinfo
& INSN_WRITE_FPR_D
)
1669 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1670 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1671 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1672 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1673 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1674 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1675 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1676 if (pinfo
& INSN_COP
)
1678 /* We don't keep enough information to sort these cases out. */
1680 /* Never set the bit for $0, which is always zero. */
1681 mips_gprmask
&=~ 1 << 0;
1685 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1686 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1687 & MIPS16OP_MASK_RX
);
1688 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1689 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1690 & MIPS16OP_MASK_RY
);
1691 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1692 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1693 & MIPS16OP_MASK_RZ
);
1694 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1695 mips_gprmask
|= 1 << TREG
;
1696 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1697 mips_gprmask
|= 1 << SP
;
1698 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1699 mips_gprmask
|= 1 << RA
;
1700 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1701 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1702 if (pinfo
& MIPS16_INSN_READ_Z
)
1703 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1704 & MIPS16OP_MASK_MOVE32Z
);
1705 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1706 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1707 & MIPS16OP_MASK_REGR32
);
1710 if (place
== NULL
&& ! mips_noreorder
)
1712 /* Filling the branch delay slot is more complex. We try to
1713 switch the branch with the previous instruction, which we can
1714 do if the previous instruction does not set up a condition
1715 that the branch tests and if the branch is not itself the
1716 target of any branch. */
1717 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1718 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1720 if (mips_optimize
< 2
1721 /* If we have seen .set volatile or .set nomove, don't
1724 /* If we had to emit any NOP instructions, then we
1725 already know we can not swap. */
1727 /* If we don't even know the previous insn, we can not
1729 || ! prev_insn_valid
1730 /* If the previous insn is already in a branch delay
1731 slot, then we can not swap. */
1732 || prev_insn_is_delay_slot
1733 /* If the previous previous insn was in a .set
1734 noreorder, we can't swap. Actually, the MIPS
1735 assembler will swap in this situation. However, gcc
1736 configured -with-gnu-as will generate code like
1742 in which we can not swap the bne and INSN. If gcc is
1743 not configured -with-gnu-as, it does not output the
1744 .set pseudo-ops. We don't have to check
1745 prev_insn_unreordered, because prev_insn_valid will
1746 be 0 in that case. We don't want to use
1747 prev_prev_insn_valid, because we do want to be able
1748 to swap at the start of a function. */
1749 || prev_prev_insn_unreordered
1750 /* If the branch is itself the target of a branch, we
1751 can not swap. We cheat on this; all we check for is
1752 whether there is a label on this instruction. If
1753 there are any branches to anything other than a
1754 label, users must use .set noreorder. */
1755 || insn_labels
!= NULL
1756 /* If the previous instruction is in a variant frag, we
1757 can not do the swap. This does not apply to the
1758 mips16, which uses variant frags for different
1761 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1762 /* If the branch reads the condition codes, we don't
1763 even try to swap, because in the sequence
1768 we can not swap, and I don't feel like handling that
1772 && (pinfo
& INSN_READ_COND_CODE
))
1773 /* We can not swap with an instruction that requires a
1774 delay slot, becase the target of the branch might
1775 interfere with that instruction. */
1779 & (INSN_LOAD_COPROC_DELAY
1780 | INSN_COPROC_MOVE_DELAY
1781 | INSN_WRITE_COND_CODE
)))
1789 & (INSN_LOAD_MEMORY_DELAY
1790 | INSN_COPROC_MEMORY_DELAY
)))
1791 /* We can not swap with a branch instruction. */
1793 & (INSN_UNCOND_BRANCH_DELAY
1794 | INSN_COND_BRANCH_DELAY
1795 | INSN_COND_BRANCH_LIKELY
))
1796 /* We do not swap with a trap instruction, since it
1797 complicates trap handlers to have the trap
1798 instruction be in a delay slot. */
1799 || (prev_pinfo
& INSN_TRAP
)
1800 /* If the branch reads a register that the previous
1801 instruction sets, we can not swap. */
1803 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1804 && insn_uses_reg (ip
,
1805 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1809 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1810 && insn_uses_reg (ip
,
1811 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1815 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1816 && insn_uses_reg (ip
,
1817 ((prev_insn
.insn_opcode
1819 & MIPS16OP_MASK_RX
),
1821 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1822 && insn_uses_reg (ip
,
1823 ((prev_insn
.insn_opcode
1825 & MIPS16OP_MASK_RY
),
1827 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1828 && insn_uses_reg (ip
,
1829 ((prev_insn
.insn_opcode
1831 & MIPS16OP_MASK_RZ
),
1833 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1834 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1835 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1836 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1837 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1838 && insn_uses_reg (ip
,
1839 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1842 /* If the branch writes a register that the previous
1843 instruction sets, we can not swap (we know that
1844 branches write only to RD or to $31). */
1846 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1847 && (((pinfo
& INSN_WRITE_GPR_D
)
1848 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1849 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1850 || ((pinfo
& INSN_WRITE_GPR_31
)
1851 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1855 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1856 && (((pinfo
& INSN_WRITE_GPR_D
)
1857 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1858 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1859 || ((pinfo
& INSN_WRITE_GPR_31
)
1860 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1864 && (pinfo
& MIPS16_INSN_WRITE_31
)
1865 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1866 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1867 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1869 /* If the branch writes a register that the previous
1870 instruction reads, we can not swap (we know that
1871 branches only write to RD or to $31). */
1873 && (pinfo
& INSN_WRITE_GPR_D
)
1874 && insn_uses_reg (&prev_insn
,
1875 ((ip
->insn_opcode
>> OP_SH_RD
)
1879 && (pinfo
& INSN_WRITE_GPR_31
)
1880 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1882 && (pinfo
& MIPS16_INSN_WRITE_31
)
1883 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1884 /* If we are generating embedded PIC code, the branch
1885 might be expanded into a sequence which uses $at, so
1886 we can't swap with an instruction which reads it. */
1887 || (mips_pic
== EMBEDDED_PIC
1888 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1889 /* If the previous previous instruction has a load
1890 delay, and sets a register that the branch reads, we
1894 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1896 && (prev_prev_insn
.insn_mo
->pinfo
1897 & INSN_LOAD_MEMORY_DELAY
)))
1898 && insn_uses_reg (ip
,
1899 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1902 /* If one instruction sets a condition code and the
1903 other one uses a condition code, we can not swap. */
1904 || ((pinfo
& INSN_READ_COND_CODE
)
1905 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1906 || ((pinfo
& INSN_WRITE_COND_CODE
)
1907 && (prev_pinfo
& INSN_READ_COND_CODE
))
1908 /* If the previous instruction uses the PC, we can not
1911 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1912 /* If the previous instruction was extended, we can not
1914 || (mips16
&& prev_insn_extended
)
1915 /* If the previous instruction had a fixup in mips16
1916 mode, we can not swap. This normally means that the
1917 previous instruction was a 4 byte branch anyhow. */
1918 || (mips16
&& prev_insn_fixp
))
1920 /* We could do even better for unconditional branches to
1921 portions of this object file; we could pick up the
1922 instruction at the destination, put it in the delay
1923 slot, and bump the destination address. */
1925 /* Update the previous insn information. */
1926 prev_prev_insn
= *ip
;
1927 prev_insn
.insn_mo
= &dummy_opcode
;
1931 /* It looks like we can actually do the swap. */
1937 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1938 memcpy (temp
, prev_f
, 4);
1939 memcpy (prev_f
, f
, 4);
1940 memcpy (f
, temp
, 4);
1943 prev_insn_fixp
->fx_frag
= frag_now
;
1944 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1948 fixp
->fx_frag
= prev_insn_frag
;
1949 fixp
->fx_where
= prev_insn_where
;
1957 assert (prev_insn_fixp
== NULL
);
1958 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1959 memcpy (temp
, prev_f
, 2);
1960 memcpy (prev_f
, f
, 2);
1961 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1963 assert (reloc_type
== BFD_RELOC_UNUSED
);
1964 memcpy (f
, temp
, 2);
1968 memcpy (f
, f
+ 2, 2);
1969 memcpy (f
+ 2, temp
, 2);
1973 fixp
->fx_frag
= prev_insn_frag
;
1974 fixp
->fx_where
= prev_insn_where
;
1978 /* Update the previous insn information; leave prev_insn
1980 prev_prev_insn
= *ip
;
1982 prev_insn_is_delay_slot
= 1;
1984 /* If that was an unconditional branch, forget the previous
1985 insn information. */
1986 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1988 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1989 prev_insn
.insn_mo
= &dummy_opcode
;
1992 prev_insn_fixp
= NULL
;
1993 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1994 prev_insn_extended
= 0;
1996 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1998 /* We don't yet optimize a branch likely. What we should do
1999 is look at the target, copy the instruction found there
2000 into the delay slot, and increment the branch to jump to
2001 the next instruction. */
2003 /* Update the previous insn information. */
2004 prev_prev_insn
= *ip
;
2005 prev_insn
.insn_mo
= &dummy_opcode
;
2006 prev_insn_fixp
= NULL
;
2007 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2008 prev_insn_extended
= 0;
2012 /* Update the previous insn information. */
2014 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2016 prev_prev_insn
= prev_insn
;
2019 /* Any time we see a branch, we always fill the delay slot
2020 immediately; since this insn is not a branch, we know it
2021 is not in a delay slot. */
2022 prev_insn_is_delay_slot
= 0;
2024 prev_insn_fixp
= fixp
;
2025 prev_insn_reloc_type
= reloc_type
;
2027 prev_insn_extended
= (ip
->use_extend
2028 || reloc_type
> BFD_RELOC_UNUSED
);
2031 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2032 prev_insn_unreordered
= 0;
2033 prev_insn_frag
= frag_now
;
2034 prev_insn_where
= f
- frag_now
->fr_literal
;
2035 prev_insn_valid
= 1;
2037 else if (place
== NULL
)
2039 /* We need to record a bit of information even when we are not
2040 reordering, in order to determine the base address for mips16
2041 PC relative relocs. */
2042 prev_prev_insn
= prev_insn
;
2044 prev_insn_reloc_type
= reloc_type
;
2045 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2046 prev_insn_unreordered
= 1;
2049 /* We just output an insn, so the next one doesn't have a label. */
2050 mips_clear_insn_labels ();
2053 /* This function forgets that there was any previous instruction or
2054 label. If PRESERVE is non-zero, it remembers enough information to
2055 know whether nops are needed before a noreorder section. */
2058 mips_no_prev_insn (preserve
)
2063 prev_insn
.insn_mo
= &dummy_opcode
;
2064 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2065 prev_nop_frag
= NULL
;
2066 prev_nop_frag_holds
= 0;
2067 prev_nop_frag_required
= 0;
2068 prev_nop_frag_since
= 0;
2070 prev_insn_valid
= 0;
2071 prev_insn_is_delay_slot
= 0;
2072 prev_insn_unreordered
= 0;
2073 prev_insn_extended
= 0;
2074 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2075 prev_prev_insn_unreordered
= 0;
2076 mips_clear_insn_labels ();
2079 /* This function must be called whenever we turn on noreorder or emit
2080 something other than instructions. It inserts any NOPS which might
2081 be needed by the previous instruction, and clears the information
2082 kept for the previous instructions. The INSNS parameter is true if
2083 instructions are to follow. */
2086 mips_emit_delays (insns
)
2089 if (! mips_noreorder
)
2096 && (! cop_interlocks
2097 && (prev_insn
.insn_mo
->pinfo
2098 & (INSN_LOAD_COPROC_DELAY
2099 | INSN_COPROC_MOVE_DELAY
2100 | INSN_WRITE_COND_CODE
))))
2102 && (prev_insn
.insn_mo
->pinfo
2107 && (prev_insn
.insn_mo
->pinfo
2108 & (INSN_LOAD_MEMORY_DELAY
2109 | INSN_COPROC_MEMORY_DELAY
))))
2114 && (! cop_interlocks
2115 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2117 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2118 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2121 if (prev_insn_unreordered
)
2126 && (! cop_interlocks
2127 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2129 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2130 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2132 if (! prev_prev_insn_unreordered
)
2138 struct insn_label_list
*l
;
2142 /* Record the frag which holds the nop instructions, so
2143 that we can remove them if we don't need them. */
2144 frag_grow (mips16
? nops
* 2 : nops
* 4);
2145 prev_nop_frag
= frag_now
;
2146 prev_nop_frag_holds
= nops
;
2147 prev_nop_frag_required
= 0;
2148 prev_nop_frag_since
= 0;
2151 for (; nops
> 0; --nops
)
2156 /* Move on to a new frag, so that it is safe to simply
2157 decrease the size of prev_nop_frag. */
2158 frag_wane (frag_now
);
2162 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2164 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2165 l
->label
->sy_frag
= frag_now
;
2166 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2167 /* mips16 text labels are stored as odd. */
2169 ++l
->label
->sy_value
.X_add_number
;
2174 /* Mark instruction labels in mips16 mode. This permits the linker
2175 to handle them specially, such as generating jalx instructions
2176 when needed. We also make them odd for the duration of the
2177 assembly, in order to generate the right sort of code. We will
2178 make them even in the adjust_symtab routine, while leaving them
2179 marked. This is convenient for the debugger and the
2180 disassembler. The linker knows to make them odd again. */
2181 if (mips16
&& insns
)
2183 struct insn_label_list
*l
;
2185 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2188 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2189 S_SET_OTHER (l
->label
, STO_MIPS16
);
2191 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2192 ++l
->label
->sy_value
.X_add_number
;
2196 mips_no_prev_insn (insns
);
2199 /* Build an instruction created by a macro expansion. This is passed
2200 a pointer to the count of instructions created so far, an
2201 expression, the name of the instruction to build, an operand format
2202 string, and corresponding arguments. */
2206 macro_build (char *place
,
2214 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2223 struct mips_cl_insn insn
;
2224 bfd_reloc_code_real_type r
;
2228 va_start (args
, fmt
);
2234 * If the macro is about to expand into a second instruction,
2235 * print a warning if needed. We need to pass ip as a parameter
2236 * to generate a better warning message here...
2238 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2239 as_warn ("Macro instruction expanded into multiple instructions");
2242 *counter
+= 1; /* bump instruction counter */
2246 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2251 r
= BFD_RELOC_UNUSED
;
2252 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2253 assert (insn
.insn_mo
);
2254 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2256 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2257 || insn
.insn_mo
->pinfo
== INSN_MACRO
2258 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2260 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2262 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2264 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2266 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2268 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2270 /* start-sanitize-r5900 */
2271 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2273 /* end-sanitize-r5900 */
2277 assert (insn
.insn_mo
->name
);
2278 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2280 insn
.insn_opcode
= insn
.insn_mo
->match
;
2296 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2302 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2307 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2312 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2319 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2323 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2327 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2334 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2340 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2341 assert (r
== BFD_RELOC_MIPS_GPREL
2342 || r
== BFD_RELOC_MIPS_LITERAL
2343 || r
== BFD_RELOC_LO16
2344 || r
== BFD_RELOC_MIPS_GOT16
2345 || r
== BFD_RELOC_MIPS_CALL16
2346 || r
== BFD_RELOC_MIPS_GOT_LO16
2347 || r
== BFD_RELOC_MIPS_CALL_LO16
2348 || (ep
->X_op
== O_subtract
2349 && now_seg
== text_section
2350 && r
== BFD_RELOC_PCREL_LO16
));
2354 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2356 && (ep
->X_op
== O_constant
2357 || (ep
->X_op
== O_symbol
2358 && (r
== BFD_RELOC_HI16_S
2359 || r
== BFD_RELOC_HI16
2360 || r
== BFD_RELOC_MIPS_GOT_HI16
2361 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2362 || (ep
->X_op
== O_subtract
2363 && now_seg
== text_section
2364 && r
== BFD_RELOC_PCREL_HI16_S
)));
2365 if (ep
->X_op
== O_constant
)
2367 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2369 r
= BFD_RELOC_UNUSED
;
2374 assert (ep
!= NULL
);
2376 * This allows macro() to pass an immediate expression for
2377 * creating short branches without creating a symbol.
2378 * Note that the expression still might come from the assembly
2379 * input, in which case the value is not checked for range nor
2380 * is a relocation entry generated (yuck).
2382 if (ep
->X_op
== O_constant
)
2384 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2388 r
= BFD_RELOC_16_PCREL_S2
;
2392 assert (ep
!= NULL
);
2393 r
= BFD_RELOC_MIPS_JMP
;
2402 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2404 append_insn (place
, &insn
, ep
, r
, false);
2408 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2416 struct mips_cl_insn insn
;
2417 bfd_reloc_code_real_type r
;
2419 r
= BFD_RELOC_UNUSED
;
2420 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2421 assert (insn
.insn_mo
);
2422 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2424 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2425 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2428 assert (insn
.insn_mo
->name
);
2429 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2432 insn
.insn_opcode
= insn
.insn_mo
->match
;
2433 insn
.use_extend
= false;
2452 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2457 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2461 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2465 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2475 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2482 regno
= va_arg (args
, int);
2483 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2484 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2505 assert (ep
!= NULL
);
2507 if (ep
->X_op
!= O_constant
)
2508 r
= BFD_RELOC_UNUSED
+ c
;
2511 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2512 false, false, &insn
.insn_opcode
,
2513 &insn
.use_extend
, &insn
.extend
);
2515 r
= BFD_RELOC_UNUSED
;
2521 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2528 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2530 append_insn (place
, &insn
, ep
, r
, false);
2534 * Generate a "lui" instruction.
2537 macro_build_lui (place
, counter
, ep
, regnum
)
2543 expressionS high_expr
;
2544 struct mips_cl_insn insn
;
2545 bfd_reloc_code_real_type r
;
2546 CONST
char *name
= "lui";
2547 CONST
char *fmt
= "t,u";
2555 high_expr
.X_op
= O_constant
;
2556 high_expr
.X_add_number
= ep
->X_add_number
;
2559 if (high_expr
.X_op
== O_constant
)
2561 /* we can compute the instruction now without a relocation entry */
2562 if (high_expr
.X_add_number
& 0x8000)
2563 high_expr
.X_add_number
+= 0x10000;
2564 high_expr
.X_add_number
=
2565 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2566 r
= BFD_RELOC_UNUSED
;
2570 assert (ep
->X_op
== O_symbol
);
2571 /* _gp_disp is a special case, used from s_cpload. */
2572 assert (mips_pic
== NO_PIC
2573 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2574 r
= BFD_RELOC_HI16_S
;
2578 * If the macro is about to expand into a second instruction,
2579 * print a warning if needed. We need to pass ip as a parameter
2580 * to generate a better warning message here...
2582 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2583 as_warn ("Macro instruction expanded into multiple instructions");
2586 *counter
+= 1; /* bump instruction counter */
2588 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2589 assert (insn
.insn_mo
);
2590 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2591 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2593 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2594 if (r
== BFD_RELOC_UNUSED
)
2596 insn
.insn_opcode
|= high_expr
.X_add_number
;
2597 append_insn (place
, &insn
, NULL
, r
, false);
2600 append_insn (place
, &insn
, &high_expr
, r
, false);
2604 * Generates code to set the $at register to true (one)
2605 * if reg is less than the immediate expression.
2608 set_at (counter
, reg
, unsignedp
)
2613 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2614 macro_build ((char *) NULL
, counter
, &imm_expr
,
2615 unsignedp
? "sltiu" : "slti",
2616 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2619 load_register (counter
, AT
, &imm_expr
, 0);
2620 macro_build ((char *) NULL
, counter
, NULL
,
2621 unsignedp
? "sltu" : "slt",
2622 "d,v,t", AT
, reg
, AT
);
2626 /* Warn if an expression is not a constant. */
2629 check_absolute_expr (ip
, ex
)
2630 struct mips_cl_insn
*ip
;
2633 if (ex
->X_op
!= O_constant
)
2634 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2637 /* Count the leading zeroes by performing a binary chop. This is a
2638 bulky bit of source, but performance is a LOT better for the
2639 majority of values than a simple loop to count the bits:
2640 for (lcnt = 0; (lcnt < 32); lcnt++)
2641 if ((v) & (1 << (31 - lcnt)))
2643 However it is not code size friendly, and the gain will drop a bit
2644 on certain cached systems.
2646 #define COUNT_TOP_ZEROES(v) \
2647 (((v) & ~0xffff) == 0 \
2648 ? ((v) & ~0xff) == 0 \
2649 ? ((v) & ~0xf) == 0 \
2650 ? ((v) & ~0x3) == 0 \
2651 ? ((v) & ~0x1) == 0 \
2656 : ((v) & ~0x7) == 0 \
2659 : ((v) & ~0x3f) == 0 \
2660 ? ((v) & ~0x1f) == 0 \
2663 : ((v) & ~0x7f) == 0 \
2666 : ((v) & ~0xfff) == 0 \
2667 ? ((v) & ~0x3ff) == 0 \
2668 ? ((v) & ~0x1ff) == 0 \
2671 : ((v) & ~0x7ff) == 0 \
2674 : ((v) & ~0x3fff) == 0 \
2675 ? ((v) & ~0x1fff) == 0 \
2678 : ((v) & ~0x7fff) == 0 \
2681 : ((v) & ~0xffffff) == 0 \
2682 ? ((v) & ~0xfffff) == 0 \
2683 ? ((v) & ~0x3ffff) == 0 \
2684 ? ((v) & ~0x1ffff) == 0 \
2687 : ((v) & ~0x7ffff) == 0 \
2690 : ((v) & ~0x3fffff) == 0 \
2691 ? ((v) & ~0x1fffff) == 0 \
2694 : ((v) & ~0x7fffff) == 0 \
2697 : ((v) & ~0xfffffff) == 0 \
2698 ? ((v) & ~0x3ffffff) == 0 \
2699 ? ((v) & ~0x1ffffff) == 0 \
2702 : ((v) & ~0x7ffffff) == 0 \
2705 : ((v) & ~0x3fffffff) == 0 \
2706 ? ((v) & ~0x1fffffff) == 0 \
2709 : ((v) & ~0x7fffffff) == 0 \
2714 * This routine generates the least number of instructions neccessary to load
2715 * an absolute expression value into a register.
2718 load_register (counter
, reg
, ep
, dbl
)
2725 expressionS hi32
, lo32
;
2727 if (ep
->X_op
!= O_big
)
2729 assert (ep
->X_op
== O_constant
);
2730 if (ep
->X_add_number
< 0x8000
2731 && (ep
->X_add_number
>= 0
2732 || (ep
->X_add_number
>= -0x8000
2735 || sizeof (ep
->X_add_number
) > 4))))
2737 /* We can handle 16 bit signed values with an addiu to
2738 $zero. No need to ever use daddiu here, since $zero and
2739 the result are always correct in 32 bit mode. */
2740 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2741 (int) BFD_RELOC_LO16
);
2744 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2746 /* We can handle 16 bit unsigned values with an ori to
2748 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2749 (int) BFD_RELOC_LO16
);
2752 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2753 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2754 == ~ (offsetT
) 0x7fffffff))
2757 || sizeof (ep
->X_add_number
) > 4
2758 || (ep
->X_add_number
& 0x80000000) == 0))
2759 || ((mips_isa
< 3 || !dbl
)
2760 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2762 /* 32 bit values require an lui. */
2763 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2764 (int) BFD_RELOC_HI16
);
2765 if ((ep
->X_add_number
& 0xffff) != 0)
2766 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2767 (int) BFD_RELOC_LO16
);
2772 /* The value is larger than 32 bits. */
2776 as_bad ("Number larger than 32 bits");
2777 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2778 (int) BFD_RELOC_LO16
);
2782 if (ep
->X_op
!= O_big
)
2785 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2786 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2787 hi32
.X_add_number
&= 0xffffffff;
2789 lo32
.X_add_number
&= 0xffffffff;
2793 assert (ep
->X_add_number
> 2);
2794 if (ep
->X_add_number
== 3)
2795 generic_bignum
[3] = 0;
2796 else if (ep
->X_add_number
> 4)
2797 as_bad ("Number larger than 64 bits");
2798 lo32
.X_op
= O_constant
;
2799 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2800 hi32
.X_op
= O_constant
;
2801 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2804 if (hi32
.X_add_number
== 0)
2809 unsigned long hi
, lo
;
2811 if (hi32
.X_add_number
== 0xffffffff)
2813 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2815 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2816 reg
, 0, (int) BFD_RELOC_LO16
);
2819 if (lo32
.X_add_number
& 0x80000000)
2821 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2822 (int) BFD_RELOC_HI16
);
2823 if (lo32
.X_add_number
& 0xffff)
2824 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2825 reg
, reg
, (int) BFD_RELOC_LO16
);
2830 /* Check for 16bit shifted constant. We know that hi32 is
2831 non-zero, so start the mask on the first bit of the hi32
2836 unsigned long himask
, lomask
;
2840 himask
= 0xffff >> (32 - shift
);
2841 lomask
= (0xffff << shift
) & 0xffffffff;
2845 himask
= 0xffff << (shift
- 32);
2848 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2849 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2853 tmp
.X_op
= O_constant
;
2855 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2856 | (lo32
.X_add_number
>> shift
));
2858 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2859 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2860 (int) BFD_RELOC_LO16
);
2861 macro_build ((char *) NULL
, counter
, NULL
,
2862 (shift
>= 32) ? "dsll32" : "dsll",
2864 (shift
>= 32) ? shift
- 32 : shift
);
2868 } while (shift
<= (64 - 16));
2870 /* Find the bit number of the lowest one bit, and store the
2871 shifted value in hi/lo. */
2872 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2873 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2877 while ((lo
& 1) == 0)
2882 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2888 while ((hi
& 1) == 0)
2897 /* Optimize if the shifted value is a (power of 2) - 1. */
2898 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2899 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2901 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2906 /* This instruction will set the register to be all
2908 tmp
.X_op
= O_constant
;
2909 tmp
.X_add_number
= (offsetT
) -1;
2910 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2911 reg
, 0, (int) BFD_RELOC_LO16
);
2915 macro_build ((char *) NULL
, counter
, NULL
,
2916 (bit
>= 32) ? "dsll32" : "dsll",
2918 (bit
>= 32) ? bit
- 32 : bit
);
2920 macro_build ((char *) NULL
, counter
, NULL
,
2921 (shift
>= 32) ? "dsrl32" : "dsrl",
2923 (shift
>= 32) ? shift
- 32 : shift
);
2928 /* Sign extend hi32 before calling load_register, because we can
2929 generally get better code when we load a sign extended value. */
2930 if ((hi32
.X_add_number
& 0x80000000) != 0)
2931 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2932 load_register (counter
, reg
, &hi32
, 0);
2935 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2939 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2948 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2950 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2951 (int) BFD_RELOC_HI16
);
2952 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2959 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2964 mid16
.X_add_number
>>= 16;
2965 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2966 freg
, (int) BFD_RELOC_LO16
);
2967 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2971 if ((lo32
.X_add_number
& 0xffff) != 0)
2972 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2973 (int) BFD_RELOC_LO16
);
2976 /* Load an address into a register. */
2979 load_address (counter
, reg
, ep
)
2986 if (ep
->X_op
!= O_constant
2987 && ep
->X_op
!= O_symbol
)
2989 as_bad ("expression too complex");
2990 ep
->X_op
= O_constant
;
2993 if (ep
->X_op
== O_constant
)
2995 load_register (counter
, reg
, ep
, 0);
2999 if (mips_pic
== NO_PIC
)
3001 /* If this is a reference to a GP relative symbol, we want
3002 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3004 lui $reg,<sym> (BFD_RELOC_HI16_S)
3005 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3006 If we have an addend, we always use the latter form. */
3007 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3008 || nopic_need_relax (ep
->X_add_symbol
))
3013 macro_build ((char *) NULL
, counter
, ep
,
3014 mips_isa
< 3 ? "addiu" : "daddiu",
3015 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3016 p
= frag_var (rs_machine_dependent
, 8, 0,
3017 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
3018 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3020 macro_build_lui (p
, counter
, ep
, reg
);
3023 macro_build (p
, counter
, ep
,
3024 mips_isa
< 3 ? "addiu" : "daddiu",
3025 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3027 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3031 /* If this is a reference to an external symbol, we want
3032 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3034 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3036 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3037 If there is a constant, it must be added in after. */
3038 ex
.X_add_number
= ep
->X_add_number
;
3039 ep
->X_add_number
= 0;
3041 macro_build ((char *) NULL
, counter
, ep
,
3042 mips_isa
< 3 ? "lw" : "ld",
3043 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3044 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3045 p
= frag_var (rs_machine_dependent
, 4, 0,
3046 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
3047 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3048 macro_build (p
, counter
, ep
,
3049 mips_isa
< 3 ? "addiu" : "daddiu",
3050 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3051 if (ex
.X_add_number
!= 0)
3053 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3054 as_bad ("PIC code offset overflow (max 16 signed bits)");
3055 ex
.X_op
= O_constant
;
3056 macro_build ((char *) NULL
, counter
, &ex
,
3057 mips_isa
< 3 ? "addiu" : "daddiu",
3058 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3061 else if (mips_pic
== SVR4_PIC
)
3066 /* This is the large GOT case. If this is a reference to an
3067 external symbol, we want
3068 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3070 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3071 Otherwise, for a reference to a local symbol, we want
3072 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3074 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3075 If there is a constant, it must be added in after. */
3076 ex
.X_add_number
= ep
->X_add_number
;
3077 ep
->X_add_number
= 0;
3078 if (reg_needs_delay (GP
))
3083 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3084 (int) BFD_RELOC_MIPS_GOT_HI16
);
3085 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3086 mips_isa
< 3 ? "addu" : "daddu",
3087 "d,v,t", reg
, reg
, GP
);
3088 macro_build ((char *) NULL
, counter
, ep
,
3089 mips_isa
< 3 ? "lw" : "ld",
3090 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3091 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3092 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3093 mips_warn_about_macros
),
3094 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
3097 /* We need a nop before loading from $gp. This special
3098 check is required because the lui which starts the main
3099 instruction stream does not refer to $gp, and so will not
3100 insert the nop which may be required. */
3101 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3104 macro_build (p
, counter
, ep
,
3105 mips_isa
< 3 ? "lw" : "ld",
3106 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3108 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3110 macro_build (p
, counter
, ep
,
3111 mips_isa
< 3 ? "addiu" : "daddiu",
3112 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3113 if (ex
.X_add_number
!= 0)
3115 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3116 as_bad ("PIC code offset overflow (max 16 signed bits)");
3117 ex
.X_op
= O_constant
;
3118 macro_build ((char *) NULL
, counter
, &ex
,
3119 mips_isa
< 3 ? "addiu" : "daddiu",
3120 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3123 else if (mips_pic
== EMBEDDED_PIC
)
3126 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3128 macro_build ((char *) NULL
, counter
, ep
,
3129 mips_isa
< 3 ? "addiu" : "daddiu",
3130 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3138 * This routine implements the seemingly endless macro or synthesized
3139 * instructions and addressing modes in the mips assembly language. Many
3140 * of these macros are simple and are similar to each other. These could
3141 * probably be handled by some kind of table or grammer aproach instead of
3142 * this verbose method. Others are not simple macros but are more like
3143 * optimizing code generation.
3144 * One interesting optimization is when several store macros appear
3145 * consecutivly that would load AT with the upper half of the same address.
3146 * The ensuing load upper instructions are ommited. This implies some kind
3147 * of global optimization. We currently only optimize within a single macro.
3148 * For many of the load and store macros if the address is specified as a
3149 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3150 * first load register 'at' with zero and use it as the base register. The
3151 * mips assembler simply uses register $zero. Just one tiny optimization
3156 struct mips_cl_insn
*ip
;
3158 register int treg
, sreg
, dreg
, breg
;
3173 bfd_reloc_code_real_type r
;
3175 int hold_mips_optimize
;
3179 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3180 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3181 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3182 mask
= ip
->insn_mo
->mask
;
3184 expr1
.X_op
= O_constant
;
3185 expr1
.X_op_symbol
= NULL
;
3186 expr1
.X_add_symbol
= NULL
;
3187 expr1
.X_add_number
= 1;
3199 mips_emit_delays (true);
3201 mips_any_noreorder
= 1;
3203 expr1
.X_add_number
= 8;
3204 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3206 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3208 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3209 macro_build ((char *) NULL
, &icnt
, NULL
,
3210 dbl
? "dsub" : "sub",
3211 "d,v,t", dreg
, 0, sreg
);
3234 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3236 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3237 (int) BFD_RELOC_LO16
);
3240 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3241 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3260 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3262 if (mask
!= M_NOR_I
)
3263 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3264 sreg
, (int) BFD_RELOC_LO16
);
3267 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3268 treg
, sreg
, (int) BFD_RELOC_LO16
);
3269 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3275 load_register (&icnt
, AT
, &imm_expr
, 0);
3276 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3293 if (imm_expr
.X_add_number
== 0)
3295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3299 load_register (&icnt
, AT
, &imm_expr
, 0);
3300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3308 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3309 likely
? "bgezl" : "bgez",
3315 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3316 likely
? "blezl" : "blez",
3320 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3321 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3322 likely
? "beql" : "beq",
3329 /* check for > max integer */
3330 maxnum
= 0x7fffffff;
3338 if (imm_expr
.X_add_number
>= maxnum
3339 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3342 /* result is always false */
3345 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3346 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3350 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3351 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3356 imm_expr
.X_add_number
++;
3360 if (mask
== M_BGEL_I
)
3362 if (imm_expr
.X_add_number
== 0)
3364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3365 likely
? "bgezl" : "bgez",
3369 if (imm_expr
.X_add_number
== 1)
3371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3372 likely
? "bgtzl" : "bgtz",
3376 maxnum
= 0x7fffffff;
3384 maxnum
= - maxnum
- 1;
3385 if (imm_expr
.X_add_number
<= maxnum
3386 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3389 /* result is always true */
3390 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3391 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3394 set_at (&icnt
, sreg
, 0);
3395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3396 likely
? "beql" : "beq",
3407 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3408 likely
? "beql" : "beq",
3412 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3414 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3415 likely
? "beql" : "beq",
3422 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3424 imm_expr
.X_add_number
++;
3428 if (mask
== M_BGEUL_I
)
3430 if (imm_expr
.X_add_number
== 0)
3432 if (imm_expr
.X_add_number
== 1)
3434 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3435 likely
? "bnel" : "bne",
3439 set_at (&icnt
, sreg
, 1);
3440 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3441 likely
? "beql" : "beq",
3450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3451 likely
? "bgtzl" : "bgtz",
3457 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3458 likely
? "bltzl" : "bltz",
3462 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3463 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3464 likely
? "bnel" : "bne",
3473 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3474 likely
? "bnel" : "bne",
3480 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3482 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3483 likely
? "bnel" : "bne",
3492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3493 likely
? "blezl" : "blez",
3499 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3500 likely
? "bgezl" : "bgez",
3504 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3506 likely
? "beql" : "beq",
3513 maxnum
= 0x7fffffff;
3521 if (imm_expr
.X_add_number
>= maxnum
3522 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3524 imm_expr
.X_add_number
++;
3528 if (mask
== M_BLTL_I
)
3530 if (imm_expr
.X_add_number
== 0)
3532 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3533 likely
? "bltzl" : "bltz",
3537 if (imm_expr
.X_add_number
== 1)
3539 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3540 likely
? "blezl" : "blez",
3544 set_at (&icnt
, sreg
, 0);
3545 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3546 likely
? "bnel" : "bne",
3555 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3556 likely
? "beql" : "beq",
3562 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3564 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3565 likely
? "beql" : "beq",
3572 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3574 imm_expr
.X_add_number
++;
3578 if (mask
== M_BLTUL_I
)
3580 if (imm_expr
.X_add_number
== 0)
3582 if (imm_expr
.X_add_number
== 1)
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3585 likely
? "beql" : "beq",
3589 set_at (&icnt
, sreg
, 1);
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3591 likely
? "bnel" : "bne",
3600 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3601 likely
? "bltzl" : "bltz",
3607 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3608 likely
? "bgtzl" : "bgtz",
3612 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3613 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3614 likely
? "bnel" : "bne",
3625 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3626 likely
? "bnel" : "bne",
3630 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3632 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3633 likely
? "bnel" : "bne",
3649 as_warn ("Divide by zero.");
3651 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3653 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3657 mips_emit_delays (true);
3659 mips_any_noreorder
= 1;
3660 macro_build ((char *) NULL
, &icnt
, NULL
,
3661 dbl
? "ddiv" : "div",
3662 "z,s,t", sreg
, treg
);
3664 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3667 expr1
.X_add_number
= 8;
3668 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3670 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3672 expr1
.X_add_number
= -1;
3673 macro_build ((char *) NULL
, &icnt
, &expr1
,
3674 dbl
? "daddiu" : "addiu",
3675 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3676 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3677 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3680 expr1
.X_add_number
= 1;
3681 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3682 (int) BFD_RELOC_LO16
);
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3688 expr1
.X_add_number
= 0x80000000;
3689 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3690 (int) BFD_RELOC_HI16
);
3693 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3696 expr1
.X_add_number
= 8;
3697 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3698 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3702 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3741 if (imm_expr
.X_add_number
== 0)
3743 as_warn ("Divide by zero.");
3745 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3747 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3750 if (imm_expr
.X_add_number
== 1)
3752 if (strcmp (s2
, "mflo") == 0)
3753 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3756 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3759 if (imm_expr
.X_add_number
== -1
3760 && s
[strlen (s
) - 1] != 'u')
3762 if (strcmp (s2
, "mflo") == 0)
3765 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3768 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3772 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3776 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3777 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3778 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3797 mips_emit_delays (true);
3799 mips_any_noreorder
= 1;
3800 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3802 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3805 expr1
.X_add_number
= 8;
3806 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3807 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3808 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3811 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3817 /* Load the address of a symbol into a register. If breg is not
3818 zero, we then add a base register to it. */
3820 /* When generating embedded PIC code, we permit expressions of
3823 where bar is an address in the .text section. These are used
3824 when getting the addresses of functions. We don't permit
3825 X_add_number to be non-zero, because if the symbol is
3826 external the relaxing code needs to know that any addend is
3827 purely the offset to X_op_symbol. */
3828 if (mips_pic
== EMBEDDED_PIC
3829 && offset_expr
.X_op
== O_subtract
3830 && now_seg
== text_section
3831 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3832 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3833 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3834 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3835 ->sy_value
.X_add_symbol
)
3838 && offset_expr
.X_add_number
== 0)
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3841 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3842 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3843 mips_isa
< 3 ? "addiu" : "daddiu",
3844 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3848 if (offset_expr
.X_op
!= O_symbol
3849 && offset_expr
.X_op
!= O_constant
)
3851 as_bad ("expression too complex");
3852 offset_expr
.X_op
= O_constant
;
3866 if (offset_expr
.X_op
== O_constant
)
3867 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3868 else if (mips_pic
== NO_PIC
)
3870 /* If this is a reference to an GP relative symbol, we want
3871 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3873 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3874 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3875 If we have a constant, we need two instructions anyhow,
3876 so we may as well always use the latter form. */
3877 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3878 || nopic_need_relax (offset_expr
.X_add_symbol
))
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3884 mips_isa
< 3 ? "addiu" : "daddiu",
3885 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3886 p
= frag_var (rs_machine_dependent
, 8, 0,
3887 RELAX_ENCODE (4, 8, 0, 4, 0,
3888 mips_warn_about_macros
),
3889 offset_expr
.X_add_symbol
, (long) 0,
3892 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3895 macro_build (p
, &icnt
, &offset_expr
,
3896 mips_isa
< 3 ? "addiu" : "daddiu",
3897 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3899 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3901 /* If this is a reference to an external symbol, and there
3902 is no constant, we want
3903 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3904 For a local symbol, we want
3905 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3907 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3909 If we have a small constant, and this is a reference to
3910 an external symbol, we want
3911 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3913 addiu $tempreg,$tempreg,<constant>
3914 For a local symbol, we want the same instruction
3915 sequence, but we output a BFD_RELOC_LO16 reloc on the
3918 If we have a large constant, and this is a reference to
3919 an external symbol, we want
3920 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3921 lui $at,<hiconstant>
3922 addiu $at,$at,<loconstant>
3923 addu $tempreg,$tempreg,$at
3924 For a local symbol, we want the same instruction
3925 sequence, but we output a BFD_RELOC_LO16 reloc on the
3926 addiu instruction. */
3927 expr1
.X_add_number
= offset_expr
.X_add_number
;
3928 offset_expr
.X_add_number
= 0;
3930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3932 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3933 if (expr1
.X_add_number
== 0)
3941 /* We're going to put in an addu instruction using
3942 tempreg, so we may as well insert the nop right
3944 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3948 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3949 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3951 ? mips_warn_about_macros
3953 offset_expr
.X_add_symbol
, (long) 0,
3957 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3960 macro_build (p
, &icnt
, &expr1
,
3961 mips_isa
< 3 ? "addiu" : "daddiu",
3962 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3963 /* FIXME: If breg == 0, and the next instruction uses
3964 $tempreg, then if this variant case is used an extra
3965 nop will be generated. */
3967 else if (expr1
.X_add_number
>= -0x8000
3968 && expr1
.X_add_number
< 0x8000)
3970 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3972 macro_build ((char *) NULL
, &icnt
, &expr1
,
3973 mips_isa
< 3 ? "addiu" : "daddiu",
3974 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3975 (void) frag_var (rs_machine_dependent
, 0, 0,
3976 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3977 offset_expr
.X_add_symbol
, (long) 0,
3984 /* If we are going to add in a base register, and the
3985 target register and the base register are the same,
3986 then we are using AT as a temporary register. Since
3987 we want to load the constant into AT, we add our
3988 current AT (from the global offset table) and the
3989 register into the register now, and pretend we were
3990 not using a base register. */
3995 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3997 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3998 mips_isa
< 3 ? "addu" : "daddu",
3999 "d,v,t", treg
, AT
, breg
);
4005 /* Set mips_optimize around the lui instruction to avoid
4006 inserting an unnecessary nop after the lw. */
4007 hold_mips_optimize
= mips_optimize
;
4009 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4010 mips_optimize
= hold_mips_optimize
;
4012 macro_build ((char *) NULL
, &icnt
, &expr1
,
4013 mips_isa
< 3 ? "addiu" : "daddiu",
4014 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4016 mips_isa
< 3 ? "addu" : "daddu",
4017 "d,v,t", tempreg
, tempreg
, AT
);
4018 (void) frag_var (rs_machine_dependent
, 0, 0,
4019 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4020 offset_expr
.X_add_symbol
, (long) 0,
4025 else if (mips_pic
== SVR4_PIC
)
4029 /* This is the large GOT case. If this is a reference to an
4030 external symbol, and there is no constant, we want
4031 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4032 addu $tempreg,$tempreg,$gp
4033 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4034 For a local symbol, we want
4035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4037 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4039 If we have a small constant, and this is a reference to
4040 an external symbol, we want
4041 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4042 addu $tempreg,$tempreg,$gp
4043 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4045 addiu $tempreg,$tempreg,<constant>
4046 For a local symbol, we want
4047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4049 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4051 If we have a large constant, and this is a reference to
4052 an external symbol, we want
4053 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4054 addu $tempreg,$tempreg,$gp
4055 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4056 lui $at,<hiconstant>
4057 addiu $at,$at,<loconstant>
4058 addu $tempreg,$tempreg,$at
4059 For a local symbol, we want
4060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4061 lui $at,<hiconstant>
4062 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4063 addu $tempreg,$tempreg,$at
4065 expr1
.X_add_number
= offset_expr
.X_add_number
;
4066 offset_expr
.X_add_number
= 0;
4068 if (reg_needs_delay (GP
))
4072 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4073 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4074 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4075 mips_isa
< 3 ? "addu" : "daddu",
4076 "d,v,t", tempreg
, tempreg
, GP
);
4077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4079 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4081 if (expr1
.X_add_number
== 0)
4089 /* We're going to put in an addu instruction using
4090 tempreg, so we may as well insert the nop right
4092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4097 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4098 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4101 ? mips_warn_about_macros
4103 offset_expr
.X_add_symbol
, (long) 0,
4106 else if (expr1
.X_add_number
>= -0x8000
4107 && expr1
.X_add_number
< 0x8000)
4109 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4111 macro_build ((char *) NULL
, &icnt
, &expr1
,
4112 mips_isa
< 3 ? "addiu" : "daddiu",
4113 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4115 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4116 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4118 ? mips_warn_about_macros
4120 offset_expr
.X_add_symbol
, (long) 0,
4127 /* If we are going to add in a base register, and the
4128 target register and the base register are the same,
4129 then we are using AT as a temporary register. Since
4130 we want to load the constant into AT, we add our
4131 current AT (from the global offset table) and the
4132 register into the register now, and pretend we were
4133 not using a base register. */
4141 assert (tempreg
== AT
);
4142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4145 mips_isa
< 3 ? "addu" : "daddu",
4146 "d,v,t", treg
, AT
, breg
);
4151 /* Set mips_optimize around the lui instruction to avoid
4152 inserting an unnecessary nop after the lw. */
4153 hold_mips_optimize
= mips_optimize
;
4155 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4156 mips_optimize
= hold_mips_optimize
;
4158 macro_build ((char *) NULL
, &icnt
, &expr1
,
4159 mips_isa
< 3 ? "addiu" : "daddiu",
4160 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4161 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4162 mips_isa
< 3 ? "addu" : "daddu",
4163 "d,v,t", dreg
, dreg
, AT
);
4165 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4166 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4169 ? mips_warn_about_macros
4171 offset_expr
.X_add_symbol
, (long) 0,
4179 /* This is needed because this instruction uses $gp, but
4180 the first instruction on the main stream does not. */
4181 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4184 macro_build (p
, &icnt
, &offset_expr
,
4186 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4188 if (expr1
.X_add_number
>= -0x8000
4189 && expr1
.X_add_number
< 0x8000)
4191 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4193 macro_build (p
, &icnt
, &expr1
,
4194 mips_isa
< 3 ? "addiu" : "daddiu",
4195 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4196 /* FIXME: If add_number is 0, and there was no base
4197 register, the external symbol case ended with a load,
4198 so if the symbol turns out to not be external, and
4199 the next instruction uses tempreg, an unnecessary nop
4200 will be inserted. */
4206 /* We must add in the base register now, as in the
4207 external symbol case. */
4208 assert (tempreg
== AT
);
4209 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4211 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4212 mips_isa
< 3 ? "addu" : "daddu",
4213 "d,v,t", treg
, AT
, breg
);
4216 /* We set breg to 0 because we have arranged to add
4217 it in in both cases. */
4221 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4223 macro_build (p
, &icnt
, &expr1
,
4224 mips_isa
< 3 ? "addiu" : "daddiu",
4225 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4227 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4228 mips_isa
< 3 ? "addu" : "daddu",
4229 "d,v,t", tempreg
, tempreg
, AT
);
4233 else if (mips_pic
== EMBEDDED_PIC
)
4236 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4239 mips_isa
< 3 ? "addiu" : "daddiu",
4240 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4247 mips_isa
< 3 ? "addu" : "daddu",
4248 "d,v,t", treg
, tempreg
, breg
);
4256 /* The j instruction may not be used in PIC code, since it
4257 requires an absolute address. We convert it to a b
4259 if (mips_pic
== NO_PIC
)
4260 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4262 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4265 /* The jal instructions must be handled as macros because when
4266 generating PIC code they expand to multi-instruction
4267 sequences. Normally they are simple instructions. */
4272 if (mips_pic
== NO_PIC
4273 || mips_pic
== EMBEDDED_PIC
)
4274 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4276 else if (mips_pic
== SVR4_PIC
)
4278 if (sreg
!= PIC_CALL_REG
)
4279 as_warn ("MIPS PIC call to register other than $25");
4281 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4283 if (mips_cprestore_offset
< 0)
4284 as_warn ("No .cprestore pseudo-op used in PIC code");
4287 expr1
.X_add_number
= mips_cprestore_offset
;
4288 macro_build ((char *) NULL
, &icnt
, &expr1
,
4289 mips_isa
< 3 ? "lw" : "ld",
4290 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4299 if (mips_pic
== NO_PIC
)
4300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4301 else if (mips_pic
== SVR4_PIC
)
4303 /* If this is a reference to an external symbol, and we are
4304 using a small GOT, we want
4305 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4309 lw $gp,cprestore($sp)
4310 The cprestore value is set using the .cprestore
4311 pseudo-op. If we are using a big GOT, we want
4312 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4314 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4318 lw $gp,cprestore($sp)
4319 If the symbol is not external, we want
4320 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4322 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4325 lw $gp,cprestore($sp) */
4329 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4330 mips_isa
< 3 ? "lw" : "ld",
4331 "t,o(b)", PIC_CALL_REG
,
4332 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4335 p
= frag_var (rs_machine_dependent
, 4, 0,
4336 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4337 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4343 if (reg_needs_delay (GP
))
4347 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4348 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4349 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4350 mips_isa
< 3 ? "addu" : "daddu",
4351 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4352 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4353 mips_isa
< 3 ? "lw" : "ld",
4354 "t,o(b)", PIC_CALL_REG
,
4355 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4358 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4359 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4361 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4364 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4367 macro_build (p
, &icnt
, &offset_expr
,
4368 mips_isa
< 3 ? "lw" : "ld",
4369 "t,o(b)", PIC_CALL_REG
,
4370 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4372 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4375 macro_build (p
, &icnt
, &offset_expr
,
4376 mips_isa
< 3 ? "addiu" : "daddiu",
4377 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4378 (int) BFD_RELOC_LO16
);
4379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4380 "jalr", "s", PIC_CALL_REG
);
4381 if (mips_cprestore_offset
< 0)
4382 as_warn ("No .cprestore pseudo-op used in PIC code");
4386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4388 expr1
.X_add_number
= mips_cprestore_offset
;
4389 macro_build ((char *) NULL
, &icnt
, &expr1
,
4390 mips_isa
< 3 ? "lw" : "ld",
4391 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4395 else if (mips_pic
== EMBEDDED_PIC
)
4397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4398 /* The linker may expand the call to a longer sequence which
4399 uses $at, so we must break rather than return. */
4475 if (breg
== treg
|| coproc
|| lr
)
4544 if (mask
== M_LWC1_AB
4545 || mask
== M_SWC1_AB
4546 || mask
== M_LDC1_AB
4547 || mask
== M_SDC1_AB
4556 if (offset_expr
.X_op
!= O_constant
4557 && offset_expr
.X_op
!= O_symbol
)
4559 as_bad ("expression too complex");
4560 offset_expr
.X_op
= O_constant
;
4563 /* A constant expression in PIC code can be handled just as it
4564 is in non PIC code. */
4565 if (mips_pic
== NO_PIC
4566 || offset_expr
.X_op
== O_constant
)
4568 /* If this is a reference to a GP relative symbol, and there
4569 is no base register, we want
4570 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4571 Otherwise, if there is no base register, we want
4572 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4573 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4574 If we have a constant, we need two instructions anyhow,
4575 so we always use the latter form.
4577 If we have a base register, and this is a reference to a
4578 GP relative symbol, we want
4579 addu $tempreg,$breg,$gp
4580 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4582 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4583 addu $tempreg,$tempreg,$breg
4584 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4585 With a constant we always use the latter case. */
4588 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4589 || nopic_need_relax (offset_expr
.X_add_symbol
))
4594 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4595 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4596 p
= frag_var (rs_machine_dependent
, 8, 0,
4597 RELAX_ENCODE (4, 8, 0, 4, 0,
4598 (mips_warn_about_macros
4599 || (used_at
&& mips_noat
))),
4600 offset_expr
.X_add_symbol
, (long) 0,
4604 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4607 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4608 (int) BFD_RELOC_LO16
, tempreg
);
4612 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4613 || nopic_need_relax (offset_expr
.X_add_symbol
))
4618 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4619 mips_isa
< 3 ? "addu" : "daddu",
4620 "d,v,t", tempreg
, breg
, GP
);
4621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4622 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4623 p
= frag_var (rs_machine_dependent
, 12, 0,
4624 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4625 offset_expr
.X_add_symbol
, (long) 0,
4628 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4631 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4632 mips_isa
< 3 ? "addu" : "daddu",
4633 "d,v,t", tempreg
, tempreg
, breg
);
4636 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4637 (int) BFD_RELOC_LO16
, tempreg
);
4640 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4642 /* If this is a reference to an external symbol, we want
4643 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4645 <op> $treg,0($tempreg)
4647 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4649 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4650 <op> $treg,0($tempreg)
4651 If there is a base register, we add it to $tempreg before
4652 the <op>. If there is a constant, we stick it in the
4653 <op> instruction. We don't handle constants larger than
4654 16 bits, because we have no way to load the upper 16 bits
4655 (actually, we could handle them for the subset of cases
4656 in which we are not using $at). */
4657 assert (offset_expr
.X_op
== O_symbol
);
4658 expr1
.X_add_number
= offset_expr
.X_add_number
;
4659 offset_expr
.X_add_number
= 0;
4660 if (expr1
.X_add_number
< -0x8000
4661 || expr1
.X_add_number
>= 0x8000)
4662 as_bad ("PIC code offset overflow (max 16 signed bits)");
4664 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4665 mips_isa
< 3 ? "lw" : "ld",
4666 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4668 p
= frag_var (rs_machine_dependent
, 4, 0,
4669 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4670 offset_expr
.X_add_symbol
, (long) 0,
4672 macro_build (p
, &icnt
, &offset_expr
,
4673 mips_isa
< 3 ? "addiu" : "daddiu",
4674 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4676 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4677 mips_isa
< 3 ? "addu" : "daddu",
4678 "d,v,t", tempreg
, tempreg
, breg
);
4679 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4680 (int) BFD_RELOC_LO16
, tempreg
);
4682 else if (mips_pic
== SVR4_PIC
)
4686 /* If this is a reference to an external symbol, we want
4687 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4688 addu $tempreg,$tempreg,$gp
4689 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4690 <op> $treg,0($tempreg)
4692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4694 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4695 <op> $treg,0($tempreg)
4696 If there is a base register, we add it to $tempreg before
4697 the <op>. If there is a constant, we stick it in the
4698 <op> instruction. We don't handle constants larger than
4699 16 bits, because we have no way to load the upper 16 bits
4700 (actually, we could handle them for the subset of cases
4701 in which we are not using $at). */
4702 assert (offset_expr
.X_op
== O_symbol
);
4703 expr1
.X_add_number
= offset_expr
.X_add_number
;
4704 offset_expr
.X_add_number
= 0;
4705 if (expr1
.X_add_number
< -0x8000
4706 || expr1
.X_add_number
>= 0x8000)
4707 as_bad ("PIC code offset overflow (max 16 signed bits)");
4708 if (reg_needs_delay (GP
))
4713 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4714 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4716 mips_isa
< 3 ? "addu" : "daddu",
4717 "d,v,t", tempreg
, tempreg
, GP
);
4718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4719 mips_isa
< 3 ? "lw" : "ld",
4720 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4722 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4723 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4724 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4727 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4730 macro_build (p
, &icnt
, &offset_expr
,
4731 mips_isa
< 3 ? "lw" : "ld",
4732 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4734 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4736 macro_build (p
, &icnt
, &offset_expr
,
4737 mips_isa
< 3 ? "addiu" : "daddiu",
4738 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4740 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4741 mips_isa
< 3 ? "addu" : "daddu",
4742 "d,v,t", tempreg
, tempreg
, breg
);
4743 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4744 (int) BFD_RELOC_LO16
, tempreg
);
4746 else if (mips_pic
== EMBEDDED_PIC
)
4748 /* If there is no base register, we want
4749 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4750 If there is a base register, we want
4751 addu $tempreg,$breg,$gp
4752 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4754 assert (offset_expr
.X_op
== O_symbol
);
4757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4758 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4763 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4764 mips_isa
< 3 ? "addu" : "daddu",
4765 "d,v,t", tempreg
, breg
, GP
);
4766 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4767 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4780 load_register (&icnt
, treg
, &imm_expr
, 0);
4784 load_register (&icnt
, treg
, &imm_expr
, 1);
4788 if (imm_expr
.X_op
== O_constant
)
4790 load_register (&icnt
, AT
, &imm_expr
, 0);
4791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4792 "mtc1", "t,G", AT
, treg
);
4797 assert (offset_expr
.X_op
== O_symbol
4798 && strcmp (segment_name (S_GET_SEGMENT
4799 (offset_expr
.X_add_symbol
)),
4801 && offset_expr
.X_add_number
== 0);
4802 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4803 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4808 /* We know that sym is in the .rdata section. First we get the
4809 upper 16 bits of the address. */
4810 if (mips_pic
== NO_PIC
)
4812 /* FIXME: This won't work for a 64 bit address. */
4813 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4815 else if (mips_pic
== SVR4_PIC
)
4817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4818 mips_isa
< 3 ? "lw" : "ld",
4819 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4821 else if (mips_pic
== EMBEDDED_PIC
)
4823 /* For embedded PIC we pick up the entire address off $gp in
4824 a single instruction. */
4825 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4826 mips_isa
< 3 ? "addiu" : "daddiu",
4827 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4828 offset_expr
.X_op
= O_constant
;
4829 offset_expr
.X_add_number
= 0;
4834 /* Now we load the register(s). */
4836 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4837 treg
, (int) BFD_RELOC_LO16
, AT
);
4840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4841 treg
, (int) BFD_RELOC_LO16
, AT
);
4844 /* FIXME: How in the world do we deal with the possible
4846 offset_expr
.X_add_number
+= 4;
4847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4848 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4852 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4853 does not become a variant frag. */
4854 frag_wane (frag_now
);
4860 assert (offset_expr
.X_op
== O_symbol
4861 && offset_expr
.X_add_number
== 0);
4862 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4863 if (strcmp (s
, ".lit8") == 0)
4867 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4868 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4872 r
= BFD_RELOC_MIPS_LITERAL
;
4877 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4878 if (mips_pic
== SVR4_PIC
)
4879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4880 mips_isa
< 3 ? "lw" : "ld",
4881 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4884 /* FIXME: This won't work for a 64 bit address. */
4885 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4890 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4891 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4893 /* To avoid confusion in tc_gen_reloc, we must ensure
4894 that this does not become a variant frag. */
4895 frag_wane (frag_now
);
4906 /* Even on a big endian machine $fn comes before $fn+1. We have
4907 to adjust when loading from memory. */
4910 assert (mips_isa
< 2);
4911 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4912 target_big_endian
? treg
+ 1 : treg
,
4914 /* FIXME: A possible overflow which I don't know how to deal
4916 offset_expr
.X_add_number
+= 4;
4917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4918 target_big_endian
? treg
: treg
+ 1,
4921 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4922 does not become a variant frag. */
4923 frag_wane (frag_now
);
4932 * The MIPS assembler seems to check for X_add_number not
4933 * being double aligned and generating:
4936 * addiu at,at,%lo(foo+1)
4939 * But, the resulting address is the same after relocation so why
4940 * generate the extra instruction?
4987 if (offset_expr
.X_op
!= O_symbol
4988 && offset_expr
.X_op
!= O_constant
)
4990 as_bad ("expression too complex");
4991 offset_expr
.X_op
= O_constant
;
4994 /* Even on a big endian machine $fn comes before $fn+1. We have
4995 to adjust when loading from memory. We set coproc if we must
4996 load $fn+1 first. */
4997 if (! target_big_endian
)
5000 if (mips_pic
== NO_PIC
5001 || offset_expr
.X_op
== O_constant
)
5003 /* If this is a reference to a GP relative symbol, we want
5004 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5005 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5006 If we have a base register, we use this
5008 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5009 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5010 If this is not a GP relative symbol, we want
5011 lui $at,<sym> (BFD_RELOC_HI16_S)
5012 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5013 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5014 If there is a base register, we add it to $at after the
5015 lui instruction. If there is a constant, we always use
5017 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5018 || nopic_need_relax (offset_expr
.X_add_symbol
))
5037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5038 mips_isa
< 3 ? "addu" : "daddu",
5039 "d,v,t", AT
, breg
, GP
);
5045 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5046 coproc
? treg
+ 1 : treg
,
5047 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5048 offset_expr
.X_add_number
+= 4;
5050 /* Set mips_optimize to 2 to avoid inserting an
5052 hold_mips_optimize
= mips_optimize
;
5054 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5055 coproc
? treg
: treg
+ 1,
5056 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5057 mips_optimize
= hold_mips_optimize
;
5059 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5060 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5061 used_at
&& mips_noat
),
5062 offset_expr
.X_add_symbol
, (long) 0,
5065 /* We just generated two relocs. When tc_gen_reloc
5066 handles this case, it will skip the first reloc and
5067 handle the second. The second reloc already has an
5068 extra addend of 4, which we added above. We must
5069 subtract it out, and then subtract another 4 to make
5070 the first reloc come out right. The second reloc
5071 will come out right because we are going to add 4 to
5072 offset_expr when we build its instruction below. */
5073 offset_expr
.X_add_number
-= 8;
5074 offset_expr
.X_op
= O_constant
;
5076 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5081 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5082 mips_isa
< 3 ? "addu" : "daddu",
5083 "d,v,t", AT
, breg
, AT
);
5087 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5088 coproc
? treg
+ 1 : treg
,
5089 (int) BFD_RELOC_LO16
, AT
);
5092 /* FIXME: How do we handle overflow here? */
5093 offset_expr
.X_add_number
+= 4;
5094 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5095 coproc
? treg
: treg
+ 1,
5096 (int) BFD_RELOC_LO16
, AT
);
5098 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5102 /* If this is a reference to an external symbol, we want
5103 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5108 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5110 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5111 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5112 If there is a base register we add it to $at before the
5113 lwc1 instructions. If there is a constant we include it
5114 in the lwc1 instructions. */
5116 expr1
.X_add_number
= offset_expr
.X_add_number
;
5117 offset_expr
.X_add_number
= 0;
5118 if (expr1
.X_add_number
< -0x8000
5119 || expr1
.X_add_number
>= 0x8000 - 4)
5120 as_bad ("PIC code offset overflow (max 16 signed bits)");
5125 frag_grow (24 + off
);
5126 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5127 mips_isa
< 3 ? "lw" : "ld",
5128 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5129 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5132 mips_isa
< 3 ? "addu" : "daddu",
5133 "d,v,t", AT
, breg
, AT
);
5134 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5135 coproc
? treg
+ 1 : treg
,
5136 (int) BFD_RELOC_LO16
, AT
);
5137 expr1
.X_add_number
+= 4;
5139 /* Set mips_optimize to 2 to avoid inserting an undesired
5141 hold_mips_optimize
= mips_optimize
;
5143 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5144 coproc
? treg
: treg
+ 1,
5145 (int) BFD_RELOC_LO16
, AT
);
5146 mips_optimize
= hold_mips_optimize
;
5148 (void) frag_var (rs_machine_dependent
, 0, 0,
5149 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5150 offset_expr
.X_add_symbol
, (long) 0,
5153 else if (mips_pic
== SVR4_PIC
)
5157 /* If this is a reference to an external symbol, we want
5158 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5160 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5165 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5167 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5168 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5169 If there is a base register we add it to $at before the
5170 lwc1 instructions. If there is a constant we include it
5171 in the lwc1 instructions. */
5173 expr1
.X_add_number
= offset_expr
.X_add_number
;
5174 offset_expr
.X_add_number
= 0;
5175 if (expr1
.X_add_number
< -0x8000
5176 || expr1
.X_add_number
>= 0x8000 - 4)
5177 as_bad ("PIC code offset overflow (max 16 signed bits)");
5178 if (reg_needs_delay (GP
))
5187 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5188 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5190 mips_isa
< 3 ? "addu" : "daddu",
5191 "d,v,t", AT
, AT
, GP
);
5192 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5193 mips_isa
< 3 ? "lw" : "ld",
5194 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5195 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5198 mips_isa
< 3 ? "addu" : "daddu",
5199 "d,v,t", AT
, breg
, AT
);
5200 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5201 coproc
? treg
+ 1 : treg
,
5202 (int) BFD_RELOC_LO16
, AT
);
5203 expr1
.X_add_number
+= 4;
5205 /* Set mips_optimize to 2 to avoid inserting an undesired
5207 hold_mips_optimize
= mips_optimize
;
5209 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5210 coproc
? treg
: treg
+ 1,
5211 (int) BFD_RELOC_LO16
, AT
);
5212 mips_optimize
= hold_mips_optimize
;
5213 expr1
.X_add_number
-= 4;
5215 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5216 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5217 8 + gpdel
+ off
, 1, 0),
5218 offset_expr
.X_add_symbol
, (long) 0,
5222 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5225 macro_build (p
, &icnt
, &offset_expr
,
5226 mips_isa
< 3 ? "lw" : "ld",
5227 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5229 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5233 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5234 mips_isa
< 3 ? "addu" : "daddu",
5235 "d,v,t", AT
, breg
, AT
);
5238 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5239 coproc
? treg
+ 1 : treg
,
5240 (int) BFD_RELOC_LO16
, AT
);
5242 expr1
.X_add_number
+= 4;
5244 /* Set mips_optimize to 2 to avoid inserting an undesired
5246 hold_mips_optimize
= mips_optimize
;
5248 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5249 coproc
? treg
: treg
+ 1,
5250 (int) BFD_RELOC_LO16
, AT
);
5251 mips_optimize
= hold_mips_optimize
;
5253 else if (mips_pic
== EMBEDDED_PIC
)
5255 /* If there is no base register, we use
5256 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5257 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5258 If we have a base register, we use
5260 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5261 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5270 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5271 mips_isa
< 3 ? "addu" : "daddu",
5272 "d,v,t", AT
, breg
, GP
);
5277 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5278 coproc
? treg
+ 1 : treg
,
5279 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5280 offset_expr
.X_add_number
+= 4;
5281 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5282 coproc
? treg
: treg
+ 1,
5283 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5299 assert (mips_isa
< 3);
5300 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5301 (int) BFD_RELOC_LO16
, breg
);
5302 offset_expr
.X_add_number
+= 4;
5303 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5304 (int) BFD_RELOC_LO16
, breg
);
5306 #ifdef LOSING_COMPILER
5312 as_warn ("Macro used $at after \".set noat\"");
5317 struct mips_cl_insn
*ip
;
5319 register int treg
, sreg
, dreg
, breg
;
5334 bfd_reloc_code_real_type r
;
5337 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5338 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5339 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5340 mask
= ip
->insn_mo
->mask
;
5342 expr1
.X_op
= O_constant
;
5343 expr1
.X_op_symbol
= NULL
;
5344 expr1
.X_add_symbol
= NULL
;
5345 expr1
.X_add_number
= 1;
5349 #endif /* LOSING_COMPILER */
5354 macro_build ((char *) NULL
, &icnt
, NULL
,
5355 dbl
? "dmultu" : "multu",
5357 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5363 /* The MIPS assembler some times generates shifts and adds. I'm
5364 not trying to be that fancy. GCC should do this for us
5366 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5367 macro_build ((char *) NULL
, &icnt
, NULL
,
5368 dbl
? "dmult" : "mult",
5370 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5376 mips_emit_delays (true);
5378 mips_any_noreorder
= 1;
5379 macro_build ((char *) NULL
, &icnt
, NULL
,
5380 dbl
? "dmult" : "mult",
5382 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5383 macro_build ((char *) NULL
, &icnt
, NULL
,
5384 dbl
? "dsra32" : "sra",
5385 "d,w,<", dreg
, dreg
, 31);
5386 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5388 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5391 expr1
.X_add_number
= 8;
5392 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5393 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5394 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5397 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5403 mips_emit_delays (true);
5405 mips_any_noreorder
= 1;
5406 macro_build ((char *) NULL
, &icnt
, NULL
,
5407 dbl
? "dmultu" : "multu",
5409 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5410 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5412 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5415 expr1
.X_add_number
= 8;
5416 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5417 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5418 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5424 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5425 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5426 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5428 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5432 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5433 (int) (imm_expr
.X_add_number
& 0x1f));
5434 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5435 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5436 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5440 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5441 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5442 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5444 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5448 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5449 (int) (imm_expr
.X_add_number
& 0x1f));
5450 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5451 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5452 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5456 assert (mips_isa
< 2);
5457 /* Even on a big endian machine $fn comes before $fn+1. We have
5458 to adjust when storing to memory. */
5459 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5460 target_big_endian
? treg
+ 1 : treg
,
5461 (int) BFD_RELOC_LO16
, breg
);
5462 offset_expr
.X_add_number
+= 4;
5463 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5464 target_big_endian
? treg
: treg
+ 1,
5465 (int) BFD_RELOC_LO16
, breg
);
5470 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5471 treg
, (int) BFD_RELOC_LO16
);
5473 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5474 sreg
, (int) BFD_RELOC_LO16
);
5477 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5479 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5480 dreg
, (int) BFD_RELOC_LO16
);
5485 if (imm_expr
.X_add_number
== 0)
5487 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5488 sreg
, (int) BFD_RELOC_LO16
);
5493 as_warn ("Instruction %s: result is always false",
5495 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5498 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5500 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5501 sreg
, (int) BFD_RELOC_LO16
);
5504 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5506 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5507 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5508 mips_isa
< 3 ? "addiu" : "daddiu",
5509 "t,r,j", dreg
, sreg
,
5510 (int) BFD_RELOC_LO16
);
5515 load_register (&icnt
, AT
, &imm_expr
, 0);
5516 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5520 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5521 (int) BFD_RELOC_LO16
);
5526 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5532 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5533 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5534 (int) BFD_RELOC_LO16
);
5537 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5539 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5541 macro_build ((char *) NULL
, &icnt
, &expr1
,
5542 mask
== M_SGE_I
? "slti" : "sltiu",
5543 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5548 load_register (&icnt
, AT
, &imm_expr
, 0);
5549 macro_build ((char *) NULL
, &icnt
, NULL
,
5550 mask
== M_SGE_I
? "slt" : "sltu",
5551 "d,v,t", dreg
, sreg
, AT
);
5554 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5555 (int) BFD_RELOC_LO16
);
5560 case M_SGT
: /* sreg > treg <==> treg < sreg */
5566 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5569 case M_SGT_I
: /* sreg > I <==> I < sreg */
5575 load_register (&icnt
, AT
, &imm_expr
, 0);
5576 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5579 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5585 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5586 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5587 (int) BFD_RELOC_LO16
);
5590 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5596 load_register (&icnt
, AT
, &imm_expr
, 0);
5597 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5598 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5599 (int) BFD_RELOC_LO16
);
5603 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5605 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5606 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5609 load_register (&icnt
, AT
, &imm_expr
, 0);
5610 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5614 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5616 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5617 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5620 load_register (&icnt
, AT
, &imm_expr
, 0);
5621 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5627 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5630 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5634 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5636 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5642 if (imm_expr
.X_add_number
== 0)
5644 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5650 as_warn ("Instruction %s: result is always true",
5652 macro_build ((char *) NULL
, &icnt
, &expr1
,
5653 mips_isa
< 3 ? "addiu" : "daddiu",
5654 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5657 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5659 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5660 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5663 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5665 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5666 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5667 mips_isa
< 3 ? "addiu" : "daddiu",
5668 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5673 load_register (&icnt
, AT
, &imm_expr
, 0);
5674 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5678 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5686 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5688 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5689 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5690 dbl
? "daddi" : "addi",
5691 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5694 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5695 macro_build ((char *) NULL
, &icnt
, NULL
,
5696 dbl
? "dsub" : "sub",
5697 "d,v,t", dreg
, sreg
, AT
);
5703 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5705 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5706 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5707 dbl
? "daddiu" : "addiu",
5708 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5711 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5712 macro_build ((char *) NULL
, &icnt
, NULL
,
5713 dbl
? "dsubu" : "subu",
5714 "d,v,t", dreg
, sreg
, AT
);
5735 load_register (&icnt
, AT
, &imm_expr
, 0);
5736 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5741 assert (mips_isa
< 2);
5742 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5743 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5746 * Is the double cfc1 instruction a bug in the mips assembler;
5747 * or is there a reason for it?
5749 mips_emit_delays (true);
5751 mips_any_noreorder
= 1;
5752 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5753 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5754 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5755 expr1
.X_add_number
= 3;
5756 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5757 (int) BFD_RELOC_LO16
);
5758 expr1
.X_add_number
= 2;
5759 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5760 (int) BFD_RELOC_LO16
);
5761 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5762 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5763 macro_build ((char *) NULL
, &icnt
, NULL
,
5764 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5765 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5766 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5776 if (offset_expr
.X_add_number
>= 0x7fff)
5777 as_bad ("operand overflow");
5778 /* avoid load delay */
5779 if (! target_big_endian
)
5780 offset_expr
.X_add_number
+= 1;
5781 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5782 (int) BFD_RELOC_LO16
, breg
);
5783 if (! target_big_endian
)
5784 offset_expr
.X_add_number
-= 1;
5786 offset_expr
.X_add_number
+= 1;
5787 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5788 (int) BFD_RELOC_LO16
, breg
);
5789 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5790 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5803 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5804 as_bad ("operand overflow");
5805 if (! target_big_endian
)
5806 offset_expr
.X_add_number
+= off
;
5807 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5808 (int) BFD_RELOC_LO16
, breg
);
5809 if (! target_big_endian
)
5810 offset_expr
.X_add_number
-= off
;
5812 offset_expr
.X_add_number
+= off
;
5813 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5814 (int) BFD_RELOC_LO16
, breg
);
5827 load_address (&icnt
, AT
, &offset_expr
);
5829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5830 mips_isa
< 3 ? "addu" : "daddu",
5831 "d,v,t", AT
, AT
, breg
);
5832 if (! target_big_endian
)
5833 expr1
.X_add_number
= off
;
5835 expr1
.X_add_number
= 0;
5836 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5837 (int) BFD_RELOC_LO16
, AT
);
5838 if (! target_big_endian
)
5839 expr1
.X_add_number
= 0;
5841 expr1
.X_add_number
= off
;
5842 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5843 (int) BFD_RELOC_LO16
, AT
);
5848 load_address (&icnt
, AT
, &offset_expr
);
5850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5851 mips_isa
< 3 ? "addu" : "daddu",
5852 "d,v,t", AT
, AT
, breg
);
5853 if (target_big_endian
)
5854 expr1
.X_add_number
= 0;
5855 macro_build ((char *) NULL
, &icnt
, &expr1
,
5856 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5857 (int) BFD_RELOC_LO16
, AT
);
5858 if (target_big_endian
)
5859 expr1
.X_add_number
= 1;
5861 expr1
.X_add_number
= 0;
5862 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5863 (int) BFD_RELOC_LO16
, AT
);
5864 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5866 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5871 if (offset_expr
.X_add_number
>= 0x7fff)
5872 as_bad ("operand overflow");
5873 if (target_big_endian
)
5874 offset_expr
.X_add_number
+= 1;
5875 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5876 (int) BFD_RELOC_LO16
, breg
);
5877 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5878 if (target_big_endian
)
5879 offset_expr
.X_add_number
-= 1;
5881 offset_expr
.X_add_number
+= 1;
5882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5883 (int) BFD_RELOC_LO16
, breg
);
5896 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5897 as_bad ("operand overflow");
5898 if (! target_big_endian
)
5899 offset_expr
.X_add_number
+= off
;
5900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5901 (int) BFD_RELOC_LO16
, breg
);
5902 if (! target_big_endian
)
5903 offset_expr
.X_add_number
-= off
;
5905 offset_expr
.X_add_number
+= off
;
5906 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5907 (int) BFD_RELOC_LO16
, breg
);
5920 load_address (&icnt
, AT
, &offset_expr
);
5922 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5923 mips_isa
< 3 ? "addu" : "daddu",
5924 "d,v,t", AT
, AT
, breg
);
5925 if (! target_big_endian
)
5926 expr1
.X_add_number
= off
;
5928 expr1
.X_add_number
= 0;
5929 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5930 (int) BFD_RELOC_LO16
, AT
);
5931 if (! target_big_endian
)
5932 expr1
.X_add_number
= 0;
5934 expr1
.X_add_number
= off
;
5935 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5936 (int) BFD_RELOC_LO16
, AT
);
5940 load_address (&icnt
, AT
, &offset_expr
);
5942 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5943 mips_isa
< 3 ? "addu" : "daddu",
5944 "d,v,t", AT
, AT
, breg
);
5945 if (! target_big_endian
)
5946 expr1
.X_add_number
= 0;
5947 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5948 (int) BFD_RELOC_LO16
, AT
);
5949 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5951 if (! target_big_endian
)
5952 expr1
.X_add_number
= 1;
5954 expr1
.X_add_number
= 0;
5955 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5956 (int) BFD_RELOC_LO16
, AT
);
5957 if (! target_big_endian
)
5958 expr1
.X_add_number
= 0;
5960 expr1
.X_add_number
= 1;
5961 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5962 (int) BFD_RELOC_LO16
, AT
);
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5965 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5970 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5974 as_warn ("Macro used $at after \".set noat\"");
5977 /* Implement macros in mips16 mode. */
5981 struct mips_cl_insn
*ip
;
5984 int xreg
, yreg
, zreg
, tmp
;
5988 const char *s
, *s2
, *s3
;
5990 mask
= ip
->insn_mo
->mask
;
5992 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5993 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5994 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5998 expr1
.X_op
= O_constant
;
5999 expr1
.X_op_symbol
= NULL
;
6000 expr1
.X_add_symbol
= NULL
;
6001 expr1
.X_add_number
= 1;
6020 mips_emit_delays (true);
6022 mips_any_noreorder
= 1;
6023 macro_build ((char *) NULL
, &icnt
, NULL
,
6024 dbl
? "ddiv" : "div",
6025 "0,x,y", xreg
, yreg
);
6026 expr1
.X_add_number
= 2;
6027 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6029 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6030 since that causes an overflow. We should do that as well,
6031 but I don't see how to do the comparisons without a temporary
6034 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6053 mips_emit_delays (true);
6055 mips_any_noreorder
= 1;
6056 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6057 expr1
.X_add_number
= 2;
6058 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6059 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6061 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6069 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6070 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6071 dbl
? "daddiu" : "addiu",
6072 "y,x,4", yreg
, xreg
);
6076 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6077 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6082 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6083 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6106 goto do_reverse_branch
;
6110 goto do_reverse_branch
;
6122 goto do_reverse_branch
;
6133 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6135 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6162 goto do_addone_branch_i
;
6167 goto do_addone_branch_i
;
6182 goto do_addone_branch_i
;
6189 ++imm_expr
.X_add_number
;
6192 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6193 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6197 expr1
.X_add_number
= 0;
6198 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6201 "move", "y,X", xreg
, yreg
);
6202 expr1
.X_add_number
= 2;
6203 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6204 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6205 "neg", "x,w", xreg
, xreg
);
6209 /* This routine assembles an instruction into its binary format. As a
6210 side effect, it sets one of the global variables imm_reloc or
6211 offset_reloc to the type of relocation to do if one of the operands
6212 is an address expression. */
6217 struct mips_cl_insn
*ip
;
6222 struct mips_opcode
*insn
;
6225 unsigned int lastregno
= 0;
6230 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6242 as_fatal ("Unknown opcode: `%s'", str
);
6244 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6246 insn_error
= "unrecognized opcode";
6254 assert (strcmp (insn
->name
, str
) == 0);
6256 if (insn
->pinfo
== INSN_MACRO
)
6257 insn_isa
= insn
->match
;
6258 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6260 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6262 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6267 if (insn_isa
> mips_isa
6268 || (insn
->pinfo
!= INSN_MACRO
6269 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6271 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6273 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6275 /* start-sanitize-r5900 */
6276 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6278 /* end-sanitize-r5900 */
6281 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6282 && strcmp (insn
->name
, insn
[1].name
) == 0)
6287 if (insn_isa
<= mips_isa
)
6288 insn_error
= "opcode not supported on this processor";
6291 static char buf
[100];
6293 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6300 ip
->insn_opcode
= insn
->match
;
6301 for (args
= insn
->args
;; ++args
)
6307 case '\0': /* end of args */
6320 ip
->insn_opcode
|= lastregno
<< 21;
6325 ip
->insn_opcode
|= lastregno
<< 16;
6329 ip
->insn_opcode
|= lastregno
<< 11;
6335 /* handle optional base register.
6336 Either the base register is omitted or
6337 we must have a left paren. */
6338 /* this is dependent on the next operand specifier
6339 is a 'b' for base register */
6340 assert (args
[1] == 'b');
6344 case ')': /* these must match exactly */
6349 case '<': /* must be at least one digit */
6351 * According to the manual, if the shift amount is greater
6352 * than 31 or less than 0 the the shift amount should be
6353 * mod 32. In reality the mips assembler issues an error.
6354 * We issue a warning and mask out all but the low 5 bits.
6356 my_getExpression (&imm_expr
, s
);
6357 check_absolute_expr (ip
, &imm_expr
);
6358 if ((unsigned long) imm_expr
.X_add_number
> 31)
6360 as_warn ("Improper shift amount (%ld)",
6361 (long) imm_expr
.X_add_number
);
6362 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6364 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6365 imm_expr
.X_op
= O_absent
;
6369 case '>': /* shift amount minus 32 */
6370 my_getExpression (&imm_expr
, s
);
6371 check_absolute_expr (ip
, &imm_expr
);
6372 if ((unsigned long) imm_expr
.X_add_number
< 32
6373 || (unsigned long) imm_expr
.X_add_number
> 63)
6375 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6376 imm_expr
.X_op
= O_absent
;
6380 case 'k': /* cache code */
6381 case 'h': /* prefx code */
6382 my_getExpression (&imm_expr
, s
);
6383 check_absolute_expr (ip
, &imm_expr
);
6384 if ((unsigned long) imm_expr
.X_add_number
> 31)
6386 as_warn ("Invalid value for `%s' (%lu)",
6388 (unsigned long) imm_expr
.X_add_number
);
6389 imm_expr
.X_add_number
&= 0x1f;
6392 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6394 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6395 imm_expr
.X_op
= O_absent
;
6399 case 'c': /* break code */
6400 my_getExpression (&imm_expr
, s
);
6401 check_absolute_expr (ip
, &imm_expr
);
6402 if ((unsigned) imm_expr
.X_add_number
> 1023)
6403 as_warn ("Illegal break code (%ld)",
6404 (long) imm_expr
.X_add_number
);
6405 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6406 imm_expr
.X_op
= O_absent
;
6410 case 'B': /* syscall code */
6411 my_getExpression (&imm_expr
, s
);
6412 check_absolute_expr (ip
, &imm_expr
);
6413 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6414 as_warn ("Illegal syscall code (%ld)",
6415 (long) imm_expr
.X_add_number
);
6416 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6417 imm_expr
.X_op
= O_absent
;
6421 case 'C': /* Coprocessor code */
6422 my_getExpression (&imm_expr
, s
);
6423 check_absolute_expr (ip
, &imm_expr
);
6424 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6426 as_warn ("Coproccesor code > 25 bits (%ld)",
6427 (long) imm_expr
.X_add_number
);
6428 imm_expr
.X_add_number
&= ((1<<25) - 1);
6430 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6431 imm_expr
.X_op
= O_absent
;
6435 case 'b': /* base register */
6436 case 'd': /* destination register */
6437 case 's': /* source register */
6438 case 't': /* target register */
6439 case 'r': /* both target and source */
6440 case 'v': /* both dest and source */
6441 case 'w': /* both dest and target */
6442 case 'E': /* coprocessor target register */
6443 case 'G': /* coprocessor destination register */
6444 case 'x': /* ignore register name */
6445 case 'z': /* must be zero register */
6459 while (isdigit (*s
));
6461 as_bad ("Invalid register number (%d)", regno
);
6463 else if (*args
== 'E' || *args
== 'G')
6467 if (s
[1] == 'f' && s
[2] == 'p')
6472 else if (s
[1] == 's' && s
[2] == 'p')
6477 else if (s
[1] == 'g' && s
[2] == 'p')
6482 else if (s
[1] == 'a' && s
[2] == 't')
6487 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6492 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6504 as_warn ("Used $at without \".set noat\"");
6510 if (c
== 'r' || c
== 'v' || c
== 'w')
6517 /* 'z' only matches $0. */
6518 if (c
== 'z' && regno
!= 0)
6526 ip
->insn_opcode
|= regno
<< 21;
6530 ip
->insn_opcode
|= regno
<< 11;
6535 ip
->insn_opcode
|= regno
<< 16;
6538 /* This case exists because on the r3000 trunc
6539 expands into a macro which requires a gp
6540 register. On the r6000 or r4000 it is
6541 assembled into a single instruction which
6542 ignores the register. Thus the insn version
6543 is MIPS_ISA2 and uses 'x', and the macro
6544 version is MIPS_ISA1 and uses 't'. */
6547 /* This case is for the div instruction, which
6548 acts differently if the destination argument
6549 is $0. This only matches $0, and is checked
6550 outside the switch. */
6561 ip
->insn_opcode
|= lastregno
<< 21;
6564 ip
->insn_opcode
|= lastregno
<< 16;
6569 case 'D': /* floating point destination register */
6570 case 'S': /* floating point source register */
6571 case 'T': /* floating point target register */
6572 case 'R': /* floating point source register */
6576 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6586 while (isdigit (*s
));
6589 as_bad ("Invalid float register number (%d)", regno
);
6591 if ((regno
& 1) != 0
6593 && ! (strcmp (str
, "mtc1") == 0
6594 || strcmp (str
, "mfc1") == 0
6595 || strcmp (str
, "lwc1") == 0
6596 || strcmp (str
, "swc1") == 0
6597 || strcmp (str
, "l.s") == 0
6598 || strcmp (str
, "s.s") == 0))
6599 as_warn ("Float register should be even, was %d",
6607 if (c
== 'V' || c
== 'W')
6617 ip
->insn_opcode
|= regno
<< 6;
6621 ip
->insn_opcode
|= regno
<< 11;
6625 ip
->insn_opcode
|= regno
<< 16;
6628 ip
->insn_opcode
|= regno
<< 21;
6637 ip
->insn_opcode
|= lastregno
<< 11;
6640 ip
->insn_opcode
|= lastregno
<< 16;
6646 my_getExpression (&imm_expr
, s
);
6647 if (imm_expr
.X_op
!= O_big
6648 && imm_expr
.X_op
!= O_constant
)
6649 insn_error
= "absolute expression required";
6654 my_getExpression (&offset_expr
, s
);
6655 imm_reloc
= BFD_RELOC_32
;
6667 unsigned char temp
[8];
6669 unsigned int length
;
6674 /* These only appear as the last operand in an
6675 instruction, and every instruction that accepts
6676 them in any variant accepts them in all variants.
6677 This means we don't have to worry about backing out
6678 any changes if the instruction does not match.
6680 The difference between them is the size of the
6681 floating point constant and where it goes. For 'F'
6682 and 'L' the constant is 64 bits; for 'f' and 'l' it
6683 is 32 bits. Where the constant is placed is based
6684 on how the MIPS assembler does things:
6687 f -- immediate value
6690 The .lit4 and .lit8 sections are only used if
6691 permitted by the -G argument.
6693 When generating embedded PIC code, we use the
6694 .lit8 section but not the .lit4 section (we can do
6695 .lit4 inline easily; we need to put .lit8
6696 somewhere in the data segment, and using .lit8
6697 permits the linker to eventually combine identical
6700 f64
= *args
== 'F' || *args
== 'L';
6702 save_in
= input_line_pointer
;
6703 input_line_pointer
= s
;
6704 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6706 s
= input_line_pointer
;
6707 input_line_pointer
= save_in
;
6708 if (err
!= NULL
&& *err
!= '\0')
6710 as_bad ("Bad floating point constant: %s", err
);
6711 memset (temp
, '\0', sizeof temp
);
6712 length
= f64
? 8 : 4;
6715 assert (length
== (f64
? 8 : 4));
6719 && (! USE_GLOBAL_POINTER_OPT
6720 || mips_pic
== EMBEDDED_PIC
6721 || g_switch_value
< 4)
6724 imm_expr
.X_op
= O_constant
;
6725 if (! target_big_endian
)
6726 imm_expr
.X_add_number
=
6727 (((((((int) temp
[3] << 8)
6732 imm_expr
.X_add_number
=
6733 (((((((int) temp
[0] << 8)
6740 const char *newname
;
6743 /* Switch to the right section. */
6745 subseg
= now_subseg
;
6748 default: /* unused default case avoids warnings. */
6750 newname
= RDATA_SECTION_NAME
;
6751 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6755 newname
= RDATA_SECTION_NAME
;
6758 assert (!USE_GLOBAL_POINTER_OPT
6759 || g_switch_value
>= 4);
6763 new_seg
= subseg_new (newname
, (subsegT
) 0);
6764 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6765 bfd_set_section_flags (stdoutput
, new_seg
,
6770 frag_align (*args
== 'l' ? 2 : 3, 0);
6771 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6772 record_alignment (new_seg
, 4);
6774 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6776 as_bad ("Can't use floating point insn in this section");
6778 /* Set the argument to the current address in the
6780 offset_expr
.X_op
= O_symbol
;
6781 offset_expr
.X_add_symbol
=
6782 symbol_new ("L0\001", now_seg
,
6783 (valueT
) frag_now_fix (), frag_now
);
6784 offset_expr
.X_add_number
= 0;
6786 /* Put the floating point number into the section. */
6787 p
= frag_more ((int) length
);
6788 memcpy (p
, temp
, length
);
6790 /* Switch back to the original section. */
6791 subseg_set (seg
, subseg
);
6796 case 'i': /* 16 bit unsigned immediate */
6797 case 'j': /* 16 bit signed immediate */
6798 imm_reloc
= BFD_RELOC_LO16
;
6799 c
= my_getSmallExpression (&imm_expr
, s
);
6804 if (imm_expr
.X_op
== O_constant
)
6805 imm_expr
.X_add_number
=
6806 (imm_expr
.X_add_number
>> 16) & 0xffff;
6809 imm_reloc
= BFD_RELOC_HI16_S
;
6810 imm_unmatched_hi
= true;
6813 imm_reloc
= BFD_RELOC_HI16
;
6818 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6819 || ((imm_expr
.X_add_number
< 0
6820 || imm_expr
.X_add_number
>= 0x10000)
6821 && imm_expr
.X_op
== O_constant
))
6823 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6824 !strcmp (insn
->name
, insn
[1].name
))
6826 if (imm_expr
.X_op
!= O_constant
6827 && imm_expr
.X_op
!= O_big
)
6828 insn_error
= "absolute expression required";
6830 as_bad ("16 bit expression not in range 0..65535");
6838 /* The upper bound should be 0x8000, but
6839 unfortunately the MIPS assembler accepts numbers
6840 from 0x8000 to 0xffff and sign extends them, and
6841 we want to be compatible. We only permit this
6842 extended range for an instruction which does not
6843 provide any further alternates, since those
6844 alternates may handle other cases. People should
6845 use the numbers they mean, rather than relying on
6846 a mysterious sign extension. */
6847 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6848 strcmp (insn
->name
, insn
[1].name
) == 0);
6853 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6854 || ((imm_expr
.X_add_number
< -0x8000
6855 || imm_expr
.X_add_number
>= max
)
6856 && imm_expr
.X_op
== O_constant
)
6858 && imm_expr
.X_add_number
< 0
6860 && imm_expr
.X_unsigned
6861 && sizeof (imm_expr
.X_add_number
) <= 4))
6865 if (imm_expr
.X_op
!= O_constant
6866 && imm_expr
.X_op
!= O_big
)
6867 insn_error
= "absolute expression required";
6869 as_bad ("16 bit expression not in range -32768..32767");
6875 case 'o': /* 16 bit offset */
6876 c
= my_getSmallExpression (&offset_expr
, s
);
6878 /* If this value won't fit into a 16 bit offset, then go
6879 find a macro that will generate the 32 bit offset
6880 code pattern. As a special hack, we accept the
6881 difference of two local symbols as a constant. This
6882 is required to suppose embedded PIC switches, which
6883 use an instruction which looks like
6884 lw $4,$L12-$LS12($4)
6885 The problem with handling this in a more general
6886 fashion is that the macro function doesn't expect to
6887 see anything which can be handled in a single
6888 constant instruction. */
6890 && (offset_expr
.X_op
!= O_constant
6891 || offset_expr
.X_add_number
>= 0x8000
6892 || offset_expr
.X_add_number
< -0x8000)
6893 && (mips_pic
!= EMBEDDED_PIC
6894 || offset_expr
.X_op
!= O_subtract
6895 || now_seg
!= text_section
6896 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6900 offset_reloc
= BFD_RELOC_LO16
;
6901 if (c
== 'h' || c
== 'H')
6903 assert (offset_expr
.X_op
== O_constant
);
6904 offset_expr
.X_add_number
=
6905 (offset_expr
.X_add_number
>> 16) & 0xffff;
6910 case 'p': /* pc relative offset */
6911 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6912 my_getExpression (&offset_expr
, s
);
6916 case 'u': /* upper 16 bits */
6917 c
= my_getSmallExpression (&imm_expr
, s
);
6918 if (imm_expr
.X_op
== O_constant
6919 && (imm_expr
.X_add_number
< 0
6920 || imm_expr
.X_add_number
>= 0x10000))
6921 as_bad ("lui expression not in range 0..65535");
6922 imm_reloc
= BFD_RELOC_LO16
;
6927 if (imm_expr
.X_op
== O_constant
)
6928 imm_expr
.X_add_number
=
6929 (imm_expr
.X_add_number
>> 16) & 0xffff;
6932 imm_reloc
= BFD_RELOC_HI16_S
;
6933 imm_unmatched_hi
= true;
6936 imm_reloc
= BFD_RELOC_HI16
;
6942 case 'a': /* 26 bit address */
6943 my_getExpression (&offset_expr
, s
);
6945 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6948 case 'N': /* 3 bit branch condition code */
6949 case 'M': /* 3 bit compare condition code */
6950 if (strncmp (s
, "$fcc", 4) != 0)
6960 while (isdigit (*s
));
6962 as_bad ("invalid condition code register $fcc%d", regno
);
6964 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6966 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6970 fprintf (stderr
, "bad char = '%c'\n", *args
);
6975 /* Args don't match. */
6976 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6977 !strcmp (insn
->name
, insn
[1].name
))
6983 insn_error
= "illegal operands";
6988 /* This routine assembles an instruction into its binary format when
6989 assembling for the mips16. As a side effect, it sets one of the
6990 global variables imm_reloc or offset_reloc to the type of
6991 relocation to do if one of the operands is an address expression.
6992 It also sets mips16_small and mips16_ext if the user explicitly
6993 requested a small or extended instruction. */
6998 struct mips_cl_insn
*ip
;
7002 struct mips_opcode
*insn
;
7005 unsigned int lastregno
= 0;
7010 mips16_small
= false;
7013 for (s
= str
; islower (*s
); ++s
)
7025 if (s
[1] == 't' && s
[2] == ' ')
7028 mips16_small
= true;
7032 else if (s
[1] == 'e' && s
[2] == ' ')
7041 insn_error
= "unknown opcode";
7045 if (! mips16_autoextend
&& ! mips16_ext
)
7046 mips16_small
= true;
7048 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7050 insn_error
= "unrecognized opcode";
7057 assert (strcmp (insn
->name
, str
) == 0);
7060 ip
->insn_opcode
= insn
->match
;
7061 ip
->use_extend
= false;
7062 imm_expr
.X_op
= O_absent
;
7063 imm_reloc
= BFD_RELOC_UNUSED
;
7064 offset_expr
.X_op
= O_absent
;
7065 offset_reloc
= BFD_RELOC_UNUSED
;
7066 for (args
= insn
->args
; 1; ++args
)
7073 /* In this switch statement we call break if we did not find
7074 a match, continue if we did find a match, or return if we
7083 /* Stuff the immediate value in now, if we can. */
7084 if (imm_expr
.X_op
== O_constant
7085 && imm_reloc
> BFD_RELOC_UNUSED
7086 && insn
->pinfo
!= INSN_MACRO
)
7088 mips16_immed ((char *) NULL
, 0,
7089 imm_reloc
- BFD_RELOC_UNUSED
,
7090 imm_expr
.X_add_number
, true, mips16_small
,
7091 mips16_ext
, &ip
->insn_opcode
,
7092 &ip
->use_extend
, &ip
->extend
);
7093 imm_expr
.X_op
= O_absent
;
7094 imm_reloc
= BFD_RELOC_UNUSED
;
7108 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7111 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7127 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7129 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7156 while (isdigit (*s
));
7159 as_bad ("invalid register number (%d)", regno
);
7165 if (s
[1] == 'f' && s
[2] == 'p')
7170 else if (s
[1] == 's' && s
[2] == 'p')
7175 else if (s
[1] == 'g' && s
[2] == 'p')
7180 else if (s
[1] == 'a' && s
[2] == 't')
7185 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7190 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7203 if (c
== 'v' || c
== 'w')
7205 regno
= mips16_to_32_reg_map
[lastregno
];
7219 regno
= mips32_to_16_reg_map
[regno
];
7224 regno
= ILLEGAL_REG
;
7229 regno
= ILLEGAL_REG
;
7234 regno
= ILLEGAL_REG
;
7239 if (regno
== AT
&& ! mips_noat
)
7240 as_warn ("used $at without \".set noat\"");
7247 if (regno
== ILLEGAL_REG
)
7254 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7258 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7261 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7264 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7270 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7273 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7274 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7284 if (strncmp (s
, "$pc", 3) == 0)
7308 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7310 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7311 and generate the appropriate reloc. If the text
7312 inside %gprel is not a symbol name with an
7313 optional offset, then we generate a normal reloc
7314 and will probably fail later. */
7315 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7316 if (imm_expr
.X_op
== O_symbol
)
7319 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7321 ip
->use_extend
= true;
7328 /* Just pick up a normal expression. */
7329 my_getExpression (&imm_expr
, s
);
7332 if (imm_expr
.X_op
== O_register
)
7334 /* What we thought was an expression turned out to
7337 if (s
[0] == '(' && args
[1] == '(')
7339 /* It looks like the expression was omitted
7340 before a register indirection, which means
7341 that the expression is implicitly zero. We
7342 still set up imm_expr, so that we handle
7343 explicit extensions correctly. */
7344 imm_expr
.X_op
= O_constant
;
7345 imm_expr
.X_add_number
= 0;
7346 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7353 /* We need to relax this instruction. */
7354 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7363 /* We use offset_reloc rather than imm_reloc for the PC
7364 relative operands. This lets macros with both
7365 immediate and address operands work correctly. */
7366 my_getExpression (&offset_expr
, s
);
7368 if (offset_expr
.X_op
== O_register
)
7371 /* We need to relax this instruction. */
7372 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7376 case '6': /* break code */
7377 my_getExpression (&imm_expr
, s
);
7378 check_absolute_expr (ip
, &imm_expr
);
7379 if ((unsigned long) imm_expr
.X_add_number
> 63)
7381 as_warn ("Invalid value for `%s' (%lu)",
7383 (unsigned long) imm_expr
.X_add_number
);
7384 imm_expr
.X_add_number
&= 0x3f;
7386 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7387 imm_expr
.X_op
= O_absent
;
7391 case 'a': /* 26 bit address */
7392 my_getExpression (&offset_expr
, s
);
7394 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7395 ip
->insn_opcode
<<= 16;
7398 case 'l': /* register list for entry macro */
7399 case 'L': /* register list for exit macro */
7409 int freg
, reg1
, reg2
;
7411 while (*s
== ' ' || *s
== ',')
7415 as_bad ("can't parse register list");
7427 while (isdigit (*s
))
7449 as_bad ("invalid register list");
7454 while (isdigit (*s
))
7461 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7466 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7471 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7472 mask
|= (reg2
- 3) << 3;
7473 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7474 mask
|= (reg2
- 15) << 1;
7475 else if (reg1
== 31 && reg2
== 31)
7479 as_bad ("invalid register list");
7483 /* The mask is filled in in the opcode table for the
7484 benefit of the disassembler. We remove it before
7485 applying the actual mask. */
7486 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7487 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7491 case 'e': /* extend code */
7492 my_getExpression (&imm_expr
, s
);
7493 check_absolute_expr (ip
, &imm_expr
);
7494 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7496 as_warn ("Invalid value for `%s' (%lu)",
7498 (unsigned long) imm_expr
.X_add_number
);
7499 imm_expr
.X_add_number
&= 0x7ff;
7501 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7502 imm_expr
.X_op
= O_absent
;
7512 /* Args don't match. */
7513 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7514 strcmp (insn
->name
, insn
[1].name
) == 0)
7521 insn_error
= "illegal operands";
7527 /* This structure holds information we know about a mips16 immediate
7530 struct mips16_immed_operand
7532 /* The type code used in the argument string in the opcode table. */
7534 /* The number of bits in the short form of the opcode. */
7536 /* The number of bits in the extended form of the opcode. */
7538 /* The amount by which the short form is shifted when it is used;
7539 for example, the sw instruction has a shift count of 2. */
7541 /* The amount by which the short form is shifted when it is stored
7542 into the instruction code. */
7544 /* Non-zero if the short form is unsigned. */
7546 /* Non-zero if the extended form is unsigned. */
7548 /* Non-zero if the value is PC relative. */
7552 /* The mips16 immediate operand types. */
7554 static const struct mips16_immed_operand mips16_immed_operands
[] =
7556 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7557 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7558 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7559 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7560 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7561 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7562 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7563 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7564 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7565 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7566 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7567 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7568 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7569 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7570 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7571 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7572 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7573 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7574 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7575 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7576 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7579 #define MIPS16_NUM_IMMED \
7580 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7582 /* Handle a mips16 instruction with an immediate value. This or's the
7583 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7584 whether an extended value is needed; if one is needed, it sets
7585 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7586 If SMALL is true, an unextended opcode was explicitly requested.
7587 If EXT is true, an extended opcode was explicitly requested. If
7588 WARN is true, warn if EXT does not match reality. */
7591 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7600 unsigned long *insn
;
7601 boolean
*use_extend
;
7602 unsigned short *extend
;
7604 register const struct mips16_immed_operand
*op
;
7605 int mintiny
, maxtiny
;
7608 op
= mips16_immed_operands
;
7609 while (op
->type
!= type
)
7612 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7617 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7620 maxtiny
= 1 << op
->nbits
;
7625 maxtiny
= (1 << op
->nbits
) - 1;
7630 mintiny
= - (1 << (op
->nbits
- 1));
7631 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7634 /* Branch offsets have an implicit 0 in the lowest bit. */
7635 if (type
== 'p' || type
== 'q')
7638 if ((val
& ((1 << op
->shift
) - 1)) != 0
7639 || val
< (mintiny
<< op
->shift
)
7640 || val
> (maxtiny
<< op
->shift
))
7645 if (warn
&& ext
&& ! needext
)
7646 as_warn_where (file
, line
, "extended operand requested but not required");
7647 if (small
&& needext
)
7648 as_bad_where (file
, line
, "invalid unextended operand value");
7650 if (small
|| (! ext
&& ! needext
))
7654 *use_extend
= false;
7655 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7656 insnval
<<= op
->op_shift
;
7661 long minext
, maxext
;
7667 maxext
= (1 << op
->extbits
) - 1;
7671 minext
= - (1 << (op
->extbits
- 1));
7672 maxext
= (1 << (op
->extbits
- 1)) - 1;
7674 if (val
< minext
|| val
> maxext
)
7675 as_bad_where (file
, line
,
7676 "operand value out of range for instruction");
7679 if (op
->extbits
== 16)
7681 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7684 else if (op
->extbits
== 15)
7686 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7691 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7695 *extend
= (unsigned short) extval
;
7704 my_getSmallExpression (ep
, str
)
7715 ((str
[1] == 'h' && str
[2] == 'i')
7716 || (str
[1] == 'H' && str
[2] == 'I')
7717 || (str
[1] == 'l' && str
[2] == 'o'))
7729 * A small expression may be followed by a base register.
7730 * Scan to the end of this operand, and then back over a possible
7731 * base register. Then scan the small expression up to that
7732 * point. (Based on code in sparc.c...)
7734 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7736 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7738 if (isdigit (sp
[-2]))
7740 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7742 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7748 else if (sp
- 5 >= str
7751 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7752 || (sp
[-3] == 's' && sp
[-2] == 'p')
7753 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7754 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7760 /* no expression means zero offset */
7763 /* %xx(reg) is an error */
7764 ep
->X_op
= O_absent
;
7769 ep
->X_op
= O_constant
;
7772 ep
->X_add_symbol
= NULL
;
7773 ep
->X_op_symbol
= NULL
;
7774 ep
->X_add_number
= 0;
7779 my_getExpression (ep
, str
);
7786 my_getExpression (ep
, str
);
7787 return c
; /* => %hi or %lo encountered */
7791 my_getExpression (ep
, str
)
7797 save_in
= input_line_pointer
;
7798 input_line_pointer
= str
;
7800 expr_end
= input_line_pointer
;
7801 input_line_pointer
= save_in
;
7803 /* If we are in mips16 mode, and this is an expression based on `.',
7804 then we bump the value of the symbol by 1 since that is how other
7805 text symbols are handled. We don't bother to handle complex
7806 expressions, just `.' plus or minus a constant. */
7808 && ep
->X_op
== O_symbol
7809 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
7810 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
7811 && ep
->X_add_symbol
->sy_frag
== frag_now
7812 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
7813 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
7814 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
7817 /* Turn a string in input_line_pointer into a floating point constant
7818 of type type, and store the appropriate bytes in *litP. The number
7819 of LITTLENUMS emitted is stored in *sizeP . An error message is
7820 returned, or NULL on OK. */
7823 md_atof (type
, litP
, sizeP
)
7829 LITTLENUM_TYPE words
[4];
7845 return "bad call to md_atof";
7848 t
= atof_ieee (input_line_pointer
, type
, words
);
7850 input_line_pointer
= t
;
7854 if (! target_big_endian
)
7856 for (i
= prec
- 1; i
>= 0; i
--)
7858 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7864 for (i
= 0; i
< prec
; i
++)
7866 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7875 md_number_to_chars (buf
, val
, n
)
7880 if (target_big_endian
)
7881 number_to_chars_bigendian (buf
, val
, n
);
7883 number_to_chars_littleendian (buf
, val
, n
);
7886 CONST
char *md_shortopts
= "O::g::G:";
7888 struct option md_longopts
[] = {
7889 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7890 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7891 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7892 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7893 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7894 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7895 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7896 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7897 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7898 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7899 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7900 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7901 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7902 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7903 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7904 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7905 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7906 {"break", no_argument
, NULL
, OPTION_BREAK
},
7907 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7908 #define OPTION_EB (OPTION_MD_BASE + 11)
7909 {"EB", no_argument
, NULL
, OPTION_EB
},
7910 #define OPTION_EL (OPTION_MD_BASE + 12)
7911 {"EL", no_argument
, NULL
, OPTION_EL
},
7912 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7913 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7914 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7915 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7916 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7917 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7918 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7919 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7920 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7921 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7922 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7923 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7924 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7925 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7926 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7927 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7928 /* start-sanitize-5900 */
7929 #define OPTION_M5900 (OPTION_MD_BASE + 24)
7930 {"m5900", no_argument
, NULL
, OPTION_M5900
},
7931 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
7932 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
7933 /* end-sanitize-5900 */
7935 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7936 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7937 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7938 #define OPTION_32 (OPTION_MD_BASE + 20)
7939 #define OPTION_64 (OPTION_MD_BASE + 21)
7941 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7942 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7943 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7944 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7945 {"32", no_argument
, NULL
, OPTION_32
},
7946 {"64", no_argument
, NULL
, OPTION_64
},
7949 {NULL
, no_argument
, NULL
, 0}
7951 size_t md_longopts_size
= sizeof(md_longopts
);
7954 md_parse_option (c
, arg
)
7969 target_big_endian
= 1;
7973 target_big_endian
= 0;
7977 if (arg
&& arg
[1] == '0')
7987 mips_debug
= atoi (arg
);
7988 /* When the MIPS assembler sees -g or -g2, it does not do
7989 optimizations which limit full symbolic debugging. We take
7990 that to be equivalent to -O0. */
7991 if (mips_debug
== 2)
8023 /* Identify the processor type */
8025 if (strcmp (p
, "default") == 0
8026 || strcmp (p
, "DEFAULT") == 0)
8032 /* We need to cope with the various "vr" prefixes for the 4300
8034 if (*p
== 'v' || *p
== 'V')
8040 if (*p
== 'r' || *p
== 'R')
8047 if (strcmp (p
, "10000") == 0
8048 || strcmp (p
, "10k") == 0
8049 || strcmp (p
, "10K") == 0)
8054 if (strcmp (p
, "2000") == 0
8055 || strcmp (p
, "2k") == 0
8056 || strcmp (p
, "2K") == 0)
8061 if (strcmp (p
, "3000") == 0
8062 || strcmp (p
, "3k") == 0
8063 || strcmp (p
, "3K") == 0)
8068 if (strcmp (p
, "4000") == 0
8069 || strcmp (p
, "4k") == 0
8070 || strcmp (p
, "4K") == 0)
8072 else if (strcmp (p
, "4100") == 0)
8078 else if (strcmp (p
, "4300") == 0)
8080 else if (strcmp (p
, "4400") == 0)
8082 else if (strcmp (p
, "4600") == 0)
8084 else if (strcmp (p
, "4650") == 0)
8090 else if (strcmp (p
, "4010") == 0)
8099 if (strcmp (p
, "5000") == 0
8100 || strcmp (p
, "5k") == 0
8101 || strcmp (p
, "5K") == 0)
8103 /* start-sanitize-r5900 */
8104 else if (strcmp (p
, "5900") == 0)
8106 /* end-sanitize-r5900 */
8110 if (strcmp (p
, "6000") == 0
8111 || strcmp (p
, "6k") == 0
8112 || strcmp (p
, "6K") == 0)
8117 if (strcmp (p
, "8000") == 0
8118 || strcmp (p
, "8k") == 0
8119 || strcmp (p
, "8K") == 0)
8124 if (strcmp (p
, "orion") == 0)
8129 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8131 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8137 as_bad ("invalid architecture -mcpu=%s", arg
);
8148 case OPTION_NO_M4650
:
8156 case OPTION_NO_M4010
:
8164 case OPTION_NO_M4100
:
8168 /* start-sanitize-r5900 */
8173 case OPTION_NO_M5900
:
8176 /* end-sanitize-r5900 */
8180 mips_no_prev_insn (false);
8183 case OPTION_NO_MIPS16
:
8185 mips_no_prev_insn (false);
8188 case OPTION_MEMBEDDED_PIC
:
8189 mips_pic
= EMBEDDED_PIC
;
8190 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8192 as_bad ("-G may not be used with embedded PIC code");
8195 g_switch_value
= 0x7fffffff;
8198 /* When generating ELF code, we permit -KPIC and -call_shared to
8199 select SVR4_PIC, and -non_shared to select no PIC. This is
8200 intended to be compatible with Irix 5. */
8201 case OPTION_CALL_SHARED
:
8202 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8204 as_bad ("-call_shared is supported only for ELF format");
8207 mips_pic
= SVR4_PIC
;
8208 if (g_switch_seen
&& g_switch_value
!= 0)
8210 as_bad ("-G may not be used with SVR4 PIC code");
8216 case OPTION_NON_SHARED
:
8217 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8219 as_bad ("-non_shared is supported only for ELF format");
8225 /* The -xgot option tells the assembler to use 32 offsets when
8226 accessing the got in SVR4_PIC mode. It is for Irix
8233 if (! USE_GLOBAL_POINTER_OPT
)
8235 as_bad ("-G is not supported for this configuration");
8238 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8240 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8244 g_switch_value
= atoi (arg
);
8248 /* The -32 and -64 options tell the assembler to output the 32
8249 bit or the 64 bit MIPS ELF format. */
8256 const char **list
, **l
;
8258 list
= bfd_target_list ();
8259 for (l
= list
; *l
!= NULL
; l
++)
8260 if (strcmp (*l
, "elf64-bigmips") == 0
8261 || strcmp (*l
, "elf64-littlemips") == 0)
8264 as_fatal ("No compiled in support for 64 bit object file format");
8278 md_show_usage (stream
)
8283 -membedded-pic generate embedded position independent code\n\
8284 -EB generate big endian output\n\
8285 -EL generate little endian output\n\
8286 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8287 -G NUM allow referencing objects up to NUM bytes\n\
8288 implicitly with the gp register [default 8]\n");
8290 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8291 -mips2, -mcpu=r6000 generate code for r6000\n\
8292 -mips3, -mcpu=r4000 generate code for r4000\n\
8293 -mips4, -mcpu=r8000 generate code for r8000\n\
8294 -mcpu=vr4300 generate code for vr4300\n\
8295 -mcpu=vr4100 generate code for vr4100\n\
8296 -m4650 permit R4650 instructions\n\
8297 -no-m4650 do not permit R4650 instructions\n\
8298 -m4010 permit R4010 instructions\n\
8299 -no-m4010 do not permit R4010 instructions\n\
8300 -m4100 permit VR4100 instructions\n\
8301 -no-m4100 do not permit VR4100 instructions\n");
8303 -mips16 generate mips16 instructions\n\
8304 -no-mips16 do not generate mips16 instructions\n");
8306 -O0 remove unneeded NOPs, do not swap branches\n\
8307 -O remove unneeded NOPs and swap branches\n\
8308 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8309 --break, --no-trap break exception on div by 0 and mult overflow\n");
8312 -KPIC, -call_shared generate SVR4 position independent code\n\
8313 -non_shared do not generate position independent code\n\
8314 -xgot assume a 32 bit GOT\n\
8315 -32 create 32 bit object file (default)\n\
8316 -64 create 64 bit object file\n");
8321 md_pcrel_from (fixP
)
8324 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8325 && fixP
->fx_addsy
!= (symbolS
*) NULL
8326 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8328 /* This makes a branch to an undefined symbol be a branch to the
8329 current location. */
8333 /* return the address of the delay slot */
8334 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8337 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8338 reloc for a cons. We could use the definition there, except that
8339 we want to handle 64 bit relocs specially. */
8342 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8345 unsigned int nbytes
;
8349 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8351 if (nbytes
== 8 && ! mips_64
)
8353 if (target_big_endian
)
8359 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8360 as_bad ("Unsupported reloc size %d", nbytes
);
8362 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8365 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8368 /* Sort any unmatched HI16_S relocs so that they immediately precede
8369 the corresponding LO reloc. This is called before md_apply_fix and
8370 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8371 explicit use of the %hi modifier. */
8376 struct mips_hi_fixup
*l
;
8378 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8380 segment_info_type
*seginfo
;
8383 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8385 /* Check quickly whether the next fixup happens to be a matching
8387 if (l
->fixp
->fx_next
!= NULL
8388 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8389 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8390 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8393 /* Look through the fixups for this segment for a matching %lo.
8394 When we find one, move the %hi just in front of it. We do
8395 this in two passes. In the first pass, we try to find a
8396 unique %lo. In the second pass, we permit multiple %hi
8397 relocs for a single %lo (this is a GNU extension). */
8398 seginfo
= seg_info (l
->seg
);
8399 for (pass
= 0; pass
< 2; pass
++)
8404 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8406 /* Check whether this is a %lo fixup which matches l->fixp. */
8407 if (f
->fx_r_type
== BFD_RELOC_LO16
8408 && f
->fx_addsy
== l
->fixp
->fx_addsy
8409 && f
->fx_offset
== l
->fixp
->fx_offset
8412 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8413 || prev
->fx_addsy
!= f
->fx_addsy
8414 || prev
->fx_offset
!= f
->fx_offset
))
8418 /* Move l->fixp before f. */
8419 for (pf
= &seginfo
->fix_root
;
8421 pf
= &(*pf
)->fx_next
)
8422 assert (*pf
!= NULL
);
8424 *pf
= l
->fixp
->fx_next
;
8426 l
->fixp
->fx_next
= f
;
8428 seginfo
->fix_root
= l
->fixp
;
8430 prev
->fx_next
= l
->fixp
;
8442 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8443 "Unmatched %%hi reloc");
8448 /* When generating embedded PIC code we need to use a special
8449 relocation to represent the difference of two symbols in the .text
8450 section (switch tables use a difference of this sort). See
8451 include/coff/mips.h for details. This macro checks whether this
8452 fixup requires the special reloc. */
8453 #define SWITCH_TABLE(fixp) \
8454 ((fixp)->fx_r_type == BFD_RELOC_32 \
8455 && (fixp)->fx_addsy != NULL \
8456 && (fixp)->fx_subsy != NULL \
8457 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8458 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8460 /* When generating embedded PIC code we must keep all PC relative
8461 relocations, in case the linker has to relax a call. We also need
8462 to keep relocations for switch table entries. */
8466 mips_force_relocation (fixp
)
8469 return (mips_pic
== EMBEDDED_PIC
8471 || SWITCH_TABLE (fixp
)
8472 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8473 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8476 /* Apply a fixup to the object file. */
8479 md_apply_fix (fixP
, valueP
)
8486 assert (fixP
->fx_size
== 4
8487 || fixP
->fx_r_type
== BFD_RELOC_16
8488 || fixP
->fx_r_type
== BFD_RELOC_64
);
8492 /* If we aren't adjusting this fixup to be against the section
8493 symbol, we need to adjust the value. */
8495 if (fixP
->fx_addsy
!= NULL
8496 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8497 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8499 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8500 if (value
!= 0 && ! fixP
->fx_pcrel
)
8502 /* In this case, the bfd_install_relocation routine will
8503 incorrectly add the symbol value back in. We just want
8504 the addend to appear in the object file. */
8505 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8510 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8512 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8515 switch (fixP
->fx_r_type
)
8517 case BFD_RELOC_MIPS_JMP
:
8518 case BFD_RELOC_HI16
:
8519 case BFD_RELOC_HI16_S
:
8520 case BFD_RELOC_MIPS_GPREL
:
8521 case BFD_RELOC_MIPS_LITERAL
:
8522 case BFD_RELOC_MIPS_CALL16
:
8523 case BFD_RELOC_MIPS_GOT16
:
8524 case BFD_RELOC_MIPS_GPREL32
:
8525 case BFD_RELOC_MIPS_GOT_HI16
:
8526 case BFD_RELOC_MIPS_GOT_LO16
:
8527 case BFD_RELOC_MIPS_CALL_HI16
:
8528 case BFD_RELOC_MIPS_CALL_LO16
:
8529 case BFD_RELOC_MIPS16_GPREL
:
8531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8532 "Invalid PC relative reloc");
8533 /* Nothing needed to do. The value comes from the reloc entry */
8536 case BFD_RELOC_MIPS16_JMP
:
8537 /* We currently always generate a reloc against a symbol, which
8538 means that we don't want an addend even if the symbol is
8540 fixP
->fx_addnumber
= 0;
8543 case BFD_RELOC_PCREL_HI16_S
:
8544 /* The addend for this is tricky if it is internal, so we just
8545 do everything here rather than in bfd_perform_relocation. */
8546 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8548 /* For an external symbol adjust by the address to make it
8549 pcrel_offset. We use the address of the RELLO reloc
8550 which follows this one. */
8551 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8552 + fixP
->fx_next
->fx_where
);
8557 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8558 if (target_big_endian
)
8560 md_number_to_chars (buf
, value
, 2);
8563 case BFD_RELOC_PCREL_LO16
:
8564 /* The addend for this is tricky if it is internal, so we just
8565 do everything here rather than in bfd_perform_relocation. */
8566 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8567 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8568 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8569 if (target_big_endian
)
8571 md_number_to_chars (buf
, value
, 2);
8575 /* This is handled like BFD_RELOC_32, but we output a sign
8576 extended value if we are only 32 bits. */
8578 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8580 if (8 <= sizeof (valueT
))
8581 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8588 w1
= w2
= fixP
->fx_where
;
8589 if (target_big_endian
)
8593 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8594 if ((value
& 0x80000000) != 0)
8598 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8604 /* If we are deleting this reloc entry, we must fill in the
8605 value now. This can happen if we have a .word which is not
8606 resolved when it appears but is later defined. We also need
8607 to fill in the value if this is an embedded PIC switch table
8610 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8611 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8616 /* If we are deleting this reloc entry, we must fill in the
8618 assert (fixP
->fx_size
== 2);
8620 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8624 case BFD_RELOC_LO16
:
8625 /* When handling an embedded PIC switch statement, we can wind
8626 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8629 if (value
< -0x8000 || value
> 0x7fff)
8630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8631 "relocation overflow");
8632 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8633 if (target_big_endian
)
8635 md_number_to_chars (buf
, value
, 2);
8639 case BFD_RELOC_16_PCREL_S2
:
8641 * We need to save the bits in the instruction since fixup_segment()
8642 * might be deleting the relocation entry (i.e., a branch within
8643 * the current segment).
8645 if ((value
& 0x3) != 0)
8646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8647 "Branch to odd address (%lx)", value
);
8650 /* update old instruction data */
8651 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8652 if (target_big_endian
)
8653 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8655 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8657 if (value
>= -0x8000 && value
< 0x8000)
8658 insn
|= value
& 0xffff;
8661 /* The branch offset is too large. If this is an
8662 unconditional branch, and we are not generating PIC code,
8663 we can convert it to an absolute jump instruction. */
8664 if (mips_pic
== NO_PIC
8666 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8667 && (fixP
->fx_frag
->fr_address
8668 < text_section
->vma
+ text_section
->_raw_size
)
8669 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8670 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8671 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8673 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8674 insn
= 0x0c000000; /* jal */
8676 insn
= 0x08000000; /* j */
8677 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8679 fixP
->fx_addsy
= section_symbol (text_section
);
8680 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8684 /* FIXME. It would be possible in principle to handle
8685 conditional branches which overflow. They could be
8686 transformed into a branch around a jump. This would
8687 require setting up variant frags for each different
8688 branch type. The native MIPS assembler attempts to
8689 handle these cases, but it appears to do it
8691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8692 "Relocation overflow");
8696 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8711 const struct mips_opcode
*p
;
8712 int treg
, sreg
, dreg
, shamt
;
8717 for (i
= 0; i
< NUMOPCODES
; ++i
)
8719 p
= &mips_opcodes
[i
];
8720 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8722 printf ("%08lx %s\t", oc
, p
->name
);
8723 treg
= (oc
>> 16) & 0x1f;
8724 sreg
= (oc
>> 21) & 0x1f;
8725 dreg
= (oc
>> 11) & 0x1f;
8726 shamt
= (oc
>> 6) & 0x1f;
8728 for (args
= p
->args
;; ++args
)
8739 printf ("%c", *args
);
8743 assert (treg
== sreg
);
8744 printf ("$%d,$%d", treg
, sreg
);
8749 printf ("$%d", dreg
);
8754 printf ("$%d", treg
);
8758 printf ("0x%x", treg
);
8763 printf ("$%d", sreg
);
8767 printf ("0x%08lx", oc
& 0x1ffffff);
8779 printf ("$%d", shamt
);
8790 printf ("%08lx UNDEFINED\n", oc
);
8801 name
= input_line_pointer
;
8802 c
= get_symbol_end ();
8803 p
= (symbolS
*) symbol_find_or_make (name
);
8804 *input_line_pointer
= c
;
8808 /* Align the current frag to a given power of two. The MIPS assembler
8809 also automatically adjusts any preceding label. */
8812 mips_align (to
, fill
, label
)
8817 mips_emit_delays (false);
8818 frag_align (to
, fill
);
8819 record_alignment (now_seg
, to
);
8822 assert (S_GET_SEGMENT (label
) == now_seg
);
8823 label
->sy_frag
= frag_now
;
8824 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8828 /* Align to a given power of two. .align 0 turns off the automatic
8829 alignment used by the data creating pseudo-ops. */
8836 register long temp_fill
;
8837 long max_alignment
= 15;
8841 o Note that the assembler pulls down any immediately preceeding label
8842 to the aligned address.
8843 o It's not documented but auto alignment is reinstated by
8844 a .align pseudo instruction.
8845 o Note also that after auto alignment is turned off the mips assembler
8846 issues an error on attempt to assemble an improperly aligned data item.
8851 temp
= get_absolute_expression ();
8852 if (temp
> max_alignment
)
8853 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8856 as_warn ("Alignment negative: 0 assumed.");
8859 if (*input_line_pointer
== ',')
8861 input_line_pointer
++;
8862 temp_fill
= get_absolute_expression ();
8869 mips_align (temp
, (int) temp_fill
,
8870 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8877 demand_empty_rest_of_line ();
8881 mips_flush_pending_output ()
8883 mips_emit_delays (false);
8884 mips_clear_insn_labels ();
8893 /* When generating embedded PIC code, we only use the .text, .lit8,
8894 .sdata and .sbss sections. We change the .data and .rdata
8895 pseudo-ops to use .sdata. */
8896 if (mips_pic
== EMBEDDED_PIC
8897 && (sec
== 'd' || sec
== 'r'))
8900 mips_emit_delays (false);
8910 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8911 demand_empty_rest_of_line ();
8915 if (USE_GLOBAL_POINTER_OPT
)
8917 seg
= subseg_new (RDATA_SECTION_NAME
,
8918 (subsegT
) get_absolute_expression ());
8919 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8921 bfd_set_section_flags (stdoutput
, seg
,
8927 if (strcmp (TARGET_OS
, "elf") != 0)
8928 bfd_set_section_alignment (stdoutput
, seg
, 4);
8930 demand_empty_rest_of_line ();
8934 as_bad ("No read only data section in this object file format");
8935 demand_empty_rest_of_line ();
8941 if (USE_GLOBAL_POINTER_OPT
)
8943 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8944 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8946 bfd_set_section_flags (stdoutput
, seg
,
8947 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8949 if (strcmp (TARGET_OS
, "elf") != 0)
8950 bfd_set_section_alignment (stdoutput
, seg
, 4);
8952 demand_empty_rest_of_line ();
8957 as_bad ("Global pointers not supported; recompile -G 0");
8958 demand_empty_rest_of_line ();
8967 mips_enable_auto_align ()
8978 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8979 mips_emit_delays (false);
8980 if (log_size
> 0 && auto_align
)
8981 mips_align (log_size
, 0, label
);
8982 mips_clear_insn_labels ();
8983 cons (1 << log_size
);
8992 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8994 mips_emit_delays (false);
8998 mips_align (3, 0, label
);
9000 mips_align (2, 0, label
);
9002 mips_clear_insn_labels ();
9007 /* Handle .globl. We need to override it because on Irix 5 you are
9010 where foo is an undefined symbol, to mean that foo should be
9011 considered to be the address of a function. */
9022 name
= input_line_pointer
;
9023 c
= get_symbol_end ();
9024 symbolP
= symbol_find_or_make (name
);
9025 *input_line_pointer
= c
;
9028 /* On Irix 5, every global symbol that is not explicitly labelled as
9029 being a function is apparently labelled as being an object. */
9032 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9037 secname
= input_line_pointer
;
9038 c
= get_symbol_end ();
9039 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9041 as_bad ("%s: no such section", secname
);
9042 *input_line_pointer
= c
;
9044 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9045 flag
= BSF_FUNCTION
;
9048 symbolP
->bsym
->flags
|= flag
;
9050 S_SET_EXTERNAL (symbolP
);
9051 demand_empty_rest_of_line ();
9061 opt
= input_line_pointer
;
9062 c
= get_symbol_end ();
9066 /* FIXME: What does this mean? */
9068 else if (strncmp (opt
, "pic", 3) == 0)
9076 mips_pic
= SVR4_PIC
;
9078 as_bad (".option pic%d not supported", i
);
9080 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9082 if (g_switch_seen
&& g_switch_value
!= 0)
9083 as_warn ("-G may not be used with SVR4 PIC code");
9085 bfd_set_gp_size (stdoutput
, 0);
9089 as_warn ("Unrecognized option \"%s\"", opt
);
9091 *input_line_pointer
= c
;
9092 demand_empty_rest_of_line ();
9099 char *name
= input_line_pointer
, ch
;
9101 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9102 input_line_pointer
++;
9103 ch
= *input_line_pointer
;
9104 *input_line_pointer
= '\0';
9106 if (strcmp (name
, "reorder") == 0)
9108 if (mips_noreorder
&& prev_nop_frag
!= NULL
)
9110 /* If we still have pending nops, we can discard them. The
9111 usual nop handling will insert any that are still
9113 prev_nop_frag
->fr_fix
-= prev_nop_frag_holds
* (mips16
? 2 : 4);
9114 prev_nop_frag
= NULL
;
9118 else if (strcmp (name
, "noreorder") == 0)
9120 mips_emit_delays (true);
9122 mips_any_noreorder
= 1;
9124 else if (strcmp (name
, "at") == 0)
9128 else if (strcmp (name
, "noat") == 0)
9132 else if (strcmp (name
, "macro") == 0)
9134 mips_warn_about_macros
= 0;
9136 else if (strcmp (name
, "nomacro") == 0)
9138 if (mips_noreorder
== 0)
9139 as_bad ("`noreorder' must be set before `nomacro'");
9140 mips_warn_about_macros
= 1;
9142 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9146 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9150 else if (strcmp (name
, "bopt") == 0)
9154 else if (strcmp (name
, "nobopt") == 0)
9158 else if (strcmp (name
, "mips16") == 0
9159 || strcmp (name
, "MIPS-16") == 0)
9161 else if (strcmp (name
, "nomips16") == 0
9162 || strcmp (name
, "noMIPS-16") == 0)
9164 else if (strncmp (name
, "mips", 4) == 0)
9168 /* Permit the user to change the ISA on the fly. Needless to
9169 say, misuse can cause serious problems. */
9170 isa
= atoi (name
+ 4);
9172 mips_isa
= file_mips_isa
;
9173 else if (isa
< 1 || isa
> 4)
9174 as_bad ("unknown ISA level");
9178 else if (strcmp (name
, "autoextend") == 0)
9179 mips16_autoextend
= 1;
9180 else if (strcmp (name
, "noautoextend") == 0)
9181 mips16_autoextend
= 0;
9184 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9186 *input_line_pointer
= ch
;
9187 demand_empty_rest_of_line ();
9190 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9191 .option pic2. It means to generate SVR4 PIC calls. */
9197 mips_pic
= SVR4_PIC
;
9198 if (USE_GLOBAL_POINTER_OPT
)
9200 if (g_switch_seen
&& g_switch_value
!= 0)
9201 as_warn ("-G may not be used with SVR4 PIC code");
9204 bfd_set_gp_size (stdoutput
, 0);
9205 demand_empty_rest_of_line ();
9208 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9209 PIC code. It sets the $gp register for the function based on the
9210 function address, which is in the register named in the argument.
9211 This uses a relocation against _gp_disp, which is handled specially
9212 by the linker. The result is:
9213 lui $gp,%hi(_gp_disp)
9214 addiu $gp,$gp,%lo(_gp_disp)
9215 addu $gp,$gp,.cpload argument
9216 The .cpload argument is normally $25 == $t9. */
9225 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9226 if (mips_pic
!= SVR4_PIC
)
9232 /* .cpload should be a in .set noreorder section. */
9233 if (mips_noreorder
== 0)
9234 as_warn (".cpload not in noreorder section");
9237 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9238 ex
.X_op_symbol
= NULL
;
9239 ex
.X_add_number
= 0;
9241 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9242 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9244 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9245 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9246 (int) BFD_RELOC_LO16
);
9248 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9249 GP
, GP
, tc_get_register (0));
9251 demand_empty_rest_of_line ();
9254 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9255 offset from $sp. The offset is remembered, and after making a PIC
9256 call $gp is restored from that location. */
9259 s_cprestore (ignore
)
9265 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9266 if (mips_pic
!= SVR4_PIC
)
9272 mips_cprestore_offset
= get_absolute_expression ();
9274 ex
.X_op
= O_constant
;
9275 ex
.X_add_symbol
= NULL
;
9276 ex
.X_op_symbol
= NULL
;
9277 ex
.X_add_number
= mips_cprestore_offset
;
9279 macro_build ((char *) NULL
, &icnt
, &ex
,
9280 mips_isa
< 3 ? "sw" : "sd",
9281 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9283 demand_empty_rest_of_line ();
9286 /* Handle the .gpword pseudo-op. This is used when generating PIC
9287 code. It generates a 32 bit GP relative reloc. */
9297 /* When not generating PIC code, this is treated as .word. */
9298 if (mips_pic
!= SVR4_PIC
)
9304 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9305 mips_emit_delays (true);
9307 mips_align (2, 0, label
);
9308 mips_clear_insn_labels ();
9312 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9314 as_bad ("Unsupported use of .gpword");
9315 ignore_rest_of_line ();
9319 md_number_to_chars (p
, (valueT
) 0, 4);
9320 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9321 BFD_RELOC_MIPS_GPREL32
);
9323 demand_empty_rest_of_line ();
9326 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9327 tables in SVR4 PIC code. */
9336 /* This is ignored when not generating SVR4 PIC code. */
9337 if (mips_pic
!= SVR4_PIC
)
9343 /* Add $gp to the register named as an argument. */
9344 reg
= tc_get_register (0);
9345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9346 mips_isa
< 3 ? "addu" : "daddu",
9347 "d,v,t", reg
, reg
, GP
);
9349 demand_empty_rest_of_line ();
9352 /* Handle the .insn pseudo-op. This marks instruction labels in
9353 mips16 mode. This permits the linker to handle them specially,
9354 such as generating jalx instructions when needed. We also make
9355 them odd for the duration of the assembly, in order to generate the
9356 right sort of code. We will make them even in the adjust_symtab
9357 routine, while leaving them marked. This is convenient for the
9358 debugger and the disassembler. The linker knows to make them odd
9367 struct insn_label_list
*l
;
9369 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
9372 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9373 S_SET_OTHER (l
->label
, STO_MIPS16
);
9375 ++l
->label
->sy_value
.X_add_number
;
9378 mips_clear_insn_labels ();
9381 demand_empty_rest_of_line ();
9384 /* Parse a register string into a number. Called from the ECOFF code
9385 to parse .frame. The argument is non-zero if this is the frame
9386 register, so that we can record it in mips_frame_reg. */
9389 tc_get_register (frame
)
9395 if (*input_line_pointer
++ != '$')
9397 as_warn ("expected `$'");
9400 else if (isdigit ((unsigned char) *input_line_pointer
))
9402 reg
= get_absolute_expression ();
9403 if (reg
< 0 || reg
>= 32)
9405 as_warn ("Bad register number");
9411 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9413 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9415 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9417 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9421 as_warn ("Unrecognized register name");
9424 input_line_pointer
+= 2;
9427 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9432 md_section_align (seg
, addr
)
9436 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9439 /* We don't need to align ELF sections to the full alignment.
9440 However, Irix 5 may prefer that we align them at least to a 16
9441 byte boundary. We don't bother to align the sections if we are
9442 targeted for an embedded system. */
9443 if (strcmp (TARGET_OS
, "elf") == 0)
9449 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9452 /* Utility routine, called from above as well. If called while the
9453 input file is still being read, it's only an approximation. (For
9454 example, a symbol may later become defined which appeared to be
9455 undefined earlier.) */
9458 nopic_need_relax (sym
)
9464 if (USE_GLOBAL_POINTER_OPT
)
9466 const char *symname
;
9469 /* Find out whether this symbol can be referenced off the GP
9470 register. It can be if it is smaller than the -G size or if
9471 it is in the .sdata or .sbss section. Certain symbols can
9472 not be referenced off the GP, although it appears as though
9474 symname
= S_GET_NAME (sym
);
9475 if (symname
!= (const char *) NULL
9476 && (strcmp (symname
, "eprol") == 0
9477 || strcmp (symname
, "etext") == 0
9478 || strcmp (symname
, "_gp") == 0
9479 || strcmp (symname
, "edata") == 0
9480 || strcmp (symname
, "_fbss") == 0
9481 || strcmp (symname
, "_fdata") == 0
9482 || strcmp (symname
, "_ftext") == 0
9483 || strcmp (symname
, "end") == 0
9484 || strcmp (symname
, "_gp_disp") == 0))
9486 else if (! S_IS_DEFINED (sym
)
9488 #ifndef NO_ECOFF_DEBUGGING
9489 || (sym
->ecoff_extern_size
!= 0
9490 && sym
->ecoff_extern_size
<= g_switch_value
)
9492 || (S_GET_VALUE (sym
) != 0
9493 && S_GET_VALUE (sym
) <= g_switch_value
)))
9497 const char *segname
;
9499 segname
= segment_name (S_GET_SEGMENT (sym
));
9500 assert (strcmp (segname
, ".lit8") != 0
9501 && strcmp (segname
, ".lit4") != 0);
9502 change
= (strcmp (segname
, ".sdata") != 0
9503 && strcmp (segname
, ".sbss") != 0);
9508 /* We are not optimizing for the GP register. */
9512 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9513 extended opcode. SEC is the section the frag is in. */
9516 mips16_extended_frag (fragp
, sec
, stretch
)
9522 register const struct mips16_immed_operand
*op
;
9524 int mintiny
, maxtiny
;
9527 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9529 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9532 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9533 op
= mips16_immed_operands
;
9534 while (op
->type
!= type
)
9537 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9542 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9545 maxtiny
= 1 << op
->nbits
;
9550 maxtiny
= (1 << op
->nbits
) - 1;
9555 mintiny
= - (1 << (op
->nbits
- 1));
9556 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9559 /* We can't call S_GET_VALUE here, because we don't want to lock in
9560 a particular frag address. */
9561 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9563 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9564 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9565 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9567 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9568 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9571 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9572 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9573 + fragp
->fr_symbol
->sy_value
.X_add_number
9574 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9575 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9584 /* We won't have the section when we are called from
9585 mips_relax_frag. However, we will always have been called
9586 from md_estimate_size_before_relax first. If this is a
9587 branch to a different section, we mark it as such. If SEC is
9588 NULL, and the frag is not marked, then it must be a branch to
9589 the same section. */
9592 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9600 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9602 /* FIXME: We should support this, and let the linker
9603 catch branches and loads that are out of range. */
9604 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9605 "unsupported PC relative reference to different section");
9611 /* In this case, we know for sure that the symbol fragment is in
9612 the same section. If the fr_address of the symbol fragment
9613 is greater then the address of this fragment we want to add
9614 in STRETCH in order to get a better estimate of the address.
9615 This particularly matters because of the shift bits. */
9617 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9621 /* Adjust stretch for any alignment frag. */
9622 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9625 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9628 stretch
= - ((- stretch
)
9629 & ~ ((1 << (int) f
->fr_offset
) - 1));
9631 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9639 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9641 /* The base address rules are complicated. The base address of
9642 a branch is the following instruction. The base address of a
9643 PC relative load or add is the instruction itself, but if it
9644 is in a delay slot (in which case it can not be extended) use
9645 the address of the instruction whose delay slot it is in. */
9646 if (type
== 'p' || type
== 'q')
9650 /* If we are currently assuming that this frag should be
9651 extended, then, the current address is two bytes
9653 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9656 /* Ignore the low bit in the target, since it will be set
9657 for a text label. */
9661 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9663 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9666 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9668 /* Branch offsets have an implicit 0 in the lowest bit. */
9669 if (type
== 'p' || type
== 'q')
9672 /* If any of the shifted bits are set, we must use an extended
9673 opcode. If the address depends on the size of this
9674 instruction, this can lead to a loop, so we arrange to always
9675 use an extended opcode. We only check this when we are in
9676 the main relaxation loop, when SEC is NULL. */
9677 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9680 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9684 /* If we are about to mark a frag as extended because the value
9685 is precisely maxtiny + 1, then there is a chance of an
9686 infinite loop as in the following code:
9691 In this case when the la is extended, foo is 0x3fc bytes
9692 away, so the la can be shrunk, but then foo is 0x400 away, so
9693 the la must be extended. To avoid this loop, we mark the
9694 frag as extended if it was small, and is about to become
9695 extended with a value of maxtiny + 1. */
9696 if (val
== ((maxtiny
+ 1) << op
->shift
)
9697 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9701 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9705 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9706 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9708 if ((val
& ((1 << op
->shift
) - 1)) != 0
9709 || val
< (mintiny
<< op
->shift
)
9710 || val
> (maxtiny
<< op
->shift
))
9716 /* Estimate the size of a frag before relaxing. Unless this is the
9717 mips16, we are not really relaxing here, and the final size is
9718 encoded in the subtype information. For the mips16, we have to
9719 decide whether we are using an extended opcode or not. */
9723 md_estimate_size_before_relax (fragp
, segtype
)
9729 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9731 if (mips16_extended_frag (fragp
, segtype
, 0))
9733 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9738 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9743 if (mips_pic
== NO_PIC
)
9745 change
= nopic_need_relax (fragp
->fr_symbol
);
9747 else if (mips_pic
== SVR4_PIC
)
9749 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9751 /* This must duplicate the test in adjust_reloc_syms. */
9752 change
= (symsec
!= &bfd_und_section
9753 && symsec
!= &bfd_abs_section
9754 && ! bfd_is_com_section (symsec
));
9761 /* Record the offset to the first reloc in the fr_opcode field.
9762 This lets md_convert_frag and tc_gen_reloc know that the code
9763 must be expanded. */
9764 fragp
->fr_opcode
= (fragp
->fr_literal
9766 - RELAX_OLD (fragp
->fr_subtype
)
9767 + RELAX_RELOC1 (fragp
->fr_subtype
));
9768 /* FIXME: This really needs as_warn_where. */
9769 if (RELAX_WARN (fragp
->fr_subtype
))
9770 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9776 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9779 /* This is called to see whether a reloc against a defined symbol
9780 should be converted into a reloc against a section. Don't adjust
9781 MIPS16 jump relocations, so we don't have to worry about the format
9782 of the offset in the .o file. Don't adjust relocations against
9783 mips16 symbols, so that the linker can find them if it needs to set
9787 mips_fix_adjustable (fixp
)
9790 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9792 if (fixp
->fx_addsy
== NULL
)
9795 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9796 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9802 /* Translate internal representation of relocation info to BFD target
9806 tc_gen_reloc (section
, fixp
)
9810 static arelent
*retval
[4];
9812 bfd_reloc_code_real_type code
;
9814 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9817 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9818 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9820 if (mips_pic
== EMBEDDED_PIC
9821 && SWITCH_TABLE (fixp
))
9823 /* For a switch table entry we use a special reloc. The addend
9824 is actually the difference between the reloc address and the
9826 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9827 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9828 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9829 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9831 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9833 /* We use a special addend for an internal RELLO reloc. */
9834 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9835 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9837 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9839 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9841 assert (fixp
->fx_next
!= NULL
9842 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9843 /* We use a special addend for an internal RELHI reloc. The
9844 reloc is relative to the RELLO; adjust the addend
9846 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9847 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9848 + fixp
->fx_next
->fx_where
9849 - S_GET_VALUE (fixp
->fx_subsy
));
9851 reloc
->addend
= (fixp
->fx_addnumber
9852 + fixp
->fx_next
->fx_frag
->fr_address
9853 + fixp
->fx_next
->fx_where
);
9855 else if (fixp
->fx_pcrel
== 0)
9856 reloc
->addend
= fixp
->fx_addnumber
;
9859 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9860 /* A gruesome hack which is a result of the gruesome gas reloc
9862 reloc
->addend
= reloc
->address
;
9864 reloc
->addend
= -reloc
->address
;
9867 /* If this is a variant frag, we may need to adjust the existing
9868 reloc and generate a new one. */
9869 if (fixp
->fx_frag
->fr_opcode
!= NULL
9870 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9871 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9872 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9873 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9874 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9875 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9876 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9880 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9882 /* If this is not the last reloc in this frag, then we have two
9883 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9884 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9885 the second one handle all of them. */
9886 if (fixp
->fx_next
!= NULL
9887 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9889 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9890 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9891 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9892 && (fixp
->fx_next
->fx_r_type
9893 == BFD_RELOC_MIPS_GOT_LO16
))
9894 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9895 && (fixp
->fx_next
->fx_r_type
9896 == BFD_RELOC_MIPS_CALL_LO16
)));
9901 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9902 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9903 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9905 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9906 reloc2
->address
= (reloc
->address
9907 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9908 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9909 reloc2
->addend
= fixp
->fx_addnumber
;
9910 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9911 assert (reloc2
->howto
!= NULL
);
9913 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9917 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9920 reloc3
->address
+= 4;
9923 if (mips_pic
== NO_PIC
)
9925 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9926 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9928 else if (mips_pic
== SVR4_PIC
)
9930 switch (fixp
->fx_r_type
)
9934 case BFD_RELOC_MIPS_GOT16
:
9936 case BFD_RELOC_MIPS_CALL16
:
9937 case BFD_RELOC_MIPS_GOT_LO16
:
9938 case BFD_RELOC_MIPS_CALL_LO16
:
9939 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9947 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9948 fixup_segment converted a non-PC relative reloc into a PC
9949 relative reloc. In such a case, we need to convert the reloc
9951 code
= fixp
->fx_r_type
;
9957 code
= BFD_RELOC_8_PCREL
;
9960 code
= BFD_RELOC_16_PCREL
;
9963 code
= BFD_RELOC_32_PCREL
;
9966 code
= BFD_RELOC_64_PCREL
;
9968 case BFD_RELOC_8_PCREL
:
9969 case BFD_RELOC_16_PCREL
:
9970 case BFD_RELOC_32_PCREL
:
9971 case BFD_RELOC_64_PCREL
:
9972 case BFD_RELOC_16_PCREL_S2
:
9973 case BFD_RELOC_PCREL_HI16_S
:
9974 case BFD_RELOC_PCREL_LO16
:
9977 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9978 "Cannot make %s relocation PC relative",
9979 bfd_get_reloc_code_name (code
));
9983 /* To support a PC relative reloc when generating embedded PIC code
9984 for ECOFF, we use a Cygnus extension. We check for that here to
9985 make sure that we don't let such a reloc escape normally. */
9986 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9987 && code
== BFD_RELOC_16_PCREL_S2
9988 && mips_pic
!= EMBEDDED_PIC
)
9989 reloc
->howto
= NULL
;
9991 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9993 if (reloc
->howto
== NULL
)
9995 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9996 "Can not represent %s relocation in this object file format",
9997 bfd_get_reloc_code_name (code
));
10004 /* Relax a machine dependent frag. This returns the amount by which
10005 the current size of the frag should change. */
10008 mips_relax_frag (fragp
, stretch
)
10012 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10015 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10017 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10019 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10024 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10026 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10033 /* Convert a machine dependent frag. */
10036 md_convert_frag (abfd
, asec
, fragp
)
10044 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10047 register const struct mips16_immed_operand
*op
;
10048 boolean small
, ext
;
10051 unsigned long insn
;
10052 boolean use_extend
;
10053 unsigned short extend
;
10055 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10056 op
= mips16_immed_operands
;
10057 while (op
->type
!= type
)
10060 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10071 resolve_symbol_value (fragp
->fr_symbol
);
10072 val
= S_GET_VALUE (fragp
->fr_symbol
);
10077 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10079 /* The rules for the base address of a PC relative reloc are
10080 complicated; see mips16_extended_frag. */
10081 if (type
== 'p' || type
== 'q')
10086 /* Ignore the low bit in the target, since it will be
10087 set for a text label. */
10088 if ((val
& 1) != 0)
10091 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10093 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10096 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10099 /* Make sure the section winds up with the alignment we have
10102 record_alignment (asec
, op
->shift
);
10106 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10107 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10108 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10109 "extended instruction in delay slot");
10111 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10113 if (target_big_endian
)
10114 insn
= bfd_getb16 (buf
);
10116 insn
= bfd_getl16 (buf
);
10118 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10119 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10120 small
, ext
, &insn
, &use_extend
, &extend
);
10124 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10125 fragp
->fr_fix
+= 2;
10129 md_number_to_chars (buf
, insn
, 2);
10130 fragp
->fr_fix
+= 2;
10135 if (fragp
->fr_opcode
== NULL
)
10138 old
= RELAX_OLD (fragp
->fr_subtype
);
10139 new = RELAX_NEW (fragp
->fr_subtype
);
10140 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10143 memcpy (fixptr
- old
, fixptr
, new);
10145 fragp
->fr_fix
+= new - old
;
10151 /* This function is called after the relocs have been generated.
10152 We've been storing mips16 text labels as odd. Here we convert them
10153 back to even for the convenience of the debugger. */
10156 mips_frob_file_after_relocs ()
10159 unsigned int count
, i
;
10161 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10164 syms
= bfd_get_outsymbols (stdoutput
);
10165 count
= bfd_get_symcount (stdoutput
);
10166 for (i
= 0; i
< count
; i
++, syms
++)
10168 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10169 && ((*syms
)->value
& 1) != 0)
10171 (*syms
)->value
&= ~1;
10172 /* If the symbol has an odd size, it was probably computed
10173 incorrectly, so adjust that as well. */
10174 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10175 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10182 /* This function is called whenever a label is defined. It is used
10183 when handling branch delays; if a branch has a label, we assume we
10184 can not move it. */
10187 mips_define_label (sym
)
10190 struct insn_label_list
*l
;
10192 if (free_insn_labels
== NULL
)
10193 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10196 l
= free_insn_labels
;
10197 free_insn_labels
= l
->next
;
10201 l
->next
= insn_labels
;
10205 /* Decide whether a label is local. This is called by LOCAL_LABEL.
10206 In order to work with gcc when using mips-tfile, we must keep all
10207 local labels. However, in other cases, we want to discard them,
10208 since they are useless. */
10211 mips_local_label (name
)
10214 #ifndef NO_ECOFF_DEBUGGING
10215 if (ECOFF_DEBUGGING
10217 && ! ecoff_debugging_seen
)
10219 /* We were called with -g, but we didn't see any debugging
10220 information. That may mean that gcc is smuggling debugging
10221 information through to mips-tfile, in which case we must
10222 generate all local labels. */
10227 /* Here it's OK to discard local labels. */
10229 return name
[0] == '$';
10232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10234 /* Some special processing for a MIPS ELF file. */
10237 mips_elf_final_processing ()
10239 /* Write out the register information. */
10244 s
.ri_gprmask
= mips_gprmask
;
10245 s
.ri_cprmask
[0] = mips_cprmask
[0];
10246 s
.ri_cprmask
[1] = mips_cprmask
[1];
10247 s
.ri_cprmask
[2] = mips_cprmask
[2];
10248 s
.ri_cprmask
[3] = mips_cprmask
[3];
10249 /* The gp_value field is set by the MIPS ELF backend. */
10251 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10252 ((Elf32_External_RegInfo
*)
10253 mips_regmask_frag
));
10257 Elf64_Internal_RegInfo s
;
10259 s
.ri_gprmask
= mips_gprmask
;
10261 s
.ri_cprmask
[0] = mips_cprmask
[0];
10262 s
.ri_cprmask
[1] = mips_cprmask
[1];
10263 s
.ri_cprmask
[2] = mips_cprmask
[2];
10264 s
.ri_cprmask
[3] = mips_cprmask
[3];
10265 /* The gp_value field is set by the MIPS ELF backend. */
10267 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10268 ((Elf64_External_RegInfo
*)
10269 mips_regmask_frag
));
10272 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10273 sort of BFD interface for this. */
10274 if (mips_any_noreorder
)
10275 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10276 if (mips_pic
!= NO_PIC
)
10277 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10280 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10282 /* These functions should really be defined by the object file format,
10283 since they are related to debugging information. However, this
10284 code has to work for the a.out format, which does not define them,
10285 so we provide simple versions here. These don't actually generate
10286 any debugging information, but they do simple checking and someday
10287 somebody may make them useful. */
10291 struct loc
*loc_next
;
10292 unsigned long loc_fileno
;
10293 unsigned long loc_lineno
;
10294 unsigned long loc_offset
;
10295 unsigned short loc_delta
;
10296 unsigned short loc_count
;
10303 typedef struct proc
10305 struct proc
*proc_next
;
10306 struct symbol
*proc_isym
;
10307 struct symbol
*proc_end
;
10308 unsigned long proc_reg_mask
;
10309 unsigned long proc_reg_offset
;
10310 unsigned long proc_fpreg_mask
;
10311 unsigned long proc_fpreg_offset
;
10312 unsigned long proc_frameoffset
;
10313 unsigned long proc_framereg
;
10314 unsigned long proc_pcreg
;
10316 struct file
*proc_file
;
10321 typedef struct file
10323 struct file
*file_next
;
10324 unsigned long file_fileno
;
10325 struct symbol
*file_symbol
;
10326 struct symbol
*file_end
;
10327 struct proc
*file_proc
;
10332 static struct obstack proc_frags
;
10333 static procS
*proc_lastP
;
10334 static procS
*proc_rootP
;
10335 static int numprocs
;
10340 obstack_begin (&proc_frags
, 0x2000);
10346 /* check for premature end, nesting errors, etc */
10347 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10348 as_warn ("missing `.end' at end of assembly");
10357 if (*input_line_pointer
== '-')
10359 ++input_line_pointer
;
10362 if (!isdigit (*input_line_pointer
))
10363 as_bad ("Expected simple number.");
10364 if (input_line_pointer
[0] == '0')
10366 if (input_line_pointer
[1] == 'x')
10368 input_line_pointer
+= 2;
10369 while (isxdigit (*input_line_pointer
))
10372 val
|= hex_value (*input_line_pointer
++);
10374 return negative
? -val
: val
;
10378 ++input_line_pointer
;
10379 while (isdigit (*input_line_pointer
))
10382 val
|= *input_line_pointer
++ - '0';
10384 return negative
? -val
: val
;
10387 if (!isdigit (*input_line_pointer
))
10389 printf (" *input_line_pointer == '%c' 0x%02x\n",
10390 *input_line_pointer
, *input_line_pointer
);
10391 as_warn ("Invalid number");
10394 while (isdigit (*input_line_pointer
))
10397 val
+= *input_line_pointer
++ - '0';
10399 return negative
? -val
: val
;
10402 /* The .file directive; just like the usual .file directive, but there
10403 is an initial number which is the ECOFF file index. */
10411 line
= get_number ();
10416 /* The .end directive. */
10424 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10427 demand_empty_rest_of_line ();
10431 if (now_seg
!= text_section
)
10432 as_warn (".end not in text section");
10435 as_warn (".end and no .ent seen yet.");
10441 assert (S_GET_NAME (p
));
10442 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10443 as_warn (".end symbol does not match .ent symbol.");
10446 proc_lastP
->proc_end
= (symbolS
*) 1;
10449 /* The .aent and .ent directives. */
10459 symbolP
= get_symbol ();
10460 if (*input_line_pointer
== ',')
10461 input_line_pointer
++;
10462 SKIP_WHITESPACE ();
10463 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10464 number
= get_number ();
10465 if (now_seg
!= text_section
)
10466 as_warn (".ent or .aent not in text section.");
10468 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10469 as_warn ("missing `.end'");
10473 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10474 procP
->proc_isym
= symbolP
;
10475 procP
->proc_reg_mask
= 0;
10476 procP
->proc_reg_offset
= 0;
10477 procP
->proc_fpreg_mask
= 0;
10478 procP
->proc_fpreg_offset
= 0;
10479 procP
->proc_frameoffset
= 0;
10480 procP
->proc_framereg
= 0;
10481 procP
->proc_pcreg
= 0;
10482 procP
->proc_end
= NULL
;
10483 procP
->proc_next
= NULL
;
10485 proc_lastP
->proc_next
= procP
;
10487 proc_rootP
= procP
;
10488 proc_lastP
= procP
;
10491 demand_empty_rest_of_line ();
10494 /* The .frame directive. */
10507 frame_reg
= tc_get_register (1);
10508 if (*input_line_pointer
== ',')
10509 input_line_pointer
++;
10510 frame_off
= get_absolute_expression ();
10511 if (*input_line_pointer
== ',')
10512 input_line_pointer
++;
10513 pcreg
= tc_get_register (0);
10515 /* bob third eye */
10516 assert (proc_rootP
);
10517 proc_rootP
->proc_framereg
= frame_reg
;
10518 proc_rootP
->proc_frameoffset
= frame_off
;
10519 proc_rootP
->proc_pcreg
= pcreg
;
10520 /* bob macho .frame */
10522 /* We don't have to write out a frame stab for unoptimized code. */
10523 if (!(frame_reg
== FP
&& frame_off
== 0))
10526 as_warn ("No .ent for .frame to use.");
10527 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10528 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10529 S_SET_TYPE (symP
, N_RMASK
);
10530 S_SET_OTHER (symP
, 0);
10531 S_SET_DESC (symP
, 0);
10532 symP
->sy_forward
= proc_lastP
->proc_isym
;
10533 /* bob perhaps I should have used pseudo set */
10535 demand_empty_rest_of_line ();
10539 /* The .fmask and .mask directives. */
10546 char str
[100], *strP
;
10552 mask
= get_number ();
10553 if (*input_line_pointer
== ',')
10554 input_line_pointer
++;
10555 off
= get_absolute_expression ();
10557 /* bob only for coff */
10558 assert (proc_rootP
);
10559 if (reg_type
== 'F')
10561 proc_rootP
->proc_fpreg_mask
= mask
;
10562 proc_rootP
->proc_fpreg_offset
= off
;
10566 proc_rootP
->proc_reg_mask
= mask
;
10567 proc_rootP
->proc_reg_offset
= off
;
10570 /* bob macho .mask + .fmask */
10572 /* We don't have to write out a mask stab if no saved regs. */
10576 as_warn ("No .ent for .mask to use.");
10578 for (i
= 0; i
< 32; i
++)
10582 sprintf (strP
, "%c%d,", reg_type
, i
);
10583 strP
+= strlen (strP
);
10587 sprintf (strP
, ";%d,", off
);
10588 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10589 S_SET_TYPE (symP
, N_RMASK
);
10590 S_SET_OTHER (symP
, 0);
10591 S_SET_DESC (symP
, 0);
10592 symP
->sy_forward
= proc_lastP
->proc_isym
;
10593 /* bob perhaps I should have used pseudo set */
10598 /* The .loc directive. */
10609 assert (now_seg
== text_section
);
10611 lineno
= get_number ();
10612 addroff
= frag_now_fix ();
10614 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10615 S_SET_TYPE (symbolP
, N_SLINE
);
10616 S_SET_OTHER (symbolP
, 0);
10617 S_SET_DESC (symbolP
, lineno
);
10618 symbolP
->sy_segment
= now_seg
;