1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* The maximum number of NOPs needed to satisfy a hardware hazard
561 or processor errata. */
564 /* A list of previous instructions, with index 0 being the most recent.
565 We need to look back MAX_NOPS instructions when filling delay slots
566 or working around processor errata. We need to look back one
567 instruction further if we're thinking about using history[0] to
568 fill a branch delay slot. */
569 static struct mips_cl_insn history
[1 + MAX_NOPS
];
571 /* Nop instructions used by emit_nop. */
572 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
574 /* The appropriate nop for the current mode. */
575 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
577 /* If this is set, it points to a frag holding nop instructions which
578 were inserted before the start of a noreorder section. If those
579 nops turn out to be unnecessary, the size of the frag can be
581 static fragS
*prev_nop_frag
;
583 /* The number of nop instructions we created in prev_nop_frag. */
584 static int prev_nop_frag_holds
;
586 /* The number of nop instructions that we know we need in
588 static int prev_nop_frag_required
;
590 /* The number of instructions we've seen since prev_nop_frag. */
591 static int prev_nop_frag_since
;
593 /* For ECOFF and ELF, relocations against symbols are done in two
594 parts, with a HI relocation and a LO relocation. Each relocation
595 has only 16 bits of space to store an addend. This means that in
596 order for the linker to handle carries correctly, it must be able
597 to locate both the HI and the LO relocation. This means that the
598 relocations must appear in order in the relocation table.
600 In order to implement this, we keep track of each unmatched HI
601 relocation. We then sort them so that they immediately precede the
602 corresponding LO relocation. */
607 struct mips_hi_fixup
*next
;
610 /* The section this fixup is in. */
614 /* The list of unmatched HI relocs. */
616 static struct mips_hi_fixup
*mips_hi_fixup_list
;
618 /* The frag containing the last explicit relocation operator.
619 Null if explicit relocations have not been used. */
621 static fragS
*prev_reloc_op_frag
;
623 /* Map normal MIPS register numbers to mips16 register numbers. */
625 #define X ILLEGAL_REG
626 static const int mips32_to_16_reg_map
[] =
628 X
, X
, 2, 3, 4, 5, 6, 7,
629 X
, X
, X
, X
, X
, X
, X
, X
,
630 0, 1, X
, X
, X
, X
, X
, X
,
631 X
, X
, X
, X
, X
, X
, X
, X
635 /* Map mips16 register numbers to normal MIPS register numbers. */
637 static const unsigned int mips16_to_32_reg_map
[] =
639 16, 17, 2, 3, 4, 5, 6, 7
642 /* Classifies the kind of instructions we're interested in when
643 implementing -mfix-vr4120. */
644 enum fix_vr4120_class
{
651 NUM_FIX_VR4120_CLASSES
654 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
655 there must be at least one other instruction between an instruction
656 of type X and an instruction of type Y. */
657 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
659 /* True if -mfix-vr4120 is in force. */
660 static int mips_fix_vr4120
;
662 /* We don't relax branches by default, since this causes us to expand
663 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
664 fail to compute the offset before expanding the macro to the most
665 efficient expansion. */
667 static int mips_relax_branch
;
669 /* The expansion of many macros depends on the type of symbol that
670 they refer to. For example, when generating position-dependent code,
671 a macro that refers to a symbol may have two different expansions,
672 one which uses GP-relative addresses and one which uses absolute
673 addresses. When generating SVR4-style PIC, a macro may have
674 different expansions for local and global symbols.
676 We handle these situations by generating both sequences and putting
677 them in variant frags. In position-dependent code, the first sequence
678 will be the GP-relative one and the second sequence will be the
679 absolute one. In SVR4 PIC, the first sequence will be for global
680 symbols and the second will be for local symbols.
682 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
683 SECOND are the lengths of the two sequences in bytes. These fields
684 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
685 the subtype has the following flags:
688 Set if it has been decided that we should use the second
689 sequence instead of the first.
692 Set in the first variant frag if the macro's second implementation
693 is longer than its first. This refers to the macro as a whole,
694 not an individual relaxation.
697 Set in the first variant frag if the macro appeared in a .set nomacro
698 block and if one alternative requires a warning but the other does not.
701 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
704 The frag's "opcode" points to the first fixup for relaxable code.
706 Relaxable macros are generated using a sequence such as:
708 relax_start (SYMBOL);
709 ... generate first expansion ...
711 ... generate second expansion ...
714 The code and fixups for the unwanted alternative are discarded
715 by md_convert_frag. */
716 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
718 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
719 #define RELAX_SECOND(X) ((X) & 0xff)
720 #define RELAX_USE_SECOND 0x10000
721 #define RELAX_SECOND_LONGER 0x20000
722 #define RELAX_NOMACRO 0x40000
723 #define RELAX_DELAY_SLOT 0x80000
725 /* Branch without likely bit. If label is out of range, we turn:
727 beq reg1, reg2, label
737 with the following opcode replacements:
744 bltzal <-> bgezal (with jal label instead of j label)
746 Even though keeping the delay slot instruction in the delay slot of
747 the branch would be more efficient, it would be very tricky to do
748 correctly, because we'd have to introduce a variable frag *after*
749 the delay slot instruction, and expand that instead. Let's do it
750 the easy way for now, even if the branch-not-taken case now costs
751 one additional instruction. Out-of-range branches are not supposed
752 to be common, anyway.
754 Branch likely. If label is out of range, we turn:
756 beql reg1, reg2, label
757 delay slot (annulled if branch not taken)
766 delay slot (executed only if branch taken)
769 It would be possible to generate a shorter sequence by losing the
770 likely bit, generating something like:
775 delay slot (executed only if branch taken)
787 bltzall -> bgezal (with jal label instead of j label)
788 bgezall -> bltzal (ditto)
791 but it's not clear that it would actually improve performance. */
792 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
795 | ((toofar) ? 1 : 0) \
797 | ((likely) ? 4 : 0) \
798 | ((uncond) ? 8 : 0)))
799 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
800 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
801 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
802 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
803 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
805 /* For mips16 code, we use an entirely different form of relaxation.
806 mips16 supports two versions of most instructions which take
807 immediate values: a small one which takes some small value, and a
808 larger one which takes a 16 bit value. Since branches also follow
809 this pattern, relaxing these values is required.
811 We can assemble both mips16 and normal MIPS code in a single
812 object. Therefore, we need to support this type of relaxation at
813 the same time that we support the relaxation described above. We
814 use the high bit of the subtype field to distinguish these cases.
816 The information we store for this type of relaxation is the
817 argument code found in the opcode file for this relocation, whether
818 the user explicitly requested a small or extended form, and whether
819 the relocation is in a jump or jal delay slot. That tells us the
820 size of the value, and how it should be stored. We also store
821 whether the fragment is considered to be extended or not. We also
822 store whether this is known to be a branch to a different section,
823 whether we have tried to relax this frag yet, and whether we have
824 ever extended a PC relative fragment because of a shift count. */
825 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
828 | ((small) ? 0x100 : 0) \
829 | ((ext) ? 0x200 : 0) \
830 | ((dslot) ? 0x400 : 0) \
831 | ((jal_dslot) ? 0x800 : 0))
832 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
833 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
834 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
835 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
836 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
837 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
838 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
839 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
840 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
841 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
842 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
843 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
845 /* Is the given value a sign-extended 32-bit value? */
846 #define IS_SEXT_32BIT_NUM(x) \
847 (((x) &~ (offsetT) 0x7fffffff) == 0 \
848 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
850 /* Is the given value a sign-extended 16-bit value? */
851 #define IS_SEXT_16BIT_NUM(x) \
852 (((x) &~ (offsetT) 0x7fff) == 0 \
853 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
855 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
856 VALUE << SHIFT. VALUE is evaluated exactly once. */
857 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
858 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
859 | (((VALUE) & (MASK)) << (SHIFT)))
861 /* Extract bits MASK << SHIFT from STRUCT and shift them right
863 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
864 (((STRUCT) >> (SHIFT)) & (MASK))
866 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
867 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
869 include/opcode/mips.h specifies operand fields using the macros
870 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
871 with "MIPS16OP" instead of "OP". */
872 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
873 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
874 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
875 INSERT_BITS ((INSN).insn_opcode, VALUE, \
876 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
878 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
879 #define EXTRACT_OPERAND(FIELD, INSN) \
880 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
881 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
882 EXTRACT_BITS ((INSN).insn_opcode, \
883 MIPS16OP_MASK_##FIELD, \
886 /* Global variables used when generating relaxable macros. See the
887 comment above RELAX_ENCODE for more details about how relaxation
890 /* 0 if we're not emitting a relaxable macro.
891 1 if we're emitting the first of the two relaxation alternatives.
892 2 if we're emitting the second alternative. */
895 /* The first relaxable fixup in the current frag. (In other words,
896 the first fixup that refers to relaxable code.) */
899 /* sizes[0] says how many bytes of the first alternative are stored in
900 the current frag. Likewise sizes[1] for the second alternative. */
901 unsigned int sizes
[2];
903 /* The symbol on which the choice of sequence depends. */
907 /* Global variables used to decide whether a macro needs a warning. */
909 /* True if the macro is in a branch delay slot. */
910 bfd_boolean delay_slot_p
;
912 /* For relaxable macros, sizes[0] is the length of the first alternative
913 in bytes and sizes[1] is the length of the second alternative.
914 For non-relaxable macros, both elements give the length of the
916 unsigned int sizes
[2];
918 /* The first variant frag for this macro. */
920 } mips_macro_warning
;
922 /* Prototypes for static functions. */
924 #define internalError() \
925 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
927 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
929 static void append_insn
930 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
931 static void mips_no_prev_insn (int);
932 static void mips16_macro_build
933 (expressionS
*, const char *, const char *, va_list);
934 static void load_register (int, expressionS
*, int);
935 static void macro_start (void);
936 static void macro_end (void);
937 static void macro (struct mips_cl_insn
* ip
);
938 static void mips16_macro (struct mips_cl_insn
* ip
);
939 #ifdef LOSING_COMPILER
940 static void macro2 (struct mips_cl_insn
* ip
);
942 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
943 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
944 static void mips16_immed
945 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
946 unsigned long *, bfd_boolean
*, unsigned short *);
947 static size_t my_getSmallExpression
948 (expressionS
*, bfd_reloc_code_real_type
*, char *);
949 static void my_getExpression (expressionS
*, char *);
950 static void s_align (int);
951 static void s_change_sec (int);
952 static void s_change_section (int);
953 static void s_cons (int);
954 static void s_float_cons (int);
955 static void s_mips_globl (int);
956 static void s_option (int);
957 static void s_mipsset (int);
958 static void s_abicalls (int);
959 static void s_cpload (int);
960 static void s_cpsetup (int);
961 static void s_cplocal (int);
962 static void s_cprestore (int);
963 static void s_cpreturn (int);
964 static void s_gpvalue (int);
965 static void s_gpword (int);
966 static void s_gpdword (int);
967 static void s_cpadd (int);
968 static void s_insn (int);
969 static void md_obj_begin (void);
970 static void md_obj_end (void);
971 static void s_mips_ent (int);
972 static void s_mips_end (int);
973 static void s_mips_frame (int);
974 static void s_mips_mask (int reg_type
);
975 static void s_mips_stab (int);
976 static void s_mips_weakext (int);
977 static void s_mips_file (int);
978 static void s_mips_loc (int);
979 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
980 static int relaxed_branch_length (fragS
*, asection
*, int);
981 static int validate_mips_insn (const struct mips_opcode
*);
983 /* Table and functions used to map between CPU/ISA names, and
984 ISA levels, and CPU numbers. */
988 const char *name
; /* CPU or ISA name. */
989 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
990 int isa
; /* ISA level. */
991 int cpu
; /* CPU number (default CPU if ISA). */
994 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
995 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
996 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1000 The following pseudo-ops from the Kane and Heinrich MIPS book
1001 should be defined here, but are currently unsupported: .alias,
1002 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1004 The following pseudo-ops from the Kane and Heinrich MIPS book are
1005 specific to the type of debugging information being generated, and
1006 should be defined by the object format: .aent, .begin, .bend,
1007 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1010 The following pseudo-ops from the Kane and Heinrich MIPS book are
1011 not MIPS CPU specific, but are also not specific to the object file
1012 format. This file is probably the best place to define them, but
1013 they are not currently supported: .asm0, .endr, .lab, .repeat,
1016 static const pseudo_typeS mips_pseudo_table
[] =
1018 /* MIPS specific pseudo-ops. */
1019 {"option", s_option
, 0},
1020 {"set", s_mipsset
, 0},
1021 {"rdata", s_change_sec
, 'r'},
1022 {"sdata", s_change_sec
, 's'},
1023 {"livereg", s_ignore
, 0},
1024 {"abicalls", s_abicalls
, 0},
1025 {"cpload", s_cpload
, 0},
1026 {"cpsetup", s_cpsetup
, 0},
1027 {"cplocal", s_cplocal
, 0},
1028 {"cprestore", s_cprestore
, 0},
1029 {"cpreturn", s_cpreturn
, 0},
1030 {"gpvalue", s_gpvalue
, 0},
1031 {"gpword", s_gpword
, 0},
1032 {"gpdword", s_gpdword
, 0},
1033 {"cpadd", s_cpadd
, 0},
1034 {"insn", s_insn
, 0},
1036 /* Relatively generic pseudo-ops that happen to be used on MIPS
1038 {"asciiz", stringer
, 1},
1039 {"bss", s_change_sec
, 'b'},
1041 {"half", s_cons
, 1},
1042 {"dword", s_cons
, 3},
1043 {"weakext", s_mips_weakext
, 0},
1045 /* These pseudo-ops are defined in read.c, but must be overridden
1046 here for one reason or another. */
1047 {"align", s_align
, 0},
1048 {"byte", s_cons
, 0},
1049 {"data", s_change_sec
, 'd'},
1050 {"double", s_float_cons
, 'd'},
1051 {"float", s_float_cons
, 'f'},
1052 {"globl", s_mips_globl
, 0},
1053 {"global", s_mips_globl
, 0},
1054 {"hword", s_cons
, 1},
1056 {"long", s_cons
, 2},
1057 {"octa", s_cons
, 4},
1058 {"quad", s_cons
, 3},
1059 {"section", s_change_section
, 0},
1060 {"short", s_cons
, 1},
1061 {"single", s_float_cons
, 'f'},
1062 {"stabn", s_mips_stab
, 'n'},
1063 {"text", s_change_sec
, 't'},
1064 {"word", s_cons
, 2},
1066 { "extern", ecoff_directive_extern
, 0},
1071 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1073 /* These pseudo-ops should be defined by the object file format.
1074 However, a.out doesn't support them, so we have versions here. */
1075 {"aent", s_mips_ent
, 1},
1076 {"bgnb", s_ignore
, 0},
1077 {"end", s_mips_end
, 0},
1078 {"endb", s_ignore
, 0},
1079 {"ent", s_mips_ent
, 0},
1080 {"file", s_mips_file
, 0},
1081 {"fmask", s_mips_mask
, 'F'},
1082 {"frame", s_mips_frame
, 0},
1083 {"loc", s_mips_loc
, 0},
1084 {"mask", s_mips_mask
, 'R'},
1085 {"verstamp", s_ignore
, 0},
1089 extern void pop_insert (const pseudo_typeS
*);
1092 mips_pop_insert (void)
1094 pop_insert (mips_pseudo_table
);
1095 if (! ECOFF_DEBUGGING
)
1096 pop_insert (mips_nonecoff_pseudo_table
);
1099 /* Symbols labelling the current insn. */
1101 struct insn_label_list
1103 struct insn_label_list
*next
;
1107 static struct insn_label_list
*insn_labels
;
1108 static struct insn_label_list
*free_insn_labels
;
1110 static void mips_clear_insn_labels (void);
1113 mips_clear_insn_labels (void)
1115 register struct insn_label_list
**pl
;
1117 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1123 static char *expr_end
;
1125 /* Expressions which appear in instructions. These are set by
1128 static expressionS imm_expr
;
1129 static expressionS imm2_expr
;
1130 static expressionS offset_expr
;
1132 /* Relocs associated with imm_expr and offset_expr. */
1134 static bfd_reloc_code_real_type imm_reloc
[3]
1135 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1136 static bfd_reloc_code_real_type offset_reloc
[3]
1137 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1139 /* These are set by mips16_ip if an explicit extension is used. */
1141 static bfd_boolean mips16_small
, mips16_ext
;
1144 /* The pdr segment for per procedure frame/regmask info. Not used for
1147 static segT pdr_seg
;
1150 /* The default target format to use. */
1153 mips_target_format (void)
1155 switch (OUTPUT_FLAVOR
)
1157 case bfd_target_ecoff_flavour
:
1158 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1159 case bfd_target_coff_flavour
:
1161 case bfd_target_elf_flavour
:
1163 /* This is traditional mips. */
1164 return (target_big_endian
1165 ? (HAVE_64BIT_OBJECTS
1166 ? "elf64-tradbigmips"
1168 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1169 : (HAVE_64BIT_OBJECTS
1170 ? "elf64-tradlittlemips"
1172 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1174 return (target_big_endian
1175 ? (HAVE_64BIT_OBJECTS
1178 ? "elf32-nbigmips" : "elf32-bigmips"))
1179 : (HAVE_64BIT_OBJECTS
1180 ? "elf64-littlemips"
1182 ? "elf32-nlittlemips" : "elf32-littlemips")));
1190 /* Return the length of instruction INSN. */
1192 static inline unsigned int
1193 insn_length (const struct mips_cl_insn
*insn
)
1195 if (!mips_opts
.mips16
)
1197 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1200 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1203 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1208 insn
->use_extend
= FALSE
;
1210 insn
->insn_opcode
= mo
->match
;
1213 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1214 insn
->fixp
[i
] = NULL
;
1215 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1216 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1217 insn
->mips16_absolute_jump_p
= 0;
1220 /* Install INSN at the location specified by its "frag" and "where" fields. */
1223 install_insn (const struct mips_cl_insn
*insn
)
1225 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1226 if (!mips_opts
.mips16
)
1227 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1228 else if (insn
->mips16_absolute_jump_p
)
1230 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1231 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1235 if (insn
->use_extend
)
1237 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1240 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1244 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1245 and install the opcode in the new location. */
1248 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1253 insn
->where
= where
;
1254 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1255 if (insn
->fixp
[i
] != NULL
)
1257 insn
->fixp
[i
]->fx_frag
= frag
;
1258 insn
->fixp
[i
]->fx_where
= where
;
1260 install_insn (insn
);
1263 /* Add INSN to the end of the output. */
1266 add_fixed_insn (struct mips_cl_insn
*insn
)
1268 char *f
= frag_more (insn_length (insn
));
1269 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1272 /* Start a variant frag and move INSN to the start of the variant part,
1273 marking it as fixed. The other arguments are as for frag_var. */
1276 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1277 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1279 frag_grow (max_chars
);
1280 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1282 frag_var (rs_machine_dependent
, max_chars
, var
,
1283 subtype
, symbol
, offset
, NULL
);
1286 /* Insert N copies of INSN into the history buffer, starting at
1287 position FIRST. Neither FIRST nor N need to be clipped. */
1290 insert_into_history (unsigned int first
, unsigned int n
,
1291 const struct mips_cl_insn
*insn
)
1293 if (mips_relax
.sequence
!= 2)
1297 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1299 history
[i
] = history
[i
- n
];
1305 /* Emit a nop instruction, recording it in the history buffer. */
1310 add_fixed_insn (NOP_INSN
);
1311 insert_into_history (0, 1, NOP_INSN
);
1314 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1315 the idea is to make it obvious at a glance that each errata is
1319 init_vr4120_conflicts (void)
1321 #define CONFLICT(FIRST, SECOND) \
1322 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1324 /* Errata 21 - [D]DIV[U] after [D]MACC */
1325 CONFLICT (MACC
, DIV
);
1326 CONFLICT (DMACC
, DIV
);
1328 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1329 CONFLICT (DMULT
, DMULT
);
1330 CONFLICT (DMULT
, DMACC
);
1331 CONFLICT (DMACC
, DMULT
);
1332 CONFLICT (DMACC
, DMACC
);
1334 /* Errata 24 - MT{LO,HI} after [D]MACC */
1335 CONFLICT (MACC
, MTHILO
);
1336 CONFLICT (DMACC
, MTHILO
);
1338 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1339 instruction is executed immediately after a MACC or DMACC
1340 instruction, the result of [either instruction] is incorrect." */
1341 CONFLICT (MACC
, MULT
);
1342 CONFLICT (MACC
, DMULT
);
1343 CONFLICT (DMACC
, MULT
);
1344 CONFLICT (DMACC
, DMULT
);
1346 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1347 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1348 DDIV or DDIVU instruction, the result of the MACC or
1349 DMACC instruction is incorrect.". */
1350 CONFLICT (DMULT
, MACC
);
1351 CONFLICT (DMULT
, DMACC
);
1352 CONFLICT (DIV
, MACC
);
1353 CONFLICT (DIV
, DMACC
);
1358 /* This function is called once, at assembler startup time. It should
1359 set up all the tables, etc. that the MD part of the assembler will need. */
1364 register const char *retval
= NULL
;
1368 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1369 as_warn (_("Could not set architecture and machine"));
1371 op_hash
= hash_new ();
1373 for (i
= 0; i
< NUMOPCODES
;)
1375 const char *name
= mips_opcodes
[i
].name
;
1377 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1380 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1381 mips_opcodes
[i
].name
, retval
);
1382 /* Probably a memory allocation problem? Give up now. */
1383 as_fatal (_("Broken assembler. No assembly attempted."));
1387 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1389 if (!validate_mips_insn (&mips_opcodes
[i
]))
1391 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1393 create_insn (&nop_insn
, mips_opcodes
+ i
);
1394 nop_insn
.fixed_p
= 1;
1399 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1402 mips16_op_hash
= hash_new ();
1405 while (i
< bfd_mips16_num_opcodes
)
1407 const char *name
= mips16_opcodes
[i
].name
;
1409 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1411 as_fatal (_("internal: can't hash `%s': %s"),
1412 mips16_opcodes
[i
].name
, retval
);
1415 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1416 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1417 != mips16_opcodes
[i
].match
))
1419 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1420 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1423 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1425 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1426 mips16_nop_insn
.fixed_p
= 1;
1430 while (i
< bfd_mips16_num_opcodes
1431 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1435 as_fatal (_("Broken assembler. No assembly attempted."));
1437 /* We add all the general register names to the symbol table. This
1438 helps us detect invalid uses of them. */
1439 for (i
= 0; i
< 32; i
++)
1443 sprintf (buf
, "$%d", i
);
1444 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1445 &zero_address_frag
));
1447 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1448 &zero_address_frag
));
1449 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1450 &zero_address_frag
));
1451 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1452 &zero_address_frag
));
1453 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1454 &zero_address_frag
));
1455 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1456 &zero_address_frag
));
1457 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1458 &zero_address_frag
));
1459 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1460 &zero_address_frag
));
1461 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1462 &zero_address_frag
));
1463 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1464 &zero_address_frag
));
1466 /* If we don't add these register names to the symbol table, they
1467 may end up being added as regular symbols by operand(), and then
1468 make it to the object file as undefined in case they're not
1469 regarded as local symbols. They're local in o32, since `$' is a
1470 local symbol prefix, but not in n32 or n64. */
1471 for (i
= 0; i
< 8; i
++)
1475 sprintf (buf
, "$fcc%i", i
);
1476 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1477 &zero_address_frag
));
1480 mips_no_prev_insn (FALSE
);
1483 mips_cprmask
[0] = 0;
1484 mips_cprmask
[1] = 0;
1485 mips_cprmask
[2] = 0;
1486 mips_cprmask
[3] = 0;
1488 /* set the default alignment for the text section (2**2) */
1489 record_alignment (text_section
, 2);
1491 bfd_set_gp_size (stdoutput
, g_switch_value
);
1493 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1495 /* On a native system, sections must be aligned to 16 byte
1496 boundaries. When configured for an embedded ELF target, we
1498 if (strcmp (TARGET_OS
, "elf") != 0)
1500 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1501 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1502 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1505 /* Create a .reginfo section for register masks and a .mdebug
1506 section for debugging information. */
1514 subseg
= now_subseg
;
1516 /* The ABI says this section should be loaded so that the
1517 running program can access it. However, we don't load it
1518 if we are configured for an embedded target */
1519 flags
= SEC_READONLY
| SEC_DATA
;
1520 if (strcmp (TARGET_OS
, "elf") != 0)
1521 flags
|= SEC_ALLOC
| SEC_LOAD
;
1523 if (mips_abi
!= N64_ABI
)
1525 sec
= subseg_new (".reginfo", (subsegT
) 0);
1527 bfd_set_section_flags (stdoutput
, sec
, flags
);
1528 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1531 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1536 /* The 64-bit ABI uses a .MIPS.options section rather than
1537 .reginfo section. */
1538 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1539 bfd_set_section_flags (stdoutput
, sec
, flags
);
1540 bfd_set_section_alignment (stdoutput
, sec
, 3);
1543 /* Set up the option header. */
1545 Elf_Internal_Options opthdr
;
1548 opthdr
.kind
= ODK_REGINFO
;
1549 opthdr
.size
= (sizeof (Elf_External_Options
)
1550 + sizeof (Elf64_External_RegInfo
));
1553 f
= frag_more (sizeof (Elf_External_Options
));
1554 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1555 (Elf_External_Options
*) f
);
1557 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1562 if (ECOFF_DEBUGGING
)
1564 sec
= subseg_new (".mdebug", (subsegT
) 0);
1565 (void) bfd_set_section_flags (stdoutput
, sec
,
1566 SEC_HAS_CONTENTS
| SEC_READONLY
);
1567 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1570 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1572 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1573 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1574 SEC_READONLY
| SEC_RELOC
1576 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1580 subseg_set (seg
, subseg
);
1584 if (! ECOFF_DEBUGGING
)
1587 if (mips_fix_vr4120
)
1588 init_vr4120_conflicts ();
1594 if (! ECOFF_DEBUGGING
)
1599 md_assemble (char *str
)
1601 struct mips_cl_insn insn
;
1602 bfd_reloc_code_real_type unused_reloc
[3]
1603 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1605 imm_expr
.X_op
= O_absent
;
1606 imm2_expr
.X_op
= O_absent
;
1607 offset_expr
.X_op
= O_absent
;
1608 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1609 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1610 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1611 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1612 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1613 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1615 if (mips_opts
.mips16
)
1616 mips16_ip (str
, &insn
);
1619 mips_ip (str
, &insn
);
1620 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1621 str
, insn
.insn_opcode
));
1626 as_bad ("%s `%s'", insn_error
, str
);
1630 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1633 if (mips_opts
.mips16
)
1634 mips16_macro (&insn
);
1641 if (imm_expr
.X_op
!= O_absent
)
1642 append_insn (&insn
, &imm_expr
, imm_reloc
);
1643 else if (offset_expr
.X_op
!= O_absent
)
1644 append_insn (&insn
, &offset_expr
, offset_reloc
);
1646 append_insn (&insn
, NULL
, unused_reloc
);
1650 /* Return true if the given relocation might need a matching %lo().
1651 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1652 applied to local symbols. */
1654 static inline bfd_boolean
1655 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1657 return (HAVE_IN_PLACE_ADDENDS
1658 && (reloc
== BFD_RELOC_HI16_S
1659 || reloc
== BFD_RELOC_MIPS_GOT16
1660 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1663 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1666 static inline bfd_boolean
1667 fixup_has_matching_lo_p (fixS
*fixp
)
1669 return (fixp
->fx_next
!= NULL
1670 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1671 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1672 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1673 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1676 /* See whether instruction IP reads register REG. CLASS is the type
1680 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1681 enum mips_regclass
class)
1683 if (class == MIPS16_REG
)
1685 assert (mips_opts
.mips16
);
1686 reg
= mips16_to_32_reg_map
[reg
];
1687 class = MIPS_GR_REG
;
1690 /* Don't report on general register ZERO, since it never changes. */
1691 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1694 if (class == MIPS_FP_REG
)
1696 assert (! mips_opts
.mips16
);
1697 /* If we are called with either $f0 or $f1, we must check $f0.
1698 This is not optimal, because it will introduce an unnecessary
1699 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1700 need to distinguish reading both $f0 and $f1 or just one of
1701 them. Note that we don't have to check the other way,
1702 because there is no instruction that sets both $f0 and $f1
1703 and requires a delay. */
1704 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1705 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1706 == (reg
&~ (unsigned) 1)))
1708 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1709 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1710 == (reg
&~ (unsigned) 1)))
1713 else if (! mips_opts
.mips16
)
1715 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1716 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1718 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1719 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1724 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1725 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1727 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1728 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1730 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1731 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1734 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1736 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1738 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1740 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1741 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1748 /* This function returns true if modifying a register requires a
1752 reg_needs_delay (unsigned int reg
)
1754 unsigned long prev_pinfo
;
1756 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1757 if (! mips_opts
.noreorder
1758 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1759 && ! gpr_interlocks
)
1760 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1761 && ! cop_interlocks
)))
1763 /* A load from a coprocessor or from memory. All load delays
1764 delay the use of general register rt for one instruction. */
1765 /* Itbl support may require additional care here. */
1766 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1767 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1774 /* Move all labels in insn_labels to the current insertion point. */
1777 mips_move_labels (void)
1779 struct insn_label_list
*l
;
1782 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1784 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1785 symbol_set_frag (l
->label
, frag_now
);
1786 val
= (valueT
) frag_now_fix ();
1787 /* mips16 text labels are stored as odd. */
1788 if (mips_opts
.mips16
)
1790 S_SET_VALUE (l
->label
, val
);
1794 /* Mark instruction labels in mips16 mode. This permits the linker to
1795 handle them specially, such as generating jalx instructions when
1796 needed. We also make them odd for the duration of the assembly, in
1797 order to generate the right sort of code. We will make them even
1798 in the adjust_symtab routine, while leaving them marked. This is
1799 convenient for the debugger and the disassembler. The linker knows
1800 to make them odd again. */
1803 mips16_mark_labels (void)
1805 if (mips_opts
.mips16
)
1807 struct insn_label_list
*l
;
1810 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1813 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1814 S_SET_OTHER (l
->label
, STO_MIPS16
);
1816 val
= S_GET_VALUE (l
->label
);
1818 S_SET_VALUE (l
->label
, val
+ 1);
1823 /* End the current frag. Make it a variant frag and record the
1827 relax_close_frag (void)
1829 mips_macro_warning
.first_frag
= frag_now
;
1830 frag_var (rs_machine_dependent
, 0, 0,
1831 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1832 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1834 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1835 mips_relax
.first_fixup
= 0;
1838 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1839 See the comment above RELAX_ENCODE for more details. */
1842 relax_start (symbolS
*symbol
)
1844 assert (mips_relax
.sequence
== 0);
1845 mips_relax
.sequence
= 1;
1846 mips_relax
.symbol
= symbol
;
1849 /* Start generating the second version of a relaxable sequence.
1850 See the comment above RELAX_ENCODE for more details. */
1855 assert (mips_relax
.sequence
== 1);
1856 mips_relax
.sequence
= 2;
1859 /* End the current relaxable sequence. */
1864 assert (mips_relax
.sequence
== 2);
1865 relax_close_frag ();
1866 mips_relax
.sequence
= 0;
1869 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1870 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1871 by VR4120 errata. */
1874 classify_vr4120_insn (const char *name
)
1876 if (strncmp (name
, "macc", 4) == 0)
1877 return FIX_VR4120_MACC
;
1878 if (strncmp (name
, "dmacc", 5) == 0)
1879 return FIX_VR4120_DMACC
;
1880 if (strncmp (name
, "mult", 4) == 0)
1881 return FIX_VR4120_MULT
;
1882 if (strncmp (name
, "dmult", 5) == 0)
1883 return FIX_VR4120_DMULT
;
1884 if (strstr (name
, "div"))
1885 return FIX_VR4120_DIV
;
1886 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1887 return FIX_VR4120_MTHILO
;
1888 return NUM_FIX_VR4120_CLASSES
;
1891 /* Return the number of instructions that must separate INSN1 and INSN2,
1892 where INSN1 is the earlier instruction. Return the worst-case value
1893 for any INSN2 if INSN2 is null. */
1896 insns_between (const struct mips_cl_insn
*insn1
,
1897 const struct mips_cl_insn
*insn2
)
1899 unsigned long pinfo1
, pinfo2
;
1901 /* This function needs to know which pinfo flags are set for INSN2
1902 and which registers INSN2 uses. The former is stored in PINFO2 and
1903 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1904 will have every flag set and INSN2_USES_REG will always return true. */
1905 pinfo1
= insn1
->insn_mo
->pinfo
;
1906 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1908 #define INSN2_USES_REG(REG, CLASS) \
1909 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1911 /* For most targets, write-after-read dependencies on the HI and LO
1912 registers must be separated by at least two instructions. */
1913 if (!hilo_interlocks
)
1915 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1917 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1921 /* If we're working around r7000 errata, there must be two instructions
1922 between an mfhi or mflo and any instruction that uses the result. */
1923 if (mips_7000_hilo_fix
1924 && MF_HILO_INSN (pinfo1
)
1925 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1928 /* If working around VR4120 errata, check for combinations that need
1929 a single intervening instruction. */
1930 if (mips_fix_vr4120
)
1932 unsigned int class1
, class2
;
1934 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1935 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1939 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1940 if (vr4120_conflicts
[class1
] & (1 << class2
))
1945 if (!mips_opts
.mips16
)
1947 /* Check for GPR or coprocessor load delays. All such delays
1948 are on the RT register. */
1949 /* Itbl support may require additional care here. */
1950 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1951 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
1953 know (pinfo1
& INSN_WRITE_GPR_T
);
1954 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
1958 /* Check for generic coprocessor hazards.
1960 This case is not handled very well. There is no special
1961 knowledge of CP0 handling, and the coprocessors other than
1962 the floating point unit are not distinguished at all. */
1963 /* Itbl support may require additional care here. FIXME!
1964 Need to modify this to include knowledge about
1965 user specified delays! */
1966 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
1967 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
1969 /* Handle cases where INSN1 writes to a known general coprocessor
1970 register. There must be a one instruction delay before INSN2
1971 if INSN2 reads that register, otherwise no delay is needed. */
1972 if (pinfo1
& INSN_WRITE_FPR_T
)
1974 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
1977 else if (pinfo1
& INSN_WRITE_FPR_S
)
1979 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
1984 /* Read-after-write dependencies on the control registers
1985 require a two-instruction gap. */
1986 if ((pinfo1
& INSN_WRITE_COND_CODE
)
1987 && (pinfo2
& INSN_READ_COND_CODE
))
1990 /* We don't know exactly what INSN1 does. If INSN2 is
1991 also a coprocessor instruction, assume there must be
1992 a one instruction gap. */
1993 if (pinfo2
& INSN_COP
)
1998 /* Check for read-after-write dependencies on the coprocessor
1999 control registers in cases where INSN1 does not need a general
2000 coprocessor delay. This means that INSN1 is a floating point
2001 comparison instruction. */
2002 /* Itbl support may require additional care here. */
2003 else if (!cop_interlocks
2004 && (pinfo1
& INSN_WRITE_COND_CODE
)
2005 && (pinfo2
& INSN_READ_COND_CODE
))
2009 #undef INSN2_USES_REG
2014 /* Return the number of nops that would be needed if instruction INSN
2015 immediately followed the MAX_NOPS instructions given by HISTORY,
2016 where HISTORY[0] is the most recent instruction. If INSN is null,
2017 return the worse-case number of nops for any instruction. */
2020 nops_for_insn (const struct mips_cl_insn
*history
,
2021 const struct mips_cl_insn
*insn
)
2023 int i
, nops
, tmp_nops
;
2026 for (i
= 0; i
< MAX_NOPS
; i
++)
2027 if (!history
[i
].noreorder_p
)
2029 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2030 if (tmp_nops
> nops
)
2036 /* The variable arguments provide NUM_INSNS extra instructions that
2037 might be added to HISTORY. Return the largest number of nops that
2038 would be needed after the extended sequence. */
2041 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2044 struct mips_cl_insn buffer
[MAX_NOPS
];
2045 struct mips_cl_insn
*cursor
;
2048 va_start (args
, history
);
2049 cursor
= buffer
+ num_insns
;
2050 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2051 while (cursor
> buffer
)
2052 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2054 nops
= nops_for_insn (buffer
, NULL
);
2059 /* Like nops_for_insn, but if INSN is a branch, take into account the
2060 worst-case delay for the branch target. */
2063 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2064 const struct mips_cl_insn
*insn
)
2068 nops
= nops_for_insn (history
, insn
);
2069 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2070 | INSN_COND_BRANCH_DELAY
2071 | INSN_COND_BRANCH_LIKELY
))
2073 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2074 if (tmp_nops
> nops
)
2077 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2079 tmp_nops
= nops_for_sequence (1, history
, insn
);
2080 if (tmp_nops
> nops
)
2086 /* Output an instruction. IP is the instruction information.
2087 ADDRESS_EXPR is an operand of the instruction to be used with
2091 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2092 bfd_reloc_code_real_type
*reloc_type
)
2094 register unsigned long prev_pinfo
, pinfo
;
2095 relax_stateT prev_insn_frag_type
= 0;
2096 bfd_boolean relaxed_branch
= FALSE
;
2098 /* Mark instruction labels in mips16 mode. */
2099 mips16_mark_labels ();
2101 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2102 pinfo
= ip
->insn_mo
->pinfo
;
2104 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2106 /* There are a lot of optimizations we could do that we don't.
2107 In particular, we do not, in general, reorder instructions.
2108 If you use gcc with optimization, it will reorder
2109 instructions and generally do much more optimization then we
2110 do here; repeating all that work in the assembler would only
2111 benefit hand written assembly code, and does not seem worth
2113 int nops
= (mips_optimize
== 0
2114 ? nops_for_insn (history
, NULL
)
2115 : nops_for_insn_or_target (history
, ip
));
2119 unsigned long old_frag_offset
;
2122 old_frag
= frag_now
;
2123 old_frag_offset
= frag_now_fix ();
2125 for (i
= 0; i
< nops
; i
++)
2130 listing_prev_line ();
2131 /* We may be at the start of a variant frag. In case we
2132 are, make sure there is enough space for the frag
2133 after the frags created by listing_prev_line. The
2134 argument to frag_grow here must be at least as large
2135 as the argument to all other calls to frag_grow in
2136 this file. We don't have to worry about being in the
2137 middle of a variant frag, because the variants insert
2138 all needed nop instructions themselves. */
2142 mips_move_labels ();
2144 #ifndef NO_ECOFF_DEBUGGING
2145 if (ECOFF_DEBUGGING
)
2146 ecoff_fix_loc (old_frag
, old_frag_offset
);
2150 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2152 /* Work out how many nops in prev_nop_frag are needed by IP. */
2153 int nops
= nops_for_insn_or_target (history
, ip
);
2154 assert (nops
<= prev_nop_frag_holds
);
2156 /* Enforce NOPS as a minimum. */
2157 if (nops
> prev_nop_frag_required
)
2158 prev_nop_frag_required
= nops
;
2160 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2162 /* Settle for the current number of nops. Update the history
2163 accordingly (for the benefit of any future .set reorder code). */
2164 prev_nop_frag
= NULL
;
2165 insert_into_history (prev_nop_frag_since
,
2166 prev_nop_frag_holds
, NOP_INSN
);
2170 /* Allow this instruction to replace one of the nops that was
2171 tentatively added to prev_nop_frag. */
2172 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2173 prev_nop_frag_holds
--;
2174 prev_nop_frag_since
++;
2179 /* The value passed to dwarf2_emit_insn is the distance between
2180 the beginning of the current instruction and the address that
2181 should be recorded in the debug tables. For MIPS16 debug info
2182 we want to use ISA-encoded addresses, so we pass -1 for an
2183 address higher by one than the current. */
2184 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2187 /* Record the frag type before frag_var. */
2188 if (history
[0].frag
)
2189 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2192 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2193 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2194 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2195 && mips_relax_branch
2196 /* Don't try branch relaxation within .set nomacro, or within
2197 .set noat if we use $at for PIC computations. If it turns
2198 out that the branch was out-of-range, we'll get an error. */
2199 && !mips_opts
.warn_about_macros
2200 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2201 && !mips_opts
.mips16
)
2203 relaxed_branch
= TRUE
;
2204 add_relaxed_insn (ip
, (relaxed_branch_length
2206 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2207 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2210 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2211 pinfo
& INSN_COND_BRANCH_LIKELY
,
2212 pinfo
& INSN_WRITE_GPR_31
,
2214 address_expr
->X_add_symbol
,
2215 address_expr
->X_add_number
);
2216 *reloc_type
= BFD_RELOC_UNUSED
;
2218 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2220 /* We need to set up a variant frag. */
2221 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2222 add_relaxed_insn (ip
, 4, 0,
2224 (*reloc_type
- BFD_RELOC_UNUSED
,
2225 mips16_small
, mips16_ext
,
2226 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2227 history
[0].mips16_absolute_jump_p
),
2228 make_expr_symbol (address_expr
), 0);
2230 else if (mips_opts
.mips16
2232 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2234 /* Make sure there is enough room to swap this instruction with
2235 a following jump instruction. */
2237 add_fixed_insn (ip
);
2241 if (mips_opts
.mips16
2242 && mips_opts
.noreorder
2243 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2244 as_warn (_("extended instruction in delay slot"));
2246 if (mips_relax
.sequence
)
2248 /* If we've reached the end of this frag, turn it into a variant
2249 frag and record the information for the instructions we've
2251 if (frag_room () < 4)
2252 relax_close_frag ();
2253 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2256 if (mips_relax
.sequence
!= 2)
2257 mips_macro_warning
.sizes
[0] += 4;
2258 if (mips_relax
.sequence
!= 1)
2259 mips_macro_warning
.sizes
[1] += 4;
2261 if (mips_opts
.mips16
)
2264 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2266 add_fixed_insn (ip
);
2269 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2271 if (address_expr
->X_op
== O_constant
)
2275 switch (*reloc_type
)
2278 ip
->insn_opcode
|= address_expr
->X_add_number
;
2281 case BFD_RELOC_MIPS_HIGHEST
:
2282 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2283 ip
->insn_opcode
|= tmp
& 0xffff;
2286 case BFD_RELOC_MIPS_HIGHER
:
2287 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2288 ip
->insn_opcode
|= tmp
& 0xffff;
2291 case BFD_RELOC_HI16_S
:
2292 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2293 ip
->insn_opcode
|= tmp
& 0xffff;
2296 case BFD_RELOC_HI16
:
2297 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2300 case BFD_RELOC_UNUSED
:
2301 case BFD_RELOC_LO16
:
2302 case BFD_RELOC_MIPS_GOT_DISP
:
2303 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2306 case BFD_RELOC_MIPS_JMP
:
2307 if ((address_expr
->X_add_number
& 3) != 0)
2308 as_bad (_("jump to misaligned address (0x%lx)"),
2309 (unsigned long) address_expr
->X_add_number
);
2310 if (address_expr
->X_add_number
& ~0xfffffff)
2311 as_bad (_("jump address range overflow (0x%lx)"),
2312 (unsigned long) address_expr
->X_add_number
);
2313 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2316 case BFD_RELOC_MIPS16_JMP
:
2317 if ((address_expr
->X_add_number
& 3) != 0)
2318 as_bad (_("jump to misaligned address (0x%lx)"),
2319 (unsigned long) address_expr
->X_add_number
);
2320 if (address_expr
->X_add_number
& ~0xfffffff)
2321 as_bad (_("jump address range overflow (0x%lx)"),
2322 (unsigned long) address_expr
->X_add_number
);
2324 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2325 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2326 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2329 case BFD_RELOC_16_PCREL_S2
:
2336 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2339 reloc_howto_type
*howto
;
2342 /* In a compound relocation, it is the final (outermost)
2343 operator that determines the relocated field. */
2344 for (i
= 1; i
< 3; i
++)
2345 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2348 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2349 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2350 bfd_get_reloc_size (howto
),
2352 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2355 /* These relocations can have an addend that won't fit in
2356 4 octets for 64bit assembly. */
2358 && ! howto
->partial_inplace
2359 && (reloc_type
[0] == BFD_RELOC_16
2360 || reloc_type
[0] == BFD_RELOC_32
2361 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2362 || reloc_type
[0] == BFD_RELOC_HI16_S
2363 || reloc_type
[0] == BFD_RELOC_LO16
2364 || reloc_type
[0] == BFD_RELOC_GPREL16
2365 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2366 || reloc_type
[0] == BFD_RELOC_GPREL32
2367 || reloc_type
[0] == BFD_RELOC_64
2368 || reloc_type
[0] == BFD_RELOC_CTOR
2369 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2370 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2371 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2372 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2373 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2374 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2375 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2376 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2377 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2378 ip
->fixp
[0]->fx_no_overflow
= 1;
2380 if (mips_relax
.sequence
)
2382 if (mips_relax
.first_fixup
== 0)
2383 mips_relax
.first_fixup
= ip
->fixp
[0];
2385 else if (reloc_needs_lo_p (*reloc_type
))
2387 struct mips_hi_fixup
*hi_fixup
;
2389 /* Reuse the last entry if it already has a matching %lo. */
2390 hi_fixup
= mips_hi_fixup_list
;
2392 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2394 hi_fixup
= ((struct mips_hi_fixup
*)
2395 xmalloc (sizeof (struct mips_hi_fixup
)));
2396 hi_fixup
->next
= mips_hi_fixup_list
;
2397 mips_hi_fixup_list
= hi_fixup
;
2399 hi_fixup
->fixp
= ip
->fixp
[0];
2400 hi_fixup
->seg
= now_seg
;
2403 /* Add fixups for the second and third relocations, if given.
2404 Note that the ABI allows the second relocation to be
2405 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2406 moment we only use RSS_UNDEF, but we could add support
2407 for the others if it ever becomes necessary. */
2408 for (i
= 1; i
< 3; i
++)
2409 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2411 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2412 ip
->fixp
[0]->fx_size
, NULL
, 0,
2413 FALSE
, reloc_type
[i
]);
2415 /* Use fx_tcbit to mark compound relocs. */
2416 ip
->fixp
[0]->fx_tcbit
= 1;
2417 ip
->fixp
[i
]->fx_tcbit
= 1;
2423 /* Update the register mask information. */
2424 if (! mips_opts
.mips16
)
2426 if (pinfo
& INSN_WRITE_GPR_D
)
2427 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2428 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2429 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2430 if (pinfo
& INSN_READ_GPR_S
)
2431 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2432 if (pinfo
& INSN_WRITE_GPR_31
)
2433 mips_gprmask
|= 1 << RA
;
2434 if (pinfo
& INSN_WRITE_FPR_D
)
2435 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2436 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2437 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2438 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2439 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2440 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2441 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2442 if (pinfo
& INSN_COP
)
2444 /* We don't keep enough information to sort these cases out.
2445 The itbl support does keep this information however, although
2446 we currently don't support itbl fprmats as part of the cop
2447 instruction. May want to add this support in the future. */
2449 /* Never set the bit for $0, which is always zero. */
2450 mips_gprmask
&= ~1 << 0;
2454 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2455 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2456 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2457 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2458 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2459 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2460 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2461 mips_gprmask
|= 1 << TREG
;
2462 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2463 mips_gprmask
|= 1 << SP
;
2464 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2465 mips_gprmask
|= 1 << RA
;
2466 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2467 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2468 if (pinfo
& MIPS16_INSN_READ_Z
)
2469 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2470 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2471 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2474 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2476 /* Filling the branch delay slot is more complex. We try to
2477 switch the branch with the previous instruction, which we can
2478 do if the previous instruction does not set up a condition
2479 that the branch tests and if the branch is not itself the
2480 target of any branch. */
2481 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2482 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2484 if (mips_optimize
< 2
2485 /* If we have seen .set volatile or .set nomove, don't
2487 || mips_opts
.nomove
!= 0
2488 /* We can't swap if the previous instruction's position
2490 || history
[0].fixed_p
2491 /* If the previous previous insn was in a .set
2492 noreorder, we can't swap. Actually, the MIPS
2493 assembler will swap in this situation. However, gcc
2494 configured -with-gnu-as will generate code like
2500 in which we can not swap the bne and INSN. If gcc is
2501 not configured -with-gnu-as, it does not output the
2503 || history
[1].noreorder_p
2504 /* If the branch is itself the target of a branch, we
2505 can not swap. We cheat on this; all we check for is
2506 whether there is a label on this instruction. If
2507 there are any branches to anything other than a
2508 label, users must use .set noreorder. */
2509 || insn_labels
!= NULL
2510 /* If the previous instruction is in a variant frag
2511 other than this branch's one, we cannot do the swap.
2512 This does not apply to the mips16, which uses variant
2513 frags for different purposes. */
2514 || (! mips_opts
.mips16
2515 && prev_insn_frag_type
== rs_machine_dependent
)
2516 /* If the branch reads the condition codes, we don't
2517 even try to swap, because in the sequence
2522 we can not swap, and I don't feel like handling that
2524 || (! mips_opts
.mips16
2525 && (pinfo
& INSN_READ_COND_CODE
)
2526 && ! cop_interlocks
)
2527 /* Check for conflicts between the branch and the instructions
2528 before the candidate delay slot. */
2529 || nops_for_insn (history
+ 1, ip
) > 0
2530 /* Check for conflicts between the swapped sequence and the
2531 target of the branch. */
2532 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2533 /* We do not swap with a trap instruction, since it
2534 complicates trap handlers to have the trap
2535 instruction be in a delay slot. */
2536 || (prev_pinfo
& INSN_TRAP
)
2537 /* If the branch reads a register that the previous
2538 instruction sets, we can not swap. */
2539 || (! mips_opts
.mips16
2540 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2541 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2543 || (! mips_opts
.mips16
2544 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2545 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2547 || (mips_opts
.mips16
2548 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2550 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2552 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2554 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2556 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2558 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2560 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2561 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2562 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2563 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2564 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2565 && insn_uses_reg (ip
,
2566 MIPS16OP_EXTRACT_REG32R
2567 (history
[0].insn_opcode
),
2569 /* If the branch writes a register that the previous
2570 instruction sets, we can not swap (we know that
2571 branches write only to RD or to $31). */
2572 || (! mips_opts
.mips16
2573 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2574 && (((pinfo
& INSN_WRITE_GPR_D
)
2575 && (EXTRACT_OPERAND (RT
, history
[0])
2576 == EXTRACT_OPERAND (RD
, *ip
)))
2577 || ((pinfo
& INSN_WRITE_GPR_31
)
2578 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2579 || (! mips_opts
.mips16
2580 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2581 && (((pinfo
& INSN_WRITE_GPR_D
)
2582 && (EXTRACT_OPERAND (RD
, history
[0])
2583 == EXTRACT_OPERAND (RD
, *ip
)))
2584 || ((pinfo
& INSN_WRITE_GPR_31
)
2585 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2586 || (mips_opts
.mips16
2587 && (pinfo
& MIPS16_INSN_WRITE_31
)
2588 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2589 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2590 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2592 /* If the branch writes a register that the previous
2593 instruction reads, we can not swap (we know that
2594 branches only write to RD or to $31). */
2595 || (! mips_opts
.mips16
2596 && (pinfo
& INSN_WRITE_GPR_D
)
2597 && insn_uses_reg (&history
[0],
2598 EXTRACT_OPERAND (RD
, *ip
),
2600 || (! mips_opts
.mips16
2601 && (pinfo
& INSN_WRITE_GPR_31
)
2602 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2603 || (mips_opts
.mips16
2604 && (pinfo
& MIPS16_INSN_WRITE_31
)
2605 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2606 /* If one instruction sets a condition code and the
2607 other one uses a condition code, we can not swap. */
2608 || ((pinfo
& INSN_READ_COND_CODE
)
2609 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2610 || ((pinfo
& INSN_WRITE_COND_CODE
)
2611 && (prev_pinfo
& INSN_READ_COND_CODE
))
2612 /* If the previous instruction uses the PC, we can not
2614 || (mips_opts
.mips16
2615 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2616 /* If the previous instruction had a fixup in mips16
2617 mode, we can not swap. This normally means that the
2618 previous instruction was a 4 byte branch anyhow. */
2619 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2620 /* If the previous instruction is a sync, sync.l, or
2621 sync.p, we can not swap. */
2622 || (prev_pinfo
& INSN_SYNC
))
2624 /* We could do even better for unconditional branches to
2625 portions of this object file; we could pick up the
2626 instruction at the destination, put it in the delay
2627 slot, and bump the destination address. */
2628 insert_into_history (0, 1, ip
);
2630 if (mips_relax
.sequence
)
2631 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2635 /* It looks like we can actually do the swap. */
2636 struct mips_cl_insn delay
= history
[0];
2637 if (mips_opts
.mips16
)
2639 know (delay
.frag
== ip
->frag
);
2640 move_insn (ip
, delay
.frag
, delay
.where
);
2641 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2643 else if (relaxed_branch
)
2645 /* Add the delay slot instruction to the end of the
2646 current frag and shrink the fixed part of the
2647 original frag. If the branch occupies the tail of
2648 the latter, move it backwards to cover the gap. */
2649 delay
.frag
->fr_fix
-= 4;
2650 if (delay
.frag
== ip
->frag
)
2651 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2652 add_fixed_insn (&delay
);
2656 move_insn (&delay
, ip
->frag
, ip
->where
);
2657 move_insn (ip
, history
[0].frag
, history
[0].where
);
2661 insert_into_history (0, 1, &delay
);
2664 /* If that was an unconditional branch, forget the previous
2665 insn information. */
2666 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2667 mips_no_prev_insn (FALSE
);
2669 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2671 /* We don't yet optimize a branch likely. What we should do
2672 is look at the target, copy the instruction found there
2673 into the delay slot, and increment the branch to jump to
2674 the next instruction. */
2675 insert_into_history (0, 1, ip
);
2679 insert_into_history (0, 1, ip
);
2682 insert_into_history (0, 1, ip
);
2684 /* We just output an insn, so the next one doesn't have a label. */
2685 mips_clear_insn_labels ();
2688 /* This function forgets that there was any previous instruction or
2689 label. If PRESERVE is non-zero, it remembers enough information to
2690 know whether nops are needed before a noreorder section. */
2693 mips_no_prev_insn (int preserve
)
2699 prev_nop_frag
= NULL
;
2700 prev_nop_frag_holds
= 0;
2701 prev_nop_frag_required
= 0;
2702 prev_nop_frag_since
= 0;
2703 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2704 history
[i
] = (mips_opts
.mips16
? mips16_nop_insn
: nop_insn
);
2707 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2709 history
[i
].fixed_p
= 1;
2710 history
[i
].noreorder_p
= 0;
2711 history
[i
].mips16_absolute_jump_p
= 0;
2713 mips_clear_insn_labels ();
2716 /* This function must be called whenever we turn on noreorder or emit
2717 something other than instructions. It inserts any NOPS which might
2718 be needed by the previous instruction, and clears the information
2719 kept for the previous instructions. The INSNS parameter is true if
2720 instructions are to follow. */
2723 mips_emit_delays (bfd_boolean insns
)
2725 if (! mips_opts
.noreorder
)
2727 int nops
= nops_for_insn (history
, NULL
);
2730 if (insns
&& mips_optimize
!= 0)
2732 /* Record the frag which holds the nop instructions, so
2733 that we can remove them if we don't need them. */
2734 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2735 prev_nop_frag
= frag_now
;
2736 prev_nop_frag_holds
= nops
;
2737 prev_nop_frag_required
= 0;
2738 prev_nop_frag_since
= 0;
2741 for (; nops
> 0; --nops
)
2742 add_fixed_insn (NOP_INSN
);
2746 /* Move on to a new frag, so that it is safe to simply
2747 decrease the size of prev_nop_frag. */
2748 frag_wane (frag_now
);
2752 mips_move_labels ();
2756 /* Mark instruction labels in mips16 mode. */
2758 mips16_mark_labels ();
2760 mips_no_prev_insn (insns
);
2763 /* Set up global variables for the start of a new macro. */
2768 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2769 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2770 && (history
[0].insn_mo
->pinfo
2771 & (INSN_UNCOND_BRANCH_DELAY
2772 | INSN_COND_BRANCH_DELAY
2773 | INSN_COND_BRANCH_LIKELY
)) != 0);
2776 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2777 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2778 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2781 macro_warning (relax_substateT subtype
)
2783 if (subtype
& RELAX_DELAY_SLOT
)
2784 return _("Macro instruction expanded into multiple instructions"
2785 " in a branch delay slot");
2786 else if (subtype
& RELAX_NOMACRO
)
2787 return _("Macro instruction expanded into multiple instructions");
2792 /* Finish up a macro. Emit warnings as appropriate. */
2797 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2799 relax_substateT subtype
;
2801 /* Set up the relaxation warning flags. */
2803 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2804 subtype
|= RELAX_SECOND_LONGER
;
2805 if (mips_opts
.warn_about_macros
)
2806 subtype
|= RELAX_NOMACRO
;
2807 if (mips_macro_warning
.delay_slot_p
)
2808 subtype
|= RELAX_DELAY_SLOT
;
2810 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2812 /* Either the macro has a single implementation or both
2813 implementations are longer than 4 bytes. Emit the
2815 const char *msg
= macro_warning (subtype
);
2821 /* One implementation might need a warning but the other
2822 definitely doesn't. */
2823 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2828 /* Read a macro's relocation codes from *ARGS and store them in *R.
2829 The first argument in *ARGS will be either the code for a single
2830 relocation or -1 followed by the three codes that make up a
2831 composite relocation. */
2834 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2838 next
= va_arg (*args
, int);
2840 r
[0] = (bfd_reloc_code_real_type
) next
;
2842 for (i
= 0; i
< 3; i
++)
2843 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2846 /* Build an instruction created by a macro expansion. This is passed
2847 a pointer to the count of instructions created so far, an
2848 expression, the name of the instruction to build, an operand format
2849 string, and corresponding arguments. */
2852 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2854 const struct mips_opcode
*mo
;
2855 struct mips_cl_insn insn
;
2856 bfd_reloc_code_real_type r
[3];
2859 va_start (args
, fmt
);
2861 if (mips_opts
.mips16
)
2863 mips16_macro_build (ep
, name
, fmt
, args
);
2868 r
[0] = BFD_RELOC_UNUSED
;
2869 r
[1] = BFD_RELOC_UNUSED
;
2870 r
[2] = BFD_RELOC_UNUSED
;
2871 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2873 assert (strcmp (name
, mo
->name
) == 0);
2875 /* Search until we get a match for NAME. It is assumed here that
2876 macros will never generate MDMX or MIPS-3D instructions. */
2877 while (strcmp (fmt
, mo
->args
) != 0
2878 || mo
->pinfo
== INSN_MACRO
2879 || !OPCODE_IS_MEMBER (mo
,
2881 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2883 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2887 assert (strcmp (name
, mo
->name
) == 0);
2890 create_insn (&insn
, mo
);
2908 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2913 /* Note that in the macro case, these arguments are already
2914 in MSB form. (When handling the instruction in the
2915 non-macro case, these arguments are sizes from which
2916 MSB values must be calculated.) */
2917 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
2923 /* Note that in the macro case, these arguments are already
2924 in MSBD form. (When handling the instruction in the
2925 non-macro case, these arguments are sizes from which
2926 MSBD values must be calculated.) */
2927 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
2938 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
2942 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
2947 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
2953 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
2958 int tmp
= va_arg (args
, int);
2960 INSERT_OPERAND (RT
, insn
, tmp
);
2961 INSERT_OPERAND (RD
, insn
, tmp
);
2967 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
2974 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2978 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
2982 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
2986 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
2990 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
2997 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3003 macro_read_relocs (&args
, r
);
3004 assert (*r
== BFD_RELOC_GPREL16
3005 || *r
== BFD_RELOC_MIPS_LITERAL
3006 || *r
== BFD_RELOC_MIPS_HIGHER
3007 || *r
== BFD_RELOC_HI16_S
3008 || *r
== BFD_RELOC_LO16
3009 || *r
== BFD_RELOC_MIPS_GOT16
3010 || *r
== BFD_RELOC_MIPS_CALL16
3011 || *r
== BFD_RELOC_MIPS_GOT_DISP
3012 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3013 || *r
== BFD_RELOC_MIPS_GOT_OFST
3014 || *r
== BFD_RELOC_MIPS_GOT_LO16
3015 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3019 macro_read_relocs (&args
, r
);
3021 && (ep
->X_op
== O_constant
3022 || (ep
->X_op
== O_symbol
3023 && (*r
== BFD_RELOC_MIPS_HIGHEST
3024 || *r
== BFD_RELOC_HI16_S
3025 || *r
== BFD_RELOC_HI16
3026 || *r
== BFD_RELOC_GPREL16
3027 || *r
== BFD_RELOC_MIPS_GOT_HI16
3028 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3032 assert (ep
!= NULL
);
3034 * This allows macro() to pass an immediate expression for
3035 * creating short branches without creating a symbol.
3036 * Note that the expression still might come from the assembly
3037 * input, in which case the value is not checked for range nor
3038 * is a relocation entry generated (yuck).
3040 if (ep
->X_op
== O_constant
)
3042 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3046 *r
= BFD_RELOC_16_PCREL_S2
;
3050 assert (ep
!= NULL
);
3051 *r
= BFD_RELOC_MIPS_JMP
;
3055 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3064 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3066 append_insn (&insn
, ep
, r
);
3070 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3073 struct mips_opcode
*mo
;
3074 struct mips_cl_insn insn
;
3075 bfd_reloc_code_real_type r
[3]
3076 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3078 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3080 assert (strcmp (name
, mo
->name
) == 0);
3082 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3086 assert (strcmp (name
, mo
->name
) == 0);
3089 create_insn (&insn
, mo
);
3107 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3112 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3116 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3120 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3130 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3137 regno
= va_arg (args
, int);
3138 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3139 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3160 assert (ep
!= NULL
);
3162 if (ep
->X_op
!= O_constant
)
3163 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3166 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3167 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3170 *r
= BFD_RELOC_UNUSED
;
3176 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3183 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3185 append_insn (&insn
, ep
, r
);
3189 * Generate a "jalr" instruction with a relocation hint to the called
3190 * function. This occurs in NewABI PIC code.
3193 macro_build_jalr (expressionS
*ep
)
3202 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3204 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3205 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3209 * Generate a "lui" instruction.
3212 macro_build_lui (expressionS
*ep
, int regnum
)
3214 expressionS high_expr
;
3215 const struct mips_opcode
*mo
;
3216 struct mips_cl_insn insn
;
3217 bfd_reloc_code_real_type r
[3]
3218 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3219 const char *name
= "lui";
3220 const char *fmt
= "t,u";
3222 assert (! mips_opts
.mips16
);
3226 if (high_expr
.X_op
== O_constant
)
3228 /* we can compute the instruction now without a relocation entry */
3229 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3231 *r
= BFD_RELOC_UNUSED
;
3235 assert (ep
->X_op
== O_symbol
);
3236 /* _gp_disp is a special case, used from s_cpload.
3237 __gnu_local_gp is used if mips_no_shared. */
3238 assert (mips_pic
== NO_PIC
3240 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3241 || (! mips_in_shared
3242 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3243 "__gnu_local_gp") == 0));
3244 *r
= BFD_RELOC_HI16_S
;
3247 mo
= hash_find (op_hash
, name
);
3248 assert (strcmp (name
, mo
->name
) == 0);
3249 assert (strcmp (fmt
, mo
->args
) == 0);
3250 create_insn (&insn
, mo
);
3252 insn
.insn_opcode
= insn
.insn_mo
->match
;
3253 INSERT_OPERAND (RT
, insn
, regnum
);
3254 if (*r
== BFD_RELOC_UNUSED
)
3256 insn
.insn_opcode
|= high_expr
.X_add_number
;
3257 append_insn (&insn
, NULL
, r
);
3260 append_insn (&insn
, &high_expr
, r
);
3263 /* Generate a sequence of instructions to do a load or store from a constant
3264 offset off of a base register (breg) into/from a target register (treg),
3265 using AT if necessary. */
3267 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3268 int treg
, int breg
, int dbl
)
3270 assert (ep
->X_op
== O_constant
);
3272 /* Sign-extending 32-bit constants makes their handling easier. */
3273 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3274 == ~((bfd_vma
) 0x7fffffff)))
3276 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3277 as_bad (_("constant too large"));
3279 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3283 /* Right now, this routine can only handle signed 32-bit constants. */
3284 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3285 as_warn (_("operand overflow"));
3287 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3289 /* Signed 16-bit offset will fit in the op. Easy! */
3290 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3294 /* 32-bit offset, need multiple instructions and AT, like:
3295 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3296 addu $tempreg,$tempreg,$breg
3297 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3298 to handle the complete offset. */
3299 macro_build_lui (ep
, AT
);
3300 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3301 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3304 as_bad (_("Macro used $at after \".set noat\""));
3309 * Generates code to set the $at register to true (one)
3310 * if reg is less than the immediate expression.
3313 set_at (int reg
, int unsignedp
)
3315 if (imm_expr
.X_op
== O_constant
3316 && imm_expr
.X_add_number
>= -0x8000
3317 && imm_expr
.X_add_number
< 0x8000)
3318 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3319 AT
, reg
, BFD_RELOC_LO16
);
3322 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3323 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3328 normalize_constant_expr (expressionS
*ex
)
3330 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3331 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3335 /* Warn if an expression is not a constant. */
3338 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3340 if (ex
->X_op
== O_big
)
3341 as_bad (_("unsupported large constant"));
3342 else if (ex
->X_op
!= O_constant
)
3343 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3345 normalize_constant_expr (ex
);
3348 /* Count the leading zeroes by performing a binary chop. This is a
3349 bulky bit of source, but performance is a LOT better for the
3350 majority of values than a simple loop to count the bits:
3351 for (lcnt = 0; (lcnt < 32); lcnt++)
3352 if ((v) & (1 << (31 - lcnt)))
3354 However it is not code size friendly, and the gain will drop a bit
3355 on certain cached systems.
3357 #define COUNT_TOP_ZEROES(v) \
3358 (((v) & ~0xffff) == 0 \
3359 ? ((v) & ~0xff) == 0 \
3360 ? ((v) & ~0xf) == 0 \
3361 ? ((v) & ~0x3) == 0 \
3362 ? ((v) & ~0x1) == 0 \
3367 : ((v) & ~0x7) == 0 \
3370 : ((v) & ~0x3f) == 0 \
3371 ? ((v) & ~0x1f) == 0 \
3374 : ((v) & ~0x7f) == 0 \
3377 : ((v) & ~0xfff) == 0 \
3378 ? ((v) & ~0x3ff) == 0 \
3379 ? ((v) & ~0x1ff) == 0 \
3382 : ((v) & ~0x7ff) == 0 \
3385 : ((v) & ~0x3fff) == 0 \
3386 ? ((v) & ~0x1fff) == 0 \
3389 : ((v) & ~0x7fff) == 0 \
3392 : ((v) & ~0xffffff) == 0 \
3393 ? ((v) & ~0xfffff) == 0 \
3394 ? ((v) & ~0x3ffff) == 0 \
3395 ? ((v) & ~0x1ffff) == 0 \
3398 : ((v) & ~0x7ffff) == 0 \
3401 : ((v) & ~0x3fffff) == 0 \
3402 ? ((v) & ~0x1fffff) == 0 \
3405 : ((v) & ~0x7fffff) == 0 \
3408 : ((v) & ~0xfffffff) == 0 \
3409 ? ((v) & ~0x3ffffff) == 0 \
3410 ? ((v) & ~0x1ffffff) == 0 \
3413 : ((v) & ~0x7ffffff) == 0 \
3416 : ((v) & ~0x3fffffff) == 0 \
3417 ? ((v) & ~0x1fffffff) == 0 \
3420 : ((v) & ~0x7fffffff) == 0 \
3425 * This routine generates the least number of instructions necessary to load
3426 * an absolute expression value into a register.
3429 load_register (int reg
, expressionS
*ep
, int dbl
)
3432 expressionS hi32
, lo32
;
3434 if (ep
->X_op
!= O_big
)
3436 assert (ep
->X_op
== O_constant
);
3438 /* Sign-extending 32-bit constants makes their handling easier. */
3439 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3440 == ~((bfd_vma
) 0x7fffffff)))
3442 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3443 as_bad (_("constant too large"));
3445 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3449 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3451 /* We can handle 16 bit signed values with an addiu to
3452 $zero. No need to ever use daddiu here, since $zero and
3453 the result are always correct in 32 bit mode. */
3454 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3457 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3459 /* We can handle 16 bit unsigned values with an ori to
3461 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3464 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3466 /* 32 bit values require an lui. */
3467 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3468 if ((ep
->X_add_number
& 0xffff) != 0)
3469 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3474 /* The value is larger than 32 bits. */
3476 if (HAVE_32BIT_GPRS
)
3478 as_bad (_("Number (0x%lx) larger than 32 bits"),
3479 (unsigned long) ep
->X_add_number
);
3480 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3484 if (ep
->X_op
!= O_big
)
3487 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3488 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3489 hi32
.X_add_number
&= 0xffffffff;
3491 lo32
.X_add_number
&= 0xffffffff;
3495 assert (ep
->X_add_number
> 2);
3496 if (ep
->X_add_number
== 3)
3497 generic_bignum
[3] = 0;
3498 else if (ep
->X_add_number
> 4)
3499 as_bad (_("Number larger than 64 bits"));
3500 lo32
.X_op
= O_constant
;
3501 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3502 hi32
.X_op
= O_constant
;
3503 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3506 if (hi32
.X_add_number
== 0)
3511 unsigned long hi
, lo
;
3513 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3515 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3517 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3520 if (lo32
.X_add_number
& 0x80000000)
3522 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3523 if (lo32
.X_add_number
& 0xffff)
3524 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3529 /* Check for 16bit shifted constant. We know that hi32 is
3530 non-zero, so start the mask on the first bit of the hi32
3535 unsigned long himask
, lomask
;
3539 himask
= 0xffff >> (32 - shift
);
3540 lomask
= (0xffff << shift
) & 0xffffffff;
3544 himask
= 0xffff << (shift
- 32);
3547 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3548 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3552 tmp
.X_op
= O_constant
;
3554 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3555 | (lo32
.X_add_number
>> shift
));
3557 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3558 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3559 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3560 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3565 while (shift
<= (64 - 16));
3567 /* Find the bit number of the lowest one bit, and store the
3568 shifted value in hi/lo. */
3569 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3570 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3574 while ((lo
& 1) == 0)
3579 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3585 while ((hi
& 1) == 0)
3594 /* Optimize if the shifted value is a (power of 2) - 1. */
3595 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3596 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3598 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3603 /* This instruction will set the register to be all
3605 tmp
.X_op
= O_constant
;
3606 tmp
.X_add_number
= (offsetT
) -1;
3607 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3611 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3612 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3614 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3615 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3620 /* Sign extend hi32 before calling load_register, because we can
3621 generally get better code when we load a sign extended value. */
3622 if ((hi32
.X_add_number
& 0x80000000) != 0)
3623 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3624 load_register (reg
, &hi32
, 0);
3627 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3631 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3639 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3641 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3642 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3648 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3652 mid16
.X_add_number
>>= 16;
3653 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3654 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3657 if ((lo32
.X_add_number
& 0xffff) != 0)
3658 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3662 load_delay_nop (void)
3664 if (!gpr_interlocks
)
3665 macro_build (NULL
, "nop", "");
3668 /* Load an address into a register. */
3671 load_address (int reg
, expressionS
*ep
, int *used_at
)
3673 if (ep
->X_op
!= O_constant
3674 && ep
->X_op
!= O_symbol
)
3676 as_bad (_("expression too complex"));
3677 ep
->X_op
= O_constant
;
3680 if (ep
->X_op
== O_constant
)
3682 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3686 if (mips_pic
== NO_PIC
)
3688 /* If this is a reference to a GP relative symbol, we want
3689 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3691 lui $reg,<sym> (BFD_RELOC_HI16_S)
3692 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3693 If we have an addend, we always use the latter form.
3695 With 64bit address space and a usable $at we want
3696 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3697 lui $at,<sym> (BFD_RELOC_HI16_S)
3698 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3699 daddiu $at,<sym> (BFD_RELOC_LO16)
3703 If $at is already in use, we use a path which is suboptimal
3704 on superscalar processors.
3705 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3706 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3708 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3710 daddiu $reg,<sym> (BFD_RELOC_LO16)
3712 For GP relative symbols in 64bit address space we can use
3713 the same sequence as in 32bit address space. */
3714 if (HAVE_64BIT_SYMBOLS
)
3716 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3717 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3719 relax_start (ep
->X_add_symbol
);
3720 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3721 mips_gp_register
, BFD_RELOC_GPREL16
);
3725 if (*used_at
== 0 && !mips_opts
.noat
)
3727 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3728 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3729 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3730 BFD_RELOC_MIPS_HIGHER
);
3731 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3732 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3733 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3738 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3739 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3740 BFD_RELOC_MIPS_HIGHER
);
3741 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3742 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3743 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3744 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3747 if (mips_relax
.sequence
)
3752 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3753 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3755 relax_start (ep
->X_add_symbol
);
3756 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3757 mips_gp_register
, BFD_RELOC_GPREL16
);
3760 macro_build_lui (ep
, reg
);
3761 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3762 reg
, reg
, BFD_RELOC_LO16
);
3763 if (mips_relax
.sequence
)
3767 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3771 /* If this is a reference to an external symbol, we want
3772 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3774 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3776 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3777 If there is a constant, it must be added in after.
3779 If we have NewABI, we want
3780 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3781 unless we're referencing a global symbol with a non-zero
3782 offset, in which case cst must be added separately. */
3785 if (ep
->X_add_number
)
3787 ex
.X_add_number
= ep
->X_add_number
;
3788 ep
->X_add_number
= 0;
3789 relax_start (ep
->X_add_symbol
);
3790 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3791 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3792 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3793 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3794 ex
.X_op
= O_constant
;
3795 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3796 reg
, reg
, BFD_RELOC_LO16
);
3797 ep
->X_add_number
= ex
.X_add_number
;
3800 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3801 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3802 if (mips_relax
.sequence
)
3807 ex
.X_add_number
= ep
->X_add_number
;
3808 ep
->X_add_number
= 0;
3809 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3810 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3812 relax_start (ep
->X_add_symbol
);
3814 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3818 if (ex
.X_add_number
!= 0)
3820 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3821 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3822 ex
.X_op
= O_constant
;
3823 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3824 reg
, reg
, BFD_RELOC_LO16
);
3828 else if (mips_pic
== SVR4_PIC
)
3832 /* This is the large GOT case. If this is a reference to an
3833 external symbol, we want
3834 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3836 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3838 Otherwise, for a reference to a local symbol in old ABI, we want
3839 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3841 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3842 If there is a constant, it must be added in after.
3844 In the NewABI, for local symbols, with or without offsets, we want:
3845 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3846 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3850 ex
.X_add_number
= ep
->X_add_number
;
3851 ep
->X_add_number
= 0;
3852 relax_start (ep
->X_add_symbol
);
3853 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3854 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3855 reg
, reg
, mips_gp_register
);
3856 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3857 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3858 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3859 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3860 else if (ex
.X_add_number
)
3862 ex
.X_op
= O_constant
;
3863 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3867 ep
->X_add_number
= ex
.X_add_number
;
3869 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3870 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3871 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3872 BFD_RELOC_MIPS_GOT_OFST
);
3877 ex
.X_add_number
= ep
->X_add_number
;
3878 ep
->X_add_number
= 0;
3879 relax_start (ep
->X_add_symbol
);
3880 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3881 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3882 reg
, reg
, mips_gp_register
);
3883 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3884 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3886 if (reg_needs_delay (mips_gp_register
))
3888 /* We need a nop before loading from $gp. This special
3889 check is required because the lui which starts the main
3890 instruction stream does not refer to $gp, and so will not
3891 insert the nop which may be required. */
3892 macro_build (NULL
, "nop", "");
3894 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3895 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3897 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3901 if (ex
.X_add_number
!= 0)
3903 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3904 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3905 ex
.X_op
= O_constant
;
3906 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3914 if (mips_opts
.noat
&& *used_at
== 1)
3915 as_bad (_("Macro used $at after \".set noat\""));
3918 /* Move the contents of register SOURCE into register DEST. */
3921 move_register (int dest
, int source
)
3923 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
3927 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
3928 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
3929 The two alternatives are:
3931 Global symbol Local sybmol
3932 ------------- ------------
3933 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
3935 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
3937 load_got_offset emits the first instruction and add_got_offset
3938 emits the second for a 16-bit offset or add_got_offset_hilo emits
3939 a sequence to add a 32-bit offset using a scratch register. */
3942 load_got_offset (int dest
, expressionS
*local
)
3947 global
.X_add_number
= 0;
3949 relax_start (local
->X_add_symbol
);
3950 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3951 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3953 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
3954 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3959 add_got_offset (int dest
, expressionS
*local
)
3963 global
.X_op
= O_constant
;
3964 global
.X_op_symbol
= NULL
;
3965 global
.X_add_symbol
= NULL
;
3966 global
.X_add_number
= local
->X_add_number
;
3968 relax_start (local
->X_add_symbol
);
3969 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
3970 dest
, dest
, BFD_RELOC_LO16
);
3972 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
3977 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
3980 int hold_mips_optimize
;
3982 global
.X_op
= O_constant
;
3983 global
.X_op_symbol
= NULL
;
3984 global
.X_add_symbol
= NULL
;
3985 global
.X_add_number
= local
->X_add_number
;
3987 relax_start (local
->X_add_symbol
);
3988 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
3990 /* Set mips_optimize around the lui instruction to avoid
3991 inserting an unnecessary nop after the lw. */
3992 hold_mips_optimize
= mips_optimize
;
3994 macro_build_lui (&global
, tmp
);
3995 mips_optimize
= hold_mips_optimize
;
3996 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
3999 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4004 * This routine implements the seemingly endless macro or synthesized
4005 * instructions and addressing modes in the mips assembly language. Many
4006 * of these macros are simple and are similar to each other. These could
4007 * probably be handled by some kind of table or grammar approach instead of
4008 * this verbose method. Others are not simple macros but are more like
4009 * optimizing code generation.
4010 * One interesting optimization is when several store macros appear
4011 * consecutively that would load AT with the upper half of the same address.
4012 * The ensuing load upper instructions are ommited. This implies some kind
4013 * of global optimization. We currently only optimize within a single macro.
4014 * For many of the load and store macros if the address is specified as a
4015 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4016 * first load register 'at' with zero and use it as the base register. The
4017 * mips assembler simply uses register $zero. Just one tiny optimization
4021 macro (struct mips_cl_insn
*ip
)
4023 register int treg
, sreg
, dreg
, breg
;
4039 bfd_reloc_code_real_type r
;
4040 int hold_mips_optimize
;
4042 assert (! mips_opts
.mips16
);
4044 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4045 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4046 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4047 mask
= ip
->insn_mo
->mask
;
4049 expr1
.X_op
= O_constant
;
4050 expr1
.X_op_symbol
= NULL
;
4051 expr1
.X_add_symbol
= NULL
;
4052 expr1
.X_add_number
= 1;
4064 mips_emit_delays (TRUE
);
4065 ++mips_opts
.noreorder
;
4066 mips_any_noreorder
= 1;
4068 expr1
.X_add_number
= 8;
4069 macro_build (&expr1
, "bgez", "s,p", sreg
);
4071 macro_build (NULL
, "nop", "", 0);
4073 move_register (dreg
, sreg
);
4074 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4076 --mips_opts
.noreorder
;
4097 if (imm_expr
.X_op
== O_constant
4098 && imm_expr
.X_add_number
>= -0x8000
4099 && imm_expr
.X_add_number
< 0x8000)
4101 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4105 load_register (AT
, &imm_expr
, dbl
);
4106 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4125 if (imm_expr
.X_op
== O_constant
4126 && imm_expr
.X_add_number
>= 0
4127 && imm_expr
.X_add_number
< 0x10000)
4129 if (mask
!= M_NOR_I
)
4130 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4133 macro_build (&imm_expr
, "ori", "t,r,i",
4134 treg
, sreg
, BFD_RELOC_LO16
);
4135 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4141 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4142 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4159 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4161 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4165 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4166 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4174 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4179 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4183 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4184 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4190 /* check for > max integer */
4191 maxnum
= 0x7fffffff;
4192 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4199 if (imm_expr
.X_op
== O_constant
4200 && imm_expr
.X_add_number
>= maxnum
4201 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4204 /* result is always false */
4206 macro_build (NULL
, "nop", "", 0);
4208 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4211 if (imm_expr
.X_op
!= O_constant
)
4212 as_bad (_("Unsupported large constant"));
4213 ++imm_expr
.X_add_number
;
4217 if (mask
== M_BGEL_I
)
4219 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4221 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4224 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4226 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4229 maxnum
= 0x7fffffff;
4230 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4237 maxnum
= - maxnum
- 1;
4238 if (imm_expr
.X_op
== O_constant
4239 && imm_expr
.X_add_number
<= maxnum
4240 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4243 /* result is always true */
4244 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4245 macro_build (&offset_expr
, "b", "p");
4250 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4260 macro_build (&offset_expr
, likely
? "beql" : "beq",
4265 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4266 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4274 && imm_expr
.X_op
== O_constant
4275 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4277 if (imm_expr
.X_op
!= O_constant
)
4278 as_bad (_("Unsupported large constant"));
4279 ++imm_expr
.X_add_number
;
4283 if (mask
== M_BGEUL_I
)
4285 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4287 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4289 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4295 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4303 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4308 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4312 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4313 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4321 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4328 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4329 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4337 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4342 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4346 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4347 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4353 maxnum
= 0x7fffffff;
4354 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4361 if (imm_expr
.X_op
== O_constant
4362 && imm_expr
.X_add_number
>= maxnum
4363 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4365 if (imm_expr
.X_op
!= O_constant
)
4366 as_bad (_("Unsupported large constant"));
4367 ++imm_expr
.X_add_number
;
4371 if (mask
== M_BLTL_I
)
4373 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4375 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4378 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4380 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4385 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4393 macro_build (&offset_expr
, likely
? "beql" : "beq",
4400 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4401 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4409 && imm_expr
.X_op
== O_constant
4410 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4412 if (imm_expr
.X_op
!= O_constant
)
4413 as_bad (_("Unsupported large constant"));
4414 ++imm_expr
.X_add_number
;
4418 if (mask
== M_BLTUL_I
)
4420 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4422 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4424 macro_build (&offset_expr
, likely
? "beql" : "beq",
4430 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4438 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4443 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4447 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4448 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4458 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4463 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4464 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4472 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4474 as_bad (_("Unsupported large constant"));
4479 pos
= (unsigned long) imm_expr
.X_add_number
;
4480 size
= (unsigned long) imm2_expr
.X_add_number
;
4485 as_bad (_("Improper position (%lu)"), pos
);
4488 if (size
== 0 || size
> 64
4489 || (pos
+ size
- 1) > 63)
4491 as_bad (_("Improper extract size (%lu, position %lu)"),
4496 if (size
<= 32 && pos
< 32)
4501 else if (size
<= 32)
4511 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4520 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4522 as_bad (_("Unsupported large constant"));
4527 pos
= (unsigned long) imm_expr
.X_add_number
;
4528 size
= (unsigned long) imm2_expr
.X_add_number
;
4533 as_bad (_("Improper position (%lu)"), pos
);
4536 if (size
== 0 || size
> 64
4537 || (pos
+ size
- 1) > 63)
4539 as_bad (_("Improper insert size (%lu, position %lu)"),
4544 if (pos
< 32 && (pos
+ size
- 1) < 32)
4559 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4576 as_warn (_("Divide by zero."));
4578 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4580 macro_build (NULL
, "break", "c", 7);
4584 mips_emit_delays (TRUE
);
4585 ++mips_opts
.noreorder
;
4586 mips_any_noreorder
= 1;
4589 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4590 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4594 expr1
.X_add_number
= 8;
4595 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4596 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4597 macro_build (NULL
, "break", "c", 7);
4599 expr1
.X_add_number
= -1;
4601 load_register (AT
, &expr1
, dbl
);
4602 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4603 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4606 expr1
.X_add_number
= 1;
4607 load_register (AT
, &expr1
, dbl
);
4608 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4612 expr1
.X_add_number
= 0x80000000;
4613 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4617 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4618 /* We want to close the noreorder block as soon as possible, so
4619 that later insns are available for delay slot filling. */
4620 --mips_opts
.noreorder
;
4624 expr1
.X_add_number
= 8;
4625 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4626 macro_build (NULL
, "nop", "", 0);
4628 /* We want to close the noreorder block as soon as possible, so
4629 that later insns are available for delay slot filling. */
4630 --mips_opts
.noreorder
;
4632 macro_build (NULL
, "break", "c", 6);
4634 macro_build (NULL
, s
, "d", dreg
);
4673 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4675 as_warn (_("Divide by zero."));
4677 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4679 macro_build (NULL
, "break", "c", 7);
4682 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4684 if (strcmp (s2
, "mflo") == 0)
4685 move_register (dreg
, sreg
);
4687 move_register (dreg
, 0);
4690 if (imm_expr
.X_op
== O_constant
4691 && imm_expr
.X_add_number
== -1
4692 && s
[strlen (s
) - 1] != 'u')
4694 if (strcmp (s2
, "mflo") == 0)
4696 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4699 move_register (dreg
, 0);
4704 load_register (AT
, &imm_expr
, dbl
);
4705 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4706 macro_build (NULL
, s2
, "d", dreg
);
4725 mips_emit_delays (TRUE
);
4726 ++mips_opts
.noreorder
;
4727 mips_any_noreorder
= 1;
4730 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4731 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4732 /* We want to close the noreorder block as soon as possible, so
4733 that later insns are available for delay slot filling. */
4734 --mips_opts
.noreorder
;
4738 expr1
.X_add_number
= 8;
4739 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4740 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4742 /* We want to close the noreorder block as soon as possible, so
4743 that later insns are available for delay slot filling. */
4744 --mips_opts
.noreorder
;
4745 macro_build (NULL
, "break", "c", 7);
4747 macro_build (NULL
, s2
, "d", dreg
);
4759 /* Load the address of a symbol into a register. If breg is not
4760 zero, we then add a base register to it. */
4762 if (dbl
&& HAVE_32BIT_GPRS
)
4763 as_warn (_("dla used to load 32-bit register"));
4765 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4766 as_warn (_("la used to load 64-bit address"));
4768 if (offset_expr
.X_op
== O_constant
4769 && offset_expr
.X_add_number
>= -0x8000
4770 && offset_expr
.X_add_number
< 0x8000)
4772 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4773 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4777 if (!mips_opts
.noat
&& (treg
== breg
))
4787 if (offset_expr
.X_op
!= O_symbol
4788 && offset_expr
.X_op
!= O_constant
)
4790 as_bad (_("expression too complex"));
4791 offset_expr
.X_op
= O_constant
;
4794 if (offset_expr
.X_op
== O_constant
)
4795 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4796 else if (mips_pic
== NO_PIC
)
4798 /* If this is a reference to a GP relative symbol, we want
4799 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4801 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4802 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4803 If we have a constant, we need two instructions anyhow,
4804 so we may as well always use the latter form.
4806 With 64bit address space and a usable $at we want
4807 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4808 lui $at,<sym> (BFD_RELOC_HI16_S)
4809 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4810 daddiu $at,<sym> (BFD_RELOC_LO16)
4812 daddu $tempreg,$tempreg,$at
4814 If $at is already in use, we use a path which is suboptimal
4815 on superscalar processors.
4816 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4817 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4819 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4821 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4823 For GP relative symbols in 64bit address space we can use
4824 the same sequence as in 32bit address space. */
4825 if (HAVE_64BIT_SYMBOLS
)
4827 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4828 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4830 relax_start (offset_expr
.X_add_symbol
);
4831 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4832 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4836 if (used_at
== 0 && !mips_opts
.noat
)
4838 macro_build (&offset_expr
, "lui", "t,u",
4839 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4840 macro_build (&offset_expr
, "lui", "t,u",
4841 AT
, BFD_RELOC_HI16_S
);
4842 macro_build (&offset_expr
, "daddiu", "t,r,j",
4843 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4844 macro_build (&offset_expr
, "daddiu", "t,r,j",
4845 AT
, AT
, BFD_RELOC_LO16
);
4846 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4847 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4852 macro_build (&offset_expr
, "lui", "t,u",
4853 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4854 macro_build (&offset_expr
, "daddiu", "t,r,j",
4855 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4856 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4857 macro_build (&offset_expr
, "daddiu", "t,r,j",
4858 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4859 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4860 macro_build (&offset_expr
, "daddiu", "t,r,j",
4861 tempreg
, tempreg
, BFD_RELOC_LO16
);
4864 if (mips_relax
.sequence
)
4869 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4870 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4872 relax_start (offset_expr
.X_add_symbol
);
4873 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4874 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4877 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4878 as_bad (_("offset too large"));
4879 macro_build_lui (&offset_expr
, tempreg
);
4880 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4881 tempreg
, tempreg
, BFD_RELOC_LO16
);
4882 if (mips_relax
.sequence
)
4886 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4888 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4890 /* If this is a reference to an external symbol, and there
4891 is no constant, we want
4892 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4893 or for lca or if tempreg is PIC_CALL_REG
4894 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4895 For a local symbol, we want
4896 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4898 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4900 If we have a small constant, and this is a reference to
4901 an external symbol, we want
4902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4904 addiu $tempreg,$tempreg,<constant>
4905 For a local symbol, we want the same instruction
4906 sequence, but we output a BFD_RELOC_LO16 reloc on the
4909 If we have a large constant, and this is a reference to
4910 an external symbol, we want
4911 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4912 lui $at,<hiconstant>
4913 addiu $at,$at,<loconstant>
4914 addu $tempreg,$tempreg,$at
4915 For a local symbol, we want the same instruction
4916 sequence, but we output a BFD_RELOC_LO16 reloc on the
4920 if (offset_expr
.X_add_number
== 0)
4922 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
4923 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4925 relax_start (offset_expr
.X_add_symbol
);
4926 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
4927 lw_reloc_type
, mips_gp_register
);
4930 /* We're going to put in an addu instruction using
4931 tempreg, so we may as well insert the nop right
4936 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
4937 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4939 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4940 tempreg
, tempreg
, BFD_RELOC_LO16
);
4942 /* FIXME: If breg == 0, and the next instruction uses
4943 $tempreg, then if this variant case is used an extra
4944 nop will be generated. */
4946 else if (offset_expr
.X_add_number
>= -0x8000
4947 && offset_expr
.X_add_number
< 0x8000)
4949 load_got_offset (tempreg
, &offset_expr
);
4951 add_got_offset (tempreg
, &offset_expr
);
4955 expr1
.X_add_number
= offset_expr
.X_add_number
;
4956 offset_expr
.X_add_number
=
4957 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
4958 load_got_offset (tempreg
, &offset_expr
);
4959 offset_expr
.X_add_number
= expr1
.X_add_number
;
4960 /* If we are going to add in a base register, and the
4961 target register and the base register are the same,
4962 then we are using AT as a temporary register. Since
4963 we want to load the constant into AT, we add our
4964 current AT (from the global offset table) and the
4965 register into the register now, and pretend we were
4966 not using a base register. */
4970 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4975 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
4979 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
4981 int add_breg_early
= 0;
4983 /* If this is a reference to an external, and there is no
4984 constant, or local symbol (*), with or without a
4986 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4987 or for lca or if tempreg is PIC_CALL_REG
4988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4990 If we have a small constant, and this is a reference to
4991 an external symbol, we want
4992 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4993 addiu $tempreg,$tempreg,<constant>
4995 If we have a large constant, and this is a reference to
4996 an external symbol, we want
4997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4998 lui $at,<hiconstant>
4999 addiu $at,$at,<loconstant>
5000 addu $tempreg,$tempreg,$at
5002 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5003 local symbols, even though it introduces an additional
5006 if (offset_expr
.X_add_number
)
5008 expr1
.X_add_number
= offset_expr
.X_add_number
;
5009 offset_expr
.X_add_number
= 0;
5011 relax_start (offset_expr
.X_add_symbol
);
5012 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5013 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5015 if (expr1
.X_add_number
>= -0x8000
5016 && expr1
.X_add_number
< 0x8000)
5018 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5019 tempreg
, tempreg
, BFD_RELOC_LO16
);
5021 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5025 /* If we are going to add in a base register, and the
5026 target register and the base register are the same,
5027 then we are using AT as a temporary register. Since
5028 we want to load the constant into AT, we add our
5029 current AT (from the global offset table) and the
5030 register into the register now, and pretend we were
5031 not using a base register. */
5036 assert (tempreg
== AT
);
5037 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5043 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5044 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5050 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5053 offset_expr
.X_add_number
= expr1
.X_add_number
;
5055 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5056 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5059 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5060 treg
, tempreg
, breg
);
5066 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5068 relax_start (offset_expr
.X_add_symbol
);
5069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5070 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5072 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5073 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5078 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5079 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5082 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5085 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5086 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5087 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5089 /* This is the large GOT case. If this is a reference to an
5090 external symbol, and there is no constant, we want
5091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5092 addu $tempreg,$tempreg,$gp
5093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5094 or for lca or if tempreg is PIC_CALL_REG
5095 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5096 addu $tempreg,$tempreg,$gp
5097 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5098 For a local symbol, we want
5099 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5101 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5103 If we have a small constant, and this is a reference to
5104 an external symbol, we want
5105 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5106 addu $tempreg,$tempreg,$gp
5107 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5109 addiu $tempreg,$tempreg,<constant>
5110 For a local symbol, we want
5111 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5113 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5115 If we have a large constant, and this is a reference to
5116 an external symbol, we want
5117 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5118 addu $tempreg,$tempreg,$gp
5119 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5120 lui $at,<hiconstant>
5121 addiu $at,$at,<loconstant>
5122 addu $tempreg,$tempreg,$at
5123 For a local symbol, we want
5124 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5125 lui $at,<hiconstant>
5126 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5127 addu $tempreg,$tempreg,$at
5130 expr1
.X_add_number
= offset_expr
.X_add_number
;
5131 offset_expr
.X_add_number
= 0;
5132 relax_start (offset_expr
.X_add_symbol
);
5133 gpdelay
= reg_needs_delay (mips_gp_register
);
5134 if (expr1
.X_add_number
== 0 && breg
== 0
5135 && (call
|| tempreg
== PIC_CALL_REG
))
5137 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5138 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5140 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5141 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5142 tempreg
, tempreg
, mips_gp_register
);
5143 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5144 tempreg
, lw_reloc_type
, tempreg
);
5145 if (expr1
.X_add_number
== 0)
5149 /* We're going to put in an addu instruction using
5150 tempreg, so we may as well insert the nop right
5155 else if (expr1
.X_add_number
>= -0x8000
5156 && expr1
.X_add_number
< 0x8000)
5159 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5160 tempreg
, tempreg
, BFD_RELOC_LO16
);
5166 /* If we are going to add in a base register, and the
5167 target register and the base register are the same,
5168 then we are using AT as a temporary register. Since
5169 we want to load the constant into AT, we add our
5170 current AT (from the global offset table) and the
5171 register into the register now, and pretend we were
5172 not using a base register. */
5177 assert (tempreg
== AT
);
5179 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5184 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5185 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5189 offset_expr
.X_add_number
=
5190 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5195 /* This is needed because this instruction uses $gp, but
5196 the first instruction on the main stream does not. */
5197 macro_build (NULL
, "nop", "");
5200 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5201 local_reloc_type
, mips_gp_register
);
5202 if (expr1
.X_add_number
>= -0x8000
5203 && expr1
.X_add_number
< 0x8000)
5206 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5207 tempreg
, tempreg
, BFD_RELOC_LO16
);
5208 /* FIXME: If add_number is 0, and there was no base
5209 register, the external symbol case ended with a load,
5210 so if the symbol turns out to not be external, and
5211 the next instruction uses tempreg, an unnecessary nop
5212 will be inserted. */
5218 /* We must add in the base register now, as in the
5219 external symbol case. */
5220 assert (tempreg
== AT
);
5222 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5225 /* We set breg to 0 because we have arranged to add
5226 it in in both cases. */
5230 macro_build_lui (&expr1
, AT
);
5231 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5232 AT
, AT
, BFD_RELOC_LO16
);
5233 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5234 tempreg
, tempreg
, AT
);
5239 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5241 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5242 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5243 int add_breg_early
= 0;
5245 /* This is the large GOT case. If this is a reference to an
5246 external symbol, and there is no constant, we want
5247 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5248 add $tempreg,$tempreg,$gp
5249 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5250 or for lca or if tempreg is PIC_CALL_REG
5251 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5252 add $tempreg,$tempreg,$gp
5253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5255 If we have a small constant, and this is a reference to
5256 an external symbol, we want
5257 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5258 add $tempreg,$tempreg,$gp
5259 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5260 addi $tempreg,$tempreg,<constant>
5262 If we have a large constant, and this is a reference to
5263 an external symbol, we want
5264 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5265 addu $tempreg,$tempreg,$gp
5266 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5267 lui $at,<hiconstant>
5268 addi $at,$at,<loconstant>
5269 add $tempreg,$tempreg,$at
5271 If we have NewABI, and we know it's a local symbol, we want
5272 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5273 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5274 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5276 relax_start (offset_expr
.X_add_symbol
);
5278 expr1
.X_add_number
= offset_expr
.X_add_number
;
5279 offset_expr
.X_add_number
= 0;
5281 if (expr1
.X_add_number
== 0 && breg
== 0
5282 && (call
|| tempreg
== PIC_CALL_REG
))
5284 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5285 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5287 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5288 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5289 tempreg
, tempreg
, mips_gp_register
);
5290 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5291 tempreg
, lw_reloc_type
, tempreg
);
5293 if (expr1
.X_add_number
== 0)
5295 else if (expr1
.X_add_number
>= -0x8000
5296 && expr1
.X_add_number
< 0x8000)
5298 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5299 tempreg
, tempreg
, BFD_RELOC_LO16
);
5301 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5305 /* If we are going to add in a base register, and the
5306 target register and the base register are the same,
5307 then we are using AT as a temporary register. Since
5308 we want to load the constant into AT, we add our
5309 current AT (from the global offset table) and the
5310 register into the register now, and pretend we were
5311 not using a base register. */
5316 assert (tempreg
== AT
);
5317 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5323 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5324 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5329 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5332 offset_expr
.X_add_number
= expr1
.X_add_number
;
5333 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5334 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5335 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5336 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5339 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5340 treg
, tempreg
, breg
);
5350 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5354 /* The j instruction may not be used in PIC code, since it
5355 requires an absolute address. We convert it to a b
5357 if (mips_pic
== NO_PIC
)
5358 macro_build (&offset_expr
, "j", "a");
5360 macro_build (&offset_expr
, "b", "p");
5363 /* The jal instructions must be handled as macros because when
5364 generating PIC code they expand to multi-instruction
5365 sequences. Normally they are simple instructions. */
5370 if (mips_pic
== NO_PIC
)
5371 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5372 else if (mips_pic
== SVR4_PIC
)
5374 if (sreg
!= PIC_CALL_REG
)
5375 as_warn (_("MIPS PIC call to register other than $25"));
5377 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5380 if (mips_cprestore_offset
< 0)
5381 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5384 if (! mips_frame_reg_valid
)
5386 as_warn (_("No .frame pseudo-op used in PIC code"));
5387 /* Quiet this warning. */
5388 mips_frame_reg_valid
= 1;
5390 if (! mips_cprestore_valid
)
5392 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5393 /* Quiet this warning. */
5394 mips_cprestore_valid
= 1;
5396 expr1
.X_add_number
= mips_cprestore_offset
;
5397 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5400 HAVE_64BIT_ADDRESSES
);
5410 if (mips_pic
== NO_PIC
)
5411 macro_build (&offset_expr
, "jal", "a");
5412 else if (mips_pic
== SVR4_PIC
)
5414 /* If this is a reference to an external symbol, and we are
5415 using a small GOT, we want
5416 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5420 lw $gp,cprestore($sp)
5421 The cprestore value is set using the .cprestore
5422 pseudo-op. If we are using a big GOT, we want
5423 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5425 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5429 lw $gp,cprestore($sp)
5430 If the symbol is not external, we want
5431 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5433 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5436 lw $gp,cprestore($sp)
5438 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5439 sequences above, minus nops, unless the symbol is local,
5440 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5446 relax_start (offset_expr
.X_add_symbol
);
5447 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5448 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5451 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5452 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5458 relax_start (offset_expr
.X_add_symbol
);
5459 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5460 BFD_RELOC_MIPS_CALL_HI16
);
5461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5462 PIC_CALL_REG
, mips_gp_register
);
5463 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5464 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5467 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5468 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5470 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5471 PIC_CALL_REG
, PIC_CALL_REG
,
5472 BFD_RELOC_MIPS_GOT_OFST
);
5476 macro_build_jalr (&offset_expr
);
5480 relax_start (offset_expr
.X_add_symbol
);
5483 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5484 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5493 gpdelay
= reg_needs_delay (mips_gp_register
);
5494 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5495 BFD_RELOC_MIPS_CALL_HI16
);
5496 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5497 PIC_CALL_REG
, mips_gp_register
);
5498 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5499 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5504 macro_build (NULL
, "nop", "");
5506 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5507 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5510 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5511 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5513 macro_build_jalr (&offset_expr
);
5515 if (mips_cprestore_offset
< 0)
5516 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5519 if (! mips_frame_reg_valid
)
5521 as_warn (_("No .frame pseudo-op used in PIC code"));
5522 /* Quiet this warning. */
5523 mips_frame_reg_valid
= 1;
5525 if (! mips_cprestore_valid
)
5527 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5528 /* Quiet this warning. */
5529 mips_cprestore_valid
= 1;
5531 if (mips_opts
.noreorder
)
5532 macro_build (NULL
, "nop", "");
5533 expr1
.X_add_number
= mips_cprestore_offset
;
5534 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5537 HAVE_64BIT_ADDRESSES
);
5563 /* Itbl support may require additional care here. */
5568 /* Itbl support may require additional care here. */
5573 /* Itbl support may require additional care here. */
5578 /* Itbl support may require additional care here. */
5590 if (mips_opts
.arch
== CPU_R4650
)
5592 as_bad (_("opcode not supported on this processor"));
5596 /* Itbl support may require additional care here. */
5601 /* Itbl support may require additional care here. */
5606 /* Itbl support may require additional care here. */
5626 if (breg
== treg
|| coproc
|| lr
)
5647 /* Itbl support may require additional care here. */
5652 /* Itbl support may require additional care here. */
5657 /* Itbl support may require additional care here. */
5662 /* Itbl support may require additional care here. */
5678 if (mips_opts
.arch
== CPU_R4650
)
5680 as_bad (_("opcode not supported on this processor"));
5685 /* Itbl support may require additional care here. */
5689 /* Itbl support may require additional care here. */
5694 /* Itbl support may require additional care here. */
5706 /* Itbl support may require additional care here. */
5707 if (mask
== M_LWC1_AB
5708 || mask
== M_SWC1_AB
5709 || mask
== M_LDC1_AB
5710 || mask
== M_SDC1_AB
5719 if (offset_expr
.X_op
!= O_constant
5720 && offset_expr
.X_op
!= O_symbol
)
5722 as_bad (_("expression too complex"));
5723 offset_expr
.X_op
= O_constant
;
5726 /* A constant expression in PIC code can be handled just as it
5727 is in non PIC code. */
5728 if (offset_expr
.X_op
== O_constant
)
5730 if (HAVE_32BIT_ADDRESSES
5731 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5732 as_bad (_("constant too large"));
5734 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5735 & ~(bfd_vma
) 0xffff);
5736 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5738 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5739 tempreg
, tempreg
, breg
);
5740 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5742 else if (mips_pic
== NO_PIC
)
5744 /* If this is a reference to a GP relative symbol, and there
5745 is no base register, we want
5746 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5747 Otherwise, if there is no base register, we want
5748 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5749 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5750 If we have a constant, we need two instructions anyhow,
5751 so we always use the latter form.
5753 If we have a base register, and this is a reference to a
5754 GP relative symbol, we want
5755 addu $tempreg,$breg,$gp
5756 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5758 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5759 addu $tempreg,$tempreg,$breg
5760 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5761 With a constant we always use the latter case.
5763 With 64bit address space and no base register and $at usable,
5765 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5766 lui $at,<sym> (BFD_RELOC_HI16_S)
5767 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5770 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5771 If we have a base register, we want
5772 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5773 lui $at,<sym> (BFD_RELOC_HI16_S)
5774 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5778 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5780 Without $at we can't generate the optimal path for superscalar
5781 processors here since this would require two temporary registers.
5782 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5783 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5785 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5787 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5788 If we have a base register, we want
5789 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5790 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5792 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5794 daddu $tempreg,$tempreg,$breg
5795 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5797 For GP relative symbols in 64bit address space we can use
5798 the same sequence as in 32bit address space. */
5799 if (HAVE_64BIT_SYMBOLS
)
5801 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5802 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5804 relax_start (offset_expr
.X_add_symbol
);
5807 macro_build (&offset_expr
, s
, fmt
, treg
,
5808 BFD_RELOC_GPREL16
, mips_gp_register
);
5812 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5813 tempreg
, breg
, mips_gp_register
);
5814 macro_build (&offset_expr
, s
, fmt
, treg
,
5815 BFD_RELOC_GPREL16
, tempreg
);
5820 if (used_at
== 0 && !mips_opts
.noat
)
5822 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5823 BFD_RELOC_MIPS_HIGHEST
);
5824 macro_build (&offset_expr
, "lui", "t,u", AT
,
5826 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5827 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5829 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5830 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5831 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5832 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5838 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5839 BFD_RELOC_MIPS_HIGHEST
);
5840 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5841 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5842 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5843 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5844 tempreg
, BFD_RELOC_HI16_S
);
5845 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5847 macro_build (NULL
, "daddu", "d,v,t",
5848 tempreg
, tempreg
, breg
);
5849 macro_build (&offset_expr
, s
, fmt
, treg
,
5850 BFD_RELOC_LO16
, tempreg
);
5853 if (mips_relax
.sequence
)
5860 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5861 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5863 relax_start (offset_expr
.X_add_symbol
);
5864 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5868 macro_build_lui (&offset_expr
, tempreg
);
5869 macro_build (&offset_expr
, s
, fmt
, treg
,
5870 BFD_RELOC_LO16
, tempreg
);
5871 if (mips_relax
.sequence
)
5876 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5877 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5879 relax_start (offset_expr
.X_add_symbol
);
5880 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5881 tempreg
, breg
, mips_gp_register
);
5882 macro_build (&offset_expr
, s
, fmt
, treg
,
5883 BFD_RELOC_GPREL16
, tempreg
);
5886 macro_build_lui (&offset_expr
, tempreg
);
5887 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5888 tempreg
, tempreg
, breg
);
5889 macro_build (&offset_expr
, s
, fmt
, treg
,
5890 BFD_RELOC_LO16
, tempreg
);
5891 if (mips_relax
.sequence
)
5895 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5897 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5899 /* If this is a reference to an external symbol, we want
5900 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5902 <op> $treg,0($tempreg)
5904 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5906 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5907 <op> $treg,0($tempreg)
5910 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5911 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5913 If there is a base register, we add it to $tempreg before
5914 the <op>. If there is a constant, we stick it in the
5915 <op> instruction. We don't handle constants larger than
5916 16 bits, because we have no way to load the upper 16 bits
5917 (actually, we could handle them for the subset of cases
5918 in which we are not using $at). */
5919 assert (offset_expr
.X_op
== O_symbol
);
5922 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5923 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5926 tempreg
, tempreg
, breg
);
5927 macro_build (&offset_expr
, s
, fmt
, treg
,
5928 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
5931 expr1
.X_add_number
= offset_expr
.X_add_number
;
5932 offset_expr
.X_add_number
= 0;
5933 if (expr1
.X_add_number
< -0x8000
5934 || expr1
.X_add_number
>= 0x8000)
5935 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5936 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5937 lw_reloc_type
, mips_gp_register
);
5939 relax_start (offset_expr
.X_add_symbol
);
5941 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5942 tempreg
, BFD_RELOC_LO16
);
5945 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5946 tempreg
, tempreg
, breg
);
5947 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5949 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5953 /* If this is a reference to an external symbol, we want
5954 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5955 addu $tempreg,$tempreg,$gp
5956 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5957 <op> $treg,0($tempreg)
5959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5961 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5962 <op> $treg,0($tempreg)
5963 If there is a base register, we add it to $tempreg before
5964 the <op>. If there is a constant, we stick it in the
5965 <op> instruction. We don't handle constants larger than
5966 16 bits, because we have no way to load the upper 16 bits
5967 (actually, we could handle them for the subset of cases
5968 in which we are not using $at). */
5969 assert (offset_expr
.X_op
== O_symbol
);
5970 expr1
.X_add_number
= offset_expr
.X_add_number
;
5971 offset_expr
.X_add_number
= 0;
5972 if (expr1
.X_add_number
< -0x8000
5973 || expr1
.X_add_number
>= 0x8000)
5974 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5975 gpdelay
= reg_needs_delay (mips_gp_register
);
5976 relax_start (offset_expr
.X_add_symbol
);
5977 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5978 BFD_RELOC_MIPS_GOT_HI16
);
5979 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
5981 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5982 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
5985 macro_build (NULL
, "nop", "");
5986 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5987 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5989 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5990 tempreg
, BFD_RELOC_LO16
);
5994 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5995 tempreg
, tempreg
, breg
);
5996 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5998 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6000 /* If this is a reference to an external symbol, we want
6001 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6002 add $tempreg,$tempreg,$gp
6003 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6004 <op> $treg,<ofst>($tempreg)
6005 Otherwise, for local symbols, we want:
6006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6007 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6008 assert (offset_expr
.X_op
== O_symbol
);
6009 expr1
.X_add_number
= offset_expr
.X_add_number
;
6010 offset_expr
.X_add_number
= 0;
6011 if (expr1
.X_add_number
< -0x8000
6012 || expr1
.X_add_number
>= 0x8000)
6013 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6014 relax_start (offset_expr
.X_add_symbol
);
6015 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6016 BFD_RELOC_MIPS_GOT_HI16
);
6017 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6019 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6020 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6022 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6023 tempreg
, tempreg
, breg
);
6024 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6027 offset_expr
.X_add_number
= expr1
.X_add_number
;
6028 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6029 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6032 tempreg
, tempreg
, breg
);
6033 macro_build (&offset_expr
, s
, fmt
, treg
,
6034 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6044 load_register (treg
, &imm_expr
, 0);
6048 load_register (treg
, &imm_expr
, 1);
6052 if (imm_expr
.X_op
== O_constant
)
6055 load_register (AT
, &imm_expr
, 0);
6056 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6061 assert (offset_expr
.X_op
== O_symbol
6062 && strcmp (segment_name (S_GET_SEGMENT
6063 (offset_expr
.X_add_symbol
)),
6065 && offset_expr
.X_add_number
== 0);
6066 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6067 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6072 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6073 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6074 order 32 bits of the value and the low order 32 bits are either
6075 zero or in OFFSET_EXPR. */
6076 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6078 if (HAVE_64BIT_GPRS
)
6079 load_register (treg
, &imm_expr
, 1);
6084 if (target_big_endian
)
6096 load_register (hreg
, &imm_expr
, 0);
6099 if (offset_expr
.X_op
== O_absent
)
6100 move_register (lreg
, 0);
6103 assert (offset_expr
.X_op
== O_constant
);
6104 load_register (lreg
, &offset_expr
, 0);
6111 /* We know that sym is in the .rdata section. First we get the
6112 upper 16 bits of the address. */
6113 if (mips_pic
== NO_PIC
)
6115 macro_build_lui (&offset_expr
, AT
);
6118 else if (mips_pic
== SVR4_PIC
)
6120 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6121 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6127 /* Now we load the register(s). */
6128 if (HAVE_64BIT_GPRS
)
6131 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6136 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6139 /* FIXME: How in the world do we deal with the possible
6141 offset_expr
.X_add_number
+= 4;
6142 macro_build (&offset_expr
, "lw", "t,o(b)",
6143 treg
+ 1, BFD_RELOC_LO16
, AT
);
6149 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6150 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6151 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6152 the value and the low order 32 bits are either zero or in
6154 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6157 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6158 if (HAVE_64BIT_FPRS
)
6160 assert (HAVE_64BIT_GPRS
);
6161 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6165 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6166 if (offset_expr
.X_op
== O_absent
)
6167 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6170 assert (offset_expr
.X_op
== O_constant
);
6171 load_register (AT
, &offset_expr
, 0);
6172 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6178 assert (offset_expr
.X_op
== O_symbol
6179 && offset_expr
.X_add_number
== 0);
6180 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6181 if (strcmp (s
, ".lit8") == 0)
6183 if (mips_opts
.isa
!= ISA_MIPS1
)
6185 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6186 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6189 breg
= mips_gp_register
;
6190 r
= BFD_RELOC_MIPS_LITERAL
;
6195 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6197 if (mips_pic
== SVR4_PIC
)
6198 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6199 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6202 /* FIXME: This won't work for a 64 bit address. */
6203 macro_build_lui (&offset_expr
, AT
);
6206 if (mips_opts
.isa
!= ISA_MIPS1
)
6208 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6209 treg
, BFD_RELOC_LO16
, AT
);
6218 if (mips_opts
.arch
== CPU_R4650
)
6220 as_bad (_("opcode not supported on this processor"));
6223 /* Even on a big endian machine $fn comes before $fn+1. We have
6224 to adjust when loading from memory. */
6227 assert (mips_opts
.isa
== ISA_MIPS1
);
6228 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6229 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6230 /* FIXME: A possible overflow which I don't know how to deal
6232 offset_expr
.X_add_number
+= 4;
6233 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6234 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6239 * The MIPS assembler seems to check for X_add_number not
6240 * being double aligned and generating:
6243 * addiu at,at,%lo(foo+1)
6246 * But, the resulting address is the same after relocation so why
6247 * generate the extra instruction?
6249 if (mips_opts
.arch
== CPU_R4650
)
6251 as_bad (_("opcode not supported on this processor"));
6254 /* Itbl support may require additional care here. */
6256 if (mips_opts
.isa
!= ISA_MIPS1
)
6267 if (mips_opts
.arch
== CPU_R4650
)
6269 as_bad (_("opcode not supported on this processor"));
6273 if (mips_opts
.isa
!= ISA_MIPS1
)
6281 /* Itbl support may require additional care here. */
6286 if (HAVE_64BIT_GPRS
)
6297 if (HAVE_64BIT_GPRS
)
6307 if (offset_expr
.X_op
!= O_symbol
6308 && offset_expr
.X_op
!= O_constant
)
6310 as_bad (_("expression too complex"));
6311 offset_expr
.X_op
= O_constant
;
6314 /* Even on a big endian machine $fn comes before $fn+1. We have
6315 to adjust when loading from memory. We set coproc if we must
6316 load $fn+1 first. */
6317 /* Itbl support may require additional care here. */
6318 if (! target_big_endian
)
6321 if (mips_pic
== NO_PIC
6322 || offset_expr
.X_op
== O_constant
)
6324 /* If this is a reference to a GP relative symbol, we want
6325 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6326 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6327 If we have a base register, we use this
6329 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6330 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6331 If this is not a GP relative symbol, we want
6332 lui $at,<sym> (BFD_RELOC_HI16_S)
6333 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6334 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6335 If there is a base register, we add it to $at after the
6336 lui instruction. If there is a constant, we always use
6338 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6339 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6341 relax_start (offset_expr
.X_add_symbol
);
6344 tempreg
= mips_gp_register
;
6348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6349 AT
, breg
, mips_gp_register
);
6354 /* Itbl support may require additional care here. */
6355 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6356 BFD_RELOC_GPREL16
, tempreg
);
6357 offset_expr
.X_add_number
+= 4;
6359 /* Set mips_optimize to 2 to avoid inserting an
6361 hold_mips_optimize
= mips_optimize
;
6363 /* Itbl support may require additional care here. */
6364 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6365 BFD_RELOC_GPREL16
, tempreg
);
6366 mips_optimize
= hold_mips_optimize
;
6370 /* We just generated two relocs. When tc_gen_reloc
6371 handles this case, it will skip the first reloc and
6372 handle the second. The second reloc already has an
6373 extra addend of 4, which we added above. We must
6374 subtract it out, and then subtract another 4 to make
6375 the first reloc come out right. The second reloc
6376 will come out right because we are going to add 4 to
6377 offset_expr when we build its instruction below.
6379 If we have a symbol, then we don't want to include
6380 the offset, because it will wind up being included
6381 when we generate the reloc. */
6383 if (offset_expr
.X_op
== O_constant
)
6384 offset_expr
.X_add_number
-= 8;
6387 offset_expr
.X_add_number
= -4;
6388 offset_expr
.X_op
= O_constant
;
6392 macro_build_lui (&offset_expr
, AT
);
6394 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6395 /* Itbl support may require additional care here. */
6396 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6397 BFD_RELOC_LO16
, AT
);
6398 /* FIXME: How do we handle overflow here? */
6399 offset_expr
.X_add_number
+= 4;
6400 /* Itbl support may require additional care here. */
6401 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6402 BFD_RELOC_LO16
, AT
);
6403 if (mips_relax
.sequence
)
6406 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6408 /* If this is a reference to an external symbol, we want
6409 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6414 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6416 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6417 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6418 If there is a base register we add it to $at before the
6419 lwc1 instructions. If there is a constant we include it
6420 in the lwc1 instructions. */
6422 expr1
.X_add_number
= offset_expr
.X_add_number
;
6423 if (expr1
.X_add_number
< -0x8000
6424 || expr1
.X_add_number
>= 0x8000 - 4)
6425 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6426 load_got_offset (AT
, &offset_expr
);
6429 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6431 /* Set mips_optimize to 2 to avoid inserting an undesired
6433 hold_mips_optimize
= mips_optimize
;
6436 /* Itbl support may require additional care here. */
6437 relax_start (offset_expr
.X_add_symbol
);
6438 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6439 BFD_RELOC_LO16
, AT
);
6440 expr1
.X_add_number
+= 4;
6441 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6442 BFD_RELOC_LO16
, AT
);
6444 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6445 BFD_RELOC_LO16
, AT
);
6446 offset_expr
.X_add_number
+= 4;
6447 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6448 BFD_RELOC_LO16
, AT
);
6451 mips_optimize
= hold_mips_optimize
;
6453 else if (mips_pic
== SVR4_PIC
)
6457 /* If this is a reference to an external symbol, we want
6458 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6460 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6465 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6467 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6468 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6469 If there is a base register we add it to $at before the
6470 lwc1 instructions. If there is a constant we include it
6471 in the lwc1 instructions. */
6473 expr1
.X_add_number
= offset_expr
.X_add_number
;
6474 offset_expr
.X_add_number
= 0;
6475 if (expr1
.X_add_number
< -0x8000
6476 || expr1
.X_add_number
>= 0x8000 - 4)
6477 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6478 gpdelay
= reg_needs_delay (mips_gp_register
);
6479 relax_start (offset_expr
.X_add_symbol
);
6480 macro_build (&offset_expr
, "lui", "t,u",
6481 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6482 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6483 AT
, AT
, mips_gp_register
);
6484 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6485 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6488 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6489 /* Itbl support may require additional care here. */
6490 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6491 BFD_RELOC_LO16
, AT
);
6492 expr1
.X_add_number
+= 4;
6494 /* Set mips_optimize to 2 to avoid inserting an undesired
6496 hold_mips_optimize
= mips_optimize
;
6498 /* Itbl support may require additional care here. */
6499 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6500 BFD_RELOC_LO16
, AT
);
6501 mips_optimize
= hold_mips_optimize
;
6502 expr1
.X_add_number
-= 4;
6505 offset_expr
.X_add_number
= expr1
.X_add_number
;
6507 macro_build (NULL
, "nop", "");
6508 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6509 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6512 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6513 /* Itbl support may require additional care here. */
6514 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6515 BFD_RELOC_LO16
, AT
);
6516 offset_expr
.X_add_number
+= 4;
6518 /* Set mips_optimize to 2 to avoid inserting an undesired
6520 hold_mips_optimize
= mips_optimize
;
6522 /* Itbl support may require additional care here. */
6523 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6524 BFD_RELOC_LO16
, AT
);
6525 mips_optimize
= hold_mips_optimize
;
6539 assert (HAVE_32BIT_ADDRESSES
);
6540 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6541 offset_expr
.X_add_number
+= 4;
6542 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6545 /* New code added to support COPZ instructions.
6546 This code builds table entries out of the macros in mip_opcodes.
6547 R4000 uses interlocks to handle coproc delays.
6548 Other chips (like the R3000) require nops to be inserted for delays.
6550 FIXME: Currently, we require that the user handle delays.
6551 In order to fill delay slots for non-interlocked chips,
6552 we must have a way to specify delays based on the coprocessor.
6553 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6554 What are the side-effects of the cop instruction?
6555 What cache support might we have and what are its effects?
6556 Both coprocessor & memory require delays. how long???
6557 What registers are read/set/modified?
6559 If an itbl is provided to interpret cop instructions,
6560 this knowledge can be encoded in the itbl spec. */
6574 /* For now we just do C (same as Cz). The parameter will be
6575 stored in insn_opcode by mips_ip. */
6576 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6580 move_register (dreg
, sreg
);
6583 #ifdef LOSING_COMPILER
6585 /* Try and see if this is a new itbl instruction.
6586 This code builds table entries out of the macros in mip_opcodes.
6587 FIXME: For now we just assemble the expression and pass it's
6588 value along as a 32-bit immediate.
6589 We may want to have the assembler assemble this value,
6590 so that we gain the assembler's knowledge of delay slots,
6592 Would it be more efficient to use mask (id) here? */
6593 if (itbl_have_entries
6594 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6596 s
= ip
->insn_mo
->name
;
6598 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6599 macro_build (&immed_expr
, s
, "C");
6605 if (mips_opts
.noat
&& used_at
)
6606 as_bad (_("Macro used $at after \".set noat\""));
6610 macro2 (struct mips_cl_insn
*ip
)
6612 register int treg
, sreg
, dreg
, breg
;
6627 bfd_reloc_code_real_type r
;
6629 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6630 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6631 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6632 mask
= ip
->insn_mo
->mask
;
6634 expr1
.X_op
= O_constant
;
6635 expr1
.X_op_symbol
= NULL
;
6636 expr1
.X_add_symbol
= NULL
;
6637 expr1
.X_add_number
= 1;
6641 #endif /* LOSING_COMPILER */
6646 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6647 macro_build (NULL
, "mflo", "d", dreg
);
6653 /* The MIPS assembler some times generates shifts and adds. I'm
6654 not trying to be that fancy. GCC should do this for us
6657 load_register (AT
, &imm_expr
, dbl
);
6658 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6659 macro_build (NULL
, "mflo", "d", dreg
);
6672 mips_emit_delays (TRUE
);
6673 ++mips_opts
.noreorder
;
6674 mips_any_noreorder
= 1;
6677 load_register (AT
, &imm_expr
, dbl
);
6678 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6679 macro_build (NULL
, "mflo", "d", dreg
);
6680 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6681 macro_build (NULL
, "mfhi", "d", AT
);
6683 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6686 expr1
.X_add_number
= 8;
6687 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6688 macro_build (NULL
, "nop", "", 0);
6689 macro_build (NULL
, "break", "c", 6);
6691 --mips_opts
.noreorder
;
6692 macro_build (NULL
, "mflo", "d", dreg
);
6705 mips_emit_delays (TRUE
);
6706 ++mips_opts
.noreorder
;
6707 mips_any_noreorder
= 1;
6710 load_register (AT
, &imm_expr
, dbl
);
6711 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6712 sreg
, imm
? AT
: treg
);
6713 macro_build (NULL
, "mfhi", "d", AT
);
6714 macro_build (NULL
, "mflo", "d", dreg
);
6716 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6719 expr1
.X_add_number
= 8;
6720 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6721 macro_build (NULL
, "nop", "", 0);
6722 macro_build (NULL
, "break", "c", 6);
6724 --mips_opts
.noreorder
;
6728 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6739 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6740 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6744 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6745 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6746 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6747 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6751 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6762 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6763 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6767 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6768 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6769 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6770 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6778 if (imm_expr
.X_op
!= O_constant
)
6779 as_bad (_("Improper rotate count"));
6780 rot
= imm_expr
.X_add_number
& 0x3f;
6781 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6783 rot
= (64 - rot
) & 0x3f;
6785 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6787 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6792 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6795 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6796 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6799 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6800 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6801 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6809 if (imm_expr
.X_op
!= O_constant
)
6810 as_bad (_("Improper rotate count"));
6811 rot
= imm_expr
.X_add_number
& 0x1f;
6812 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6814 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6819 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6823 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6824 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6825 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6830 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6832 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6836 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6837 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6838 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6839 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6843 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6845 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6849 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6850 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6851 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6852 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6860 if (imm_expr
.X_op
!= O_constant
)
6861 as_bad (_("Improper rotate count"));
6862 rot
= imm_expr
.X_add_number
& 0x3f;
6863 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6866 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6868 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6873 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6876 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6877 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6880 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6881 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6882 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6890 if (imm_expr
.X_op
!= O_constant
)
6891 as_bad (_("Improper rotate count"));
6892 rot
= imm_expr
.X_add_number
& 0x1f;
6893 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6895 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6900 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6904 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6905 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6906 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6911 if (mips_opts
.arch
== CPU_R4650
)
6913 as_bad (_("opcode not supported on this processor"));
6916 assert (mips_opts
.isa
== ISA_MIPS1
);
6917 /* Even on a big endian machine $fn comes before $fn+1. We have
6918 to adjust when storing to memory. */
6919 macro_build (&offset_expr
, "swc1", "T,o(b)",
6920 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
6921 offset_expr
.X_add_number
+= 4;
6922 macro_build (&offset_expr
, "swc1", "T,o(b)",
6923 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
6928 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
6930 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6933 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
6934 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6939 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6941 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6946 as_warn (_("Instruction %s: result is always false"),
6948 move_register (dreg
, 0);
6951 if (imm_expr
.X_op
== O_constant
6952 && imm_expr
.X_add_number
>= 0
6953 && imm_expr
.X_add_number
< 0x10000)
6955 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
6957 else if (imm_expr
.X_op
== O_constant
6958 && imm_expr
.X_add_number
> -0x8000
6959 && imm_expr
.X_add_number
< 0)
6961 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6962 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6963 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
6967 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6968 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
6971 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
6974 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6980 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6981 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
6984 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6986 if (imm_expr
.X_op
== O_constant
6987 && imm_expr
.X_add_number
>= -0x8000
6988 && imm_expr
.X_add_number
< 0x8000)
6990 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
6991 dreg
, sreg
, BFD_RELOC_LO16
);
6995 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6996 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7000 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7003 case M_SGT
: /* sreg > treg <==> treg < sreg */
7009 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7012 case M_SGT_I
: /* sreg > I <==> I < sreg */
7019 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7020 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7023 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7029 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7030 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7033 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7040 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7041 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7042 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7046 if (imm_expr
.X_op
== O_constant
7047 && imm_expr
.X_add_number
>= -0x8000
7048 && imm_expr
.X_add_number
< 0x8000)
7050 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7054 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7055 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7059 if (imm_expr
.X_op
== O_constant
7060 && imm_expr
.X_add_number
>= -0x8000
7061 && imm_expr
.X_add_number
< 0x8000)
7063 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7068 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7069 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7074 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7076 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7079 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7080 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7085 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7087 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7092 as_warn (_("Instruction %s: result is always true"),
7094 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7095 dreg
, 0, BFD_RELOC_LO16
);
7098 if (imm_expr
.X_op
== O_constant
7099 && imm_expr
.X_add_number
>= 0
7100 && imm_expr
.X_add_number
< 0x10000)
7102 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7104 else if (imm_expr
.X_op
== O_constant
7105 && imm_expr
.X_add_number
> -0x8000
7106 && imm_expr
.X_add_number
< 0)
7108 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7109 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7110 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7114 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7115 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7118 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7124 if (imm_expr
.X_op
== O_constant
7125 && imm_expr
.X_add_number
> -0x8000
7126 && imm_expr
.X_add_number
<= 0x8000)
7128 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7129 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7130 dreg
, sreg
, BFD_RELOC_LO16
);
7134 load_register (AT
, &imm_expr
, dbl
);
7135 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7141 if (imm_expr
.X_op
== O_constant
7142 && imm_expr
.X_add_number
> -0x8000
7143 && imm_expr
.X_add_number
<= 0x8000)
7145 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7146 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7147 dreg
, sreg
, BFD_RELOC_LO16
);
7151 load_register (AT
, &imm_expr
, dbl
);
7152 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7174 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7175 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7180 assert (mips_opts
.isa
== ISA_MIPS1
);
7182 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7183 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7186 * Is the double cfc1 instruction a bug in the mips assembler;
7187 * or is there a reason for it?
7189 mips_emit_delays (TRUE
);
7190 ++mips_opts
.noreorder
;
7191 mips_any_noreorder
= 1;
7192 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7193 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7194 macro_build (NULL
, "nop", "");
7195 expr1
.X_add_number
= 3;
7196 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7197 expr1
.X_add_number
= 2;
7198 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7199 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7200 macro_build (NULL
, "nop", "");
7201 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7203 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7204 macro_build (NULL
, "nop", "");
7205 --mips_opts
.noreorder
;
7215 if (offset_expr
.X_add_number
>= 0x7fff)
7216 as_bad (_("operand overflow"));
7217 if (! target_big_endian
)
7218 ++offset_expr
.X_add_number
;
7219 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7220 if (! target_big_endian
)
7221 --offset_expr
.X_add_number
;
7223 ++offset_expr
.X_add_number
;
7224 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7225 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7226 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7239 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7240 as_bad (_("operand overflow"));
7248 if (! target_big_endian
)
7249 offset_expr
.X_add_number
+= off
;
7250 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7251 if (! target_big_endian
)
7252 offset_expr
.X_add_number
-= off
;
7254 offset_expr
.X_add_number
+= off
;
7255 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7257 /* If necessary, move the result in tempreg the final destination. */
7258 if (treg
== tempreg
)
7260 /* Protect second load's delay slot. */
7262 move_register (treg
, tempreg
);
7276 load_address (AT
, &offset_expr
, &used_at
);
7278 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7279 if (! target_big_endian
)
7280 expr1
.X_add_number
= off
;
7282 expr1
.X_add_number
= 0;
7283 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7284 if (! target_big_endian
)
7285 expr1
.X_add_number
= 0;
7287 expr1
.X_add_number
= off
;
7288 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7294 load_address (AT
, &offset_expr
, &used_at
);
7296 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7297 if (target_big_endian
)
7298 expr1
.X_add_number
= 0;
7299 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7300 treg
, BFD_RELOC_LO16
, AT
);
7301 if (target_big_endian
)
7302 expr1
.X_add_number
= 1;
7304 expr1
.X_add_number
= 0;
7305 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7306 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7307 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7312 if (offset_expr
.X_add_number
>= 0x7fff)
7313 as_bad (_("operand overflow"));
7314 if (target_big_endian
)
7315 ++offset_expr
.X_add_number
;
7316 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7317 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7318 if (target_big_endian
)
7319 --offset_expr
.X_add_number
;
7321 ++offset_expr
.X_add_number
;
7322 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7335 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7336 as_bad (_("operand overflow"));
7337 if (! target_big_endian
)
7338 offset_expr
.X_add_number
+= off
;
7339 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7340 if (! target_big_endian
)
7341 offset_expr
.X_add_number
-= off
;
7343 offset_expr
.X_add_number
+= off
;
7344 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7358 load_address (AT
, &offset_expr
, &used_at
);
7360 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7361 if (! target_big_endian
)
7362 expr1
.X_add_number
= off
;
7364 expr1
.X_add_number
= 0;
7365 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7366 if (! target_big_endian
)
7367 expr1
.X_add_number
= 0;
7369 expr1
.X_add_number
= off
;
7370 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7375 load_address (AT
, &offset_expr
, &used_at
);
7377 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7378 if (! target_big_endian
)
7379 expr1
.X_add_number
= 0;
7380 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7381 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7382 if (! target_big_endian
)
7383 expr1
.X_add_number
= 1;
7385 expr1
.X_add_number
= 0;
7386 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7387 if (! target_big_endian
)
7388 expr1
.X_add_number
= 0;
7390 expr1
.X_add_number
= 1;
7391 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7392 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7393 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7397 /* FIXME: Check if this is one of the itbl macros, since they
7398 are added dynamically. */
7399 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7402 if (mips_opts
.noat
&& used_at
)
7403 as_bad (_("Macro used $at after \".set noat\""));
7406 /* Implement macros in mips16 mode. */
7409 mips16_macro (struct mips_cl_insn
*ip
)
7412 int xreg
, yreg
, zreg
, tmp
;
7415 const char *s
, *s2
, *s3
;
7417 mask
= ip
->insn_mo
->mask
;
7419 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7420 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7421 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7423 expr1
.X_op
= O_constant
;
7424 expr1
.X_op_symbol
= NULL
;
7425 expr1
.X_add_symbol
= NULL
;
7426 expr1
.X_add_number
= 1;
7445 mips_emit_delays (TRUE
);
7446 ++mips_opts
.noreorder
;
7447 mips_any_noreorder
= 1;
7448 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7449 expr1
.X_add_number
= 2;
7450 macro_build (&expr1
, "bnez", "x,p", yreg
);
7451 macro_build (NULL
, "break", "6", 7);
7453 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7454 since that causes an overflow. We should do that as well,
7455 but I don't see how to do the comparisons without a temporary
7457 --mips_opts
.noreorder
;
7458 macro_build (NULL
, s
, "x", zreg
);
7477 mips_emit_delays (TRUE
);
7478 ++mips_opts
.noreorder
;
7479 mips_any_noreorder
= 1;
7480 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7481 expr1
.X_add_number
= 2;
7482 macro_build (&expr1
, "bnez", "x,p", yreg
);
7483 macro_build (NULL
, "break", "6", 7);
7484 --mips_opts
.noreorder
;
7485 macro_build (NULL
, s2
, "x", zreg
);
7491 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7492 macro_build (NULL
, "mflo", "x", zreg
);
7500 if (imm_expr
.X_op
!= O_constant
)
7501 as_bad (_("Unsupported large constant"));
7502 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7503 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7507 if (imm_expr
.X_op
!= O_constant
)
7508 as_bad (_("Unsupported large constant"));
7509 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7510 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7514 if (imm_expr
.X_op
!= O_constant
)
7515 as_bad (_("Unsupported large constant"));
7516 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7517 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7539 goto do_reverse_branch
;
7543 goto do_reverse_branch
;
7555 goto do_reverse_branch
;
7566 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7567 macro_build (&offset_expr
, s2
, "p");
7594 goto do_addone_branch_i
;
7599 goto do_addone_branch_i
;
7614 goto do_addone_branch_i
;
7621 if (imm_expr
.X_op
!= O_constant
)
7622 as_bad (_("Unsupported large constant"));
7623 ++imm_expr
.X_add_number
;
7626 macro_build (&imm_expr
, s
, s3
, xreg
);
7627 macro_build (&offset_expr
, s2
, "p");
7631 expr1
.X_add_number
= 0;
7632 macro_build (&expr1
, "slti", "x,8", yreg
);
7634 move_register (xreg
, yreg
);
7635 expr1
.X_add_number
= 2;
7636 macro_build (&expr1
, "bteqz", "p");
7637 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7641 /* For consistency checking, verify that all bits are specified either
7642 by the match/mask part of the instruction definition, or by the
7645 validate_mips_insn (const struct mips_opcode
*opc
)
7647 const char *p
= opc
->args
;
7649 unsigned long used_bits
= opc
->mask
;
7651 if ((used_bits
& opc
->match
) != opc
->match
)
7653 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7654 opc
->name
, opc
->args
);
7657 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7667 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7668 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7669 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7670 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7671 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7672 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7673 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7674 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7675 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7678 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7679 c
, opc
->name
, opc
->args
);
7683 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7684 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7686 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7687 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7688 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7689 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7691 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7692 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7694 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7695 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7697 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7698 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7699 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7700 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7701 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7702 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7703 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7704 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7705 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7706 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7707 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7708 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7709 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7710 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7711 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7712 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7713 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7715 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7716 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7717 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7718 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7720 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7721 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7722 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7723 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7724 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7725 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7726 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7727 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7728 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7731 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7732 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7733 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7734 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7735 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7739 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7740 c
, opc
->name
, opc
->args
);
7744 if (used_bits
!= 0xffffffff)
7746 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7747 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7753 /* This routine assembles an instruction into its binary format. As a
7754 side effect, it sets one of the global variables imm_reloc or
7755 offset_reloc to the type of relocation to do if one of the operands
7756 is an address expression. */
7759 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7764 struct mips_opcode
*insn
;
7767 unsigned int lastregno
= 0;
7768 unsigned int lastpos
= 0;
7769 unsigned int limlo
, limhi
;
7775 /* If the instruction contains a '.', we first try to match an instruction
7776 including the '.'. Then we try again without the '.'. */
7778 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7781 /* If we stopped on whitespace, then replace the whitespace with null for
7782 the call to hash_find. Save the character we replaced just in case we
7783 have to re-parse the instruction. */
7790 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7792 /* If we didn't find the instruction in the opcode table, try again, but
7793 this time with just the instruction up to, but not including the
7797 /* Restore the character we overwrite above (if any). */
7801 /* Scan up to the first '.' or whitespace. */
7803 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7807 /* If we did not find a '.', then we can quit now. */
7810 insn_error
= "unrecognized opcode";
7814 /* Lookup the instruction in the hash table. */
7816 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7818 insn_error
= "unrecognized opcode";
7828 assert (strcmp (insn
->name
, str
) == 0);
7830 if (OPCODE_IS_MEMBER (insn
,
7832 | (file_ase_mips16
? INSN_MIPS16
: 0)
7833 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7834 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7840 if (insn
->pinfo
!= INSN_MACRO
)
7842 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7848 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7849 && strcmp (insn
->name
, insn
[1].name
) == 0)
7858 static char buf
[100];
7860 _("opcode not supported on this processor: %s (%s)"),
7861 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7862 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7871 create_insn (ip
, insn
);
7873 for (args
= insn
->args
;; ++args
)
7877 s
+= strspn (s
, " \t");
7881 case '\0': /* end of args */
7894 INSERT_OPERAND (RS
, *ip
, lastregno
);
7898 INSERT_OPERAND (RT
, *ip
, lastregno
);
7902 INSERT_OPERAND (FT
, *ip
, lastregno
);
7906 INSERT_OPERAND (FS
, *ip
, lastregno
);
7912 /* Handle optional base register.
7913 Either the base register is omitted or
7914 we must have a left paren. */
7915 /* This is dependent on the next operand specifier
7916 is a base register specification. */
7917 assert (args
[1] == 'b' || args
[1] == '5'
7918 || args
[1] == '-' || args
[1] == '4');
7922 case ')': /* these must match exactly */
7929 case '+': /* Opcode extension character. */
7932 case 'A': /* ins/ext position, becomes LSB. */
7941 my_getExpression (&imm_expr
, s
);
7942 check_absolute_expr (ip
, &imm_expr
);
7943 if ((unsigned long) imm_expr
.X_add_number
< limlo
7944 || (unsigned long) imm_expr
.X_add_number
> limhi
)
7946 as_bad (_("Improper position (%lu)"),
7947 (unsigned long) imm_expr
.X_add_number
);
7948 imm_expr
.X_add_number
= limlo
;
7950 lastpos
= imm_expr
.X_add_number
;
7951 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
7952 imm_expr
.X_op
= O_absent
;
7956 case 'B': /* ins size, becomes MSB. */
7965 my_getExpression (&imm_expr
, s
);
7966 check_absolute_expr (ip
, &imm_expr
);
7967 /* Check for negative input so that small negative numbers
7968 will not succeed incorrectly. The checks against
7969 (pos+size) transitively check "size" itself,
7970 assuming that "pos" is reasonable. */
7971 if ((long) imm_expr
.X_add_number
< 0
7972 || ((unsigned long) imm_expr
.X_add_number
7974 || ((unsigned long) imm_expr
.X_add_number
7977 as_bad (_("Improper insert size (%lu, position %lu)"),
7978 (unsigned long) imm_expr
.X_add_number
,
7979 (unsigned long) lastpos
);
7980 imm_expr
.X_add_number
= limlo
- lastpos
;
7982 INSERT_OPERAND (INSMSB
, *ip
,
7983 lastpos
+ imm_expr
.X_add_number
- 1);
7984 imm_expr
.X_op
= O_absent
;
7988 case 'C': /* ext size, becomes MSBD. */
8001 my_getExpression (&imm_expr
, s
);
8002 check_absolute_expr (ip
, &imm_expr
);
8003 /* Check for negative input so that small negative numbers
8004 will not succeed incorrectly. The checks against
8005 (pos+size) transitively check "size" itself,
8006 assuming that "pos" is reasonable. */
8007 if ((long) imm_expr
.X_add_number
< 0
8008 || ((unsigned long) imm_expr
.X_add_number
8010 || ((unsigned long) imm_expr
.X_add_number
8013 as_bad (_("Improper extract size (%lu, position %lu)"),
8014 (unsigned long) imm_expr
.X_add_number
,
8015 (unsigned long) lastpos
);
8016 imm_expr
.X_add_number
= limlo
- lastpos
;
8018 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8019 imm_expr
.X_op
= O_absent
;
8024 /* +D is for disassembly only; never match. */
8028 /* "+I" is like "I", except that imm2_expr is used. */
8029 my_getExpression (&imm2_expr
, s
);
8030 if (imm2_expr
.X_op
!= O_big
8031 && imm2_expr
.X_op
!= O_constant
)
8032 insn_error
= _("absolute expression required");
8033 normalize_constant_expr (&imm2_expr
);
8038 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8039 *args
, insn
->name
, insn
->args
);
8040 /* Further processing is fruitless. */
8045 case '<': /* must be at least one digit */
8047 * According to the manual, if the shift amount is greater
8048 * than 31 or less than 0, then the shift amount should be
8049 * mod 32. In reality the mips assembler issues an error.
8050 * We issue a warning and mask out all but the low 5 bits.
8052 my_getExpression (&imm_expr
, s
);
8053 check_absolute_expr (ip
, &imm_expr
);
8054 if ((unsigned long) imm_expr
.X_add_number
> 31)
8055 as_warn (_("Improper shift amount (%lu)"),
8056 (unsigned long) imm_expr
.X_add_number
);
8057 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8058 imm_expr
.X_op
= O_absent
;
8062 case '>': /* shift amount minus 32 */
8063 my_getExpression (&imm_expr
, s
);
8064 check_absolute_expr (ip
, &imm_expr
);
8065 if ((unsigned long) imm_expr
.X_add_number
< 32
8066 || (unsigned long) imm_expr
.X_add_number
> 63)
8068 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8069 imm_expr
.X_op
= O_absent
;
8073 case 'k': /* cache code */
8074 case 'h': /* prefx code */
8075 my_getExpression (&imm_expr
, s
);
8076 check_absolute_expr (ip
, &imm_expr
);
8077 if ((unsigned long) imm_expr
.X_add_number
> 31)
8078 as_warn (_("Invalid value for `%s' (%lu)"),
8080 (unsigned long) imm_expr
.X_add_number
);
8082 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8084 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8085 imm_expr
.X_op
= O_absent
;
8089 case 'c': /* break code */
8090 my_getExpression (&imm_expr
, s
);
8091 check_absolute_expr (ip
, &imm_expr
);
8092 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8093 as_warn (_("Illegal break code (%lu)"),
8094 (unsigned long) imm_expr
.X_add_number
);
8095 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8096 imm_expr
.X_op
= O_absent
;
8100 case 'q': /* lower break code */
8101 my_getExpression (&imm_expr
, s
);
8102 check_absolute_expr (ip
, &imm_expr
);
8103 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8104 as_warn (_("Illegal lower break code (%lu)"),
8105 (unsigned long) imm_expr
.X_add_number
);
8106 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8107 imm_expr
.X_op
= O_absent
;
8111 case 'B': /* 20-bit syscall/break code. */
8112 my_getExpression (&imm_expr
, s
);
8113 check_absolute_expr (ip
, &imm_expr
);
8114 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8115 as_warn (_("Illegal 20-bit code (%lu)"),
8116 (unsigned long) imm_expr
.X_add_number
);
8117 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8118 imm_expr
.X_op
= O_absent
;
8122 case 'C': /* Coprocessor code */
8123 my_getExpression (&imm_expr
, s
);
8124 check_absolute_expr (ip
, &imm_expr
);
8125 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8127 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8128 (unsigned long) imm_expr
.X_add_number
);
8129 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8131 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8132 imm_expr
.X_op
= O_absent
;
8136 case 'J': /* 19-bit wait code. */
8137 my_getExpression (&imm_expr
, s
);
8138 check_absolute_expr (ip
, &imm_expr
);
8139 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8140 as_warn (_("Illegal 19-bit code (%lu)"),
8141 (unsigned long) imm_expr
.X_add_number
);
8142 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8143 imm_expr
.X_op
= O_absent
;
8147 case 'P': /* Performance register */
8148 my_getExpression (&imm_expr
, s
);
8149 check_absolute_expr (ip
, &imm_expr
);
8150 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8151 as_warn (_("Invalid performance register (%lu)"),
8152 (unsigned long) imm_expr
.X_add_number
);
8153 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8154 imm_expr
.X_op
= O_absent
;
8158 case 'b': /* base register */
8159 case 'd': /* destination register */
8160 case 's': /* source register */
8161 case 't': /* target register */
8162 case 'r': /* both target and source */
8163 case 'v': /* both dest and source */
8164 case 'w': /* both dest and target */
8165 case 'E': /* coprocessor target register */
8166 case 'G': /* coprocessor destination register */
8167 case 'K': /* 'rdhwr' destination register */
8168 case 'x': /* ignore register name */
8169 case 'z': /* must be zero register */
8170 case 'U': /* destination register (clo/clz). */
8185 while (ISDIGIT (*s
));
8187 as_bad (_("Invalid register number (%d)"), regno
);
8189 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8193 if (s
[1] == 'r' && s
[2] == 'a')
8198 else if (s
[1] == 'f' && s
[2] == 'p')
8203 else if (s
[1] == 's' && s
[2] == 'p')
8208 else if (s
[1] == 'g' && s
[2] == 'p')
8213 else if (s
[1] == 'a' && s
[2] == 't')
8218 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8223 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8228 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8233 else if (itbl_have_entries
)
8238 p
= s
+ 1; /* advance past '$' */
8239 n
= itbl_get_field (&p
); /* n is name */
8241 /* See if this is a register defined in an
8243 if (itbl_get_reg_val (n
, &r
))
8245 /* Get_field advances to the start of
8246 the next field, so we need to back
8247 rack to the end of the last field. */
8251 s
= strchr (s
, '\0');
8265 as_warn (_("Used $at without \".set noat\""));
8271 if (c
== 'r' || c
== 'v' || c
== 'w')
8278 /* 'z' only matches $0. */
8279 if (c
== 'z' && regno
!= 0)
8282 /* Now that we have assembled one operand, we use the args string
8283 * to figure out where it goes in the instruction. */
8290 INSERT_OPERAND (RS
, *ip
, regno
);
8295 INSERT_OPERAND (RD
, *ip
, regno
);
8298 INSERT_OPERAND (RD
, *ip
, regno
);
8299 INSERT_OPERAND (RT
, *ip
, regno
);
8304 INSERT_OPERAND (RT
, *ip
, regno
);
8307 /* This case exists because on the r3000 trunc
8308 expands into a macro which requires a gp
8309 register. On the r6000 or r4000 it is
8310 assembled into a single instruction which
8311 ignores the register. Thus the insn version
8312 is MIPS_ISA2 and uses 'x', and the macro
8313 version is MIPS_ISA1 and uses 't'. */
8316 /* This case is for the div instruction, which
8317 acts differently if the destination argument
8318 is $0. This only matches $0, and is checked
8319 outside the switch. */
8322 /* Itbl operand; not yet implemented. FIXME ?? */
8324 /* What about all other operands like 'i', which
8325 can be specified in the opcode table? */
8335 INSERT_OPERAND (RS
, *ip
, lastregno
);
8338 INSERT_OPERAND (RT
, *ip
, lastregno
);
8343 case 'O': /* MDMX alignment immediate constant. */
8344 my_getExpression (&imm_expr
, s
);
8345 check_absolute_expr (ip
, &imm_expr
);
8346 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8347 as_warn ("Improper align amount (%ld), using low bits",
8348 (long) imm_expr
.X_add_number
);
8349 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8350 imm_expr
.X_op
= O_absent
;
8354 case 'Q': /* MDMX vector, element sel, or const. */
8357 /* MDMX Immediate. */
8358 my_getExpression (&imm_expr
, s
);
8359 check_absolute_expr (ip
, &imm_expr
);
8360 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8361 as_warn (_("Invalid MDMX Immediate (%ld)"),
8362 (long) imm_expr
.X_add_number
);
8363 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8364 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8365 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8367 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8368 imm_expr
.X_op
= O_absent
;
8372 /* Not MDMX Immediate. Fall through. */
8373 case 'X': /* MDMX destination register. */
8374 case 'Y': /* MDMX source register. */
8375 case 'Z': /* MDMX target register. */
8377 case 'D': /* floating point destination register */
8378 case 'S': /* floating point source register */
8379 case 'T': /* floating point target register */
8380 case 'R': /* floating point source register */
8384 /* Accept $fN for FP and MDMX register numbers, and in
8385 addition accept $vN for MDMX register numbers. */
8386 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8387 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8398 while (ISDIGIT (*s
));
8401 as_bad (_("Invalid float register number (%d)"), regno
);
8403 if ((regno
& 1) != 0
8405 && ! (strcmp (str
, "mtc1") == 0
8406 || strcmp (str
, "mfc1") == 0
8407 || strcmp (str
, "lwc1") == 0
8408 || strcmp (str
, "swc1") == 0
8409 || strcmp (str
, "l.s") == 0
8410 || strcmp (str
, "s.s") == 0))
8411 as_warn (_("Float register should be even, was %d"),
8419 if (c
== 'V' || c
== 'W')
8430 INSERT_OPERAND (FD
, *ip
, regno
);
8435 INSERT_OPERAND (FS
, *ip
, regno
);
8438 /* This is like 'Z', but also needs to fix the MDMX
8439 vector/scalar select bits. Note that the
8440 scalar immediate case is handled above. */
8443 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8444 int max_el
= (is_qh
? 3 : 7);
8446 my_getExpression(&imm_expr
, s
);
8447 check_absolute_expr (ip
, &imm_expr
);
8449 if (imm_expr
.X_add_number
> max_el
)
8450 as_bad(_("Bad element selector %ld"),
8451 (long) imm_expr
.X_add_number
);
8452 imm_expr
.X_add_number
&= max_el
;
8453 ip
->insn_opcode
|= (imm_expr
.X_add_number
8456 imm_expr
.X_op
= O_absent
;
8458 as_warn(_("Expecting ']' found '%s'"), s
);
8464 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8465 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8468 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8475 INSERT_OPERAND (FT
, *ip
, regno
);
8478 INSERT_OPERAND (FR
, *ip
, regno
);
8488 INSERT_OPERAND (FS
, *ip
, lastregno
);
8491 INSERT_OPERAND (FT
, *ip
, lastregno
);
8497 my_getExpression (&imm_expr
, s
);
8498 if (imm_expr
.X_op
!= O_big
8499 && imm_expr
.X_op
!= O_constant
)
8500 insn_error
= _("absolute expression required");
8501 normalize_constant_expr (&imm_expr
);
8506 my_getExpression (&offset_expr
, s
);
8507 *imm_reloc
= BFD_RELOC_32
;
8520 unsigned char temp
[8];
8522 unsigned int length
;
8527 /* These only appear as the last operand in an
8528 instruction, and every instruction that accepts
8529 them in any variant accepts them in all variants.
8530 This means we don't have to worry about backing out
8531 any changes if the instruction does not match.
8533 The difference between them is the size of the
8534 floating point constant and where it goes. For 'F'
8535 and 'L' the constant is 64 bits; for 'f' and 'l' it
8536 is 32 bits. Where the constant is placed is based
8537 on how the MIPS assembler does things:
8540 f -- immediate value
8543 The .lit4 and .lit8 sections are only used if
8544 permitted by the -G argument.
8546 The code below needs to know whether the target register
8547 is 32 or 64 bits wide. It relies on the fact 'f' and
8548 'F' are used with GPR-based instructions and 'l' and
8549 'L' are used with FPR-based instructions. */
8551 f64
= *args
== 'F' || *args
== 'L';
8552 using_gprs
= *args
== 'F' || *args
== 'f';
8554 save_in
= input_line_pointer
;
8555 input_line_pointer
= s
;
8556 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8558 s
= input_line_pointer
;
8559 input_line_pointer
= save_in
;
8560 if (err
!= NULL
&& *err
!= '\0')
8562 as_bad (_("Bad floating point constant: %s"), err
);
8563 memset (temp
, '\0', sizeof temp
);
8564 length
= f64
? 8 : 4;
8567 assert (length
== (unsigned) (f64
? 8 : 4));
8571 && (g_switch_value
< 4
8572 || (temp
[0] == 0 && temp
[1] == 0)
8573 || (temp
[2] == 0 && temp
[3] == 0))))
8575 imm_expr
.X_op
= O_constant
;
8576 if (! target_big_endian
)
8577 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8579 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8582 && ! mips_disable_float_construction
8583 /* Constants can only be constructed in GPRs and
8584 copied to FPRs if the GPRs are at least as wide
8585 as the FPRs. Force the constant into memory if
8586 we are using 64-bit FPRs but the GPRs are only
8589 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8590 && ((temp
[0] == 0 && temp
[1] == 0)
8591 || (temp
[2] == 0 && temp
[3] == 0))
8592 && ((temp
[4] == 0 && temp
[5] == 0)
8593 || (temp
[6] == 0 && temp
[7] == 0)))
8595 /* The value is simple enough to load with a couple of
8596 instructions. If using 32-bit registers, set
8597 imm_expr to the high order 32 bits and offset_expr to
8598 the low order 32 bits. Otherwise, set imm_expr to
8599 the entire 64 bit constant. */
8600 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8602 imm_expr
.X_op
= O_constant
;
8603 offset_expr
.X_op
= O_constant
;
8604 if (! target_big_endian
)
8606 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8607 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8611 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8612 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8614 if (offset_expr
.X_add_number
== 0)
8615 offset_expr
.X_op
= O_absent
;
8617 else if (sizeof (imm_expr
.X_add_number
) > 4)
8619 imm_expr
.X_op
= O_constant
;
8620 if (! target_big_endian
)
8621 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8623 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8627 imm_expr
.X_op
= O_big
;
8628 imm_expr
.X_add_number
= 4;
8629 if (! target_big_endian
)
8631 generic_bignum
[0] = bfd_getl16 (temp
);
8632 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8633 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8634 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8638 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8639 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8640 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8641 generic_bignum
[3] = bfd_getb16 (temp
);
8647 const char *newname
;
8650 /* Switch to the right section. */
8652 subseg
= now_subseg
;
8655 default: /* unused default case avoids warnings. */
8657 newname
= RDATA_SECTION_NAME
;
8658 if (g_switch_value
>= 8)
8662 newname
= RDATA_SECTION_NAME
;
8665 assert (g_switch_value
>= 4);
8669 new_seg
= subseg_new (newname
, (subsegT
) 0);
8670 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8671 bfd_set_section_flags (stdoutput
, new_seg
,
8676 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8677 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8678 && strcmp (TARGET_OS
, "elf") != 0)
8679 record_alignment (new_seg
, 4);
8681 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8683 as_bad (_("Can't use floating point insn in this section"));
8685 /* Set the argument to the current address in the
8687 offset_expr
.X_op
= O_symbol
;
8688 offset_expr
.X_add_symbol
=
8689 symbol_new ("L0\001", now_seg
,
8690 (valueT
) frag_now_fix (), frag_now
);
8691 offset_expr
.X_add_number
= 0;
8693 /* Put the floating point number into the section. */
8694 p
= frag_more ((int) length
);
8695 memcpy (p
, temp
, length
);
8697 /* Switch back to the original section. */
8698 subseg_set (seg
, subseg
);
8703 case 'i': /* 16 bit unsigned immediate */
8704 case 'j': /* 16 bit signed immediate */
8705 *imm_reloc
= BFD_RELOC_LO16
;
8706 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8709 offsetT minval
, maxval
;
8711 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8712 && strcmp (insn
->name
, insn
[1].name
) == 0);
8714 /* If the expression was written as an unsigned number,
8715 only treat it as signed if there are no more
8719 && sizeof (imm_expr
.X_add_number
) <= 4
8720 && imm_expr
.X_op
== O_constant
8721 && imm_expr
.X_add_number
< 0
8722 && imm_expr
.X_unsigned
8726 /* For compatibility with older assemblers, we accept
8727 0x8000-0xffff as signed 16-bit numbers when only
8728 signed numbers are allowed. */
8730 minval
= 0, maxval
= 0xffff;
8732 minval
= -0x8000, maxval
= 0x7fff;
8734 minval
= -0x8000, maxval
= 0xffff;
8736 if (imm_expr
.X_op
!= O_constant
8737 || imm_expr
.X_add_number
< minval
8738 || imm_expr
.X_add_number
> maxval
)
8742 if (imm_expr
.X_op
== O_constant
8743 || imm_expr
.X_op
== O_big
)
8744 as_bad (_("expression out of range"));
8750 case 'o': /* 16 bit offset */
8751 /* Check whether there is only a single bracketed expression
8752 left. If so, it must be the base register and the
8753 constant must be zero. */
8754 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8756 offset_expr
.X_op
= O_constant
;
8757 offset_expr
.X_add_number
= 0;
8761 /* If this value won't fit into a 16 bit offset, then go
8762 find a macro that will generate the 32 bit offset
8764 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8765 && (offset_expr
.X_op
!= O_constant
8766 || offset_expr
.X_add_number
>= 0x8000
8767 || offset_expr
.X_add_number
< -0x8000))
8773 case 'p': /* pc relative offset */
8774 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8775 my_getExpression (&offset_expr
, s
);
8779 case 'u': /* upper 16 bits */
8780 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8781 && imm_expr
.X_op
== O_constant
8782 && (imm_expr
.X_add_number
< 0
8783 || imm_expr
.X_add_number
>= 0x10000))
8784 as_bad (_("lui expression not in range 0..65535"));
8788 case 'a': /* 26 bit address */
8789 my_getExpression (&offset_expr
, s
);
8791 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8794 case 'N': /* 3 bit branch condition code */
8795 case 'M': /* 3 bit compare condition code */
8796 if (strncmp (s
, "$fcc", 4) != 0)
8806 while (ISDIGIT (*s
));
8808 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8809 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8810 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8811 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8812 && (regno
& 1) != 0)
8813 as_warn(_("Condition code register should be even for %s, was %d"),
8815 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8816 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8817 && (regno
& 3) != 0)
8818 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8821 INSERT_OPERAND (BCC
, *ip
, regno
);
8823 INSERT_OPERAND (CCC
, *ip
, regno
);
8827 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8838 while (ISDIGIT (*s
));
8841 c
= 8; /* Invalid sel value. */
8844 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8845 ip
->insn_opcode
|= c
;
8849 /* Must be at least one digit. */
8850 my_getExpression (&imm_expr
, s
);
8851 check_absolute_expr (ip
, &imm_expr
);
8853 if ((unsigned long) imm_expr
.X_add_number
8854 > (unsigned long) OP_MASK_VECBYTE
)
8856 as_bad (_("bad byte vector index (%ld)"),
8857 (long) imm_expr
.X_add_number
);
8858 imm_expr
.X_add_number
= 0;
8861 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8862 imm_expr
.X_op
= O_absent
;
8867 my_getExpression (&imm_expr
, s
);
8868 check_absolute_expr (ip
, &imm_expr
);
8870 if ((unsigned long) imm_expr
.X_add_number
8871 > (unsigned long) OP_MASK_VECALIGN
)
8873 as_bad (_("bad byte vector index (%ld)"),
8874 (long) imm_expr
.X_add_number
);
8875 imm_expr
.X_add_number
= 0;
8878 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8879 imm_expr
.X_op
= O_absent
;
8884 as_bad (_("bad char = '%c'\n"), *args
);
8889 /* Args don't match. */
8890 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8891 !strcmp (insn
->name
, insn
[1].name
))
8895 insn_error
= _("illegal operands");
8900 insn_error
= _("illegal operands");
8905 /* This routine assembles an instruction into its binary format when
8906 assembling for the mips16. As a side effect, it sets one of the
8907 global variables imm_reloc or offset_reloc to the type of
8908 relocation to do if one of the operands is an address expression.
8909 It also sets mips16_small and mips16_ext if the user explicitly
8910 requested a small or extended instruction. */
8913 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
8917 struct mips_opcode
*insn
;
8920 unsigned int lastregno
= 0;
8926 mips16_small
= FALSE
;
8929 for (s
= str
; ISLOWER (*s
); ++s
)
8941 if (s
[1] == 't' && s
[2] == ' ')
8944 mips16_small
= TRUE
;
8948 else if (s
[1] == 'e' && s
[2] == ' ')
8957 insn_error
= _("unknown opcode");
8961 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8962 mips16_small
= TRUE
;
8964 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8966 insn_error
= _("unrecognized opcode");
8973 assert (strcmp (insn
->name
, str
) == 0);
8975 create_insn (ip
, insn
);
8976 imm_expr
.X_op
= O_absent
;
8977 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8978 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8979 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8980 imm2_expr
.X_op
= O_absent
;
8981 offset_expr
.X_op
= O_absent
;
8982 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8983 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8984 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8985 for (args
= insn
->args
; 1; ++args
)
8992 /* In this switch statement we call break if we did not find
8993 a match, continue if we did find a match, or return if we
9002 /* Stuff the immediate value in now, if we can. */
9003 if (imm_expr
.X_op
== O_constant
9004 && *imm_reloc
> BFD_RELOC_UNUSED
9005 && insn
->pinfo
!= INSN_MACRO
)
9009 switch (*offset_reloc
)
9011 case BFD_RELOC_MIPS16_HI16_S
:
9012 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9015 case BFD_RELOC_MIPS16_HI16
:
9016 tmp
= imm_expr
.X_add_number
>> 16;
9019 case BFD_RELOC_MIPS16_LO16
:
9020 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9024 case BFD_RELOC_UNUSED
:
9025 tmp
= imm_expr
.X_add_number
;
9031 *offset_reloc
= BFD_RELOC_UNUSED
;
9033 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9034 tmp
, TRUE
, mips16_small
,
9035 mips16_ext
, &ip
->insn_opcode
,
9036 &ip
->use_extend
, &ip
->extend
);
9037 imm_expr
.X_op
= O_absent
;
9038 *imm_reloc
= BFD_RELOC_UNUSED
;
9052 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9055 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9071 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9073 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9100 while (ISDIGIT (*s
));
9103 as_bad (_("invalid register number (%d)"), regno
);
9109 if (s
[1] == 'r' && s
[2] == 'a')
9114 else if (s
[1] == 'f' && s
[2] == 'p')
9119 else if (s
[1] == 's' && s
[2] == 'p')
9124 else if (s
[1] == 'g' && s
[2] == 'p')
9129 else if (s
[1] == 'a' && s
[2] == 't')
9134 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9139 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9144 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9157 if (c
== 'v' || c
== 'w')
9159 regno
= mips16_to_32_reg_map
[lastregno
];
9173 regno
= mips32_to_16_reg_map
[regno
];
9178 regno
= ILLEGAL_REG
;
9183 regno
= ILLEGAL_REG
;
9188 regno
= ILLEGAL_REG
;
9193 if (regno
== AT
&& ! mips_opts
.noat
)
9194 as_warn (_("used $at without \".set noat\""));
9201 if (regno
== ILLEGAL_REG
)
9208 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9212 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9215 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9218 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9224 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9227 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9228 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9238 if (strncmp (s
, "$pc", 3) == 0)
9255 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9258 if (imm_expr
.X_op
!= O_constant
)
9261 ip
->use_extend
= TRUE
;
9266 /* We need to relax this instruction. */
9267 *offset_reloc
= *imm_reloc
;
9268 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9273 *imm_reloc
= BFD_RELOC_UNUSED
;
9281 my_getExpression (&imm_expr
, s
);
9282 if (imm_expr
.X_op
== O_register
)
9284 /* What we thought was an expression turned out to
9287 if (s
[0] == '(' && args
[1] == '(')
9289 /* It looks like the expression was omitted
9290 before a register indirection, which means
9291 that the expression is implicitly zero. We
9292 still set up imm_expr, so that we handle
9293 explicit extensions correctly. */
9294 imm_expr
.X_op
= O_constant
;
9295 imm_expr
.X_add_number
= 0;
9296 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9303 /* We need to relax this instruction. */
9304 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9313 /* We use offset_reloc rather than imm_reloc for the PC
9314 relative operands. This lets macros with both
9315 immediate and address operands work correctly. */
9316 my_getExpression (&offset_expr
, s
);
9318 if (offset_expr
.X_op
== O_register
)
9321 /* We need to relax this instruction. */
9322 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9326 case '6': /* break code */
9327 my_getExpression (&imm_expr
, s
);
9328 check_absolute_expr (ip
, &imm_expr
);
9329 if ((unsigned long) imm_expr
.X_add_number
> 63)
9330 as_warn (_("Invalid value for `%s' (%lu)"),
9332 (unsigned long) imm_expr
.X_add_number
);
9333 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9334 imm_expr
.X_op
= O_absent
;
9338 case 'a': /* 26 bit address */
9339 my_getExpression (&offset_expr
, s
);
9341 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9342 ip
->insn_opcode
<<= 16;
9345 case 'l': /* register list for entry macro */
9346 case 'L': /* register list for exit macro */
9356 int freg
, reg1
, reg2
;
9358 while (*s
== ' ' || *s
== ',')
9362 as_bad (_("can't parse register list"));
9374 while (ISDIGIT (*s
))
9396 as_bad (_("invalid register list"));
9401 while (ISDIGIT (*s
))
9408 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9413 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9418 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9419 mask
|= (reg2
- 3) << 3;
9420 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9421 mask
|= (reg2
- 15) << 1;
9422 else if (reg1
== RA
&& reg2
== RA
)
9426 as_bad (_("invalid register list"));
9430 /* The mask is filled in in the opcode table for the
9431 benefit of the disassembler. We remove it before
9432 applying the actual mask. */
9433 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9434 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9438 case 'e': /* extend code */
9439 my_getExpression (&imm_expr
, s
);
9440 check_absolute_expr (ip
, &imm_expr
);
9441 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9443 as_warn (_("Invalid value for `%s' (%lu)"),
9445 (unsigned long) imm_expr
.X_add_number
);
9446 imm_expr
.X_add_number
&= 0x7ff;
9448 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9449 imm_expr
.X_op
= O_absent
;
9459 /* Args don't match. */
9460 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9461 strcmp (insn
->name
, insn
[1].name
) == 0)
9468 insn_error
= _("illegal operands");
9474 /* This structure holds information we know about a mips16 immediate
9477 struct mips16_immed_operand
9479 /* The type code used in the argument string in the opcode table. */
9481 /* The number of bits in the short form of the opcode. */
9483 /* The number of bits in the extended form of the opcode. */
9485 /* The amount by which the short form is shifted when it is used;
9486 for example, the sw instruction has a shift count of 2. */
9488 /* The amount by which the short form is shifted when it is stored
9489 into the instruction code. */
9491 /* Non-zero if the short form is unsigned. */
9493 /* Non-zero if the extended form is unsigned. */
9495 /* Non-zero if the value is PC relative. */
9499 /* The mips16 immediate operand types. */
9501 static const struct mips16_immed_operand mips16_immed_operands
[] =
9503 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9504 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9505 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9506 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9507 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9508 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9509 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9510 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9511 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9512 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9513 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9514 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9515 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9516 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9517 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9518 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9519 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9520 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9521 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9522 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9523 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9526 #define MIPS16_NUM_IMMED \
9527 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9529 /* Handle a mips16 instruction with an immediate value. This or's the
9530 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9531 whether an extended value is needed; if one is needed, it sets
9532 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9533 If SMALL is true, an unextended opcode was explicitly requested.
9534 If EXT is true, an extended opcode was explicitly requested. If
9535 WARN is true, warn if EXT does not match reality. */
9538 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9539 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9540 unsigned long *insn
, bfd_boolean
*use_extend
,
9541 unsigned short *extend
)
9543 register const struct mips16_immed_operand
*op
;
9544 int mintiny
, maxtiny
;
9545 bfd_boolean needext
;
9547 op
= mips16_immed_operands
;
9548 while (op
->type
!= type
)
9551 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9556 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9559 maxtiny
= 1 << op
->nbits
;
9564 maxtiny
= (1 << op
->nbits
) - 1;
9569 mintiny
= - (1 << (op
->nbits
- 1));
9570 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9573 /* Branch offsets have an implicit 0 in the lowest bit. */
9574 if (type
== 'p' || type
== 'q')
9577 if ((val
& ((1 << op
->shift
) - 1)) != 0
9578 || val
< (mintiny
<< op
->shift
)
9579 || val
> (maxtiny
<< op
->shift
))
9584 if (warn
&& ext
&& ! needext
)
9585 as_warn_where (file
, line
,
9586 _("extended operand requested but not required"));
9587 if (small
&& needext
)
9588 as_bad_where (file
, line
, _("invalid unextended operand value"));
9590 if (small
|| (! ext
&& ! needext
))
9594 *use_extend
= FALSE
;
9595 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9596 insnval
<<= op
->op_shift
;
9601 long minext
, maxext
;
9607 maxext
= (1 << op
->extbits
) - 1;
9611 minext
= - (1 << (op
->extbits
- 1));
9612 maxext
= (1 << (op
->extbits
- 1)) - 1;
9614 if (val
< minext
|| val
> maxext
)
9615 as_bad_where (file
, line
,
9616 _("operand value out of range for instruction"));
9619 if (op
->extbits
== 16)
9621 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9624 else if (op
->extbits
== 15)
9626 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9631 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9635 *extend
= (unsigned short) extval
;
9640 struct percent_op_match
9643 bfd_reloc_code_real_type reloc
;
9646 static const struct percent_op_match mips_percent_op
[] =
9648 {"%lo", BFD_RELOC_LO16
},
9650 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9651 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9652 {"%call16", BFD_RELOC_MIPS_CALL16
},
9653 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9654 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9655 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9656 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9657 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9658 {"%got", BFD_RELOC_MIPS_GOT16
},
9659 {"%gp_rel", BFD_RELOC_GPREL16
},
9660 {"%half", BFD_RELOC_16
},
9661 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9662 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9663 {"%neg", BFD_RELOC_MIPS_SUB
},
9664 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9665 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9666 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9667 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9668 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9669 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9670 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9672 {"%hi", BFD_RELOC_HI16_S
}
9675 static const struct percent_op_match mips16_percent_op
[] =
9677 {"%lo", BFD_RELOC_MIPS16_LO16
},
9678 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9679 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9683 /* Return true if *STR points to a relocation operator. When returning true,
9684 move *STR over the operator and store its relocation code in *RELOC.
9685 Leave both *STR and *RELOC alone when returning false. */
9688 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9690 const struct percent_op_match
*percent_op
;
9693 if (mips_opts
.mips16
)
9695 percent_op
= mips16_percent_op
;
9696 limit
= ARRAY_SIZE (mips16_percent_op
);
9700 percent_op
= mips_percent_op
;
9701 limit
= ARRAY_SIZE (mips_percent_op
);
9704 for (i
= 0; i
< limit
; i
++)
9705 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9707 int len
= strlen (percent_op
[i
].str
);
9709 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9712 *str
+= strlen (percent_op
[i
].str
);
9713 *reloc
= percent_op
[i
].reloc
;
9715 /* Check whether the output BFD supports this relocation.
9716 If not, issue an error and fall back on something safe. */
9717 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9719 as_bad ("relocation %s isn't supported by the current ABI",
9721 *reloc
= BFD_RELOC_UNUSED
;
9729 /* Parse string STR as a 16-bit relocatable operand. Store the
9730 expression in *EP and the relocations in the array starting
9731 at RELOC. Return the number of relocation operators used.
9733 On exit, EXPR_END points to the first character after the expression. */
9736 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9739 bfd_reloc_code_real_type reversed_reloc
[3];
9740 size_t reloc_index
, i
;
9741 int crux_depth
, str_depth
;
9744 /* Search for the start of the main expression, recoding relocations
9745 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9746 of the main expression and with CRUX_DEPTH containing the number
9747 of open brackets at that point. */
9754 crux_depth
= str_depth
;
9756 /* Skip over whitespace and brackets, keeping count of the number
9758 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9763 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9764 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9766 my_getExpression (ep
, crux
);
9769 /* Match every open bracket. */
9770 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9775 as_bad ("unclosed '('");
9779 if (reloc_index
!= 0)
9781 prev_reloc_op_frag
= frag_now
;
9782 for (i
= 0; i
< reloc_index
; i
++)
9783 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9790 my_getExpression (expressionS
*ep
, char *str
)
9795 save_in
= input_line_pointer
;
9796 input_line_pointer
= str
;
9798 expr_end
= input_line_pointer
;
9799 input_line_pointer
= save_in
;
9801 /* If we are in mips16 mode, and this is an expression based on `.',
9802 then we bump the value of the symbol by 1 since that is how other
9803 text symbols are handled. We don't bother to handle complex
9804 expressions, just `.' plus or minus a constant. */
9805 if (mips_opts
.mips16
9806 && ep
->X_op
== O_symbol
9807 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9808 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9809 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9810 && symbol_constant_p (ep
->X_add_symbol
)
9811 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9812 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9815 /* Turn a string in input_line_pointer into a floating point constant
9816 of type TYPE, and store the appropriate bytes in *LITP. The number
9817 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9818 returned, or NULL on OK. */
9821 md_atof (int type
, char *litP
, int *sizeP
)
9824 LITTLENUM_TYPE words
[4];
9840 return _("bad call to md_atof");
9843 t
= atof_ieee (input_line_pointer
, type
, words
);
9845 input_line_pointer
= t
;
9849 if (! target_big_endian
)
9851 for (i
= prec
- 1; i
>= 0; i
--)
9853 md_number_to_chars (litP
, words
[i
], 2);
9859 for (i
= 0; i
< prec
; i
++)
9861 md_number_to_chars (litP
, words
[i
], 2);
9870 md_number_to_chars (char *buf
, valueT val
, int n
)
9872 if (target_big_endian
)
9873 number_to_chars_bigendian (buf
, val
, n
);
9875 number_to_chars_littleendian (buf
, val
, n
);
9879 static int support_64bit_objects(void)
9881 const char **list
, **l
;
9884 list
= bfd_target_list ();
9885 for (l
= list
; *l
!= NULL
; l
++)
9887 /* This is traditional mips */
9888 if (strcmp (*l
, "elf64-tradbigmips") == 0
9889 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9891 if (strcmp (*l
, "elf64-bigmips") == 0
9892 || strcmp (*l
, "elf64-littlemips") == 0)
9899 #endif /* OBJ_ELF */
9901 const char *md_shortopts
= "O::g::G:";
9903 struct option md_longopts
[] =
9905 /* Options which specify architecture. */
9906 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9907 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9908 {"march", required_argument
, NULL
, OPTION_MARCH
},
9909 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9910 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9911 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9912 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9913 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9914 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
9915 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9916 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
9917 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9918 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
9919 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9920 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
9921 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9922 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
9923 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9924 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
9925 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9926 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
9927 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
9928 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
9929 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
9931 /* Options which specify Application Specific Extensions (ASEs). */
9932 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
9933 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
9934 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9935 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
9936 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9937 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
9938 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
9939 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
9940 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
9941 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
9942 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
9943 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
9944 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
9946 /* Old-style architecture options. Don't add more of these. */
9947 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
9948 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
9949 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9950 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
9951 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9952 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
9953 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9954 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
9955 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9956 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
9957 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9958 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
9959 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9960 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
9961 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9962 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
9963 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9965 /* Options which enable bug fixes. */
9966 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
9967 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
9968 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9969 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
9970 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9971 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
9972 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
9973 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
9974 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
9975 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
9977 /* Miscellaneous options. */
9978 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
9979 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
9980 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9981 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9982 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
9983 {"break", no_argument
, NULL
, OPTION_BREAK
},
9984 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9985 #define OPTION_EB (OPTION_MISC_BASE + 2)
9986 {"EB", no_argument
, NULL
, OPTION_EB
},
9987 #define OPTION_EL (OPTION_MISC_BASE + 3)
9988 {"EL", no_argument
, NULL
, OPTION_EL
},
9989 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
9990 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9991 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
9992 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9993 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
9994 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9995 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
9996 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9997 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
9998 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
9999 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10000 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10001 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10002 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10003 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10004 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10005 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10006 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10007 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10008 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10009 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10010 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10011 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10012 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10014 /* ELF-specific options. */
10016 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10017 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10018 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10019 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10020 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10021 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10022 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10023 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10024 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10025 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10026 #define OPTION_32 (OPTION_ELF_BASE + 4)
10027 {"32", no_argument
, NULL
, OPTION_32
},
10028 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10029 {"n32", no_argument
, NULL
, OPTION_N32
},
10030 #define OPTION_64 (OPTION_ELF_BASE + 6)
10031 {"64", no_argument
, NULL
, OPTION_64
},
10032 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10033 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10034 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10035 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10036 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10037 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10038 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10039 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10040 #endif /* OBJ_ELF */
10042 {NULL
, no_argument
, NULL
, 0}
10044 size_t md_longopts_size
= sizeof (md_longopts
);
10046 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10047 NEW_VALUE. Warn if another value was already specified. Note:
10048 we have to defer parsing the -march and -mtune arguments in order
10049 to handle 'from-abi' correctly, since the ABI might be specified
10050 in a later argument. */
10053 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10055 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10056 as_warn (_("A different %s was already specified, is now %s"),
10057 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10060 *string_ptr
= new_value
;
10064 md_parse_option (int c
, char *arg
)
10068 case OPTION_CONSTRUCT_FLOATS
:
10069 mips_disable_float_construction
= 0;
10072 case OPTION_NO_CONSTRUCT_FLOATS
:
10073 mips_disable_float_construction
= 1;
10085 target_big_endian
= 1;
10089 target_big_endian
= 0;
10093 if (arg
&& arg
[1] == '0')
10103 mips_debug
= atoi (arg
);
10104 /* When the MIPS assembler sees -g or -g2, it does not do
10105 optimizations which limit full symbolic debugging. We take
10106 that to be equivalent to -O0. */
10107 if (mips_debug
== 2)
10112 file_mips_isa
= ISA_MIPS1
;
10116 file_mips_isa
= ISA_MIPS2
;
10120 file_mips_isa
= ISA_MIPS3
;
10124 file_mips_isa
= ISA_MIPS4
;
10128 file_mips_isa
= ISA_MIPS5
;
10131 case OPTION_MIPS32
:
10132 file_mips_isa
= ISA_MIPS32
;
10135 case OPTION_MIPS32R2
:
10136 file_mips_isa
= ISA_MIPS32R2
;
10139 case OPTION_MIPS64R2
:
10140 file_mips_isa
= ISA_MIPS64R2
;
10143 case OPTION_MIPS64
:
10144 file_mips_isa
= ISA_MIPS64
;
10148 mips_set_option_string (&mips_tune_string
, arg
);
10152 mips_set_option_string (&mips_arch_string
, arg
);
10156 mips_set_option_string (&mips_arch_string
, "4650");
10157 mips_set_option_string (&mips_tune_string
, "4650");
10160 case OPTION_NO_M4650
:
10164 mips_set_option_string (&mips_arch_string
, "4010");
10165 mips_set_option_string (&mips_tune_string
, "4010");
10168 case OPTION_NO_M4010
:
10172 mips_set_option_string (&mips_arch_string
, "4100");
10173 mips_set_option_string (&mips_tune_string
, "4100");
10176 case OPTION_NO_M4100
:
10180 mips_set_option_string (&mips_arch_string
, "3900");
10181 mips_set_option_string (&mips_tune_string
, "3900");
10184 case OPTION_NO_M3900
:
10188 mips_opts
.ase_mdmx
= 1;
10191 case OPTION_NO_MDMX
:
10192 mips_opts
.ase_mdmx
= 0;
10195 case OPTION_MIPS16
:
10196 mips_opts
.mips16
= 1;
10197 mips_no_prev_insn (FALSE
);
10200 case OPTION_NO_MIPS16
:
10201 mips_opts
.mips16
= 0;
10202 mips_no_prev_insn (FALSE
);
10205 case OPTION_MIPS3D
:
10206 mips_opts
.ase_mips3d
= 1;
10209 case OPTION_NO_MIPS3D
:
10210 mips_opts
.ase_mips3d
= 0;
10213 case OPTION_FIX_VR4120
:
10214 mips_fix_vr4120
= 1;
10217 case OPTION_NO_FIX_VR4120
:
10218 mips_fix_vr4120
= 0;
10221 case OPTION_RELAX_BRANCH
:
10222 mips_relax_branch
= 1;
10225 case OPTION_NO_RELAX_BRANCH
:
10226 mips_relax_branch
= 0;
10229 case OPTION_MSHARED
:
10230 mips_in_shared
= TRUE
;
10233 case OPTION_MNO_SHARED
:
10234 mips_in_shared
= FALSE
;
10237 case OPTION_MSYM32
:
10238 mips_opts
.sym32
= TRUE
;
10241 case OPTION_MNO_SYM32
:
10242 mips_opts
.sym32
= FALSE
;
10246 /* When generating ELF code, we permit -KPIC and -call_shared to
10247 select SVR4_PIC, and -non_shared to select no PIC. This is
10248 intended to be compatible with Irix 5. */
10249 case OPTION_CALL_SHARED
:
10250 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10252 as_bad (_("-call_shared is supported only for ELF format"));
10255 mips_pic
= SVR4_PIC
;
10256 mips_abicalls
= TRUE
;
10257 if (g_switch_seen
&& g_switch_value
!= 0)
10259 as_bad (_("-G may not be used with SVR4 PIC code"));
10262 g_switch_value
= 0;
10265 case OPTION_NON_SHARED
:
10266 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10268 as_bad (_("-non_shared is supported only for ELF format"));
10272 mips_abicalls
= FALSE
;
10275 /* The -xgot option tells the assembler to use 32 offsets when
10276 accessing the got in SVR4_PIC mode. It is for Irix
10281 #endif /* OBJ_ELF */
10284 g_switch_value
= atoi (arg
);
10286 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10288 as_bad (_("-G may not be used with SVR4 PIC code"));
10294 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10297 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10299 as_bad (_("-32 is supported for ELF format only"));
10302 mips_abi
= O32_ABI
;
10306 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10308 as_bad (_("-n32 is supported for ELF format only"));
10311 mips_abi
= N32_ABI
;
10315 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10317 as_bad (_("-64 is supported for ELF format only"));
10320 mips_abi
= N64_ABI
;
10321 if (! support_64bit_objects())
10322 as_fatal (_("No compiled in support for 64 bit object file format"));
10324 #endif /* OBJ_ELF */
10327 file_mips_gp32
= 1;
10331 file_mips_gp32
= 0;
10335 file_mips_fp32
= 1;
10339 file_mips_fp32
= 0;
10344 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10346 as_bad (_("-mabi is supported for ELF format only"));
10349 if (strcmp (arg
, "32") == 0)
10350 mips_abi
= O32_ABI
;
10351 else if (strcmp (arg
, "o64") == 0)
10352 mips_abi
= O64_ABI
;
10353 else if (strcmp (arg
, "n32") == 0)
10354 mips_abi
= N32_ABI
;
10355 else if (strcmp (arg
, "64") == 0)
10357 mips_abi
= N64_ABI
;
10358 if (! support_64bit_objects())
10359 as_fatal (_("No compiled in support for 64 bit object file "
10362 else if (strcmp (arg
, "eabi") == 0)
10363 mips_abi
= EABI_ABI
;
10366 as_fatal (_("invalid abi -mabi=%s"), arg
);
10370 #endif /* OBJ_ELF */
10372 case OPTION_M7000_HILO_FIX
:
10373 mips_7000_hilo_fix
= TRUE
;
10376 case OPTION_MNO_7000_HILO_FIX
:
10377 mips_7000_hilo_fix
= FALSE
;
10381 case OPTION_MDEBUG
:
10382 mips_flag_mdebug
= TRUE
;
10385 case OPTION_NO_MDEBUG
:
10386 mips_flag_mdebug
= FALSE
;
10390 mips_flag_pdr
= TRUE
;
10393 case OPTION_NO_PDR
:
10394 mips_flag_pdr
= FALSE
;
10396 #endif /* OBJ_ELF */
10405 /* Set up globals to generate code for the ISA or processor
10406 described by INFO. */
10409 mips_set_architecture (const struct mips_cpu_info
*info
)
10413 file_mips_arch
= info
->cpu
;
10414 mips_opts
.arch
= info
->cpu
;
10415 mips_opts
.isa
= info
->isa
;
10420 /* Likewise for tuning. */
10423 mips_set_tune (const struct mips_cpu_info
*info
)
10426 mips_tune
= info
->cpu
;
10431 mips_after_parse_args (void)
10433 const struct mips_cpu_info
*arch_info
= 0;
10434 const struct mips_cpu_info
*tune_info
= 0;
10436 /* GP relative stuff not working for PE */
10437 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10439 if (g_switch_seen
&& g_switch_value
!= 0)
10440 as_bad (_("-G not supported in this configuration."));
10441 g_switch_value
= 0;
10444 if (mips_abi
== NO_ABI
)
10445 mips_abi
= MIPS_DEFAULT_ABI
;
10447 /* The following code determines the architecture and register size.
10448 Similar code was added to GCC 3.3 (see override_options() in
10449 config/mips/mips.c). The GAS and GCC code should be kept in sync
10450 as much as possible. */
10452 if (mips_arch_string
!= 0)
10453 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10455 if (file_mips_isa
!= ISA_UNKNOWN
)
10457 /* Handle -mipsN. At this point, file_mips_isa contains the
10458 ISA level specified by -mipsN, while arch_info->isa contains
10459 the -march selection (if any). */
10460 if (arch_info
!= 0)
10462 /* -march takes precedence over -mipsN, since it is more descriptive.
10463 There's no harm in specifying both as long as the ISA levels
10465 if (file_mips_isa
!= arch_info
->isa
)
10466 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10467 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10468 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10471 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10474 if (arch_info
== 0)
10475 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10477 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10478 as_bad ("-march=%s is not compatible with the selected ABI",
10481 mips_set_architecture (arch_info
);
10483 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10484 if (mips_tune_string
!= 0)
10485 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10487 if (tune_info
== 0)
10488 mips_set_tune (arch_info
);
10490 mips_set_tune (tune_info
);
10492 if (file_mips_gp32
>= 0)
10494 /* The user specified the size of the integer registers. Make sure
10495 it agrees with the ABI and ISA. */
10496 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10497 as_bad (_("-mgp64 used with a 32-bit processor"));
10498 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10499 as_bad (_("-mgp32 used with a 64-bit ABI"));
10500 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10501 as_bad (_("-mgp64 used with a 32-bit ABI"));
10505 /* Infer the integer register size from the ABI and processor.
10506 Restrict ourselves to 32-bit registers if that's all the
10507 processor has, or if the ABI cannot handle 64-bit registers. */
10508 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10509 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10512 /* ??? GAS treats single-float processors as though they had 64-bit
10513 float registers (although it complains when double-precision
10514 instructions are used). As things stand, saying they have 32-bit
10515 registers would lead to spurious "register must be even" messages.
10516 So here we assume float registers are always the same size as
10517 integer ones, unless the user says otherwise. */
10518 if (file_mips_fp32
< 0)
10519 file_mips_fp32
= file_mips_gp32
;
10521 /* End of GCC-shared inference code. */
10523 /* This flag is set when we have a 64-bit capable CPU but use only
10524 32-bit wide registers. Note that EABI does not use it. */
10525 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10526 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10527 || mips_abi
== O32_ABI
))
10528 mips_32bitmode
= 1;
10530 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10531 as_bad (_("trap exception not supported at ISA 1"));
10533 /* If the selected architecture includes support for ASEs, enable
10534 generation of code for them. */
10535 if (mips_opts
.mips16
== -1)
10536 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10537 if (mips_opts
.ase_mips3d
== -1)
10538 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10539 if (mips_opts
.ase_mdmx
== -1)
10540 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10542 file_mips_isa
= mips_opts
.isa
;
10543 file_ase_mips16
= mips_opts
.mips16
;
10544 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10545 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10546 mips_opts
.gp32
= file_mips_gp32
;
10547 mips_opts
.fp32
= file_mips_fp32
;
10549 if (mips_flag_mdebug
< 0)
10551 #ifdef OBJ_MAYBE_ECOFF
10552 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10553 mips_flag_mdebug
= 1;
10555 #endif /* OBJ_MAYBE_ECOFF */
10556 mips_flag_mdebug
= 0;
10561 mips_init_after_args (void)
10563 /* initialize opcodes */
10564 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10565 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10569 md_pcrel_from (fixS
*fixP
)
10571 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10572 switch (fixP
->fx_r_type
)
10574 case BFD_RELOC_16_PCREL_S2
:
10575 case BFD_RELOC_MIPS_JMP
:
10576 /* Return the address of the delay slot. */
10583 /* This is called before the symbol table is processed. In order to
10584 work with gcc when using mips-tfile, we must keep all local labels.
10585 However, in other cases, we want to discard them. If we were
10586 called with -g, but we didn't see any debugging information, it may
10587 mean that gcc is smuggling debugging information through to
10588 mips-tfile, in which case we must generate all local labels. */
10591 mips_frob_file_before_adjust (void)
10593 #ifndef NO_ECOFF_DEBUGGING
10594 if (ECOFF_DEBUGGING
10596 && ! ecoff_debugging_seen
)
10597 flag_keep_locals
= 1;
10601 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10602 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10603 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10604 relocation operators.
10606 For our purposes, a %lo() expression matches a %got() or %hi()
10609 (a) it refers to the same symbol; and
10610 (b) the offset applied in the %lo() expression is no lower than
10611 the offset applied in the %got() or %hi().
10613 (b) allows us to cope with code like:
10616 lh $4,%lo(foo+2)($4)
10618 ...which is legal on RELA targets, and has a well-defined behaviour
10619 if the user knows that adding 2 to "foo" will not induce a carry to
10622 When several %lo()s match a particular %got() or %hi(), we use the
10623 following rules to distinguish them:
10625 (1) %lo()s with smaller offsets are a better match than %lo()s with
10628 (2) %lo()s with no matching %got() or %hi() are better than those
10629 that already have a matching %got() or %hi().
10631 (3) later %lo()s are better than earlier %lo()s.
10633 These rules are applied in order.
10635 (1) means, among other things, that %lo()s with identical offsets are
10636 chosen if they exist.
10638 (2) means that we won't associate several high-part relocations with
10639 the same low-part relocation unless there's no alternative. Having
10640 several high parts for the same low part is a GNU extension; this rule
10641 allows careful users to avoid it.
10643 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10644 with the last high-part relocation being at the front of the list.
10645 It therefore makes sense to choose the last matching low-part
10646 relocation, all other things being equal. It's also easier
10647 to code that way. */
10650 mips_frob_file (void)
10652 struct mips_hi_fixup
*l
;
10654 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10656 segment_info_type
*seginfo
;
10657 bfd_boolean matched_lo_p
;
10658 fixS
**hi_pos
, **lo_pos
, **pos
;
10660 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10662 /* If a GOT16 relocation turns out to be against a global symbol,
10663 there isn't supposed to be a matching LO. */
10664 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10665 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10668 /* Check quickly whether the next fixup happens to be a matching %lo. */
10669 if (fixup_has_matching_lo_p (l
->fixp
))
10672 seginfo
= seg_info (l
->seg
);
10674 /* Set HI_POS to the position of this relocation in the chain.
10675 Set LO_POS to the position of the chosen low-part relocation.
10676 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10677 relocation that matches an immediately-preceding high-part
10681 matched_lo_p
= FALSE
;
10682 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10684 if (*pos
== l
->fixp
)
10687 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10688 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10689 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10691 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10693 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10696 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10697 && fixup_has_matching_lo_p (*pos
));
10700 /* If we found a match, remove the high-part relocation from its
10701 current position and insert it before the low-part relocation.
10702 Make the offsets match so that fixup_has_matching_lo_p()
10705 We don't warn about unmatched high-part relocations since some
10706 versions of gcc have been known to emit dead "lui ...%hi(...)"
10708 if (lo_pos
!= NULL
)
10710 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10711 if (l
->fixp
->fx_next
!= *lo_pos
)
10713 *hi_pos
= l
->fixp
->fx_next
;
10714 l
->fixp
->fx_next
= *lo_pos
;
10721 /* We may have combined relocations without symbols in the N32/N64 ABI.
10722 We have to prevent gas from dropping them. */
10725 mips_force_relocation (fixS
*fixp
)
10727 if (generic_force_reloc (fixp
))
10731 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10732 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10733 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10734 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10740 /* This hook is called before a fix is simplified. We don't really
10741 decide whether to skip a fix here. Rather, we turn global symbols
10742 used as branch targets into local symbols, such that they undergo
10743 simplification. We can only do this if the symbol is defined and
10744 it is in the same section as the branch. If this doesn't hold, we
10745 emit a better error message than just saying the relocation is not
10746 valid for the selected object format.
10748 FIXP is the fix-up we're going to try to simplify, SEG is the
10749 segment in which the fix up occurs. The return value should be
10750 non-zero to indicate the fix-up is valid for further
10751 simplifications. */
10754 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10756 /* There's a lot of discussion on whether it should be possible to
10757 use R_MIPS_PC16 to represent branch relocations. The outcome
10758 seems to be that it can, but gas/bfd are very broken in creating
10759 RELA relocations for this, so for now we only accept branches to
10760 symbols in the same section. Anything else is of dubious value,
10761 since there's no guarantee that at link time the symbol would be
10762 in range. Even for branches to local symbols this is arguably
10763 wrong, since it we assume the symbol is not going to be
10764 overridden, which should be possible per ELF library semantics,
10765 but then, there isn't a dynamic relocation that could be used to
10766 this effect, and the target would likely be out of range as well.
10768 Unfortunately, it seems that there is too much code out there
10769 that relies on branches to symbols that are global to be resolved
10770 as if they were local, like the IRIX tools do, so we do it as
10771 well, but with a warning so that people are reminded to fix their
10772 code. If we ever get back to using R_MIPS_PC16 for branch
10773 targets, this entire block should go away (and probably the
10774 whole function). */
10776 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10777 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10778 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10779 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10782 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10785 _("Cannot branch to undefined symbol."));
10786 /* Avoid any further errors about this fixup. */
10789 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10791 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10792 _("Cannot branch to symbol in another section."));
10795 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10797 symbolS
*sym
= fixP
->fx_addsy
;
10799 if (mips_pic
== SVR4_PIC
)
10800 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10801 _("Pretending global symbol used as branch target is local."));
10803 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10804 S_GET_SEGMENT (sym
),
10806 symbol_get_frag (sym
));
10807 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10808 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10809 assert (symbol_resolved_p (sym
));
10810 symbol_mark_resolved (fixP
->fx_addsy
);
10817 /* Apply a fixup to the object file. */
10820 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10824 reloc_howto_type
*howto
;
10826 /* We ignore generic BFD relocations we don't know about. */
10827 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10831 assert (fixP
->fx_size
== 4
10832 || fixP
->fx_r_type
== BFD_RELOC_16
10833 || fixP
->fx_r_type
== BFD_RELOC_64
10834 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10835 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10836 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10837 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10839 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10841 assert (! fixP
->fx_pcrel
);
10843 /* Don't treat parts of a composite relocation as done. There are two
10846 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10847 should nevertheless be emitted if the first part is.
10849 (2) In normal usage, composite relocations are never assembly-time
10850 constants. The easiest way of dealing with the pathological
10851 exceptions is to generate a relocation against STN_UNDEF and
10852 leave everything up to the linker. */
10853 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10856 switch (fixP
->fx_r_type
)
10858 case BFD_RELOC_MIPS_TLS_GD
:
10859 case BFD_RELOC_MIPS_TLS_LDM
:
10860 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10861 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10862 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10863 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10864 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10865 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10868 case BFD_RELOC_MIPS_JMP
:
10869 case BFD_RELOC_MIPS_SHIFT5
:
10870 case BFD_RELOC_MIPS_SHIFT6
:
10871 case BFD_RELOC_MIPS_GOT_DISP
:
10872 case BFD_RELOC_MIPS_GOT_PAGE
:
10873 case BFD_RELOC_MIPS_GOT_OFST
:
10874 case BFD_RELOC_MIPS_SUB
:
10875 case BFD_RELOC_MIPS_INSERT_A
:
10876 case BFD_RELOC_MIPS_INSERT_B
:
10877 case BFD_RELOC_MIPS_DELETE
:
10878 case BFD_RELOC_MIPS_HIGHEST
:
10879 case BFD_RELOC_MIPS_HIGHER
:
10880 case BFD_RELOC_MIPS_SCN_DISP
:
10881 case BFD_RELOC_MIPS_REL16
:
10882 case BFD_RELOC_MIPS_RELGOT
:
10883 case BFD_RELOC_MIPS_JALR
:
10884 case BFD_RELOC_HI16
:
10885 case BFD_RELOC_HI16_S
:
10886 case BFD_RELOC_GPREL16
:
10887 case BFD_RELOC_MIPS_LITERAL
:
10888 case BFD_RELOC_MIPS_CALL16
:
10889 case BFD_RELOC_MIPS_GOT16
:
10890 case BFD_RELOC_GPREL32
:
10891 case BFD_RELOC_MIPS_GOT_HI16
:
10892 case BFD_RELOC_MIPS_GOT_LO16
:
10893 case BFD_RELOC_MIPS_CALL_HI16
:
10894 case BFD_RELOC_MIPS_CALL_LO16
:
10895 case BFD_RELOC_MIPS16_GPREL
:
10896 case BFD_RELOC_MIPS16_HI16
:
10897 case BFD_RELOC_MIPS16_HI16_S
:
10898 assert (! fixP
->fx_pcrel
);
10899 /* Nothing needed to do. The value comes from the reloc entry */
10902 case BFD_RELOC_MIPS16_JMP
:
10903 /* We currently always generate a reloc against a symbol, which
10904 means that we don't want an addend even if the symbol is
10910 /* This is handled like BFD_RELOC_32, but we output a sign
10911 extended value if we are only 32 bits. */
10914 if (8 <= sizeof (valueT
))
10915 md_number_to_chars ((char *) buf
, *valP
, 8);
10920 if ((*valP
& 0x80000000) != 0)
10924 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
10926 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
10932 case BFD_RELOC_RVA
:
10934 /* If we are deleting this reloc entry, we must fill in the
10935 value now. This can happen if we have a .word which is not
10936 resolved when it appears but is later defined. */
10938 md_number_to_chars ((char *) buf
, *valP
, 4);
10942 /* If we are deleting this reloc entry, we must fill in the
10945 md_number_to_chars ((char *) buf
, *valP
, 2);
10948 case BFD_RELOC_LO16
:
10949 case BFD_RELOC_MIPS16_LO16
:
10950 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
10951 may be safe to remove, but if so it's not obvious. */
10952 /* When handling an embedded PIC switch statement, we can wind
10953 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10956 if (*valP
+ 0x8000 > 0xffff)
10957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10958 _("relocation overflow"));
10959 if (target_big_endian
)
10961 md_number_to_chars ((char *) buf
, *valP
, 2);
10965 case BFD_RELOC_16_PCREL_S2
:
10966 if ((*valP
& 0x3) != 0)
10967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10968 _("Branch to odd address (%lx)"), (long) *valP
);
10971 * We need to save the bits in the instruction since fixup_segment()
10972 * might be deleting the relocation entry (i.e., a branch within
10973 * the current segment).
10975 if (! fixP
->fx_done
)
10978 /* update old instruction data */
10979 if (target_big_endian
)
10980 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10982 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10984 if (*valP
+ 0x20000 <= 0x3ffff)
10986 insn
|= (*valP
>> 2) & 0xffff;
10987 md_number_to_chars ((char *) buf
, insn
, 4);
10989 else if (mips_pic
== NO_PIC
10991 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10992 && (fixP
->fx_frag
->fr_address
10993 < text_section
->vma
+ bfd_get_section_size (text_section
))
10994 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10995 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10996 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10998 /* The branch offset is too large. If this is an
10999 unconditional branch, and we are not generating PIC code,
11000 we can convert it to an absolute jump instruction. */
11001 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11002 insn
= 0x0c000000; /* jal */
11004 insn
= 0x08000000; /* j */
11005 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11007 fixP
->fx_addsy
= section_symbol (text_section
);
11008 *valP
+= md_pcrel_from (fixP
);
11009 md_number_to_chars ((char *) buf
, insn
, 4);
11013 /* If we got here, we have branch-relaxation disabled,
11014 and there's nothing we can do to fix this instruction
11015 without turning it into a longer sequence. */
11016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11017 _("Branch out of range"));
11021 case BFD_RELOC_VTABLE_INHERIT
:
11024 && !S_IS_DEFINED (fixP
->fx_addsy
)
11025 && !S_IS_WEAK (fixP
->fx_addsy
))
11026 S_SET_WEAK (fixP
->fx_addsy
);
11029 case BFD_RELOC_VTABLE_ENTRY
:
11037 /* Remember value for tc_gen_reloc. */
11038 fixP
->fx_addnumber
= *valP
;
11048 name
= input_line_pointer
;
11049 c
= get_symbol_end ();
11050 p
= (symbolS
*) symbol_find_or_make (name
);
11051 *input_line_pointer
= c
;
11055 /* Align the current frag to a given power of two. The MIPS assembler
11056 also automatically adjusts any preceding label. */
11059 mips_align (int to
, int fill
, symbolS
*label
)
11061 mips_emit_delays (FALSE
);
11062 frag_align (to
, fill
, 0);
11063 record_alignment (now_seg
, to
);
11066 assert (S_GET_SEGMENT (label
) == now_seg
);
11067 symbol_set_frag (label
, frag_now
);
11068 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11072 /* Align to a given power of two. .align 0 turns off the automatic
11073 alignment used by the data creating pseudo-ops. */
11076 s_align (int x ATTRIBUTE_UNUSED
)
11079 register long temp_fill
;
11080 long max_alignment
= 15;
11084 o Note that the assembler pulls down any immediately preceding label
11085 to the aligned address.
11086 o It's not documented but auto alignment is reinstated by
11087 a .align pseudo instruction.
11088 o Note also that after auto alignment is turned off the mips assembler
11089 issues an error on attempt to assemble an improperly aligned data item.
11094 temp
= get_absolute_expression ();
11095 if (temp
> max_alignment
)
11096 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11099 as_warn (_("Alignment negative: 0 assumed."));
11102 if (*input_line_pointer
== ',')
11104 ++input_line_pointer
;
11105 temp_fill
= get_absolute_expression ();
11112 mips_align (temp
, (int) temp_fill
,
11113 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11120 demand_empty_rest_of_line ();
11124 mips_flush_pending_output (void)
11126 mips_emit_delays (FALSE
);
11127 mips_clear_insn_labels ();
11131 s_change_sec (int sec
)
11136 /* The ELF backend needs to know that we are changing sections, so
11137 that .previous works correctly. We could do something like check
11138 for an obj_section_change_hook macro, but that might be confusing
11139 as it would not be appropriate to use it in the section changing
11140 functions in read.c, since obj-elf.c intercepts those. FIXME:
11141 This should be cleaner, somehow. */
11142 obj_elf_section_change_hook ();
11145 mips_emit_delays (FALSE
);
11155 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11156 demand_empty_rest_of_line ();
11160 seg
= subseg_new (RDATA_SECTION_NAME
,
11161 (subsegT
) get_absolute_expression ());
11162 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11164 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11165 | SEC_READONLY
| SEC_RELOC
11167 if (strcmp (TARGET_OS
, "elf") != 0)
11168 record_alignment (seg
, 4);
11170 demand_empty_rest_of_line ();
11174 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11175 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11177 bfd_set_section_flags (stdoutput
, seg
,
11178 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11179 if (strcmp (TARGET_OS
, "elf") != 0)
11180 record_alignment (seg
, 4);
11182 demand_empty_rest_of_line ();
11190 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11193 char *section_name
;
11198 int section_entry_size
;
11199 int section_alignment
;
11201 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11204 section_name
= input_line_pointer
;
11205 c
= get_symbol_end ();
11207 next_c
= *(input_line_pointer
+ 1);
11209 /* Do we have .section Name<,"flags">? */
11210 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11212 /* just after name is now '\0'. */
11213 *input_line_pointer
= c
;
11214 input_line_pointer
= section_name
;
11215 obj_elf_section (ignore
);
11218 input_line_pointer
++;
11220 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11222 section_type
= get_absolute_expression ();
11225 if (*input_line_pointer
++ == ',')
11226 section_flag
= get_absolute_expression ();
11229 if (*input_line_pointer
++ == ',')
11230 section_entry_size
= get_absolute_expression ();
11232 section_entry_size
= 0;
11233 if (*input_line_pointer
++ == ',')
11234 section_alignment
= get_absolute_expression ();
11236 section_alignment
= 0;
11238 section_name
= xstrdup (section_name
);
11240 /* When using the generic form of .section (as implemented by obj-elf.c),
11241 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11242 traditionally had to fall back on the more common @progbits instead.
11244 There's nothing really harmful in this, since bfd will correct
11245 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11246 means that, for backwards compatibiltiy, the special_section entries
11247 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11249 Even so, we shouldn't force users of the MIPS .section syntax to
11250 incorrectly label the sections as SHT_PROGBITS. The best compromise
11251 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11252 generic type-checking code. */
11253 if (section_type
== SHT_MIPS_DWARF
)
11254 section_type
= SHT_PROGBITS
;
11256 obj_elf_change_section (section_name
, section_type
, section_flag
,
11257 section_entry_size
, 0, 0, 0);
11259 if (now_seg
->name
!= section_name
)
11260 free (section_name
);
11261 #endif /* OBJ_ELF */
11265 mips_enable_auto_align (void)
11271 s_cons (int log_size
)
11275 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11276 mips_emit_delays (FALSE
);
11277 if (log_size
> 0 && auto_align
)
11278 mips_align (log_size
, 0, label
);
11279 mips_clear_insn_labels ();
11280 cons (1 << log_size
);
11284 s_float_cons (int type
)
11288 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11290 mips_emit_delays (FALSE
);
11295 mips_align (3, 0, label
);
11297 mips_align (2, 0, label
);
11300 mips_clear_insn_labels ();
11305 /* Handle .globl. We need to override it because on Irix 5 you are
11308 where foo is an undefined symbol, to mean that foo should be
11309 considered to be the address of a function. */
11312 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11319 name
= input_line_pointer
;
11320 c
= get_symbol_end ();
11321 symbolP
= symbol_find_or_make (name
);
11322 *input_line_pointer
= c
;
11323 SKIP_WHITESPACE ();
11325 /* On Irix 5, every global symbol that is not explicitly labelled as
11326 being a function is apparently labelled as being an object. */
11329 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11334 secname
= input_line_pointer
;
11335 c
= get_symbol_end ();
11336 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11338 as_bad (_("%s: no such section"), secname
);
11339 *input_line_pointer
= c
;
11341 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11342 flag
= BSF_FUNCTION
;
11345 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11347 S_SET_EXTERNAL (symbolP
);
11348 demand_empty_rest_of_line ();
11352 s_option (int x ATTRIBUTE_UNUSED
)
11357 opt
= input_line_pointer
;
11358 c
= get_symbol_end ();
11362 /* FIXME: What does this mean? */
11364 else if (strncmp (opt
, "pic", 3) == 0)
11368 i
= atoi (opt
+ 3);
11373 mips_pic
= SVR4_PIC
;
11374 mips_abicalls
= TRUE
;
11377 as_bad (_(".option pic%d not supported"), i
);
11379 if (mips_pic
== SVR4_PIC
)
11381 if (g_switch_seen
&& g_switch_value
!= 0)
11382 as_warn (_("-G may not be used with SVR4 PIC code"));
11383 g_switch_value
= 0;
11384 bfd_set_gp_size (stdoutput
, 0);
11388 as_warn (_("Unrecognized option \"%s\""), opt
);
11390 *input_line_pointer
= c
;
11391 demand_empty_rest_of_line ();
11394 /* This structure is used to hold a stack of .set values. */
11396 struct mips_option_stack
11398 struct mips_option_stack
*next
;
11399 struct mips_set_options options
;
11402 static struct mips_option_stack
*mips_opts_stack
;
11404 /* Handle the .set pseudo-op. */
11407 s_mipsset (int x ATTRIBUTE_UNUSED
)
11409 char *name
= input_line_pointer
, ch
;
11411 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11412 ++input_line_pointer
;
11413 ch
= *input_line_pointer
;
11414 *input_line_pointer
= '\0';
11416 if (strcmp (name
, "reorder") == 0)
11418 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11420 /* If we still have pending nops, we can discard them. The
11421 usual nop handling will insert any that are still
11423 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11424 * (mips_opts
.mips16
? 2 : 4));
11425 prev_nop_frag
= NULL
;
11427 mips_opts
.noreorder
= 0;
11429 else if (strcmp (name
, "noreorder") == 0)
11431 mips_emit_delays (TRUE
);
11432 mips_opts
.noreorder
= 1;
11433 mips_any_noreorder
= 1;
11435 else if (strcmp (name
, "at") == 0)
11437 mips_opts
.noat
= 0;
11439 else if (strcmp (name
, "noat") == 0)
11441 mips_opts
.noat
= 1;
11443 else if (strcmp (name
, "macro") == 0)
11445 mips_opts
.warn_about_macros
= 0;
11447 else if (strcmp (name
, "nomacro") == 0)
11449 if (mips_opts
.noreorder
== 0)
11450 as_bad (_("`noreorder' must be set before `nomacro'"));
11451 mips_opts
.warn_about_macros
= 1;
11453 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11455 mips_opts
.nomove
= 0;
11457 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11459 mips_opts
.nomove
= 1;
11461 else if (strcmp (name
, "bopt") == 0)
11463 mips_opts
.nobopt
= 0;
11465 else if (strcmp (name
, "nobopt") == 0)
11467 mips_opts
.nobopt
= 1;
11469 else if (strcmp (name
, "mips16") == 0
11470 || strcmp (name
, "MIPS-16") == 0)
11471 mips_opts
.mips16
= 1;
11472 else if (strcmp (name
, "nomips16") == 0
11473 || strcmp (name
, "noMIPS-16") == 0)
11474 mips_opts
.mips16
= 0;
11475 else if (strcmp (name
, "mips3d") == 0)
11476 mips_opts
.ase_mips3d
= 1;
11477 else if (strcmp (name
, "nomips3d") == 0)
11478 mips_opts
.ase_mips3d
= 0;
11479 else if (strcmp (name
, "mdmx") == 0)
11480 mips_opts
.ase_mdmx
= 1;
11481 else if (strcmp (name
, "nomdmx") == 0)
11482 mips_opts
.ase_mdmx
= 0;
11483 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11487 /* Permit the user to change the ISA and architecture on the fly.
11488 Needless to say, misuse can cause serious problems. */
11489 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11492 mips_opts
.isa
= file_mips_isa
;
11493 mips_opts
.arch
= file_mips_arch
;
11495 else if (strncmp (name
, "arch=", 5) == 0)
11497 const struct mips_cpu_info
*p
;
11499 p
= mips_parse_cpu("internal use", name
+ 5);
11501 as_bad (_("unknown architecture %s"), name
+ 5);
11504 mips_opts
.arch
= p
->cpu
;
11505 mips_opts
.isa
= p
->isa
;
11508 else if (strncmp (name
, "mips", 4) == 0)
11510 const struct mips_cpu_info
*p
;
11512 p
= mips_parse_cpu("internal use", name
);
11514 as_bad (_("unknown ISA level %s"), name
+ 4);
11517 mips_opts
.arch
= p
->cpu
;
11518 mips_opts
.isa
= p
->isa
;
11522 as_bad (_("unknown ISA or architecture %s"), name
);
11524 switch (mips_opts
.isa
)
11532 mips_opts
.gp32
= 1;
11533 mips_opts
.fp32
= 1;
11540 mips_opts
.gp32
= 0;
11541 mips_opts
.fp32
= 0;
11544 as_bad (_("unknown ISA level %s"), name
+ 4);
11549 mips_opts
.gp32
= file_mips_gp32
;
11550 mips_opts
.fp32
= file_mips_fp32
;
11553 else if (strcmp (name
, "autoextend") == 0)
11554 mips_opts
.noautoextend
= 0;
11555 else if (strcmp (name
, "noautoextend") == 0)
11556 mips_opts
.noautoextend
= 1;
11557 else if (strcmp (name
, "push") == 0)
11559 struct mips_option_stack
*s
;
11561 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11562 s
->next
= mips_opts_stack
;
11563 s
->options
= mips_opts
;
11564 mips_opts_stack
= s
;
11566 else if (strcmp (name
, "pop") == 0)
11568 struct mips_option_stack
*s
;
11570 s
= mips_opts_stack
;
11572 as_bad (_(".set pop with no .set push"));
11575 /* If we're changing the reorder mode we need to handle
11576 delay slots correctly. */
11577 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11578 mips_emit_delays (TRUE
);
11579 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11581 if (prev_nop_frag
!= NULL
)
11583 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11584 * (mips_opts
.mips16
? 2 : 4));
11585 prev_nop_frag
= NULL
;
11589 mips_opts
= s
->options
;
11590 mips_opts_stack
= s
->next
;
11594 else if (strcmp (name
, "sym32") == 0)
11595 mips_opts
.sym32
= TRUE
;
11596 else if (strcmp (name
, "nosym32") == 0)
11597 mips_opts
.sym32
= FALSE
;
11600 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11602 *input_line_pointer
= ch
;
11603 demand_empty_rest_of_line ();
11606 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11607 .option pic2. It means to generate SVR4 PIC calls. */
11610 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11612 mips_pic
= SVR4_PIC
;
11613 mips_abicalls
= TRUE
;
11615 if (g_switch_seen
&& g_switch_value
!= 0)
11616 as_warn (_("-G may not be used with SVR4 PIC code"));
11617 g_switch_value
= 0;
11619 bfd_set_gp_size (stdoutput
, 0);
11620 demand_empty_rest_of_line ();
11623 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11624 PIC code. It sets the $gp register for the function based on the
11625 function address, which is in the register named in the argument.
11626 This uses a relocation against _gp_disp, which is handled specially
11627 by the linker. The result is:
11628 lui $gp,%hi(_gp_disp)
11629 addiu $gp,$gp,%lo(_gp_disp)
11630 addu $gp,$gp,.cpload argument
11631 The .cpload argument is normally $25 == $t9.
11633 The -mno-shared option changes this to:
11634 lui $gp,%hi(__gnu_local_gp)
11635 addiu $gp,$gp,%lo(__gnu_local_gp)
11636 and the argument is ignored. This saves an instruction, but the
11637 resulting code is not position independent; it uses an absolute
11638 address for __gnu_local_gp. Thus code assembled with -mno-shared
11639 can go into an ordinary executable, but not into a shared library. */
11642 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11648 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11649 .cpload is ignored. */
11650 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11656 /* .cpload should be in a .set noreorder section. */
11657 if (mips_opts
.noreorder
== 0)
11658 as_warn (_(".cpload not in noreorder section"));
11660 reg
= tc_get_register (0);
11662 /* If we need to produce a 64-bit address, we are better off using
11663 the default instruction sequence. */
11664 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11666 ex
.X_op
= O_symbol
;
11667 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11669 ex
.X_op_symbol
= NULL
;
11670 ex
.X_add_number
= 0;
11672 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11673 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11676 macro_build_lui (&ex
, mips_gp_register
);
11677 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11678 mips_gp_register
, BFD_RELOC_LO16
);
11680 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11681 mips_gp_register
, reg
);
11684 demand_empty_rest_of_line ();
11687 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11688 .cpsetup $reg1, offset|$reg2, label
11690 If offset is given, this results in:
11691 sd $gp, offset($sp)
11692 lui $gp, %hi(%neg(%gp_rel(label)))
11693 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11694 daddu $gp, $gp, $reg1
11696 If $reg2 is given, this results in:
11697 daddu $reg2, $gp, $0
11698 lui $gp, %hi(%neg(%gp_rel(label)))
11699 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11700 daddu $gp, $gp, $reg1
11701 $reg1 is normally $25 == $t9.
11703 The -mno-shared option replaces the last three instructions with
11705 addiu $gp,$gp,%lo(_gp)
11709 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11711 expressionS ex_off
;
11712 expressionS ex_sym
;
11715 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11716 We also need NewABI support. */
11717 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11723 reg1
= tc_get_register (0);
11724 SKIP_WHITESPACE ();
11725 if (*input_line_pointer
!= ',')
11727 as_bad (_("missing argument separator ',' for .cpsetup"));
11731 ++input_line_pointer
;
11732 SKIP_WHITESPACE ();
11733 if (*input_line_pointer
== '$')
11735 mips_cpreturn_register
= tc_get_register (0);
11736 mips_cpreturn_offset
= -1;
11740 mips_cpreturn_offset
= get_absolute_expression ();
11741 mips_cpreturn_register
= -1;
11743 SKIP_WHITESPACE ();
11744 if (*input_line_pointer
!= ',')
11746 as_bad (_("missing argument separator ',' for .cpsetup"));
11750 ++input_line_pointer
;
11751 SKIP_WHITESPACE ();
11752 expression (&ex_sym
);
11755 if (mips_cpreturn_register
== -1)
11757 ex_off
.X_op
= O_constant
;
11758 ex_off
.X_add_symbol
= NULL
;
11759 ex_off
.X_op_symbol
= NULL
;
11760 ex_off
.X_add_number
= mips_cpreturn_offset
;
11762 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11763 BFD_RELOC_LO16
, SP
);
11766 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11767 mips_gp_register
, 0);
11769 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11771 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11772 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11775 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11776 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11777 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11779 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11780 mips_gp_register
, reg1
);
11786 ex
.X_op
= O_symbol
;
11787 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11788 ex
.X_op_symbol
= NULL
;
11789 ex
.X_add_number
= 0;
11791 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11792 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11794 macro_build_lui (&ex
, mips_gp_register
);
11795 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11796 mips_gp_register
, BFD_RELOC_LO16
);
11801 demand_empty_rest_of_line ();
11805 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11807 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11808 .cplocal is ignored. */
11809 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11815 mips_gp_register
= tc_get_register (0);
11816 demand_empty_rest_of_line ();
11819 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11820 offset from $sp. The offset is remembered, and after making a PIC
11821 call $gp is restored from that location. */
11824 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11828 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11829 .cprestore is ignored. */
11830 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11836 mips_cprestore_offset
= get_absolute_expression ();
11837 mips_cprestore_valid
= 1;
11839 ex
.X_op
= O_constant
;
11840 ex
.X_add_symbol
= NULL
;
11841 ex
.X_op_symbol
= NULL
;
11842 ex
.X_add_number
= mips_cprestore_offset
;
11845 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11846 SP
, HAVE_64BIT_ADDRESSES
);
11849 demand_empty_rest_of_line ();
11852 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11853 was given in the preceding .cpsetup, it results in:
11854 ld $gp, offset($sp)
11856 If a register $reg2 was given there, it results in:
11857 daddu $gp, $reg2, $0
11860 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11864 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11865 We also need NewABI support. */
11866 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11873 if (mips_cpreturn_register
== -1)
11875 ex
.X_op
= O_constant
;
11876 ex
.X_add_symbol
= NULL
;
11877 ex
.X_op_symbol
= NULL
;
11878 ex
.X_add_number
= mips_cpreturn_offset
;
11880 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11883 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11884 mips_cpreturn_register
, 0);
11887 demand_empty_rest_of_line ();
11890 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11891 code. It sets the offset to use in gp_rel relocations. */
11894 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11896 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11897 We also need NewABI support. */
11898 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11904 mips_gprel_offset
= get_absolute_expression ();
11906 demand_empty_rest_of_line ();
11909 /* Handle the .gpword pseudo-op. This is used when generating PIC
11910 code. It generates a 32 bit GP relative reloc. */
11913 s_gpword (int ignore ATTRIBUTE_UNUSED
)
11919 /* When not generating PIC code, this is treated as .word. */
11920 if (mips_pic
!= SVR4_PIC
)
11926 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11927 mips_emit_delays (TRUE
);
11929 mips_align (2, 0, label
);
11930 mips_clear_insn_labels ();
11934 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11936 as_bad (_("Unsupported use of .gpword"));
11937 ignore_rest_of_line ();
11941 md_number_to_chars (p
, 0, 4);
11942 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11943 BFD_RELOC_GPREL32
);
11945 demand_empty_rest_of_line ();
11949 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
11955 /* When not generating PIC code, this is treated as .dword. */
11956 if (mips_pic
!= SVR4_PIC
)
11962 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11963 mips_emit_delays (TRUE
);
11965 mips_align (3, 0, label
);
11966 mips_clear_insn_labels ();
11970 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11972 as_bad (_("Unsupported use of .gpdword"));
11973 ignore_rest_of_line ();
11977 md_number_to_chars (p
, 0, 8);
11978 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
11979 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
11981 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
11982 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
11983 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
11985 demand_empty_rest_of_line ();
11988 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11989 tables in SVR4 PIC code. */
11992 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
11996 /* This is ignored when not generating SVR4 PIC code. */
11997 if (mips_pic
!= SVR4_PIC
)
12003 /* Add $gp to the register named as an argument. */
12005 reg
= tc_get_register (0);
12006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12009 demand_empty_rest_of_line ();
12012 /* Handle the .insn pseudo-op. This marks instruction labels in
12013 mips16 mode. This permits the linker to handle them specially,
12014 such as generating jalx instructions when needed. We also make
12015 them odd for the duration of the assembly, in order to generate the
12016 right sort of code. We will make them even in the adjust_symtab
12017 routine, while leaving them marked. This is convenient for the
12018 debugger and the disassembler. The linker knows to make them odd
12022 s_insn (int ignore ATTRIBUTE_UNUSED
)
12024 mips16_mark_labels ();
12026 demand_empty_rest_of_line ();
12029 /* Handle a .stabn directive. We need these in order to mark a label
12030 as being a mips16 text label correctly. Sometimes the compiler
12031 will emit a label, followed by a .stabn, and then switch sections.
12032 If the label and .stabn are in mips16 mode, then the label is
12033 really a mips16 text label. */
12036 s_mips_stab (int type
)
12039 mips16_mark_labels ();
12044 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12048 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12055 name
= input_line_pointer
;
12056 c
= get_symbol_end ();
12057 symbolP
= symbol_find_or_make (name
);
12058 S_SET_WEAK (symbolP
);
12059 *input_line_pointer
= c
;
12061 SKIP_WHITESPACE ();
12063 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12065 if (S_IS_DEFINED (symbolP
))
12067 as_bad ("ignoring attempt to redefine symbol %s",
12068 S_GET_NAME (symbolP
));
12069 ignore_rest_of_line ();
12073 if (*input_line_pointer
== ',')
12075 ++input_line_pointer
;
12076 SKIP_WHITESPACE ();
12080 if (exp
.X_op
!= O_symbol
)
12082 as_bad ("bad .weakext directive");
12083 ignore_rest_of_line ();
12086 symbol_set_value_expression (symbolP
, &exp
);
12089 demand_empty_rest_of_line ();
12092 /* Parse a register string into a number. Called from the ECOFF code
12093 to parse .frame. The argument is non-zero if this is the frame
12094 register, so that we can record it in mips_frame_reg. */
12097 tc_get_register (int frame
)
12101 SKIP_WHITESPACE ();
12102 if (*input_line_pointer
++ != '$')
12104 as_warn (_("expected `$'"));
12107 else if (ISDIGIT (*input_line_pointer
))
12109 reg
= get_absolute_expression ();
12110 if (reg
< 0 || reg
>= 32)
12112 as_warn (_("Bad register number"));
12118 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12121 input_line_pointer
+= 2;
12123 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12126 input_line_pointer
+= 2;
12128 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12131 input_line_pointer
+= 2;
12133 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12136 input_line_pointer
+= 2;
12138 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12141 input_line_pointer
+= 2;
12143 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12146 input_line_pointer
+= 3;
12148 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12151 input_line_pointer
+= 3;
12153 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12156 input_line_pointer
+= 4;
12160 as_warn (_("Unrecognized register name"));
12162 while (ISALNUM(*input_line_pointer
))
12163 input_line_pointer
++;
12168 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12169 mips_frame_reg_valid
= 1;
12170 mips_cprestore_valid
= 0;
12176 md_section_align (asection
*seg
, valueT addr
)
12178 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12181 /* We don't need to align ELF sections to the full alignment.
12182 However, Irix 5 may prefer that we align them at least to a 16
12183 byte boundary. We don't bother to align the sections if we are
12184 targeted for an embedded system. */
12185 if (strcmp (TARGET_OS
, "elf") == 0)
12191 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12194 /* Utility routine, called from above as well. If called while the
12195 input file is still being read, it's only an approximation. (For
12196 example, a symbol may later become defined which appeared to be
12197 undefined earlier.) */
12200 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12205 if (g_switch_value
> 0)
12207 const char *symname
;
12210 /* Find out whether this symbol can be referenced off the $gp
12211 register. It can be if it is smaller than the -G size or if
12212 it is in the .sdata or .sbss section. Certain symbols can
12213 not be referenced off the $gp, although it appears as though
12215 symname
= S_GET_NAME (sym
);
12216 if (symname
!= (const char *) NULL
12217 && (strcmp (symname
, "eprol") == 0
12218 || strcmp (symname
, "etext") == 0
12219 || strcmp (symname
, "_gp") == 0
12220 || strcmp (symname
, "edata") == 0
12221 || strcmp (symname
, "_fbss") == 0
12222 || strcmp (symname
, "_fdata") == 0
12223 || strcmp (symname
, "_ftext") == 0
12224 || strcmp (symname
, "end") == 0
12225 || strcmp (symname
, "_gp_disp") == 0))
12227 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12229 #ifndef NO_ECOFF_DEBUGGING
12230 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12231 && (symbol_get_obj (sym
)->ecoff_extern_size
12232 <= g_switch_value
))
12234 /* We must defer this decision until after the whole
12235 file has been read, since there might be a .extern
12236 after the first use of this symbol. */
12237 || (before_relaxing
12238 #ifndef NO_ECOFF_DEBUGGING
12239 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12241 && S_GET_VALUE (sym
) == 0)
12242 || (S_GET_VALUE (sym
) != 0
12243 && S_GET_VALUE (sym
) <= g_switch_value
)))
12247 const char *segname
;
12249 segname
= segment_name (S_GET_SEGMENT (sym
));
12250 assert (strcmp (segname
, ".lit8") != 0
12251 && strcmp (segname
, ".lit4") != 0);
12252 change
= (strcmp (segname
, ".sdata") != 0
12253 && strcmp (segname
, ".sbss") != 0
12254 && strncmp (segname
, ".sdata.", 7) != 0
12255 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12260 /* We are not optimizing for the $gp register. */
12265 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12268 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12271 bfd_boolean linkonce
;
12273 /* Handle the case of a symbol equated to another symbol. */
12274 while (symbol_equated_reloc_p (sym
))
12278 /* It's possible to get a loop here in a badly written
12280 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12286 symsec
= S_GET_SEGMENT (sym
);
12288 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12290 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12292 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12296 /* The GNU toolchain uses an extension for ELF: a section
12297 beginning with the magic string .gnu.linkonce is a linkonce
12299 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12300 sizeof ".gnu.linkonce" - 1) == 0)
12304 /* This must duplicate the test in adjust_reloc_syms. */
12305 return (symsec
!= &bfd_und_section
12306 && symsec
!= &bfd_abs_section
12307 && ! bfd_is_com_section (symsec
)
12310 /* A global or weak symbol is treated as external. */
12311 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12312 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12318 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12319 extended opcode. SEC is the section the frag is in. */
12322 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12325 register const struct mips16_immed_operand
*op
;
12327 int mintiny
, maxtiny
;
12331 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12333 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12336 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12337 op
= mips16_immed_operands
;
12338 while (op
->type
!= type
)
12341 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12346 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12349 maxtiny
= 1 << op
->nbits
;
12354 maxtiny
= (1 << op
->nbits
) - 1;
12359 mintiny
= - (1 << (op
->nbits
- 1));
12360 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12363 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12364 val
= S_GET_VALUE (fragp
->fr_symbol
);
12365 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12371 /* We won't have the section when we are called from
12372 mips_relax_frag. However, we will always have been called
12373 from md_estimate_size_before_relax first. If this is a
12374 branch to a different section, we mark it as such. If SEC is
12375 NULL, and the frag is not marked, then it must be a branch to
12376 the same section. */
12379 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12384 /* Must have been called from md_estimate_size_before_relax. */
12387 fragp
->fr_subtype
=
12388 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12390 /* FIXME: We should support this, and let the linker
12391 catch branches and loads that are out of range. */
12392 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12393 _("unsupported PC relative reference to different section"));
12397 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12398 /* Assume non-extended on the first relaxation pass.
12399 The address we have calculated will be bogus if this is
12400 a forward branch to another frag, as the forward frag
12401 will have fr_address == 0. */
12405 /* In this case, we know for sure that the symbol fragment is in
12406 the same section. If the relax_marker of the symbol fragment
12407 differs from the relax_marker of this fragment, we have not
12408 yet adjusted the symbol fragment fr_address. We want to add
12409 in STRETCH in order to get a better estimate of the address.
12410 This particularly matters because of the shift bits. */
12412 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12416 /* Adjust stretch for any alignment frag. Note that if have
12417 been expanding the earlier code, the symbol may be
12418 defined in what appears to be an earlier frag. FIXME:
12419 This doesn't handle the fr_subtype field, which specifies
12420 a maximum number of bytes to skip when doing an
12422 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12424 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12427 stretch
= - ((- stretch
)
12428 & ~ ((1 << (int) f
->fr_offset
) - 1));
12430 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12439 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12441 /* The base address rules are complicated. The base address of
12442 a branch is the following instruction. The base address of a
12443 PC relative load or add is the instruction itself, but if it
12444 is in a delay slot (in which case it can not be extended) use
12445 the address of the instruction whose delay slot it is in. */
12446 if (type
== 'p' || type
== 'q')
12450 /* If we are currently assuming that this frag should be
12451 extended, then, the current address is two bytes
12453 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12456 /* Ignore the low bit in the target, since it will be set
12457 for a text label. */
12458 if ((val
& 1) != 0)
12461 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12463 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12466 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12468 /* Branch offsets have an implicit 0 in the lowest bit. */
12469 if (type
== 'p' || type
== 'q')
12472 /* If any of the shifted bits are set, we must use an extended
12473 opcode. If the address depends on the size of this
12474 instruction, this can lead to a loop, so we arrange to always
12475 use an extended opcode. We only check this when we are in
12476 the main relaxation loop, when SEC is NULL. */
12477 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12479 fragp
->fr_subtype
=
12480 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12484 /* If we are about to mark a frag as extended because the value
12485 is precisely maxtiny + 1, then there is a chance of an
12486 infinite loop as in the following code:
12491 In this case when the la is extended, foo is 0x3fc bytes
12492 away, so the la can be shrunk, but then foo is 0x400 away, so
12493 the la must be extended. To avoid this loop, we mark the
12494 frag as extended if it was small, and is about to become
12495 extended with a value of maxtiny + 1. */
12496 if (val
== ((maxtiny
+ 1) << op
->shift
)
12497 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12500 fragp
->fr_subtype
=
12501 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12505 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12506 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12508 if ((val
& ((1 << op
->shift
) - 1)) != 0
12509 || val
< (mintiny
<< op
->shift
)
12510 || val
> (maxtiny
<< op
->shift
))
12516 /* Compute the length of a branch sequence, and adjust the
12517 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12518 worst-case length is computed, with UPDATE being used to indicate
12519 whether an unconditional (-1), branch-likely (+1) or regular (0)
12520 branch is to be computed. */
12522 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12524 bfd_boolean toofar
;
12528 && S_IS_DEFINED (fragp
->fr_symbol
)
12529 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12534 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12536 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12540 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12543 /* If the symbol is not defined or it's in a different segment,
12544 assume the user knows what's going on and emit a short
12550 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12552 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12553 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12554 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12560 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12563 if (mips_pic
!= NO_PIC
)
12565 /* Additional space for PIC loading of target address. */
12567 if (mips_opts
.isa
== ISA_MIPS1
)
12568 /* Additional space for $at-stabilizing nop. */
12572 /* If branch is conditional. */
12573 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12580 /* Estimate the size of a frag before relaxing. Unless this is the
12581 mips16, we are not really relaxing here, and the final size is
12582 encoded in the subtype information. For the mips16, we have to
12583 decide whether we are using an extended opcode or not. */
12586 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12590 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12593 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12595 return fragp
->fr_var
;
12598 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12599 /* We don't want to modify the EXTENDED bit here; it might get us
12600 into infinite loops. We change it only in mips_relax_frag(). */
12601 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12603 if (mips_pic
== NO_PIC
)
12604 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12605 else if (mips_pic
== SVR4_PIC
)
12606 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12612 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12613 return -RELAX_FIRST (fragp
->fr_subtype
);
12616 return -RELAX_SECOND (fragp
->fr_subtype
);
12619 /* This is called to see whether a reloc against a defined symbol
12620 should be converted into a reloc against a section. */
12623 mips_fix_adjustable (fixS
*fixp
)
12625 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12626 about the format of the offset in the .o file. */
12627 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12630 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12631 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12634 if (fixp
->fx_addsy
== NULL
)
12637 /* If symbol SYM is in a mergeable section, relocations of the form
12638 SYM + 0 can usually be made section-relative. The mergeable data
12639 is then identified by the section offset rather than by the symbol.
12641 However, if we're generating REL LO16 relocations, the offset is split
12642 between the LO16 and parterning high part relocation. The linker will
12643 need to recalculate the complete offset in order to correctly identify
12646 The linker has traditionally not looked for the parterning high part
12647 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12648 placed anywhere. Rather than break backwards compatibility by changing
12649 this, it seems better not to force the issue, and instead keep the
12650 original symbol. This will work with either linker behavior. */
12651 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12652 && HAVE_IN_PLACE_ADDENDS
12653 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12657 /* Don't adjust relocations against mips16 symbols, so that the linker
12658 can find them if it needs to set up a stub. */
12659 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12660 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12661 && fixp
->fx_subsy
== NULL
)
12668 /* Translate internal representation of relocation info to BFD target
12672 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12674 static arelent
*retval
[4];
12676 bfd_reloc_code_real_type code
;
12678 memset (retval
, 0, sizeof(retval
));
12679 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12680 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12681 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12682 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12684 assert (! fixp
->fx_pcrel
);
12685 reloc
->addend
= fixp
->fx_addnumber
;
12687 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12688 entry to be used in the relocation's section offset. */
12689 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12691 reloc
->address
= reloc
->addend
;
12695 code
= fixp
->fx_r_type
;
12697 /* To support a PC relative reloc, we used a Cygnus extension.
12698 We check for that here to make sure that we don't let such a
12699 reloc escape normally. (FIXME: This was formerly used by
12700 embedded-PIC support, but is now used by branch handling in
12701 general. That probably should be fixed.) */
12702 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12703 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12704 && code
== BFD_RELOC_16_PCREL_S2
)
12705 reloc
->howto
= NULL
;
12707 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12709 if (reloc
->howto
== NULL
)
12711 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12712 _("Can not represent %s relocation in this object file format"),
12713 bfd_get_reloc_code_name (code
));
12720 /* Relax a machine dependent frag. This returns the amount by which
12721 the current size of the frag should change. */
12724 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12726 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12728 offsetT old_var
= fragp
->fr_var
;
12730 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12732 return fragp
->fr_var
- old_var
;
12735 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12738 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12740 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12742 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12747 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12749 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12756 /* Convert a machine dependent frag. */
12759 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12761 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12764 unsigned long insn
;
12768 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12770 if (target_big_endian
)
12771 insn
= bfd_getb32 (buf
);
12773 insn
= bfd_getl32 (buf
);
12775 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12777 /* We generate a fixup instead of applying it right now
12778 because, if there are linker relaxations, we're going to
12779 need the relocations. */
12780 exp
.X_op
= O_symbol
;
12781 exp
.X_add_symbol
= fragp
->fr_symbol
;
12782 exp
.X_add_number
= fragp
->fr_offset
;
12784 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12786 BFD_RELOC_16_PCREL_S2
);
12787 fixp
->fx_file
= fragp
->fr_file
;
12788 fixp
->fx_line
= fragp
->fr_line
;
12790 md_number_to_chars ((char *) buf
, insn
, 4);
12797 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12798 _("relaxed out-of-range branch into a jump"));
12800 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12803 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12805 /* Reverse the branch. */
12806 switch ((insn
>> 28) & 0xf)
12809 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12810 have the condition reversed by tweaking a single
12811 bit, and their opcodes all have 0x4???????. */
12812 assert ((insn
& 0xf1000000) == 0x41000000);
12813 insn
^= 0x00010000;
12817 /* bltz 0x04000000 bgez 0x04010000
12818 bltzal 0x04100000 bgezal 0x04110000 */
12819 assert ((insn
& 0xfc0e0000) == 0x04000000);
12820 insn
^= 0x00010000;
12824 /* beq 0x10000000 bne 0x14000000
12825 blez 0x18000000 bgtz 0x1c000000 */
12826 insn
^= 0x04000000;
12834 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12836 /* Clear the and-link bit. */
12837 assert ((insn
& 0xfc1c0000) == 0x04100000);
12839 /* bltzal 0x04100000 bgezal 0x04110000
12840 bltzall 0x04120000 bgezall 0x04130000 */
12841 insn
&= ~0x00100000;
12844 /* Branch over the branch (if the branch was likely) or the
12845 full jump (not likely case). Compute the offset from the
12846 current instruction to branch to. */
12847 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12851 /* How many bytes in instructions we've already emitted? */
12852 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12853 /* How many bytes in instructions from here to the end? */
12854 i
= fragp
->fr_var
- i
;
12856 /* Convert to instruction count. */
12858 /* Branch counts from the next instruction. */
12861 /* Branch over the jump. */
12862 md_number_to_chars ((char *) buf
, insn
, 4);
12866 md_number_to_chars ((char *) buf
, 0, 4);
12869 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12871 /* beql $0, $0, 2f */
12873 /* Compute the PC offset from the current instruction to
12874 the end of the variable frag. */
12875 /* How many bytes in instructions we've already emitted? */
12876 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12877 /* How many bytes in instructions from here to the end? */
12878 i
= fragp
->fr_var
- i
;
12879 /* Convert to instruction count. */
12881 /* Don't decrement i, because we want to branch over the
12885 md_number_to_chars ((char *) buf
, insn
, 4);
12888 md_number_to_chars ((char *) buf
, 0, 4);
12893 if (mips_pic
== NO_PIC
)
12896 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12897 ? 0x0c000000 : 0x08000000);
12898 exp
.X_op
= O_symbol
;
12899 exp
.X_add_symbol
= fragp
->fr_symbol
;
12900 exp
.X_add_number
= fragp
->fr_offset
;
12902 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12903 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12904 fixp
->fx_file
= fragp
->fr_file
;
12905 fixp
->fx_line
= fragp
->fr_line
;
12907 md_number_to_chars ((char *) buf
, insn
, 4);
12912 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12913 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12914 exp
.X_op
= O_symbol
;
12915 exp
.X_add_symbol
= fragp
->fr_symbol
;
12916 exp
.X_add_number
= fragp
->fr_offset
;
12918 if (fragp
->fr_offset
)
12920 exp
.X_add_symbol
= make_expr_symbol (&exp
);
12921 exp
.X_add_number
= 0;
12924 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12925 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
12926 fixp
->fx_file
= fragp
->fr_file
;
12927 fixp
->fx_line
= fragp
->fr_line
;
12929 md_number_to_chars ((char *) buf
, insn
, 4);
12932 if (mips_opts
.isa
== ISA_MIPS1
)
12935 md_number_to_chars ((char *) buf
, 0, 4);
12939 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
12940 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
12942 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12943 4, &exp
, 0, BFD_RELOC_LO16
);
12944 fixp
->fx_file
= fragp
->fr_file
;
12945 fixp
->fx_line
= fragp
->fr_line
;
12947 md_number_to_chars ((char *) buf
, insn
, 4);
12951 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12956 md_number_to_chars ((char *) buf
, insn
, 4);
12961 assert (buf
== (bfd_byte
*)fragp
->fr_literal
12962 + fragp
->fr_fix
+ fragp
->fr_var
);
12964 fragp
->fr_fix
+= fragp
->fr_var
;
12969 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12972 register const struct mips16_immed_operand
*op
;
12973 bfd_boolean small
, ext
;
12976 unsigned long insn
;
12977 bfd_boolean use_extend
;
12978 unsigned short extend
;
12980 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12981 op
= mips16_immed_operands
;
12982 while (op
->type
!= type
)
12985 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12996 resolve_symbol_value (fragp
->fr_symbol
);
12997 val
= S_GET_VALUE (fragp
->fr_symbol
);
13002 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13004 /* The rules for the base address of a PC relative reloc are
13005 complicated; see mips16_extended_frag. */
13006 if (type
== 'p' || type
== 'q')
13011 /* Ignore the low bit in the target, since it will be
13012 set for a text label. */
13013 if ((val
& 1) != 0)
13016 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13018 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13021 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13024 /* Make sure the section winds up with the alignment we have
13027 record_alignment (asec
, op
->shift
);
13031 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13032 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13033 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13034 _("extended instruction in delay slot"));
13036 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13038 if (target_big_endian
)
13039 insn
= bfd_getb16 (buf
);
13041 insn
= bfd_getl16 (buf
);
13043 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13044 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13045 small
, ext
, &insn
, &use_extend
, &extend
);
13049 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13050 fragp
->fr_fix
+= 2;
13054 md_number_to_chars ((char *) buf
, insn
, 2);
13055 fragp
->fr_fix
+= 2;
13063 first
= RELAX_FIRST (fragp
->fr_subtype
);
13064 second
= RELAX_SECOND (fragp
->fr_subtype
);
13065 fixp
= (fixS
*) fragp
->fr_opcode
;
13067 /* Possibly emit a warning if we've chosen the longer option. */
13068 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13069 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13071 const char *msg
= macro_warning (fragp
->fr_subtype
);
13073 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13076 /* Go through all the fixups for the first sequence. Disable them
13077 (by marking them as done) if we're going to use the second
13078 sequence instead. */
13080 && fixp
->fx_frag
== fragp
13081 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13083 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13085 fixp
= fixp
->fx_next
;
13088 /* Go through the fixups for the second sequence. Disable them if
13089 we're going to use the first sequence, otherwise adjust their
13090 addresses to account for the relaxation. */
13091 while (fixp
&& fixp
->fx_frag
== fragp
)
13093 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13094 fixp
->fx_where
-= first
;
13097 fixp
= fixp
->fx_next
;
13100 /* Now modify the frag contents. */
13101 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13105 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13106 memmove (start
, start
+ first
, second
);
13107 fragp
->fr_fix
-= first
;
13110 fragp
->fr_fix
-= second
;
13116 /* This function is called after the relocs have been generated.
13117 We've been storing mips16 text labels as odd. Here we convert them
13118 back to even for the convenience of the debugger. */
13121 mips_frob_file_after_relocs (void)
13124 unsigned int count
, i
;
13126 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13129 syms
= bfd_get_outsymbols (stdoutput
);
13130 count
= bfd_get_symcount (stdoutput
);
13131 for (i
= 0; i
< count
; i
++, syms
++)
13133 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13134 && ((*syms
)->value
& 1) != 0)
13136 (*syms
)->value
&= ~1;
13137 /* If the symbol has an odd size, it was probably computed
13138 incorrectly, so adjust that as well. */
13139 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13140 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13147 /* This function is called whenever a label is defined. It is used
13148 when handling branch delays; if a branch has a label, we assume we
13149 can not move it. */
13152 mips_define_label (symbolS
*sym
)
13154 struct insn_label_list
*l
;
13156 if (free_insn_labels
== NULL
)
13157 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13160 l
= free_insn_labels
;
13161 free_insn_labels
= l
->next
;
13165 l
->next
= insn_labels
;
13169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13171 /* Some special processing for a MIPS ELF file. */
13174 mips_elf_final_processing (void)
13176 /* Write out the register information. */
13177 if (mips_abi
!= N64_ABI
)
13181 s
.ri_gprmask
= mips_gprmask
;
13182 s
.ri_cprmask
[0] = mips_cprmask
[0];
13183 s
.ri_cprmask
[1] = mips_cprmask
[1];
13184 s
.ri_cprmask
[2] = mips_cprmask
[2];
13185 s
.ri_cprmask
[3] = mips_cprmask
[3];
13186 /* The gp_value field is set by the MIPS ELF backend. */
13188 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13189 ((Elf32_External_RegInfo
*)
13190 mips_regmask_frag
));
13194 Elf64_Internal_RegInfo s
;
13196 s
.ri_gprmask
= mips_gprmask
;
13198 s
.ri_cprmask
[0] = mips_cprmask
[0];
13199 s
.ri_cprmask
[1] = mips_cprmask
[1];
13200 s
.ri_cprmask
[2] = mips_cprmask
[2];
13201 s
.ri_cprmask
[3] = mips_cprmask
[3];
13202 /* The gp_value field is set by the MIPS ELF backend. */
13204 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13205 ((Elf64_External_RegInfo
*)
13206 mips_regmask_frag
));
13209 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13210 sort of BFD interface for this. */
13211 if (mips_any_noreorder
)
13212 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13213 if (mips_pic
!= NO_PIC
)
13215 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13216 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13219 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13221 /* Set MIPS ELF flags for ASEs. */
13222 if (file_ase_mips16
)
13223 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13224 #if 0 /* XXX FIXME */
13225 if (file_ase_mips3d
)
13226 elf_elfheader (stdoutput
)->e_flags
|= ???;
13229 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13231 /* Set the MIPS ELF ABI flags. */
13232 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13233 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13234 else if (mips_abi
== O64_ABI
)
13235 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13236 else if (mips_abi
== EABI_ABI
)
13238 if (!file_mips_gp32
)
13239 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13241 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13243 else if (mips_abi
== N32_ABI
)
13244 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13246 /* Nothing to do for N64_ABI. */
13248 if (mips_32bitmode
)
13249 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13252 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13254 typedef struct proc
{
13256 symbolS
*func_end_sym
;
13257 unsigned long reg_mask
;
13258 unsigned long reg_offset
;
13259 unsigned long fpreg_mask
;
13260 unsigned long fpreg_offset
;
13261 unsigned long frame_offset
;
13262 unsigned long frame_reg
;
13263 unsigned long pc_reg
;
13266 static procS cur_proc
;
13267 static procS
*cur_proc_ptr
;
13268 static int numprocs
;
13270 /* Fill in an rs_align_code fragment. */
13273 mips_handle_align (fragS
*fragp
)
13275 if (fragp
->fr_type
!= rs_align_code
)
13278 if (mips_opts
.mips16
)
13280 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13281 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13286 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13287 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13295 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13299 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13303 md_obj_begin (void)
13310 /* check for premature end, nesting errors, etc */
13312 as_warn (_("missing .end at end of assembly"));
13321 if (*input_line_pointer
== '-')
13323 ++input_line_pointer
;
13326 if (!ISDIGIT (*input_line_pointer
))
13327 as_bad (_("expected simple number"));
13328 if (input_line_pointer
[0] == '0')
13330 if (input_line_pointer
[1] == 'x')
13332 input_line_pointer
+= 2;
13333 while (ISXDIGIT (*input_line_pointer
))
13336 val
|= hex_value (*input_line_pointer
++);
13338 return negative
? -val
: val
;
13342 ++input_line_pointer
;
13343 while (ISDIGIT (*input_line_pointer
))
13346 val
|= *input_line_pointer
++ - '0';
13348 return negative
? -val
: val
;
13351 if (!ISDIGIT (*input_line_pointer
))
13353 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13354 *input_line_pointer
, *input_line_pointer
);
13355 as_warn (_("invalid number"));
13358 while (ISDIGIT (*input_line_pointer
))
13361 val
+= *input_line_pointer
++ - '0';
13363 return negative
? -val
: val
;
13366 /* The .file directive; just like the usual .file directive, but there
13367 is an initial number which is the ECOFF file index. In the non-ECOFF
13368 case .file implies DWARF-2. */
13371 s_mips_file (int x ATTRIBUTE_UNUSED
)
13373 static int first_file_directive
= 0;
13375 if (ECOFF_DEBUGGING
)
13384 filename
= dwarf2_directive_file (0);
13386 /* Versions of GCC up to 3.1 start files with a ".file"
13387 directive even for stabs output. Make sure that this
13388 ".file" is handled. Note that you need a version of GCC
13389 after 3.1 in order to support DWARF-2 on MIPS. */
13390 if (filename
!= NULL
&& ! first_file_directive
)
13392 (void) new_logical_line (filename
, -1);
13393 s_app_file_string (filename
, 0);
13395 first_file_directive
= 1;
13399 /* The .loc directive, implying DWARF-2. */
13402 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13404 if (!ECOFF_DEBUGGING
)
13405 dwarf2_directive_loc (0);
13408 /* The .end directive. */
13411 s_mips_end (int x ATTRIBUTE_UNUSED
)
13415 /* Following functions need their own .frame and .cprestore directives. */
13416 mips_frame_reg_valid
= 0;
13417 mips_cprestore_valid
= 0;
13419 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13422 demand_empty_rest_of_line ();
13427 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13428 as_warn (_(".end not in text section"));
13432 as_warn (_(".end directive without a preceding .ent directive."));
13433 demand_empty_rest_of_line ();
13439 assert (S_GET_NAME (p
));
13440 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13441 as_warn (_(".end symbol does not match .ent symbol."));
13443 if (debug_type
== DEBUG_STABS
)
13444 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13448 as_warn (_(".end directive missing or unknown symbol"));
13451 /* Create an expression to calculate the size of the function. */
13452 if (p
&& cur_proc_ptr
)
13454 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13455 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13458 exp
->X_op
= O_subtract
;
13459 exp
->X_add_symbol
= symbol_temp_new_now ();
13460 exp
->X_op_symbol
= p
;
13461 exp
->X_add_number
= 0;
13463 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13466 /* Generate a .pdr section. */
13467 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13470 segT saved_seg
= now_seg
;
13471 subsegT saved_subseg
= now_subseg
;
13476 dot
= frag_now_fix ();
13478 #ifdef md_flush_pending_output
13479 md_flush_pending_output ();
13483 subseg_set (pdr_seg
, 0);
13485 /* Write the symbol. */
13486 exp
.X_op
= O_symbol
;
13487 exp
.X_add_symbol
= p
;
13488 exp
.X_add_number
= 0;
13489 emit_expr (&exp
, 4);
13491 fragp
= frag_more (7 * 4);
13493 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13494 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13495 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13496 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13497 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13498 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13499 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13501 subseg_set (saved_seg
, saved_subseg
);
13503 #endif /* OBJ_ELF */
13505 cur_proc_ptr
= NULL
;
13508 /* The .aent and .ent directives. */
13511 s_mips_ent (int aent
)
13515 symbolP
= get_symbol ();
13516 if (*input_line_pointer
== ',')
13517 ++input_line_pointer
;
13518 SKIP_WHITESPACE ();
13519 if (ISDIGIT (*input_line_pointer
)
13520 || *input_line_pointer
== '-')
13523 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13524 as_warn (_(".ent or .aent not in text section."));
13526 if (!aent
&& cur_proc_ptr
)
13527 as_warn (_("missing .end"));
13531 /* This function needs its own .frame and .cprestore directives. */
13532 mips_frame_reg_valid
= 0;
13533 mips_cprestore_valid
= 0;
13535 cur_proc_ptr
= &cur_proc
;
13536 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13538 cur_proc_ptr
->func_sym
= symbolP
;
13540 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13544 if (debug_type
== DEBUG_STABS
)
13545 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13546 S_GET_NAME (symbolP
));
13549 demand_empty_rest_of_line ();
13552 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13553 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13554 s_mips_frame is used so that we can set the PDR information correctly.
13555 We can't use the ecoff routines because they make reference to the ecoff
13556 symbol table (in the mdebug section). */
13559 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13562 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13566 if (cur_proc_ptr
== (procS
*) NULL
)
13568 as_warn (_(".frame outside of .ent"));
13569 demand_empty_rest_of_line ();
13573 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13575 SKIP_WHITESPACE ();
13576 if (*input_line_pointer
++ != ','
13577 || get_absolute_expression_and_terminator (&val
) != ',')
13579 as_warn (_("Bad .frame directive"));
13580 --input_line_pointer
;
13581 demand_empty_rest_of_line ();
13585 cur_proc_ptr
->frame_offset
= val
;
13586 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13588 demand_empty_rest_of_line ();
13591 #endif /* OBJ_ELF */
13595 /* The .fmask and .mask directives. If the mdebug section is present
13596 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13597 embedded targets, s_mips_mask is used so that we can set the PDR
13598 information correctly. We can't use the ecoff routines because they
13599 make reference to the ecoff symbol table (in the mdebug section). */
13602 s_mips_mask (int reg_type
)
13605 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13609 if (cur_proc_ptr
== (procS
*) NULL
)
13611 as_warn (_(".mask/.fmask outside of .ent"));
13612 demand_empty_rest_of_line ();
13616 if (get_absolute_expression_and_terminator (&mask
) != ',')
13618 as_warn (_("Bad .mask/.fmask directive"));
13619 --input_line_pointer
;
13620 demand_empty_rest_of_line ();
13624 off
= get_absolute_expression ();
13626 if (reg_type
== 'F')
13628 cur_proc_ptr
->fpreg_mask
= mask
;
13629 cur_proc_ptr
->fpreg_offset
= off
;
13633 cur_proc_ptr
->reg_mask
= mask
;
13634 cur_proc_ptr
->reg_offset
= off
;
13637 demand_empty_rest_of_line ();
13640 #endif /* OBJ_ELF */
13641 s_ignore (reg_type
);
13644 /* A table describing all the processors gas knows about. Names are
13645 matched in the order listed.
13647 To ease comparison, please keep this table in the same order as
13648 gcc's mips_cpu_info_table[]. */
13649 static const struct mips_cpu_info mips_cpu_info_table
[] =
13651 /* Entries for generic ISAs */
13652 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13653 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13654 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13655 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13656 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13657 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13658 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13659 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13660 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13663 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13664 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13665 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13668 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13671 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13672 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13673 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13674 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13675 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13676 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13677 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13678 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13679 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13680 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13681 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13682 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13685 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13686 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13687 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13688 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13689 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13690 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13691 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13692 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13693 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13694 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13695 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13696 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13697 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13700 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13701 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13702 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13705 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13706 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13708 /* Broadcom SB-1 CPU core */
13709 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13716 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13717 with a final "000" replaced by "k". Ignore case.
13719 Note: this function is shared between GCC and GAS. */
13722 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13724 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13725 given
++, canonical
++;
13727 return ((*given
== 0 && *canonical
== 0)
13728 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13732 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13733 CPU name. We've traditionally allowed a lot of variation here.
13735 Note: this function is shared between GCC and GAS. */
13738 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13740 /* First see if the name matches exactly, or with a final "000"
13741 turned into "k". */
13742 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13745 /* If not, try comparing based on numerical designation alone.
13746 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13747 if (TOLOWER (*given
) == 'r')
13749 if (!ISDIGIT (*given
))
13752 /* Skip over some well-known prefixes in the canonical name,
13753 hoping to find a number there too. */
13754 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13756 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13758 else if (TOLOWER (canonical
[0]) == 'r')
13761 return mips_strict_matching_cpu_name_p (canonical
, given
);
13765 /* Parse an option that takes the name of a processor as its argument.
13766 OPTION is the name of the option and CPU_STRING is the argument.
13767 Return the corresponding processor enumeration if the CPU_STRING is
13768 recognized, otherwise report an error and return null.
13770 A similar function exists in GCC. */
13772 static const struct mips_cpu_info
*
13773 mips_parse_cpu (const char *option
, const char *cpu_string
)
13775 const struct mips_cpu_info
*p
;
13777 /* 'from-abi' selects the most compatible architecture for the given
13778 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13779 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13780 version. Look first at the -mgp options, if given, otherwise base
13781 the choice on MIPS_DEFAULT_64BIT.
13783 Treat NO_ABI like the EABIs. One reason to do this is that the
13784 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13785 architecture. This code picks MIPS I for 'mips' and MIPS III for
13786 'mips64', just as we did in the days before 'from-abi'. */
13787 if (strcasecmp (cpu_string
, "from-abi") == 0)
13789 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13790 return mips_cpu_info_from_isa (ISA_MIPS1
);
13792 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13793 return mips_cpu_info_from_isa (ISA_MIPS3
);
13795 if (file_mips_gp32
>= 0)
13796 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13798 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13803 /* 'default' has traditionally been a no-op. Probably not very useful. */
13804 if (strcasecmp (cpu_string
, "default") == 0)
13807 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13808 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13811 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13815 /* Return the canonical processor information for ISA (a member of the
13816 ISA_MIPS* enumeration). */
13818 static const struct mips_cpu_info
*
13819 mips_cpu_info_from_isa (int isa
)
13823 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13824 if (mips_cpu_info_table
[i
].is_isa
13825 && isa
== mips_cpu_info_table
[i
].isa
)
13826 return (&mips_cpu_info_table
[i
]);
13831 static const struct mips_cpu_info
*
13832 mips_cpu_info_from_arch (int arch
)
13836 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13837 if (arch
== mips_cpu_info_table
[i
].cpu
)
13838 return (&mips_cpu_info_table
[i
]);
13844 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13848 fprintf (stream
, "%24s", "");
13853 fprintf (stream
, ", ");
13857 if (*col_p
+ strlen (string
) > 72)
13859 fprintf (stream
, "\n%24s", "");
13863 fprintf (stream
, "%s", string
);
13864 *col_p
+= strlen (string
);
13870 md_show_usage (FILE *stream
)
13875 fprintf (stream
, _("\
13877 -EB generate big endian output\n\
13878 -EL generate little endian output\n\
13879 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13880 -G NUM allow referencing objects up to NUM bytes\n\
13881 implicitly with the gp register [default 8]\n"));
13882 fprintf (stream
, _("\
13883 -mips1 generate MIPS ISA I instructions\n\
13884 -mips2 generate MIPS ISA II instructions\n\
13885 -mips3 generate MIPS ISA III instructions\n\
13886 -mips4 generate MIPS ISA IV instructions\n\
13887 -mips5 generate MIPS ISA V instructions\n\
13888 -mips32 generate MIPS32 ISA instructions\n\
13889 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13890 -mips64 generate MIPS64 ISA instructions\n\
13891 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13892 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13896 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13897 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13898 show (stream
, "from-abi", &column
, &first
);
13899 fputc ('\n', stream
);
13901 fprintf (stream
, _("\
13902 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13903 -no-mCPU don't generate code specific to CPU.\n\
13904 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13908 show (stream
, "3900", &column
, &first
);
13909 show (stream
, "4010", &column
, &first
);
13910 show (stream
, "4100", &column
, &first
);
13911 show (stream
, "4650", &column
, &first
);
13912 fputc ('\n', stream
);
13914 fprintf (stream
, _("\
13915 -mips16 generate mips16 instructions\n\
13916 -no-mips16 do not generate mips16 instructions\n"));
13917 fprintf (stream
, _("\
13918 -mfix-vr4120 work around certain VR4120 errata\n\
13919 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13920 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13921 -mno-shared optimize output for executables\n\
13922 -msym32 assume all symbols have 32-bit values\n\
13923 -O0 remove unneeded NOPs, do not swap branches\n\
13924 -O remove unneeded NOPs and swap branches\n\
13925 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13926 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13927 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13929 fprintf (stream
, _("\
13930 -KPIC, -call_shared generate SVR4 position independent code\n\
13931 -non_shared do not generate position independent code\n\
13932 -xgot assume a 32 bit GOT\n\
13933 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
13934 -mshared, -mno-shared disable/enable .cpload optimization for\n\
13936 -mabi=ABI create ABI conformant object file for:\n"));
13940 show (stream
, "32", &column
, &first
);
13941 show (stream
, "o64", &column
, &first
);
13942 show (stream
, "n32", &column
, &first
);
13943 show (stream
, "64", &column
, &first
);
13944 show (stream
, "eabi", &column
, &first
);
13946 fputc ('\n', stream
);
13948 fprintf (stream
, _("\
13949 -32 create o32 ABI object file (default)\n\
13950 -n32 create n32 ABI object file\n\
13951 -64 create 64 ABI object file\n"));
13956 mips_dwarf2_format (void)
13958 if (mips_abi
== N64_ABI
)
13961 return dwarf2_format_64bit_irix
;
13963 return dwarf2_format_64bit
;
13967 return dwarf2_format_32bit
;
13971 mips_dwarf2_addr_size (void)
13973 if (mips_abi
== N64_ABI
)