1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* The name of the readonly data section. */
95 #define RDATA_SECTION_NAME ".data"
98 #define RDATA_SECTION_NAME ".rdata"
101 #define RDATA_SECTION_NAME ".rodata"
104 /* These variables are filled in with the masks of registers used.
105 The object format code reads them and puts them in the appropriate
107 unsigned long mips_gprmask
;
108 unsigned long mips_cprmask
[4];
110 /* MIPS ISA (Instruction Set Architecture) level (may be changed
111 temporarily using .set mipsN). */
112 static int mips_isa
= -1;
114 /* MIPS ISA we are using for this output file. */
115 static int file_mips_isa
;
117 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
120 /* MIPS PIC level. */
124 /* Do not generate PIC code. */
127 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
128 not sure what it is supposed to do. */
131 /* Generate PIC code as in the SVR4 MIPS ABI. */
134 /* Generate PIC code without using a global offset table: the data
135 segment has a maximum size of 64K, all data references are off
136 the $gp register, and all text references are PC relative. This
137 is used on some embedded systems. */
141 static enum mips_pic_level mips_pic
;
143 /* 1 if trap instructions should used for overflow rather than break
145 static int mips_trap
;
147 static int mips_warn_about_macros
;
148 static int mips_noreorder
;
149 static int mips_any_noreorder
;
150 static int mips_nomove
;
151 static int mips_noat
;
152 static int mips_nobopt
;
155 /* The size of the small data section. */
156 static int g_switch_value
= 8;
157 /* Whether the -G option was used. */
158 static int g_switch_seen
= 0;
164 /* handle of the OPCODE hash table */
165 static struct hash_control
*op_hash
= NULL
;
167 /* This array holds the chars that always start a comment. If the
168 pre-processor is disabled, these aren't very useful */
169 const char comment_chars
[] = "#";
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that C style comments are always supported. */
178 const char line_comment_chars
[] = "#";
180 /* This array holds machine specific line separator characters. */
181 const char line_separator_chars
[] = "";
183 /* Chars that can be used to separate mant from exp in floating point nums */
184 const char EXP_CHARS
[] = "eE";
186 /* Chars that mean this number is a floating point constant */
189 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
191 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
192 changed in read.c . Ideally it shouldn't have to know about it at all,
193 but nothing is ideal around here.
196 static char *insn_error
;
198 static int byte_order
= BYTE_ORDER
;
200 static int auto_align
= 1;
202 /* Symbol labelling the current insn. */
203 static symbolS
*insn_label
;
205 /* When outputting SVR4 PIC code, the assembler needs to know the
206 offset in the stack frame from which to restore the $gp register.
207 This is set by the .cprestore pseudo-op, and saved in this
209 static offsetT mips_cprestore_offset
= -1;
211 /* This is the register which holds the stack frame, as set by the
212 .frame pseudo-op. This is needed to implement .cprestore. */
213 static int mips_frame_reg
= SP
;
215 /* To output NOP instructions correctly, we need to keep information
216 about the previous two instructions. */
218 /* Whether we are optimizing. The default value of 2 means to remove
219 unneeded NOPs and swap branch instructions when possible. A value
220 of 1 means to not swap branches. A value of 0 means to always
222 static int mips_optimize
= 2;
224 /* The previous instruction. */
225 static struct mips_cl_insn prev_insn
;
227 /* The instruction before prev_insn. */
228 static struct mips_cl_insn prev_prev_insn
;
230 /* If we don't want information for prev_insn or prev_prev_insn, we
231 point the insn_mo field at this dummy integer. */
232 static const struct mips_opcode dummy_opcode
= { 0 };
234 /* Non-zero if prev_insn is valid. */
235 static int prev_insn_valid
;
237 /* The frag for the previous instruction. */
238 static struct frag
*prev_insn_frag
;
240 /* The offset into prev_insn_frag for the previous instruction. */
241 static long prev_insn_where
;
243 /* The reloc for the previous instruction, if any. */
244 static fixS
*prev_insn_fixp
;
246 /* Non-zero if the previous instruction was in a delay slot. */
247 static int prev_insn_is_delay_slot
;
249 /* Non-zero if the previous instruction was in a .set noreorder. */
250 static int prev_insn_unreordered
;
252 /* Non-zero if the previous previous instruction was in a .set
254 static int prev_prev_insn_unreordered
;
256 /* The number of instructions since the last instruction which
257 accesses the data cache. The instruction itself counts as 1, so 0
258 means no information. This is used to work around a bug on the
259 r4600 (ORION) chip. */
260 static int insns_since_cache_access
;
262 /* Since the MIPS does not have multiple forms of PC relative
263 instructions, we do not have to do relaxing as is done on other
264 platforms. However, we do have to handle GP relative addressing
265 correctly, which turns out to be a similar problem.
267 Every macro that refers to a symbol can occur in (at least) two
268 forms, one with GP relative addressing and one without. For
269 example, loading a global variable into a register generally uses
270 a macro instruction like this:
272 If i can be addressed off the GP register (this is true if it is in
273 the .sbss or .sdata section, or if it is known to be smaller than
274 the -G argument) this will generate the following instruction:
276 This instruction will use a GPREL reloc. If i can not be addressed
277 off the GP register, the following instruction sequence will be used:
280 In this case the first instruction will have a HI16 reloc, and the
281 second reloc will have a LO16 reloc. Both relocs will be against
284 The issue here is that we may not know whether i is GP addressable
285 until after we see the instruction that uses it. Therefore, we
286 want to be able to choose the final instruction sequence only at
287 the end of the assembly. This is similar to the way other
288 platforms choose the size of a PC relative instruction only at the
291 When generating position independent code we do not use GP
292 addressing in quite the same way, but the issue still arises as
293 external symbols and local symbols must be handled differently.
295 We handle these issues by actually generating both possible
296 instruction sequences. The longer one is put in a frag_var with
297 type rs_machine_dependent. We encode what to do with the frag in
298 the subtype field. We encode (1) the number of existing bytes to
299 replace, (2) the number of new bytes to use, (3) the offset from
300 the start of the existing bytes to the first reloc we must generate
301 (that is, the offset is applied from the start of the existing
302 bytes after they are replaced by the new bytes, if any), (4) the
303 offset from the start of the existing bytes to the second reloc,
304 (5) whether a third reloc is needed (the third reloc is always four
305 bytes after the second reloc), and (6) whether to warn if this
306 variant is used (this is sometimes needed if .set nomacro or .set
307 noat is in effect). All these numbers are reasonably small.
309 Generating two instruction sequences must be handled carefully to
310 ensure that delay slots are handled correctly. Fortunately, there
311 are a limited number of cases. When the second instruction
312 sequence is generated, append_insn is directed to maintain the
313 existing delay slot information, so it continues to apply to any
314 code after the second instruction sequence. This means that the
315 second instruction sequence must not impose any requirements not
316 required by the first instruction sequence.
318 These variant frags are then handled in functions called by the
319 machine independent code. md_estimate_size_before_relax returns
320 the final size of the frag. md_convert_frag sets up the final form
321 of the frag. tc_gen_reloc adjust the first reloc and adds a second
323 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
327 | (((reloc1) + 64) << 9) \
328 | (((reloc2) + 64) << 2) \
329 | ((reloc3) ? (1 << 1) : 0) \
331 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
332 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
333 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
334 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
335 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
336 #define RELAX_WARN(i) ((i) & 1)
338 /* Prototypes for static functions. */
341 #define internalError() \
342 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
344 #define internalError() as_fatal ("MIPS internal Error");
347 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
348 unsigned int reg
, int fpr
));
349 static void append_insn
PARAMS ((char *place
,
350 struct mips_cl_insn
* ip
,
352 bfd_reloc_code_real_type r
));
353 static void mips_no_prev_insn
PARAMS ((void));
354 static void mips_emit_delays
PARAMS ((void));
355 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
356 const char *name
, const char *fmt
,
358 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
359 expressionS
* ep
, int regnum
));
360 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
361 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
363 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
364 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
365 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
366 #ifdef LOSING_COMPILER
367 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
369 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
370 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
371 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
372 static symbolS
*get_symbol
PARAMS ((void));
373 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
374 static void s_align
PARAMS ((int));
375 static void s_stringer
PARAMS ((int));
376 static void s_change_sec
PARAMS ((int));
377 static void s_cons
PARAMS ((int));
378 static void s_err
PARAMS ((int));
379 static void s_extern
PARAMS ((int));
380 static void s_float_cons
PARAMS ((int));
381 static void s_mips_globl
PARAMS ((int));
382 static void s_option
PARAMS ((int));
383 static void s_mipsset
PARAMS ((int));
384 static void s_mips_space
PARAMS ((int));
385 static void s_abicalls
PARAMS ((int));
386 static void s_cpload
PARAMS ((int));
387 static void s_cprestore
PARAMS ((int));
388 static void s_gpword
PARAMS ((int));
389 static void s_cpadd
PARAMS ((int));
390 #ifndef ECOFF_DEBUGGING
391 static void md_obj_begin
PARAMS ((void));
392 static void md_obj_end
PARAMS ((void));
393 static long get_number
PARAMS ((void));
394 static void s_ent
PARAMS ((int));
395 static void s_mipsend
PARAMS ((int));
396 static void s_file
PARAMS ((int));
398 static void s_frame
PARAMS ((int));
399 static void s_loc
PARAMS ((int));
400 static void s_mask
PARAMS ((char));
406 The following pseudo-ops from the Kane and Heinrich MIPS book
407 should be defined here, but are currently unsupported: .alias,
408 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
410 The following pseudo-ops from the Kane and Heinrich MIPS book are
411 specific to the type of debugging information being generated, and
412 should be defined by the object format: .aent, .begin, .bend,
413 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
416 The following pseudo-ops from the Kane and Heinrich MIPS book are
417 not MIPS CPU specific, but are also not specific to the object file
418 format. This file is probably the best place to define them, but
419 they are not currently supported: .asm0, .endr, .lab, .repeat,
420 .struct, .weakext. */
422 const pseudo_typeS md_pseudo_table
[] =
424 /* MIPS specific pseudo-ops. */
425 {"option", s_option
, 0},
426 {"set", s_mipsset
, 0},
427 {"rdata", s_change_sec
, 'r'},
428 {"sdata", s_change_sec
, 's'},
429 {"livereg", s_ignore
, 0},
430 { "abicalls", s_abicalls
, 0},
431 { "cpload", s_cpload
, 0},
432 { "cprestore", s_cprestore
, 0},
433 { "gpword", s_gpword
, 0},
434 { "cpadd", s_cpadd
, 0},
436 /* Relatively generic pseudo-ops that happen to be used on MIPS
438 {"asciiz", s_stringer
, 1},
439 {"bss", s_change_sec
, 'b'},
442 {"dword", s_cons
, 3},
444 /* These pseudo-ops are defined in read.c, but must be overridden
445 here for one reason or another. */
446 {"align", s_align
, 0},
447 {"ascii", s_stringer
, 0},
448 {"asciz", s_stringer
, 1},
450 {"data", s_change_sec
, 'd'},
451 {"double", s_float_cons
, 'd'},
452 {"extern", s_extern
, 0},
453 {"float", s_float_cons
, 'f'},
454 {"globl", s_mips_globl
, 0},
455 {"global", s_mips_globl
, 0},
456 {"hword", s_cons
, 1},
461 {"short", s_cons
, 1},
462 {"single", s_float_cons
, 'f'},
463 {"space", s_mips_space
, 0},
464 {"text", s_change_sec
, 't'},
467 #ifndef ECOFF_DEBUGGING
468 /* These pseudo-ops should be defined by the object file format.
469 However, a.out doesn't support them, so we have versions here. */
471 {"bgnb", s_ignore
, 0},
472 {"end", s_mipsend
, 0},
473 {"endb", s_ignore
, 0},
476 {"fmask", s_ignore
, 'F'},
477 {"frame", s_ignore
, 0},
478 {"loc", s_ignore
, 0},
479 {"mask", s_ignore
, 'R'},
480 {"verstamp", s_ignore
, 0},
487 const relax_typeS md_relax_table
[] =
492 static char *expr_end
;
494 static expressionS imm_expr
;
495 static expressionS offset_expr
;
496 static bfd_reloc_code_real_type imm_reloc
;
497 static bfd_reloc_code_real_type offset_reloc
;
499 /* FIXME: This should be handled in a different way. */
500 extern int target_big_endian
;
503 * This function is called once, at assembler startup time. It should
504 * set up all the tables, etc. that the MD part of the assembler will need.
510 register const char *retval
= NULL
;
511 register unsigned int i
= 0;
519 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
521 a
= xmalloc (sizeof TARGET_CPU
);
522 strcpy (a
, TARGET_CPU
);
523 a
[(sizeof TARGET_CPU
) - 3] = '\0';
527 if (strcmp (cpu
, "mips") == 0)
532 else if (strcmp (cpu
, "r6000") == 0
533 || strcmp (cpu
, "mips2") == 0)
538 else if (strcmp (cpu
, "mips64") == 0
539 || strcmp (cpu
, "r4000") == 0
540 || strcmp (cpu
, "mips3") == 0)
545 else if (strcmp (cpu
, "r4400") == 0)
550 else if (strcmp (cpu
, "mips64orion") == 0
551 || strcmp (cpu
, "r4600") == 0)
566 if (mips_isa
< 2 && mips_trap
)
567 as_bad ("trap exception not supported at ISA 1");
572 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
575 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
578 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
582 as_warn ("Could not set architecture and machine");
584 file_mips_isa
= mips_isa
;
586 op_hash
= hash_new ();
588 for (i
= 0; i
< NUMOPCODES
;)
590 const char *name
= mips_opcodes
[i
].name
;
592 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
595 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
596 mips_opcodes
[i
].name
, retval
);
597 as_fatal ("Broken assembler. No assembly attempted.");
601 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
602 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
603 != mips_opcodes
[i
].match
))
605 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
606 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
607 as_fatal ("Broken assembler. No assembly attempted.");
611 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
614 mips_no_prev_insn ();
622 /* set the default alignment for the text section (2**2) */
623 record_alignment (text_section
, 2);
625 /* FIXME: This should be handled in a different way. */
626 target_big_endian
= byte_order
== BIG_ENDIAN
;
629 bfd_set_gp_size (stdoutput
, g_switch_value
);
633 /* Sections must be aligned to 16 byte boundaries. */
634 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
635 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
636 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
638 /* Create a .reginfo section for register masks and a .mdebug
639 section for debugging information. */
647 sec
= subseg_new (".reginfo", (subsegT
) 0);
649 /* The ABI says this section should be loaded so that the running
650 program can access it. */
651 (void) bfd_set_section_flags (stdoutput
, sec
,
652 (SEC_ALLOC
| SEC_LOAD
653 | SEC_READONLY
| SEC_DATA
));
654 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
656 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
658 #ifdef ECOFF_DEBUGGING
659 sec
= subseg_new (".mdebug", (subsegT
) 0);
660 (void) bfd_set_section_flags (stdoutput
, sec
,
661 SEC_HAS_CONTENTS
| SEC_READONLY
);
662 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
665 subseg_set (seg
, subseg
);
669 #ifndef ECOFF_DEBUGGING
677 #ifndef ECOFF_DEBUGGING
686 struct mips_cl_insn insn
;
688 imm_expr
.X_op
= O_absent
;
689 offset_expr
.X_op
= O_absent
;
691 mips_ip (str
, &insn
);
694 as_bad ("%s `%s'", insn_error
, str
);
697 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
703 if (imm_expr
.X_op
!= O_absent
)
704 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
705 else if (offset_expr
.X_op
!= O_absent
)
706 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
708 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
712 /* See whether instruction IP reads register REG. If FPR is non-zero,
713 REG is a floating point register. */
716 insn_uses_reg (ip
, reg
, fpr
)
717 struct mips_cl_insn
*ip
;
721 /* Don't report on general register 0, since it never changes. */
722 if (! fpr
&& reg
== 0)
727 /* If we are called with either $f0 or $f1, we must check $f0.
728 This is not optimal, because it will introduce an unnecessary
729 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
730 need to distinguish reading both $f0 and $f1 or just one of
731 them. Note that we don't have to check the other way,
732 because there is no instruction that sets both $f0 and $f1
733 and requires a delay. */
734 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
735 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
736 == (reg
&~ (unsigned) 1)))
738 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
739 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
740 == (reg
&~ (unsigned) 1)))
745 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
746 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
748 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
749 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
756 /* Output an instruction. PLACE is where to put the instruction; if
757 it is NULL, this uses frag_more to get room. IP is the instruction
758 information. ADDRESS_EXPR is an operand of the instruction to be
759 used with RELOC_TYPE. */
762 append_insn (place
, ip
, address_expr
, reloc_type
)
764 struct mips_cl_insn
*ip
;
765 expressionS
*address_expr
;
766 bfd_reloc_code_real_type reloc_type
;
768 register unsigned long prev_pinfo
, pinfo
;
773 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
774 pinfo
= ip
->insn_mo
->pinfo
;
776 if (place
== NULL
&& ! mips_noreorder
)
778 /* If the previous insn required any delay slots, see if we need
779 to insert a NOP or two. There are eight kinds of possible
780 hazards, of which an instruction can have at most one type.
781 (1) a load from memory delay
782 (2) a load from a coprocessor delay
783 (3) an unconditional branch delay
784 (4) a conditional branch delay
785 (5) a move to coprocessor register delay
786 (6) a load coprocessor register from memory delay
787 (7) a coprocessor condition code delay
788 (8) a HI/LO special register delay
790 There are a lot of optimizations we could do that we don't.
791 In particular, we do not, in general, reorder instructions.
792 If you use gcc with optimization, it will reorder
793 instructions and generally do much more optimization then we
794 do here; repeating all that work in the assembler would only
795 benefit hand written assembly code, and does not seem worth
798 /* This is how a NOP is emitted. */
799 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
801 /* The previous insn might require a delay slot, depending upon
802 the contents of the current insn. */
803 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
805 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
807 /* A load from a coprocessor or from memory. All load
808 delays delay the use of general register rt for one
809 instruction on the r3000. The r6000 and r4000 use
811 know (prev_pinfo
& INSN_WRITE_GPR_T
);
812 if (mips_optimize
== 0
813 || insn_uses_reg (ip
,
814 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
819 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
821 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
823 /* A generic coprocessor delay. The previous instruction
824 modified a coprocessor general or control register. If
825 it modified a control register, we need to avoid any
826 coprocessor instruction (this is probably not always
827 required, but it sometimes is). If it modified a general
828 register, we avoid using that register.
830 On the r6000 and r4000 loading a coprocessor register
831 from memory is interlocked, and does not require a delay.
833 This case is not handled very well. There is no special
834 knowledge of CP0 handling, and the coprocessors other
835 than the floating point unit are not distinguished at
837 if (prev_pinfo
& INSN_WRITE_FPR_T
)
839 if (mips_optimize
== 0
840 || insn_uses_reg (ip
,
841 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
846 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
848 if (mips_optimize
== 0
849 || insn_uses_reg (ip
,
850 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
857 /* We don't know exactly what the previous instruction
858 does. If the current instruction uses a coprocessor
859 register, we must insert a NOP. If previous
860 instruction may set the condition codes, and the
861 current instruction uses them, we must insert two
863 if (mips_optimize
== 0
864 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
865 && (pinfo
& INSN_READ_COND_CODE
)))
867 else if (pinfo
& INSN_COP
)
871 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
873 /* The previous instruction sets the coprocessor condition
874 codes, but does not require a general coprocessor delay
875 (this means it is a floating point comparison
876 instruction). If this instruction uses the condition
877 codes, we need to insert a single NOP. */
878 if (mips_optimize
== 0
879 || (pinfo
& INSN_READ_COND_CODE
))
882 else if (prev_pinfo
& INSN_READ_LO
)
884 /* The previous instruction reads the LO register; if the
885 current instruction writes to the LO register, we must
887 if (mips_optimize
== 0
888 || (pinfo
& INSN_WRITE_LO
))
891 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
893 /* The previous instruction reads the HI register; if the
894 current instruction writes to the HI register, we must
896 if (mips_optimize
== 0
897 || (pinfo
& INSN_WRITE_HI
))
901 /* There are two cases which require two intervening
902 instructions: 1) setting the condition codes using a move to
903 coprocessor instruction which requires a general coprocessor
904 delay and then reading the condition codes 2) reading the HI
905 or LO register and then writing to it. If we are not already
906 emitting a NOP instruction, we must check for these cases
907 compared to the instruction previous to the previous
910 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
911 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
912 && (pinfo
& INSN_READ_COND_CODE
))
913 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
914 && (pinfo
& INSN_WRITE_LO
))
915 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
916 && (pinfo
& INSN_WRITE_HI
))))
919 /* The r4600 (ORION) chip has a bug: at least four instructions
920 are required between an instruction which accesses memory and
921 a certain set of CACHE instructions. Handle that now. */
923 && insns_since_cache_access
!= 0
924 && 5 - insns_since_cache_access
> nops
925 && ((ip
->insn_opcode
& 0xffff0000) == 0xbc0d0000
926 || (ip
->insn_opcode
& 0xffff0000) == 0xbc110000
927 || (ip
->insn_opcode
& 0xfc1f0000) == 0xbc150000
928 || (ip
->insn_opcode
& 0xffff0000) == 0xbc190000))
929 nops
= 5 - insns_since_cache_access
;
931 /* If we are being given a nop instruction, don't bother with
932 one of the nops we would otherwise output. This will only
933 happen when a nop instruction is used with mips_optimize set
935 if (nops
> 0 && ip
->insn_opcode
== 0)
938 /* Now emit the right number of NOP instructions. */
943 for (i
= 0; i
< nops
; i
++)
946 listing_prev_line ();
947 if (insn_label
!= NULL
)
949 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
950 insn_label
->sy_frag
= frag_now
;
951 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
961 if (address_expr
!= NULL
)
963 if (address_expr
->X_op
== O_constant
)
968 ip
->insn_opcode
|= address_expr
->X_add_number
;
972 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
975 case BFD_RELOC_MIPS_JMP
:
976 case BFD_RELOC_16_PCREL_S2
:
985 assert (reloc_type
!= BFD_RELOC_UNUSED
);
987 /* Don't generate a reloc if we are writing into a variant
990 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
992 reloc_type
== BFD_RELOC_16_PCREL_S2
,
997 md_number_to_chars (f
, ip
->insn_opcode
, 4);
999 /* Update the register mask information. */
1000 if (pinfo
& INSN_WRITE_GPR_D
)
1001 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1002 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1003 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1004 if (pinfo
& INSN_READ_GPR_S
)
1005 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1006 if (pinfo
& INSN_WRITE_GPR_31
)
1007 mips_gprmask
|= 1 << 31;
1008 if (pinfo
& INSN_WRITE_FPR_D
)
1009 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1010 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1011 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1012 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1013 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1014 if (pinfo
& INSN_COP
)
1016 /* We don't keep enough information to sort these cases out. */
1018 /* Never set the bit for $0, which is always zero. */
1019 mips_gprmask
&=~ 1 << 0;
1021 if (place
== NULL
&& ! mips_noreorder
)
1023 /* Filling the branch delay slot is more complex. We try to
1024 switch the branch with the previous instruction, which we can
1025 do if the previous instruction does not set up a condition
1026 that the branch tests and if the branch is not itself the
1027 target of any branch. */
1028 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1029 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1031 if (mips_optimize
< 2
1032 /* If we have seen .set volatile or .set nomove, don't
1035 /* If we had to emit any NOP instructions, then we
1036 already know we can not swap. */
1038 /* If we don't even know the previous insn, we can not
1040 || ! prev_insn_valid
1041 /* If the previous insn is already in a branch delay
1042 slot, then we can not swap. */
1043 || prev_insn_is_delay_slot
1044 /* If the previous previous insn was in a .set
1045 noreorder, we can't swap. Actually, the MIPS
1046 assembler will swap in this situation. However, gcc
1047 configured -with-gnu-as will generate code like
1053 in which we can not swap the bne and INSN. If gcc is
1054 not configured -with-gnu-as, it does not output the
1055 .set pseudo-ops. We don't have to check
1056 prev_insn_unreordered, because prev_insn_valid will
1057 be 0 in that case. We don't want to use
1058 prev_prev_insn_valid, because we do want to be able
1059 to swap at the start of a function. */
1060 || prev_prev_insn_unreordered
1061 /* If the branch is itself the target of a branch, we
1062 can not swap. We cheat on this; all we check for is
1063 whether there is a label on this instruction. If
1064 there are any branches to anything other than a
1065 label, users must use .set noreorder. */
1066 || insn_label
!= NULL
1067 /* If the previous instruction is in a variant frag, we
1068 can not do the swap. */
1069 || prev_insn_frag
->fr_type
== rs_machine_dependent
1070 /* If the branch reads the condition codes, we don't
1071 even try to swap, because in the sequence
1076 we can not swap, and I don't feel like handling that
1078 || (pinfo
& INSN_READ_COND_CODE
)
1079 /* We can not swap with an instruction that requires a
1080 delay slot, becase the target of the branch might
1081 interfere with that instruction. */
1083 & (INSN_LOAD_COPROC_DELAY
1084 | INSN_COPROC_MOVE_DELAY
1085 | INSN_WRITE_COND_CODE
1090 & (INSN_LOAD_MEMORY_DELAY
1091 | INSN_COPROC_MEMORY_DELAY
)))
1092 /* We can not swap with a branch instruction. */
1094 & (INSN_UNCOND_BRANCH_DELAY
1095 | INSN_COND_BRANCH_DELAY
1096 | INSN_COND_BRANCH_LIKELY
))
1097 /* We do not swap with a trap instruction, since it
1098 complicates trap handlers to have the trap
1099 instruction be in a delay slot. */
1100 || (prev_pinfo
& INSN_TRAP
)
1101 /* If the branch reads a register that the previous
1102 instruction sets, we can not swap. */
1103 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1104 && insn_uses_reg (ip
,
1105 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1108 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1109 && insn_uses_reg (ip
,
1110 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1113 /* If the branch writes a register that the previous
1114 instruction sets, we can not swap (we know that
1115 branches write only to RD or to $31). */
1116 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1117 && (((pinfo
& INSN_WRITE_GPR_D
)
1118 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1119 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1120 || ((pinfo
& INSN_WRITE_GPR_31
)
1121 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1124 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1125 && (((pinfo
& INSN_WRITE_GPR_D
)
1126 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1127 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1128 || ((pinfo
& INSN_WRITE_GPR_31
)
1129 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1132 /* If the branch writes a register that the previous
1133 instruction reads, we can not swap (we know that
1134 branches only write to RD or to $31). */
1135 || ((pinfo
& INSN_WRITE_GPR_D
)
1136 && insn_uses_reg (&prev_insn
,
1137 ((ip
->insn_opcode
>> OP_SH_RD
)
1140 || ((pinfo
& INSN_WRITE_GPR_31
)
1141 && insn_uses_reg (&prev_insn
, 31, 0))
1142 /* If we are generating embedded PIC code, the branch
1143 might be expanded into a sequence which uses $at, so
1144 we can't swap with an instruction which reads it. */
1145 || (mips_pic
== EMBEDDED_PIC
1146 && insn_uses_reg (&prev_insn
, AT
, 0))
1147 /* If the previous previous instruction has a load
1148 delay, and sets a register that the branch reads, we
1150 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1152 && (prev_prev_insn
.insn_mo
->pinfo
1153 & INSN_LOAD_MEMORY_DELAY
)))
1154 && insn_uses_reg (ip
,
1155 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1159 /* We could do even better for unconditional branches to
1160 portions of this object file; we could pick up the
1161 instruction at the destination, put it in the delay
1162 slot, and bump the destination address. */
1164 /* Update the previous insn information. */
1165 prev_prev_insn
= *ip
;
1166 prev_insn
.insn_mo
= &dummy_opcode
;
1173 /* It looks like we can actually do the swap. */
1174 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1175 memcpy (temp
, prev_f
, 4);
1176 memcpy (prev_f
, f
, 4);
1177 memcpy (f
, temp
, 4);
1180 prev_insn_fixp
->fx_frag
= frag_now
;
1181 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1185 fixp
->fx_frag
= prev_insn_frag
;
1186 fixp
->fx_where
= prev_insn_where
;
1188 /* Update the previous insn information; leave prev_insn
1190 prev_prev_insn
= *ip
;
1192 prev_insn_is_delay_slot
= 1;
1194 /* If that was an unconditional branch, forget the previous
1195 insn information. */
1196 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1198 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1199 prev_insn
.insn_mo
= &dummy_opcode
;
1202 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1204 /* We don't yet optimize a branch likely. What we should do
1205 is look at the target, copy the instruction found there
1206 into the delay slot, and increment the branch to jump to
1207 the next instruction. */
1209 /* Update the previous insn information. */
1210 prev_prev_insn
= *ip
;
1211 prev_insn
.insn_mo
= &dummy_opcode
;
1215 /* Update the previous insn information. */
1217 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1219 prev_prev_insn
= prev_insn
;
1222 /* Any time we see a branch, we always fill the delay slot
1223 immediately; since this insn is not a branch, we know it
1224 is not in a delay slot. */
1225 prev_insn_is_delay_slot
= 0;
1228 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1229 prev_insn_unreordered
= 0;
1230 prev_insn_frag
= frag_now
;
1231 prev_insn_where
= f
- frag_now
->fr_literal
;
1232 prev_insn_fixp
= fixp
;
1233 prev_insn_valid
= 1;
1234 if ((pinfo
& INSN_LOAD_MEMORY_DELAY
) != 0
1235 || (pinfo
& INSN_STORE_MEMORY
) != 0)
1236 insns_since_cache_access
= 1;
1237 else if (insns_since_cache_access
!= 0)
1238 ++insns_since_cache_access
;
1241 /* We just output an insn, so the next one doesn't have a label. */
1245 /* This function forgets that there was any previous instruction or
1249 mips_no_prev_insn ()
1251 prev_insn
.insn_mo
= &dummy_opcode
;
1252 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1253 prev_insn_valid
= 0;
1254 prev_insn_is_delay_slot
= 0;
1255 prev_insn_unreordered
= 0;
1256 prev_prev_insn_unreordered
= 0;
1260 /* This function must be called whenever we turn on noreorder or emit
1261 something other than instructions. It inserts any NOPS which might
1262 be needed by the previous instruction, and clears the information
1263 kept for the previous instructions. */
1268 if (! mips_noreorder
)
1273 if ((prev_insn
.insn_mo
->pinfo
1274 & (INSN_LOAD_COPROC_DELAY
1275 | INSN_COPROC_MOVE_DELAY
1276 | INSN_WRITE_COND_CODE
1280 && (prev_insn
.insn_mo
->pinfo
1281 & (INSN_LOAD_MEMORY_DELAY
1282 | INSN_COPROC_MEMORY_DELAY
))))
1285 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1286 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1287 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1290 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1291 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1292 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1297 if (insn_label
!= NULL
)
1299 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1300 insn_label
->sy_frag
= frag_now
;
1301 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1306 mips_no_prev_insn ();
1309 /* Build an instruction created by a macro expansion. This is passed
1310 a pointer to the count of instructions created so far, an
1311 expression, the name of the instruction to build, an operand format
1312 string, and corresponding arguments. */
1316 macro_build (char *place
,
1322 #else /* ! defined (NO_STDARG) */
1324 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1331 #endif /* ! defined (NO_STDARG) */
1333 struct mips_cl_insn insn
;
1334 bfd_reloc_code_real_type r
;
1338 va_start (args
, fmt
);
1344 * If the macro is about to expand into a second instruction,
1345 * print a warning if needed. We need to pass ip as a parameter
1346 * to generate a better warning message here...
1348 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1349 as_warn ("Macro instruction expanded into multiple instructions");
1352 *counter
+= 1; /* bump instruction counter */
1354 r
= BFD_RELOC_UNUSED
;
1355 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1356 assert (insn
.insn_mo
);
1357 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1359 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1360 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1363 assert (insn
.insn_mo
->name
);
1364 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1366 insn
.insn_opcode
= insn
.insn_mo
->match
;
1382 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1388 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1393 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1398 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1405 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1409 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1413 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1420 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1426 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1427 assert (r
== BFD_RELOC_MIPS_GPREL
1428 || r
== BFD_RELOC_MIPS_LITERAL
1429 || r
== BFD_RELOC_LO16
1430 || r
== BFD_RELOC_MIPS_GOT16
1431 || r
== BFD_RELOC_MIPS_CALL16
1432 || (ep
->X_op
== O_subtract
1433 && now_seg
== text_section
1434 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1435 && r
== BFD_RELOC_PCREL_LO16
));
1439 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1441 && (ep
->X_op
== O_constant
1442 || (ep
->X_op
== O_symbol
1443 && (r
== BFD_RELOC_HI16_S
1444 || r
== BFD_RELOC_HI16
))
1445 || (ep
->X_op
== O_subtract
1446 && now_seg
== text_section
1447 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1448 && r
== BFD_RELOC_PCREL_HI16_S
)));
1449 if (ep
->X_op
== O_constant
)
1451 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1453 r
= BFD_RELOC_UNUSED
;
1458 assert (ep
!= NULL
);
1460 * This allows macro() to pass an immediate expression for
1461 * creating short branches without creating a symbol.
1462 * Note that the expression still might come from the assembly
1463 * input, in which case the value is not checked for range nor
1464 * is a relocation entry generated (yuck).
1466 if (ep
->X_op
== O_constant
)
1468 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1472 r
= BFD_RELOC_16_PCREL_S2
;
1476 assert (ep
!= NULL
);
1477 r
= BFD_RELOC_MIPS_JMP
;
1486 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1488 append_insn (place
, &insn
, ep
, r
);
1492 * Generate a "lui" instruction.
1495 macro_build_lui (place
, counter
, ep
, regnum
)
1501 expressionS high_expr
;
1502 struct mips_cl_insn insn
;
1503 bfd_reloc_code_real_type r
;
1504 CONST
char *name
= "lui";
1505 CONST
char *fmt
= "t,u";
1511 high_expr
.X_op
= O_constant
;
1512 high_expr
.X_add_number
= 0;
1515 if (high_expr
.X_op
== O_constant
)
1517 /* we can compute the instruction now without a relocation entry */
1518 if (high_expr
.X_add_number
& 0x8000)
1519 high_expr
.X_add_number
+= 0x10000;
1520 high_expr
.X_add_number
=
1521 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1522 r
= BFD_RELOC_UNUSED
;
1526 assert (ep
->X_op
== O_symbol
);
1527 /* _gp_disp is a special case, used from s_cpload. */
1528 assert (mips_pic
== NO_PIC
1529 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1530 r
= BFD_RELOC_HI16_S
;
1534 * If the macro is about to expand into a second instruction,
1535 * print a warning if needed. We need to pass ip as a parameter
1536 * to generate a better warning message here...
1538 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1539 as_warn ("Macro instruction expanded into multiple instructions");
1542 *counter
+= 1; /* bump instruction counter */
1544 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1545 assert (insn
.insn_mo
);
1546 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1547 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1549 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1550 if (r
== BFD_RELOC_UNUSED
)
1552 insn
.insn_opcode
|= high_expr
.X_add_number
;
1553 append_insn (place
, &insn
, NULL
, r
);
1556 append_insn (place
, &insn
, &high_expr
, r
);
1560 * Generates code to set the $at register to true (one)
1561 * if reg is less than the immediate expression.
1564 set_at (counter
, reg
, unsignedp
)
1569 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1570 macro_build ((char *) NULL
, counter
, &imm_expr
,
1571 unsignedp
? "sltiu" : "slti",
1572 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1575 load_register (counter
, AT
, &imm_expr
);
1576 macro_build ((char *) NULL
, counter
, NULL
,
1577 unsignedp
? "sltu" : "slt",
1578 "d,v,t", AT
, reg
, AT
);
1582 /* Warn if an expression is not a constant. */
1585 check_absolute_expr (ip
, ex
)
1586 struct mips_cl_insn
*ip
;
1589 if (ex
->X_op
!= O_constant
)
1590 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1594 * This routine generates the least number of instructions neccessary to load
1595 * an absolute expression value into a register.
1598 load_register (counter
, reg
, ep
)
1603 assert (ep
->X_op
== O_constant
);
1604 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1605 macro_build ((char *) NULL
, counter
, ep
,
1606 mips_isa
< 3 ? "addiu" : "daddiu",
1607 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1608 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1609 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1610 (int) BFD_RELOC_LO16
);
1611 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1612 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1613 == ~ (offsetT
) 0x7fffffff))
1615 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1616 (int) BFD_RELOC_HI16
);
1617 if ((ep
->X_add_number
& 0xffff) != 0)
1618 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1619 (int) BFD_RELOC_LO16
);
1621 else if (mips_isa
< 3)
1623 as_bad ("Number larger than 32 bits");
1624 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1625 (int) BFD_RELOC_LO16
);
1630 expressionS hi32
, lo32
;
1634 hi32
.X_add_number
>>= shift
;
1635 hi32
.X_add_number
&= 0xffffffff;
1636 if ((hi32
.X_add_number
& 0x80000000) != 0)
1637 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1638 load_register (counter
, reg
, &hi32
);
1640 lo32
.X_add_number
&= 0xffffffff;
1641 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1642 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1648 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1651 mid16
.X_add_number
>>= 16;
1652 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1653 reg
, (int) BFD_RELOC_LO16
);
1654 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1657 if ((lo32
.X_add_number
& 0xffff) != 0)
1658 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1659 (int) BFD_RELOC_LO16
);
1663 /* Load an address into a register. */
1666 load_address (counter
, reg
, ep
)
1673 if (ep
->X_op
!= O_constant
1674 && ep
->X_op
!= O_symbol
)
1676 as_bad ("expression too complex");
1677 ep
->X_op
= O_constant
;
1680 if (ep
->X_op
== O_constant
)
1682 load_register (counter
, reg
, ep
);
1686 if (mips_pic
== NO_PIC
)
1688 /* If this is a reference to a GP relative symbol, we want
1689 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1691 lui $reg,<sym> (BFD_RELOC_HI16_S)
1692 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1693 If we have an addend, we always use the latter form. */
1694 if (ep
->X_add_number
!= 0)
1699 macro_build ((char *) NULL
, counter
, ep
,
1700 mips_isa
< 3 ? "addiu" : "daddiu",
1701 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1702 p
= frag_var (rs_machine_dependent
, 8, 0,
1703 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1704 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1706 macro_build_lui (p
, counter
, ep
, reg
);
1709 macro_build (p
, counter
, ep
,
1710 mips_isa
< 3 ? "addiu" : "daddiu",
1711 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1713 else if (mips_pic
== SVR4_PIC
)
1717 /* If this is a reference to an external symbol, we want
1718 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1720 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1722 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1723 If there is a constant, it must be added in after. */
1724 ex
.X_add_number
= ep
->X_add_number
;
1725 ep
->X_add_number
= 0;
1727 macro_build ((char *) NULL
, counter
, ep
,
1728 mips_isa
< 3 ? "lw" : "ld",
1729 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1730 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1731 p
= frag_var (rs_machine_dependent
, 4, 0,
1732 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1733 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1734 macro_build (p
, counter
, ep
,
1735 mips_isa
< 3 ? "addiu" : "daddiu",
1736 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1737 if (ex
.X_add_number
!= 0)
1739 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1740 as_bad ("PIC code offset overflow (max 16 signed bits)");
1741 ex
.X_op
= O_constant
;
1742 macro_build (p
, counter
, &ex
,
1743 mips_isa
< 3 ? "addiu" : "daddiu",
1744 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1747 else if (mips_pic
== EMBEDDED_PIC
)
1750 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1752 macro_build ((char *) NULL
, counter
, ep
,
1753 mips_isa
< 3 ? "addiu" : "daddiu",
1754 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1762 * This routine implements the seemingly endless macro or synthesized
1763 * instructions and addressing modes in the mips assembly language. Many
1764 * of these macros are simple and are similar to each other. These could
1765 * probably be handled by some kind of table or grammer aproach instead of
1766 * this verbose method. Others are not simple macros but are more like
1767 * optimizing code generation.
1768 * One interesting optimization is when several store macros appear
1769 * consecutivly that would load AT with the upper half of the same address.
1770 * The ensuing load upper instructions are ommited. This implies some kind
1771 * of global optimization. We currently only optimize within a single macro.
1772 * For many of the load and store macros if the address is specified as a
1773 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1774 * first load register 'at' with zero and use it as the base register. The
1775 * mips assembler simply uses register $zero. Just one tiny optimization
1780 struct mips_cl_insn
*ip
;
1782 register int treg
, sreg
, dreg
, breg
;
1795 bfd_reloc_code_real_type r
;
1797 int hold_mips_optimize
;
1799 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1800 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1801 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1802 mask
= ip
->insn_mo
->mask
;
1804 expr1
.X_op
= O_constant
;
1805 expr1
.X_op_symbol
= NULL
;
1806 expr1
.X_add_symbol
= NULL
;
1807 expr1
.X_add_number
= 1;
1819 mips_emit_delays ();
1821 mips_any_noreorder
= 1;
1823 expr1
.X_add_number
= 8;
1824 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1826 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1828 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1829 macro_build ((char *) NULL
, &icnt
, NULL
,
1830 dbl
? "dsub" : "sub",
1831 "d,v,t", dreg
, 0, sreg
);
1854 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1856 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1857 (int) BFD_RELOC_LO16
);
1860 load_register (&icnt
, AT
, &imm_expr
);
1861 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1880 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1882 if (mask
!= M_NOR_I
)
1883 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1884 sreg
, (int) BFD_RELOC_LO16
);
1887 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1888 treg
, sreg
, (int) BFD_RELOC_LO16
);
1889 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1895 load_register (&icnt
, AT
, &imm_expr
);
1896 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1913 if (imm_expr
.X_add_number
== 0)
1915 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1919 load_register (&icnt
, AT
, &imm_expr
);
1920 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1929 likely
? "bgezl" : "bgez",
1935 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1936 likely
? "blezl" : "blez",
1940 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1941 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1942 likely
? "beql" : "beq",
1949 /* check for > max integer */
1950 maxnum
= 0x7fffffff;
1958 if (imm_expr
.X_add_number
>= maxnum
)
1961 /* result is always false */
1964 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1965 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1969 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1970 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1975 imm_expr
.X_add_number
++;
1979 if (mask
== M_BGEL_I
)
1981 if (imm_expr
.X_add_number
== 0)
1983 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1984 likely
? "bgezl" : "bgez",
1988 if (imm_expr
.X_add_number
== 1)
1990 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1991 likely
? "bgtzl" : "bgtz",
1995 maxnum
= 0x7fffffff;
2003 maxnum
= - maxnum
- 1;
2004 if (imm_expr
.X_add_number
<= maxnum
)
2007 /* result is always true */
2008 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2009 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2012 set_at (&icnt
, sreg
, 0);
2013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2014 likely
? "beql" : "beq",
2025 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2026 likely
? "beql" : "beq",
2030 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2033 likely
? "beql" : "beq",
2040 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2042 imm_expr
.X_add_number
++;
2046 if (mask
== M_BGEUL_I
)
2048 if (imm_expr
.X_add_number
== 0)
2050 if (imm_expr
.X_add_number
== 1)
2052 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2053 likely
? "bnel" : "bne",
2057 set_at (&icnt
, sreg
, 1);
2058 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2059 likely
? "beql" : "beq",
2068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2069 likely
? "bgtzl" : "bgtz",
2075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2076 likely
? "bltzl" : "bltz",
2080 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2081 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2082 likely
? "bnel" : "bne",
2091 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2092 likely
? "bnel" : "bne",
2098 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2101 likely
? "bnel" : "bne",
2110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2111 likely
? "blezl" : "blez",
2117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2118 likely
? "bgezl" : "bgez",
2122 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2124 likely
? "beql" : "beq",
2131 maxnum
= 0x7fffffff;
2139 if (imm_expr
.X_add_number
>= maxnum
)
2141 imm_expr
.X_add_number
++;
2145 if (mask
== M_BLTL_I
)
2147 if (imm_expr
.X_add_number
== 0)
2149 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2150 likely
? "bltzl" : "bltz",
2154 if (imm_expr
.X_add_number
== 1)
2156 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2157 likely
? "blezl" : "blez",
2161 set_at (&icnt
, sreg
, 0);
2162 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2163 likely
? "bnel" : "bne",
2172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2173 likely
? "beql" : "beq",
2179 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2181 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2182 likely
? "beql" : "beq",
2189 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2191 imm_expr
.X_add_number
++;
2195 if (mask
== M_BLTUL_I
)
2197 if (imm_expr
.X_add_number
== 0)
2199 if (imm_expr
.X_add_number
== 1)
2201 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2202 likely
? "beql" : "beq",
2206 set_at (&icnt
, sreg
, 1);
2207 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2208 likely
? "bnel" : "bne",
2217 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2218 likely
? "bltzl" : "bltz",
2224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2225 likely
? "bgtzl" : "bgtz",
2229 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2230 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2231 likely
? "bnel" : "bne",
2242 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2243 likely
? "bnel" : "bne",
2247 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2249 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2250 likely
? "bnel" : "bne",
2266 as_warn ("Divide by zero.");
2268 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2270 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2274 mips_emit_delays ();
2276 mips_any_noreorder
= 1;
2277 macro_build ((char *) NULL
, &icnt
, NULL
,
2278 dbl
? "ddiv" : "div",
2279 "z,s,t", sreg
, treg
);
2281 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2284 expr1
.X_add_number
= 8;
2285 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2286 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2287 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2289 expr1
.X_add_number
= -1;
2290 macro_build ((char *) NULL
, &icnt
, &expr1
,
2291 dbl
? "daddiu" : "addiu",
2292 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2293 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2294 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2297 expr1
.X_add_number
= 1;
2298 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2299 (int) BFD_RELOC_LO16
);
2300 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2305 expr1
.X_add_number
= 0x80000000;
2306 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2307 (int) BFD_RELOC_HI16
);
2310 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2313 expr1
.X_add_number
= 8;
2314 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2315 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2316 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2319 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2358 if (imm_expr
.X_add_number
== 0)
2360 as_warn ("Divide by zero.");
2362 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2364 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2367 if (imm_expr
.X_add_number
== 1)
2369 if (strcmp (s2
, "mflo") == 0)
2370 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2373 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2376 if (imm_expr
.X_add_number
== -1
2377 && s
[strlen (s
) - 1] != 'u')
2379 if (strcmp (s2
, "mflo") == 0)
2382 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2385 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2389 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2393 load_register (&icnt
, AT
, &imm_expr
);
2394 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2395 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2414 mips_emit_delays ();
2416 mips_any_noreorder
= 1;
2417 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2419 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2422 expr1
.X_add_number
= 8;
2423 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2424 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2425 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2428 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2432 /* Load the address of a symbol into a register. If breg is not
2433 zero, we then add a base register to it. */
2435 /* When generating embedded PIC code, we permit expressions of
2438 where bar is an address in the .text section. These are used
2439 when getting the addresses of functions. We don't permit
2440 X_add_number to be non-zero, because if the symbol is
2441 external the relaxing code needs to know that any addend is
2442 purely the offset to X_op_symbol. */
2443 if (mips_pic
== EMBEDDED_PIC
2444 && offset_expr
.X_op
== O_subtract
2445 && now_seg
== text_section
2446 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2448 && offset_expr
.X_add_number
== 0)
2450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2451 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2452 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2453 mips_isa
< 3 ? "addiu" : "daddiu",
2454 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2458 if (offset_expr
.X_op
!= O_symbol
2459 && offset_expr
.X_op
!= O_constant
)
2461 as_bad ("expression too complex");
2462 offset_expr
.X_op
= O_constant
;
2476 if (offset_expr
.X_op
== O_constant
)
2477 load_register (&icnt
, tempreg
, &offset_expr
);
2478 else if (mips_pic
== NO_PIC
)
2480 /* If this is a reference to an GP relative symbol, we want
2481 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2483 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2484 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2485 If we have a constant, we need two instructions anyhow,
2486 so we may as well always use the latter form. */
2487 if (offset_expr
.X_add_number
!= 0)
2492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2493 mips_isa
< 3 ? "addiu" : "daddiu",
2494 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2495 p
= frag_var (rs_machine_dependent
, 8, 0,
2496 RELAX_ENCODE (4, 8, 0, 4, 0,
2497 mips_warn_about_macros
),
2498 offset_expr
.X_add_symbol
, (long) 0,
2501 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2504 macro_build (p
, &icnt
, &offset_expr
,
2505 mips_isa
< 3 ? "addiu" : "daddiu",
2506 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2508 else if (mips_pic
== SVR4_PIC
)
2510 /* If this is a reference to an external symbol, and there
2511 is no constant, we want
2512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2513 For a local symbol, we want
2514 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2516 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2518 If we have a small constant, and this is a reference to
2519 an external symbol, we want
2520 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2522 addiu $tempreg,$tempreg,<constant>
2523 For a local symbol, we want the same instruction
2524 sequence, but we output a BFD_RELOC_LO16 reloc on the
2527 If we have a large constant, and this is a reference to
2528 an external symbol, we want
2529 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2530 lui $at,<hiconstant>
2531 addiu $at,$at,<loconstant>
2532 addu $tempreg,$tempreg,$at
2533 For a local symbol, we want the same instruction
2534 sequence, but we output a BFD_RELOC_LO16 reloc on the
2535 addiu instruction. */
2536 expr1
.X_add_number
= offset_expr
.X_add_number
;
2537 offset_expr
.X_add_number
= 0;
2539 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2540 mips_isa
< 3 ? "lw" : "ld",
2541 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2542 if (expr1
.X_add_number
== 0)
2550 /* We're going to put in an addu instruction using
2551 tempreg, so we may as well insert the nop right
2553 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2557 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2558 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2560 ? mips_warn_about_macros
2562 offset_expr
.X_add_symbol
, (long) 0,
2566 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2569 macro_build (p
, &icnt
, &expr1
,
2570 mips_isa
< 3 ? "addiu" : "daddiu",
2571 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2572 /* FIXME: If breg == 0, and the next instruction uses
2573 $tempreg, then if this variant case is used an extra
2574 nop will be generated. */
2576 else if (expr1
.X_add_number
>= -0x8000
2577 && expr1
.X_add_number
< 0x8000)
2579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2581 macro_build ((char *) NULL
, &icnt
, &expr1
,
2582 mips_isa
< 3 ? "addiu" : "daddiu",
2583 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2584 (void) frag_var (rs_machine_dependent
, 0, 0,
2585 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2586 offset_expr
.X_add_symbol
, (long) 0,
2593 /* If we are going to add in a base register, and the
2594 target register and the base register are the same,
2595 then we are using AT as a temporary register. Since
2596 we want to load the constant into AT, we add our
2597 current AT (from the global offset table) and the
2598 register into the register now, and pretend we were
2599 not using a base register. */
2604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2607 mips_isa
< 3 ? "addu" : "daddu",
2608 "d,v,t", treg
, AT
, breg
);
2614 /* Set mips_optimize around the lui instruction to avoid
2615 inserting an unnecessary nop after the lw. */
2616 hold_mips_optimize
= mips_optimize
;
2618 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2619 mips_optimize
= hold_mips_optimize
;
2621 macro_build ((char *) NULL
, &icnt
, &expr1
,
2622 mips_isa
< 3 ? "addiu" : "daddiu",
2623 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2624 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2625 mips_isa
< 3 ? "addu" : "daddu",
2626 "d,v,t", tempreg
, tempreg
, AT
);
2627 (void) frag_var (rs_machine_dependent
, 0, 0,
2628 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2629 offset_expr
.X_add_symbol
, (long) 0,
2634 else if (mips_pic
== EMBEDDED_PIC
)
2637 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2640 mips_isa
< 3 ? "addiu" : "daddiu",
2641 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2647 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2648 mips_isa
< 3 ? "addu" : "daddu",
2649 "d,v,t", treg
, tempreg
, breg
);
2657 /* The j instruction may not be used in PIC code, since it
2658 requires an absolute address. We convert it to a b
2660 if (mips_pic
== NO_PIC
)
2661 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2663 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2666 /* The jal instructions must be handled as macros because when
2667 generating PIC code they expand to multi-instruction
2668 sequences. Normally they are simple instructions. */
2673 if (mips_pic
== NO_PIC
2674 || mips_pic
== EMBEDDED_PIC
)
2675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2677 else if (mips_pic
== SVR4_PIC
)
2679 if (sreg
!= PIC_CALL_REG
)
2680 as_warn ("MIPS PIC call to register other than $25");
2682 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2684 if (mips_cprestore_offset
< 0)
2685 as_warn ("No .cprestore pseudo-op used in PIC code");
2688 expr1
.X_add_number
= mips_cprestore_offset
;
2689 macro_build ((char *) NULL
, &icnt
, &expr1
,
2690 mips_isa
< 3 ? "lw" : "ld",
2691 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2700 if (mips_pic
== NO_PIC
)
2701 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2702 else if (mips_pic
== SVR4_PIC
)
2704 /* If this is a reference to an external symbol, we want
2705 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2709 lw $gp,cprestore($sp)
2710 The cprestore value is set using the .cprestore
2711 pseudo-op. If the symbol is not external, we want
2712 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2714 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2717 lw $gp,cprestore($sp)
2720 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2721 mips_isa
< 3 ? "lw" : "ld",
2722 "t,o(b)", PIC_CALL_REG
,
2723 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2725 p
= frag_var (rs_machine_dependent
, 4, 0,
2726 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2727 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2728 macro_build (p
, &icnt
, &offset_expr
,
2729 mips_isa
< 3 ? "addiu" : "daddiu",
2730 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2731 (int) BFD_RELOC_LO16
);
2732 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2733 "jalr", "s", PIC_CALL_REG
);
2734 if (mips_cprestore_offset
< 0)
2735 as_warn ("No .cprestore pseudo-op used in PIC code");
2739 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2741 expr1
.X_add_number
= mips_cprestore_offset
;
2742 macro_build ((char *) NULL
, &icnt
, &expr1
,
2743 mips_isa
< 3 ? "lw" : "ld",
2744 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2748 else if (mips_pic
== EMBEDDED_PIC
)
2750 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2751 /* The linker may expand the call to a longer sequence which
2752 uses $at, so we must break rather than return. */
2824 if (breg
== treg
|| coproc
)
2893 if (mask
== M_LWC1_AB
2894 || mask
== M_SWC1_AB
2895 || mask
== M_LDC1_AB
2896 || mask
== M_SDC1_AB
2905 if (offset_expr
.X_op
!= O_constant
2906 && offset_expr
.X_op
!= O_symbol
)
2908 as_bad ("expression too complex");
2909 offset_expr
.X_op
= O_constant
;
2912 /* A constant expression in PIC code can be handled just as it
2913 is in non PIC code. */
2914 if (mips_pic
== NO_PIC
2915 || offset_expr
.X_op
== O_constant
)
2917 /* If this is a reference to a GP relative symbol, and there
2918 is no base register, we want
2919 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2920 Otherwise, if there is no base register, we want
2921 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2922 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2923 If we have a constant, we need two instructions anyhow,
2924 so we always use the latter form.
2926 If we have a base register, and this is a reference to a
2927 GP relative symbol, we want
2928 addu $tempreg,$breg,$gp
2929 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2931 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2932 addu $tempreg,$tempreg,$breg
2933 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2934 With a constant we always use the latter case. */
2937 if (offset_expr
.X_add_number
!= 0)
2942 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2943 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2944 p
= frag_var (rs_machine_dependent
, 8, 0,
2945 RELAX_ENCODE (4, 8, 0, 4, 0,
2946 (mips_warn_about_macros
2947 || (used_at
&& mips_noat
))),
2948 offset_expr
.X_add_symbol
, (long) 0,
2952 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2955 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2956 (int) BFD_RELOC_LO16
, tempreg
);
2960 if (offset_expr
.X_add_number
!= 0)
2965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2966 mips_isa
< 3 ? "addu" : "daddu",
2967 "d,v,t", tempreg
, breg
, GP
);
2968 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2969 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2970 p
= frag_var (rs_machine_dependent
, 12, 0,
2971 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2972 offset_expr
.X_add_symbol
, (long) 0,
2975 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2978 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2979 mips_isa
< 3 ? "addu" : "daddu",
2980 "d,v,t", tempreg
, tempreg
, breg
);
2983 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2984 (int) BFD_RELOC_LO16
, tempreg
);
2987 else if (mips_pic
== SVR4_PIC
)
2989 /* If this is a reference to an external symbol, we want
2990 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2992 <op> $treg,0($tempreg)
2994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2996 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2997 <op> $treg,0($tempreg)
2998 If there is a base register, we add it to $tempreg before
2999 the <op>. If there is a constant, we stick it in the
3000 <op> instruction. We don't handle constants larger than
3001 16 bits, because we have no way to load the upper 16 bits
3002 (actually, we could handle them for the subset of cases
3003 in which we are not using $at). */
3004 assert (offset_expr
.X_op
== O_symbol
);
3005 expr1
.X_add_number
= offset_expr
.X_add_number
;
3006 offset_expr
.X_add_number
= 0;
3007 if (expr1
.X_add_number
< -0x8000
3008 || expr1
.X_add_number
>= 0x8000)
3009 as_bad ("PIC code offset overflow (max 16 signed bits)");
3011 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3012 mips_isa
< 3 ? "lw" : "ld",
3013 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3015 p
= frag_var (rs_machine_dependent
, 4, 0,
3016 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3017 offset_expr
.X_add_symbol
, (long) 0,
3019 macro_build (p
, &icnt
, &offset_expr
,
3020 mips_isa
< 3 ? "addiu" : "daddiu",
3021 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3024 mips_isa
< 3 ? "addu" : "daddu",
3025 "d,v,t", tempreg
, tempreg
, breg
);
3026 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3027 (int) BFD_RELOC_LO16
, tempreg
);
3029 else if (mips_pic
== EMBEDDED_PIC
)
3031 /* If there is no base register, we want
3032 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3033 If there is a base register, we want
3034 addu $tempreg,$breg,$gp
3035 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3037 assert (offset_expr
.X_op
== O_symbol
);
3040 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3041 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3046 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3047 mips_isa
< 3 ? "addu" : "daddu",
3048 "d,v,t", tempreg
, breg
, GP
);
3049 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3050 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3063 load_register (&icnt
, treg
, &imm_expr
);
3067 if (imm_expr
.X_op
== O_constant
)
3069 load_register (&icnt
, AT
, &imm_expr
);
3070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3071 "mtc1", "t,G", AT
, treg
);
3076 assert (offset_expr
.X_op
== O_symbol
3077 && strcmp (segment_name (S_GET_SEGMENT
3078 (offset_expr
.X_add_symbol
)),
3080 && offset_expr
.X_add_number
== 0);
3081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3082 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3087 /* We know that sym is in the .rdata section. First we get the
3088 upper 16 bits of the address. */
3089 if (mips_pic
== NO_PIC
)
3091 /* FIXME: This won't work for a 64 bit address. */
3092 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3094 else if (mips_pic
== SVR4_PIC
)
3096 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3097 mips_isa
< 3 ? "lw" : "ld",
3098 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3100 else if (mips_pic
== EMBEDDED_PIC
)
3102 /* For embedded PIC we pick up the entire address off $gp in
3103 a single instruction. */
3104 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3105 mips_isa
< 3 ? "addiu" : "daddiu",
3106 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3107 offset_expr
.X_op
= O_constant
;
3108 offset_expr
.X_add_number
= 0;
3113 /* Now we load the register(s). */
3115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3116 treg
, (int) BFD_RELOC_LO16
, AT
);
3119 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3120 treg
, (int) BFD_RELOC_LO16
, AT
);
3123 /* FIXME: How in the world do we deal with the possible
3125 offset_expr
.X_add_number
+= 4;
3126 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3127 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3131 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3132 does not become a variant frag. */
3133 frag_wane (frag_now
);
3139 assert (offset_expr
.X_op
== O_symbol
3140 && offset_expr
.X_add_number
== 0);
3141 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3142 if (strcmp (s
, ".lit8") == 0)
3146 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3147 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3151 r
= BFD_RELOC_MIPS_LITERAL
;
3156 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3157 if (mips_pic
== SVR4_PIC
)
3158 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3159 mips_isa
< 3 ? "lw" : "ld",
3160 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3163 /* FIXME: This won't work for a 64 bit address. */
3164 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3169 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3170 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3179 /* Even on a big endian machine $fn comes before $fn+1. We have
3180 to adjust when loading from memory. */
3183 assert (mips_isa
< 2);
3184 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3185 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3187 /* FIXME: A possible overflow which I don't know how to deal
3189 offset_expr
.X_add_number
+= 4;
3190 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3191 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3194 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3195 does not become a variant frag. */
3196 frag_wane (frag_now
);
3205 * The MIPS assembler seems to check for X_add_number not
3206 * being double aligned and generating:
3209 * addiu at,at,%lo(foo+1)
3212 * But, the resulting address is the same after relocation so why
3213 * generate the extra instruction?
3260 if (offset_expr
.X_op
!= O_symbol
3261 && offset_expr
.X_op
!= O_constant
)
3263 as_bad ("expression too complex");
3264 offset_expr
.X_op
= O_constant
;
3267 /* Even on a big endian machine $fn comes before $fn+1. We have
3268 to adjust when loading from memory. We set coproc if we must
3269 load $fn+1 first. */
3270 if (byte_order
== LITTLE_ENDIAN
)
3273 if (mips_pic
== NO_PIC
3274 || offset_expr
.X_op
== O_constant
)
3276 /* If this is a reference to a GP relative symbol, we want
3277 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3278 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3279 If we have a base register, we use this
3281 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3282 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3283 If this is not a GP relative symbol, we want
3284 lui $at,<sym> (BFD_RELOC_HI16_S)
3285 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3286 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3287 If there is a base register, we add it to $at after the
3288 lui instruction. If there is a constant, we always use
3290 if (offset_expr
.X_add_number
!= 0)
3309 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3310 mips_isa
< 3 ? "addu" : "daddu",
3311 "d,v,t", AT
, breg
, GP
);
3317 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3318 coproc
? treg
+ 1 : treg
,
3319 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3320 offset_expr
.X_add_number
+= 4;
3322 /* Set mips_optimize to 2 to avoid inserting an
3324 hold_mips_optimize
= mips_optimize
;
3326 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3327 coproc
? treg
: treg
+ 1,
3328 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3329 mips_optimize
= hold_mips_optimize
;
3331 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3332 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3333 used_at
&& mips_noat
),
3334 offset_expr
.X_add_symbol
, (long) 0,
3337 /* We just generated two relocs. When tc_gen_reloc
3338 handles this case, it will skip the first reloc and
3339 handle the second. The second reloc already has an
3340 extra addend of 4, which we added above. We must
3341 subtract it out, and then subtract another 4 to make
3342 the first reloc come out right. The second reloc
3343 will come out right because we are going to add 4 to
3344 offset_expr when we build its instruction below. */
3345 offset_expr
.X_add_number
-= 8;
3346 offset_expr
.X_op
= O_constant
;
3348 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3353 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3354 mips_isa
< 3 ? "addu" : "daddu",
3355 "d,v,t", AT
, breg
, AT
);
3359 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3360 coproc
? treg
+ 1 : treg
,
3361 (int) BFD_RELOC_LO16
, AT
);
3364 /* FIXME: How do we handle overflow here? */
3365 offset_expr
.X_add_number
+= 4;
3366 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3367 coproc
? treg
: treg
+ 1,
3368 (int) BFD_RELOC_LO16
, AT
);
3370 else if (mips_pic
== SVR4_PIC
)
3374 /* If this is a reference to an external symbol, we want
3375 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3380 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3382 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3383 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3384 If there is a base register we add it to $at before the
3385 lwc1 instructions. If there is a constant we include it
3386 in the lwc1 instructions. */
3388 expr1
.X_add_number
= offset_expr
.X_add_number
;
3389 offset_expr
.X_add_number
= 0;
3390 if (expr1
.X_add_number
< -0x8000
3391 || expr1
.X_add_number
>= 0x8000 - 4)
3392 as_bad ("PIC code offset overflow (max 16 signed bits)");
3397 frag_grow (24 + off
);
3398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3399 mips_isa
< 3 ? "lw" : "ld",
3400 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3401 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3404 mips_isa
< 3 ? "addu" : "daddu",
3405 "d,v,t", AT
, breg
, AT
);
3406 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3407 coproc
? treg
+ 1 : treg
,
3408 (int) BFD_RELOC_LO16
, AT
);
3409 expr1
.X_add_number
+= 4;
3411 /* Set mips_optimize to 2 to avoid inserting an undesired
3413 hold_mips_optimize
= mips_optimize
;
3415 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3416 coproc
? treg
: treg
+ 1,
3417 (int) BFD_RELOC_LO16
, AT
);
3418 mips_optimize
= hold_mips_optimize
;
3420 (void) frag_var (rs_machine_dependent
, 0, 0,
3421 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3422 offset_expr
.X_add_symbol
, (long) 0,
3425 else if (mips_pic
== EMBEDDED_PIC
)
3427 /* If there is no base register, we use
3428 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3429 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3430 If we have a base register, we use
3432 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3433 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3442 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3443 mips_isa
< 3 ? "addu" : "daddu",
3444 "d,v,t", AT
, breg
, GP
);
3449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3450 coproc
? treg
+ 1 : treg
,
3451 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3452 offset_expr
.X_add_number
+= 4;
3453 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3454 coproc
? treg
: treg
+ 1,
3455 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3471 assert (mips_isa
< 3);
3472 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3473 (int) BFD_RELOC_LO16
, breg
);
3474 offset_expr
.X_add_number
+= 4;
3475 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3476 (int) BFD_RELOC_LO16
, breg
);
3478 #ifdef LOSING_COMPILER
3484 as_warn ("Macro used $at after \".set noat\"");
3489 struct mips_cl_insn
*ip
;
3491 register int treg
, sreg
, dreg
, breg
;
3504 bfd_reloc_code_real_type r
;
3507 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3508 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3509 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3510 mask
= ip
->insn_mo
->mask
;
3512 expr1
.X_op
= O_constant
;
3513 expr1
.X_op_symbol
= NULL
;
3514 expr1
.X_add_symbol
= NULL
;
3515 expr1
.X_add_number
= 1;
3519 #endif /* LOSING_COMPILER */
3524 macro_build ((char *) NULL
, &icnt
, NULL
,
3525 dbl
? "dmultu" : "multu",
3527 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3533 /* The MIPS assembler some times generates shifts and adds. I'm
3534 not trying to be that fancy. GCC should do this for us
3536 load_register (&icnt
, AT
, &imm_expr
);
3537 macro_build ((char *) NULL
, &icnt
, NULL
,
3538 dbl
? "dmult" : "mult",
3540 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3546 mips_emit_delays ();
3548 mips_any_noreorder
= 1;
3549 macro_build ((char *) NULL
, &icnt
, NULL
,
3550 dbl
? "dmult" : "mult",
3552 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3553 macro_build ((char *) NULL
, &icnt
, NULL
,
3554 dbl
? "dsra32" : "sra",
3555 "d,w,<", dreg
, dreg
, 31);
3556 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3558 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3561 expr1
.X_add_number
= 8;
3562 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3563 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3564 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3567 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3573 mips_emit_delays ();
3575 mips_any_noreorder
= 1;
3576 macro_build ((char *) NULL
, &icnt
, NULL
,
3577 dbl
? "dmultu" : "multu",
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3580 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3582 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3585 expr1
.X_add_number
= 8;
3586 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3587 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3588 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3594 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3595 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3596 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3598 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3602 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3603 imm_expr
.X_add_number
& 0x1f);
3604 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3605 (0 - imm_expr
.X_add_number
) & 0x1f);
3606 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3610 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3611 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3612 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3614 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3619 imm_expr
.X_add_number
& 0x1f);
3620 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3621 (0 - imm_expr
.X_add_number
) & 0x1f);
3622 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3626 assert (mips_isa
< 2);
3627 /* Even on a big endian machine $fn comes before $fn+1. We have
3628 to adjust when storing to memory. */
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3630 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3631 (int) BFD_RELOC_LO16
, breg
);
3632 offset_expr
.X_add_number
+= 4;
3633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3634 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3635 (int) BFD_RELOC_LO16
, breg
);
3640 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3641 treg
, (int) BFD_RELOC_LO16
);
3643 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3644 sreg
, (int) BFD_RELOC_LO16
);
3647 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3649 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3650 dreg
, (int) BFD_RELOC_LO16
);
3655 if (imm_expr
.X_add_number
== 0)
3657 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3658 sreg
, (int) BFD_RELOC_LO16
);
3663 as_warn ("Instruction %s: result is always false",
3665 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3668 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3670 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3671 sreg
, (int) BFD_RELOC_LO16
);
3674 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3676 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3677 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3678 mips_isa
< 3 ? "addiu" : "daddiu",
3679 "t,r,j", dreg
, sreg
,
3680 (int) BFD_RELOC_LO16
);
3685 load_register (&icnt
, AT
, &imm_expr
);
3686 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3690 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3691 (int) BFD_RELOC_LO16
);
3696 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3702 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3703 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3704 (int) BFD_RELOC_LO16
);
3707 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3709 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3711 macro_build ((char *) NULL
, &icnt
, &expr1
,
3712 mask
== M_SGE_I
? "slti" : "sltiu",
3713 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3718 load_register (&icnt
, AT
, &imm_expr
);
3719 macro_build ((char *) NULL
, &icnt
, NULL
,
3720 mask
== M_SGE_I
? "slt" : "sltu",
3721 "d,v,t", dreg
, sreg
, AT
);
3724 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3725 (int) BFD_RELOC_LO16
);
3730 case M_SGT
: /* sreg > treg <==> treg < sreg */
3736 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3739 case M_SGT_I
: /* sreg > I <==> I < sreg */
3745 load_register (&icnt
, AT
, &imm_expr
);
3746 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3749 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3755 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3756 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3757 (int) BFD_RELOC_LO16
);
3760 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3766 load_register (&icnt
, AT
, &imm_expr
);
3767 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3768 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3769 (int) BFD_RELOC_LO16
);
3773 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3775 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3776 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3779 load_register (&icnt
, AT
, &imm_expr
);
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3784 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3786 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3787 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3790 load_register (&icnt
, AT
, &imm_expr
);
3791 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3800 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3804 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3806 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3812 if (imm_expr
.X_add_number
== 0)
3814 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3820 as_warn ("Instruction %s: result is always true",
3822 macro_build ((char *) NULL
, &icnt
, &expr1
,
3823 mips_isa
< 3 ? "addiu" : "daddiu",
3824 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3827 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3829 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3830 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3833 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3835 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3836 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3837 mips_isa
< 3 ? "addiu" : "daddiu",
3838 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3843 load_register (&icnt
, AT
, &imm_expr
);
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3848 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3856 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3858 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3859 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3860 dbl
? "daddi" : "addi",
3861 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3864 load_register (&icnt
, AT
, &imm_expr
);
3865 macro_build ((char *) NULL
, &icnt
, NULL
,
3866 dbl
? "dsub" : "sub",
3867 "d,v,t", dreg
, sreg
, AT
);
3873 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3875 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3876 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3877 dbl
? "daddiu" : "addiu",
3878 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3881 load_register (&icnt
, AT
, &imm_expr
);
3882 macro_build ((char *) NULL
, &icnt
, NULL
,
3883 dbl
? "dsubu" : "subu",
3884 "d,v,t", dreg
, sreg
, AT
);
3905 load_register (&icnt
, AT
, &imm_expr
);
3906 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3911 assert (mips_isa
< 2);
3912 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3913 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3916 * Is the double cfc1 instruction a bug in the mips assembler;
3917 * or is there a reason for it?
3919 mips_emit_delays ();
3921 mips_any_noreorder
= 1;
3922 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3923 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3924 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3925 expr1
.X_add_number
= 3;
3926 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3927 (int) BFD_RELOC_LO16
);
3928 expr1
.X_add_number
= 2;
3929 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3930 (int) BFD_RELOC_LO16
);
3931 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3932 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3933 macro_build ((char *) NULL
, &icnt
, NULL
,
3934 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3935 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3936 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3946 if (offset_expr
.X_add_number
>= 0x7fff)
3947 as_bad ("operand overflow");
3948 /* avoid load delay */
3949 if (byte_order
== LITTLE_ENDIAN
)
3950 offset_expr
.X_add_number
+= 1;
3951 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3952 (int) BFD_RELOC_LO16
, breg
);
3953 if (byte_order
== LITTLE_ENDIAN
)
3954 offset_expr
.X_add_number
-= 1;
3956 offset_expr
.X_add_number
+= 1;
3957 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3958 (int) BFD_RELOC_LO16
, breg
);
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3964 if (offset_expr
.X_add_number
>= 0x7ffd)
3965 as_bad ("operand overflow");
3966 if (byte_order
== LITTLE_ENDIAN
)
3967 offset_expr
.X_add_number
+= 3;
3968 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3969 (int) BFD_RELOC_LO16
, breg
);
3970 if (byte_order
== LITTLE_ENDIAN
)
3971 offset_expr
.X_add_number
-= 3;
3973 offset_expr
.X_add_number
+= 3;
3974 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3975 (int) BFD_RELOC_LO16
, breg
);
3981 load_address (&icnt
, AT
, &offset_expr
);
3982 if (mask
== M_ULW_A
)
3984 if (byte_order
== LITTLE_ENDIAN
)
3985 expr1
.X_add_number
= 3;
3987 expr1
.X_add_number
= 0;
3988 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3989 (int) BFD_RELOC_LO16
, AT
);
3990 if (byte_order
== LITTLE_ENDIAN
)
3991 expr1
.X_add_number
= 0;
3993 expr1
.X_add_number
= 3;
3994 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3995 (int) BFD_RELOC_LO16
, AT
);
3999 if (byte_order
== BIG_ENDIAN
)
4000 expr1
.X_add_number
= 0;
4001 macro_build ((char *) NULL
, &icnt
, &expr1
,
4002 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4003 (int) BFD_RELOC_LO16
, AT
);
4004 if (byte_order
== BIG_ENDIAN
)
4005 expr1
.X_add_number
= 1;
4007 expr1
.X_add_number
= 0;
4008 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4009 (int) BFD_RELOC_LO16
, AT
);
4010 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4012 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4018 if (offset_expr
.X_add_number
>= 0x7fff)
4019 as_bad ("operand overflow");
4020 if (byte_order
== BIG_ENDIAN
)
4021 offset_expr
.X_add_number
+= 1;
4022 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4023 (int) BFD_RELOC_LO16
, breg
);
4024 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4025 if (byte_order
== BIG_ENDIAN
)
4026 offset_expr
.X_add_number
-= 1;
4028 offset_expr
.X_add_number
+= 1;
4029 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4030 (int) BFD_RELOC_LO16
, breg
);
4034 if (offset_expr
.X_add_number
>= 0x7ffd)
4035 as_bad ("operand overflow");
4036 if (byte_order
== LITTLE_ENDIAN
)
4037 offset_expr
.X_add_number
+= 3;
4038 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
4039 (int) BFD_RELOC_LO16
, breg
);
4040 if (byte_order
== LITTLE_ENDIAN
)
4041 offset_expr
.X_add_number
-= 3;
4043 offset_expr
.X_add_number
+= 3;
4044 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
4045 (int) BFD_RELOC_LO16
, breg
);
4050 load_address (&icnt
, AT
, &offset_expr
);
4051 if (mask
== M_USW_A
)
4053 if (byte_order
== LITTLE_ENDIAN
)
4054 expr1
.X_add_number
= 3;
4056 expr1
.X_add_number
= 0;
4057 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
4058 (int) BFD_RELOC_LO16
, AT
);
4059 if (byte_order
== LITTLE_ENDIAN
)
4060 expr1
.X_add_number
= 0;
4062 expr1
.X_add_number
= 3;
4063 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
4064 (int) BFD_RELOC_LO16
, AT
);
4068 if (byte_order
== LITTLE_ENDIAN
)
4069 expr1
.X_add_number
= 0;
4070 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4071 (int) BFD_RELOC_LO16
, AT
);
4072 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4074 if (byte_order
== LITTLE_ENDIAN
)
4075 expr1
.X_add_number
= 1;
4077 expr1
.X_add_number
= 0;
4078 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4079 (int) BFD_RELOC_LO16
, AT
);
4080 if (byte_order
== LITTLE_ENDIAN
)
4081 expr1
.X_add_number
= 0;
4083 expr1
.X_add_number
= 1;
4084 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4085 (int) BFD_RELOC_LO16
, AT
);
4086 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4088 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4094 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4098 as_warn ("Macro used $at after \".set noat\"");
4103 This routine assembles an instruction into its binary format. As a side
4104 effect it sets one of the global variables imm_reloc or offset_reloc to the
4105 type of relocation to do if one of the operands is an address expression.
4110 struct mips_cl_insn
*ip
;
4115 struct mips_opcode
*insn
;
4118 unsigned int lastregno
= 0;
4123 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4135 as_fatal ("Unknown opcode: `%s'", str
);
4137 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4139 as_warn ("`%s' not in hash table.", str
);
4140 insn_error
= "ERROR: Unrecognized opcode";
4148 assert (strcmp (insn
->name
, str
) == 0);
4150 if (insn
->pinfo
== INSN_MACRO
)
4151 insn_isa
= insn
->match
;
4152 else if (insn
->pinfo
& INSN_ISA2
)
4154 else if (insn
->pinfo
& INSN_ISA3
)
4159 if (insn_isa
> mips_isa
)
4161 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4162 && strcmp (insn
->name
, insn
[1].name
) == 0)
4167 as_warn ("Instruction not supported on this processor");
4171 ip
->insn_opcode
= insn
->match
;
4172 for (args
= insn
->args
;; ++args
)
4178 case '\0': /* end of args */
4191 ip
->insn_opcode
|= lastregno
<< 21;
4196 ip
->insn_opcode
|= lastregno
<< 16;
4200 ip
->insn_opcode
|= lastregno
<< 11;
4206 /* handle optional base register.
4207 Either the base register is omitted or
4208 we must have a left paren. */
4209 /* this is dependent on the next operand specifier
4210 is a 'b' for base register */
4211 assert (args
[1] == 'b');
4215 case ')': /* these must match exactly */
4220 case '<': /* must be at least one digit */
4222 * According to the manual, if the shift amount is greater
4223 * than 31 or less than 0 the the shift amount should be
4224 * mod 32. In reality the mips assembler issues an error.
4225 * We issue a warning and mask out all but the low 5 bits.
4227 my_getExpression (&imm_expr
, s
);
4228 check_absolute_expr (ip
, &imm_expr
);
4229 if ((unsigned long) imm_expr
.X_add_number
> 31)
4231 as_warn ("Improper shift amount (%ld)",
4232 (long) imm_expr
.X_add_number
);
4233 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4235 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4236 imm_expr
.X_op
= O_absent
;
4240 case '>': /* shift amount minus 32 */
4241 my_getExpression (&imm_expr
, s
);
4242 check_absolute_expr (ip
, &imm_expr
);
4243 if ((unsigned long) imm_expr
.X_add_number
< 32
4244 || (unsigned long) imm_expr
.X_add_number
> 63)
4246 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4247 imm_expr
.X_op
= O_absent
;
4251 case 'k': /* cache code */
4252 my_getExpression (&imm_expr
, s
);
4253 check_absolute_expr (ip
, &imm_expr
);
4254 if ((unsigned long) imm_expr
.X_add_number
> 31)
4256 as_warn ("Invalid cahce opcode (%lu)",
4257 (unsigned long) imm_expr
.X_add_number
);
4258 imm_expr
.X_add_number
&= 0x1f;
4260 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4261 imm_expr
.X_op
= O_absent
;
4265 case 'c': /* break code */
4266 my_getExpression (&imm_expr
, s
);
4267 check_absolute_expr (ip
, &imm_expr
);
4268 if ((unsigned) imm_expr
.X_add_number
> 1023)
4269 as_warn ("Illegal break code (%ld)",
4270 (long) imm_expr
.X_add_number
);
4271 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4272 imm_expr
.X_op
= O_absent
;
4276 case 'B': /* syscall code */
4277 my_getExpression (&imm_expr
, s
);
4278 check_absolute_expr (ip
, &imm_expr
);
4279 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4280 as_warn ("Illegal syscall code (%ld)",
4281 (long) imm_expr
.X_add_number
);
4282 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4283 imm_expr
.X_op
= O_absent
;
4287 case 'C': /* Coprocessor code */
4288 my_getExpression (&imm_expr
, s
);
4289 check_absolute_expr (ip
, &imm_expr
);
4290 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4292 as_warn ("Coproccesor code > 25 bits (%ld)",
4293 (long) imm_expr
.X_add_number
);
4294 imm_expr
.X_add_number
&= ((1<<25) - 1);
4296 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4297 imm_expr
.X_op
= O_absent
;
4301 case 'b': /* base register */
4302 case 'd': /* destination register */
4303 case 's': /* source register */
4304 case 't': /* target register */
4305 case 'r': /* both target and source */
4306 case 'v': /* both dest and source */
4307 case 'w': /* both dest and target */
4308 case 'E': /* coprocessor target register */
4309 case 'G': /* coprocessor destination register */
4310 case 'x': /* ignore register name */
4311 case 'z': /* must be zero register */
4325 while (isdigit (*s
));
4327 as_bad ("Invalid register number (%d)", regno
);
4329 else if (*args
== 'E' || *args
== 'G')
4333 if (s
[1] == 'f' && s
[2] == 'p')
4338 else if (s
[1] == 's' && s
[2] == 'p')
4343 else if (s
[1] == 'g' && s
[2] == 'p')
4348 else if (s
[1] == 'a' && s
[2] == 't')
4356 if (regno
== AT
&& ! mips_noat
)
4357 as_warn ("Used $at without \".set noat\"");
4363 if (c
== 'r' || c
== 'v' || c
== 'w')
4370 /* 'z' only matches $0. */
4371 if (c
== 'z' && regno
!= 0)
4379 ip
->insn_opcode
|= regno
<< 21;
4383 ip
->insn_opcode
|= regno
<< 11;
4388 ip
->insn_opcode
|= regno
<< 16;
4391 /* This case exists because on the r3000 trunc
4392 expands into a macro which requires a gp
4393 register. On the r6000 or r4000 it is
4394 assembled into a single instruction which
4395 ignores the register. Thus the insn version
4396 is MIPS_ISA2 and uses 'x', and the macro
4397 version is MIPS_ISA1 and uses 't'. */
4400 /* This case is for the div instruction, which
4401 acts differently if the destination argument
4402 is $0. This only matches $0, and is checked
4403 outside the switch. */
4414 ip
->insn_opcode
|= lastregno
<< 21;
4417 ip
->insn_opcode
|= lastregno
<< 16;
4422 case 'D': /* floating point destination register */
4423 case 'S': /* floating point source register */
4424 case 'T': /* floating point target register */
4428 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4438 while (isdigit (*s
));
4441 as_bad ("Invalid float register number (%d)", regno
);
4443 if ((regno
& 1) != 0
4445 && ! (strcmp (str
, "mtc1") == 0 ||
4446 strcmp (str
, "mfc1") == 0 ||
4447 strcmp (str
, "lwc1") == 0 ||
4448 strcmp (str
, "swc1") == 0))
4449 as_warn ("Float register should be even, was %d",
4457 if (c
== 'V' || c
== 'W')
4467 ip
->insn_opcode
|= regno
<< 6;
4471 ip
->insn_opcode
|= regno
<< 11;
4475 ip
->insn_opcode
|= regno
<< 16;
4483 ip
->insn_opcode
|= lastregno
<< 11;
4486 ip
->insn_opcode
|= lastregno
<< 16;
4492 my_getExpression (&imm_expr
, s
);
4493 check_absolute_expr (ip
, &imm_expr
);
4498 my_getExpression (&offset_expr
, s
);
4499 imm_reloc
= BFD_RELOC_32
;
4511 unsigned char temp
[8];
4513 unsigned int length
;
4518 /* These only appear as the last operand in an
4519 instruction, and every instruction that accepts
4520 them in any variant accepts them in all variants.
4521 This means we don't have to worry about backing out
4522 any changes if the instruction does not match.
4524 The difference between them is the size of the
4525 floating point constant and where it goes. For 'F'
4526 and 'L' the constant is 64 bits; for 'f' and 'l' it
4527 is 32 bits. Where the constant is placed is based
4528 on how the MIPS assembler does things:
4531 f -- immediate value
4534 The .lit4 and .lit8 sections are only used if
4535 permitted by the -G argument.
4537 When generating embedded PIC code, we use the
4538 .lit8 section but not the .lit4 section (we can do
4539 .lit4 inline easily; we need to put .lit8
4540 somewhere in the data segment, and using .lit8
4541 permits the linker to eventually combine identical
4544 f64
= *args
== 'F' || *args
== 'L';
4546 save_in
= input_line_pointer
;
4547 input_line_pointer
= s
;
4548 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4550 s
= input_line_pointer
;
4551 input_line_pointer
= save_in
;
4552 if (err
!= NULL
&& *err
!= '\0')
4554 as_bad ("Bad floating point constant: %s", err
);
4555 memset (temp
, '\0', sizeof temp
);
4556 length
= f64
? 8 : 4;
4559 assert (length
== (f64
? 8 : 4));
4563 && (mips_pic
== EMBEDDED_PIC
4565 || g_switch_value
< 4
4569 imm_expr
.X_op
= O_constant
;
4570 if (byte_order
== LITTLE_ENDIAN
)
4571 imm_expr
.X_add_number
=
4572 (((((((int) temp
[3] << 8)
4577 imm_expr
.X_add_number
=
4578 (((((((int) temp
[0] << 8)
4585 const char *newname
;
4588 /* Switch to the right section. */
4590 subseg
= now_subseg
;
4593 default: /* unused default case avoids warnings. */
4597 if (g_switch_value
< 8)
4598 newname
= RDATA_SECTION_NAME
;
4602 newname
= RDATA_SECTION_NAME
;
4606 assert (g_switch_value
>= 4);
4611 new_seg
= subseg_new (newname
, (subsegT
) 0);
4612 frag_align (*args
== 'l' ? 2 : 3, 0);
4614 record_alignment (new_seg
, 4);
4616 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4619 as_bad ("Can't use floating point insn in this section");
4621 /* Set the argument to the current address in the
4623 offset_expr
.X_op
= O_symbol
;
4624 offset_expr
.X_add_symbol
=
4625 symbol_new ("L0\001", now_seg
,
4626 (valueT
) frag_now_fix (), frag_now
);
4627 offset_expr
.X_add_number
= 0;
4629 /* Put the floating point number into the section. */
4630 p
= frag_more ((int) length
);
4631 memcpy (p
, temp
, length
);
4633 /* Switch back to the original section. */
4634 subseg_set (seg
, subseg
);
4639 case 'i': /* 16 bit unsigned immediate */
4640 case 'j': /* 16 bit signed immediate */
4641 imm_reloc
= BFD_RELOC_LO16
;
4642 c
= my_getSmallExpression (&imm_expr
, s
);
4647 if (imm_expr
.X_op
== O_constant
)
4648 imm_expr
.X_add_number
=
4649 (imm_expr
.X_add_number
>> 16) & 0xffff;
4651 imm_reloc
= BFD_RELOC_HI16_S
;
4653 imm_reloc
= BFD_RELOC_HI16
;
4657 check_absolute_expr (ip
, &imm_expr
);
4660 if (imm_expr
.X_add_number
< 0
4661 || imm_expr
.X_add_number
>= 0x10000)
4663 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4664 !strcmp (insn
->name
, insn
[1].name
))
4666 as_bad ("16 bit expression not in range 0..65535");
4674 /* The upper bound should be 0x8000, but
4675 unfortunately the MIPS assembler accepts numbers
4676 from 0x8000 to 0xffff and sign extends them, and
4677 we want to be compatible. We only permit this
4678 extended range for an instruction which does not
4679 provide any further alternates, since those
4680 alternates may handle other cases. People should
4681 use the numbers they mean, rather than relying on
4682 a mysterious sign extension. */
4683 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4684 strcmp (insn
->name
, insn
[1].name
) == 0);
4689 if (imm_expr
.X_add_number
< -0x8000 ||
4690 imm_expr
.X_add_number
>= max
)
4694 as_bad ("16 bit expression not in range -32768..32767");
4700 case 'o': /* 16 bit offset */
4701 c
= my_getSmallExpression (&offset_expr
, s
);
4703 /* If this value won't fit into a 16 bit offset, then go
4704 find a macro that will generate the 32 bit offset
4705 code pattern. As a special hack, we accept the
4706 difference of two local symbols as a constant. This
4707 is required to suppose embedded PIC switches, which
4708 use an instruction which looks like
4709 lw $4,$L12-$LS12($4)
4710 The problem with handling this in a more general
4711 fashion is that the macro function doesn't expect to
4712 see anything which can be handled in a single
4713 constant instruction. */
4715 && (offset_expr
.X_op
!= O_constant
4716 || offset_expr
.X_add_number
>= 0x8000
4717 || offset_expr
.X_add_number
< -0x8000)
4718 && (mips_pic
!= EMBEDDED_PIC
4719 || offset_expr
.X_op
!= O_subtract
4720 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4721 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4724 offset_reloc
= BFD_RELOC_LO16
;
4725 if (c
== 'h' || c
== 'H')
4727 assert (offset_expr
.X_op
== O_constant
);
4728 offset_expr
.X_add_number
=
4729 (offset_expr
.X_add_number
>> 16) & 0xffff;
4734 case 'p': /* pc relative offset */
4735 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4736 my_getExpression (&offset_expr
, s
);
4740 case 'u': /* upper 16 bits */
4741 c
= my_getSmallExpression (&imm_expr
, s
);
4742 if (imm_expr
.X_op
== O_constant
4743 && (imm_expr
.X_add_number
< 0
4744 || imm_expr
.X_add_number
>= 0x10000))
4745 as_bad ("lui expression not in range 0..65535");
4746 imm_reloc
= BFD_RELOC_LO16
;
4751 if (imm_expr
.X_op
== O_constant
)
4752 imm_expr
.X_add_number
=
4753 (imm_expr
.X_add_number
>> 16) & 0xffff;
4755 imm_reloc
= BFD_RELOC_HI16_S
;
4757 imm_reloc
= BFD_RELOC_HI16
;
4763 case 'a': /* 26 bit address */
4764 my_getExpression (&offset_expr
, s
);
4766 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4770 fprintf (stderr
, "bad char = '%c'\n", *args
);
4775 /* Args don't match. */
4776 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4777 !strcmp (insn
->name
, insn
[1].name
))
4783 insn_error
= "ERROR: Illegal operands";
4792 my_getSmallExpression (ep
, str
)
4803 ((str
[1] == 'h' && str
[2] == 'i')
4804 || (str
[1] == 'H' && str
[2] == 'I')
4805 || (str
[1] == 'l' && str
[2] == 'o'))
4817 * A small expression may be followed by a base register.
4818 * Scan to the end of this operand, and then back over a possible
4819 * base register. Then scan the small expression up to that
4820 * point. (Based on code in sparc.c...)
4822 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4824 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4826 if (isdigit (sp
[-2]))
4828 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4830 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4836 else if (sp
- 5 >= str
4839 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4840 || (sp
[-3] == 's' && sp
[-2] == 'p')
4841 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4842 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4848 /* no expression means zero offset */
4851 /* %xx(reg) is an error */
4852 ep
->X_op
= O_absent
;
4857 ep
->X_op
= O_constant
;
4860 ep
->X_add_symbol
= NULL
;
4861 ep
->X_op_symbol
= NULL
;
4862 ep
->X_add_number
= 0;
4867 my_getExpression (ep
, str
);
4874 my_getExpression (ep
, str
);
4875 return c
; /* => %hi or %lo encountered */
4879 my_getExpression (ep
, str
)
4885 save_in
= input_line_pointer
;
4886 input_line_pointer
= str
;
4888 expr_end
= input_line_pointer
;
4889 input_line_pointer
= save_in
;
4892 /* Turn a string in input_line_pointer into a floating point constant
4893 of type type, and store the appropriate bytes in *litP. The number
4894 of LITTLENUMS emitted is stored in *sizeP . An error message is
4895 returned, or NULL on OK. */
4898 md_atof (type
, litP
, sizeP
)
4904 LITTLENUM_TYPE words
[4];
4920 return "bad call to md_atof";
4923 t
= atof_ieee (input_line_pointer
, type
, words
);
4925 input_line_pointer
= t
;
4929 if (byte_order
== LITTLE_ENDIAN
)
4931 for (i
= prec
- 1; i
>= 0; i
--)
4933 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4939 for (i
= 0; i
< prec
; i
++)
4941 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4950 md_number_to_chars (buf
, val
, n
)
4958 number_to_chars_littleendian (buf
, val
, n
);
4962 number_to_chars_bigendian (buf
, val
, n
);
4971 CONST
char *md_shortopts
= "E:O::g::G:";
4973 CONST
char *md_shortopts
= "E:O::g::";
4975 struct option md_longopts
[] = {
4976 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4977 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4978 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4979 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4980 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4981 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4982 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4983 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4984 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4985 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4986 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4987 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4988 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4989 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4990 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4991 {"break", no_argument
, NULL
, OPTION_BREAK
},
4992 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4995 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
4996 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
4997 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
4998 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
4999 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5002 {NULL
, no_argument
, NULL
, 0}
5004 size_t md_longopts_size
= sizeof(md_longopts
);
5007 md_parse_option (c
, arg
)
5023 byte_order
= BIG_ENDIAN
;
5024 else if (arg
[1] == 'L')
5025 byte_order
= LITTLE_ENDIAN
;
5028 as_bad("invalid endianness -E%c", arg
[1]);
5034 mips_target_format
= "a.out-mips-big";
5036 mips_target_format
= "a.out-mips-little";
5040 mips_target_format
= "ecoff-bigmips";
5042 mips_target_format
= "ecoff-littlemips";
5046 mips_target_format
= "elf32-bigmips";
5048 mips_target_format
= "elf32-littlemips";
5051 /* FIXME: This breaks -L -EL. */
5052 flag_keep_locals
= 0;
5056 if (arg
&& arg
[1] == '0')
5063 if (arg
== NULL
|| arg
[1] == '2')
5086 /* Identify the processor type */
5088 if (strcmp (p
, "default") == 0
5089 || strcmp (p
, "DEFAULT") == 0)
5093 if (*p
== 'r' || *p
== 'R')
5100 if (strcmp (p
, "2000") == 0
5101 || strcmp (p
, "2k") == 0
5102 || strcmp (p
, "2K") == 0)
5110 if (strcmp (p
, "3000") == 0
5111 || strcmp (p
, "3k") == 0
5112 || strcmp (p
, "3K") == 0)
5120 if (strcmp (p
, "4000") == 0
5121 || strcmp (p
, "4k") == 0
5122 || strcmp (p
, "4K") == 0)
5127 else if (strcmp (p
, "4400") == 0)
5132 else if (strcmp (p
, "4600") == 0)
5140 if (strcmp (p
, "6000") == 0
5141 || strcmp (p
, "6k") == 0
5142 || strcmp (p
, "6K") == 0)
5150 if (strcmp (p
, "orion") == 0)
5160 as_bad ("invalid architecture -mcpu=%s", arg
);
5167 case OPTION_MEMBEDDED_PIC
:
5168 mips_pic
= EMBEDDED_PIC
;
5172 as_bad ("-G may not be used with embedded PIC code");
5175 g_switch_value
= 0x7fffffff;
5180 /* When generating ELF code, we permit -KPIC and -call_shared to
5181 select SVR4_PIC, and -non_shared to select no PIC. This is
5182 intended to be compatible with Irix 5. */
5183 case OPTION_CALL_SHARED
:
5184 mips_pic
= SVR4_PIC
;
5185 if (g_switch_seen
&& g_switch_value
!= 0)
5187 as_bad ("-G may not be used with SVR4 PIC code");
5193 case OPTION_NON_SHARED
:
5196 #endif /* OBJ_ELF */
5200 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5202 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5206 g_switch_value
= atoi (arg
);
5219 md_show_usage (stream
)
5224 -membedded-pic generate embedded position independent code\n\
5225 -EB generate big endian output\n\
5226 -EL generate little endian output\n\
5227 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5228 -G NUM allow referencing objects up to NUM bytes\n\
5229 implicitly with the gp register [default 8]\n");
5231 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5232 -mips2, -mcpu=r6000 generate code for r6000\n\
5233 -mips3, -mcpu=r4000 generate code for r4000\n\
5234 -O0 remove unneeded NOPs, do not swap branches\n\
5235 -O remove unneeded NOPs and swap branches\n\
5236 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5237 --break, --no-trap break exception on div by 0 and mult overflow\n");
5240 -KPIC, -call_shared generate SVR4 position independent code\n\
5241 -non_shared do not generate position independent code\n");
5246 md_pcrel_from (fixP
)
5250 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5251 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5253 /* This makes a branch to an undefined symbol be a branch to the
5254 current location. */
5259 /* return the address of the delay slot */
5260 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5263 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5264 reloc for a cons. We could use the definition there, except that
5265 we want to handle 64 bit relocs specially. */
5268 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5271 unsigned int nbytes
;
5274 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5276 FIXME: There is no way to select anything but 32 bit mode right
5280 if (byte_order
== BIG_ENDIAN
)
5285 if (nbytes
!= 2 && nbytes
!= 4)
5286 as_bad ("Unsupported reloc size %d", nbytes
);
5288 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5289 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5292 /* When generating embedded PIC code we need to use a special
5293 relocation to represent the difference of two symbols in the .text
5294 section (switch tables use a difference of this sort). See
5295 include/coff/mips.h for details. This macro checks whether this
5296 fixup requires the special reloc. */
5297 #define SWITCH_TABLE(fixp) \
5298 ((fixp)->fx_r_type == BFD_RELOC_32 \
5299 && (fixp)->fx_addsy != NULL \
5300 && (fixp)->fx_subsy != NULL \
5301 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5302 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5304 /* When generating embedded PIC code we must keep all PC relative
5305 relocations, in case the linker has to relax a call. We also need
5306 to keep relocations for switch table entries. */
5310 mips_force_relocation (fixp
)
5313 return (mips_pic
== EMBEDDED_PIC
5315 || SWITCH_TABLE (fixp
)
5316 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5317 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5320 /* Apply a fixup to the object file. */
5323 md_apply_fix (fixP
, valueP
)
5330 assert (fixP
->fx_size
== 4);
5333 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5335 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5338 switch (fixP
->fx_r_type
)
5340 case BFD_RELOC_MIPS_JMP
:
5341 case BFD_RELOC_HI16
:
5342 case BFD_RELOC_HI16_S
:
5343 case BFD_RELOC_MIPS_GPREL
:
5344 case BFD_RELOC_MIPS_LITERAL
:
5345 case BFD_RELOC_MIPS_CALL16
:
5346 case BFD_RELOC_MIPS_GOT16
:
5347 case BFD_RELOC_MIPS_GPREL32
:
5349 as_bad ("Invalid PC relative reloc");
5350 /* Nothing needed to do. The value comes from the reloc entry */
5353 case BFD_RELOC_PCREL_HI16_S
:
5354 /* The addend for this is tricky if it is internal, so we just
5355 do everything here rather than in bfd_perform_relocation. */
5356 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5358 /* For an external symbol adjust by the address to make it
5359 pcrel_offset. We use the address of the RELLO reloc
5360 which follows this one. */
5361 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5362 + fixP
->fx_next
->fx_where
);
5367 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5368 if (byte_order
== BIG_ENDIAN
)
5370 md_number_to_chars (buf
, value
, 2);
5373 case BFD_RELOC_PCREL_LO16
:
5374 /* The addend for this is tricky if it is internal, so we just
5375 do everything here rather than in bfd_perform_relocation. */
5376 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5377 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5378 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5379 if (byte_order
== BIG_ENDIAN
)
5381 md_number_to_chars (buf
, value
, 2);
5385 /* If we are deleting this reloc entry, we must fill in the
5386 value now. This can happen if we have a .word which is not
5387 resolved when it appears but is later defined. We also need
5388 to fill in the value if this is an embedded PIC switch table
5391 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5392 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5396 case BFD_RELOC_LO16
:
5397 /* When handling an embedded PIC switch statement, we can wind
5398 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5401 if (value
< -0x8000 || value
> 0x7fff)
5402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5403 "relocation overflow");
5404 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5405 if (byte_order
== BIG_ENDIAN
)
5407 md_number_to_chars (buf
, value
, 2);
5411 case BFD_RELOC_16_PCREL_S2
:
5413 * We need to save the bits in the instruction since fixup_segment()
5414 * might be deleting the relocation entry (i.e., a branch within
5415 * the current segment).
5418 as_warn ("Branch to odd address (%lx)", value
);
5420 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5421 as_bad ("Relocation overflow");
5423 /* update old instruction data */
5424 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5428 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5432 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5439 insn
|= value
& 0xFFFF;
5440 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5455 const struct mips_opcode
*p
;
5456 int treg
, sreg
, dreg
, shamt
;
5461 for (i
= 0; i
< NUMOPCODES
; ++i
)
5463 p
= &mips_opcodes
[i
];
5464 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5466 printf ("%08lx %s\t", oc
, p
->name
);
5467 treg
= (oc
>> 16) & 0x1f;
5468 sreg
= (oc
>> 21) & 0x1f;
5469 dreg
= (oc
>> 11) & 0x1f;
5470 shamt
= (oc
>> 6) & 0x1f;
5472 for (args
= p
->args
;; ++args
)
5483 printf ("%c", *args
);
5487 assert (treg
== sreg
);
5488 printf ("$%d,$%d", treg
, sreg
);
5493 printf ("$%d", dreg
);
5498 printf ("$%d", treg
);
5502 printf ("0x%x", treg
);
5507 printf ("$%d", sreg
);
5511 printf ("0x%08lx", oc
& 0x1ffffff);
5523 printf ("$%d", shamt
);
5534 printf ("%08lx UNDEFINED\n", oc
);
5545 name
= input_line_pointer
;
5546 c
= get_symbol_end ();
5547 p
= (symbolS
*) symbol_find_or_make (name
);
5548 *input_line_pointer
= c
;
5552 /* Align the current frag to a given power of two. The MIPS assembler
5553 also automatically adjusts any preceding label. */
5556 mips_align (to
, fill
, label
)
5561 mips_emit_delays ();
5562 frag_align (to
, fill
);
5563 record_alignment (now_seg
, to
);
5566 assert (S_GET_SEGMENT (label
) == now_seg
);
5567 label
->sy_frag
= frag_now
;
5568 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5572 /* Align to a given power of two. .align 0 turns off the automatic
5573 alignment used by the data creating pseudo-ops. */
5580 register long temp_fill
;
5581 long max_alignment
= 15;
5585 o Note that the assembler pulls down any immediately preceeding label
5586 to the aligned address.
5587 o It's not documented but auto alignment is reinstated by
5588 a .align pseudo instruction.
5589 o Note also that after auto alignment is turned off the mips assembler
5590 issues an error on attempt to assemble an improperly aligned data item.
5595 temp
= get_absolute_expression ();
5596 if (temp
> max_alignment
)
5597 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5600 as_warn ("Alignment negative: 0 assumed.");
5603 if (*input_line_pointer
== ',')
5605 input_line_pointer
++;
5606 temp_fill
= get_absolute_expression ();
5613 mips_align (temp
, (int) temp_fill
, insn_label
);
5620 demand_empty_rest_of_line ();
5623 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5624 that there was a previous instruction. */
5627 s_stringer (append_zero
)
5630 mips_emit_delays ();
5632 stringer (append_zero
);
5643 /* When generating embedded PIC code, we only use the .text, .lit8,
5644 .sdata and .sbss sections. We change the .data and .rdata
5645 pseudo-ops to use .sdata. */
5646 if (mips_pic
== EMBEDDED_PIC
5647 && (sec
== 'd' || sec
== 'r'))
5650 mips_emit_delays ();
5660 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5661 demand_empty_rest_of_line ();
5665 seg
= subseg_new (RDATA_SECTION_NAME
,
5666 (subsegT
) get_absolute_expression ());
5668 bfd_set_section_flags (stdoutput
, seg
,
5674 bfd_set_section_alignment (stdoutput
, seg
, 4);
5676 demand_empty_rest_of_line ();
5681 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5683 bfd_set_section_flags (stdoutput
, seg
,
5684 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5685 bfd_set_section_alignment (stdoutput
, seg
, 4);
5687 demand_empty_rest_of_line ();
5689 #else /* ! defined (GPOPT) */
5690 as_bad ("Global pointers not supported; recompile -G 0");
5691 demand_empty_rest_of_line ();
5693 #endif /* ! defined (GPOPT) */
5706 mips_emit_delays ();
5707 if (log_size
> 0 && auto_align
)
5708 mips_align (log_size
, 0, label
);
5710 cons (1 << log_size
);
5717 as_fatal ("Encountered `.err', aborting assembly");
5727 symbolP
= get_symbol ();
5728 if (*input_line_pointer
== ',')
5729 input_line_pointer
++;
5730 size
= get_absolute_expression ();
5731 S_SET_EXTERNAL (symbolP
);
5733 #ifdef ECOFF_DEBUGGING
5734 symbolP
->ecoff_extern_size
= size
;
5746 mips_emit_delays ();
5750 mips_align (3, 0, label
);
5752 mips_align (2, 0, label
);
5759 /* Handle .globl. We need to override it because on Irix 5 you are
5762 where foo is an undefined symbol, to mean that foo should be
5763 considered to be the address of a function. */
5773 name
= input_line_pointer
;
5774 c
= get_symbol_end ();
5775 symbolP
= symbol_find_or_make (name
);
5776 *input_line_pointer
= c
;
5778 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5783 secname
= input_line_pointer
;
5784 c
= get_symbol_end ();
5785 sec
= bfd_get_section_by_name (stdoutput
, secname
);
5787 as_bad ("%s: no such section", secname
);
5788 *input_line_pointer
= c
;
5790 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
5791 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
5794 S_SET_EXTERNAL (symbolP
);
5795 demand_empty_rest_of_line ();
5805 opt
= input_line_pointer
;
5806 c
= get_symbol_end ();
5810 /* FIXME: What does this mean? */
5812 else if (strncmp (opt
, "pic", 3) == 0)
5820 mips_pic
= SVR4_PIC
;
5822 as_bad (".option pic%d not supported", i
);
5825 if (mips_pic
== SVR4_PIC
)
5827 if (g_switch_seen
&& g_switch_value
!= 0)
5828 as_warn ("-G may not be used with SVR4 PIC code");
5830 bfd_set_gp_size (stdoutput
, 0);
5835 as_warn ("Unrecognized option \"%s\"", opt
);
5837 *input_line_pointer
= c
;
5838 demand_empty_rest_of_line ();
5845 char *name
= input_line_pointer
, ch
;
5847 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5848 input_line_pointer
++;
5849 ch
= *input_line_pointer
;
5850 *input_line_pointer
= '\0';
5852 if (strcmp (name
, "reorder") == 0)
5856 prev_insn_unreordered
= 1;
5857 prev_prev_insn_unreordered
= 1;
5861 else if (strcmp (name
, "noreorder") == 0)
5863 mips_emit_delays ();
5865 mips_any_noreorder
= 1;
5867 else if (strcmp (name
, "at") == 0)
5871 else if (strcmp (name
, "noat") == 0)
5875 else if (strcmp (name
, "macro") == 0)
5877 mips_warn_about_macros
= 0;
5879 else if (strcmp (name
, "nomacro") == 0)
5881 if (mips_noreorder
== 0)
5882 as_bad ("`noreorder' must be set before `nomacro'");
5883 mips_warn_about_macros
= 1;
5885 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5889 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5893 else if (strcmp (name
, "bopt") == 0)
5897 else if (strcmp (name
, "nobopt") == 0)
5901 else if (strncmp (name
, "mips", 4) == 0)
5905 /* Permit the user to change the ISA on the fly. Needless to
5906 say, misuse can cause serious problems. */
5907 isa
= atoi (name
+ 4);
5909 mips_isa
= file_mips_isa
;
5910 else if (isa
< 1 || isa
> 3)
5911 as_bad ("unknown ISA level");
5917 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5919 *input_line_pointer
= ch
;
5920 demand_empty_rest_of_line ();
5923 /* The same as the usual .space directive, except that we have to
5924 forget about any previous instruction. */
5927 s_mips_space (param
)
5930 mips_emit_delays ();
5935 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5936 .option pic2. It means to generate SVR4 PIC calls. */
5942 mips_pic
= SVR4_PIC
;
5944 if (g_switch_seen
&& g_switch_value
!= 0)
5945 as_warn ("-G may not be used with SVR4 PIC code");
5948 bfd_set_gp_size (stdoutput
, 0);
5949 demand_empty_rest_of_line ();
5952 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5953 PIC code. It sets the $gp register for the function based on the
5954 function address, which is in the register named in the argument.
5955 This uses a relocation against _gp_disp, which is handled specially
5956 by the linker. The result is:
5957 lui $gp,%hi(_gp_disp)
5958 addiu $gp,$gp,%lo(_gp_disp)
5959 addu $gp,$gp,.cpload argument
5960 The .cpload argument is normally $25 == $t9. */
5969 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5970 if (mips_pic
!= SVR4_PIC
)
5976 /* .cpload should be a in .set noreorder section. */
5977 if (mips_noreorder
== 0)
5978 as_warn (".cpload not in noreorder section");
5981 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5982 ex
.X_op_symbol
= NULL
;
5983 ex
.X_add_number
= 0;
5985 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5986 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5987 (int) BFD_RELOC_LO16
);
5989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5990 GP
, GP
, tc_get_register (0));
5992 demand_empty_rest_of_line ();
5995 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5996 offset from $sp. The offset is remembered, and after making a PIC
5997 call $gp is restored from that location. */
6000 s_cprestore (ignore
)
6006 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6007 if (mips_pic
!= SVR4_PIC
)
6013 mips_cprestore_offset
= get_absolute_expression ();
6015 ex
.X_op
= O_constant
;
6016 ex
.X_add_symbol
= NULL
;
6017 ex
.X_op_symbol
= NULL
;
6018 ex
.X_add_number
= mips_cprestore_offset
;
6020 macro_build ((char *) NULL
, &icnt
, &ex
,
6021 mips_isa
< 3 ? "sw" : "sd",
6022 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
6024 demand_empty_rest_of_line ();
6027 /* Handle the .gpword pseudo-op. This is used when generating PIC
6028 code. It generates a 32 bit GP relative reloc. */
6038 /* When not generating PIC code, this is treated as .word. */
6039 if (mips_pic
!= SVR4_PIC
)
6046 mips_emit_delays ();
6048 mips_align (2, 0, label
);
6053 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6055 as_bad ("Unsupported use of .gpword");
6056 ignore_rest_of_line ();
6060 md_number_to_chars (p
, (valueT
) 0, 4);
6061 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6062 BFD_RELOC_MIPS_GPREL32
);
6064 demand_empty_rest_of_line ();
6067 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6068 tables in SVR4 PIC code. */
6077 /* This is ignored when not generating SVR4 PIC code. */
6078 if (mips_pic
!= SVR4_PIC
)
6084 /* Add $gp to the register named as an argument. */
6085 reg
= tc_get_register (0);
6086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6087 mips_isa
< 3 ? "addu" : "daddu",
6088 "d,v,t", reg
, reg
, GP
);
6090 demand_empty_rest_of_line ();
6093 /* Parse a register string into a number. Called from the ECOFF code
6094 to parse .frame. The argument is non-zero if this is the frame
6095 register, so that we can record it in mips_frame_reg. */
6098 tc_get_register (frame
)
6104 if (*input_line_pointer
++ != '$')
6106 as_warn ("expected `$'");
6109 else if (isdigit ((unsigned char) *input_line_pointer
))
6111 reg
= get_absolute_expression ();
6112 if (reg
< 0 || reg
>= 32)
6114 as_warn ("Bad register number");
6120 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6122 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6124 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6126 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6130 as_warn ("Unrecognized register name");
6133 input_line_pointer
+= 2;
6136 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6141 md_section_align (seg
, addr
)
6145 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6147 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6150 /* Estimate the size of a frag before relaxing. We are not really
6151 relaxing here, and the final size is encoded in the subtype
6156 md_estimate_size_before_relax (fragp
, segtype
)
6162 if (mips_pic
== NO_PIC
)
6165 const char *symname
;
6167 /* Find out whether this symbol can be referenced off the GP
6168 register. It can be if it is smaller than the -G size or if
6169 it is in the .sdata or .sbss section. Certain symbols can
6170 not be referenced off the GP, although it appears as though
6172 symname
= S_GET_NAME (fragp
->fr_symbol
);
6173 if (symname
!= (const char *) NULL
6174 && (strcmp (symname
, "eprol") == 0
6175 || strcmp (symname
, "etext") == 0
6176 || strcmp (symname
, "_gp") == 0
6177 || strcmp (symname
, "edata") == 0
6178 || strcmp (symname
, "_fbss") == 0
6179 || strcmp (symname
, "_fdata") == 0
6180 || strcmp (symname
, "_ftext") == 0
6181 || strcmp (symname
, "end") == 0
6182 || strcmp (symname
, "_gp_disp") == 0))
6184 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6185 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6186 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6187 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6188 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6192 const char *segname
;
6194 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6195 assert (strcmp (segname
, ".lit8") != 0
6196 && strcmp (segname
, ".lit4") != 0);
6197 change
= (strcmp (segname
, ".sdata") != 0
6198 && strcmp (segname
, ".sbss") != 0);
6200 #else /* ! defined (GPOPT) */
6201 /* We are not optimizing for the GP register. */
6203 #endif /* ! defined (GPOPT) */
6205 else if (mips_pic
== SVR4_PIC
)
6207 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6209 /* This must duplicate the test in adjust_reloc_syms. */
6210 change
= (symsec
!= &bfd_und_section
6211 && symsec
!= &bfd_abs_section
6212 && ! bfd_is_com_section (symsec
));
6219 /* Record the offset to the first reloc in the fr_opcode field.
6220 This lets md_convert_frag and tc_gen_reloc know that the code
6221 must be expanded. */
6222 fragp
->fr_opcode
= (fragp
->fr_literal
6224 - RELAX_OLD (fragp
->fr_subtype
)
6225 + RELAX_RELOC1 (fragp
->fr_subtype
));
6226 /* FIXME: This really needs as_warn_where. */
6227 if (RELAX_WARN (fragp
->fr_subtype
))
6228 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6234 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6237 /* Translate internal representation of relocation info to BFD target
6241 tc_gen_reloc (section
, fixp
)
6245 static arelent
*retval
[4];
6248 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6251 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6252 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6254 if (mips_pic
== EMBEDDED_PIC
6255 && SWITCH_TABLE (fixp
))
6257 /* For a switch table entry we use a special reloc. The addend
6258 is actually the difference between the reloc address and the
6260 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6262 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6264 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6266 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6268 /* We use a special addend for an internal RELLO reloc. */
6269 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6270 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6272 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6274 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6276 assert (fixp
->fx_next
!= NULL
6277 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6278 /* We use a special addend for an internal RELHI reloc. The
6279 reloc is relative to the RELLO; adjust the addend
6281 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6282 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6283 + fixp
->fx_next
->fx_where
6284 - S_GET_VALUE (fixp
->fx_subsy
));
6286 reloc
->addend
= (fixp
->fx_addnumber
6287 + fixp
->fx_next
->fx_frag
->fr_address
6288 + fixp
->fx_next
->fx_where
);
6290 else if (fixp
->fx_pcrel
== 0)
6291 reloc
->addend
= fixp
->fx_addnumber
;
6295 /* A gruesome hack which is a result of the gruesome gas reloc
6297 reloc
->addend
= reloc
->address
;
6299 reloc
->addend
= -reloc
->address
;
6303 /* If this is a variant frag, we may need to adjust the existing
6304 reloc and generate a new one. */
6305 if (fixp
->fx_frag
->fr_opcode
!= NULL
6306 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6307 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6308 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6312 /* If this is not the last reloc in this frag, then we have two
6313 GPREL relocs, both of which are being replaced. Let the
6314 second one handle all of them. */
6315 if (fixp
->fx_next
!= NULL
6316 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6318 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6319 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6324 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6325 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6326 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6328 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6329 reloc2
->address
= (reloc
->address
6330 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6331 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6332 reloc2
->addend
= fixp
->fx_addnumber
;
6333 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6334 assert (reloc2
->howto
!= NULL
);
6336 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6340 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6343 reloc3
->address
+= 4;
6346 if (mips_pic
== NO_PIC
)
6348 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6349 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6351 else if (mips_pic
== SVR4_PIC
)
6353 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6355 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6356 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6363 /* To support a PC relative reloc when generating embedded PIC code
6364 for ECOFF, we use a Cygnus extension. We check for that here to
6365 make sure that we don't let such a reloc escape normally. */
6367 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6368 && mips_pic
!= EMBEDDED_PIC
)
6369 reloc
->howto
= NULL
;
6372 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6374 if (reloc
->howto
== NULL
)
6376 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6377 "Can not represent relocation in this object file format");
6384 /* Convert a machine dependent frag. */
6387 md_convert_frag (abfd
, asec
, fragp
)
6395 if (fragp
->fr_opcode
== NULL
)
6398 old
= RELAX_OLD (fragp
->fr_subtype
);
6399 new = RELAX_NEW (fragp
->fr_subtype
);
6400 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6403 memcpy (fixptr
- old
, fixptr
, new);
6405 fragp
->fr_fix
+= new - old
;
6408 /* This function is called whenever a label is defined. It is used
6409 when handling branch delays; if a branch has a label, we assume we
6413 mips_define_label (sym
)
6421 /* Some special processing for a MIPS ELF file. */
6424 mips_elf_final_processing ()
6428 /* Write out the .reginfo section. */
6429 s
.ri_gprmask
= mips_gprmask
;
6430 s
.ri_cprmask
[0] = mips_cprmask
[0];
6431 s
.ri_cprmask
[1] = mips_cprmask
[1];
6432 s
.ri_cprmask
[2] = mips_cprmask
[2];
6433 s
.ri_cprmask
[3] = mips_cprmask
[3];
6434 /* The gp_value field is set by the MIPS ELF backend. */
6436 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6437 ((Elf32_External_RegInfo
*)
6438 mips_regmask_frag
));
6440 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6441 sort of BFD interface for this. */
6442 if (mips_any_noreorder
)
6443 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6444 if (mips_pic
!= NO_PIC
)
6445 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6448 #endif /* OBJ_ELF */
6450 #ifndef ECOFF_DEBUGGING
6452 /* These functions should really be defined by the object file format,
6453 since they are related to debugging information. However, this
6454 code has to work for the a.out format, which does not define them,
6455 so we provide simple versions here. These don't actually generate
6456 any debugging information, but they do simple checking and someday
6457 somebody may make them useful. */
6461 struct loc
*loc_next
;
6462 unsigned long loc_fileno
;
6463 unsigned long loc_lineno
;
6464 unsigned long loc_offset
;
6465 unsigned short loc_delta
;
6466 unsigned short loc_count
;
6475 struct proc
*proc_next
;
6476 struct symbol
*proc_isym
;
6477 struct symbol
*proc_end
;
6478 unsigned long proc_reg_mask
;
6479 unsigned long proc_reg_offset
;
6480 unsigned long proc_fpreg_mask
;
6481 unsigned long proc_fpreg_offset
;
6482 unsigned long proc_frameoffset
;
6483 unsigned long proc_framereg
;
6484 unsigned long proc_pcreg
;
6486 struct file
*proc_file
;
6493 struct file
*file_next
;
6494 unsigned long file_fileno
;
6495 struct symbol
*file_symbol
;
6496 struct symbol
*file_end
;
6497 struct proc
*file_proc
;
6502 static struct obstack proc_frags
;
6503 static procS
*proc_lastP
;
6504 static procS
*proc_rootP
;
6505 static int numprocs
;
6510 obstack_begin (&proc_frags
, 0x2000);
6516 /* check for premature end, nesting errors, etc */
6517 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6518 as_warn ("missing `.end' at end of assembly");
6521 extern char hex_value
[];
6529 if (*input_line_pointer
== '-')
6531 ++input_line_pointer
;
6534 if (!isdigit (*input_line_pointer
))
6535 as_bad ("Expected simple number.");
6536 if (input_line_pointer
[0] == '0')
6538 if (input_line_pointer
[1] == 'x')
6540 input_line_pointer
+= 2;
6541 while (isxdigit (*input_line_pointer
))
6544 val
|= hex_value
[(int) *input_line_pointer
++];
6546 return negative
? -val
: val
;
6550 ++input_line_pointer
;
6551 while (isdigit (*input_line_pointer
))
6554 val
|= *input_line_pointer
++ - '0';
6556 return negative
? -val
: val
;
6559 if (!isdigit (*input_line_pointer
))
6561 printf (" *input_line_pointer == '%c' 0x%02x\n",
6562 *input_line_pointer
, *input_line_pointer
);
6563 as_warn ("Invalid number");
6566 while (isdigit (*input_line_pointer
))
6569 val
+= *input_line_pointer
++ - '0';
6571 return negative
? -val
: val
;
6574 /* The .file directive; just like the usual .file directive, but there
6575 is an initial number which is the ECOFF file index. */
6583 line
= get_number ();
6588 /* The .end directive. */
6596 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6599 demand_empty_rest_of_line ();
6603 if (now_seg
!= text_section
)
6604 as_warn (".end not in text section");
6607 as_warn (".end and no .ent seen yet.");
6613 assert (S_GET_NAME (p
));
6614 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6615 as_warn (".end symbol does not match .ent symbol.");
6618 proc_lastP
->proc_end
= (symbolS
*) 1;
6621 /* The .aent and .ent directives. */
6631 symbolP
= get_symbol ();
6632 if (*input_line_pointer
== ',')
6633 input_line_pointer
++;
6635 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6636 number
= get_number ();
6637 if (now_seg
!= text_section
)
6638 as_warn (".ent or .aent not in text section.");
6640 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6641 as_warn ("missing `.end'");
6645 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6646 procP
->proc_isym
= symbolP
;
6647 procP
->proc_reg_mask
= 0;
6648 procP
->proc_reg_offset
= 0;
6649 procP
->proc_fpreg_mask
= 0;
6650 procP
->proc_fpreg_offset
= 0;
6651 procP
->proc_frameoffset
= 0;
6652 procP
->proc_framereg
= 0;
6653 procP
->proc_pcreg
= 0;
6654 procP
->proc_end
= NULL
;
6655 procP
->proc_next
= NULL
;
6657 proc_lastP
->proc_next
= procP
;
6663 demand_empty_rest_of_line ();
6666 /* The .frame directive. */
6679 frame_reg
= tc_get_register (1);
6680 if (*input_line_pointer
== ',')
6681 input_line_pointer
++;
6682 frame_off
= get_absolute_expression ();
6683 if (*input_line_pointer
== ',')
6684 input_line_pointer
++;
6685 pcreg
= tc_get_register (0);
6688 assert (proc_rootP
);
6689 proc_rootP
->proc_framereg
= frame_reg
;
6690 proc_rootP
->proc_frameoffset
= frame_off
;
6691 proc_rootP
->proc_pcreg
= pcreg
;
6692 /* bob macho .frame */
6694 /* We don't have to write out a frame stab for unoptimized code. */
6695 if (!(frame_reg
== FP
&& frame_off
== 0))
6698 as_warn ("No .ent for .frame to use.");
6699 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6700 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6701 S_SET_TYPE (symP
, N_RMASK
);
6702 S_SET_OTHER (symP
, 0);
6703 S_SET_DESC (symP
, 0);
6704 symP
->sy_forward
= proc_lastP
->proc_isym
;
6705 /* bob perhaps I should have used pseudo set */
6707 demand_empty_rest_of_line ();
6711 /* The .fmask and .mask directives. */
6718 char str
[100], *strP
;
6724 mask
= get_number ();
6725 if (*input_line_pointer
== ',')
6726 input_line_pointer
++;
6727 off
= get_absolute_expression ();
6729 /* bob only for coff */
6730 assert (proc_rootP
);
6731 if (reg_type
== 'F')
6733 proc_rootP
->proc_fpreg_mask
= mask
;
6734 proc_rootP
->proc_fpreg_offset
= off
;
6738 proc_rootP
->proc_reg_mask
= mask
;
6739 proc_rootP
->proc_reg_offset
= off
;
6742 /* bob macho .mask + .fmask */
6744 /* We don't have to write out a mask stab if no saved regs. */
6748 as_warn ("No .ent for .mask to use.");
6750 for (i
= 0; i
< 32; i
++)
6754 sprintf (strP
, "%c%d,", reg_type
, i
);
6755 strP
+= strlen (strP
);
6759 sprintf (strP
, ";%d,", off
);
6760 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6761 S_SET_TYPE (symP
, N_RMASK
);
6762 S_SET_OTHER (symP
, 0);
6763 S_SET_DESC (symP
, 0);
6764 symP
->sy_forward
= proc_lastP
->proc_isym
;
6765 /* bob perhaps I should have used pseudo set */
6770 /* The .loc directive. */
6781 assert (now_seg
== text_section
);
6783 lineno
= get_number ();
6784 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6786 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6787 S_SET_TYPE (symbolP
, N_SLINE
);
6788 S_SET_OTHER (symbolP
, 0);
6789 S_SET_DESC (symbolP
, lineno
);
6790 symbolP
->sy_segment
= now_seg
;
6794 #endif /* ! defined (ECOFF_DEBUGGING) */