Remove duplicate definitions of the md_atof() function
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
7 Support.
8
9 This file is part of GAS.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26 #include "as.h"
27 #include "config.h"
28 #include "subsegs.h"
29 #include "safe-ctype.h"
30
31 #include "opcode/mips.h"
32 #include "itbl-ops.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35
36 #ifdef DEBUG
37 #define DBG(x) printf x
38 #else
39 #define DBG(x)
40 #endif
41
42 #ifdef OBJ_MAYBE_ELF
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
46 #undef OBJ_PROCESS_STAB
47 #undef OUTPUT_FLAVOR
48 #undef S_GET_ALIGN
49 #undef S_GET_SIZE
50 #undef S_SET_ALIGN
51 #undef S_SET_SIZE
52 #undef obj_frob_file
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
55 #undef obj_pop_insert
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
58
59 #include "obj-elf.h"
60 /* Fix any of them that we actually care about. */
61 #undef OUTPUT_FLAVOR
62 #define OUTPUT_FLAVOR mips_output_flavor()
63 #endif
64
65 #if defined (OBJ_ELF)
66 #include "elf/mips.h"
67 #endif
68
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
72 #endif
73
74 int mips_flag_mdebug = -1;
75
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
79 #ifdef TE_IRIX
80 int mips_flag_pdr = FALSE;
81 #else
82 int mips_flag_pdr = TRUE;
83 #endif
84
85 #include "ecoff.h"
86
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag;
89 #endif
90
91 #define ZERO 0
92 #define ATREG 1
93 #define TREG 24
94 #define PIC_CALL_REG 25
95 #define KT0 26
96 #define KT1 27
97 #define GP 28
98 #define SP 29
99 #define FP 30
100 #define RA 31
101
102 #define ILLEGAL_REG (32)
103
104 #define AT mips_opts.at
105
106 /* Allow override of standard little-endian ECOFF format. */
107
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
110 #endif
111
112 extern int target_big_endian;
113
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 ? ".rdata" \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 ? ".rdata" \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 ? ".rodata" \
121 : (abort (), ""))
122
123 /* Information about an instruction, including its format, operands
124 and fixups. */
125 struct mips_cl_insn
126 {
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode *insn_mo;
129
130 /* True if this is a mips16 instruction and if we want the extended
131 form of INSN_MO. */
132 bfd_boolean use_extend;
133
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend;
136
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode;
140
141 /* The frag that contains the instruction. */
142 struct frag *frag;
143
144 /* The offset into FRAG of the first instruction byte. */
145 long where;
146
147 /* The relocs associated with the instruction, if any. */
148 fixS *fixp[3];
149
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p : 1;
152
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p : 1;
155
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p : 1;
158 };
159
160 /* The ABI to use. */
161 enum mips_abi_level
162 {
163 NO_ABI = 0,
164 O32_ABI,
165 O64_ABI,
166 N32_ABI,
167 N64_ABI,
168 EABI_ABI
169 };
170
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi = NO_ABI;
173
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls = FALSE;
176
177 /* Whether or not we have code which can be put into a shared
178 library. */
179 static bfd_boolean mips_in_shared = TRUE;
180
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
183 reliable. */
184
185 struct mips_set_options
186 {
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
190 int isa;
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
194 int ase_mips3d;
195 int ase_mdmx;
196 int ase_smartmips;
197 int ase_dsp;
198 int ase_dspr2;
199 int ase_mt;
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
204 int mips16;
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
207 int noreorder;
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
212 unsigned int at;
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
215 `.set macro'. */
216 int warn_about_macros;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
219 int nomove;
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
223 nobopt'. */
224 int nobopt;
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
227 int noautoextend;
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
231 int gp32;
232 int fp32;
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
235 int arch;
236 /* True if ".set sym32" is in effect. */
237 bfd_boolean sym32;
238 };
239
240 /* True if -mgp32 was passed. */
241 static int file_mips_gp32 = -1;
242
243 /* True if -mfp32 was passed. */
244 static int file_mips_fp32 = -1;
245
246 /* This is the struct we use to hold the current set of options. Note
247 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
248 -1 to indicate that they have not been initialized. */
249
250 static struct mips_set_options mips_opts =
251 {
252 ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, ATREG, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
253 };
254
255 /* These variables are filled in with the masks of registers used.
256 The object format code reads them and puts them in the appropriate
257 place. */
258 unsigned long mips_gprmask;
259 unsigned long mips_cprmask[4];
260
261 /* MIPS ISA we are using for this output file. */
262 static int file_mips_isa = ISA_UNKNOWN;
263
264 /* True if -mips16 was passed or implied by arguments passed on the
265 command line (e.g., by -march). */
266 static int file_ase_mips16;
267
268 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
269 || mips_opts.isa == ISA_MIPS32R2 \
270 || mips_opts.isa == ISA_MIPS64 \
271 || mips_opts.isa == ISA_MIPS64R2)
272
273 /* True if -mips3d was passed or implied by arguments passed on the
274 command line (e.g., by -march). */
275 static int file_ase_mips3d;
276
277 /* True if -mdmx was passed or implied by arguments passed on the
278 command line (e.g., by -march). */
279 static int file_ase_mdmx;
280
281 /* True if -msmartmips was passed or implied by arguments passed on the
282 command line (e.g., by -march). */
283 static int file_ase_smartmips;
284
285 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
286 || mips_opts.isa == ISA_MIPS32R2)
287
288 /* True if -mdsp was passed or implied by arguments passed on the
289 command line (e.g., by -march). */
290 static int file_ase_dsp;
291
292 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64R2)
294
295 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
296
297 /* True if -mdspr2 was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_dspr2;
300
301 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
302 || mips_opts.isa == ISA_MIPS64R2)
303
304 /* True if -mmt was passed or implied by arguments passed on the
305 command line (e.g., by -march). */
306 static int file_ase_mt;
307
308 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
309 || mips_opts.isa == ISA_MIPS64R2)
310
311 /* The argument of the -march= flag. The architecture we are assembling. */
312 static int file_mips_arch = CPU_UNKNOWN;
313 static const char *mips_arch_string;
314
315 /* The argument of the -mtune= flag. The architecture for which we
316 are optimizing. */
317 static int mips_tune = CPU_UNKNOWN;
318 static const char *mips_tune_string;
319
320 /* True when generating 32-bit code for a 64-bit processor. */
321 static int mips_32bitmode = 0;
322
323 /* True if the given ABI requires 32-bit registers. */
324 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
325
326 /* Likewise 64-bit registers. */
327 #define ABI_NEEDS_64BIT_REGS(ABI) \
328 ((ABI) == N32_ABI \
329 || (ABI) == N64_ABI \
330 || (ABI) == O64_ABI)
331
332 /* Return true if ISA supports 64 bit wide gp registers. */
333 #define ISA_HAS_64BIT_REGS(ISA) \
334 ((ISA) == ISA_MIPS3 \
335 || (ISA) == ISA_MIPS4 \
336 || (ISA) == ISA_MIPS5 \
337 || (ISA) == ISA_MIPS64 \
338 || (ISA) == ISA_MIPS64R2)
339
340 /* Return true if ISA supports 64 bit wide float registers. */
341 #define ISA_HAS_64BIT_FPRS(ISA) \
342 ((ISA) == ISA_MIPS3 \
343 || (ISA) == ISA_MIPS4 \
344 || (ISA) == ISA_MIPS5 \
345 || (ISA) == ISA_MIPS32R2 \
346 || (ISA) == ISA_MIPS64 \
347 || (ISA) == ISA_MIPS64R2)
348
349 /* Return true if ISA supports 64-bit right rotate (dror et al.)
350 instructions. */
351 #define ISA_HAS_DROR(ISA) \
352 ((ISA) == ISA_MIPS64R2)
353
354 /* Return true if ISA supports 32-bit right rotate (ror et al.)
355 instructions. */
356 #define ISA_HAS_ROR(ISA) \
357 ((ISA) == ISA_MIPS32R2 \
358 || (ISA) == ISA_MIPS64R2 \
359 || mips_opts.ase_smartmips)
360
361 /* Return true if ISA supports single-precision floats in odd registers. */
362 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
363 ((ISA) == ISA_MIPS32 \
364 || (ISA) == ISA_MIPS32R2 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2)
367
368 /* Return true if ISA supports move to/from high part of a 64-bit
369 floating-point register. */
370 #define ISA_HAS_MXHC1(ISA) \
371 ((ISA) == ISA_MIPS32R2 \
372 || (ISA) == ISA_MIPS64R2)
373
374 #define HAVE_32BIT_GPRS \
375 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
376
377 #define HAVE_32BIT_FPRS \
378 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
379
380 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
381 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
382
383 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
384
385 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
386
387 /* True if relocations are stored in-place. */
388 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
389
390 /* The ABI-derived address size. */
391 #define HAVE_64BIT_ADDRESSES \
392 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
393 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
394
395 /* The size of symbolic constants (i.e., expressions of the form
396 "SYMBOL" or "SYMBOL + OFFSET"). */
397 #define HAVE_32BIT_SYMBOLS \
398 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
399 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
400
401 /* Addresses are loaded in different ways, depending on the address size
402 in use. The n32 ABI Documentation also mandates the use of additions
403 with overflow checking, but existing implementations don't follow it. */
404 #define ADDRESS_ADD_INSN \
405 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
406
407 #define ADDRESS_ADDI_INSN \
408 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
409
410 #define ADDRESS_LOAD_INSN \
411 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
412
413 #define ADDRESS_STORE_INSN \
414 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
415
416 /* Return true if the given CPU supports the MIPS16 ASE. */
417 #define CPU_HAS_MIPS16(cpu) \
418 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
419 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
420
421 /* True if CPU has a dror instruction. */
422 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
423
424 /* True if CPU has a ror instruction. */
425 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
426
427 /* True if mflo and mfhi can be immediately followed by instructions
428 which write to the HI and LO registers.
429
430 According to MIPS specifications, MIPS ISAs I, II, and III need
431 (at least) two instructions between the reads of HI/LO and
432 instructions which write them, and later ISAs do not. Contradicting
433 the MIPS specifications, some MIPS IV processor user manuals (e.g.
434 the UM for the NEC Vr5000) document needing the instructions between
435 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
436 MIPS64 and later ISAs to have the interlocks, plus any specific
437 earlier-ISA CPUs for which CPU documentation declares that the
438 instructions are really interlocked. */
439 #define hilo_interlocks \
440 (mips_opts.isa == ISA_MIPS32 \
441 || mips_opts.isa == ISA_MIPS32R2 \
442 || mips_opts.isa == ISA_MIPS64 \
443 || mips_opts.isa == ISA_MIPS64R2 \
444 || mips_opts.arch == CPU_R4010 \
445 || mips_opts.arch == CPU_R10000 \
446 || mips_opts.arch == CPU_R12000 \
447 || mips_opts.arch == CPU_RM7000 \
448 || mips_opts.arch == CPU_VR5500 \
449 )
450
451 /* Whether the processor uses hardware interlocks to protect reads
452 from the GPRs after they are loaded from memory, and thus does not
453 require nops to be inserted. This applies to instructions marked
454 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
455 level I. */
456 #define gpr_interlocks \
457 (mips_opts.isa != ISA_MIPS1 \
458 || mips_opts.arch == CPU_R3900)
459
460 /* Whether the processor uses hardware interlocks to avoid delays
461 required by coprocessor instructions, and thus does not require
462 nops to be inserted. This applies to instructions marked
463 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
464 between instructions marked INSN_WRITE_COND_CODE and ones marked
465 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
466 levels I, II, and III. */
467 /* Itbl support may require additional care here. */
468 #define cop_interlocks \
469 ((mips_opts.isa != ISA_MIPS1 \
470 && mips_opts.isa != ISA_MIPS2 \
471 && mips_opts.isa != ISA_MIPS3) \
472 || mips_opts.arch == CPU_R4300 \
473 )
474
475 /* Whether the processor uses hardware interlocks to protect reads
476 from coprocessor registers after they are loaded from memory, and
477 thus does not require nops to be inserted. This applies to
478 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
479 requires at MIPS ISA level I. */
480 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
481
482 /* Is this a mfhi or mflo instruction? */
483 #define MF_HILO_INSN(PINFO) \
484 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
485
486 /* MIPS PIC level. */
487
488 enum mips_pic_level mips_pic;
489
490 /* 1 if we should generate 32 bit offsets from the $gp register in
491 SVR4_PIC mode. Currently has no meaning in other modes. */
492 static int mips_big_got = 0;
493
494 /* 1 if trap instructions should used for overflow rather than break
495 instructions. */
496 static int mips_trap = 0;
497
498 /* 1 if double width floating point constants should not be constructed
499 by assembling two single width halves into two single width floating
500 point registers which just happen to alias the double width destination
501 register. On some architectures this aliasing can be disabled by a bit
502 in the status register, and the setting of this bit cannot be determined
503 automatically at assemble time. */
504 static int mips_disable_float_construction;
505
506 /* Non-zero if any .set noreorder directives were used. */
507
508 static int mips_any_noreorder;
509
510 /* Non-zero if nops should be inserted when the register referenced in
511 an mfhi/mflo instruction is read in the next two instructions. */
512 static int mips_7000_hilo_fix;
513
514 /* The size of objects in the small data section. */
515 static unsigned int g_switch_value = 8;
516 /* Whether the -G option was used. */
517 static int g_switch_seen = 0;
518
519 #define N_RMASK 0xc4
520 #define N_VFP 0xd4
521
522 /* If we can determine in advance that GP optimization won't be
523 possible, we can skip the relaxation stuff that tries to produce
524 GP-relative references. This makes delay slot optimization work
525 better.
526
527 This function can only provide a guess, but it seems to work for
528 gcc output. It needs to guess right for gcc, otherwise gcc
529 will put what it thinks is a GP-relative instruction in a branch
530 delay slot.
531
532 I don't know if a fix is needed for the SVR4_PIC mode. I've only
533 fixed it for the non-PIC mode. KR 95/04/07 */
534 static int nopic_need_relax (symbolS *, int);
535
536 /* handle of the OPCODE hash table */
537 static struct hash_control *op_hash = NULL;
538
539 /* The opcode hash table we use for the mips16. */
540 static struct hash_control *mips16_op_hash = NULL;
541
542 /* This array holds the chars that always start a comment. If the
543 pre-processor is disabled, these aren't very useful */
544 const char comment_chars[] = "#";
545
546 /* This array holds the chars that only start a comment at the beginning of
547 a line. If the line seems to have the form '# 123 filename'
548 .line and .file directives will appear in the pre-processed output */
549 /* Note that input_file.c hand checks for '#' at the beginning of the
550 first line of the input file. This is because the compiler outputs
551 #NO_APP at the beginning of its output. */
552 /* Also note that C style comments are always supported. */
553 const char line_comment_chars[] = "#";
554
555 /* This array holds machine specific line separator characters. */
556 const char line_separator_chars[] = ";";
557
558 /* Chars that can be used to separate mant from exp in floating point nums */
559 const char EXP_CHARS[] = "eE";
560
561 /* Chars that mean this number is a floating point constant */
562 /* As in 0f12.456 */
563 /* or 0d1.2345e12 */
564 const char FLT_CHARS[] = "rRsSfFdDxXpP";
565
566 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
567 changed in read.c . Ideally it shouldn't have to know about it at all,
568 but nothing is ideal around here.
569 */
570
571 static char *insn_error;
572
573 static int auto_align = 1;
574
575 /* When outputting SVR4 PIC code, the assembler needs to know the
576 offset in the stack frame from which to restore the $gp register.
577 This is set by the .cprestore pseudo-op, and saved in this
578 variable. */
579 static offsetT mips_cprestore_offset = -1;
580
581 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
582 more optimizations, it can use a register value instead of a memory-saved
583 offset and even an other register than $gp as global pointer. */
584 static offsetT mips_cpreturn_offset = -1;
585 static int mips_cpreturn_register = -1;
586 static int mips_gp_register = GP;
587 static int mips_gprel_offset = 0;
588
589 /* Whether mips_cprestore_offset has been set in the current function
590 (or whether it has already been warned about, if not). */
591 static int mips_cprestore_valid = 0;
592
593 /* This is the register which holds the stack frame, as set by the
594 .frame pseudo-op. This is needed to implement .cprestore. */
595 static int mips_frame_reg = SP;
596
597 /* Whether mips_frame_reg has been set in the current function
598 (or whether it has already been warned about, if not). */
599 static int mips_frame_reg_valid = 0;
600
601 /* To output NOP instructions correctly, we need to keep information
602 about the previous two instructions. */
603
604 /* Whether we are optimizing. The default value of 2 means to remove
605 unneeded NOPs and swap branch instructions when possible. A value
606 of 1 means to not swap branches. A value of 0 means to always
607 insert NOPs. */
608 static int mips_optimize = 2;
609
610 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
611 equivalent to seeing no -g option at all. */
612 static int mips_debug = 0;
613
614 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
615 #define MAX_VR4130_NOPS 4
616
617 /* The maximum number of NOPs needed to fill delay slots. */
618 #define MAX_DELAY_NOPS 2
619
620 /* The maximum number of NOPs needed for any purpose. */
621 #define MAX_NOPS 4
622
623 /* A list of previous instructions, with index 0 being the most recent.
624 We need to look back MAX_NOPS instructions when filling delay slots
625 or working around processor errata. We need to look back one
626 instruction further if we're thinking about using history[0] to
627 fill a branch delay slot. */
628 static struct mips_cl_insn history[1 + MAX_NOPS];
629
630 /* Nop instructions used by emit_nop. */
631 static struct mips_cl_insn nop_insn, mips16_nop_insn;
632
633 /* The appropriate nop for the current mode. */
634 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
635
636 /* If this is set, it points to a frag holding nop instructions which
637 were inserted before the start of a noreorder section. If those
638 nops turn out to be unnecessary, the size of the frag can be
639 decreased. */
640 static fragS *prev_nop_frag;
641
642 /* The number of nop instructions we created in prev_nop_frag. */
643 static int prev_nop_frag_holds;
644
645 /* The number of nop instructions that we know we need in
646 prev_nop_frag. */
647 static int prev_nop_frag_required;
648
649 /* The number of instructions we've seen since prev_nop_frag. */
650 static int prev_nop_frag_since;
651
652 /* For ECOFF and ELF, relocations against symbols are done in two
653 parts, with a HI relocation and a LO relocation. Each relocation
654 has only 16 bits of space to store an addend. This means that in
655 order for the linker to handle carries correctly, it must be able
656 to locate both the HI and the LO relocation. This means that the
657 relocations must appear in order in the relocation table.
658
659 In order to implement this, we keep track of each unmatched HI
660 relocation. We then sort them so that they immediately precede the
661 corresponding LO relocation. */
662
663 struct mips_hi_fixup
664 {
665 /* Next HI fixup. */
666 struct mips_hi_fixup *next;
667 /* This fixup. */
668 fixS *fixp;
669 /* The section this fixup is in. */
670 segT seg;
671 };
672
673 /* The list of unmatched HI relocs. */
674
675 static struct mips_hi_fixup *mips_hi_fixup_list;
676
677 /* The frag containing the last explicit relocation operator.
678 Null if explicit relocations have not been used. */
679
680 static fragS *prev_reloc_op_frag;
681
682 /* Map normal MIPS register numbers to mips16 register numbers. */
683
684 #define X ILLEGAL_REG
685 static const int mips32_to_16_reg_map[] =
686 {
687 X, X, 2, 3, 4, 5, 6, 7,
688 X, X, X, X, X, X, X, X,
689 0, 1, X, X, X, X, X, X,
690 X, X, X, X, X, X, X, X
691 };
692 #undef X
693
694 /* Map mips16 register numbers to normal MIPS register numbers. */
695
696 static const unsigned int mips16_to_32_reg_map[] =
697 {
698 16, 17, 2, 3, 4, 5, 6, 7
699 };
700
701 /* Classifies the kind of instructions we're interested in when
702 implementing -mfix-vr4120. */
703 enum fix_vr4120_class {
704 FIX_VR4120_MACC,
705 FIX_VR4120_DMACC,
706 FIX_VR4120_MULT,
707 FIX_VR4120_DMULT,
708 FIX_VR4120_DIV,
709 FIX_VR4120_MTHILO,
710 NUM_FIX_VR4120_CLASSES
711 };
712
713 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
714 there must be at least one other instruction between an instruction
715 of type X and an instruction of type Y. */
716 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
717
718 /* True if -mfix-vr4120 is in force. */
719 static int mips_fix_vr4120;
720
721 /* ...likewise -mfix-vr4130. */
722 static int mips_fix_vr4130;
723
724 /* We don't relax branches by default, since this causes us to expand
725 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
726 fail to compute the offset before expanding the macro to the most
727 efficient expansion. */
728
729 static int mips_relax_branch;
730 \f
731 /* The expansion of many macros depends on the type of symbol that
732 they refer to. For example, when generating position-dependent code,
733 a macro that refers to a symbol may have two different expansions,
734 one which uses GP-relative addresses and one which uses absolute
735 addresses. When generating SVR4-style PIC, a macro may have
736 different expansions for local and global symbols.
737
738 We handle these situations by generating both sequences and putting
739 them in variant frags. In position-dependent code, the first sequence
740 will be the GP-relative one and the second sequence will be the
741 absolute one. In SVR4 PIC, the first sequence will be for global
742 symbols and the second will be for local symbols.
743
744 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
745 SECOND are the lengths of the two sequences in bytes. These fields
746 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
747 the subtype has the following flags:
748
749 RELAX_USE_SECOND
750 Set if it has been decided that we should use the second
751 sequence instead of the first.
752
753 RELAX_SECOND_LONGER
754 Set in the first variant frag if the macro's second implementation
755 is longer than its first. This refers to the macro as a whole,
756 not an individual relaxation.
757
758 RELAX_NOMACRO
759 Set in the first variant frag if the macro appeared in a .set nomacro
760 block and if one alternative requires a warning but the other does not.
761
762 RELAX_DELAY_SLOT
763 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
764 delay slot.
765
766 The frag's "opcode" points to the first fixup for relaxable code.
767
768 Relaxable macros are generated using a sequence such as:
769
770 relax_start (SYMBOL);
771 ... generate first expansion ...
772 relax_switch ();
773 ... generate second expansion ...
774 relax_end ();
775
776 The code and fixups for the unwanted alternative are discarded
777 by md_convert_frag. */
778 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
779
780 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
781 #define RELAX_SECOND(X) ((X) & 0xff)
782 #define RELAX_USE_SECOND 0x10000
783 #define RELAX_SECOND_LONGER 0x20000
784 #define RELAX_NOMACRO 0x40000
785 #define RELAX_DELAY_SLOT 0x80000
786
787 /* Branch without likely bit. If label is out of range, we turn:
788
789 beq reg1, reg2, label
790 delay slot
791
792 into
793
794 bne reg1, reg2, 0f
795 nop
796 j label
797 0: delay slot
798
799 with the following opcode replacements:
800
801 beq <-> bne
802 blez <-> bgtz
803 bltz <-> bgez
804 bc1f <-> bc1t
805
806 bltzal <-> bgezal (with jal label instead of j label)
807
808 Even though keeping the delay slot instruction in the delay slot of
809 the branch would be more efficient, it would be very tricky to do
810 correctly, because we'd have to introduce a variable frag *after*
811 the delay slot instruction, and expand that instead. Let's do it
812 the easy way for now, even if the branch-not-taken case now costs
813 one additional instruction. Out-of-range branches are not supposed
814 to be common, anyway.
815
816 Branch likely. If label is out of range, we turn:
817
818 beql reg1, reg2, label
819 delay slot (annulled if branch not taken)
820
821 into
822
823 beql reg1, reg2, 1f
824 nop
825 beql $0, $0, 2f
826 nop
827 1: j[al] label
828 delay slot (executed only if branch taken)
829 2:
830
831 It would be possible to generate a shorter sequence by losing the
832 likely bit, generating something like:
833
834 bne reg1, reg2, 0f
835 nop
836 j[al] label
837 delay slot (executed only if branch taken)
838 0:
839
840 beql -> bne
841 bnel -> beq
842 blezl -> bgtz
843 bgtzl -> blez
844 bltzl -> bgez
845 bgezl -> bltz
846 bc1fl -> bc1t
847 bc1tl -> bc1f
848
849 bltzall -> bgezal (with jal label instead of j label)
850 bgezall -> bltzal (ditto)
851
852
853 but it's not clear that it would actually improve performance. */
854 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
855 ((relax_substateT) \
856 (0xc0000000 \
857 | ((toofar) ? 1 : 0) \
858 | ((link) ? 2 : 0) \
859 | ((likely) ? 4 : 0) \
860 | ((uncond) ? 8 : 0)))
861 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
862 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
863 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
864 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
865 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
866
867 /* For mips16 code, we use an entirely different form of relaxation.
868 mips16 supports two versions of most instructions which take
869 immediate values: a small one which takes some small value, and a
870 larger one which takes a 16 bit value. Since branches also follow
871 this pattern, relaxing these values is required.
872
873 We can assemble both mips16 and normal MIPS code in a single
874 object. Therefore, we need to support this type of relaxation at
875 the same time that we support the relaxation described above. We
876 use the high bit of the subtype field to distinguish these cases.
877
878 The information we store for this type of relaxation is the
879 argument code found in the opcode file for this relocation, whether
880 the user explicitly requested a small or extended form, and whether
881 the relocation is in a jump or jal delay slot. That tells us the
882 size of the value, and how it should be stored. We also store
883 whether the fragment is considered to be extended or not. We also
884 store whether this is known to be a branch to a different section,
885 whether we have tried to relax this frag yet, and whether we have
886 ever extended a PC relative fragment because of a shift count. */
887 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
888 (0x80000000 \
889 | ((type) & 0xff) \
890 | ((small) ? 0x100 : 0) \
891 | ((ext) ? 0x200 : 0) \
892 | ((dslot) ? 0x400 : 0) \
893 | ((jal_dslot) ? 0x800 : 0))
894 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
895 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
896 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
897 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
898 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
899 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
900 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
901 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
902 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
903 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
904 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
905 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
906
907 /* Is the given value a sign-extended 32-bit value? */
908 #define IS_SEXT_32BIT_NUM(x) \
909 (((x) &~ (offsetT) 0x7fffffff) == 0 \
910 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
911
912 /* Is the given value a sign-extended 16-bit value? */
913 #define IS_SEXT_16BIT_NUM(x) \
914 (((x) &~ (offsetT) 0x7fff) == 0 \
915 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
916
917 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
918 #define IS_ZEXT_32BIT_NUM(x) \
919 (((x) &~ (offsetT) 0xffffffff) == 0 \
920 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
921
922 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
923 VALUE << SHIFT. VALUE is evaluated exactly once. */
924 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
925 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
926 | (((VALUE) & (MASK)) << (SHIFT)))
927
928 /* Extract bits MASK << SHIFT from STRUCT and shift them right
929 SHIFT places. */
930 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
931 (((STRUCT) >> (SHIFT)) & (MASK))
932
933 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
934 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
935
936 include/opcode/mips.h specifies operand fields using the macros
937 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
938 with "MIPS16OP" instead of "OP". */
939 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
940 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
941 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
942 INSERT_BITS ((INSN).insn_opcode, VALUE, \
943 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
944
945 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
946 #define EXTRACT_OPERAND(FIELD, INSN) \
947 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
948 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
949 EXTRACT_BITS ((INSN).insn_opcode, \
950 MIPS16OP_MASK_##FIELD, \
951 MIPS16OP_SH_##FIELD)
952 \f
953 /* Global variables used when generating relaxable macros. See the
954 comment above RELAX_ENCODE for more details about how relaxation
955 is used. */
956 static struct {
957 /* 0 if we're not emitting a relaxable macro.
958 1 if we're emitting the first of the two relaxation alternatives.
959 2 if we're emitting the second alternative. */
960 int sequence;
961
962 /* The first relaxable fixup in the current frag. (In other words,
963 the first fixup that refers to relaxable code.) */
964 fixS *first_fixup;
965
966 /* sizes[0] says how many bytes of the first alternative are stored in
967 the current frag. Likewise sizes[1] for the second alternative. */
968 unsigned int sizes[2];
969
970 /* The symbol on which the choice of sequence depends. */
971 symbolS *symbol;
972 } mips_relax;
973 \f
974 /* Global variables used to decide whether a macro needs a warning. */
975 static struct {
976 /* True if the macro is in a branch delay slot. */
977 bfd_boolean delay_slot_p;
978
979 /* For relaxable macros, sizes[0] is the length of the first alternative
980 in bytes and sizes[1] is the length of the second alternative.
981 For non-relaxable macros, both elements give the length of the
982 macro in bytes. */
983 unsigned int sizes[2];
984
985 /* The first variant frag for this macro. */
986 fragS *first_frag;
987 } mips_macro_warning;
988 \f
989 /* Prototypes for static functions. */
990
991 #define internalError() \
992 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
993
994 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
995
996 static void append_insn
997 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
998 static void mips_no_prev_insn (void);
999 static void mips16_macro_build
1000 (expressionS *, const char *, const char *, va_list);
1001 static void load_register (int, expressionS *, int);
1002 static void macro_start (void);
1003 static void macro_end (void);
1004 static void macro (struct mips_cl_insn * ip);
1005 static void mips16_macro (struct mips_cl_insn * ip);
1006 #ifdef LOSING_COMPILER
1007 static void macro2 (struct mips_cl_insn * ip);
1008 #endif
1009 static void mips_ip (char *str, struct mips_cl_insn * ip);
1010 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1011 static void mips16_immed
1012 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1013 unsigned long *, bfd_boolean *, unsigned short *);
1014 static size_t my_getSmallExpression
1015 (expressionS *, bfd_reloc_code_real_type *, char *);
1016 static void my_getExpression (expressionS *, char *);
1017 static void s_align (int);
1018 static void s_change_sec (int);
1019 static void s_change_section (int);
1020 static void s_cons (int);
1021 static void s_float_cons (int);
1022 static void s_mips_globl (int);
1023 static void s_option (int);
1024 static void s_mipsset (int);
1025 static void s_abicalls (int);
1026 static void s_cpload (int);
1027 static void s_cpsetup (int);
1028 static void s_cplocal (int);
1029 static void s_cprestore (int);
1030 static void s_cpreturn (int);
1031 static void s_dtprelword (int);
1032 static void s_dtpreldword (int);
1033 static void s_gpvalue (int);
1034 static void s_gpword (int);
1035 static void s_gpdword (int);
1036 static void s_cpadd (int);
1037 static void s_insn (int);
1038 static void md_obj_begin (void);
1039 static void md_obj_end (void);
1040 static void s_mips_ent (int);
1041 static void s_mips_end (int);
1042 static void s_mips_frame (int);
1043 static void s_mips_mask (int reg_type);
1044 static void s_mips_stab (int);
1045 static void s_mips_weakext (int);
1046 static void s_mips_file (int);
1047 static void s_mips_loc (int);
1048 static bfd_boolean pic_need_relax (symbolS *, asection *);
1049 static int relaxed_branch_length (fragS *, asection *, int);
1050 static int validate_mips_insn (const struct mips_opcode *);
1051
1052 /* Table and functions used to map between CPU/ISA names, and
1053 ISA levels, and CPU numbers. */
1054
1055 struct mips_cpu_info
1056 {
1057 const char *name; /* CPU or ISA name. */
1058 int flags; /* ASEs available, or ISA flag. */
1059 int isa; /* ISA level. */
1060 int cpu; /* CPU number (default CPU if ISA). */
1061 };
1062
1063 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1064 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1065 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1066 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1067 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1068 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1069 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1070
1071 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1072 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1073 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1074 \f
1075 /* Pseudo-op table.
1076
1077 The following pseudo-ops from the Kane and Heinrich MIPS book
1078 should be defined here, but are currently unsupported: .alias,
1079 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1080
1081 The following pseudo-ops from the Kane and Heinrich MIPS book are
1082 specific to the type of debugging information being generated, and
1083 should be defined by the object format: .aent, .begin, .bend,
1084 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1085 .vreg.
1086
1087 The following pseudo-ops from the Kane and Heinrich MIPS book are
1088 not MIPS CPU specific, but are also not specific to the object file
1089 format. This file is probably the best place to define them, but
1090 they are not currently supported: .asm0, .endr, .lab, .struct. */
1091
1092 static const pseudo_typeS mips_pseudo_table[] =
1093 {
1094 /* MIPS specific pseudo-ops. */
1095 {"option", s_option, 0},
1096 {"set", s_mipsset, 0},
1097 {"rdata", s_change_sec, 'r'},
1098 {"sdata", s_change_sec, 's'},
1099 {"livereg", s_ignore, 0},
1100 {"abicalls", s_abicalls, 0},
1101 {"cpload", s_cpload, 0},
1102 {"cpsetup", s_cpsetup, 0},
1103 {"cplocal", s_cplocal, 0},
1104 {"cprestore", s_cprestore, 0},
1105 {"cpreturn", s_cpreturn, 0},
1106 {"dtprelword", s_dtprelword, 0},
1107 {"dtpreldword", s_dtpreldword, 0},
1108 {"gpvalue", s_gpvalue, 0},
1109 {"gpword", s_gpword, 0},
1110 {"gpdword", s_gpdword, 0},
1111 {"cpadd", s_cpadd, 0},
1112 {"insn", s_insn, 0},
1113
1114 /* Relatively generic pseudo-ops that happen to be used on MIPS
1115 chips. */
1116 {"asciiz", stringer, 8 + 1},
1117 {"bss", s_change_sec, 'b'},
1118 {"err", s_err, 0},
1119 {"half", s_cons, 1},
1120 {"dword", s_cons, 3},
1121 {"weakext", s_mips_weakext, 0},
1122 {"origin", s_org, 0},
1123 {"repeat", s_rept, 0},
1124
1125 /* These pseudo-ops are defined in read.c, but must be overridden
1126 here for one reason or another. */
1127 {"align", s_align, 0},
1128 {"byte", s_cons, 0},
1129 {"data", s_change_sec, 'd'},
1130 {"double", s_float_cons, 'd'},
1131 {"float", s_float_cons, 'f'},
1132 {"globl", s_mips_globl, 0},
1133 {"global", s_mips_globl, 0},
1134 {"hword", s_cons, 1},
1135 {"int", s_cons, 2},
1136 {"long", s_cons, 2},
1137 {"octa", s_cons, 4},
1138 {"quad", s_cons, 3},
1139 {"section", s_change_section, 0},
1140 {"short", s_cons, 1},
1141 {"single", s_float_cons, 'f'},
1142 {"stabn", s_mips_stab, 'n'},
1143 {"text", s_change_sec, 't'},
1144 {"word", s_cons, 2},
1145
1146 { "extern", ecoff_directive_extern, 0},
1147
1148 { NULL, NULL, 0 },
1149 };
1150
1151 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1152 {
1153 /* These pseudo-ops should be defined by the object file format.
1154 However, a.out doesn't support them, so we have versions here. */
1155 {"aent", s_mips_ent, 1},
1156 {"bgnb", s_ignore, 0},
1157 {"end", s_mips_end, 0},
1158 {"endb", s_ignore, 0},
1159 {"ent", s_mips_ent, 0},
1160 {"file", s_mips_file, 0},
1161 {"fmask", s_mips_mask, 'F'},
1162 {"frame", s_mips_frame, 0},
1163 {"loc", s_mips_loc, 0},
1164 {"mask", s_mips_mask, 'R'},
1165 {"verstamp", s_ignore, 0},
1166 { NULL, NULL, 0 },
1167 };
1168
1169 extern void pop_insert (const pseudo_typeS *);
1170
1171 void
1172 mips_pop_insert (void)
1173 {
1174 pop_insert (mips_pseudo_table);
1175 if (! ECOFF_DEBUGGING)
1176 pop_insert (mips_nonecoff_pseudo_table);
1177 }
1178 \f
1179 /* Symbols labelling the current insn. */
1180
1181 struct insn_label_list
1182 {
1183 struct insn_label_list *next;
1184 symbolS *label;
1185 };
1186
1187 static struct insn_label_list *free_insn_labels;
1188 #define label_list tc_segment_info_data
1189
1190 static void mips_clear_insn_labels (void);
1191
1192 static inline void
1193 mips_clear_insn_labels (void)
1194 {
1195 register struct insn_label_list **pl;
1196 segment_info_type *si;
1197
1198 if (now_seg)
1199 {
1200 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1201 ;
1202
1203 si = seg_info (now_seg);
1204 *pl = si->label_list;
1205 si->label_list = NULL;
1206 }
1207 }
1208
1209 \f
1210 static char *expr_end;
1211
1212 /* Expressions which appear in instructions. These are set by
1213 mips_ip. */
1214
1215 static expressionS imm_expr;
1216 static expressionS imm2_expr;
1217 static expressionS offset_expr;
1218
1219 /* Relocs associated with imm_expr and offset_expr. */
1220
1221 static bfd_reloc_code_real_type imm_reloc[3]
1222 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1223 static bfd_reloc_code_real_type offset_reloc[3]
1224 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1225
1226 /* These are set by mips16_ip if an explicit extension is used. */
1227
1228 static bfd_boolean mips16_small, mips16_ext;
1229
1230 #ifdef OBJ_ELF
1231 /* The pdr segment for per procedure frame/regmask info. Not used for
1232 ECOFF debugging. */
1233
1234 static segT pdr_seg;
1235 #endif
1236
1237 /* The default target format to use. */
1238
1239 const char *
1240 mips_target_format (void)
1241 {
1242 switch (OUTPUT_FLAVOR)
1243 {
1244 case bfd_target_ecoff_flavour:
1245 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1246 case bfd_target_coff_flavour:
1247 return "pe-mips";
1248 case bfd_target_elf_flavour:
1249 #ifdef TE_VXWORKS
1250 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1251 return (target_big_endian
1252 ? "elf32-bigmips-vxworks"
1253 : "elf32-littlemips-vxworks");
1254 #endif
1255 #ifdef TE_TMIPS
1256 /* This is traditional mips. */
1257 return (target_big_endian
1258 ? (HAVE_64BIT_OBJECTS
1259 ? "elf64-tradbigmips"
1260 : (HAVE_NEWABI
1261 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1262 : (HAVE_64BIT_OBJECTS
1263 ? "elf64-tradlittlemips"
1264 : (HAVE_NEWABI
1265 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1266 #else
1267 return (target_big_endian
1268 ? (HAVE_64BIT_OBJECTS
1269 ? "elf64-bigmips"
1270 : (HAVE_NEWABI
1271 ? "elf32-nbigmips" : "elf32-bigmips"))
1272 : (HAVE_64BIT_OBJECTS
1273 ? "elf64-littlemips"
1274 : (HAVE_NEWABI
1275 ? "elf32-nlittlemips" : "elf32-littlemips")));
1276 #endif
1277 default:
1278 abort ();
1279 return NULL;
1280 }
1281 }
1282
1283 /* Return the length of instruction INSN. */
1284
1285 static inline unsigned int
1286 insn_length (const struct mips_cl_insn *insn)
1287 {
1288 if (!mips_opts.mips16)
1289 return 4;
1290 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1291 }
1292
1293 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1294
1295 static void
1296 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1297 {
1298 size_t i;
1299
1300 insn->insn_mo = mo;
1301 insn->use_extend = FALSE;
1302 insn->extend = 0;
1303 insn->insn_opcode = mo->match;
1304 insn->frag = NULL;
1305 insn->where = 0;
1306 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1307 insn->fixp[i] = NULL;
1308 insn->fixed_p = (mips_opts.noreorder > 0);
1309 insn->noreorder_p = (mips_opts.noreorder > 0);
1310 insn->mips16_absolute_jump_p = 0;
1311 }
1312
1313 /* Install INSN at the location specified by its "frag" and "where" fields. */
1314
1315 static void
1316 install_insn (const struct mips_cl_insn *insn)
1317 {
1318 char *f = insn->frag->fr_literal + insn->where;
1319 if (!mips_opts.mips16)
1320 md_number_to_chars (f, insn->insn_opcode, 4);
1321 else if (insn->mips16_absolute_jump_p)
1322 {
1323 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1324 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1325 }
1326 else
1327 {
1328 if (insn->use_extend)
1329 {
1330 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1331 f += 2;
1332 }
1333 md_number_to_chars (f, insn->insn_opcode, 2);
1334 }
1335 }
1336
1337 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1338 and install the opcode in the new location. */
1339
1340 static void
1341 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1342 {
1343 size_t i;
1344
1345 insn->frag = frag;
1346 insn->where = where;
1347 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1348 if (insn->fixp[i] != NULL)
1349 {
1350 insn->fixp[i]->fx_frag = frag;
1351 insn->fixp[i]->fx_where = where;
1352 }
1353 install_insn (insn);
1354 }
1355
1356 /* Add INSN to the end of the output. */
1357
1358 static void
1359 add_fixed_insn (struct mips_cl_insn *insn)
1360 {
1361 char *f = frag_more (insn_length (insn));
1362 move_insn (insn, frag_now, f - frag_now->fr_literal);
1363 }
1364
1365 /* Start a variant frag and move INSN to the start of the variant part,
1366 marking it as fixed. The other arguments are as for frag_var. */
1367
1368 static void
1369 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1370 relax_substateT subtype, symbolS *symbol, offsetT offset)
1371 {
1372 frag_grow (max_chars);
1373 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1374 insn->fixed_p = 1;
1375 frag_var (rs_machine_dependent, max_chars, var,
1376 subtype, symbol, offset, NULL);
1377 }
1378
1379 /* Insert N copies of INSN into the history buffer, starting at
1380 position FIRST. Neither FIRST nor N need to be clipped. */
1381
1382 static void
1383 insert_into_history (unsigned int first, unsigned int n,
1384 const struct mips_cl_insn *insn)
1385 {
1386 if (mips_relax.sequence != 2)
1387 {
1388 unsigned int i;
1389
1390 for (i = ARRAY_SIZE (history); i-- > first;)
1391 if (i >= first + n)
1392 history[i] = history[i - n];
1393 else
1394 history[i] = *insn;
1395 }
1396 }
1397
1398 /* Emit a nop instruction, recording it in the history buffer. */
1399
1400 static void
1401 emit_nop (void)
1402 {
1403 add_fixed_insn (NOP_INSN);
1404 insert_into_history (0, 1, NOP_INSN);
1405 }
1406
1407 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1408 the idea is to make it obvious at a glance that each errata is
1409 included. */
1410
1411 static void
1412 init_vr4120_conflicts (void)
1413 {
1414 #define CONFLICT(FIRST, SECOND) \
1415 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1416
1417 /* Errata 21 - [D]DIV[U] after [D]MACC */
1418 CONFLICT (MACC, DIV);
1419 CONFLICT (DMACC, DIV);
1420
1421 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1422 CONFLICT (DMULT, DMULT);
1423 CONFLICT (DMULT, DMACC);
1424 CONFLICT (DMACC, DMULT);
1425 CONFLICT (DMACC, DMACC);
1426
1427 /* Errata 24 - MT{LO,HI} after [D]MACC */
1428 CONFLICT (MACC, MTHILO);
1429 CONFLICT (DMACC, MTHILO);
1430
1431 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1432 instruction is executed immediately after a MACC or DMACC
1433 instruction, the result of [either instruction] is incorrect." */
1434 CONFLICT (MACC, MULT);
1435 CONFLICT (MACC, DMULT);
1436 CONFLICT (DMACC, MULT);
1437 CONFLICT (DMACC, DMULT);
1438
1439 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1440 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1441 DDIV or DDIVU instruction, the result of the MACC or
1442 DMACC instruction is incorrect.". */
1443 CONFLICT (DMULT, MACC);
1444 CONFLICT (DMULT, DMACC);
1445 CONFLICT (DIV, MACC);
1446 CONFLICT (DIV, DMACC);
1447
1448 #undef CONFLICT
1449 }
1450
1451 struct regname {
1452 const char *name;
1453 unsigned int num;
1454 };
1455
1456 #define RTYPE_MASK 0x1ff00
1457 #define RTYPE_NUM 0x00100
1458 #define RTYPE_FPU 0x00200
1459 #define RTYPE_FCC 0x00400
1460 #define RTYPE_VEC 0x00800
1461 #define RTYPE_GP 0x01000
1462 #define RTYPE_CP0 0x02000
1463 #define RTYPE_PC 0x04000
1464 #define RTYPE_ACC 0x08000
1465 #define RTYPE_CCC 0x10000
1466 #define RNUM_MASK 0x000ff
1467 #define RWARN 0x80000
1468
1469 #define GENERIC_REGISTER_NUMBERS \
1470 {"$0", RTYPE_NUM | 0}, \
1471 {"$1", RTYPE_NUM | 1}, \
1472 {"$2", RTYPE_NUM | 2}, \
1473 {"$3", RTYPE_NUM | 3}, \
1474 {"$4", RTYPE_NUM | 4}, \
1475 {"$5", RTYPE_NUM | 5}, \
1476 {"$6", RTYPE_NUM | 6}, \
1477 {"$7", RTYPE_NUM | 7}, \
1478 {"$8", RTYPE_NUM | 8}, \
1479 {"$9", RTYPE_NUM | 9}, \
1480 {"$10", RTYPE_NUM | 10}, \
1481 {"$11", RTYPE_NUM | 11}, \
1482 {"$12", RTYPE_NUM | 12}, \
1483 {"$13", RTYPE_NUM | 13}, \
1484 {"$14", RTYPE_NUM | 14}, \
1485 {"$15", RTYPE_NUM | 15}, \
1486 {"$16", RTYPE_NUM | 16}, \
1487 {"$17", RTYPE_NUM | 17}, \
1488 {"$18", RTYPE_NUM | 18}, \
1489 {"$19", RTYPE_NUM | 19}, \
1490 {"$20", RTYPE_NUM | 20}, \
1491 {"$21", RTYPE_NUM | 21}, \
1492 {"$22", RTYPE_NUM | 22}, \
1493 {"$23", RTYPE_NUM | 23}, \
1494 {"$24", RTYPE_NUM | 24}, \
1495 {"$25", RTYPE_NUM | 25}, \
1496 {"$26", RTYPE_NUM | 26}, \
1497 {"$27", RTYPE_NUM | 27}, \
1498 {"$28", RTYPE_NUM | 28}, \
1499 {"$29", RTYPE_NUM | 29}, \
1500 {"$30", RTYPE_NUM | 30}, \
1501 {"$31", RTYPE_NUM | 31}
1502
1503 #define FPU_REGISTER_NAMES \
1504 {"$f0", RTYPE_FPU | 0}, \
1505 {"$f1", RTYPE_FPU | 1}, \
1506 {"$f2", RTYPE_FPU | 2}, \
1507 {"$f3", RTYPE_FPU | 3}, \
1508 {"$f4", RTYPE_FPU | 4}, \
1509 {"$f5", RTYPE_FPU | 5}, \
1510 {"$f6", RTYPE_FPU | 6}, \
1511 {"$f7", RTYPE_FPU | 7}, \
1512 {"$f8", RTYPE_FPU | 8}, \
1513 {"$f9", RTYPE_FPU | 9}, \
1514 {"$f10", RTYPE_FPU | 10}, \
1515 {"$f11", RTYPE_FPU | 11}, \
1516 {"$f12", RTYPE_FPU | 12}, \
1517 {"$f13", RTYPE_FPU | 13}, \
1518 {"$f14", RTYPE_FPU | 14}, \
1519 {"$f15", RTYPE_FPU | 15}, \
1520 {"$f16", RTYPE_FPU | 16}, \
1521 {"$f17", RTYPE_FPU | 17}, \
1522 {"$f18", RTYPE_FPU | 18}, \
1523 {"$f19", RTYPE_FPU | 19}, \
1524 {"$f20", RTYPE_FPU | 20}, \
1525 {"$f21", RTYPE_FPU | 21}, \
1526 {"$f22", RTYPE_FPU | 22}, \
1527 {"$f23", RTYPE_FPU | 23}, \
1528 {"$f24", RTYPE_FPU | 24}, \
1529 {"$f25", RTYPE_FPU | 25}, \
1530 {"$f26", RTYPE_FPU | 26}, \
1531 {"$f27", RTYPE_FPU | 27}, \
1532 {"$f28", RTYPE_FPU | 28}, \
1533 {"$f29", RTYPE_FPU | 29}, \
1534 {"$f30", RTYPE_FPU | 30}, \
1535 {"$f31", RTYPE_FPU | 31}
1536
1537 #define FPU_CONDITION_CODE_NAMES \
1538 {"$fcc0", RTYPE_FCC | 0}, \
1539 {"$fcc1", RTYPE_FCC | 1}, \
1540 {"$fcc2", RTYPE_FCC | 2}, \
1541 {"$fcc3", RTYPE_FCC | 3}, \
1542 {"$fcc4", RTYPE_FCC | 4}, \
1543 {"$fcc5", RTYPE_FCC | 5}, \
1544 {"$fcc6", RTYPE_FCC | 6}, \
1545 {"$fcc7", RTYPE_FCC | 7}
1546
1547 #define COPROC_CONDITION_CODE_NAMES \
1548 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1549 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1550 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1551 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1552 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1553 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1554 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1555 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1556
1557 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1558 {"$a4", RTYPE_GP | 8}, \
1559 {"$a5", RTYPE_GP | 9}, \
1560 {"$a6", RTYPE_GP | 10}, \
1561 {"$a7", RTYPE_GP | 11}, \
1562 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1563 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1564 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1565 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1566 {"$t0", RTYPE_GP | 12}, \
1567 {"$t1", RTYPE_GP | 13}, \
1568 {"$t2", RTYPE_GP | 14}, \
1569 {"$t3", RTYPE_GP | 15}
1570
1571 #define O32_SYMBOLIC_REGISTER_NAMES \
1572 {"$t0", RTYPE_GP | 8}, \
1573 {"$t1", RTYPE_GP | 9}, \
1574 {"$t2", RTYPE_GP | 10}, \
1575 {"$t3", RTYPE_GP | 11}, \
1576 {"$t4", RTYPE_GP | 12}, \
1577 {"$t5", RTYPE_GP | 13}, \
1578 {"$t6", RTYPE_GP | 14}, \
1579 {"$t7", RTYPE_GP | 15}, \
1580 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1581 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1582 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1583 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1584
1585 /* Remaining symbolic register names */
1586 #define SYMBOLIC_REGISTER_NAMES \
1587 {"$zero", RTYPE_GP | 0}, \
1588 {"$at", RTYPE_GP | 1}, \
1589 {"$AT", RTYPE_GP | 1}, \
1590 {"$v0", RTYPE_GP | 2}, \
1591 {"$v1", RTYPE_GP | 3}, \
1592 {"$a0", RTYPE_GP | 4}, \
1593 {"$a1", RTYPE_GP | 5}, \
1594 {"$a2", RTYPE_GP | 6}, \
1595 {"$a3", RTYPE_GP | 7}, \
1596 {"$s0", RTYPE_GP | 16}, \
1597 {"$s1", RTYPE_GP | 17}, \
1598 {"$s2", RTYPE_GP | 18}, \
1599 {"$s3", RTYPE_GP | 19}, \
1600 {"$s4", RTYPE_GP | 20}, \
1601 {"$s5", RTYPE_GP | 21}, \
1602 {"$s6", RTYPE_GP | 22}, \
1603 {"$s7", RTYPE_GP | 23}, \
1604 {"$t8", RTYPE_GP | 24}, \
1605 {"$t9", RTYPE_GP | 25}, \
1606 {"$k0", RTYPE_GP | 26}, \
1607 {"$kt0", RTYPE_GP | 26}, \
1608 {"$k1", RTYPE_GP | 27}, \
1609 {"$kt1", RTYPE_GP | 27}, \
1610 {"$gp", RTYPE_GP | 28}, \
1611 {"$sp", RTYPE_GP | 29}, \
1612 {"$s8", RTYPE_GP | 30}, \
1613 {"$fp", RTYPE_GP | 30}, \
1614 {"$ra", RTYPE_GP | 31}
1615
1616 #define MIPS16_SPECIAL_REGISTER_NAMES \
1617 {"$pc", RTYPE_PC | 0}
1618
1619 #define MDMX_VECTOR_REGISTER_NAMES \
1620 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1621 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1622 {"$v2", RTYPE_VEC | 2}, \
1623 {"$v3", RTYPE_VEC | 3}, \
1624 {"$v4", RTYPE_VEC | 4}, \
1625 {"$v5", RTYPE_VEC | 5}, \
1626 {"$v6", RTYPE_VEC | 6}, \
1627 {"$v7", RTYPE_VEC | 7}, \
1628 {"$v8", RTYPE_VEC | 8}, \
1629 {"$v9", RTYPE_VEC | 9}, \
1630 {"$v10", RTYPE_VEC | 10}, \
1631 {"$v11", RTYPE_VEC | 11}, \
1632 {"$v12", RTYPE_VEC | 12}, \
1633 {"$v13", RTYPE_VEC | 13}, \
1634 {"$v14", RTYPE_VEC | 14}, \
1635 {"$v15", RTYPE_VEC | 15}, \
1636 {"$v16", RTYPE_VEC | 16}, \
1637 {"$v17", RTYPE_VEC | 17}, \
1638 {"$v18", RTYPE_VEC | 18}, \
1639 {"$v19", RTYPE_VEC | 19}, \
1640 {"$v20", RTYPE_VEC | 20}, \
1641 {"$v21", RTYPE_VEC | 21}, \
1642 {"$v22", RTYPE_VEC | 22}, \
1643 {"$v23", RTYPE_VEC | 23}, \
1644 {"$v24", RTYPE_VEC | 24}, \
1645 {"$v25", RTYPE_VEC | 25}, \
1646 {"$v26", RTYPE_VEC | 26}, \
1647 {"$v27", RTYPE_VEC | 27}, \
1648 {"$v28", RTYPE_VEC | 28}, \
1649 {"$v29", RTYPE_VEC | 29}, \
1650 {"$v30", RTYPE_VEC | 30}, \
1651 {"$v31", RTYPE_VEC | 31}
1652
1653 #define MIPS_DSP_ACCUMULATOR_NAMES \
1654 {"$ac0", RTYPE_ACC | 0}, \
1655 {"$ac1", RTYPE_ACC | 1}, \
1656 {"$ac2", RTYPE_ACC | 2}, \
1657 {"$ac3", RTYPE_ACC | 3}
1658
1659 static const struct regname reg_names[] = {
1660 GENERIC_REGISTER_NUMBERS,
1661 FPU_REGISTER_NAMES,
1662 FPU_CONDITION_CODE_NAMES,
1663 COPROC_CONDITION_CODE_NAMES,
1664
1665 /* The $txx registers depends on the abi,
1666 these will be added later into the symbol table from
1667 one of the tables below once mips_abi is set after
1668 parsing of arguments from the command line. */
1669 SYMBOLIC_REGISTER_NAMES,
1670
1671 MIPS16_SPECIAL_REGISTER_NAMES,
1672 MDMX_VECTOR_REGISTER_NAMES,
1673 MIPS_DSP_ACCUMULATOR_NAMES,
1674 {0, 0}
1675 };
1676
1677 static const struct regname reg_names_o32[] = {
1678 O32_SYMBOLIC_REGISTER_NAMES,
1679 {0, 0}
1680 };
1681
1682 static const struct regname reg_names_n32n64[] = {
1683 N32N64_SYMBOLIC_REGISTER_NAMES,
1684 {0, 0}
1685 };
1686
1687 static int
1688 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1689 {
1690 symbolS *symbolP;
1691 char *e;
1692 char save_c;
1693 int reg = -1;
1694
1695 /* Find end of name. */
1696 e = *s;
1697 if (is_name_beginner (*e))
1698 ++e;
1699 while (is_part_of_name (*e))
1700 ++e;
1701
1702 /* Terminate name. */
1703 save_c = *e;
1704 *e = '\0';
1705
1706 /* Look for a register symbol. */
1707 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1708 {
1709 int r = S_GET_VALUE (symbolP);
1710 if (r & types)
1711 reg = r & RNUM_MASK;
1712 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1713 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1714 reg = (r & RNUM_MASK) - 2;
1715 }
1716 /* Else see if this is a register defined in an itbl entry. */
1717 else if ((types & RTYPE_GP) && itbl_have_entries)
1718 {
1719 char *n = *s;
1720 unsigned long r;
1721
1722 if (*n == '$')
1723 ++n;
1724 if (itbl_get_reg_val (n, &r))
1725 reg = r & RNUM_MASK;
1726 }
1727
1728 /* Advance to next token if a register was recognised. */
1729 if (reg >= 0)
1730 *s = e;
1731 else if (types & RWARN)
1732 as_warn ("Unrecognized register name `%s'", *s);
1733
1734 *e = save_c;
1735 if (regnop)
1736 *regnop = reg;
1737 return reg >= 0;
1738 }
1739
1740 /* This function is called once, at assembler startup time. It should set up
1741 all the tables, etc. that the MD part of the assembler will need. */
1742
1743 void
1744 md_begin (void)
1745 {
1746 const char *retval = NULL;
1747 int i = 0;
1748 int broken = 0;
1749
1750 if (mips_pic != NO_PIC)
1751 {
1752 if (g_switch_seen && g_switch_value != 0)
1753 as_bad (_("-G may not be used in position-independent code"));
1754 g_switch_value = 0;
1755 }
1756
1757 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1758 as_warn (_("Could not set architecture and machine"));
1759
1760 op_hash = hash_new ();
1761
1762 for (i = 0; i < NUMOPCODES;)
1763 {
1764 const char *name = mips_opcodes[i].name;
1765
1766 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1767 if (retval != NULL)
1768 {
1769 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1770 mips_opcodes[i].name, retval);
1771 /* Probably a memory allocation problem? Give up now. */
1772 as_fatal (_("Broken assembler. No assembly attempted."));
1773 }
1774 do
1775 {
1776 if (mips_opcodes[i].pinfo != INSN_MACRO)
1777 {
1778 if (!validate_mips_insn (&mips_opcodes[i]))
1779 broken = 1;
1780 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1781 {
1782 create_insn (&nop_insn, mips_opcodes + i);
1783 nop_insn.fixed_p = 1;
1784 }
1785 }
1786 ++i;
1787 }
1788 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1789 }
1790
1791 mips16_op_hash = hash_new ();
1792
1793 i = 0;
1794 while (i < bfd_mips16_num_opcodes)
1795 {
1796 const char *name = mips16_opcodes[i].name;
1797
1798 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1799 if (retval != NULL)
1800 as_fatal (_("internal: can't hash `%s': %s"),
1801 mips16_opcodes[i].name, retval);
1802 do
1803 {
1804 if (mips16_opcodes[i].pinfo != INSN_MACRO
1805 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1806 != mips16_opcodes[i].match))
1807 {
1808 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1809 mips16_opcodes[i].name, mips16_opcodes[i].args);
1810 broken = 1;
1811 }
1812 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1813 {
1814 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1815 mips16_nop_insn.fixed_p = 1;
1816 }
1817 ++i;
1818 }
1819 while (i < bfd_mips16_num_opcodes
1820 && strcmp (mips16_opcodes[i].name, name) == 0);
1821 }
1822
1823 if (broken)
1824 as_fatal (_("Broken assembler. No assembly attempted."));
1825
1826 /* We add all the general register names to the symbol table. This
1827 helps us detect invalid uses of them. */
1828 for (i = 0; reg_names[i].name; i++)
1829 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1830 reg_names[i].num, // & RNUM_MASK,
1831 &zero_address_frag));
1832 if (HAVE_NEWABI)
1833 for (i = 0; reg_names_n32n64[i].name; i++)
1834 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1835 reg_names_n32n64[i].num, // & RNUM_MASK,
1836 &zero_address_frag));
1837 else
1838 for (i = 0; reg_names_o32[i].name; i++)
1839 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1840 reg_names_o32[i].num, // & RNUM_MASK,
1841 &zero_address_frag));
1842
1843 mips_no_prev_insn ();
1844
1845 mips_gprmask = 0;
1846 mips_cprmask[0] = 0;
1847 mips_cprmask[1] = 0;
1848 mips_cprmask[2] = 0;
1849 mips_cprmask[3] = 0;
1850
1851 /* set the default alignment for the text section (2**2) */
1852 record_alignment (text_section, 2);
1853
1854 bfd_set_gp_size (stdoutput, g_switch_value);
1855
1856 #ifdef OBJ_ELF
1857 if (IS_ELF)
1858 {
1859 /* On a native system other than VxWorks, sections must be aligned
1860 to 16 byte boundaries. When configured for an embedded ELF
1861 target, we don't bother. */
1862 if (strcmp (TARGET_OS, "elf") != 0
1863 && strcmp (TARGET_OS, "vxworks") != 0)
1864 {
1865 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1866 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1867 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1868 }
1869
1870 /* Create a .reginfo section for register masks and a .mdebug
1871 section for debugging information. */
1872 {
1873 segT seg;
1874 subsegT subseg;
1875 flagword flags;
1876 segT sec;
1877
1878 seg = now_seg;
1879 subseg = now_subseg;
1880
1881 /* The ABI says this section should be loaded so that the
1882 running program can access it. However, we don't load it
1883 if we are configured for an embedded target */
1884 flags = SEC_READONLY | SEC_DATA;
1885 if (strcmp (TARGET_OS, "elf") != 0)
1886 flags |= SEC_ALLOC | SEC_LOAD;
1887
1888 if (mips_abi != N64_ABI)
1889 {
1890 sec = subseg_new (".reginfo", (subsegT) 0);
1891
1892 bfd_set_section_flags (stdoutput, sec, flags);
1893 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1894
1895 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1896 }
1897 else
1898 {
1899 /* The 64-bit ABI uses a .MIPS.options section rather than
1900 .reginfo section. */
1901 sec = subseg_new (".MIPS.options", (subsegT) 0);
1902 bfd_set_section_flags (stdoutput, sec, flags);
1903 bfd_set_section_alignment (stdoutput, sec, 3);
1904
1905 /* Set up the option header. */
1906 {
1907 Elf_Internal_Options opthdr;
1908 char *f;
1909
1910 opthdr.kind = ODK_REGINFO;
1911 opthdr.size = (sizeof (Elf_External_Options)
1912 + sizeof (Elf64_External_RegInfo));
1913 opthdr.section = 0;
1914 opthdr.info = 0;
1915 f = frag_more (sizeof (Elf_External_Options));
1916 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1917 (Elf_External_Options *) f);
1918
1919 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1920 }
1921 }
1922
1923 if (ECOFF_DEBUGGING)
1924 {
1925 sec = subseg_new (".mdebug", (subsegT) 0);
1926 (void) bfd_set_section_flags (stdoutput, sec,
1927 SEC_HAS_CONTENTS | SEC_READONLY);
1928 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1929 }
1930 else if (mips_flag_pdr)
1931 {
1932 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1933 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1934 SEC_READONLY | SEC_RELOC
1935 | SEC_DEBUGGING);
1936 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1937 }
1938
1939 subseg_set (seg, subseg);
1940 }
1941 }
1942 #endif /* OBJ_ELF */
1943
1944 if (! ECOFF_DEBUGGING)
1945 md_obj_begin ();
1946
1947 if (mips_fix_vr4120)
1948 init_vr4120_conflicts ();
1949 }
1950
1951 void
1952 md_mips_end (void)
1953 {
1954 if (! ECOFF_DEBUGGING)
1955 md_obj_end ();
1956 }
1957
1958 void
1959 md_assemble (char *str)
1960 {
1961 struct mips_cl_insn insn;
1962 bfd_reloc_code_real_type unused_reloc[3]
1963 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1964
1965 imm_expr.X_op = O_absent;
1966 imm2_expr.X_op = O_absent;
1967 offset_expr.X_op = O_absent;
1968 imm_reloc[0] = BFD_RELOC_UNUSED;
1969 imm_reloc[1] = BFD_RELOC_UNUSED;
1970 imm_reloc[2] = BFD_RELOC_UNUSED;
1971 offset_reloc[0] = BFD_RELOC_UNUSED;
1972 offset_reloc[1] = BFD_RELOC_UNUSED;
1973 offset_reloc[2] = BFD_RELOC_UNUSED;
1974
1975 if (mips_opts.mips16)
1976 mips16_ip (str, &insn);
1977 else
1978 {
1979 mips_ip (str, &insn);
1980 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1981 str, insn.insn_opcode));
1982 }
1983
1984 if (insn_error)
1985 {
1986 as_bad ("%s `%s'", insn_error, str);
1987 return;
1988 }
1989
1990 if (insn.insn_mo->pinfo == INSN_MACRO)
1991 {
1992 macro_start ();
1993 if (mips_opts.mips16)
1994 mips16_macro (&insn);
1995 else
1996 macro (&insn);
1997 macro_end ();
1998 }
1999 else
2000 {
2001 if (imm_expr.X_op != O_absent)
2002 append_insn (&insn, &imm_expr, imm_reloc);
2003 else if (offset_expr.X_op != O_absent)
2004 append_insn (&insn, &offset_expr, offset_reloc);
2005 else
2006 append_insn (&insn, NULL, unused_reloc);
2007 }
2008 }
2009
2010 /* Return true if the given relocation might need a matching %lo().
2011 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2012 need a matching %lo() when applied to local symbols. */
2013
2014 static inline bfd_boolean
2015 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2016 {
2017 return (HAVE_IN_PLACE_ADDENDS
2018 && (reloc == BFD_RELOC_HI16_S
2019 || reloc == BFD_RELOC_MIPS16_HI16_S
2020 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2021 all GOT16 relocations evaluate to "G". */
2022 || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC)));
2023 }
2024
2025 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2026 relocation. */
2027
2028 static inline bfd_boolean
2029 fixup_has_matching_lo_p (fixS *fixp)
2030 {
2031 return (fixp->fx_next != NULL
2032 && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
2033 || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
2034 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2035 && fixp->fx_offset == fixp->fx_next->fx_offset);
2036 }
2037
2038 /* See whether instruction IP reads register REG. CLASS is the type
2039 of register. */
2040
2041 static int
2042 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2043 enum mips_regclass class)
2044 {
2045 if (class == MIPS16_REG)
2046 {
2047 assert (mips_opts.mips16);
2048 reg = mips16_to_32_reg_map[reg];
2049 class = MIPS_GR_REG;
2050 }
2051
2052 /* Don't report on general register ZERO, since it never changes. */
2053 if (class == MIPS_GR_REG && reg == ZERO)
2054 return 0;
2055
2056 if (class == MIPS_FP_REG)
2057 {
2058 assert (! mips_opts.mips16);
2059 /* If we are called with either $f0 or $f1, we must check $f0.
2060 This is not optimal, because it will introduce an unnecessary
2061 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2062 need to distinguish reading both $f0 and $f1 or just one of
2063 them. Note that we don't have to check the other way,
2064 because there is no instruction that sets both $f0 and $f1
2065 and requires a delay. */
2066 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2067 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2068 == (reg &~ (unsigned) 1)))
2069 return 1;
2070 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2071 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2072 == (reg &~ (unsigned) 1)))
2073 return 1;
2074 }
2075 else if (! mips_opts.mips16)
2076 {
2077 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2078 && EXTRACT_OPERAND (RS, *ip) == reg)
2079 return 1;
2080 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2081 && EXTRACT_OPERAND (RT, *ip) == reg)
2082 return 1;
2083 }
2084 else
2085 {
2086 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2087 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2088 return 1;
2089 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2090 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2091 return 1;
2092 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2093 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2094 == reg))
2095 return 1;
2096 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2097 return 1;
2098 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2099 return 1;
2100 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2101 return 1;
2102 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2103 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2104 return 1;
2105 }
2106
2107 return 0;
2108 }
2109
2110 /* This function returns true if modifying a register requires a
2111 delay. */
2112
2113 static int
2114 reg_needs_delay (unsigned int reg)
2115 {
2116 unsigned long prev_pinfo;
2117
2118 prev_pinfo = history[0].insn_mo->pinfo;
2119 if (! mips_opts.noreorder
2120 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2121 && ! gpr_interlocks)
2122 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2123 && ! cop_interlocks)))
2124 {
2125 /* A load from a coprocessor or from memory. All load delays
2126 delay the use of general register rt for one instruction. */
2127 /* Itbl support may require additional care here. */
2128 know (prev_pinfo & INSN_WRITE_GPR_T);
2129 if (reg == EXTRACT_OPERAND (RT, history[0]))
2130 return 1;
2131 }
2132
2133 return 0;
2134 }
2135
2136 /* Move all labels in insn_labels to the current insertion point. */
2137
2138 static void
2139 mips_move_labels (void)
2140 {
2141 segment_info_type *si = seg_info (now_seg);
2142 struct insn_label_list *l;
2143 valueT val;
2144
2145 for (l = si->label_list; l != NULL; l = l->next)
2146 {
2147 assert (S_GET_SEGMENT (l->label) == now_seg);
2148 symbol_set_frag (l->label, frag_now);
2149 val = (valueT) frag_now_fix ();
2150 /* mips16 text labels are stored as odd. */
2151 if (mips_opts.mips16)
2152 ++val;
2153 S_SET_VALUE (l->label, val);
2154 }
2155 }
2156
2157 static bfd_boolean
2158 s_is_linkonce (symbolS *sym, segT from_seg)
2159 {
2160 bfd_boolean linkonce = FALSE;
2161 segT symseg = S_GET_SEGMENT (sym);
2162
2163 if (symseg != from_seg && !S_IS_LOCAL (sym))
2164 {
2165 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2166 linkonce = TRUE;
2167 #ifdef OBJ_ELF
2168 /* The GNU toolchain uses an extension for ELF: a section
2169 beginning with the magic string .gnu.linkonce is a
2170 linkonce section. */
2171 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2172 sizeof ".gnu.linkonce" - 1) == 0)
2173 linkonce = TRUE;
2174 #endif
2175 }
2176 return linkonce;
2177 }
2178
2179 /* Mark instruction labels in mips16 mode. This permits the linker to
2180 handle them specially, such as generating jalx instructions when
2181 needed. We also make them odd for the duration of the assembly, in
2182 order to generate the right sort of code. We will make them even
2183 in the adjust_symtab routine, while leaving them marked. This is
2184 convenient for the debugger and the disassembler. The linker knows
2185 to make them odd again. */
2186
2187 static void
2188 mips16_mark_labels (void)
2189 {
2190 segment_info_type *si = seg_info (now_seg);
2191 struct insn_label_list *l;
2192
2193 if (!mips_opts.mips16)
2194 return;
2195
2196 for (l = si->label_list; l != NULL; l = l->next)
2197 {
2198 symbolS *label = l->label;
2199
2200 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2201 if (IS_ELF)
2202 S_SET_OTHER (label, STO_MIPS16);
2203 #endif
2204 if ((S_GET_VALUE (label) & 1) == 0
2205 /* Don't adjust the address if the label is global or weak, or
2206 in a link-once section, since we'll be emitting symbol reloc
2207 references to it which will be patched up by the linker, and
2208 the final value of the symbol may or may not be MIPS16. */
2209 && ! S_IS_WEAK (label)
2210 && ! S_IS_EXTERNAL (label)
2211 && ! s_is_linkonce (label, now_seg))
2212 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2213 }
2214 }
2215
2216 /* End the current frag. Make it a variant frag and record the
2217 relaxation info. */
2218
2219 static void
2220 relax_close_frag (void)
2221 {
2222 mips_macro_warning.first_frag = frag_now;
2223 frag_var (rs_machine_dependent, 0, 0,
2224 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2225 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2226
2227 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2228 mips_relax.first_fixup = 0;
2229 }
2230
2231 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2232 See the comment above RELAX_ENCODE for more details. */
2233
2234 static void
2235 relax_start (symbolS *symbol)
2236 {
2237 assert (mips_relax.sequence == 0);
2238 mips_relax.sequence = 1;
2239 mips_relax.symbol = symbol;
2240 }
2241
2242 /* Start generating the second version of a relaxable sequence.
2243 See the comment above RELAX_ENCODE for more details. */
2244
2245 static void
2246 relax_switch (void)
2247 {
2248 assert (mips_relax.sequence == 1);
2249 mips_relax.sequence = 2;
2250 }
2251
2252 /* End the current relaxable sequence. */
2253
2254 static void
2255 relax_end (void)
2256 {
2257 assert (mips_relax.sequence == 2);
2258 relax_close_frag ();
2259 mips_relax.sequence = 0;
2260 }
2261
2262 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2263 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2264 by VR4120 errata. */
2265
2266 static unsigned int
2267 classify_vr4120_insn (const char *name)
2268 {
2269 if (strncmp (name, "macc", 4) == 0)
2270 return FIX_VR4120_MACC;
2271 if (strncmp (name, "dmacc", 5) == 0)
2272 return FIX_VR4120_DMACC;
2273 if (strncmp (name, "mult", 4) == 0)
2274 return FIX_VR4120_MULT;
2275 if (strncmp (name, "dmult", 5) == 0)
2276 return FIX_VR4120_DMULT;
2277 if (strstr (name, "div"))
2278 return FIX_VR4120_DIV;
2279 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2280 return FIX_VR4120_MTHILO;
2281 return NUM_FIX_VR4120_CLASSES;
2282 }
2283
2284 /* Return the number of instructions that must separate INSN1 and INSN2,
2285 where INSN1 is the earlier instruction. Return the worst-case value
2286 for any INSN2 if INSN2 is null. */
2287
2288 static unsigned int
2289 insns_between (const struct mips_cl_insn *insn1,
2290 const struct mips_cl_insn *insn2)
2291 {
2292 unsigned long pinfo1, pinfo2;
2293
2294 /* This function needs to know which pinfo flags are set for INSN2
2295 and which registers INSN2 uses. The former is stored in PINFO2 and
2296 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2297 will have every flag set and INSN2_USES_REG will always return true. */
2298 pinfo1 = insn1->insn_mo->pinfo;
2299 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2300
2301 #define INSN2_USES_REG(REG, CLASS) \
2302 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2303
2304 /* For most targets, write-after-read dependencies on the HI and LO
2305 registers must be separated by at least two instructions. */
2306 if (!hilo_interlocks)
2307 {
2308 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2309 return 2;
2310 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2311 return 2;
2312 }
2313
2314 /* If we're working around r7000 errata, there must be two instructions
2315 between an mfhi or mflo and any instruction that uses the result. */
2316 if (mips_7000_hilo_fix
2317 && MF_HILO_INSN (pinfo1)
2318 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2319 return 2;
2320
2321 /* If working around VR4120 errata, check for combinations that need
2322 a single intervening instruction. */
2323 if (mips_fix_vr4120)
2324 {
2325 unsigned int class1, class2;
2326
2327 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2328 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2329 {
2330 if (insn2 == NULL)
2331 return 1;
2332 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2333 if (vr4120_conflicts[class1] & (1 << class2))
2334 return 1;
2335 }
2336 }
2337
2338 if (!mips_opts.mips16)
2339 {
2340 /* Check for GPR or coprocessor load delays. All such delays
2341 are on the RT register. */
2342 /* Itbl support may require additional care here. */
2343 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2344 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2345 {
2346 know (pinfo1 & INSN_WRITE_GPR_T);
2347 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2348 return 1;
2349 }
2350
2351 /* Check for generic coprocessor hazards.
2352
2353 This case is not handled very well. There is no special
2354 knowledge of CP0 handling, and the coprocessors other than
2355 the floating point unit are not distinguished at all. */
2356 /* Itbl support may require additional care here. FIXME!
2357 Need to modify this to include knowledge about
2358 user specified delays! */
2359 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2360 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2361 {
2362 /* Handle cases where INSN1 writes to a known general coprocessor
2363 register. There must be a one instruction delay before INSN2
2364 if INSN2 reads that register, otherwise no delay is needed. */
2365 if (pinfo1 & INSN_WRITE_FPR_T)
2366 {
2367 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2368 return 1;
2369 }
2370 else if (pinfo1 & INSN_WRITE_FPR_S)
2371 {
2372 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2373 return 1;
2374 }
2375 else
2376 {
2377 /* Read-after-write dependencies on the control registers
2378 require a two-instruction gap. */
2379 if ((pinfo1 & INSN_WRITE_COND_CODE)
2380 && (pinfo2 & INSN_READ_COND_CODE))
2381 return 2;
2382
2383 /* We don't know exactly what INSN1 does. If INSN2 is
2384 also a coprocessor instruction, assume there must be
2385 a one instruction gap. */
2386 if (pinfo2 & INSN_COP)
2387 return 1;
2388 }
2389 }
2390
2391 /* Check for read-after-write dependencies on the coprocessor
2392 control registers in cases where INSN1 does not need a general
2393 coprocessor delay. This means that INSN1 is a floating point
2394 comparison instruction. */
2395 /* Itbl support may require additional care here. */
2396 else if (!cop_interlocks
2397 && (pinfo1 & INSN_WRITE_COND_CODE)
2398 && (pinfo2 & INSN_READ_COND_CODE))
2399 return 1;
2400 }
2401
2402 #undef INSN2_USES_REG
2403
2404 return 0;
2405 }
2406
2407 /* Return the number of nops that would be needed to work around the
2408 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2409 the MAX_VR4130_NOPS instructions described by HISTORY. */
2410
2411 static int
2412 nops_for_vr4130 (const struct mips_cl_insn *history,
2413 const struct mips_cl_insn *insn)
2414 {
2415 int i, j, reg;
2416
2417 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2418 are not affected by the errata. */
2419 if (insn != 0
2420 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2421 || strcmp (insn->insn_mo->name, "mtlo") == 0
2422 || strcmp (insn->insn_mo->name, "mthi") == 0))
2423 return 0;
2424
2425 /* Search for the first MFLO or MFHI. */
2426 for (i = 0; i < MAX_VR4130_NOPS; i++)
2427 if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
2428 {
2429 /* Extract the destination register. */
2430 if (mips_opts.mips16)
2431 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
2432 else
2433 reg = EXTRACT_OPERAND (RD, history[i]);
2434
2435 /* No nops are needed if INSN reads that register. */
2436 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2437 return 0;
2438
2439 /* ...or if any of the intervening instructions do. */
2440 for (j = 0; j < i; j++)
2441 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
2442 return 0;
2443
2444 return MAX_VR4130_NOPS - i;
2445 }
2446 return 0;
2447 }
2448
2449 /* Return the number of nops that would be needed if instruction INSN
2450 immediately followed the MAX_NOPS instructions given by HISTORY,
2451 where HISTORY[0] is the most recent instruction. If INSN is null,
2452 return the worse-case number of nops for any instruction. */
2453
2454 static int
2455 nops_for_insn (const struct mips_cl_insn *history,
2456 const struct mips_cl_insn *insn)
2457 {
2458 int i, nops, tmp_nops;
2459
2460 nops = 0;
2461 for (i = 0; i < MAX_DELAY_NOPS; i++)
2462 if (!history[i].noreorder_p)
2463 {
2464 tmp_nops = insns_between (history + i, insn) - i;
2465 if (tmp_nops > nops)
2466 nops = tmp_nops;
2467 }
2468
2469 if (mips_fix_vr4130)
2470 {
2471 tmp_nops = nops_for_vr4130 (history, insn);
2472 if (tmp_nops > nops)
2473 nops = tmp_nops;
2474 }
2475
2476 return nops;
2477 }
2478
2479 /* The variable arguments provide NUM_INSNS extra instructions that
2480 might be added to HISTORY. Return the largest number of nops that
2481 would be needed after the extended sequence. */
2482
2483 static int
2484 nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
2485 {
2486 va_list args;
2487 struct mips_cl_insn buffer[MAX_NOPS];
2488 struct mips_cl_insn *cursor;
2489 int nops;
2490
2491 va_start (args, history);
2492 cursor = buffer + num_insns;
2493 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
2494 while (cursor > buffer)
2495 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2496
2497 nops = nops_for_insn (buffer, NULL);
2498 va_end (args);
2499 return nops;
2500 }
2501
2502 /* Like nops_for_insn, but if INSN is a branch, take into account the
2503 worst-case delay for the branch target. */
2504
2505 static int
2506 nops_for_insn_or_target (const struct mips_cl_insn *history,
2507 const struct mips_cl_insn *insn)
2508 {
2509 int nops, tmp_nops;
2510
2511 nops = nops_for_insn (history, insn);
2512 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2513 | INSN_COND_BRANCH_DELAY
2514 | INSN_COND_BRANCH_LIKELY))
2515 {
2516 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
2517 if (tmp_nops > nops)
2518 nops = tmp_nops;
2519 }
2520 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2521 {
2522 tmp_nops = nops_for_sequence (1, history, insn);
2523 if (tmp_nops > nops)
2524 nops = tmp_nops;
2525 }
2526 return nops;
2527 }
2528
2529 /* Output an instruction. IP is the instruction information.
2530 ADDRESS_EXPR is an operand of the instruction to be used with
2531 RELOC_TYPE. */
2532
2533 static void
2534 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2535 bfd_reloc_code_real_type *reloc_type)
2536 {
2537 unsigned long prev_pinfo, pinfo;
2538 relax_stateT prev_insn_frag_type = 0;
2539 bfd_boolean relaxed_branch = FALSE;
2540 segment_info_type *si = seg_info (now_seg);
2541
2542 /* Mark instruction labels in mips16 mode. */
2543 mips16_mark_labels ();
2544
2545 prev_pinfo = history[0].insn_mo->pinfo;
2546 pinfo = ip->insn_mo->pinfo;
2547
2548 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2549 {
2550 /* There are a lot of optimizations we could do that we don't.
2551 In particular, we do not, in general, reorder instructions.
2552 If you use gcc with optimization, it will reorder
2553 instructions and generally do much more optimization then we
2554 do here; repeating all that work in the assembler would only
2555 benefit hand written assembly code, and does not seem worth
2556 it. */
2557 int nops = (mips_optimize == 0
2558 ? nops_for_insn (history, NULL)
2559 : nops_for_insn_or_target (history, ip));
2560 if (nops > 0)
2561 {
2562 fragS *old_frag;
2563 unsigned long old_frag_offset;
2564 int i;
2565
2566 old_frag = frag_now;
2567 old_frag_offset = frag_now_fix ();
2568
2569 for (i = 0; i < nops; i++)
2570 emit_nop ();
2571
2572 if (listing)
2573 {
2574 listing_prev_line ();
2575 /* We may be at the start of a variant frag. In case we
2576 are, make sure there is enough space for the frag
2577 after the frags created by listing_prev_line. The
2578 argument to frag_grow here must be at least as large
2579 as the argument to all other calls to frag_grow in
2580 this file. We don't have to worry about being in the
2581 middle of a variant frag, because the variants insert
2582 all needed nop instructions themselves. */
2583 frag_grow (40);
2584 }
2585
2586 mips_move_labels ();
2587
2588 #ifndef NO_ECOFF_DEBUGGING
2589 if (ECOFF_DEBUGGING)
2590 ecoff_fix_loc (old_frag, old_frag_offset);
2591 #endif
2592 }
2593 }
2594 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2595 {
2596 /* Work out how many nops in prev_nop_frag are needed by IP. */
2597 int nops = nops_for_insn_or_target (history, ip);
2598 assert (nops <= prev_nop_frag_holds);
2599
2600 /* Enforce NOPS as a minimum. */
2601 if (nops > prev_nop_frag_required)
2602 prev_nop_frag_required = nops;
2603
2604 if (prev_nop_frag_holds == prev_nop_frag_required)
2605 {
2606 /* Settle for the current number of nops. Update the history
2607 accordingly (for the benefit of any future .set reorder code). */
2608 prev_nop_frag = NULL;
2609 insert_into_history (prev_nop_frag_since,
2610 prev_nop_frag_holds, NOP_INSN);
2611 }
2612 else
2613 {
2614 /* Allow this instruction to replace one of the nops that was
2615 tentatively added to prev_nop_frag. */
2616 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2617 prev_nop_frag_holds--;
2618 prev_nop_frag_since++;
2619 }
2620 }
2621
2622 #ifdef OBJ_ELF
2623 /* The value passed to dwarf2_emit_insn is the distance between
2624 the beginning of the current instruction and the address that
2625 should be recorded in the debug tables. For MIPS16 debug info
2626 we want to use ISA-encoded addresses, so we pass -1 for an
2627 address higher by one than the current. */
2628 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2629 #endif
2630
2631 /* Record the frag type before frag_var. */
2632 if (history[0].frag)
2633 prev_insn_frag_type = history[0].frag->fr_type;
2634
2635 if (address_expr
2636 && *reloc_type == BFD_RELOC_16_PCREL_S2
2637 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2638 || pinfo & INSN_COND_BRANCH_LIKELY)
2639 && mips_relax_branch
2640 /* Don't try branch relaxation within .set nomacro, or within
2641 .set noat if we use $at for PIC computations. If it turns
2642 out that the branch was out-of-range, we'll get an error. */
2643 && !mips_opts.warn_about_macros
2644 && (mips_opts.at || mips_pic == NO_PIC)
2645 && !mips_opts.mips16)
2646 {
2647 relaxed_branch = TRUE;
2648 add_relaxed_insn (ip, (relaxed_branch_length
2649 (NULL, NULL,
2650 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2651 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2652 : 0)), 4,
2653 RELAX_BRANCH_ENCODE
2654 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2655 pinfo & INSN_COND_BRANCH_LIKELY,
2656 pinfo & INSN_WRITE_GPR_31,
2657 0),
2658 address_expr->X_add_symbol,
2659 address_expr->X_add_number);
2660 *reloc_type = BFD_RELOC_UNUSED;
2661 }
2662 else if (*reloc_type > BFD_RELOC_UNUSED)
2663 {
2664 /* We need to set up a variant frag. */
2665 assert (mips_opts.mips16 && address_expr != NULL);
2666 add_relaxed_insn (ip, 4, 0,
2667 RELAX_MIPS16_ENCODE
2668 (*reloc_type - BFD_RELOC_UNUSED,
2669 mips16_small, mips16_ext,
2670 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2671 history[0].mips16_absolute_jump_p),
2672 make_expr_symbol (address_expr), 0);
2673 }
2674 else if (mips_opts.mips16
2675 && ! ip->use_extend
2676 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2677 {
2678 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2679 /* Make sure there is enough room to swap this instruction with
2680 a following jump instruction. */
2681 frag_grow (6);
2682 add_fixed_insn (ip);
2683 }
2684 else
2685 {
2686 if (mips_opts.mips16
2687 && mips_opts.noreorder
2688 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2689 as_warn (_("extended instruction in delay slot"));
2690
2691 if (mips_relax.sequence)
2692 {
2693 /* If we've reached the end of this frag, turn it into a variant
2694 frag and record the information for the instructions we've
2695 written so far. */
2696 if (frag_room () < 4)
2697 relax_close_frag ();
2698 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2699 }
2700
2701 if (mips_relax.sequence != 2)
2702 mips_macro_warning.sizes[0] += 4;
2703 if (mips_relax.sequence != 1)
2704 mips_macro_warning.sizes[1] += 4;
2705
2706 if (mips_opts.mips16)
2707 {
2708 ip->fixed_p = 1;
2709 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2710 }
2711 add_fixed_insn (ip);
2712 }
2713
2714 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2715 {
2716 if (address_expr->X_op == O_constant)
2717 {
2718 unsigned int tmp;
2719
2720 switch (*reloc_type)
2721 {
2722 case BFD_RELOC_32:
2723 ip->insn_opcode |= address_expr->X_add_number;
2724 break;
2725
2726 case BFD_RELOC_MIPS_HIGHEST:
2727 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2728 ip->insn_opcode |= tmp & 0xffff;
2729 break;
2730
2731 case BFD_RELOC_MIPS_HIGHER:
2732 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2733 ip->insn_opcode |= tmp & 0xffff;
2734 break;
2735
2736 case BFD_RELOC_HI16_S:
2737 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2738 ip->insn_opcode |= tmp & 0xffff;
2739 break;
2740
2741 case BFD_RELOC_HI16:
2742 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2743 break;
2744
2745 case BFD_RELOC_UNUSED:
2746 case BFD_RELOC_LO16:
2747 case BFD_RELOC_MIPS_GOT_DISP:
2748 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2749 break;
2750
2751 case BFD_RELOC_MIPS_JMP:
2752 if ((address_expr->X_add_number & 3) != 0)
2753 as_bad (_("jump to misaligned address (0x%lx)"),
2754 (unsigned long) address_expr->X_add_number);
2755 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2756 break;
2757
2758 case BFD_RELOC_MIPS16_JMP:
2759 if ((address_expr->X_add_number & 3) != 0)
2760 as_bad (_("jump to misaligned address (0x%lx)"),
2761 (unsigned long) address_expr->X_add_number);
2762 ip->insn_opcode |=
2763 (((address_expr->X_add_number & 0x7c0000) << 3)
2764 | ((address_expr->X_add_number & 0xf800000) >> 7)
2765 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2766 break;
2767
2768 case BFD_RELOC_16_PCREL_S2:
2769 if ((address_expr->X_add_number & 3) != 0)
2770 as_bad (_("branch to misaligned address (0x%lx)"),
2771 (unsigned long) address_expr->X_add_number);
2772 if (mips_relax_branch)
2773 goto need_reloc;
2774 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
2775 as_bad (_("branch address range overflow (0x%lx)"),
2776 (unsigned long) address_expr->X_add_number);
2777 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
2778 break;
2779
2780 default:
2781 internalError ();
2782 }
2783 }
2784 else if (*reloc_type < BFD_RELOC_UNUSED)
2785 need_reloc:
2786 {
2787 reloc_howto_type *howto;
2788 int i;
2789
2790 /* In a compound relocation, it is the final (outermost)
2791 operator that determines the relocated field. */
2792 for (i = 1; i < 3; i++)
2793 if (reloc_type[i] == BFD_RELOC_UNUSED)
2794 break;
2795
2796 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2797 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
2798 bfd_get_reloc_size (howto),
2799 address_expr,
2800 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2801 reloc_type[0]);
2802
2803 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2804 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
2805 && ip->fixp[0]->fx_addsy)
2806 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
2807
2808 /* These relocations can have an addend that won't fit in
2809 4 octets for 64bit assembly. */
2810 if (HAVE_64BIT_GPRS
2811 && ! howto->partial_inplace
2812 && (reloc_type[0] == BFD_RELOC_16
2813 || reloc_type[0] == BFD_RELOC_32
2814 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2815 || reloc_type[0] == BFD_RELOC_HI16_S
2816 || reloc_type[0] == BFD_RELOC_LO16
2817 || reloc_type[0] == BFD_RELOC_GPREL16
2818 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2819 || reloc_type[0] == BFD_RELOC_GPREL32
2820 || reloc_type[0] == BFD_RELOC_64
2821 || reloc_type[0] == BFD_RELOC_CTOR
2822 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2823 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2824 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2825 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2826 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2827 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
2828 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
2829 || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
2830 || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
2831 ip->fixp[0]->fx_no_overflow = 1;
2832
2833 if (mips_relax.sequence)
2834 {
2835 if (mips_relax.first_fixup == 0)
2836 mips_relax.first_fixup = ip->fixp[0];
2837 }
2838 else if (reloc_needs_lo_p (*reloc_type))
2839 {
2840 struct mips_hi_fixup *hi_fixup;
2841
2842 /* Reuse the last entry if it already has a matching %lo. */
2843 hi_fixup = mips_hi_fixup_list;
2844 if (hi_fixup == 0
2845 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2846 {
2847 hi_fixup = ((struct mips_hi_fixup *)
2848 xmalloc (sizeof (struct mips_hi_fixup)));
2849 hi_fixup->next = mips_hi_fixup_list;
2850 mips_hi_fixup_list = hi_fixup;
2851 }
2852 hi_fixup->fixp = ip->fixp[0];
2853 hi_fixup->seg = now_seg;
2854 }
2855
2856 /* Add fixups for the second and third relocations, if given.
2857 Note that the ABI allows the second relocation to be
2858 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2859 moment we only use RSS_UNDEF, but we could add support
2860 for the others if it ever becomes necessary. */
2861 for (i = 1; i < 3; i++)
2862 if (reloc_type[i] != BFD_RELOC_UNUSED)
2863 {
2864 ip->fixp[i] = fix_new (ip->frag, ip->where,
2865 ip->fixp[0]->fx_size, NULL, 0,
2866 FALSE, reloc_type[i]);
2867
2868 /* Use fx_tcbit to mark compound relocs. */
2869 ip->fixp[0]->fx_tcbit = 1;
2870 ip->fixp[i]->fx_tcbit = 1;
2871 }
2872 }
2873 }
2874 install_insn (ip);
2875
2876 /* Update the register mask information. */
2877 if (! mips_opts.mips16)
2878 {
2879 if (pinfo & INSN_WRITE_GPR_D)
2880 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
2881 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2882 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
2883 if (pinfo & INSN_READ_GPR_S)
2884 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
2885 if (pinfo & INSN_WRITE_GPR_31)
2886 mips_gprmask |= 1 << RA;
2887 if (pinfo & INSN_WRITE_FPR_D)
2888 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
2889 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2890 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
2891 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2892 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
2893 if ((pinfo & INSN_READ_FPR_R) != 0)
2894 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
2895 if (pinfo & INSN_COP)
2896 {
2897 /* We don't keep enough information to sort these cases out.
2898 The itbl support does keep this information however, although
2899 we currently don't support itbl fprmats as part of the cop
2900 instruction. May want to add this support in the future. */
2901 }
2902 /* Never set the bit for $0, which is always zero. */
2903 mips_gprmask &= ~1 << 0;
2904 }
2905 else
2906 {
2907 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2908 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
2909 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2910 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
2911 if (pinfo & MIPS16_INSN_WRITE_Z)
2912 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
2913 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2914 mips_gprmask |= 1 << TREG;
2915 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2916 mips_gprmask |= 1 << SP;
2917 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2918 mips_gprmask |= 1 << RA;
2919 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2920 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2921 if (pinfo & MIPS16_INSN_READ_Z)
2922 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
2923 if (pinfo & MIPS16_INSN_READ_GPR_X)
2924 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2925 }
2926
2927 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2928 {
2929 /* Filling the branch delay slot is more complex. We try to
2930 switch the branch with the previous instruction, which we can
2931 do if the previous instruction does not set up a condition
2932 that the branch tests and if the branch is not itself the
2933 target of any branch. */
2934 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2935 || (pinfo & INSN_COND_BRANCH_DELAY))
2936 {
2937 if (mips_optimize < 2
2938 /* If we have seen .set volatile or .set nomove, don't
2939 optimize. */
2940 || mips_opts.nomove != 0
2941 /* We can't swap if the previous instruction's position
2942 is fixed. */
2943 || history[0].fixed_p
2944 /* If the previous previous insn was in a .set
2945 noreorder, we can't swap. Actually, the MIPS
2946 assembler will swap in this situation. However, gcc
2947 configured -with-gnu-as will generate code like
2948 .set noreorder
2949 lw $4,XXX
2950 .set reorder
2951 INSN
2952 bne $4,$0,foo
2953 in which we can not swap the bne and INSN. If gcc is
2954 not configured -with-gnu-as, it does not output the
2955 .set pseudo-ops. */
2956 || history[1].noreorder_p
2957 /* If the branch is itself the target of a branch, we
2958 can not swap. We cheat on this; all we check for is
2959 whether there is a label on this instruction. If
2960 there are any branches to anything other than a
2961 label, users must use .set noreorder. */
2962 || si->label_list != NULL
2963 /* If the previous instruction is in a variant frag
2964 other than this branch's one, we cannot do the swap.
2965 This does not apply to the mips16, which uses variant
2966 frags for different purposes. */
2967 || (! mips_opts.mips16
2968 && prev_insn_frag_type == rs_machine_dependent)
2969 /* Check for conflicts between the branch and the instructions
2970 before the candidate delay slot. */
2971 || nops_for_insn (history + 1, ip) > 0
2972 /* Check for conflicts between the swapped sequence and the
2973 target of the branch. */
2974 || nops_for_sequence (2, history + 1, ip, history) > 0
2975 /* We do not swap with a trap instruction, since it
2976 complicates trap handlers to have the trap
2977 instruction be in a delay slot. */
2978 || (prev_pinfo & INSN_TRAP)
2979 /* If the branch reads a register that the previous
2980 instruction sets, we can not swap. */
2981 || (! mips_opts.mips16
2982 && (prev_pinfo & INSN_WRITE_GPR_T)
2983 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
2984 MIPS_GR_REG))
2985 || (! mips_opts.mips16
2986 && (prev_pinfo & INSN_WRITE_GPR_D)
2987 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
2988 MIPS_GR_REG))
2989 || (mips_opts.mips16
2990 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2991 && (insn_uses_reg
2992 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
2993 MIPS16_REG)))
2994 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2995 && (insn_uses_reg
2996 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
2997 MIPS16_REG)))
2998 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2999 && (insn_uses_reg
3000 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3001 MIPS16_REG)))
3002 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3003 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3004 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3005 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3006 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3007 && insn_uses_reg (ip,
3008 MIPS16OP_EXTRACT_REG32R
3009 (history[0].insn_opcode),
3010 MIPS_GR_REG))))
3011 /* If the branch writes a register that the previous
3012 instruction sets, we can not swap (we know that
3013 branches write only to RD or to $31). */
3014 || (! mips_opts.mips16
3015 && (prev_pinfo & INSN_WRITE_GPR_T)
3016 && (((pinfo & INSN_WRITE_GPR_D)
3017 && (EXTRACT_OPERAND (RT, history[0])
3018 == EXTRACT_OPERAND (RD, *ip)))
3019 || ((pinfo & INSN_WRITE_GPR_31)
3020 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3021 || (! mips_opts.mips16
3022 && (prev_pinfo & INSN_WRITE_GPR_D)
3023 && (((pinfo & INSN_WRITE_GPR_D)
3024 && (EXTRACT_OPERAND (RD, history[0])
3025 == EXTRACT_OPERAND (RD, *ip)))
3026 || ((pinfo & INSN_WRITE_GPR_31)
3027 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3028 || (mips_opts.mips16
3029 && (pinfo & MIPS16_INSN_WRITE_31)
3030 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3031 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3032 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3033 == RA))))
3034 /* If the branch writes a register that the previous
3035 instruction reads, we can not swap (we know that
3036 branches only write to RD or to $31). */
3037 || (! mips_opts.mips16
3038 && (pinfo & INSN_WRITE_GPR_D)
3039 && insn_uses_reg (&history[0],
3040 EXTRACT_OPERAND (RD, *ip),
3041 MIPS_GR_REG))
3042 || (! mips_opts.mips16
3043 && (pinfo & INSN_WRITE_GPR_31)
3044 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3045 || (mips_opts.mips16
3046 && (pinfo & MIPS16_INSN_WRITE_31)
3047 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3048 /* If one instruction sets a condition code and the
3049 other one uses a condition code, we can not swap. */
3050 || ((pinfo & INSN_READ_COND_CODE)
3051 && (prev_pinfo & INSN_WRITE_COND_CODE))
3052 || ((pinfo & INSN_WRITE_COND_CODE)
3053 && (prev_pinfo & INSN_READ_COND_CODE))
3054 /* If the previous instruction uses the PC, we can not
3055 swap. */
3056 || (mips_opts.mips16
3057 && (prev_pinfo & MIPS16_INSN_READ_PC))
3058 /* If the previous instruction had a fixup in mips16
3059 mode, we can not swap. This normally means that the
3060 previous instruction was a 4 byte branch anyhow. */
3061 || (mips_opts.mips16 && history[0].fixp[0])
3062 /* If the previous instruction is a sync, sync.l, or
3063 sync.p, we can not swap. */
3064 || (prev_pinfo & INSN_SYNC))
3065 {
3066 if (mips_opts.mips16
3067 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3068 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3069 && ISA_SUPPORTS_MIPS16E)
3070 {
3071 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3072 ip->insn_opcode |= 0x0080;
3073 install_insn (ip);
3074 insert_into_history (0, 1, ip);
3075 }
3076 else
3077 {
3078 /* We could do even better for unconditional branches to
3079 portions of this object file; we could pick up the
3080 instruction at the destination, put it in the delay
3081 slot, and bump the destination address. */
3082 insert_into_history (0, 1, ip);
3083 emit_nop ();
3084 }
3085
3086 if (mips_relax.sequence)
3087 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3088 }
3089 else
3090 {
3091 /* It looks like we can actually do the swap. */
3092 struct mips_cl_insn delay = history[0];
3093 if (mips_opts.mips16)
3094 {
3095 know (delay.frag == ip->frag);
3096 move_insn (ip, delay.frag, delay.where);
3097 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3098 }
3099 else if (relaxed_branch)
3100 {
3101 /* Add the delay slot instruction to the end of the
3102 current frag and shrink the fixed part of the
3103 original frag. If the branch occupies the tail of
3104 the latter, move it backwards to cover the gap. */
3105 delay.frag->fr_fix -= 4;
3106 if (delay.frag == ip->frag)
3107 move_insn (ip, ip->frag, ip->where - 4);
3108 add_fixed_insn (&delay);
3109 }
3110 else
3111 {
3112 move_insn (&delay, ip->frag, ip->where);
3113 move_insn (ip, history[0].frag, history[0].where);
3114 }
3115 history[0] = *ip;
3116 delay.fixed_p = 1;
3117 insert_into_history (0, 1, &delay);
3118 }
3119
3120 /* If that was an unconditional branch, forget the previous
3121 insn information. */
3122 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3123 mips_no_prev_insn ();
3124 }
3125 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3126 {
3127 /* We don't yet optimize a branch likely. What we should do
3128 is look at the target, copy the instruction found there
3129 into the delay slot, and increment the branch to jump to
3130 the next instruction. */
3131 insert_into_history (0, 1, ip);
3132 emit_nop ();
3133 }
3134 else
3135 insert_into_history (0, 1, ip);
3136 }
3137 else
3138 insert_into_history (0, 1, ip);
3139
3140 /* We just output an insn, so the next one doesn't have a label. */
3141 mips_clear_insn_labels ();
3142 }
3143
3144 /* Forget that there was any previous instruction or label. */
3145
3146 static void
3147 mips_no_prev_insn (void)
3148 {
3149 prev_nop_frag = NULL;
3150 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3151 mips_clear_insn_labels ();
3152 }
3153
3154 /* This function must be called before we emit something other than
3155 instructions. It is like mips_no_prev_insn except that it inserts
3156 any NOPS that might be needed by previous instructions. */
3157
3158 void
3159 mips_emit_delays (void)
3160 {
3161 if (! mips_opts.noreorder)
3162 {
3163 int nops = nops_for_insn (history, NULL);
3164 if (nops > 0)
3165 {
3166 while (nops-- > 0)
3167 add_fixed_insn (NOP_INSN);
3168 mips_move_labels ();
3169 }
3170 }
3171 mips_no_prev_insn ();
3172 }
3173
3174 /* Start a (possibly nested) noreorder block. */
3175
3176 static void
3177 start_noreorder (void)
3178 {
3179 if (mips_opts.noreorder == 0)
3180 {
3181 unsigned int i;
3182 int nops;
3183
3184 /* None of the instructions before the .set noreorder can be moved. */
3185 for (i = 0; i < ARRAY_SIZE (history); i++)
3186 history[i].fixed_p = 1;
3187
3188 /* Insert any nops that might be needed between the .set noreorder
3189 block and the previous instructions. We will later remove any
3190 nops that turn out not to be needed. */
3191 nops = nops_for_insn (history, NULL);
3192 if (nops > 0)
3193 {
3194 if (mips_optimize != 0)
3195 {
3196 /* Record the frag which holds the nop instructions, so
3197 that we can remove them if we don't need them. */
3198 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3199 prev_nop_frag = frag_now;
3200 prev_nop_frag_holds = nops;
3201 prev_nop_frag_required = 0;
3202 prev_nop_frag_since = 0;
3203 }
3204
3205 for (; nops > 0; --nops)
3206 add_fixed_insn (NOP_INSN);
3207
3208 /* Move on to a new frag, so that it is safe to simply
3209 decrease the size of prev_nop_frag. */
3210 frag_wane (frag_now);
3211 frag_new (0);
3212 mips_move_labels ();
3213 }
3214 mips16_mark_labels ();
3215 mips_clear_insn_labels ();
3216 }
3217 mips_opts.noreorder++;
3218 mips_any_noreorder = 1;
3219 }
3220
3221 /* End a nested noreorder block. */
3222
3223 static void
3224 end_noreorder (void)
3225 {
3226 mips_opts.noreorder--;
3227 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3228 {
3229 /* Commit to inserting prev_nop_frag_required nops and go back to
3230 handling nop insertion the .set reorder way. */
3231 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3232 * (mips_opts.mips16 ? 2 : 4));
3233 insert_into_history (prev_nop_frag_since,
3234 prev_nop_frag_required, NOP_INSN);
3235 prev_nop_frag = NULL;
3236 }
3237 }
3238
3239 /* Set up global variables for the start of a new macro. */
3240
3241 static void
3242 macro_start (void)
3243 {
3244 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3245 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3246 && (history[0].insn_mo->pinfo
3247 & (INSN_UNCOND_BRANCH_DELAY
3248 | INSN_COND_BRANCH_DELAY
3249 | INSN_COND_BRANCH_LIKELY)) != 0);
3250 }
3251
3252 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3253 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3254 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3255
3256 static const char *
3257 macro_warning (relax_substateT subtype)
3258 {
3259 if (subtype & RELAX_DELAY_SLOT)
3260 return _("Macro instruction expanded into multiple instructions"
3261 " in a branch delay slot");
3262 else if (subtype & RELAX_NOMACRO)
3263 return _("Macro instruction expanded into multiple instructions");
3264 else
3265 return 0;
3266 }
3267
3268 /* Finish up a macro. Emit warnings as appropriate. */
3269
3270 static void
3271 macro_end (void)
3272 {
3273 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3274 {
3275 relax_substateT subtype;
3276
3277 /* Set up the relaxation warning flags. */
3278 subtype = 0;
3279 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3280 subtype |= RELAX_SECOND_LONGER;
3281 if (mips_opts.warn_about_macros)
3282 subtype |= RELAX_NOMACRO;
3283 if (mips_macro_warning.delay_slot_p)
3284 subtype |= RELAX_DELAY_SLOT;
3285
3286 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3287 {
3288 /* Either the macro has a single implementation or both
3289 implementations are longer than 4 bytes. Emit the
3290 warning now. */
3291 const char *msg = macro_warning (subtype);
3292 if (msg != 0)
3293 as_warn (msg);
3294 }
3295 else
3296 {
3297 /* One implementation might need a warning but the other
3298 definitely doesn't. */
3299 mips_macro_warning.first_frag->fr_subtype |= subtype;
3300 }
3301 }
3302 }
3303
3304 /* Read a macro's relocation codes from *ARGS and store them in *R.
3305 The first argument in *ARGS will be either the code for a single
3306 relocation or -1 followed by the three codes that make up a
3307 composite relocation. */
3308
3309 static void
3310 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3311 {
3312 int i, next;
3313
3314 next = va_arg (*args, int);
3315 if (next >= 0)
3316 r[0] = (bfd_reloc_code_real_type) next;
3317 else
3318 for (i = 0; i < 3; i++)
3319 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3320 }
3321
3322 /* Build an instruction created by a macro expansion. This is passed
3323 a pointer to the count of instructions created so far, an
3324 expression, the name of the instruction to build, an operand format
3325 string, and corresponding arguments. */
3326
3327 static void
3328 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3329 {
3330 const struct mips_opcode *mo;
3331 struct mips_cl_insn insn;
3332 bfd_reloc_code_real_type r[3];
3333 va_list args;
3334
3335 va_start (args, fmt);
3336
3337 if (mips_opts.mips16)
3338 {
3339 mips16_macro_build (ep, name, fmt, args);
3340 va_end (args);
3341 return;
3342 }
3343
3344 r[0] = BFD_RELOC_UNUSED;
3345 r[1] = BFD_RELOC_UNUSED;
3346 r[2] = BFD_RELOC_UNUSED;
3347 mo = (struct mips_opcode *) hash_find (op_hash, name);
3348 assert (mo);
3349 assert (strcmp (name, mo->name) == 0);
3350
3351 while (1)
3352 {
3353 /* Search until we get a match for NAME. It is assumed here that
3354 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3355 if (strcmp (fmt, mo->args) == 0
3356 && mo->pinfo != INSN_MACRO
3357 && OPCODE_IS_MEMBER (mo,
3358 (mips_opts.isa
3359 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
3360 | (mips_opts.ase_dsp ? INSN_DSP : 0)
3361 | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
3362 ? INSN_DSP64 : 0)
3363 | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
3364 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
3365 mips_opts.arch)
3366 && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
3367 break;
3368
3369 ++mo;
3370 assert (mo->name);
3371 assert (strcmp (name, mo->name) == 0);
3372 }
3373
3374 create_insn (&insn, mo);
3375 for (;;)
3376 {
3377 switch (*fmt++)
3378 {
3379 case '\0':
3380 break;
3381
3382 case ',':
3383 case '(':
3384 case ')':
3385 continue;
3386
3387 case '+':
3388 switch (*fmt++)
3389 {
3390 case 'A':
3391 case 'E':
3392 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3393 continue;
3394
3395 case 'B':
3396 case 'F':
3397 /* Note that in the macro case, these arguments are already
3398 in MSB form. (When handling the instruction in the
3399 non-macro case, these arguments are sizes from which
3400 MSB values must be calculated.) */
3401 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3402 continue;
3403
3404 case 'C':
3405 case 'G':
3406 case 'H':
3407 /* Note that in the macro case, these arguments are already
3408 in MSBD form. (When handling the instruction in the
3409 non-macro case, these arguments are sizes from which
3410 MSBD values must be calculated.) */
3411 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3412 continue;
3413
3414 default:
3415 internalError ();
3416 }
3417 continue;
3418
3419 case '2':
3420 INSERT_OPERAND (BP, insn, va_arg (args, int));
3421 continue;
3422
3423 case 't':
3424 case 'w':
3425 case 'E':
3426 INSERT_OPERAND (RT, insn, va_arg (args, int));
3427 continue;
3428
3429 case 'c':
3430 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3431 continue;
3432
3433 case 'T':
3434 case 'W':
3435 INSERT_OPERAND (FT, insn, va_arg (args, int));
3436 continue;
3437
3438 case 'd':
3439 case 'G':
3440 case 'K':
3441 INSERT_OPERAND (RD, insn, va_arg (args, int));
3442 continue;
3443
3444 case 'U':
3445 {
3446 int tmp = va_arg (args, int);
3447
3448 INSERT_OPERAND (RT, insn, tmp);
3449 INSERT_OPERAND (RD, insn, tmp);
3450 continue;
3451 }
3452
3453 case 'V':
3454 case 'S':
3455 INSERT_OPERAND (FS, insn, va_arg (args, int));
3456 continue;
3457
3458 case 'z':
3459 continue;
3460
3461 case '<':
3462 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3463 continue;
3464
3465 case 'D':
3466 INSERT_OPERAND (FD, insn, va_arg (args, int));
3467 continue;
3468
3469 case 'B':
3470 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3471 continue;
3472
3473 case 'J':
3474 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3475 continue;
3476
3477 case 'q':
3478 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3479 continue;
3480
3481 case 'b':
3482 case 's':
3483 case 'r':
3484 case 'v':
3485 INSERT_OPERAND (RS, insn, va_arg (args, int));
3486 continue;
3487
3488 case 'i':
3489 case 'j':
3490 case 'o':
3491 macro_read_relocs (&args, r);
3492 assert (*r == BFD_RELOC_GPREL16
3493 || *r == BFD_RELOC_MIPS_LITERAL
3494 || *r == BFD_RELOC_MIPS_HIGHER
3495 || *r == BFD_RELOC_HI16_S
3496 || *r == BFD_RELOC_LO16
3497 || *r == BFD_RELOC_MIPS_GOT16
3498 || *r == BFD_RELOC_MIPS_CALL16
3499 || *r == BFD_RELOC_MIPS_GOT_DISP
3500 || *r == BFD_RELOC_MIPS_GOT_PAGE
3501 || *r == BFD_RELOC_MIPS_GOT_OFST
3502 || *r == BFD_RELOC_MIPS_GOT_LO16
3503 || *r == BFD_RELOC_MIPS_CALL_LO16);
3504 continue;
3505
3506 case 'u':
3507 macro_read_relocs (&args, r);
3508 assert (ep != NULL
3509 && (ep->X_op == O_constant
3510 || (ep->X_op == O_symbol
3511 && (*r == BFD_RELOC_MIPS_HIGHEST
3512 || *r == BFD_RELOC_HI16_S
3513 || *r == BFD_RELOC_HI16
3514 || *r == BFD_RELOC_GPREL16
3515 || *r == BFD_RELOC_MIPS_GOT_HI16
3516 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3517 continue;
3518
3519 case 'p':
3520 assert (ep != NULL);
3521
3522 /*
3523 * This allows macro() to pass an immediate expression for
3524 * creating short branches without creating a symbol.
3525 *
3526 * We don't allow branch relaxation for these branches, as
3527 * they should only appear in ".set nomacro" anyway.
3528 */
3529 if (ep->X_op == O_constant)
3530 {
3531 if ((ep->X_add_number & 3) != 0)
3532 as_bad (_("branch to misaligned address (0x%lx)"),
3533 (unsigned long) ep->X_add_number);
3534 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3535 as_bad (_("branch address range overflow (0x%lx)"),
3536 (unsigned long) ep->X_add_number);
3537 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3538 ep = NULL;
3539 }
3540 else
3541 *r = BFD_RELOC_16_PCREL_S2;
3542 continue;
3543
3544 case 'a':
3545 assert (ep != NULL);
3546 *r = BFD_RELOC_MIPS_JMP;
3547 continue;
3548
3549 case 'C':
3550 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3551 continue;
3552
3553 case 'k':
3554 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3555 continue;
3556
3557 default:
3558 internalError ();
3559 }
3560 break;
3561 }
3562 va_end (args);
3563 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3564
3565 append_insn (&insn, ep, r);
3566 }
3567
3568 static void
3569 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3570 va_list args)
3571 {
3572 struct mips_opcode *mo;
3573 struct mips_cl_insn insn;
3574 bfd_reloc_code_real_type r[3]
3575 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3576
3577 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3578 assert (mo);
3579 assert (strcmp (name, mo->name) == 0);
3580
3581 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3582 {
3583 ++mo;
3584 assert (mo->name);
3585 assert (strcmp (name, mo->name) == 0);
3586 }
3587
3588 create_insn (&insn, mo);
3589 for (;;)
3590 {
3591 int c;
3592
3593 c = *fmt++;
3594 switch (c)
3595 {
3596 case '\0':
3597 break;
3598
3599 case ',':
3600 case '(':
3601 case ')':
3602 continue;
3603
3604 case 'y':
3605 case 'w':
3606 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3607 continue;
3608
3609 case 'x':
3610 case 'v':
3611 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3612 continue;
3613
3614 case 'z':
3615 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3616 continue;
3617
3618 case 'Z':
3619 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3620 continue;
3621
3622 case '0':
3623 case 'S':
3624 case 'P':
3625 case 'R':
3626 continue;
3627
3628 case 'X':
3629 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3630 continue;
3631
3632 case 'Y':
3633 {
3634 int regno;
3635
3636 regno = va_arg (args, int);
3637 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3638 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3639 }
3640 continue;
3641
3642 case '<':
3643 case '>':
3644 case '4':
3645 case '5':
3646 case 'H':
3647 case 'W':
3648 case 'D':
3649 case 'j':
3650 case '8':
3651 case 'V':
3652 case 'C':
3653 case 'U':
3654 case 'k':
3655 case 'K':
3656 case 'p':
3657 case 'q':
3658 {
3659 assert (ep != NULL);
3660
3661 if (ep->X_op != O_constant)
3662 *r = (int) BFD_RELOC_UNUSED + c;
3663 else
3664 {
3665 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3666 FALSE, &insn.insn_opcode, &insn.use_extend,
3667 &insn.extend);
3668 ep = NULL;
3669 *r = BFD_RELOC_UNUSED;
3670 }
3671 }
3672 continue;
3673
3674 case '6':
3675 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3676 continue;
3677 }
3678
3679 break;
3680 }
3681
3682 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3683
3684 append_insn (&insn, ep, r);
3685 }
3686
3687 /*
3688 * Sign-extend 32-bit mode constants that have bit 31 set and all
3689 * higher bits unset.
3690 */
3691 static void
3692 normalize_constant_expr (expressionS *ex)
3693 {
3694 if (ex->X_op == O_constant
3695 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3696 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3697 - 0x80000000);
3698 }
3699
3700 /*
3701 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3702 * all higher bits unset.
3703 */
3704 static void
3705 normalize_address_expr (expressionS *ex)
3706 {
3707 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3708 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3709 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3710 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3711 - 0x80000000);
3712 }
3713
3714 /*
3715 * Generate a "jalr" instruction with a relocation hint to the called
3716 * function. This occurs in NewABI PIC code.
3717 */
3718 static void
3719 macro_build_jalr (expressionS *ep)
3720 {
3721 char *f = NULL;
3722
3723 if (HAVE_NEWABI)
3724 {
3725 frag_grow (8);
3726 f = frag_more (0);
3727 }
3728 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3729 if (HAVE_NEWABI)
3730 fix_new_exp (frag_now, f - frag_now->fr_literal,
3731 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3732 }
3733
3734 /*
3735 * Generate a "lui" instruction.
3736 */
3737 static void
3738 macro_build_lui (expressionS *ep, int regnum)
3739 {
3740 expressionS high_expr;
3741 const struct mips_opcode *mo;
3742 struct mips_cl_insn insn;
3743 bfd_reloc_code_real_type r[3]
3744 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3745 const char *name = "lui";
3746 const char *fmt = "t,u";
3747
3748 assert (! mips_opts.mips16);
3749
3750 high_expr = *ep;
3751
3752 if (high_expr.X_op == O_constant)
3753 {
3754 /* We can compute the instruction now without a relocation entry. */
3755 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3756 >> 16) & 0xffff;
3757 *r = BFD_RELOC_UNUSED;
3758 }
3759 else
3760 {
3761 assert (ep->X_op == O_symbol);
3762 /* _gp_disp is a special case, used from s_cpload.
3763 __gnu_local_gp is used if mips_no_shared. */
3764 assert (mips_pic == NO_PIC
3765 || (! HAVE_NEWABI
3766 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
3767 || (! mips_in_shared
3768 && strcmp (S_GET_NAME (ep->X_add_symbol),
3769 "__gnu_local_gp") == 0));
3770 *r = BFD_RELOC_HI16_S;
3771 }
3772
3773 mo = hash_find (op_hash, name);
3774 assert (strcmp (name, mo->name) == 0);
3775 assert (strcmp (fmt, mo->args) == 0);
3776 create_insn (&insn, mo);
3777
3778 insn.insn_opcode = insn.insn_mo->match;
3779 INSERT_OPERAND (RT, insn, regnum);
3780 if (*r == BFD_RELOC_UNUSED)
3781 {
3782 insn.insn_opcode |= high_expr.X_add_number;
3783 append_insn (&insn, NULL, r);
3784 }
3785 else
3786 append_insn (&insn, &high_expr, r);
3787 }
3788
3789 /* Generate a sequence of instructions to do a load or store from a constant
3790 offset off of a base register (breg) into/from a target register (treg),
3791 using AT if necessary. */
3792 static void
3793 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3794 int treg, int breg, int dbl)
3795 {
3796 assert (ep->X_op == O_constant);
3797
3798 /* Sign-extending 32-bit constants makes their handling easier. */
3799 if (!dbl)
3800 normalize_constant_expr (ep);
3801
3802 /* Right now, this routine can only handle signed 32-bit constants. */
3803 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3804 as_warn (_("operand overflow"));
3805
3806 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3807 {
3808 /* Signed 16-bit offset will fit in the op. Easy! */
3809 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3810 }
3811 else
3812 {
3813 /* 32-bit offset, need multiple instructions and AT, like:
3814 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3815 addu $tempreg,$tempreg,$breg
3816 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3817 to handle the complete offset. */
3818 macro_build_lui (ep, AT);
3819 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3820 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3821
3822 if (!mips_opts.at)
3823 as_bad (_("Macro used $at after \".set noat\""));
3824 }
3825 }
3826
3827 /* set_at()
3828 * Generates code to set the $at register to true (one)
3829 * if reg is less than the immediate expression.
3830 */
3831 static void
3832 set_at (int reg, int unsignedp)
3833 {
3834 if (imm_expr.X_op == O_constant
3835 && imm_expr.X_add_number >= -0x8000
3836 && imm_expr.X_add_number < 0x8000)
3837 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3838 AT, reg, BFD_RELOC_LO16);
3839 else
3840 {
3841 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3842 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3843 }
3844 }
3845
3846 /* Warn if an expression is not a constant. */
3847
3848 static void
3849 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3850 {
3851 if (ex->X_op == O_big)
3852 as_bad (_("unsupported large constant"));
3853 else if (ex->X_op != O_constant)
3854 as_bad (_("Instruction %s requires absolute expression"),
3855 ip->insn_mo->name);
3856
3857 if (HAVE_32BIT_GPRS)
3858 normalize_constant_expr (ex);
3859 }
3860
3861 /* Count the leading zeroes by performing a binary chop. This is a
3862 bulky bit of source, but performance is a LOT better for the
3863 majority of values than a simple loop to count the bits:
3864 for (lcnt = 0; (lcnt < 32); lcnt++)
3865 if ((v) & (1 << (31 - lcnt)))
3866 break;
3867 However it is not code size friendly, and the gain will drop a bit
3868 on certain cached systems.
3869 */
3870 #define COUNT_TOP_ZEROES(v) \
3871 (((v) & ~0xffff) == 0 \
3872 ? ((v) & ~0xff) == 0 \
3873 ? ((v) & ~0xf) == 0 \
3874 ? ((v) & ~0x3) == 0 \
3875 ? ((v) & ~0x1) == 0 \
3876 ? !(v) \
3877 ? 32 \
3878 : 31 \
3879 : 30 \
3880 : ((v) & ~0x7) == 0 \
3881 ? 29 \
3882 : 28 \
3883 : ((v) & ~0x3f) == 0 \
3884 ? ((v) & ~0x1f) == 0 \
3885 ? 27 \
3886 : 26 \
3887 : ((v) & ~0x7f) == 0 \
3888 ? 25 \
3889 : 24 \
3890 : ((v) & ~0xfff) == 0 \
3891 ? ((v) & ~0x3ff) == 0 \
3892 ? ((v) & ~0x1ff) == 0 \
3893 ? 23 \
3894 : 22 \
3895 : ((v) & ~0x7ff) == 0 \
3896 ? 21 \
3897 : 20 \
3898 : ((v) & ~0x3fff) == 0 \
3899 ? ((v) & ~0x1fff) == 0 \
3900 ? 19 \
3901 : 18 \
3902 : ((v) & ~0x7fff) == 0 \
3903 ? 17 \
3904 : 16 \
3905 : ((v) & ~0xffffff) == 0 \
3906 ? ((v) & ~0xfffff) == 0 \
3907 ? ((v) & ~0x3ffff) == 0 \
3908 ? ((v) & ~0x1ffff) == 0 \
3909 ? 15 \
3910 : 14 \
3911 : ((v) & ~0x7ffff) == 0 \
3912 ? 13 \
3913 : 12 \
3914 : ((v) & ~0x3fffff) == 0 \
3915 ? ((v) & ~0x1fffff) == 0 \
3916 ? 11 \
3917 : 10 \
3918 : ((v) & ~0x7fffff) == 0 \
3919 ? 9 \
3920 : 8 \
3921 : ((v) & ~0xfffffff) == 0 \
3922 ? ((v) & ~0x3ffffff) == 0 \
3923 ? ((v) & ~0x1ffffff) == 0 \
3924 ? 7 \
3925 : 6 \
3926 : ((v) & ~0x7ffffff) == 0 \
3927 ? 5 \
3928 : 4 \
3929 : ((v) & ~0x3fffffff) == 0 \
3930 ? ((v) & ~0x1fffffff) == 0 \
3931 ? 3 \
3932 : 2 \
3933 : ((v) & ~0x7fffffff) == 0 \
3934 ? 1 \
3935 : 0)
3936
3937 /* load_register()
3938 * This routine generates the least number of instructions necessary to load
3939 * an absolute expression value into a register.
3940 */
3941 static void
3942 load_register (int reg, expressionS *ep, int dbl)
3943 {
3944 int freg;
3945 expressionS hi32, lo32;
3946
3947 if (ep->X_op != O_big)
3948 {
3949 assert (ep->X_op == O_constant);
3950
3951 /* Sign-extending 32-bit constants makes their handling easier. */
3952 if (!dbl)
3953 normalize_constant_expr (ep);
3954
3955 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3956 {
3957 /* We can handle 16 bit signed values with an addiu to
3958 $zero. No need to ever use daddiu here, since $zero and
3959 the result are always correct in 32 bit mode. */
3960 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3961 return;
3962 }
3963 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3964 {
3965 /* We can handle 16 bit unsigned values with an ori to
3966 $zero. */
3967 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3968 return;
3969 }
3970 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3971 {
3972 /* 32 bit values require an lui. */
3973 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3974 if ((ep->X_add_number & 0xffff) != 0)
3975 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3976 return;
3977 }
3978 }
3979
3980 /* The value is larger than 32 bits. */
3981
3982 if (!dbl || HAVE_32BIT_GPRS)
3983 {
3984 char value[32];
3985
3986 sprintf_vma (value, ep->X_add_number);
3987 as_bad (_("Number (0x%s) larger than 32 bits"), value);
3988 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3989 return;
3990 }
3991
3992 if (ep->X_op != O_big)
3993 {
3994 hi32 = *ep;
3995 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3996 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3997 hi32.X_add_number &= 0xffffffff;
3998 lo32 = *ep;
3999 lo32.X_add_number &= 0xffffffff;
4000 }
4001 else
4002 {
4003 assert (ep->X_add_number > 2);
4004 if (ep->X_add_number == 3)
4005 generic_bignum[3] = 0;
4006 else if (ep->X_add_number > 4)
4007 as_bad (_("Number larger than 64 bits"));
4008 lo32.X_op = O_constant;
4009 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4010 hi32.X_op = O_constant;
4011 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4012 }
4013
4014 if (hi32.X_add_number == 0)
4015 freg = 0;
4016 else
4017 {
4018 int shift, bit;
4019 unsigned long hi, lo;
4020
4021 if (hi32.X_add_number == (offsetT) 0xffffffff)
4022 {
4023 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4024 {
4025 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4026 return;
4027 }
4028 if (lo32.X_add_number & 0x80000000)
4029 {
4030 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4031 if (lo32.X_add_number & 0xffff)
4032 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4033 return;
4034 }
4035 }
4036
4037 /* Check for 16bit shifted constant. We know that hi32 is
4038 non-zero, so start the mask on the first bit of the hi32
4039 value. */
4040 shift = 17;
4041 do
4042 {
4043 unsigned long himask, lomask;
4044
4045 if (shift < 32)
4046 {
4047 himask = 0xffff >> (32 - shift);
4048 lomask = (0xffff << shift) & 0xffffffff;
4049 }
4050 else
4051 {
4052 himask = 0xffff << (shift - 32);
4053 lomask = 0;
4054 }
4055 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4056 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4057 {
4058 expressionS tmp;
4059
4060 tmp.X_op = O_constant;
4061 if (shift < 32)
4062 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4063 | (lo32.X_add_number >> shift));
4064 else
4065 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4066 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4067 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4068 reg, reg, (shift >= 32) ? shift - 32 : shift);
4069 return;
4070 }
4071 ++shift;
4072 }
4073 while (shift <= (64 - 16));
4074
4075 /* Find the bit number of the lowest one bit, and store the
4076 shifted value in hi/lo. */
4077 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4078 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4079 if (lo != 0)
4080 {
4081 bit = 0;
4082 while ((lo & 1) == 0)
4083 {
4084 lo >>= 1;
4085 ++bit;
4086 }
4087 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4088 hi >>= bit;
4089 }
4090 else
4091 {
4092 bit = 32;
4093 while ((hi & 1) == 0)
4094 {
4095 hi >>= 1;
4096 ++bit;
4097 }
4098 lo = hi;
4099 hi = 0;
4100 }
4101
4102 /* Optimize if the shifted value is a (power of 2) - 1. */
4103 if ((hi == 0 && ((lo + 1) & lo) == 0)
4104 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4105 {
4106 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4107 if (shift != 0)
4108 {
4109 expressionS tmp;
4110
4111 /* This instruction will set the register to be all
4112 ones. */
4113 tmp.X_op = O_constant;
4114 tmp.X_add_number = (offsetT) -1;
4115 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4116 if (bit != 0)
4117 {
4118 bit += shift;
4119 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4120 reg, reg, (bit >= 32) ? bit - 32 : bit);
4121 }
4122 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4123 reg, reg, (shift >= 32) ? shift - 32 : shift);
4124 return;
4125 }
4126 }
4127
4128 /* Sign extend hi32 before calling load_register, because we can
4129 generally get better code when we load a sign extended value. */
4130 if ((hi32.X_add_number & 0x80000000) != 0)
4131 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4132 load_register (reg, &hi32, 0);
4133 freg = reg;
4134 }
4135 if ((lo32.X_add_number & 0xffff0000) == 0)
4136 {
4137 if (freg != 0)
4138 {
4139 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4140 freg = reg;
4141 }
4142 }
4143 else
4144 {
4145 expressionS mid16;
4146
4147 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4148 {
4149 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4150 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4151 return;
4152 }
4153
4154 if (freg != 0)
4155 {
4156 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4157 freg = reg;
4158 }
4159 mid16 = lo32;
4160 mid16.X_add_number >>= 16;
4161 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4162 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4163 freg = reg;
4164 }
4165 if ((lo32.X_add_number & 0xffff) != 0)
4166 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4167 }
4168
4169 static inline void
4170 load_delay_nop (void)
4171 {
4172 if (!gpr_interlocks)
4173 macro_build (NULL, "nop", "");
4174 }
4175
4176 /* Load an address into a register. */
4177
4178 static void
4179 load_address (int reg, expressionS *ep, int *used_at)
4180 {
4181 if (ep->X_op != O_constant
4182 && ep->X_op != O_symbol)
4183 {
4184 as_bad (_("expression too complex"));
4185 ep->X_op = O_constant;
4186 }
4187
4188 if (ep->X_op == O_constant)
4189 {
4190 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4191 return;
4192 }
4193
4194 if (mips_pic == NO_PIC)
4195 {
4196 /* If this is a reference to a GP relative symbol, we want
4197 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4198 Otherwise we want
4199 lui $reg,<sym> (BFD_RELOC_HI16_S)
4200 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4201 If we have an addend, we always use the latter form.
4202
4203 With 64bit address space and a usable $at we want
4204 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4205 lui $at,<sym> (BFD_RELOC_HI16_S)
4206 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4207 daddiu $at,<sym> (BFD_RELOC_LO16)
4208 dsll32 $reg,0
4209 daddu $reg,$reg,$at
4210
4211 If $at is already in use, we use a path which is suboptimal
4212 on superscalar processors.
4213 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4214 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4215 dsll $reg,16
4216 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4217 dsll $reg,16
4218 daddiu $reg,<sym> (BFD_RELOC_LO16)
4219
4220 For GP relative symbols in 64bit address space we can use
4221 the same sequence as in 32bit address space. */
4222 if (HAVE_64BIT_SYMBOLS)
4223 {
4224 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4225 && !nopic_need_relax (ep->X_add_symbol, 1))
4226 {
4227 relax_start (ep->X_add_symbol);
4228 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4229 mips_gp_register, BFD_RELOC_GPREL16);
4230 relax_switch ();
4231 }
4232
4233 if (*used_at == 0 && mips_opts.at)
4234 {
4235 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4236 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4237 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4238 BFD_RELOC_MIPS_HIGHER);
4239 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4240 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4241 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4242 *used_at = 1;
4243 }
4244 else
4245 {
4246 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4247 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4248 BFD_RELOC_MIPS_HIGHER);
4249 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4250 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4251 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4252 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4253 }
4254
4255 if (mips_relax.sequence)
4256 relax_end ();
4257 }
4258 else
4259 {
4260 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4261 && !nopic_need_relax (ep->X_add_symbol, 1))
4262 {
4263 relax_start (ep->X_add_symbol);
4264 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4265 mips_gp_register, BFD_RELOC_GPREL16);
4266 relax_switch ();
4267 }
4268 macro_build_lui (ep, reg);
4269 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4270 reg, reg, BFD_RELOC_LO16);
4271 if (mips_relax.sequence)
4272 relax_end ();
4273 }
4274 }
4275 else if (!mips_big_got)
4276 {
4277 expressionS ex;
4278
4279 /* If this is a reference to an external symbol, we want
4280 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4281 Otherwise we want
4282 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4283 nop
4284 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4285 If there is a constant, it must be added in after.
4286
4287 If we have NewABI, we want
4288 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4289 unless we're referencing a global symbol with a non-zero
4290 offset, in which case cst must be added separately. */
4291 if (HAVE_NEWABI)
4292 {
4293 if (ep->X_add_number)
4294 {
4295 ex.X_add_number = ep->X_add_number;
4296 ep->X_add_number = 0;
4297 relax_start (ep->X_add_symbol);
4298 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4299 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4300 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4301 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4302 ex.X_op = O_constant;
4303 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4304 reg, reg, BFD_RELOC_LO16);
4305 ep->X_add_number = ex.X_add_number;
4306 relax_switch ();
4307 }
4308 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4309 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4310 if (mips_relax.sequence)
4311 relax_end ();
4312 }
4313 else
4314 {
4315 ex.X_add_number = ep->X_add_number;
4316 ep->X_add_number = 0;
4317 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4318 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4319 load_delay_nop ();
4320 relax_start (ep->X_add_symbol);
4321 relax_switch ();
4322 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4323 BFD_RELOC_LO16);
4324 relax_end ();
4325
4326 if (ex.X_add_number != 0)
4327 {
4328 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4329 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4330 ex.X_op = O_constant;
4331 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4332 reg, reg, BFD_RELOC_LO16);
4333 }
4334 }
4335 }
4336 else if (mips_big_got)
4337 {
4338 expressionS ex;
4339
4340 /* This is the large GOT case. If this is a reference to an
4341 external symbol, we want
4342 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4343 addu $reg,$reg,$gp
4344 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4345
4346 Otherwise, for a reference to a local symbol in old ABI, we want
4347 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4348 nop
4349 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4350 If there is a constant, it must be added in after.
4351
4352 In the NewABI, for local symbols, with or without offsets, we want:
4353 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4354 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4355 */
4356 if (HAVE_NEWABI)
4357 {
4358 ex.X_add_number = ep->X_add_number;
4359 ep->X_add_number = 0;
4360 relax_start (ep->X_add_symbol);
4361 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4362 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4363 reg, reg, mips_gp_register);
4364 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4365 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4366 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4367 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4368 else if (ex.X_add_number)
4369 {
4370 ex.X_op = O_constant;
4371 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4372 BFD_RELOC_LO16);
4373 }
4374
4375 ep->X_add_number = ex.X_add_number;
4376 relax_switch ();
4377 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4378 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4379 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4380 BFD_RELOC_MIPS_GOT_OFST);
4381 relax_end ();
4382 }
4383 else
4384 {
4385 ex.X_add_number = ep->X_add_number;
4386 ep->X_add_number = 0;
4387 relax_start (ep->X_add_symbol);
4388 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4389 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4390 reg, reg, mips_gp_register);
4391 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4392 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4393 relax_switch ();
4394 if (reg_needs_delay (mips_gp_register))
4395 {
4396 /* We need a nop before loading from $gp. This special
4397 check is required because the lui which starts the main
4398 instruction stream does not refer to $gp, and so will not
4399 insert the nop which may be required. */
4400 macro_build (NULL, "nop", "");
4401 }
4402 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4403 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4404 load_delay_nop ();
4405 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4406 BFD_RELOC_LO16);
4407 relax_end ();
4408
4409 if (ex.X_add_number != 0)
4410 {
4411 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4412 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4413 ex.X_op = O_constant;
4414 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4415 BFD_RELOC_LO16);
4416 }
4417 }
4418 }
4419 else
4420 abort ();
4421
4422 if (!mips_opts.at && *used_at == 1)
4423 as_bad (_("Macro used $at after \".set noat\""));
4424 }
4425
4426 /* Move the contents of register SOURCE into register DEST. */
4427
4428 static void
4429 move_register (int dest, int source)
4430 {
4431 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4432 dest, source, 0);
4433 }
4434
4435 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4436 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4437 The two alternatives are:
4438
4439 Global symbol Local sybmol
4440 ------------- ------------
4441 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4442 ... ...
4443 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4444
4445 load_got_offset emits the first instruction and add_got_offset
4446 emits the second for a 16-bit offset or add_got_offset_hilo emits
4447 a sequence to add a 32-bit offset using a scratch register. */
4448
4449 static void
4450 load_got_offset (int dest, expressionS *local)
4451 {
4452 expressionS global;
4453
4454 global = *local;
4455 global.X_add_number = 0;
4456
4457 relax_start (local->X_add_symbol);
4458 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4459 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4460 relax_switch ();
4461 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4462 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4463 relax_end ();
4464 }
4465
4466 static void
4467 add_got_offset (int dest, expressionS *local)
4468 {
4469 expressionS global;
4470
4471 global.X_op = O_constant;
4472 global.X_op_symbol = NULL;
4473 global.X_add_symbol = NULL;
4474 global.X_add_number = local->X_add_number;
4475
4476 relax_start (local->X_add_symbol);
4477 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4478 dest, dest, BFD_RELOC_LO16);
4479 relax_switch ();
4480 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4481 relax_end ();
4482 }
4483
4484 static void
4485 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4486 {
4487 expressionS global;
4488 int hold_mips_optimize;
4489
4490 global.X_op = O_constant;
4491 global.X_op_symbol = NULL;
4492 global.X_add_symbol = NULL;
4493 global.X_add_number = local->X_add_number;
4494
4495 relax_start (local->X_add_symbol);
4496 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4497 relax_switch ();
4498 /* Set mips_optimize around the lui instruction to avoid
4499 inserting an unnecessary nop after the lw. */
4500 hold_mips_optimize = mips_optimize;
4501 mips_optimize = 2;
4502 macro_build_lui (&global, tmp);
4503 mips_optimize = hold_mips_optimize;
4504 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4505 relax_end ();
4506
4507 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4508 }
4509
4510 /*
4511 * Build macros
4512 * This routine implements the seemingly endless macro or synthesized
4513 * instructions and addressing modes in the mips assembly language. Many
4514 * of these macros are simple and are similar to each other. These could
4515 * probably be handled by some kind of table or grammar approach instead of
4516 * this verbose method. Others are not simple macros but are more like
4517 * optimizing code generation.
4518 * One interesting optimization is when several store macros appear
4519 * consecutively that would load AT with the upper half of the same address.
4520 * The ensuing load upper instructions are ommited. This implies some kind
4521 * of global optimization. We currently only optimize within a single macro.
4522 * For many of the load and store macros if the address is specified as a
4523 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4524 * first load register 'at' with zero and use it as the base register. The
4525 * mips assembler simply uses register $zero. Just one tiny optimization
4526 * we're missing.
4527 */
4528 static void
4529 macro (struct mips_cl_insn *ip)
4530 {
4531 unsigned int treg, sreg, dreg, breg;
4532 unsigned int tempreg;
4533 int mask;
4534 int used_at = 0;
4535 expressionS expr1;
4536 const char *s;
4537 const char *s2;
4538 const char *fmt;
4539 int likely = 0;
4540 int dbl = 0;
4541 int coproc = 0;
4542 int lr = 0;
4543 int imm = 0;
4544 int call = 0;
4545 int off;
4546 offsetT maxnum;
4547 bfd_reloc_code_real_type r;
4548 int hold_mips_optimize;
4549
4550 assert (! mips_opts.mips16);
4551
4552 treg = (ip->insn_opcode >> 16) & 0x1f;
4553 dreg = (ip->insn_opcode >> 11) & 0x1f;
4554 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4555 mask = ip->insn_mo->mask;
4556
4557 expr1.X_op = O_constant;
4558 expr1.X_op_symbol = NULL;
4559 expr1.X_add_symbol = NULL;
4560 expr1.X_add_number = 1;
4561
4562 switch (mask)
4563 {
4564 case M_DABS:
4565 dbl = 1;
4566 case M_ABS:
4567 /* bgez $a0,.+12
4568 move v0,$a0
4569 sub v0,$zero,$a0
4570 */
4571
4572 start_noreorder ();
4573
4574 expr1.X_add_number = 8;
4575 macro_build (&expr1, "bgez", "s,p", sreg);
4576 if (dreg == sreg)
4577 macro_build (NULL, "nop", "", 0);
4578 else
4579 move_register (dreg, sreg);
4580 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4581
4582 end_noreorder ();
4583 break;
4584
4585 case M_ADD_I:
4586 s = "addi";
4587 s2 = "add";
4588 goto do_addi;
4589 case M_ADDU_I:
4590 s = "addiu";
4591 s2 = "addu";
4592 goto do_addi;
4593 case M_DADD_I:
4594 dbl = 1;
4595 s = "daddi";
4596 s2 = "dadd";
4597 goto do_addi;
4598 case M_DADDU_I:
4599 dbl = 1;
4600 s = "daddiu";
4601 s2 = "daddu";
4602 do_addi:
4603 if (imm_expr.X_op == O_constant
4604 && imm_expr.X_add_number >= -0x8000
4605 && imm_expr.X_add_number < 0x8000)
4606 {
4607 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4608 break;
4609 }
4610 used_at = 1;
4611 load_register (AT, &imm_expr, dbl);
4612 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4613 break;
4614
4615 case M_AND_I:
4616 s = "andi";
4617 s2 = "and";
4618 goto do_bit;
4619 case M_OR_I:
4620 s = "ori";
4621 s2 = "or";
4622 goto do_bit;
4623 case M_NOR_I:
4624 s = "";
4625 s2 = "nor";
4626 goto do_bit;
4627 case M_XOR_I:
4628 s = "xori";
4629 s2 = "xor";
4630 do_bit:
4631 if (imm_expr.X_op == O_constant
4632 && imm_expr.X_add_number >= 0
4633 && imm_expr.X_add_number < 0x10000)
4634 {
4635 if (mask != M_NOR_I)
4636 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4637 else
4638 {
4639 macro_build (&imm_expr, "ori", "t,r,i",
4640 treg, sreg, BFD_RELOC_LO16);
4641 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4642 }
4643 break;
4644 }
4645
4646 used_at = 1;
4647 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4648 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4649 break;
4650
4651 case M_BALIGN:
4652 switch (imm_expr.X_add_number)
4653 {
4654 case 0:
4655 macro_build (NULL, "nop", "");
4656 break;
4657 case 2:
4658 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4659 break;
4660 default:
4661 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4662 (int)imm_expr.X_add_number);
4663 break;
4664 }
4665 break;
4666
4667 case M_BEQ_I:
4668 s = "beq";
4669 goto beq_i;
4670 case M_BEQL_I:
4671 s = "beql";
4672 likely = 1;
4673 goto beq_i;
4674 case M_BNE_I:
4675 s = "bne";
4676 goto beq_i;
4677 case M_BNEL_I:
4678 s = "bnel";
4679 likely = 1;
4680 beq_i:
4681 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4682 {
4683 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4684 break;
4685 }
4686 used_at = 1;
4687 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4688 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4689 break;
4690
4691 case M_BGEL:
4692 likely = 1;
4693 case M_BGE:
4694 if (treg == 0)
4695 {
4696 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4697 break;
4698 }
4699 if (sreg == 0)
4700 {
4701 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4702 break;
4703 }
4704 used_at = 1;
4705 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4706 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4707 break;
4708
4709 case M_BGTL_I:
4710 likely = 1;
4711 case M_BGT_I:
4712 /* check for > max integer */
4713 maxnum = 0x7fffffff;
4714 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4715 {
4716 maxnum <<= 16;
4717 maxnum |= 0xffff;
4718 maxnum <<= 16;
4719 maxnum |= 0xffff;
4720 }
4721 if (imm_expr.X_op == O_constant
4722 && imm_expr.X_add_number >= maxnum
4723 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4724 {
4725 do_false:
4726 /* result is always false */
4727 if (! likely)
4728 macro_build (NULL, "nop", "", 0);
4729 else
4730 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4731 break;
4732 }
4733 if (imm_expr.X_op != O_constant)
4734 as_bad (_("Unsupported large constant"));
4735 ++imm_expr.X_add_number;
4736 /* FALLTHROUGH */
4737 case M_BGE_I:
4738 case M_BGEL_I:
4739 if (mask == M_BGEL_I)
4740 likely = 1;
4741 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4742 {
4743 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4744 break;
4745 }
4746 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4747 {
4748 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4749 break;
4750 }
4751 maxnum = 0x7fffffff;
4752 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4753 {
4754 maxnum <<= 16;
4755 maxnum |= 0xffff;
4756 maxnum <<= 16;
4757 maxnum |= 0xffff;
4758 }
4759 maxnum = - maxnum - 1;
4760 if (imm_expr.X_op == O_constant
4761 && imm_expr.X_add_number <= maxnum
4762 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4763 {
4764 do_true:
4765 /* result is always true */
4766 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4767 macro_build (&offset_expr, "b", "p");
4768 break;
4769 }
4770 used_at = 1;
4771 set_at (sreg, 0);
4772 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4773 break;
4774
4775 case M_BGEUL:
4776 likely = 1;
4777 case M_BGEU:
4778 if (treg == 0)
4779 goto do_true;
4780 if (sreg == 0)
4781 {
4782 macro_build (&offset_expr, likely ? "beql" : "beq",
4783 "s,t,p", 0, treg);
4784 break;
4785 }
4786 used_at = 1;
4787 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4788 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4789 break;
4790
4791 case M_BGTUL_I:
4792 likely = 1;
4793 case M_BGTU_I:
4794 if (sreg == 0
4795 || (HAVE_32BIT_GPRS
4796 && imm_expr.X_op == O_constant
4797 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4798 goto do_false;
4799 if (imm_expr.X_op != O_constant)
4800 as_bad (_("Unsupported large constant"));
4801 ++imm_expr.X_add_number;
4802 /* FALLTHROUGH */
4803 case M_BGEU_I:
4804 case M_BGEUL_I:
4805 if (mask == M_BGEUL_I)
4806 likely = 1;
4807 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4808 goto do_true;
4809 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4810 {
4811 macro_build (&offset_expr, likely ? "bnel" : "bne",
4812 "s,t,p", sreg, 0);
4813 break;
4814 }
4815 used_at = 1;
4816 set_at (sreg, 1);
4817 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4818 break;
4819
4820 case M_BGTL:
4821 likely = 1;
4822 case M_BGT:
4823 if (treg == 0)
4824 {
4825 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4826 break;
4827 }
4828 if (sreg == 0)
4829 {
4830 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4831 break;
4832 }
4833 used_at = 1;
4834 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4835 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4836 break;
4837
4838 case M_BGTUL:
4839 likely = 1;
4840 case M_BGTU:
4841 if (treg == 0)
4842 {
4843 macro_build (&offset_expr, likely ? "bnel" : "bne",
4844 "s,t,p", sreg, 0);
4845 break;
4846 }
4847 if (sreg == 0)
4848 goto do_false;
4849 used_at = 1;
4850 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4851 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4852 break;
4853
4854 case M_BLEL:
4855 likely = 1;
4856 case M_BLE:
4857 if (treg == 0)
4858 {
4859 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4860 break;
4861 }
4862 if (sreg == 0)
4863 {
4864 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4865 break;
4866 }
4867 used_at = 1;
4868 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4869 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4870 break;
4871
4872 case M_BLEL_I:
4873 likely = 1;
4874 case M_BLE_I:
4875 maxnum = 0x7fffffff;
4876 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4877 {
4878 maxnum <<= 16;
4879 maxnum |= 0xffff;
4880 maxnum <<= 16;
4881 maxnum |= 0xffff;
4882 }
4883 if (imm_expr.X_op == O_constant
4884 && imm_expr.X_add_number >= maxnum
4885 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4886 goto do_true;
4887 if (imm_expr.X_op != O_constant)
4888 as_bad (_("Unsupported large constant"));
4889 ++imm_expr.X_add_number;
4890 /* FALLTHROUGH */
4891 case M_BLT_I:
4892 case M_BLTL_I:
4893 if (mask == M_BLTL_I)
4894 likely = 1;
4895 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4896 {
4897 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4898 break;
4899 }
4900 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4901 {
4902 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4903 break;
4904 }
4905 used_at = 1;
4906 set_at (sreg, 0);
4907 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4908 break;
4909
4910 case M_BLEUL:
4911 likely = 1;
4912 case M_BLEU:
4913 if (treg == 0)
4914 {
4915 macro_build (&offset_expr, likely ? "beql" : "beq",
4916 "s,t,p", sreg, 0);
4917 break;
4918 }
4919 if (sreg == 0)
4920 goto do_true;
4921 used_at = 1;
4922 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4923 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4924 break;
4925
4926 case M_BLEUL_I:
4927 likely = 1;
4928 case M_BLEU_I:
4929 if (sreg == 0
4930 || (HAVE_32BIT_GPRS
4931 && imm_expr.X_op == O_constant
4932 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4933 goto do_true;
4934 if (imm_expr.X_op != O_constant)
4935 as_bad (_("Unsupported large constant"));
4936 ++imm_expr.X_add_number;
4937 /* FALLTHROUGH */
4938 case M_BLTU_I:
4939 case M_BLTUL_I:
4940 if (mask == M_BLTUL_I)
4941 likely = 1;
4942 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4943 goto do_false;
4944 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4945 {
4946 macro_build (&offset_expr, likely ? "beql" : "beq",
4947 "s,t,p", sreg, 0);
4948 break;
4949 }
4950 used_at = 1;
4951 set_at (sreg, 1);
4952 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4953 break;
4954
4955 case M_BLTL:
4956 likely = 1;
4957 case M_BLT:
4958 if (treg == 0)
4959 {
4960 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4961 break;
4962 }
4963 if (sreg == 0)
4964 {
4965 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4966 break;
4967 }
4968 used_at = 1;
4969 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4970 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4971 break;
4972
4973 case M_BLTUL:
4974 likely = 1;
4975 case M_BLTU:
4976 if (treg == 0)
4977 goto do_false;
4978 if (sreg == 0)
4979 {
4980 macro_build (&offset_expr, likely ? "bnel" : "bne",
4981 "s,t,p", 0, treg);
4982 break;
4983 }
4984 used_at = 1;
4985 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4986 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4987 break;
4988
4989 case M_DEXT:
4990 {
4991 unsigned long pos;
4992 unsigned long size;
4993
4994 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4995 {
4996 as_bad (_("Unsupported large constant"));
4997 pos = size = 1;
4998 }
4999 else
5000 {
5001 pos = (unsigned long) imm_expr.X_add_number;
5002 size = (unsigned long) imm2_expr.X_add_number;
5003 }
5004
5005 if (pos > 63)
5006 {
5007 as_bad (_("Improper position (%lu)"), pos);
5008 pos = 1;
5009 }
5010 if (size == 0 || size > 64
5011 || (pos + size - 1) > 63)
5012 {
5013 as_bad (_("Improper extract size (%lu, position %lu)"),
5014 size, pos);
5015 size = 1;
5016 }
5017
5018 if (size <= 32 && pos < 32)
5019 {
5020 s = "dext";
5021 fmt = "t,r,+A,+C";
5022 }
5023 else if (size <= 32)
5024 {
5025 s = "dextu";
5026 fmt = "t,r,+E,+H";
5027 }
5028 else
5029 {
5030 s = "dextm";
5031 fmt = "t,r,+A,+G";
5032 }
5033 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5034 }
5035 break;
5036
5037 case M_DINS:
5038 {
5039 unsigned long pos;
5040 unsigned long size;
5041
5042 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5043 {
5044 as_bad (_("Unsupported large constant"));
5045 pos = size = 1;
5046 }
5047 else
5048 {
5049 pos = (unsigned long) imm_expr.X_add_number;
5050 size = (unsigned long) imm2_expr.X_add_number;
5051 }
5052
5053 if (pos > 63)
5054 {
5055 as_bad (_("Improper position (%lu)"), pos);
5056 pos = 1;
5057 }
5058 if (size == 0 || size > 64
5059 || (pos + size - 1) > 63)
5060 {
5061 as_bad (_("Improper insert size (%lu, position %lu)"),
5062 size, pos);
5063 size = 1;
5064 }
5065
5066 if (pos < 32 && (pos + size - 1) < 32)
5067 {
5068 s = "dins";
5069 fmt = "t,r,+A,+B";
5070 }
5071 else if (pos >= 32)
5072 {
5073 s = "dinsu";
5074 fmt = "t,r,+E,+F";
5075 }
5076 else
5077 {
5078 s = "dinsm";
5079 fmt = "t,r,+A,+F";
5080 }
5081 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
5082 pos + size - 1);
5083 }
5084 break;
5085
5086 case M_DDIV_3:
5087 dbl = 1;
5088 case M_DIV_3:
5089 s = "mflo";
5090 goto do_div3;
5091 case M_DREM_3:
5092 dbl = 1;
5093 case M_REM_3:
5094 s = "mfhi";
5095 do_div3:
5096 if (treg == 0)
5097 {
5098 as_warn (_("Divide by zero."));
5099 if (mips_trap)
5100 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5101 else
5102 macro_build (NULL, "break", "c", 7);
5103 break;
5104 }
5105
5106 start_noreorder ();
5107 if (mips_trap)
5108 {
5109 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5110 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5111 }
5112 else
5113 {
5114 expr1.X_add_number = 8;
5115 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5116 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5117 macro_build (NULL, "break", "c", 7);
5118 }
5119 expr1.X_add_number = -1;
5120 used_at = 1;
5121 load_register (AT, &expr1, dbl);
5122 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5123 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5124 if (dbl)
5125 {
5126 expr1.X_add_number = 1;
5127 load_register (AT, &expr1, dbl);
5128 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5129 }
5130 else
5131 {
5132 expr1.X_add_number = 0x80000000;
5133 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5134 }
5135 if (mips_trap)
5136 {
5137 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5138 /* We want to close the noreorder block as soon as possible, so
5139 that later insns are available for delay slot filling. */
5140 end_noreorder ();
5141 }
5142 else
5143 {
5144 expr1.X_add_number = 8;
5145 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5146 macro_build (NULL, "nop", "", 0);
5147
5148 /* We want to close the noreorder block as soon as possible, so
5149 that later insns are available for delay slot filling. */
5150 end_noreorder ();
5151
5152 macro_build (NULL, "break", "c", 6);
5153 }
5154 macro_build (NULL, s, "d", dreg);
5155 break;
5156
5157 case M_DIV_3I:
5158 s = "div";
5159 s2 = "mflo";
5160 goto do_divi;
5161 case M_DIVU_3I:
5162 s = "divu";
5163 s2 = "mflo";
5164 goto do_divi;
5165 case M_REM_3I:
5166 s = "div";
5167 s2 = "mfhi";
5168 goto do_divi;
5169 case M_REMU_3I:
5170 s = "divu";
5171 s2 = "mfhi";
5172 goto do_divi;
5173 case M_DDIV_3I:
5174 dbl = 1;
5175 s = "ddiv";
5176 s2 = "mflo";
5177 goto do_divi;
5178 case M_DDIVU_3I:
5179 dbl = 1;
5180 s = "ddivu";
5181 s2 = "mflo";
5182 goto do_divi;
5183 case M_DREM_3I:
5184 dbl = 1;
5185 s = "ddiv";
5186 s2 = "mfhi";
5187 goto do_divi;
5188 case M_DREMU_3I:
5189 dbl = 1;
5190 s = "ddivu";
5191 s2 = "mfhi";
5192 do_divi:
5193 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5194 {
5195 as_warn (_("Divide by zero."));
5196 if (mips_trap)
5197 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5198 else
5199 macro_build (NULL, "break", "c", 7);
5200 break;
5201 }
5202 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5203 {
5204 if (strcmp (s2, "mflo") == 0)
5205 move_register (dreg, sreg);
5206 else
5207 move_register (dreg, 0);
5208 break;
5209 }
5210 if (imm_expr.X_op == O_constant
5211 && imm_expr.X_add_number == -1
5212 && s[strlen (s) - 1] != 'u')
5213 {
5214 if (strcmp (s2, "mflo") == 0)
5215 {
5216 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5217 }
5218 else
5219 move_register (dreg, 0);
5220 break;
5221 }
5222
5223 used_at = 1;
5224 load_register (AT, &imm_expr, dbl);
5225 macro_build (NULL, s, "z,s,t", sreg, AT);
5226 macro_build (NULL, s2, "d", dreg);
5227 break;
5228
5229 case M_DIVU_3:
5230 s = "divu";
5231 s2 = "mflo";
5232 goto do_divu3;
5233 case M_REMU_3:
5234 s = "divu";
5235 s2 = "mfhi";
5236 goto do_divu3;
5237 case M_DDIVU_3:
5238 s = "ddivu";
5239 s2 = "mflo";
5240 goto do_divu3;
5241 case M_DREMU_3:
5242 s = "ddivu";
5243 s2 = "mfhi";
5244 do_divu3:
5245 start_noreorder ();
5246 if (mips_trap)
5247 {
5248 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5249 macro_build (NULL, s, "z,s,t", sreg, treg);
5250 /* We want to close the noreorder block as soon as possible, so
5251 that later insns are available for delay slot filling. */
5252 end_noreorder ();
5253 }
5254 else
5255 {
5256 expr1.X_add_number = 8;
5257 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5258 macro_build (NULL, s, "z,s,t", sreg, treg);
5259
5260 /* We want to close the noreorder block as soon as possible, so
5261 that later insns are available for delay slot filling. */
5262 end_noreorder ();
5263 macro_build (NULL, "break", "c", 7);
5264 }
5265 macro_build (NULL, s2, "d", dreg);
5266 break;
5267
5268 case M_DLCA_AB:
5269 dbl = 1;
5270 case M_LCA_AB:
5271 call = 1;
5272 goto do_la;
5273 case M_DLA_AB:
5274 dbl = 1;
5275 case M_LA_AB:
5276 do_la:
5277 /* Load the address of a symbol into a register. If breg is not
5278 zero, we then add a base register to it. */
5279
5280 if (dbl && HAVE_32BIT_GPRS)
5281 as_warn (_("dla used to load 32-bit register"));
5282
5283 if (! dbl && HAVE_64BIT_OBJECTS)
5284 as_warn (_("la used to load 64-bit address"));
5285
5286 if (offset_expr.X_op == O_constant
5287 && offset_expr.X_add_number >= -0x8000
5288 && offset_expr.X_add_number < 0x8000)
5289 {
5290 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5291 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5292 break;
5293 }
5294
5295 if (mips_opts.at && (treg == breg))
5296 {
5297 tempreg = AT;
5298 used_at = 1;
5299 }
5300 else
5301 {
5302 tempreg = treg;
5303 }
5304
5305 if (offset_expr.X_op != O_symbol
5306 && offset_expr.X_op != O_constant)
5307 {
5308 as_bad (_("expression too complex"));
5309 offset_expr.X_op = O_constant;
5310 }
5311
5312 if (offset_expr.X_op == O_constant)
5313 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5314 else if (mips_pic == NO_PIC)
5315 {
5316 /* If this is a reference to a GP relative symbol, we want
5317 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5318 Otherwise we want
5319 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5320 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5321 If we have a constant, we need two instructions anyhow,
5322 so we may as well always use the latter form.
5323
5324 With 64bit address space and a usable $at we want
5325 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5326 lui $at,<sym> (BFD_RELOC_HI16_S)
5327 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5328 daddiu $at,<sym> (BFD_RELOC_LO16)
5329 dsll32 $tempreg,0
5330 daddu $tempreg,$tempreg,$at
5331
5332 If $at is already in use, we use a path which is suboptimal
5333 on superscalar processors.
5334 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5335 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5336 dsll $tempreg,16
5337 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5338 dsll $tempreg,16
5339 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5340
5341 For GP relative symbols in 64bit address space we can use
5342 the same sequence as in 32bit address space. */
5343 if (HAVE_64BIT_SYMBOLS)
5344 {
5345 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5346 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5347 {
5348 relax_start (offset_expr.X_add_symbol);
5349 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5350 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5351 relax_switch ();
5352 }
5353
5354 if (used_at == 0 && mips_opts.at)
5355 {
5356 macro_build (&offset_expr, "lui", "t,u",
5357 tempreg, BFD_RELOC_MIPS_HIGHEST);
5358 macro_build (&offset_expr, "lui", "t,u",
5359 AT, BFD_RELOC_HI16_S);
5360 macro_build (&offset_expr, "daddiu", "t,r,j",
5361 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5362 macro_build (&offset_expr, "daddiu", "t,r,j",
5363 AT, AT, BFD_RELOC_LO16);
5364 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5365 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5366 used_at = 1;
5367 }
5368 else
5369 {
5370 macro_build (&offset_expr, "lui", "t,u",
5371 tempreg, BFD_RELOC_MIPS_HIGHEST);
5372 macro_build (&offset_expr, "daddiu", "t,r,j",
5373 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5374 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5375 macro_build (&offset_expr, "daddiu", "t,r,j",
5376 tempreg, tempreg, BFD_RELOC_HI16_S);
5377 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5378 macro_build (&offset_expr, "daddiu", "t,r,j",
5379 tempreg, tempreg, BFD_RELOC_LO16);
5380 }
5381
5382 if (mips_relax.sequence)
5383 relax_end ();
5384 }
5385 else
5386 {
5387 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5388 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5389 {
5390 relax_start (offset_expr.X_add_symbol);
5391 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5392 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5393 relax_switch ();
5394 }
5395 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5396 as_bad (_("offset too large"));
5397 macro_build_lui (&offset_expr, tempreg);
5398 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5399 tempreg, tempreg, BFD_RELOC_LO16);
5400 if (mips_relax.sequence)
5401 relax_end ();
5402 }
5403 }
5404 else if (!mips_big_got && !HAVE_NEWABI)
5405 {
5406 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5407
5408 /* If this is a reference to an external symbol, and there
5409 is no constant, we want
5410 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5411 or for lca or if tempreg is PIC_CALL_REG
5412 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5413 For a local symbol, we want
5414 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5415 nop
5416 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5417
5418 If we have a small constant, and this is a reference to
5419 an external symbol, we want
5420 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5421 nop
5422 addiu $tempreg,$tempreg,<constant>
5423 For a local symbol, we want the same instruction
5424 sequence, but we output a BFD_RELOC_LO16 reloc on the
5425 addiu instruction.
5426
5427 If we have a large constant, and this is a reference to
5428 an external symbol, we want
5429 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5430 lui $at,<hiconstant>
5431 addiu $at,$at,<loconstant>
5432 addu $tempreg,$tempreg,$at
5433 For a local symbol, we want the same instruction
5434 sequence, but we output a BFD_RELOC_LO16 reloc on the
5435 addiu instruction.
5436 */
5437
5438 if (offset_expr.X_add_number == 0)
5439 {
5440 if (mips_pic == SVR4_PIC
5441 && breg == 0
5442 && (call || tempreg == PIC_CALL_REG))
5443 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5444
5445 relax_start (offset_expr.X_add_symbol);
5446 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5447 lw_reloc_type, mips_gp_register);
5448 if (breg != 0)
5449 {
5450 /* We're going to put in an addu instruction using
5451 tempreg, so we may as well insert the nop right
5452 now. */
5453 load_delay_nop ();
5454 }
5455 relax_switch ();
5456 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5457 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5458 load_delay_nop ();
5459 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5460 tempreg, tempreg, BFD_RELOC_LO16);
5461 relax_end ();
5462 /* FIXME: If breg == 0, and the next instruction uses
5463 $tempreg, then if this variant case is used an extra
5464 nop will be generated. */
5465 }
5466 else if (offset_expr.X_add_number >= -0x8000
5467 && offset_expr.X_add_number < 0x8000)
5468 {
5469 load_got_offset (tempreg, &offset_expr);
5470 load_delay_nop ();
5471 add_got_offset (tempreg, &offset_expr);
5472 }
5473 else
5474 {
5475 expr1.X_add_number = offset_expr.X_add_number;
5476 offset_expr.X_add_number =
5477 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5478 load_got_offset (tempreg, &offset_expr);
5479 offset_expr.X_add_number = expr1.X_add_number;
5480 /* If we are going to add in a base register, and the
5481 target register and the base register are the same,
5482 then we are using AT as a temporary register. Since
5483 we want to load the constant into AT, we add our
5484 current AT (from the global offset table) and the
5485 register into the register now, and pretend we were
5486 not using a base register. */
5487 if (breg == treg)
5488 {
5489 load_delay_nop ();
5490 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5491 treg, AT, breg);
5492 breg = 0;
5493 tempreg = treg;
5494 }
5495 add_got_offset_hilo (tempreg, &offset_expr, AT);
5496 used_at = 1;
5497 }
5498 }
5499 else if (!mips_big_got && HAVE_NEWABI)
5500 {
5501 int add_breg_early = 0;
5502
5503 /* If this is a reference to an external, and there is no
5504 constant, or local symbol (*), with or without a
5505 constant, we want
5506 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5507 or for lca or if tempreg is PIC_CALL_REG
5508 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5509
5510 If we have a small constant, and this is a reference to
5511 an external symbol, we want
5512 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5513 addiu $tempreg,$tempreg,<constant>
5514
5515 If we have a large constant, and this is a reference to
5516 an external symbol, we want
5517 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5518 lui $at,<hiconstant>
5519 addiu $at,$at,<loconstant>
5520 addu $tempreg,$tempreg,$at
5521
5522 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5523 local symbols, even though it introduces an additional
5524 instruction. */
5525
5526 if (offset_expr.X_add_number)
5527 {
5528 expr1.X_add_number = offset_expr.X_add_number;
5529 offset_expr.X_add_number = 0;
5530
5531 relax_start (offset_expr.X_add_symbol);
5532 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5533 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5534
5535 if (expr1.X_add_number >= -0x8000
5536 && expr1.X_add_number < 0x8000)
5537 {
5538 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5539 tempreg, tempreg, BFD_RELOC_LO16);
5540 }
5541 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5542 {
5543 int dreg;
5544
5545 /* If we are going to add in a base register, and the
5546 target register and the base register are the same,
5547 then we are using AT as a temporary register. Since
5548 we want to load the constant into AT, we add our
5549 current AT (from the global offset table) and the
5550 register into the register now, and pretend we were
5551 not using a base register. */
5552 if (breg != treg)
5553 dreg = tempreg;
5554 else
5555 {
5556 assert (tempreg == AT);
5557 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5558 treg, AT, breg);
5559 dreg = treg;
5560 add_breg_early = 1;
5561 }
5562
5563 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5565 dreg, dreg, AT);
5566
5567 used_at = 1;
5568 }
5569 else
5570 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5571
5572 relax_switch ();
5573 offset_expr.X_add_number = expr1.X_add_number;
5574
5575 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5576 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5577 if (add_breg_early)
5578 {
5579 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5580 treg, tempreg, breg);
5581 breg = 0;
5582 tempreg = treg;
5583 }
5584 relax_end ();
5585 }
5586 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5587 {
5588 relax_start (offset_expr.X_add_symbol);
5589 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5590 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5591 relax_switch ();
5592 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5593 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5594 relax_end ();
5595 }
5596 else
5597 {
5598 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5599 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5600 }
5601 }
5602 else if (mips_big_got && !HAVE_NEWABI)
5603 {
5604 int gpdelay;
5605 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5606 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5607 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5608
5609 /* This is the large GOT case. If this is a reference to an
5610 external symbol, and there is no constant, we want
5611 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5612 addu $tempreg,$tempreg,$gp
5613 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5614 or for lca or if tempreg is PIC_CALL_REG
5615 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5616 addu $tempreg,$tempreg,$gp
5617 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5618 For a local symbol, we want
5619 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5620 nop
5621 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5622
5623 If we have a small constant, and this is a reference to
5624 an external symbol, we want
5625 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5626 addu $tempreg,$tempreg,$gp
5627 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5628 nop
5629 addiu $tempreg,$tempreg,<constant>
5630 For a local symbol, we want
5631 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5632 nop
5633 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5634
5635 If we have a large constant, and this is a reference to
5636 an external symbol, we want
5637 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5638 addu $tempreg,$tempreg,$gp
5639 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5640 lui $at,<hiconstant>
5641 addiu $at,$at,<loconstant>
5642 addu $tempreg,$tempreg,$at
5643 For a local symbol, we want
5644 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5645 lui $at,<hiconstant>
5646 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5647 addu $tempreg,$tempreg,$at
5648 */
5649
5650 expr1.X_add_number = offset_expr.X_add_number;
5651 offset_expr.X_add_number = 0;
5652 relax_start (offset_expr.X_add_symbol);
5653 gpdelay = reg_needs_delay (mips_gp_register);
5654 if (expr1.X_add_number == 0 && breg == 0
5655 && (call || tempreg == PIC_CALL_REG))
5656 {
5657 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5658 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5659 }
5660 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5661 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5662 tempreg, tempreg, mips_gp_register);
5663 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5664 tempreg, lw_reloc_type, tempreg);
5665 if (expr1.X_add_number == 0)
5666 {
5667 if (breg != 0)
5668 {
5669 /* We're going to put in an addu instruction using
5670 tempreg, so we may as well insert the nop right
5671 now. */
5672 load_delay_nop ();
5673 }
5674 }
5675 else if (expr1.X_add_number >= -0x8000
5676 && expr1.X_add_number < 0x8000)
5677 {
5678 load_delay_nop ();
5679 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5680 tempreg, tempreg, BFD_RELOC_LO16);
5681 }
5682 else
5683 {
5684 int dreg;
5685
5686 /* If we are going to add in a base register, and the
5687 target register and the base register are the same,
5688 then we are using AT as a temporary register. Since
5689 we want to load the constant into AT, we add our
5690 current AT (from the global offset table) and the
5691 register into the register now, and pretend we were
5692 not using a base register. */
5693 if (breg != treg)
5694 dreg = tempreg;
5695 else
5696 {
5697 assert (tempreg == AT);
5698 load_delay_nop ();
5699 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5700 treg, AT, breg);
5701 dreg = treg;
5702 }
5703
5704 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5705 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5706
5707 used_at = 1;
5708 }
5709 offset_expr.X_add_number =
5710 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5711 relax_switch ();
5712
5713 if (gpdelay)
5714 {
5715 /* This is needed because this instruction uses $gp, but
5716 the first instruction on the main stream does not. */
5717 macro_build (NULL, "nop", "");
5718 }
5719
5720 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5721 local_reloc_type, mips_gp_register);
5722 if (expr1.X_add_number >= -0x8000
5723 && expr1.X_add_number < 0x8000)
5724 {
5725 load_delay_nop ();
5726 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5727 tempreg, tempreg, BFD_RELOC_LO16);
5728 /* FIXME: If add_number is 0, and there was no base
5729 register, the external symbol case ended with a load,
5730 so if the symbol turns out to not be external, and
5731 the next instruction uses tempreg, an unnecessary nop
5732 will be inserted. */
5733 }
5734 else
5735 {
5736 if (breg == treg)
5737 {
5738 /* We must add in the base register now, as in the
5739 external symbol case. */
5740 assert (tempreg == AT);
5741 load_delay_nop ();
5742 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5743 treg, AT, breg);
5744 tempreg = treg;
5745 /* We set breg to 0 because we have arranged to add
5746 it in in both cases. */
5747 breg = 0;
5748 }
5749
5750 macro_build_lui (&expr1, AT);
5751 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5752 AT, AT, BFD_RELOC_LO16);
5753 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5754 tempreg, tempreg, AT);
5755 used_at = 1;
5756 }
5757 relax_end ();
5758 }
5759 else if (mips_big_got && HAVE_NEWABI)
5760 {
5761 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5762 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5763 int add_breg_early = 0;
5764
5765 /* This is the large GOT case. If this is a reference to an
5766 external symbol, and there is no constant, we want
5767 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5768 add $tempreg,$tempreg,$gp
5769 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5770 or for lca or if tempreg is PIC_CALL_REG
5771 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5772 add $tempreg,$tempreg,$gp
5773 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5774
5775 If we have a small constant, and this is a reference to
5776 an external symbol, we want
5777 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5778 add $tempreg,$tempreg,$gp
5779 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5780 addi $tempreg,$tempreg,<constant>
5781
5782 If we have a large constant, and this is a reference to
5783 an external symbol, we want
5784 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5785 addu $tempreg,$tempreg,$gp
5786 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5787 lui $at,<hiconstant>
5788 addi $at,$at,<loconstant>
5789 add $tempreg,$tempreg,$at
5790
5791 If we have NewABI, and we know it's a local symbol, we want
5792 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5793 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5794 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5795
5796 relax_start (offset_expr.X_add_symbol);
5797
5798 expr1.X_add_number = offset_expr.X_add_number;
5799 offset_expr.X_add_number = 0;
5800
5801 if (expr1.X_add_number == 0 && breg == 0
5802 && (call || tempreg == PIC_CALL_REG))
5803 {
5804 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5805 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5806 }
5807 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5808 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5809 tempreg, tempreg, mips_gp_register);
5810 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5811 tempreg, lw_reloc_type, tempreg);
5812
5813 if (expr1.X_add_number == 0)
5814 ;
5815 else if (expr1.X_add_number >= -0x8000
5816 && expr1.X_add_number < 0x8000)
5817 {
5818 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5819 tempreg, tempreg, BFD_RELOC_LO16);
5820 }
5821 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5822 {
5823 int dreg;
5824
5825 /* If we are going to add in a base register, and the
5826 target register and the base register are the same,
5827 then we are using AT as a temporary register. Since
5828 we want to load the constant into AT, we add our
5829 current AT (from the global offset table) and the
5830 register into the register now, and pretend we were
5831 not using a base register. */
5832 if (breg != treg)
5833 dreg = tempreg;
5834 else
5835 {
5836 assert (tempreg == AT);
5837 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5838 treg, AT, breg);
5839 dreg = treg;
5840 add_breg_early = 1;
5841 }
5842
5843 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5844 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5845
5846 used_at = 1;
5847 }
5848 else
5849 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5850
5851 relax_switch ();
5852 offset_expr.X_add_number = expr1.X_add_number;
5853 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5854 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5855 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5856 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5857 if (add_breg_early)
5858 {
5859 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5860 treg, tempreg, breg);
5861 breg = 0;
5862 tempreg = treg;
5863 }
5864 relax_end ();
5865 }
5866 else
5867 abort ();
5868
5869 if (breg != 0)
5870 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
5871 break;
5872
5873 case M_J_A:
5874 /* The j instruction may not be used in PIC code, since it
5875 requires an absolute address. We convert it to a b
5876 instruction. */
5877 if (mips_pic == NO_PIC)
5878 macro_build (&offset_expr, "j", "a");
5879 else
5880 macro_build (&offset_expr, "b", "p");
5881 break;
5882
5883 /* The jal instructions must be handled as macros because when
5884 generating PIC code they expand to multi-instruction
5885 sequences. Normally they are simple instructions. */
5886 case M_JAL_1:
5887 dreg = RA;
5888 /* Fall through. */
5889 case M_JAL_2:
5890 if (mips_pic == NO_PIC)
5891 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5892 else
5893 {
5894 if (sreg != PIC_CALL_REG)
5895 as_warn (_("MIPS PIC call to register other than $25"));
5896
5897 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5898 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
5899 {
5900 if (mips_cprestore_offset < 0)
5901 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5902 else
5903 {
5904 if (! mips_frame_reg_valid)
5905 {
5906 as_warn (_("No .frame pseudo-op used in PIC code"));
5907 /* Quiet this warning. */
5908 mips_frame_reg_valid = 1;
5909 }
5910 if (! mips_cprestore_valid)
5911 {
5912 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5913 /* Quiet this warning. */
5914 mips_cprestore_valid = 1;
5915 }
5916 expr1.X_add_number = mips_cprestore_offset;
5917 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5918 mips_gp_register,
5919 mips_frame_reg,
5920 HAVE_64BIT_ADDRESSES);
5921 }
5922 }
5923 }
5924
5925 break;
5926
5927 case M_JAL_A:
5928 if (mips_pic == NO_PIC)
5929 macro_build (&offset_expr, "jal", "a");
5930 else if (mips_pic == SVR4_PIC)
5931 {
5932 /* If this is a reference to an external symbol, and we are
5933 using a small GOT, we want
5934 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5935 nop
5936 jalr $ra,$25
5937 nop
5938 lw $gp,cprestore($sp)
5939 The cprestore value is set using the .cprestore
5940 pseudo-op. If we are using a big GOT, we want
5941 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5942 addu $25,$25,$gp
5943 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5944 nop
5945 jalr $ra,$25
5946 nop
5947 lw $gp,cprestore($sp)
5948 If the symbol is not external, we want
5949 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5950 nop
5951 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5952 jalr $ra,$25
5953 nop
5954 lw $gp,cprestore($sp)
5955
5956 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5957 sequences above, minus nops, unless the symbol is local,
5958 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5959 GOT_DISP. */
5960 if (HAVE_NEWABI)
5961 {
5962 if (! mips_big_got)
5963 {
5964 relax_start (offset_expr.X_add_symbol);
5965 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5966 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5967 mips_gp_register);
5968 relax_switch ();
5969 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5970 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5971 mips_gp_register);
5972 relax_end ();
5973 }
5974 else
5975 {
5976 relax_start (offset_expr.X_add_symbol);
5977 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5978 BFD_RELOC_MIPS_CALL_HI16);
5979 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5980 PIC_CALL_REG, mips_gp_register);
5981 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5982 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5983 PIC_CALL_REG);
5984 relax_switch ();
5985 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5986 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5987 mips_gp_register);
5988 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5989 PIC_CALL_REG, PIC_CALL_REG,
5990 BFD_RELOC_MIPS_GOT_OFST);
5991 relax_end ();
5992 }
5993
5994 macro_build_jalr (&offset_expr);
5995 }
5996 else
5997 {
5998 relax_start (offset_expr.X_add_symbol);
5999 if (! mips_big_got)
6000 {
6001 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6002 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6003 mips_gp_register);
6004 load_delay_nop ();
6005 relax_switch ();
6006 }
6007 else
6008 {
6009 int gpdelay;
6010
6011 gpdelay = reg_needs_delay (mips_gp_register);
6012 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6013 BFD_RELOC_MIPS_CALL_HI16);
6014 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6015 PIC_CALL_REG, mips_gp_register);
6016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6017 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6018 PIC_CALL_REG);
6019 load_delay_nop ();
6020 relax_switch ();
6021 if (gpdelay)
6022 macro_build (NULL, "nop", "");
6023 }
6024 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6025 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6026 mips_gp_register);
6027 load_delay_nop ();
6028 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6029 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6030 relax_end ();
6031 macro_build_jalr (&offset_expr);
6032
6033 if (mips_cprestore_offset < 0)
6034 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6035 else
6036 {
6037 if (! mips_frame_reg_valid)
6038 {
6039 as_warn (_("No .frame pseudo-op used in PIC code"));
6040 /* Quiet this warning. */
6041 mips_frame_reg_valid = 1;
6042 }
6043 if (! mips_cprestore_valid)
6044 {
6045 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6046 /* Quiet this warning. */
6047 mips_cprestore_valid = 1;
6048 }
6049 if (mips_opts.noreorder)
6050 macro_build (NULL, "nop", "");
6051 expr1.X_add_number = mips_cprestore_offset;
6052 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6053 mips_gp_register,
6054 mips_frame_reg,
6055 HAVE_64BIT_ADDRESSES);
6056 }
6057 }
6058 }
6059 else if (mips_pic == VXWORKS_PIC)
6060 as_bad (_("Non-PIC jump used in PIC library"));
6061 else
6062 abort ();
6063
6064 break;
6065
6066 case M_LB_AB:
6067 s = "lb";
6068 goto ld;
6069 case M_LBU_AB:
6070 s = "lbu";
6071 goto ld;
6072 case M_LH_AB:
6073 s = "lh";
6074 goto ld;
6075 case M_LHU_AB:
6076 s = "lhu";
6077 goto ld;
6078 case M_LW_AB:
6079 s = "lw";
6080 goto ld;
6081 case M_LWC0_AB:
6082 s = "lwc0";
6083 /* Itbl support may require additional care here. */
6084 coproc = 1;
6085 goto ld;
6086 case M_LWC1_AB:
6087 s = "lwc1";
6088 /* Itbl support may require additional care here. */
6089 coproc = 1;
6090 goto ld;
6091 case M_LWC2_AB:
6092 s = "lwc2";
6093 /* Itbl support may require additional care here. */
6094 coproc = 1;
6095 goto ld;
6096 case M_LWC3_AB:
6097 s = "lwc3";
6098 /* Itbl support may require additional care here. */
6099 coproc = 1;
6100 goto ld;
6101 case M_LWL_AB:
6102 s = "lwl";
6103 lr = 1;
6104 goto ld;
6105 case M_LWR_AB:
6106 s = "lwr";
6107 lr = 1;
6108 goto ld;
6109 case M_LDC1_AB:
6110 if (mips_opts.arch == CPU_R4650)
6111 {
6112 as_bad (_("opcode not supported on this processor"));
6113 break;
6114 }
6115 s = "ldc1";
6116 /* Itbl support may require additional care here. */
6117 coproc = 1;
6118 goto ld;
6119 case M_LDC2_AB:
6120 s = "ldc2";
6121 /* Itbl support may require additional care here. */
6122 coproc = 1;
6123 goto ld;
6124 case M_LDC3_AB:
6125 s = "ldc3";
6126 /* Itbl support may require additional care here. */
6127 coproc = 1;
6128 goto ld;
6129 case M_LDL_AB:
6130 s = "ldl";
6131 lr = 1;
6132 goto ld;
6133 case M_LDR_AB:
6134 s = "ldr";
6135 lr = 1;
6136 goto ld;
6137 case M_LL_AB:
6138 s = "ll";
6139 goto ld;
6140 case M_LLD_AB:
6141 s = "lld";
6142 goto ld;
6143 case M_LWU_AB:
6144 s = "lwu";
6145 ld:
6146 if (breg == treg || coproc || lr)
6147 {
6148 tempreg = AT;
6149 used_at = 1;
6150 }
6151 else
6152 {
6153 tempreg = treg;
6154 }
6155 goto ld_st;
6156 case M_SB_AB:
6157 s = "sb";
6158 goto st;
6159 case M_SH_AB:
6160 s = "sh";
6161 goto st;
6162 case M_SW_AB:
6163 s = "sw";
6164 goto st;
6165 case M_SWC0_AB:
6166 s = "swc0";
6167 /* Itbl support may require additional care here. */
6168 coproc = 1;
6169 goto st;
6170 case M_SWC1_AB:
6171 s = "swc1";
6172 /* Itbl support may require additional care here. */
6173 coproc = 1;
6174 goto st;
6175 case M_SWC2_AB:
6176 s = "swc2";
6177 /* Itbl support may require additional care here. */
6178 coproc = 1;
6179 goto st;
6180 case M_SWC3_AB:
6181 s = "swc3";
6182 /* Itbl support may require additional care here. */
6183 coproc = 1;
6184 goto st;
6185 case M_SWL_AB:
6186 s = "swl";
6187 goto st;
6188 case M_SWR_AB:
6189 s = "swr";
6190 goto st;
6191 case M_SC_AB:
6192 s = "sc";
6193 goto st;
6194 case M_SCD_AB:
6195 s = "scd";
6196 goto st;
6197 case M_CACHE_AB:
6198 s = "cache";
6199 goto st;
6200 case M_SDC1_AB:
6201 if (mips_opts.arch == CPU_R4650)
6202 {
6203 as_bad (_("opcode not supported on this processor"));
6204 break;
6205 }
6206 s = "sdc1";
6207 coproc = 1;
6208 /* Itbl support may require additional care here. */
6209 goto st;
6210 case M_SDC2_AB:
6211 s = "sdc2";
6212 /* Itbl support may require additional care here. */
6213 coproc = 1;
6214 goto st;
6215 case M_SDC3_AB:
6216 s = "sdc3";
6217 /* Itbl support may require additional care here. */
6218 coproc = 1;
6219 goto st;
6220 case M_SDL_AB:
6221 s = "sdl";
6222 goto st;
6223 case M_SDR_AB:
6224 s = "sdr";
6225 st:
6226 tempreg = AT;
6227 used_at = 1;
6228 ld_st:
6229 /* Itbl support may require additional care here. */
6230 if (mask == M_LWC1_AB
6231 || mask == M_SWC1_AB
6232 || mask == M_LDC1_AB
6233 || mask == M_SDC1_AB
6234 || mask == M_L_DAB
6235 || mask == M_S_DAB)
6236 fmt = "T,o(b)";
6237 else if (mask == M_CACHE_AB)
6238 fmt = "k,o(b)";
6239 else if (coproc)
6240 fmt = "E,o(b)";
6241 else
6242 fmt = "t,o(b)";
6243
6244 if (offset_expr.X_op != O_constant
6245 && offset_expr.X_op != O_symbol)
6246 {
6247 as_bad (_("expression too complex"));
6248 offset_expr.X_op = O_constant;
6249 }
6250
6251 if (HAVE_32BIT_ADDRESSES
6252 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6253 {
6254 char value [32];
6255
6256 sprintf_vma (value, offset_expr.X_add_number);
6257 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6258 }
6259
6260 /* A constant expression in PIC code can be handled just as it
6261 is in non PIC code. */
6262 if (offset_expr.X_op == O_constant)
6263 {
6264 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6265 & ~(bfd_vma) 0xffff);
6266 normalize_address_expr (&expr1);
6267 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6268 if (breg != 0)
6269 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6270 tempreg, tempreg, breg);
6271 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6272 }
6273 else if (mips_pic == NO_PIC)
6274 {
6275 /* If this is a reference to a GP relative symbol, and there
6276 is no base register, we want
6277 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6278 Otherwise, if there is no base register, we want
6279 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6280 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6281 If we have a constant, we need two instructions anyhow,
6282 so we always use the latter form.
6283
6284 If we have a base register, and this is a reference to a
6285 GP relative symbol, we want
6286 addu $tempreg,$breg,$gp
6287 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6288 Otherwise we want
6289 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6290 addu $tempreg,$tempreg,$breg
6291 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6292 With a constant we always use the latter case.
6293
6294 With 64bit address space and no base register and $at usable,
6295 we want
6296 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6297 lui $at,<sym> (BFD_RELOC_HI16_S)
6298 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6299 dsll32 $tempreg,0
6300 daddu $tempreg,$at
6301 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6302 If we have a base register, we want
6303 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6304 lui $at,<sym> (BFD_RELOC_HI16_S)
6305 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6306 daddu $at,$breg
6307 dsll32 $tempreg,0
6308 daddu $tempreg,$at
6309 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6310
6311 Without $at we can't generate the optimal path for superscalar
6312 processors here since this would require two temporary registers.
6313 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6314 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6315 dsll $tempreg,16
6316 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6317 dsll $tempreg,16
6318 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6319 If we have a base register, we want
6320 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6321 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6322 dsll $tempreg,16
6323 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6324 dsll $tempreg,16
6325 daddu $tempreg,$tempreg,$breg
6326 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6327
6328 For GP relative symbols in 64bit address space we can use
6329 the same sequence as in 32bit address space. */
6330 if (HAVE_64BIT_SYMBOLS)
6331 {
6332 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6333 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6334 {
6335 relax_start (offset_expr.X_add_symbol);
6336 if (breg == 0)
6337 {
6338 macro_build (&offset_expr, s, fmt, treg,
6339 BFD_RELOC_GPREL16, mips_gp_register);
6340 }
6341 else
6342 {
6343 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6344 tempreg, breg, mips_gp_register);
6345 macro_build (&offset_expr, s, fmt, treg,
6346 BFD_RELOC_GPREL16, tempreg);
6347 }
6348 relax_switch ();
6349 }
6350
6351 if (used_at == 0 && mips_opts.at)
6352 {
6353 macro_build (&offset_expr, "lui", "t,u", tempreg,
6354 BFD_RELOC_MIPS_HIGHEST);
6355 macro_build (&offset_expr, "lui", "t,u", AT,
6356 BFD_RELOC_HI16_S);
6357 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6358 tempreg, BFD_RELOC_MIPS_HIGHER);
6359 if (breg != 0)
6360 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6361 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6362 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6363 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6364 tempreg);
6365 used_at = 1;
6366 }
6367 else
6368 {
6369 macro_build (&offset_expr, "lui", "t,u", tempreg,
6370 BFD_RELOC_MIPS_HIGHEST);
6371 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6372 tempreg, BFD_RELOC_MIPS_HIGHER);
6373 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6374 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6375 tempreg, BFD_RELOC_HI16_S);
6376 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6377 if (breg != 0)
6378 macro_build (NULL, "daddu", "d,v,t",
6379 tempreg, tempreg, breg);
6380 macro_build (&offset_expr, s, fmt, treg,
6381 BFD_RELOC_LO16, tempreg);
6382 }
6383
6384 if (mips_relax.sequence)
6385 relax_end ();
6386 break;
6387 }
6388
6389 if (breg == 0)
6390 {
6391 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6392 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6393 {
6394 relax_start (offset_expr.X_add_symbol);
6395 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6396 mips_gp_register);
6397 relax_switch ();
6398 }
6399 macro_build_lui (&offset_expr, tempreg);
6400 macro_build (&offset_expr, s, fmt, treg,
6401 BFD_RELOC_LO16, tempreg);
6402 if (mips_relax.sequence)
6403 relax_end ();
6404 }
6405 else
6406 {
6407 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6408 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6409 {
6410 relax_start (offset_expr.X_add_symbol);
6411 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6412 tempreg, breg, mips_gp_register);
6413 macro_build (&offset_expr, s, fmt, treg,
6414 BFD_RELOC_GPREL16, tempreg);
6415 relax_switch ();
6416 }
6417 macro_build_lui (&offset_expr, tempreg);
6418 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6419 tempreg, tempreg, breg);
6420 macro_build (&offset_expr, s, fmt, treg,
6421 BFD_RELOC_LO16, tempreg);
6422 if (mips_relax.sequence)
6423 relax_end ();
6424 }
6425 }
6426 else if (!mips_big_got)
6427 {
6428 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6429
6430 /* If this is a reference to an external symbol, we want
6431 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6432 nop
6433 <op> $treg,0($tempreg)
6434 Otherwise we want
6435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6436 nop
6437 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6438 <op> $treg,0($tempreg)
6439
6440 For NewABI, we want
6441 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6442 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6443
6444 If there is a base register, we add it to $tempreg before
6445 the <op>. If there is a constant, we stick it in the
6446 <op> instruction. We don't handle constants larger than
6447 16 bits, because we have no way to load the upper 16 bits
6448 (actually, we could handle them for the subset of cases
6449 in which we are not using $at). */
6450 assert (offset_expr.X_op == O_symbol);
6451 if (HAVE_NEWABI)
6452 {
6453 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6454 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6455 if (breg != 0)
6456 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6457 tempreg, tempreg, breg);
6458 macro_build (&offset_expr, s, fmt, treg,
6459 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6460 break;
6461 }
6462 expr1.X_add_number = offset_expr.X_add_number;
6463 offset_expr.X_add_number = 0;
6464 if (expr1.X_add_number < -0x8000
6465 || expr1.X_add_number >= 0x8000)
6466 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6467 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6468 lw_reloc_type, mips_gp_register);
6469 load_delay_nop ();
6470 relax_start (offset_expr.X_add_symbol);
6471 relax_switch ();
6472 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6473 tempreg, BFD_RELOC_LO16);
6474 relax_end ();
6475 if (breg != 0)
6476 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6477 tempreg, tempreg, breg);
6478 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6479 }
6480 else if (mips_big_got && !HAVE_NEWABI)
6481 {
6482 int gpdelay;
6483
6484 /* If this is a reference to an external symbol, we want
6485 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6486 addu $tempreg,$tempreg,$gp
6487 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6488 <op> $treg,0($tempreg)
6489 Otherwise we want
6490 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6491 nop
6492 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6493 <op> $treg,0($tempreg)
6494 If there is a base register, we add it to $tempreg before
6495 the <op>. If there is a constant, we stick it in the
6496 <op> instruction. We don't handle constants larger than
6497 16 bits, because we have no way to load the upper 16 bits
6498 (actually, we could handle them for the subset of cases
6499 in which we are not using $at). */
6500 assert (offset_expr.X_op == O_symbol);
6501 expr1.X_add_number = offset_expr.X_add_number;
6502 offset_expr.X_add_number = 0;
6503 if (expr1.X_add_number < -0x8000
6504 || expr1.X_add_number >= 0x8000)
6505 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6506 gpdelay = reg_needs_delay (mips_gp_register);
6507 relax_start (offset_expr.X_add_symbol);
6508 macro_build (&offset_expr, "lui", "t,u", tempreg,
6509 BFD_RELOC_MIPS_GOT_HI16);
6510 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6511 mips_gp_register);
6512 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6513 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6514 relax_switch ();
6515 if (gpdelay)
6516 macro_build (NULL, "nop", "");
6517 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6518 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6519 load_delay_nop ();
6520 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6521 tempreg, BFD_RELOC_LO16);
6522 relax_end ();
6523
6524 if (breg != 0)
6525 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6526 tempreg, tempreg, breg);
6527 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6528 }
6529 else if (mips_big_got && HAVE_NEWABI)
6530 {
6531 /* If this is a reference to an external symbol, we want
6532 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6533 add $tempreg,$tempreg,$gp
6534 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6535 <op> $treg,<ofst>($tempreg)
6536 Otherwise, for local symbols, we want:
6537 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6538 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6539 assert (offset_expr.X_op == O_symbol);
6540 expr1.X_add_number = offset_expr.X_add_number;
6541 offset_expr.X_add_number = 0;
6542 if (expr1.X_add_number < -0x8000
6543 || expr1.X_add_number >= 0x8000)
6544 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6545 relax_start (offset_expr.X_add_symbol);
6546 macro_build (&offset_expr, "lui", "t,u", tempreg,
6547 BFD_RELOC_MIPS_GOT_HI16);
6548 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6549 mips_gp_register);
6550 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6551 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6552 if (breg != 0)
6553 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6554 tempreg, tempreg, breg);
6555 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6556
6557 relax_switch ();
6558 offset_expr.X_add_number = expr1.X_add_number;
6559 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6560 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6561 if (breg != 0)
6562 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6563 tempreg, tempreg, breg);
6564 macro_build (&offset_expr, s, fmt, treg,
6565 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6566 relax_end ();
6567 }
6568 else
6569 abort ();
6570
6571 break;
6572
6573 case M_LI:
6574 case M_LI_S:
6575 load_register (treg, &imm_expr, 0);
6576 break;
6577
6578 case M_DLI:
6579 load_register (treg, &imm_expr, 1);
6580 break;
6581
6582 case M_LI_SS:
6583 if (imm_expr.X_op == O_constant)
6584 {
6585 used_at = 1;
6586 load_register (AT, &imm_expr, 0);
6587 macro_build (NULL, "mtc1", "t,G", AT, treg);
6588 break;
6589 }
6590 else
6591 {
6592 assert (offset_expr.X_op == O_symbol
6593 && strcmp (segment_name (S_GET_SEGMENT
6594 (offset_expr.X_add_symbol)),
6595 ".lit4") == 0
6596 && offset_expr.X_add_number == 0);
6597 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6598 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6599 break;
6600 }
6601
6602 case M_LI_D:
6603 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6604 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6605 order 32 bits of the value and the low order 32 bits are either
6606 zero or in OFFSET_EXPR. */
6607 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6608 {
6609 if (HAVE_64BIT_GPRS)
6610 load_register (treg, &imm_expr, 1);
6611 else
6612 {
6613 int hreg, lreg;
6614
6615 if (target_big_endian)
6616 {
6617 hreg = treg;
6618 lreg = treg + 1;
6619 }
6620 else
6621 {
6622 hreg = treg + 1;
6623 lreg = treg;
6624 }
6625
6626 if (hreg <= 31)
6627 load_register (hreg, &imm_expr, 0);
6628 if (lreg <= 31)
6629 {
6630 if (offset_expr.X_op == O_absent)
6631 move_register (lreg, 0);
6632 else
6633 {
6634 assert (offset_expr.X_op == O_constant);
6635 load_register (lreg, &offset_expr, 0);
6636 }
6637 }
6638 }
6639 break;
6640 }
6641
6642 /* We know that sym is in the .rdata section. First we get the
6643 upper 16 bits of the address. */
6644 if (mips_pic == NO_PIC)
6645 {
6646 macro_build_lui (&offset_expr, AT);
6647 used_at = 1;
6648 }
6649 else
6650 {
6651 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6652 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6653 used_at = 1;
6654 }
6655
6656 /* Now we load the register(s). */
6657 if (HAVE_64BIT_GPRS)
6658 {
6659 used_at = 1;
6660 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6661 }
6662 else
6663 {
6664 used_at = 1;
6665 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6666 if (treg != RA)
6667 {
6668 /* FIXME: How in the world do we deal with the possible
6669 overflow here? */
6670 offset_expr.X_add_number += 4;
6671 macro_build (&offset_expr, "lw", "t,o(b)",
6672 treg + 1, BFD_RELOC_LO16, AT);
6673 }
6674 }
6675 break;
6676
6677 case M_LI_DD:
6678 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6679 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6680 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6681 the value and the low order 32 bits are either zero or in
6682 OFFSET_EXPR. */
6683 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6684 {
6685 used_at = 1;
6686 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6687 if (HAVE_64BIT_FPRS)
6688 {
6689 assert (HAVE_64BIT_GPRS);
6690 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6691 }
6692 else
6693 {
6694 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6695 if (offset_expr.X_op == O_absent)
6696 macro_build (NULL, "mtc1", "t,G", 0, treg);
6697 else
6698 {
6699 assert (offset_expr.X_op == O_constant);
6700 load_register (AT, &offset_expr, 0);
6701 macro_build (NULL, "mtc1", "t,G", AT, treg);
6702 }
6703 }
6704 break;
6705 }
6706
6707 assert (offset_expr.X_op == O_symbol
6708 && offset_expr.X_add_number == 0);
6709 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6710 if (strcmp (s, ".lit8") == 0)
6711 {
6712 if (mips_opts.isa != ISA_MIPS1)
6713 {
6714 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6715 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6716 break;
6717 }
6718 breg = mips_gp_register;
6719 r = BFD_RELOC_MIPS_LITERAL;
6720 goto dob;
6721 }
6722 else
6723 {
6724 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6725 used_at = 1;
6726 if (mips_pic != NO_PIC)
6727 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6728 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6729 else
6730 {
6731 /* FIXME: This won't work for a 64 bit address. */
6732 macro_build_lui (&offset_expr, AT);
6733 }
6734
6735 if (mips_opts.isa != ISA_MIPS1)
6736 {
6737 macro_build (&offset_expr, "ldc1", "T,o(b)",
6738 treg, BFD_RELOC_LO16, AT);
6739 break;
6740 }
6741 breg = AT;
6742 r = BFD_RELOC_LO16;
6743 goto dob;
6744 }
6745
6746 case M_L_DOB:
6747 if (mips_opts.arch == CPU_R4650)
6748 {
6749 as_bad (_("opcode not supported on this processor"));
6750 break;
6751 }
6752 /* Even on a big endian machine $fn comes before $fn+1. We have
6753 to adjust when loading from memory. */
6754 r = BFD_RELOC_LO16;
6755 dob:
6756 assert (mips_opts.isa == ISA_MIPS1);
6757 macro_build (&offset_expr, "lwc1", "T,o(b)",
6758 target_big_endian ? treg + 1 : treg, r, breg);
6759 /* FIXME: A possible overflow which I don't know how to deal
6760 with. */
6761 offset_expr.X_add_number += 4;
6762 macro_build (&offset_expr, "lwc1", "T,o(b)",
6763 target_big_endian ? treg : treg + 1, r, breg);
6764 break;
6765
6766 case M_L_DAB:
6767 /*
6768 * The MIPS assembler seems to check for X_add_number not
6769 * being double aligned and generating:
6770 * lui at,%hi(foo+1)
6771 * addu at,at,v1
6772 * addiu at,at,%lo(foo+1)
6773 * lwc1 f2,0(at)
6774 * lwc1 f3,4(at)
6775 * But, the resulting address is the same after relocation so why
6776 * generate the extra instruction?
6777 */
6778 if (mips_opts.arch == CPU_R4650)
6779 {
6780 as_bad (_("opcode not supported on this processor"));
6781 break;
6782 }
6783 /* Itbl support may require additional care here. */
6784 coproc = 1;
6785 if (mips_opts.isa != ISA_MIPS1)
6786 {
6787 s = "ldc1";
6788 goto ld;
6789 }
6790
6791 s = "lwc1";
6792 fmt = "T,o(b)";
6793 goto ldd_std;
6794
6795 case M_S_DAB:
6796 if (mips_opts.arch == CPU_R4650)
6797 {
6798 as_bad (_("opcode not supported on this processor"));
6799 break;
6800 }
6801
6802 if (mips_opts.isa != ISA_MIPS1)
6803 {
6804 s = "sdc1";
6805 goto st;
6806 }
6807
6808 s = "swc1";
6809 fmt = "T,o(b)";
6810 /* Itbl support may require additional care here. */
6811 coproc = 1;
6812 goto ldd_std;
6813
6814 case M_LD_AB:
6815 if (HAVE_64BIT_GPRS)
6816 {
6817 s = "ld";
6818 goto ld;
6819 }
6820
6821 s = "lw";
6822 fmt = "t,o(b)";
6823 goto ldd_std;
6824
6825 case M_SD_AB:
6826 if (HAVE_64BIT_GPRS)
6827 {
6828 s = "sd";
6829 goto st;
6830 }
6831
6832 s = "sw";
6833 fmt = "t,o(b)";
6834
6835 ldd_std:
6836 if (offset_expr.X_op != O_symbol
6837 && offset_expr.X_op != O_constant)
6838 {
6839 as_bad (_("expression too complex"));
6840 offset_expr.X_op = O_constant;
6841 }
6842
6843 if (HAVE_32BIT_ADDRESSES
6844 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6845 {
6846 char value [32];
6847
6848 sprintf_vma (value, offset_expr.X_add_number);
6849 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6850 }
6851
6852 /* Even on a big endian machine $fn comes before $fn+1. We have
6853 to adjust when loading from memory. We set coproc if we must
6854 load $fn+1 first. */
6855 /* Itbl support may require additional care here. */
6856 if (! target_big_endian)
6857 coproc = 0;
6858
6859 if (mips_pic == NO_PIC
6860 || offset_expr.X_op == O_constant)
6861 {
6862 /* If this is a reference to a GP relative symbol, we want
6863 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6864 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6865 If we have a base register, we use this
6866 addu $at,$breg,$gp
6867 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6868 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6869 If this is not a GP relative symbol, we want
6870 lui $at,<sym> (BFD_RELOC_HI16_S)
6871 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6872 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6873 If there is a base register, we add it to $at after the
6874 lui instruction. If there is a constant, we always use
6875 the last case. */
6876 if (offset_expr.X_op == O_symbol
6877 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6878 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6879 {
6880 relax_start (offset_expr.X_add_symbol);
6881 if (breg == 0)
6882 {
6883 tempreg = mips_gp_register;
6884 }
6885 else
6886 {
6887 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6888 AT, breg, mips_gp_register);
6889 tempreg = AT;
6890 used_at = 1;
6891 }
6892
6893 /* Itbl support may require additional care here. */
6894 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6895 BFD_RELOC_GPREL16, tempreg);
6896 offset_expr.X_add_number += 4;
6897
6898 /* Set mips_optimize to 2 to avoid inserting an
6899 undesired nop. */
6900 hold_mips_optimize = mips_optimize;
6901 mips_optimize = 2;
6902 /* Itbl support may require additional care here. */
6903 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6904 BFD_RELOC_GPREL16, tempreg);
6905 mips_optimize = hold_mips_optimize;
6906
6907 relax_switch ();
6908
6909 /* We just generated two relocs. When tc_gen_reloc
6910 handles this case, it will skip the first reloc and
6911 handle the second. The second reloc already has an
6912 extra addend of 4, which we added above. We must
6913 subtract it out, and then subtract another 4 to make
6914 the first reloc come out right. The second reloc
6915 will come out right because we are going to add 4 to
6916 offset_expr when we build its instruction below.
6917
6918 If we have a symbol, then we don't want to include
6919 the offset, because it will wind up being included
6920 when we generate the reloc. */
6921
6922 if (offset_expr.X_op == O_constant)
6923 offset_expr.X_add_number -= 8;
6924 else
6925 {
6926 offset_expr.X_add_number = -4;
6927 offset_expr.X_op = O_constant;
6928 }
6929 }
6930 used_at = 1;
6931 macro_build_lui (&offset_expr, AT);
6932 if (breg != 0)
6933 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6934 /* Itbl support may require additional care here. */
6935 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6936 BFD_RELOC_LO16, AT);
6937 /* FIXME: How do we handle overflow here? */
6938 offset_expr.X_add_number += 4;
6939 /* Itbl support may require additional care here. */
6940 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6941 BFD_RELOC_LO16, AT);
6942 if (mips_relax.sequence)
6943 relax_end ();
6944 }
6945 else if (!mips_big_got)
6946 {
6947 /* If this is a reference to an external symbol, we want
6948 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6949 nop
6950 <op> $treg,0($at)
6951 <op> $treg+1,4($at)
6952 Otherwise we want
6953 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6954 nop
6955 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6956 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6957 If there is a base register we add it to $at before the
6958 lwc1 instructions. If there is a constant we include it
6959 in the lwc1 instructions. */
6960 used_at = 1;
6961 expr1.X_add_number = offset_expr.X_add_number;
6962 if (expr1.X_add_number < -0x8000
6963 || expr1.X_add_number >= 0x8000 - 4)
6964 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6965 load_got_offset (AT, &offset_expr);
6966 load_delay_nop ();
6967 if (breg != 0)
6968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6969
6970 /* Set mips_optimize to 2 to avoid inserting an undesired
6971 nop. */
6972 hold_mips_optimize = mips_optimize;
6973 mips_optimize = 2;
6974
6975 /* Itbl support may require additional care here. */
6976 relax_start (offset_expr.X_add_symbol);
6977 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6978 BFD_RELOC_LO16, AT);
6979 expr1.X_add_number += 4;
6980 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6981 BFD_RELOC_LO16, AT);
6982 relax_switch ();
6983 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6984 BFD_RELOC_LO16, AT);
6985 offset_expr.X_add_number += 4;
6986 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6987 BFD_RELOC_LO16, AT);
6988 relax_end ();
6989
6990 mips_optimize = hold_mips_optimize;
6991 }
6992 else if (mips_big_got)
6993 {
6994 int gpdelay;
6995
6996 /* If this is a reference to an external symbol, we want
6997 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6998 addu $at,$at,$gp
6999 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7000 nop
7001 <op> $treg,0($at)
7002 <op> $treg+1,4($at)
7003 Otherwise we want
7004 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7005 nop
7006 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7007 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7008 If there is a base register we add it to $at before the
7009 lwc1 instructions. If there is a constant we include it
7010 in the lwc1 instructions. */
7011 used_at = 1;
7012 expr1.X_add_number = offset_expr.X_add_number;
7013 offset_expr.X_add_number = 0;
7014 if (expr1.X_add_number < -0x8000
7015 || expr1.X_add_number >= 0x8000 - 4)
7016 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7017 gpdelay = reg_needs_delay (mips_gp_register);
7018 relax_start (offset_expr.X_add_symbol);
7019 macro_build (&offset_expr, "lui", "t,u",
7020 AT, BFD_RELOC_MIPS_GOT_HI16);
7021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7022 AT, AT, mips_gp_register);
7023 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7024 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7025 load_delay_nop ();
7026 if (breg != 0)
7027 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7028 /* Itbl support may require additional care here. */
7029 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7030 BFD_RELOC_LO16, AT);
7031 expr1.X_add_number += 4;
7032
7033 /* Set mips_optimize to 2 to avoid inserting an undesired
7034 nop. */
7035 hold_mips_optimize = mips_optimize;
7036 mips_optimize = 2;
7037 /* Itbl support may require additional care here. */
7038 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7039 BFD_RELOC_LO16, AT);
7040 mips_optimize = hold_mips_optimize;
7041 expr1.X_add_number -= 4;
7042
7043 relax_switch ();
7044 offset_expr.X_add_number = expr1.X_add_number;
7045 if (gpdelay)
7046 macro_build (NULL, "nop", "");
7047 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7048 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7049 load_delay_nop ();
7050 if (breg != 0)
7051 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7052 /* Itbl support may require additional care here. */
7053 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7054 BFD_RELOC_LO16, AT);
7055 offset_expr.X_add_number += 4;
7056
7057 /* Set mips_optimize to 2 to avoid inserting an undesired
7058 nop. */
7059 hold_mips_optimize = mips_optimize;
7060 mips_optimize = 2;
7061 /* Itbl support may require additional care here. */
7062 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7063 BFD_RELOC_LO16, AT);
7064 mips_optimize = hold_mips_optimize;
7065 relax_end ();
7066 }
7067 else
7068 abort ();
7069
7070 break;
7071
7072 case M_LD_OB:
7073 s = "lw";
7074 goto sd_ob;
7075 case M_SD_OB:
7076 s = "sw";
7077 sd_ob:
7078 assert (HAVE_32BIT_ADDRESSES);
7079 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7080 offset_expr.X_add_number += 4;
7081 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7082 break;
7083
7084 /* New code added to support COPZ instructions.
7085 This code builds table entries out of the macros in mip_opcodes.
7086 R4000 uses interlocks to handle coproc delays.
7087 Other chips (like the R3000) require nops to be inserted for delays.
7088
7089 FIXME: Currently, we require that the user handle delays.
7090 In order to fill delay slots for non-interlocked chips,
7091 we must have a way to specify delays based on the coprocessor.
7092 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7093 What are the side-effects of the cop instruction?
7094 What cache support might we have and what are its effects?
7095 Both coprocessor & memory require delays. how long???
7096 What registers are read/set/modified?
7097
7098 If an itbl is provided to interpret cop instructions,
7099 this knowledge can be encoded in the itbl spec. */
7100
7101 case M_COP0:
7102 s = "c0";
7103 goto copz;
7104 case M_COP1:
7105 s = "c1";
7106 goto copz;
7107 case M_COP2:
7108 s = "c2";
7109 goto copz;
7110 case M_COP3:
7111 s = "c3";
7112 copz:
7113 /* For now we just do C (same as Cz). The parameter will be
7114 stored in insn_opcode by mips_ip. */
7115 macro_build (NULL, s, "C", ip->insn_opcode);
7116 break;
7117
7118 case M_MOVE:
7119 move_register (dreg, sreg);
7120 break;
7121
7122 #ifdef LOSING_COMPILER
7123 default:
7124 /* Try and see if this is a new itbl instruction.
7125 This code builds table entries out of the macros in mip_opcodes.
7126 FIXME: For now we just assemble the expression and pass it's
7127 value along as a 32-bit immediate.
7128 We may want to have the assembler assemble this value,
7129 so that we gain the assembler's knowledge of delay slots,
7130 symbols, etc.
7131 Would it be more efficient to use mask (id) here? */
7132 if (itbl_have_entries
7133 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7134 {
7135 s = ip->insn_mo->name;
7136 s2 = "cop3";
7137 coproc = ITBL_DECODE_PNUM (immed_expr);;
7138 macro_build (&immed_expr, s, "C");
7139 break;
7140 }
7141 macro2 (ip);
7142 break;
7143 }
7144 if (!mips_opts.at && used_at)
7145 as_bad (_("Macro used $at after \".set noat\""));
7146 }
7147
7148 static void
7149 macro2 (struct mips_cl_insn *ip)
7150 {
7151 unsigned int treg, sreg, dreg, breg;
7152 unsigned int tempreg;
7153 int mask;
7154 int used_at;
7155 expressionS expr1;
7156 const char *s;
7157 const char *s2;
7158 const char *fmt;
7159 int likely = 0;
7160 int dbl = 0;
7161 int coproc = 0;
7162 int lr = 0;
7163 int imm = 0;
7164 int off;
7165 offsetT maxnum;
7166 bfd_reloc_code_real_type r;
7167
7168 treg = (ip->insn_opcode >> 16) & 0x1f;
7169 dreg = (ip->insn_opcode >> 11) & 0x1f;
7170 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7171 mask = ip->insn_mo->mask;
7172
7173 expr1.X_op = O_constant;
7174 expr1.X_op_symbol = NULL;
7175 expr1.X_add_symbol = NULL;
7176 expr1.X_add_number = 1;
7177
7178 switch (mask)
7179 {
7180 #endif /* LOSING_COMPILER */
7181
7182 case M_DMUL:
7183 dbl = 1;
7184 case M_MUL:
7185 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7186 macro_build (NULL, "mflo", "d", dreg);
7187 break;
7188
7189 case M_DMUL_I:
7190 dbl = 1;
7191 case M_MUL_I:
7192 /* The MIPS assembler some times generates shifts and adds. I'm
7193 not trying to be that fancy. GCC should do this for us
7194 anyway. */
7195 used_at = 1;
7196 load_register (AT, &imm_expr, dbl);
7197 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7198 macro_build (NULL, "mflo", "d", dreg);
7199 break;
7200
7201 case M_DMULO_I:
7202 dbl = 1;
7203 case M_MULO_I:
7204 imm = 1;
7205 goto do_mulo;
7206
7207 case M_DMULO:
7208 dbl = 1;
7209 case M_MULO:
7210 do_mulo:
7211 start_noreorder ();
7212 used_at = 1;
7213 if (imm)
7214 load_register (AT, &imm_expr, dbl);
7215 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7216 macro_build (NULL, "mflo", "d", dreg);
7217 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7218 macro_build (NULL, "mfhi", "d", AT);
7219 if (mips_trap)
7220 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7221 else
7222 {
7223 expr1.X_add_number = 8;
7224 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7225 macro_build (NULL, "nop", "", 0);
7226 macro_build (NULL, "break", "c", 6);
7227 }
7228 end_noreorder ();
7229 macro_build (NULL, "mflo", "d", dreg);
7230 break;
7231
7232 case M_DMULOU_I:
7233 dbl = 1;
7234 case M_MULOU_I:
7235 imm = 1;
7236 goto do_mulou;
7237
7238 case M_DMULOU:
7239 dbl = 1;
7240 case M_MULOU:
7241 do_mulou:
7242 start_noreorder ();
7243 used_at = 1;
7244 if (imm)
7245 load_register (AT, &imm_expr, dbl);
7246 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7247 sreg, imm ? AT : treg);
7248 macro_build (NULL, "mfhi", "d", AT);
7249 macro_build (NULL, "mflo", "d", dreg);
7250 if (mips_trap)
7251 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7252 else
7253 {
7254 expr1.X_add_number = 8;
7255 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7256 macro_build (NULL, "nop", "", 0);
7257 macro_build (NULL, "break", "c", 6);
7258 }
7259 end_noreorder ();
7260 break;
7261
7262 case M_DROL:
7263 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7264 {
7265 if (dreg == sreg)
7266 {
7267 tempreg = AT;
7268 used_at = 1;
7269 }
7270 else
7271 {
7272 tempreg = dreg;
7273 }
7274 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7275 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7276 break;
7277 }
7278 used_at = 1;
7279 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7280 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7281 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7282 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7283 break;
7284
7285 case M_ROL:
7286 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7287 {
7288 if (dreg == sreg)
7289 {
7290 tempreg = AT;
7291 used_at = 1;
7292 }
7293 else
7294 {
7295 tempreg = dreg;
7296 }
7297 macro_build (NULL, "negu", "d,w", tempreg, treg);
7298 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7299 break;
7300 }
7301 used_at = 1;
7302 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7303 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7304 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7305 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7306 break;
7307
7308 case M_DROL_I:
7309 {
7310 unsigned int rot;
7311 char *l, *r;
7312
7313 if (imm_expr.X_op != O_constant)
7314 as_bad (_("Improper rotate count"));
7315 rot = imm_expr.X_add_number & 0x3f;
7316 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7317 {
7318 rot = (64 - rot) & 0x3f;
7319 if (rot >= 32)
7320 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7321 else
7322 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7323 break;
7324 }
7325 if (rot == 0)
7326 {
7327 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7328 break;
7329 }
7330 l = (rot < 0x20) ? "dsll" : "dsll32";
7331 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7332 rot &= 0x1f;
7333 used_at = 1;
7334 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7335 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7336 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7337 }
7338 break;
7339
7340 case M_ROL_I:
7341 {
7342 unsigned int rot;
7343
7344 if (imm_expr.X_op != O_constant)
7345 as_bad (_("Improper rotate count"));
7346 rot = imm_expr.X_add_number & 0x1f;
7347 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7348 {
7349 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7350 break;
7351 }
7352 if (rot == 0)
7353 {
7354 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7355 break;
7356 }
7357 used_at = 1;
7358 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7359 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7360 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7361 }
7362 break;
7363
7364 case M_DROR:
7365 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7366 {
7367 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7368 break;
7369 }
7370 used_at = 1;
7371 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7372 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7373 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7374 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7375 break;
7376
7377 case M_ROR:
7378 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7379 {
7380 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7381 break;
7382 }
7383 used_at = 1;
7384 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7385 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7386 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7387 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7388 break;
7389
7390 case M_DROR_I:
7391 {
7392 unsigned int rot;
7393 char *l, *r;
7394
7395 if (imm_expr.X_op != O_constant)
7396 as_bad (_("Improper rotate count"));
7397 rot = imm_expr.X_add_number & 0x3f;
7398 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7399 {
7400 if (rot >= 32)
7401 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7402 else
7403 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7404 break;
7405 }
7406 if (rot == 0)
7407 {
7408 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7409 break;
7410 }
7411 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7412 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7413 rot &= 0x1f;
7414 used_at = 1;
7415 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7416 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7417 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7418 }
7419 break;
7420
7421 case M_ROR_I:
7422 {
7423 unsigned int rot;
7424
7425 if (imm_expr.X_op != O_constant)
7426 as_bad (_("Improper rotate count"));
7427 rot = imm_expr.X_add_number & 0x1f;
7428 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7429 {
7430 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7431 break;
7432 }
7433 if (rot == 0)
7434 {
7435 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7436 break;
7437 }
7438 used_at = 1;
7439 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7440 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7441 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7442 }
7443 break;
7444
7445 case M_S_DOB:
7446 if (mips_opts.arch == CPU_R4650)
7447 {
7448 as_bad (_("opcode not supported on this processor"));
7449 break;
7450 }
7451 assert (mips_opts.isa == ISA_MIPS1);
7452 /* Even on a big endian machine $fn comes before $fn+1. We have
7453 to adjust when storing to memory. */
7454 macro_build (&offset_expr, "swc1", "T,o(b)",
7455 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7456 offset_expr.X_add_number += 4;
7457 macro_build (&offset_expr, "swc1", "T,o(b)",
7458 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7459 break;
7460
7461 case M_SEQ:
7462 if (sreg == 0)
7463 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7464 else if (treg == 0)
7465 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7466 else
7467 {
7468 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7469 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7470 }
7471 break;
7472
7473 case M_SEQ_I:
7474 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7475 {
7476 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7477 break;
7478 }
7479 if (sreg == 0)
7480 {
7481 as_warn (_("Instruction %s: result is always false"),
7482 ip->insn_mo->name);
7483 move_register (dreg, 0);
7484 break;
7485 }
7486 if (imm_expr.X_op == O_constant
7487 && imm_expr.X_add_number >= 0
7488 && imm_expr.X_add_number < 0x10000)
7489 {
7490 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7491 }
7492 else if (imm_expr.X_op == O_constant
7493 && imm_expr.X_add_number > -0x8000
7494 && imm_expr.X_add_number < 0)
7495 {
7496 imm_expr.X_add_number = -imm_expr.X_add_number;
7497 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7498 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7499 }
7500 else
7501 {
7502 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7503 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7504 used_at = 1;
7505 }
7506 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7507 break;
7508
7509 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7510 s = "slt";
7511 goto sge;
7512 case M_SGEU:
7513 s = "sltu";
7514 sge:
7515 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7516 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7517 break;
7518
7519 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7520 case M_SGEU_I:
7521 if (imm_expr.X_op == O_constant
7522 && imm_expr.X_add_number >= -0x8000
7523 && imm_expr.X_add_number < 0x8000)
7524 {
7525 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7526 dreg, sreg, BFD_RELOC_LO16);
7527 }
7528 else
7529 {
7530 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7531 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7532 dreg, sreg, AT);
7533 used_at = 1;
7534 }
7535 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7536 break;
7537
7538 case M_SGT: /* sreg > treg <==> treg < sreg */
7539 s = "slt";
7540 goto sgt;
7541 case M_SGTU:
7542 s = "sltu";
7543 sgt:
7544 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7545 break;
7546
7547 case M_SGT_I: /* sreg > I <==> I < sreg */
7548 s = "slt";
7549 goto sgti;
7550 case M_SGTU_I:
7551 s = "sltu";
7552 sgti:
7553 used_at = 1;
7554 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7555 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7556 break;
7557
7558 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7559 s = "slt";
7560 goto sle;
7561 case M_SLEU:
7562 s = "sltu";
7563 sle:
7564 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7565 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7566 break;
7567
7568 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7569 s = "slt";
7570 goto slei;
7571 case M_SLEU_I:
7572 s = "sltu";
7573 slei:
7574 used_at = 1;
7575 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7576 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7577 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7578 break;
7579
7580 case M_SLT_I:
7581 if (imm_expr.X_op == O_constant
7582 && imm_expr.X_add_number >= -0x8000
7583 && imm_expr.X_add_number < 0x8000)
7584 {
7585 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7586 break;
7587 }
7588 used_at = 1;
7589 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7590 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7591 break;
7592
7593 case M_SLTU_I:
7594 if (imm_expr.X_op == O_constant
7595 && imm_expr.X_add_number >= -0x8000
7596 && imm_expr.X_add_number < 0x8000)
7597 {
7598 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7599 BFD_RELOC_LO16);
7600 break;
7601 }
7602 used_at = 1;
7603 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7604 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7605 break;
7606
7607 case M_SNE:
7608 if (sreg == 0)
7609 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7610 else if (treg == 0)
7611 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7612 else
7613 {
7614 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7615 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7616 }
7617 break;
7618
7619 case M_SNE_I:
7620 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7621 {
7622 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7623 break;
7624 }
7625 if (sreg == 0)
7626 {
7627 as_warn (_("Instruction %s: result is always true"),
7628 ip->insn_mo->name);
7629 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7630 dreg, 0, BFD_RELOC_LO16);
7631 break;
7632 }
7633 if (imm_expr.X_op == O_constant
7634 && imm_expr.X_add_number >= 0
7635 && imm_expr.X_add_number < 0x10000)
7636 {
7637 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7638 }
7639 else if (imm_expr.X_op == O_constant
7640 && imm_expr.X_add_number > -0x8000
7641 && imm_expr.X_add_number < 0)
7642 {
7643 imm_expr.X_add_number = -imm_expr.X_add_number;
7644 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7645 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7646 }
7647 else
7648 {
7649 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7650 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7651 used_at = 1;
7652 }
7653 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7654 break;
7655
7656 case M_DSUB_I:
7657 dbl = 1;
7658 case M_SUB_I:
7659 if (imm_expr.X_op == O_constant
7660 && imm_expr.X_add_number > -0x8000
7661 && imm_expr.X_add_number <= 0x8000)
7662 {
7663 imm_expr.X_add_number = -imm_expr.X_add_number;
7664 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7665 dreg, sreg, BFD_RELOC_LO16);
7666 break;
7667 }
7668 used_at = 1;
7669 load_register (AT, &imm_expr, dbl);
7670 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7671 break;
7672
7673 case M_DSUBU_I:
7674 dbl = 1;
7675 case M_SUBU_I:
7676 if (imm_expr.X_op == O_constant
7677 && imm_expr.X_add_number > -0x8000
7678 && imm_expr.X_add_number <= 0x8000)
7679 {
7680 imm_expr.X_add_number = -imm_expr.X_add_number;
7681 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7682 dreg, sreg, BFD_RELOC_LO16);
7683 break;
7684 }
7685 used_at = 1;
7686 load_register (AT, &imm_expr, dbl);
7687 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7688 break;
7689
7690 case M_TEQ_I:
7691 s = "teq";
7692 goto trap;
7693 case M_TGE_I:
7694 s = "tge";
7695 goto trap;
7696 case M_TGEU_I:
7697 s = "tgeu";
7698 goto trap;
7699 case M_TLT_I:
7700 s = "tlt";
7701 goto trap;
7702 case M_TLTU_I:
7703 s = "tltu";
7704 goto trap;
7705 case M_TNE_I:
7706 s = "tne";
7707 trap:
7708 used_at = 1;
7709 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7710 macro_build (NULL, s, "s,t", sreg, AT);
7711 break;
7712
7713 case M_TRUNCWS:
7714 case M_TRUNCWD:
7715 assert (mips_opts.isa == ISA_MIPS1);
7716 used_at = 1;
7717 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7718 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7719
7720 /*
7721 * Is the double cfc1 instruction a bug in the mips assembler;
7722 * or is there a reason for it?
7723 */
7724 start_noreorder ();
7725 macro_build (NULL, "cfc1", "t,G", treg, RA);
7726 macro_build (NULL, "cfc1", "t,G", treg, RA);
7727 macro_build (NULL, "nop", "");
7728 expr1.X_add_number = 3;
7729 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7730 expr1.X_add_number = 2;
7731 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7732 macro_build (NULL, "ctc1", "t,G", AT, RA);
7733 macro_build (NULL, "nop", "");
7734 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7735 dreg, sreg);
7736 macro_build (NULL, "ctc1", "t,G", treg, RA);
7737 macro_build (NULL, "nop", "");
7738 end_noreorder ();
7739 break;
7740
7741 case M_ULH:
7742 s = "lb";
7743 goto ulh;
7744 case M_ULHU:
7745 s = "lbu";
7746 ulh:
7747 used_at = 1;
7748 if (offset_expr.X_add_number >= 0x7fff)
7749 as_bad (_("operand overflow"));
7750 if (! target_big_endian)
7751 ++offset_expr.X_add_number;
7752 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7753 if (! target_big_endian)
7754 --offset_expr.X_add_number;
7755 else
7756 ++offset_expr.X_add_number;
7757 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7758 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7759 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7760 break;
7761
7762 case M_ULD:
7763 s = "ldl";
7764 s2 = "ldr";
7765 off = 7;
7766 goto ulw;
7767 case M_ULW:
7768 s = "lwl";
7769 s2 = "lwr";
7770 off = 3;
7771 ulw:
7772 if (offset_expr.X_add_number >= 0x8000 - off)
7773 as_bad (_("operand overflow"));
7774 if (treg != breg)
7775 tempreg = treg;
7776 else
7777 {
7778 used_at = 1;
7779 tempreg = AT;
7780 }
7781 if (! target_big_endian)
7782 offset_expr.X_add_number += off;
7783 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7784 if (! target_big_endian)
7785 offset_expr.X_add_number -= off;
7786 else
7787 offset_expr.X_add_number += off;
7788 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7789
7790 /* If necessary, move the result in tempreg the final destination. */
7791 if (treg == tempreg)
7792 break;
7793 /* Protect second load's delay slot. */
7794 load_delay_nop ();
7795 move_register (treg, tempreg);
7796 break;
7797
7798 case M_ULD_A:
7799 s = "ldl";
7800 s2 = "ldr";
7801 off = 7;
7802 goto ulwa;
7803 case M_ULW_A:
7804 s = "lwl";
7805 s2 = "lwr";
7806 off = 3;
7807 ulwa:
7808 used_at = 1;
7809 load_address (AT, &offset_expr, &used_at);
7810 if (breg != 0)
7811 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7812 if (! target_big_endian)
7813 expr1.X_add_number = off;
7814 else
7815 expr1.X_add_number = 0;
7816 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7817 if (! target_big_endian)
7818 expr1.X_add_number = 0;
7819 else
7820 expr1.X_add_number = off;
7821 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7822 break;
7823
7824 case M_ULH_A:
7825 case M_ULHU_A:
7826 used_at = 1;
7827 load_address (AT, &offset_expr, &used_at);
7828 if (breg != 0)
7829 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7830 if (target_big_endian)
7831 expr1.X_add_number = 0;
7832 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7833 treg, BFD_RELOC_LO16, AT);
7834 if (target_big_endian)
7835 expr1.X_add_number = 1;
7836 else
7837 expr1.X_add_number = 0;
7838 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7839 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7840 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7841 break;
7842
7843 case M_USH:
7844 used_at = 1;
7845 if (offset_expr.X_add_number >= 0x7fff)
7846 as_bad (_("operand overflow"));
7847 if (target_big_endian)
7848 ++offset_expr.X_add_number;
7849 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7850 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7851 if (target_big_endian)
7852 --offset_expr.X_add_number;
7853 else
7854 ++offset_expr.X_add_number;
7855 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7856 break;
7857
7858 case M_USD:
7859 s = "sdl";
7860 s2 = "sdr";
7861 off = 7;
7862 goto usw;
7863 case M_USW:
7864 s = "swl";
7865 s2 = "swr";
7866 off = 3;
7867 usw:
7868 if (offset_expr.X_add_number >= 0x8000 - off)
7869 as_bad (_("operand overflow"));
7870 if (! target_big_endian)
7871 offset_expr.X_add_number += off;
7872 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7873 if (! target_big_endian)
7874 offset_expr.X_add_number -= off;
7875 else
7876 offset_expr.X_add_number += off;
7877 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7878 break;
7879
7880 case M_USD_A:
7881 s = "sdl";
7882 s2 = "sdr";
7883 off = 7;
7884 goto uswa;
7885 case M_USW_A:
7886 s = "swl";
7887 s2 = "swr";
7888 off = 3;
7889 uswa:
7890 used_at = 1;
7891 load_address (AT, &offset_expr, &used_at);
7892 if (breg != 0)
7893 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7894 if (! target_big_endian)
7895 expr1.X_add_number = off;
7896 else
7897 expr1.X_add_number = 0;
7898 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7899 if (! target_big_endian)
7900 expr1.X_add_number = 0;
7901 else
7902 expr1.X_add_number = off;
7903 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7904 break;
7905
7906 case M_USH_A:
7907 used_at = 1;
7908 load_address (AT, &offset_expr, &used_at);
7909 if (breg != 0)
7910 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7911 if (! target_big_endian)
7912 expr1.X_add_number = 0;
7913 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7914 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7915 if (! target_big_endian)
7916 expr1.X_add_number = 1;
7917 else
7918 expr1.X_add_number = 0;
7919 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7920 if (! target_big_endian)
7921 expr1.X_add_number = 0;
7922 else
7923 expr1.X_add_number = 1;
7924 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7925 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7926 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7927 break;
7928
7929 default:
7930 /* FIXME: Check if this is one of the itbl macros, since they
7931 are added dynamically. */
7932 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7933 break;
7934 }
7935 if (!mips_opts.at && used_at)
7936 as_bad (_("Macro used $at after \".set noat\""));
7937 }
7938
7939 /* Implement macros in mips16 mode. */
7940
7941 static void
7942 mips16_macro (struct mips_cl_insn *ip)
7943 {
7944 int mask;
7945 int xreg, yreg, zreg, tmp;
7946 expressionS expr1;
7947 int dbl;
7948 const char *s, *s2, *s3;
7949
7950 mask = ip->insn_mo->mask;
7951
7952 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
7953 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
7954 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
7955
7956 expr1.X_op = O_constant;
7957 expr1.X_op_symbol = NULL;
7958 expr1.X_add_symbol = NULL;
7959 expr1.X_add_number = 1;
7960
7961 dbl = 0;
7962
7963 switch (mask)
7964 {
7965 default:
7966 internalError ();
7967
7968 case M_DDIV_3:
7969 dbl = 1;
7970 case M_DIV_3:
7971 s = "mflo";
7972 goto do_div3;
7973 case M_DREM_3:
7974 dbl = 1;
7975 case M_REM_3:
7976 s = "mfhi";
7977 do_div3:
7978 start_noreorder ();
7979 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7980 expr1.X_add_number = 2;
7981 macro_build (&expr1, "bnez", "x,p", yreg);
7982 macro_build (NULL, "break", "6", 7);
7983
7984 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7985 since that causes an overflow. We should do that as well,
7986 but I don't see how to do the comparisons without a temporary
7987 register. */
7988 end_noreorder ();
7989 macro_build (NULL, s, "x", zreg);
7990 break;
7991
7992 case M_DIVU_3:
7993 s = "divu";
7994 s2 = "mflo";
7995 goto do_divu3;
7996 case M_REMU_3:
7997 s = "divu";
7998 s2 = "mfhi";
7999 goto do_divu3;
8000 case M_DDIVU_3:
8001 s = "ddivu";
8002 s2 = "mflo";
8003 goto do_divu3;
8004 case M_DREMU_3:
8005 s = "ddivu";
8006 s2 = "mfhi";
8007 do_divu3:
8008 start_noreorder ();
8009 macro_build (NULL, s, "0,x,y", xreg, yreg);
8010 expr1.X_add_number = 2;
8011 macro_build (&expr1, "bnez", "x,p", yreg);
8012 macro_build (NULL, "break", "6", 7);
8013 end_noreorder ();
8014 macro_build (NULL, s2, "x", zreg);
8015 break;
8016
8017 case M_DMUL:
8018 dbl = 1;
8019 case M_MUL:
8020 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8021 macro_build (NULL, "mflo", "x", zreg);
8022 break;
8023
8024 case M_DSUBU_I:
8025 dbl = 1;
8026 goto do_subu;
8027 case M_SUBU_I:
8028 do_subu:
8029 if (imm_expr.X_op != O_constant)
8030 as_bad (_("Unsupported large constant"));
8031 imm_expr.X_add_number = -imm_expr.X_add_number;
8032 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8033 break;
8034
8035 case M_SUBU_I_2:
8036 if (imm_expr.X_op != O_constant)
8037 as_bad (_("Unsupported large constant"));
8038 imm_expr.X_add_number = -imm_expr.X_add_number;
8039 macro_build (&imm_expr, "addiu", "x,k", xreg);
8040 break;
8041
8042 case M_DSUBU_I_2:
8043 if (imm_expr.X_op != O_constant)
8044 as_bad (_("Unsupported large constant"));
8045 imm_expr.X_add_number = -imm_expr.X_add_number;
8046 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8047 break;
8048
8049 case M_BEQ:
8050 s = "cmp";
8051 s2 = "bteqz";
8052 goto do_branch;
8053 case M_BNE:
8054 s = "cmp";
8055 s2 = "btnez";
8056 goto do_branch;
8057 case M_BLT:
8058 s = "slt";
8059 s2 = "btnez";
8060 goto do_branch;
8061 case M_BLTU:
8062 s = "sltu";
8063 s2 = "btnez";
8064 goto do_branch;
8065 case M_BLE:
8066 s = "slt";
8067 s2 = "bteqz";
8068 goto do_reverse_branch;
8069 case M_BLEU:
8070 s = "sltu";
8071 s2 = "bteqz";
8072 goto do_reverse_branch;
8073 case M_BGE:
8074 s = "slt";
8075 s2 = "bteqz";
8076 goto do_branch;
8077 case M_BGEU:
8078 s = "sltu";
8079 s2 = "bteqz";
8080 goto do_branch;
8081 case M_BGT:
8082 s = "slt";
8083 s2 = "btnez";
8084 goto do_reverse_branch;
8085 case M_BGTU:
8086 s = "sltu";
8087 s2 = "btnez";
8088
8089 do_reverse_branch:
8090 tmp = xreg;
8091 xreg = yreg;
8092 yreg = tmp;
8093
8094 do_branch:
8095 macro_build (NULL, s, "x,y", xreg, yreg);
8096 macro_build (&offset_expr, s2, "p");
8097 break;
8098
8099 case M_BEQ_I:
8100 s = "cmpi";
8101 s2 = "bteqz";
8102 s3 = "x,U";
8103 goto do_branch_i;
8104 case M_BNE_I:
8105 s = "cmpi";
8106 s2 = "btnez";
8107 s3 = "x,U";
8108 goto do_branch_i;
8109 case M_BLT_I:
8110 s = "slti";
8111 s2 = "btnez";
8112 s3 = "x,8";
8113 goto do_branch_i;
8114 case M_BLTU_I:
8115 s = "sltiu";
8116 s2 = "btnez";
8117 s3 = "x,8";
8118 goto do_branch_i;
8119 case M_BLE_I:
8120 s = "slti";
8121 s2 = "btnez";
8122 s3 = "x,8";
8123 goto do_addone_branch_i;
8124 case M_BLEU_I:
8125 s = "sltiu";
8126 s2 = "btnez";
8127 s3 = "x,8";
8128 goto do_addone_branch_i;
8129 case M_BGE_I:
8130 s = "slti";
8131 s2 = "bteqz";
8132 s3 = "x,8";
8133 goto do_branch_i;
8134 case M_BGEU_I:
8135 s = "sltiu";
8136 s2 = "bteqz";
8137 s3 = "x,8";
8138 goto do_branch_i;
8139 case M_BGT_I:
8140 s = "slti";
8141 s2 = "bteqz";
8142 s3 = "x,8";
8143 goto do_addone_branch_i;
8144 case M_BGTU_I:
8145 s = "sltiu";
8146 s2 = "bteqz";
8147 s3 = "x,8";
8148
8149 do_addone_branch_i:
8150 if (imm_expr.X_op != O_constant)
8151 as_bad (_("Unsupported large constant"));
8152 ++imm_expr.X_add_number;
8153
8154 do_branch_i:
8155 macro_build (&imm_expr, s, s3, xreg);
8156 macro_build (&offset_expr, s2, "p");
8157 break;
8158
8159 case M_ABS:
8160 expr1.X_add_number = 0;
8161 macro_build (&expr1, "slti", "x,8", yreg);
8162 if (xreg != yreg)
8163 move_register (xreg, yreg);
8164 expr1.X_add_number = 2;
8165 macro_build (&expr1, "bteqz", "p");
8166 macro_build (NULL, "neg", "x,w", xreg, xreg);
8167 }
8168 }
8169
8170 /* For consistency checking, verify that all bits are specified either
8171 by the match/mask part of the instruction definition, or by the
8172 operand list. */
8173 static int
8174 validate_mips_insn (const struct mips_opcode *opc)
8175 {
8176 const char *p = opc->args;
8177 char c;
8178 unsigned long used_bits = opc->mask;
8179
8180 if ((used_bits & opc->match) != opc->match)
8181 {
8182 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8183 opc->name, opc->args);
8184 return 0;
8185 }
8186 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8187 while (*p)
8188 switch (c = *p++)
8189 {
8190 case ',': break;
8191 case '(': break;
8192 case ')': break;
8193 case '+':
8194 switch (c = *p++)
8195 {
8196 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8197 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8198 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8199 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8200 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8201 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8202 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8203 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8204 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8205 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8206 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8207 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8208 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8209 case 'I': break;
8210 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8211 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8212 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8213 default:
8214 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8215 c, opc->name, opc->args);
8216 return 0;
8217 }
8218 break;
8219 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8220 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8221 case 'A': break;
8222 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8223 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8224 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8225 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8226 case 'F': break;
8227 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8228 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8229 case 'I': break;
8230 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8231 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8232 case 'L': break;
8233 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8234 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8235 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8236 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8237 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8238 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8239 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8240 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8241 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8242 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8243 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8244 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8245 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8246 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8247 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8248 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8249 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8250 case 'f': break;
8251 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8252 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8253 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8254 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8255 case 'l': break;
8256 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8257 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8258 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8259 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8260 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8261 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8262 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8263 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8264 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8265 case 'x': break;
8266 case 'z': break;
8267 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8268 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8269 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8270 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8271 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8272 case '[': break;
8273 case ']': break;
8274 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8275 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8276 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8277 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8278 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8279 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8280 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8281 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8282 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8283 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8284 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8285 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8286 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8287 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8288 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8289 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8290 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8291 default:
8292 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8293 c, opc->name, opc->args);
8294 return 0;
8295 }
8296 #undef USE_BITS
8297 if (used_bits != 0xffffffff)
8298 {
8299 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8300 ~used_bits & 0xffffffff, opc->name, opc->args);
8301 return 0;
8302 }
8303 return 1;
8304 }
8305
8306 /* UDI immediates. */
8307 struct mips_immed {
8308 char type;
8309 unsigned int shift;
8310 unsigned long mask;
8311 const char * desc;
8312 };
8313
8314 static const struct mips_immed mips_immed[] = {
8315 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8316 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8317 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8318 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8319 { 0,0,0,0 }
8320 };
8321
8322 /* Check whether an odd floating-point register is allowed. */
8323 static int
8324 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8325 {
8326 const char *s = insn->name;
8327
8328 if (insn->pinfo == INSN_MACRO)
8329 /* Let a macro pass, we'll catch it later when it is expanded. */
8330 return 1;
8331
8332 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8333 {
8334 /* Allow odd registers for single-precision ops. */
8335 switch (insn->pinfo & (FP_S | FP_D))
8336 {
8337 case FP_S:
8338 case 0:
8339 return 1; /* both single precision - ok */
8340 case FP_D:
8341 return 0; /* both double precision - fail */
8342 default:
8343 break;
8344 }
8345
8346 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8347 s = strchr (insn->name, '.');
8348 if (argnum == 2)
8349 s = s != NULL ? strchr (s + 1, '.') : NULL;
8350 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8351 }
8352
8353 /* Single-precision coprocessor loads and moves are OK too. */
8354 if ((insn->pinfo & FP_S)
8355 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8356 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8357 return 1;
8358
8359 return 0;
8360 }
8361
8362 /* This routine assembles an instruction into its binary format. As a
8363 side effect, it sets one of the global variables imm_reloc or
8364 offset_reloc to the type of relocation to do if one of the operands
8365 is an address expression. */
8366
8367 static void
8368 mips_ip (char *str, struct mips_cl_insn *ip)
8369 {
8370 char *s;
8371 const char *args;
8372 char c = 0;
8373 struct mips_opcode *insn;
8374 char *argsStart;
8375 unsigned int regno;
8376 unsigned int lastregno = 0;
8377 unsigned int lastpos = 0;
8378 unsigned int limlo, limhi;
8379 char *s_reset;
8380 char save_c = 0;
8381 offsetT min_range, max_range;
8382 int argnum;
8383 unsigned int rtype;
8384
8385 insn_error = NULL;
8386
8387 /* If the instruction contains a '.', we first try to match an instruction
8388 including the '.'. Then we try again without the '.'. */
8389 insn = NULL;
8390 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8391 continue;
8392
8393 /* If we stopped on whitespace, then replace the whitespace with null for
8394 the call to hash_find. Save the character we replaced just in case we
8395 have to re-parse the instruction. */
8396 if (ISSPACE (*s))
8397 {
8398 save_c = *s;
8399 *s++ = '\0';
8400 }
8401
8402 insn = (struct mips_opcode *) hash_find (op_hash, str);
8403
8404 /* If we didn't find the instruction in the opcode table, try again, but
8405 this time with just the instruction up to, but not including the
8406 first '.'. */
8407 if (insn == NULL)
8408 {
8409 /* Restore the character we overwrite above (if any). */
8410 if (save_c)
8411 *(--s) = save_c;
8412
8413 /* Scan up to the first '.' or whitespace. */
8414 for (s = str;
8415 *s != '\0' && *s != '.' && !ISSPACE (*s);
8416 ++s)
8417 continue;
8418
8419 /* If we did not find a '.', then we can quit now. */
8420 if (*s != '.')
8421 {
8422 insn_error = "unrecognized opcode";
8423 return;
8424 }
8425
8426 /* Lookup the instruction in the hash table. */
8427 *s++ = '\0';
8428 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8429 {
8430 insn_error = "unrecognized opcode";
8431 return;
8432 }
8433 }
8434
8435 argsStart = s;
8436 for (;;)
8437 {
8438 bfd_boolean ok;
8439
8440 assert (strcmp (insn->name, str) == 0);
8441
8442 if (OPCODE_IS_MEMBER (insn,
8443 (mips_opts.isa
8444 /* We don't check for mips_opts.mips16 here since
8445 we want to allow jalx if -mips16 was specified
8446 on the command line. */
8447 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8448 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8449 | (mips_opts.ase_dsp ? INSN_DSP : 0)
8450 | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
8451 ? INSN_DSP64 : 0)
8452 | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
8453 | (mips_opts.ase_mt ? INSN_MT : 0)
8454 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
8455 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
8456 mips_opts.arch))
8457 ok = TRUE;
8458 else
8459 ok = FALSE;
8460
8461 if (insn->pinfo != INSN_MACRO)
8462 {
8463 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8464 ok = FALSE;
8465 }
8466
8467 if (! ok)
8468 {
8469 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8470 && strcmp (insn->name, insn[1].name) == 0)
8471 {
8472 ++insn;
8473 continue;
8474 }
8475 else
8476 {
8477 if (!insn_error)
8478 {
8479 static char buf[100];
8480 sprintf (buf,
8481 _("opcode not supported on this processor: %s (%s)"),
8482 mips_cpu_info_from_arch (mips_opts.arch)->name,
8483 mips_cpu_info_from_isa (mips_opts.isa)->name);
8484 insn_error = buf;
8485 }
8486 if (save_c)
8487 *(--s) = save_c;
8488 return;
8489 }
8490 }
8491
8492 create_insn (ip, insn);
8493 insn_error = NULL;
8494 argnum = 1;
8495 for (args = insn->args;; ++args)
8496 {
8497 int is_mdmx;
8498
8499 s += strspn (s, " \t");
8500 is_mdmx = 0;
8501 switch (*args)
8502 {
8503 case '\0': /* end of args */
8504 if (*s == '\0')
8505 return;
8506 break;
8507
8508 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8509 my_getExpression (&imm_expr, s);
8510 check_absolute_expr (ip, &imm_expr);
8511 if ((unsigned long) imm_expr.X_add_number != 1
8512 && (unsigned long) imm_expr.X_add_number != 3)
8513 {
8514 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8515 (unsigned long) imm_expr.X_add_number);
8516 }
8517 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8518 imm_expr.X_op = O_absent;
8519 s = expr_end;
8520 continue;
8521
8522 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8523 my_getExpression (&imm_expr, s);
8524 check_absolute_expr (ip, &imm_expr);
8525 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8526 {
8527 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8528 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8529 }
8530 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8531 imm_expr.X_op = O_absent;
8532 s = expr_end;
8533 continue;
8534
8535 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8536 my_getExpression (&imm_expr, s);
8537 check_absolute_expr (ip, &imm_expr);
8538 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8539 {
8540 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8541 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8542 }
8543 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8544 imm_expr.X_op = O_absent;
8545 s = expr_end;
8546 continue;
8547
8548 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8549 my_getExpression (&imm_expr, s);
8550 check_absolute_expr (ip, &imm_expr);
8551 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8552 {
8553 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8554 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8555 }
8556 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8557 imm_expr.X_op = O_absent;
8558 s = expr_end;
8559 continue;
8560
8561 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8562 my_getExpression (&imm_expr, s);
8563 check_absolute_expr (ip, &imm_expr);
8564 if (imm_expr.X_add_number & ~OP_MASK_RS)
8565 {
8566 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8567 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8568 }
8569 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8570 imm_expr.X_op = O_absent;
8571 s = expr_end;
8572 continue;
8573
8574 case '7': /* four dsp accumulators in bits 11,12 */
8575 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8576 s[3] >= '0' && s[3] <= '3')
8577 {
8578 regno = s[3] - '0';
8579 s += 4;
8580 INSERT_OPERAND (DSPACC, *ip, regno);
8581 continue;
8582 }
8583 else
8584 as_bad (_("Invalid dsp acc register"));
8585 break;
8586
8587 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8588 my_getExpression (&imm_expr, s);
8589 check_absolute_expr (ip, &imm_expr);
8590 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8591 {
8592 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8593 OP_MASK_WRDSP,
8594 (unsigned long) imm_expr.X_add_number);
8595 }
8596 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8597 imm_expr.X_op = O_absent;
8598 s = expr_end;
8599 continue;
8600
8601 case '9': /* four dsp accumulators in bits 21,22 */
8602 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8603 s[3] >= '0' && s[3] <= '3')
8604 {
8605 regno = s[3] - '0';
8606 s += 4;
8607 INSERT_OPERAND (DSPACC_S, *ip, regno);
8608 continue;
8609 }
8610 else
8611 as_bad (_("Invalid dsp acc register"));
8612 break;
8613
8614 case '0': /* dsp 6-bit signed immediate in bit 20 */
8615 my_getExpression (&imm_expr, s);
8616 check_absolute_expr (ip, &imm_expr);
8617 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8618 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8619 if (imm_expr.X_add_number < min_range ||
8620 imm_expr.X_add_number > max_range)
8621 {
8622 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8623 (long) min_range, (long) max_range,
8624 (long) imm_expr.X_add_number);
8625 }
8626 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8627 imm_expr.X_op = O_absent;
8628 s = expr_end;
8629 continue;
8630
8631 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8632 my_getExpression (&imm_expr, s);
8633 check_absolute_expr (ip, &imm_expr);
8634 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8635 {
8636 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8637 OP_MASK_RDDSP,
8638 (unsigned long) imm_expr.X_add_number);
8639 }
8640 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8641 imm_expr.X_op = O_absent;
8642 s = expr_end;
8643 continue;
8644
8645 case ':': /* dsp 7-bit signed immediate in bit 19 */
8646 my_getExpression (&imm_expr, s);
8647 check_absolute_expr (ip, &imm_expr);
8648 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8649 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8650 if (imm_expr.X_add_number < min_range ||
8651 imm_expr.X_add_number > max_range)
8652 {
8653 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8654 (long) min_range, (long) max_range,
8655 (long) imm_expr.X_add_number);
8656 }
8657 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8658 imm_expr.X_op = O_absent;
8659 s = expr_end;
8660 continue;
8661
8662 case '@': /* dsp 10-bit signed immediate in bit 16 */
8663 my_getExpression (&imm_expr, s);
8664 check_absolute_expr (ip, &imm_expr);
8665 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8666 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8667 if (imm_expr.X_add_number < min_range ||
8668 imm_expr.X_add_number > max_range)
8669 {
8670 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8671 (long) min_range, (long) max_range,
8672 (long) imm_expr.X_add_number);
8673 }
8674 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8675 imm_expr.X_op = O_absent;
8676 s = expr_end;
8677 continue;
8678
8679 case '!': /* MT usermode flag bit. */
8680 my_getExpression (&imm_expr, s);
8681 check_absolute_expr (ip, &imm_expr);
8682 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8683 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8684 (unsigned long) imm_expr.X_add_number);
8685 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8686 imm_expr.X_op = O_absent;
8687 s = expr_end;
8688 continue;
8689
8690 case '$': /* MT load high flag bit. */
8691 my_getExpression (&imm_expr, s);
8692 check_absolute_expr (ip, &imm_expr);
8693 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8694 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8695 (unsigned long) imm_expr.X_add_number);
8696 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
8697 imm_expr.X_op = O_absent;
8698 s = expr_end;
8699 continue;
8700
8701 case '*': /* four dsp accumulators in bits 18,19 */
8702 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8703 s[3] >= '0' && s[3] <= '3')
8704 {
8705 regno = s[3] - '0';
8706 s += 4;
8707 INSERT_OPERAND (MTACC_T, *ip, regno);
8708 continue;
8709 }
8710 else
8711 as_bad (_("Invalid dsp/smartmips acc register"));
8712 break;
8713
8714 case '&': /* four dsp accumulators in bits 13,14 */
8715 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8716 s[3] >= '0' && s[3] <= '3')
8717 {
8718 regno = s[3] - '0';
8719 s += 4;
8720 INSERT_OPERAND (MTACC_D, *ip, regno);
8721 continue;
8722 }
8723 else
8724 as_bad (_("Invalid dsp/smartmips acc register"));
8725 break;
8726
8727 case ',':
8728 ++argnum;
8729 if (*s++ == *args)
8730 continue;
8731 s--;
8732 switch (*++args)
8733 {
8734 case 'r':
8735 case 'v':
8736 INSERT_OPERAND (RS, *ip, lastregno);
8737 continue;
8738
8739 case 'w':
8740 INSERT_OPERAND (RT, *ip, lastregno);
8741 continue;
8742
8743 case 'W':
8744 INSERT_OPERAND (FT, *ip, lastregno);
8745 continue;
8746
8747 case 'V':
8748 INSERT_OPERAND (FS, *ip, lastregno);
8749 continue;
8750 }
8751 break;
8752
8753 case '(':
8754 /* Handle optional base register.
8755 Either the base register is omitted or
8756 we must have a left paren. */
8757 /* This is dependent on the next operand specifier
8758 is a base register specification. */
8759 assert (args[1] == 'b' || args[1] == '5'
8760 || args[1] == '-' || args[1] == '4');
8761 if (*s == '\0')
8762 return;
8763
8764 case ')': /* these must match exactly */
8765 case '[':
8766 case ']':
8767 if (*s++ == *args)
8768 continue;
8769 break;
8770
8771 case '+': /* Opcode extension character. */
8772 switch (*++args)
8773 {
8774 case '1': /* UDI immediates. */
8775 case '2':
8776 case '3':
8777 case '4':
8778 {
8779 const struct mips_immed *imm = mips_immed;
8780
8781 while (imm->type && imm->type != *args)
8782 ++imm;
8783 if (! imm->type)
8784 internalError ();
8785 my_getExpression (&imm_expr, s);
8786 check_absolute_expr (ip, &imm_expr);
8787 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
8788 {
8789 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8790 imm->desc ? imm->desc : ip->insn_mo->name,
8791 (unsigned long) imm_expr.X_add_number,
8792 (unsigned long) imm_expr.X_add_number);
8793 imm_expr.X_add_number &= imm->mask;
8794 }
8795 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8796 << imm->shift);
8797 imm_expr.X_op = O_absent;
8798 s = expr_end;
8799 }
8800 continue;
8801
8802 case 'A': /* ins/ext position, becomes LSB. */
8803 limlo = 0;
8804 limhi = 31;
8805 goto do_lsb;
8806 case 'E':
8807 limlo = 32;
8808 limhi = 63;
8809 goto do_lsb;
8810 do_lsb:
8811 my_getExpression (&imm_expr, s);
8812 check_absolute_expr (ip, &imm_expr);
8813 if ((unsigned long) imm_expr.X_add_number < limlo
8814 || (unsigned long) imm_expr.X_add_number > limhi)
8815 {
8816 as_bad (_("Improper position (%lu)"),
8817 (unsigned long) imm_expr.X_add_number);
8818 imm_expr.X_add_number = limlo;
8819 }
8820 lastpos = imm_expr.X_add_number;
8821 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
8822 imm_expr.X_op = O_absent;
8823 s = expr_end;
8824 continue;
8825
8826 case 'B': /* ins size, becomes MSB. */
8827 limlo = 1;
8828 limhi = 32;
8829 goto do_msb;
8830 case 'F':
8831 limlo = 33;
8832 limhi = 64;
8833 goto do_msb;
8834 do_msb:
8835 my_getExpression (&imm_expr, s);
8836 check_absolute_expr (ip, &imm_expr);
8837 /* Check for negative input so that small negative numbers
8838 will not succeed incorrectly. The checks against
8839 (pos+size) transitively check "size" itself,
8840 assuming that "pos" is reasonable. */
8841 if ((long) imm_expr.X_add_number < 0
8842 || ((unsigned long) imm_expr.X_add_number
8843 + lastpos) < limlo
8844 || ((unsigned long) imm_expr.X_add_number
8845 + lastpos) > limhi)
8846 {
8847 as_bad (_("Improper insert size (%lu, position %lu)"),
8848 (unsigned long) imm_expr.X_add_number,
8849 (unsigned long) lastpos);
8850 imm_expr.X_add_number = limlo - lastpos;
8851 }
8852 INSERT_OPERAND (INSMSB, *ip,
8853 lastpos + imm_expr.X_add_number - 1);
8854 imm_expr.X_op = O_absent;
8855 s = expr_end;
8856 continue;
8857
8858 case 'C': /* ext size, becomes MSBD. */
8859 limlo = 1;
8860 limhi = 32;
8861 goto do_msbd;
8862 case 'G':
8863 limlo = 33;
8864 limhi = 64;
8865 goto do_msbd;
8866 case 'H':
8867 limlo = 33;
8868 limhi = 64;
8869 goto do_msbd;
8870 do_msbd:
8871 my_getExpression (&imm_expr, s);
8872 check_absolute_expr (ip, &imm_expr);
8873 /* Check for negative input so that small negative numbers
8874 will not succeed incorrectly. The checks against
8875 (pos+size) transitively check "size" itself,
8876 assuming that "pos" is reasonable. */
8877 if ((long) imm_expr.X_add_number < 0
8878 || ((unsigned long) imm_expr.X_add_number
8879 + lastpos) < limlo
8880 || ((unsigned long) imm_expr.X_add_number
8881 + lastpos) > limhi)
8882 {
8883 as_bad (_("Improper extract size (%lu, position %lu)"),
8884 (unsigned long) imm_expr.X_add_number,
8885 (unsigned long) lastpos);
8886 imm_expr.X_add_number = limlo - lastpos;
8887 }
8888 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
8889 imm_expr.X_op = O_absent;
8890 s = expr_end;
8891 continue;
8892
8893 case 'D':
8894 /* +D is for disassembly only; never match. */
8895 break;
8896
8897 case 'I':
8898 /* "+I" is like "I", except that imm2_expr is used. */
8899 my_getExpression (&imm2_expr, s);
8900 if (imm2_expr.X_op != O_big
8901 && imm2_expr.X_op != O_constant)
8902 insn_error = _("absolute expression required");
8903 if (HAVE_32BIT_GPRS)
8904 normalize_constant_expr (&imm2_expr);
8905 s = expr_end;
8906 continue;
8907
8908 case 'T': /* Coprocessor register. */
8909 /* +T is for disassembly only; never match. */
8910 break;
8911
8912 case 't': /* Coprocessor register number. */
8913 if (s[0] == '$' && ISDIGIT (s[1]))
8914 {
8915 ++s;
8916 regno = 0;
8917 do
8918 {
8919 regno *= 10;
8920 regno += *s - '0';
8921 ++s;
8922 }
8923 while (ISDIGIT (*s));
8924 if (regno > 31)
8925 as_bad (_("Invalid register number (%d)"), regno);
8926 else
8927 {
8928 INSERT_OPERAND (RT, *ip, regno);
8929 continue;
8930 }
8931 }
8932 else
8933 as_bad (_("Invalid coprocessor 0 register number"));
8934 break;
8935
8936 default:
8937 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8938 *args, insn->name, insn->args);
8939 /* Further processing is fruitless. */
8940 return;
8941 }
8942 break;
8943
8944 case '<': /* must be at least one digit */
8945 /*
8946 * According to the manual, if the shift amount is greater
8947 * than 31 or less than 0, then the shift amount should be
8948 * mod 32. In reality the mips assembler issues an error.
8949 * We issue a warning and mask out all but the low 5 bits.
8950 */
8951 my_getExpression (&imm_expr, s);
8952 check_absolute_expr (ip, &imm_expr);
8953 if ((unsigned long) imm_expr.X_add_number > 31)
8954 as_warn (_("Improper shift amount (%lu)"),
8955 (unsigned long) imm_expr.X_add_number);
8956 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
8957 imm_expr.X_op = O_absent;
8958 s = expr_end;
8959 continue;
8960
8961 case '>': /* shift amount minus 32 */
8962 my_getExpression (&imm_expr, s);
8963 check_absolute_expr (ip, &imm_expr);
8964 if ((unsigned long) imm_expr.X_add_number < 32
8965 || (unsigned long) imm_expr.X_add_number > 63)
8966 break;
8967 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
8968 imm_expr.X_op = O_absent;
8969 s = expr_end;
8970 continue;
8971
8972 case 'k': /* cache code */
8973 case 'h': /* prefx code */
8974 my_getExpression (&imm_expr, s);
8975 check_absolute_expr (ip, &imm_expr);
8976 if ((unsigned long) imm_expr.X_add_number > 31)
8977 as_warn (_("Invalid value for `%s' (%lu)"),
8978 ip->insn_mo->name,
8979 (unsigned long) imm_expr.X_add_number);
8980 if (*args == 'k')
8981 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
8982 else
8983 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
8984 imm_expr.X_op = O_absent;
8985 s = expr_end;
8986 continue;
8987
8988 case 'c': /* break code */
8989 my_getExpression (&imm_expr, s);
8990 check_absolute_expr (ip, &imm_expr);
8991 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
8992 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
8993 ip->insn_mo->name,
8994 (unsigned long) imm_expr.X_add_number);
8995 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
8996 imm_expr.X_op = O_absent;
8997 s = expr_end;
8998 continue;
8999
9000 case 'q': /* lower break code */
9001 my_getExpression (&imm_expr, s);
9002 check_absolute_expr (ip, &imm_expr);
9003 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9004 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9005 ip->insn_mo->name,
9006 (unsigned long) imm_expr.X_add_number);
9007 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9008 imm_expr.X_op = O_absent;
9009 s = expr_end;
9010 continue;
9011
9012 case 'B': /* 20-bit syscall/break code. */
9013 my_getExpression (&imm_expr, s);
9014 check_absolute_expr (ip, &imm_expr);
9015 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9016 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9017 ip->insn_mo->name,
9018 (unsigned long) imm_expr.X_add_number);
9019 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9020 imm_expr.X_op = O_absent;
9021 s = expr_end;
9022 continue;
9023
9024 case 'C': /* Coprocessor code */
9025 my_getExpression (&imm_expr, s);
9026 check_absolute_expr (ip, &imm_expr);
9027 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9028 {
9029 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9030 (unsigned long) imm_expr.X_add_number);
9031 imm_expr.X_add_number &= OP_MASK_COPZ;
9032 }
9033 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9034 imm_expr.X_op = O_absent;
9035 s = expr_end;
9036 continue;
9037
9038 case 'J': /* 19-bit wait code. */
9039 my_getExpression (&imm_expr, s);
9040 check_absolute_expr (ip, &imm_expr);
9041 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9042 {
9043 as_warn (_("Illegal 19-bit code (%lu)"),
9044 (unsigned long) imm_expr.X_add_number);
9045 imm_expr.X_add_number &= OP_MASK_CODE19;
9046 }
9047 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9048 imm_expr.X_op = O_absent;
9049 s = expr_end;
9050 continue;
9051
9052 case 'P': /* Performance register. */
9053 my_getExpression (&imm_expr, s);
9054 check_absolute_expr (ip, &imm_expr);
9055 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9056 as_warn (_("Invalid performance register (%lu)"),
9057 (unsigned long) imm_expr.X_add_number);
9058 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9059 imm_expr.X_op = O_absent;
9060 s = expr_end;
9061 continue;
9062
9063 case 'G': /* Coprocessor destination register. */
9064 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9065 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
9066 else
9067 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9068 INSERT_OPERAND (RD, *ip, regno);
9069 if (ok)
9070 {
9071 lastregno = regno;
9072 continue;
9073 }
9074 else
9075 break;
9076
9077 case 'b': /* base register */
9078 case 'd': /* destination register */
9079 case 's': /* source register */
9080 case 't': /* target register */
9081 case 'r': /* both target and source */
9082 case 'v': /* both dest and source */
9083 case 'w': /* both dest and target */
9084 case 'E': /* coprocessor target register */
9085 case 'K': /* 'rdhwr' destination register */
9086 case 'x': /* ignore register name */
9087 case 'z': /* must be zero register */
9088 case 'U': /* destination register (clo/clz). */
9089 case 'g': /* coprocessor destination register */
9090 s_reset = s;
9091 if (*args == 'E' || *args == 'K')
9092 ok = reg_lookup (&s, RTYPE_NUM, &regno);
9093 else
9094 {
9095 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9096 if (regno == AT && mips_opts.at)
9097 {
9098 if (mips_opts.at == ATREG)
9099 as_warn (_("used $at without \".set noat\""));
9100 else
9101 as_warn (_("used $%u with \".set at=$%u\""),
9102 regno, mips_opts.at);
9103 }
9104 }
9105 if (ok)
9106 {
9107 c = *args;
9108 if (*s == ' ')
9109 ++s;
9110 if (args[1] != *s)
9111 {
9112 if (c == 'r' || c == 'v' || c == 'w')
9113 {
9114 regno = lastregno;
9115 s = s_reset;
9116 ++args;
9117 }
9118 }
9119 /* 'z' only matches $0. */
9120 if (c == 'z' && regno != 0)
9121 break;
9122
9123 /* Now that we have assembled one operand, we use the args string
9124 * to figure out where it goes in the instruction. */
9125 switch (c)
9126 {
9127 case 'r':
9128 case 's':
9129 case 'v':
9130 case 'b':
9131 INSERT_OPERAND (RS, *ip, regno);
9132 break;
9133 case 'd':
9134 case 'G':
9135 case 'K':
9136 case 'g':
9137 INSERT_OPERAND (RD, *ip, regno);
9138 break;
9139 case 'U':
9140 INSERT_OPERAND (RD, *ip, regno);
9141 INSERT_OPERAND (RT, *ip, regno);
9142 break;
9143 case 'w':
9144 case 't':
9145 case 'E':
9146 INSERT_OPERAND (RT, *ip, regno);
9147 break;
9148 case 'x':
9149 /* This case exists because on the r3000 trunc
9150 expands into a macro which requires a gp
9151 register. On the r6000 or r4000 it is
9152 assembled into a single instruction which
9153 ignores the register. Thus the insn version
9154 is MIPS_ISA2 and uses 'x', and the macro
9155 version is MIPS_ISA1 and uses 't'. */
9156 break;
9157 case 'z':
9158 /* This case is for the div instruction, which
9159 acts differently if the destination argument
9160 is $0. This only matches $0, and is checked
9161 outside the switch. */
9162 break;
9163 case 'D':
9164 /* Itbl operand; not yet implemented. FIXME ?? */
9165 break;
9166 /* What about all other operands like 'i', which
9167 can be specified in the opcode table? */
9168 }
9169 lastregno = regno;
9170 continue;
9171 }
9172 switch (*args++)
9173 {
9174 case 'r':
9175 case 'v':
9176 INSERT_OPERAND (RS, *ip, lastregno);
9177 continue;
9178 case 'w':
9179 INSERT_OPERAND (RT, *ip, lastregno);
9180 continue;
9181 }
9182 break;
9183
9184 case 'O': /* MDMX alignment immediate constant. */
9185 my_getExpression (&imm_expr, s);
9186 check_absolute_expr (ip, &imm_expr);
9187 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9188 as_warn ("Improper align amount (%ld), using low bits",
9189 (long) imm_expr.X_add_number);
9190 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9191 imm_expr.X_op = O_absent;
9192 s = expr_end;
9193 continue;
9194
9195 case 'Q': /* MDMX vector, element sel, or const. */
9196 if (s[0] != '$')
9197 {
9198 /* MDMX Immediate. */
9199 my_getExpression (&imm_expr, s);
9200 check_absolute_expr (ip, &imm_expr);
9201 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9202 as_warn (_("Invalid MDMX Immediate (%ld)"),
9203 (long) imm_expr.X_add_number);
9204 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9205 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9206 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9207 else
9208 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9209 imm_expr.X_op = O_absent;
9210 s = expr_end;
9211 continue;
9212 }
9213 /* Not MDMX Immediate. Fall through. */
9214 case 'X': /* MDMX destination register. */
9215 case 'Y': /* MDMX source register. */
9216 case 'Z': /* MDMX target register. */
9217 is_mdmx = 1;
9218 case 'D': /* floating point destination register */
9219 case 'S': /* floating point source register */
9220 case 'T': /* floating point target register */
9221 case 'R': /* floating point source register */
9222 case 'V':
9223 case 'W':
9224 rtype = RTYPE_FPU;
9225 if (is_mdmx
9226 || (mips_opts.ase_mdmx
9227 && (ip->insn_mo->pinfo & FP_D)
9228 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9229 | INSN_COPROC_MEMORY_DELAY
9230 | INSN_LOAD_COPROC_DELAY
9231 | INSN_LOAD_MEMORY_DELAY
9232 | INSN_STORE_MEMORY))))
9233 rtype |= RTYPE_VEC;
9234 s_reset = s;
9235 if (reg_lookup (&s, rtype, &regno))
9236 {
9237 if ((regno & 1) != 0
9238 && HAVE_32BIT_FPRS
9239 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9240 as_warn (_("Float register should be even, was %d"),
9241 regno);
9242
9243 c = *args;
9244 if (*s == ' ')
9245 ++s;
9246 if (args[1] != *s)
9247 {
9248 if (c == 'V' || c == 'W')
9249 {
9250 regno = lastregno;
9251 s = s_reset;
9252 ++args;
9253 }
9254 }
9255 switch (c)
9256 {
9257 case 'D':
9258 case 'X':
9259 INSERT_OPERAND (FD, *ip, regno);
9260 break;
9261 case 'V':
9262 case 'S':
9263 case 'Y':
9264 INSERT_OPERAND (FS, *ip, regno);
9265 break;
9266 case 'Q':
9267 /* This is like 'Z', but also needs to fix the MDMX
9268 vector/scalar select bits. Note that the
9269 scalar immediate case is handled above. */
9270 if (*s == '[')
9271 {
9272 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9273 int max_el = (is_qh ? 3 : 7);
9274 s++;
9275 my_getExpression(&imm_expr, s);
9276 check_absolute_expr (ip, &imm_expr);
9277 s = expr_end;
9278 if (imm_expr.X_add_number > max_el)
9279 as_bad(_("Bad element selector %ld"),
9280 (long) imm_expr.X_add_number);
9281 imm_expr.X_add_number &= max_el;
9282 ip->insn_opcode |= (imm_expr.X_add_number
9283 << (OP_SH_VSEL +
9284 (is_qh ? 2 : 1)));
9285 imm_expr.X_op = O_absent;
9286 if (*s != ']')
9287 as_warn(_("Expecting ']' found '%s'"), s);
9288 else
9289 s++;
9290 }
9291 else
9292 {
9293 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9294 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9295 << OP_SH_VSEL);
9296 else
9297 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9298 OP_SH_VSEL);
9299 }
9300 /* Fall through */
9301 case 'W':
9302 case 'T':
9303 case 'Z':
9304 INSERT_OPERAND (FT, *ip, regno);
9305 break;
9306 case 'R':
9307 INSERT_OPERAND (FR, *ip, regno);
9308 break;
9309 }
9310 lastregno = regno;
9311 continue;
9312 }
9313
9314 switch (*args++)
9315 {
9316 case 'V':
9317 INSERT_OPERAND (FS, *ip, lastregno);
9318 continue;
9319 case 'W':
9320 INSERT_OPERAND (FT, *ip, lastregno);
9321 continue;
9322 }
9323 break;
9324
9325 case 'I':
9326 my_getExpression (&imm_expr, s);
9327 if (imm_expr.X_op != O_big
9328 && imm_expr.X_op != O_constant)
9329 insn_error = _("absolute expression required");
9330 if (HAVE_32BIT_GPRS)
9331 normalize_constant_expr (&imm_expr);
9332 s = expr_end;
9333 continue;
9334
9335 case 'A':
9336 my_getExpression (&offset_expr, s);
9337 normalize_address_expr (&offset_expr);
9338 *imm_reloc = BFD_RELOC_32;
9339 s = expr_end;
9340 continue;
9341
9342 case 'F':
9343 case 'L':
9344 case 'f':
9345 case 'l':
9346 {
9347 int f64;
9348 int using_gprs;
9349 char *save_in;
9350 char *err;
9351 unsigned char temp[8];
9352 int len;
9353 unsigned int length;
9354 segT seg;
9355 subsegT subseg;
9356 char *p;
9357
9358 /* These only appear as the last operand in an
9359 instruction, and every instruction that accepts
9360 them in any variant accepts them in all variants.
9361 This means we don't have to worry about backing out
9362 any changes if the instruction does not match.
9363
9364 The difference between them is the size of the
9365 floating point constant and where it goes. For 'F'
9366 and 'L' the constant is 64 bits; for 'f' and 'l' it
9367 is 32 bits. Where the constant is placed is based
9368 on how the MIPS assembler does things:
9369 F -- .rdata
9370 L -- .lit8
9371 f -- immediate value
9372 l -- .lit4
9373
9374 The .lit4 and .lit8 sections are only used if
9375 permitted by the -G argument.
9376
9377 The code below needs to know whether the target register
9378 is 32 or 64 bits wide. It relies on the fact 'f' and
9379 'F' are used with GPR-based instructions and 'l' and
9380 'L' are used with FPR-based instructions. */
9381
9382 f64 = *args == 'F' || *args == 'L';
9383 using_gprs = *args == 'F' || *args == 'f';
9384
9385 save_in = input_line_pointer;
9386 input_line_pointer = s;
9387 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9388 length = len;
9389 s = input_line_pointer;
9390 input_line_pointer = save_in;
9391 if (err != NULL && *err != '\0')
9392 {
9393 as_bad (_("Bad floating point constant: %s"), err);
9394 memset (temp, '\0', sizeof temp);
9395 length = f64 ? 8 : 4;
9396 }
9397
9398 assert (length == (unsigned) (f64 ? 8 : 4));
9399
9400 if (*args == 'f'
9401 || (*args == 'l'
9402 && (g_switch_value < 4
9403 || (temp[0] == 0 && temp[1] == 0)
9404 || (temp[2] == 0 && temp[3] == 0))))
9405 {
9406 imm_expr.X_op = O_constant;
9407 if (! target_big_endian)
9408 imm_expr.X_add_number = bfd_getl32 (temp);
9409 else
9410 imm_expr.X_add_number = bfd_getb32 (temp);
9411 }
9412 else if (length > 4
9413 && ! mips_disable_float_construction
9414 /* Constants can only be constructed in GPRs and
9415 copied to FPRs if the GPRs are at least as wide
9416 as the FPRs. Force the constant into memory if
9417 we are using 64-bit FPRs but the GPRs are only
9418 32 bits wide. */
9419 && (using_gprs
9420 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9421 && ((temp[0] == 0 && temp[1] == 0)
9422 || (temp[2] == 0 && temp[3] == 0))
9423 && ((temp[4] == 0 && temp[5] == 0)
9424 || (temp[6] == 0 && temp[7] == 0)))
9425 {
9426 /* The value is simple enough to load with a couple of
9427 instructions. If using 32-bit registers, set
9428 imm_expr to the high order 32 bits and offset_expr to
9429 the low order 32 bits. Otherwise, set imm_expr to
9430 the entire 64 bit constant. */
9431 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9432 {
9433 imm_expr.X_op = O_constant;
9434 offset_expr.X_op = O_constant;
9435 if (! target_big_endian)
9436 {
9437 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9438 offset_expr.X_add_number = bfd_getl32 (temp);
9439 }
9440 else
9441 {
9442 imm_expr.X_add_number = bfd_getb32 (temp);
9443 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9444 }
9445 if (offset_expr.X_add_number == 0)
9446 offset_expr.X_op = O_absent;
9447 }
9448 else if (sizeof (imm_expr.X_add_number) > 4)
9449 {
9450 imm_expr.X_op = O_constant;
9451 if (! target_big_endian)
9452 imm_expr.X_add_number = bfd_getl64 (temp);
9453 else
9454 imm_expr.X_add_number = bfd_getb64 (temp);
9455 }
9456 else
9457 {
9458 imm_expr.X_op = O_big;
9459 imm_expr.X_add_number = 4;
9460 if (! target_big_endian)
9461 {
9462 generic_bignum[0] = bfd_getl16 (temp);
9463 generic_bignum[1] = bfd_getl16 (temp + 2);
9464 generic_bignum[2] = bfd_getl16 (temp + 4);
9465 generic_bignum[3] = bfd_getl16 (temp + 6);
9466 }
9467 else
9468 {
9469 generic_bignum[0] = bfd_getb16 (temp + 6);
9470 generic_bignum[1] = bfd_getb16 (temp + 4);
9471 generic_bignum[2] = bfd_getb16 (temp + 2);
9472 generic_bignum[3] = bfd_getb16 (temp);
9473 }
9474 }
9475 }
9476 else
9477 {
9478 const char *newname;
9479 segT new_seg;
9480
9481 /* Switch to the right section. */
9482 seg = now_seg;
9483 subseg = now_subseg;
9484 switch (*args)
9485 {
9486 default: /* unused default case avoids warnings. */
9487 case 'L':
9488 newname = RDATA_SECTION_NAME;
9489 if (g_switch_value >= 8)
9490 newname = ".lit8";
9491 break;
9492 case 'F':
9493 newname = RDATA_SECTION_NAME;
9494 break;
9495 case 'l':
9496 assert (g_switch_value >= 4);
9497 newname = ".lit4";
9498 break;
9499 }
9500 new_seg = subseg_new (newname, (subsegT) 0);
9501 if (IS_ELF)
9502 bfd_set_section_flags (stdoutput, new_seg,
9503 (SEC_ALLOC
9504 | SEC_LOAD
9505 | SEC_READONLY
9506 | SEC_DATA));
9507 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9508 if (IS_ELF && strcmp (TARGET_OS, "elf") != 0)
9509 record_alignment (new_seg, 4);
9510 else
9511 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9512 if (seg == now_seg)
9513 as_bad (_("Can't use floating point insn in this section"));
9514
9515 /* Set the argument to the current address in the
9516 section. */
9517 offset_expr.X_op = O_symbol;
9518 offset_expr.X_add_symbol =
9519 symbol_new ("L0\001", now_seg,
9520 (valueT) frag_now_fix (), frag_now);
9521 offset_expr.X_add_number = 0;
9522
9523 /* Put the floating point number into the section. */
9524 p = frag_more ((int) length);
9525 memcpy (p, temp, length);
9526
9527 /* Switch back to the original section. */
9528 subseg_set (seg, subseg);
9529 }
9530 }
9531 continue;
9532
9533 case 'i': /* 16 bit unsigned immediate */
9534 case 'j': /* 16 bit signed immediate */
9535 *imm_reloc = BFD_RELOC_LO16;
9536 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9537 {
9538 int more;
9539 offsetT minval, maxval;
9540
9541 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9542 && strcmp (insn->name, insn[1].name) == 0);
9543
9544 /* If the expression was written as an unsigned number,
9545 only treat it as signed if there are no more
9546 alternatives. */
9547 if (more
9548 && *args == 'j'
9549 && sizeof (imm_expr.X_add_number) <= 4
9550 && imm_expr.X_op == O_constant
9551 && imm_expr.X_add_number < 0
9552 && imm_expr.X_unsigned
9553 && HAVE_64BIT_GPRS)
9554 break;
9555
9556 /* For compatibility with older assemblers, we accept
9557 0x8000-0xffff as signed 16-bit numbers when only
9558 signed numbers are allowed. */
9559 if (*args == 'i')
9560 minval = 0, maxval = 0xffff;
9561 else if (more)
9562 minval = -0x8000, maxval = 0x7fff;
9563 else
9564 minval = -0x8000, maxval = 0xffff;
9565
9566 if (imm_expr.X_op != O_constant
9567 || imm_expr.X_add_number < minval
9568 || imm_expr.X_add_number > maxval)
9569 {
9570 if (more)
9571 break;
9572 if (imm_expr.X_op == O_constant
9573 || imm_expr.X_op == O_big)
9574 as_bad (_("expression out of range"));
9575 }
9576 }
9577 s = expr_end;
9578 continue;
9579
9580 case 'o': /* 16 bit offset */
9581 /* Check whether there is only a single bracketed expression
9582 left. If so, it must be the base register and the
9583 constant must be zero. */
9584 if (*s == '(' && strchr (s + 1, '(') == 0)
9585 {
9586 offset_expr.X_op = O_constant;
9587 offset_expr.X_add_number = 0;
9588 continue;
9589 }
9590
9591 /* If this value won't fit into a 16 bit offset, then go
9592 find a macro that will generate the 32 bit offset
9593 code pattern. */
9594 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9595 && (offset_expr.X_op != O_constant
9596 || offset_expr.X_add_number >= 0x8000
9597 || offset_expr.X_add_number < -0x8000))
9598 break;
9599
9600 s = expr_end;
9601 continue;
9602
9603 case 'p': /* pc relative offset */
9604 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9605 my_getExpression (&offset_expr, s);
9606 s = expr_end;
9607 continue;
9608
9609 case 'u': /* upper 16 bits */
9610 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9611 && imm_expr.X_op == O_constant
9612 && (imm_expr.X_add_number < 0
9613 || imm_expr.X_add_number >= 0x10000))
9614 as_bad (_("lui expression not in range 0..65535"));
9615 s = expr_end;
9616 continue;
9617
9618 case 'a': /* 26 bit address */
9619 my_getExpression (&offset_expr, s);
9620 s = expr_end;
9621 *offset_reloc = BFD_RELOC_MIPS_JMP;
9622 continue;
9623
9624 case 'N': /* 3 bit branch condition code */
9625 case 'M': /* 3 bit compare condition code */
9626 rtype = RTYPE_CCC;
9627 if (ip->insn_mo->pinfo & (FP_D| FP_S))
9628 rtype |= RTYPE_FCC;
9629 if (!reg_lookup (&s, rtype, &regno))
9630 break;
9631 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9632 || strcmp(str + strlen(str) - 5, "any2f") == 0
9633 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9634 && (regno & 1) != 0)
9635 as_warn(_("Condition code register should be even for %s, was %d"),
9636 str, regno);
9637 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9638 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9639 && (regno & 3) != 0)
9640 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9641 str, regno);
9642 if (*args == 'N')
9643 INSERT_OPERAND (BCC, *ip, regno);
9644 else
9645 INSERT_OPERAND (CCC, *ip, regno);
9646 continue;
9647
9648 case 'H':
9649 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9650 s += 2;
9651 if (ISDIGIT (*s))
9652 {
9653 c = 0;
9654 do
9655 {
9656 c *= 10;
9657 c += *s - '0';
9658 ++s;
9659 }
9660 while (ISDIGIT (*s));
9661 }
9662 else
9663 c = 8; /* Invalid sel value. */
9664
9665 if (c > 7)
9666 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9667 ip->insn_opcode |= c;
9668 continue;
9669
9670 case 'e':
9671 /* Must be at least one digit. */
9672 my_getExpression (&imm_expr, s);
9673 check_absolute_expr (ip, &imm_expr);
9674
9675 if ((unsigned long) imm_expr.X_add_number
9676 > (unsigned long) OP_MASK_VECBYTE)
9677 {
9678 as_bad (_("bad byte vector index (%ld)"),
9679 (long) imm_expr.X_add_number);
9680 imm_expr.X_add_number = 0;
9681 }
9682
9683 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
9684 imm_expr.X_op = O_absent;
9685 s = expr_end;
9686 continue;
9687
9688 case '%':
9689 my_getExpression (&imm_expr, s);
9690 check_absolute_expr (ip, &imm_expr);
9691
9692 if ((unsigned long) imm_expr.X_add_number
9693 > (unsigned long) OP_MASK_VECALIGN)
9694 {
9695 as_bad (_("bad byte vector index (%ld)"),
9696 (long) imm_expr.X_add_number);
9697 imm_expr.X_add_number = 0;
9698 }
9699
9700 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
9701 imm_expr.X_op = O_absent;
9702 s = expr_end;
9703 continue;
9704
9705 default:
9706 as_bad (_("bad char = '%c'\n"), *args);
9707 internalError ();
9708 }
9709 break;
9710 }
9711 /* Args don't match. */
9712 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9713 !strcmp (insn->name, insn[1].name))
9714 {
9715 ++insn;
9716 s = argsStart;
9717 insn_error = _("illegal operands");
9718 continue;
9719 }
9720 if (save_c)
9721 *(--s) = save_c;
9722 insn_error = _("illegal operands");
9723 return;
9724 }
9725 }
9726
9727 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9728
9729 /* This routine assembles an instruction into its binary format when
9730 assembling for the mips16. As a side effect, it sets one of the
9731 global variables imm_reloc or offset_reloc to the type of
9732 relocation to do if one of the operands is an address expression.
9733 It also sets mips16_small and mips16_ext if the user explicitly
9734 requested a small or extended instruction. */
9735
9736 static void
9737 mips16_ip (char *str, struct mips_cl_insn *ip)
9738 {
9739 char *s;
9740 const char *args;
9741 struct mips_opcode *insn;
9742 char *argsstart;
9743 unsigned int regno;
9744 unsigned int lastregno = 0;
9745 char *s_reset;
9746 size_t i;
9747
9748 insn_error = NULL;
9749
9750 mips16_small = FALSE;
9751 mips16_ext = FALSE;
9752
9753 for (s = str; ISLOWER (*s); ++s)
9754 ;
9755 switch (*s)
9756 {
9757 case '\0':
9758 break;
9759
9760 case ' ':
9761 *s++ = '\0';
9762 break;
9763
9764 case '.':
9765 if (s[1] == 't' && s[2] == ' ')
9766 {
9767 *s = '\0';
9768 mips16_small = TRUE;
9769 s += 3;
9770 break;
9771 }
9772 else if (s[1] == 'e' && s[2] == ' ')
9773 {
9774 *s = '\0';
9775 mips16_ext = TRUE;
9776 s += 3;
9777 break;
9778 }
9779 /* Fall through. */
9780 default:
9781 insn_error = _("unknown opcode");
9782 return;
9783 }
9784
9785 if (mips_opts.noautoextend && ! mips16_ext)
9786 mips16_small = TRUE;
9787
9788 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9789 {
9790 insn_error = _("unrecognized opcode");
9791 return;
9792 }
9793
9794 argsstart = s;
9795 for (;;)
9796 {
9797 bfd_boolean ok;
9798
9799 assert (strcmp (insn->name, str) == 0);
9800
9801 if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
9802 ok = TRUE;
9803 else
9804 ok = FALSE;
9805
9806 if (! ok)
9807 {
9808 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
9809 && strcmp (insn->name, insn[1].name) == 0)
9810 {
9811 ++insn;
9812 continue;
9813 }
9814 else
9815 {
9816 if (!insn_error)
9817 {
9818 static char buf[100];
9819 sprintf (buf,
9820 _("opcode not supported on this processor: %s (%s)"),
9821 mips_cpu_info_from_arch (mips_opts.arch)->name,
9822 mips_cpu_info_from_isa (mips_opts.isa)->name);
9823 insn_error = buf;
9824 }
9825 return;
9826 }
9827 }
9828
9829 create_insn (ip, insn);
9830 imm_expr.X_op = O_absent;
9831 imm_reloc[0] = BFD_RELOC_UNUSED;
9832 imm_reloc[1] = BFD_RELOC_UNUSED;
9833 imm_reloc[2] = BFD_RELOC_UNUSED;
9834 imm2_expr.X_op = O_absent;
9835 offset_expr.X_op = O_absent;
9836 offset_reloc[0] = BFD_RELOC_UNUSED;
9837 offset_reloc[1] = BFD_RELOC_UNUSED;
9838 offset_reloc[2] = BFD_RELOC_UNUSED;
9839 for (args = insn->args; 1; ++args)
9840 {
9841 int c;
9842
9843 if (*s == ' ')
9844 ++s;
9845
9846 /* In this switch statement we call break if we did not find
9847 a match, continue if we did find a match, or return if we
9848 are done. */
9849
9850 c = *args;
9851 switch (c)
9852 {
9853 case '\0':
9854 if (*s == '\0')
9855 {
9856 /* Stuff the immediate value in now, if we can. */
9857 if (imm_expr.X_op == O_constant
9858 && *imm_reloc > BFD_RELOC_UNUSED
9859 && insn->pinfo != INSN_MACRO)
9860 {
9861 valueT tmp;
9862
9863 switch (*offset_reloc)
9864 {
9865 case BFD_RELOC_MIPS16_HI16_S:
9866 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
9867 break;
9868
9869 case BFD_RELOC_MIPS16_HI16:
9870 tmp = imm_expr.X_add_number >> 16;
9871 break;
9872
9873 case BFD_RELOC_MIPS16_LO16:
9874 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
9875 - 0x8000;
9876 break;
9877
9878 case BFD_RELOC_UNUSED:
9879 tmp = imm_expr.X_add_number;
9880 break;
9881
9882 default:
9883 internalError ();
9884 }
9885 *offset_reloc = BFD_RELOC_UNUSED;
9886
9887 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9888 tmp, TRUE, mips16_small,
9889 mips16_ext, &ip->insn_opcode,
9890 &ip->use_extend, &ip->extend);
9891 imm_expr.X_op = O_absent;
9892 *imm_reloc = BFD_RELOC_UNUSED;
9893 }
9894
9895 return;
9896 }
9897 break;
9898
9899 case ',':
9900 if (*s++ == c)
9901 continue;
9902 s--;
9903 switch (*++args)
9904 {
9905 case 'v':
9906 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9907 continue;
9908 case 'w':
9909 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9910 continue;
9911 }
9912 break;
9913
9914 case '(':
9915 case ')':
9916 if (*s++ == c)
9917 continue;
9918 break;
9919
9920 case 'v':
9921 case 'w':
9922 if (s[0] != '$')
9923 {
9924 if (c == 'v')
9925 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9926 else
9927 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9928 ++args;
9929 continue;
9930 }
9931 /* Fall through. */
9932 case 'x':
9933 case 'y':
9934 case 'z':
9935 case 'Z':
9936 case '0':
9937 case 'S':
9938 case 'R':
9939 case 'X':
9940 case 'Y':
9941 s_reset = s;
9942 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
9943 {
9944 if (c == 'v' || c == 'w')
9945 {
9946 if (c == 'v')
9947 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9948 else
9949 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9950 ++args;
9951 continue;
9952 }
9953 break;
9954 }
9955
9956 if (*s == ' ')
9957 ++s;
9958 if (args[1] != *s)
9959 {
9960 if (c == 'v' || c == 'w')
9961 {
9962 regno = mips16_to_32_reg_map[lastregno];
9963 s = s_reset;
9964 ++args;
9965 }
9966 }
9967
9968 switch (c)
9969 {
9970 case 'x':
9971 case 'y':
9972 case 'z':
9973 case 'v':
9974 case 'w':
9975 case 'Z':
9976 regno = mips32_to_16_reg_map[regno];
9977 break;
9978
9979 case '0':
9980 if (regno != 0)
9981 regno = ILLEGAL_REG;
9982 break;
9983
9984 case 'S':
9985 if (regno != SP)
9986 regno = ILLEGAL_REG;
9987 break;
9988
9989 case 'R':
9990 if (regno != RA)
9991 regno = ILLEGAL_REG;
9992 break;
9993
9994 case 'X':
9995 case 'Y':
9996 if (regno == AT && mips_opts.at)
9997 {
9998 if (mips_opts.at == ATREG)
9999 as_warn (_("used $at without \".set noat\""));
10000 else
10001 as_warn (_("used $%u with \".set at=$%u\""),
10002 regno, mips_opts.at);
10003 }
10004 break;
10005
10006 default:
10007 internalError ();
10008 }
10009
10010 if (regno == ILLEGAL_REG)
10011 break;
10012
10013 switch (c)
10014 {
10015 case 'x':
10016 case 'v':
10017 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10018 break;
10019 case 'y':
10020 case 'w':
10021 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10022 break;
10023 case 'z':
10024 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10025 break;
10026 case 'Z':
10027 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10028 case '0':
10029 case 'S':
10030 case 'R':
10031 break;
10032 case 'X':
10033 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10034 break;
10035 case 'Y':
10036 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10037 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10038 break;
10039 default:
10040 internalError ();
10041 }
10042
10043 lastregno = regno;
10044 continue;
10045
10046 case 'P':
10047 if (strncmp (s, "$pc", 3) == 0)
10048 {
10049 s += 3;
10050 continue;
10051 }
10052 break;
10053
10054 case '5':
10055 case 'H':
10056 case 'W':
10057 case 'D':
10058 case 'j':
10059 case 'V':
10060 case 'C':
10061 case 'U':
10062 case 'k':
10063 case 'K':
10064 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10065 if (i > 0)
10066 {
10067 if (imm_expr.X_op != O_constant)
10068 {
10069 mips16_ext = TRUE;
10070 ip->use_extend = TRUE;
10071 ip->extend = 0;
10072 }
10073 else
10074 {
10075 /* We need to relax this instruction. */
10076 *offset_reloc = *imm_reloc;
10077 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10078 }
10079 s = expr_end;
10080 continue;
10081 }
10082 *imm_reloc = BFD_RELOC_UNUSED;
10083 /* Fall through. */
10084 case '<':
10085 case '>':
10086 case '[':
10087 case ']':
10088 case '4':
10089 case '8':
10090 my_getExpression (&imm_expr, s);
10091 if (imm_expr.X_op == O_register)
10092 {
10093 /* What we thought was an expression turned out to
10094 be a register. */
10095
10096 if (s[0] == '(' && args[1] == '(')
10097 {
10098 /* It looks like the expression was omitted
10099 before a register indirection, which means
10100 that the expression is implicitly zero. We
10101 still set up imm_expr, so that we handle
10102 explicit extensions correctly. */
10103 imm_expr.X_op = O_constant;
10104 imm_expr.X_add_number = 0;
10105 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10106 continue;
10107 }
10108
10109 break;
10110 }
10111
10112 /* We need to relax this instruction. */
10113 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10114 s = expr_end;
10115 continue;
10116
10117 case 'p':
10118 case 'q':
10119 case 'A':
10120 case 'B':
10121 case 'E':
10122 /* We use offset_reloc rather than imm_reloc for the PC
10123 relative operands. This lets macros with both
10124 immediate and address operands work correctly. */
10125 my_getExpression (&offset_expr, s);
10126
10127 if (offset_expr.X_op == O_register)
10128 break;
10129
10130 /* We need to relax this instruction. */
10131 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10132 s = expr_end;
10133 continue;
10134
10135 case '6': /* break code */
10136 my_getExpression (&imm_expr, s);
10137 check_absolute_expr (ip, &imm_expr);
10138 if ((unsigned long) imm_expr.X_add_number > 63)
10139 as_warn (_("Invalid value for `%s' (%lu)"),
10140 ip->insn_mo->name,
10141 (unsigned long) imm_expr.X_add_number);
10142 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10143 imm_expr.X_op = O_absent;
10144 s = expr_end;
10145 continue;
10146
10147 case 'a': /* 26 bit address */
10148 my_getExpression (&offset_expr, s);
10149 s = expr_end;
10150 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10151 ip->insn_opcode <<= 16;
10152 continue;
10153
10154 case 'l': /* register list for entry macro */
10155 case 'L': /* register list for exit macro */
10156 {
10157 int mask;
10158
10159 if (c == 'l')
10160 mask = 0;
10161 else
10162 mask = 7 << 3;
10163 while (*s != '\0')
10164 {
10165 unsigned int freg, reg1, reg2;
10166
10167 while (*s == ' ' || *s == ',')
10168 ++s;
10169 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10170 freg = 0;
10171 else if (reg_lookup (&s, RTYPE_FPU, &reg1))
10172 freg = 1;
10173 else
10174 {
10175 as_bad (_("can't parse register list"));
10176 break;
10177 }
10178 if (*s == ' ')
10179 ++s;
10180 if (*s != '-')
10181 reg2 = reg1;
10182 else
10183 {
10184 ++s;
10185 if (!reg_lookup (&s, freg ? RTYPE_FPU
10186 : (RTYPE_GP | RTYPE_NUM), &reg2))
10187 {
10188 as_bad (_("invalid register list"));
10189 break;
10190 }
10191 }
10192 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10193 {
10194 mask &= ~ (7 << 3);
10195 mask |= 5 << 3;
10196 }
10197 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10198 {
10199 mask &= ~ (7 << 3);
10200 mask |= 6 << 3;
10201 }
10202 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10203 mask |= (reg2 - 3) << 3;
10204 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10205 mask |= (reg2 - 15) << 1;
10206 else if (reg1 == RA && reg2 == RA)
10207 mask |= 1;
10208 else
10209 {
10210 as_bad (_("invalid register list"));
10211 break;
10212 }
10213 }
10214 /* The mask is filled in in the opcode table for the
10215 benefit of the disassembler. We remove it before
10216 applying the actual mask. */
10217 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10218 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10219 }
10220 continue;
10221
10222 case 'm': /* Register list for save insn. */
10223 case 'M': /* Register list for restore insn. */
10224 {
10225 int opcode = 0;
10226 int framesz = 0, seen_framesz = 0;
10227 int args = 0, statics = 0, sregs = 0;
10228
10229 while (*s != '\0')
10230 {
10231 unsigned int reg1, reg2;
10232
10233 SKIP_SPACE_TABS (s);
10234 while (*s == ',')
10235 ++s;
10236 SKIP_SPACE_TABS (s);
10237
10238 my_getExpression (&imm_expr, s);
10239 if (imm_expr.X_op == O_constant)
10240 {
10241 /* Handle the frame size. */
10242 if (seen_framesz)
10243 {
10244 as_bad (_("more than one frame size in list"));
10245 break;
10246 }
10247 seen_framesz = 1;
10248 framesz = imm_expr.X_add_number;
10249 imm_expr.X_op = O_absent;
10250 s = expr_end;
10251 continue;
10252 }
10253
10254 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10255 {
10256 as_bad (_("can't parse register list"));
10257 break;
10258 }
10259
10260 while (*s == ' ')
10261 ++s;
10262
10263 if (*s != '-')
10264 reg2 = reg1;
10265 else
10266 {
10267 ++s;
10268 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
10269 || reg2 < reg1)
10270 {
10271 as_bad (_("can't parse register list"));
10272 break;
10273 }
10274 }
10275
10276 while (reg1 <= reg2)
10277 {
10278 if (reg1 >= 4 && reg1 <= 7)
10279 {
10280 if (!seen_framesz)
10281 /* args $a0-$a3 */
10282 args |= 1 << (reg1 - 4);
10283 else
10284 /* statics $a0-$a3 */
10285 statics |= 1 << (reg1 - 4);
10286 }
10287 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10288 {
10289 /* $s0-$s8 */
10290 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10291 }
10292 else if (reg1 == 31)
10293 {
10294 /* Add $ra to insn. */
10295 opcode |= 0x40;
10296 }
10297 else
10298 {
10299 as_bad (_("unexpected register in list"));
10300 break;
10301 }
10302 if (++reg1 == 24)
10303 reg1 = 30;
10304 }
10305 }
10306
10307 /* Encode args/statics combination. */
10308 if (args & statics)
10309 as_bad (_("arg/static registers overlap"));
10310 else if (args == 0xf)
10311 /* All $a0-$a3 are args. */
10312 opcode |= MIPS16_ALL_ARGS << 16;
10313 else if (statics == 0xf)
10314 /* All $a0-$a3 are statics. */
10315 opcode |= MIPS16_ALL_STATICS << 16;
10316 else
10317 {
10318 int narg = 0, nstat = 0;
10319
10320 /* Count arg registers. */
10321 while (args & 0x1)
10322 {
10323 args >>= 1;
10324 narg++;
10325 }
10326 if (args != 0)
10327 as_bad (_("invalid arg register list"));
10328
10329 /* Count static registers. */
10330 while (statics & 0x8)
10331 {
10332 statics = (statics << 1) & 0xf;
10333 nstat++;
10334 }
10335 if (statics != 0)
10336 as_bad (_("invalid static register list"));
10337
10338 /* Encode args/statics. */
10339 opcode |= ((narg << 2) | nstat) << 16;
10340 }
10341
10342 /* Encode $s0/$s1. */
10343 if (sregs & (1 << 0)) /* $s0 */
10344 opcode |= 0x20;
10345 if (sregs & (1 << 1)) /* $s1 */
10346 opcode |= 0x10;
10347 sregs >>= 2;
10348
10349 if (sregs != 0)
10350 {
10351 /* Count regs $s2-$s8. */
10352 int nsreg = 0;
10353 while (sregs & 1)
10354 {
10355 sregs >>= 1;
10356 nsreg++;
10357 }
10358 if (sregs != 0)
10359 as_bad (_("invalid static register list"));
10360 /* Encode $s2-$s8. */
10361 opcode |= nsreg << 24;
10362 }
10363
10364 /* Encode frame size. */
10365 if (!seen_framesz)
10366 as_bad (_("missing frame size"));
10367 else if ((framesz & 7) != 0 || framesz < 0
10368 || framesz > 0xff * 8)
10369 as_bad (_("invalid frame size"));
10370 else if (framesz != 128 || (opcode >> 16) != 0)
10371 {
10372 framesz /= 8;
10373 opcode |= (((framesz & 0xf0) << 16)
10374 | (framesz & 0x0f));
10375 }
10376
10377 /* Finally build the instruction. */
10378 if ((opcode >> 16) != 0 || framesz == 0)
10379 {
10380 ip->use_extend = TRUE;
10381 ip->extend = opcode >> 16;
10382 }
10383 ip->insn_opcode |= opcode & 0x7f;
10384 }
10385 continue;
10386
10387 case 'e': /* extend code */
10388 my_getExpression (&imm_expr, s);
10389 check_absolute_expr (ip, &imm_expr);
10390 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10391 {
10392 as_warn (_("Invalid value for `%s' (%lu)"),
10393 ip->insn_mo->name,
10394 (unsigned long) imm_expr.X_add_number);
10395 imm_expr.X_add_number &= 0x7ff;
10396 }
10397 ip->insn_opcode |= imm_expr.X_add_number;
10398 imm_expr.X_op = O_absent;
10399 s = expr_end;
10400 continue;
10401
10402 default:
10403 internalError ();
10404 }
10405 break;
10406 }
10407
10408 /* Args don't match. */
10409 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10410 strcmp (insn->name, insn[1].name) == 0)
10411 {
10412 ++insn;
10413 s = argsstart;
10414 continue;
10415 }
10416
10417 insn_error = _("illegal operands");
10418
10419 return;
10420 }
10421 }
10422
10423 /* This structure holds information we know about a mips16 immediate
10424 argument type. */
10425
10426 struct mips16_immed_operand
10427 {
10428 /* The type code used in the argument string in the opcode table. */
10429 int type;
10430 /* The number of bits in the short form of the opcode. */
10431 int nbits;
10432 /* The number of bits in the extended form of the opcode. */
10433 int extbits;
10434 /* The amount by which the short form is shifted when it is used;
10435 for example, the sw instruction has a shift count of 2. */
10436 int shift;
10437 /* The amount by which the short form is shifted when it is stored
10438 into the instruction code. */
10439 int op_shift;
10440 /* Non-zero if the short form is unsigned. */
10441 int unsp;
10442 /* Non-zero if the extended form is unsigned. */
10443 int extu;
10444 /* Non-zero if the value is PC relative. */
10445 int pcrel;
10446 };
10447
10448 /* The mips16 immediate operand types. */
10449
10450 static const struct mips16_immed_operand mips16_immed_operands[] =
10451 {
10452 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10453 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10454 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10455 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10456 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10457 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10458 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10459 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10460 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10461 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10462 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10463 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10464 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10465 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10466 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10467 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10468 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10469 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10470 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10471 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10472 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10473 };
10474
10475 #define MIPS16_NUM_IMMED \
10476 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10477
10478 /* Handle a mips16 instruction with an immediate value. This or's the
10479 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10480 whether an extended value is needed; if one is needed, it sets
10481 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10482 If SMALL is true, an unextended opcode was explicitly requested.
10483 If EXT is true, an extended opcode was explicitly requested. If
10484 WARN is true, warn if EXT does not match reality. */
10485
10486 static void
10487 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10488 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10489 unsigned long *insn, bfd_boolean *use_extend,
10490 unsigned short *extend)
10491 {
10492 const struct mips16_immed_operand *op;
10493 int mintiny, maxtiny;
10494 bfd_boolean needext;
10495
10496 op = mips16_immed_operands;
10497 while (op->type != type)
10498 {
10499 ++op;
10500 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10501 }
10502
10503 if (op->unsp)
10504 {
10505 if (type == '<' || type == '>' || type == '[' || type == ']')
10506 {
10507 mintiny = 1;
10508 maxtiny = 1 << op->nbits;
10509 }
10510 else
10511 {
10512 mintiny = 0;
10513 maxtiny = (1 << op->nbits) - 1;
10514 }
10515 }
10516 else
10517 {
10518 mintiny = - (1 << (op->nbits - 1));
10519 maxtiny = (1 << (op->nbits - 1)) - 1;
10520 }
10521
10522 /* Branch offsets have an implicit 0 in the lowest bit. */
10523 if (type == 'p' || type == 'q')
10524 val /= 2;
10525
10526 if ((val & ((1 << op->shift) - 1)) != 0
10527 || val < (mintiny << op->shift)
10528 || val > (maxtiny << op->shift))
10529 needext = TRUE;
10530 else
10531 needext = FALSE;
10532
10533 if (warn && ext && ! needext)
10534 as_warn_where (file, line,
10535 _("extended operand requested but not required"));
10536 if (small && needext)
10537 as_bad_where (file, line, _("invalid unextended operand value"));
10538
10539 if (small || (! ext && ! needext))
10540 {
10541 int insnval;
10542
10543 *use_extend = FALSE;
10544 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10545 insnval <<= op->op_shift;
10546 *insn |= insnval;
10547 }
10548 else
10549 {
10550 long minext, maxext;
10551 int extval;
10552
10553 if (op->extu)
10554 {
10555 minext = 0;
10556 maxext = (1 << op->extbits) - 1;
10557 }
10558 else
10559 {
10560 minext = - (1 << (op->extbits - 1));
10561 maxext = (1 << (op->extbits - 1)) - 1;
10562 }
10563 if (val < minext || val > maxext)
10564 as_bad_where (file, line,
10565 _("operand value out of range for instruction"));
10566
10567 *use_extend = TRUE;
10568 if (op->extbits == 16)
10569 {
10570 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10571 val &= 0x1f;
10572 }
10573 else if (op->extbits == 15)
10574 {
10575 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10576 val &= 0xf;
10577 }
10578 else
10579 {
10580 extval = ((val & 0x1f) << 6) | (val & 0x20);
10581 val = 0;
10582 }
10583
10584 *extend = (unsigned short) extval;
10585 *insn |= val;
10586 }
10587 }
10588 \f
10589 struct percent_op_match
10590 {
10591 const char *str;
10592 bfd_reloc_code_real_type reloc;
10593 };
10594
10595 static const struct percent_op_match mips_percent_op[] =
10596 {
10597 {"%lo", BFD_RELOC_LO16},
10598 #ifdef OBJ_ELF
10599 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10600 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10601 {"%call16", BFD_RELOC_MIPS_CALL16},
10602 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10603 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10604 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10605 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10606 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10607 {"%got", BFD_RELOC_MIPS_GOT16},
10608 {"%gp_rel", BFD_RELOC_GPREL16},
10609 {"%half", BFD_RELOC_16},
10610 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10611 {"%higher", BFD_RELOC_MIPS_HIGHER},
10612 {"%neg", BFD_RELOC_MIPS_SUB},
10613 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
10614 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
10615 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
10616 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
10617 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
10618 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
10619 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
10620 #endif
10621 {"%hi", BFD_RELOC_HI16_S}
10622 };
10623
10624 static const struct percent_op_match mips16_percent_op[] =
10625 {
10626 {"%lo", BFD_RELOC_MIPS16_LO16},
10627 {"%gprel", BFD_RELOC_MIPS16_GPREL},
10628 {"%hi", BFD_RELOC_MIPS16_HI16_S}
10629 };
10630
10631
10632 /* Return true if *STR points to a relocation operator. When returning true,
10633 move *STR over the operator and store its relocation code in *RELOC.
10634 Leave both *STR and *RELOC alone when returning false. */
10635
10636 static bfd_boolean
10637 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10638 {
10639 const struct percent_op_match *percent_op;
10640 size_t limit, i;
10641
10642 if (mips_opts.mips16)
10643 {
10644 percent_op = mips16_percent_op;
10645 limit = ARRAY_SIZE (mips16_percent_op);
10646 }
10647 else
10648 {
10649 percent_op = mips_percent_op;
10650 limit = ARRAY_SIZE (mips_percent_op);
10651 }
10652
10653 for (i = 0; i < limit; i++)
10654 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10655 {
10656 int len = strlen (percent_op[i].str);
10657
10658 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
10659 continue;
10660
10661 *str += strlen (percent_op[i].str);
10662 *reloc = percent_op[i].reloc;
10663
10664 /* Check whether the output BFD supports this relocation.
10665 If not, issue an error and fall back on something safe. */
10666 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10667 {
10668 as_bad ("relocation %s isn't supported by the current ABI",
10669 percent_op[i].str);
10670 *reloc = BFD_RELOC_UNUSED;
10671 }
10672 return TRUE;
10673 }
10674 return FALSE;
10675 }
10676
10677
10678 /* Parse string STR as a 16-bit relocatable operand. Store the
10679 expression in *EP and the relocations in the array starting
10680 at RELOC. Return the number of relocation operators used.
10681
10682 On exit, EXPR_END points to the first character after the expression. */
10683
10684 static size_t
10685 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10686 char *str)
10687 {
10688 bfd_reloc_code_real_type reversed_reloc[3];
10689 size_t reloc_index, i;
10690 int crux_depth, str_depth;
10691 char *crux;
10692
10693 /* Search for the start of the main expression, recoding relocations
10694 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10695 of the main expression and with CRUX_DEPTH containing the number
10696 of open brackets at that point. */
10697 reloc_index = -1;
10698 str_depth = 0;
10699 do
10700 {
10701 reloc_index++;
10702 crux = str;
10703 crux_depth = str_depth;
10704
10705 /* Skip over whitespace and brackets, keeping count of the number
10706 of brackets. */
10707 while (*str == ' ' || *str == '\t' || *str == '(')
10708 if (*str++ == '(')
10709 str_depth++;
10710 }
10711 while (*str == '%'
10712 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10713 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10714
10715 my_getExpression (ep, crux);
10716 str = expr_end;
10717
10718 /* Match every open bracket. */
10719 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10720 if (*str++ == ')')
10721 crux_depth--;
10722
10723 if (crux_depth > 0)
10724 as_bad ("unclosed '('");
10725
10726 expr_end = str;
10727
10728 if (reloc_index != 0)
10729 {
10730 prev_reloc_op_frag = frag_now;
10731 for (i = 0; i < reloc_index; i++)
10732 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10733 }
10734
10735 return reloc_index;
10736 }
10737
10738 static void
10739 my_getExpression (expressionS *ep, char *str)
10740 {
10741 char *save_in;
10742 valueT val;
10743
10744 save_in = input_line_pointer;
10745 input_line_pointer = str;
10746 expression (ep);
10747 expr_end = input_line_pointer;
10748 input_line_pointer = save_in;
10749
10750 /* If we are in mips16 mode, and this is an expression based on `.',
10751 then we bump the value of the symbol by 1 since that is how other
10752 text symbols are handled. We don't bother to handle complex
10753 expressions, just `.' plus or minus a constant. */
10754 if (mips_opts.mips16
10755 && ep->X_op == O_symbol
10756 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10757 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10758 && symbol_get_frag (ep->X_add_symbol) == frag_now
10759 && symbol_constant_p (ep->X_add_symbol)
10760 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10761 S_SET_VALUE (ep->X_add_symbol, val + 1);
10762 }
10763
10764 char *
10765 md_atof (int type, char *litP, int *sizeP)
10766 {
10767 return ieee_md_atof (type, litP, sizeP, target_big_endian);
10768 }
10769
10770 void
10771 md_number_to_chars (char *buf, valueT val, int n)
10772 {
10773 if (target_big_endian)
10774 number_to_chars_bigendian (buf, val, n);
10775 else
10776 number_to_chars_littleendian (buf, val, n);
10777 }
10778 \f
10779 #ifdef OBJ_ELF
10780 static int support_64bit_objects(void)
10781 {
10782 const char **list, **l;
10783 int yes;
10784
10785 list = bfd_target_list ();
10786 for (l = list; *l != NULL; l++)
10787 #ifdef TE_TMIPS
10788 /* This is traditional mips */
10789 if (strcmp (*l, "elf64-tradbigmips") == 0
10790 || strcmp (*l, "elf64-tradlittlemips") == 0)
10791 #else
10792 if (strcmp (*l, "elf64-bigmips") == 0
10793 || strcmp (*l, "elf64-littlemips") == 0)
10794 #endif
10795 break;
10796 yes = (*l != NULL);
10797 free (list);
10798 return yes;
10799 }
10800 #endif /* OBJ_ELF */
10801
10802 const char *md_shortopts = "O::g::G:";
10803
10804 struct option md_longopts[] =
10805 {
10806 /* Options which specify architecture. */
10807 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10808 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10809 {"march", required_argument, NULL, OPTION_MARCH},
10810 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10811 {"mtune", required_argument, NULL, OPTION_MTUNE},
10812 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10813 {"mips0", no_argument, NULL, OPTION_MIPS1},
10814 {"mips1", no_argument, NULL, OPTION_MIPS1},
10815 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10816 {"mips2", no_argument, NULL, OPTION_MIPS2},
10817 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10818 {"mips3", no_argument, NULL, OPTION_MIPS3},
10819 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10820 {"mips4", no_argument, NULL, OPTION_MIPS4},
10821 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10822 {"mips5", no_argument, NULL, OPTION_MIPS5},
10823 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10824 {"mips32", no_argument, NULL, OPTION_MIPS32},
10825 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10826 {"mips64", no_argument, NULL, OPTION_MIPS64},
10827 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10828 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10829 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10830 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10831
10832 /* Options which specify Application Specific Extensions (ASEs). */
10833 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10834 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10835 {"mips16", no_argument, NULL, OPTION_MIPS16},
10836 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10837 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10838 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10839 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10840 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10841 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10842 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10843 {"mdmx", no_argument, NULL, OPTION_MDMX},
10844 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10845 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10846 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10847 {"mdsp", no_argument, NULL, OPTION_DSP},
10848 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10849 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
10850 #define OPTION_MT (OPTION_ASE_BASE + 8)
10851 {"mmt", no_argument, NULL, OPTION_MT},
10852 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10853 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
10854 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10855 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
10856 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10857 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
10858 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
10859 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
10860 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
10861 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
10862
10863 /* Old-style architecture options. Don't add more of these. */
10864 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
10865 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10866 {"m4650", no_argument, NULL, OPTION_M4650},
10867 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10868 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10869 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10870 {"m4010", no_argument, NULL, OPTION_M4010},
10871 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10872 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10873 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10874 {"m4100", no_argument, NULL, OPTION_M4100},
10875 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10876 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10877 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10878 {"m3900", no_argument, NULL, OPTION_M3900},
10879 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10880 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10881
10882 /* Options which enable bug fixes. */
10883 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10884 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10885 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10886 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10887 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10888 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10889 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10890 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10891 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10892 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10893 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10894 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10895 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
10896 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
10897
10898 /* Miscellaneous options. */
10899 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10900 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10901 {"trap", no_argument, NULL, OPTION_TRAP},
10902 {"no-break", no_argument, NULL, OPTION_TRAP},
10903 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10904 {"break", no_argument, NULL, OPTION_BREAK},
10905 {"no-trap", no_argument, NULL, OPTION_BREAK},
10906 #define OPTION_EB (OPTION_MISC_BASE + 2)
10907 {"EB", no_argument, NULL, OPTION_EB},
10908 #define OPTION_EL (OPTION_MISC_BASE + 3)
10909 {"EL", no_argument, NULL, OPTION_EL},
10910 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10911 {"mfp32", no_argument, NULL, OPTION_FP32},
10912 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10913 {"mgp32", no_argument, NULL, OPTION_GP32},
10914 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10915 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10916 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10917 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10918 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10919 {"mfp64", no_argument, NULL, OPTION_FP64},
10920 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10921 {"mgp64", no_argument, NULL, OPTION_GP64},
10922 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10923 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10924 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10925 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10926 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10927 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10928 {"mshared", no_argument, NULL, OPTION_MSHARED},
10929 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
10930 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10931 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10932 {"msym32", no_argument, NULL, OPTION_MSYM32},
10933 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
10934
10935 /* ELF-specific options. */
10936 #ifdef OBJ_ELF
10937 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10938 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10939 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10940 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10941 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10942 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10943 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10944 {"xgot", no_argument, NULL, OPTION_XGOT},
10945 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10946 {"mabi", required_argument, NULL, OPTION_MABI},
10947 #define OPTION_32 (OPTION_ELF_BASE + 4)
10948 {"32", no_argument, NULL, OPTION_32},
10949 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10950 {"n32", no_argument, NULL, OPTION_N32},
10951 #define OPTION_64 (OPTION_ELF_BASE + 6)
10952 {"64", no_argument, NULL, OPTION_64},
10953 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10954 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10955 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10956 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10957 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10958 {"mpdr", no_argument, NULL, OPTION_PDR},
10959 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10960 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10961 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10962 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
10963 #endif /* OBJ_ELF */
10964
10965 {NULL, no_argument, NULL, 0}
10966 };
10967 size_t md_longopts_size = sizeof (md_longopts);
10968
10969 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10970 NEW_VALUE. Warn if another value was already specified. Note:
10971 we have to defer parsing the -march and -mtune arguments in order
10972 to handle 'from-abi' correctly, since the ABI might be specified
10973 in a later argument. */
10974
10975 static void
10976 mips_set_option_string (const char **string_ptr, const char *new_value)
10977 {
10978 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10979 as_warn (_("A different %s was already specified, is now %s"),
10980 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10981 new_value);
10982
10983 *string_ptr = new_value;
10984 }
10985
10986 int
10987 md_parse_option (int c, char *arg)
10988 {
10989 switch (c)
10990 {
10991 case OPTION_CONSTRUCT_FLOATS:
10992 mips_disable_float_construction = 0;
10993 break;
10994
10995 case OPTION_NO_CONSTRUCT_FLOATS:
10996 mips_disable_float_construction = 1;
10997 break;
10998
10999 case OPTION_TRAP:
11000 mips_trap = 1;
11001 break;
11002
11003 case OPTION_BREAK:
11004 mips_trap = 0;
11005 break;
11006
11007 case OPTION_EB:
11008 target_big_endian = 1;
11009 break;
11010
11011 case OPTION_EL:
11012 target_big_endian = 0;
11013 break;
11014
11015 case 'O':
11016 if (arg && arg[0] == '0')
11017 mips_optimize = 1;
11018 else
11019 mips_optimize = 2;
11020 break;
11021
11022 case 'g':
11023 if (arg == NULL)
11024 mips_debug = 2;
11025 else
11026 mips_debug = atoi (arg);
11027 break;
11028
11029 case OPTION_MIPS1:
11030 file_mips_isa = ISA_MIPS1;
11031 break;
11032
11033 case OPTION_MIPS2:
11034 file_mips_isa = ISA_MIPS2;
11035 break;
11036
11037 case OPTION_MIPS3:
11038 file_mips_isa = ISA_MIPS3;
11039 break;
11040
11041 case OPTION_MIPS4:
11042 file_mips_isa = ISA_MIPS4;
11043 break;
11044
11045 case OPTION_MIPS5:
11046 file_mips_isa = ISA_MIPS5;
11047 break;
11048
11049 case OPTION_MIPS32:
11050 file_mips_isa = ISA_MIPS32;
11051 break;
11052
11053 case OPTION_MIPS32R2:
11054 file_mips_isa = ISA_MIPS32R2;
11055 break;
11056
11057 case OPTION_MIPS64R2:
11058 file_mips_isa = ISA_MIPS64R2;
11059 break;
11060
11061 case OPTION_MIPS64:
11062 file_mips_isa = ISA_MIPS64;
11063 break;
11064
11065 case OPTION_MTUNE:
11066 mips_set_option_string (&mips_tune_string, arg);
11067 break;
11068
11069 case OPTION_MARCH:
11070 mips_set_option_string (&mips_arch_string, arg);
11071 break;
11072
11073 case OPTION_M4650:
11074 mips_set_option_string (&mips_arch_string, "4650");
11075 mips_set_option_string (&mips_tune_string, "4650");
11076 break;
11077
11078 case OPTION_NO_M4650:
11079 break;
11080
11081 case OPTION_M4010:
11082 mips_set_option_string (&mips_arch_string, "4010");
11083 mips_set_option_string (&mips_tune_string, "4010");
11084 break;
11085
11086 case OPTION_NO_M4010:
11087 break;
11088
11089 case OPTION_M4100:
11090 mips_set_option_string (&mips_arch_string, "4100");
11091 mips_set_option_string (&mips_tune_string, "4100");
11092 break;
11093
11094 case OPTION_NO_M4100:
11095 break;
11096
11097 case OPTION_M3900:
11098 mips_set_option_string (&mips_arch_string, "3900");
11099 mips_set_option_string (&mips_tune_string, "3900");
11100 break;
11101
11102 case OPTION_NO_M3900:
11103 break;
11104
11105 case OPTION_MDMX:
11106 mips_opts.ase_mdmx = 1;
11107 break;
11108
11109 case OPTION_NO_MDMX:
11110 mips_opts.ase_mdmx = 0;
11111 break;
11112
11113 case OPTION_DSP:
11114 mips_opts.ase_dsp = 1;
11115 mips_opts.ase_dspr2 = 0;
11116 break;
11117
11118 case OPTION_NO_DSP:
11119 mips_opts.ase_dsp = 0;
11120 mips_opts.ase_dspr2 = 0;
11121 break;
11122
11123 case OPTION_DSPR2:
11124 mips_opts.ase_dspr2 = 1;
11125 mips_opts.ase_dsp = 1;
11126 break;
11127
11128 case OPTION_NO_DSPR2:
11129 mips_opts.ase_dspr2 = 0;
11130 mips_opts.ase_dsp = 0;
11131 break;
11132
11133 case OPTION_MT:
11134 mips_opts.ase_mt = 1;
11135 break;
11136
11137 case OPTION_NO_MT:
11138 mips_opts.ase_mt = 0;
11139 break;
11140
11141 case OPTION_MIPS16:
11142 mips_opts.mips16 = 1;
11143 mips_no_prev_insn ();
11144 break;
11145
11146 case OPTION_NO_MIPS16:
11147 mips_opts.mips16 = 0;
11148 mips_no_prev_insn ();
11149 break;
11150
11151 case OPTION_MIPS3D:
11152 mips_opts.ase_mips3d = 1;
11153 break;
11154
11155 case OPTION_NO_MIPS3D:
11156 mips_opts.ase_mips3d = 0;
11157 break;
11158
11159 case OPTION_SMARTMIPS:
11160 mips_opts.ase_smartmips = 1;
11161 break;
11162
11163 case OPTION_NO_SMARTMIPS:
11164 mips_opts.ase_smartmips = 0;
11165 break;
11166
11167 case OPTION_FIX_VR4120:
11168 mips_fix_vr4120 = 1;
11169 break;
11170
11171 case OPTION_NO_FIX_VR4120:
11172 mips_fix_vr4120 = 0;
11173 break;
11174
11175 case OPTION_FIX_VR4130:
11176 mips_fix_vr4130 = 1;
11177 break;
11178
11179 case OPTION_NO_FIX_VR4130:
11180 mips_fix_vr4130 = 0;
11181 break;
11182
11183 case OPTION_RELAX_BRANCH:
11184 mips_relax_branch = 1;
11185 break;
11186
11187 case OPTION_NO_RELAX_BRANCH:
11188 mips_relax_branch = 0;
11189 break;
11190
11191 case OPTION_MSHARED:
11192 mips_in_shared = TRUE;
11193 break;
11194
11195 case OPTION_MNO_SHARED:
11196 mips_in_shared = FALSE;
11197 break;
11198
11199 case OPTION_MSYM32:
11200 mips_opts.sym32 = TRUE;
11201 break;
11202
11203 case OPTION_MNO_SYM32:
11204 mips_opts.sym32 = FALSE;
11205 break;
11206
11207 #ifdef OBJ_ELF
11208 /* When generating ELF code, we permit -KPIC and -call_shared to
11209 select SVR4_PIC, and -non_shared to select no PIC. This is
11210 intended to be compatible with Irix 5. */
11211 case OPTION_CALL_SHARED:
11212 if (!IS_ELF)
11213 {
11214 as_bad (_("-call_shared is supported only for ELF format"));
11215 return 0;
11216 }
11217 mips_pic = SVR4_PIC;
11218 mips_abicalls = TRUE;
11219 break;
11220
11221 case OPTION_NON_SHARED:
11222 if (!IS_ELF)
11223 {
11224 as_bad (_("-non_shared is supported only for ELF format"));
11225 return 0;
11226 }
11227 mips_pic = NO_PIC;
11228 mips_abicalls = FALSE;
11229 break;
11230
11231 /* The -xgot option tells the assembler to use 32 bit offsets
11232 when accessing the got in SVR4_PIC mode. It is for Irix
11233 compatibility. */
11234 case OPTION_XGOT:
11235 mips_big_got = 1;
11236 break;
11237 #endif /* OBJ_ELF */
11238
11239 case 'G':
11240 g_switch_value = atoi (arg);
11241 g_switch_seen = 1;
11242 break;
11243
11244 #ifdef OBJ_ELF
11245 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11246 and -mabi=64. */
11247 case OPTION_32:
11248 if (!IS_ELF)
11249 {
11250 as_bad (_("-32 is supported for ELF format only"));
11251 return 0;
11252 }
11253 mips_abi = O32_ABI;
11254 break;
11255
11256 case OPTION_N32:
11257 if (!IS_ELF)
11258 {
11259 as_bad (_("-n32 is supported for ELF format only"));
11260 return 0;
11261 }
11262 mips_abi = N32_ABI;
11263 break;
11264
11265 case OPTION_64:
11266 if (!IS_ELF)
11267 {
11268 as_bad (_("-64 is supported for ELF format only"));
11269 return 0;
11270 }
11271 mips_abi = N64_ABI;
11272 if (!support_64bit_objects())
11273 as_fatal (_("No compiled in support for 64 bit object file format"));
11274 break;
11275 #endif /* OBJ_ELF */
11276
11277 case OPTION_GP32:
11278 file_mips_gp32 = 1;
11279 break;
11280
11281 case OPTION_GP64:
11282 file_mips_gp32 = 0;
11283 break;
11284
11285 case OPTION_FP32:
11286 file_mips_fp32 = 1;
11287 break;
11288
11289 case OPTION_FP64:
11290 file_mips_fp32 = 0;
11291 break;
11292
11293 #ifdef OBJ_ELF
11294 case OPTION_MABI:
11295 if (!IS_ELF)
11296 {
11297 as_bad (_("-mabi is supported for ELF format only"));
11298 return 0;
11299 }
11300 if (strcmp (arg, "32") == 0)
11301 mips_abi = O32_ABI;
11302 else if (strcmp (arg, "o64") == 0)
11303 mips_abi = O64_ABI;
11304 else if (strcmp (arg, "n32") == 0)
11305 mips_abi = N32_ABI;
11306 else if (strcmp (arg, "64") == 0)
11307 {
11308 mips_abi = N64_ABI;
11309 if (! support_64bit_objects())
11310 as_fatal (_("No compiled in support for 64 bit object file "
11311 "format"));
11312 }
11313 else if (strcmp (arg, "eabi") == 0)
11314 mips_abi = EABI_ABI;
11315 else
11316 {
11317 as_fatal (_("invalid abi -mabi=%s"), arg);
11318 return 0;
11319 }
11320 break;
11321 #endif /* OBJ_ELF */
11322
11323 case OPTION_M7000_HILO_FIX:
11324 mips_7000_hilo_fix = TRUE;
11325 break;
11326
11327 case OPTION_MNO_7000_HILO_FIX:
11328 mips_7000_hilo_fix = FALSE;
11329 break;
11330
11331 #ifdef OBJ_ELF
11332 case OPTION_MDEBUG:
11333 mips_flag_mdebug = TRUE;
11334 break;
11335
11336 case OPTION_NO_MDEBUG:
11337 mips_flag_mdebug = FALSE;
11338 break;
11339
11340 case OPTION_PDR:
11341 mips_flag_pdr = TRUE;
11342 break;
11343
11344 case OPTION_NO_PDR:
11345 mips_flag_pdr = FALSE;
11346 break;
11347
11348 case OPTION_MVXWORKS_PIC:
11349 mips_pic = VXWORKS_PIC;
11350 break;
11351 #endif /* OBJ_ELF */
11352
11353 default:
11354 return 0;
11355 }
11356
11357 return 1;
11358 }
11359 \f
11360 /* Set up globals to generate code for the ISA or processor
11361 described by INFO. */
11362
11363 static void
11364 mips_set_architecture (const struct mips_cpu_info *info)
11365 {
11366 if (info != 0)
11367 {
11368 file_mips_arch = info->cpu;
11369 mips_opts.arch = info->cpu;
11370 mips_opts.isa = info->isa;
11371 }
11372 }
11373
11374
11375 /* Likewise for tuning. */
11376
11377 static void
11378 mips_set_tune (const struct mips_cpu_info *info)
11379 {
11380 if (info != 0)
11381 mips_tune = info->cpu;
11382 }
11383
11384
11385 void
11386 mips_after_parse_args (void)
11387 {
11388 const struct mips_cpu_info *arch_info = 0;
11389 const struct mips_cpu_info *tune_info = 0;
11390
11391 /* GP relative stuff not working for PE */
11392 if (strncmp (TARGET_OS, "pe", 2) == 0)
11393 {
11394 if (g_switch_seen && g_switch_value != 0)
11395 as_bad (_("-G not supported in this configuration."));
11396 g_switch_value = 0;
11397 }
11398
11399 if (mips_abi == NO_ABI)
11400 mips_abi = MIPS_DEFAULT_ABI;
11401
11402 /* The following code determines the architecture and register size.
11403 Similar code was added to GCC 3.3 (see override_options() in
11404 config/mips/mips.c). The GAS and GCC code should be kept in sync
11405 as much as possible. */
11406
11407 if (mips_arch_string != 0)
11408 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11409
11410 if (file_mips_isa != ISA_UNKNOWN)
11411 {
11412 /* Handle -mipsN. At this point, file_mips_isa contains the
11413 ISA level specified by -mipsN, while arch_info->isa contains
11414 the -march selection (if any). */
11415 if (arch_info != 0)
11416 {
11417 /* -march takes precedence over -mipsN, since it is more descriptive.
11418 There's no harm in specifying both as long as the ISA levels
11419 are the same. */
11420 if (file_mips_isa != arch_info->isa)
11421 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11422 mips_cpu_info_from_isa (file_mips_isa)->name,
11423 mips_cpu_info_from_isa (arch_info->isa)->name);
11424 }
11425 else
11426 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11427 }
11428
11429 if (arch_info == 0)
11430 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11431
11432 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11433 as_bad ("-march=%s is not compatible with the selected ABI",
11434 arch_info->name);
11435
11436 mips_set_architecture (arch_info);
11437
11438 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11439 if (mips_tune_string != 0)
11440 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11441
11442 if (tune_info == 0)
11443 mips_set_tune (arch_info);
11444 else
11445 mips_set_tune (tune_info);
11446
11447 if (file_mips_gp32 >= 0)
11448 {
11449 /* The user specified the size of the integer registers. Make sure
11450 it agrees with the ABI and ISA. */
11451 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11452 as_bad (_("-mgp64 used with a 32-bit processor"));
11453 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11454 as_bad (_("-mgp32 used with a 64-bit ABI"));
11455 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11456 as_bad (_("-mgp64 used with a 32-bit ABI"));
11457 }
11458 else
11459 {
11460 /* Infer the integer register size from the ABI and processor.
11461 Restrict ourselves to 32-bit registers if that's all the
11462 processor has, or if the ABI cannot handle 64-bit registers. */
11463 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11464 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11465 }
11466
11467 switch (file_mips_fp32)
11468 {
11469 default:
11470 case -1:
11471 /* No user specified float register size.
11472 ??? GAS treats single-float processors as though they had 64-bit
11473 float registers (although it complains when double-precision
11474 instructions are used). As things stand, saying they have 32-bit
11475 registers would lead to spurious "register must be even" messages.
11476 So here we assume float registers are never smaller than the
11477 integer ones. */
11478 if (file_mips_gp32 == 0)
11479 /* 64-bit integer registers implies 64-bit float registers. */
11480 file_mips_fp32 = 0;
11481 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11482 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11483 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11484 file_mips_fp32 = 0;
11485 else
11486 /* 32-bit float registers. */
11487 file_mips_fp32 = 1;
11488 break;
11489
11490 /* The user specified the size of the float registers. Check if it
11491 agrees with the ABI and ISA. */
11492 case 0:
11493 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11494 as_bad (_("-mfp64 used with a 32-bit fpu"));
11495 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11496 && !ISA_HAS_MXHC1 (mips_opts.isa))
11497 as_warn (_("-mfp64 used with a 32-bit ABI"));
11498 break;
11499 case 1:
11500 if (ABI_NEEDS_64BIT_REGS (mips_abi))
11501 as_warn (_("-mfp32 used with a 64-bit ABI"));
11502 break;
11503 }
11504
11505 /* End of GCC-shared inference code. */
11506
11507 /* This flag is set when we have a 64-bit capable CPU but use only
11508 32-bit wide registers. Note that EABI does not use it. */
11509 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11510 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11511 || mips_abi == O32_ABI))
11512 mips_32bitmode = 1;
11513
11514 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11515 as_bad (_("trap exception not supported at ISA 1"));
11516
11517 /* If the selected architecture includes support for ASEs, enable
11518 generation of code for them. */
11519 if (mips_opts.mips16 == -1)
11520 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11521 if (mips_opts.ase_mips3d == -1)
11522 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
11523 && file_mips_fp32 == 0) ? 1 : 0;
11524 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
11525 as_bad (_("-mfp32 used with -mips3d"));
11526
11527 if (mips_opts.ase_mdmx == -1)
11528 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
11529 && file_mips_fp32 == 0) ? 1 : 0;
11530 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
11531 as_bad (_("-mfp32 used with -mdmx"));
11532
11533 if (mips_opts.ase_smartmips == -1)
11534 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
11535 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
11536 as_warn ("%s ISA does not support SmartMIPS",
11537 mips_cpu_info_from_isa (mips_opts.isa)->name);
11538
11539 if (mips_opts.ase_dsp == -1)
11540 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11541 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
11542 as_warn ("%s ISA does not support DSP ASE",
11543 mips_cpu_info_from_isa (mips_opts.isa)->name);
11544
11545 if (mips_opts.ase_dspr2 == -1)
11546 {
11547 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
11548 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11549 }
11550 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
11551 as_warn ("%s ISA does not support DSP R2 ASE",
11552 mips_cpu_info_from_isa (mips_opts.isa)->name);
11553
11554 if (mips_opts.ase_mt == -1)
11555 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
11556 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
11557 as_warn ("%s ISA does not support MT ASE",
11558 mips_cpu_info_from_isa (mips_opts.isa)->name);
11559
11560 file_mips_isa = mips_opts.isa;
11561 file_ase_mips16 = mips_opts.mips16;
11562 file_ase_mips3d = mips_opts.ase_mips3d;
11563 file_ase_mdmx = mips_opts.ase_mdmx;
11564 file_ase_smartmips = mips_opts.ase_smartmips;
11565 file_ase_dsp = mips_opts.ase_dsp;
11566 file_ase_dspr2 = mips_opts.ase_dspr2;
11567 file_ase_mt = mips_opts.ase_mt;
11568 mips_opts.gp32 = file_mips_gp32;
11569 mips_opts.fp32 = file_mips_fp32;
11570
11571 if (mips_flag_mdebug < 0)
11572 {
11573 #ifdef OBJ_MAYBE_ECOFF
11574 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11575 mips_flag_mdebug = 1;
11576 else
11577 #endif /* OBJ_MAYBE_ECOFF */
11578 mips_flag_mdebug = 0;
11579 }
11580 }
11581 \f
11582 void
11583 mips_init_after_args (void)
11584 {
11585 /* initialize opcodes */
11586 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
11587 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
11588 }
11589
11590 long
11591 md_pcrel_from (fixS *fixP)
11592 {
11593 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11594 switch (fixP->fx_r_type)
11595 {
11596 case BFD_RELOC_16_PCREL_S2:
11597 case BFD_RELOC_MIPS_JMP:
11598 /* Return the address of the delay slot. */
11599 return addr + 4;
11600 default:
11601 /* We have no relocation type for PC relative MIPS16 instructions. */
11602 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
11603 as_bad_where (fixP->fx_file, fixP->fx_line,
11604 _("PC relative MIPS16 instruction references a different section"));
11605 return addr;
11606 }
11607 }
11608
11609 /* This is called before the symbol table is processed. In order to
11610 work with gcc when using mips-tfile, we must keep all local labels.
11611 However, in other cases, we want to discard them. If we were
11612 called with -g, but we didn't see any debugging information, it may
11613 mean that gcc is smuggling debugging information through to
11614 mips-tfile, in which case we must generate all local labels. */
11615
11616 void
11617 mips_frob_file_before_adjust (void)
11618 {
11619 #ifndef NO_ECOFF_DEBUGGING
11620 if (ECOFF_DEBUGGING
11621 && mips_debug != 0
11622 && ! ecoff_debugging_seen)
11623 flag_keep_locals = 1;
11624 #endif
11625 }
11626
11627 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11628 the corresponding LO16 reloc. This is called before md_apply_fix and
11629 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11630 relocation operators.
11631
11632 For our purposes, a %lo() expression matches a %got() or %hi()
11633 expression if:
11634
11635 (a) it refers to the same symbol; and
11636 (b) the offset applied in the %lo() expression is no lower than
11637 the offset applied in the %got() or %hi().
11638
11639 (b) allows us to cope with code like:
11640
11641 lui $4,%hi(foo)
11642 lh $4,%lo(foo+2)($4)
11643
11644 ...which is legal on RELA targets, and has a well-defined behaviour
11645 if the user knows that adding 2 to "foo" will not induce a carry to
11646 the high 16 bits.
11647
11648 When several %lo()s match a particular %got() or %hi(), we use the
11649 following rules to distinguish them:
11650
11651 (1) %lo()s with smaller offsets are a better match than %lo()s with
11652 higher offsets.
11653
11654 (2) %lo()s with no matching %got() or %hi() are better than those
11655 that already have a matching %got() or %hi().
11656
11657 (3) later %lo()s are better than earlier %lo()s.
11658
11659 These rules are applied in order.
11660
11661 (1) means, among other things, that %lo()s with identical offsets are
11662 chosen if they exist.
11663
11664 (2) means that we won't associate several high-part relocations with
11665 the same low-part relocation unless there's no alternative. Having
11666 several high parts for the same low part is a GNU extension; this rule
11667 allows careful users to avoid it.
11668
11669 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11670 with the last high-part relocation being at the front of the list.
11671 It therefore makes sense to choose the last matching low-part
11672 relocation, all other things being equal. It's also easier
11673 to code that way. */
11674
11675 void
11676 mips_frob_file (void)
11677 {
11678 struct mips_hi_fixup *l;
11679
11680 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11681 {
11682 segment_info_type *seginfo;
11683 bfd_boolean matched_lo_p;
11684 fixS **hi_pos, **lo_pos, **pos;
11685
11686 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11687
11688 /* If a GOT16 relocation turns out to be against a global symbol,
11689 there isn't supposed to be a matching LO. */
11690 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11691 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11692 continue;
11693
11694 /* Check quickly whether the next fixup happens to be a matching %lo. */
11695 if (fixup_has_matching_lo_p (l->fixp))
11696 continue;
11697
11698 seginfo = seg_info (l->seg);
11699
11700 /* Set HI_POS to the position of this relocation in the chain.
11701 Set LO_POS to the position of the chosen low-part relocation.
11702 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11703 relocation that matches an immediately-preceding high-part
11704 relocation. */
11705 hi_pos = NULL;
11706 lo_pos = NULL;
11707 matched_lo_p = FALSE;
11708 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
11709 {
11710 if (*pos == l->fixp)
11711 hi_pos = pos;
11712
11713 if (((*pos)->fx_r_type == BFD_RELOC_LO16
11714 || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16)
11715 && (*pos)->fx_addsy == l->fixp->fx_addsy
11716 && (*pos)->fx_offset >= l->fixp->fx_offset
11717 && (lo_pos == NULL
11718 || (*pos)->fx_offset < (*lo_pos)->fx_offset
11719 || (!matched_lo_p
11720 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
11721 lo_pos = pos;
11722
11723 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
11724 && fixup_has_matching_lo_p (*pos));
11725 }
11726
11727 /* If we found a match, remove the high-part relocation from its
11728 current position and insert it before the low-part relocation.
11729 Make the offsets match so that fixup_has_matching_lo_p()
11730 will return true.
11731
11732 We don't warn about unmatched high-part relocations since some
11733 versions of gcc have been known to emit dead "lui ...%hi(...)"
11734 instructions. */
11735 if (lo_pos != NULL)
11736 {
11737 l->fixp->fx_offset = (*lo_pos)->fx_offset;
11738 if (l->fixp->fx_next != *lo_pos)
11739 {
11740 *hi_pos = l->fixp->fx_next;
11741 l->fixp->fx_next = *lo_pos;
11742 *lo_pos = l->fixp;
11743 }
11744 }
11745 }
11746 }
11747
11748 /* We may have combined relocations without symbols in the N32/N64 ABI.
11749 We have to prevent gas from dropping them. */
11750
11751 int
11752 mips_force_relocation (fixS *fixp)
11753 {
11754 if (generic_force_reloc (fixp))
11755 return 1;
11756
11757 if (HAVE_NEWABI
11758 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11759 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11760 || fixp->fx_r_type == BFD_RELOC_HI16_S
11761 || fixp->fx_r_type == BFD_RELOC_LO16))
11762 return 1;
11763
11764 return 0;
11765 }
11766
11767 /* Apply a fixup to the object file. */
11768
11769 void
11770 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11771 {
11772 bfd_byte *buf;
11773 long insn;
11774 reloc_howto_type *howto;
11775
11776 /* We ignore generic BFD relocations we don't know about. */
11777 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11778 if (! howto)
11779 return;
11780
11781 assert (fixP->fx_size == 4
11782 || fixP->fx_r_type == BFD_RELOC_16
11783 || fixP->fx_r_type == BFD_RELOC_64
11784 || fixP->fx_r_type == BFD_RELOC_CTOR
11785 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11786 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11787 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
11788 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
11789
11790 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11791
11792 assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
11793
11794 /* Don't treat parts of a composite relocation as done. There are two
11795 reasons for this:
11796
11797 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11798 should nevertheless be emitted if the first part is.
11799
11800 (2) In normal usage, composite relocations are never assembly-time
11801 constants. The easiest way of dealing with the pathological
11802 exceptions is to generate a relocation against STN_UNDEF and
11803 leave everything up to the linker. */
11804 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
11805 fixP->fx_done = 1;
11806
11807 switch (fixP->fx_r_type)
11808 {
11809 case BFD_RELOC_MIPS_TLS_GD:
11810 case BFD_RELOC_MIPS_TLS_LDM:
11811 case BFD_RELOC_MIPS_TLS_DTPREL32:
11812 case BFD_RELOC_MIPS_TLS_DTPREL64:
11813 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
11814 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
11815 case BFD_RELOC_MIPS_TLS_GOTTPREL:
11816 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
11817 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
11818 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11819 /* fall through */
11820
11821 case BFD_RELOC_MIPS_JMP:
11822 case BFD_RELOC_MIPS_SHIFT5:
11823 case BFD_RELOC_MIPS_SHIFT6:
11824 case BFD_RELOC_MIPS_GOT_DISP:
11825 case BFD_RELOC_MIPS_GOT_PAGE:
11826 case BFD_RELOC_MIPS_GOT_OFST:
11827 case BFD_RELOC_MIPS_SUB:
11828 case BFD_RELOC_MIPS_INSERT_A:
11829 case BFD_RELOC_MIPS_INSERT_B:
11830 case BFD_RELOC_MIPS_DELETE:
11831 case BFD_RELOC_MIPS_HIGHEST:
11832 case BFD_RELOC_MIPS_HIGHER:
11833 case BFD_RELOC_MIPS_SCN_DISP:
11834 case BFD_RELOC_MIPS_REL16:
11835 case BFD_RELOC_MIPS_RELGOT:
11836 case BFD_RELOC_MIPS_JALR:
11837 case BFD_RELOC_HI16:
11838 case BFD_RELOC_HI16_S:
11839 case BFD_RELOC_GPREL16:
11840 case BFD_RELOC_MIPS_LITERAL:
11841 case BFD_RELOC_MIPS_CALL16:
11842 case BFD_RELOC_MIPS_GOT16:
11843 case BFD_RELOC_GPREL32:
11844 case BFD_RELOC_MIPS_GOT_HI16:
11845 case BFD_RELOC_MIPS_GOT_LO16:
11846 case BFD_RELOC_MIPS_CALL_HI16:
11847 case BFD_RELOC_MIPS_CALL_LO16:
11848 case BFD_RELOC_MIPS16_GPREL:
11849 case BFD_RELOC_MIPS16_HI16:
11850 case BFD_RELOC_MIPS16_HI16_S:
11851 case BFD_RELOC_MIPS16_JMP:
11852 /* Nothing needed to do. The value comes from the reloc entry. */
11853 break;
11854
11855 case BFD_RELOC_64:
11856 /* This is handled like BFD_RELOC_32, but we output a sign
11857 extended value if we are only 32 bits. */
11858 if (fixP->fx_done)
11859 {
11860 if (8 <= sizeof (valueT))
11861 md_number_to_chars ((char *) buf, *valP, 8);
11862 else
11863 {
11864 valueT hiv;
11865
11866 if ((*valP & 0x80000000) != 0)
11867 hiv = 0xffffffff;
11868 else
11869 hiv = 0;
11870 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
11871 *valP, 4);
11872 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
11873 hiv, 4);
11874 }
11875 }
11876 break;
11877
11878 case BFD_RELOC_RVA:
11879 case BFD_RELOC_32:
11880 case BFD_RELOC_16:
11881 /* If we are deleting this reloc entry, we must fill in the
11882 value now. This can happen if we have a .word which is not
11883 resolved when it appears but is later defined. */
11884 if (fixP->fx_done)
11885 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
11886 break;
11887
11888 case BFD_RELOC_LO16:
11889 case BFD_RELOC_MIPS16_LO16:
11890 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11891 may be safe to remove, but if so it's not obvious. */
11892 /* When handling an embedded PIC switch statement, we can wind
11893 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11894 if (fixP->fx_done)
11895 {
11896 if (*valP + 0x8000 > 0xffff)
11897 as_bad_where (fixP->fx_file, fixP->fx_line,
11898 _("relocation overflow"));
11899 if (target_big_endian)
11900 buf += 2;
11901 md_number_to_chars ((char *) buf, *valP, 2);
11902 }
11903 break;
11904
11905 case BFD_RELOC_16_PCREL_S2:
11906 if ((*valP & 0x3) != 0)
11907 as_bad_where (fixP->fx_file, fixP->fx_line,
11908 _("Branch to misaligned address (%lx)"), (long) *valP);
11909
11910 /* We need to save the bits in the instruction since fixup_segment()
11911 might be deleting the relocation entry (i.e., a branch within
11912 the current segment). */
11913 if (! fixP->fx_done)
11914 break;
11915
11916 /* Update old instruction data. */
11917 if (target_big_endian)
11918 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11919 else
11920 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11921
11922 if (*valP + 0x20000 <= 0x3ffff)
11923 {
11924 insn |= (*valP >> 2) & 0xffff;
11925 md_number_to_chars ((char *) buf, insn, 4);
11926 }
11927 else if (mips_pic == NO_PIC
11928 && fixP->fx_done
11929 && fixP->fx_frag->fr_address >= text_section->vma
11930 && (fixP->fx_frag->fr_address
11931 < text_section->vma + bfd_get_section_size (text_section))
11932 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11933 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11934 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11935 {
11936 /* The branch offset is too large. If this is an
11937 unconditional branch, and we are not generating PIC code,
11938 we can convert it to an absolute jump instruction. */
11939 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11940 insn = 0x0c000000; /* jal */
11941 else
11942 insn = 0x08000000; /* j */
11943 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11944 fixP->fx_done = 0;
11945 fixP->fx_addsy = section_symbol (text_section);
11946 *valP += md_pcrel_from (fixP);
11947 md_number_to_chars ((char *) buf, insn, 4);
11948 }
11949 else
11950 {
11951 /* If we got here, we have branch-relaxation disabled,
11952 and there's nothing we can do to fix this instruction
11953 without turning it into a longer sequence. */
11954 as_bad_where (fixP->fx_file, fixP->fx_line,
11955 _("Branch out of range"));
11956 }
11957 break;
11958
11959 case BFD_RELOC_VTABLE_INHERIT:
11960 fixP->fx_done = 0;
11961 if (fixP->fx_addsy
11962 && !S_IS_DEFINED (fixP->fx_addsy)
11963 && !S_IS_WEAK (fixP->fx_addsy))
11964 S_SET_WEAK (fixP->fx_addsy);
11965 break;
11966
11967 case BFD_RELOC_VTABLE_ENTRY:
11968 fixP->fx_done = 0;
11969 break;
11970
11971 default:
11972 internalError ();
11973 }
11974
11975 /* Remember value for tc_gen_reloc. */
11976 fixP->fx_addnumber = *valP;
11977 }
11978
11979 static symbolS *
11980 get_symbol (void)
11981 {
11982 int c;
11983 char *name;
11984 symbolS *p;
11985
11986 name = input_line_pointer;
11987 c = get_symbol_end ();
11988 p = (symbolS *) symbol_find_or_make (name);
11989 *input_line_pointer = c;
11990 return p;
11991 }
11992
11993 /* Align the current frag to a given power of two. The MIPS assembler
11994 also automatically adjusts any preceding label. */
11995
11996 static void
11997 mips_align (int to, int fill, symbolS *label)
11998 {
11999 mips_emit_delays ();
12000 frag_align (to, fill, 0);
12001 record_alignment (now_seg, to);
12002 if (label != NULL)
12003 {
12004 assert (S_GET_SEGMENT (label) == now_seg);
12005 symbol_set_frag (label, frag_now);
12006 S_SET_VALUE (label, (valueT) frag_now_fix ());
12007 }
12008 }
12009
12010 /* Align to a given power of two. .align 0 turns off the automatic
12011 alignment used by the data creating pseudo-ops. */
12012
12013 static void
12014 s_align (int x ATTRIBUTE_UNUSED)
12015 {
12016 int temp;
12017 long temp_fill;
12018 long max_alignment = 28;
12019
12020 /* o Note that the assembler pulls down any immediately preceding label
12021 to the aligned address.
12022 o It's not documented but auto alignment is reinstated by
12023 a .align pseudo instruction.
12024 o Note also that after auto alignment is turned off the mips assembler
12025 issues an error on attempt to assemble an improperly aligned data item.
12026 We don't. */
12027
12028 temp = get_absolute_expression ();
12029 if (temp > max_alignment)
12030 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12031 else if (temp < 0)
12032 {
12033 as_warn (_("Alignment negative: 0 assumed."));
12034 temp = 0;
12035 }
12036 if (*input_line_pointer == ',')
12037 {
12038 ++input_line_pointer;
12039 temp_fill = get_absolute_expression ();
12040 }
12041 else
12042 temp_fill = 0;
12043 if (temp)
12044 {
12045 segment_info_type *si = seg_info (now_seg);
12046 struct insn_label_list *l = si->label_list;
12047 /* Auto alignment should be switched on by next section change. */
12048 auto_align = 1;
12049 mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL);
12050 }
12051 else
12052 {
12053 auto_align = 0;
12054 }
12055
12056 demand_empty_rest_of_line ();
12057 }
12058
12059 static void
12060 s_change_sec (int sec)
12061 {
12062 segT seg;
12063
12064 #ifdef OBJ_ELF
12065 /* The ELF backend needs to know that we are changing sections, so
12066 that .previous works correctly. We could do something like check
12067 for an obj_section_change_hook macro, but that might be confusing
12068 as it would not be appropriate to use it in the section changing
12069 functions in read.c, since obj-elf.c intercepts those. FIXME:
12070 This should be cleaner, somehow. */
12071 if (IS_ELF)
12072 obj_elf_section_change_hook ();
12073 #endif
12074
12075 mips_emit_delays ();
12076 switch (sec)
12077 {
12078 case 't':
12079 s_text (0);
12080 break;
12081 case 'd':
12082 s_data (0);
12083 break;
12084 case 'b':
12085 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12086 demand_empty_rest_of_line ();
12087 break;
12088
12089 case 'r':
12090 seg = subseg_new (RDATA_SECTION_NAME,
12091 (subsegT) get_absolute_expression ());
12092 if (IS_ELF)
12093 {
12094 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12095 | SEC_READONLY | SEC_RELOC
12096 | SEC_DATA));
12097 if (strcmp (TARGET_OS, "elf") != 0)
12098 record_alignment (seg, 4);
12099 }
12100 demand_empty_rest_of_line ();
12101 break;
12102
12103 case 's':
12104 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12105 if (IS_ELF)
12106 {
12107 bfd_set_section_flags (stdoutput, seg,
12108 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12109 if (strcmp (TARGET_OS, "elf") != 0)
12110 record_alignment (seg, 4);
12111 }
12112 demand_empty_rest_of_line ();
12113 break;
12114 }
12115
12116 auto_align = 1;
12117 }
12118
12119 void
12120 s_change_section (int ignore ATTRIBUTE_UNUSED)
12121 {
12122 #ifdef OBJ_ELF
12123 char *section_name;
12124 char c;
12125 char next_c = 0;
12126 int section_type;
12127 int section_flag;
12128 int section_entry_size;
12129 int section_alignment;
12130
12131 if (!IS_ELF)
12132 return;
12133
12134 section_name = input_line_pointer;
12135 c = get_symbol_end ();
12136 if (c)
12137 next_c = *(input_line_pointer + 1);
12138
12139 /* Do we have .section Name<,"flags">? */
12140 if (c != ',' || (c == ',' && next_c == '"'))
12141 {
12142 /* just after name is now '\0'. */
12143 *input_line_pointer = c;
12144 input_line_pointer = section_name;
12145 obj_elf_section (ignore);
12146 return;
12147 }
12148 input_line_pointer++;
12149
12150 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12151 if (c == ',')
12152 section_type = get_absolute_expression ();
12153 else
12154 section_type = 0;
12155 if (*input_line_pointer++ == ',')
12156 section_flag = get_absolute_expression ();
12157 else
12158 section_flag = 0;
12159 if (*input_line_pointer++ == ',')
12160 section_entry_size = get_absolute_expression ();
12161 else
12162 section_entry_size = 0;
12163 if (*input_line_pointer++ == ',')
12164 section_alignment = get_absolute_expression ();
12165 else
12166 section_alignment = 0;
12167
12168 section_name = xstrdup (section_name);
12169
12170 /* When using the generic form of .section (as implemented by obj-elf.c),
12171 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12172 traditionally had to fall back on the more common @progbits instead.
12173
12174 There's nothing really harmful in this, since bfd will correct
12175 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12176 means that, for backwards compatibility, the special_section entries
12177 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12178
12179 Even so, we shouldn't force users of the MIPS .section syntax to
12180 incorrectly label the sections as SHT_PROGBITS. The best compromise
12181 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12182 generic type-checking code. */
12183 if (section_type == SHT_MIPS_DWARF)
12184 section_type = SHT_PROGBITS;
12185
12186 obj_elf_change_section (section_name, section_type, section_flag,
12187 section_entry_size, 0, 0, 0);
12188
12189 if (now_seg->name != section_name)
12190 free (section_name);
12191 #endif /* OBJ_ELF */
12192 }
12193
12194 void
12195 mips_enable_auto_align (void)
12196 {
12197 auto_align = 1;
12198 }
12199
12200 static void
12201 s_cons (int log_size)
12202 {
12203 segment_info_type *si = seg_info (now_seg);
12204 struct insn_label_list *l = si->label_list;
12205 symbolS *label;
12206
12207 label = l != NULL ? l->label : NULL;
12208 mips_emit_delays ();
12209 if (log_size > 0 && auto_align)
12210 mips_align (log_size, 0, label);
12211 mips_clear_insn_labels ();
12212 cons (1 << log_size);
12213 }
12214
12215 static void
12216 s_float_cons (int type)
12217 {
12218 segment_info_type *si = seg_info (now_seg);
12219 struct insn_label_list *l = si->label_list;
12220 symbolS *label;
12221
12222 label = l != NULL ? l->label : NULL;
12223
12224 mips_emit_delays ();
12225
12226 if (auto_align)
12227 {
12228 if (type == 'd')
12229 mips_align (3, 0, label);
12230 else
12231 mips_align (2, 0, label);
12232 }
12233
12234 mips_clear_insn_labels ();
12235
12236 float_cons (type);
12237 }
12238
12239 /* Handle .globl. We need to override it because on Irix 5 you are
12240 permitted to say
12241 .globl foo .text
12242 where foo is an undefined symbol, to mean that foo should be
12243 considered to be the address of a function. */
12244
12245 static void
12246 s_mips_globl (int x ATTRIBUTE_UNUSED)
12247 {
12248 char *name;
12249 int c;
12250 symbolS *symbolP;
12251 flagword flag;
12252
12253 do
12254 {
12255 name = input_line_pointer;
12256 c = get_symbol_end ();
12257 symbolP = symbol_find_or_make (name);
12258 S_SET_EXTERNAL (symbolP);
12259
12260 *input_line_pointer = c;
12261 SKIP_WHITESPACE ();
12262
12263 /* On Irix 5, every global symbol that is not explicitly labelled as
12264 being a function is apparently labelled as being an object. */
12265 flag = BSF_OBJECT;
12266
12267 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12268 && (*input_line_pointer != ','))
12269 {
12270 char *secname;
12271 asection *sec;
12272
12273 secname = input_line_pointer;
12274 c = get_symbol_end ();
12275 sec = bfd_get_section_by_name (stdoutput, secname);
12276 if (sec == NULL)
12277 as_bad (_("%s: no such section"), secname);
12278 *input_line_pointer = c;
12279
12280 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12281 flag = BSF_FUNCTION;
12282 }
12283
12284 symbol_get_bfdsym (symbolP)->flags |= flag;
12285
12286 c = *input_line_pointer;
12287 if (c == ',')
12288 {
12289 input_line_pointer++;
12290 SKIP_WHITESPACE ();
12291 if (is_end_of_line[(unsigned char) *input_line_pointer])
12292 c = '\n';
12293 }
12294 }
12295 while (c == ',');
12296
12297 demand_empty_rest_of_line ();
12298 }
12299
12300 static void
12301 s_option (int x ATTRIBUTE_UNUSED)
12302 {
12303 char *opt;
12304 char c;
12305
12306 opt = input_line_pointer;
12307 c = get_symbol_end ();
12308
12309 if (*opt == 'O')
12310 {
12311 /* FIXME: What does this mean? */
12312 }
12313 else if (strncmp (opt, "pic", 3) == 0)
12314 {
12315 int i;
12316
12317 i = atoi (opt + 3);
12318 if (i == 0)
12319 mips_pic = NO_PIC;
12320 else if (i == 2)
12321 {
12322 mips_pic = SVR4_PIC;
12323 mips_abicalls = TRUE;
12324 }
12325 else
12326 as_bad (_(".option pic%d not supported"), i);
12327
12328 if (mips_pic == SVR4_PIC)
12329 {
12330 if (g_switch_seen && g_switch_value != 0)
12331 as_warn (_("-G may not be used with SVR4 PIC code"));
12332 g_switch_value = 0;
12333 bfd_set_gp_size (stdoutput, 0);
12334 }
12335 }
12336 else
12337 as_warn (_("Unrecognized option \"%s\""), opt);
12338
12339 *input_line_pointer = c;
12340 demand_empty_rest_of_line ();
12341 }
12342
12343 /* This structure is used to hold a stack of .set values. */
12344
12345 struct mips_option_stack
12346 {
12347 struct mips_option_stack *next;
12348 struct mips_set_options options;
12349 };
12350
12351 static struct mips_option_stack *mips_opts_stack;
12352
12353 /* Handle the .set pseudo-op. */
12354
12355 static void
12356 s_mipsset (int x ATTRIBUTE_UNUSED)
12357 {
12358 char *name = input_line_pointer, ch;
12359
12360 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12361 ++input_line_pointer;
12362 ch = *input_line_pointer;
12363 *input_line_pointer = '\0';
12364
12365 if (strcmp (name, "reorder") == 0)
12366 {
12367 if (mips_opts.noreorder)
12368 end_noreorder ();
12369 }
12370 else if (strcmp (name, "noreorder") == 0)
12371 {
12372 if (!mips_opts.noreorder)
12373 start_noreorder ();
12374 }
12375 else if (strncmp (name, "at=", 3) == 0)
12376 {
12377 char *s = name + 3;
12378
12379 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12380 as_bad (_("Unrecognized register name `%s'"), s);
12381 }
12382 else if (strcmp (name, "at") == 0)
12383 {
12384 mips_opts.at = ATREG;
12385 }
12386 else if (strcmp (name, "noat") == 0)
12387 {
12388 mips_opts.at = ZERO;
12389 }
12390 else if (strcmp (name, "macro") == 0)
12391 {
12392 mips_opts.warn_about_macros = 0;
12393 }
12394 else if (strcmp (name, "nomacro") == 0)
12395 {
12396 if (mips_opts.noreorder == 0)
12397 as_bad (_("`noreorder' must be set before `nomacro'"));
12398 mips_opts.warn_about_macros = 1;
12399 }
12400 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12401 {
12402 mips_opts.nomove = 0;
12403 }
12404 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12405 {
12406 mips_opts.nomove = 1;
12407 }
12408 else if (strcmp (name, "bopt") == 0)
12409 {
12410 mips_opts.nobopt = 0;
12411 }
12412 else if (strcmp (name, "nobopt") == 0)
12413 {
12414 mips_opts.nobopt = 1;
12415 }
12416 else if (strcmp (name, "gp=default") == 0)
12417 mips_opts.gp32 = file_mips_gp32;
12418 else if (strcmp (name, "gp=32") == 0)
12419 mips_opts.gp32 = 1;
12420 else if (strcmp (name, "gp=64") == 0)
12421 {
12422 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12423 as_warn ("%s isa does not support 64-bit registers",
12424 mips_cpu_info_from_isa (mips_opts.isa)->name);
12425 mips_opts.gp32 = 0;
12426 }
12427 else if (strcmp (name, "fp=default") == 0)
12428 mips_opts.fp32 = file_mips_fp32;
12429 else if (strcmp (name, "fp=32") == 0)
12430 mips_opts.fp32 = 1;
12431 else if (strcmp (name, "fp=64") == 0)
12432 {
12433 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12434 as_warn ("%s isa does not support 64-bit floating point registers",
12435 mips_cpu_info_from_isa (mips_opts.isa)->name);
12436 mips_opts.fp32 = 0;
12437 }
12438 else if (strcmp (name, "mips16") == 0
12439 || strcmp (name, "MIPS-16") == 0)
12440 mips_opts.mips16 = 1;
12441 else if (strcmp (name, "nomips16") == 0
12442 || strcmp (name, "noMIPS-16") == 0)
12443 mips_opts.mips16 = 0;
12444 else if (strcmp (name, "smartmips") == 0)
12445 {
12446 if (!ISA_SUPPORTS_SMARTMIPS)
12447 as_warn ("%s ISA does not support SmartMIPS ASE",
12448 mips_cpu_info_from_isa (mips_opts.isa)->name);
12449 mips_opts.ase_smartmips = 1;
12450 }
12451 else if (strcmp (name, "nosmartmips") == 0)
12452 mips_opts.ase_smartmips = 0;
12453 else if (strcmp (name, "mips3d") == 0)
12454 mips_opts.ase_mips3d = 1;
12455 else if (strcmp (name, "nomips3d") == 0)
12456 mips_opts.ase_mips3d = 0;
12457 else if (strcmp (name, "mdmx") == 0)
12458 mips_opts.ase_mdmx = 1;
12459 else if (strcmp (name, "nomdmx") == 0)
12460 mips_opts.ase_mdmx = 0;
12461 else if (strcmp (name, "dsp") == 0)
12462 {
12463 if (!ISA_SUPPORTS_DSP_ASE)
12464 as_warn ("%s ISA does not support DSP ASE",
12465 mips_cpu_info_from_isa (mips_opts.isa)->name);
12466 mips_opts.ase_dsp = 1;
12467 mips_opts.ase_dspr2 = 0;
12468 }
12469 else if (strcmp (name, "nodsp") == 0)
12470 {
12471 mips_opts.ase_dsp = 0;
12472 mips_opts.ase_dspr2 = 0;
12473 }
12474 else if (strcmp (name, "dspr2") == 0)
12475 {
12476 if (!ISA_SUPPORTS_DSPR2_ASE)
12477 as_warn ("%s ISA does not support DSP R2 ASE",
12478 mips_cpu_info_from_isa (mips_opts.isa)->name);
12479 mips_opts.ase_dspr2 = 1;
12480 mips_opts.ase_dsp = 1;
12481 }
12482 else if (strcmp (name, "nodspr2") == 0)
12483 {
12484 mips_opts.ase_dspr2 = 0;
12485 mips_opts.ase_dsp = 0;
12486 }
12487 else if (strcmp (name, "mt") == 0)
12488 {
12489 if (!ISA_SUPPORTS_MT_ASE)
12490 as_warn ("%s ISA does not support MT ASE",
12491 mips_cpu_info_from_isa (mips_opts.isa)->name);
12492 mips_opts.ase_mt = 1;
12493 }
12494 else if (strcmp (name, "nomt") == 0)
12495 mips_opts.ase_mt = 0;
12496 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12497 {
12498 int reset = 0;
12499
12500 /* Permit the user to change the ISA and architecture on the fly.
12501 Needless to say, misuse can cause serious problems. */
12502 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
12503 {
12504 reset = 1;
12505 mips_opts.isa = file_mips_isa;
12506 mips_opts.arch = file_mips_arch;
12507 }
12508 else if (strncmp (name, "arch=", 5) == 0)
12509 {
12510 const struct mips_cpu_info *p;
12511
12512 p = mips_parse_cpu("internal use", name + 5);
12513 if (!p)
12514 as_bad (_("unknown architecture %s"), name + 5);
12515 else
12516 {
12517 mips_opts.arch = p->cpu;
12518 mips_opts.isa = p->isa;
12519 }
12520 }
12521 else if (strncmp (name, "mips", 4) == 0)
12522 {
12523 const struct mips_cpu_info *p;
12524
12525 p = mips_parse_cpu("internal use", name);
12526 if (!p)
12527 as_bad (_("unknown ISA level %s"), name + 4);
12528 else
12529 {
12530 mips_opts.arch = p->cpu;
12531 mips_opts.isa = p->isa;
12532 }
12533 }
12534 else
12535 as_bad (_("unknown ISA or architecture %s"), name);
12536
12537 switch (mips_opts.isa)
12538 {
12539 case 0:
12540 break;
12541 case ISA_MIPS1:
12542 case ISA_MIPS2:
12543 case ISA_MIPS32:
12544 case ISA_MIPS32R2:
12545 mips_opts.gp32 = 1;
12546 mips_opts.fp32 = 1;
12547 break;
12548 case ISA_MIPS3:
12549 case ISA_MIPS4:
12550 case ISA_MIPS5:
12551 case ISA_MIPS64:
12552 case ISA_MIPS64R2:
12553 mips_opts.gp32 = 0;
12554 mips_opts.fp32 = 0;
12555 break;
12556 default:
12557 as_bad (_("unknown ISA level %s"), name + 4);
12558 break;
12559 }
12560 if (reset)
12561 {
12562 mips_opts.gp32 = file_mips_gp32;
12563 mips_opts.fp32 = file_mips_fp32;
12564 }
12565 }
12566 else if (strcmp (name, "autoextend") == 0)
12567 mips_opts.noautoextend = 0;
12568 else if (strcmp (name, "noautoextend") == 0)
12569 mips_opts.noautoextend = 1;
12570 else if (strcmp (name, "push") == 0)
12571 {
12572 struct mips_option_stack *s;
12573
12574 s = (struct mips_option_stack *) xmalloc (sizeof *s);
12575 s->next = mips_opts_stack;
12576 s->options = mips_opts;
12577 mips_opts_stack = s;
12578 }
12579 else if (strcmp (name, "pop") == 0)
12580 {
12581 struct mips_option_stack *s;
12582
12583 s = mips_opts_stack;
12584 if (s == NULL)
12585 as_bad (_(".set pop with no .set push"));
12586 else
12587 {
12588 /* If we're changing the reorder mode we need to handle
12589 delay slots correctly. */
12590 if (s->options.noreorder && ! mips_opts.noreorder)
12591 start_noreorder ();
12592 else if (! s->options.noreorder && mips_opts.noreorder)
12593 end_noreorder ();
12594
12595 mips_opts = s->options;
12596 mips_opts_stack = s->next;
12597 free (s);
12598 }
12599 }
12600 else if (strcmp (name, "sym32") == 0)
12601 mips_opts.sym32 = TRUE;
12602 else if (strcmp (name, "nosym32") == 0)
12603 mips_opts.sym32 = FALSE;
12604 else if (strchr (name, ','))
12605 {
12606 /* Generic ".set" directive; use the generic handler. */
12607 *input_line_pointer = ch;
12608 input_line_pointer = name;
12609 s_set (0);
12610 return;
12611 }
12612 else
12613 {
12614 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12615 }
12616 *input_line_pointer = ch;
12617 demand_empty_rest_of_line ();
12618 }
12619
12620 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12621 .option pic2. It means to generate SVR4 PIC calls. */
12622
12623 static void
12624 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12625 {
12626 mips_pic = SVR4_PIC;
12627 mips_abicalls = TRUE;
12628
12629 if (g_switch_seen && g_switch_value != 0)
12630 as_warn (_("-G may not be used with SVR4 PIC code"));
12631 g_switch_value = 0;
12632
12633 bfd_set_gp_size (stdoutput, 0);
12634 demand_empty_rest_of_line ();
12635 }
12636
12637 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12638 PIC code. It sets the $gp register for the function based on the
12639 function address, which is in the register named in the argument.
12640 This uses a relocation against _gp_disp, which is handled specially
12641 by the linker. The result is:
12642 lui $gp,%hi(_gp_disp)
12643 addiu $gp,$gp,%lo(_gp_disp)
12644 addu $gp,$gp,.cpload argument
12645 The .cpload argument is normally $25 == $t9.
12646
12647 The -mno-shared option changes this to:
12648 lui $gp,%hi(__gnu_local_gp)
12649 addiu $gp,$gp,%lo(__gnu_local_gp)
12650 and the argument is ignored. This saves an instruction, but the
12651 resulting code is not position independent; it uses an absolute
12652 address for __gnu_local_gp. Thus code assembled with -mno-shared
12653 can go into an ordinary executable, but not into a shared library. */
12654
12655 static void
12656 s_cpload (int ignore ATTRIBUTE_UNUSED)
12657 {
12658 expressionS ex;
12659 int reg;
12660 int in_shared;
12661
12662 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12663 .cpload is ignored. */
12664 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12665 {
12666 s_ignore (0);
12667 return;
12668 }
12669
12670 /* .cpload should be in a .set noreorder section. */
12671 if (mips_opts.noreorder == 0)
12672 as_warn (_(".cpload not in noreorder section"));
12673
12674 reg = tc_get_register (0);
12675
12676 /* If we need to produce a 64-bit address, we are better off using
12677 the default instruction sequence. */
12678 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
12679
12680 ex.X_op = O_symbol;
12681 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
12682 "__gnu_local_gp");
12683 ex.X_op_symbol = NULL;
12684 ex.X_add_number = 0;
12685
12686 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12687 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12688
12689 macro_start ();
12690 macro_build_lui (&ex, mips_gp_register);
12691 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12692 mips_gp_register, BFD_RELOC_LO16);
12693 if (in_shared)
12694 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12695 mips_gp_register, reg);
12696 macro_end ();
12697
12698 demand_empty_rest_of_line ();
12699 }
12700
12701 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12702 .cpsetup $reg1, offset|$reg2, label
12703
12704 If offset is given, this results in:
12705 sd $gp, offset($sp)
12706 lui $gp, %hi(%neg(%gp_rel(label)))
12707 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12708 daddu $gp, $gp, $reg1
12709
12710 If $reg2 is given, this results in:
12711 daddu $reg2, $gp, $0
12712 lui $gp, %hi(%neg(%gp_rel(label)))
12713 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12714 daddu $gp, $gp, $reg1
12715 $reg1 is normally $25 == $t9.
12716
12717 The -mno-shared option replaces the last three instructions with
12718 lui $gp,%hi(_gp)
12719 addiu $gp,$gp,%lo(_gp) */
12720
12721 static void
12722 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12723 {
12724 expressionS ex_off;
12725 expressionS ex_sym;
12726 int reg1;
12727
12728 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12729 We also need NewABI support. */
12730 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12731 {
12732 s_ignore (0);
12733 return;
12734 }
12735
12736 reg1 = tc_get_register (0);
12737 SKIP_WHITESPACE ();
12738 if (*input_line_pointer != ',')
12739 {
12740 as_bad (_("missing argument separator ',' for .cpsetup"));
12741 return;
12742 }
12743 else
12744 ++input_line_pointer;
12745 SKIP_WHITESPACE ();
12746 if (*input_line_pointer == '$')
12747 {
12748 mips_cpreturn_register = tc_get_register (0);
12749 mips_cpreturn_offset = -1;
12750 }
12751 else
12752 {
12753 mips_cpreturn_offset = get_absolute_expression ();
12754 mips_cpreturn_register = -1;
12755 }
12756 SKIP_WHITESPACE ();
12757 if (*input_line_pointer != ',')
12758 {
12759 as_bad (_("missing argument separator ',' for .cpsetup"));
12760 return;
12761 }
12762 else
12763 ++input_line_pointer;
12764 SKIP_WHITESPACE ();
12765 expression (&ex_sym);
12766
12767 macro_start ();
12768 if (mips_cpreturn_register == -1)
12769 {
12770 ex_off.X_op = O_constant;
12771 ex_off.X_add_symbol = NULL;
12772 ex_off.X_op_symbol = NULL;
12773 ex_off.X_add_number = mips_cpreturn_offset;
12774
12775 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12776 BFD_RELOC_LO16, SP);
12777 }
12778 else
12779 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12780 mips_gp_register, 0);
12781
12782 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
12783 {
12784 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
12785 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
12786 BFD_RELOC_HI16_S);
12787
12788 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12789 mips_gp_register, -1, BFD_RELOC_GPREL16,
12790 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
12791
12792 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12793 mips_gp_register, reg1);
12794 }
12795 else
12796 {
12797 expressionS ex;
12798
12799 ex.X_op = O_symbol;
12800 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
12801 ex.X_op_symbol = NULL;
12802 ex.X_add_number = 0;
12803
12804 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12805 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12806
12807 macro_build_lui (&ex, mips_gp_register);
12808 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12809 mips_gp_register, BFD_RELOC_LO16);
12810 }
12811
12812 macro_end ();
12813
12814 demand_empty_rest_of_line ();
12815 }
12816
12817 static void
12818 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12819 {
12820 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12821 .cplocal is ignored. */
12822 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12823 {
12824 s_ignore (0);
12825 return;
12826 }
12827
12828 mips_gp_register = tc_get_register (0);
12829 demand_empty_rest_of_line ();
12830 }
12831
12832 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12833 offset from $sp. The offset is remembered, and after making a PIC
12834 call $gp is restored from that location. */
12835
12836 static void
12837 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12838 {
12839 expressionS ex;
12840
12841 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12842 .cprestore is ignored. */
12843 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12844 {
12845 s_ignore (0);
12846 return;
12847 }
12848
12849 mips_cprestore_offset = get_absolute_expression ();
12850 mips_cprestore_valid = 1;
12851
12852 ex.X_op = O_constant;
12853 ex.X_add_symbol = NULL;
12854 ex.X_op_symbol = NULL;
12855 ex.X_add_number = mips_cprestore_offset;
12856
12857 macro_start ();
12858 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
12859 SP, HAVE_64BIT_ADDRESSES);
12860 macro_end ();
12861
12862 demand_empty_rest_of_line ();
12863 }
12864
12865 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12866 was given in the preceding .cpsetup, it results in:
12867 ld $gp, offset($sp)
12868
12869 If a register $reg2 was given there, it results in:
12870 daddu $gp, $reg2, $0 */
12871
12872 static void
12873 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12874 {
12875 expressionS ex;
12876
12877 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12878 We also need NewABI support. */
12879 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12880 {
12881 s_ignore (0);
12882 return;
12883 }
12884
12885 macro_start ();
12886 if (mips_cpreturn_register == -1)
12887 {
12888 ex.X_op = O_constant;
12889 ex.X_add_symbol = NULL;
12890 ex.X_op_symbol = NULL;
12891 ex.X_add_number = mips_cpreturn_offset;
12892
12893 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12894 }
12895 else
12896 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12897 mips_cpreturn_register, 0);
12898 macro_end ();
12899
12900 demand_empty_rest_of_line ();
12901 }
12902
12903 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
12904 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
12905 use in DWARF debug information. */
12906
12907 static void
12908 s_dtprel_internal (size_t bytes)
12909 {
12910 expressionS ex;
12911 char *p;
12912
12913 expression (&ex);
12914
12915 if (ex.X_op != O_symbol)
12916 {
12917 as_bad (_("Unsupported use of %s"), (bytes == 8
12918 ? ".dtpreldword"
12919 : ".dtprelword"));
12920 ignore_rest_of_line ();
12921 }
12922
12923 p = frag_more (bytes);
12924 md_number_to_chars (p, 0, bytes);
12925 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
12926 (bytes == 8
12927 ? BFD_RELOC_MIPS_TLS_DTPREL64
12928 : BFD_RELOC_MIPS_TLS_DTPREL32));
12929
12930 demand_empty_rest_of_line ();
12931 }
12932
12933 /* Handle .dtprelword. */
12934
12935 static void
12936 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
12937 {
12938 s_dtprel_internal (4);
12939 }
12940
12941 /* Handle .dtpreldword. */
12942
12943 static void
12944 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
12945 {
12946 s_dtprel_internal (8);
12947 }
12948
12949 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12950 code. It sets the offset to use in gp_rel relocations. */
12951
12952 static void
12953 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12954 {
12955 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12956 We also need NewABI support. */
12957 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12958 {
12959 s_ignore (0);
12960 return;
12961 }
12962
12963 mips_gprel_offset = get_absolute_expression ();
12964
12965 demand_empty_rest_of_line ();
12966 }
12967
12968 /* Handle the .gpword pseudo-op. This is used when generating PIC
12969 code. It generates a 32 bit GP relative reloc. */
12970
12971 static void
12972 s_gpword (int ignore ATTRIBUTE_UNUSED)
12973 {
12974 segment_info_type *si;
12975 struct insn_label_list *l;
12976 symbolS *label;
12977 expressionS ex;
12978 char *p;
12979
12980 /* When not generating PIC code, this is treated as .word. */
12981 if (mips_pic != SVR4_PIC)
12982 {
12983 s_cons (2);
12984 return;
12985 }
12986
12987 si = seg_info (now_seg);
12988 l = si->label_list;
12989 label = l != NULL ? l->label : NULL;
12990 mips_emit_delays ();
12991 if (auto_align)
12992 mips_align (2, 0, label);
12993 mips_clear_insn_labels ();
12994
12995 expression (&ex);
12996
12997 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12998 {
12999 as_bad (_("Unsupported use of .gpword"));
13000 ignore_rest_of_line ();
13001 }
13002
13003 p = frag_more (4);
13004 md_number_to_chars (p, 0, 4);
13005 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13006 BFD_RELOC_GPREL32);
13007
13008 demand_empty_rest_of_line ();
13009 }
13010
13011 static void
13012 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13013 {
13014 segment_info_type *si;
13015 struct insn_label_list *l;
13016 symbolS *label;
13017 expressionS ex;
13018 char *p;
13019
13020 /* When not generating PIC code, this is treated as .dword. */
13021 if (mips_pic != SVR4_PIC)
13022 {
13023 s_cons (3);
13024 return;
13025 }
13026
13027 si = seg_info (now_seg);
13028 l = si->label_list;
13029 label = l != NULL ? l->label : NULL;
13030 mips_emit_delays ();
13031 if (auto_align)
13032 mips_align (3, 0, label);
13033 mips_clear_insn_labels ();
13034
13035 expression (&ex);
13036
13037 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13038 {
13039 as_bad (_("Unsupported use of .gpdword"));
13040 ignore_rest_of_line ();
13041 }
13042
13043 p = frag_more (8);
13044 md_number_to_chars (p, 0, 8);
13045 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13046 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13047
13048 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13049 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13050 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13051
13052 demand_empty_rest_of_line ();
13053 }
13054
13055 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13056 tables in SVR4 PIC code. */
13057
13058 static void
13059 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13060 {
13061 int reg;
13062
13063 /* This is ignored when not generating SVR4 PIC code. */
13064 if (mips_pic != SVR4_PIC)
13065 {
13066 s_ignore (0);
13067 return;
13068 }
13069
13070 /* Add $gp to the register named as an argument. */
13071 macro_start ();
13072 reg = tc_get_register (0);
13073 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13074 macro_end ();
13075
13076 demand_empty_rest_of_line ();
13077 }
13078
13079 /* Handle the .insn pseudo-op. This marks instruction labels in
13080 mips16 mode. This permits the linker to handle them specially,
13081 such as generating jalx instructions when needed. We also make
13082 them odd for the duration of the assembly, in order to generate the
13083 right sort of code. We will make them even in the adjust_symtab
13084 routine, while leaving them marked. This is convenient for the
13085 debugger and the disassembler. The linker knows to make them odd
13086 again. */
13087
13088 static void
13089 s_insn (int ignore ATTRIBUTE_UNUSED)
13090 {
13091 mips16_mark_labels ();
13092
13093 demand_empty_rest_of_line ();
13094 }
13095
13096 /* Handle a .stabn directive. We need these in order to mark a label
13097 as being a mips16 text label correctly. Sometimes the compiler
13098 will emit a label, followed by a .stabn, and then switch sections.
13099 If the label and .stabn are in mips16 mode, then the label is
13100 really a mips16 text label. */
13101
13102 static void
13103 s_mips_stab (int type)
13104 {
13105 if (type == 'n')
13106 mips16_mark_labels ();
13107
13108 s_stab (type);
13109 }
13110
13111 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13112
13113 static void
13114 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13115 {
13116 char *name;
13117 int c;
13118 symbolS *symbolP;
13119 expressionS exp;
13120
13121 name = input_line_pointer;
13122 c = get_symbol_end ();
13123 symbolP = symbol_find_or_make (name);
13124 S_SET_WEAK (symbolP);
13125 *input_line_pointer = c;
13126
13127 SKIP_WHITESPACE ();
13128
13129 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13130 {
13131 if (S_IS_DEFINED (symbolP))
13132 {
13133 as_bad ("ignoring attempt to redefine symbol %s",
13134 S_GET_NAME (symbolP));
13135 ignore_rest_of_line ();
13136 return;
13137 }
13138
13139 if (*input_line_pointer == ',')
13140 {
13141 ++input_line_pointer;
13142 SKIP_WHITESPACE ();
13143 }
13144
13145 expression (&exp);
13146 if (exp.X_op != O_symbol)
13147 {
13148 as_bad ("bad .weakext directive");
13149 ignore_rest_of_line ();
13150 return;
13151 }
13152 symbol_set_value_expression (symbolP, &exp);
13153 }
13154
13155 demand_empty_rest_of_line ();
13156 }
13157
13158 /* Parse a register string into a number. Called from the ECOFF code
13159 to parse .frame. The argument is non-zero if this is the frame
13160 register, so that we can record it in mips_frame_reg. */
13161
13162 int
13163 tc_get_register (int frame)
13164 {
13165 unsigned int reg;
13166
13167 SKIP_WHITESPACE ();
13168 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
13169 reg = 0;
13170 if (frame)
13171 {
13172 mips_frame_reg = reg != 0 ? reg : SP;
13173 mips_frame_reg_valid = 1;
13174 mips_cprestore_valid = 0;
13175 }
13176 return reg;
13177 }
13178
13179 valueT
13180 md_section_align (asection *seg, valueT addr)
13181 {
13182 int align = bfd_get_section_alignment (stdoutput, seg);
13183
13184 if (IS_ELF)
13185 {
13186 /* We don't need to align ELF sections to the full alignment.
13187 However, Irix 5 may prefer that we align them at least to a 16
13188 byte boundary. We don't bother to align the sections if we
13189 are targeted for an embedded system. */
13190 if (strcmp (TARGET_OS, "elf") == 0)
13191 return addr;
13192 if (align > 4)
13193 align = 4;
13194 }
13195
13196 return ((addr + (1 << align) - 1) & (-1 << align));
13197 }
13198
13199 /* Utility routine, called from above as well. If called while the
13200 input file is still being read, it's only an approximation. (For
13201 example, a symbol may later become defined which appeared to be
13202 undefined earlier.) */
13203
13204 static int
13205 nopic_need_relax (symbolS *sym, int before_relaxing)
13206 {
13207 if (sym == 0)
13208 return 0;
13209
13210 if (g_switch_value > 0)
13211 {
13212 const char *symname;
13213 int change;
13214
13215 /* Find out whether this symbol can be referenced off the $gp
13216 register. It can be if it is smaller than the -G size or if
13217 it is in the .sdata or .sbss section. Certain symbols can
13218 not be referenced off the $gp, although it appears as though
13219 they can. */
13220 symname = S_GET_NAME (sym);
13221 if (symname != (const char *) NULL
13222 && (strcmp (symname, "eprol") == 0
13223 || strcmp (symname, "etext") == 0
13224 || strcmp (symname, "_gp") == 0
13225 || strcmp (symname, "edata") == 0
13226 || strcmp (symname, "_fbss") == 0
13227 || strcmp (symname, "_fdata") == 0
13228 || strcmp (symname, "_ftext") == 0
13229 || strcmp (symname, "end") == 0
13230 || strcmp (symname, "_gp_disp") == 0))
13231 change = 1;
13232 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13233 && (0
13234 #ifndef NO_ECOFF_DEBUGGING
13235 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13236 && (symbol_get_obj (sym)->ecoff_extern_size
13237 <= g_switch_value))
13238 #endif
13239 /* We must defer this decision until after the whole
13240 file has been read, since there might be a .extern
13241 after the first use of this symbol. */
13242 || (before_relaxing
13243 #ifndef NO_ECOFF_DEBUGGING
13244 && symbol_get_obj (sym)->ecoff_extern_size == 0
13245 #endif
13246 && S_GET_VALUE (sym) == 0)
13247 || (S_GET_VALUE (sym) != 0
13248 && S_GET_VALUE (sym) <= g_switch_value)))
13249 change = 0;
13250 else
13251 {
13252 const char *segname;
13253
13254 segname = segment_name (S_GET_SEGMENT (sym));
13255 assert (strcmp (segname, ".lit8") != 0
13256 && strcmp (segname, ".lit4") != 0);
13257 change = (strcmp (segname, ".sdata") != 0
13258 && strcmp (segname, ".sbss") != 0
13259 && strncmp (segname, ".sdata.", 7) != 0
13260 && strncmp (segname, ".sbss.", 6) != 0
13261 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13262 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13263 }
13264 return change;
13265 }
13266 else
13267 /* We are not optimizing for the $gp register. */
13268 return 1;
13269 }
13270
13271
13272 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13273
13274 static bfd_boolean
13275 pic_need_relax (symbolS *sym, asection *segtype)
13276 {
13277 asection *symsec;
13278
13279 /* Handle the case of a symbol equated to another symbol. */
13280 while (symbol_equated_reloc_p (sym))
13281 {
13282 symbolS *n;
13283
13284 /* It's possible to get a loop here in a badly written program. */
13285 n = symbol_get_value_expression (sym)->X_add_symbol;
13286 if (n == sym)
13287 break;
13288 sym = n;
13289 }
13290
13291 if (symbol_section_p (sym))
13292 return TRUE;
13293
13294 symsec = S_GET_SEGMENT (sym);
13295
13296 /* This must duplicate the test in adjust_reloc_syms. */
13297 return (symsec != &bfd_und_section
13298 && symsec != &bfd_abs_section
13299 && !bfd_is_com_section (symsec)
13300 && !s_is_linkonce (sym, segtype)
13301 #ifdef OBJ_ELF
13302 /* A global or weak symbol is treated as external. */
13303 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13304 #endif
13305 );
13306 }
13307
13308
13309 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13310 extended opcode. SEC is the section the frag is in. */
13311
13312 static int
13313 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13314 {
13315 int type;
13316 const struct mips16_immed_operand *op;
13317 offsetT val;
13318 int mintiny, maxtiny;
13319 segT symsec;
13320 fragS *sym_frag;
13321
13322 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13323 return 0;
13324 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13325 return 1;
13326
13327 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13328 op = mips16_immed_operands;
13329 while (op->type != type)
13330 {
13331 ++op;
13332 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13333 }
13334
13335 if (op->unsp)
13336 {
13337 if (type == '<' || type == '>' || type == '[' || type == ']')
13338 {
13339 mintiny = 1;
13340 maxtiny = 1 << op->nbits;
13341 }
13342 else
13343 {
13344 mintiny = 0;
13345 maxtiny = (1 << op->nbits) - 1;
13346 }
13347 }
13348 else
13349 {
13350 mintiny = - (1 << (op->nbits - 1));
13351 maxtiny = (1 << (op->nbits - 1)) - 1;
13352 }
13353
13354 sym_frag = symbol_get_frag (fragp->fr_symbol);
13355 val = S_GET_VALUE (fragp->fr_symbol);
13356 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13357
13358 if (op->pcrel)
13359 {
13360 addressT addr;
13361
13362 /* We won't have the section when we are called from
13363 mips_relax_frag. However, we will always have been called
13364 from md_estimate_size_before_relax first. If this is a
13365 branch to a different section, we mark it as such. If SEC is
13366 NULL, and the frag is not marked, then it must be a branch to
13367 the same section. */
13368 if (sec == NULL)
13369 {
13370 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13371 return 1;
13372 }
13373 else
13374 {
13375 /* Must have been called from md_estimate_size_before_relax. */
13376 if (symsec != sec)
13377 {
13378 fragp->fr_subtype =
13379 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13380
13381 /* FIXME: We should support this, and let the linker
13382 catch branches and loads that are out of range. */
13383 as_bad_where (fragp->fr_file, fragp->fr_line,
13384 _("unsupported PC relative reference to different section"));
13385
13386 return 1;
13387 }
13388 if (fragp != sym_frag && sym_frag->fr_address == 0)
13389 /* Assume non-extended on the first relaxation pass.
13390 The address we have calculated will be bogus if this is
13391 a forward branch to another frag, as the forward frag
13392 will have fr_address == 0. */
13393 return 0;
13394 }
13395
13396 /* In this case, we know for sure that the symbol fragment is in
13397 the same section. If the relax_marker of the symbol fragment
13398 differs from the relax_marker of this fragment, we have not
13399 yet adjusted the symbol fragment fr_address. We want to add
13400 in STRETCH in order to get a better estimate of the address.
13401 This particularly matters because of the shift bits. */
13402 if (stretch != 0
13403 && sym_frag->relax_marker != fragp->relax_marker)
13404 {
13405 fragS *f;
13406
13407 /* Adjust stretch for any alignment frag. Note that if have
13408 been expanding the earlier code, the symbol may be
13409 defined in what appears to be an earlier frag. FIXME:
13410 This doesn't handle the fr_subtype field, which specifies
13411 a maximum number of bytes to skip when doing an
13412 alignment. */
13413 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13414 {
13415 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13416 {
13417 if (stretch < 0)
13418 stretch = - ((- stretch)
13419 & ~ ((1 << (int) f->fr_offset) - 1));
13420 else
13421 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13422 if (stretch == 0)
13423 break;
13424 }
13425 }
13426 if (f != NULL)
13427 val += stretch;
13428 }
13429
13430 addr = fragp->fr_address + fragp->fr_fix;
13431
13432 /* The base address rules are complicated. The base address of
13433 a branch is the following instruction. The base address of a
13434 PC relative load or add is the instruction itself, but if it
13435 is in a delay slot (in which case it can not be extended) use
13436 the address of the instruction whose delay slot it is in. */
13437 if (type == 'p' || type == 'q')
13438 {
13439 addr += 2;
13440
13441 /* If we are currently assuming that this frag should be
13442 extended, then, the current address is two bytes
13443 higher. */
13444 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13445 addr += 2;
13446
13447 /* Ignore the low bit in the target, since it will be set
13448 for a text label. */
13449 if ((val & 1) != 0)
13450 --val;
13451 }
13452 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13453 addr -= 4;
13454 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13455 addr -= 2;
13456
13457 val -= addr & ~ ((1 << op->shift) - 1);
13458
13459 /* Branch offsets have an implicit 0 in the lowest bit. */
13460 if (type == 'p' || type == 'q')
13461 val /= 2;
13462
13463 /* If any of the shifted bits are set, we must use an extended
13464 opcode. If the address depends on the size of this
13465 instruction, this can lead to a loop, so we arrange to always
13466 use an extended opcode. We only check this when we are in
13467 the main relaxation loop, when SEC is NULL. */
13468 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13469 {
13470 fragp->fr_subtype =
13471 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13472 return 1;
13473 }
13474
13475 /* If we are about to mark a frag as extended because the value
13476 is precisely maxtiny + 1, then there is a chance of an
13477 infinite loop as in the following code:
13478 la $4,foo
13479 .skip 1020
13480 .align 2
13481 foo:
13482 In this case when the la is extended, foo is 0x3fc bytes
13483 away, so the la can be shrunk, but then foo is 0x400 away, so
13484 the la must be extended. To avoid this loop, we mark the
13485 frag as extended if it was small, and is about to become
13486 extended with a value of maxtiny + 1. */
13487 if (val == ((maxtiny + 1) << op->shift)
13488 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13489 && sec == NULL)
13490 {
13491 fragp->fr_subtype =
13492 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13493 return 1;
13494 }
13495 }
13496 else if (symsec != absolute_section && sec != NULL)
13497 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13498
13499 if ((val & ((1 << op->shift) - 1)) != 0
13500 || val < (mintiny << op->shift)
13501 || val > (maxtiny << op->shift))
13502 return 1;
13503 else
13504 return 0;
13505 }
13506
13507 /* Compute the length of a branch sequence, and adjust the
13508 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13509 worst-case length is computed, with UPDATE being used to indicate
13510 whether an unconditional (-1), branch-likely (+1) or regular (0)
13511 branch is to be computed. */
13512 static int
13513 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13514 {
13515 bfd_boolean toofar;
13516 int length;
13517
13518 if (fragp
13519 && S_IS_DEFINED (fragp->fr_symbol)
13520 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13521 {
13522 addressT addr;
13523 offsetT val;
13524
13525 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13526
13527 addr = fragp->fr_address + fragp->fr_fix + 4;
13528
13529 val -= addr;
13530
13531 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13532 }
13533 else if (fragp)
13534 /* If the symbol is not defined or it's in a different segment,
13535 assume the user knows what's going on and emit a short
13536 branch. */
13537 toofar = FALSE;
13538 else
13539 toofar = TRUE;
13540
13541 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13542 fragp->fr_subtype
13543 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13544 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13545 RELAX_BRANCH_LINK (fragp->fr_subtype),
13546 toofar);
13547
13548 length = 4;
13549 if (toofar)
13550 {
13551 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
13552 length += 8;
13553
13554 if (mips_pic != NO_PIC)
13555 {
13556 /* Additional space for PIC loading of target address. */
13557 length += 8;
13558 if (mips_opts.isa == ISA_MIPS1)
13559 /* Additional space for $at-stabilizing nop. */
13560 length += 4;
13561 }
13562
13563 /* If branch is conditional. */
13564 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
13565 length += 8;
13566 }
13567
13568 return length;
13569 }
13570
13571 /* Estimate the size of a frag before relaxing. Unless this is the
13572 mips16, we are not really relaxing here, and the final size is
13573 encoded in the subtype information. For the mips16, we have to
13574 decide whether we are using an extended opcode or not. */
13575
13576 int
13577 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
13578 {
13579 int change;
13580
13581 if (RELAX_BRANCH_P (fragp->fr_subtype))
13582 {
13583
13584 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
13585
13586 return fragp->fr_var;
13587 }
13588
13589 if (RELAX_MIPS16_P (fragp->fr_subtype))
13590 /* We don't want to modify the EXTENDED bit here; it might get us
13591 into infinite loops. We change it only in mips_relax_frag(). */
13592 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13593
13594 if (mips_pic == NO_PIC)
13595 change = nopic_need_relax (fragp->fr_symbol, 0);
13596 else if (mips_pic == SVR4_PIC)
13597 change = pic_need_relax (fragp->fr_symbol, segtype);
13598 else if (mips_pic == VXWORKS_PIC)
13599 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13600 change = 0;
13601 else
13602 abort ();
13603
13604 if (change)
13605 {
13606 fragp->fr_subtype |= RELAX_USE_SECOND;
13607 return -RELAX_FIRST (fragp->fr_subtype);
13608 }
13609 else
13610 return -RELAX_SECOND (fragp->fr_subtype);
13611 }
13612
13613 /* This is called to see whether a reloc against a defined symbol
13614 should be converted into a reloc against a section. */
13615
13616 int
13617 mips_fix_adjustable (fixS *fixp)
13618 {
13619 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13620 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13621 return 0;
13622
13623 if (fixp->fx_addsy == NULL)
13624 return 1;
13625
13626 /* If symbol SYM is in a mergeable section, relocations of the form
13627 SYM + 0 can usually be made section-relative. The mergeable data
13628 is then identified by the section offset rather than by the symbol.
13629
13630 However, if we're generating REL LO16 relocations, the offset is split
13631 between the LO16 and parterning high part relocation. The linker will
13632 need to recalculate the complete offset in order to correctly identify
13633 the merge data.
13634
13635 The linker has traditionally not looked for the parterning high part
13636 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13637 placed anywhere. Rather than break backwards compatibility by changing
13638 this, it seems better not to force the issue, and instead keep the
13639 original symbol. This will work with either linker behavior. */
13640 if ((fixp->fx_r_type == BFD_RELOC_LO16
13641 || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16
13642 || reloc_needs_lo_p (fixp->fx_r_type))
13643 && HAVE_IN_PLACE_ADDENDS
13644 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
13645 return 0;
13646
13647 #ifdef OBJ_ELF
13648 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
13649 to a floating-point stub. The same is true for non-R_MIPS16_26
13650 relocations against MIPS16 functions; in this case, the stub becomes
13651 the function's canonical address.
13652
13653 Floating-point stubs are stored in unique .mips16.call.* or
13654 .mips16.fn.* sections. If a stub T for function F is in section S,
13655 the first relocation in section S must be against F; this is how the
13656 linker determines the target function. All relocations that might
13657 resolve to T must also be against F. We therefore have the following
13658 restrictions, which are given in an intentionally-redundant way:
13659
13660 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
13661 symbols.
13662
13663 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
13664 if that stub might be used.
13665
13666 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
13667 symbols.
13668
13669 4. We cannot reduce a stub's relocations against MIPS16 symbols if
13670 that stub might be used.
13671
13672 There is a further restriction:
13673
13674 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
13675 on targets with in-place addends; the relocation field cannot
13676 encode the low bit.
13677
13678 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
13679 against a MIPS16 symbol.
13680
13681 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
13682 relocation against some symbol R, no relocation against R may be
13683 reduced. (Note that this deals with (2) as well as (1) because
13684 relocations against global symbols will never be reduced on ELF
13685 targets.) This approach is a little simpler than trying to detect
13686 stub sections, and gives the "all or nothing" per-symbol consistency
13687 that we have for MIPS16 symbols. */
13688 if (IS_ELF
13689 && fixp->fx_subsy == NULL
13690 && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13691 || *symbol_get_tc (fixp->fx_addsy)))
13692 return 0;
13693 #endif
13694
13695 return 1;
13696 }
13697
13698 /* Translate internal representation of relocation info to BFD target
13699 format. */
13700
13701 arelent **
13702 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13703 {
13704 static arelent *retval[4];
13705 arelent *reloc;
13706 bfd_reloc_code_real_type code;
13707
13708 memset (retval, 0, sizeof(retval));
13709 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13710 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13711 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13712 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13713
13714 if (fixp->fx_pcrel)
13715 {
13716 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
13717
13718 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13719 Relocations want only the symbol offset. */
13720 reloc->addend = fixp->fx_addnumber + reloc->address;
13721 if (!IS_ELF)
13722 {
13723 /* A gruesome hack which is a result of the gruesome gas
13724 reloc handling. What's worse, for COFF (as opposed to
13725 ECOFF), we might need yet another copy of reloc->address.
13726 See bfd_install_relocation. */
13727 reloc->addend += reloc->address;
13728 }
13729 }
13730 else
13731 reloc->addend = fixp->fx_addnumber;
13732
13733 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13734 entry to be used in the relocation's section offset. */
13735 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13736 {
13737 reloc->address = reloc->addend;
13738 reloc->addend = 0;
13739 }
13740
13741 code = fixp->fx_r_type;
13742
13743 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13744 if (reloc->howto == NULL)
13745 {
13746 as_bad_where (fixp->fx_file, fixp->fx_line,
13747 _("Can not represent %s relocation in this object file format"),
13748 bfd_get_reloc_code_name (code));
13749 retval[0] = NULL;
13750 }
13751
13752 return retval;
13753 }
13754
13755 /* Relax a machine dependent frag. This returns the amount by which
13756 the current size of the frag should change. */
13757
13758 int
13759 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13760 {
13761 if (RELAX_BRANCH_P (fragp->fr_subtype))
13762 {
13763 offsetT old_var = fragp->fr_var;
13764
13765 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13766
13767 return fragp->fr_var - old_var;
13768 }
13769
13770 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13771 return 0;
13772
13773 if (mips16_extended_frag (fragp, NULL, stretch))
13774 {
13775 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13776 return 0;
13777 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13778 return 2;
13779 }
13780 else
13781 {
13782 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13783 return 0;
13784 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13785 return -2;
13786 }
13787
13788 return 0;
13789 }
13790
13791 /* Convert a machine dependent frag. */
13792
13793 void
13794 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13795 {
13796 if (RELAX_BRANCH_P (fragp->fr_subtype))
13797 {
13798 bfd_byte *buf;
13799 unsigned long insn;
13800 expressionS exp;
13801 fixS *fixp;
13802
13803 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13804
13805 if (target_big_endian)
13806 insn = bfd_getb32 (buf);
13807 else
13808 insn = bfd_getl32 (buf);
13809
13810 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13811 {
13812 /* We generate a fixup instead of applying it right now
13813 because, if there are linker relaxations, we're going to
13814 need the relocations. */
13815 exp.X_op = O_symbol;
13816 exp.X_add_symbol = fragp->fr_symbol;
13817 exp.X_add_number = fragp->fr_offset;
13818
13819 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13820 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
13821 fixp->fx_file = fragp->fr_file;
13822 fixp->fx_line = fragp->fr_line;
13823
13824 md_number_to_chars ((char *) buf, insn, 4);
13825 buf += 4;
13826 }
13827 else
13828 {
13829 int i;
13830
13831 as_warn_where (fragp->fr_file, fragp->fr_line,
13832 _("relaxed out-of-range branch into a jump"));
13833
13834 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13835 goto uncond;
13836
13837 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13838 {
13839 /* Reverse the branch. */
13840 switch ((insn >> 28) & 0xf)
13841 {
13842 case 4:
13843 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13844 have the condition reversed by tweaking a single
13845 bit, and their opcodes all have 0x4???????. */
13846 assert ((insn & 0xf1000000) == 0x41000000);
13847 insn ^= 0x00010000;
13848 break;
13849
13850 case 0:
13851 /* bltz 0x04000000 bgez 0x04010000
13852 bltzal 0x04100000 bgezal 0x04110000 */
13853 assert ((insn & 0xfc0e0000) == 0x04000000);
13854 insn ^= 0x00010000;
13855 break;
13856
13857 case 1:
13858 /* beq 0x10000000 bne 0x14000000
13859 blez 0x18000000 bgtz 0x1c000000 */
13860 insn ^= 0x04000000;
13861 break;
13862
13863 default:
13864 abort ();
13865 }
13866 }
13867
13868 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13869 {
13870 /* Clear the and-link bit. */
13871 assert ((insn & 0xfc1c0000) == 0x04100000);
13872
13873 /* bltzal 0x04100000 bgezal 0x04110000
13874 bltzall 0x04120000 bgezall 0x04130000 */
13875 insn &= ~0x00100000;
13876 }
13877
13878 /* Branch over the branch (if the branch was likely) or the
13879 full jump (not likely case). Compute the offset from the
13880 current instruction to branch to. */
13881 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13882 i = 16;
13883 else
13884 {
13885 /* How many bytes in instructions we've already emitted? */
13886 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13887 /* How many bytes in instructions from here to the end? */
13888 i = fragp->fr_var - i;
13889 }
13890 /* Convert to instruction count. */
13891 i >>= 2;
13892 /* Branch counts from the next instruction. */
13893 i--;
13894 insn |= i;
13895 /* Branch over the jump. */
13896 md_number_to_chars ((char *) buf, insn, 4);
13897 buf += 4;
13898
13899 /* nop */
13900 md_number_to_chars ((char *) buf, 0, 4);
13901 buf += 4;
13902
13903 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13904 {
13905 /* beql $0, $0, 2f */
13906 insn = 0x50000000;
13907 /* Compute the PC offset from the current instruction to
13908 the end of the variable frag. */
13909 /* How many bytes in instructions we've already emitted? */
13910 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13911 /* How many bytes in instructions from here to the end? */
13912 i = fragp->fr_var - i;
13913 /* Convert to instruction count. */
13914 i >>= 2;
13915 /* Don't decrement i, because we want to branch over the
13916 delay slot. */
13917
13918 insn |= i;
13919 md_number_to_chars ((char *) buf, insn, 4);
13920 buf += 4;
13921
13922 md_number_to_chars ((char *) buf, 0, 4);
13923 buf += 4;
13924 }
13925
13926 uncond:
13927 if (mips_pic == NO_PIC)
13928 {
13929 /* j or jal. */
13930 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13931 ? 0x0c000000 : 0x08000000);
13932 exp.X_op = O_symbol;
13933 exp.X_add_symbol = fragp->fr_symbol;
13934 exp.X_add_number = fragp->fr_offset;
13935
13936 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13937 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
13938 fixp->fx_file = fragp->fr_file;
13939 fixp->fx_line = fragp->fr_line;
13940
13941 md_number_to_chars ((char *) buf, insn, 4);
13942 buf += 4;
13943 }
13944 else
13945 {
13946 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13947 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13948 exp.X_op = O_symbol;
13949 exp.X_add_symbol = fragp->fr_symbol;
13950 exp.X_add_number = fragp->fr_offset;
13951
13952 if (fragp->fr_offset)
13953 {
13954 exp.X_add_symbol = make_expr_symbol (&exp);
13955 exp.X_add_number = 0;
13956 }
13957
13958 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13959 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
13960 fixp->fx_file = fragp->fr_file;
13961 fixp->fx_line = fragp->fr_line;
13962
13963 md_number_to_chars ((char *) buf, insn, 4);
13964 buf += 4;
13965
13966 if (mips_opts.isa == ISA_MIPS1)
13967 {
13968 /* nop */
13969 md_number_to_chars ((char *) buf, 0, 4);
13970 buf += 4;
13971 }
13972
13973 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13974 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13975
13976 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13977 4, &exp, FALSE, BFD_RELOC_LO16);
13978 fixp->fx_file = fragp->fr_file;
13979 fixp->fx_line = fragp->fr_line;
13980
13981 md_number_to_chars ((char *) buf, insn, 4);
13982 buf += 4;
13983
13984 /* j(al)r $at. */
13985 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13986 insn = 0x0020f809;
13987 else
13988 insn = 0x00200008;
13989
13990 md_number_to_chars ((char *) buf, insn, 4);
13991 buf += 4;
13992 }
13993 }
13994
13995 assert (buf == (bfd_byte *)fragp->fr_literal
13996 + fragp->fr_fix + fragp->fr_var);
13997
13998 fragp->fr_fix += fragp->fr_var;
13999
14000 return;
14001 }
14002
14003 if (RELAX_MIPS16_P (fragp->fr_subtype))
14004 {
14005 int type;
14006 const struct mips16_immed_operand *op;
14007 bfd_boolean small, ext;
14008 offsetT val;
14009 bfd_byte *buf;
14010 unsigned long insn;
14011 bfd_boolean use_extend;
14012 unsigned short extend;
14013
14014 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14015 op = mips16_immed_operands;
14016 while (op->type != type)
14017 ++op;
14018
14019 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14020 {
14021 small = FALSE;
14022 ext = TRUE;
14023 }
14024 else
14025 {
14026 small = TRUE;
14027 ext = FALSE;
14028 }
14029
14030 resolve_symbol_value (fragp->fr_symbol);
14031 val = S_GET_VALUE (fragp->fr_symbol);
14032 if (op->pcrel)
14033 {
14034 addressT addr;
14035
14036 addr = fragp->fr_address + fragp->fr_fix;
14037
14038 /* The rules for the base address of a PC relative reloc are
14039 complicated; see mips16_extended_frag. */
14040 if (type == 'p' || type == 'q')
14041 {
14042 addr += 2;
14043 if (ext)
14044 addr += 2;
14045 /* Ignore the low bit in the target, since it will be
14046 set for a text label. */
14047 if ((val & 1) != 0)
14048 --val;
14049 }
14050 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14051 addr -= 4;
14052 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14053 addr -= 2;
14054
14055 addr &= ~ (addressT) ((1 << op->shift) - 1);
14056 val -= addr;
14057
14058 /* Make sure the section winds up with the alignment we have
14059 assumed. */
14060 if (op->shift > 0)
14061 record_alignment (asec, op->shift);
14062 }
14063
14064 if (ext
14065 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14066 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14067 as_warn_where (fragp->fr_file, fragp->fr_line,
14068 _("extended instruction in delay slot"));
14069
14070 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14071
14072 if (target_big_endian)
14073 insn = bfd_getb16 (buf);
14074 else
14075 insn = bfd_getl16 (buf);
14076
14077 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14078 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14079 small, ext, &insn, &use_extend, &extend);
14080
14081 if (use_extend)
14082 {
14083 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14084 fragp->fr_fix += 2;
14085 buf += 2;
14086 }
14087
14088 md_number_to_chars ((char *) buf, insn, 2);
14089 fragp->fr_fix += 2;
14090 buf += 2;
14091 }
14092 else
14093 {
14094 int first, second;
14095 fixS *fixp;
14096
14097 first = RELAX_FIRST (fragp->fr_subtype);
14098 second = RELAX_SECOND (fragp->fr_subtype);
14099 fixp = (fixS *) fragp->fr_opcode;
14100
14101 /* Possibly emit a warning if we've chosen the longer option. */
14102 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14103 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14104 {
14105 const char *msg = macro_warning (fragp->fr_subtype);
14106 if (msg != 0)
14107 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
14108 }
14109
14110 /* Go through all the fixups for the first sequence. Disable them
14111 (by marking them as done) if we're going to use the second
14112 sequence instead. */
14113 while (fixp
14114 && fixp->fx_frag == fragp
14115 && fixp->fx_where < fragp->fr_fix - second)
14116 {
14117 if (fragp->fr_subtype & RELAX_USE_SECOND)
14118 fixp->fx_done = 1;
14119 fixp = fixp->fx_next;
14120 }
14121
14122 /* Go through the fixups for the second sequence. Disable them if
14123 we're going to use the first sequence, otherwise adjust their
14124 addresses to account for the relaxation. */
14125 while (fixp && fixp->fx_frag == fragp)
14126 {
14127 if (fragp->fr_subtype & RELAX_USE_SECOND)
14128 fixp->fx_where -= first;
14129 else
14130 fixp->fx_done = 1;
14131 fixp = fixp->fx_next;
14132 }
14133
14134 /* Now modify the frag contents. */
14135 if (fragp->fr_subtype & RELAX_USE_SECOND)
14136 {
14137 char *start;
14138
14139 start = fragp->fr_literal + fragp->fr_fix - first - second;
14140 memmove (start, start + first, second);
14141 fragp->fr_fix -= first;
14142 }
14143 else
14144 fragp->fr_fix -= second;
14145 }
14146 }
14147
14148 #ifdef OBJ_ELF
14149
14150 /* This function is called after the relocs have been generated.
14151 We've been storing mips16 text labels as odd. Here we convert them
14152 back to even for the convenience of the debugger. */
14153
14154 void
14155 mips_frob_file_after_relocs (void)
14156 {
14157 asymbol **syms;
14158 unsigned int count, i;
14159
14160 if (!IS_ELF)
14161 return;
14162
14163 syms = bfd_get_outsymbols (stdoutput);
14164 count = bfd_get_symcount (stdoutput);
14165 for (i = 0; i < count; i++, syms++)
14166 {
14167 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
14168 && ((*syms)->value & 1) != 0)
14169 {
14170 (*syms)->value &= ~1;
14171 /* If the symbol has an odd size, it was probably computed
14172 incorrectly, so adjust that as well. */
14173 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14174 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14175 }
14176 }
14177 }
14178
14179 #endif
14180
14181 /* This function is called whenever a label is defined. It is used
14182 when handling branch delays; if a branch has a label, we assume we
14183 can not move it. */
14184
14185 void
14186 mips_define_label (symbolS *sym)
14187 {
14188 segment_info_type *si = seg_info (now_seg);
14189 struct insn_label_list *l;
14190
14191 if (free_insn_labels == NULL)
14192 l = (struct insn_label_list *) xmalloc (sizeof *l);
14193 else
14194 {
14195 l = free_insn_labels;
14196 free_insn_labels = l->next;
14197 }
14198
14199 l->label = sym;
14200 l->next = si->label_list;
14201 si->label_list = l;
14202
14203 #ifdef OBJ_ELF
14204 dwarf2_emit_label (sym);
14205 #endif
14206 }
14207 \f
14208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14209
14210 /* Some special processing for a MIPS ELF file. */
14211
14212 void
14213 mips_elf_final_processing (void)
14214 {
14215 /* Write out the register information. */
14216 if (mips_abi != N64_ABI)
14217 {
14218 Elf32_RegInfo s;
14219
14220 s.ri_gprmask = mips_gprmask;
14221 s.ri_cprmask[0] = mips_cprmask[0];
14222 s.ri_cprmask[1] = mips_cprmask[1];
14223 s.ri_cprmask[2] = mips_cprmask[2];
14224 s.ri_cprmask[3] = mips_cprmask[3];
14225 /* The gp_value field is set by the MIPS ELF backend. */
14226
14227 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14228 ((Elf32_External_RegInfo *)
14229 mips_regmask_frag));
14230 }
14231 else
14232 {
14233 Elf64_Internal_RegInfo s;
14234
14235 s.ri_gprmask = mips_gprmask;
14236 s.ri_pad = 0;
14237 s.ri_cprmask[0] = mips_cprmask[0];
14238 s.ri_cprmask[1] = mips_cprmask[1];
14239 s.ri_cprmask[2] = mips_cprmask[2];
14240 s.ri_cprmask[3] = mips_cprmask[3];
14241 /* The gp_value field is set by the MIPS ELF backend. */
14242
14243 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14244 ((Elf64_External_RegInfo *)
14245 mips_regmask_frag));
14246 }
14247
14248 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14249 sort of BFD interface for this. */
14250 if (mips_any_noreorder)
14251 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14252 if (mips_pic != NO_PIC)
14253 {
14254 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14255 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14256 }
14257 if (mips_abicalls)
14258 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14259
14260 /* Set MIPS ELF flags for ASEs. */
14261 /* We may need to define a new flag for DSP ASE, and set this flag when
14262 file_ase_dsp is true. */
14263 /* Same for DSP R2. */
14264 /* We may need to define a new flag for MT ASE, and set this flag when
14265 file_ase_mt is true. */
14266 if (file_ase_mips16)
14267 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14268 #if 0 /* XXX FIXME */
14269 if (file_ase_mips3d)
14270 elf_elfheader (stdoutput)->e_flags |= ???;
14271 #endif
14272 if (file_ase_mdmx)
14273 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14274
14275 /* Set the MIPS ELF ABI flags. */
14276 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14277 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14278 else if (mips_abi == O64_ABI)
14279 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14280 else if (mips_abi == EABI_ABI)
14281 {
14282 if (!file_mips_gp32)
14283 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14284 else
14285 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14286 }
14287 else if (mips_abi == N32_ABI)
14288 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14289
14290 /* Nothing to do for N64_ABI. */
14291
14292 if (mips_32bitmode)
14293 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14294
14295 #if 0 /* XXX FIXME */
14296 /* 32 bit code with 64 bit FP registers. */
14297 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14298 elf_elfheader (stdoutput)->e_flags |= ???;
14299 #endif
14300 }
14301
14302 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14303 \f
14304 typedef struct proc {
14305 symbolS *func_sym;
14306 symbolS *func_end_sym;
14307 unsigned long reg_mask;
14308 unsigned long reg_offset;
14309 unsigned long fpreg_mask;
14310 unsigned long fpreg_offset;
14311 unsigned long frame_offset;
14312 unsigned long frame_reg;
14313 unsigned long pc_reg;
14314 } procS;
14315
14316 static procS cur_proc;
14317 static procS *cur_proc_ptr;
14318 static int numprocs;
14319
14320 /* Fill in an rs_align_code fragment. */
14321
14322 void
14323 mips_handle_align (fragS *fragp)
14324 {
14325 if (fragp->fr_type != rs_align_code)
14326 return;
14327
14328 if (mips_opts.mips16)
14329 {
14330 static const unsigned char be_nop[] = { 0x65, 0x00 };
14331 static const unsigned char le_nop[] = { 0x00, 0x65 };
14332
14333 int bytes;
14334 char *p;
14335
14336 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14337 p = fragp->fr_literal + fragp->fr_fix;
14338
14339 if (bytes & 1)
14340 {
14341 *p++ = 0;
14342 fragp->fr_fix++;
14343 }
14344
14345 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
14346 fragp->fr_var = 2;
14347 }
14348
14349 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14350 }
14351
14352 static void
14353 md_obj_begin (void)
14354 {
14355 }
14356
14357 static void
14358 md_obj_end (void)
14359 {
14360 /* Check for premature end, nesting errors, etc. */
14361 if (cur_proc_ptr)
14362 as_warn (_("missing .end at end of assembly"));
14363 }
14364
14365 static long
14366 get_number (void)
14367 {
14368 int negative = 0;
14369 long val = 0;
14370
14371 if (*input_line_pointer == '-')
14372 {
14373 ++input_line_pointer;
14374 negative = 1;
14375 }
14376 if (!ISDIGIT (*input_line_pointer))
14377 as_bad (_("expected simple number"));
14378 if (input_line_pointer[0] == '0')
14379 {
14380 if (input_line_pointer[1] == 'x')
14381 {
14382 input_line_pointer += 2;
14383 while (ISXDIGIT (*input_line_pointer))
14384 {
14385 val <<= 4;
14386 val |= hex_value (*input_line_pointer++);
14387 }
14388 return negative ? -val : val;
14389 }
14390 else
14391 {
14392 ++input_line_pointer;
14393 while (ISDIGIT (*input_line_pointer))
14394 {
14395 val <<= 3;
14396 val |= *input_line_pointer++ - '0';
14397 }
14398 return negative ? -val : val;
14399 }
14400 }
14401 if (!ISDIGIT (*input_line_pointer))
14402 {
14403 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14404 *input_line_pointer, *input_line_pointer);
14405 as_warn (_("invalid number"));
14406 return -1;
14407 }
14408 while (ISDIGIT (*input_line_pointer))
14409 {
14410 val *= 10;
14411 val += *input_line_pointer++ - '0';
14412 }
14413 return negative ? -val : val;
14414 }
14415
14416 /* The .file directive; just like the usual .file directive, but there
14417 is an initial number which is the ECOFF file index. In the non-ECOFF
14418 case .file implies DWARF-2. */
14419
14420 static void
14421 s_mips_file (int x ATTRIBUTE_UNUSED)
14422 {
14423 static int first_file_directive = 0;
14424
14425 if (ECOFF_DEBUGGING)
14426 {
14427 get_number ();
14428 s_app_file (0);
14429 }
14430 else
14431 {
14432 char *filename;
14433
14434 filename = dwarf2_directive_file (0);
14435
14436 /* Versions of GCC up to 3.1 start files with a ".file"
14437 directive even for stabs output. Make sure that this
14438 ".file" is handled. Note that you need a version of GCC
14439 after 3.1 in order to support DWARF-2 on MIPS. */
14440 if (filename != NULL && ! first_file_directive)
14441 {
14442 (void) new_logical_line (filename, -1);
14443 s_app_file_string (filename, 0);
14444 }
14445 first_file_directive = 1;
14446 }
14447 }
14448
14449 /* The .loc directive, implying DWARF-2. */
14450
14451 static void
14452 s_mips_loc (int x ATTRIBUTE_UNUSED)
14453 {
14454 if (!ECOFF_DEBUGGING)
14455 dwarf2_directive_loc (0);
14456 }
14457
14458 /* The .end directive. */
14459
14460 static void
14461 s_mips_end (int x ATTRIBUTE_UNUSED)
14462 {
14463 symbolS *p;
14464
14465 /* Following functions need their own .frame and .cprestore directives. */
14466 mips_frame_reg_valid = 0;
14467 mips_cprestore_valid = 0;
14468
14469 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14470 {
14471 p = get_symbol ();
14472 demand_empty_rest_of_line ();
14473 }
14474 else
14475 p = NULL;
14476
14477 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14478 as_warn (_(".end not in text section"));
14479
14480 if (!cur_proc_ptr)
14481 {
14482 as_warn (_(".end directive without a preceding .ent directive."));
14483 demand_empty_rest_of_line ();
14484 return;
14485 }
14486
14487 if (p != NULL)
14488 {
14489 assert (S_GET_NAME (p));
14490 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
14491 as_warn (_(".end symbol does not match .ent symbol."));
14492
14493 if (debug_type == DEBUG_STABS)
14494 stabs_generate_asm_endfunc (S_GET_NAME (p),
14495 S_GET_NAME (p));
14496 }
14497 else
14498 as_warn (_(".end directive missing or unknown symbol"));
14499
14500 #ifdef OBJ_ELF
14501 /* Create an expression to calculate the size of the function. */
14502 if (p && cur_proc_ptr)
14503 {
14504 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
14505 expressionS *exp = xmalloc (sizeof (expressionS));
14506
14507 obj->size = exp;
14508 exp->X_op = O_subtract;
14509 exp->X_add_symbol = symbol_temp_new_now ();
14510 exp->X_op_symbol = p;
14511 exp->X_add_number = 0;
14512
14513 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
14514 }
14515
14516 /* Generate a .pdr section. */
14517 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
14518 {
14519 segT saved_seg = now_seg;
14520 subsegT saved_subseg = now_subseg;
14521 valueT dot;
14522 expressionS exp;
14523 char *fragp;
14524
14525 dot = frag_now_fix ();
14526
14527 #ifdef md_flush_pending_output
14528 md_flush_pending_output ();
14529 #endif
14530
14531 assert (pdr_seg);
14532 subseg_set (pdr_seg, 0);
14533
14534 /* Write the symbol. */
14535 exp.X_op = O_symbol;
14536 exp.X_add_symbol = p;
14537 exp.X_add_number = 0;
14538 emit_expr (&exp, 4);
14539
14540 fragp = frag_more (7 * 4);
14541
14542 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14543 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14544 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14545 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14546 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14547 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14548 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14549
14550 subseg_set (saved_seg, saved_subseg);
14551 }
14552 #endif /* OBJ_ELF */
14553
14554 cur_proc_ptr = NULL;
14555 }
14556
14557 /* The .aent and .ent directives. */
14558
14559 static void
14560 s_mips_ent (int aent)
14561 {
14562 symbolS *symbolP;
14563
14564 symbolP = get_symbol ();
14565 if (*input_line_pointer == ',')
14566 ++input_line_pointer;
14567 SKIP_WHITESPACE ();
14568 if (ISDIGIT (*input_line_pointer)
14569 || *input_line_pointer == '-')
14570 get_number ();
14571
14572 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14573 as_warn (_(".ent or .aent not in text section."));
14574
14575 if (!aent && cur_proc_ptr)
14576 as_warn (_("missing .end"));
14577
14578 if (!aent)
14579 {
14580 /* This function needs its own .frame and .cprestore directives. */
14581 mips_frame_reg_valid = 0;
14582 mips_cprestore_valid = 0;
14583
14584 cur_proc_ptr = &cur_proc;
14585 memset (cur_proc_ptr, '\0', sizeof (procS));
14586
14587 cur_proc_ptr->func_sym = symbolP;
14588
14589 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14590
14591 ++numprocs;
14592
14593 if (debug_type == DEBUG_STABS)
14594 stabs_generate_asm_func (S_GET_NAME (symbolP),
14595 S_GET_NAME (symbolP));
14596 }
14597
14598 demand_empty_rest_of_line ();
14599 }
14600
14601 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14602 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14603 s_mips_frame is used so that we can set the PDR information correctly.
14604 We can't use the ecoff routines because they make reference to the ecoff
14605 symbol table (in the mdebug section). */
14606
14607 static void
14608 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14609 {
14610 #ifdef OBJ_ELF
14611 if (IS_ELF && !ECOFF_DEBUGGING)
14612 {
14613 long val;
14614
14615 if (cur_proc_ptr == (procS *) NULL)
14616 {
14617 as_warn (_(".frame outside of .ent"));
14618 demand_empty_rest_of_line ();
14619 return;
14620 }
14621
14622 cur_proc_ptr->frame_reg = tc_get_register (1);
14623
14624 SKIP_WHITESPACE ();
14625 if (*input_line_pointer++ != ','
14626 || get_absolute_expression_and_terminator (&val) != ',')
14627 {
14628 as_warn (_("Bad .frame directive"));
14629 --input_line_pointer;
14630 demand_empty_rest_of_line ();
14631 return;
14632 }
14633
14634 cur_proc_ptr->frame_offset = val;
14635 cur_proc_ptr->pc_reg = tc_get_register (0);
14636
14637 demand_empty_rest_of_line ();
14638 }
14639 else
14640 #endif /* OBJ_ELF */
14641 s_ignore (ignore);
14642 }
14643
14644 /* The .fmask and .mask directives. If the mdebug section is present
14645 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14646 embedded targets, s_mips_mask is used so that we can set the PDR
14647 information correctly. We can't use the ecoff routines because they
14648 make reference to the ecoff symbol table (in the mdebug section). */
14649
14650 static void
14651 s_mips_mask (int reg_type)
14652 {
14653 #ifdef OBJ_ELF
14654 if (IS_ELF && !ECOFF_DEBUGGING)
14655 {
14656 long mask, off;
14657
14658 if (cur_proc_ptr == (procS *) NULL)
14659 {
14660 as_warn (_(".mask/.fmask outside of .ent"));
14661 demand_empty_rest_of_line ();
14662 return;
14663 }
14664
14665 if (get_absolute_expression_and_terminator (&mask) != ',')
14666 {
14667 as_warn (_("Bad .mask/.fmask directive"));
14668 --input_line_pointer;
14669 demand_empty_rest_of_line ();
14670 return;
14671 }
14672
14673 off = get_absolute_expression ();
14674
14675 if (reg_type == 'F')
14676 {
14677 cur_proc_ptr->fpreg_mask = mask;
14678 cur_proc_ptr->fpreg_offset = off;
14679 }
14680 else
14681 {
14682 cur_proc_ptr->reg_mask = mask;
14683 cur_proc_ptr->reg_offset = off;
14684 }
14685
14686 demand_empty_rest_of_line ();
14687 }
14688 else
14689 #endif /* OBJ_ELF */
14690 s_ignore (reg_type);
14691 }
14692
14693 /* A table describing all the processors gas knows about. Names are
14694 matched in the order listed.
14695
14696 To ease comparison, please keep this table in the same order as
14697 gcc's mips_cpu_info_table[]. */
14698 static const struct mips_cpu_info mips_cpu_info_table[] =
14699 {
14700 /* Entries for generic ISAs */
14701 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
14702 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
14703 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
14704 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
14705 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
14706 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
14707 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
14708 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
14709 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
14710
14711 /* MIPS I */
14712 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14713 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14714 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14715
14716 /* MIPS II */
14717 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14718
14719 /* MIPS III */
14720 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14721 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14722 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14723 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14724 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14725 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14726 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14727 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14728 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14729 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14730 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14731 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14732
14733 /* MIPS IV */
14734 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14735 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14736 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14737 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14738 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14739 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14740 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14741 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14742 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14743 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14744 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14745 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14746 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
14747
14748 /* MIPS 32 */
14749 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14750 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14751 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14752 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
14753
14754 /* MIPS 32 Release 2 */
14755 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14756 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14757 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14758 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
14759 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14760 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14761 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14762 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14763 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14764 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14765 /* Deprecated forms of the above. */
14766 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14767 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14768 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
14769 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14770 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14771 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14772 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14773 /* Deprecated forms of the above. */
14774 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14775 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
14776 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
14777 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
14778 ISA_MIPS32R2, CPU_MIPS32R2 },
14779 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
14780 ISA_MIPS32R2, CPU_MIPS32R2 },
14781 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
14782 ISA_MIPS32R2, CPU_MIPS32R2 },
14783 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
14784 ISA_MIPS32R2, CPU_MIPS32R2 },
14785 /* Deprecated forms of the above. */
14786 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
14787 ISA_MIPS32R2, CPU_MIPS32R2 },
14788 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
14789 ISA_MIPS32R2, CPU_MIPS32R2 },
14790 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
14791 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14792 ISA_MIPS32R2, CPU_MIPS32R2 },
14793 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14794 ISA_MIPS32R2, CPU_MIPS32R2 },
14795 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14796 ISA_MIPS32R2, CPU_MIPS32R2 },
14797 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14798 ISA_MIPS32R2, CPU_MIPS32R2 },
14799 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14800 ISA_MIPS32R2, CPU_MIPS32R2 },
14801 /* Deprecated forms of the above. */
14802 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14803 ISA_MIPS32R2, CPU_MIPS32R2 },
14804 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
14805 ISA_MIPS32R2, CPU_MIPS32R2 },
14806
14807 /* MIPS 64 */
14808 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14809 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
14810 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
14811 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
14812
14813 /* MIPS 64 Release 2 */
14814
14815 /* Broadcom SB-1 CPU core */
14816 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
14817 ISA_MIPS64, CPU_SB1 },
14818 /* Broadcom SB-1A CPU core */
14819 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
14820 ISA_MIPS64, CPU_SB1 },
14821
14822 /* End marker */
14823 { NULL, 0, 0, 0 }
14824 };
14825
14826
14827 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14828 with a final "000" replaced by "k". Ignore case.
14829
14830 Note: this function is shared between GCC and GAS. */
14831
14832 static bfd_boolean
14833 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14834 {
14835 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14836 given++, canonical++;
14837
14838 return ((*given == 0 && *canonical == 0)
14839 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14840 }
14841
14842
14843 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14844 CPU name. We've traditionally allowed a lot of variation here.
14845
14846 Note: this function is shared between GCC and GAS. */
14847
14848 static bfd_boolean
14849 mips_matching_cpu_name_p (const char *canonical, const char *given)
14850 {
14851 /* First see if the name matches exactly, or with a final "000"
14852 turned into "k". */
14853 if (mips_strict_matching_cpu_name_p (canonical, given))
14854 return TRUE;
14855
14856 /* If not, try comparing based on numerical designation alone.
14857 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14858 if (TOLOWER (*given) == 'r')
14859 given++;
14860 if (!ISDIGIT (*given))
14861 return FALSE;
14862
14863 /* Skip over some well-known prefixes in the canonical name,
14864 hoping to find a number there too. */
14865 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14866 canonical += 2;
14867 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14868 canonical += 2;
14869 else if (TOLOWER (canonical[0]) == 'r')
14870 canonical += 1;
14871
14872 return mips_strict_matching_cpu_name_p (canonical, given);
14873 }
14874
14875
14876 /* Parse an option that takes the name of a processor as its argument.
14877 OPTION is the name of the option and CPU_STRING is the argument.
14878 Return the corresponding processor enumeration if the CPU_STRING is
14879 recognized, otherwise report an error and return null.
14880
14881 A similar function exists in GCC. */
14882
14883 static const struct mips_cpu_info *
14884 mips_parse_cpu (const char *option, const char *cpu_string)
14885 {
14886 const struct mips_cpu_info *p;
14887
14888 /* 'from-abi' selects the most compatible architecture for the given
14889 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14890 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14891 version. Look first at the -mgp options, if given, otherwise base
14892 the choice on MIPS_DEFAULT_64BIT.
14893
14894 Treat NO_ABI like the EABIs. One reason to do this is that the
14895 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14896 architecture. This code picks MIPS I for 'mips' and MIPS III for
14897 'mips64', just as we did in the days before 'from-abi'. */
14898 if (strcasecmp (cpu_string, "from-abi") == 0)
14899 {
14900 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14901 return mips_cpu_info_from_isa (ISA_MIPS1);
14902
14903 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14904 return mips_cpu_info_from_isa (ISA_MIPS3);
14905
14906 if (file_mips_gp32 >= 0)
14907 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14908
14909 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14910 ? ISA_MIPS3
14911 : ISA_MIPS1);
14912 }
14913
14914 /* 'default' has traditionally been a no-op. Probably not very useful. */
14915 if (strcasecmp (cpu_string, "default") == 0)
14916 return 0;
14917
14918 for (p = mips_cpu_info_table; p->name != 0; p++)
14919 if (mips_matching_cpu_name_p (p->name, cpu_string))
14920 return p;
14921
14922 as_bad ("Bad value (%s) for %s", cpu_string, option);
14923 return 0;
14924 }
14925
14926 /* Return the canonical processor information for ISA (a member of the
14927 ISA_MIPS* enumeration). */
14928
14929 static const struct mips_cpu_info *
14930 mips_cpu_info_from_isa (int isa)
14931 {
14932 int i;
14933
14934 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14935 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
14936 && isa == mips_cpu_info_table[i].isa)
14937 return (&mips_cpu_info_table[i]);
14938
14939 return NULL;
14940 }
14941
14942 static const struct mips_cpu_info *
14943 mips_cpu_info_from_arch (int arch)
14944 {
14945 int i;
14946
14947 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14948 if (arch == mips_cpu_info_table[i].cpu)
14949 return (&mips_cpu_info_table[i]);
14950
14951 return NULL;
14952 }
14953 \f
14954 static void
14955 show (FILE *stream, const char *string, int *col_p, int *first_p)
14956 {
14957 if (*first_p)
14958 {
14959 fprintf (stream, "%24s", "");
14960 *col_p = 24;
14961 }
14962 else
14963 {
14964 fprintf (stream, ", ");
14965 *col_p += 2;
14966 }
14967
14968 if (*col_p + strlen (string) > 72)
14969 {
14970 fprintf (stream, "\n%24s", "");
14971 *col_p = 24;
14972 }
14973
14974 fprintf (stream, "%s", string);
14975 *col_p += strlen (string);
14976
14977 *first_p = 0;
14978 }
14979
14980 void
14981 md_show_usage (FILE *stream)
14982 {
14983 int column, first;
14984 size_t i;
14985
14986 fprintf (stream, _("\
14987 MIPS options:\n\
14988 -EB generate big endian output\n\
14989 -EL generate little endian output\n\
14990 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14991 -G NUM allow referencing objects up to NUM bytes\n\
14992 implicitly with the gp register [default 8]\n"));
14993 fprintf (stream, _("\
14994 -mips1 generate MIPS ISA I instructions\n\
14995 -mips2 generate MIPS ISA II instructions\n\
14996 -mips3 generate MIPS ISA III instructions\n\
14997 -mips4 generate MIPS ISA IV instructions\n\
14998 -mips5 generate MIPS ISA V instructions\n\
14999 -mips32 generate MIPS32 ISA instructions\n\
15000 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15001 -mips64 generate MIPS64 ISA instructions\n\
15002 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15003 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15004
15005 first = 1;
15006
15007 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15008 show (stream, mips_cpu_info_table[i].name, &column, &first);
15009 show (stream, "from-abi", &column, &first);
15010 fputc ('\n', stream);
15011
15012 fprintf (stream, _("\
15013 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15014 -no-mCPU don't generate code specific to CPU.\n\
15015 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15016
15017 first = 1;
15018
15019 show (stream, "3900", &column, &first);
15020 show (stream, "4010", &column, &first);
15021 show (stream, "4100", &column, &first);
15022 show (stream, "4650", &column, &first);
15023 fputc ('\n', stream);
15024
15025 fprintf (stream, _("\
15026 -mips16 generate mips16 instructions\n\
15027 -no-mips16 do not generate mips16 instructions\n"));
15028 fprintf (stream, _("\
15029 -msmartmips generate smartmips instructions\n\
15030 -mno-smartmips do not generate smartmips instructions\n"));
15031 fprintf (stream, _("\
15032 -mdsp generate DSP instructions\n\
15033 -mno-dsp do not generate DSP instructions\n"));
15034 fprintf (stream, _("\
15035 -mdspr2 generate DSP R2 instructions\n\
15036 -mno-dspr2 do not generate DSP R2 instructions\n"));
15037 fprintf (stream, _("\
15038 -mmt generate MT instructions\n\
15039 -mno-mt do not generate MT instructions\n"));
15040 fprintf (stream, _("\
15041 -mfix-vr4120 work around certain VR4120 errata\n\
15042 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15043 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15044 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15045 -msym32 assume all symbols have 32-bit values\n\
15046 -O0 remove unneeded NOPs, do not swap branches\n\
15047 -O remove unneeded NOPs and swap branches\n\
15048 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
15049 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15050 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15051 #ifdef OBJ_ELF
15052 fprintf (stream, _("\
15053 -KPIC, -call_shared generate SVR4 position independent code\n\
15054 -mvxworks-pic generate VxWorks position independent code\n\
15055 -non_shared do not generate position independent code\n\
15056 -xgot assume a 32 bit GOT\n\
15057 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15058 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15059 position dependent (non shared) code\n\
15060 -mabi=ABI create ABI conformant object file for:\n"));
15061
15062 first = 1;
15063
15064 show (stream, "32", &column, &first);
15065 show (stream, "o64", &column, &first);
15066 show (stream, "n32", &column, &first);
15067 show (stream, "64", &column, &first);
15068 show (stream, "eabi", &column, &first);
15069
15070 fputc ('\n', stream);
15071
15072 fprintf (stream, _("\
15073 -32 create o32 ABI object file (default)\n\
15074 -n32 create n32 ABI object file\n\
15075 -64 create 64 ABI object file\n"));
15076 #endif
15077 }
15078
15079 enum dwarf2_format
15080 mips_dwarf2_format (void)
15081 {
15082 if (HAVE_64BIT_SYMBOLS)
15083 {
15084 #ifdef TE_IRIX
15085 return dwarf2_format_64bit_irix;
15086 #else
15087 return dwarf2_format_64bit;
15088 #endif
15089 }
15090 else
15091 return dwarf2_format_32bit;
15092 }
15093
15094 int
15095 mips_dwarf2_addr_size (void)
15096 {
15097 if (HAVE_64BIT_SYMBOLS)
15098 return 8;
15099 else
15100 return 4;
15101 }
15102
15103 /* Standard calling conventions leave the CFA at SP on entry. */
15104 void
15105 mips_cfi_frame_initial_instructions (void)
15106 {
15107 cfi_add_CFA_def_cfa_register (SP);
15108 }
15109
15110 int
15111 tc_mips_regname_to_dw2regnum (char *regname)
15112 {
15113 unsigned int regnum = -1;
15114 unsigned int reg;
15115
15116 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
15117 regnum = reg;
15118
15119 return regnum;
15120 }
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