1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* This is the set of options which may be modified by the .set
117 pseudo-op. We use a struct so that .set push and .set pop are more
120 struct mips_set_options
122 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
123 if it has not been initialized. Changed by `.set mipsN', and the
124 -mipsN command line option, and the default CPU. */
126 /* Whether we are assembling for the mips16 processor. 0 if we are
127 not, 1 if we are, and -1 if the value has not been initialized.
128 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
129 -nomips16 command line options, and the default CPU. */
131 /* Non-zero if we should not reorder instructions. Changed by `.set
132 reorder' and `.set noreorder'. */
134 /* Non-zero if we should not permit the $at ($1) register to be used
135 in instructions. Changed by `.set at' and `.set noat'. */
137 /* Non-zero if we should warn when a macro instruction expands into
138 more than one machine instruction. Changed by `.set nomacro' and
140 int warn_about_macros
;
141 /* Non-zero if we should not move instructions. Changed by `.set
142 move', `.set volatile', `.set nomove', and `.set novolatile'. */
144 /* Non-zero if we should not optimize branches by moving the target
145 of the branch into the delay slot. Actually, we don't perform
146 this optimization anyhow. Changed by `.set bopt' and `.set
149 /* Non-zero if we should not autoextend mips16 instructions.
150 Changed by `.set autoextend' and `.set noautoextend'. */
154 /* This is the struct we use to hold the current set of options. Note
155 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
156 -1 to indicate that they have not been initialized. */
158 static struct mips_set_options mips_opts
=
160 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
163 /* These variables are filled in with the masks of registers used.
164 The object format code reads them and puts them in the appropriate
166 unsigned long mips_gprmask
;
167 unsigned long mips_cprmask
[4];
169 /* MIPS ISA we are using for this output file. */
170 static int file_mips_isa
= ISA_UNKNOWN
;
172 /* The argument of the -mcpu= flag. Historical for code generation. */
173 static int mips_cpu
= CPU_UNKNOWN
;
175 /* The argument of the -march= flag. The architecture we are assembling. */
176 static int mips_arch
= CPU_UNKNOWN
;
178 /* The argument of the -mtune= flag. The architecture for which we
180 static int mips_tune
= CPU_UNKNOWN
;
182 /* The ABI to use. */
193 static enum mips_abi_level mips_abi
= NO_ABI
;
195 /* Whether we should mark the file EABI64 or EABI32. */
196 static int mips_eabi64
= 0;
198 /* If they asked for mips1 or mips2 and a cpu that is
199 mips3 or greater, then mark the object file 32BITMODE. */
200 static int mips_32bitmode
= 0;
202 /* True if -mgp32 was passed. */
203 static int mips_gp32
= 0;
205 /* True if -mfp32 was passed. */
206 static int mips_fp32
= 0;
208 /* Some ISA's have delay slots for instructions which read or write
209 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
210 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
211 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
212 delay slot in this ISA. The uses of this macro assume that any
213 ISA that has delay slots for one of these, has them for all. They
214 also assume that ISAs which don't have delays for these insns, don't
215 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
216 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
218 || (ISA) == ISA_MIPS2 \
219 || (ISA) == ISA_MIPS3 \
222 /* Return true if ISA supports 64 bit gp register instructions. */
223 #define ISA_HAS_64BIT_REGS(ISA) ( \
225 || (ISA) == ISA_MIPS4 \
226 || (ISA) == ISA_MIPS5 \
227 || (ISA) == ISA_MIPS64 \
230 #define HAVE_32BIT_GPRS \
232 || mips_abi == O32_ABI \
233 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
235 #define HAVE_32BIT_FPRS \
237 || mips_abi == O32_ABI \
238 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
240 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
241 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
243 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
245 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
247 /* We can only have 64bit addresses if the object file format
249 #define HAVE_32BIT_ADDRESSES \
251 || bfd_arch_bits_per_address (stdoutput) == 32 \
252 || ! HAVE_64BIT_OBJECTS)
254 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
256 /* Whether the processor uses hardware interlocks to protect
257 reads from the HI and LO registers, and thus does not
258 require nops to be inserted. */
260 #define hilo_interlocks (mips_arch == CPU_R4010 \
263 /* Whether the processor uses hardware interlocks to protect reads
264 from the GPRs, and thus does not require nops to be inserted. */
265 #define gpr_interlocks \
266 (mips_opts.isa != ISA_MIPS1 \
267 || mips_arch == CPU_R3900)
269 /* As with other "interlocks" this is used by hardware that has FP
270 (co-processor) interlocks. */
271 /* Itbl support may require additional care here. */
272 #define cop_interlocks (mips_arch == CPU_R4300 \
275 /* Is this a mfhi or mflo instruction? */
276 #define MF_HILO_INSN(PINFO) \
277 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
279 /* MIPS PIC level. */
283 /* Do not generate PIC code. */
286 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
287 not sure what it is supposed to do. */
290 /* Generate PIC code as in the SVR4 MIPS ABI. */
293 /* Generate PIC code without using a global offset table: the data
294 segment has a maximum size of 64K, all data references are off
295 the $gp register, and all text references are PC relative. This
296 is used on some embedded systems. */
300 static enum mips_pic_level mips_pic
;
302 /* Warn about all NOPS that the assembler generates. */
303 static int warn_nops
= 0;
305 /* 1 if we should generate 32 bit offsets from the GP register in
306 SVR4_PIC mode. Currently has no meaning in other modes. */
307 static int mips_big_got
;
309 /* 1 if trap instructions should used for overflow rather than break
311 static int mips_trap
;
313 /* 1 if double width floating point constants should not be constructed
314 by a assembling two single width halves into two single width floating
315 point registers which just happen to alias the double width destination
316 register. On some architectures this aliasing can be disabled by a bit
317 in the status register, and the setting of this bit cannot be determined
318 automatically at assemble time. */
319 static int mips_disable_float_construction
;
321 /* Non-zero if any .set noreorder directives were used. */
323 static int mips_any_noreorder
;
325 /* Non-zero if nops should be inserted when the register referenced in
326 an mfhi/mflo instruction is read in the next two instructions. */
327 static int mips_7000_hilo_fix
;
329 /* The size of the small data section. */
330 static unsigned int g_switch_value
= 8;
331 /* Whether the -G option was used. */
332 static int g_switch_seen
= 0;
337 /* If we can determine in advance that GP optimization won't be
338 possible, we can skip the relaxation stuff that tries to produce
339 GP-relative references. This makes delay slot optimization work
342 This function can only provide a guess, but it seems to work for
343 gcc output. It needs to guess right for gcc, otherwise gcc
344 will put what it thinks is a GP-relative instruction in a branch
347 I don't know if a fix is needed for the SVR4_PIC mode. I've only
348 fixed it for the non-PIC mode. KR 95/04/07 */
349 static int nopic_need_relax
PARAMS ((symbolS
*, int));
351 /* handle of the OPCODE hash table */
352 static struct hash_control
*op_hash
= NULL
;
354 /* The opcode hash table we use for the mips16. */
355 static struct hash_control
*mips16_op_hash
= NULL
;
357 /* This array holds the chars that always start a comment. If the
358 pre-processor is disabled, these aren't very useful */
359 const char comment_chars
[] = "#";
361 /* This array holds the chars that only start a comment at the beginning of
362 a line. If the line seems to have the form '# 123 filename'
363 .line and .file directives will appear in the pre-processed output */
364 /* Note that input_file.c hand checks for '#' at the beginning of the
365 first line of the input file. This is because the compiler outputs
366 #NO_APP at the beginning of its output. */
367 /* Also note that C style comments are always supported. */
368 const char line_comment_chars
[] = "#";
370 /* This array holds machine specific line separator characters. */
371 const char line_separator_chars
[] = ";";
373 /* Chars that can be used to separate mant from exp in floating point nums */
374 const char EXP_CHARS
[] = "eE";
376 /* Chars that mean this number is a floating point constant */
379 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
381 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
382 changed in read.c . Ideally it shouldn't have to know about it at all,
383 but nothing is ideal around here.
386 static char *insn_error
;
388 static int auto_align
= 1;
390 /* When outputting SVR4 PIC code, the assembler needs to know the
391 offset in the stack frame from which to restore the $gp register.
392 This is set by the .cprestore pseudo-op, and saved in this
394 static offsetT mips_cprestore_offset
= -1;
396 /* This is the register which holds the stack frame, as set by the
397 .frame pseudo-op. This is needed to implement .cprestore. */
398 static int mips_frame_reg
= SP
;
400 /* To output NOP instructions correctly, we need to keep information
401 about the previous two instructions. */
403 /* Whether we are optimizing. The default value of 2 means to remove
404 unneeded NOPs and swap branch instructions when possible. A value
405 of 1 means to not swap branches. A value of 0 means to always
407 static int mips_optimize
= 2;
409 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
410 equivalent to seeing no -g option at all. */
411 static int mips_debug
= 0;
413 /* The previous instruction. */
414 static struct mips_cl_insn prev_insn
;
416 /* The instruction before prev_insn. */
417 static struct mips_cl_insn prev_prev_insn
;
419 /* If we don't want information for prev_insn or prev_prev_insn, we
420 point the insn_mo field at this dummy integer. */
421 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
423 /* Non-zero if prev_insn is valid. */
424 static int prev_insn_valid
;
426 /* The frag for the previous instruction. */
427 static struct frag
*prev_insn_frag
;
429 /* The offset into prev_insn_frag for the previous instruction. */
430 static long prev_insn_where
;
432 /* The reloc type for the previous instruction, if any. */
433 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
435 /* The reloc for the previous instruction, if any. */
436 static fixS
*prev_insn_fixp
[3];
438 /* Non-zero if the previous instruction was in a delay slot. */
439 static int prev_insn_is_delay_slot
;
441 /* Non-zero if the previous instruction was in a .set noreorder. */
442 static int prev_insn_unreordered
;
444 /* Non-zero if the previous instruction uses an extend opcode (if
446 static int prev_insn_extended
;
448 /* Non-zero if the previous previous instruction was in a .set
450 static int prev_prev_insn_unreordered
;
452 /* If this is set, it points to a frag holding nop instructions which
453 were inserted before the start of a noreorder section. If those
454 nops turn out to be unnecessary, the size of the frag can be
456 static fragS
*prev_nop_frag
;
458 /* The number of nop instructions we created in prev_nop_frag. */
459 static int prev_nop_frag_holds
;
461 /* The number of nop instructions that we know we need in
463 static int prev_nop_frag_required
;
465 /* The number of instructions we've seen since prev_nop_frag. */
466 static int prev_nop_frag_since
;
468 /* For ECOFF and ELF, relocations against symbols are done in two
469 parts, with a HI relocation and a LO relocation. Each relocation
470 has only 16 bits of space to store an addend. This means that in
471 order for the linker to handle carries correctly, it must be able
472 to locate both the HI and the LO relocation. This means that the
473 relocations must appear in order in the relocation table.
475 In order to implement this, we keep track of each unmatched HI
476 relocation. We then sort them so that they immediately precede the
477 corresponding LO relocation. */
482 struct mips_hi_fixup
*next
;
485 /* The section this fixup is in. */
489 /* The list of unmatched HI relocs. */
491 static struct mips_hi_fixup
*mips_hi_fixup_list
;
493 /* Map normal MIPS register numbers to mips16 register numbers. */
495 #define X ILLEGAL_REG
496 static const int mips32_to_16_reg_map
[] =
498 X
, X
, 2, 3, 4, 5, 6, 7,
499 X
, X
, X
, X
, X
, X
, X
, X
,
500 0, 1, X
, X
, X
, X
, X
, X
,
501 X
, X
, X
, X
, X
, X
, X
, X
505 /* Map mips16 register numbers to normal MIPS register numbers. */
507 static const unsigned int mips16_to_32_reg_map
[] =
509 16, 17, 2, 3, 4, 5, 6, 7
512 /* Since the MIPS does not have multiple forms of PC relative
513 instructions, we do not have to do relaxing as is done on other
514 platforms. However, we do have to handle GP relative addressing
515 correctly, which turns out to be a similar problem.
517 Every macro that refers to a symbol can occur in (at least) two
518 forms, one with GP relative addressing and one without. For
519 example, loading a global variable into a register generally uses
520 a macro instruction like this:
522 If i can be addressed off the GP register (this is true if it is in
523 the .sbss or .sdata section, or if it is known to be smaller than
524 the -G argument) this will generate the following instruction:
526 This instruction will use a GPREL reloc. If i can not be addressed
527 off the GP register, the following instruction sequence will be used:
530 In this case the first instruction will have a HI16 reloc, and the
531 second reloc will have a LO16 reloc. Both relocs will be against
534 The issue here is that we may not know whether i is GP addressable
535 until after we see the instruction that uses it. Therefore, we
536 want to be able to choose the final instruction sequence only at
537 the end of the assembly. This is similar to the way other
538 platforms choose the size of a PC relative instruction only at the
541 When generating position independent code we do not use GP
542 addressing in quite the same way, but the issue still arises as
543 external symbols and local symbols must be handled differently.
545 We handle these issues by actually generating both possible
546 instruction sequences. The longer one is put in a frag_var with
547 type rs_machine_dependent. We encode what to do with the frag in
548 the subtype field. We encode (1) the number of existing bytes to
549 replace, (2) the number of new bytes to use, (3) the offset from
550 the start of the existing bytes to the first reloc we must generate
551 (that is, the offset is applied from the start of the existing
552 bytes after they are replaced by the new bytes, if any), (4) the
553 offset from the start of the existing bytes to the second reloc,
554 (5) whether a third reloc is needed (the third reloc is always four
555 bytes after the second reloc), and (6) whether to warn if this
556 variant is used (this is sometimes needed if .set nomacro or .set
557 noat is in effect). All these numbers are reasonably small.
559 Generating two instruction sequences must be handled carefully to
560 ensure that delay slots are handled correctly. Fortunately, there
561 are a limited number of cases. When the second instruction
562 sequence is generated, append_insn is directed to maintain the
563 existing delay slot information, so it continues to apply to any
564 code after the second instruction sequence. This means that the
565 second instruction sequence must not impose any requirements not
566 required by the first instruction sequence.
568 These variant frags are then handled in functions called by the
569 machine independent code. md_estimate_size_before_relax returns
570 the final size of the frag. md_convert_frag sets up the final form
571 of the frag. tc_gen_reloc adjust the first reloc and adds a second
573 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
577 | (((reloc1) + 64) << 9) \
578 | (((reloc2) + 64) << 2) \
579 | ((reloc3) ? (1 << 1) : 0) \
581 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
582 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
583 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
584 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
585 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
586 #define RELAX_WARN(i) ((i) & 1)
588 /* For mips16 code, we use an entirely different form of relaxation.
589 mips16 supports two versions of most instructions which take
590 immediate values: a small one which takes some small value, and a
591 larger one which takes a 16 bit value. Since branches also follow
592 this pattern, relaxing these values is required.
594 We can assemble both mips16 and normal MIPS code in a single
595 object. Therefore, we need to support this type of relaxation at
596 the same time that we support the relaxation described above. We
597 use the high bit of the subtype field to distinguish these cases.
599 The information we store for this type of relaxation is the
600 argument code found in the opcode file for this relocation, whether
601 the user explicitly requested a small or extended form, and whether
602 the relocation is in a jump or jal delay slot. That tells us the
603 size of the value, and how it should be stored. We also store
604 whether the fragment is considered to be extended or not. We also
605 store whether this is known to be a branch to a different section,
606 whether we have tried to relax this frag yet, and whether we have
607 ever extended a PC relative fragment because of a shift count. */
608 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
611 | ((small) ? 0x100 : 0) \
612 | ((ext) ? 0x200 : 0) \
613 | ((dslot) ? 0x400 : 0) \
614 | ((jal_dslot) ? 0x800 : 0))
615 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
616 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
617 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
618 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
619 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
620 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
621 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
622 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
623 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
624 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
625 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
626 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
628 /* Prototypes for static functions. */
631 #define internalError() \
632 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
634 #define internalError() as_fatal (_("MIPS internal Error"));
637 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
639 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
640 unsigned int reg
, enum mips_regclass
class));
641 static int reg_needs_delay
PARAMS ((unsigned int));
642 static void mips16_mark_labels
PARAMS ((void));
643 static void append_insn
PARAMS ((char *place
,
644 struct mips_cl_insn
* ip
,
646 bfd_reloc_code_real_type
*r
,
648 static void mips_no_prev_insn
PARAMS ((int));
649 static void mips_emit_delays
PARAMS ((boolean
));
651 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
652 const char *name
, const char *fmt
,
655 static void macro_build ();
657 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
658 const char *, const char *,
660 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
661 expressionS
* ep
, int regnum
));
662 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
663 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
665 static void load_register
PARAMS ((int *, int, expressionS
*, int));
666 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
667 static void move_register
PARAMS ((int *, int, int));
668 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
669 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
670 #ifdef LOSING_COMPILER
671 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
673 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
674 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
675 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
676 boolean
, boolean
, unsigned long *,
677 boolean
*, unsigned short *));
678 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
679 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
680 static int support_64bit_objects
PARAMS((void));
681 static symbolS
*get_symbol
PARAMS ((void));
682 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
683 static void s_align
PARAMS ((int));
684 static void s_change_sec
PARAMS ((int));
685 static void s_cons
PARAMS ((int));
686 static void s_float_cons
PARAMS ((int));
687 static void s_mips_globl
PARAMS ((int));
688 static void s_option
PARAMS ((int));
689 static void s_mipsset
PARAMS ((int));
690 static void s_abicalls
PARAMS ((int));
691 static void s_cpload
PARAMS ((int));
692 static void s_cprestore
PARAMS ((int));
693 static void s_gpword
PARAMS ((int));
694 static void s_cpadd
PARAMS ((int));
695 static void s_insn
PARAMS ((int));
696 static void md_obj_begin
PARAMS ((void));
697 static void md_obj_end
PARAMS ((void));
698 static long get_number
PARAMS ((void));
699 static void s_mips_ent
PARAMS ((int));
700 static void s_mips_end
PARAMS ((int));
701 static void s_mips_frame
PARAMS ((int));
702 static void s_mips_mask
PARAMS ((int));
703 static void s_mips_stab
PARAMS ((int));
704 static void s_mips_weakext
PARAMS ((int));
705 static void s_file
PARAMS ((int));
706 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
707 static const char *mips_isa_to_str
PARAMS ((int));
708 static const char *mips_cpu_to_str
PARAMS ((int));
709 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
710 static void show
PARAMS ((FILE *, char *, int *, int *));
712 /* Return values of my_getSmallExpression() */
725 /* Table and functions used to map between CPU/ISA names, and
726 ISA levels, and CPU numbers. */
730 const char *name
; /* CPU or ISA name. */
731 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
732 int isa
; /* ISA level. */
733 int cpu
; /* CPU number (default CPU if ISA). */
736 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
737 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
738 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
742 The following pseudo-ops from the Kane and Heinrich MIPS book
743 should be defined here, but are currently unsupported: .alias,
744 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
746 The following pseudo-ops from the Kane and Heinrich MIPS book are
747 specific to the type of debugging information being generated, and
748 should be defined by the object format: .aent, .begin, .bend,
749 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
752 The following pseudo-ops from the Kane and Heinrich MIPS book are
753 not MIPS CPU specific, but are also not specific to the object file
754 format. This file is probably the best place to define them, but
755 they are not currently supported: .asm0, .endr, .lab, .repeat,
758 static const pseudo_typeS mips_pseudo_table
[] =
760 /* MIPS specific pseudo-ops. */
761 {"option", s_option
, 0},
762 {"set", s_mipsset
, 0},
763 {"rdata", s_change_sec
, 'r'},
764 {"sdata", s_change_sec
, 's'},
765 {"livereg", s_ignore
, 0},
766 {"abicalls", s_abicalls
, 0},
767 {"cpload", s_cpload
, 0},
768 {"cprestore", s_cprestore
, 0},
769 {"gpword", s_gpword
, 0},
770 {"cpadd", s_cpadd
, 0},
773 /* Relatively generic pseudo-ops that happen to be used on MIPS
775 {"asciiz", stringer
, 1},
776 {"bss", s_change_sec
, 'b'},
779 {"dword", s_cons
, 3},
780 {"weakext", s_mips_weakext
, 0},
782 /* These pseudo-ops are defined in read.c, but must be overridden
783 here for one reason or another. */
784 {"align", s_align
, 0},
786 {"data", s_change_sec
, 'd'},
787 {"double", s_float_cons
, 'd'},
788 {"float", s_float_cons
, 'f'},
789 {"globl", s_mips_globl
, 0},
790 {"global", s_mips_globl
, 0},
791 {"hword", s_cons
, 1},
796 {"short", s_cons
, 1},
797 {"single", s_float_cons
, 'f'},
798 {"stabn", s_mips_stab
, 'n'},
799 {"text", s_change_sec
, 't'},
802 #ifdef MIPS_STABS_ELF
803 { "extern", ecoff_directive_extern
, 0},
809 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
811 /* These pseudo-ops should be defined by the object file format.
812 However, a.out doesn't support them, so we have versions here. */
813 {"aent", s_mips_ent
, 1},
814 {"bgnb", s_ignore
, 0},
815 {"end", s_mips_end
, 0},
816 {"endb", s_ignore
, 0},
817 {"ent", s_mips_ent
, 0},
819 {"fmask", s_mips_mask
, 'F'},
820 {"frame", s_mips_frame
, 0},
821 {"loc", s_ignore
, 0},
822 {"mask", s_mips_mask
, 'R'},
823 {"verstamp", s_ignore
, 0},
827 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
832 pop_insert (mips_pseudo_table
);
833 if (! ECOFF_DEBUGGING
)
834 pop_insert (mips_nonecoff_pseudo_table
);
837 /* Symbols labelling the current insn. */
839 struct insn_label_list
841 struct insn_label_list
*next
;
845 static struct insn_label_list
*insn_labels
;
846 static struct insn_label_list
*free_insn_labels
;
848 static void mips_clear_insn_labels
PARAMS ((void));
851 mips_clear_insn_labels ()
853 register struct insn_label_list
**pl
;
855 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
861 static char *expr_end
;
863 /* Expressions which appear in instructions. These are set by
866 static expressionS imm_expr
;
867 static expressionS offset_expr
;
869 /* Relocs associated with imm_expr and offset_expr. */
871 static bfd_reloc_code_real_type imm_reloc
[3]
872 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
873 static bfd_reloc_code_real_type offset_reloc
[3]
874 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
876 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
878 static boolean imm_unmatched_hi
;
880 /* These are set by mips16_ip if an explicit extension is used. */
882 static boolean mips16_small
, mips16_ext
;
884 #ifdef MIPS_STABS_ELF
885 /* The pdr segment for per procedure frame/regmask info */
891 mips_isa_to_str (isa
)
894 const struct mips_cpu_info
*ci
;
897 ci
= mips_cpu_info_from_isa (isa
);
901 sprintf (s
, "ISA#%d", isa
);
906 mips_cpu_to_str (cpu
)
909 const struct mips_cpu_info
*ci
;
912 ci
= mips_cpu_info_from_cpu (cpu
);
916 sprintf (s
, "CPU#%d", cpu
);
920 /* The default target format to use. */
923 mips_target_format ()
925 switch (OUTPUT_FLAVOR
)
927 case bfd_target_aout_flavour
:
928 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
929 case bfd_target_ecoff_flavour
:
930 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
931 case bfd_target_coff_flavour
:
933 case bfd_target_elf_flavour
:
935 /* This is traditional mips */
936 return (target_big_endian
937 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
938 : "elf32-tradbigmips")
939 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
940 : "elf32-tradlittlemips"));
942 return (target_big_endian
943 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
944 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
945 : "elf32-littlemips"));
953 /* This function is called once, at assembler startup time. It should
954 set up all the tables, etc. that the MD part of the assembler will need. */
959 register const char *retval
= NULL
;
964 int mips_isa_from_cpu
;
965 int target_cpu_had_mips16
= 0;
966 const struct mips_cpu_info
*ci
;
968 /* GP relative stuff not working for PE */
969 if (strncmp (TARGET_OS
, "pe", 2) == 0
970 && g_switch_value
!= 0)
973 as_bad (_("-G not supported in this configuration."));
978 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
980 a
= xmalloc (sizeof TARGET_CPU
);
981 strcpy (a
, TARGET_CPU
);
982 a
[(sizeof TARGET_CPU
) - 3] = '\0';
986 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
988 target_cpu_had_mips16
= 1;
989 cpu
+= sizeof "mips16" - 1;
992 if (mips_opts
.mips16
< 0)
993 mips_opts
.mips16
= target_cpu_had_mips16
;
995 /* Backward compatibility for historic -mcpu= option. Check for
996 incompatible options, warn if -mcpu is used. */
997 if (mips_cpu
!= CPU_UNKNOWN
998 && mips_arch
!= CPU_UNKNOWN
999 && mips_cpu
!= mips_arch
)
1001 as_fatal (_("The -mcpu option can't be used together with -march. "
1002 "Use -mtune instead of -mcpu."));
1005 if (mips_cpu
!= CPU_UNKNOWN
1006 && mips_tune
!= CPU_UNKNOWN
1007 && mips_cpu
!= mips_tune
)
1009 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1010 "Use -march instead of -mcpu."));
1013 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1015 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1016 assert (ci
!= NULL
);
1017 mips_arch
= ci
->cpu
;
1018 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1019 "-mtune instead."));
1022 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1023 specified on the command line, or some other value if one was.
1024 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1025 the command line, or will be set otherwise if one was. */
1026 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1028 /* We have to check if the isa is the default isa of arch. Otherwise
1029 we'll get invalid object file headers. */
1030 ci
= mips_cpu_info_from_cpu (mips_arch
);
1031 assert (ci
!= NULL
);
1032 if (mips_opts
.isa
!= ci
->isa
)
1034 /* This really should be an error instead of a warning, but old
1035 compilers only have -mcpu which sets both arch and tune. For
1036 now, we discard arch and preserve tune. */
1037 as_warn (_("The -march option is incompatible to -mipsN and "
1038 "therefore ignored."));
1039 if (mips_tune
== CPU_UNKNOWN
)
1040 mips_tune
= mips_arch
;
1041 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1042 assert (ci
!= NULL
);
1043 mips_arch
= ci
->cpu
;
1046 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1048 /* We have ARCH, we need ISA. */
1049 ci
= mips_cpu_info_from_cpu (mips_arch
);
1050 assert (ci
!= NULL
);
1051 mips_opts
.isa
= ci
->isa
;
1053 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1055 /* We have ISA, we need default ARCH. */
1056 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1057 assert (ci
!= NULL
);
1058 mips_arch
= ci
->cpu
;
1062 /* We need to set both ISA and ARCH from target cpu. */
1063 ci
= mips_cpu_info_from_name (cpu
);
1065 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1066 assert (ci
!= NULL
);
1067 mips_opts
.isa
= ci
->isa
;
1068 mips_arch
= ci
->cpu
;
1071 if (mips_tune
== CPU_UNKNOWN
)
1072 mips_tune
= mips_arch
;
1074 ci
= mips_cpu_info_from_cpu (mips_arch
);
1075 assert (ci
!= NULL
);
1076 mips_isa_from_cpu
= ci
->isa
;
1078 /* End of TARGET_CPU processing, get rid of malloced memory
1087 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1088 as_bad (_("trap exception not supported at ISA 1"));
1090 /* Set the EABI kind based on the ISA before the user gets
1091 to change the ISA with directives. This isn't really
1092 the best, but then neither is basing the abi on the isa. */
1093 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1094 && mips_abi
== EABI_ABI
)
1097 /* If they asked for mips1 or mips2 and a cpu that is
1098 mips3 or greater, then mark the object file 32BITMODE. */
1099 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1100 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1101 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1104 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1105 as_warn (_("Could not set architecture and machine"));
1107 file_mips_isa
= mips_opts
.isa
;
1109 op_hash
= hash_new ();
1111 for (i
= 0; i
< NUMOPCODES
;)
1113 const char *name
= mips_opcodes
[i
].name
;
1115 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1118 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1119 mips_opcodes
[i
].name
, retval
);
1120 /* Probably a memory allocation problem? Give up now. */
1121 as_fatal (_("Broken assembler. No assembly attempted."));
1125 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1127 if (!validate_mips_insn (&mips_opcodes
[i
]))
1132 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1135 mips16_op_hash
= hash_new ();
1138 while (i
< bfd_mips16_num_opcodes
)
1140 const char *name
= mips16_opcodes
[i
].name
;
1142 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1144 as_fatal (_("internal: can't hash `%s': %s"),
1145 mips16_opcodes
[i
].name
, retval
);
1148 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1149 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1150 != mips16_opcodes
[i
].match
))
1152 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1153 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1158 while (i
< bfd_mips16_num_opcodes
1159 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1163 as_fatal (_("Broken assembler. No assembly attempted."));
1165 /* We add all the general register names to the symbol table. This
1166 helps us detect invalid uses of them. */
1167 for (i
= 0; i
< 32; i
++)
1171 sprintf (buf
, "$%d", i
);
1172 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1173 &zero_address_frag
));
1175 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1176 &zero_address_frag
));
1177 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1178 &zero_address_frag
));
1179 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1180 &zero_address_frag
));
1181 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1182 &zero_address_frag
));
1183 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1184 &zero_address_frag
));
1185 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1186 &zero_address_frag
));
1187 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1188 &zero_address_frag
));
1190 mips_no_prev_insn (false);
1193 mips_cprmask
[0] = 0;
1194 mips_cprmask
[1] = 0;
1195 mips_cprmask
[2] = 0;
1196 mips_cprmask
[3] = 0;
1198 /* set the default alignment for the text section (2**2) */
1199 record_alignment (text_section
, 2);
1201 if (USE_GLOBAL_POINTER_OPT
)
1202 bfd_set_gp_size (stdoutput
, g_switch_value
);
1204 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1206 /* On a native system, sections must be aligned to 16 byte
1207 boundaries. When configured for an embedded ELF target, we
1209 if (strcmp (TARGET_OS
, "elf") != 0)
1211 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1212 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1213 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1216 /* Create a .reginfo section for register masks and a .mdebug
1217 section for debugging information. */
1225 subseg
= now_subseg
;
1227 /* The ABI says this section should be loaded so that the
1228 running program can access it. However, we don't load it
1229 if we are configured for an embedded target */
1230 flags
= SEC_READONLY
| SEC_DATA
;
1231 if (strcmp (TARGET_OS
, "elf") != 0)
1232 flags
|= SEC_ALLOC
| SEC_LOAD
;
1236 sec
= subseg_new (".reginfo", (subsegT
) 0);
1238 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1239 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1242 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1247 /* The 64-bit ABI uses a .MIPS.options section rather than
1248 .reginfo section. */
1249 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1250 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1251 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1254 /* Set up the option header. */
1256 Elf_Internal_Options opthdr
;
1259 opthdr
.kind
= ODK_REGINFO
;
1260 opthdr
.size
= (sizeof (Elf_External_Options
)
1261 + sizeof (Elf64_External_RegInfo
));
1264 f
= frag_more (sizeof (Elf_External_Options
));
1265 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1266 (Elf_External_Options
*) f
);
1268 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1273 if (ECOFF_DEBUGGING
)
1275 sec
= subseg_new (".mdebug", (subsegT
) 0);
1276 (void) bfd_set_section_flags (stdoutput
, sec
,
1277 SEC_HAS_CONTENTS
| SEC_READONLY
);
1278 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1281 #ifdef MIPS_STABS_ELF
1282 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1283 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1284 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1285 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1288 subseg_set (seg
, subseg
);
1292 if (! ECOFF_DEBUGGING
)
1299 if (! ECOFF_DEBUGGING
)
1307 struct mips_cl_insn insn
;
1308 bfd_reloc_code_real_type unused_reloc
[3]
1309 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1311 imm_expr
.X_op
= O_absent
;
1312 imm_unmatched_hi
= false;
1313 offset_expr
.X_op
= O_absent
;
1314 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1315 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1316 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1317 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1318 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1319 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1321 if (mips_opts
.mips16
)
1322 mips16_ip (str
, &insn
);
1325 mips_ip (str
, &insn
);
1326 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1327 str
, insn
.insn_opcode
));
1332 as_bad ("%s `%s'", insn_error
, str
);
1336 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1338 if (mips_opts
.mips16
)
1339 mips16_macro (&insn
);
1345 if (imm_expr
.X_op
!= O_absent
)
1346 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1348 else if (offset_expr
.X_op
!= O_absent
)
1349 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1351 append_insn ((char *) NULL
, &insn
, NULL
, unused_reloc
, false);
1355 /* See whether instruction IP reads register REG. CLASS is the type
1359 insn_uses_reg (ip
, reg
, class)
1360 struct mips_cl_insn
*ip
;
1362 enum mips_regclass
class;
1364 if (class == MIPS16_REG
)
1366 assert (mips_opts
.mips16
);
1367 reg
= mips16_to_32_reg_map
[reg
];
1368 class = MIPS_GR_REG
;
1371 /* Don't report on general register 0, since it never changes. */
1372 if (class == MIPS_GR_REG
&& reg
== 0)
1375 if (class == MIPS_FP_REG
)
1377 assert (! mips_opts
.mips16
);
1378 /* If we are called with either $f0 or $f1, we must check $f0.
1379 This is not optimal, because it will introduce an unnecessary
1380 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1381 need to distinguish reading both $f0 and $f1 or just one of
1382 them. Note that we don't have to check the other way,
1383 because there is no instruction that sets both $f0 and $f1
1384 and requires a delay. */
1385 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1386 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1387 == (reg
&~ (unsigned) 1)))
1389 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1390 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1391 == (reg
&~ (unsigned) 1)))
1394 else if (! mips_opts
.mips16
)
1396 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1397 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1399 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1400 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1405 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1406 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1407 & MIPS16OP_MASK_RX
)]
1410 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1411 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1412 & MIPS16OP_MASK_RY
)]
1415 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1416 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1417 & MIPS16OP_MASK_MOVE32Z
)]
1420 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1422 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1424 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1426 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1427 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1428 & MIPS16OP_MASK_REGR32
) == reg
)
1435 /* This function returns true if modifying a register requires a
1439 reg_needs_delay (reg
)
1442 unsigned long prev_pinfo
;
1444 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1445 if (! mips_opts
.noreorder
1446 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1447 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1448 || (! gpr_interlocks
1449 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1451 /* A load from a coprocessor or from memory. All load
1452 delays delay the use of general register rt for one
1453 instruction on the r3000. The r6000 and r4000 use
1455 /* Itbl support may require additional care here. */
1456 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1457 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1464 /* Mark instruction labels in mips16 mode. This permits the linker to
1465 handle them specially, such as generating jalx instructions when
1466 needed. We also make them odd for the duration of the assembly, in
1467 order to generate the right sort of code. We will make them even
1468 in the adjust_symtab routine, while leaving them marked. This is
1469 convenient for the debugger and the disassembler. The linker knows
1470 to make them odd again. */
1473 mips16_mark_labels ()
1475 if (mips_opts
.mips16
)
1477 struct insn_label_list
*l
;
1480 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1483 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1484 S_SET_OTHER (l
->label
, STO_MIPS16
);
1486 val
= S_GET_VALUE (l
->label
);
1488 S_SET_VALUE (l
->label
, val
+ 1);
1493 /* Output an instruction. PLACE is where to put the instruction; if
1494 it is NULL, this uses frag_more to get room. IP is the instruction
1495 information. ADDRESS_EXPR is an operand of the instruction to be
1496 used with RELOC_TYPE. */
1499 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1501 struct mips_cl_insn
*ip
;
1502 expressionS
*address_expr
;
1503 bfd_reloc_code_real_type
*reloc_type
;
1504 boolean unmatched_hi
;
1506 register unsigned long prev_pinfo
, pinfo
;
1511 /* Mark instruction labels in mips16 mode. */
1512 if (mips_opts
.mips16
)
1513 mips16_mark_labels ();
1515 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1516 pinfo
= ip
->insn_mo
->pinfo
;
1518 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1522 /* If the previous insn required any delay slots, see if we need
1523 to insert a NOP or two. There are eight kinds of possible
1524 hazards, of which an instruction can have at most one type.
1525 (1) a load from memory delay
1526 (2) a load from a coprocessor delay
1527 (3) an unconditional branch delay
1528 (4) a conditional branch delay
1529 (5) a move to coprocessor register delay
1530 (6) a load coprocessor register from memory delay
1531 (7) a coprocessor condition code delay
1532 (8) a HI/LO special register delay
1534 There are a lot of optimizations we could do that we don't.
1535 In particular, we do not, in general, reorder instructions.
1536 If you use gcc with optimization, it will reorder
1537 instructions and generally do much more optimization then we
1538 do here; repeating all that work in the assembler would only
1539 benefit hand written assembly code, and does not seem worth
1542 /* This is how a NOP is emitted. */
1543 #define emit_nop() \
1545 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1546 : md_number_to_chars (frag_more (4), 0, 4))
1548 /* The previous insn might require a delay slot, depending upon
1549 the contents of the current insn. */
1550 if (! mips_opts
.mips16
1551 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1552 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1553 && ! cop_interlocks
)
1554 || (! gpr_interlocks
1555 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1557 /* A load from a coprocessor or from memory. All load
1558 delays delay the use of general register rt for one
1559 instruction on the r3000. The r6000 and r4000 use
1561 /* Itbl support may require additional care here. */
1562 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1563 if (mips_optimize
== 0
1564 || insn_uses_reg (ip
,
1565 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1570 else if (! mips_opts
.mips16
1571 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1572 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1573 && ! cop_interlocks
)
1574 || (mips_opts
.isa
== ISA_MIPS1
1575 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1577 /* A generic coprocessor delay. The previous instruction
1578 modified a coprocessor general or control register. If
1579 it modified a control register, we need to avoid any
1580 coprocessor instruction (this is probably not always
1581 required, but it sometimes is). If it modified a general
1582 register, we avoid using that register.
1584 On the r6000 and r4000 loading a coprocessor register
1585 from memory is interlocked, and does not require a delay.
1587 This case is not handled very well. There is no special
1588 knowledge of CP0 handling, and the coprocessors other
1589 than the floating point unit are not distinguished at
1591 /* Itbl support may require additional care here. FIXME!
1592 Need to modify this to include knowledge about
1593 user specified delays! */
1594 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1596 if (mips_optimize
== 0
1597 || insn_uses_reg (ip
,
1598 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1603 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1605 if (mips_optimize
== 0
1606 || insn_uses_reg (ip
,
1607 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1614 /* We don't know exactly what the previous instruction
1615 does. If the current instruction uses a coprocessor
1616 register, we must insert a NOP. If previous
1617 instruction may set the condition codes, and the
1618 current instruction uses them, we must insert two
1620 /* Itbl support may require additional care here. */
1621 if (mips_optimize
== 0
1622 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1623 && (pinfo
& INSN_READ_COND_CODE
)))
1625 else if (pinfo
& INSN_COP
)
1629 else if (! mips_opts
.mips16
1630 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1631 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1632 && ! cop_interlocks
)
1634 /* The previous instruction sets the coprocessor condition
1635 codes, but does not require a general coprocessor delay
1636 (this means it is a floating point comparison
1637 instruction). If this instruction uses the condition
1638 codes, we need to insert a single NOP. */
1639 /* Itbl support may require additional care here. */
1640 if (mips_optimize
== 0
1641 || (pinfo
& INSN_READ_COND_CODE
))
1645 /* If we're fixing up mfhi/mflo for the r7000 and the
1646 previous insn was an mfhi/mflo and the current insn
1647 reads the register that the mfhi/mflo wrote to, then
1650 else if (mips_7000_hilo_fix
1651 && MF_HILO_INSN (prev_pinfo
)
1652 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1659 /* If we're fixing up mfhi/mflo for the r7000 and the
1660 2nd previous insn was an mfhi/mflo and the current insn
1661 reads the register that the mfhi/mflo wrote to, then
1664 else if (mips_7000_hilo_fix
1665 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1666 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1674 else if (prev_pinfo
& INSN_READ_LO
)
1676 /* The previous instruction reads the LO register; if the
1677 current instruction writes to the LO register, we must
1678 insert two NOPS. Some newer processors have interlocks.
1679 Also the tx39's multiply instructions can be exectuted
1680 immediatly after a read from HI/LO (without the delay),
1681 though the tx39's divide insns still do require the
1683 if (! (hilo_interlocks
1684 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1685 && (mips_optimize
== 0
1686 || (pinfo
& INSN_WRITE_LO
)))
1688 /* Most mips16 branch insns don't have a delay slot.
1689 If a read from LO is immediately followed by a branch
1690 to a write to LO we have a read followed by a write
1691 less than 2 insns away. We assume the target of
1692 a branch might be a write to LO, and insert a nop
1693 between a read and an immediately following branch. */
1694 else if (mips_opts
.mips16
1695 && (mips_optimize
== 0
1696 || (pinfo
& MIPS16_INSN_BRANCH
)))
1699 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1701 /* The previous instruction reads the HI register; if the
1702 current instruction writes to the HI register, we must
1703 insert a NOP. Some newer processors have interlocks.
1704 Also the note tx39's multiply above. */
1705 if (! (hilo_interlocks
1706 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1707 && (mips_optimize
== 0
1708 || (pinfo
& INSN_WRITE_HI
)))
1710 /* Most mips16 branch insns don't have a delay slot.
1711 If a read from HI is immediately followed by a branch
1712 to a write to HI we have a read followed by a write
1713 less than 2 insns away. We assume the target of
1714 a branch might be a write to HI, and insert a nop
1715 between a read and an immediately following branch. */
1716 else if (mips_opts
.mips16
1717 && (mips_optimize
== 0
1718 || (pinfo
& MIPS16_INSN_BRANCH
)))
1722 /* If the previous instruction was in a noreorder section, then
1723 we don't want to insert the nop after all. */
1724 /* Itbl support may require additional care here. */
1725 if (prev_insn_unreordered
)
1728 /* There are two cases which require two intervening
1729 instructions: 1) setting the condition codes using a move to
1730 coprocessor instruction which requires a general coprocessor
1731 delay and then reading the condition codes 2) reading the HI
1732 or LO register and then writing to it (except on processors
1733 which have interlocks). If we are not already emitting a NOP
1734 instruction, we must check for these cases compared to the
1735 instruction previous to the previous instruction. */
1736 if ((! mips_opts
.mips16
1737 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1738 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1739 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1740 && (pinfo
& INSN_READ_COND_CODE
)
1741 && ! cop_interlocks
)
1742 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1743 && (pinfo
& INSN_WRITE_LO
)
1744 && ! (hilo_interlocks
1745 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1746 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1747 && (pinfo
& INSN_WRITE_HI
)
1748 && ! (hilo_interlocks
1749 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1754 if (prev_prev_insn_unreordered
)
1757 if (prev_prev_nop
&& nops
== 0)
1760 /* If we are being given a nop instruction, don't bother with
1761 one of the nops we would otherwise output. This will only
1762 happen when a nop instruction is used with mips_optimize set
1765 && ! mips_opts
.noreorder
1766 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1769 /* Now emit the right number of NOP instructions. */
1770 if (nops
> 0 && ! mips_opts
.noreorder
)
1773 unsigned long old_frag_offset
;
1775 struct insn_label_list
*l
;
1777 old_frag
= frag_now
;
1778 old_frag_offset
= frag_now_fix ();
1780 for (i
= 0; i
< nops
; i
++)
1785 listing_prev_line ();
1786 /* We may be at the start of a variant frag. In case we
1787 are, make sure there is enough space for the frag
1788 after the frags created by listing_prev_line. The
1789 argument to frag_grow here must be at least as large
1790 as the argument to all other calls to frag_grow in
1791 this file. We don't have to worry about being in the
1792 middle of a variant frag, because the variants insert
1793 all needed nop instructions themselves. */
1797 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1801 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1802 symbol_set_frag (l
->label
, frag_now
);
1803 val
= (valueT
) frag_now_fix ();
1804 /* mips16 text labels are stored as odd. */
1805 if (mips_opts
.mips16
)
1807 S_SET_VALUE (l
->label
, val
);
1810 #ifndef NO_ECOFF_DEBUGGING
1811 if (ECOFF_DEBUGGING
)
1812 ecoff_fix_loc (old_frag
, old_frag_offset
);
1815 else if (prev_nop_frag
!= NULL
)
1817 /* We have a frag holding nops we may be able to remove. If
1818 we don't need any nops, we can decrease the size of
1819 prev_nop_frag by the size of one instruction. If we do
1820 need some nops, we count them in prev_nops_required. */
1821 if (prev_nop_frag_since
== 0)
1825 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1826 --prev_nop_frag_holds
;
1829 prev_nop_frag_required
+= nops
;
1833 if (prev_prev_nop
== 0)
1835 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1836 --prev_nop_frag_holds
;
1839 ++prev_nop_frag_required
;
1842 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1843 prev_nop_frag
= NULL
;
1845 ++prev_nop_frag_since
;
1847 /* Sanity check: by the time we reach the second instruction
1848 after prev_nop_frag, we should have used up all the nops
1849 one way or another. */
1850 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1854 if (*reloc_type
> BFD_RELOC_UNUSED
)
1856 /* We need to set up a variant frag. */
1857 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1858 f
= frag_var (rs_machine_dependent
, 4, 0,
1859 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1860 mips16_small
, mips16_ext
,
1862 & INSN_UNCOND_BRANCH_DELAY
),
1863 (*prev_insn_reloc_type
1864 == BFD_RELOC_MIPS16_JMP
)),
1865 make_expr_symbol (address_expr
), (offsetT
) 0,
1868 else if (place
!= NULL
)
1870 else if (mips_opts
.mips16
1872 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1874 /* Make sure there is enough room to swap this instruction with
1875 a following jump instruction. */
1881 if (mips_opts
.mips16
1882 && mips_opts
.noreorder
1883 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1884 as_warn (_("extended instruction in delay slot"));
1889 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1890 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1892 if (address_expr
->X_op
== O_constant
)
1896 switch (*reloc_type
)
1899 ip
->insn_opcode
|= address_expr
->X_add_number
;
1902 case BFD_RELOC_MIPS_HIGHEST
:
1903 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1905 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1908 case BFD_RELOC_MIPS_HIGHER
:
1909 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1910 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1913 case BFD_RELOC_HI16_S
:
1914 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1918 case BFD_RELOC_HI16
:
1919 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1922 case BFD_RELOC_LO16
:
1923 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1926 case BFD_RELOC_MIPS_JMP
:
1927 if ((address_expr
->X_add_number
& 3) != 0)
1928 as_bad (_("jump to misaligned address (0x%lx)"),
1929 (unsigned long) address_expr
->X_add_number
);
1930 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1933 case BFD_RELOC_MIPS16_JMP
:
1934 if ((address_expr
->X_add_number
& 3) != 0)
1935 as_bad (_("jump to misaligned address (0x%lx)"),
1936 (unsigned long) address_expr
->X_add_number
);
1938 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1939 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1940 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1943 case BFD_RELOC_16_PCREL
:
1944 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1947 case BFD_RELOC_16_PCREL_S2
:
1957 /* Don't generate a reloc if we are writing into a variant frag. */
1960 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1962 (*reloc_type
== BFD_RELOC_16_PCREL
1963 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
1966 /* These relocations can have a addend that won't fit in
1967 4 octets for 64bit assembly. */
1968 if (HAVE_64BIT_GPRS
&&
1969 (*reloc_type
== BFD_RELOC_16
1970 || *reloc_type
== BFD_RELOC_32
1971 || *reloc_type
== BFD_RELOC_MIPS_JMP
1972 || *reloc_type
== BFD_RELOC_HI16_S
1973 || *reloc_type
== BFD_RELOC_LO16
1974 || *reloc_type
== BFD_RELOC_GPREL16
1975 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
1976 || *reloc_type
== BFD_RELOC_GPREL32
1977 || *reloc_type
== BFD_RELOC_64
1978 || *reloc_type
== BFD_RELOC_CTOR
1979 || *reloc_type
== BFD_RELOC_MIPS_SUB
1980 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
1981 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
1982 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
1983 || *reloc_type
== BFD_RELOC_MIPS_REL16
1984 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
1985 fixp
[0]->fx_no_overflow
= 1;
1989 struct mips_hi_fixup
*hi_fixup
;
1991 assert (*reloc_type
== BFD_RELOC_HI16_S
);
1992 hi_fixup
= ((struct mips_hi_fixup
*)
1993 xmalloc (sizeof (struct mips_hi_fixup
)));
1994 hi_fixup
->fixp
= fixp
[0];
1995 hi_fixup
->seg
= now_seg
;
1996 hi_fixup
->next
= mips_hi_fixup_list
;
1997 mips_hi_fixup_list
= hi_fixup
;
2000 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2002 /* FIXME: This symbol can be one of
2003 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2004 address_expr
->X_op
= O_absent
;
2005 address_expr
->X_add_symbol
= 0;
2006 address_expr
->X_add_number
= 0;
2008 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2009 4, address_expr
, false,
2012 /* These relocations can have a addend that won't fit in
2013 4 octets for 64bit assembly. */
2014 if (HAVE_64BIT_GPRS
&&
2015 (*reloc_type
== BFD_RELOC_16
2016 || *reloc_type
== BFD_RELOC_32
2017 || *reloc_type
== BFD_RELOC_MIPS_JMP
2018 || *reloc_type
== BFD_RELOC_HI16_S
2019 || *reloc_type
== BFD_RELOC_LO16
2020 || *reloc_type
== BFD_RELOC_GPREL16
2021 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2022 || *reloc_type
== BFD_RELOC_GPREL32
2023 || *reloc_type
== BFD_RELOC_64
2024 || *reloc_type
== BFD_RELOC_CTOR
2025 || *reloc_type
== BFD_RELOC_MIPS_SUB
2026 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2027 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2028 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2029 || *reloc_type
== BFD_RELOC_MIPS_REL16
2030 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2031 fixp
[1]->fx_no_overflow
= 1;
2033 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2035 address_expr
->X_op
= O_absent
;
2036 address_expr
->X_add_symbol
= 0;
2037 address_expr
->X_add_number
= 0;
2039 fixp
[2] = fix_new_exp (frag_now
,
2040 f
- frag_now
->fr_literal
, 4,
2041 address_expr
, false,
2044 /* These relocations can have a addend that won't fit in
2045 4 octets for 64bit assembly. */
2046 if (HAVE_64BIT_GPRS
&&
2047 (*reloc_type
== BFD_RELOC_16
2048 || *reloc_type
== BFD_RELOC_32
2049 || *reloc_type
== BFD_RELOC_MIPS_JMP
2050 || *reloc_type
== BFD_RELOC_HI16_S
2051 || *reloc_type
== BFD_RELOC_LO16
2052 || *reloc_type
== BFD_RELOC_GPREL16
2053 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2054 || *reloc_type
== BFD_RELOC_GPREL32
2055 || *reloc_type
== BFD_RELOC_64
2056 || *reloc_type
== BFD_RELOC_CTOR
2057 || *reloc_type
== BFD_RELOC_MIPS_SUB
2058 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2059 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2060 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2061 || *reloc_type
== BFD_RELOC_MIPS_REL16
2062 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2063 fixp
[2]->fx_no_overflow
= 1;
2070 if (! mips_opts
.mips16
)
2071 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2072 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2074 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2075 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2081 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2084 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2087 /* Update the register mask information. */
2088 if (! mips_opts
.mips16
)
2090 if (pinfo
& INSN_WRITE_GPR_D
)
2091 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2092 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2093 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2094 if (pinfo
& INSN_READ_GPR_S
)
2095 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2096 if (pinfo
& INSN_WRITE_GPR_31
)
2097 mips_gprmask
|= 1 << 31;
2098 if (pinfo
& INSN_WRITE_FPR_D
)
2099 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2100 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2101 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2102 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2103 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2104 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2105 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2106 if (pinfo
& INSN_COP
)
2108 /* We don't keep enough information to sort these cases out.
2109 The itbl support does keep this information however, although
2110 we currently don't support itbl fprmats as part of the cop
2111 instruction. May want to add this support in the future. */
2113 /* Never set the bit for $0, which is always zero. */
2114 mips_gprmask
&= ~1 << 0;
2118 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2119 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2120 & MIPS16OP_MASK_RX
);
2121 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2122 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2123 & MIPS16OP_MASK_RY
);
2124 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2125 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2126 & MIPS16OP_MASK_RZ
);
2127 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2128 mips_gprmask
|= 1 << TREG
;
2129 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2130 mips_gprmask
|= 1 << SP
;
2131 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2132 mips_gprmask
|= 1 << RA
;
2133 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2134 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2135 if (pinfo
& MIPS16_INSN_READ_Z
)
2136 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2137 & MIPS16OP_MASK_MOVE32Z
);
2138 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2139 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2140 & MIPS16OP_MASK_REGR32
);
2143 if (place
== NULL
&& ! mips_opts
.noreorder
)
2145 /* Filling the branch delay slot is more complex. We try to
2146 switch the branch with the previous instruction, which we can
2147 do if the previous instruction does not set up a condition
2148 that the branch tests and if the branch is not itself the
2149 target of any branch. */
2150 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2151 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2153 if (mips_optimize
< 2
2154 /* If we have seen .set volatile or .set nomove, don't
2156 || mips_opts
.nomove
!= 0
2157 /* If we had to emit any NOP instructions, then we
2158 already know we can not swap. */
2160 /* If we don't even know the previous insn, we can not
2162 || ! prev_insn_valid
2163 /* If the previous insn is already in a branch delay
2164 slot, then we can not swap. */
2165 || prev_insn_is_delay_slot
2166 /* If the previous previous insn was in a .set
2167 noreorder, we can't swap. Actually, the MIPS
2168 assembler will swap in this situation. However, gcc
2169 configured -with-gnu-as will generate code like
2175 in which we can not swap the bne and INSN. If gcc is
2176 not configured -with-gnu-as, it does not output the
2177 .set pseudo-ops. We don't have to check
2178 prev_insn_unreordered, because prev_insn_valid will
2179 be 0 in that case. We don't want to use
2180 prev_prev_insn_valid, because we do want to be able
2181 to swap at the start of a function. */
2182 || prev_prev_insn_unreordered
2183 /* If the branch is itself the target of a branch, we
2184 can not swap. We cheat on this; all we check for is
2185 whether there is a label on this instruction. If
2186 there are any branches to anything other than a
2187 label, users must use .set noreorder. */
2188 || insn_labels
!= NULL
2189 /* If the previous instruction is in a variant frag, we
2190 can not do the swap. This does not apply to the
2191 mips16, which uses variant frags for different
2193 || (! mips_opts
.mips16
2194 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2195 /* If the branch reads the condition codes, we don't
2196 even try to swap, because in the sequence
2201 we can not swap, and I don't feel like handling that
2203 || (! mips_opts
.mips16
2204 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2205 && (pinfo
& INSN_READ_COND_CODE
))
2206 /* We can not swap with an instruction that requires a
2207 delay slot, becase the target of the branch might
2208 interfere with that instruction. */
2209 || (! mips_opts
.mips16
2210 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2212 /* Itbl support may require additional care here. */
2213 & (INSN_LOAD_COPROC_DELAY
2214 | INSN_COPROC_MOVE_DELAY
2215 | INSN_WRITE_COND_CODE
)))
2216 || (! (hilo_interlocks
2217 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2221 || (! mips_opts
.mips16
2223 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2224 || (! mips_opts
.mips16
2225 && mips_opts
.isa
== ISA_MIPS1
2226 /* Itbl support may require additional care here. */
2227 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2228 /* We can not swap with a branch instruction. */
2230 & (INSN_UNCOND_BRANCH_DELAY
2231 | INSN_COND_BRANCH_DELAY
2232 | INSN_COND_BRANCH_LIKELY
))
2233 /* We do not swap with a trap instruction, since it
2234 complicates trap handlers to have the trap
2235 instruction be in a delay slot. */
2236 || (prev_pinfo
& INSN_TRAP
)
2237 /* If the branch reads a register that the previous
2238 instruction sets, we can not swap. */
2239 || (! mips_opts
.mips16
2240 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2241 && insn_uses_reg (ip
,
2242 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2245 || (! mips_opts
.mips16
2246 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2247 && insn_uses_reg (ip
,
2248 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2251 || (mips_opts
.mips16
2252 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2253 && insn_uses_reg (ip
,
2254 ((prev_insn
.insn_opcode
2256 & MIPS16OP_MASK_RX
),
2258 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2259 && insn_uses_reg (ip
,
2260 ((prev_insn
.insn_opcode
2262 & MIPS16OP_MASK_RY
),
2264 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2265 && insn_uses_reg (ip
,
2266 ((prev_insn
.insn_opcode
2268 & MIPS16OP_MASK_RZ
),
2270 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2271 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2272 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2273 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2274 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2275 && insn_uses_reg (ip
,
2276 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2279 /* If the branch writes a register that the previous
2280 instruction sets, we can not swap (we know that
2281 branches write only to RD or to $31). */
2282 || (! mips_opts
.mips16
2283 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2284 && (((pinfo
& INSN_WRITE_GPR_D
)
2285 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2286 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2287 || ((pinfo
& INSN_WRITE_GPR_31
)
2288 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2291 || (! mips_opts
.mips16
2292 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2293 && (((pinfo
& INSN_WRITE_GPR_D
)
2294 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2295 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2296 || ((pinfo
& INSN_WRITE_GPR_31
)
2297 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2300 || (mips_opts
.mips16
2301 && (pinfo
& MIPS16_INSN_WRITE_31
)
2302 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2303 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2304 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2306 /* If the branch writes a register that the previous
2307 instruction reads, we can not swap (we know that
2308 branches only write to RD or to $31). */
2309 || (! mips_opts
.mips16
2310 && (pinfo
& INSN_WRITE_GPR_D
)
2311 && insn_uses_reg (&prev_insn
,
2312 ((ip
->insn_opcode
>> OP_SH_RD
)
2315 || (! mips_opts
.mips16
2316 && (pinfo
& INSN_WRITE_GPR_31
)
2317 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2318 || (mips_opts
.mips16
2319 && (pinfo
& MIPS16_INSN_WRITE_31
)
2320 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2321 /* If we are generating embedded PIC code, the branch
2322 might be expanded into a sequence which uses $at, so
2323 we can't swap with an instruction which reads it. */
2324 || (mips_pic
== EMBEDDED_PIC
2325 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2326 /* If the previous previous instruction has a load
2327 delay, and sets a register that the branch reads, we
2329 || (! mips_opts
.mips16
2330 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2331 /* Itbl support may require additional care here. */
2332 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2333 || (! gpr_interlocks
2334 && (prev_prev_insn
.insn_mo
->pinfo
2335 & INSN_LOAD_MEMORY_DELAY
)))
2336 && insn_uses_reg (ip
,
2337 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2340 /* If one instruction sets a condition code and the
2341 other one uses a condition code, we can not swap. */
2342 || ((pinfo
& INSN_READ_COND_CODE
)
2343 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2344 || ((pinfo
& INSN_WRITE_COND_CODE
)
2345 && (prev_pinfo
& INSN_READ_COND_CODE
))
2346 /* If the previous instruction uses the PC, we can not
2348 || (mips_opts
.mips16
2349 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2350 /* If the previous instruction was extended, we can not
2352 || (mips_opts
.mips16
&& prev_insn_extended
)
2353 /* If the previous instruction had a fixup in mips16
2354 mode, we can not swap. This normally means that the
2355 previous instruction was a 4 byte branch anyhow. */
2356 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2357 /* If the previous instruction is a sync, sync.l, or
2358 sync.p, we can not swap. */
2359 || (prev_pinfo
& INSN_SYNC
))
2361 /* We could do even better for unconditional branches to
2362 portions of this object file; we could pick up the
2363 instruction at the destination, put it in the delay
2364 slot, and bump the destination address. */
2366 /* Update the previous insn information. */
2367 prev_prev_insn
= *ip
;
2368 prev_insn
.insn_mo
= &dummy_opcode
;
2372 /* It looks like we can actually do the swap. */
2373 if (! mips_opts
.mips16
)
2378 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2379 memcpy (temp
, prev_f
, 4);
2380 memcpy (prev_f
, f
, 4);
2381 memcpy (f
, temp
, 4);
2382 if (prev_insn_fixp
[0])
2384 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2385 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2387 if (prev_insn_fixp
[1])
2389 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2390 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2392 if (prev_insn_fixp
[2])
2394 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2395 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2399 fixp
[0]->fx_frag
= prev_insn_frag
;
2400 fixp
[0]->fx_where
= prev_insn_where
;
2404 fixp
[1]->fx_frag
= prev_insn_frag
;
2405 fixp
[1]->fx_where
= prev_insn_where
;
2409 fixp
[2]->fx_frag
= prev_insn_frag
;
2410 fixp
[2]->fx_where
= prev_insn_where
;
2418 assert (prev_insn_fixp
[0] == NULL
);
2419 assert (prev_insn_fixp
[1] == NULL
);
2420 assert (prev_insn_fixp
[2] == NULL
);
2421 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2422 memcpy (temp
, prev_f
, 2);
2423 memcpy (prev_f
, f
, 2);
2424 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2426 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2427 memcpy (f
, temp
, 2);
2431 memcpy (f
, f
+ 2, 2);
2432 memcpy (f
+ 2, temp
, 2);
2436 fixp
[0]->fx_frag
= prev_insn_frag
;
2437 fixp
[0]->fx_where
= prev_insn_where
;
2441 fixp
[1]->fx_frag
= prev_insn_frag
;
2442 fixp
[1]->fx_where
= prev_insn_where
;
2446 fixp
[2]->fx_frag
= prev_insn_frag
;
2447 fixp
[2]->fx_where
= prev_insn_where
;
2451 /* Update the previous insn information; leave prev_insn
2453 prev_prev_insn
= *ip
;
2455 prev_insn_is_delay_slot
= 1;
2457 /* If that was an unconditional branch, forget the previous
2458 insn information. */
2459 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2461 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2462 prev_insn
.insn_mo
= &dummy_opcode
;
2465 prev_insn_fixp
[0] = NULL
;
2466 prev_insn_fixp
[1] = NULL
;
2467 prev_insn_fixp
[2] = NULL
;
2468 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2469 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2470 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2471 prev_insn_extended
= 0;
2473 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2475 /* We don't yet optimize a branch likely. What we should do
2476 is look at the target, copy the instruction found there
2477 into the delay slot, and increment the branch to jump to
2478 the next instruction. */
2480 /* Update the previous insn information. */
2481 prev_prev_insn
= *ip
;
2482 prev_insn
.insn_mo
= &dummy_opcode
;
2483 prev_insn_fixp
[0] = NULL
;
2484 prev_insn_fixp
[1] = NULL
;
2485 prev_insn_fixp
[2] = NULL
;
2486 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2487 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2488 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2489 prev_insn_extended
= 0;
2493 /* Update the previous insn information. */
2495 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2497 prev_prev_insn
= prev_insn
;
2500 /* Any time we see a branch, we always fill the delay slot
2501 immediately; since this insn is not a branch, we know it
2502 is not in a delay slot. */
2503 prev_insn_is_delay_slot
= 0;
2505 prev_insn_fixp
[0] = fixp
[0];
2506 prev_insn_fixp
[1] = fixp
[1];
2507 prev_insn_fixp
[2] = fixp
[2];
2508 prev_insn_reloc_type
[0] = reloc_type
[0];
2509 prev_insn_reloc_type
[1] = reloc_type
[1];
2510 prev_insn_reloc_type
[2] = reloc_type
[2];
2511 if (mips_opts
.mips16
)
2512 prev_insn_extended
= (ip
->use_extend
2513 || *reloc_type
> BFD_RELOC_UNUSED
);
2516 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2517 prev_insn_unreordered
= 0;
2518 prev_insn_frag
= frag_now
;
2519 prev_insn_where
= f
- frag_now
->fr_literal
;
2520 prev_insn_valid
= 1;
2522 else if (place
== NULL
)
2524 /* We need to record a bit of information even when we are not
2525 reordering, in order to determine the base address for mips16
2526 PC relative relocs. */
2527 prev_prev_insn
= prev_insn
;
2529 prev_insn_reloc_type
[0] = reloc_type
[0];
2530 prev_insn_reloc_type
[1] = reloc_type
[1];
2531 prev_insn_reloc_type
[2] = reloc_type
[2];
2532 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2533 prev_insn_unreordered
= 1;
2536 /* We just output an insn, so the next one doesn't have a label. */
2537 mips_clear_insn_labels ();
2539 /* We must ensure that a fixup associated with an unmatched %hi
2540 reloc does not become a variant frag. Otherwise, the
2541 rearrangement of %hi relocs in frob_file may confuse
2545 frag_wane (frag_now
);
2550 /* This function forgets that there was any previous instruction or
2551 label. If PRESERVE is non-zero, it remembers enough information to
2552 know whether nops are needed before a noreorder section. */
2555 mips_no_prev_insn (preserve
)
2560 prev_insn
.insn_mo
= &dummy_opcode
;
2561 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2562 prev_nop_frag
= NULL
;
2563 prev_nop_frag_holds
= 0;
2564 prev_nop_frag_required
= 0;
2565 prev_nop_frag_since
= 0;
2567 prev_insn_valid
= 0;
2568 prev_insn_is_delay_slot
= 0;
2569 prev_insn_unreordered
= 0;
2570 prev_insn_extended
= 0;
2571 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2572 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2573 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2574 prev_prev_insn_unreordered
= 0;
2575 mips_clear_insn_labels ();
2578 /* This function must be called whenever we turn on noreorder or emit
2579 something other than instructions. It inserts any NOPS which might
2580 be needed by the previous instruction, and clears the information
2581 kept for the previous instructions. The INSNS parameter is true if
2582 instructions are to follow. */
2585 mips_emit_delays (insns
)
2588 if (! mips_opts
.noreorder
)
2593 if ((! mips_opts
.mips16
2594 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2595 && (! cop_interlocks
2596 && (prev_insn
.insn_mo
->pinfo
2597 & (INSN_LOAD_COPROC_DELAY
2598 | INSN_COPROC_MOVE_DELAY
2599 | INSN_WRITE_COND_CODE
))))
2600 || (! hilo_interlocks
2601 && (prev_insn
.insn_mo
->pinfo
2604 || (! mips_opts
.mips16
2606 && (prev_insn
.insn_mo
->pinfo
2607 & INSN_LOAD_MEMORY_DELAY
))
2608 || (! mips_opts
.mips16
2609 && mips_opts
.isa
== ISA_MIPS1
2610 && (prev_insn
.insn_mo
->pinfo
2611 & INSN_COPROC_MEMORY_DELAY
)))
2613 /* Itbl support may require additional care here. */
2615 if ((! mips_opts
.mips16
2616 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2617 && (! cop_interlocks
2618 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2619 || (! hilo_interlocks
2620 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2621 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2624 if (prev_insn_unreordered
)
2627 else if ((! mips_opts
.mips16
2628 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2629 && (! cop_interlocks
2630 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2631 || (! hilo_interlocks
2632 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2633 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2635 /* Itbl support may require additional care here. */
2636 if (! prev_prev_insn_unreordered
)
2642 struct insn_label_list
*l
;
2646 /* Record the frag which holds the nop instructions, so
2647 that we can remove them if we don't need them. */
2648 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2649 prev_nop_frag
= frag_now
;
2650 prev_nop_frag_holds
= nops
;
2651 prev_nop_frag_required
= 0;
2652 prev_nop_frag_since
= 0;
2655 for (; nops
> 0; --nops
)
2660 /* Move on to a new frag, so that it is safe to simply
2661 decrease the size of prev_nop_frag. */
2662 frag_wane (frag_now
);
2666 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2670 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2671 symbol_set_frag (l
->label
, frag_now
);
2672 val
= (valueT
) frag_now_fix ();
2673 /* mips16 text labels are stored as odd. */
2674 if (mips_opts
.mips16
)
2676 S_SET_VALUE (l
->label
, val
);
2681 /* Mark instruction labels in mips16 mode. */
2682 if (mips_opts
.mips16
&& insns
)
2683 mips16_mark_labels ();
2685 mips_no_prev_insn (insns
);
2688 /* Build an instruction created by a macro expansion. This is passed
2689 a pointer to the count of instructions created so far, an
2690 expression, the name of the instruction to build, an operand format
2691 string, and corresponding arguments. */
2695 macro_build (char *place
,
2703 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2712 struct mips_cl_insn insn
;
2713 bfd_reloc_code_real_type r
[3];
2717 va_start (args
, fmt
);
2723 * If the macro is about to expand into a second instruction,
2724 * print a warning if needed. We need to pass ip as a parameter
2725 * to generate a better warning message here...
2727 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2728 as_warn (_("Macro instruction expanded into multiple instructions"));
2731 *counter
+= 1; /* bump instruction counter */
2733 if (mips_opts
.mips16
)
2735 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2740 r
[0] = BFD_RELOC_UNUSED
;
2741 r
[1] = BFD_RELOC_UNUSED
;
2742 r
[2] = BFD_RELOC_UNUSED
;
2743 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2744 assert (insn
.insn_mo
);
2745 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2747 /* Search until we get a match for NAME. */
2750 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2751 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2752 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2753 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2757 assert (insn
.insn_mo
->name
);
2758 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2761 insn
.insn_opcode
= insn
.insn_mo
->match
;
2777 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2781 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2786 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2791 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2796 int tmp
= va_arg (args
, int);
2798 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2799 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2805 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2812 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2816 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2820 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2824 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2828 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2835 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2841 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2842 assert (*r
== BFD_RELOC_MIPS_GPREL
2843 || *r
== BFD_RELOC_MIPS_LITERAL
2844 || *r
== BFD_RELOC_MIPS_HIGHER
2845 || *r
== BFD_RELOC_HI16_S
2846 || *r
== BFD_RELOC_LO16
2847 || *r
== BFD_RELOC_MIPS_GOT16
2848 || *r
== BFD_RELOC_MIPS_CALL16
2849 || *r
== BFD_RELOC_MIPS_GOT_LO16
2850 || *r
== BFD_RELOC_MIPS_CALL_LO16
2851 || (ep
->X_op
== O_subtract
2852 && *r
== BFD_RELOC_PCREL_LO16
));
2856 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2858 && (ep
->X_op
== O_constant
2859 || (ep
->X_op
== O_symbol
2860 && (*r
== BFD_RELOC_MIPS_HIGHEST
2861 || *r
== BFD_RELOC_HI16_S
2862 || *r
== BFD_RELOC_HI16
2863 || *r
== BFD_RELOC_GPREL16
2864 || *r
== BFD_RELOC_MIPS_GOT_HI16
2865 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2866 || (ep
->X_op
== O_subtract
2867 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2871 assert (ep
!= NULL
);
2873 * This allows macro() to pass an immediate expression for
2874 * creating short branches without creating a symbol.
2875 * Note that the expression still might come from the assembly
2876 * input, in which case the value is not checked for range nor
2877 * is a relocation entry generated (yuck).
2879 if (ep
->X_op
== O_constant
)
2881 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2885 if (mips_pic
== EMBEDDED_PIC
)
2886 *r
= BFD_RELOC_16_PCREL_S2
;
2888 *r
= BFD_RELOC_16_PCREL
;
2892 assert (ep
!= NULL
);
2893 *r
= BFD_RELOC_MIPS_JMP
;
2897 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2906 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2908 append_insn (place
, &insn
, ep
, r
, false);
2912 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2914 int *counter ATTRIBUTE_UNUSED
;
2920 struct mips_cl_insn insn
;
2921 bfd_reloc_code_real_type r
[3]
2922 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2924 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2925 assert (insn
.insn_mo
);
2926 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2928 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2929 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2932 assert (insn
.insn_mo
->name
);
2933 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2936 insn
.insn_opcode
= insn
.insn_mo
->match
;
2937 insn
.use_extend
= false;
2956 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2961 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2965 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2969 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2979 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2986 regno
= va_arg (args
, int);
2987 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2988 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3009 assert (ep
!= NULL
);
3011 if (ep
->X_op
!= O_constant
)
3012 *r
= BFD_RELOC_UNUSED
+ c
;
3015 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
3016 false, false, &insn
.insn_opcode
,
3017 &insn
.use_extend
, &insn
.extend
);
3019 *r
= BFD_RELOC_UNUSED
;
3025 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3032 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3034 append_insn (place
, &insn
, ep
, r
, false);
3038 * Generate a "lui" instruction.
3041 macro_build_lui (place
, counter
, ep
, regnum
)
3047 expressionS high_expr
;
3048 struct mips_cl_insn insn
;
3049 bfd_reloc_code_real_type r
[3]
3050 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3051 CONST
char *name
= "lui";
3052 CONST
char *fmt
= "t,u";
3054 assert (! mips_opts
.mips16
);
3060 high_expr
.X_op
= O_constant
;
3061 high_expr
.X_add_number
= ep
->X_add_number
;
3064 if (high_expr
.X_op
== O_constant
)
3066 /* we can compute the instruction now without a relocation entry */
3067 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3069 *r
= BFD_RELOC_UNUSED
;
3071 else if (! HAVE_NEWABI
)
3073 assert (ep
->X_op
== O_symbol
);
3074 /* _gp_disp is a special case, used from s_cpload. */
3075 assert (mips_pic
== NO_PIC
3076 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3077 *r
= BFD_RELOC_HI16_S
;
3081 * If the macro is about to expand into a second instruction,
3082 * print a warning if needed. We need to pass ip as a parameter
3083 * to generate a better warning message here...
3085 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3086 as_warn (_("Macro instruction expanded into multiple instructions"));
3089 *counter
+= 1; /* bump instruction counter */
3091 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3092 assert (insn
.insn_mo
);
3093 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3094 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3096 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3097 if (*r
== BFD_RELOC_UNUSED
)
3099 insn
.insn_opcode
|= high_expr
.X_add_number
;
3100 append_insn (place
, &insn
, NULL
, r
, false);
3103 append_insn (place
, &insn
, &high_expr
, r
, false);
3107 * Generates code to set the $at register to true (one)
3108 * if reg is less than the immediate expression.
3111 set_at (counter
, reg
, unsignedp
)
3116 if (imm_expr
.X_op
== O_constant
3117 && imm_expr
.X_add_number
>= -0x8000
3118 && imm_expr
.X_add_number
< 0x8000)
3119 macro_build ((char *) NULL
, counter
, &imm_expr
,
3120 unsignedp
? "sltiu" : "slti",
3121 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3124 load_register (counter
, AT
, &imm_expr
, 0);
3125 macro_build ((char *) NULL
, counter
, NULL
,
3126 unsignedp
? "sltu" : "slt",
3127 "d,v,t", AT
, reg
, AT
);
3131 /* Warn if an expression is not a constant. */
3134 check_absolute_expr (ip
, ex
)
3135 struct mips_cl_insn
*ip
;
3138 if (ex
->X_op
== O_big
)
3139 as_bad (_("unsupported large constant"));
3140 else if (ex
->X_op
!= O_constant
)
3141 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3144 /* Count the leading zeroes by performing a binary chop. This is a
3145 bulky bit of source, but performance is a LOT better for the
3146 majority of values than a simple loop to count the bits:
3147 for (lcnt = 0; (lcnt < 32); lcnt++)
3148 if ((v) & (1 << (31 - lcnt)))
3150 However it is not code size friendly, and the gain will drop a bit
3151 on certain cached systems.
3153 #define COUNT_TOP_ZEROES(v) \
3154 (((v) & ~0xffff) == 0 \
3155 ? ((v) & ~0xff) == 0 \
3156 ? ((v) & ~0xf) == 0 \
3157 ? ((v) & ~0x3) == 0 \
3158 ? ((v) & ~0x1) == 0 \
3163 : ((v) & ~0x7) == 0 \
3166 : ((v) & ~0x3f) == 0 \
3167 ? ((v) & ~0x1f) == 0 \
3170 : ((v) & ~0x7f) == 0 \
3173 : ((v) & ~0xfff) == 0 \
3174 ? ((v) & ~0x3ff) == 0 \
3175 ? ((v) & ~0x1ff) == 0 \
3178 : ((v) & ~0x7ff) == 0 \
3181 : ((v) & ~0x3fff) == 0 \
3182 ? ((v) & ~0x1fff) == 0 \
3185 : ((v) & ~0x7fff) == 0 \
3188 : ((v) & ~0xffffff) == 0 \
3189 ? ((v) & ~0xfffff) == 0 \
3190 ? ((v) & ~0x3ffff) == 0 \
3191 ? ((v) & ~0x1ffff) == 0 \
3194 : ((v) & ~0x7ffff) == 0 \
3197 : ((v) & ~0x3fffff) == 0 \
3198 ? ((v) & ~0x1fffff) == 0 \
3201 : ((v) & ~0x7fffff) == 0 \
3204 : ((v) & ~0xfffffff) == 0 \
3205 ? ((v) & ~0x3ffffff) == 0 \
3206 ? ((v) & ~0x1ffffff) == 0 \
3209 : ((v) & ~0x7ffffff) == 0 \
3212 : ((v) & ~0x3fffffff) == 0 \
3213 ? ((v) & ~0x1fffffff) == 0 \
3216 : ((v) & ~0x7fffffff) == 0 \
3221 * This routine generates the least number of instructions neccessary to load
3222 * an absolute expression value into a register.
3225 load_register (counter
, reg
, ep
, dbl
)
3232 expressionS hi32
, lo32
;
3234 if (ep
->X_op
!= O_big
)
3236 assert (ep
->X_op
== O_constant
);
3237 if (ep
->X_add_number
< 0x8000
3238 && (ep
->X_add_number
>= 0
3239 || (ep
->X_add_number
>= -0x8000
3242 || sizeof (ep
->X_add_number
) > 4))))
3244 /* We can handle 16 bit signed values with an addiu to
3245 $zero. No need to ever use daddiu here, since $zero and
3246 the result are always correct in 32 bit mode. */
3247 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3248 (int) BFD_RELOC_LO16
);
3251 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3253 /* We can handle 16 bit unsigned values with an ori to
3255 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3256 (int) BFD_RELOC_LO16
);
3259 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3260 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3261 == ~ (offsetT
) 0x7fffffff))
3264 || sizeof (ep
->X_add_number
) > 4
3265 || (ep
->X_add_number
& 0x80000000) == 0))
3266 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3267 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3270 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3271 == ~ (offsetT
) 0xffffffff)))
3273 /* 32 bit values require an lui. */
3274 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3275 (int) BFD_RELOC_HI16
);
3276 if ((ep
->X_add_number
& 0xffff) != 0)
3277 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3278 (int) BFD_RELOC_LO16
);
3283 /* The value is larger than 32 bits. */
3285 if (HAVE_32BIT_GPRS
)
3287 as_bad (_("Number larger than 32 bits"));
3288 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3289 (int) BFD_RELOC_LO16
);
3293 if (ep
->X_op
!= O_big
)
3296 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3297 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3298 hi32
.X_add_number
&= 0xffffffff;
3300 lo32
.X_add_number
&= 0xffffffff;
3304 assert (ep
->X_add_number
> 2);
3305 if (ep
->X_add_number
== 3)
3306 generic_bignum
[3] = 0;
3307 else if (ep
->X_add_number
> 4)
3308 as_bad (_("Number larger than 64 bits"));
3309 lo32
.X_op
= O_constant
;
3310 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3311 hi32
.X_op
= O_constant
;
3312 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3315 if (hi32
.X_add_number
== 0)
3320 unsigned long hi
, lo
;
3322 if (hi32
.X_add_number
== 0xffffffff)
3324 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3326 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3327 reg
, 0, (int) BFD_RELOC_LO16
);
3330 if (lo32
.X_add_number
& 0x80000000)
3332 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3333 (int) BFD_RELOC_HI16
);
3334 if (lo32
.X_add_number
& 0xffff)
3335 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3336 reg
, reg
, (int) BFD_RELOC_LO16
);
3341 /* Check for 16bit shifted constant. We know that hi32 is
3342 non-zero, so start the mask on the first bit of the hi32
3347 unsigned long himask
, lomask
;
3351 himask
= 0xffff >> (32 - shift
);
3352 lomask
= (0xffff << shift
) & 0xffffffff;
3356 himask
= 0xffff << (shift
- 32);
3359 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3360 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3364 tmp
.X_op
= O_constant
;
3366 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3367 | (lo32
.X_add_number
>> shift
));
3369 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3370 macro_build ((char *) NULL
, counter
, &tmp
,
3371 "ori", "t,r,i", reg
, 0,
3372 (int) BFD_RELOC_LO16
);
3373 macro_build ((char *) NULL
, counter
, NULL
,
3374 (shift
>= 32) ? "dsll32" : "dsll",
3376 (shift
>= 32) ? shift
- 32 : shift
);
3381 while (shift
<= (64 - 16));
3383 /* Find the bit number of the lowest one bit, and store the
3384 shifted value in hi/lo. */
3385 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3386 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3390 while ((lo
& 1) == 0)
3395 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3401 while ((hi
& 1) == 0)
3410 /* Optimize if the shifted value is a (power of 2) - 1. */
3411 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3412 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3414 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3419 /* This instruction will set the register to be all
3421 tmp
.X_op
= O_constant
;
3422 tmp
.X_add_number
= (offsetT
) -1;
3423 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3424 reg
, 0, (int) BFD_RELOC_LO16
);
3428 macro_build ((char *) NULL
, counter
, NULL
,
3429 (bit
>= 32) ? "dsll32" : "dsll",
3431 (bit
>= 32) ? bit
- 32 : bit
);
3433 macro_build ((char *) NULL
, counter
, NULL
,
3434 (shift
>= 32) ? "dsrl32" : "dsrl",
3436 (shift
>= 32) ? shift
- 32 : shift
);
3441 /* Sign extend hi32 before calling load_register, because we can
3442 generally get better code when we load a sign extended value. */
3443 if ((hi32
.X_add_number
& 0x80000000) != 0)
3444 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3445 load_register (counter
, reg
, &hi32
, 0);
3448 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3452 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3461 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3463 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3464 (int) BFD_RELOC_HI16
);
3465 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3472 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3477 mid16
.X_add_number
>>= 16;
3478 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3479 freg
, (int) BFD_RELOC_LO16
);
3480 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3484 if ((lo32
.X_add_number
& 0xffff) != 0)
3485 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3486 (int) BFD_RELOC_LO16
);
3489 /* Load an address into a register. */
3492 load_address (counter
, reg
, ep
)
3499 if (ep
->X_op
!= O_constant
3500 && ep
->X_op
!= O_symbol
)
3502 as_bad (_("expression too complex"));
3503 ep
->X_op
= O_constant
;
3506 if (ep
->X_op
== O_constant
)
3508 load_register (counter
, reg
, ep
, 0);
3512 if (mips_pic
== NO_PIC
)
3514 /* If this is a reference to a GP relative symbol, we want
3515 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3517 lui $reg,<sym> (BFD_RELOC_HI16_S)
3518 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3519 If we have an addend, we always use the latter form. */
3520 if ((valueT
) ep
->X_add_number
> MAX_GPREL_OFFSET
3521 || nopic_need_relax (ep
->X_add_symbol
, 1))
3526 macro_build ((char *) NULL
, counter
, ep
,
3527 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3528 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3529 p
= frag_var (rs_machine_dependent
, 8, 0,
3530 RELAX_ENCODE (4, 8, 0, 4, 0,
3531 mips_opts
.warn_about_macros
),
3532 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3534 macro_build_lui (p
, counter
, ep
, reg
);
3537 macro_build (p
, counter
, ep
,
3538 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3539 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3541 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3545 /* If this is a reference to an external symbol, we want
3546 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3548 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3550 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3551 If there is a constant, it must be added in after. */
3552 ex
.X_add_number
= ep
->X_add_number
;
3553 ep
->X_add_number
= 0;
3555 macro_build ((char *) NULL
, counter
, ep
,
3556 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3557 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3558 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3559 p
= frag_var (rs_machine_dependent
, 4, 0,
3560 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3561 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3562 macro_build (p
, counter
, ep
,
3563 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3564 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3565 if (ex
.X_add_number
!= 0)
3567 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3568 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3569 ex
.X_op
= O_constant
;
3570 macro_build ((char *) NULL
, counter
, &ex
,
3571 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3572 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3575 else if (mips_pic
== SVR4_PIC
)
3580 /* This is the large GOT case. If this is a reference to an
3581 external symbol, we want
3582 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3584 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3585 Otherwise, for a reference to a local symbol, we want
3586 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3588 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3589 If there is a constant, it must be added in after. */
3590 ex
.X_add_number
= ep
->X_add_number
;
3591 ep
->X_add_number
= 0;
3592 if (reg_needs_delay (GP
))
3597 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3598 (int) BFD_RELOC_MIPS_GOT_HI16
);
3599 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3600 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3601 "d,v,t", reg
, reg
, GP
);
3602 macro_build ((char *) NULL
, counter
, ep
,
3603 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3604 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3605 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3606 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3607 mips_opts
.warn_about_macros
),
3608 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3611 /* We need a nop before loading from $gp. This special
3612 check is required because the lui which starts the main
3613 instruction stream does not refer to $gp, and so will not
3614 insert the nop which may be required. */
3615 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3618 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3619 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3621 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3623 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3624 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3625 if (ex
.X_add_number
!= 0)
3627 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3628 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3629 ex
.X_op
= O_constant
;
3630 macro_build ((char *) NULL
, counter
, &ex
,
3631 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3632 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3635 else if (mips_pic
== EMBEDDED_PIC
)
3638 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3640 macro_build ((char *) NULL
, counter
, ep
,
3641 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3642 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3648 /* Move the contents of register SOURCE into register DEST. */
3651 move_register (counter
, dest
, source
)
3656 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3657 HAVE_32BIT_GPRS
? "addu" : "daddu",
3658 "d,v,t", dest
, source
, 0);
3663 * This routine implements the seemingly endless macro or synthesized
3664 * instructions and addressing modes in the mips assembly language. Many
3665 * of these macros are simple and are similar to each other. These could
3666 * probably be handled by some kind of table or grammer aproach instead of
3667 * this verbose method. Others are not simple macros but are more like
3668 * optimizing code generation.
3669 * One interesting optimization is when several store macros appear
3670 * consecutivly that would load AT with the upper half of the same address.
3671 * The ensuing load upper instructions are ommited. This implies some kind
3672 * of global optimization. We currently only optimize within a single macro.
3673 * For many of the load and store macros if the address is specified as a
3674 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3675 * first load register 'at' with zero and use it as the base register. The
3676 * mips assembler simply uses register $zero. Just one tiny optimization
3681 struct mips_cl_insn
*ip
;
3683 register int treg
, sreg
, dreg
, breg
;
3699 bfd_reloc_code_real_type r
;
3701 int hold_mips_optimize
;
3703 assert (! mips_opts
.mips16
);
3705 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3706 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3707 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3708 mask
= ip
->insn_mo
->mask
;
3710 expr1
.X_op
= O_constant
;
3711 expr1
.X_op_symbol
= NULL
;
3712 expr1
.X_add_symbol
= NULL
;
3713 expr1
.X_add_number
= 1;
3725 mips_emit_delays (true);
3726 ++mips_opts
.noreorder
;
3727 mips_any_noreorder
= 1;
3729 expr1
.X_add_number
= 8;
3730 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3732 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3734 move_register (&icnt
, dreg
, sreg
);
3735 macro_build ((char *) NULL
, &icnt
, NULL
,
3736 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3738 --mips_opts
.noreorder
;
3759 if (imm_expr
.X_op
== O_constant
3760 && imm_expr
.X_add_number
>= -0x8000
3761 && imm_expr
.X_add_number
< 0x8000)
3763 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3764 (int) BFD_RELOC_LO16
);
3767 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3768 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3787 if (imm_expr
.X_op
== O_constant
3788 && imm_expr
.X_add_number
>= 0
3789 && imm_expr
.X_add_number
< 0x10000)
3791 if (mask
!= M_NOR_I
)
3792 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3793 sreg
, (int) BFD_RELOC_LO16
);
3796 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3797 treg
, sreg
, (int) BFD_RELOC_LO16
);
3798 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3804 load_register (&icnt
, AT
, &imm_expr
, 0);
3805 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3822 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3824 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3828 load_register (&icnt
, AT
, &imm_expr
, 0);
3829 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3837 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3838 likely
? "bgezl" : "bgez",
3844 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3845 likely
? "blezl" : "blez",
3849 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3850 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3851 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3857 /* check for > max integer */
3858 maxnum
= 0x7fffffff;
3859 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3866 if (imm_expr
.X_op
== O_constant
3867 && imm_expr
.X_add_number
>= maxnum
3868 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3871 /* result is always false */
3875 as_warn (_("Branch %s is always false (nop)"),
3877 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3882 as_warn (_("Branch likely %s is always false"),
3884 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3889 if (imm_expr
.X_op
!= O_constant
)
3890 as_bad (_("Unsupported large constant"));
3891 imm_expr
.X_add_number
++;
3895 if (mask
== M_BGEL_I
)
3897 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3899 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3900 likely
? "bgezl" : "bgez", "s,p", sreg
);
3903 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3905 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3906 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3909 maxnum
= 0x7fffffff;
3910 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3917 maxnum
= - maxnum
- 1;
3918 if (imm_expr
.X_op
== O_constant
3919 && imm_expr
.X_add_number
<= maxnum
3920 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3923 /* result is always true */
3924 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3925 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3928 set_at (&icnt
, sreg
, 0);
3929 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3930 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3940 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3941 likely
? "beql" : "beq", "s,t,p", 0, treg
);
3944 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3946 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3947 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3955 && imm_expr
.X_op
== O_constant
3956 && imm_expr
.X_add_number
== 0xffffffff))
3958 if (imm_expr
.X_op
!= O_constant
)
3959 as_bad (_("Unsupported large constant"));
3960 imm_expr
.X_add_number
++;
3964 if (mask
== M_BGEUL_I
)
3966 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3968 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3970 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3971 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
3974 set_at (&icnt
, sreg
, 1);
3975 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3976 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3984 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3985 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
3990 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3991 likely
? "bltzl" : "bltz", "s,p", treg
);
3994 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3995 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3996 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4004 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4005 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4010 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4012 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4013 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4021 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4022 likely
? "blezl" : "blez", "s,p", sreg
);
4027 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4028 likely
? "bgezl" : "bgez", "s,p", treg
);
4031 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4033 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4039 maxnum
= 0x7fffffff;
4040 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4047 if (imm_expr
.X_op
== O_constant
4048 && imm_expr
.X_add_number
>= maxnum
4049 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4051 if (imm_expr
.X_op
!= O_constant
)
4052 as_bad (_("Unsupported large constant"));
4053 imm_expr
.X_add_number
++;
4057 if (mask
== M_BLTL_I
)
4059 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4061 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4062 likely
? "bltzl" : "bltz", "s,p", sreg
);
4065 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4068 likely
? "blezl" : "blez", "s,p", sreg
);
4071 set_at (&icnt
, sreg
, 0);
4072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4073 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4081 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4082 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4087 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4089 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4090 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4098 && imm_expr
.X_op
== O_constant
4099 && imm_expr
.X_add_number
== 0xffffffff))
4101 if (imm_expr
.X_op
!= O_constant
)
4102 as_bad (_("Unsupported large constant"));
4103 imm_expr
.X_add_number
++;
4107 if (mask
== M_BLTUL_I
)
4109 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4111 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4113 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4114 likely
? "beql" : "beq",
4118 set_at (&icnt
, sreg
, 1);
4119 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4120 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4128 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4129 likely
? "bltzl" : "bltz", "s,p", sreg
);
4134 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4135 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4138 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4140 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4150 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4151 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4154 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4156 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4157 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4172 as_warn (_("Divide by zero."));
4174 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4176 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4180 mips_emit_delays (true);
4181 ++mips_opts
.noreorder
;
4182 mips_any_noreorder
= 1;
4185 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4186 macro_build ((char *) NULL
, &icnt
, NULL
,
4187 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4191 expr1
.X_add_number
= 8;
4192 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4193 macro_build ((char *) NULL
, &icnt
, NULL
,
4194 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4195 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4197 expr1
.X_add_number
= -1;
4198 macro_build ((char *) NULL
, &icnt
, &expr1
,
4199 dbl
? "daddiu" : "addiu",
4200 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4201 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4202 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4205 expr1
.X_add_number
= 1;
4206 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4207 (int) BFD_RELOC_LO16
);
4208 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4213 expr1
.X_add_number
= 0x80000000;
4214 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4215 (int) BFD_RELOC_HI16
);
4219 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4220 /* We want to close the noreorder block as soon as possible, so
4221 that later insns are available for delay slot filling. */
4222 --mips_opts
.noreorder
;
4226 expr1
.X_add_number
= 8;
4227 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4228 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4230 /* We want to close the noreorder block as soon as possible, so
4231 that later insns are available for delay slot filling. */
4232 --mips_opts
.noreorder
;
4234 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4236 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4275 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4277 as_warn (_("Divide by zero."));
4279 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4281 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4284 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4286 if (strcmp (s2
, "mflo") == 0)
4287 move_register (&icnt
, dreg
, sreg
);
4289 move_register (&icnt
, dreg
, 0);
4292 if (imm_expr
.X_op
== O_constant
4293 && imm_expr
.X_add_number
== -1
4294 && s
[strlen (s
) - 1] != 'u')
4296 if (strcmp (s2
, "mflo") == 0)
4298 macro_build ((char *) NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg",
4302 move_register (&icnt
, dreg
, 0);
4306 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4307 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4308 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4327 mips_emit_delays (true);
4328 ++mips_opts
.noreorder
;
4329 mips_any_noreorder
= 1;
4332 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4333 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4334 /* We want to close the noreorder block as soon as possible, so
4335 that later insns are available for delay slot filling. */
4336 --mips_opts
.noreorder
;
4340 expr1
.X_add_number
= 8;
4341 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4342 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4344 /* We want to close the noreorder block as soon as possible, so
4345 that later insns are available for delay slot filling. */
4346 --mips_opts
.noreorder
;
4347 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4349 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4355 /* Load the address of a symbol into a register. If breg is not
4356 zero, we then add a base register to it. */
4358 /* When generating embedded PIC code, we permit expressions of
4361 where bar is an address in the current section. These are used
4362 when getting the addresses of functions. We don't permit
4363 X_add_number to be non-zero, because if the symbol is
4364 external the relaxing code needs to know that any addend is
4365 purely the offset to X_op_symbol. */
4366 if (mips_pic
== EMBEDDED_PIC
4367 && offset_expr
.X_op
== O_subtract
4368 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4369 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4370 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4372 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4376 && (offset_expr
.X_add_number
== 0
4377 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4379 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4380 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4382 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4383 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4387 if (offset_expr
.X_op
!= O_symbol
4388 && offset_expr
.X_op
!= O_constant
)
4390 as_bad (_("expression too complex"));
4391 offset_expr
.X_op
= O_constant
;
4405 if (offset_expr
.X_op
== O_constant
)
4406 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4407 else if (mips_pic
== NO_PIC
)
4409 /* If this is a reference to an GP relative symbol, we want
4410 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4412 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4413 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4414 If we have a constant, we need two instructions anyhow,
4415 so we may as well always use the latter form. */
4416 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
4417 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4422 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4423 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4424 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4425 p
= frag_var (rs_machine_dependent
, 8, 0,
4426 RELAX_ENCODE (4, 8, 0, 4, 0,
4427 mips_opts
.warn_about_macros
),
4428 offset_expr
.X_add_symbol
, (offsetT
) 0,
4431 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4434 macro_build (p
, &icnt
, &offset_expr
,
4435 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4436 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4438 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4440 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4442 /* If this is a reference to an external symbol, and there
4443 is no constant, we want
4444 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4445 or if tempreg is PIC_CALL_REG
4446 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4447 For a local symbol, we want
4448 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4450 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4452 If we have a small constant, and this is a reference to
4453 an external symbol, we want
4454 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4456 addiu $tempreg,$tempreg,<constant>
4457 For a local symbol, we want the same instruction
4458 sequence, but we output a BFD_RELOC_LO16 reloc on the
4461 If we have a large constant, and this is a reference to
4462 an external symbol, we want
4463 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4464 lui $at,<hiconstant>
4465 addiu $at,$at,<loconstant>
4466 addu $tempreg,$tempreg,$at
4467 For a local symbol, we want the same instruction
4468 sequence, but we output a BFD_RELOC_LO16 reloc on the
4469 addiu instruction. */
4470 expr1
.X_add_number
= offset_expr
.X_add_number
;
4471 offset_expr
.X_add_number
= 0;
4473 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4474 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4475 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4477 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4478 if (expr1
.X_add_number
== 0)
4486 /* We're going to put in an addu instruction using
4487 tempreg, so we may as well insert the nop right
4489 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4493 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4494 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4496 ? mips_opts
.warn_about_macros
4498 offset_expr
.X_add_symbol
, (offsetT
) 0,
4502 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4505 macro_build (p
, &icnt
, &expr1
,
4506 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4507 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4508 /* FIXME: If breg == 0, and the next instruction uses
4509 $tempreg, then if this variant case is used an extra
4510 nop will be generated. */
4512 else if (expr1
.X_add_number
>= -0x8000
4513 && expr1
.X_add_number
< 0x8000)
4515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4517 macro_build ((char *) NULL
, &icnt
, &expr1
,
4518 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4519 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4520 (void) frag_var (rs_machine_dependent
, 0, 0,
4521 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4522 offset_expr
.X_add_symbol
, (offsetT
) 0,
4529 /* If we are going to add in a base register, and the
4530 target register and the base register are the same,
4531 then we are using AT as a temporary register. Since
4532 we want to load the constant into AT, we add our
4533 current AT (from the global offset table) and the
4534 register into the register now, and pretend we were
4535 not using a base register. */
4540 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4543 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4544 "d,v,t", treg
, AT
, breg
);
4550 /* Set mips_optimize around the lui instruction to avoid
4551 inserting an unnecessary nop after the lw. */
4552 hold_mips_optimize
= mips_optimize
;
4554 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4555 mips_optimize
= hold_mips_optimize
;
4557 macro_build ((char *) NULL
, &icnt
, &expr1
,
4558 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4559 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4560 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4561 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4562 "d,v,t", tempreg
, tempreg
, AT
);
4563 (void) frag_var (rs_machine_dependent
, 0, 0,
4564 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4565 offset_expr
.X_add_symbol
, (offsetT
) 0,
4570 else if (mips_pic
== SVR4_PIC
)
4573 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4574 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4576 /* This is the large GOT case. If this is a reference to an
4577 external symbol, and there is no constant, we want
4578 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4579 addu $tempreg,$tempreg,$gp
4580 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4581 or if tempreg is PIC_CALL_REG
4582 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4583 addu $tempreg,$tempreg,$gp
4584 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4585 For a local symbol, we want
4586 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4588 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4590 If we have a small constant, and this is a reference to
4591 an external symbol, we want
4592 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4593 addu $tempreg,$tempreg,$gp
4594 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4596 addiu $tempreg,$tempreg,<constant>
4597 For a local symbol, we want
4598 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4600 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4602 If we have a large constant, and this is a reference to
4603 an external symbol, we want
4604 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4605 addu $tempreg,$tempreg,$gp
4606 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4607 lui $at,<hiconstant>
4608 addiu $at,$at,<loconstant>
4609 addu $tempreg,$tempreg,$at
4610 For a local symbol, we want
4611 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4612 lui $at,<hiconstant>
4613 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4614 addu $tempreg,$tempreg,$at
4616 expr1
.X_add_number
= offset_expr
.X_add_number
;
4617 offset_expr
.X_add_number
= 0;
4619 if (reg_needs_delay (GP
))
4623 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4625 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4626 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4628 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4629 tempreg
, lui_reloc_type
);
4630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4631 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4632 "d,v,t", tempreg
, tempreg
, GP
);
4633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4635 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4636 if (expr1
.X_add_number
== 0)
4644 /* We're going to put in an addu instruction using
4645 tempreg, so we may as well insert the nop right
4647 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4652 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4653 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4656 ? mips_opts
.warn_about_macros
4658 offset_expr
.X_add_symbol
, (offsetT
) 0,
4661 else if (expr1
.X_add_number
>= -0x8000
4662 && expr1
.X_add_number
< 0x8000)
4664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4666 macro_build ((char *) NULL
, &icnt
, &expr1
,
4667 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4668 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4670 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4671 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4673 ? mips_opts
.warn_about_macros
4675 offset_expr
.X_add_symbol
, (offsetT
) 0,
4682 /* If we are going to add in a base register, and the
4683 target register and the base register are the same,
4684 then we are using AT as a temporary register. Since
4685 we want to load the constant into AT, we add our
4686 current AT (from the global offset table) and the
4687 register into the register now, and pretend we were
4688 not using a base register. */
4696 assert (tempreg
== AT
);
4697 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4700 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4701 "d,v,t", treg
, AT
, breg
);
4706 /* Set mips_optimize around the lui instruction to avoid
4707 inserting an unnecessary nop after the lw. */
4708 hold_mips_optimize
= mips_optimize
;
4710 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4711 mips_optimize
= hold_mips_optimize
;
4713 macro_build ((char *) NULL
, &icnt
, &expr1
,
4714 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4715 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4716 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4717 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4718 "d,v,t", dreg
, dreg
, AT
);
4720 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4721 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4724 ? mips_opts
.warn_about_macros
4726 offset_expr
.X_add_symbol
, (offsetT
) 0,
4734 /* This is needed because this instruction uses $gp, but
4735 the first instruction on the main stream does not. */
4736 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4739 macro_build (p
, &icnt
, &offset_expr
,
4741 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4743 if (expr1
.X_add_number
>= -0x8000
4744 && expr1
.X_add_number
< 0x8000)
4746 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4748 macro_build (p
, &icnt
, &expr1
,
4749 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4750 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4751 /* FIXME: If add_number is 0, and there was no base
4752 register, the external symbol case ended with a load,
4753 so if the symbol turns out to not be external, and
4754 the next instruction uses tempreg, an unnecessary nop
4755 will be inserted. */
4761 /* We must add in the base register now, as in the
4762 external symbol case. */
4763 assert (tempreg
== AT
);
4764 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4766 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4767 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4768 "d,v,t", treg
, AT
, breg
);
4771 /* We set breg to 0 because we have arranged to add
4772 it in in both cases. */
4776 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4778 macro_build (p
, &icnt
, &expr1
,
4779 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4780 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4782 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4783 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4784 "d,v,t", tempreg
, tempreg
, AT
);
4788 else if (mips_pic
== EMBEDDED_PIC
)
4791 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4793 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4794 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4795 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4801 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4802 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4803 "d,v,t", treg
, tempreg
, breg
);
4811 /* The j instruction may not be used in PIC code, since it
4812 requires an absolute address. We convert it to a b
4814 if (mips_pic
== NO_PIC
)
4815 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4817 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4820 /* The jal instructions must be handled as macros because when
4821 generating PIC code they expand to multi-instruction
4822 sequences. Normally they are simple instructions. */
4827 if (mips_pic
== NO_PIC
4828 || mips_pic
== EMBEDDED_PIC
)
4829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4831 else if (mips_pic
== SVR4_PIC
)
4833 if (sreg
!= PIC_CALL_REG
)
4834 as_warn (_("MIPS PIC call to register other than $25"));
4836 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4838 if (mips_cprestore_offset
< 0)
4839 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4842 expr1
.X_add_number
= mips_cprestore_offset
;
4843 macro_build ((char *) NULL
, &icnt
, &expr1
,
4844 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4845 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4854 if (mips_pic
== NO_PIC
)
4855 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4856 else if (mips_pic
== SVR4_PIC
)
4858 /* If this is a reference to an external symbol, and we are
4859 using a small GOT, we want
4860 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4864 lw $gp,cprestore($sp)
4865 The cprestore value is set using the .cprestore
4866 pseudo-op. If we are using a big GOT, we want
4867 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4869 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4873 lw $gp,cprestore($sp)
4874 If the symbol is not external, we want
4875 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4877 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4880 lw $gp,cprestore($sp) */
4884 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4885 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4886 "t,o(b)", PIC_CALL_REG
,
4887 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4888 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4890 p
= frag_var (rs_machine_dependent
, 4, 0,
4891 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4892 offset_expr
.X_add_symbol
, (offsetT
) 0,
4899 if (reg_needs_delay (GP
))
4903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4904 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4906 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4907 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4909 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4910 "t,o(b)", PIC_CALL_REG
,
4911 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4914 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4915 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4917 offset_expr
.X_add_symbol
, (offsetT
) 0,
4921 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4924 macro_build (p
, &icnt
, &offset_expr
,
4925 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4926 "t,o(b)", PIC_CALL_REG
,
4927 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4929 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4932 macro_build (p
, &icnt
, &offset_expr
,
4933 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4934 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4935 (int) BFD_RELOC_LO16
);
4936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4937 "jalr", "s", PIC_CALL_REG
);
4938 if (mips_cprestore_offset
< 0)
4939 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4942 if (mips_opts
.noreorder
)
4943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4945 expr1
.X_add_number
= mips_cprestore_offset
;
4946 macro_build ((char *) NULL
, &icnt
, &expr1
,
4947 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4948 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4952 else if (mips_pic
== EMBEDDED_PIC
)
4954 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4955 /* The linker may expand the call to a longer sequence which
4956 uses $at, so we must break rather than return. */
4981 /* Itbl support may require additional care here. */
4986 /* Itbl support may require additional care here. */
4991 /* Itbl support may require additional care here. */
4996 /* Itbl support may require additional care here. */
5008 if (mips_arch
== CPU_R4650
)
5010 as_bad (_("opcode not supported on this processor"));
5014 /* Itbl support may require additional care here. */
5019 /* Itbl support may require additional care here. */
5024 /* Itbl support may require additional care here. */
5044 if (breg
== treg
|| coproc
|| lr
)
5066 /* Itbl support may require additional care here. */
5071 /* Itbl support may require additional care here. */
5076 /* Itbl support may require additional care here. */
5081 /* Itbl support may require additional care here. */
5097 if (mips_arch
== CPU_R4650
)
5099 as_bad (_("opcode not supported on this processor"));
5104 /* Itbl support may require additional care here. */
5108 /* Itbl support may require additional care here. */
5113 /* Itbl support may require additional care here. */
5125 /* Itbl support may require additional care here. */
5126 if (mask
== M_LWC1_AB
5127 || mask
== M_SWC1_AB
5128 || mask
== M_LDC1_AB
5129 || mask
== M_SDC1_AB
5138 if (offset_expr
.X_op
!= O_constant
5139 && offset_expr
.X_op
!= O_symbol
)
5141 as_bad (_("expression too complex"));
5142 offset_expr
.X_op
= O_constant
;
5145 /* A constant expression in PIC code can be handled just as it
5146 is in non PIC code. */
5147 if (mips_pic
== NO_PIC
5148 || offset_expr
.X_op
== O_constant
)
5150 /* If this is a reference to a GP relative symbol, and there
5151 is no base register, we want
5152 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5153 Otherwise, if there is no base register, we want
5154 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5155 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5156 If we have a constant, we need two instructions anyhow,
5157 so we always use the latter form.
5159 If we have a base register, and this is a reference to a
5160 GP relative symbol, we want
5161 addu $tempreg,$breg,$gp
5162 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5164 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5165 addu $tempreg,$tempreg,$breg
5166 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5167 With a constant we always use the latter case. */
5170 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5171 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5176 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5177 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5178 p
= frag_var (rs_machine_dependent
, 8, 0,
5179 RELAX_ENCODE (4, 8, 0, 4, 0,
5180 (mips_opts
.warn_about_macros
5182 && mips_opts
.noat
))),
5183 offset_expr
.X_add_symbol
, (offsetT
) 0,
5187 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5190 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5191 (int) BFD_RELOC_LO16
, tempreg
);
5195 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5196 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5201 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5202 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5203 "d,v,t", tempreg
, breg
, GP
);
5204 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5205 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5206 p
= frag_var (rs_machine_dependent
, 12, 0,
5207 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5208 offset_expr
.X_add_symbol
, (offsetT
) 0,
5211 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5214 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5215 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5216 "d,v,t", tempreg
, tempreg
, breg
);
5219 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5220 (int) BFD_RELOC_LO16
, tempreg
);
5223 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5225 /* If this is a reference to an external symbol, we want
5226 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5228 <op> $treg,0($tempreg)
5230 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5232 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5233 <op> $treg,0($tempreg)
5234 If there is a base register, we add it to $tempreg before
5235 the <op>. If there is a constant, we stick it in the
5236 <op> instruction. We don't handle constants larger than
5237 16 bits, because we have no way to load the upper 16 bits
5238 (actually, we could handle them for the subset of cases
5239 in which we are not using $at). */
5240 assert (offset_expr
.X_op
== O_symbol
);
5241 expr1
.X_add_number
= offset_expr
.X_add_number
;
5242 offset_expr
.X_add_number
= 0;
5243 if (expr1
.X_add_number
< -0x8000
5244 || expr1
.X_add_number
>= 0x8000)
5245 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5247 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5248 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5249 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5251 p
= frag_var (rs_machine_dependent
, 4, 0,
5252 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5253 offset_expr
.X_add_symbol
, (offsetT
) 0,
5255 macro_build (p
, &icnt
, &offset_expr
,
5256 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5257 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5259 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5260 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5261 "d,v,t", tempreg
, tempreg
, breg
);
5262 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5263 (int) BFD_RELOC_LO16
, tempreg
);
5265 else if (mips_pic
== SVR4_PIC
)
5269 /* If this is a reference to an external symbol, we want
5270 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5271 addu $tempreg,$tempreg,$gp
5272 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5273 <op> $treg,0($tempreg)
5275 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5277 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5278 <op> $treg,0($tempreg)
5279 If there is a base register, we add it to $tempreg before
5280 the <op>. If there is a constant, we stick it in the
5281 <op> instruction. We don't handle constants larger than
5282 16 bits, because we have no way to load the upper 16 bits
5283 (actually, we could handle them for the subset of cases
5284 in which we are not using $at). */
5285 assert (offset_expr
.X_op
== O_symbol
);
5286 expr1
.X_add_number
= offset_expr
.X_add_number
;
5287 offset_expr
.X_add_number
= 0;
5288 if (expr1
.X_add_number
< -0x8000
5289 || expr1
.X_add_number
>= 0x8000)
5290 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5291 if (reg_needs_delay (GP
))
5296 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5297 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5299 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5300 "d,v,t", tempreg
, tempreg
, GP
);
5301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5302 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5303 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5305 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5306 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5307 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5310 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5313 macro_build (p
, &icnt
, &offset_expr
,
5314 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5315 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5317 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5319 macro_build (p
, &icnt
, &offset_expr
,
5320 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5321 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5323 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5324 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5325 "d,v,t", tempreg
, tempreg
, breg
);
5326 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5327 (int) BFD_RELOC_LO16
, tempreg
);
5329 else if (mips_pic
== EMBEDDED_PIC
)
5331 /* If there is no base register, we want
5332 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5333 If there is a base register, we want
5334 addu $tempreg,$breg,$gp
5335 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5337 assert (offset_expr
.X_op
== O_symbol
);
5340 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5341 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5347 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5348 "d,v,t", tempreg
, breg
, GP
);
5349 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5350 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5363 load_register (&icnt
, treg
, &imm_expr
, 0);
5367 load_register (&icnt
, treg
, &imm_expr
, 1);
5371 if (imm_expr
.X_op
== O_constant
)
5373 load_register (&icnt
, AT
, &imm_expr
, 0);
5374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5375 "mtc1", "t,G", AT
, treg
);
5380 assert (offset_expr
.X_op
== O_symbol
5381 && strcmp (segment_name (S_GET_SEGMENT
5382 (offset_expr
.X_add_symbol
)),
5384 && offset_expr
.X_add_number
== 0);
5385 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5386 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5391 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5392 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5393 order 32 bits of the value and the low order 32 bits are either
5394 zero or in OFFSET_EXPR. */
5395 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5397 if (HAVE_64BIT_GPRS
)
5398 load_register (&icnt
, treg
, &imm_expr
, 1);
5403 if (target_big_endian
)
5415 load_register (&icnt
, hreg
, &imm_expr
, 0);
5418 if (offset_expr
.X_op
== O_absent
)
5419 move_register (&icnt
, lreg
, 0);
5422 assert (offset_expr
.X_op
== O_constant
);
5423 load_register (&icnt
, lreg
, &offset_expr
, 0);
5430 /* We know that sym is in the .rdata section. First we get the
5431 upper 16 bits of the address. */
5432 if (mips_pic
== NO_PIC
)
5434 /* FIXME: This won't work for a 64 bit address. */
5435 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5437 else if (mips_pic
== SVR4_PIC
)
5439 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5440 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5441 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5443 else if (mips_pic
== EMBEDDED_PIC
)
5445 /* For embedded PIC we pick up the entire address off $gp in
5446 a single instruction. */
5447 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5448 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5449 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5450 offset_expr
.X_op
= O_constant
;
5451 offset_expr
.X_add_number
= 0;
5456 /* Now we load the register(s). */
5457 if (HAVE_64BIT_GPRS
)
5458 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5459 treg
, (int) BFD_RELOC_LO16
, AT
);
5462 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5463 treg
, (int) BFD_RELOC_LO16
, AT
);
5466 /* FIXME: How in the world do we deal with the possible
5468 offset_expr
.X_add_number
+= 4;
5469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5470 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5474 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5475 does not become a variant frag. */
5476 frag_wane (frag_now
);
5482 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5483 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5484 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5485 the value and the low order 32 bits are either zero or in
5487 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5489 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5490 if (HAVE_64BIT_FPRS
)
5492 assert (HAVE_64BIT_GPRS
);
5493 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5494 "dmtc1", "t,S", AT
, treg
);
5498 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5499 "mtc1", "t,G", AT
, treg
+ 1);
5500 if (offset_expr
.X_op
== O_absent
)
5501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5502 "mtc1", "t,G", 0, treg
);
5505 assert (offset_expr
.X_op
== O_constant
);
5506 load_register (&icnt
, AT
, &offset_expr
, 0);
5507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5508 "mtc1", "t,G", AT
, treg
);
5514 assert (offset_expr
.X_op
== O_symbol
5515 && offset_expr
.X_add_number
== 0);
5516 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5517 if (strcmp (s
, ".lit8") == 0)
5519 if (mips_opts
.isa
!= ISA_MIPS1
)
5521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5522 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5526 r
= BFD_RELOC_MIPS_LITERAL
;
5531 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5532 if (mips_pic
== SVR4_PIC
)
5533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5534 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5535 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5538 /* FIXME: This won't work for a 64 bit address. */
5539 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5542 if (mips_opts
.isa
!= ISA_MIPS1
)
5544 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5545 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5547 /* To avoid confusion in tc_gen_reloc, we must ensure
5548 that this does not become a variant frag. */
5549 frag_wane (frag_now
);
5560 if (mips_arch
== CPU_R4650
)
5562 as_bad (_("opcode not supported on this processor"));
5565 /* Even on a big endian machine $fn comes before $fn+1. We have
5566 to adjust when loading from memory. */
5569 assert (mips_opts
.isa
== ISA_MIPS1
);
5570 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5571 target_big_endian
? treg
+ 1 : treg
,
5573 /* FIXME: A possible overflow which I don't know how to deal
5575 offset_expr
.X_add_number
+= 4;
5576 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5577 target_big_endian
? treg
: treg
+ 1,
5580 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5581 does not become a variant frag. */
5582 frag_wane (frag_now
);
5591 * The MIPS assembler seems to check for X_add_number not
5592 * being double aligned and generating:
5595 * addiu at,at,%lo(foo+1)
5598 * But, the resulting address is the same after relocation so why
5599 * generate the extra instruction?
5601 if (mips_arch
== CPU_R4650
)
5603 as_bad (_("opcode not supported on this processor"));
5606 /* Itbl support may require additional care here. */
5608 if (mips_opts
.isa
!= ISA_MIPS1
)
5619 if (mips_arch
== CPU_R4650
)
5621 as_bad (_("opcode not supported on this processor"));
5625 if (mips_opts
.isa
!= ISA_MIPS1
)
5633 /* Itbl support may require additional care here. */
5638 if (HAVE_64BIT_GPRS
)
5649 if (HAVE_64BIT_GPRS
)
5659 if (offset_expr
.X_op
!= O_symbol
5660 && offset_expr
.X_op
!= O_constant
)
5662 as_bad (_("expression too complex"));
5663 offset_expr
.X_op
= O_constant
;
5666 /* Even on a big endian machine $fn comes before $fn+1. We have
5667 to adjust when loading from memory. We set coproc if we must
5668 load $fn+1 first. */
5669 /* Itbl support may require additional care here. */
5670 if (! target_big_endian
)
5673 if (mips_pic
== NO_PIC
5674 || offset_expr
.X_op
== O_constant
)
5676 /* If this is a reference to a GP relative symbol, we want
5677 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5678 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5679 If we have a base register, we use this
5681 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5682 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5683 If this is not a GP relative symbol, we want
5684 lui $at,<sym> (BFD_RELOC_HI16_S)
5685 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5686 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5687 If there is a base register, we add it to $at after the
5688 lui instruction. If there is a constant, we always use
5690 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5691 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5711 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5712 "d,v,t", AT
, breg
, GP
);
5718 /* Itbl support may require additional care here. */
5719 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5720 coproc
? treg
+ 1 : treg
,
5721 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5722 offset_expr
.X_add_number
+= 4;
5724 /* Set mips_optimize to 2 to avoid inserting an
5726 hold_mips_optimize
= mips_optimize
;
5728 /* Itbl support may require additional care here. */
5729 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5730 coproc
? treg
: treg
+ 1,
5731 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5732 mips_optimize
= hold_mips_optimize
;
5734 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5735 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5736 used_at
&& mips_opts
.noat
),
5737 offset_expr
.X_add_symbol
, (offsetT
) 0,
5740 /* We just generated two relocs. When tc_gen_reloc
5741 handles this case, it will skip the first reloc and
5742 handle the second. The second reloc already has an
5743 extra addend of 4, which we added above. We must
5744 subtract it out, and then subtract another 4 to make
5745 the first reloc come out right. The second reloc
5746 will come out right because we are going to add 4 to
5747 offset_expr when we build its instruction below.
5749 If we have a symbol, then we don't want to include
5750 the offset, because it will wind up being included
5751 when we generate the reloc. */
5753 if (offset_expr
.X_op
== O_constant
)
5754 offset_expr
.X_add_number
-= 8;
5757 offset_expr
.X_add_number
= -4;
5758 offset_expr
.X_op
= O_constant
;
5761 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5766 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5767 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5768 "d,v,t", AT
, breg
, AT
);
5772 /* Itbl support may require additional care here. */
5773 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5774 coproc
? treg
+ 1 : treg
,
5775 (int) BFD_RELOC_LO16
, AT
);
5778 /* FIXME: How do we handle overflow here? */
5779 offset_expr
.X_add_number
+= 4;
5780 /* Itbl support may require additional care here. */
5781 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5782 coproc
? treg
: treg
+ 1,
5783 (int) BFD_RELOC_LO16
, AT
);
5785 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5789 /* If this is a reference to an external symbol, we want
5790 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5795 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5797 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5798 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5799 If there is a base register we add it to $at before the
5800 lwc1 instructions. If there is a constant we include it
5801 in the lwc1 instructions. */
5803 expr1
.X_add_number
= offset_expr
.X_add_number
;
5804 offset_expr
.X_add_number
= 0;
5805 if (expr1
.X_add_number
< -0x8000
5806 || expr1
.X_add_number
>= 0x8000 - 4)
5807 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5812 frag_grow (24 + off
);
5813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5814 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5815 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5818 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5819 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5820 "d,v,t", AT
, breg
, AT
);
5821 /* Itbl support may require additional care here. */
5822 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5823 coproc
? treg
+ 1 : treg
,
5824 (int) BFD_RELOC_LO16
, AT
);
5825 expr1
.X_add_number
+= 4;
5827 /* Set mips_optimize to 2 to avoid inserting an undesired
5829 hold_mips_optimize
= mips_optimize
;
5831 /* Itbl support may require additional care here. */
5832 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5833 coproc
? treg
: treg
+ 1,
5834 (int) BFD_RELOC_LO16
, AT
);
5835 mips_optimize
= hold_mips_optimize
;
5837 (void) frag_var (rs_machine_dependent
, 0, 0,
5838 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5839 offset_expr
.X_add_symbol
, (offsetT
) 0,
5842 else if (mips_pic
== SVR4_PIC
)
5846 /* If this is a reference to an external symbol, we want
5847 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5849 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5854 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5856 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5857 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5858 If there is a base register we add it to $at before the
5859 lwc1 instructions. If there is a constant we include it
5860 in the lwc1 instructions. */
5862 expr1
.X_add_number
= offset_expr
.X_add_number
;
5863 offset_expr
.X_add_number
= 0;
5864 if (expr1
.X_add_number
< -0x8000
5865 || expr1
.X_add_number
>= 0x8000 - 4)
5866 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5867 if (reg_needs_delay (GP
))
5876 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5877 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5878 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5879 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5880 "d,v,t", AT
, AT
, GP
);
5881 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5882 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5883 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5884 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5887 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5888 "d,v,t", AT
, breg
, AT
);
5889 /* Itbl support may require additional care here. */
5890 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5891 coproc
? treg
+ 1 : treg
,
5892 (int) BFD_RELOC_LO16
, AT
);
5893 expr1
.X_add_number
+= 4;
5895 /* Set mips_optimize to 2 to avoid inserting an undesired
5897 hold_mips_optimize
= mips_optimize
;
5899 /* Itbl support may require additional care here. */
5900 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5901 coproc
? treg
: treg
+ 1,
5902 (int) BFD_RELOC_LO16
, AT
);
5903 mips_optimize
= hold_mips_optimize
;
5904 expr1
.X_add_number
-= 4;
5906 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5907 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5908 8 + gpdel
+ off
, 1, 0),
5909 offset_expr
.X_add_symbol
, (offsetT
) 0,
5913 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5916 macro_build (p
, &icnt
, &offset_expr
,
5917 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5918 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5920 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5924 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5925 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5926 "d,v,t", AT
, breg
, AT
);
5929 /* Itbl support may require additional care here. */
5930 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5931 coproc
? treg
+ 1 : treg
,
5932 (int) BFD_RELOC_LO16
, AT
);
5934 expr1
.X_add_number
+= 4;
5936 /* Set mips_optimize to 2 to avoid inserting an undesired
5938 hold_mips_optimize
= mips_optimize
;
5940 /* Itbl support may require additional care here. */
5941 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5942 coproc
? treg
: treg
+ 1,
5943 (int) BFD_RELOC_LO16
, AT
);
5944 mips_optimize
= hold_mips_optimize
;
5946 else if (mips_pic
== EMBEDDED_PIC
)
5948 /* If there is no base register, we use
5949 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5950 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5951 If we have a base register, we use
5953 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5954 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5964 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5965 "d,v,t", AT
, breg
, GP
);
5970 /* Itbl support may require additional care here. */
5971 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5972 coproc
? treg
+ 1 : treg
,
5973 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5974 offset_expr
.X_add_number
+= 4;
5975 /* Itbl support may require additional care here. */
5976 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5977 coproc
? treg
: treg
+ 1,
5978 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5994 assert (HAVE_32BIT_ADDRESSES
);
5995 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5996 (int) BFD_RELOC_LO16
, breg
);
5997 offset_expr
.X_add_number
+= 4;
5998 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5999 (int) BFD_RELOC_LO16
, breg
);
6002 /* New code added to support COPZ instructions.
6003 This code builds table entries out of the macros in mip_opcodes.
6004 R4000 uses interlocks to handle coproc delays.
6005 Other chips (like the R3000) require nops to be inserted for delays.
6007 FIXME: Currently, we require that the user handle delays.
6008 In order to fill delay slots for non-interlocked chips,
6009 we must have a way to specify delays based on the coprocessor.
6010 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6011 What are the side-effects of the cop instruction?
6012 What cache support might we have and what are its effects?
6013 Both coprocessor & memory require delays. how long???
6014 What registers are read/set/modified?
6016 If an itbl is provided to interpret cop instructions,
6017 this knowledge can be encoded in the itbl spec. */
6031 /* For now we just do C (same as Cz). The parameter will be
6032 stored in insn_opcode by mips_ip. */
6033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6038 move_register (&icnt
, dreg
, sreg
);
6041 #ifdef LOSING_COMPILER
6043 /* Try and see if this is a new itbl instruction.
6044 This code builds table entries out of the macros in mip_opcodes.
6045 FIXME: For now we just assemble the expression and pass it's
6046 value along as a 32-bit immediate.
6047 We may want to have the assembler assemble this value,
6048 so that we gain the assembler's knowledge of delay slots,
6050 Would it be more efficient to use mask (id) here? */
6051 if (itbl_have_entries
6052 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6054 s
= ip
->insn_mo
->name
;
6056 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6057 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6064 as_warn (_("Macro used $at after \".set noat\""));
6069 struct mips_cl_insn
*ip
;
6071 register int treg
, sreg
, dreg
, breg
;
6087 bfd_reloc_code_real_type r
;
6090 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6091 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6092 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6093 mask
= ip
->insn_mo
->mask
;
6095 expr1
.X_op
= O_constant
;
6096 expr1
.X_op_symbol
= NULL
;
6097 expr1
.X_add_symbol
= NULL
;
6098 expr1
.X_add_number
= 1;
6102 #endif /* LOSING_COMPILER */
6107 macro_build ((char *) NULL
, &icnt
, NULL
,
6108 dbl
? "dmultu" : "multu",
6110 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6116 /* The MIPS assembler some times generates shifts and adds. I'm
6117 not trying to be that fancy. GCC should do this for us
6119 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6120 macro_build ((char *) NULL
, &icnt
, NULL
,
6121 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6122 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6135 mips_emit_delays (true);
6136 ++mips_opts
.noreorder
;
6137 mips_any_noreorder
= 1;
6139 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6140 macro_build ((char *) NULL
, &icnt
, NULL
,
6141 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6142 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6143 macro_build ((char *) NULL
, &icnt
, NULL
,
6144 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6145 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6147 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6150 expr1
.X_add_number
= 8;
6151 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6152 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6153 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6155 --mips_opts
.noreorder
;
6156 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6169 mips_emit_delays (true);
6170 ++mips_opts
.noreorder
;
6171 mips_any_noreorder
= 1;
6173 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6174 macro_build ((char *) NULL
, &icnt
, NULL
,
6175 dbl
? "dmultu" : "multu",
6176 "s,t", sreg
, imm
? AT
: treg
);
6177 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6178 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6180 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6183 expr1
.X_add_number
= 8;
6184 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6185 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6186 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6188 --mips_opts
.noreorder
;
6192 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6193 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6194 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6196 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6200 if (imm_expr
.X_op
!= O_constant
)
6201 as_bad (_("rotate count too large"));
6202 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6203 (int) (imm_expr
.X_add_number
& 0x1f));
6204 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6205 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6206 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6210 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6211 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6212 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6214 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6218 if (imm_expr
.X_op
!= O_constant
)
6219 as_bad (_("rotate count too large"));
6220 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6221 (int) (imm_expr
.X_add_number
& 0x1f));
6222 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6223 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6224 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6228 if (mips_arch
== CPU_R4650
)
6230 as_bad (_("opcode not supported on this processor"));
6233 assert (mips_opts
.isa
== ISA_MIPS1
);
6234 /* Even on a big endian machine $fn comes before $fn+1. We have
6235 to adjust when storing to memory. */
6236 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6237 target_big_endian
? treg
+ 1 : treg
,
6238 (int) BFD_RELOC_LO16
, breg
);
6239 offset_expr
.X_add_number
+= 4;
6240 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6241 target_big_endian
? treg
: treg
+ 1,
6242 (int) BFD_RELOC_LO16
, breg
);
6247 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6248 treg
, (int) BFD_RELOC_LO16
);
6250 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6251 sreg
, (int) BFD_RELOC_LO16
);
6254 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6256 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6257 dreg
, (int) BFD_RELOC_LO16
);
6262 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6264 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6265 sreg
, (int) BFD_RELOC_LO16
);
6270 as_warn (_("Instruction %s: result is always false"),
6272 move_register (&icnt
, dreg
, 0);
6275 if (imm_expr
.X_op
== O_constant
6276 && imm_expr
.X_add_number
>= 0
6277 && imm_expr
.X_add_number
< 0x10000)
6279 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6280 sreg
, (int) BFD_RELOC_LO16
);
6283 else if (imm_expr
.X_op
== O_constant
6284 && imm_expr
.X_add_number
> -0x8000
6285 && imm_expr
.X_add_number
< 0)
6287 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6288 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6289 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6290 "t,r,j", dreg
, sreg
,
6291 (int) BFD_RELOC_LO16
);
6296 load_register (&icnt
, AT
, &imm_expr
, 0);
6297 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6301 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6302 (int) BFD_RELOC_LO16
);
6307 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6313 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6314 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6315 (int) BFD_RELOC_LO16
);
6318 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6320 if (imm_expr
.X_op
== O_constant
6321 && imm_expr
.X_add_number
>= -0x8000
6322 && imm_expr
.X_add_number
< 0x8000)
6324 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6325 mask
== M_SGE_I
? "slti" : "sltiu",
6326 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6331 load_register (&icnt
, AT
, &imm_expr
, 0);
6332 macro_build ((char *) NULL
, &icnt
, NULL
,
6333 mask
== M_SGE_I
? "slt" : "sltu",
6334 "d,v,t", dreg
, sreg
, AT
);
6337 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6338 (int) BFD_RELOC_LO16
);
6343 case M_SGT
: /* sreg > treg <==> treg < sreg */
6349 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6352 case M_SGT_I
: /* sreg > I <==> I < sreg */
6358 load_register (&icnt
, AT
, &imm_expr
, 0);
6359 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6362 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6368 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6369 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6370 (int) BFD_RELOC_LO16
);
6373 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6379 load_register (&icnt
, AT
, &imm_expr
, 0);
6380 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6381 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6382 (int) BFD_RELOC_LO16
);
6386 if (imm_expr
.X_op
== O_constant
6387 && imm_expr
.X_add_number
>= -0x8000
6388 && imm_expr
.X_add_number
< 0x8000)
6390 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6391 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6394 load_register (&icnt
, AT
, &imm_expr
, 0);
6395 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6399 if (imm_expr
.X_op
== O_constant
6400 && imm_expr
.X_add_number
>= -0x8000
6401 && imm_expr
.X_add_number
< 0x8000)
6403 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6404 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6407 load_register (&icnt
, AT
, &imm_expr
, 0);
6408 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6414 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6417 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6421 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6423 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6429 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6431 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6437 as_warn (_("Instruction %s: result is always true"),
6439 macro_build ((char *) NULL
, &icnt
, &expr1
,
6440 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6441 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6444 if (imm_expr
.X_op
== O_constant
6445 && imm_expr
.X_add_number
>= 0
6446 && imm_expr
.X_add_number
< 0x10000)
6448 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6449 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6452 else if (imm_expr
.X_op
== O_constant
6453 && imm_expr
.X_add_number
> -0x8000
6454 && imm_expr
.X_add_number
< 0)
6456 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6457 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6458 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6459 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6464 load_register (&icnt
, AT
, &imm_expr
, 0);
6465 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6469 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6477 if (imm_expr
.X_op
== O_constant
6478 && imm_expr
.X_add_number
> -0x8000
6479 && imm_expr
.X_add_number
<= 0x8000)
6481 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6482 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6483 dbl
? "daddi" : "addi",
6484 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6487 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6488 macro_build ((char *) NULL
, &icnt
, NULL
,
6489 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6495 if (imm_expr
.X_op
== O_constant
6496 && imm_expr
.X_add_number
> -0x8000
6497 && imm_expr
.X_add_number
<= 0x8000)
6499 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6500 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6501 dbl
? "daddiu" : "addiu",
6502 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6505 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6506 macro_build ((char *) NULL
, &icnt
, NULL
,
6507 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6528 load_register (&icnt
, AT
, &imm_expr
, 0);
6529 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6534 assert (mips_opts
.isa
== ISA_MIPS1
);
6535 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6536 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6539 * Is the double cfc1 instruction a bug in the mips assembler;
6540 * or is there a reason for it?
6542 mips_emit_delays (true);
6543 ++mips_opts
.noreorder
;
6544 mips_any_noreorder
= 1;
6545 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6546 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6547 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6548 expr1
.X_add_number
= 3;
6549 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6550 (int) BFD_RELOC_LO16
);
6551 expr1
.X_add_number
= 2;
6552 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6553 (int) BFD_RELOC_LO16
);
6554 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6555 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6556 macro_build ((char *) NULL
, &icnt
, NULL
,
6557 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6558 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6559 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6560 --mips_opts
.noreorder
;
6569 if (offset_expr
.X_add_number
>= 0x7fff)
6570 as_bad (_("operand overflow"));
6571 /* avoid load delay */
6572 if (! target_big_endian
)
6573 offset_expr
.X_add_number
+= 1;
6574 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6575 (int) BFD_RELOC_LO16
, breg
);
6576 if (! target_big_endian
)
6577 offset_expr
.X_add_number
-= 1;
6579 offset_expr
.X_add_number
+= 1;
6580 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6581 (int) BFD_RELOC_LO16
, breg
);
6582 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6583 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6596 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6597 as_bad (_("operand overflow"));
6598 if (! target_big_endian
)
6599 offset_expr
.X_add_number
+= off
;
6600 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6601 (int) BFD_RELOC_LO16
, breg
);
6602 if (! target_big_endian
)
6603 offset_expr
.X_add_number
-= off
;
6605 offset_expr
.X_add_number
+= off
;
6606 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6607 (int) BFD_RELOC_LO16
, breg
);
6620 load_address (&icnt
, AT
, &offset_expr
);
6622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6623 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6624 "d,v,t", AT
, AT
, breg
);
6625 if (! target_big_endian
)
6626 expr1
.X_add_number
= off
;
6628 expr1
.X_add_number
= 0;
6629 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6630 (int) BFD_RELOC_LO16
, AT
);
6631 if (! target_big_endian
)
6632 expr1
.X_add_number
= 0;
6634 expr1
.X_add_number
= off
;
6635 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6636 (int) BFD_RELOC_LO16
, AT
);
6641 load_address (&icnt
, AT
, &offset_expr
);
6643 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6644 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6645 "d,v,t", AT
, AT
, breg
);
6646 if (target_big_endian
)
6647 expr1
.X_add_number
= 0;
6648 macro_build ((char *) NULL
, &icnt
, &expr1
,
6649 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6650 (int) BFD_RELOC_LO16
, AT
);
6651 if (target_big_endian
)
6652 expr1
.X_add_number
= 1;
6654 expr1
.X_add_number
= 0;
6655 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6656 (int) BFD_RELOC_LO16
, AT
);
6657 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6659 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6664 if (offset_expr
.X_add_number
>= 0x7fff)
6665 as_bad (_("operand overflow"));
6666 if (target_big_endian
)
6667 offset_expr
.X_add_number
+= 1;
6668 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6669 (int) BFD_RELOC_LO16
, breg
);
6670 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6671 if (target_big_endian
)
6672 offset_expr
.X_add_number
-= 1;
6674 offset_expr
.X_add_number
+= 1;
6675 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6676 (int) BFD_RELOC_LO16
, breg
);
6689 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6690 as_bad (_("operand overflow"));
6691 if (! target_big_endian
)
6692 offset_expr
.X_add_number
+= off
;
6693 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6694 (int) BFD_RELOC_LO16
, breg
);
6695 if (! target_big_endian
)
6696 offset_expr
.X_add_number
-= off
;
6698 offset_expr
.X_add_number
+= off
;
6699 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6700 (int) BFD_RELOC_LO16
, breg
);
6713 load_address (&icnt
, AT
, &offset_expr
);
6715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6716 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6717 "d,v,t", AT
, AT
, breg
);
6718 if (! target_big_endian
)
6719 expr1
.X_add_number
= off
;
6721 expr1
.X_add_number
= 0;
6722 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6723 (int) BFD_RELOC_LO16
, AT
);
6724 if (! target_big_endian
)
6725 expr1
.X_add_number
= 0;
6727 expr1
.X_add_number
= off
;
6728 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6729 (int) BFD_RELOC_LO16
, AT
);
6733 load_address (&icnt
, AT
, &offset_expr
);
6735 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6736 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6737 "d,v,t", AT
, AT
, breg
);
6738 if (! target_big_endian
)
6739 expr1
.X_add_number
= 0;
6740 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6741 (int) BFD_RELOC_LO16
, AT
);
6742 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6744 if (! target_big_endian
)
6745 expr1
.X_add_number
= 1;
6747 expr1
.X_add_number
= 0;
6748 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6749 (int) BFD_RELOC_LO16
, AT
);
6750 if (! target_big_endian
)
6751 expr1
.X_add_number
= 0;
6753 expr1
.X_add_number
= 1;
6754 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6755 (int) BFD_RELOC_LO16
, AT
);
6756 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6758 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6763 /* FIXME: Check if this is one of the itbl macros, since they
6764 are added dynamically. */
6765 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6769 as_warn (_("Macro used $at after \".set noat\""));
6772 /* Implement macros in mips16 mode. */
6776 struct mips_cl_insn
*ip
;
6779 int xreg
, yreg
, zreg
, tmp
;
6783 const char *s
, *s2
, *s3
;
6785 mask
= ip
->insn_mo
->mask
;
6787 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6788 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6789 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6793 expr1
.X_op
= O_constant
;
6794 expr1
.X_op_symbol
= NULL
;
6795 expr1
.X_add_symbol
= NULL
;
6796 expr1
.X_add_number
= 1;
6815 mips_emit_delays (true);
6816 ++mips_opts
.noreorder
;
6817 mips_any_noreorder
= 1;
6818 macro_build ((char *) NULL
, &icnt
, NULL
,
6819 dbl
? "ddiv" : "div",
6820 "0,x,y", xreg
, yreg
);
6821 expr1
.X_add_number
= 2;
6822 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6823 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6825 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6826 since that causes an overflow. We should do that as well,
6827 but I don't see how to do the comparisons without a temporary
6829 --mips_opts
.noreorder
;
6830 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6849 mips_emit_delays (true);
6850 ++mips_opts
.noreorder
;
6851 mips_any_noreorder
= 1;
6852 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6853 expr1
.X_add_number
= 2;
6854 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6855 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6856 --mips_opts
.noreorder
;
6857 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6863 macro_build ((char *) NULL
, &icnt
, NULL
,
6864 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
6865 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6873 if (imm_expr
.X_op
!= O_constant
)
6874 as_bad (_("Unsupported large constant"));
6875 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6876 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6877 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
6881 if (imm_expr
.X_op
!= O_constant
)
6882 as_bad (_("Unsupported large constant"));
6883 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6884 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6889 if (imm_expr
.X_op
!= O_constant
)
6890 as_bad (_("Unsupported large constant"));
6891 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6892 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6915 goto do_reverse_branch
;
6919 goto do_reverse_branch
;
6931 goto do_reverse_branch
;
6942 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6944 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6971 goto do_addone_branch_i
;
6976 goto do_addone_branch_i
;
6991 goto do_addone_branch_i
;
6998 if (imm_expr
.X_op
!= O_constant
)
6999 as_bad (_("Unsupported large constant"));
7000 ++imm_expr
.X_add_number
;
7003 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7004 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7008 expr1
.X_add_number
= 0;
7009 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7011 move_register (&icnt
, xreg
, yreg
);
7012 expr1
.X_add_number
= 2;
7013 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7015 "neg", "x,w", xreg
, xreg
);
7019 /* For consistency checking, verify that all bits are specified either
7020 by the match/mask part of the instruction definition, or by the
7023 validate_mips_insn (opc
)
7024 const struct mips_opcode
*opc
;
7026 const char *p
= opc
->args
;
7028 unsigned long used_bits
= opc
->mask
;
7030 if ((used_bits
& opc
->match
) != opc
->match
)
7032 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7033 opc
->name
, opc
->args
);
7036 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7043 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7044 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7046 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7047 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7048 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7049 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7051 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7052 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7054 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7056 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7057 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7058 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7059 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7060 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7061 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7062 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7063 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7064 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7065 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7066 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7068 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7069 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7070 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7071 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7073 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7074 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7075 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7076 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7077 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7078 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7079 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7080 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7081 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7084 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7085 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7086 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7088 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7089 c
, opc
->name
, opc
->args
);
7093 if (used_bits
!= 0xffffffff)
7095 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7096 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7102 /* This routine assembles an instruction into its binary format. As a
7103 side effect, it sets one of the global variables imm_reloc or
7104 offset_reloc to the type of relocation to do if one of the operands
7105 is an address expression. */
7110 struct mips_cl_insn
*ip
;
7115 struct mips_opcode
*insn
;
7118 unsigned int lastregno
= 0;
7121 int full_opcode_match
= 1;
7125 /* If the instruction contains a '.', we first try to match an instruction
7126 including the '.'. Then we try again without the '.'. */
7128 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7131 /* If we stopped on whitespace, then replace the whitespace with null for
7132 the call to hash_find. Save the character we replaced just in case we
7133 have to re-parse the instruction. */
7140 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7142 /* If we didn't find the instruction in the opcode table, try again, but
7143 this time with just the instruction up to, but not including the
7147 /* Restore the character we overwrite above (if any). */
7151 /* Scan up to the first '.' or whitespace. */
7153 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7157 /* If we did not find a '.', then we can quit now. */
7160 insn_error
= "unrecognized opcode";
7164 /* Lookup the instruction in the hash table. */
7166 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7168 insn_error
= "unrecognized opcode";
7172 full_opcode_match
= 0;
7180 assert (strcmp (insn
->name
, str
) == 0);
7182 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7187 if (insn
->pinfo
!= INSN_MACRO
)
7189 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7195 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7196 && strcmp (insn
->name
, insn
[1].name
) == 0)
7205 static char buf
[100];
7207 _("opcode not supported on this processor: %s (%s)"),
7208 mips_cpu_to_str (mips_arch
),
7209 mips_isa_to_str (mips_opts
.isa
));
7220 ip
->insn_opcode
= insn
->match
;
7222 for (args
= insn
->args
;; ++args
)
7228 case '\0': /* end of args */
7241 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7245 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7249 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7253 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7259 /* Handle optional base register.
7260 Either the base register is omitted or
7261 we must have a left paren. */
7262 /* This is dependent on the next operand specifier
7263 is a base register specification. */
7264 assert (args
[1] == 'b' || args
[1] == '5'
7265 || args
[1] == '-' || args
[1] == '4');
7269 case ')': /* these must match exactly */
7274 case '<': /* must be at least one digit */
7276 * According to the manual, if the shift amount is greater
7277 * than 31 or less than 0 the the shift amount should be
7278 * mod 32. In reality the mips assembler issues an error.
7279 * We issue a warning and mask out all but the low 5 bits.
7281 my_getExpression (&imm_expr
, s
);
7282 check_absolute_expr (ip
, &imm_expr
);
7283 if ((unsigned long) imm_expr
.X_add_number
> 31)
7285 as_warn (_("Improper shift amount (%ld)"),
7286 (long) imm_expr
.X_add_number
);
7287 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7289 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7290 imm_expr
.X_op
= O_absent
;
7294 case '>': /* shift amount minus 32 */
7295 my_getExpression (&imm_expr
, s
);
7296 check_absolute_expr (ip
, &imm_expr
);
7297 if ((unsigned long) imm_expr
.X_add_number
< 32
7298 || (unsigned long) imm_expr
.X_add_number
> 63)
7300 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7301 imm_expr
.X_op
= O_absent
;
7305 case 'k': /* cache code */
7306 case 'h': /* prefx code */
7307 my_getExpression (&imm_expr
, s
);
7308 check_absolute_expr (ip
, &imm_expr
);
7309 if ((unsigned long) imm_expr
.X_add_number
> 31)
7311 as_warn (_("Invalid value for `%s' (%lu)"),
7313 (unsigned long) imm_expr
.X_add_number
);
7314 imm_expr
.X_add_number
&= 0x1f;
7317 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7319 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7320 imm_expr
.X_op
= O_absent
;
7324 case 'c': /* break code */
7325 my_getExpression (&imm_expr
, s
);
7326 check_absolute_expr (ip
, &imm_expr
);
7327 if ((unsigned) imm_expr
.X_add_number
> 1023)
7329 as_warn (_("Illegal break code (%ld)"),
7330 (long) imm_expr
.X_add_number
);
7331 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7333 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7334 imm_expr
.X_op
= O_absent
;
7338 case 'q': /* lower break code */
7339 my_getExpression (&imm_expr
, s
);
7340 check_absolute_expr (ip
, &imm_expr
);
7341 if ((unsigned) imm_expr
.X_add_number
> 1023)
7343 as_warn (_("Illegal lower break code (%ld)"),
7344 (long) imm_expr
.X_add_number
);
7345 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7347 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7348 imm_expr
.X_op
= O_absent
;
7352 case 'B': /* 20-bit syscall/break code. */
7353 my_getExpression (&imm_expr
, s
);
7354 check_absolute_expr (ip
, &imm_expr
);
7355 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7356 as_warn (_("Illegal 20-bit code (%ld)"),
7357 (long) imm_expr
.X_add_number
);
7358 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7359 imm_expr
.X_op
= O_absent
;
7363 case 'C': /* Coprocessor code */
7364 my_getExpression (&imm_expr
, s
);
7365 check_absolute_expr (ip
, &imm_expr
);
7366 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7368 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7369 (long) imm_expr
.X_add_number
);
7370 imm_expr
.X_add_number
&= ((1<<25) - 1);
7372 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7373 imm_expr
.X_op
= O_absent
;
7377 case 'J': /* 19-bit wait code. */
7378 my_getExpression (&imm_expr
, s
);
7379 check_absolute_expr (ip
, &imm_expr
);
7380 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7381 as_warn (_("Illegal 19-bit code (%ld)"),
7382 (long) imm_expr
.X_add_number
);
7383 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7384 imm_expr
.X_op
= O_absent
;
7388 case 'P': /* Performance register */
7389 my_getExpression (&imm_expr
, s
);
7390 check_absolute_expr (ip
, &imm_expr
);
7391 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7393 as_warn (_("Invalid performance register (%ld)"),
7394 (long) imm_expr
.X_add_number
);
7395 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7397 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7398 imm_expr
.X_op
= O_absent
;
7402 case 'b': /* base register */
7403 case 'd': /* destination register */
7404 case 's': /* source register */
7405 case 't': /* target register */
7406 case 'r': /* both target and source */
7407 case 'v': /* both dest and source */
7408 case 'w': /* both dest and target */
7409 case 'E': /* coprocessor target register */
7410 case 'G': /* coprocessor destination register */
7411 case 'x': /* ignore register name */
7412 case 'z': /* must be zero register */
7413 case 'U': /* destination register (clo/clz). */
7428 while (ISDIGIT (*s
));
7430 as_bad (_("Invalid register number (%d)"), regno
);
7432 else if (*args
== 'E' || *args
== 'G')
7436 if (s
[1] == 'f' && s
[2] == 'p')
7441 else if (s
[1] == 's' && s
[2] == 'p')
7446 else if (s
[1] == 'g' && s
[2] == 'p')
7451 else if (s
[1] == 'a' && s
[2] == 't')
7456 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7461 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7466 else if (itbl_have_entries
)
7471 p
= s
+ 1; /* advance past '$' */
7472 n
= itbl_get_field (&p
); /* n is name */
7474 /* See if this is a register defined in an
7476 if (itbl_get_reg_val (n
, &r
))
7478 /* Get_field advances to the start of
7479 the next field, so we need to back
7480 rack to the end of the last field. */
7484 s
= strchr (s
, '\0');
7497 as_warn (_("Used $at without \".set noat\""));
7503 if (c
== 'r' || c
== 'v' || c
== 'w')
7510 /* 'z' only matches $0. */
7511 if (c
== 'z' && regno
!= 0)
7514 /* Now that we have assembled one operand, we use the args string
7515 * to figure out where it goes in the instruction. */
7522 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7526 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7529 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7530 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7535 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7538 /* This case exists because on the r3000 trunc
7539 expands into a macro which requires a gp
7540 register. On the r6000 or r4000 it is
7541 assembled into a single instruction which
7542 ignores the register. Thus the insn version
7543 is MIPS_ISA2 and uses 'x', and the macro
7544 version is MIPS_ISA1 and uses 't'. */
7547 /* This case is for the div instruction, which
7548 acts differently if the destination argument
7549 is $0. This only matches $0, and is checked
7550 outside the switch. */
7553 /* Itbl operand; not yet implemented. FIXME ?? */
7555 /* What about all other operands like 'i', which
7556 can be specified in the opcode table? */
7566 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7569 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7574 case 'D': /* floating point destination register */
7575 case 'S': /* floating point source register */
7576 case 'T': /* floating point target register */
7577 case 'R': /* floating point source register */
7581 if (s
[0] == '$' && s
[1] == 'f'
7592 while (ISDIGIT (*s
));
7595 as_bad (_("Invalid float register number (%d)"), regno
);
7597 if ((regno
& 1) != 0
7599 && ! (strcmp (str
, "mtc1") == 0
7600 || strcmp (str
, "mfc1") == 0
7601 || strcmp (str
, "lwc1") == 0
7602 || strcmp (str
, "swc1") == 0
7603 || strcmp (str
, "l.s") == 0
7604 || strcmp (str
, "s.s") == 0))
7605 as_warn (_("Float register should be even, was %d"),
7613 if (c
== 'V' || c
== 'W')
7623 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7627 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7631 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7634 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
7644 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7647 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7653 my_getExpression (&imm_expr
, s
);
7654 if (imm_expr
.X_op
!= O_big
7655 && imm_expr
.X_op
!= O_constant
)
7656 insn_error
= _("absolute expression required");
7661 my_getExpression (&offset_expr
, s
);
7662 *imm_reloc
= BFD_RELOC_32
;
7675 unsigned char temp
[8];
7677 unsigned int length
;
7682 /* These only appear as the last operand in an
7683 instruction, and every instruction that accepts
7684 them in any variant accepts them in all variants.
7685 This means we don't have to worry about backing out
7686 any changes if the instruction does not match.
7688 The difference between them is the size of the
7689 floating point constant and where it goes. For 'F'
7690 and 'L' the constant is 64 bits; for 'f' and 'l' it
7691 is 32 bits. Where the constant is placed is based
7692 on how the MIPS assembler does things:
7695 f -- immediate value
7698 The .lit4 and .lit8 sections are only used if
7699 permitted by the -G argument.
7701 When generating embedded PIC code, we use the
7702 .lit8 section but not the .lit4 section (we can do
7703 .lit4 inline easily; we need to put .lit8
7704 somewhere in the data segment, and using .lit8
7705 permits the linker to eventually combine identical
7708 The code below needs to know whether the target register
7709 is 32 or 64 bits wide. It relies on the fact 'f' and
7710 'F' are used with GPR-based instructions and 'l' and
7711 'L' are used with FPR-based instructions. */
7713 f64
= *args
== 'F' || *args
== 'L';
7714 using_gprs
= *args
== 'F' || *args
== 'f';
7716 save_in
= input_line_pointer
;
7717 input_line_pointer
= s
;
7718 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7720 s
= input_line_pointer
;
7721 input_line_pointer
= save_in
;
7722 if (err
!= NULL
&& *err
!= '\0')
7724 as_bad (_("Bad floating point constant: %s"), err
);
7725 memset (temp
, '\0', sizeof temp
);
7726 length
= f64
? 8 : 4;
7729 assert (length
== (unsigned) (f64
? 8 : 4));
7733 && (! USE_GLOBAL_POINTER_OPT
7734 || mips_pic
== EMBEDDED_PIC
7735 || g_switch_value
< 4
7736 || (temp
[0] == 0 && temp
[1] == 0)
7737 || (temp
[2] == 0 && temp
[3] == 0))))
7739 imm_expr
.X_op
= O_constant
;
7740 if (! target_big_endian
)
7741 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7743 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7746 && ! mips_disable_float_construction
7747 /* Constants can only be constructed in GPRs and
7748 copied to FPRs if the GPRs are at least as wide
7749 as the FPRs. Force the constant into memory if
7750 we are using 64-bit FPRs but the GPRs are only
7753 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
7754 && ((temp
[0] == 0 && temp
[1] == 0)
7755 || (temp
[2] == 0 && temp
[3] == 0))
7756 && ((temp
[4] == 0 && temp
[5] == 0)
7757 || (temp
[6] == 0 && temp
[7] == 0)))
7759 /* The value is simple enough to load with a couple of
7760 instructions. If using 32-bit registers, set
7761 imm_expr to the high order 32 bits and offset_expr to
7762 the low order 32 bits. Otherwise, set imm_expr to
7763 the entire 64 bit constant. */
7764 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
7766 imm_expr
.X_op
= O_constant
;
7767 offset_expr
.X_op
= O_constant
;
7768 if (! target_big_endian
)
7770 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7771 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7775 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7776 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7778 if (offset_expr
.X_add_number
== 0)
7779 offset_expr
.X_op
= O_absent
;
7781 else if (sizeof (imm_expr
.X_add_number
) > 4)
7783 imm_expr
.X_op
= O_constant
;
7784 if (! target_big_endian
)
7785 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7787 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7791 imm_expr
.X_op
= O_big
;
7792 imm_expr
.X_add_number
= 4;
7793 if (! target_big_endian
)
7795 generic_bignum
[0] = bfd_getl16 (temp
);
7796 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7797 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7798 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7802 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7803 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7804 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7805 generic_bignum
[3] = bfd_getb16 (temp
);
7811 const char *newname
;
7814 /* Switch to the right section. */
7816 subseg
= now_subseg
;
7819 default: /* unused default case avoids warnings. */
7821 newname
= RDATA_SECTION_NAME
;
7822 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7823 || mips_pic
== EMBEDDED_PIC
)
7827 if (mips_pic
== EMBEDDED_PIC
)
7830 newname
= RDATA_SECTION_NAME
;
7833 assert (!USE_GLOBAL_POINTER_OPT
7834 || g_switch_value
>= 4);
7838 new_seg
= subseg_new (newname
, (subsegT
) 0);
7839 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7840 bfd_set_section_flags (stdoutput
, new_seg
,
7845 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7846 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7847 && strcmp (TARGET_OS
, "elf") != 0)
7848 record_alignment (new_seg
, 4);
7850 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7852 as_bad (_("Can't use floating point insn in this section"));
7854 /* Set the argument to the current address in the
7856 offset_expr
.X_op
= O_symbol
;
7857 offset_expr
.X_add_symbol
=
7858 symbol_new ("L0\001", now_seg
,
7859 (valueT
) frag_now_fix (), frag_now
);
7860 offset_expr
.X_add_number
= 0;
7862 /* Put the floating point number into the section. */
7863 p
= frag_more ((int) length
);
7864 memcpy (p
, temp
, length
);
7866 /* Switch back to the original section. */
7867 subseg_set (seg
, subseg
);
7872 case 'i': /* 16 bit unsigned immediate */
7873 case 'j': /* 16 bit signed immediate */
7874 *imm_reloc
= BFD_RELOC_LO16
;
7875 c
= my_getSmallExpression (&imm_expr
, s
);
7880 if (imm_expr
.X_op
== O_constant
)
7881 imm_expr
.X_add_number
=
7882 (imm_expr
.X_add_number
>> 16) & 0xffff;
7883 else if (c
== S_EX_HIGHEST
)
7884 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
7885 else if (c
== S_EX_HIGHER
)
7886 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
7887 else if (c
== S_EX_HI
)
7889 *imm_reloc
= BFD_RELOC_HI16_S
;
7890 imm_unmatched_hi
= true;
7893 *imm_reloc
= BFD_RELOC_HI16
;
7895 else if (imm_expr
.X_op
== O_constant
)
7896 imm_expr
.X_add_number
&= 0xffff;
7900 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
7901 || ((imm_expr
.X_add_number
< 0
7902 || imm_expr
.X_add_number
>= 0x10000)
7903 && imm_expr
.X_op
== O_constant
))
7905 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7906 !strcmp (insn
->name
, insn
[1].name
))
7908 if (imm_expr
.X_op
== O_constant
7909 || imm_expr
.X_op
== O_big
)
7910 as_bad (_("16 bit expression not in range 0..65535"));
7918 /* The upper bound should be 0x8000, but
7919 unfortunately the MIPS assembler accepts numbers
7920 from 0x8000 to 0xffff and sign extends them, and
7921 we want to be compatible. We only permit this
7922 extended range for an instruction which does not
7923 provide any further alternates, since those
7924 alternates may handle other cases. People should
7925 use the numbers they mean, rather than relying on
7926 a mysterious sign extension. */
7927 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7928 strcmp (insn
->name
, insn
[1].name
) == 0);
7933 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
7934 || ((imm_expr
.X_add_number
< -0x8000
7935 || imm_expr
.X_add_number
>= max
)
7936 && imm_expr
.X_op
== O_constant
)
7938 && imm_expr
.X_add_number
< 0
7940 && imm_expr
.X_unsigned
7941 && sizeof (imm_expr
.X_add_number
) <= 4))
7945 if (imm_expr
.X_op
== O_constant
7946 || imm_expr
.X_op
== O_big
)
7947 as_bad (_("16 bit expression not in range -32768..32767"));
7953 case 'o': /* 16 bit offset */
7954 c
= my_getSmallExpression (&offset_expr
, s
);
7956 /* If this value won't fit into a 16 bit offset, then go
7957 find a macro that will generate the 32 bit offset
7958 code pattern. As a special hack, we accept the
7959 difference of two local symbols as a constant. This
7960 is required to suppose embedded PIC switches, which
7961 use an instruction which looks like
7962 lw $4,$L12-$LS12($4)
7963 The problem with handling this in a more general
7964 fashion is that the macro function doesn't expect to
7965 see anything which can be handled in a single
7966 constant instruction. */
7968 && (offset_expr
.X_op
!= O_constant
7969 || offset_expr
.X_add_number
>= 0x8000
7970 || offset_expr
.X_add_number
< -0x8000)
7971 && (mips_pic
!= EMBEDDED_PIC
7972 || offset_expr
.X_op
!= O_subtract
7973 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7974 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7979 if (offset_expr
.X_op
!= O_constant
)
7981 offset_expr
.X_add_number
=
7982 (offset_expr
.X_add_number
>> 16) & 0xffff;
7984 *offset_reloc
= BFD_RELOC_LO16
;
7988 case 'p': /* pc relative offset */
7989 if (mips_pic
== EMBEDDED_PIC
)
7990 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7992 *offset_reloc
= BFD_RELOC_16_PCREL
;
7993 my_getExpression (&offset_expr
, s
);
7997 case 'u': /* upper 16 bits */
7998 c
= my_getSmallExpression (&imm_expr
, s
);
7999 *imm_reloc
= BFD_RELOC_LO16
;
8004 if (imm_expr
.X_op
== O_constant
)
8005 imm_expr
.X_add_number
=
8006 (imm_expr
.X_add_number
>> 16) & 0xffff;
8007 else if (c
== S_EX_HIGHEST
)
8008 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8009 else if (c
== S_EX_HI
)
8011 *imm_reloc
= BFD_RELOC_HI16_S
;
8012 imm_unmatched_hi
= true;
8015 *imm_reloc
= BFD_RELOC_HI16
;
8017 else if (imm_expr
.X_op
== O_constant
)
8018 imm_expr
.X_add_number
&= 0xffff;
8020 if (imm_expr
.X_op
== O_constant
8021 && (imm_expr
.X_add_number
< 0
8022 || imm_expr
.X_add_number
>= 0x10000))
8023 as_bad (_("lui expression not in range 0..65535"));
8027 case 'a': /* 26 bit address */
8028 my_getExpression (&offset_expr
, s
);
8030 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8033 case 'N': /* 3 bit branch condition code */
8034 case 'M': /* 3 bit compare condition code */
8035 if (strncmp (s
, "$fcc", 4) != 0)
8045 while (ISDIGIT (*s
));
8047 as_bad (_("invalid condition code register $fcc%d"), regno
);
8049 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8051 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8055 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8066 while (ISDIGIT (*s
));
8069 c
= 8; /* Invalid sel value. */
8072 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8073 ip
->insn_opcode
|= c
;
8077 as_bad (_("bad char = '%c'\n"), *args
);
8082 /* Args don't match. */
8083 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8084 !strcmp (insn
->name
, insn
[1].name
))
8088 insn_error
= _("illegal operands");
8093 insn_error
= _("illegal operands");
8098 /* This routine assembles an instruction into its binary format when
8099 assembling for the mips16. As a side effect, it sets one of the
8100 global variables imm_reloc or offset_reloc to the type of
8101 relocation to do if one of the operands is an address expression.
8102 It also sets mips16_small and mips16_ext if the user explicitly
8103 requested a small or extended instruction. */
8108 struct mips_cl_insn
*ip
;
8112 struct mips_opcode
*insn
;
8115 unsigned int lastregno
= 0;
8120 mips16_small
= false;
8123 for (s
= str
; ISLOWER (*s
); ++s
)
8135 if (s
[1] == 't' && s
[2] == ' ')
8138 mips16_small
= true;
8142 else if (s
[1] == 'e' && s
[2] == ' ')
8151 insn_error
= _("unknown opcode");
8155 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8156 mips16_small
= true;
8158 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8160 insn_error
= _("unrecognized opcode");
8167 assert (strcmp (insn
->name
, str
) == 0);
8170 ip
->insn_opcode
= insn
->match
;
8171 ip
->use_extend
= false;
8172 imm_expr
.X_op
= O_absent
;
8173 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8174 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8175 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8176 offset_expr
.X_op
= O_absent
;
8177 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8178 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8179 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8180 for (args
= insn
->args
; 1; ++args
)
8187 /* In this switch statement we call break if we did not find
8188 a match, continue if we did find a match, or return if we
8197 /* Stuff the immediate value in now, if we can. */
8198 if (imm_expr
.X_op
== O_constant
8199 && *imm_reloc
> BFD_RELOC_UNUSED
8200 && insn
->pinfo
!= INSN_MACRO
)
8202 mips16_immed ((char *) NULL
, 0,
8203 *imm_reloc
- BFD_RELOC_UNUSED
,
8204 imm_expr
.X_add_number
, true, mips16_small
,
8205 mips16_ext
, &ip
->insn_opcode
,
8206 &ip
->use_extend
, &ip
->extend
);
8207 imm_expr
.X_op
= O_absent
;
8208 *imm_reloc
= BFD_RELOC_UNUSED
;
8222 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8225 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8241 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8243 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8270 while (ISDIGIT (*s
));
8273 as_bad (_("invalid register number (%d)"), regno
);
8279 if (s
[1] == 'f' && s
[2] == 'p')
8284 else if (s
[1] == 's' && s
[2] == 'p')
8289 else if (s
[1] == 'g' && s
[2] == 'p')
8294 else if (s
[1] == 'a' && s
[2] == 't')
8299 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8304 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8317 if (c
== 'v' || c
== 'w')
8319 regno
= mips16_to_32_reg_map
[lastregno
];
8333 regno
= mips32_to_16_reg_map
[regno
];
8338 regno
= ILLEGAL_REG
;
8343 regno
= ILLEGAL_REG
;
8348 regno
= ILLEGAL_REG
;
8353 if (regno
== AT
&& ! mips_opts
.noat
)
8354 as_warn (_("used $at without \".set noat\""));
8361 if (regno
== ILLEGAL_REG
)
8368 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8372 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8375 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8378 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8384 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8387 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8388 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8398 if (strncmp (s
, "$pc", 3) == 0)
8422 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8424 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8425 and generate the appropriate reloc. If the text
8426 inside %gprel is not a symbol name with an
8427 optional offset, then we generate a normal reloc
8428 and will probably fail later. */
8429 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8430 if (imm_expr
.X_op
== O_symbol
)
8433 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8435 ip
->use_extend
= true;
8442 /* Just pick up a normal expression. */
8443 my_getExpression (&imm_expr
, s
);
8446 if (imm_expr
.X_op
== O_register
)
8448 /* What we thought was an expression turned out to
8451 if (s
[0] == '(' && args
[1] == '(')
8453 /* It looks like the expression was omitted
8454 before a register indirection, which means
8455 that the expression is implicitly zero. We
8456 still set up imm_expr, so that we handle
8457 explicit extensions correctly. */
8458 imm_expr
.X_op
= O_constant
;
8459 imm_expr
.X_add_number
= 0;
8460 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8467 /* We need to relax this instruction. */
8468 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8477 /* We use offset_reloc rather than imm_reloc for the PC
8478 relative operands. This lets macros with both
8479 immediate and address operands work correctly. */
8480 my_getExpression (&offset_expr
, s
);
8482 if (offset_expr
.X_op
== O_register
)
8485 /* We need to relax this instruction. */
8486 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8490 case '6': /* break code */
8491 my_getExpression (&imm_expr
, s
);
8492 check_absolute_expr (ip
, &imm_expr
);
8493 if ((unsigned long) imm_expr
.X_add_number
> 63)
8495 as_warn (_("Invalid value for `%s' (%lu)"),
8497 (unsigned long) imm_expr
.X_add_number
);
8498 imm_expr
.X_add_number
&= 0x3f;
8500 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8501 imm_expr
.X_op
= O_absent
;
8505 case 'a': /* 26 bit address */
8506 my_getExpression (&offset_expr
, s
);
8508 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8509 ip
->insn_opcode
<<= 16;
8512 case 'l': /* register list for entry macro */
8513 case 'L': /* register list for exit macro */
8523 int freg
, reg1
, reg2
;
8525 while (*s
== ' ' || *s
== ',')
8529 as_bad (_("can't parse register list"));
8541 while (ISDIGIT (*s
))
8563 as_bad (_("invalid register list"));
8568 while (ISDIGIT (*s
))
8575 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8580 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8585 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8586 mask
|= (reg2
- 3) << 3;
8587 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8588 mask
|= (reg2
- 15) << 1;
8589 else if (reg1
== 31 && reg2
== 31)
8593 as_bad (_("invalid register list"));
8597 /* The mask is filled in in the opcode table for the
8598 benefit of the disassembler. We remove it before
8599 applying the actual mask. */
8600 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8601 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8605 case 'e': /* extend code */
8606 my_getExpression (&imm_expr
, s
);
8607 check_absolute_expr (ip
, &imm_expr
);
8608 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8610 as_warn (_("Invalid value for `%s' (%lu)"),
8612 (unsigned long) imm_expr
.X_add_number
);
8613 imm_expr
.X_add_number
&= 0x7ff;
8615 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8616 imm_expr
.X_op
= O_absent
;
8626 /* Args don't match. */
8627 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8628 strcmp (insn
->name
, insn
[1].name
) == 0)
8635 insn_error
= _("illegal operands");
8641 /* This structure holds information we know about a mips16 immediate
8644 struct mips16_immed_operand
8646 /* The type code used in the argument string in the opcode table. */
8648 /* The number of bits in the short form of the opcode. */
8650 /* The number of bits in the extended form of the opcode. */
8652 /* The amount by which the short form is shifted when it is used;
8653 for example, the sw instruction has a shift count of 2. */
8655 /* The amount by which the short form is shifted when it is stored
8656 into the instruction code. */
8658 /* Non-zero if the short form is unsigned. */
8660 /* Non-zero if the extended form is unsigned. */
8662 /* Non-zero if the value is PC relative. */
8666 /* The mips16 immediate operand types. */
8668 static const struct mips16_immed_operand mips16_immed_operands
[] =
8670 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8671 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8672 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8673 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8674 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8675 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8676 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8677 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8678 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8679 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8680 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8681 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8682 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8683 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8684 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8685 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8686 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8687 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8688 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8689 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8690 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8693 #define MIPS16_NUM_IMMED \
8694 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8696 /* Handle a mips16 instruction with an immediate value. This or's the
8697 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8698 whether an extended value is needed; if one is needed, it sets
8699 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8700 If SMALL is true, an unextended opcode was explicitly requested.
8701 If EXT is true, an extended opcode was explicitly requested. If
8702 WARN is true, warn if EXT does not match reality. */
8705 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8714 unsigned long *insn
;
8715 boolean
*use_extend
;
8716 unsigned short *extend
;
8718 register const struct mips16_immed_operand
*op
;
8719 int mintiny
, maxtiny
;
8722 op
= mips16_immed_operands
;
8723 while (op
->type
!= type
)
8726 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8731 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8734 maxtiny
= 1 << op
->nbits
;
8739 maxtiny
= (1 << op
->nbits
) - 1;
8744 mintiny
= - (1 << (op
->nbits
- 1));
8745 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8748 /* Branch offsets have an implicit 0 in the lowest bit. */
8749 if (type
== 'p' || type
== 'q')
8752 if ((val
& ((1 << op
->shift
) - 1)) != 0
8753 || val
< (mintiny
<< op
->shift
)
8754 || val
> (maxtiny
<< op
->shift
))
8759 if (warn
&& ext
&& ! needext
)
8760 as_warn_where (file
, line
,
8761 _("extended operand requested but not required"));
8762 if (small
&& needext
)
8763 as_bad_where (file
, line
, _("invalid unextended operand value"));
8765 if (small
|| (! ext
&& ! needext
))
8769 *use_extend
= false;
8770 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8771 insnval
<<= op
->op_shift
;
8776 long minext
, maxext
;
8782 maxext
= (1 << op
->extbits
) - 1;
8786 minext
= - (1 << (op
->extbits
- 1));
8787 maxext
= (1 << (op
->extbits
- 1)) - 1;
8789 if (val
< minext
|| val
> maxext
)
8790 as_bad_where (file
, line
,
8791 _("operand value out of range for instruction"));
8794 if (op
->extbits
== 16)
8796 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8799 else if (op
->extbits
== 15)
8801 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8806 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8810 *extend
= (unsigned short) extval
;
8817 my_getSmallExpression (ep
, str
)
8829 else if (str
[0] == '%'
8830 && TOLOWER (str
[1]) == 'l'
8831 && TOLOWER (str
[2]) == 'o'
8835 str
+= sizeof ("%lo(") - 2;
8837 else if (str
[0] == '%'
8838 && TOLOWER (str
[1]) == 'h'
8839 && TOLOWER (str
[2]) == 'i'
8843 str
+= sizeof ("%hi(") - 2;
8845 else if (str
[0] == '%'
8846 && TOLOWER (str
[1]) == 'h'
8847 && TOLOWER (str
[2]) == 'i'
8848 && TOLOWER (str
[3]) == 'g'
8849 && TOLOWER (str
[4]) == 'h'
8850 && TOLOWER (str
[5]) == 'e'
8851 && TOLOWER (str
[6]) == 'r'
8855 str
+= sizeof ("%higher(") - 2;
8857 else if (str
[0] == '%'
8858 && TOLOWER (str
[1]) == 'h'
8859 && TOLOWER (str
[2]) == 'i'
8860 && TOLOWER (str
[3]) == 'g'
8861 && TOLOWER (str
[4]) == 'h'
8862 && TOLOWER (str
[5]) == 'e'
8863 && TOLOWER (str
[6]) == 's'
8864 && TOLOWER (str
[7]) == 't'
8868 str
+= sizeof ("%highest(") - 2;
8870 /* currently unsupported */
8872 else if (str
[0] == '%'
8873 && TOLOWER (str
[1]) == 'g'
8874 && TOLOWER (str
[2]) == 'p'
8875 && TOLOWER (str
[3]) == '_'
8876 && TOLOWER (str
[4]) == 'r'
8877 && TOLOWER (str
[5]) == 'e'
8878 && TOLOWER (str
[6]) == 'l'
8882 str
+= sizeof ("%gp_rel(") - 2;
8884 else if (str
[0] == '%'
8885 && TOLOWER (str
[1]) == 'n'
8886 && TOLOWER (str
[2]) == 'e'
8887 && TOLOWER (str
[3]) == 'g'
8891 str
+= sizeof ("%neg(") - 2;
8896 my_getExpression (ep
, str
);
8901 * A small expression may be followed by a base register.
8902 * Scan to the end of this operand, and then back over a possible
8903 * base register. Then scan the small expression up to that
8904 * point. (Based on code in sparc.c...)
8906 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8908 if (sp
- 4 >= str
&& sp
[-1] == ')')
8910 if (ISDIGIT (sp
[-2]))
8912 for (sp
-= 3; sp
>= str
&& ISDIGIT (*sp
); sp
--)
8914 if (*sp
== '$' && sp
> str
&& sp
[-1] == '(')
8920 else if (sp
- 5 >= str
8923 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8924 || (sp
[-3] == 's' && sp
[-2] == 'p')
8925 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8926 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8932 /* no expression means zero offset */
8935 /* %xx(reg) is an error */
8936 ep
->X_op
= O_absent
;
8941 ep
->X_op
= O_constant
;
8944 ep
->X_add_symbol
= NULL
;
8945 ep
->X_op_symbol
= NULL
;
8946 ep
->X_add_number
= 0;
8951 my_getExpression (ep
, str
);
8957 my_getExpression (ep
, str
);
8959 /* => %highest, %higher, %hi, %lo, %gprel, %neg encountered */
8964 my_getExpression (ep
, str
)
8971 save_in
= input_line_pointer
;
8972 input_line_pointer
= str
;
8974 expr_end
= input_line_pointer
;
8975 input_line_pointer
= save_in
;
8977 /* If we are in mips16 mode, and this is an expression based on `.',
8978 then we bump the value of the symbol by 1 since that is how other
8979 text symbols are handled. We don't bother to handle complex
8980 expressions, just `.' plus or minus a constant. */
8981 if (mips_opts
.mips16
8982 && ep
->X_op
== O_symbol
8983 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8984 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8985 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8986 && symbol_constant_p (ep
->X_add_symbol
)
8987 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
8988 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
8991 /* Turn a string in input_line_pointer into a floating point constant
8992 of type TYPE, and store the appropriate bytes in *LITP. The number
8993 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8994 returned, or NULL on OK. */
8997 md_atof (type
, litP
, sizeP
)
9003 LITTLENUM_TYPE words
[4];
9019 return _("bad call to md_atof");
9022 t
= atof_ieee (input_line_pointer
, type
, words
);
9024 input_line_pointer
= t
;
9028 if (! target_big_endian
)
9030 for (i
= prec
- 1; i
>= 0; i
--)
9032 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9038 for (i
= 0; i
< prec
; i
++)
9040 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9049 md_number_to_chars (buf
, val
, n
)
9054 if (target_big_endian
)
9055 number_to_chars_bigendian (buf
, val
, n
);
9057 number_to_chars_littleendian (buf
, val
, n
);
9060 static int support_64bit_objects(void)
9062 const char **list
, **l
;
9064 list
= bfd_target_list ();
9065 for (l
= list
; *l
!= NULL
; l
++)
9067 /* This is traditional mips */
9068 if (strcmp (*l
, "elf64-tradbigmips") == 0
9069 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9071 if (strcmp (*l
, "elf64-bigmips") == 0
9072 || strcmp (*l
, "elf64-littlemips") == 0)
9076 return (*l
!= NULL
);
9079 CONST
char *md_shortopts
= "nO::g::G:";
9081 struct option md_longopts
[] =
9083 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9084 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9085 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9086 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9087 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9088 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9089 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9090 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9091 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9092 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9093 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9094 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9095 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9096 #define OPTION_TRAP (OPTION_MD_BASE + 7)
9097 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9098 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9099 #define OPTION_BREAK (OPTION_MD_BASE + 8)
9100 {"break", no_argument
, NULL
, OPTION_BREAK
},
9101 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9102 #define OPTION_EB (OPTION_MD_BASE + 9)
9103 {"EB", no_argument
, NULL
, OPTION_EB
},
9104 #define OPTION_EL (OPTION_MD_BASE + 10)
9105 {"EL", no_argument
, NULL
, OPTION_EL
},
9106 #define OPTION_M4650 (OPTION_MD_BASE + 11)
9107 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9108 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
9109 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9110 #define OPTION_M4010 (OPTION_MD_BASE + 13)
9111 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9112 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
9113 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9114 #define OPTION_M4100 (OPTION_MD_BASE + 15)
9115 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9116 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
9117 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9118 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
9119 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9120 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
9121 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9122 #define OPTION_M3900 (OPTION_MD_BASE + 19)
9123 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9124 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
9125 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9126 #define OPTION_MABI (OPTION_MD_BASE + 21)
9127 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9128 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
9129 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9130 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
9131 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9132 #define OPTION_GP32 (OPTION_MD_BASE + 24)
9133 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9134 #define OPTION_GP64 (OPTION_MD_BASE + 25)
9135 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9136 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
9137 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9138 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
9139 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9140 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
9141 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9142 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
9143 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9144 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
9145 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9146 #define OPTION_MARCH (OPTION_MD_BASE + 31)
9147 {"march", required_argument
, NULL
, OPTION_MARCH
},
9148 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
9149 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9150 #define OPTION_FP32 (OPTION_MD_BASE + 33)
9151 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9153 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9154 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9155 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9156 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9157 #define OPTION_32 (OPTION_ELF_BASE + 3)
9158 #define OPTION_N32 (OPTION_ELF_BASE + 4)
9159 #define OPTION_64 (OPTION_ELF_BASE + 5)
9160 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9161 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9162 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9163 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9164 {"32", no_argument
, NULL
, OPTION_32
},
9165 {"n32", no_argument
, NULL
, OPTION_N32
},
9166 {"64", no_argument
, NULL
, OPTION_64
},
9169 {NULL
, no_argument
, NULL
, 0}
9171 size_t md_longopts_size
= sizeof (md_longopts
);
9174 md_parse_option (c
, arg
)
9180 case OPTION_CONSTRUCT_FLOATS
:
9181 mips_disable_float_construction
= 0;
9184 case OPTION_NO_CONSTRUCT_FLOATS
:
9185 mips_disable_float_construction
= 1;
9197 target_big_endian
= 1;
9201 target_big_endian
= 0;
9209 if (arg
&& arg
[1] == '0')
9219 mips_debug
= atoi (arg
);
9220 /* When the MIPS assembler sees -g or -g2, it does not do
9221 optimizations which limit full symbolic debugging. We take
9222 that to be equivalent to -O0. */
9223 if (mips_debug
== 2)
9228 mips_opts
.isa
= ISA_MIPS1
;
9232 mips_opts
.isa
= ISA_MIPS2
;
9236 mips_opts
.isa
= ISA_MIPS3
;
9240 mips_opts
.isa
= ISA_MIPS4
;
9244 mips_opts
.isa
= ISA_MIPS5
;
9248 mips_opts
.isa
= ISA_MIPS32
;
9252 mips_opts
.isa
= ISA_MIPS64
;
9259 int cpu
= CPU_UNKNOWN
;
9261 /* Identify the processor type. */
9262 if (strcasecmp (arg
, "default") != 0)
9264 const struct mips_cpu_info
*ci
;
9266 ci
= mips_cpu_info_from_name (arg
);
9267 if (ci
== NULL
|| ci
->is_isa
)
9272 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9275 as_fatal (_("invalid architecture -march=%s"), arg
);
9278 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9289 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9290 as_warn(_("A different -mtune= was already specified, is now "
9295 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9296 as_warn(_("A different -march= was already specified, is now "
9301 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9302 as_warn(_("A different -mcpu= was already specified, is now "
9310 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9311 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9312 as_warn(_("A different -march= or -mtune= was already specified, "
9314 mips_arch
= CPU_R4650
;
9315 mips_tune
= CPU_R4650
;
9318 case OPTION_NO_M4650
:
9322 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9323 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9324 as_warn(_("A different -march= or -mtune= was already specified, "
9326 mips_arch
= CPU_R4010
;
9327 mips_tune
= CPU_R4010
;
9330 case OPTION_NO_M4010
:
9334 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9335 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9336 as_warn(_("A different -march= or -mtune= was already specified, "
9338 mips_arch
= CPU_VR4100
;
9339 mips_tune
= CPU_VR4100
;
9342 case OPTION_NO_M4100
:
9346 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9347 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9348 as_warn(_("A different -march= or -mtune= was already specified, "
9350 mips_arch
= CPU_R3900
;
9351 mips_tune
= CPU_R3900
;
9354 case OPTION_NO_M3900
:
9358 mips_opts
.mips16
= 1;
9359 mips_no_prev_insn (false);
9362 case OPTION_NO_MIPS16
:
9363 mips_opts
.mips16
= 0;
9364 mips_no_prev_insn (false);
9367 case OPTION_MEMBEDDED_PIC
:
9368 mips_pic
= EMBEDDED_PIC
;
9369 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9371 as_bad (_("-G may not be used with embedded PIC code"));
9374 g_switch_value
= 0x7fffffff;
9378 /* When generating ELF code, we permit -KPIC and -call_shared to
9379 select SVR4_PIC, and -non_shared to select no PIC. This is
9380 intended to be compatible with Irix 5. */
9381 case OPTION_CALL_SHARED
:
9382 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9384 as_bad (_("-call_shared is supported only for ELF format"));
9387 mips_pic
= SVR4_PIC
;
9388 if (g_switch_seen
&& g_switch_value
!= 0)
9390 as_bad (_("-G may not be used with SVR4 PIC code"));
9396 case OPTION_NON_SHARED
:
9397 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9399 as_bad (_("-non_shared is supported only for ELF format"));
9405 /* The -xgot option tells the assembler to use 32 offsets when
9406 accessing the got in SVR4_PIC mode. It is for Irix
9411 #endif /* OBJ_ELF */
9414 if (! USE_GLOBAL_POINTER_OPT
)
9416 as_bad (_("-G is not supported for this configuration"));
9419 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9421 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9425 g_switch_value
= atoi (arg
);
9430 /* The -32 and -64 options tell the assembler to output the 32
9431 bit or the 64 bit MIPS ELF format. */
9442 if (! support_64bit_objects())
9443 as_fatal (_("No compiled in support for 64 bit object file format"));
9448 if (mips_abi
!= O32_ABI
)
9454 if (mips_abi
== O32_ABI
)
9460 if (mips_abi
!= O32_ABI
)
9465 if (strcmp (arg
, "32") == 0)
9467 else if (strcmp (arg
, "o64") == 0)
9469 else if (strcmp (arg
, "n32") == 0)
9471 else if (strcmp (arg
, "64") == 0)
9474 if (! support_64bit_objects())
9475 as_fatal (_("No compiled in support for 64 bit object file "
9478 else if (strcmp (arg
, "eabi") == 0)
9479 mips_abi
= EABI_ABI
;
9483 #endif /* OBJ_ELF */
9485 case OPTION_M7000_HILO_FIX
:
9486 mips_7000_hilo_fix
= true;
9489 case OPTION_NO_M7000_HILO_FIX
:
9490 mips_7000_hilo_fix
= false;
9501 show (stream
, string
, col_p
, first_p
)
9509 fprintf (stream
, "%24s", "");
9514 fprintf (stream
, ", ");
9518 if (*col_p
+ strlen (string
) > 72)
9520 fprintf (stream
, "\n%24s", "");
9524 fprintf (stream
, "%s", string
);
9525 *col_p
+= strlen (string
);
9531 md_show_usage (stream
)
9536 fprintf (stream
, _("\
9538 -membedded-pic generate embedded position independent code\n\
9539 -EB generate big endian output\n\
9540 -EL generate little endian output\n\
9541 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9542 -G NUM allow referencing objects up to NUM bytes\n\
9543 implicitly with the gp register [default 8]\n"));
9544 fprintf (stream
, _("\
9545 -mips1 generate MIPS ISA I instructions\n\
9546 -mips2 generate MIPS ISA II instructions\n\
9547 -mips3 generate MIPS ISA III instructions\n\
9548 -mips4 generate MIPS ISA IV instructions\n\
9549 -mips5 generate MIPS ISA V instructions\n\
9550 -mips32 generate MIPS32 ISA instructions\n\
9551 -mips64 generate MIPS64 ISA instructions\n\
9552 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9556 show (stream
, "2000", &column
, &first
);
9557 show (stream
, "3000", &column
, &first
);
9558 show (stream
, "3900", &column
, &first
);
9559 show (stream
, "4000", &column
, &first
);
9560 show (stream
, "4010", &column
, &first
);
9561 show (stream
, "4100", &column
, &first
);
9562 show (stream
, "4111", &column
, &first
);
9563 show (stream
, "4300", &column
, &first
);
9564 show (stream
, "4400", &column
, &first
);
9565 show (stream
, "4600", &column
, &first
);
9566 show (stream
, "4650", &column
, &first
);
9567 show (stream
, "5000", &column
, &first
);
9568 show (stream
, "5200", &column
, &first
);
9569 show (stream
, "5230", &column
, &first
);
9570 show (stream
, "5231", &column
, &first
);
9571 show (stream
, "5261", &column
, &first
);
9572 show (stream
, "5721", &column
, &first
);
9573 show (stream
, "6000", &column
, &first
);
9574 show (stream
, "8000", &column
, &first
);
9575 show (stream
, "10000", &column
, &first
);
9576 show (stream
, "12000", &column
, &first
);
9577 show (stream
, "sb-1", &column
, &first
);
9578 fputc ('\n', stream
);
9580 fprintf (stream
, _("\
9581 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9582 -no-mCPU don't generate code specific to CPU.\n\
9583 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9587 show (stream
, "3900", &column
, &first
);
9588 show (stream
, "4010", &column
, &first
);
9589 show (stream
, "4100", &column
, &first
);
9590 show (stream
, "4650", &column
, &first
);
9591 fputc ('\n', stream
);
9593 fprintf (stream
, _("\
9594 -mips16 generate mips16 instructions\n\
9595 -no-mips16 do not generate mips16 instructions\n"));
9596 fprintf (stream
, _("\
9597 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9598 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9599 -O0 remove unneeded NOPs, do not swap branches\n\
9600 -O remove unneeded NOPs and swap branches\n\
9601 -n warn about NOPs generated from macros\n\
9602 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9603 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9604 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9606 fprintf (stream
, _("\
9607 -KPIC, -call_shared generate SVR4 position independent code\n\
9608 -non_shared do not generate position independent code\n\
9609 -xgot assume a 32 bit GOT\n\
9610 -32 create o32 ABI object file (default)\n\
9611 -n32 create n32 ABI object file\n\
9612 -64 create 64 ABI object file\n"));
9617 mips_init_after_args ()
9619 /* initialize opcodes */
9620 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9621 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9625 md_pcrel_from (fixP
)
9628 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9629 && fixP
->fx_addsy
!= (symbolS
*) NULL
9630 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9632 if (mips_pic
== EMBEDDED_PIC
)
9634 /* This makes a branch to an undefined symbol be a branch to the
9635 current location. */
9644 /* return the address of the delay slot */
9645 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9648 /* This is called before the symbol table is processed. In order to
9649 work with gcc when using mips-tfile, we must keep all local labels.
9650 However, in other cases, we want to discard them. If we were
9651 called with -g, but we didn't see any debugging information, it may
9652 mean that gcc is smuggling debugging information through to
9653 mips-tfile, in which case we must generate all local labels. */
9656 mips_frob_file_before_adjust ()
9658 #ifndef NO_ECOFF_DEBUGGING
9661 && ! ecoff_debugging_seen
)
9662 flag_keep_locals
= 1;
9666 /* Sort any unmatched HI16_S relocs so that they immediately precede
9667 the corresponding LO reloc. This is called before md_apply_fix and
9668 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9669 explicit use of the %hi modifier. */
9674 struct mips_hi_fixup
*l
;
9676 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9678 segment_info_type
*seginfo
;
9681 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9683 /* Check quickly whether the next fixup happens to be a matching
9685 if (l
->fixp
->fx_next
!= NULL
9686 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9687 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9688 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9691 /* Look through the fixups for this segment for a matching %lo.
9692 When we find one, move the %hi just in front of it. We do
9693 this in two passes. In the first pass, we try to find a
9694 unique %lo. In the second pass, we permit multiple %hi
9695 relocs for a single %lo (this is a GNU extension). */
9696 seginfo
= seg_info (l
->seg
);
9697 for (pass
= 0; pass
< 2; pass
++)
9702 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9704 /* Check whether this is a %lo fixup which matches l->fixp. */
9705 if (f
->fx_r_type
== BFD_RELOC_LO16
9706 && f
->fx_addsy
== l
->fixp
->fx_addsy
9707 && f
->fx_offset
== l
->fixp
->fx_offset
9710 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9711 || prev
->fx_addsy
!= f
->fx_addsy
9712 || prev
->fx_offset
!= f
->fx_offset
))
9716 /* Move l->fixp before f. */
9717 for (pf
= &seginfo
->fix_root
;
9719 pf
= &(*pf
)->fx_next
)
9720 assert (*pf
!= NULL
);
9722 *pf
= l
->fixp
->fx_next
;
9724 l
->fixp
->fx_next
= f
;
9726 seginfo
->fix_root
= l
->fixp
;
9728 prev
->fx_next
= l
->fixp
;
9739 #if 0 /* GCC code motion plus incomplete dead code elimination
9740 can leave a %hi without a %lo. */
9742 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9743 _("Unmatched %%hi reloc"));
9749 /* When generating embedded PIC code we need to use a special
9750 relocation to represent the difference of two symbols in the .text
9751 section (switch tables use a difference of this sort). See
9752 include/coff/mips.h for details. This macro checks whether this
9753 fixup requires the special reloc. */
9754 #define SWITCH_TABLE(fixp) \
9755 ((fixp)->fx_r_type == BFD_RELOC_32 \
9756 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9757 && (fixp)->fx_addsy != NULL \
9758 && (fixp)->fx_subsy != NULL \
9759 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9760 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9762 /* When generating embedded PIC code we must keep all PC relative
9763 relocations, in case the linker has to relax a call. We also need
9764 to keep relocations for switch table entries.
9766 We may have combined relocations without symbols in the N32/N64 ABI.
9767 We have to prevent gas from dropping them. */
9770 mips_force_relocation (fixp
)
9773 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9774 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9778 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
9779 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
9780 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
9781 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
9784 return (mips_pic
== EMBEDDED_PIC
9786 || SWITCH_TABLE (fixp
)
9787 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9788 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9791 /* Apply a fixup to the object file. */
9794 md_apply_fix (fixP
, valueP
)
9802 assert (fixP
->fx_size
== 4
9803 || fixP
->fx_r_type
== BFD_RELOC_16
9804 || fixP
->fx_r_type
== BFD_RELOC_32
9805 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
9806 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
9807 || fixP
->fx_r_type
== BFD_RELOC_LO16
9808 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
9809 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
9810 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
9811 || fixP
->fx_r_type
== BFD_RELOC_64
9812 || fixP
->fx_r_type
== BFD_RELOC_CTOR
9813 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
9814 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
9815 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
9816 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
9817 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
9818 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
9819 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9820 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9824 /* If we aren't adjusting this fixup to be against the section
9825 symbol, we need to adjust the value. */
9827 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9829 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9830 || ((S_IS_WEAK (fixP
->fx_addsy
)
9831 || S_IS_EXTERN (fixP
->fx_addsy
))
9832 && !S_IS_COMMON (fixP
->fx_addsy
))
9833 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9834 && (((bfd_get_section_flags (stdoutput
,
9835 S_GET_SEGMENT (fixP
->fx_addsy
))
9836 & SEC_LINK_ONCE
) != 0)
9837 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9839 sizeof (".gnu.linkonce") - 1))))
9842 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
9846 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
9848 /* In this case, the bfd_install_relocation routine will
9849 incorrectly add the symbol value back in. We just want
9850 the addend to appear in the object file. */
9853 /* Make sure the addend is still non-zero. If it became zero
9854 after the last operation, set it to a spurious value and
9855 subtract the same value from the object file's contents. */
9860 /* The in-place addends for LO16 relocations are signed;
9861 leave the matching HI16 in-place addends as zero. */
9862 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
9864 reloc_howto_type
*howto
;
9865 bfd_vma contents
, mask
, field
;
9867 howto
= bfd_reloc_type_lookup (stdoutput
,
9870 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
9875 /* MASK has bits set where the relocation should go.
9876 FIELD is -value, shifted into the appropriate place
9877 for this relocation. */
9878 mask
= 1 << (howto
->bitsize
- 1);
9879 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
9880 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
9882 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
9883 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9891 /* This code was generated using trial and error and so is
9892 fragile and not trustworthy. If you change it, you should
9893 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9895 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9897 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9899 /* BFD's REL handling, for MIPS, is _very_ weird.
9900 This gives the right results, but it can't possibly
9901 be the way things are supposed to work. */
9902 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
9903 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
9904 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9905 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9910 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9912 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9915 switch (fixP
->fx_r_type
)
9917 case BFD_RELOC_MIPS_JMP
:
9918 case BFD_RELOC_HI16
:
9919 case BFD_RELOC_HI16_S
:
9920 case BFD_RELOC_MIPS_GPREL
:
9921 case BFD_RELOC_MIPS_LITERAL
:
9922 case BFD_RELOC_MIPS_CALL16
:
9923 case BFD_RELOC_MIPS_GOT16
:
9924 case BFD_RELOC_MIPS_GPREL32
:
9925 case BFD_RELOC_MIPS_GOT_HI16
:
9926 case BFD_RELOC_MIPS_GOT_LO16
:
9927 case BFD_RELOC_MIPS_CALL_HI16
:
9928 case BFD_RELOC_MIPS_CALL_LO16
:
9929 case BFD_RELOC_MIPS16_GPREL
:
9931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9932 _("Invalid PC relative reloc"));
9933 /* Nothing needed to do. The value comes from the reloc entry */
9936 case BFD_RELOC_MIPS16_JMP
:
9937 /* We currently always generate a reloc against a symbol, which
9938 means that we don't want an addend even if the symbol is
9940 fixP
->fx_addnumber
= 0;
9943 case BFD_RELOC_PCREL_HI16_S
:
9944 /* The addend for this is tricky if it is internal, so we just
9945 do everything here rather than in bfd_install_relocation. */
9946 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9951 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9953 /* For an external symbol adjust by the address to make it
9954 pcrel_offset. We use the address of the RELLO reloc
9955 which follows this one. */
9956 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9957 + fixP
->fx_next
->fx_where
);
9959 value
= ((value
+ 0x8000) >> 16) & 0xffff;
9960 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9961 if (target_big_endian
)
9963 md_number_to_chars (buf
, value
, 2);
9966 case BFD_RELOC_PCREL_LO16
:
9967 /* The addend for this is tricky if it is internal, so we just
9968 do everything here rather than in bfd_install_relocation. */
9969 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9974 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9975 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9976 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9977 if (target_big_endian
)
9979 md_number_to_chars (buf
, value
, 2);
9983 /* This is handled like BFD_RELOC_32, but we output a sign
9984 extended value if we are only 32 bits. */
9986 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9988 if (8 <= sizeof (valueT
))
9989 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9996 w1
= w2
= fixP
->fx_where
;
9997 if (target_big_endian
)
10001 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10002 if ((value
& 0x80000000) != 0)
10006 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10011 case BFD_RELOC_RVA
:
10013 /* If we are deleting this reloc entry, we must fill in the
10014 value now. This can happen if we have a .word which is not
10015 resolved when it appears but is later defined. We also need
10016 to fill in the value if this is an embedded PIC switch table
10019 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10020 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10025 /* If we are deleting this reloc entry, we must fill in the
10027 assert (fixP
->fx_size
== 2);
10029 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10033 case BFD_RELOC_LO16
:
10034 /* When handling an embedded PIC switch statement, we can wind
10035 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10038 if (value
+ 0x8000 > 0xffff)
10039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10040 _("relocation overflow"));
10041 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10042 if (target_big_endian
)
10044 md_number_to_chars (buf
, value
, 2);
10048 case BFD_RELOC_16_PCREL_S2
:
10049 if ((value
& 0x3) != 0)
10050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10051 _("Branch to odd address (%lx)"), (long) value
);
10053 /* Fall through. */
10055 case BFD_RELOC_16_PCREL
:
10057 * We need to save the bits in the instruction since fixup_segment()
10058 * might be deleting the relocation entry (i.e., a branch within
10059 * the current segment).
10061 if (!fixP
->fx_done
&& value
!= 0)
10063 /* If 'value' is zero, the remaining reloc code won't actually
10064 do the store, so it must be done here. This is probably
10065 a bug somewhere. */
10066 if (!fixP
->fx_done
)
10067 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10069 value
= (offsetT
) value
>> 2;
10071 /* update old instruction data */
10072 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10073 if (target_big_endian
)
10074 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10076 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10078 if (value
+ 0x8000 <= 0xffff)
10079 insn
|= value
& 0xffff;
10082 /* The branch offset is too large. If this is an
10083 unconditional branch, and we are not generating PIC code,
10084 we can convert it to an absolute jump instruction. */
10085 if (mips_pic
== NO_PIC
10087 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10088 && (fixP
->fx_frag
->fr_address
10089 < text_section
->vma
+ text_section
->_raw_size
)
10090 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10091 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10092 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10094 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10095 insn
= 0x0c000000; /* jal */
10097 insn
= 0x08000000; /* j */
10098 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10100 fixP
->fx_addsy
= section_symbol (text_section
);
10101 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10105 /* FIXME. It would be possible in principle to handle
10106 conditional branches which overflow. They could be
10107 transformed into a branch around a jump. This would
10108 require setting up variant frags for each different
10109 branch type. The native MIPS assembler attempts to
10110 handle these cases, but it appears to do it
10112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10113 _("Branch out of range"));
10117 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10120 case BFD_RELOC_VTABLE_INHERIT
:
10123 && !S_IS_DEFINED (fixP
->fx_addsy
)
10124 && !S_IS_WEAK (fixP
->fx_addsy
))
10125 S_SET_WEAK (fixP
->fx_addsy
);
10128 case BFD_RELOC_VTABLE_ENTRY
:
10144 const struct mips_opcode
*p
;
10145 int treg
, sreg
, dreg
, shamt
;
10150 for (i
= 0; i
< NUMOPCODES
; ++i
)
10152 p
= &mips_opcodes
[i
];
10153 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10155 printf ("%08lx %s\t", oc
, p
->name
);
10156 treg
= (oc
>> 16) & 0x1f;
10157 sreg
= (oc
>> 21) & 0x1f;
10158 dreg
= (oc
>> 11) & 0x1f;
10159 shamt
= (oc
>> 6) & 0x1f;
10161 for (args
= p
->args
;; ++args
)
10172 printf ("%c", *args
);
10176 assert (treg
== sreg
);
10177 printf ("$%d,$%d", treg
, sreg
);
10182 printf ("$%d", dreg
);
10187 printf ("$%d", treg
);
10191 printf ("0x%x", treg
);
10196 printf ("$%d", sreg
);
10200 printf ("0x%08lx", oc
& 0x1ffffff);
10207 printf ("%d", imm
);
10212 printf ("$%d", shamt
);
10223 printf (_("%08lx UNDEFINED\n"), oc
);
10234 name
= input_line_pointer
;
10235 c
= get_symbol_end ();
10236 p
= (symbolS
*) symbol_find_or_make (name
);
10237 *input_line_pointer
= c
;
10241 /* Align the current frag to a given power of two. The MIPS assembler
10242 also automatically adjusts any preceding label. */
10245 mips_align (to
, fill
, label
)
10250 mips_emit_delays (false);
10251 frag_align (to
, fill
, 0);
10252 record_alignment (now_seg
, to
);
10255 assert (S_GET_SEGMENT (label
) == now_seg
);
10256 symbol_set_frag (label
, frag_now
);
10257 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10261 /* Align to a given power of two. .align 0 turns off the automatic
10262 alignment used by the data creating pseudo-ops. */
10266 int x ATTRIBUTE_UNUSED
;
10269 register long temp_fill
;
10270 long max_alignment
= 15;
10274 o Note that the assembler pulls down any immediately preceeding label
10275 to the aligned address.
10276 o It's not documented but auto alignment is reinstated by
10277 a .align pseudo instruction.
10278 o Note also that after auto alignment is turned off the mips assembler
10279 issues an error on attempt to assemble an improperly aligned data item.
10284 temp
= get_absolute_expression ();
10285 if (temp
> max_alignment
)
10286 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10289 as_warn (_("Alignment negative: 0 assumed."));
10292 if (*input_line_pointer
== ',')
10294 input_line_pointer
++;
10295 temp_fill
= get_absolute_expression ();
10302 mips_align (temp
, (int) temp_fill
,
10303 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10310 demand_empty_rest_of_line ();
10314 mips_flush_pending_output ()
10316 mips_emit_delays (false);
10317 mips_clear_insn_labels ();
10326 /* When generating embedded PIC code, we only use the .text, .lit8,
10327 .sdata and .sbss sections. We change the .data and .rdata
10328 pseudo-ops to use .sdata. */
10329 if (mips_pic
== EMBEDDED_PIC
10330 && (sec
== 'd' || sec
== 'r'))
10334 /* The ELF backend needs to know that we are changing sections, so
10335 that .previous works correctly. We could do something like check
10336 for a obj_section_change_hook macro, but that might be confusing
10337 as it would not be appropriate to use it in the section changing
10338 functions in read.c, since obj-elf.c intercepts those. FIXME:
10339 This should be cleaner, somehow. */
10340 obj_elf_section_change_hook ();
10343 mips_emit_delays (false);
10353 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10354 demand_empty_rest_of_line ();
10358 if (USE_GLOBAL_POINTER_OPT
)
10360 seg
= subseg_new (RDATA_SECTION_NAME
,
10361 (subsegT
) get_absolute_expression ());
10362 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10364 bfd_set_section_flags (stdoutput
, seg
,
10370 if (strcmp (TARGET_OS
, "elf") != 0)
10371 record_alignment (seg
, 4);
10373 demand_empty_rest_of_line ();
10377 as_bad (_("No read only data section in this object file format"));
10378 demand_empty_rest_of_line ();
10384 if (USE_GLOBAL_POINTER_OPT
)
10386 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10387 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10389 bfd_set_section_flags (stdoutput
, seg
,
10390 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10392 if (strcmp (TARGET_OS
, "elf") != 0)
10393 record_alignment (seg
, 4);
10395 demand_empty_rest_of_line ();
10400 as_bad (_("Global pointers not supported; recompile -G 0"));
10401 demand_empty_rest_of_line ();
10410 mips_enable_auto_align ()
10421 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10422 mips_emit_delays (false);
10423 if (log_size
> 0 && auto_align
)
10424 mips_align (log_size
, 0, label
);
10425 mips_clear_insn_labels ();
10426 cons (1 << log_size
);
10430 s_float_cons (type
)
10435 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10437 mips_emit_delays (false);
10442 mips_align (3, 0, label
);
10444 mips_align (2, 0, label
);
10447 mips_clear_insn_labels ();
10452 /* Handle .globl. We need to override it because on Irix 5 you are
10455 where foo is an undefined symbol, to mean that foo should be
10456 considered to be the address of a function. */
10460 int x ATTRIBUTE_UNUSED
;
10467 name
= input_line_pointer
;
10468 c
= get_symbol_end ();
10469 symbolP
= symbol_find_or_make (name
);
10470 *input_line_pointer
= c
;
10471 SKIP_WHITESPACE ();
10473 /* On Irix 5, every global symbol that is not explicitly labelled as
10474 being a function is apparently labelled as being an object. */
10477 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10482 secname
= input_line_pointer
;
10483 c
= get_symbol_end ();
10484 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10486 as_bad (_("%s: no such section"), secname
);
10487 *input_line_pointer
= c
;
10489 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10490 flag
= BSF_FUNCTION
;
10493 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10495 S_SET_EXTERNAL (symbolP
);
10496 demand_empty_rest_of_line ();
10501 int x ATTRIBUTE_UNUSED
;
10506 opt
= input_line_pointer
;
10507 c
= get_symbol_end ();
10511 /* FIXME: What does this mean? */
10513 else if (strncmp (opt
, "pic", 3) == 0)
10517 i
= atoi (opt
+ 3);
10521 mips_pic
= SVR4_PIC
;
10523 as_bad (_(".option pic%d not supported"), i
);
10525 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10527 if (g_switch_seen
&& g_switch_value
!= 0)
10528 as_warn (_("-G may not be used with SVR4 PIC code"));
10529 g_switch_value
= 0;
10530 bfd_set_gp_size (stdoutput
, 0);
10534 as_warn (_("Unrecognized option \"%s\""), opt
);
10536 *input_line_pointer
= c
;
10537 demand_empty_rest_of_line ();
10540 /* This structure is used to hold a stack of .set values. */
10542 struct mips_option_stack
10544 struct mips_option_stack
*next
;
10545 struct mips_set_options options
;
10548 static struct mips_option_stack
*mips_opts_stack
;
10550 /* Handle the .set pseudo-op. */
10554 int x ATTRIBUTE_UNUSED
;
10556 char *name
= input_line_pointer
, ch
;
10558 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10559 input_line_pointer
++;
10560 ch
= *input_line_pointer
;
10561 *input_line_pointer
= '\0';
10563 if (strcmp (name
, "reorder") == 0)
10565 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10567 /* If we still have pending nops, we can discard them. The
10568 usual nop handling will insert any that are still
10570 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10571 * (mips_opts
.mips16
? 2 : 4));
10572 prev_nop_frag
= NULL
;
10574 mips_opts
.noreorder
= 0;
10576 else if (strcmp (name
, "noreorder") == 0)
10578 mips_emit_delays (true);
10579 mips_opts
.noreorder
= 1;
10580 mips_any_noreorder
= 1;
10582 else if (strcmp (name
, "at") == 0)
10584 mips_opts
.noat
= 0;
10586 else if (strcmp (name
, "noat") == 0)
10588 mips_opts
.noat
= 1;
10590 else if (strcmp (name
, "macro") == 0)
10592 mips_opts
.warn_about_macros
= 0;
10594 else if (strcmp (name
, "nomacro") == 0)
10596 if (mips_opts
.noreorder
== 0)
10597 as_bad (_("`noreorder' must be set before `nomacro'"));
10598 mips_opts
.warn_about_macros
= 1;
10600 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10602 mips_opts
.nomove
= 0;
10604 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10606 mips_opts
.nomove
= 1;
10608 else if (strcmp (name
, "bopt") == 0)
10610 mips_opts
.nobopt
= 0;
10612 else if (strcmp (name
, "nobopt") == 0)
10614 mips_opts
.nobopt
= 1;
10616 else if (strcmp (name
, "mips16") == 0
10617 || strcmp (name
, "MIPS-16") == 0)
10618 mips_opts
.mips16
= 1;
10619 else if (strcmp (name
, "nomips16") == 0
10620 || strcmp (name
, "noMIPS-16") == 0)
10621 mips_opts
.mips16
= 0;
10622 else if (strncmp (name
, "mips", 4) == 0)
10625 static int saved_mips_gp32
;
10626 static int saved_mips_fp32
;
10627 static enum mips_abi_level saved_mips_abi
;
10628 static int is_saved
;
10630 /* Permit the user to change the ISA on the fly. Needless to
10631 say, misuse can cause serious problems. */
10632 isa
= atoi (name
+ 4);
10636 mips_gp32
= saved_mips_gp32
;
10637 mips_fp32
= saved_mips_fp32
;
10638 mips_abi
= saved_mips_abi
;
10646 saved_mips_gp32
= mips_gp32
;
10647 saved_mips_fp32
= mips_fp32
;
10648 saved_mips_abi
= mips_abi
;
10660 saved_mips_gp32
= mips_gp32
;
10661 saved_mips_fp32
= mips_fp32
;
10662 saved_mips_abi
= mips_abi
;
10670 as_bad (_("unknown ISA level"));
10676 case 0: mips_opts
.isa
= file_mips_isa
; break;
10677 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10678 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10679 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10680 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10681 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10682 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10683 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10684 default: as_bad (_("unknown ISA level")); break;
10687 else if (strcmp (name
, "autoextend") == 0)
10688 mips_opts
.noautoextend
= 0;
10689 else if (strcmp (name
, "noautoextend") == 0)
10690 mips_opts
.noautoextend
= 1;
10691 else if (strcmp (name
, "push") == 0)
10693 struct mips_option_stack
*s
;
10695 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10696 s
->next
= mips_opts_stack
;
10697 s
->options
= mips_opts
;
10698 mips_opts_stack
= s
;
10700 else if (strcmp (name
, "pop") == 0)
10702 struct mips_option_stack
*s
;
10704 s
= mips_opts_stack
;
10706 as_bad (_(".set pop with no .set push"));
10709 /* If we're changing the reorder mode we need to handle
10710 delay slots correctly. */
10711 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10712 mips_emit_delays (true);
10713 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10715 if (prev_nop_frag
!= NULL
)
10717 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10718 * (mips_opts
.mips16
? 2 : 4));
10719 prev_nop_frag
= NULL
;
10723 mips_opts
= s
->options
;
10724 mips_opts_stack
= s
->next
;
10730 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10732 *input_line_pointer
= ch
;
10733 demand_empty_rest_of_line ();
10736 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10737 .option pic2. It means to generate SVR4 PIC calls. */
10740 s_abicalls (ignore
)
10741 int ignore ATTRIBUTE_UNUSED
;
10743 mips_pic
= SVR4_PIC
;
10744 if (USE_GLOBAL_POINTER_OPT
)
10746 if (g_switch_seen
&& g_switch_value
!= 0)
10747 as_warn (_("-G may not be used with SVR4 PIC code"));
10748 g_switch_value
= 0;
10750 bfd_set_gp_size (stdoutput
, 0);
10751 demand_empty_rest_of_line ();
10754 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10755 PIC code. It sets the $gp register for the function based on the
10756 function address, which is in the register named in the argument.
10757 This uses a relocation against _gp_disp, which is handled specially
10758 by the linker. The result is:
10759 lui $gp,%hi(_gp_disp)
10760 addiu $gp,$gp,%lo(_gp_disp)
10761 addu $gp,$gp,.cpload argument
10762 The .cpload argument is normally $25 == $t9. */
10766 int ignore ATTRIBUTE_UNUSED
;
10771 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10772 if (mips_pic
!= SVR4_PIC
)
10778 /* .cpload should be a in .set noreorder section. */
10779 if (mips_opts
.noreorder
== 0)
10780 as_warn (_(".cpload not in noreorder section"));
10782 ex
.X_op
= O_symbol
;
10783 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10784 ex
.X_op_symbol
= NULL
;
10785 ex
.X_add_number
= 0;
10787 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10788 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10790 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10791 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10792 (int) BFD_RELOC_LO16
);
10794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10795 GP
, GP
, tc_get_register (0));
10797 demand_empty_rest_of_line ();
10800 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10801 offset from $sp. The offset is remembered, and after making a PIC
10802 call $gp is restored from that location. */
10805 s_cprestore (ignore
)
10806 int ignore ATTRIBUTE_UNUSED
;
10811 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10812 if (mips_pic
!= SVR4_PIC
)
10818 mips_cprestore_offset
= get_absolute_expression ();
10820 ex
.X_op
= O_constant
;
10821 ex
.X_add_symbol
= NULL
;
10822 ex
.X_op_symbol
= NULL
;
10823 ex
.X_add_number
= mips_cprestore_offset
;
10825 macro_build ((char *) NULL
, &icnt
, &ex
,
10826 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
10827 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10829 demand_empty_rest_of_line ();
10832 /* Handle the .gpword pseudo-op. This is used when generating PIC
10833 code. It generates a 32 bit GP relative reloc. */
10837 int ignore ATTRIBUTE_UNUSED
;
10843 /* When not generating PIC code, this is treated as .word. */
10844 if (mips_pic
!= SVR4_PIC
)
10850 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10851 mips_emit_delays (true);
10853 mips_align (2, 0, label
);
10854 mips_clear_insn_labels ();
10858 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10860 as_bad (_("Unsupported use of .gpword"));
10861 ignore_rest_of_line ();
10865 md_number_to_chars (p
, (valueT
) 0, 4);
10866 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10867 BFD_RELOC_MIPS_GPREL32
);
10869 demand_empty_rest_of_line ();
10872 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10873 tables in SVR4 PIC code. */
10877 int ignore ATTRIBUTE_UNUSED
;
10882 /* This is ignored when not generating SVR4 PIC code. */
10883 if (mips_pic
!= SVR4_PIC
)
10889 /* Add $gp to the register named as an argument. */
10890 reg
= tc_get_register (0);
10891 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10892 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
10893 "d,v,t", reg
, reg
, GP
);
10895 demand_empty_rest_of_line ();
10898 /* Handle the .insn pseudo-op. This marks instruction labels in
10899 mips16 mode. This permits the linker to handle them specially,
10900 such as generating jalx instructions when needed. We also make
10901 them odd for the duration of the assembly, in order to generate the
10902 right sort of code. We will make them even in the adjust_symtab
10903 routine, while leaving them marked. This is convenient for the
10904 debugger and the disassembler. The linker knows to make them odd
10909 int ignore ATTRIBUTE_UNUSED
;
10911 if (mips_opts
.mips16
)
10912 mips16_mark_labels ();
10914 demand_empty_rest_of_line ();
10917 /* Handle a .stabn directive. We need these in order to mark a label
10918 as being a mips16 text label correctly. Sometimes the compiler
10919 will emit a label, followed by a .stabn, and then switch sections.
10920 If the label and .stabn are in mips16 mode, then the label is
10921 really a mips16 text label. */
10927 if (type
== 'n' && mips_opts
.mips16
)
10928 mips16_mark_labels ();
10933 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10937 s_mips_weakext (ignore
)
10938 int ignore ATTRIBUTE_UNUSED
;
10945 name
= input_line_pointer
;
10946 c
= get_symbol_end ();
10947 symbolP
= symbol_find_or_make (name
);
10948 S_SET_WEAK (symbolP
);
10949 *input_line_pointer
= c
;
10951 SKIP_WHITESPACE ();
10953 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10955 if (S_IS_DEFINED (symbolP
))
10957 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10958 S_GET_NAME (symbolP
));
10959 ignore_rest_of_line ();
10963 if (*input_line_pointer
== ',')
10965 ++input_line_pointer
;
10966 SKIP_WHITESPACE ();
10970 if (exp
.X_op
!= O_symbol
)
10972 as_bad ("bad .weakext directive");
10973 ignore_rest_of_line();
10976 symbol_set_value_expression (symbolP
, &exp
);
10979 demand_empty_rest_of_line ();
10982 /* Parse a register string into a number. Called from the ECOFF code
10983 to parse .frame. The argument is non-zero if this is the frame
10984 register, so that we can record it in mips_frame_reg. */
10987 tc_get_register (frame
)
10992 SKIP_WHITESPACE ();
10993 if (*input_line_pointer
++ != '$')
10995 as_warn (_("expected `$'"));
10998 else if (ISDIGIT (*input_line_pointer
))
11000 reg
= get_absolute_expression ();
11001 if (reg
< 0 || reg
>= 32)
11003 as_warn (_("Bad register number"));
11009 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11011 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11013 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11015 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11019 as_warn (_("Unrecognized register name"));
11022 input_line_pointer
+= 2;
11025 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11030 md_section_align (seg
, addr
)
11034 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11037 /* We don't need to align ELF sections to the full alignment.
11038 However, Irix 5 may prefer that we align them at least to a 16
11039 byte boundary. We don't bother to align the sections if we are
11040 targeted for an embedded system. */
11041 if (strcmp (TARGET_OS
, "elf") == 0)
11047 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11050 /* Utility routine, called from above as well. If called while the
11051 input file is still being read, it's only an approximation. (For
11052 example, a symbol may later become defined which appeared to be
11053 undefined earlier.) */
11056 nopic_need_relax (sym
, before_relaxing
)
11058 int before_relaxing
;
11063 if (USE_GLOBAL_POINTER_OPT
)
11065 const char *symname
;
11068 /* Find out whether this symbol can be referenced off the GP
11069 register. It can be if it is smaller than the -G size or if
11070 it is in the .sdata or .sbss section. Certain symbols can
11071 not be referenced off the GP, although it appears as though
11073 symname
= S_GET_NAME (sym
);
11074 if (symname
!= (const char *) NULL
11075 && (strcmp (symname
, "eprol") == 0
11076 || strcmp (symname
, "etext") == 0
11077 || strcmp (symname
, "_gp") == 0
11078 || strcmp (symname
, "edata") == 0
11079 || strcmp (symname
, "_fbss") == 0
11080 || strcmp (symname
, "_fdata") == 0
11081 || strcmp (symname
, "_ftext") == 0
11082 || strcmp (symname
, "end") == 0
11083 || strcmp (symname
, "_gp_disp") == 0))
11085 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11087 #ifndef NO_ECOFF_DEBUGGING
11088 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11089 && (symbol_get_obj (sym
)->ecoff_extern_size
11090 <= g_switch_value
))
11092 /* We must defer this decision until after the whole
11093 file has been read, since there might be a .extern
11094 after the first use of this symbol. */
11095 || (before_relaxing
11096 #ifndef NO_ECOFF_DEBUGGING
11097 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11099 && S_GET_VALUE (sym
) == 0)
11100 || (S_GET_VALUE (sym
) != 0
11101 && S_GET_VALUE (sym
) <= g_switch_value
)))
11105 const char *segname
;
11107 segname
= segment_name (S_GET_SEGMENT (sym
));
11108 assert (strcmp (segname
, ".lit8") != 0
11109 && strcmp (segname
, ".lit4") != 0);
11110 change
= (strcmp (segname
, ".sdata") != 0
11111 && strcmp (segname
, ".sbss") != 0
11112 && strncmp (segname
, ".sdata.", 7) != 0
11113 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11118 /* We are not optimizing for the GP register. */
11122 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11123 extended opcode. SEC is the section the frag is in. */
11126 mips16_extended_frag (fragp
, sec
, stretch
)
11132 register const struct mips16_immed_operand
*op
;
11134 int mintiny
, maxtiny
;
11138 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11140 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11143 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11144 op
= mips16_immed_operands
;
11145 while (op
->type
!= type
)
11148 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11153 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11156 maxtiny
= 1 << op
->nbits
;
11161 maxtiny
= (1 << op
->nbits
) - 1;
11166 mintiny
= - (1 << (op
->nbits
- 1));
11167 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11170 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
11171 val
= S_GET_VALUE (fragp
->fr_symbol
);
11172 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11178 /* We won't have the section when we are called from
11179 mips_relax_frag. However, we will always have been called
11180 from md_estimate_size_before_relax first. If this is a
11181 branch to a different section, we mark it as such. If SEC is
11182 NULL, and the frag is not marked, then it must be a branch to
11183 the same section. */
11186 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11191 /* Must have been called from md_estimate_size_before_relax. */
11194 fragp
->fr_subtype
=
11195 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11197 /* FIXME: We should support this, and let the linker
11198 catch branches and loads that are out of range. */
11199 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11200 _("unsupported PC relative reference to different section"));
11204 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
11205 /* Assume non-extended on the first relaxation pass.
11206 The address we have calculated will be bogus if this is
11207 a forward branch to another frag, as the forward frag
11208 will have fr_address == 0. */
11212 /* In this case, we know for sure that the symbol fragment is in
11213 the same section. If the relax_marker of the symbol fragment
11214 differs from the relax_marker of this fragment, we have not
11215 yet adjusted the symbol fragment fr_address. We want to add
11216 in STRETCH in order to get a better estimate of the address.
11217 This particularly matters because of the shift bits. */
11219 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11223 /* Adjust stretch for any alignment frag. Note that if have
11224 been expanding the earlier code, the symbol may be
11225 defined in what appears to be an earlier frag. FIXME:
11226 This doesn't handle the fr_subtype field, which specifies
11227 a maximum number of bytes to skip when doing an
11229 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11231 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11234 stretch
= - ((- stretch
)
11235 & ~ ((1 << (int) f
->fr_offset
) - 1));
11237 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11246 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11248 /* The base address rules are complicated. The base address of
11249 a branch is the following instruction. The base address of a
11250 PC relative load or add is the instruction itself, but if it
11251 is in a delay slot (in which case it can not be extended) use
11252 the address of the instruction whose delay slot it is in. */
11253 if (type
== 'p' || type
== 'q')
11257 /* If we are currently assuming that this frag should be
11258 extended, then, the current address is two bytes
11260 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11263 /* Ignore the low bit in the target, since it will be set
11264 for a text label. */
11265 if ((val
& 1) != 0)
11268 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11270 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11273 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11275 /* Branch offsets have an implicit 0 in the lowest bit. */
11276 if (type
== 'p' || type
== 'q')
11279 /* If any of the shifted bits are set, we must use an extended
11280 opcode. If the address depends on the size of this
11281 instruction, this can lead to a loop, so we arrange to always
11282 use an extended opcode. We only check this when we are in
11283 the main relaxation loop, when SEC is NULL. */
11284 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11286 fragp
->fr_subtype
=
11287 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11291 /* If we are about to mark a frag as extended because the value
11292 is precisely maxtiny + 1, then there is a chance of an
11293 infinite loop as in the following code:
11298 In this case when the la is extended, foo is 0x3fc bytes
11299 away, so the la can be shrunk, but then foo is 0x400 away, so
11300 the la must be extended. To avoid this loop, we mark the
11301 frag as extended if it was small, and is about to become
11302 extended with a value of maxtiny + 1. */
11303 if (val
== ((maxtiny
+ 1) << op
->shift
)
11304 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11307 fragp
->fr_subtype
=
11308 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11312 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11313 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11315 if ((val
& ((1 << op
->shift
) - 1)) != 0
11316 || val
< (mintiny
<< op
->shift
)
11317 || val
> (maxtiny
<< op
->shift
))
11323 /* Estimate the size of a frag before relaxing. Unless this is the
11324 mips16, we are not really relaxing here, and the final size is
11325 encoded in the subtype information. For the mips16, we have to
11326 decide whether we are using an extended opcode or not. */
11329 md_estimate_size_before_relax (fragp
, segtype
)
11334 boolean linkonce
= false;
11336 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11338 if (mips16_extended_frag (fragp
, segtype
, 0))
11340 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11345 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11350 if (mips_pic
== NO_PIC
)
11352 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11354 else if (mips_pic
== SVR4_PIC
)
11359 sym
= fragp
->fr_symbol
;
11361 /* Handle the case of a symbol equated to another symbol. */
11362 while (symbol_equated_reloc_p (sym
))
11366 /* It's possible to get a loop here in a badly written
11368 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11374 symsec
= S_GET_SEGMENT (sym
);
11376 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11377 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11379 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11383 /* The GNU toolchain uses an extension for ELF: a section
11384 beginning with the magic string .gnu.linkonce is a linkonce
11386 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11387 sizeof ".gnu.linkonce" - 1) == 0)
11391 /* This must duplicate the test in adjust_reloc_syms. */
11392 change
= (symsec
!= &bfd_und_section
11393 && symsec
!= &bfd_abs_section
11394 && ! bfd_is_com_section (symsec
)
11397 /* A global or weak symbol is treated as external. */
11398 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11399 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
11408 /* Record the offset to the first reloc in the fr_opcode field.
11409 This lets md_convert_frag and tc_gen_reloc know that the code
11410 must be expanded. */
11411 fragp
->fr_opcode
= (fragp
->fr_literal
11413 - RELAX_OLD (fragp
->fr_subtype
)
11414 + RELAX_RELOC1 (fragp
->fr_subtype
));
11415 /* FIXME: This really needs as_warn_where. */
11416 if (RELAX_WARN (fragp
->fr_subtype
))
11417 as_warn (_("AT used after \".set noat\" or macro used after "
11418 "\".set nomacro\""));
11420 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11426 /* This is called to see whether a reloc against a defined symbol
11427 should be converted into a reloc against a section. Don't adjust
11428 MIPS16 jump relocations, so we don't have to worry about the format
11429 of the offset in the .o file. Don't adjust relocations against
11430 mips16 symbols, so that the linker can find them if it needs to set
11434 mips_fix_adjustable (fixp
)
11438 /* Prevent all adjustments to global symbols. */
11439 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11440 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
11443 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11445 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11446 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11448 if (fixp
->fx_addsy
== NULL
)
11451 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11452 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11453 && fixp
->fx_subsy
== NULL
)
11459 /* Translate internal representation of relocation info to BFD target
11463 tc_gen_reloc (section
, fixp
)
11464 asection
*section ATTRIBUTE_UNUSED
;
11467 static arelent
*retval
[4];
11469 bfd_reloc_code_real_type code
;
11471 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11474 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11475 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11476 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11478 if (mips_pic
== EMBEDDED_PIC
11479 && SWITCH_TABLE (fixp
))
11481 /* For a switch table entry we use a special reloc. The addend
11482 is actually the difference between the reloc address and the
11484 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11485 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11486 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11487 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11489 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11490 reloc
->addend
= fixp
->fx_addnumber
;
11491 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11493 /* We use a special addend for an internal RELLO reloc. */
11494 if (symbol_section_p (fixp
->fx_addsy
))
11495 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11497 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11499 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11501 assert (fixp
->fx_next
!= NULL
11502 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11503 /* We use a special addend for an internal RELHI reloc. The
11504 reloc is relative to the RELLO; adjust the addend
11506 if (symbol_section_p (fixp
->fx_addsy
))
11507 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11508 + fixp
->fx_next
->fx_where
11509 - S_GET_VALUE (fixp
->fx_subsy
));
11511 reloc
->addend
= (fixp
->fx_addnumber
11512 + fixp
->fx_next
->fx_frag
->fr_address
11513 + fixp
->fx_next
->fx_where
);
11517 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11518 /* A gruesome hack which is a result of the gruesome gas reloc
11520 reloc
->addend
= reloc
->address
;
11522 reloc
->addend
= -reloc
->address
;
11525 /* If this is a variant frag, we may need to adjust the existing
11526 reloc and generate a new one. */
11527 if (fixp
->fx_frag
->fr_opcode
!= NULL
11528 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11529 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11530 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11531 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11532 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11533 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11534 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11538 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11540 /* If this is not the last reloc in this frag, then we have two
11541 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11542 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11543 the second one handle all of them. */
11544 if (fixp
->fx_next
!= NULL
11545 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11547 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11548 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11549 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11550 && (fixp
->fx_next
->fx_r_type
11551 == BFD_RELOC_MIPS_GOT_LO16
))
11552 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11553 && (fixp
->fx_next
->fx_r_type
11554 == BFD_RELOC_MIPS_CALL_LO16
)));
11559 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11560 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11561 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11563 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11564 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11565 reloc2
->address
= (reloc
->address
11566 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11567 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11568 reloc2
->addend
= fixp
->fx_addnumber
;
11569 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11570 assert (reloc2
->howto
!= NULL
);
11572 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11576 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11579 reloc3
->address
+= 4;
11582 if (mips_pic
== NO_PIC
)
11584 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11585 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11587 else if (mips_pic
== SVR4_PIC
)
11589 switch (fixp
->fx_r_type
)
11593 case BFD_RELOC_MIPS_GOT16
:
11595 case BFD_RELOC_MIPS_CALL16
:
11596 case BFD_RELOC_MIPS_GOT_LO16
:
11597 case BFD_RELOC_MIPS_CALL_LO16
:
11598 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11606 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11607 to be used in the relocation's section offset. */
11608 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11610 reloc
->address
= reloc
->addend
;
11614 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11615 fixup_segment converted a non-PC relative reloc into a PC
11616 relative reloc. In such a case, we need to convert the reloc
11618 code
= fixp
->fx_r_type
;
11619 if (fixp
->fx_pcrel
)
11624 code
= BFD_RELOC_8_PCREL
;
11627 code
= BFD_RELOC_16_PCREL
;
11630 code
= BFD_RELOC_32_PCREL
;
11633 code
= BFD_RELOC_64_PCREL
;
11635 case BFD_RELOC_8_PCREL
:
11636 case BFD_RELOC_16_PCREL
:
11637 case BFD_RELOC_32_PCREL
:
11638 case BFD_RELOC_64_PCREL
:
11639 case BFD_RELOC_16_PCREL_S2
:
11640 case BFD_RELOC_PCREL_HI16_S
:
11641 case BFD_RELOC_PCREL_LO16
:
11644 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11645 _("Cannot make %s relocation PC relative"),
11646 bfd_get_reloc_code_name (code
));
11650 /* To support a PC relative reloc when generating embedded PIC code
11651 for ECOFF, we use a Cygnus extension. We check for that here to
11652 make sure that we don't let such a reloc escape normally. */
11653 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11654 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11655 && code
== BFD_RELOC_16_PCREL_S2
11656 && mips_pic
!= EMBEDDED_PIC
)
11657 reloc
->howto
= NULL
;
11659 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11661 if (reloc
->howto
== NULL
)
11663 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11664 _("Can not represent %s relocation in this object file format"),
11665 bfd_get_reloc_code_name (code
));
11672 /* Relax a machine dependent frag. This returns the amount by which
11673 the current size of the frag should change. */
11676 mips_relax_frag (fragp
, stretch
)
11680 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11683 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11685 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11687 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11692 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11694 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11701 /* Convert a machine dependent frag. */
11704 md_convert_frag (abfd
, asec
, fragp
)
11705 bfd
*abfd ATTRIBUTE_UNUSED
;
11712 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11715 register const struct mips16_immed_operand
*op
;
11716 boolean small
, ext
;
11719 unsigned long insn
;
11720 boolean use_extend
;
11721 unsigned short extend
;
11723 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11724 op
= mips16_immed_operands
;
11725 while (op
->type
!= type
)
11728 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11739 resolve_symbol_value (fragp
->fr_symbol
);
11740 val
= S_GET_VALUE (fragp
->fr_symbol
);
11745 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11747 /* The rules for the base address of a PC relative reloc are
11748 complicated; see mips16_extended_frag. */
11749 if (type
== 'p' || type
== 'q')
11754 /* Ignore the low bit in the target, since it will be
11755 set for a text label. */
11756 if ((val
& 1) != 0)
11759 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11761 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11764 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11767 /* Make sure the section winds up with the alignment we have
11770 record_alignment (asec
, op
->shift
);
11774 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11775 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11776 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11777 _("extended instruction in delay slot"));
11779 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11781 if (target_big_endian
)
11782 insn
= bfd_getb16 (buf
);
11784 insn
= bfd_getl16 (buf
);
11786 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11787 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11788 small
, ext
, &insn
, &use_extend
, &extend
);
11792 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11793 fragp
->fr_fix
+= 2;
11797 md_number_to_chars (buf
, insn
, 2);
11798 fragp
->fr_fix
+= 2;
11803 if (fragp
->fr_opcode
== NULL
)
11806 old
= RELAX_OLD (fragp
->fr_subtype
);
11807 new = RELAX_NEW (fragp
->fr_subtype
);
11808 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11811 memcpy (fixptr
- old
, fixptr
, new);
11813 fragp
->fr_fix
+= new - old
;
11819 /* This function is called after the relocs have been generated.
11820 We've been storing mips16 text labels as odd. Here we convert them
11821 back to even for the convenience of the debugger. */
11824 mips_frob_file_after_relocs ()
11827 unsigned int count
, i
;
11829 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11832 syms
= bfd_get_outsymbols (stdoutput
);
11833 count
= bfd_get_symcount (stdoutput
);
11834 for (i
= 0; i
< count
; i
++, syms
++)
11836 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11837 && ((*syms
)->value
& 1) != 0)
11839 (*syms
)->value
&= ~1;
11840 /* If the symbol has an odd size, it was probably computed
11841 incorrectly, so adjust that as well. */
11842 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11843 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11850 /* This function is called whenever a label is defined. It is used
11851 when handling branch delays; if a branch has a label, we assume we
11852 can not move it. */
11855 mips_define_label (sym
)
11858 struct insn_label_list
*l
;
11860 if (free_insn_labels
== NULL
)
11861 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11864 l
= free_insn_labels
;
11865 free_insn_labels
= l
->next
;
11869 l
->next
= insn_labels
;
11873 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11875 /* Some special processing for a MIPS ELF file. */
11878 mips_elf_final_processing ()
11880 /* Write out the register information. */
11885 s
.ri_gprmask
= mips_gprmask
;
11886 s
.ri_cprmask
[0] = mips_cprmask
[0];
11887 s
.ri_cprmask
[1] = mips_cprmask
[1];
11888 s
.ri_cprmask
[2] = mips_cprmask
[2];
11889 s
.ri_cprmask
[3] = mips_cprmask
[3];
11890 /* The gp_value field is set by the MIPS ELF backend. */
11892 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11893 ((Elf32_External_RegInfo
*)
11894 mips_regmask_frag
));
11898 Elf64_Internal_RegInfo s
;
11900 s
.ri_gprmask
= mips_gprmask
;
11902 s
.ri_cprmask
[0] = mips_cprmask
[0];
11903 s
.ri_cprmask
[1] = mips_cprmask
[1];
11904 s
.ri_cprmask
[2] = mips_cprmask
[2];
11905 s
.ri_cprmask
[3] = mips_cprmask
[3];
11906 /* The gp_value field is set by the MIPS ELF backend. */
11908 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11909 ((Elf64_External_RegInfo
*)
11910 mips_regmask_frag
));
11913 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11914 sort of BFD interface for this. */
11915 if (mips_any_noreorder
)
11916 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11917 if (mips_pic
!= NO_PIC
)
11918 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11920 /* Set the MIPS ELF ABI flags. */
11921 if (mips_abi
== NO_ABI
)
11923 else if (mips_abi
== O32_ABI
)
11924 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11925 else if (mips_abi
== O64_ABI
)
11926 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11927 else if (mips_abi
== EABI_ABI
)
11930 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11932 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11934 else if (mips_abi
== N32_ABI
)
11935 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
11937 /* Nothing to do for "64". */
11939 if (mips_32bitmode
)
11940 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11943 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11945 typedef struct proc
{
11947 unsigned long reg_mask
;
11948 unsigned long reg_offset
;
11949 unsigned long fpreg_mask
;
11950 unsigned long fpreg_offset
;
11951 unsigned long frame_offset
;
11952 unsigned long frame_reg
;
11953 unsigned long pc_reg
;
11956 static procS cur_proc
;
11957 static procS
*cur_proc_ptr
;
11958 static int numprocs
;
11960 /* Fill in an rs_align_code fragment. */
11963 mips_handle_align (fragp
)
11966 if (fragp
->fr_type
!= rs_align_code
)
11969 if (mips_opts
.mips16
)
11971 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11972 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11977 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
11978 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
11983 fragp
->fr_fix
+= 1;
11986 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
11990 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12001 /* check for premature end, nesting errors, etc */
12003 as_warn (_("missing .end at end of assembly"));
12012 if (*input_line_pointer
== '-')
12014 ++input_line_pointer
;
12017 if (!ISDIGIT (*input_line_pointer
))
12018 as_bad (_("Expected simple number."));
12019 if (input_line_pointer
[0] == '0')
12021 if (input_line_pointer
[1] == 'x')
12023 input_line_pointer
+= 2;
12024 while (ISXDIGIT (*input_line_pointer
))
12027 val
|= hex_value (*input_line_pointer
++);
12029 return negative
? -val
: val
;
12033 ++input_line_pointer
;
12034 while (ISDIGIT (*input_line_pointer
))
12037 val
|= *input_line_pointer
++ - '0';
12039 return negative
? -val
: val
;
12042 if (!ISDIGIT (*input_line_pointer
))
12044 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12045 *input_line_pointer
, *input_line_pointer
);
12046 as_warn (_("Invalid number"));
12049 while (ISDIGIT (*input_line_pointer
))
12052 val
+= *input_line_pointer
++ - '0';
12054 return negative
? -val
: val
;
12057 /* The .file directive; just like the usual .file directive, but there
12058 is an initial number which is the ECOFF file index. */
12062 int x ATTRIBUTE_UNUSED
;
12066 line
= get_number ();
12070 /* The .end directive. */
12074 int x ATTRIBUTE_UNUSED
;
12079 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12082 demand_empty_rest_of_line ();
12087 #ifdef BFD_ASSEMBLER
12088 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12093 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12100 as_warn (_(".end not in text section"));
12104 as_warn (_(".end directive without a preceding .ent directive."));
12105 demand_empty_rest_of_line ();
12111 assert (S_GET_NAME (p
));
12112 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12113 as_warn (_(".end symbol does not match .ent symbol."));
12116 as_warn (_(".end directive missing or unknown symbol"));
12118 #ifdef MIPS_STABS_ELF
12120 segT saved_seg
= now_seg
;
12121 subsegT saved_subseg
= now_subseg
;
12126 dot
= frag_now_fix ();
12128 #ifdef md_flush_pending_output
12129 md_flush_pending_output ();
12133 subseg_set (pdr_seg
, 0);
12135 /* Write the symbol. */
12136 exp
.X_op
= O_symbol
;
12137 exp
.X_add_symbol
= p
;
12138 exp
.X_add_number
= 0;
12139 emit_expr (&exp
, 4);
12141 fragp
= frag_more (7 * 4);
12143 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12144 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12145 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12146 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12147 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12148 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12149 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12151 subseg_set (saved_seg
, saved_subseg
);
12155 cur_proc_ptr
= NULL
;
12158 /* The .aent and .ent directives. */
12168 symbolP
= get_symbol ();
12169 if (*input_line_pointer
== ',')
12170 input_line_pointer
++;
12171 SKIP_WHITESPACE ();
12172 if (ISDIGIT (*input_line_pointer
)
12173 || *input_line_pointer
== '-')
12174 number
= get_number ();
12176 #ifdef BFD_ASSEMBLER
12177 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12182 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12189 as_warn (_(".ent or .aent not in text section."));
12191 if (!aent
&& cur_proc_ptr
)
12192 as_warn (_("missing .end"));
12196 cur_proc_ptr
= &cur_proc
;
12197 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12199 cur_proc_ptr
->isym
= symbolP
;
12201 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
12206 demand_empty_rest_of_line ();
12209 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12210 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12211 s_mips_frame is used so that we can set the PDR information correctly.
12212 We can't use the ecoff routines because they make reference to the ecoff
12213 symbol table (in the mdebug section). */
12216 s_mips_frame (ignore
)
12217 int ignore ATTRIBUTE_UNUSED
;
12219 #ifdef MIPS_STABS_ELF
12223 if (cur_proc_ptr
== (procS
*) NULL
)
12225 as_warn (_(".frame outside of .ent"));
12226 demand_empty_rest_of_line ();
12230 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12232 SKIP_WHITESPACE ();
12233 if (*input_line_pointer
++ != ','
12234 || get_absolute_expression_and_terminator (&val
) != ',')
12236 as_warn (_("Bad .frame directive"));
12237 --input_line_pointer
;
12238 demand_empty_rest_of_line ();
12242 cur_proc_ptr
->frame_offset
= val
;
12243 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12245 demand_empty_rest_of_line ();
12248 #endif /* MIPS_STABS_ELF */
12251 /* The .fmask and .mask directives. If the mdebug section is present
12252 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12253 embedded targets, s_mips_mask is used so that we can set the PDR
12254 information correctly. We can't use the ecoff routines because they
12255 make reference to the ecoff symbol table (in the mdebug section). */
12258 s_mips_mask (reg_type
)
12261 #ifdef MIPS_STABS_ELF
12264 if (cur_proc_ptr
== (procS
*) NULL
)
12266 as_warn (_(".mask/.fmask outside of .ent"));
12267 demand_empty_rest_of_line ();
12271 if (get_absolute_expression_and_terminator (&mask
) != ',')
12273 as_warn (_("Bad .mask/.fmask directive"));
12274 --input_line_pointer
;
12275 demand_empty_rest_of_line ();
12279 off
= get_absolute_expression ();
12281 if (reg_type
== 'F')
12283 cur_proc_ptr
->fpreg_mask
= mask
;
12284 cur_proc_ptr
->fpreg_offset
= off
;
12288 cur_proc_ptr
->reg_mask
= mask
;
12289 cur_proc_ptr
->reg_offset
= off
;
12292 demand_empty_rest_of_line ();
12294 s_ignore (reg_type
);
12295 #endif /* MIPS_STABS_ELF */
12298 /* The .loc directive. */
12309 assert (now_seg
== text_section
);
12311 lineno
= get_number ();
12312 addroff
= frag_now_fix ();
12314 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12315 S_SET_TYPE (symbolP
, N_SLINE
);
12316 S_SET_OTHER (symbolP
, 0);
12317 S_SET_DESC (symbolP
, lineno
);
12318 symbolP
->sy_segment
= now_seg
;
12322 /* CPU name/ISA/number mapping table.
12324 Entries are grouped by type. The first matching CPU or ISA entry
12325 gets chosen by CPU or ISA, so it should be the 'canonical' name
12326 for that type. Entries after that within the type are sorted
12329 Case is ignored in comparison, so put the canonical entry in the
12330 appropriate case but everything else in lower case to ease eye pain. */
12331 static const struct mips_cpu_info mips_cpu_info_table
[] =
12334 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12335 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12338 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12341 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12344 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12347 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12348 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12351 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12352 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12353 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12354 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
12355 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
12356 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
12358 /* For historical reasons. */
12359 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
12362 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
12363 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12364 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12365 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12368 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12369 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12370 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12371 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12374 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
12375 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
12376 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
12377 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12380 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12381 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12382 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12385 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12386 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12387 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12388 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12391 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12392 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12395 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12396 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12399 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12400 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12401 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12402 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12405 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12406 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12409 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12410 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12411 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12412 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12415 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12416 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12417 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12418 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12421 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12422 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12423 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12424 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12427 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
12428 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
12429 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
12430 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
12433 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12434 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12435 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12436 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12439 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12440 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12441 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12442 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12445 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12446 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12447 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12448 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12451 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12452 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12453 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12454 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12455 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12456 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12457 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
12458 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12459 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
12460 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12461 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
12462 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12463 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
12464 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12465 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
12466 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12467 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12469 /* SiByte SB-1 CPU */
12470 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12471 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12472 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12473 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12476 { NULL
, 0, 0, 0, },
12479 static const struct mips_cpu_info
*
12480 mips_cpu_info_from_name (name
)
12485 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12486 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12487 return (&mips_cpu_info_table
[i
]);
12492 static const struct mips_cpu_info
*
12493 mips_cpu_info_from_isa (isa
)
12498 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12499 if (mips_cpu_info_table
[i
].is_isa
12500 && isa
== mips_cpu_info_table
[i
].isa
)
12501 return (&mips_cpu_info_table
[i
]);
12506 static const struct mips_cpu_info
*
12507 mips_cpu_info_from_cpu (cpu
)
12512 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12513 if (!mips_cpu_info_table
[i
].is_isa
12514 && cpu
== mips_cpu_info_table
[i
].cpu
)
12515 return (&mips_cpu_info_table
[i
]);