1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode
*insn_mo
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode
;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p
: 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p
: 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p
: 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p
: 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p
: 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi
= NO_ABI
;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls
= FALSE
;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared
= TRUE
;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros
;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float
;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float
;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32
= -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32
= -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float
= 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float
= 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008
= FALSE
;
281 static struct mips_set_options mips_opts
=
283 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
287 /* soft_float */ FALSE
, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase
;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit
;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask
;
301 unsigned long mips_cprmask
[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa
= ISA_UNKNOWN
;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16
;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips
;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch
= CPU_UNKNOWN
;
331 static const char *mips_arch_string
;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune
= CPU_UNKNOWN
;
336 static const char *mips_tune_string
;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode
= 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic
;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got
= 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap
= 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction
;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder
;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix
;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value
= 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen
= 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS
*, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control
*op_hash
= NULL
;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control
*mips16_op_hash
= NULL
;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control
*micromips_op_hash
= NULL
;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars
[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars
[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars
[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS
[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format
{
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error
{
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format
;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error
;
671 static int auto_align
= 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset
= -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset
= -1;
683 static int mips_cpreturn_register
= -1;
684 static int mips_gp_register
= GP
;
685 static int mips_gprel_offset
= 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid
= 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg
= SP
;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid
= 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize
= 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug
= 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history
[1 + MAX_NOPS
];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array
{
731 const struct mips_operand
*operand
[MAX_OPERANDS
];
733 static struct mips_operand_array
*mips_operands
;
734 static struct mips_operand_array
*mips16_operands
;
735 static struct mips_operand_array
*micromips_operands
;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn
;
739 static struct mips_cl_insn mips16_nop_insn
;
740 static struct mips_cl_insn micromips_nop16_insn
;
741 static struct mips_cl_insn micromips_nop32_insn
;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS
*prev_nop_frag
;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds
;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required
;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since
;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup
*next
;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup
*mips_hi_fixup_list
;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS
*prev_reloc_op_frag
;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map
[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1
[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2
[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map
[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump
;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop
;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f
;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120
;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130
;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k
;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1
;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch
;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes
[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p
;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length
;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes
[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes
[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns
[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning
;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1226 static void append_insn
1227 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1228 bfd_boolean expansionp
);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS
*, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS
*, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS
*, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn
*ip
, char *str
);
1237 static void mips16_macro (struct mips_cl_insn
* ip
);
1238 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1239 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1245 static void my_getExpression (expressionS
*, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type
);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1282 static int relaxed_branch_length (fragS
*, asection
*, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name
; /* CPU or ISA name. */
1292 int flags
; /* MIPS_CPU_* flags. */
1293 int ase
; /* Set of ASEs implemented by the CPU. */
1294 int isa
; /* ISA level. */
1295 int cpu
; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts
= "O::g::G:";
1309 OPTION_MARCH
= OPTION_MD_BASE
,
1333 OPTION_NO_SMARTMIPS
,
1339 OPTION_NO_MICROMIPS
,
1342 OPTION_COMPAT_ARCH_BASE
,
1351 OPTION_M7000_HILO_FIX
,
1352 OPTION_MNO_7000_HILO_FIX
,
1355 OPTION_FIX_LOONGSON2F_JUMP
,
1356 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1357 OPTION_FIX_LOONGSON2F_NOP
,
1358 OPTION_NO_FIX_LOONGSON2F_NOP
,
1360 OPTION_NO_FIX_VR4120
,
1362 OPTION_NO_FIX_VR4130
,
1363 OPTION_FIX_CN63XXP1
,
1364 OPTION_NO_FIX_CN63XXP1
,
1371 OPTION_CONSTRUCT_FLOATS
,
1372 OPTION_NO_CONSTRUCT_FLOATS
,
1375 OPTION_RELAX_BRANCH
,
1376 OPTION_NO_RELAX_BRANCH
,
1385 OPTION_SINGLE_FLOAT
,
1386 OPTION_DOUBLE_FLOAT
,
1399 OPTION_MVXWORKS_PIC
,
1404 struct option md_longopts
[] =
1406 /* Options which specify architecture. */
1407 {"march", required_argument
, NULL
, OPTION_MARCH
},
1408 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1409 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1410 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1411 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1412 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1413 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1414 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1415 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1416 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1417 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1418 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1420 /* Options which specify Application Specific Extensions (ASEs). */
1421 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1422 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1423 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1424 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1425 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1426 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1427 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1428 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1429 {"mmt", no_argument
, NULL
, OPTION_MT
},
1430 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1431 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1432 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1433 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1434 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1435 {"meva", no_argument
, NULL
, OPTION_EVA
},
1436 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1437 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1438 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1439 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1440 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1441 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1442 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1444 /* Old-style architecture options. Don't add more of these. */
1445 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1446 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1447 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1448 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1449 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1450 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1451 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1452 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1454 /* Options which enable bug fixes. */
1455 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1456 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1457 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1458 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1459 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1460 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1461 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1462 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1463 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1464 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1465 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1466 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1467 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1468 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1469 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1471 /* Miscellaneous options. */
1472 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1473 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1474 {"break", no_argument
, NULL
, OPTION_BREAK
},
1475 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1476 {"EB", no_argument
, NULL
, OPTION_EB
},
1477 {"EL", no_argument
, NULL
, OPTION_EL
},
1478 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1479 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1480 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1481 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1482 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1483 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1484 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1485 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1486 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1487 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1488 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1489 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1490 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1491 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1492 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1493 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1494 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1495 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1497 /* Strictly speaking this next option is ELF specific,
1498 but we allow it for other ports as well in order to
1499 make testing easier. */
1500 {"32", no_argument
, NULL
, OPTION_32
},
1502 /* ELF-specific options. */
1503 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1504 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1505 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1506 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1507 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1508 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1509 {"n32", no_argument
, NULL
, OPTION_N32
},
1510 {"64", no_argument
, NULL
, OPTION_64
},
1511 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1512 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1513 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1514 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1515 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1516 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1518 {NULL
, no_argument
, NULL
, 0}
1520 size_t md_longopts_size
= sizeof (md_longopts
);
1522 /* Information about either an Application Specific Extension or an
1523 optional architecture feature that, for simplicity, we treat in the
1524 same way as an ASE. */
1527 /* The name of the ASE, used in both the command-line and .set options. */
1530 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1531 and 64-bit architectures, the flags here refer to the subset that
1532 is available on both. */
1535 /* The ASE_* flag used for instructions that are available on 64-bit
1536 architectures but that are not included in FLAGS. */
1537 unsigned int flags64
;
1539 /* The command-line options that turn the ASE on and off. */
1543 /* The minimum required architecture revisions for MIPS32, MIPS64,
1544 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1547 int micromips32_rev
;
1548 int micromips64_rev
;
1551 /* A table of all supported ASEs. */
1552 static const struct mips_ase mips_ases
[] = {
1553 { "dsp", ASE_DSP
, ASE_DSP64
,
1554 OPTION_DSP
, OPTION_NO_DSP
,
1557 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1558 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1561 { "eva", ASE_EVA
, 0,
1562 OPTION_EVA
, OPTION_NO_EVA
,
1565 { "mcu", ASE_MCU
, 0,
1566 OPTION_MCU
, OPTION_NO_MCU
,
1569 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1570 { "mdmx", ASE_MDMX
, 0,
1571 OPTION_MDMX
, OPTION_NO_MDMX
,
1574 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1575 { "mips3d", ASE_MIPS3D
, 0,
1576 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1580 OPTION_MT
, OPTION_NO_MT
,
1583 { "smartmips", ASE_SMARTMIPS
, 0,
1584 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1587 { "virt", ASE_VIRT
, ASE_VIRT64
,
1588 OPTION_VIRT
, OPTION_NO_VIRT
,
1592 /* The set of ASEs that require -mfp64. */
1593 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1595 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1596 static const unsigned int mips_ase_groups
[] = {
1602 The following pseudo-ops from the Kane and Heinrich MIPS book
1603 should be defined here, but are currently unsupported: .alias,
1604 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1606 The following pseudo-ops from the Kane and Heinrich MIPS book are
1607 specific to the type of debugging information being generated, and
1608 should be defined by the object format: .aent, .begin, .bend,
1609 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1612 The following pseudo-ops from the Kane and Heinrich MIPS book are
1613 not MIPS CPU specific, but are also not specific to the object file
1614 format. This file is probably the best place to define them, but
1615 they are not currently supported: .asm0, .endr, .lab, .struct. */
1617 static const pseudo_typeS mips_pseudo_table
[] =
1619 /* MIPS specific pseudo-ops. */
1620 {"option", s_option
, 0},
1621 {"set", s_mipsset
, 0},
1622 {"rdata", s_change_sec
, 'r'},
1623 {"sdata", s_change_sec
, 's'},
1624 {"livereg", s_ignore
, 0},
1625 {"abicalls", s_abicalls
, 0},
1626 {"cpload", s_cpload
, 0},
1627 {"cpsetup", s_cpsetup
, 0},
1628 {"cplocal", s_cplocal
, 0},
1629 {"cprestore", s_cprestore
, 0},
1630 {"cpreturn", s_cpreturn
, 0},
1631 {"dtprelword", s_dtprelword
, 0},
1632 {"dtpreldword", s_dtpreldword
, 0},
1633 {"tprelword", s_tprelword
, 0},
1634 {"tpreldword", s_tpreldword
, 0},
1635 {"gpvalue", s_gpvalue
, 0},
1636 {"gpword", s_gpword
, 0},
1637 {"gpdword", s_gpdword
, 0},
1638 {"ehword", s_ehword
, 0},
1639 {"cpadd", s_cpadd
, 0},
1640 {"insn", s_insn
, 0},
1643 /* Relatively generic pseudo-ops that happen to be used on MIPS
1645 {"asciiz", stringer
, 8 + 1},
1646 {"bss", s_change_sec
, 'b'},
1648 {"half", s_cons
, 1},
1649 {"dword", s_cons
, 3},
1650 {"weakext", s_mips_weakext
, 0},
1651 {"origin", s_org
, 0},
1652 {"repeat", s_rept
, 0},
1654 /* For MIPS this is non-standard, but we define it for consistency. */
1655 {"sbss", s_change_sec
, 'B'},
1657 /* These pseudo-ops are defined in read.c, but must be overridden
1658 here for one reason or another. */
1659 {"align", s_align
, 0},
1660 {"byte", s_cons
, 0},
1661 {"data", s_change_sec
, 'd'},
1662 {"double", s_float_cons
, 'd'},
1663 {"float", s_float_cons
, 'f'},
1664 {"globl", s_mips_globl
, 0},
1665 {"global", s_mips_globl
, 0},
1666 {"hword", s_cons
, 1},
1668 {"long", s_cons
, 2},
1669 {"octa", s_cons
, 4},
1670 {"quad", s_cons
, 3},
1671 {"section", s_change_section
, 0},
1672 {"short", s_cons
, 1},
1673 {"single", s_float_cons
, 'f'},
1674 {"stabd", s_mips_stab
, 'd'},
1675 {"stabn", s_mips_stab
, 'n'},
1676 {"stabs", s_mips_stab
, 's'},
1677 {"text", s_change_sec
, 't'},
1678 {"word", s_cons
, 2},
1680 { "extern", ecoff_directive_extern
, 0},
1685 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1687 /* These pseudo-ops should be defined by the object file format.
1688 However, a.out doesn't support them, so we have versions here. */
1689 {"aent", s_mips_ent
, 1},
1690 {"bgnb", s_ignore
, 0},
1691 {"end", s_mips_end
, 0},
1692 {"endb", s_ignore
, 0},
1693 {"ent", s_mips_ent
, 0},
1694 {"file", s_mips_file
, 0},
1695 {"fmask", s_mips_mask
, 'F'},
1696 {"frame", s_mips_frame
, 0},
1697 {"loc", s_mips_loc
, 0},
1698 {"mask", s_mips_mask
, 'R'},
1699 {"verstamp", s_ignore
, 0},
1703 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1704 purpose of the `.dc.a' internal pseudo-op. */
1707 mips_address_bytes (void)
1709 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1712 extern void pop_insert (const pseudo_typeS
*);
1715 mips_pop_insert (void)
1717 pop_insert (mips_pseudo_table
);
1718 if (! ECOFF_DEBUGGING
)
1719 pop_insert (mips_nonecoff_pseudo_table
);
1722 /* Symbols labelling the current insn. */
1724 struct insn_label_list
1726 struct insn_label_list
*next
;
1730 static struct insn_label_list
*free_insn_labels
;
1731 #define label_list tc_segment_info_data.labels
1733 static void mips_clear_insn_labels (void);
1734 static void mips_mark_labels (void);
1735 static void mips_compressed_mark_labels (void);
1738 mips_clear_insn_labels (void)
1740 register struct insn_label_list
**pl
;
1741 segment_info_type
*si
;
1745 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1748 si
= seg_info (now_seg
);
1749 *pl
= si
->label_list
;
1750 si
->label_list
= NULL
;
1754 /* Mark instruction labels in MIPS16/microMIPS mode. */
1757 mips_mark_labels (void)
1759 if (HAVE_CODE_COMPRESSION
)
1760 mips_compressed_mark_labels ();
1763 static char *expr_end
;
1765 /* Expressions which appear in macro instructions. These are set by
1766 mips_ip and read by macro. */
1768 static expressionS imm_expr
;
1769 static expressionS imm2_expr
;
1771 /* The relocatable field in an instruction and the relocs associated
1772 with it. These variables are used for instructions like LUI and
1773 JAL as well as true offsets. They are also used for address
1774 operands in macros. */
1776 static expressionS offset_expr
;
1777 static bfd_reloc_code_real_type offset_reloc
[3]
1778 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1780 /* This is set to the resulting size of the instruction to be produced
1781 by mips16_ip if an explicit extension is used or by mips_ip if an
1782 explicit size is supplied. */
1784 static unsigned int forced_insn_length
;
1786 /* True if we are assembling an instruction. All dot symbols defined during
1787 this time should be treated as code labels. */
1789 static bfd_boolean mips_assembling_insn
;
1791 /* The pdr segment for per procedure frame/regmask info. Not used for
1794 static segT pdr_seg
;
1796 /* The default target format to use. */
1798 #if defined (TE_FreeBSD)
1799 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1800 #elif defined (TE_TMIPS)
1801 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1803 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1807 mips_target_format (void)
1809 switch (OUTPUT_FLAVOR
)
1811 case bfd_target_elf_flavour
:
1813 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1814 return (target_big_endian
1815 ? "elf32-bigmips-vxworks"
1816 : "elf32-littlemips-vxworks");
1818 return (target_big_endian
1819 ? (HAVE_64BIT_OBJECTS
1820 ? ELF_TARGET ("elf64-", "big")
1822 ? ELF_TARGET ("elf32-n", "big")
1823 : ELF_TARGET ("elf32-", "big")))
1824 : (HAVE_64BIT_OBJECTS
1825 ? ELF_TARGET ("elf64-", "little")
1827 ? ELF_TARGET ("elf32-n", "little")
1828 : ELF_TARGET ("elf32-", "little"))));
1835 /* Return the ISA revision that is currently in use, or 0 if we are
1836 generating code for MIPS V or below. */
1841 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1844 /* microMIPS implies revision 2 or above. */
1845 if (mips_opts
.micromips
)
1848 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1854 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1857 mips_ase_mask (unsigned int flags
)
1861 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1862 if (flags
& mips_ase_groups
[i
])
1863 flags
|= mips_ase_groups
[i
];
1867 /* Check whether the current ISA supports ASE. Issue a warning if
1871 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1875 static unsigned int warned_isa
;
1876 static unsigned int warned_fp32
;
1878 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1879 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1881 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1882 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1883 && (warned_isa
& ase
->flags
) != ase
->flags
)
1885 warned_isa
|= ase
->flags
;
1886 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1887 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1889 as_warn (_("The %d-bit %s architecture does not support the"
1890 " `%s' extension"), size
, base
, ase
->name
);
1892 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1893 ase
->name
, base
, size
, min_rev
);
1895 if ((ase
->flags
& FP64_ASES
)
1897 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1899 warned_fp32
|= ase
->flags
;
1900 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1904 /* Check all enabled ASEs to see whether they are supported by the
1905 chosen architecture. */
1908 mips_check_isa_supports_ases (void)
1910 unsigned int i
, mask
;
1912 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1914 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1915 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1916 mips_check_isa_supports_ase (&mips_ases
[i
]);
1920 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1921 that were affected. */
1924 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1928 mask
= mips_ase_mask (ase
->flags
);
1929 mips_opts
.ase
&= ~mask
;
1931 mips_opts
.ase
|= ase
->flags
;
1935 /* Return the ASE called NAME, or null if none. */
1937 static const struct mips_ase
*
1938 mips_lookup_ase (const char *name
)
1942 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1943 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1944 return &mips_ases
[i
];
1948 /* Return the length of a microMIPS instruction in bytes. If bits of
1949 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1950 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1951 major opcode) will require further modifications to the opcode
1954 static inline unsigned int
1955 micromips_insn_length (const struct mips_opcode
*mo
)
1957 return (mo
->mask
>> 16) == 0 ? 2 : 4;
1960 /* Return the length of MIPS16 instruction OPCODE. */
1962 static inline unsigned int
1963 mips16_opcode_length (unsigned long opcode
)
1965 return (opcode
>> 16) == 0 ? 2 : 4;
1968 /* Return the length of instruction INSN. */
1970 static inline unsigned int
1971 insn_length (const struct mips_cl_insn
*insn
)
1973 if (mips_opts
.micromips
)
1974 return micromips_insn_length (insn
->insn_mo
);
1975 else if (mips_opts
.mips16
)
1976 return mips16_opcode_length (insn
->insn_opcode
);
1981 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1984 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1989 insn
->insn_opcode
= mo
->match
;
1992 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1993 insn
->fixp
[i
] = NULL
;
1994 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1995 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1996 insn
->mips16_absolute_jump_p
= 0;
1997 insn
->complete_p
= 0;
1998 insn
->cleared_p
= 0;
2001 /* Get a list of all the operands in INSN. */
2003 static const struct mips_operand_array
*
2004 insn_operands (const struct mips_cl_insn
*insn
)
2006 if (insn
->insn_mo
>= &mips_opcodes
[0]
2007 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2008 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2010 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2011 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2012 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2014 if (insn
->insn_mo
>= µmips_opcodes
[0]
2015 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2016 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2021 /* Get a description of operand OPNO of INSN. */
2023 static const struct mips_operand
*
2024 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2026 const struct mips_operand_array
*operands
;
2028 operands
= insn_operands (insn
);
2029 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2031 return operands
->operand
[opno
];
2034 /* Install UVAL as the value of OPERAND in INSN. */
2037 insn_insert_operand (struct mips_cl_insn
*insn
,
2038 const struct mips_operand
*operand
, unsigned int uval
)
2040 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2043 /* Extract the value of OPERAND from INSN. */
2045 static inline unsigned
2046 insn_extract_operand (const struct mips_cl_insn
*insn
,
2047 const struct mips_operand
*operand
)
2049 return mips_extract_operand (operand
, insn
->insn_opcode
);
2052 /* Record the current MIPS16/microMIPS mode in now_seg. */
2055 mips_record_compressed_mode (void)
2057 segment_info_type
*si
;
2059 si
= seg_info (now_seg
);
2060 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2061 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2062 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2063 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2066 /* Read a standard MIPS instruction from BUF. */
2068 static unsigned long
2069 read_insn (char *buf
)
2071 if (target_big_endian
)
2072 return bfd_getb32 ((bfd_byte
*) buf
);
2074 return bfd_getl32 ((bfd_byte
*) buf
);
2077 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2081 write_insn (char *buf
, unsigned int insn
)
2083 md_number_to_chars (buf
, insn
, 4);
2087 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2088 has length LENGTH. */
2090 static unsigned long
2091 read_compressed_insn (char *buf
, unsigned int length
)
2097 for (i
= 0; i
< length
; i
+= 2)
2100 if (target_big_endian
)
2101 insn
|= bfd_getb16 ((char *) buf
);
2103 insn
|= bfd_getl16 ((char *) buf
);
2109 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2110 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2113 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2117 for (i
= 0; i
< length
; i
+= 2)
2118 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2119 return buf
+ length
;
2122 /* Install INSN at the location specified by its "frag" and "where" fields. */
2125 install_insn (const struct mips_cl_insn
*insn
)
2127 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2128 if (HAVE_CODE_COMPRESSION
)
2129 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2131 write_insn (f
, insn
->insn_opcode
);
2132 mips_record_compressed_mode ();
2135 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2136 and install the opcode in the new location. */
2139 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2144 insn
->where
= where
;
2145 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2146 if (insn
->fixp
[i
] != NULL
)
2148 insn
->fixp
[i
]->fx_frag
= frag
;
2149 insn
->fixp
[i
]->fx_where
= where
;
2151 install_insn (insn
);
2154 /* Add INSN to the end of the output. */
2157 add_fixed_insn (struct mips_cl_insn
*insn
)
2159 char *f
= frag_more (insn_length (insn
));
2160 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2163 /* Start a variant frag and move INSN to the start of the variant part,
2164 marking it as fixed. The other arguments are as for frag_var. */
2167 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2168 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2170 frag_grow (max_chars
);
2171 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2173 frag_var (rs_machine_dependent
, max_chars
, var
,
2174 subtype
, symbol
, offset
, NULL
);
2177 /* Insert N copies of INSN into the history buffer, starting at
2178 position FIRST. Neither FIRST nor N need to be clipped. */
2181 insert_into_history (unsigned int first
, unsigned int n
,
2182 const struct mips_cl_insn
*insn
)
2184 if (mips_relax
.sequence
!= 2)
2188 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2190 history
[i
] = history
[i
- n
];
2196 /* Clear the error in insn_error. */
2199 clear_insn_error (void)
2201 memset (&insn_error
, 0, sizeof (insn_error
));
2204 /* Possibly record error message MSG for the current instruction.
2205 If the error is about a particular argument, ARGNUM is the 1-based
2206 number of that argument, otherwise it is 0. FORMAT is the format
2207 of MSG. Return true if MSG was used, false if the current message
2211 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2216 /* Give priority to errors against specific arguments, and to
2217 the first whole-instruction message. */
2223 /* Keep insn_error if it is against a later argument. */
2224 if (argnum
< insn_error
.min_argnum
)
2227 /* If both errors are against the same argument but are different,
2228 give up on reporting a specific error for this argument.
2229 See the comment about mips_insn_error for details. */
2230 if (argnum
== insn_error
.min_argnum
2232 && strcmp (insn_error
.msg
, msg
) != 0)
2235 insn_error
.min_argnum
+= 1;
2239 insn_error
.min_argnum
= argnum
;
2240 insn_error
.format
= format
;
2241 insn_error
.msg
= msg
;
2245 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2246 as for set_insn_error_format. */
2249 set_insn_error (int argnum
, const char *msg
)
2251 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2254 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2255 as for set_insn_error_format. */
2258 set_insn_error_i (int argnum
, const char *msg
, int i
)
2260 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2264 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2265 are as for set_insn_error_format. */
2268 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2270 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2272 insn_error
.u
.ss
[0] = s1
;
2273 insn_error
.u
.ss
[1] = s2
;
2277 /* Report the error in insn_error, which is against assembly code STR. */
2280 report_insn_error (const char *str
)
2284 msg
= ACONCAT ((insn_error
.msg
, " `%s'", NULL
));
2285 switch (insn_error
.format
)
2292 as_bad (msg
, insn_error
.u
.i
, str
);
2296 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2301 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2302 the idea is to make it obvious at a glance that each errata is
2306 init_vr4120_conflicts (void)
2308 #define CONFLICT(FIRST, SECOND) \
2309 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2311 /* Errata 21 - [D]DIV[U] after [D]MACC */
2312 CONFLICT (MACC
, DIV
);
2313 CONFLICT (DMACC
, DIV
);
2315 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2316 CONFLICT (DMULT
, DMULT
);
2317 CONFLICT (DMULT
, DMACC
);
2318 CONFLICT (DMACC
, DMULT
);
2319 CONFLICT (DMACC
, DMACC
);
2321 /* Errata 24 - MT{LO,HI} after [D]MACC */
2322 CONFLICT (MACC
, MTHILO
);
2323 CONFLICT (DMACC
, MTHILO
);
2325 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2326 instruction is executed immediately after a MACC or DMACC
2327 instruction, the result of [either instruction] is incorrect." */
2328 CONFLICT (MACC
, MULT
);
2329 CONFLICT (MACC
, DMULT
);
2330 CONFLICT (DMACC
, MULT
);
2331 CONFLICT (DMACC
, DMULT
);
2333 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2334 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2335 DDIV or DDIVU instruction, the result of the MACC or
2336 DMACC instruction is incorrect.". */
2337 CONFLICT (DMULT
, MACC
);
2338 CONFLICT (DMULT
, DMACC
);
2339 CONFLICT (DIV
, MACC
);
2340 CONFLICT (DIV
, DMACC
);
2350 #define RNUM_MASK 0x00000ff
2351 #define RTYPE_MASK 0x0efff00
2352 #define RTYPE_NUM 0x0000100
2353 #define RTYPE_FPU 0x0000200
2354 #define RTYPE_FCC 0x0000400
2355 #define RTYPE_VEC 0x0000800
2356 #define RTYPE_GP 0x0001000
2357 #define RTYPE_CP0 0x0002000
2358 #define RTYPE_PC 0x0004000
2359 #define RTYPE_ACC 0x0008000
2360 #define RTYPE_CCC 0x0010000
2361 #define RTYPE_VI 0x0020000
2362 #define RTYPE_VF 0x0040000
2363 #define RTYPE_R5900_I 0x0080000
2364 #define RTYPE_R5900_Q 0x0100000
2365 #define RTYPE_R5900_R 0x0200000
2366 #define RTYPE_R5900_ACC 0x0400000
2367 #define RWARN 0x8000000
2369 #define GENERIC_REGISTER_NUMBERS \
2370 {"$0", RTYPE_NUM | 0}, \
2371 {"$1", RTYPE_NUM | 1}, \
2372 {"$2", RTYPE_NUM | 2}, \
2373 {"$3", RTYPE_NUM | 3}, \
2374 {"$4", RTYPE_NUM | 4}, \
2375 {"$5", RTYPE_NUM | 5}, \
2376 {"$6", RTYPE_NUM | 6}, \
2377 {"$7", RTYPE_NUM | 7}, \
2378 {"$8", RTYPE_NUM | 8}, \
2379 {"$9", RTYPE_NUM | 9}, \
2380 {"$10", RTYPE_NUM | 10}, \
2381 {"$11", RTYPE_NUM | 11}, \
2382 {"$12", RTYPE_NUM | 12}, \
2383 {"$13", RTYPE_NUM | 13}, \
2384 {"$14", RTYPE_NUM | 14}, \
2385 {"$15", RTYPE_NUM | 15}, \
2386 {"$16", RTYPE_NUM | 16}, \
2387 {"$17", RTYPE_NUM | 17}, \
2388 {"$18", RTYPE_NUM | 18}, \
2389 {"$19", RTYPE_NUM | 19}, \
2390 {"$20", RTYPE_NUM | 20}, \
2391 {"$21", RTYPE_NUM | 21}, \
2392 {"$22", RTYPE_NUM | 22}, \
2393 {"$23", RTYPE_NUM | 23}, \
2394 {"$24", RTYPE_NUM | 24}, \
2395 {"$25", RTYPE_NUM | 25}, \
2396 {"$26", RTYPE_NUM | 26}, \
2397 {"$27", RTYPE_NUM | 27}, \
2398 {"$28", RTYPE_NUM | 28}, \
2399 {"$29", RTYPE_NUM | 29}, \
2400 {"$30", RTYPE_NUM | 30}, \
2401 {"$31", RTYPE_NUM | 31}
2403 #define FPU_REGISTER_NAMES \
2404 {"$f0", RTYPE_FPU | 0}, \
2405 {"$f1", RTYPE_FPU | 1}, \
2406 {"$f2", RTYPE_FPU | 2}, \
2407 {"$f3", RTYPE_FPU | 3}, \
2408 {"$f4", RTYPE_FPU | 4}, \
2409 {"$f5", RTYPE_FPU | 5}, \
2410 {"$f6", RTYPE_FPU | 6}, \
2411 {"$f7", RTYPE_FPU | 7}, \
2412 {"$f8", RTYPE_FPU | 8}, \
2413 {"$f9", RTYPE_FPU | 9}, \
2414 {"$f10", RTYPE_FPU | 10}, \
2415 {"$f11", RTYPE_FPU | 11}, \
2416 {"$f12", RTYPE_FPU | 12}, \
2417 {"$f13", RTYPE_FPU | 13}, \
2418 {"$f14", RTYPE_FPU | 14}, \
2419 {"$f15", RTYPE_FPU | 15}, \
2420 {"$f16", RTYPE_FPU | 16}, \
2421 {"$f17", RTYPE_FPU | 17}, \
2422 {"$f18", RTYPE_FPU | 18}, \
2423 {"$f19", RTYPE_FPU | 19}, \
2424 {"$f20", RTYPE_FPU | 20}, \
2425 {"$f21", RTYPE_FPU | 21}, \
2426 {"$f22", RTYPE_FPU | 22}, \
2427 {"$f23", RTYPE_FPU | 23}, \
2428 {"$f24", RTYPE_FPU | 24}, \
2429 {"$f25", RTYPE_FPU | 25}, \
2430 {"$f26", RTYPE_FPU | 26}, \
2431 {"$f27", RTYPE_FPU | 27}, \
2432 {"$f28", RTYPE_FPU | 28}, \
2433 {"$f29", RTYPE_FPU | 29}, \
2434 {"$f30", RTYPE_FPU | 30}, \
2435 {"$f31", RTYPE_FPU | 31}
2437 #define FPU_CONDITION_CODE_NAMES \
2438 {"$fcc0", RTYPE_FCC | 0}, \
2439 {"$fcc1", RTYPE_FCC | 1}, \
2440 {"$fcc2", RTYPE_FCC | 2}, \
2441 {"$fcc3", RTYPE_FCC | 3}, \
2442 {"$fcc4", RTYPE_FCC | 4}, \
2443 {"$fcc5", RTYPE_FCC | 5}, \
2444 {"$fcc6", RTYPE_FCC | 6}, \
2445 {"$fcc7", RTYPE_FCC | 7}
2447 #define COPROC_CONDITION_CODE_NAMES \
2448 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2449 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2450 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2451 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2452 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2453 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2454 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2455 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2457 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2458 {"$a4", RTYPE_GP | 8}, \
2459 {"$a5", RTYPE_GP | 9}, \
2460 {"$a6", RTYPE_GP | 10}, \
2461 {"$a7", RTYPE_GP | 11}, \
2462 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2463 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2464 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2465 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2466 {"$t0", RTYPE_GP | 12}, \
2467 {"$t1", RTYPE_GP | 13}, \
2468 {"$t2", RTYPE_GP | 14}, \
2469 {"$t3", RTYPE_GP | 15}
2471 #define O32_SYMBOLIC_REGISTER_NAMES \
2472 {"$t0", RTYPE_GP | 8}, \
2473 {"$t1", RTYPE_GP | 9}, \
2474 {"$t2", RTYPE_GP | 10}, \
2475 {"$t3", RTYPE_GP | 11}, \
2476 {"$t4", RTYPE_GP | 12}, \
2477 {"$t5", RTYPE_GP | 13}, \
2478 {"$t6", RTYPE_GP | 14}, \
2479 {"$t7", RTYPE_GP | 15}, \
2480 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2481 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2482 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2483 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2485 /* Remaining symbolic register names */
2486 #define SYMBOLIC_REGISTER_NAMES \
2487 {"$zero", RTYPE_GP | 0}, \
2488 {"$at", RTYPE_GP | 1}, \
2489 {"$AT", RTYPE_GP | 1}, \
2490 {"$v0", RTYPE_GP | 2}, \
2491 {"$v1", RTYPE_GP | 3}, \
2492 {"$a0", RTYPE_GP | 4}, \
2493 {"$a1", RTYPE_GP | 5}, \
2494 {"$a2", RTYPE_GP | 6}, \
2495 {"$a3", RTYPE_GP | 7}, \
2496 {"$s0", RTYPE_GP | 16}, \
2497 {"$s1", RTYPE_GP | 17}, \
2498 {"$s2", RTYPE_GP | 18}, \
2499 {"$s3", RTYPE_GP | 19}, \
2500 {"$s4", RTYPE_GP | 20}, \
2501 {"$s5", RTYPE_GP | 21}, \
2502 {"$s6", RTYPE_GP | 22}, \
2503 {"$s7", RTYPE_GP | 23}, \
2504 {"$t8", RTYPE_GP | 24}, \
2505 {"$t9", RTYPE_GP | 25}, \
2506 {"$k0", RTYPE_GP | 26}, \
2507 {"$kt0", RTYPE_GP | 26}, \
2508 {"$k1", RTYPE_GP | 27}, \
2509 {"$kt1", RTYPE_GP | 27}, \
2510 {"$gp", RTYPE_GP | 28}, \
2511 {"$sp", RTYPE_GP | 29}, \
2512 {"$s8", RTYPE_GP | 30}, \
2513 {"$fp", RTYPE_GP | 30}, \
2514 {"$ra", RTYPE_GP | 31}
2516 #define MIPS16_SPECIAL_REGISTER_NAMES \
2517 {"$pc", RTYPE_PC | 0}
2519 #define MDMX_VECTOR_REGISTER_NAMES \
2520 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2521 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2522 {"$v2", RTYPE_VEC | 2}, \
2523 {"$v3", RTYPE_VEC | 3}, \
2524 {"$v4", RTYPE_VEC | 4}, \
2525 {"$v5", RTYPE_VEC | 5}, \
2526 {"$v6", RTYPE_VEC | 6}, \
2527 {"$v7", RTYPE_VEC | 7}, \
2528 {"$v8", RTYPE_VEC | 8}, \
2529 {"$v9", RTYPE_VEC | 9}, \
2530 {"$v10", RTYPE_VEC | 10}, \
2531 {"$v11", RTYPE_VEC | 11}, \
2532 {"$v12", RTYPE_VEC | 12}, \
2533 {"$v13", RTYPE_VEC | 13}, \
2534 {"$v14", RTYPE_VEC | 14}, \
2535 {"$v15", RTYPE_VEC | 15}, \
2536 {"$v16", RTYPE_VEC | 16}, \
2537 {"$v17", RTYPE_VEC | 17}, \
2538 {"$v18", RTYPE_VEC | 18}, \
2539 {"$v19", RTYPE_VEC | 19}, \
2540 {"$v20", RTYPE_VEC | 20}, \
2541 {"$v21", RTYPE_VEC | 21}, \
2542 {"$v22", RTYPE_VEC | 22}, \
2543 {"$v23", RTYPE_VEC | 23}, \
2544 {"$v24", RTYPE_VEC | 24}, \
2545 {"$v25", RTYPE_VEC | 25}, \
2546 {"$v26", RTYPE_VEC | 26}, \
2547 {"$v27", RTYPE_VEC | 27}, \
2548 {"$v28", RTYPE_VEC | 28}, \
2549 {"$v29", RTYPE_VEC | 29}, \
2550 {"$v30", RTYPE_VEC | 30}, \
2551 {"$v31", RTYPE_VEC | 31}
2553 #define R5900_I_NAMES \
2554 {"$I", RTYPE_R5900_I | 0}
2556 #define R5900_Q_NAMES \
2557 {"$Q", RTYPE_R5900_Q | 0}
2559 #define R5900_R_NAMES \
2560 {"$R", RTYPE_R5900_R | 0}
2562 #define R5900_ACC_NAMES \
2563 {"$ACC", RTYPE_R5900_ACC | 0 }
2565 #define MIPS_DSP_ACCUMULATOR_NAMES \
2566 {"$ac0", RTYPE_ACC | 0}, \
2567 {"$ac1", RTYPE_ACC | 1}, \
2568 {"$ac2", RTYPE_ACC | 2}, \
2569 {"$ac3", RTYPE_ACC | 3}
2571 static const struct regname reg_names
[] = {
2572 GENERIC_REGISTER_NUMBERS
,
2574 FPU_CONDITION_CODE_NAMES
,
2575 COPROC_CONDITION_CODE_NAMES
,
2577 /* The $txx registers depends on the abi,
2578 these will be added later into the symbol table from
2579 one of the tables below once mips_abi is set after
2580 parsing of arguments from the command line. */
2581 SYMBOLIC_REGISTER_NAMES
,
2583 MIPS16_SPECIAL_REGISTER_NAMES
,
2584 MDMX_VECTOR_REGISTER_NAMES
,
2589 MIPS_DSP_ACCUMULATOR_NAMES
,
2593 static const struct regname reg_names_o32
[] = {
2594 O32_SYMBOLIC_REGISTER_NAMES
,
2598 static const struct regname reg_names_n32n64
[] = {
2599 N32N64_SYMBOLIC_REGISTER_NAMES
,
2603 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2604 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2605 of these register symbols, return the associated vector register,
2606 otherwise return SYMVAL itself. */
2609 mips_prefer_vec_regno (unsigned int symval
)
2611 if ((symval
& -2) == (RTYPE_GP
| 2))
2612 return RTYPE_VEC
| (symval
& 1);
2616 /* Return true if string [S, E) is a valid register name, storing its
2617 symbol value in *SYMVAL_PTR if so. */
2620 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2625 /* Terminate name. */
2629 /* Look up the name. */
2630 symbol
= symbol_find (s
);
2633 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2636 *symval_ptr
= S_GET_VALUE (symbol
);
2640 /* Return true if the string at *SPTR is a valid register name. Allow it
2641 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2644 When returning true, move *SPTR past the register, store the
2645 register's symbol value in *SYMVAL_PTR and the channel mask in
2646 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2647 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2648 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2651 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2652 unsigned int *channels_ptr
)
2656 unsigned int channels
, symval
, bit
;
2658 /* Find end of name. */
2660 if (is_name_beginner (*e
))
2662 while (is_part_of_name (*e
))
2666 if (!mips_parse_register_1 (s
, e
, &symval
))
2671 /* Eat characters from the end of the string that are valid
2672 channel suffixes. The preceding register must be $ACC or
2673 end with a digit, so there is no ambiguity. */
2676 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
2677 if (m
> s
&& m
[-1] == *q
)
2684 || !mips_parse_register_1 (s
, m
, &symval
)
2685 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
2690 *symval_ptr
= symval
;
2692 *channels_ptr
= channels
;
2696 /* Check if SPTR points at a valid register specifier according to TYPES.
2697 If so, then return 1, advance S to consume the specifier and store
2698 the register's number in REGNOP, otherwise return 0. */
2701 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2705 if (mips_parse_register (s
, ®no
, NULL
))
2707 if (types
& RTYPE_VEC
)
2708 regno
= mips_prefer_vec_regno (regno
);
2717 as_warn (_("Unrecognized register name `%s'"), *s
);
2722 return regno
<= RNUM_MASK
;
2725 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2726 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2729 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
2734 for (i
= 0; i
< 4; i
++)
2735 if (*s
== "xyzw"[i
])
2737 *channels
|= 1 << (3 - i
);
2743 /* Token types for parsed operand lists. */
2744 enum mips_operand_token_type
{
2745 /* A plain register, e.g. $f2. */
2748 /* A 4-bit XYZW channel mask. */
2751 /* An element of a vector, e.g. $v0[1]. */
2754 /* A continuous range of registers, e.g. $s0-$s4. */
2757 /* A (possibly relocated) expression. */
2760 /* A floating-point value. */
2763 /* A single character. This can be '(', ')' or ',', but '(' only appears
2767 /* A doubled character, either "--" or "++". */
2770 /* The end of the operand list. */
2774 /* A parsed operand token. */
2775 struct mips_operand_token
2777 /* The type of token. */
2778 enum mips_operand_token_type type
;
2781 /* The register symbol value for an OT_REG. */
2784 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2785 unsigned int channels
;
2787 /* The register symbol value and index for an OT_REG_ELEMENT. */
2793 /* The two register symbol values involved in an OT_REG_RANGE. */
2795 unsigned int regno1
;
2796 unsigned int regno2
;
2799 /* The value of an OT_INTEGER. The value is represented as an
2800 expression and the relocation operators that were applied to
2801 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2802 relocation operators were used. */
2805 bfd_reloc_code_real_type relocs
[3];
2808 /* The binary data for an OT_FLOAT constant, and the number of bytes
2811 unsigned char data
[8];
2815 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2820 /* An obstack used to construct lists of mips_operand_tokens. */
2821 static struct obstack mips_operand_tokens
;
2823 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2826 mips_add_token (struct mips_operand_token
*token
,
2827 enum mips_operand_token_type type
)
2830 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
2833 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2834 and OT_REG tokens for them if so, and return a pointer to the first
2835 unconsumed character. Return null otherwise. */
2838 mips_parse_base_start (char *s
)
2840 struct mips_operand_token token
;
2841 unsigned int regno
, channels
;
2842 bfd_boolean decrement_p
;
2848 SKIP_SPACE_TABS (s
);
2850 /* Only match "--" as part of a base expression. In other contexts "--X"
2851 is a double negative. */
2852 decrement_p
= (s
[0] == '-' && s
[1] == '-');
2856 SKIP_SPACE_TABS (s
);
2859 /* Allow a channel specifier because that leads to better error messages
2860 than treating something like "$vf0x++" as an expression. */
2861 if (!mips_parse_register (&s
, ®no
, &channels
))
2865 mips_add_token (&token
, OT_CHAR
);
2870 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2873 token
.u
.regno
= regno
;
2874 mips_add_token (&token
, OT_REG
);
2878 token
.u
.channels
= channels
;
2879 mips_add_token (&token
, OT_CHANNELS
);
2882 /* For consistency, only match "++" as part of base expressions too. */
2883 SKIP_SPACE_TABS (s
);
2884 if (s
[0] == '+' && s
[1] == '+')
2888 mips_add_token (&token
, OT_DOUBLE_CHAR
);
2894 /* Parse one or more tokens from S. Return a pointer to the first
2895 unconsumed character on success. Return null if an error was found
2896 and store the error text in insn_error. FLOAT_FORMAT is as for
2897 mips_parse_arguments. */
2900 mips_parse_argument_token (char *s
, char float_format
)
2902 char *end
, *save_in
, *err
;
2903 unsigned int regno1
, regno2
, channels
;
2904 struct mips_operand_token token
;
2906 /* First look for "($reg", since we want to treat that as an
2907 OT_CHAR and OT_REG rather than an expression. */
2908 end
= mips_parse_base_start (s
);
2912 /* Handle other characters that end up as OT_CHARs. */
2913 if (*s
== ')' || *s
== ',')
2916 mips_add_token (&token
, OT_CHAR
);
2921 /* Handle tokens that start with a register. */
2922 if (mips_parse_register (&s
, ®no1
, &channels
))
2926 /* A register and a VU0 channel suffix. */
2927 token
.u
.regno
= regno1
;
2928 mips_add_token (&token
, OT_REG
);
2930 token
.u
.channels
= channels
;
2931 mips_add_token (&token
, OT_CHANNELS
);
2935 SKIP_SPACE_TABS (s
);
2938 /* A register range. */
2940 SKIP_SPACE_TABS (s
);
2941 if (!mips_parse_register (&s
, ®no2
, NULL
))
2943 set_insn_error (0, _("Invalid register range"));
2947 token
.u
.reg_range
.regno1
= regno1
;
2948 token
.u
.reg_range
.regno2
= regno2
;
2949 mips_add_token (&token
, OT_REG_RANGE
);
2954 /* A vector element. */
2955 expressionS element
;
2958 SKIP_SPACE_TABS (s
);
2959 my_getExpression (&element
, s
);
2960 if (element
.X_op
!= O_constant
)
2962 set_insn_error (0, _("Vector element must be constant"));
2966 SKIP_SPACE_TABS (s
);
2969 set_insn_error (0, _("Missing `]'"));
2974 token
.u
.reg_element
.regno
= regno1
;
2975 token
.u
.reg_element
.index
= element
.X_add_number
;
2976 mips_add_token (&token
, OT_REG_ELEMENT
);
2980 /* Looks like just a plain register. */
2981 token
.u
.regno
= regno1
;
2982 mips_add_token (&token
, OT_REG
);
2988 /* First try to treat expressions as floats. */
2989 save_in
= input_line_pointer
;
2990 input_line_pointer
= s
;
2991 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
2992 &token
.u
.flt
.length
);
2993 end
= input_line_pointer
;
2994 input_line_pointer
= save_in
;
2997 set_insn_error (0, err
);
3002 mips_add_token (&token
, OT_FLOAT
);
3007 /* Treat everything else as an integer expression. */
3008 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3009 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3010 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3011 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3013 mips_add_token (&token
, OT_INTEGER
);
3017 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3018 if expressions should be treated as 32-bit floating-point constants,
3019 'd' if they should be treated as 64-bit floating-point constants,
3020 or 0 if they should be treated as integer expressions (the usual case).
3022 Return a list of tokens on success, otherwise return 0. The caller
3023 must obstack_free the list after use. */
3025 static struct mips_operand_token
*
3026 mips_parse_arguments (char *s
, char float_format
)
3028 struct mips_operand_token token
;
3030 SKIP_SPACE_TABS (s
);
3033 s
= mips_parse_argument_token (s
, float_format
);
3036 obstack_free (&mips_operand_tokens
,
3037 obstack_finish (&mips_operand_tokens
));
3040 SKIP_SPACE_TABS (s
);
3042 mips_add_token (&token
, OT_END
);
3043 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3046 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3047 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3050 is_opcode_valid (const struct mips_opcode
*mo
)
3052 int isa
= mips_opts
.isa
;
3053 int ase
= mips_opts
.ase
;
3057 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3058 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3059 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3060 ase
|= mips_ases
[i
].flags64
;
3062 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3065 /* Check whether the instruction or macro requires single-precision or
3066 double-precision floating-point support. Note that this information is
3067 stored differently in the opcode table for insns and macros. */
3068 if (mo
->pinfo
== INSN_MACRO
)
3070 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3071 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3075 fp_s
= mo
->pinfo
& FP_S
;
3076 fp_d
= mo
->pinfo
& FP_D
;
3079 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3082 if (fp_s
&& mips_opts
.soft_float
)
3088 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3089 selected ISA and architecture. */
3092 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3094 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
3097 /* Return TRUE if the size of the microMIPS opcode MO matches one
3098 explicitly requested. Always TRUE in the standard MIPS mode. */
3101 is_size_valid (const struct mips_opcode
*mo
)
3103 if (!mips_opts
.micromips
)
3106 if (mips_opts
.insn32
)
3108 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3110 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3113 if (!forced_insn_length
)
3115 if (mo
->pinfo
== INSN_MACRO
)
3117 return forced_insn_length
== micromips_insn_length (mo
);
3120 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3121 of the preceding instruction. Always TRUE in the standard MIPS mode.
3123 We don't accept macros in 16-bit delay slots to avoid a case where
3124 a macro expansion fails because it relies on a preceding 32-bit real
3125 instruction to have matched and does not handle the operands correctly.
3126 The only macros that may expand to 16-bit instructions are JAL that
3127 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3128 and BGT (that likewise cannot be placed in a delay slot) that decay to
3129 a NOP. In all these cases the macros precede any corresponding real
3130 instruction definitions in the opcode table, so they will match in the
3131 second pass where the size of the delay slot is ignored and therefore
3132 produce correct code. */
3135 is_delay_slot_valid (const struct mips_opcode
*mo
)
3137 if (!mips_opts
.micromips
)
3140 if (mo
->pinfo
== INSN_MACRO
)
3141 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3142 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3143 && micromips_insn_length (mo
) != 4)
3145 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3146 && micromips_insn_length (mo
) != 2)
3152 /* For consistency checking, verify that all bits of OPCODE are specified
3153 either by the match/mask part of the instruction definition, or by the
3154 operand list. Also build up a list of operands in OPERANDS.
3156 INSN_BITS says which bits of the instruction are significant.
3157 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3158 provides the mips_operand description of each operand. DECODE_OPERAND
3159 is null for MIPS16 instructions. */
3162 validate_mips_insn (const struct mips_opcode
*opcode
,
3163 unsigned long insn_bits
,
3164 const struct mips_operand
*(*decode_operand
) (const char *),
3165 struct mips_operand_array
*operands
)
3168 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3169 const struct mips_operand
*operand
;
3171 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3172 if ((mask
& opcode
->match
) != opcode
->match
)
3174 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3175 opcode
->name
, opcode
->args
);
3180 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3181 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3182 for (s
= opcode
->args
; *s
; ++s
)
3195 if (!decode_operand
)
3196 operand
= decode_mips16_operand (*s
, FALSE
);
3198 operand
= decode_operand (s
);
3199 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3201 as_bad (_("internal: unknown operand type: %s %s"),
3202 opcode
->name
, opcode
->args
);
3205 gas_assert (opno
< MAX_OPERANDS
);
3206 operands
->operand
[opno
] = operand
;
3207 if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3209 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3210 if (operand
->type
== OP_MDMX_IMM_REG
)
3211 /* Bit 5 is the format selector (OB vs QH). The opcode table
3212 has separate entries for each format. */
3213 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3214 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3215 used_bits
&= ~(mask
& 0x700);
3217 /* Skip prefix characters. */
3218 if (decode_operand
&& (*s
== '+' || *s
== 'm'))
3223 doubled
= used_bits
& mask
& insn_bits
;
3226 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3227 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3231 undefined
= ~used_bits
& insn_bits
;
3232 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3234 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3235 undefined
, opcode
->name
, opcode
->args
);
3238 used_bits
&= ~insn_bits
;
3241 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3242 used_bits
, opcode
->name
, opcode
->args
);
3248 /* The MIPS16 version of validate_mips_insn. */
3251 validate_mips16_insn (const struct mips_opcode
*opcode
,
3252 struct mips_operand_array
*operands
)
3254 if (opcode
->args
[0] == 'a' || opcode
->args
[0] == 'i')
3256 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3257 instruction. Use TMP to describe the full instruction. */
3258 struct mips_opcode tmp
;
3263 return validate_mips_insn (&tmp
, 0xffffffff, 0, operands
);
3265 return validate_mips_insn (opcode
, 0xffff, 0, operands
);
3268 /* The microMIPS version of validate_mips_insn. */
3271 validate_micromips_insn (const struct mips_opcode
*opc
,
3272 struct mips_operand_array
*operands
)
3274 unsigned long insn_bits
;
3275 unsigned long major
;
3276 unsigned int length
;
3278 if (opc
->pinfo
== INSN_MACRO
)
3279 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3282 length
= micromips_insn_length (opc
);
3283 if (length
!= 2 && length
!= 4)
3285 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3286 "%s %s"), length
, opc
->name
, opc
->args
);
3289 major
= opc
->match
>> (10 + 8 * (length
- 2));
3290 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3291 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3293 as_bad (_("Internal error: bad microMIPS opcode "
3294 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3298 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3299 insn_bits
= 1 << 4 * length
;
3300 insn_bits
<<= 4 * length
;
3302 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3306 /* This function is called once, at assembler startup time. It should set up
3307 all the tables, etc. that the MD part of the assembler will need. */
3312 const char *retval
= NULL
;
3316 if (mips_pic
!= NO_PIC
)
3318 if (g_switch_seen
&& g_switch_value
!= 0)
3319 as_bad (_("-G may not be used in position-independent code"));
3323 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
3324 as_warn (_("Could not set architecture and machine"));
3326 op_hash
= hash_new ();
3328 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3329 for (i
= 0; i
< NUMOPCODES
;)
3331 const char *name
= mips_opcodes
[i
].name
;
3333 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3336 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3337 mips_opcodes
[i
].name
, retval
);
3338 /* Probably a memory allocation problem? Give up now. */
3339 as_fatal (_("Broken assembler. No assembly attempted."));
3343 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3344 decode_mips_operand
, &mips_operands
[i
]))
3346 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3348 create_insn (&nop_insn
, mips_opcodes
+ i
);
3349 if (mips_fix_loongson2f_nop
)
3350 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3351 nop_insn
.fixed_p
= 1;
3355 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3358 mips16_op_hash
= hash_new ();
3359 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3360 bfd_mips16_num_opcodes
);
3363 while (i
< bfd_mips16_num_opcodes
)
3365 const char *name
= mips16_opcodes
[i
].name
;
3367 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3369 as_fatal (_("internal: can't hash `%s': %s"),
3370 mips16_opcodes
[i
].name
, retval
);
3373 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3375 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3377 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3378 mips16_nop_insn
.fixed_p
= 1;
3382 while (i
< bfd_mips16_num_opcodes
3383 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3386 micromips_op_hash
= hash_new ();
3387 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3388 bfd_micromips_num_opcodes
);
3391 while (i
< bfd_micromips_num_opcodes
)
3393 const char *name
= micromips_opcodes
[i
].name
;
3395 retval
= hash_insert (micromips_op_hash
, name
,
3396 (void *) µmips_opcodes
[i
]);
3398 as_fatal (_("internal: can't hash `%s': %s"),
3399 micromips_opcodes
[i
].name
, retval
);
3402 struct mips_cl_insn
*micromips_nop_insn
;
3404 if (!validate_micromips_insn (µmips_opcodes
[i
],
3405 µmips_operands
[i
]))
3408 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3410 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3411 micromips_nop_insn
= µmips_nop16_insn
;
3412 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3413 micromips_nop_insn
= µmips_nop32_insn
;
3417 if (micromips_nop_insn
->insn_mo
== NULL
3418 && strcmp (name
, "nop") == 0)
3420 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3421 micromips_nop_insn
->fixed_p
= 1;
3425 while (++i
< bfd_micromips_num_opcodes
3426 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3430 as_fatal (_("Broken assembler. No assembly attempted."));
3432 /* We add all the general register names to the symbol table. This
3433 helps us detect invalid uses of them. */
3434 for (i
= 0; reg_names
[i
].name
; i
++)
3435 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3436 reg_names
[i
].num
, /* & RNUM_MASK, */
3437 &zero_address_frag
));
3439 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3440 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3441 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3442 &zero_address_frag
));
3444 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3445 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3446 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3447 &zero_address_frag
));
3449 for (i
= 0; i
< 32; i
++)
3453 /* R5900 VU0 floating-point register. */
3454 regname
[sizeof (rename
) - 1] = 0;
3455 snprintf (regname
, sizeof (regname
) - 1, "$vf%d", i
);
3456 symbol_table_insert (symbol_new (regname
, reg_section
,
3457 RTYPE_VF
| i
, &zero_address_frag
));
3459 /* R5900 VU0 integer register. */
3460 snprintf (regname
, sizeof (regname
) - 1, "$vi%d", i
);
3461 symbol_table_insert (symbol_new (regname
, reg_section
,
3462 RTYPE_VI
| i
, &zero_address_frag
));
3466 obstack_init (&mips_operand_tokens
);
3468 mips_no_prev_insn ();
3471 mips_cprmask
[0] = 0;
3472 mips_cprmask
[1] = 0;
3473 mips_cprmask
[2] = 0;
3474 mips_cprmask
[3] = 0;
3476 /* set the default alignment for the text section (2**2) */
3477 record_alignment (text_section
, 2);
3479 bfd_set_gp_size (stdoutput
, g_switch_value
);
3481 /* On a native system other than VxWorks, sections must be aligned
3482 to 16 byte boundaries. When configured for an embedded ELF
3483 target, we don't bother. */
3484 if (strncmp (TARGET_OS
, "elf", 3) != 0
3485 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3487 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
3488 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
3489 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
3492 /* Create a .reginfo section for register masks and a .mdebug
3493 section for debugging information. */
3501 subseg
= now_subseg
;
3503 /* The ABI says this section should be loaded so that the
3504 running program can access it. However, we don't load it
3505 if we are configured for an embedded target */
3506 flags
= SEC_READONLY
| SEC_DATA
;
3507 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3508 flags
|= SEC_ALLOC
| SEC_LOAD
;
3510 if (mips_abi
!= N64_ABI
)
3512 sec
= subseg_new (".reginfo", (subsegT
) 0);
3514 bfd_set_section_flags (stdoutput
, sec
, flags
);
3515 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
3517 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3521 /* The 64-bit ABI uses a .MIPS.options section rather than
3522 .reginfo section. */
3523 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3524 bfd_set_section_flags (stdoutput
, sec
, flags
);
3525 bfd_set_section_alignment (stdoutput
, sec
, 3);
3527 /* Set up the option header. */
3529 Elf_Internal_Options opthdr
;
3532 opthdr
.kind
= ODK_REGINFO
;
3533 opthdr
.size
= (sizeof (Elf_External_Options
)
3534 + sizeof (Elf64_External_RegInfo
));
3537 f
= frag_more (sizeof (Elf_External_Options
));
3538 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3539 (Elf_External_Options
*) f
);
3541 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3545 if (ECOFF_DEBUGGING
)
3547 sec
= subseg_new (".mdebug", (subsegT
) 0);
3548 (void) bfd_set_section_flags (stdoutput
, sec
,
3549 SEC_HAS_CONTENTS
| SEC_READONLY
);
3550 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
3552 else if (mips_flag_pdr
)
3554 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3555 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
3556 SEC_READONLY
| SEC_RELOC
3558 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
3561 subseg_set (seg
, subseg
);
3564 if (! ECOFF_DEBUGGING
)
3567 if (mips_fix_vr4120
)
3568 init_vr4120_conflicts ();
3574 mips_emit_delays ();
3575 if (! ECOFF_DEBUGGING
)
3580 md_assemble (char *str
)
3582 struct mips_cl_insn insn
;
3583 bfd_reloc_code_real_type unused_reloc
[3]
3584 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3586 imm_expr
.X_op
= O_absent
;
3587 imm2_expr
.X_op
= O_absent
;
3588 offset_expr
.X_op
= O_absent
;
3589 offset_reloc
[0] = BFD_RELOC_UNUSED
;
3590 offset_reloc
[1] = BFD_RELOC_UNUSED
;
3591 offset_reloc
[2] = BFD_RELOC_UNUSED
;
3593 mips_mark_labels ();
3594 mips_assembling_insn
= TRUE
;
3595 clear_insn_error ();
3597 if (mips_opts
.mips16
)
3598 mips16_ip (str
, &insn
);
3601 mips_ip (str
, &insn
);
3602 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3603 str
, insn
.insn_opcode
));
3607 report_insn_error (str
);
3608 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
3611 if (mips_opts
.mips16
)
3612 mips16_macro (&insn
);
3619 if (offset_expr
.X_op
!= O_absent
)
3620 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3622 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3625 mips_assembling_insn
= FALSE
;
3628 /* Convenience functions for abstracting away the differences between
3629 MIPS16 and non-MIPS16 relocations. */
3631 static inline bfd_boolean
3632 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3636 case BFD_RELOC_MIPS16_JMP
:
3637 case BFD_RELOC_MIPS16_GPREL
:
3638 case BFD_RELOC_MIPS16_GOT16
:
3639 case BFD_RELOC_MIPS16_CALL16
:
3640 case BFD_RELOC_MIPS16_HI16_S
:
3641 case BFD_RELOC_MIPS16_HI16
:
3642 case BFD_RELOC_MIPS16_LO16
:
3650 static inline bfd_boolean
3651 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3655 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3656 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3657 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3658 case BFD_RELOC_MICROMIPS_GPREL16
:
3659 case BFD_RELOC_MICROMIPS_JMP
:
3660 case BFD_RELOC_MICROMIPS_HI16
:
3661 case BFD_RELOC_MICROMIPS_HI16_S
:
3662 case BFD_RELOC_MICROMIPS_LO16
:
3663 case BFD_RELOC_MICROMIPS_LITERAL
:
3664 case BFD_RELOC_MICROMIPS_GOT16
:
3665 case BFD_RELOC_MICROMIPS_CALL16
:
3666 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3667 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3668 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3669 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3670 case BFD_RELOC_MICROMIPS_SUB
:
3671 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3672 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3673 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3674 case BFD_RELOC_MICROMIPS_HIGHEST
:
3675 case BFD_RELOC_MICROMIPS_HIGHER
:
3676 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3677 case BFD_RELOC_MICROMIPS_JALR
:
3685 static inline bfd_boolean
3686 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3688 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3691 static inline bfd_boolean
3692 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3694 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3695 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3698 static inline bfd_boolean
3699 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3701 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3702 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3705 static inline bfd_boolean
3706 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3708 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3709 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3712 static inline bfd_boolean
3713 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3715 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3718 static inline bfd_boolean
3719 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
3721 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
3722 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
3725 /* Return true if RELOC is a PC-relative relocation that does not have
3726 full address range. */
3728 static inline bfd_boolean
3729 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3733 case BFD_RELOC_16_PCREL_S2
:
3734 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3735 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3736 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3739 case BFD_RELOC_32_PCREL
:
3740 return HAVE_64BIT_ADDRESSES
;
3747 /* Return true if the given relocation might need a matching %lo().
3748 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3749 need a matching %lo() when applied to local symbols. */
3751 static inline bfd_boolean
3752 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3754 return (HAVE_IN_PLACE_ADDENDS
3755 && (hi16_reloc_p (reloc
)
3756 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3757 all GOT16 relocations evaluate to "G". */
3758 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3761 /* Return the type of %lo() reloc needed by RELOC, given that
3762 reloc_needs_lo_p. */
3764 static inline bfd_reloc_code_real_type
3765 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3767 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3768 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3772 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3775 static inline bfd_boolean
3776 fixup_has_matching_lo_p (fixS
*fixp
)
3778 return (fixp
->fx_next
!= NULL
3779 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3780 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3781 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3784 /* Move all labels in LABELS to the current insertion point. TEXT_P
3785 says whether the labels refer to text or data. */
3788 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3790 struct insn_label_list
*l
;
3793 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3795 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3796 symbol_set_frag (l
->label
, frag_now
);
3797 val
= (valueT
) frag_now_fix ();
3798 /* MIPS16/microMIPS text labels are stored as odd. */
3799 if (text_p
&& HAVE_CODE_COMPRESSION
)
3801 S_SET_VALUE (l
->label
, val
);
3805 /* Move all labels in insn_labels to the current insertion point
3806 and treat them as text labels. */
3809 mips_move_text_labels (void)
3811 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3815 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3817 bfd_boolean linkonce
= FALSE
;
3818 segT symseg
= S_GET_SEGMENT (sym
);
3820 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3822 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3824 /* The GNU toolchain uses an extension for ELF: a section
3825 beginning with the magic string .gnu.linkonce is a
3826 linkonce section. */
3827 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3828 sizeof ".gnu.linkonce" - 1) == 0)
3834 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3835 linker to handle them specially, such as generating jalx instructions
3836 when needed. We also make them odd for the duration of the assembly,
3837 in order to generate the right sort of code. We will make them even
3838 in the adjust_symtab routine, while leaving them marked. This is
3839 convenient for the debugger and the disassembler. The linker knows
3840 to make them odd again. */
3843 mips_compressed_mark_label (symbolS
*label
)
3845 gas_assert (HAVE_CODE_COMPRESSION
);
3847 if (mips_opts
.mips16
)
3848 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3850 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3851 if ((S_GET_VALUE (label
) & 1) == 0
3852 /* Don't adjust the address if the label is global or weak, or
3853 in a link-once section, since we'll be emitting symbol reloc
3854 references to it which will be patched up by the linker, and
3855 the final value of the symbol may or may not be MIPS16/microMIPS. */
3856 && !S_IS_WEAK (label
)
3857 && !S_IS_EXTERNAL (label
)
3858 && !s_is_linkonce (label
, now_seg
))
3859 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3862 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3865 mips_compressed_mark_labels (void)
3867 struct insn_label_list
*l
;
3869 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3870 mips_compressed_mark_label (l
->label
);
3873 /* End the current frag. Make it a variant frag and record the
3877 relax_close_frag (void)
3879 mips_macro_warning
.first_frag
= frag_now
;
3880 frag_var (rs_machine_dependent
, 0, 0,
3881 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3882 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3884 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3885 mips_relax
.first_fixup
= 0;
3888 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3889 See the comment above RELAX_ENCODE for more details. */
3892 relax_start (symbolS
*symbol
)
3894 gas_assert (mips_relax
.sequence
== 0);
3895 mips_relax
.sequence
= 1;
3896 mips_relax
.symbol
= symbol
;
3899 /* Start generating the second version of a relaxable sequence.
3900 See the comment above RELAX_ENCODE for more details. */
3905 gas_assert (mips_relax
.sequence
== 1);
3906 mips_relax
.sequence
= 2;
3909 /* End the current relaxable sequence. */
3914 gas_assert (mips_relax
.sequence
== 2);
3915 relax_close_frag ();
3916 mips_relax
.sequence
= 0;
3919 /* Return true if IP is a delayed branch or jump. */
3921 static inline bfd_boolean
3922 delayed_branch_p (const struct mips_cl_insn
*ip
)
3924 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3925 | INSN_COND_BRANCH_DELAY
3926 | INSN_COND_BRANCH_LIKELY
)) != 0;
3929 /* Return true if IP is a compact branch or jump. */
3931 static inline bfd_boolean
3932 compact_branch_p (const struct mips_cl_insn
*ip
)
3934 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3935 | INSN2_COND_BRANCH
)) != 0;
3938 /* Return true if IP is an unconditional branch or jump. */
3940 static inline bfd_boolean
3941 uncond_branch_p (const struct mips_cl_insn
*ip
)
3943 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3944 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
3947 /* Return true if IP is a branch-likely instruction. */
3949 static inline bfd_boolean
3950 branch_likely_p (const struct mips_cl_insn
*ip
)
3952 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3955 /* Return the type of nop that should be used to fill the delay slot
3956 of delayed branch IP. */
3958 static struct mips_cl_insn
*
3959 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3961 if (mips_opts
.micromips
3962 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3963 return µmips_nop32_insn
;
3967 /* Return a mask that has bit N set if OPCODE reads the register(s)
3971 insn_read_mask (const struct mips_opcode
*opcode
)
3973 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
3976 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3980 insn_write_mask (const struct mips_opcode
*opcode
)
3982 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
3985 /* Return a mask of the registers specified by operand OPERAND of INSN.
3986 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3990 operand_reg_mask (const struct mips_cl_insn
*insn
,
3991 const struct mips_operand
*operand
,
3992 unsigned int type_mask
)
3994 unsigned int uval
, vsel
;
3996 switch (operand
->type
)
4003 case OP_ADDIUSP_INT
:
4004 case OP_ENTRY_EXIT_LIST
:
4005 case OP_REPEAT_DEST_REG
:
4006 case OP_REPEAT_PREV_REG
:
4009 case OP_VU0_MATCH_SUFFIX
:
4013 case OP_OPTIONAL_REG
:
4015 const struct mips_reg_operand
*reg_op
;
4017 reg_op
= (const struct mips_reg_operand
*) operand
;
4018 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4020 uval
= insn_extract_operand (insn
, operand
);
4021 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4026 const struct mips_reg_pair_operand
*pair_op
;
4028 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4029 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4031 uval
= insn_extract_operand (insn
, operand
);
4032 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4035 case OP_CLO_CLZ_DEST
:
4036 if (!(type_mask
& (1 << OP_REG_GP
)))
4038 uval
= insn_extract_operand (insn
, operand
);
4039 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4041 case OP_LWM_SWM_LIST
:
4044 case OP_SAVE_RESTORE_LIST
:
4047 case OP_MDMX_IMM_REG
:
4048 if (!(type_mask
& (1 << OP_REG_VEC
)))
4050 uval
= insn_extract_operand (insn
, operand
);
4052 if ((vsel
& 0x18) == 0x18)
4054 return 1 << (uval
& 31);
4059 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4060 where bit N of OPNO_MASK is set if operand N should be included.
4061 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4065 insn_reg_mask (const struct mips_cl_insn
*insn
,
4066 unsigned int type_mask
, unsigned int opno_mask
)
4068 unsigned int opno
, reg_mask
;
4072 while (opno_mask
!= 0)
4075 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4082 /* Return the mask of core registers that IP reads. */
4085 gpr_read_mask (const struct mips_cl_insn
*ip
)
4087 unsigned long pinfo
, pinfo2
;
4090 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4091 pinfo
= ip
->insn_mo
->pinfo
;
4092 pinfo2
= ip
->insn_mo
->pinfo2
;
4093 if (pinfo
& INSN_UDI
)
4095 /* UDI instructions have traditionally been assumed to read RS
4097 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4098 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4100 if (pinfo
& INSN_READ_GPR_24
)
4102 if (pinfo2
& INSN2_READ_GPR_16
)
4104 if (pinfo2
& INSN2_READ_SP
)
4106 if (pinfo2
& INSN2_READ_GPR_31
)
4108 /* Don't include register 0. */
4112 /* Return the mask of core registers that IP writes. */
4115 gpr_write_mask (const struct mips_cl_insn
*ip
)
4117 unsigned long pinfo
, pinfo2
;
4120 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4121 pinfo
= ip
->insn_mo
->pinfo
;
4122 pinfo2
= ip
->insn_mo
->pinfo2
;
4123 if (pinfo
& INSN_WRITE_GPR_24
)
4125 if (pinfo
& INSN_WRITE_GPR_31
)
4127 if (pinfo
& INSN_UDI
)
4128 /* UDI instructions have traditionally been assumed to write to RD. */
4129 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4130 if (pinfo2
& INSN2_WRITE_SP
)
4132 /* Don't include register 0. */
4136 /* Return the mask of floating-point registers that IP reads. */
4139 fpr_read_mask (const struct mips_cl_insn
*ip
)
4141 unsigned long pinfo
;
4144 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4145 insn_read_mask (ip
->insn_mo
));
4146 pinfo
= ip
->insn_mo
->pinfo
;
4147 /* Conservatively treat all operands to an FP_D instruction are doubles.
4148 (This is overly pessimistic for things like cvt.d.s.) */
4149 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4154 /* Return the mask of floating-point registers that IP writes. */
4157 fpr_write_mask (const struct mips_cl_insn
*ip
)
4159 unsigned long pinfo
;
4162 mask
= insn_reg_mask (ip
, (1 << OP_REG_FP
) | (1 << OP_REG_VEC
),
4163 insn_write_mask (ip
->insn_mo
));
4164 pinfo
= ip
->insn_mo
->pinfo
;
4165 /* Conservatively treat all operands to an FP_D instruction are doubles.
4166 (This is overly pessimistic for things like cvt.s.d.) */
4167 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
4172 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4173 Check whether that is allowed. */
4176 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4178 const char *s
= insn
->name
;
4180 if (insn
->pinfo
== INSN_MACRO
)
4181 /* Let a macro pass, we'll catch it later when it is expanded. */
4184 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || mips_opts
.arch
== CPU_R5900
)
4186 /* Allow odd registers for single-precision ops. */
4187 switch (insn
->pinfo
& (FP_S
| FP_D
))
4198 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4199 s
= strchr (insn
->name
, '.');
4200 if (s
!= NULL
&& opnum
== 2)
4201 s
= strchr (s
+ 1, '.');
4202 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
4205 /* Single-precision coprocessor loads and moves are OK too. */
4206 if ((insn
->pinfo
& FP_S
)
4207 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
4208 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
4214 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4215 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4216 this operand is normally printed in hex or decimal. */
4219 report_bad_range (struct mips_cl_insn
*insn
, int argnum
,
4220 offsetT val
, int min_val
, int max_val
,
4221 bfd_boolean print_hex
)
4223 if (print_hex
&& val
>= 0)
4224 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4226 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4228 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4230 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4232 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4234 argnum
, insn
->insn_mo
->name
, min_val
, max_val
, (unsigned long) val
);
4237 /* Report an invalid combination of position and size operands for a bitfield
4238 operation. POS and SIZE are the values that were given. */
4241 report_bad_field (offsetT pos
, offsetT size
)
4243 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4244 (unsigned long) pos
, (unsigned long) size
);
4247 /* Information about an instruction argument that we're trying to match. */
4248 struct mips_arg_info
4250 /* The instruction so far. */
4251 struct mips_cl_insn
*insn
;
4253 /* The first unconsumed operand token. */
4254 struct mips_operand_token
*token
;
4256 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4259 /* The 1-based argument number, for error reporting. This does not
4260 count elided optional registers, etc.. */
4263 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4264 unsigned int last_regno
;
4266 /* If the first operand was an OP_REG, this is the register that it
4267 specified, otherwise it is ILLEGAL_REG. */
4268 unsigned int dest_regno
;
4270 /* The value of the last OP_INT operand. Only used for OP_MSB,
4271 where it gives the lsb position. */
4272 unsigned int last_op_int
;
4274 /* If true, match routines should assume that no later instruction
4275 alternative matches and should therefore be as accomodating as
4276 possible. Match routines should not report errors if something
4277 is only invalid for !LAX_MATCH. */
4278 bfd_boolean lax_match
;
4280 /* True if a reference to the current AT register was seen. */
4281 bfd_boolean seen_at
;
4284 /* Record that the argument is out of range. */
4287 match_out_of_range (struct mips_arg_info
*arg
)
4289 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4292 /* Record that the argument isn't constant but needs to be. */
4295 match_not_constant (struct mips_arg_info
*arg
)
4297 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4301 /* Try to match an OT_CHAR token for character CH. Consume the token
4302 and return true on success, otherwise return false. */
4305 match_char (struct mips_arg_info
*arg
, char ch
)
4307 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4317 /* Try to get an expression from the next tokens in ARG. Consume the
4318 tokens and return true on success, storing the expression value in
4319 VALUE and relocation types in R. */
4322 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4323 bfd_reloc_code_real_type
*r
)
4325 /* If the next token is a '(' that was parsed as being part of a base
4326 expression, assume we have an elided offset. The later match will fail
4327 if this turns out to be wrong. */
4328 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4330 value
->X_op
= O_constant
;
4331 value
->X_add_number
= 0;
4332 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4336 /* Reject register-based expressions such as "0+$2" and "(($2))".
4337 For plain registers the default error seems more appropriate. */
4338 if (arg
->token
->type
== OT_INTEGER
4339 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4341 set_insn_error (arg
->argnum
, _("register value used as expression"));
4345 if (arg
->token
->type
== OT_INTEGER
)
4347 *value
= arg
->token
->u
.integer
.value
;
4348 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4354 (arg
->argnum
, _("operand %d must be an immediate expression"),
4359 /* Try to get a constant expression from the next tokens in ARG. Consume
4360 the tokens and return return true on success, storing the constant value
4361 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4365 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4368 bfd_reloc_code_real_type r
[3];
4370 if (!match_expression (arg
, &ex
, r
))
4373 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
4374 *value
= ex
.X_add_number
;
4377 match_not_constant (arg
);
4383 /* Return the RTYPE_* flags for a register operand of type TYPE that
4384 appears in instruction OPCODE. */
4387 convert_reg_type (const struct mips_opcode
*opcode
,
4388 enum mips_reg_operand_type type
)
4393 return RTYPE_NUM
| RTYPE_GP
;
4396 /* Allow vector register names for MDMX if the instruction is a 64-bit
4397 FPR load, store or move (including moves to and from GPRs). */
4398 if ((mips_opts
.ase
& ASE_MDMX
)
4399 && (opcode
->pinfo
& FP_D
)
4400 && (opcode
->pinfo
& (INSN_COPROC_MOVE_DELAY
4401 | INSN_COPROC_MEMORY_DELAY
4402 | INSN_LOAD_COPROC_DELAY
4403 | INSN_LOAD_MEMORY_DELAY
4404 | INSN_STORE_MEMORY
)))
4405 return RTYPE_FPU
| RTYPE_VEC
;
4409 if (opcode
->pinfo
& (FP_D
| FP_S
))
4410 return RTYPE_CCC
| RTYPE_FCC
;
4414 if (opcode
->membership
& INSN_5400
)
4416 return RTYPE_FPU
| RTYPE_VEC
;
4422 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
4423 return RTYPE_NUM
| RTYPE_CP0
;
4430 return RTYPE_NUM
| RTYPE_VI
;
4433 return RTYPE_NUM
| RTYPE_VF
;
4435 case OP_REG_R5900_I
:
4436 return RTYPE_R5900_I
;
4438 case OP_REG_R5900_Q
:
4439 return RTYPE_R5900_Q
;
4441 case OP_REG_R5900_R
:
4442 return RTYPE_R5900_R
;
4444 case OP_REG_R5900_ACC
:
4445 return RTYPE_R5900_ACC
;
4450 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4453 check_regno (struct mips_arg_info
*arg
,
4454 enum mips_reg_operand_type type
, unsigned int regno
)
4456 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
4457 arg
->seen_at
= TRUE
;
4459 if (type
== OP_REG_FP
4462 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
4463 as_warn (_("Float register should be even, was %d"), regno
);
4465 if (type
== OP_REG_CCC
)
4470 name
= arg
->insn
->insn_mo
->name
;
4471 length
= strlen (name
);
4472 if ((regno
& 1) != 0
4473 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
4474 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
4475 as_warn (_("Condition code register should be even for %s, was %d"),
4478 if ((regno
& 3) != 0
4479 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
4480 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4485 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4486 a register of type TYPE. Return true on success, storing the register
4487 number in *REGNO and warning about any dubious uses. */
4490 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4491 unsigned int symval
, unsigned int *regno
)
4493 if (type
== OP_REG_VEC
)
4494 symval
= mips_prefer_vec_regno (symval
);
4495 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
4498 *regno
= symval
& RNUM_MASK
;
4499 check_regno (arg
, type
, *regno
);
4503 /* Try to interpret the next token in ARG as a register of type TYPE.
4504 Consume the token and return true on success, storing the register
4505 number in *REGNO. Return false on failure. */
4508 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4509 unsigned int *regno
)
4511 if (arg
->token
->type
== OT_REG
4512 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
4520 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4521 Consume the token and return true on success, storing the register numbers
4522 in *REGNO1 and *REGNO2. Return false on failure. */
4525 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
4526 unsigned int *regno1
, unsigned int *regno2
)
4528 if (match_reg (arg
, type
, regno1
))
4533 if (arg
->token
->type
== OT_REG_RANGE
4534 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
4535 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
4536 && *regno1
<= *regno2
)
4544 /* OP_INT matcher. */
4547 match_int_operand (struct mips_arg_info
*arg
,
4548 const struct mips_operand
*operand_base
)
4550 const struct mips_int_operand
*operand
;
4552 int min_val
, max_val
, factor
;
4555 operand
= (const struct mips_int_operand
*) operand_base
;
4556 factor
= 1 << operand
->shift
;
4557 min_val
= mips_int_operand_min (operand
);
4558 max_val
= mips_int_operand_max (operand
);
4560 if (operand_base
->lsb
== 0
4561 && operand_base
->size
== 16
4562 && operand
->shift
== 0
4563 && operand
->bias
== 0
4564 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
4566 /* The operand can be relocated. */
4567 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
4570 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
4571 /* Relocation operators were used. Accept the arguent and
4572 leave the relocation value in offset_expr and offset_relocs
4573 for the caller to process. */
4576 if (offset_expr
.X_op
!= O_constant
)
4578 /* Accept non-constant operands if no later alternative matches,
4579 leaving it for the caller to process. */
4580 if (!arg
->lax_match
)
4582 offset_reloc
[0] = BFD_RELOC_LO16
;
4586 /* Clear the global state; we're going to install the operand
4588 sval
= offset_expr
.X_add_number
;
4589 offset_expr
.X_op
= O_absent
;
4591 /* For compatibility with older assemblers, we accept
4592 0x8000-0xffff as signed 16-bit numbers when only
4593 signed numbers are allowed. */
4596 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
4597 if (!arg
->lax_match
&& sval
<= max_val
)
4603 if (!match_const_int (arg
, &sval
))
4607 arg
->last_op_int
= sval
;
4609 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
4611 match_out_of_range (arg
);
4615 uval
= (unsigned int) sval
>> operand
->shift
;
4616 uval
-= operand
->bias
;
4618 /* Handle -mfix-cn63xxp1. */
4620 && mips_fix_cn63xxp1
4621 && !mips_opts
.micromips
4622 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
4637 /* The rest must be changed to 28. */
4642 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4646 /* OP_MAPPED_INT matcher. */
4649 match_mapped_int_operand (struct mips_arg_info
*arg
,
4650 const struct mips_operand
*operand_base
)
4652 const struct mips_mapped_int_operand
*operand
;
4653 unsigned int uval
, num_vals
;
4656 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
4657 if (!match_const_int (arg
, &sval
))
4660 num_vals
= 1 << operand_base
->size
;
4661 for (uval
= 0; uval
< num_vals
; uval
++)
4662 if (operand
->int_map
[uval
] == sval
)
4664 if (uval
== num_vals
)
4666 match_out_of_range (arg
);
4670 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4674 /* OP_MSB matcher. */
4677 match_msb_operand (struct mips_arg_info
*arg
,
4678 const struct mips_operand
*operand_base
)
4680 const struct mips_msb_operand
*operand
;
4681 int min_val
, max_val
, max_high
;
4682 offsetT size
, sval
, high
;
4684 operand
= (const struct mips_msb_operand
*) operand_base
;
4685 min_val
= operand
->bias
;
4686 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
4687 max_high
= operand
->opsize
;
4689 if (!match_const_int (arg
, &size
))
4692 high
= size
+ arg
->last_op_int
;
4693 sval
= operand
->add_lsb
? high
: size
;
4695 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
4697 match_out_of_range (arg
);
4700 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
4704 /* OP_REG matcher. */
4707 match_reg_operand (struct mips_arg_info
*arg
,
4708 const struct mips_operand
*operand_base
)
4710 const struct mips_reg_operand
*operand
;
4711 unsigned int regno
, uval
, num_vals
;
4713 operand
= (const struct mips_reg_operand
*) operand_base
;
4714 if (!match_reg (arg
, operand
->reg_type
, ®no
))
4717 if (operand
->reg_map
)
4719 num_vals
= 1 << operand
->root
.size
;
4720 for (uval
= 0; uval
< num_vals
; uval
++)
4721 if (operand
->reg_map
[uval
] == regno
)
4723 if (num_vals
== uval
)
4729 arg
->last_regno
= regno
;
4730 if (arg
->opnum
== 1)
4731 arg
->dest_regno
= regno
;
4732 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4736 /* OP_REG_PAIR matcher. */
4739 match_reg_pair_operand (struct mips_arg_info
*arg
,
4740 const struct mips_operand
*operand_base
)
4742 const struct mips_reg_pair_operand
*operand
;
4743 unsigned int regno1
, regno2
, uval
, num_vals
;
4745 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
4746 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
4747 || !match_char (arg
, ',')
4748 || !match_reg (arg
, operand
->reg_type
, ®no2
))
4751 num_vals
= 1 << operand_base
->size
;
4752 for (uval
= 0; uval
< num_vals
; uval
++)
4753 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
4755 if (uval
== num_vals
)
4758 insn_insert_operand (arg
->insn
, operand_base
, uval
);
4762 /* OP_PCREL matcher. The caller chooses the relocation type. */
4765 match_pcrel_operand (struct mips_arg_info
*arg
)
4767 bfd_reloc_code_real_type r
[3];
4769 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
4772 /* OP_PERF_REG matcher. */
4775 match_perf_reg_operand (struct mips_arg_info
*arg
,
4776 const struct mips_operand
*operand
)
4780 if (!match_const_int (arg
, &sval
))
4785 || (mips_opts
.arch
== CPU_R5900
4786 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
4787 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
4789 set_insn_error (arg
->argnum
, _("invalid performance register"));
4793 insn_insert_operand (arg
->insn
, operand
, sval
);
4797 /* OP_ADDIUSP matcher. */
4800 match_addiusp_operand (struct mips_arg_info
*arg
,
4801 const struct mips_operand
*operand
)
4806 if (!match_const_int (arg
, &sval
))
4811 match_out_of_range (arg
);
4816 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
4818 match_out_of_range (arg
);
4822 uval
= (unsigned int) sval
;
4823 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
4824 insn_insert_operand (arg
->insn
, operand
, uval
);
4828 /* OP_CLO_CLZ_DEST matcher. */
4831 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
4832 const struct mips_operand
*operand
)
4836 if (!match_reg (arg
, OP_REG_GP
, ®no
))
4839 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
4843 /* OP_LWM_SWM_LIST matcher. */
4846 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
4847 const struct mips_operand
*operand
)
4849 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
4850 struct mips_arg_info reset
;
4853 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4857 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
4862 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
4865 while (match_char (arg
, ',')
4866 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
4869 if (operand
->size
== 2)
4871 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4877 and any permutations of these. */
4878 if ((reglist
& 0xfff1ffff) != 0x80010000)
4881 sregs
= (reglist
>> 17) & 7;
4886 /* The list must include at least one of ra and s0-sN,
4887 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4888 which are $23 and $30 respectively.) E.g.:
4896 and any permutations of these. */
4897 if ((reglist
& 0x3f00ffff) != 0)
4900 ra
= (reglist
>> 27) & 0x10;
4901 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
4904 if ((sregs
& -sregs
) != sregs
)
4907 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
4911 /* OP_ENTRY_EXIT_LIST matcher. */
4914 match_entry_exit_operand (struct mips_arg_info
*arg
,
4915 const struct mips_operand
*operand
)
4918 bfd_boolean is_exit
;
4920 /* The format is the same for both ENTRY and EXIT, but the constraints
4922 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
4923 mask
= (is_exit
? 7 << 3 : 0);
4926 unsigned int regno1
, regno2
;
4927 bfd_boolean is_freg
;
4929 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4931 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
4936 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
4939 mask
|= (5 + regno2
) << 3;
4941 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
4942 mask
|= (regno2
- 3) << 3;
4943 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
4944 mask
|= (regno2
- 15) << 1;
4945 else if (regno1
== RA
&& regno2
== RA
)
4950 while (match_char (arg
, ','));
4952 insn_insert_operand (arg
->insn
, operand
, mask
);
4956 /* OP_SAVE_RESTORE_LIST matcher. */
4959 match_save_restore_list_operand (struct mips_arg_info
*arg
)
4961 unsigned int opcode
, args
, statics
, sregs
;
4962 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
4965 opcode
= arg
->insn
->insn_opcode
;
4967 num_frame_sizes
= 0;
4973 unsigned int regno1
, regno2
;
4975 if (arg
->token
->type
== OT_INTEGER
)
4977 /* Handle the frame size. */
4978 if (!match_const_int (arg
, &frame_size
))
4980 num_frame_sizes
+= 1;
4984 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
4987 while (regno1
<= regno2
)
4989 if (regno1
>= 4 && regno1
<= 7)
4991 if (num_frame_sizes
== 0)
4993 args
|= 1 << (regno1
- 4);
4995 /* statics $a0-$a3 */
4996 statics
|= 1 << (regno1
- 4);
4998 else if (regno1
>= 16 && regno1
<= 23)
5000 sregs
|= 1 << (regno1
- 16);
5001 else if (regno1
== 30)
5004 else if (regno1
== 31)
5005 /* Add $ra to insn. */
5015 while (match_char (arg
, ','));
5017 /* Encode args/statics combination. */
5020 else if (args
== 0xf)
5021 /* All $a0-$a3 are args. */
5022 opcode
|= MIPS16_ALL_ARGS
<< 16;
5023 else if (statics
== 0xf)
5024 /* All $a0-$a3 are statics. */
5025 opcode
|= MIPS16_ALL_STATICS
<< 16;
5028 /* Count arg registers. */
5038 /* Count static registers. */
5040 while (statics
& 0x8)
5042 statics
= (statics
<< 1) & 0xf;
5048 /* Encode args/statics. */
5049 opcode
|= ((num_args
<< 2) | num_statics
) << 16;
5052 /* Encode $s0/$s1. */
5053 if (sregs
& (1 << 0)) /* $s0 */
5055 if (sregs
& (1 << 1)) /* $s1 */
5059 /* Encode $s2-$s8. */
5068 opcode
|= num_sregs
<< 24;
5070 /* Encode frame size. */
5071 if (num_frame_sizes
== 0)
5073 set_insn_error (arg
->argnum
, _("missing frame size"));
5076 if (num_frame_sizes
> 1)
5078 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5081 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5083 set_insn_error (arg
->argnum
, _("invalid frame size"));
5086 if (frame_size
!= 128 || (opcode
>> 16) != 0)
5089 opcode
|= (((frame_size
& 0xf0) << 16)
5090 | (frame_size
& 0x0f));
5093 /* Finally build the instruction. */
5094 if ((opcode
>> 16) != 0 || frame_size
== 0)
5095 opcode
|= MIPS16_EXTEND
;
5096 arg
->insn
->insn_opcode
= opcode
;
5100 /* OP_MDMX_IMM_REG matcher. */
5103 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5104 const struct mips_operand
*operand
)
5106 unsigned int regno
, uval
;
5108 const struct mips_opcode
*opcode
;
5110 /* The mips_opcode records whether this is an octobyte or quadhalf
5111 instruction. Start out with that bit in place. */
5112 opcode
= arg
->insn
->insn_mo
;
5113 uval
= mips_extract_operand (operand
, opcode
->match
);
5114 is_qh
= (uval
!= 0);
5116 if (arg
->token
->type
== OT_REG
|| arg
->token
->type
== OT_REG_ELEMENT
)
5118 if ((opcode
->membership
& INSN_5400
)
5119 && strcmp (opcode
->name
, "rzu.ob") == 0)
5121 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5126 /* Check whether this is a vector register or a broadcast of
5127 a single element. */
5128 if (arg
->token
->type
== OT_REG_ELEMENT
)
5130 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.reg_element
.regno
,
5133 if (arg
->token
->u
.reg_element
.index
> (is_qh
? 3 : 7))
5135 set_insn_error (arg
->argnum
, _("invalid element selector"));
5139 uval
|= arg
->token
->u
.reg_element
.index
<< (is_qh
? 2 : 1) << 5;
5143 /* A full vector. */
5144 if ((opcode
->membership
& INSN_5400
)
5145 && (strcmp (opcode
->name
, "sll.ob") == 0
5146 || strcmp (opcode
->name
, "srl.ob") == 0))
5148 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5153 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5156 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5158 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5167 if (!match_const_int (arg
, &sval
))
5169 if (sval
< 0 || sval
> 31)
5171 match_out_of_range (arg
);
5174 uval
|= (sval
& 31);
5176 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5178 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5180 insn_insert_operand (arg
->insn
, operand
, uval
);
5184 /* OP_PC matcher. */
5187 match_pc_operand (struct mips_arg_info
*arg
)
5189 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5197 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5198 register that we need to match. */
5201 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
5205 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
5208 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5209 the length of the value in bytes (4 for float, 8 for double) and
5210 USING_GPRS says whether the destination is a GPR rather than an FPR.
5212 Return the constant in IMM and OFFSET as follows:
5214 - If the constant should be loaded via memory, set IMM to O_absent and
5215 OFFSET to the memory address.
5217 - Otherwise, if the constant should be loaded into two 32-bit registers,
5218 set IMM to the O_constant to load into the high register and OFFSET
5219 to the corresponding value for the low register.
5221 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5223 These constants only appear as the last operand in an instruction,
5224 and every instruction that accepts them in any variant accepts them
5225 in all variants. This means we don't have to worry about backing out
5226 any changes if the instruction does not match. We just match
5227 unconditionally and report an error if the constant is invalid. */
5230 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
5231 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
5236 const char *newname
;
5237 unsigned char *data
;
5239 /* Where the constant is placed is based on how the MIPS assembler
5242 length == 4 && using_gprs -- immediate value only
5243 length == 8 && using_gprs -- .rdata or immediate value
5244 length == 4 && !using_gprs -- .lit4 or immediate value
5245 length == 8 && !using_gprs -- .lit8 or immediate value
5247 The .lit4 and .lit8 sections are only used if permitted by the
5249 if (arg
->token
->type
!= OT_FLOAT
)
5251 set_insn_error (arg
->argnum
, _("floating-point expression required"));
5255 gas_assert (arg
->token
->u
.flt
.length
== length
);
5256 data
= arg
->token
->u
.flt
.data
;
5259 /* Handle 32-bit constants for which an immediate value is best. */
5262 || g_switch_value
< 4
5263 || (data
[0] == 0 && data
[1] == 0)
5264 || (data
[2] == 0 && data
[3] == 0)))
5266 imm
->X_op
= O_constant
;
5267 if (!target_big_endian
)
5268 imm
->X_add_number
= bfd_getl32 (data
);
5270 imm
->X_add_number
= bfd_getb32 (data
);
5271 offset
->X_op
= O_absent
;
5275 /* Handle 64-bit constants for which an immediate value is best. */
5277 && !mips_disable_float_construction
5278 /* Constants can only be constructed in GPRs and copied
5279 to FPRs if the GPRs are at least as wide as the FPRs.
5280 Force the constant into memory if we are using 64-bit FPRs
5281 but the GPRs are only 32 bits wide. */
5282 /* ??? No longer true with the addition of MTHC1, but this
5283 is legacy code... */
5284 && (using_gprs
|| !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
5285 && ((data
[0] == 0 && data
[1] == 0)
5286 || (data
[2] == 0 && data
[3] == 0))
5287 && ((data
[4] == 0 && data
[5] == 0)
5288 || (data
[6] == 0 && data
[7] == 0)))
5290 /* The value is simple enough to load with a couple of instructions.
5291 If using 32-bit registers, set IMM to the high order 32 bits and
5292 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5294 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
5296 imm
->X_op
= O_constant
;
5297 offset
->X_op
= O_constant
;
5298 if (!target_big_endian
)
5300 imm
->X_add_number
= bfd_getl32 (data
+ 4);
5301 offset
->X_add_number
= bfd_getl32 (data
);
5305 imm
->X_add_number
= bfd_getb32 (data
);
5306 offset
->X_add_number
= bfd_getb32 (data
+ 4);
5308 if (offset
->X_add_number
== 0)
5309 offset
->X_op
= O_absent
;
5313 imm
->X_op
= O_constant
;
5314 if (!target_big_endian
)
5315 imm
->X_add_number
= bfd_getl64 (data
);
5317 imm
->X_add_number
= bfd_getb64 (data
);
5318 offset
->X_op
= O_absent
;
5323 /* Switch to the right section. */
5325 subseg
= now_subseg
;
5328 gas_assert (!using_gprs
&& g_switch_value
>= 4);
5333 if (using_gprs
|| g_switch_value
< 8)
5334 newname
= RDATA_SECTION_NAME
;
5339 new_seg
= subseg_new (newname
, (subsegT
) 0);
5340 bfd_set_section_flags (stdoutput
, new_seg
,
5341 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
5342 frag_align (length
== 4 ? 2 : 3, 0, 0);
5343 if (strncmp (TARGET_OS
, "elf", 3) != 0)
5344 record_alignment (new_seg
, 4);
5346 record_alignment (new_seg
, length
== 4 ? 2 : 3);
5348 as_bad (_("Can't use floating point insn in this section"));
5350 /* Set the argument to the current address in the section. */
5351 imm
->X_op
= O_absent
;
5352 offset
->X_op
= O_symbol
;
5353 offset
->X_add_symbol
= symbol_temp_new_now ();
5354 offset
->X_add_number
= 0;
5356 /* Put the floating point number into the section. */
5357 p
= frag_more (length
);
5358 memcpy (p
, data
, length
);
5360 /* Switch back to the original section. */
5361 subseg_set (seg
, subseg
);
5365 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5369 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
5370 const struct mips_operand
*operand
,
5371 bfd_boolean match_p
)
5375 /* The operand can be an XYZW mask or a single 2-bit channel index
5376 (with X being 0). */
5377 gas_assert (operand
->size
== 2 || operand
->size
== 4);
5379 /* The suffix can be omitted when it is already part of the opcode. */
5380 if (arg
->token
->type
!= OT_CHANNELS
)
5383 uval
= arg
->token
->u
.channels
;
5384 if (operand
->size
== 2)
5386 /* Check that a single bit is set and convert it into a 2-bit index. */
5387 if ((uval
& -uval
) != uval
)
5389 uval
= 4 - ffs (uval
);
5392 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
5397 insn_insert_operand (arg
->insn
, operand
, uval
);
5401 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5402 of the argument text if the match is successful, otherwise return null. */
5405 match_operand (struct mips_arg_info
*arg
,
5406 const struct mips_operand
*operand
)
5408 switch (operand
->type
)
5411 return match_int_operand (arg
, operand
);
5414 return match_mapped_int_operand (arg
, operand
);
5417 return match_msb_operand (arg
, operand
);
5420 case OP_OPTIONAL_REG
:
5421 return match_reg_operand (arg
, operand
);
5424 return match_reg_pair_operand (arg
, operand
);
5427 return match_pcrel_operand (arg
);
5430 return match_perf_reg_operand (arg
, operand
);
5432 case OP_ADDIUSP_INT
:
5433 return match_addiusp_operand (arg
, operand
);
5435 case OP_CLO_CLZ_DEST
:
5436 return match_clo_clz_dest_operand (arg
, operand
);
5438 case OP_LWM_SWM_LIST
:
5439 return match_lwm_swm_list_operand (arg
, operand
);
5441 case OP_ENTRY_EXIT_LIST
:
5442 return match_entry_exit_operand (arg
, operand
);
5444 case OP_SAVE_RESTORE_LIST
:
5445 return match_save_restore_list_operand (arg
);
5447 case OP_MDMX_IMM_REG
:
5448 return match_mdmx_imm_reg_operand (arg
, operand
);
5450 case OP_REPEAT_DEST_REG
:
5451 return match_tied_reg_operand (arg
, arg
->dest_regno
);
5453 case OP_REPEAT_PREV_REG
:
5454 return match_tied_reg_operand (arg
, arg
->last_regno
);
5457 return match_pc_operand (arg
);
5460 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
5462 case OP_VU0_MATCH_SUFFIX
:
5463 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
5468 /* ARG is the state after successfully matching an instruction.
5469 Issue any queued-up warnings. */
5472 check_completed_insn (struct mips_arg_info
*arg
)
5477 as_warn (_("Used $at without \".set noat\""));
5479 as_warn (_("Used $%u with \".set at=$%u\""), AT
, AT
);
5483 /* Return true if modifying general-purpose register REG needs a delay. */
5486 reg_needs_delay (unsigned int reg
)
5488 unsigned long prev_pinfo
;
5490 prev_pinfo
= history
[0].insn_mo
->pinfo
;
5491 if (!mips_opts
.noreorder
5492 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
) && !gpr_interlocks
)
5493 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
) && !cop_interlocks
))
5494 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
5500 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5501 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5502 by VR4120 errata. */
5505 classify_vr4120_insn (const char *name
)
5507 if (strncmp (name
, "macc", 4) == 0)
5508 return FIX_VR4120_MACC
;
5509 if (strncmp (name
, "dmacc", 5) == 0)
5510 return FIX_VR4120_DMACC
;
5511 if (strncmp (name
, "mult", 4) == 0)
5512 return FIX_VR4120_MULT
;
5513 if (strncmp (name
, "dmult", 5) == 0)
5514 return FIX_VR4120_DMULT
;
5515 if (strstr (name
, "div"))
5516 return FIX_VR4120_DIV
;
5517 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
5518 return FIX_VR4120_MTHILO
;
5519 return NUM_FIX_VR4120_CLASSES
;
5522 #define INSN_ERET 0x42000018
5523 #define INSN_DERET 0x4200001f
5525 /* Return the number of instructions that must separate INSN1 and INSN2,
5526 where INSN1 is the earlier instruction. Return the worst-case value
5527 for any INSN2 if INSN2 is null. */
5530 insns_between (const struct mips_cl_insn
*insn1
,
5531 const struct mips_cl_insn
*insn2
)
5533 unsigned long pinfo1
, pinfo2
;
5536 /* If INFO2 is null, pessimistically assume that all flags are set for
5537 the second instruction. */
5538 pinfo1
= insn1
->insn_mo
->pinfo
;
5539 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
5541 /* For most targets, write-after-read dependencies on the HI and LO
5542 registers must be separated by at least two instructions. */
5543 if (!hilo_interlocks
)
5545 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
5547 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
5551 /* If we're working around r7000 errata, there must be two instructions
5552 between an mfhi or mflo and any instruction that uses the result. */
5553 if (mips_7000_hilo_fix
5554 && !mips_opts
.micromips
5555 && MF_HILO_INSN (pinfo1
)
5556 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
5559 /* If we're working around 24K errata, one instruction is required
5560 if an ERET or DERET is followed by a branch instruction. */
5561 if (mips_fix_24k
&& !mips_opts
.micromips
)
5563 if (insn1
->insn_opcode
== INSN_ERET
5564 || insn1
->insn_opcode
== INSN_DERET
)
5567 || insn2
->insn_opcode
== INSN_ERET
5568 || insn2
->insn_opcode
== INSN_DERET
5569 || delayed_branch_p (insn2
))
5574 /* If working around VR4120 errata, check for combinations that need
5575 a single intervening instruction. */
5576 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
5578 unsigned int class1
, class2
;
5580 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
5581 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
5585 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
5586 if (vr4120_conflicts
[class1
] & (1 << class2
))
5591 if (!HAVE_CODE_COMPRESSION
)
5593 /* Check for GPR or coprocessor load delays. All such delays
5594 are on the RT register. */
5595 /* Itbl support may require additional care here. */
5596 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
5597 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
5599 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
5603 /* Check for generic coprocessor hazards.
5605 This case is not handled very well. There is no special
5606 knowledge of CP0 handling, and the coprocessors other than
5607 the floating point unit are not distinguished at all. */
5608 /* Itbl support may require additional care here. FIXME!
5609 Need to modify this to include knowledge about
5610 user specified delays! */
5611 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
5612 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
5614 /* Handle cases where INSN1 writes to a known general coprocessor
5615 register. There must be a one instruction delay before INSN2
5616 if INSN2 reads that register, otherwise no delay is needed. */
5617 mask
= fpr_write_mask (insn1
);
5620 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
5625 /* Read-after-write dependencies on the control registers
5626 require a two-instruction gap. */
5627 if ((pinfo1
& INSN_WRITE_COND_CODE
)
5628 && (pinfo2
& INSN_READ_COND_CODE
))
5631 /* We don't know exactly what INSN1 does. If INSN2 is
5632 also a coprocessor instruction, assume there must be
5633 a one instruction gap. */
5634 if (pinfo2
& INSN_COP
)
5639 /* Check for read-after-write dependencies on the coprocessor
5640 control registers in cases where INSN1 does not need a general
5641 coprocessor delay. This means that INSN1 is a floating point
5642 comparison instruction. */
5643 /* Itbl support may require additional care here. */
5644 else if (!cop_interlocks
5645 && (pinfo1
& INSN_WRITE_COND_CODE
)
5646 && (pinfo2
& INSN_READ_COND_CODE
))
5653 /* Return the number of nops that would be needed to work around the
5654 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5655 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5656 that are contained within the first IGNORE instructions of HIST. */
5659 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
5660 const struct mips_cl_insn
*insn
)
5665 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5666 are not affected by the errata. */
5668 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
5669 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
5670 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
5673 /* Search for the first MFLO or MFHI. */
5674 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
5675 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
5677 /* Extract the destination register. */
5678 mask
= gpr_write_mask (&hist
[i
]);
5680 /* No nops are needed if INSN reads that register. */
5681 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
5684 /* ...or if any of the intervening instructions do. */
5685 for (j
= 0; j
< i
; j
++)
5686 if (gpr_read_mask (&hist
[j
]) & mask
)
5690 return MAX_VR4130_NOPS
- i
;
5695 #define BASE_REG_EQ(INSN1, INSN2) \
5696 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5697 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5699 /* Return the minimum alignment for this store instruction. */
5702 fix_24k_align_to (const struct mips_opcode
*mo
)
5704 if (strcmp (mo
->name
, "sh") == 0)
5707 if (strcmp (mo
->name
, "swc1") == 0
5708 || strcmp (mo
->name
, "swc2") == 0
5709 || strcmp (mo
->name
, "sw") == 0
5710 || strcmp (mo
->name
, "sc") == 0
5711 || strcmp (mo
->name
, "s.s") == 0)
5714 if (strcmp (mo
->name
, "sdc1") == 0
5715 || strcmp (mo
->name
, "sdc2") == 0
5716 || strcmp (mo
->name
, "s.d") == 0)
5723 struct fix_24k_store_info
5725 /* Immediate offset, if any, for this store instruction. */
5727 /* Alignment required by this store instruction. */
5729 /* True for register offsets. */
5730 int register_offset
;
5733 /* Comparison function used by qsort. */
5736 fix_24k_sort (const void *a
, const void *b
)
5738 const struct fix_24k_store_info
*pos1
= a
;
5739 const struct fix_24k_store_info
*pos2
= b
;
5741 return (pos1
->off
- pos2
->off
);
5744 /* INSN is a store instruction. Try to record the store information
5745 in STINFO. Return false if the information isn't known. */
5748 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
5749 const struct mips_cl_insn
*insn
)
5751 /* The instruction must have a known offset. */
5752 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
5755 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
5756 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
5760 /* Return the number of nops that would be needed to work around the 24k
5761 "lost data on stores during refill" errata if instruction INSN
5762 immediately followed the 2 instructions described by HIST.
5763 Ignore hazards that are contained within the first IGNORE
5764 instructions of HIST.
5766 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5767 for the data cache refills and store data. The following describes
5768 the scenario where the store data could be lost.
5770 * A data cache miss, due to either a load or a store, causing fill
5771 data to be supplied by the memory subsystem
5772 * The first three doublewords of fill data are returned and written
5774 * A sequence of four stores occurs in consecutive cycles around the
5775 final doubleword of the fill:
5779 * Zero, One or more instructions
5782 The four stores A-D must be to different doublewords of the line that
5783 is being filled. The fourth instruction in the sequence above permits
5784 the fill of the final doubleword to be transferred from the FSB into
5785 the cache. In the sequence above, the stores may be either integer
5786 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5787 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5788 different doublewords on the line. If the floating point unit is
5789 running in 1:2 mode, it is not possible to create the sequence above
5790 using only floating point store instructions.
5792 In this case, the cache line being filled is incorrectly marked
5793 invalid, thereby losing the data from any store to the line that
5794 occurs between the original miss and the completion of the five
5795 cycle sequence shown above.
5797 The workarounds are:
5799 * Run the data cache in write-through mode.
5800 * Insert a non-store instruction between
5801 Store A and Store B or Store B and Store C. */
5804 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
5805 const struct mips_cl_insn
*insn
)
5807 struct fix_24k_store_info pos
[3];
5808 int align
, i
, base_offset
;
5813 /* If the previous instruction wasn't a store, there's nothing to
5815 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5818 /* If the instructions after the previous one are unknown, we have
5819 to assume the worst. */
5823 /* Check whether we are dealing with three consecutive stores. */
5824 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
5825 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
5828 /* If we don't know the relationship between the store addresses,
5829 assume the worst. */
5830 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
5831 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
5834 if (!fix_24k_record_store_info (&pos
[0], insn
)
5835 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
5836 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
5839 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
5841 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5842 X bytes and such that the base register + X is known to be aligned
5845 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
5849 align
= pos
[0].align_to
;
5850 base_offset
= pos
[0].off
;
5851 for (i
= 1; i
< 3; i
++)
5852 if (align
< pos
[i
].align_to
)
5854 align
= pos
[i
].align_to
;
5855 base_offset
= pos
[i
].off
;
5857 for (i
= 0; i
< 3; i
++)
5858 pos
[i
].off
-= base_offset
;
5861 pos
[0].off
&= ~align
+ 1;
5862 pos
[1].off
&= ~align
+ 1;
5863 pos
[2].off
&= ~align
+ 1;
5865 /* If any two stores write to the same chunk, they also write to the
5866 same doubleword. The offsets are still sorted at this point. */
5867 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
5870 /* A range of at least 9 bytes is needed for the stores to be in
5871 non-overlapping doublewords. */
5872 if (pos
[2].off
- pos
[0].off
<= 8)
5875 if (pos
[2].off
- pos
[1].off
>= 24
5876 || pos
[1].off
- pos
[0].off
>= 24
5877 || pos
[2].off
- pos
[0].off
>= 32)
5883 /* Return the number of nops that would be needed if instruction INSN
5884 immediately followed the MAX_NOPS instructions given by HIST,
5885 where HIST[0] is the most recent instruction. Ignore hazards
5886 between INSN and the first IGNORE instructions in HIST.
5888 If INSN is null, return the worse-case number of nops for any
5892 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
5893 const struct mips_cl_insn
*insn
)
5895 int i
, nops
, tmp_nops
;
5898 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
5900 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
5901 if (tmp_nops
> nops
)
5905 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
5907 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
5908 if (tmp_nops
> nops
)
5912 if (mips_fix_24k
&& !mips_opts
.micromips
)
5914 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
5915 if (tmp_nops
> nops
)
5922 /* The variable arguments provide NUM_INSNS extra instructions that
5923 might be added to HIST. Return the largest number of nops that
5924 would be needed after the extended sequence, ignoring hazards
5925 in the first IGNORE instructions. */
5928 nops_for_sequence (int num_insns
, int ignore
,
5929 const struct mips_cl_insn
*hist
, ...)
5932 struct mips_cl_insn buffer
[MAX_NOPS
];
5933 struct mips_cl_insn
*cursor
;
5936 va_start (args
, hist
);
5937 cursor
= buffer
+ num_insns
;
5938 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
5939 while (cursor
> buffer
)
5940 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
5942 nops
= nops_for_insn (ignore
, buffer
, NULL
);
5947 /* Like nops_for_insn, but if INSN is a branch, take into account the
5948 worst-case delay for the branch target. */
5951 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
5952 const struct mips_cl_insn
*insn
)
5956 nops
= nops_for_insn (ignore
, hist
, insn
);
5957 if (delayed_branch_p (insn
))
5959 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
5960 hist
, insn
, get_delay_slot_nop (insn
));
5961 if (tmp_nops
> nops
)
5964 else if (compact_branch_p (insn
))
5966 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
5967 if (tmp_nops
> nops
)
5973 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5976 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
5978 gas_assert (!HAVE_CODE_COMPRESSION
);
5979 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
5980 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
5983 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5984 jr target pc &= 'hffff_ffff_cfff_ffff. */
5987 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
5989 gas_assert (!HAVE_CODE_COMPRESSION
);
5990 if (strcmp (ip
->insn_mo
->name
, "j") == 0
5991 || strcmp (ip
->insn_mo
->name
, "jr") == 0
5992 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6000 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6001 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6004 ep
.X_op
= O_constant
;
6005 ep
.X_add_number
= 0xcfff0000;
6006 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6007 ep
.X_add_number
= 0xffff;
6008 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6009 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6014 fix_loongson2f (struct mips_cl_insn
* ip
)
6016 if (mips_fix_loongson2f_nop
)
6017 fix_loongson2f_nop (ip
);
6019 if (mips_fix_loongson2f_jump
)
6020 fix_loongson2f_jump (ip
);
6023 /* IP is a branch that has a delay slot, and we need to fill it
6024 automatically. Return true if we can do that by swapping IP
6025 with the previous instruction.
6026 ADDRESS_EXPR is an operand of the instruction to be used with
6030 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6031 bfd_reloc_code_real_type
*reloc_type
)
6033 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
6034 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
6036 /* -O2 and above is required for this optimization. */
6037 if (mips_optimize
< 2)
6040 /* If we have seen .set volatile or .set nomove, don't optimize. */
6041 if (mips_opts
.nomove
)
6044 /* We can't swap if the previous instruction's position is fixed. */
6045 if (history
[0].fixed_p
)
6048 /* If the previous previous insn was in a .set noreorder, we can't
6049 swap. Actually, the MIPS assembler will swap in this situation.
6050 However, gcc configured -with-gnu-as will generate code like
6058 in which we can not swap the bne and INSN. If gcc is not configured
6059 -with-gnu-as, it does not output the .set pseudo-ops. */
6060 if (history
[1].noreorder_p
)
6063 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6064 This means that the previous instruction was a 4-byte one anyhow. */
6065 if (mips_opts
.mips16
&& history
[0].fixp
[0])
6068 /* If the branch is itself the target of a branch, we can not swap.
6069 We cheat on this; all we check for is whether there is a label on
6070 this instruction. If there are any branches to anything other than
6071 a label, users must use .set noreorder. */
6072 if (seg_info (now_seg
)->label_list
)
6075 /* If the previous instruction is in a variant frag other than this
6076 branch's one, we cannot do the swap. This does not apply to
6077 MIPS16 code, which uses variant frags for different purposes. */
6078 if (!mips_opts
.mips16
6080 && history
[0].frag
->fr_type
== rs_machine_dependent
)
6083 /* We do not swap with instructions that cannot architecturally
6084 be placed in a branch delay slot, such as SYNC or ERET. We
6085 also refrain from swapping with a trap instruction, since it
6086 complicates trap handlers to have the trap instruction be in
6088 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6089 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
6092 /* Check for conflicts between the branch and the instructions
6093 before the candidate delay slot. */
6094 if (nops_for_insn (0, history
+ 1, ip
) > 0)
6097 /* Check for conflicts between the swapped sequence and the
6098 target of the branch. */
6099 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
6102 /* If the branch reads a register that the previous
6103 instruction sets, we can not swap. */
6104 gpr_read
= gpr_read_mask (ip
);
6105 prev_gpr_write
= gpr_write_mask (&history
[0]);
6106 if (gpr_read
& prev_gpr_write
)
6109 /* If the branch writes a register that the previous
6110 instruction sets, we can not swap. */
6111 gpr_write
= gpr_write_mask (ip
);
6112 if (gpr_write
& prev_gpr_write
)
6115 /* If the branch writes a register that the previous
6116 instruction reads, we can not swap. */
6117 prev_gpr_read
= gpr_read_mask (&history
[0]);
6118 if (gpr_write
& prev_gpr_read
)
6121 /* If one instruction sets a condition code and the
6122 other one uses a condition code, we can not swap. */
6123 pinfo
= ip
->insn_mo
->pinfo
;
6124 if ((pinfo
& INSN_READ_COND_CODE
)
6125 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
6127 if ((pinfo
& INSN_WRITE_COND_CODE
)
6128 && (prev_pinfo
& INSN_READ_COND_CODE
))
6131 /* If the previous instruction uses the PC, we can not swap. */
6132 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6133 if (prev_pinfo2
& INSN2_READ_PC
)
6136 /* If the previous instruction has an incorrect size for a fixed
6137 branch delay slot in microMIPS mode, we cannot swap. */
6138 pinfo2
= ip
->insn_mo
->pinfo2
;
6139 if (mips_opts
.micromips
6140 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
6141 && insn_length (history
) != 2)
6143 if (mips_opts
.micromips
6144 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
6145 && insn_length (history
) != 4)
6148 /* On R5900 short loops need to be fixed by inserting a nop in
6149 the branch delay slots.
6150 A short loop can be terminated too early. */
6151 if (mips_opts
.arch
== CPU_R5900
6152 /* Check if instruction has a parameter, ignore "j $31". */
6153 && (address_expr
!= NULL
)
6154 /* Parameter must be 16 bit. */
6155 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
6156 /* Branch to same segment. */
6157 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
6158 /* Branch to same code fragment. */
6159 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
6160 /* Can only calculate branch offset if value is known. */
6161 && symbol_constant_p(address_expr
->X_add_symbol
)
6162 /* Check if branch is really conditional. */
6163 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6164 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
6165 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6168 /* Check if loop is shorter than 6 instructions including
6169 branch and delay slot. */
6170 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
6177 /* When the loop includes branches or jumps,
6178 it is not a short loop. */
6179 for (i
= 0; i
< (distance
/ 4); i
++)
6181 if ((history
[i
].cleared_p
)
6182 || delayed_branch_p(&history
[i
]))
6190 /* Insert nop after branch to fix short loop. */
6199 /* Decide how we should add IP to the instruction stream.
6200 ADDRESS_EXPR is an operand of the instruction to be used with
6203 static enum append_method
6204 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6205 bfd_reloc_code_real_type
*reloc_type
)
6207 /* The relaxed version of a macro sequence must be inherently
6209 if (mips_relax
.sequence
== 2)
6212 /* We must not dabble with instructions in a ".set norerorder" block. */
6213 if (mips_opts
.noreorder
)
6216 /* Otherwise, it's our responsibility to fill branch delay slots. */
6217 if (delayed_branch_p (ip
))
6219 if (!branch_likely_p (ip
)
6220 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
6223 if (mips_opts
.mips16
6224 && ISA_SUPPORTS_MIPS16E
6225 && gpr_read_mask (ip
) != 0)
6226 return APPEND_ADD_COMPACT
;
6228 return APPEND_ADD_WITH_NOP
;
6234 /* IP is a MIPS16 instruction whose opcode we have just changed.
6235 Point IP->insn_mo to the new opcode's definition. */
6238 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
6240 const struct mips_opcode
*mo
, *end
;
6242 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
6243 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
6244 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
6252 /* For microMIPS macros, we need to generate a local number label
6253 as the target of branches. */
6254 #define MICROMIPS_LABEL_CHAR '\037'
6255 static unsigned long micromips_target_label
;
6256 static char micromips_target_name
[32];
6259 micromips_label_name (void)
6261 char *p
= micromips_target_name
;
6262 char symbol_name_temporary
[24];
6270 l
= micromips_target_label
;
6271 #ifdef LOCAL_LABEL_PREFIX
6272 *p
++ = LOCAL_LABEL_PREFIX
;
6275 *p
++ = MICROMIPS_LABEL_CHAR
;
6278 symbol_name_temporary
[i
++] = l
% 10 + '0';
6283 *p
++ = symbol_name_temporary
[--i
];
6286 return micromips_target_name
;
6290 micromips_label_expr (expressionS
*label_expr
)
6292 label_expr
->X_op
= O_symbol
;
6293 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
6294 label_expr
->X_add_number
= 0;
6298 micromips_label_inc (void)
6300 micromips_target_label
++;
6301 *micromips_target_name
= '\0';
6305 micromips_add_label (void)
6309 s
= colon (micromips_label_name ());
6310 micromips_label_inc ();
6311 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
6314 /* If assembling microMIPS code, then return the microMIPS reloc
6315 corresponding to the requested one if any. Otherwise return
6316 the reloc unchanged. */
6318 static bfd_reloc_code_real_type
6319 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
6321 static const bfd_reloc_code_real_type relocs
[][2] =
6323 /* Keep sorted incrementally by the left-hand key. */
6324 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
6325 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
6326 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
6327 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
6328 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
6329 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
6330 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
6331 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
6332 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
6333 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
6334 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
6335 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
6336 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
6337 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
6338 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
6339 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
6340 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
6341 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
6342 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
6343 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
6344 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
6345 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
6346 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
6347 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
6348 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
6349 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
6350 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
6352 bfd_reloc_code_real_type r
;
6355 if (!mips_opts
.micromips
)
6357 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
6363 return relocs
[i
][1];
6368 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6369 Return true on success, storing the resolved value in RESULT. */
6372 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
6377 case BFD_RELOC_MIPS_HIGHEST
:
6378 case BFD_RELOC_MICROMIPS_HIGHEST
:
6379 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
6382 case BFD_RELOC_MIPS_HIGHER
:
6383 case BFD_RELOC_MICROMIPS_HIGHER
:
6384 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
6387 case BFD_RELOC_HI16_S
:
6388 case BFD_RELOC_MICROMIPS_HI16_S
:
6389 case BFD_RELOC_MIPS16_HI16_S
:
6390 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
6393 case BFD_RELOC_HI16
:
6394 case BFD_RELOC_MICROMIPS_HI16
:
6395 case BFD_RELOC_MIPS16_HI16
:
6396 *result
= (operand
>> 16) & 0xffff;
6399 case BFD_RELOC_LO16
:
6400 case BFD_RELOC_MICROMIPS_LO16
:
6401 case BFD_RELOC_MIPS16_LO16
:
6402 *result
= operand
& 0xffff;
6405 case BFD_RELOC_UNUSED
:
6414 /* Output an instruction. IP is the instruction information.
6415 ADDRESS_EXPR is an operand of the instruction to be used with
6416 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6417 a macro expansion. */
6420 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
6421 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
6423 unsigned long prev_pinfo2
, pinfo
;
6424 bfd_boolean relaxed_branch
= FALSE
;
6425 enum append_method method
;
6426 bfd_boolean relax32
;
6429 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
6430 fix_loongson2f (ip
);
6432 file_ase_mips16
|= mips_opts
.mips16
;
6433 file_ase_micromips
|= mips_opts
.micromips
;
6435 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
6436 pinfo
= ip
->insn_mo
->pinfo
;
6438 if (mips_opts
.micromips
6440 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
6441 && micromips_insn_length (ip
->insn_mo
) != 2)
6442 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
6443 && micromips_insn_length (ip
->insn_mo
) != 4)))
6444 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6445 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
6447 if (address_expr
== NULL
)
6449 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
6450 && reloc_type
[1] == BFD_RELOC_UNUSED
6451 && reloc_type
[2] == BFD_RELOC_UNUSED
6452 && address_expr
->X_op
== O_constant
)
6454 switch (*reloc_type
)
6456 case BFD_RELOC_MIPS_JMP
:
6460 shift
= mips_opts
.micromips
? 1 : 2;
6461 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6462 as_bad (_("jump to misaligned address (0x%lx)"),
6463 (unsigned long) address_expr
->X_add_number
);
6464 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6470 case BFD_RELOC_MIPS16_JMP
:
6471 if ((address_expr
->X_add_number
& 3) != 0)
6472 as_bad (_("jump to misaligned address (0x%lx)"),
6473 (unsigned long) address_expr
->X_add_number
);
6475 (((address_expr
->X_add_number
& 0x7c0000) << 3)
6476 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
6477 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
6481 case BFD_RELOC_16_PCREL_S2
:
6485 shift
= mips_opts
.micromips
? 1 : 2;
6486 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
6487 as_bad (_("branch to misaligned address (0x%lx)"),
6488 (unsigned long) address_expr
->X_add_number
);
6489 if (!mips_relax_branch
)
6491 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
6492 & ~((1 << (shift
+ 16)) - 1))
6493 as_bad (_("branch address range overflow (0x%lx)"),
6494 (unsigned long) address_expr
->X_add_number
);
6495 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
6505 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
6508 ip
->insn_opcode
|= value
& 0xffff;
6516 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
6518 /* There are a lot of optimizations we could do that we don't.
6519 In particular, we do not, in general, reorder instructions.
6520 If you use gcc with optimization, it will reorder
6521 instructions and generally do much more optimization then we
6522 do here; repeating all that work in the assembler would only
6523 benefit hand written assembly code, and does not seem worth
6525 int nops
= (mips_optimize
== 0
6526 ? nops_for_insn (0, history
, NULL
)
6527 : nops_for_insn_or_target (0, history
, ip
));
6531 unsigned long old_frag_offset
;
6534 old_frag
= frag_now
;
6535 old_frag_offset
= frag_now_fix ();
6537 for (i
= 0; i
< nops
; i
++)
6538 add_fixed_insn (NOP_INSN
);
6539 insert_into_history (0, nops
, NOP_INSN
);
6543 listing_prev_line ();
6544 /* We may be at the start of a variant frag. In case we
6545 are, make sure there is enough space for the frag
6546 after the frags created by listing_prev_line. The
6547 argument to frag_grow here must be at least as large
6548 as the argument to all other calls to frag_grow in
6549 this file. We don't have to worry about being in the
6550 middle of a variant frag, because the variants insert
6551 all needed nop instructions themselves. */
6555 mips_move_text_labels ();
6557 #ifndef NO_ECOFF_DEBUGGING
6558 if (ECOFF_DEBUGGING
)
6559 ecoff_fix_loc (old_frag
, old_frag_offset
);
6563 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
6567 /* Work out how many nops in prev_nop_frag are needed by IP,
6568 ignoring hazards generated by the first prev_nop_frag_since
6570 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
6571 gas_assert (nops
<= prev_nop_frag_holds
);
6573 /* Enforce NOPS as a minimum. */
6574 if (nops
> prev_nop_frag_required
)
6575 prev_nop_frag_required
= nops
;
6577 if (prev_nop_frag_holds
== prev_nop_frag_required
)
6579 /* Settle for the current number of nops. Update the history
6580 accordingly (for the benefit of any future .set reorder code). */
6581 prev_nop_frag
= NULL
;
6582 insert_into_history (prev_nop_frag_since
,
6583 prev_nop_frag_holds
, NOP_INSN
);
6587 /* Allow this instruction to replace one of the nops that was
6588 tentatively added to prev_nop_frag. */
6589 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
6590 prev_nop_frag_holds
--;
6591 prev_nop_frag_since
++;
6595 method
= get_append_method (ip
, address_expr
, reloc_type
);
6596 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
6598 dwarf2_emit_insn (0);
6599 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6600 so "move" the instruction address accordingly.
6602 Also, it doesn't seem appropriate for the assembler to reorder .loc
6603 entries. If this instruction is a branch that we are going to swap
6604 with the previous instruction, the two instructions should be
6605 treated as a unit, and the debug information for both instructions
6606 should refer to the start of the branch sequence. Using the
6607 current position is certainly wrong when swapping a 32-bit branch
6608 and a 16-bit delay slot, since the current position would then be
6609 in the middle of a branch. */
6610 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
6612 relax32
= (mips_relax_branch
6613 /* Don't try branch relaxation within .set nomacro, or within
6614 .set noat if we use $at for PIC computations. If it turns
6615 out that the branch was out-of-range, we'll get an error. */
6616 && !mips_opts
.warn_about_macros
6617 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
6618 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6619 as they have no complementing branches. */
6620 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
6622 if (!HAVE_CODE_COMPRESSION
6625 && *reloc_type
== BFD_RELOC_16_PCREL_S2
6626 && delayed_branch_p (ip
))
6628 relaxed_branch
= TRUE
;
6629 add_relaxed_insn (ip
, (relaxed_branch_length
6631 uncond_branch_p (ip
) ? -1
6632 : branch_likely_p (ip
) ? 1
6636 uncond_branch_p (ip
),
6637 branch_likely_p (ip
),
6638 pinfo
& INSN_WRITE_GPR_31
,
6640 address_expr
->X_add_symbol
,
6641 address_expr
->X_add_number
);
6642 *reloc_type
= BFD_RELOC_UNUSED
;
6644 else if (mips_opts
.micromips
6646 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
6647 || *reloc_type
> BFD_RELOC_UNUSED
)
6648 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
6649 /* Don't try branch relaxation when users specify
6650 16-bit/32-bit instructions. */
6651 && !forced_insn_length
)
6653 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
6654 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
6655 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
6656 int compact
= compact_branch_p (ip
);
6657 int al
= pinfo
& INSN_WRITE_GPR_31
;
6660 gas_assert (address_expr
!= NULL
);
6661 gas_assert (!mips_relax
.sequence
);
6663 relaxed_branch
= TRUE
;
6664 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
6665 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
6666 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
6668 address_expr
->X_add_symbol
,
6669 address_expr
->X_add_number
);
6670 *reloc_type
= BFD_RELOC_UNUSED
;
6672 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
6674 /* We need to set up a variant frag. */
6675 gas_assert (address_expr
!= NULL
);
6676 add_relaxed_insn (ip
, 4, 0,
6678 (*reloc_type
- BFD_RELOC_UNUSED
,
6679 forced_insn_length
== 2, forced_insn_length
== 4,
6680 delayed_branch_p (&history
[0]),
6681 history
[0].mips16_absolute_jump_p
),
6682 make_expr_symbol (address_expr
), 0);
6684 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
6686 if (!delayed_branch_p (ip
))
6687 /* Make sure there is enough room to swap this instruction with
6688 a following jump instruction. */
6690 add_fixed_insn (ip
);
6694 if (mips_opts
.mips16
6695 && mips_opts
.noreorder
6696 && delayed_branch_p (&history
[0]))
6697 as_warn (_("extended instruction in delay slot"));
6699 if (mips_relax
.sequence
)
6701 /* If we've reached the end of this frag, turn it into a variant
6702 frag and record the information for the instructions we've
6704 if (frag_room () < 4)
6705 relax_close_frag ();
6706 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
6709 if (mips_relax
.sequence
!= 2)
6711 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
6712 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
6713 mips_macro_warning
.sizes
[0] += insn_length (ip
);
6714 mips_macro_warning
.insns
[0]++;
6716 if (mips_relax
.sequence
!= 1)
6718 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
6719 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
6720 mips_macro_warning
.sizes
[1] += insn_length (ip
);
6721 mips_macro_warning
.insns
[1]++;
6724 if (mips_opts
.mips16
)
6727 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
6729 add_fixed_insn (ip
);
6732 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
6734 bfd_reloc_code_real_type final_type
[3];
6735 reloc_howto_type
*howto0
;
6736 reloc_howto_type
*howto
;
6739 /* Perform any necessary conversion to microMIPS relocations
6740 and find out how many relocations there actually are. */
6741 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
6742 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
6744 /* In a compound relocation, it is the final (outermost)
6745 operator that determines the relocated field. */
6746 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
6751 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
6752 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
6753 bfd_get_reloc_size (howto
),
6755 howto0
&& howto0
->pc_relative
,
6758 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6759 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
6760 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
6762 /* These relocations can have an addend that won't fit in
6763 4 octets for 64bit assembly. */
6765 && ! howto
->partial_inplace
6766 && (reloc_type
[0] == BFD_RELOC_16
6767 || reloc_type
[0] == BFD_RELOC_32
6768 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
6769 || reloc_type
[0] == BFD_RELOC_GPREL16
6770 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
6771 || reloc_type
[0] == BFD_RELOC_GPREL32
6772 || reloc_type
[0] == BFD_RELOC_64
6773 || reloc_type
[0] == BFD_RELOC_CTOR
6774 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
6775 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
6776 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
6777 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
6778 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
6779 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
6780 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
6781 || hi16_reloc_p (reloc_type
[0])
6782 || lo16_reloc_p (reloc_type
[0])))
6783 ip
->fixp
[0]->fx_no_overflow
= 1;
6785 /* These relocations can have an addend that won't fit in 2 octets. */
6786 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6787 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
6788 ip
->fixp
[0]->fx_no_overflow
= 1;
6790 if (mips_relax
.sequence
)
6792 if (mips_relax
.first_fixup
== 0)
6793 mips_relax
.first_fixup
= ip
->fixp
[0];
6795 else if (reloc_needs_lo_p (*reloc_type
))
6797 struct mips_hi_fixup
*hi_fixup
;
6799 /* Reuse the last entry if it already has a matching %lo. */
6800 hi_fixup
= mips_hi_fixup_list
;
6802 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
6804 hi_fixup
= ((struct mips_hi_fixup
*)
6805 xmalloc (sizeof (struct mips_hi_fixup
)));
6806 hi_fixup
->next
= mips_hi_fixup_list
;
6807 mips_hi_fixup_list
= hi_fixup
;
6809 hi_fixup
->fixp
= ip
->fixp
[0];
6810 hi_fixup
->seg
= now_seg
;
6813 /* Add fixups for the second and third relocations, if given.
6814 Note that the ABI allows the second relocation to be
6815 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6816 moment we only use RSS_UNDEF, but we could add support
6817 for the others if it ever becomes necessary. */
6818 for (i
= 1; i
< 3; i
++)
6819 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
6821 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
6822 ip
->fixp
[0]->fx_size
, NULL
, 0,
6823 FALSE
, final_type
[i
]);
6825 /* Use fx_tcbit to mark compound relocs. */
6826 ip
->fixp
[0]->fx_tcbit
= 1;
6827 ip
->fixp
[i
]->fx_tcbit
= 1;
6832 /* Update the register mask information. */
6833 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
6834 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
6839 insert_into_history (0, 1, ip
);
6842 case APPEND_ADD_WITH_NOP
:
6844 struct mips_cl_insn
*nop
;
6846 insert_into_history (0, 1, ip
);
6847 nop
= get_delay_slot_nop (ip
);
6848 add_fixed_insn (nop
);
6849 insert_into_history (0, 1, nop
);
6850 if (mips_relax
.sequence
)
6851 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
6855 case APPEND_ADD_COMPACT
:
6856 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6857 gas_assert (mips_opts
.mips16
);
6858 ip
->insn_opcode
|= 0x0080;
6859 find_altered_mips16_opcode (ip
);
6861 insert_into_history (0, 1, ip
);
6866 struct mips_cl_insn delay
= history
[0];
6867 if (mips_opts
.mips16
)
6869 know (delay
.frag
== ip
->frag
);
6870 move_insn (ip
, delay
.frag
, delay
.where
);
6871 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
6873 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
6875 /* Add the delay slot instruction to the end of the
6876 current frag and shrink the fixed part of the
6877 original frag. If the branch occupies the tail of
6878 the latter, move it backwards to cover the gap. */
6879 delay
.frag
->fr_fix
-= branch_disp
;
6880 if (delay
.frag
== ip
->frag
)
6881 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
6882 add_fixed_insn (&delay
);
6886 move_insn (&delay
, ip
->frag
,
6887 ip
->where
- branch_disp
+ insn_length (ip
));
6888 move_insn (ip
, history
[0].frag
, history
[0].where
);
6892 insert_into_history (0, 1, &delay
);
6897 /* If we have just completed an unconditional branch, clear the history. */
6898 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
6899 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
6903 mips_no_prev_insn ();
6905 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6906 history
[i
].cleared_p
= 1;
6909 /* We need to emit a label at the end of branch-likely macros. */
6910 if (emit_branch_likely_macro
)
6912 emit_branch_likely_macro
= FALSE
;
6913 micromips_add_label ();
6916 /* We just output an insn, so the next one doesn't have a label. */
6917 mips_clear_insn_labels ();
6920 /* Forget that there was any previous instruction or label.
6921 When BRANCH is true, the branch history is also flushed. */
6924 mips_no_prev_insn (void)
6926 prev_nop_frag
= NULL
;
6927 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
6928 mips_clear_insn_labels ();
6931 /* This function must be called before we emit something other than
6932 instructions. It is like mips_no_prev_insn except that it inserts
6933 any NOPS that might be needed by previous instructions. */
6936 mips_emit_delays (void)
6938 if (! mips_opts
.noreorder
)
6940 int nops
= nops_for_insn (0, history
, NULL
);
6944 add_fixed_insn (NOP_INSN
);
6945 mips_move_text_labels ();
6948 mips_no_prev_insn ();
6951 /* Start a (possibly nested) noreorder block. */
6954 start_noreorder (void)
6956 if (mips_opts
.noreorder
== 0)
6961 /* None of the instructions before the .set noreorder can be moved. */
6962 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
6963 history
[i
].fixed_p
= 1;
6965 /* Insert any nops that might be needed between the .set noreorder
6966 block and the previous instructions. We will later remove any
6967 nops that turn out not to be needed. */
6968 nops
= nops_for_insn (0, history
, NULL
);
6971 if (mips_optimize
!= 0)
6973 /* Record the frag which holds the nop instructions, so
6974 that we can remove them if we don't need them. */
6975 frag_grow (nops
* NOP_INSN_SIZE
);
6976 prev_nop_frag
= frag_now
;
6977 prev_nop_frag_holds
= nops
;
6978 prev_nop_frag_required
= 0;
6979 prev_nop_frag_since
= 0;
6982 for (; nops
> 0; --nops
)
6983 add_fixed_insn (NOP_INSN
);
6985 /* Move on to a new frag, so that it is safe to simply
6986 decrease the size of prev_nop_frag. */
6987 frag_wane (frag_now
);
6989 mips_move_text_labels ();
6991 mips_mark_labels ();
6992 mips_clear_insn_labels ();
6994 mips_opts
.noreorder
++;
6995 mips_any_noreorder
= 1;
6998 /* End a nested noreorder block. */
7001 end_noreorder (void)
7003 mips_opts
.noreorder
--;
7004 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
7006 /* Commit to inserting prev_nop_frag_required nops and go back to
7007 handling nop insertion the .set reorder way. */
7008 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
7010 insert_into_history (prev_nop_frag_since
,
7011 prev_nop_frag_required
, NOP_INSN
);
7012 prev_nop_frag
= NULL
;
7016 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7017 higher bits unset. */
7020 normalize_constant_expr (expressionS
*ex
)
7022 if (ex
->X_op
== O_constant
7023 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7024 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7028 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7029 all higher bits unset. */
7032 normalize_address_expr (expressionS
*ex
)
7034 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
7035 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
7036 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
7037 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
7041 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7042 Return true if the match was successful.
7044 OPCODE_EXTRA is a value that should be ORed into the opcode
7045 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7046 there are more alternatives after OPCODE and SOFT_MATCH is
7047 as for mips_arg_info. */
7050 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7051 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
7052 bfd_boolean lax_match
, bfd_boolean complete_p
)
7055 struct mips_arg_info arg
;
7056 const struct mips_operand
*operand
;
7059 imm_expr
.X_op
= O_absent
;
7060 imm2_expr
.X_op
= O_absent
;
7061 offset_expr
.X_op
= O_absent
;
7062 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7063 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7064 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7066 create_insn (insn
, opcode
);
7067 /* When no opcode suffix is specified, assume ".xyzw". */
7068 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
7069 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
7071 insn
->insn_opcode
|= opcode_extra
;
7072 memset (&arg
, 0, sizeof (arg
));
7076 arg
.last_regno
= ILLEGAL_REG
;
7077 arg
.dest_regno
= ILLEGAL_REG
;
7078 arg
.lax_match
= lax_match
;
7079 for (args
= opcode
->args
;; ++args
)
7081 if (arg
.token
->type
== OT_END
)
7083 /* Handle unary instructions in which only one operand is given.
7084 The source is then the same as the destination. */
7085 if (arg
.opnum
== 1 && *args
== ',')
7087 operand
= (mips_opts
.micromips
7088 ? decode_micromips_operand (args
+ 1)
7089 : decode_mips_operand (args
+ 1));
7090 if (operand
&& mips_optional_operand_p (operand
))
7098 /* Treat elided base registers as $0. */
7099 if (strcmp (args
, "(b)") == 0)
7107 /* The register suffix is optional. */
7112 /* Fail the match if there were too few operands. */
7116 /* Successful match. */
7119 clear_insn_error ();
7120 if (arg
.dest_regno
== arg
.last_regno
7121 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
7125 (0, _("Source and destination must be different"));
7126 else if (arg
.last_regno
== 31)
7128 (0, _("A destination register must be supplied"));
7130 check_completed_insn (&arg
);
7134 /* Fail the match if the line has too many operands. */
7138 /* Handle characters that need to match exactly. */
7139 if (*args
== '(' || *args
== ')' || *args
== ',')
7141 if (match_char (&arg
, *args
))
7148 if (arg
.token
->type
== OT_DOUBLE_CHAR
7149 && arg
.token
->u
.ch
== *args
)
7157 /* Handle special macro operands. Work out the properties of
7166 /* "+I" is like "I", except that imm2_expr is used. */
7167 if (!match_const_int (&arg
, &imm2_expr
.X_add_number
))
7169 imm2_expr
.X_op
= O_constant
;
7170 if (HAVE_32BIT_GPRS
)
7171 normalize_constant_expr (&imm2_expr
);
7176 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7182 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7184 imm_expr
.X_op
= O_constant
;
7185 if (HAVE_32BIT_GPRS
)
7186 normalize_constant_expr (&imm_expr
);
7190 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7192 /* Assume that the offset has been elided and that what
7193 we saw was a base register. The match will fail later
7194 if that assumption turns out to be wrong. */
7195 offset_expr
.X_op
= O_constant
;
7196 offset_expr
.X_add_number
= 0;
7200 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
7202 normalize_address_expr (&offset_expr
);
7207 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7213 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7219 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7225 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
7231 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7235 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
7239 gas_assert (mips_opts
.micromips
);
7245 if (!forced_insn_length
)
7246 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7248 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
7250 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
7256 operand
= (mips_opts
.micromips
7257 ? decode_micromips_operand (args
)
7258 : decode_mips_operand (args
));
7262 /* Skip prefixes. */
7263 if (*args
== '+' || *args
== 'm')
7266 if (mips_optional_operand_p (operand
)
7268 && (arg
.token
[0].type
!= OT_REG
7269 || arg
.token
[1].type
== OT_END
))
7271 /* Assume that the register has been elided and is the
7272 same as the first operand. */
7277 if (!match_operand (&arg
, operand
))
7282 /* Like match_insn, but for MIPS16. */
7285 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
7286 struct mips_operand_token
*tokens
)
7289 const struct mips_operand
*operand
;
7290 const struct mips_operand
*ext_operand
;
7291 struct mips_arg_info arg
;
7294 create_insn (insn
, opcode
);
7295 imm_expr
.X_op
= O_absent
;
7296 imm2_expr
.X_op
= O_absent
;
7297 offset_expr
.X_op
= O_absent
;
7298 offset_reloc
[0] = BFD_RELOC_UNUSED
;
7299 offset_reloc
[1] = BFD_RELOC_UNUSED
;
7300 offset_reloc
[2] = BFD_RELOC_UNUSED
;
7303 memset (&arg
, 0, sizeof (arg
));
7307 arg
.last_regno
= ILLEGAL_REG
;
7308 arg
.dest_regno
= ILLEGAL_REG
;
7310 for (args
= opcode
->args
;; ++args
)
7314 if (arg
.token
->type
== OT_END
)
7318 /* Handle unary instructions in which only one operand is given.
7319 The source is then the same as the destination. */
7320 if (arg
.opnum
== 1 && *args
== ',')
7322 operand
= decode_mips16_operand (args
[1], FALSE
);
7323 if (operand
&& mips_optional_operand_p (operand
))
7331 /* Fail the match if there were too few operands. */
7335 /* Successful match. Stuff the immediate value in now, if
7337 clear_insn_error ();
7338 if (opcode
->pinfo
== INSN_MACRO
)
7340 gas_assert (relax_char
== 0 || relax_char
== 'p');
7341 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
7344 && offset_expr
.X_op
== O_constant
7345 && calculate_reloc (*offset_reloc
,
7346 offset_expr
.X_add_number
,
7349 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
7350 forced_insn_length
, &insn
->insn_opcode
);
7351 offset_expr
.X_op
= O_absent
;
7352 *offset_reloc
= BFD_RELOC_UNUSED
;
7354 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
7356 if (forced_insn_length
== 2)
7357 set_insn_error (0, _("invalid unextended operand value"));
7358 forced_insn_length
= 4;
7359 insn
->insn_opcode
|= MIPS16_EXTEND
;
7361 else if (relax_char
)
7362 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
7364 check_completed_insn (&arg
);
7368 /* Fail the match if the line has too many operands. */
7372 /* Handle characters that need to match exactly. */
7373 if (*args
== '(' || *args
== ')' || *args
== ',')
7375 if (match_char (&arg
, *args
))
7393 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
7395 imm_expr
.X_op
= O_constant
;
7396 if (HAVE_32BIT_GPRS
)
7397 normalize_constant_expr (&imm_expr
);
7402 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7403 insn
->insn_opcode
<<= 16;
7407 operand
= decode_mips16_operand (c
, FALSE
);
7411 /* '6' is a special case. It is used for BREAK and SDBBP,
7412 whose operands are only meaningful to the software that decodes
7413 them. This means that there is no architectural reason why
7414 they cannot be prefixed by EXTEND, but in practice,
7415 exception handlers will only look at the instruction
7416 itself. We therefore allow '6' to be extended when
7417 disassembling but not when assembling. */
7418 if (operand
->type
!= OP_PCREL
&& c
!= '6')
7420 ext_operand
= decode_mips16_operand (c
, TRUE
);
7421 if (operand
!= ext_operand
)
7423 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
7425 offset_expr
.X_op
= O_constant
;
7426 offset_expr
.X_add_number
= 0;
7431 /* We need the OT_INTEGER check because some MIPS16
7432 immediate variants are listed before the register ones. */
7433 if (arg
.token
->type
!= OT_INTEGER
7434 || !match_expression (&arg
, &offset_expr
, offset_reloc
))
7437 /* '8' is used for SLTI(U) and has traditionally not
7438 been allowed to take relocation operators. */
7439 if (offset_reloc
[0] != BFD_RELOC_UNUSED
7440 && (ext_operand
->size
!= 16 || c
== '8'))
7448 if (mips_optional_operand_p (operand
)
7450 && (arg
.token
[0].type
!= OT_REG
7451 || arg
.token
[1].type
== OT_END
))
7453 /* Assume that the register has been elided and is the
7454 same as the first operand. */
7459 if (!match_operand (&arg
, operand
))
7464 /* Record that the current instruction is invalid for the current ISA. */
7467 match_invalid_for_isa (void)
7470 (0, _("Opcode not supported on this processor: %s (%s)"),
7471 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7472 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7475 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
7476 Return true if a definite match or failure was found, storing any match
7477 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
7478 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
7479 tried and failed to match under normal conditions and now want to try a
7480 more relaxed match. */
7483 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7484 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
7485 int opcode_extra
, bfd_boolean lax_match
)
7487 const struct mips_opcode
*opcode
;
7488 const struct mips_opcode
*invalid_delay_slot
;
7489 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
7491 /* Search for a match, ignoring alternatives that don't satisfy the
7492 current ISA or forced_length. */
7493 invalid_delay_slot
= 0;
7494 seen_valid_for_isa
= FALSE
;
7495 seen_valid_for_size
= FALSE
;
7499 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7500 if (is_opcode_valid (opcode
))
7502 seen_valid_for_isa
= TRUE
;
7503 if (is_size_valid (opcode
))
7505 bfd_boolean delay_slot_ok
;
7507 seen_valid_for_size
= TRUE
;
7508 delay_slot_ok
= is_delay_slot_valid (opcode
);
7509 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
7510 lax_match
, delay_slot_ok
))
7514 if (!invalid_delay_slot
)
7515 invalid_delay_slot
= opcode
;
7524 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
7526 /* If the only matches we found had the wrong length for the delay slot,
7527 pick the first such match. We'll issue an appropriate warning later. */
7528 if (invalid_delay_slot
)
7530 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
7536 /* Handle the case where we didn't try to match an instruction because
7537 all the alternatives were incompatible with the current ISA. */
7538 if (!seen_valid_for_isa
)
7540 match_invalid_for_isa ();
7544 /* Handle the case where we didn't try to match an instruction because
7545 all the alternatives were of the wrong size. */
7546 if (!seen_valid_for_size
)
7548 if (mips_opts
.insn32
)
7549 set_insn_error (0, _("Opcode not supported in the `insn32' mode"));
7552 (0, _("Unrecognized %d-bit version of microMIPS opcode"),
7553 8 * forced_insn_length
);
7560 /* Like match_insns, but for MIPS16. */
7563 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
7564 struct mips_operand_token
*tokens
)
7566 const struct mips_opcode
*opcode
;
7567 bfd_boolean seen_valid_for_isa
;
7569 /* Search for a match, ignoring alternatives that don't satisfy the
7570 current ISA. There are no separate entries for extended forms so
7571 we deal with forced_length later. */
7572 seen_valid_for_isa
= FALSE
;
7576 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
7577 if (is_opcode_valid_16 (opcode
))
7579 seen_valid_for_isa
= TRUE
;
7580 if (match_mips16_insn (insn
, opcode
, tokens
))
7585 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
7586 && strcmp (opcode
->name
, first
->name
) == 0);
7588 /* Handle the case where we didn't try to match an instruction because
7589 all the alternatives were incompatible with the current ISA. */
7590 if (!seen_valid_for_isa
)
7592 match_invalid_for_isa ();
7599 /* Set up global variables for the start of a new macro. */
7604 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
7605 memset (&mips_macro_warning
.first_insn_sizes
, 0,
7606 sizeof (mips_macro_warning
.first_insn_sizes
));
7607 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
7608 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
7609 && delayed_branch_p (&history
[0]));
7610 switch (history
[0].insn_mo
->pinfo2
7611 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
7613 case INSN2_BRANCH_DELAY_32BIT
:
7614 mips_macro_warning
.delay_slot_length
= 4;
7616 case INSN2_BRANCH_DELAY_16BIT
:
7617 mips_macro_warning
.delay_slot_length
= 2;
7620 mips_macro_warning
.delay_slot_length
= 0;
7623 mips_macro_warning
.first_frag
= NULL
;
7626 /* Given that a macro is longer than one instruction or of the wrong size,
7627 return the appropriate warning for it. Return null if no warning is
7628 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7629 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7630 and RELAX_NOMACRO. */
7633 macro_warning (relax_substateT subtype
)
7635 if (subtype
& RELAX_DELAY_SLOT
)
7636 return _("Macro instruction expanded into multiple instructions"
7637 " in a branch delay slot");
7638 else if (subtype
& RELAX_NOMACRO
)
7639 return _("Macro instruction expanded into multiple instructions");
7640 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
7641 | RELAX_DELAY_SLOT_SIZE_SECOND
))
7642 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
7643 ? _("Macro instruction expanded into a wrong size instruction"
7644 " in a 16-bit branch delay slot")
7645 : _("Macro instruction expanded into a wrong size instruction"
7646 " in a 32-bit branch delay slot"));
7651 /* Finish up a macro. Emit warnings as appropriate. */
7656 /* Relaxation warning flags. */
7657 relax_substateT subtype
= 0;
7659 /* Check delay slot size requirements. */
7660 if (mips_macro_warning
.delay_slot_length
== 2)
7661 subtype
|= RELAX_DELAY_SLOT_16BIT
;
7662 if (mips_macro_warning
.delay_slot_length
!= 0)
7664 if (mips_macro_warning
.delay_slot_length
7665 != mips_macro_warning
.first_insn_sizes
[0])
7666 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
7667 if (mips_macro_warning
.delay_slot_length
7668 != mips_macro_warning
.first_insn_sizes
[1])
7669 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
7672 /* Check instruction count requirements. */
7673 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
7675 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
7676 subtype
|= RELAX_SECOND_LONGER
;
7677 if (mips_opts
.warn_about_macros
)
7678 subtype
|= RELAX_NOMACRO
;
7679 if (mips_macro_warning
.delay_slot_p
)
7680 subtype
|= RELAX_DELAY_SLOT
;
7683 /* If both alternatives fail to fill a delay slot correctly,
7684 emit the warning now. */
7685 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
7686 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
7691 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
7692 | RELAX_DELAY_SLOT_SIZE_FIRST
7693 | RELAX_DELAY_SLOT_SIZE_SECOND
);
7694 msg
= macro_warning (s
);
7696 as_warn ("%s", msg
);
7700 /* If both implementations are longer than 1 instruction, then emit the
7702 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
7707 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
7708 msg
= macro_warning (s
);
7710 as_warn ("%s", msg
);
7714 /* If any flags still set, then one implementation might need a warning
7715 and the other either will need one of a different kind or none at all.
7716 Pass any remaining flags over to relaxation. */
7717 if (mips_macro_warning
.first_frag
!= NULL
)
7718 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
7721 /* Instruction operand formats used in macros that vary between
7722 standard MIPS and microMIPS code. */
7724 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
7725 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
7726 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
7727 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
7728 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
7729 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
7730 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
7731 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
7733 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7734 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7735 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7736 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7737 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7738 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7739 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7740 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7742 /* Read a macro's relocation codes from *ARGS and store them in *R.
7743 The first argument in *ARGS will be either the code for a single
7744 relocation or -1 followed by the three codes that make up a
7745 composite relocation. */
7748 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
7752 next
= va_arg (*args
, int);
7754 r
[0] = (bfd_reloc_code_real_type
) next
;
7757 for (i
= 0; i
< 3; i
++)
7758 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
7759 /* This function is only used for 16-bit relocation fields.
7760 To make the macro code simpler, treat an unrelocated value
7761 in the same way as BFD_RELOC_LO16. */
7762 if (r
[0] == BFD_RELOC_UNUSED
)
7763 r
[0] = BFD_RELOC_LO16
;
7767 /* Build an instruction created by a macro expansion. This is passed
7768 a pointer to the count of instructions created so far, an
7769 expression, the name of the instruction to build, an operand format
7770 string, and corresponding arguments. */
7773 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
7775 const struct mips_opcode
*mo
= NULL
;
7776 bfd_reloc_code_real_type r
[3];
7777 const struct mips_opcode
*amo
;
7778 const struct mips_operand
*operand
;
7779 struct hash_control
*hash
;
7780 struct mips_cl_insn insn
;
7784 va_start (args
, fmt
);
7786 if (mips_opts
.mips16
)
7788 mips16_macro_build (ep
, name
, fmt
, &args
);
7793 r
[0] = BFD_RELOC_UNUSED
;
7794 r
[1] = BFD_RELOC_UNUSED
;
7795 r
[2] = BFD_RELOC_UNUSED
;
7796 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
7797 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
7799 gas_assert (strcmp (name
, amo
->name
) == 0);
7803 /* Search until we get a match for NAME. It is assumed here that
7804 macros will never generate MDMX, MIPS-3D, or MT instructions.
7805 We try to match an instruction that fulfils the branch delay
7806 slot instruction length requirement (if any) of the previous
7807 instruction. While doing this we record the first instruction
7808 seen that matches all the other conditions and use it anyway
7809 if the requirement cannot be met; we will issue an appropriate
7810 warning later on. */
7811 if (strcmp (fmt
, amo
->args
) == 0
7812 && amo
->pinfo
!= INSN_MACRO
7813 && is_opcode_valid (amo
)
7814 && is_size_valid (amo
))
7816 if (is_delay_slot_valid (amo
))
7826 gas_assert (amo
->name
);
7828 while (strcmp (name
, amo
->name
) == 0);
7831 create_insn (&insn
, mo
);
7844 macro_read_relocs (&args
, r
);
7845 gas_assert (*r
== BFD_RELOC_GPREL16
7846 || *r
== BFD_RELOC_MIPS_HIGHER
7847 || *r
== BFD_RELOC_HI16_S
7848 || *r
== BFD_RELOC_LO16
7849 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
7853 macro_read_relocs (&args
, r
);
7857 macro_read_relocs (&args
, r
);
7858 gas_assert (ep
!= NULL
7859 && (ep
->X_op
== O_constant
7860 || (ep
->X_op
== O_symbol
7861 && (*r
== BFD_RELOC_MIPS_HIGHEST
7862 || *r
== BFD_RELOC_HI16_S
7863 || *r
== BFD_RELOC_HI16
7864 || *r
== BFD_RELOC_GPREL16
7865 || *r
== BFD_RELOC_MIPS_GOT_HI16
7866 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
7870 gas_assert (ep
!= NULL
);
7873 * This allows macro() to pass an immediate expression for
7874 * creating short branches without creating a symbol.
7876 * We don't allow branch relaxation for these branches, as
7877 * they should only appear in ".set nomacro" anyway.
7879 if (ep
->X_op
== O_constant
)
7881 /* For microMIPS we always use relocations for branches.
7882 So we should not resolve immediate values. */
7883 gas_assert (!mips_opts
.micromips
);
7885 if ((ep
->X_add_number
& 3) != 0)
7886 as_bad (_("branch to misaligned address (0x%lx)"),
7887 (unsigned long) ep
->X_add_number
);
7888 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
7889 as_bad (_("branch address range overflow (0x%lx)"),
7890 (unsigned long) ep
->X_add_number
);
7891 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
7895 *r
= BFD_RELOC_16_PCREL_S2
;
7899 gas_assert (ep
!= NULL
);
7900 *r
= BFD_RELOC_MIPS_JMP
;
7904 operand
= (mips_opts
.micromips
7905 ? decode_micromips_operand (fmt
)
7906 : decode_mips_operand (fmt
));
7910 uval
= va_arg (args
, int);
7911 if (operand
->type
== OP_CLO_CLZ_DEST
)
7912 uval
|= (uval
<< 5);
7913 insn_insert_operand (&insn
, operand
, uval
);
7915 if (*fmt
== '+' || *fmt
== 'm')
7921 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
7923 append_insn (&insn
, ep
, r
, TRUE
);
7927 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
7930 struct mips_opcode
*mo
;
7931 struct mips_cl_insn insn
;
7932 const struct mips_operand
*operand
;
7933 bfd_reloc_code_real_type r
[3]
7934 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
7936 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
7938 gas_assert (strcmp (name
, mo
->name
) == 0);
7940 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
7943 gas_assert (mo
->name
);
7944 gas_assert (strcmp (name
, mo
->name
) == 0);
7947 create_insn (&insn
, mo
);
7985 gas_assert (ep
!= NULL
);
7987 if (ep
->X_op
!= O_constant
)
7988 *r
= (int) BFD_RELOC_UNUSED
+ c
;
7989 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
7991 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
7993 *r
= BFD_RELOC_UNUSED
;
7999 operand
= decode_mips16_operand (c
, FALSE
);
8003 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
8008 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
8010 append_insn (&insn
, ep
, r
, TRUE
);
8014 * Generate a "jalr" instruction with a relocation hint to the called
8015 * function. This occurs in NewABI PIC code.
8018 macro_build_jalr (expressionS
*ep
, int cprestore
)
8020 static const bfd_reloc_code_real_type jalr_relocs
[2]
8021 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
8022 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
8026 if (MIPS_JALR_HINT_P (ep
))
8031 if (mips_opts
.micromips
)
8033 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
8034 ? "jalr" : "jalrs");
8035 if (MIPS_JALR_HINT_P (ep
)
8037 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8038 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
8040 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
8043 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
8044 if (MIPS_JALR_HINT_P (ep
))
8045 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
8049 * Generate a "lui" instruction.
8052 macro_build_lui (expressionS
*ep
, int regnum
)
8054 gas_assert (! mips_opts
.mips16
);
8056 if (ep
->X_op
!= O_constant
)
8058 gas_assert (ep
->X_op
== O_symbol
);
8059 /* _gp_disp is a special case, used from s_cpload.
8060 __gnu_local_gp is used if mips_no_shared. */
8061 gas_assert (mips_pic
== NO_PIC
8063 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
8064 || (! mips_in_shared
8065 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
8066 "__gnu_local_gp") == 0));
8069 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
8072 /* Generate a sequence of instructions to do a load or store from a constant
8073 offset off of a base register (breg) into/from a target register (treg),
8074 using AT if necessary. */
8076 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
8077 int treg
, int breg
, int dbl
)
8079 gas_assert (ep
->X_op
== O_constant
);
8081 /* Sign-extending 32-bit constants makes their handling easier. */
8083 normalize_constant_expr (ep
);
8085 /* Right now, this routine can only handle signed 32-bit constants. */
8086 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
8087 as_warn (_("operand overflow"));
8089 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
8091 /* Signed 16-bit offset will fit in the op. Easy! */
8092 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8096 /* 32-bit offset, need multiple instructions and AT, like:
8097 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
8098 addu $tempreg,$tempreg,$breg
8099 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
8100 to handle the complete offset. */
8101 macro_build_lui (ep
, AT
);
8102 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8103 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8106 as_bad (_("Macro used $at after \".set noat\""));
8111 * Generates code to set the $at register to true (one)
8112 * if reg is less than the immediate expression.
8115 set_at (int reg
, int unsignedp
)
8117 if (imm_expr
.X_op
== O_constant
8118 && imm_expr
.X_add_number
>= -0x8000
8119 && imm_expr
.X_add_number
< 0x8000)
8120 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
8121 AT
, reg
, BFD_RELOC_LO16
);
8124 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
8125 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
8129 /* Count the leading zeroes by performing a binary chop. This is a
8130 bulky bit of source, but performance is a LOT better for the
8131 majority of values than a simple loop to count the bits:
8132 for (lcnt = 0; (lcnt < 32); lcnt++)
8133 if ((v) & (1 << (31 - lcnt)))
8135 However it is not code size friendly, and the gain will drop a bit
8136 on certain cached systems.
8138 #define COUNT_TOP_ZEROES(v) \
8139 (((v) & ~0xffff) == 0 \
8140 ? ((v) & ~0xff) == 0 \
8141 ? ((v) & ~0xf) == 0 \
8142 ? ((v) & ~0x3) == 0 \
8143 ? ((v) & ~0x1) == 0 \
8148 : ((v) & ~0x7) == 0 \
8151 : ((v) & ~0x3f) == 0 \
8152 ? ((v) & ~0x1f) == 0 \
8155 : ((v) & ~0x7f) == 0 \
8158 : ((v) & ~0xfff) == 0 \
8159 ? ((v) & ~0x3ff) == 0 \
8160 ? ((v) & ~0x1ff) == 0 \
8163 : ((v) & ~0x7ff) == 0 \
8166 : ((v) & ~0x3fff) == 0 \
8167 ? ((v) & ~0x1fff) == 0 \
8170 : ((v) & ~0x7fff) == 0 \
8173 : ((v) & ~0xffffff) == 0 \
8174 ? ((v) & ~0xfffff) == 0 \
8175 ? ((v) & ~0x3ffff) == 0 \
8176 ? ((v) & ~0x1ffff) == 0 \
8179 : ((v) & ~0x7ffff) == 0 \
8182 : ((v) & ~0x3fffff) == 0 \
8183 ? ((v) & ~0x1fffff) == 0 \
8186 : ((v) & ~0x7fffff) == 0 \
8189 : ((v) & ~0xfffffff) == 0 \
8190 ? ((v) & ~0x3ffffff) == 0 \
8191 ? ((v) & ~0x1ffffff) == 0 \
8194 : ((v) & ~0x7ffffff) == 0 \
8197 : ((v) & ~0x3fffffff) == 0 \
8198 ? ((v) & ~0x1fffffff) == 0 \
8201 : ((v) & ~0x7fffffff) == 0 \
8206 * This routine generates the least number of instructions necessary to load
8207 * an absolute expression value into a register.
8210 load_register (int reg
, expressionS
*ep
, int dbl
)
8213 expressionS hi32
, lo32
;
8215 if (ep
->X_op
!= O_big
)
8217 gas_assert (ep
->X_op
== O_constant
);
8219 /* Sign-extending 32-bit constants makes their handling easier. */
8221 normalize_constant_expr (ep
);
8223 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
8225 /* We can handle 16 bit signed values with an addiu to
8226 $zero. No need to ever use daddiu here, since $zero and
8227 the result are always correct in 32 bit mode. */
8228 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8231 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
8233 /* We can handle 16 bit unsigned values with an ori to
8235 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8238 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
8240 /* 32 bit values require an lui. */
8241 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8242 if ((ep
->X_add_number
& 0xffff) != 0)
8243 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8248 /* The value is larger than 32 bits. */
8250 if (!dbl
|| HAVE_32BIT_GPRS
)
8254 sprintf_vma (value
, ep
->X_add_number
);
8255 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8256 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8260 if (ep
->X_op
!= O_big
)
8263 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8264 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
8265 hi32
.X_add_number
&= 0xffffffff;
8267 lo32
.X_add_number
&= 0xffffffff;
8271 gas_assert (ep
->X_add_number
> 2);
8272 if (ep
->X_add_number
== 3)
8273 generic_bignum
[3] = 0;
8274 else if (ep
->X_add_number
> 4)
8275 as_bad (_("Number larger than 64 bits"));
8276 lo32
.X_op
= O_constant
;
8277 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
8278 hi32
.X_op
= O_constant
;
8279 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
8282 if (hi32
.X_add_number
== 0)
8287 unsigned long hi
, lo
;
8289 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
8291 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
8293 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8296 if (lo32
.X_add_number
& 0x80000000)
8298 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8299 if (lo32
.X_add_number
& 0xffff)
8300 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
8305 /* Check for 16bit shifted constant. We know that hi32 is
8306 non-zero, so start the mask on the first bit of the hi32
8311 unsigned long himask
, lomask
;
8315 himask
= 0xffff >> (32 - shift
);
8316 lomask
= (0xffff << shift
) & 0xffffffff;
8320 himask
= 0xffff << (shift
- 32);
8323 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
8324 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
8328 tmp
.X_op
= O_constant
;
8330 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
8331 | (lo32
.X_add_number
>> shift
));
8333 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
8334 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
8335 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8336 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8341 while (shift
<= (64 - 16));
8343 /* Find the bit number of the lowest one bit, and store the
8344 shifted value in hi/lo. */
8345 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
8346 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
8350 while ((lo
& 1) == 0)
8355 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
8361 while ((hi
& 1) == 0)
8370 /* Optimize if the shifted value is a (power of 2) - 1. */
8371 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
8372 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
8374 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
8379 /* This instruction will set the register to be all
8381 tmp
.X_op
= O_constant
;
8382 tmp
.X_add_number
= (offsetT
) -1;
8383 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
8387 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
8388 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
8390 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
8391 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
8396 /* Sign extend hi32 before calling load_register, because we can
8397 generally get better code when we load a sign extended value. */
8398 if ((hi32
.X_add_number
& 0x80000000) != 0)
8399 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
8400 load_register (reg
, &hi32
, 0);
8403 if ((lo32
.X_add_number
& 0xffff0000) == 0)
8407 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
8415 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
8417 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
8418 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
8424 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
8428 mid16
.X_add_number
>>= 16;
8429 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8430 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8433 if ((lo32
.X_add_number
& 0xffff) != 0)
8434 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
8438 load_delay_nop (void)
8440 if (!gpr_interlocks
)
8441 macro_build (NULL
, "nop", "");
8444 /* Load an address into a register. */
8447 load_address (int reg
, expressionS
*ep
, int *used_at
)
8449 if (ep
->X_op
!= O_constant
8450 && ep
->X_op
!= O_symbol
)
8452 as_bad (_("expression too complex"));
8453 ep
->X_op
= O_constant
;
8456 if (ep
->X_op
== O_constant
)
8458 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
8462 if (mips_pic
== NO_PIC
)
8464 /* If this is a reference to a GP relative symbol, we want
8465 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8467 lui $reg,<sym> (BFD_RELOC_HI16_S)
8468 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8469 If we have an addend, we always use the latter form.
8471 With 64bit address space and a usable $at we want
8472 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8473 lui $at,<sym> (BFD_RELOC_HI16_S)
8474 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8475 daddiu $at,<sym> (BFD_RELOC_LO16)
8479 If $at is already in use, we use a path which is suboptimal
8480 on superscalar processors.
8481 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8482 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8484 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8486 daddiu $reg,<sym> (BFD_RELOC_LO16)
8488 For GP relative symbols in 64bit address space we can use
8489 the same sequence as in 32bit address space. */
8490 if (HAVE_64BIT_SYMBOLS
)
8492 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8493 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8495 relax_start (ep
->X_add_symbol
);
8496 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8497 mips_gp_register
, BFD_RELOC_GPREL16
);
8501 if (*used_at
== 0 && mips_opts
.at
)
8503 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8504 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
8505 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8506 BFD_RELOC_MIPS_HIGHER
);
8507 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
8508 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
8509 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
8514 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
8515 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
8516 BFD_RELOC_MIPS_HIGHER
);
8517 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8518 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
8519 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
8520 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
8523 if (mips_relax
.sequence
)
8528 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
8529 && !nopic_need_relax (ep
->X_add_symbol
, 1))
8531 relax_start (ep
->X_add_symbol
);
8532 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
8533 mips_gp_register
, BFD_RELOC_GPREL16
);
8536 macro_build_lui (ep
, reg
);
8537 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
8538 reg
, reg
, BFD_RELOC_LO16
);
8539 if (mips_relax
.sequence
)
8543 else if (!mips_big_got
)
8547 /* If this is a reference to an external symbol, we want
8548 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8550 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8552 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8553 If there is a constant, it must be added in after.
8555 If we have NewABI, we want
8556 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8557 unless we're referencing a global symbol with a non-zero
8558 offset, in which case cst must be added separately. */
8561 if (ep
->X_add_number
)
8563 ex
.X_add_number
= ep
->X_add_number
;
8564 ep
->X_add_number
= 0;
8565 relax_start (ep
->X_add_symbol
);
8566 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8567 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8568 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8569 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8570 ex
.X_op
= O_constant
;
8571 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8572 reg
, reg
, BFD_RELOC_LO16
);
8573 ep
->X_add_number
= ex
.X_add_number
;
8576 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8577 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
8578 if (mips_relax
.sequence
)
8583 ex
.X_add_number
= ep
->X_add_number
;
8584 ep
->X_add_number
= 0;
8585 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8586 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8588 relax_start (ep
->X_add_symbol
);
8590 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8594 if (ex
.X_add_number
!= 0)
8596 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8597 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8598 ex
.X_op
= O_constant
;
8599 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
8600 reg
, reg
, BFD_RELOC_LO16
);
8604 else if (mips_big_got
)
8608 /* This is the large GOT case. If this is a reference to an
8609 external symbol, we want
8610 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8612 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8614 Otherwise, for a reference to a local symbol in old ABI, we want
8615 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8617 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8618 If there is a constant, it must be added in after.
8620 In the NewABI, for local symbols, with or without offsets, we want:
8621 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8622 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8626 ex
.X_add_number
= ep
->X_add_number
;
8627 ep
->X_add_number
= 0;
8628 relax_start (ep
->X_add_symbol
);
8629 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8631 reg
, reg
, mips_gp_register
);
8632 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8633 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8634 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8635 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8636 else if (ex
.X_add_number
)
8638 ex
.X_op
= O_constant
;
8639 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8643 ep
->X_add_number
= ex
.X_add_number
;
8645 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8646 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8647 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8648 BFD_RELOC_MIPS_GOT_OFST
);
8653 ex
.X_add_number
= ep
->X_add_number
;
8654 ep
->X_add_number
= 0;
8655 relax_start (ep
->X_add_symbol
);
8656 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
8657 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8658 reg
, reg
, mips_gp_register
);
8659 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
8660 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
8662 if (reg_needs_delay (mips_gp_register
))
8664 /* We need a nop before loading from $gp. This special
8665 check is required because the lui which starts the main
8666 instruction stream does not refer to $gp, and so will not
8667 insert the nop which may be required. */
8668 macro_build (NULL
, "nop", "");
8670 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
8671 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8673 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8677 if (ex
.X_add_number
!= 0)
8679 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
8680 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8681 ex
.X_op
= O_constant
;
8682 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
8690 if (!mips_opts
.at
&& *used_at
== 1)
8691 as_bad (_("Macro used $at after \".set noat\""));
8694 /* Move the contents of register SOURCE into register DEST. */
8697 move_register (int dest
, int source
)
8699 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8700 instruction specifically requires a 32-bit one. */
8701 if (mips_opts
.micromips
8702 && !mips_opts
.insn32
8703 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8704 macro_build (NULL
, "move", "mp,mj", dest
, source
);
8706 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
8710 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8711 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8712 The two alternatives are:
8714 Global symbol Local sybmol
8715 ------------- ------------
8716 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8718 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8720 load_got_offset emits the first instruction and add_got_offset
8721 emits the second for a 16-bit offset or add_got_offset_hilo emits
8722 a sequence to add a 32-bit offset using a scratch register. */
8725 load_got_offset (int dest
, expressionS
*local
)
8730 global
.X_add_number
= 0;
8732 relax_start (local
->X_add_symbol
);
8733 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8734 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8736 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
8737 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
8742 add_got_offset (int dest
, expressionS
*local
)
8746 global
.X_op
= O_constant
;
8747 global
.X_op_symbol
= NULL
;
8748 global
.X_add_symbol
= NULL
;
8749 global
.X_add_number
= local
->X_add_number
;
8751 relax_start (local
->X_add_symbol
);
8752 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
8753 dest
, dest
, BFD_RELOC_LO16
);
8755 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
8760 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
8763 int hold_mips_optimize
;
8765 global
.X_op
= O_constant
;
8766 global
.X_op_symbol
= NULL
;
8767 global
.X_add_symbol
= NULL
;
8768 global
.X_add_number
= local
->X_add_number
;
8770 relax_start (local
->X_add_symbol
);
8771 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
8773 /* Set mips_optimize around the lui instruction to avoid
8774 inserting an unnecessary nop after the lw. */
8775 hold_mips_optimize
= mips_optimize
;
8777 macro_build_lui (&global
, tmp
);
8778 mips_optimize
= hold_mips_optimize
;
8779 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
8782 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
8785 /* Emit a sequence of instructions to emulate a branch likely operation.
8786 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8787 is its complementing branch with the original condition negated.
8788 CALL is set if the original branch specified the link operation.
8789 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8791 Code like this is produced in the noreorder mode:
8796 delay slot (executed only if branch taken)
8804 delay slot (executed only if branch taken)
8807 In the reorder mode the delay slot would be filled with a nop anyway,
8808 so code produced is simply:
8813 This function is used when producing code for the microMIPS ASE that
8814 does not implement branch likely instructions in hardware. */
8817 macro_build_branch_likely (const char *br
, const char *brneg
,
8818 int call
, expressionS
*ep
, const char *fmt
,
8819 unsigned int sreg
, unsigned int treg
)
8821 int noreorder
= mips_opts
.noreorder
;
8824 gas_assert (mips_opts
.micromips
);
8828 micromips_label_expr (&expr1
);
8829 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
8830 macro_build (NULL
, "nop", "");
8831 macro_build (ep
, call
? "bal" : "b", "p");
8833 /* Set to true so that append_insn adds a label. */
8834 emit_branch_likely_macro
= TRUE
;
8838 macro_build (ep
, br
, fmt
, sreg
, treg
);
8839 macro_build (NULL
, "nop", "");
8844 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8845 the condition code tested. EP specifies the branch target. */
8848 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
8875 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
8878 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8879 the register tested. EP specifies the branch target. */
8882 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
8884 const char *brneg
= NULL
;
8894 br
= mips_opts
.micromips
? "bgez" : "bgezl";
8898 gas_assert (mips_opts
.micromips
);
8899 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
8907 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
8914 br
= mips_opts
.micromips
? "blez" : "blezl";
8921 br
= mips_opts
.micromips
? "bltz" : "bltzl";
8925 gas_assert (mips_opts
.micromips
);
8926 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
8933 if (mips_opts
.micromips
&& brneg
)
8934 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
8936 macro_build (ep
, br
, "s,p", sreg
);
8939 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8940 TREG as the registers tested. EP specifies the branch target. */
8943 macro_build_branch_rsrt (int type
, expressionS
*ep
,
8944 unsigned int sreg
, unsigned int treg
)
8946 const char *brneg
= NULL
;
8958 br
= mips_opts
.micromips
? "beq" : "beql";
8967 br
= mips_opts
.micromips
? "bne" : "bnel";
8973 if (mips_opts
.micromips
&& brneg
)
8974 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
8976 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
8979 /* Return the high part that should be loaded in order to make the low
8980 part of VALUE accessible using an offset of OFFBITS bits. */
8983 offset_high_part (offsetT value
, unsigned int offbits
)
8990 bias
= 1 << (offbits
- 1);
8991 low_mask
= bias
* 2 - 1;
8992 return (value
+ bias
) & ~low_mask
;
8995 /* Return true if the value stored in offset_expr and offset_reloc
8996 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8997 amount that the caller wants to add without inducing overflow
8998 and ALIGN is the known alignment of the value in bytes. */
9001 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
9005 /* Accept any relocation operator if overflow isn't a concern. */
9006 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
9009 /* These relocations are guaranteed not to overflow in correct links. */
9010 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
9011 || gprel16_reloc_p (*offset_reloc
))
9014 if (offset_expr
.X_op
== O_constant
9015 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
9016 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
9023 * This routine implements the seemingly endless macro or synthesized
9024 * instructions and addressing modes in the mips assembly language. Many
9025 * of these macros are simple and are similar to each other. These could
9026 * probably be handled by some kind of table or grammar approach instead of
9027 * this verbose method. Others are not simple macros but are more like
9028 * optimizing code generation.
9029 * One interesting optimization is when several store macros appear
9030 * consecutively that would load AT with the upper half of the same address.
9031 * The ensuing load upper instructions are ommited. This implies some kind
9032 * of global optimization. We currently only optimize within a single macro.
9033 * For many of the load and store macros if the address is specified as a
9034 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
9035 * first load register 'at' with zero and use it as the base register. The
9036 * mips assembler simply uses register $zero. Just one tiny optimization
9040 macro (struct mips_cl_insn
*ip
, char *str
)
9042 const struct mips_operand_array
*operands
;
9043 unsigned int breg
, i
;
9044 unsigned int tempreg
;
9047 expressionS label_expr
;
9062 bfd_boolean large_offset
;
9064 int hold_mips_optimize
;
9066 unsigned int op
[MAX_OPERANDS
];
9068 gas_assert (! mips_opts
.mips16
);
9070 operands
= insn_operands (ip
);
9071 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9072 if (operands
->operand
[i
])
9073 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
9077 mask
= ip
->insn_mo
->mask
;
9079 label_expr
.X_op
= O_constant
;
9080 label_expr
.X_op_symbol
= NULL
;
9081 label_expr
.X_add_symbol
= NULL
;
9082 label_expr
.X_add_number
= 0;
9084 expr1
.X_op
= O_constant
;
9085 expr1
.X_op_symbol
= NULL
;
9086 expr1
.X_add_symbol
= NULL
;
9087 expr1
.X_add_number
= 1;
9103 if (mips_opts
.micromips
)
9104 micromips_label_expr (&label_expr
);
9106 label_expr
.X_add_number
= 8;
9107 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
9109 macro_build (NULL
, "nop", "");
9111 move_register (op
[0], op
[1]);
9112 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
9113 if (mips_opts
.micromips
)
9114 micromips_add_label ();
9131 if (!mips_opts
.micromips
)
9133 if (imm_expr
.X_op
== O_constant
9134 && imm_expr
.X_add_number
>= -0x200
9135 && imm_expr
.X_add_number
< 0x200)
9137 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], imm_expr
.X_add_number
);
9146 if (imm_expr
.X_op
== O_constant
9147 && imm_expr
.X_add_number
>= -0x8000
9148 && imm_expr
.X_add_number
< 0x8000)
9150 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
9155 load_register (AT
, &imm_expr
, dbl
);
9156 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9175 if (imm_expr
.X_op
== O_constant
9176 && imm_expr
.X_add_number
>= 0
9177 && imm_expr
.X_add_number
< 0x10000)
9179 if (mask
!= M_NOR_I
)
9180 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
9183 macro_build (&imm_expr
, "ori", "t,r,i",
9184 op
[0], op
[1], BFD_RELOC_LO16
);
9185 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
9191 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
9192 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
9196 switch (imm_expr
.X_add_number
)
9199 macro_build (NULL
, "nop", "");
9202 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
9206 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
9207 (int) imm_expr
.X_add_number
);
9210 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9211 (unsigned long) imm_expr
.X_add_number
);
9220 gas_assert (mips_opts
.micromips
);
9221 macro_build_branch_ccl (mask
, &offset_expr
,
9222 EXTRACT_OPERAND (1, BCC
, *ip
));
9229 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9235 load_register (op
[1], &imm_expr
, HAVE_64BIT_GPRS
);
9240 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
9247 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
9248 else if (op
[0] == 0)
9249 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
9253 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9254 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9255 &offset_expr
, AT
, ZERO
);
9265 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
9271 /* Check for > max integer. */
9272 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
9275 /* Result is always false. */
9277 macro_build (NULL
, "nop", "");
9279 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
9282 if (imm_expr
.X_op
!= O_constant
)
9283 as_bad (_("Unsupported large constant"));
9284 ++imm_expr
.X_add_number
;
9288 if (mask
== M_BGEL_I
)
9290 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9292 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
9293 &offset_expr
, op
[0]);
9296 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9298 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
9299 &offset_expr
, op
[0]);
9302 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
9305 /* result is always true */
9306 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
9307 macro_build (&offset_expr
, "b", "p");
9312 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9313 &offset_expr
, AT
, ZERO
);
9321 else if (op
[0] == 0)
9322 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9323 &offset_expr
, ZERO
, op
[1]);
9327 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9328 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9329 &offset_expr
, AT
, ZERO
);
9338 && imm_expr
.X_op
== O_constant
9339 && imm_expr
.X_add_number
== -1))
9341 if (imm_expr
.X_op
!= O_constant
)
9342 as_bad (_("Unsupported large constant"));
9343 ++imm_expr
.X_add_number
;
9347 if (mask
== M_BGEUL_I
)
9349 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9351 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9352 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9353 &offset_expr
, op
[0], ZERO
);
9358 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9359 &offset_expr
, AT
, ZERO
);
9367 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
9368 else if (op
[0] == 0)
9369 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
9373 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9374 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9375 &offset_expr
, AT
, ZERO
);
9383 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9384 &offset_expr
, op
[0], ZERO
);
9385 else if (op
[0] == 0)
9390 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9391 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9392 &offset_expr
, AT
, ZERO
);
9400 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9401 else if (op
[0] == 0)
9402 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
9406 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
9407 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9408 &offset_expr
, AT
, ZERO
);
9415 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
9417 if (imm_expr
.X_op
!= O_constant
)
9418 as_bad (_("Unsupported large constant"));
9419 ++imm_expr
.X_add_number
;
9423 if (mask
== M_BLTL_I
)
9425 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9426 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9427 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9428 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
9433 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9434 &offset_expr
, AT
, ZERO
);
9442 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9443 &offset_expr
, op
[0], ZERO
);
9444 else if (op
[0] == 0)
9449 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
9450 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9451 &offset_expr
, AT
, ZERO
);
9460 && imm_expr
.X_op
== O_constant
9461 && imm_expr
.X_add_number
== -1))
9463 if (imm_expr
.X_op
!= O_constant
)
9464 as_bad (_("Unsupported large constant"));
9465 ++imm_expr
.X_add_number
;
9469 if (mask
== M_BLTUL_I
)
9471 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9473 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9474 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
9475 &offset_expr
, op
[0], ZERO
);
9480 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9481 &offset_expr
, AT
, ZERO
);
9489 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
9490 else if (op
[0] == 0)
9491 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
9495 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
9496 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9497 &offset_expr
, AT
, ZERO
);
9506 else if (op
[0] == 0)
9507 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9508 &offset_expr
, ZERO
, op
[1]);
9512 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
9513 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
9514 &offset_expr
, AT
, ZERO
);
9520 /* Use unsigned arithmetic. */
9524 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
9526 as_bad (_("Unsupported large constant"));
9531 pos
= imm_expr
.X_add_number
;
9532 size
= imm2_expr
.X_add_number
;
9537 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
9540 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
9542 report_bad_field (pos
, size
);
9546 if (size
<= 32 && pos
< 32)
9551 else if (size
<= 32)
9561 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
9568 /* Use unsigned arithmetic. */
9572 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
9574 as_bad (_("Unsupported large constant"));
9579 pos
= imm_expr
.X_add_number
;
9580 size
= imm2_expr
.X_add_number
;
9585 report_bad_range (ip
, 3, pos
, 0, 63, FALSE
);
9588 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
9590 report_bad_field (pos
, size
);
9594 if (pos
< 32 && (pos
+ size
- 1) < 32)
9609 macro_build ((expressionS
*) NULL
, s
, fmt
, op
[0], op
[1], (int) pos
,
9610 (int) (pos
+ size
- 1));
9626 as_warn (_("Divide by zero."));
9628 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9630 macro_build (NULL
, "break", BRK_FMT
, 7);
9637 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9638 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9642 if (mips_opts
.micromips
)
9643 micromips_label_expr (&label_expr
);
9645 label_expr
.X_add_number
= 8;
9646 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9647 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
9648 macro_build (NULL
, "break", BRK_FMT
, 7);
9649 if (mips_opts
.micromips
)
9650 micromips_add_label ();
9652 expr1
.X_add_number
= -1;
9654 load_register (AT
, &expr1
, dbl
);
9655 if (mips_opts
.micromips
)
9656 micromips_label_expr (&label_expr
);
9658 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
9659 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
9662 expr1
.X_add_number
= 1;
9663 load_register (AT
, &expr1
, dbl
);
9664 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
9668 expr1
.X_add_number
= 0x80000000;
9669 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
9673 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
9674 /* We want to close the noreorder block as soon as possible, so
9675 that later insns are available for delay slot filling. */
9680 if (mips_opts
.micromips
)
9681 micromips_label_expr (&label_expr
);
9683 label_expr
.X_add_number
= 8;
9684 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
9685 macro_build (NULL
, "nop", "");
9687 /* We want to close the noreorder block as soon as possible, so
9688 that later insns are available for delay slot filling. */
9691 macro_build (NULL
, "break", BRK_FMT
, 6);
9693 if (mips_opts
.micromips
)
9694 micromips_add_label ();
9695 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
9734 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
9736 as_warn (_("Divide by zero."));
9738 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
9740 macro_build (NULL
, "break", BRK_FMT
, 7);
9743 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
9745 if (strcmp (s2
, "mflo") == 0)
9746 move_register (op
[0], op
[1]);
9748 move_register (op
[0], ZERO
);
9751 if (imm_expr
.X_op
== O_constant
9752 && imm_expr
.X_add_number
== -1
9753 && s
[strlen (s
) - 1] != 'u')
9755 if (strcmp (s2
, "mflo") == 0)
9756 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
9758 move_register (op
[0], ZERO
);
9763 load_register (AT
, &imm_expr
, dbl
);
9764 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
9765 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9787 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
9788 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9789 /* We want to close the noreorder block as soon as possible, so
9790 that later insns are available for delay slot filling. */
9795 if (mips_opts
.micromips
)
9796 micromips_label_expr (&label_expr
);
9798 label_expr
.X_add_number
= 8;
9799 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
9800 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
9802 /* We want to close the noreorder block as soon as possible, so
9803 that later insns are available for delay slot filling. */
9805 macro_build (NULL
, "break", BRK_FMT
, 7);
9806 if (mips_opts
.micromips
)
9807 micromips_add_label ();
9809 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
9821 /* Load the address of a symbol into a register. If breg is not
9822 zero, we then add a base register to it. */
9825 if (dbl
&& HAVE_32BIT_GPRS
)
9826 as_warn (_("dla used to load 32-bit register"));
9828 if (!dbl
&& HAVE_64BIT_OBJECTS
)
9829 as_warn (_("la used to load 64-bit address"));
9831 if (small_offset_p (0, align
, 16))
9833 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
9834 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
9838 if (mips_opts
.at
&& (op
[0] == breg
))
9846 if (offset_expr
.X_op
!= O_symbol
9847 && offset_expr
.X_op
!= O_constant
)
9849 as_bad (_("Expression too complex"));
9850 offset_expr
.X_op
= O_constant
;
9853 if (offset_expr
.X_op
== O_constant
)
9854 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
9855 else if (mips_pic
== NO_PIC
)
9857 /* If this is a reference to a GP relative symbol, we want
9858 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9860 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9861 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9862 If we have a constant, we need two instructions anyhow,
9863 so we may as well always use the latter form.
9865 With 64bit address space and a usable $at we want
9866 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9867 lui $at,<sym> (BFD_RELOC_HI16_S)
9868 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9869 daddiu $at,<sym> (BFD_RELOC_LO16)
9871 daddu $tempreg,$tempreg,$at
9873 If $at is already in use, we use a path which is suboptimal
9874 on superscalar processors.
9875 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9876 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9878 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9880 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9882 For GP relative symbols in 64bit address space we can use
9883 the same sequence as in 32bit address space. */
9884 if (HAVE_64BIT_SYMBOLS
)
9886 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9887 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9889 relax_start (offset_expr
.X_add_symbol
);
9890 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9891 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9895 if (used_at
== 0 && mips_opts
.at
)
9897 macro_build (&offset_expr
, "lui", LUI_FMT
,
9898 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9899 macro_build (&offset_expr
, "lui", LUI_FMT
,
9900 AT
, BFD_RELOC_HI16_S
);
9901 macro_build (&offset_expr
, "daddiu", "t,r,j",
9902 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9903 macro_build (&offset_expr
, "daddiu", "t,r,j",
9904 AT
, AT
, BFD_RELOC_LO16
);
9905 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9906 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9911 macro_build (&offset_expr
, "lui", LUI_FMT
,
9912 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
9913 macro_build (&offset_expr
, "daddiu", "t,r,j",
9914 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
9915 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9916 macro_build (&offset_expr
, "daddiu", "t,r,j",
9917 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
9918 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9919 macro_build (&offset_expr
, "daddiu", "t,r,j",
9920 tempreg
, tempreg
, BFD_RELOC_LO16
);
9923 if (mips_relax
.sequence
)
9928 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9929 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9931 relax_start (offset_expr
.X_add_symbol
);
9932 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9933 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
9936 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9937 as_bad (_("Offset too large"));
9938 macro_build_lui (&offset_expr
, tempreg
);
9939 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
9940 tempreg
, tempreg
, BFD_RELOC_LO16
);
9941 if (mips_relax
.sequence
)
9945 else if (!mips_big_got
&& !HAVE_NEWABI
)
9947 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9949 /* If this is a reference to an external symbol, and there
9950 is no constant, we want
9951 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9952 or for lca or if tempreg is PIC_CALL_REG
9953 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9954 For a local symbol, we want
9955 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9957 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9959 If we have a small constant, and this is a reference to
9960 an external symbol, we want
9961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9963 addiu $tempreg,$tempreg,<constant>
9964 For a local symbol, we want the same instruction
9965 sequence, but we output a BFD_RELOC_LO16 reloc on the
9968 If we have a large constant, and this is a reference to
9969 an external symbol, we want
9970 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9971 lui $at,<hiconstant>
9972 addiu $at,$at,<loconstant>
9973 addu $tempreg,$tempreg,$at
9974 For a local symbol, we want the same instruction
9975 sequence, but we output a BFD_RELOC_LO16 reloc on the
9979 if (offset_expr
.X_add_number
== 0)
9981 if (mips_pic
== SVR4_PIC
9983 && (call
|| tempreg
== PIC_CALL_REG
))
9984 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
9986 relax_start (offset_expr
.X_add_symbol
);
9987 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9988 lw_reloc_type
, mips_gp_register
);
9991 /* We're going to put in an addu instruction using
9992 tempreg, so we may as well insert the nop right
9997 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9998 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
10000 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10001 tempreg
, tempreg
, BFD_RELOC_LO16
);
10003 /* FIXME: If breg == 0, and the next instruction uses
10004 $tempreg, then if this variant case is used an extra
10005 nop will be generated. */
10007 else if (offset_expr
.X_add_number
>= -0x8000
10008 && offset_expr
.X_add_number
< 0x8000)
10010 load_got_offset (tempreg
, &offset_expr
);
10012 add_got_offset (tempreg
, &offset_expr
);
10016 expr1
.X_add_number
= offset_expr
.X_add_number
;
10017 offset_expr
.X_add_number
=
10018 SEXT_16BIT (offset_expr
.X_add_number
);
10019 load_got_offset (tempreg
, &offset_expr
);
10020 offset_expr
.X_add_number
= expr1
.X_add_number
;
10021 /* If we are going to add in a base register, and the
10022 target register and the base register are the same,
10023 then we are using AT as a temporary register. Since
10024 we want to load the constant into AT, we add our
10025 current AT (from the global offset table) and the
10026 register into the register now, and pretend we were
10027 not using a base register. */
10031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10036 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
10040 else if (!mips_big_got
&& HAVE_NEWABI
)
10042 int add_breg_early
= 0;
10044 /* If this is a reference to an external, and there is no
10045 constant, or local symbol (*), with or without a
10047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10048 or for lca or if tempreg is PIC_CALL_REG
10049 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10051 If we have a small constant, and this is a reference to
10052 an external symbol, we want
10053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10054 addiu $tempreg,$tempreg,<constant>
10056 If we have a large constant, and this is a reference to
10057 an external symbol, we want
10058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
10059 lui $at,<hiconstant>
10060 addiu $at,$at,<loconstant>
10061 addu $tempreg,$tempreg,$at
10063 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
10064 local symbols, even though it introduces an additional
10067 if (offset_expr
.X_add_number
)
10069 expr1
.X_add_number
= offset_expr
.X_add_number
;
10070 offset_expr
.X_add_number
= 0;
10072 relax_start (offset_expr
.X_add_symbol
);
10073 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10074 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10076 if (expr1
.X_add_number
>= -0x8000
10077 && expr1
.X_add_number
< 0x8000)
10079 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10080 tempreg
, tempreg
, BFD_RELOC_LO16
);
10082 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10086 /* If we are going to add in a base register, and the
10087 target register and the base register are the same,
10088 then we are using AT as a temporary register. Since
10089 we want to load the constant into AT, we add our
10090 current AT (from the global offset table) and the
10091 register into the register now, and pretend we were
10092 not using a base register. */
10097 gas_assert (tempreg
== AT
);
10098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10101 add_breg_early
= 1;
10104 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10105 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10111 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10114 offset_expr
.X_add_number
= expr1
.X_add_number
;
10116 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10117 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10118 if (add_breg_early
)
10120 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10121 op
[0], tempreg
, breg
);
10127 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
10129 relax_start (offset_expr
.X_add_symbol
);
10130 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10131 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
10133 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10134 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10139 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10140 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
10143 else if (mips_big_got
&& !HAVE_NEWABI
)
10146 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10147 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10148 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
10150 /* This is the large GOT case. If this is a reference to an
10151 external symbol, and there is no constant, we want
10152 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10153 addu $tempreg,$tempreg,$gp
10154 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10155 or for lca or if tempreg is PIC_CALL_REG
10156 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10157 addu $tempreg,$tempreg,$gp
10158 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10159 For a local symbol, we want
10160 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10162 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10164 If we have a small constant, and this is a reference to
10165 an external symbol, we want
10166 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10167 addu $tempreg,$tempreg,$gp
10168 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10170 addiu $tempreg,$tempreg,<constant>
10171 For a local symbol, we want
10172 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10174 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10176 If we have a large constant, and this is a reference to
10177 an external symbol, we want
10178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10179 addu $tempreg,$tempreg,$gp
10180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10181 lui $at,<hiconstant>
10182 addiu $at,$at,<loconstant>
10183 addu $tempreg,$tempreg,$at
10184 For a local symbol, we want
10185 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10186 lui $at,<hiconstant>
10187 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10188 addu $tempreg,$tempreg,$at
10191 expr1
.X_add_number
= offset_expr
.X_add_number
;
10192 offset_expr
.X_add_number
= 0;
10193 relax_start (offset_expr
.X_add_symbol
);
10194 gpdelay
= reg_needs_delay (mips_gp_register
);
10195 if (expr1
.X_add_number
== 0 && breg
== 0
10196 && (call
|| tempreg
== PIC_CALL_REG
))
10198 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10199 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10201 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10202 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10203 tempreg
, tempreg
, mips_gp_register
);
10204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10205 tempreg
, lw_reloc_type
, tempreg
);
10206 if (expr1
.X_add_number
== 0)
10210 /* We're going to put in an addu instruction using
10211 tempreg, so we may as well insert the nop right
10216 else if (expr1
.X_add_number
>= -0x8000
10217 && expr1
.X_add_number
< 0x8000)
10220 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10221 tempreg
, tempreg
, BFD_RELOC_LO16
);
10227 /* If we are going to add in a base register, and the
10228 target register and the base register are the same,
10229 then we are using AT as a temporary register. Since
10230 we want to load the constant into AT, we add our
10231 current AT (from the global offset table) and the
10232 register into the register now, and pretend we were
10233 not using a base register. */
10238 gas_assert (tempreg
== AT
);
10240 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10245 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10246 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10250 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
10255 /* This is needed because this instruction uses $gp, but
10256 the first instruction on the main stream does not. */
10257 macro_build (NULL
, "nop", "");
10260 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10261 local_reloc_type
, mips_gp_register
);
10262 if (expr1
.X_add_number
>= -0x8000
10263 && expr1
.X_add_number
< 0x8000)
10266 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10267 tempreg
, tempreg
, BFD_RELOC_LO16
);
10268 /* FIXME: If add_number is 0, and there was no base
10269 register, the external symbol case ended with a load,
10270 so if the symbol turns out to not be external, and
10271 the next instruction uses tempreg, an unnecessary nop
10272 will be inserted. */
10278 /* We must add in the base register now, as in the
10279 external symbol case. */
10280 gas_assert (tempreg
== AT
);
10282 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10285 /* We set breg to 0 because we have arranged to add
10286 it in in both cases. */
10290 macro_build_lui (&expr1
, AT
);
10291 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10292 AT
, AT
, BFD_RELOC_LO16
);
10293 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10294 tempreg
, tempreg
, AT
);
10299 else if (mips_big_got
&& HAVE_NEWABI
)
10301 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
10302 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
10303 int add_breg_early
= 0;
10305 /* This is the large GOT case. If this is a reference to an
10306 external symbol, and there is no constant, we want
10307 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10308 add $tempreg,$tempreg,$gp
10309 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10310 or for lca or if tempreg is PIC_CALL_REG
10311 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10312 add $tempreg,$tempreg,$gp
10313 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10315 If we have a small constant, and this is a reference to
10316 an external symbol, we want
10317 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10318 add $tempreg,$tempreg,$gp
10319 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10320 addi $tempreg,$tempreg,<constant>
10322 If we have a large constant, and this is a reference to
10323 an external symbol, we want
10324 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10325 addu $tempreg,$tempreg,$gp
10326 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10327 lui $at,<hiconstant>
10328 addi $at,$at,<loconstant>
10329 add $tempreg,$tempreg,$at
10331 If we have NewABI, and we know it's a local symbol, we want
10332 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10333 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10334 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10336 relax_start (offset_expr
.X_add_symbol
);
10338 expr1
.X_add_number
= offset_expr
.X_add_number
;
10339 offset_expr
.X_add_number
= 0;
10341 if (expr1
.X_add_number
== 0 && breg
== 0
10342 && (call
|| tempreg
== PIC_CALL_REG
))
10344 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
10345 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
10347 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
10348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10349 tempreg
, tempreg
, mips_gp_register
);
10350 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10351 tempreg
, lw_reloc_type
, tempreg
);
10353 if (expr1
.X_add_number
== 0)
10355 else if (expr1
.X_add_number
>= -0x8000
10356 && expr1
.X_add_number
< 0x8000)
10358 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
10359 tempreg
, tempreg
, BFD_RELOC_LO16
);
10361 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
10365 /* If we are going to add in a base register, and the
10366 target register and the base register are the same,
10367 then we are using AT as a temporary register. Since
10368 we want to load the constant into AT, we add our
10369 current AT (from the global offset table) and the
10370 register into the register now, and pretend we were
10371 not using a base register. */
10376 gas_assert (tempreg
== AT
);
10377 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10380 add_breg_early
= 1;
10383 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
10384 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
10389 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10392 offset_expr
.X_add_number
= expr1
.X_add_number
;
10393 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
10394 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
10395 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
10396 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
10397 if (add_breg_early
)
10399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10400 op
[0], tempreg
, breg
);
10410 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
10414 gas_assert (!mips_opts
.micromips
);
10415 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
10419 gas_assert (!mips_opts
.micromips
);
10420 macro_build (NULL
, "c2", "C", 0x02);
10424 gas_assert (!mips_opts
.micromips
);
10425 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
10429 gas_assert (!mips_opts
.micromips
);
10430 macro_build (NULL
, "c2", "C", 3);
10434 gas_assert (!mips_opts
.micromips
);
10435 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
10439 /* The j instruction may not be used in PIC code, since it
10440 requires an absolute address. We convert it to a b
10442 if (mips_pic
== NO_PIC
)
10443 macro_build (&offset_expr
, "j", "a");
10445 macro_build (&offset_expr
, "b", "p");
10448 /* The jal instructions must be handled as macros because when
10449 generating PIC code they expand to multi-instruction
10450 sequences. Normally they are simple instructions. */
10454 /* Fall through. */
10456 gas_assert (mips_opts
.micromips
);
10457 if (mips_opts
.insn32
)
10459 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
10467 /* Fall through. */
10470 if (mips_pic
== NO_PIC
)
10472 s
= jals
? "jalrs" : "jalr";
10473 if (mips_opts
.micromips
10474 && !mips_opts
.insn32
10476 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10477 macro_build (NULL
, s
, "mj", op
[1]);
10479 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10483 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
10484 && mips_cprestore_offset
>= 0);
10486 if (op
[1] != PIC_CALL_REG
)
10487 as_warn (_("MIPS PIC call to register other than $25"));
10489 s
= ((mips_opts
.micromips
10490 && !mips_opts
.insn32
10491 && (!mips_opts
.noreorder
|| cprestore
))
10492 ? "jalrs" : "jalr");
10493 if (mips_opts
.micromips
10494 && !mips_opts
.insn32
10496 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
10497 macro_build (NULL
, s
, "mj", op
[1]);
10499 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
10500 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
10502 if (mips_cprestore_offset
< 0)
10503 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10506 if (!mips_frame_reg_valid
)
10508 as_warn (_("No .frame pseudo-op used in PIC code"));
10509 /* Quiet this warning. */
10510 mips_frame_reg_valid
= 1;
10512 if (!mips_cprestore_valid
)
10514 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10515 /* Quiet this warning. */
10516 mips_cprestore_valid
= 1;
10518 if (mips_opts
.noreorder
)
10519 macro_build (NULL
, "nop", "");
10520 expr1
.X_add_number
= mips_cprestore_offset
;
10521 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10524 HAVE_64BIT_ADDRESSES
);
10532 gas_assert (mips_opts
.micromips
);
10533 if (mips_opts
.insn32
)
10535 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
10539 /* Fall through. */
10541 if (mips_pic
== NO_PIC
)
10542 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
10543 else if (mips_pic
== SVR4_PIC
)
10545 /* If this is a reference to an external symbol, and we are
10546 using a small GOT, we want
10547 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10551 lw $gp,cprestore($sp)
10552 The cprestore value is set using the .cprestore
10553 pseudo-op. If we are using a big GOT, we want
10554 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10556 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10560 lw $gp,cprestore($sp)
10561 If the symbol is not external, we want
10562 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10564 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10567 lw $gp,cprestore($sp)
10569 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10570 sequences above, minus nops, unless the symbol is local,
10571 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10577 relax_start (offset_expr
.X_add_symbol
);
10578 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10579 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10582 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10583 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
10589 relax_start (offset_expr
.X_add_symbol
);
10590 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10591 BFD_RELOC_MIPS_CALL_HI16
);
10592 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10593 PIC_CALL_REG
, mips_gp_register
);
10594 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10595 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10598 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10599 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
10601 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10602 PIC_CALL_REG
, PIC_CALL_REG
,
10603 BFD_RELOC_MIPS_GOT_OFST
);
10607 macro_build_jalr (&offset_expr
, 0);
10611 relax_start (offset_expr
.X_add_symbol
);
10614 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10615 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
10624 gpdelay
= reg_needs_delay (mips_gp_register
);
10625 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
10626 BFD_RELOC_MIPS_CALL_HI16
);
10627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
10628 PIC_CALL_REG
, mips_gp_register
);
10629 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10630 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
10635 macro_build (NULL
, "nop", "");
10637 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
10638 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
10641 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
10642 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
10644 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
10646 if (mips_cprestore_offset
< 0)
10647 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10650 if (!mips_frame_reg_valid
)
10652 as_warn (_("No .frame pseudo-op used in PIC code"));
10653 /* Quiet this warning. */
10654 mips_frame_reg_valid
= 1;
10656 if (!mips_cprestore_valid
)
10658 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10659 /* Quiet this warning. */
10660 mips_cprestore_valid
= 1;
10662 if (mips_opts
.noreorder
)
10663 macro_build (NULL
, "nop", "");
10664 expr1
.X_add_number
= mips_cprestore_offset
;
10665 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
10668 HAVE_64BIT_ADDRESSES
);
10672 else if (mips_pic
== VXWORKS_PIC
)
10673 as_bad (_("Non-PIC jump used in PIC library"));
10780 gas_assert (!mips_opts
.micromips
);
10783 /* Itbl support may require additional care here. */
10789 /* Itbl support may require additional care here. */
10795 offbits
= (mips_opts
.micromips
? 12 : 16);
10796 /* Itbl support may require additional care here. */
10800 gas_assert (!mips_opts
.micromips
);
10803 /* Itbl support may require additional care here. */
10809 offbits
= (mips_opts
.micromips
? 12 : 16);
10814 offbits
= (mips_opts
.micromips
? 12 : 16);
10819 /* Itbl support may require additional care here. */
10825 offbits
= (mips_opts
.micromips
? 12 : 16);
10826 /* Itbl support may require additional care here. */
10832 /* Itbl support may require additional care here. */
10838 /* Itbl support may require additional care here. */
10844 offbits
= (mips_opts
.micromips
? 12 : 16);
10849 offbits
= (mips_opts
.micromips
? 12 : 16);
10854 offbits
= (mips_opts
.micromips
? 12 : 16);
10859 offbits
= (mips_opts
.micromips
? 12 : 16);
10864 offbits
= (mips_opts
.micromips
? 12 : 16);
10867 gas_assert (mips_opts
.micromips
);
10874 gas_assert (mips_opts
.micromips
);
10881 gas_assert (mips_opts
.micromips
);
10887 gas_assert (mips_opts
.micromips
);
10894 /* We don't want to use $0 as tempreg. */
10895 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
10898 tempreg
= op
[0] + lp
;
10914 gas_assert (!mips_opts
.micromips
);
10917 /* Itbl support may require additional care here. */
10923 /* Itbl support may require additional care here. */
10929 offbits
= (mips_opts
.micromips
? 12 : 16);
10930 /* Itbl support may require additional care here. */
10934 gas_assert (!mips_opts
.micromips
);
10937 /* Itbl support may require additional care here. */
10943 offbits
= (mips_opts
.micromips
? 12 : 16);
10948 offbits
= (mips_opts
.micromips
? 12 : 16);
10953 offbits
= (mips_opts
.micromips
? 12 : 16);
10958 offbits
= (mips_opts
.micromips
? 12 : 16);
10962 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
10963 offbits
= (mips_opts
.micromips
? 12 : 16);
10972 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
10973 offbits
= (mips_opts
.micromips
? 12 : 16);
10984 /* Itbl support may require additional care here. */
10989 offbits
= (mips_opts
.micromips
? 12 : 16);
10990 /* Itbl support may require additional care here. */
10996 /* Itbl support may require additional care here. */
11000 gas_assert (!mips_opts
.micromips
);
11003 /* Itbl support may require additional care here. */
11009 offbits
= (mips_opts
.micromips
? 12 : 16);
11014 offbits
= (mips_opts
.micromips
? 12 : 16);
11017 gas_assert (mips_opts
.micromips
);
11023 gas_assert (mips_opts
.micromips
);
11029 gas_assert (mips_opts
.micromips
);
11035 gas_assert (mips_opts
.micromips
);
11044 if (small_offset_p (0, align
, 16))
11046 /* The first case exists for M_LD_AB and M_SD_AB, which are
11047 macros for o32 but which should act like normal instructions
11050 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11051 offset_reloc
[1], offset_reloc
[2], breg
);
11052 else if (small_offset_p (0, align
, offbits
))
11055 macro_build (NULL
, s
, fmt
, op
[0], breg
);
11057 macro_build (NULL
, s
, fmt
, op
[0],
11058 (int) offset_expr
.X_add_number
, breg
);
11064 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11065 tempreg
, breg
, -1, offset_reloc
[0],
11066 offset_reloc
[1], offset_reloc
[2]);
11068 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11070 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11078 if (offset_expr
.X_op
!= O_constant
11079 && offset_expr
.X_op
!= O_symbol
)
11081 as_bad (_("Expression too complex"));
11082 offset_expr
.X_op
= O_constant
;
11085 if (HAVE_32BIT_ADDRESSES
11086 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11090 sprintf_vma (value
, offset_expr
.X_add_number
);
11091 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11094 /* A constant expression in PIC code can be handled just as it
11095 is in non PIC code. */
11096 if (offset_expr
.X_op
== O_constant
)
11098 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
11099 offbits
== 0 ? 16 : offbits
);
11100 offset_expr
.X_add_number
-= expr1
.X_add_number
;
11102 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
11104 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11105 tempreg
, tempreg
, breg
);
11108 if (offset_expr
.X_add_number
!= 0)
11109 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
11110 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
11111 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11113 else if (offbits
== 16)
11114 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11116 macro_build (NULL
, s
, fmt
, op
[0],
11117 (int) offset_expr
.X_add_number
, tempreg
);
11119 else if (offbits
!= 16)
11121 /* The offset field is too narrow to be used for a low-part
11122 relocation, so load the whole address into the auxillary
11124 load_address (tempreg
, &offset_expr
, &used_at
);
11126 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11127 tempreg
, tempreg
, breg
);
11129 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
11131 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
11133 else if (mips_pic
== NO_PIC
)
11135 /* If this is a reference to a GP relative symbol, and there
11136 is no base register, we want
11137 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11138 Otherwise, if there is no base register, we want
11139 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11140 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11141 If we have a constant, we need two instructions anyhow,
11142 so we always use the latter form.
11144 If we have a base register, and this is a reference to a
11145 GP relative symbol, we want
11146 addu $tempreg,$breg,$gp
11147 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11149 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11150 addu $tempreg,$tempreg,$breg
11151 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11152 With a constant we always use the latter case.
11154 With 64bit address space and no base register and $at usable,
11156 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11157 lui $at,<sym> (BFD_RELOC_HI16_S)
11158 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11161 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11162 If we have a base register, we want
11163 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11164 lui $at,<sym> (BFD_RELOC_HI16_S)
11165 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11169 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11171 Without $at we can't generate the optimal path for superscalar
11172 processors here since this would require two temporary registers.
11173 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11174 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11176 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11178 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11179 If we have a base register, we want
11180 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11181 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11183 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11185 daddu $tempreg,$tempreg,$breg
11186 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11188 For GP relative symbols in 64bit address space we can use
11189 the same sequence as in 32bit address space. */
11190 if (HAVE_64BIT_SYMBOLS
)
11192 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11193 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11195 relax_start (offset_expr
.X_add_symbol
);
11198 macro_build (&offset_expr
, s
, fmt
, op
[0],
11199 BFD_RELOC_GPREL16
, mips_gp_register
);
11203 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11204 tempreg
, breg
, mips_gp_register
);
11205 macro_build (&offset_expr
, s
, fmt
, op
[0],
11206 BFD_RELOC_GPREL16
, tempreg
);
11211 if (used_at
== 0 && mips_opts
.at
)
11213 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11214 BFD_RELOC_MIPS_HIGHEST
);
11215 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
11217 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11218 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11220 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
11221 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11222 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11223 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
11229 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11230 BFD_RELOC_MIPS_HIGHEST
);
11231 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11232 tempreg
, BFD_RELOC_MIPS_HIGHER
);
11233 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11234 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
11235 tempreg
, BFD_RELOC_HI16_S
);
11236 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11238 macro_build (NULL
, "daddu", "d,v,t",
11239 tempreg
, tempreg
, breg
);
11240 macro_build (&offset_expr
, s
, fmt
, op
[0],
11241 BFD_RELOC_LO16
, tempreg
);
11244 if (mips_relax
.sequence
)
11251 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11252 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11254 relax_start (offset_expr
.X_add_symbol
);
11255 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
11259 macro_build_lui (&offset_expr
, tempreg
);
11260 macro_build (&offset_expr
, s
, fmt
, op
[0],
11261 BFD_RELOC_LO16
, tempreg
);
11262 if (mips_relax
.sequence
)
11267 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11268 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11270 relax_start (offset_expr
.X_add_symbol
);
11271 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11272 tempreg
, breg
, mips_gp_register
);
11273 macro_build (&offset_expr
, s
, fmt
, op
[0],
11274 BFD_RELOC_GPREL16
, tempreg
);
11277 macro_build_lui (&offset_expr
, tempreg
);
11278 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11279 tempreg
, tempreg
, breg
);
11280 macro_build (&offset_expr
, s
, fmt
, op
[0],
11281 BFD_RELOC_LO16
, tempreg
);
11282 if (mips_relax
.sequence
)
11286 else if (!mips_big_got
)
11288 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11290 /* If this is a reference to an external symbol, we want
11291 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11293 <op> op[0],0($tempreg)
11295 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11297 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11298 <op> op[0],0($tempreg)
11300 For NewABI, we want
11301 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11302 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11304 If there is a base register, we add it to $tempreg before
11305 the <op>. If there is a constant, we stick it in the
11306 <op> instruction. We don't handle constants larger than
11307 16 bits, because we have no way to load the upper 16 bits
11308 (actually, we could handle them for the subset of cases
11309 in which we are not using $at). */
11310 gas_assert (offset_expr
.X_op
== O_symbol
);
11313 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11314 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11316 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11317 tempreg
, tempreg
, breg
);
11318 macro_build (&offset_expr
, s
, fmt
, op
[0],
11319 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11322 expr1
.X_add_number
= offset_expr
.X_add_number
;
11323 offset_expr
.X_add_number
= 0;
11324 if (expr1
.X_add_number
< -0x8000
11325 || expr1
.X_add_number
>= 0x8000)
11326 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11327 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11328 lw_reloc_type
, mips_gp_register
);
11330 relax_start (offset_expr
.X_add_symbol
);
11332 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11333 tempreg
, BFD_RELOC_LO16
);
11336 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11337 tempreg
, tempreg
, breg
);
11338 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11340 else if (mips_big_got
&& !HAVE_NEWABI
)
11344 /* If this is a reference to an external symbol, we want
11345 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11346 addu $tempreg,$tempreg,$gp
11347 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11348 <op> op[0],0($tempreg)
11350 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11352 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11353 <op> op[0],0($tempreg)
11354 If there is a base register, we add it to $tempreg before
11355 the <op>. If there is a constant, we stick it in the
11356 <op> instruction. We don't handle constants larger than
11357 16 bits, because we have no way to load the upper 16 bits
11358 (actually, we could handle them for the subset of cases
11359 in which we are not using $at). */
11360 gas_assert (offset_expr
.X_op
== O_symbol
);
11361 expr1
.X_add_number
= offset_expr
.X_add_number
;
11362 offset_expr
.X_add_number
= 0;
11363 if (expr1
.X_add_number
< -0x8000
11364 || expr1
.X_add_number
>= 0x8000)
11365 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11366 gpdelay
= reg_needs_delay (mips_gp_register
);
11367 relax_start (offset_expr
.X_add_symbol
);
11368 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11369 BFD_RELOC_MIPS_GOT_HI16
);
11370 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11372 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11373 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11376 macro_build (NULL
, "nop", "");
11377 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11378 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11380 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11381 tempreg
, BFD_RELOC_LO16
);
11385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11386 tempreg
, tempreg
, breg
);
11387 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11389 else if (mips_big_got
&& HAVE_NEWABI
)
11391 /* If this is a reference to an external symbol, we want
11392 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11393 add $tempreg,$tempreg,$gp
11394 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11395 <op> op[0],<ofst>($tempreg)
11396 Otherwise, for local symbols, we want:
11397 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11398 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11399 gas_assert (offset_expr
.X_op
== O_symbol
);
11400 expr1
.X_add_number
= offset_expr
.X_add_number
;
11401 offset_expr
.X_add_number
= 0;
11402 if (expr1
.X_add_number
< -0x8000
11403 || expr1
.X_add_number
>= 0x8000)
11404 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11405 relax_start (offset_expr
.X_add_symbol
);
11406 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
11407 BFD_RELOC_MIPS_GOT_HI16
);
11408 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
11410 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11411 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
11413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11414 tempreg
, tempreg
, breg
);
11415 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
11418 offset_expr
.X_add_number
= expr1
.X_add_number
;
11419 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11420 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11422 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11423 tempreg
, tempreg
, breg
);
11424 macro_build (&offset_expr
, s
, fmt
, op
[0],
11425 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
11434 gas_assert (mips_opts
.micromips
);
11435 gas_assert (mips_opts
.insn32
);
11436 start_noreorder ();
11437 macro_build (NULL
, "jr", "s", RA
);
11438 expr1
.X_add_number
= op
[0] << 2;
11439 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
11444 gas_assert (mips_opts
.micromips
);
11445 gas_assert (mips_opts
.insn32
);
11446 macro_build (NULL
, "jr", "s", op
[0]);
11447 if (mips_opts
.noreorder
)
11448 macro_build (NULL
, "nop", "");
11453 load_register (op
[0], &imm_expr
, 0);
11457 load_register (op
[0], &imm_expr
, 1);
11461 if (imm_expr
.X_op
== O_constant
)
11464 load_register (AT
, &imm_expr
, 0);
11465 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11470 gas_assert (offset_expr
.X_op
== O_symbol
11471 && strcmp (segment_name (S_GET_SEGMENT
11472 (offset_expr
.X_add_symbol
)),
11474 && offset_expr
.X_add_number
== 0);
11475 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
11476 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
11481 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11482 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11483 order 32 bits of the value and the low order 32 bits are either
11484 zero or in OFFSET_EXPR. */
11485 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
11487 if (HAVE_64BIT_GPRS
)
11488 load_register (op
[0], &imm_expr
, 1);
11493 if (target_big_endian
)
11505 load_register (hreg
, &imm_expr
, 0);
11508 if (offset_expr
.X_op
== O_absent
)
11509 move_register (lreg
, 0);
11512 gas_assert (offset_expr
.X_op
== O_constant
);
11513 load_register (lreg
, &offset_expr
, 0);
11520 /* We know that sym is in the .rdata section. First we get the
11521 upper 16 bits of the address. */
11522 if (mips_pic
== NO_PIC
)
11524 macro_build_lui (&offset_expr
, AT
);
11529 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11530 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11534 /* Now we load the register(s). */
11535 if (HAVE_64BIT_GPRS
)
11538 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
11539 BFD_RELOC_LO16
, AT
);
11544 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
11545 BFD_RELOC_LO16
, AT
);
11548 /* FIXME: How in the world do we deal with the possible
11550 offset_expr
.X_add_number
+= 4;
11551 macro_build (&offset_expr
, "lw", "t,o(b)",
11552 op
[0] + 1, BFD_RELOC_LO16
, AT
);
11558 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11559 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11560 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11561 the value and the low order 32 bits are either zero or in
11563 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
11566 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
11567 if (HAVE_64BIT_FPRS
)
11569 gas_assert (HAVE_64BIT_GPRS
);
11570 macro_build (NULL
, "dmtc1", "t,S", AT
, op
[0]);
11574 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0] + 1);
11575 if (offset_expr
.X_op
== O_absent
)
11576 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
11579 gas_assert (offset_expr
.X_op
== O_constant
);
11580 load_register (AT
, &offset_expr
, 0);
11581 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
11587 gas_assert (offset_expr
.X_op
== O_symbol
11588 && offset_expr
.X_add_number
== 0);
11589 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
11590 if (strcmp (s
, ".lit8") == 0)
11592 op
[2] = mips_gp_register
;
11593 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
11594 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11595 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11599 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
11601 if (mips_pic
!= NO_PIC
)
11602 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11603 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11606 /* FIXME: This won't work for a 64 bit address. */
11607 macro_build_lui (&offset_expr
, AT
);
11611 offset_reloc
[0] = BFD_RELOC_LO16
;
11612 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11613 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11620 * The MIPS assembler seems to check for X_add_number not
11621 * being double aligned and generating:
11622 * lui at,%hi(foo+1)
11624 * addiu at,at,%lo(foo+1)
11627 * But, the resulting address is the same after relocation so why
11628 * generate the extra instruction?
11630 /* Itbl support may require additional care here. */
11633 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11642 gas_assert (!mips_opts
.micromips
);
11643 /* Itbl support may require additional care here. */
11646 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
11666 if (HAVE_64BIT_GPRS
)
11676 if (HAVE_64BIT_GPRS
)
11684 /* Even on a big endian machine $fn comes before $fn+1. We have
11685 to adjust when loading from memory. We set coproc if we must
11686 load $fn+1 first. */
11687 /* Itbl support may require additional care here. */
11688 if (!target_big_endian
)
11692 if (small_offset_p (0, align
, 16))
11695 if (!small_offset_p (4, align
, 16))
11697 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
11698 -1, offset_reloc
[0], offset_reloc
[1],
11700 expr1
.X_add_number
= 0;
11704 offset_reloc
[0] = BFD_RELOC_LO16
;
11705 offset_reloc
[1] = BFD_RELOC_UNUSED
;
11706 offset_reloc
[2] = BFD_RELOC_UNUSED
;
11708 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
11710 ep
->X_add_number
+= 4;
11711 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
11712 offset_reloc
[1], offset_reloc
[2], breg
);
11713 ep
->X_add_number
-= 4;
11714 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
11715 offset_reloc
[1], offset_reloc
[2], breg
);
11719 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
11720 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11722 ep
->X_add_number
+= 4;
11723 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
11724 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
11730 if (offset_expr
.X_op
!= O_symbol
11731 && offset_expr
.X_op
!= O_constant
)
11733 as_bad (_("Expression too complex"));
11734 offset_expr
.X_op
= O_constant
;
11737 if (HAVE_32BIT_ADDRESSES
11738 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11742 sprintf_vma (value
, offset_expr
.X_add_number
);
11743 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
11746 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
11748 /* If this is a reference to a GP relative symbol, we want
11749 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11750 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11751 If we have a base register, we use this
11753 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11754 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11755 If this is not a GP relative symbol, we want
11756 lui $at,<sym> (BFD_RELOC_HI16_S)
11757 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11758 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11759 If there is a base register, we add it to $at after the
11760 lui instruction. If there is a constant, we always use
11762 if (offset_expr
.X_op
== O_symbol
11763 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11764 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11766 relax_start (offset_expr
.X_add_symbol
);
11769 tempreg
= mips_gp_register
;
11773 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11774 AT
, breg
, mips_gp_register
);
11779 /* Itbl support may require additional care here. */
11780 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11781 BFD_RELOC_GPREL16
, tempreg
);
11782 offset_expr
.X_add_number
+= 4;
11784 /* Set mips_optimize to 2 to avoid inserting an
11786 hold_mips_optimize
= mips_optimize
;
11788 /* Itbl support may require additional care here. */
11789 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11790 BFD_RELOC_GPREL16
, tempreg
);
11791 mips_optimize
= hold_mips_optimize
;
11795 offset_expr
.X_add_number
-= 4;
11798 if (offset_high_part (offset_expr
.X_add_number
, 16)
11799 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
11801 load_address (AT
, &offset_expr
, &used_at
);
11802 offset_expr
.X_op
= O_constant
;
11803 offset_expr
.X_add_number
= 0;
11806 macro_build_lui (&offset_expr
, AT
);
11808 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11809 /* Itbl support may require additional care here. */
11810 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11811 BFD_RELOC_LO16
, AT
);
11812 /* FIXME: How do we handle overflow here? */
11813 offset_expr
.X_add_number
+= 4;
11814 /* Itbl support may require additional care here. */
11815 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11816 BFD_RELOC_LO16
, AT
);
11817 if (mips_relax
.sequence
)
11820 else if (!mips_big_got
)
11822 /* If this is a reference to an external symbol, we want
11823 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11826 <op> op[0]+1,4($at)
11828 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11830 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11831 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11832 If there is a base register we add it to $at before the
11833 lwc1 instructions. If there is a constant we include it
11834 in the lwc1 instructions. */
11836 expr1
.X_add_number
= offset_expr
.X_add_number
;
11837 if (expr1
.X_add_number
< -0x8000
11838 || expr1
.X_add_number
>= 0x8000 - 4)
11839 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11840 load_got_offset (AT
, &offset_expr
);
11843 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11845 /* Set mips_optimize to 2 to avoid inserting an undesired
11847 hold_mips_optimize
= mips_optimize
;
11850 /* Itbl support may require additional care here. */
11851 relax_start (offset_expr
.X_add_symbol
);
11852 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11853 BFD_RELOC_LO16
, AT
);
11854 expr1
.X_add_number
+= 4;
11855 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11856 BFD_RELOC_LO16
, AT
);
11858 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11859 BFD_RELOC_LO16
, AT
);
11860 offset_expr
.X_add_number
+= 4;
11861 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11862 BFD_RELOC_LO16
, AT
);
11865 mips_optimize
= hold_mips_optimize
;
11867 else if (mips_big_got
)
11871 /* If this is a reference to an external symbol, we want
11872 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11874 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11877 <op> op[0]+1,4($at)
11879 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11881 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11882 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11883 If there is a base register we add it to $at before the
11884 lwc1 instructions. If there is a constant we include it
11885 in the lwc1 instructions. */
11887 expr1
.X_add_number
= offset_expr
.X_add_number
;
11888 offset_expr
.X_add_number
= 0;
11889 if (expr1
.X_add_number
< -0x8000
11890 || expr1
.X_add_number
>= 0x8000 - 4)
11891 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11892 gpdelay
= reg_needs_delay (mips_gp_register
);
11893 relax_start (offset_expr
.X_add_symbol
);
11894 macro_build (&offset_expr
, "lui", LUI_FMT
,
11895 AT
, BFD_RELOC_MIPS_GOT_HI16
);
11896 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11897 AT
, AT
, mips_gp_register
);
11898 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11899 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
11902 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11903 /* Itbl support may require additional care here. */
11904 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11905 BFD_RELOC_LO16
, AT
);
11906 expr1
.X_add_number
+= 4;
11908 /* Set mips_optimize to 2 to avoid inserting an undesired
11910 hold_mips_optimize
= mips_optimize
;
11912 /* Itbl support may require additional care here. */
11913 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11914 BFD_RELOC_LO16
, AT
);
11915 mips_optimize
= hold_mips_optimize
;
11916 expr1
.X_add_number
-= 4;
11919 offset_expr
.X_add_number
= expr1
.X_add_number
;
11921 macro_build (NULL
, "nop", "");
11922 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
11923 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11926 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
11927 /* Itbl support may require additional care here. */
11928 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
11929 BFD_RELOC_LO16
, AT
);
11930 offset_expr
.X_add_number
+= 4;
11932 /* Set mips_optimize to 2 to avoid inserting an undesired
11934 hold_mips_optimize
= mips_optimize
;
11936 /* Itbl support may require additional care here. */
11937 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
11938 BFD_RELOC_LO16
, AT
);
11939 mips_optimize
= hold_mips_optimize
;
11958 /* New code added to support COPZ instructions.
11959 This code builds table entries out of the macros in mip_opcodes.
11960 R4000 uses interlocks to handle coproc delays.
11961 Other chips (like the R3000) require nops to be inserted for delays.
11963 FIXME: Currently, we require that the user handle delays.
11964 In order to fill delay slots for non-interlocked chips,
11965 we must have a way to specify delays based on the coprocessor.
11966 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11967 What are the side-effects of the cop instruction?
11968 What cache support might we have and what are its effects?
11969 Both coprocessor & memory require delays. how long???
11970 What registers are read/set/modified?
11972 If an itbl is provided to interpret cop instructions,
11973 this knowledge can be encoded in the itbl spec. */
11987 gas_assert (!mips_opts
.micromips
);
11988 /* For now we just do C (same as Cz). The parameter will be
11989 stored in insn_opcode by mips_ip. */
11990 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
11994 move_register (op
[0], op
[1]);
11998 gas_assert (mips_opts
.micromips
);
11999 gas_assert (mips_opts
.insn32
);
12000 move_register (micromips_to_32_reg_h_map1
[op
[0]],
12001 micromips_to_32_reg_m_map
[op
[1]]);
12002 move_register (micromips_to_32_reg_h_map2
[op
[0]],
12003 micromips_to_32_reg_n_map
[op
[2]]);
12009 if (mips_opts
.arch
== CPU_R5900
)
12010 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
12014 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
12015 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12022 /* The MIPS assembler some times generates shifts and adds. I'm
12023 not trying to be that fancy. GCC should do this for us
12026 load_register (AT
, &imm_expr
, dbl
);
12027 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
12028 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12041 start_noreorder ();
12044 load_register (AT
, &imm_expr
, dbl
);
12045 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
12046 op
[1], imm
? AT
: op
[2]);
12047 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12048 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
12049 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12051 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
12054 if (mips_opts
.micromips
)
12055 micromips_label_expr (&label_expr
);
12057 label_expr
.X_add_number
= 8;
12058 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
12059 macro_build (NULL
, "nop", "");
12060 macro_build (NULL
, "break", BRK_FMT
, 6);
12061 if (mips_opts
.micromips
)
12062 micromips_add_label ();
12065 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12078 start_noreorder ();
12081 load_register (AT
, &imm_expr
, dbl
);
12082 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
12083 op
[1], imm
? AT
: op
[2]);
12084 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
12085 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
12087 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
12090 if (mips_opts
.micromips
)
12091 micromips_label_expr (&label_expr
);
12093 label_expr
.X_add_number
= 8;
12094 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
12095 macro_build (NULL
, "nop", "");
12096 macro_build (NULL
, "break", BRK_FMT
, 6);
12097 if (mips_opts
.micromips
)
12098 micromips_add_label ();
12104 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12106 if (op
[0] == op
[1])
12113 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
12114 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
12118 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12119 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
12120 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
12121 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12125 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12127 if (op
[0] == op
[1])
12134 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
12135 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
12139 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12140 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
12141 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
12142 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12151 if (imm_expr
.X_op
!= O_constant
)
12152 as_bad (_("Improper rotate count"));
12153 rot
= imm_expr
.X_add_number
& 0x3f;
12154 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12156 rot
= (64 - rot
) & 0x3f;
12158 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12160 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12165 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12168 l
= (rot
< 0x20) ? "dsll" : "dsll32";
12169 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
12172 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
12173 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12174 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12182 if (imm_expr
.X_op
!= O_constant
)
12183 as_bad (_("Improper rotate count"));
12184 rot
= imm_expr
.X_add_number
& 0x1f;
12185 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12187 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
12188 (32 - rot
) & 0x1f);
12193 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12197 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
12198 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12199 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12204 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12206 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
12210 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
12211 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
12212 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
12213 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12217 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12219 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
12223 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
12224 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
12225 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
12226 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12235 if (imm_expr
.X_op
!= O_constant
)
12236 as_bad (_("Improper rotate count"));
12237 rot
= imm_expr
.X_add_number
& 0x3f;
12238 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
12241 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
12243 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
12248 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
12251 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
12252 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
12255 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
12256 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12257 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12265 if (imm_expr
.X_op
!= O_constant
)
12266 as_bad (_("Improper rotate count"));
12267 rot
= imm_expr
.X_add_number
& 0x1f;
12268 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
12270 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
12275 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
12279 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
12280 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
12281 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12287 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
12288 else if (op
[2] == 0)
12289 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12292 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12293 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12298 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
12300 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12305 as_warn (_("Instruction %s: result is always false"),
12306 ip
->insn_mo
->name
);
12307 move_register (op
[0], 0);
12310 if (CPU_HAS_SEQ (mips_opts
.arch
)
12311 && -512 <= imm_expr
.X_add_number
12312 && imm_expr
.X_add_number
< 512)
12314 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
12315 (int) imm_expr
.X_add_number
);
12318 if (imm_expr
.X_op
== O_constant
12319 && imm_expr
.X_add_number
>= 0
12320 && imm_expr
.X_add_number
< 0x10000)
12321 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
12322 else if (imm_expr
.X_op
== O_constant
12323 && imm_expr
.X_add_number
> -0x8000
12324 && imm_expr
.X_add_number
< 0)
12326 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12327 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12328 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12330 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12333 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12334 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
12339 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12340 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12343 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
12346 case M_SGE
: /* X >= Y <==> not (X < Y) */
12352 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
12353 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12356 case M_SGE_I
: /* X >= I <==> not (X < I) */
12358 if (imm_expr
.X_op
== O_constant
12359 && imm_expr
.X_add_number
>= -0x8000
12360 && imm_expr
.X_add_number
< 0x8000)
12361 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
12362 op
[0], op
[1], BFD_RELOC_LO16
);
12365 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12366 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
12370 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12373 case M_SGT
: /* X > Y <==> Y < X */
12379 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12382 case M_SGT_I
: /* X > I <==> I < X */
12389 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12390 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12393 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X) */
12399 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
12400 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12403 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
12410 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12411 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
12412 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
12416 if (imm_expr
.X_op
== O_constant
12417 && imm_expr
.X_add_number
>= -0x8000
12418 && imm_expr
.X_add_number
< 0x8000)
12420 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
12425 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12426 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
12430 if (imm_expr
.X_op
== O_constant
12431 && imm_expr
.X_add_number
>= -0x8000
12432 && imm_expr
.X_add_number
< 0x8000)
12434 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
12439 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12440 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
12445 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
12446 else if (op
[2] == 0)
12447 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12450 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
12451 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12456 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
12458 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
12463 as_warn (_("Instruction %s: result is always true"),
12464 ip
->insn_mo
->name
);
12465 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
12466 op
[0], 0, BFD_RELOC_LO16
);
12469 if (CPU_HAS_SEQ (mips_opts
.arch
)
12470 && -512 <= imm_expr
.X_add_number
12471 && imm_expr
.X_add_number
< 512)
12473 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
12474 (int) imm_expr
.X_add_number
);
12477 if (imm_expr
.X_op
== O_constant
12478 && imm_expr
.X_add_number
>= 0
12479 && imm_expr
.X_add_number
< 0x10000)
12481 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
12484 else if (imm_expr
.X_op
== O_constant
12485 && imm_expr
.X_add_number
> -0x8000
12486 && imm_expr
.X_add_number
< 0)
12488 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12489 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
12490 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12492 else if (CPU_HAS_SEQ (mips_opts
.arch
))
12495 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12496 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
12501 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12502 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
12505 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
12520 if (!mips_opts
.micromips
)
12522 if (imm_expr
.X_op
== O_constant
12523 && imm_expr
.X_add_number
> -0x200
12524 && imm_expr
.X_add_number
<= 0x200)
12526 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1], -imm_expr
.X_add_number
);
12535 if (imm_expr
.X_op
== O_constant
12536 && imm_expr
.X_add_number
> -0x8000
12537 && imm_expr
.X_add_number
<= 0x8000)
12539 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12540 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
12545 load_register (AT
, &imm_expr
, dbl
);
12546 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
12568 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
12569 macro_build (NULL
, s
, "s,t", op
[0], AT
);
12574 gas_assert (!mips_opts
.micromips
);
12575 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
12579 * Is the double cfc1 instruction a bug in the mips assembler;
12580 * or is there a reason for it?
12582 start_noreorder ();
12583 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12584 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
12585 macro_build (NULL
, "nop", "");
12586 expr1
.X_add_number
= 3;
12587 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
12588 expr1
.X_add_number
= 2;
12589 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
12590 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
12591 macro_build (NULL
, "nop", "");
12592 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
12594 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
12595 macro_build (NULL
, "nop", "");
12612 offbits
= (mips_opts
.micromips
? 12 : 16);
12618 offbits
= (mips_opts
.micromips
? 12 : 16);
12630 offbits
= (mips_opts
.micromips
? 12 : 16);
12637 offbits
= (mips_opts
.micromips
? 12 : 16);
12643 large_offset
= !small_offset_p (off
, align
, offbits
);
12645 expr1
.X_add_number
= 0;
12650 if (small_offset_p (0, align
, 16))
12651 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
12652 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
12655 load_address (tempreg
, ep
, &used_at
);
12657 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12658 tempreg
, tempreg
, breg
);
12660 offset_reloc
[0] = BFD_RELOC_LO16
;
12661 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12662 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12667 else if (!ust
&& op
[0] == breg
)
12678 if (!target_big_endian
)
12679 ep
->X_add_number
+= off
;
12681 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
12683 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12684 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12686 if (!target_big_endian
)
12687 ep
->X_add_number
-= off
;
12689 ep
->X_add_number
+= off
;
12691 macro_build (NULL
, s2
, "t,~(b)",
12692 tempreg
, (int) ep
->X_add_number
, breg
);
12694 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12695 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12697 /* If necessary, move the result in tempreg to the final destination. */
12698 if (!ust
&& op
[0] != tempreg
)
12700 /* Protect second load's delay slot. */
12702 move_register (op
[0], tempreg
);
12708 if (target_big_endian
== ust
)
12709 ep
->X_add_number
+= off
;
12710 tempreg
= ust
|| large_offset
? op
[0] : AT
;
12711 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
12712 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12714 /* For halfword transfers we need a temporary register to shuffle
12715 bytes. Unfortunately for M_USH_A we have none available before
12716 the next store as AT holds the base address. We deal with this
12717 case by clobbering TREG and then restoring it as with ULH. */
12718 tempreg
= ust
== large_offset
? op
[0] : AT
;
12720 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
12722 if (target_big_endian
== ust
)
12723 ep
->X_add_number
-= off
;
12725 ep
->X_add_number
+= off
;
12726 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
12727 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
12729 /* For M_USH_A re-retrieve the LSB. */
12730 if (ust
&& large_offset
)
12732 if (target_big_endian
)
12733 ep
->X_add_number
+= off
;
12735 ep
->X_add_number
-= off
;
12736 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
12737 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
12739 /* For ULH and M_USH_A OR the LSB in. */
12740 if (!ust
|| large_offset
)
12742 tempreg
= !large_offset
? AT
: op
[0];
12743 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
12744 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
12749 /* FIXME: Check if this is one of the itbl macros, since they
12750 are added dynamically. */
12751 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
12754 if (!mips_opts
.at
&& used_at
)
12755 as_bad (_("Macro used $at after \".set noat\""));
12758 /* Implement macros in mips16 mode. */
12761 mips16_macro (struct mips_cl_insn
*ip
)
12763 const struct mips_operand_array
*operands
;
12768 const char *s
, *s2
, *s3
;
12769 unsigned int op
[MAX_OPERANDS
];
12772 mask
= ip
->insn_mo
->mask
;
12774 operands
= insn_operands (ip
);
12775 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12776 if (operands
->operand
[i
])
12777 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
12781 expr1
.X_op
= O_constant
;
12782 expr1
.X_op_symbol
= NULL
;
12783 expr1
.X_add_symbol
= NULL
;
12784 expr1
.X_add_number
= 1;
12803 start_noreorder ();
12804 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", op
[1], op
[2]);
12805 expr1
.X_add_number
= 2;
12806 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12807 macro_build (NULL
, "break", "6", 7);
12809 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12810 since that causes an overflow. We should do that as well,
12811 but I don't see how to do the comparisons without a temporary
12814 macro_build (NULL
, s
, "x", op
[0]);
12833 start_noreorder ();
12834 macro_build (NULL
, s
, "0,x,y", op
[1], op
[2]);
12835 expr1
.X_add_number
= 2;
12836 macro_build (&expr1
, "bnez", "x,p", op
[2]);
12837 macro_build (NULL
, "break", "6", 7);
12839 macro_build (NULL
, s2
, "x", op
[0]);
12845 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
12846 macro_build (NULL
, "mflo", "x", op
[0]);
12854 if (imm_expr
.X_op
!= O_constant
)
12855 as_bad (_("Unsupported large constant"));
12856 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12857 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", op
[0], op
[1]);
12861 if (imm_expr
.X_op
!= O_constant
)
12862 as_bad (_("Unsupported large constant"));
12863 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12864 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
12868 if (imm_expr
.X_op
!= O_constant
)
12869 as_bad (_("Unsupported large constant"));
12870 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
12871 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
12893 goto do_reverse_branch
;
12897 goto do_reverse_branch
;
12909 goto do_reverse_branch
;
12920 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
12921 macro_build (&offset_expr
, s2
, "p");
12948 goto do_addone_branch_i
;
12953 goto do_addone_branch_i
;
12968 goto do_addone_branch_i
;
12974 do_addone_branch_i
:
12975 if (imm_expr
.X_op
!= O_constant
)
12976 as_bad (_("Unsupported large constant"));
12977 ++imm_expr
.X_add_number
;
12980 macro_build (&imm_expr
, s
, s3
, op
[0]);
12981 macro_build (&offset_expr
, s2
, "p");
12985 expr1
.X_add_number
= 0;
12986 macro_build (&expr1
, "slti", "x,8", op
[1]);
12987 if (op
[0] != op
[1])
12988 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
12989 expr1
.X_add_number
= 2;
12990 macro_build (&expr1
, "bteqz", "p");
12991 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
12996 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12997 opcode bits in *OPCODE_EXTRA. */
12999 static struct mips_opcode
*
13000 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
13001 ssize_t length
, unsigned int *opcode_extra
)
13003 char *name
, *dot
, *p
;
13004 unsigned int mask
, suffix
;
13006 struct mips_opcode
*insn
;
13008 /* Make a copy of the instruction so that we can fiddle with it. */
13009 name
= alloca (length
+ 1);
13010 memcpy (name
, start
, length
);
13011 name
[length
] = '\0';
13013 /* Look up the instruction as-is. */
13014 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13018 dot
= strchr (name
, '.');
13021 /* Try to interpret the text after the dot as a VU0 channel suffix. */
13022 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
13023 if (*p
== 0 && mask
!= 0)
13026 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13028 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
13030 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
13036 if (mips_opts
.micromips
)
13038 /* See if there's an instruction size override suffix,
13039 either `16' or `32', at the end of the mnemonic proper,
13040 that defines the operation, i.e. before the first `.'
13041 character if any. Strip it and retry. */
13042 opend
= dot
!= NULL
? dot
- name
: length
;
13043 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
13045 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
13051 memcpy (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
13052 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
13055 forced_insn_length
= suffix
;
13064 /* Assemble an instruction into its binary format. If the instruction
13065 is a macro, set imm_expr, imm2_expr and offset_expr to the values
13066 associated with "I", "+I" and "A" operands respectively. Otherwise
13067 store the value of the relocatable field (if any) in offset_expr.
13068 In both cases set offset_reloc to the relocation operators applied
13072 mips_ip (char *str
, struct mips_cl_insn
*insn
)
13074 const struct mips_opcode
*first
, *past
;
13075 struct hash_control
*hash
;
13078 struct mips_operand_token
*tokens
;
13079 unsigned int opcode_extra
;
13081 if (mips_opts
.micromips
)
13083 hash
= micromips_op_hash
;
13084 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
13089 past
= &mips_opcodes
[NUMOPCODES
];
13091 forced_insn_length
= 0;
13094 /* We first try to match an instruction up to a space or to the end. */
13095 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
13098 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
13101 set_insn_error (0, _("Unrecognized opcode"));
13105 if (strcmp (first
->name
, "li.s") == 0)
13107 else if (strcmp (first
->name
, "li.d") == 0)
13111 tokens
= mips_parse_arguments (str
+ end
, format
);
13115 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
13116 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
13117 set_insn_error (0, _("Illegal operands"));
13119 obstack_free (&mips_operand_tokens
, tokens
);
13122 /* As for mips_ip, but used when assembling MIPS16 code.
13123 Also set forced_insn_length to the resulting instruction size in
13124 bytes if the user explicitly requested a small or extended instruction. */
13127 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
13130 struct mips_opcode
*first
;
13131 struct mips_operand_token
*tokens
;
13133 forced_insn_length
= 0;
13135 for (s
= str
; ISLOWER (*s
); ++s
)
13149 if (s
[1] == 't' && s
[2] == ' ')
13151 forced_insn_length
= 2;
13155 else if (s
[1] == 'e' && s
[2] == ' ')
13157 forced_insn_length
= 4;
13161 /* Fall through. */
13163 set_insn_error (0, _("Unrecognized opcode"));
13167 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13168 forced_insn_length
= 2;
13171 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
13176 set_insn_error (0, _("Unrecognized opcode"));
13180 tokens
= mips_parse_arguments (s
, 0);
13184 if (!match_mips16_insns (insn
, first
, tokens
))
13185 set_insn_error (0, _("Illegal operands"));
13187 obstack_free (&mips_operand_tokens
, tokens
);
13190 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13191 NBITS is the number of significant bits in VAL. */
13193 static unsigned long
13194 mips16_immed_extend (offsetT val
, unsigned int nbits
)
13199 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
13202 else if (nbits
== 15)
13204 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
13209 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
13212 return (extval
<< 16) | val
;
13215 /* Like decode_mips16_operand, but require the operand to be defined and
13216 require it to be an integer. */
13218 static const struct mips_int_operand
*
13219 mips16_immed_operand (int type
, bfd_boolean extended_p
)
13221 const struct mips_operand
*operand
;
13223 operand
= decode_mips16_operand (type
, extended_p
);
13224 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
13226 return (const struct mips_int_operand
*) operand
;
13229 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13232 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
13233 bfd_reloc_code_real_type reloc
, offsetT sval
)
13235 int min_val
, max_val
;
13237 min_val
= mips_int_operand_min (operand
);
13238 max_val
= mips_int_operand_max (operand
);
13239 if (reloc
!= BFD_RELOC_UNUSED
)
13242 sval
= SEXT_16BIT (sval
);
13247 return (sval
>= min_val
13249 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
13252 /* Install immediate value VAL into MIPS16 instruction *INSN,
13253 extending it if necessary. The instruction in *INSN may
13254 already be extended.
13256 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13257 if none. In the former case, VAL is a 16-bit number with no
13258 defined signedness.
13260 TYPE is the type of the immediate field. USER_INSN_LENGTH
13261 is the length that the user requested, or 0 if none. */
13264 mips16_immed (char *file
, unsigned int line
, int type
,
13265 bfd_reloc_code_real_type reloc
, offsetT val
,
13266 unsigned int user_insn_length
, unsigned long *insn
)
13268 const struct mips_int_operand
*operand
;
13269 unsigned int uval
, length
;
13271 operand
= mips16_immed_operand (type
, FALSE
);
13272 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13274 /* We need an extended instruction. */
13275 if (user_insn_length
== 2)
13276 as_bad_where (file
, line
, _("invalid unextended operand value"));
13278 *insn
|= MIPS16_EXTEND
;
13280 else if (user_insn_length
== 4)
13282 /* The operand doesn't force an unextended instruction to be extended.
13283 Warn if the user wanted an extended instruction anyway. */
13284 *insn
|= MIPS16_EXTEND
;
13285 as_warn_where (file
, line
,
13286 _("extended operand requested but not required"));
13289 length
= mips16_opcode_length (*insn
);
13292 operand
= mips16_immed_operand (type
, TRUE
);
13293 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
13294 as_bad_where (file
, line
,
13295 _("operand value out of range for instruction"));
13297 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
13299 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
13301 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
13304 struct percent_op_match
13307 bfd_reloc_code_real_type reloc
;
13310 static const struct percent_op_match mips_percent_op
[] =
13312 {"%lo", BFD_RELOC_LO16
},
13313 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
13314 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
13315 {"%call16", BFD_RELOC_MIPS_CALL16
},
13316 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
13317 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
13318 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
13319 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
13320 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
13321 {"%got", BFD_RELOC_MIPS_GOT16
},
13322 {"%gp_rel", BFD_RELOC_GPREL16
},
13323 {"%half", BFD_RELOC_16
},
13324 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
13325 {"%higher", BFD_RELOC_MIPS_HIGHER
},
13326 {"%neg", BFD_RELOC_MIPS_SUB
},
13327 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
13328 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
13329 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
13330 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
13331 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
13332 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
13333 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
13334 {"%hi", BFD_RELOC_HI16_S
}
13337 static const struct percent_op_match mips16_percent_op
[] =
13339 {"%lo", BFD_RELOC_MIPS16_LO16
},
13340 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
13341 {"%got", BFD_RELOC_MIPS16_GOT16
},
13342 {"%call16", BFD_RELOC_MIPS16_CALL16
},
13343 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
13344 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
13345 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
13346 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
13347 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
13348 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
13349 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
13350 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
13354 /* Return true if *STR points to a relocation operator. When returning true,
13355 move *STR over the operator and store its relocation code in *RELOC.
13356 Leave both *STR and *RELOC alone when returning false. */
13359 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
13361 const struct percent_op_match
*percent_op
;
13364 if (mips_opts
.mips16
)
13366 percent_op
= mips16_percent_op
;
13367 limit
= ARRAY_SIZE (mips16_percent_op
);
13371 percent_op
= mips_percent_op
;
13372 limit
= ARRAY_SIZE (mips_percent_op
);
13375 for (i
= 0; i
< limit
; i
++)
13376 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
13378 int len
= strlen (percent_op
[i
].str
);
13380 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
13383 *str
+= strlen (percent_op
[i
].str
);
13384 *reloc
= percent_op
[i
].reloc
;
13386 /* Check whether the output BFD supports this relocation.
13387 If not, issue an error and fall back on something safe. */
13388 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
13390 as_bad (_("relocation %s isn't supported by the current ABI"),
13391 percent_op
[i
].str
);
13392 *reloc
= BFD_RELOC_UNUSED
;
13400 /* Parse string STR as a 16-bit relocatable operand. Store the
13401 expression in *EP and the relocations in the array starting
13402 at RELOC. Return the number of relocation operators used.
13404 On exit, EXPR_END points to the first character after the expression. */
13407 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
13410 bfd_reloc_code_real_type reversed_reloc
[3];
13411 size_t reloc_index
, i
;
13412 int crux_depth
, str_depth
;
13415 /* Search for the start of the main expression, recoding relocations
13416 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13417 of the main expression and with CRUX_DEPTH containing the number
13418 of open brackets at that point. */
13425 crux_depth
= str_depth
;
13427 /* Skip over whitespace and brackets, keeping count of the number
13429 while (*str
== ' ' || *str
== '\t' || *str
== '(')
13434 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
13435 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
13437 my_getExpression (ep
, crux
);
13440 /* Match every open bracket. */
13441 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
13445 if (crux_depth
> 0)
13446 as_bad (_("unclosed '('"));
13450 if (reloc_index
!= 0)
13452 prev_reloc_op_frag
= frag_now
;
13453 for (i
= 0; i
< reloc_index
; i
++)
13454 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
13457 return reloc_index
;
13461 my_getExpression (expressionS
*ep
, char *str
)
13465 save_in
= input_line_pointer
;
13466 input_line_pointer
= str
;
13468 expr_end
= input_line_pointer
;
13469 input_line_pointer
= save_in
;
13473 md_atof (int type
, char *litP
, int *sizeP
)
13475 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
13479 md_number_to_chars (char *buf
, valueT val
, int n
)
13481 if (target_big_endian
)
13482 number_to_chars_bigendian (buf
, val
, n
);
13484 number_to_chars_littleendian (buf
, val
, n
);
13487 static int support_64bit_objects(void)
13489 const char **list
, **l
;
13492 list
= bfd_target_list ();
13493 for (l
= list
; *l
!= NULL
; l
++)
13494 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
13495 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
13497 yes
= (*l
!= NULL
);
13502 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13503 NEW_VALUE. Warn if another value was already specified. Note:
13504 we have to defer parsing the -march and -mtune arguments in order
13505 to handle 'from-abi' correctly, since the ABI might be specified
13506 in a later argument. */
13509 mips_set_option_string (const char **string_ptr
, const char *new_value
)
13511 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
13512 as_warn (_("A different %s was already specified, is now %s"),
13513 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
13516 *string_ptr
= new_value
;
13520 md_parse_option (int c
, char *arg
)
13524 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
13525 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
13527 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
13528 c
== mips_ases
[i
].option_on
);
13534 case OPTION_CONSTRUCT_FLOATS
:
13535 mips_disable_float_construction
= 0;
13538 case OPTION_NO_CONSTRUCT_FLOATS
:
13539 mips_disable_float_construction
= 1;
13551 target_big_endian
= 1;
13555 target_big_endian
= 0;
13561 else if (arg
[0] == '0')
13563 else if (arg
[0] == '1')
13573 mips_debug
= atoi (arg
);
13577 file_mips_isa
= ISA_MIPS1
;
13581 file_mips_isa
= ISA_MIPS2
;
13585 file_mips_isa
= ISA_MIPS3
;
13589 file_mips_isa
= ISA_MIPS4
;
13593 file_mips_isa
= ISA_MIPS5
;
13596 case OPTION_MIPS32
:
13597 file_mips_isa
= ISA_MIPS32
;
13600 case OPTION_MIPS32R2
:
13601 file_mips_isa
= ISA_MIPS32R2
;
13604 case OPTION_MIPS64R2
:
13605 file_mips_isa
= ISA_MIPS64R2
;
13608 case OPTION_MIPS64
:
13609 file_mips_isa
= ISA_MIPS64
;
13613 mips_set_option_string (&mips_tune_string
, arg
);
13617 mips_set_option_string (&mips_arch_string
, arg
);
13621 mips_set_option_string (&mips_arch_string
, "4650");
13622 mips_set_option_string (&mips_tune_string
, "4650");
13625 case OPTION_NO_M4650
:
13629 mips_set_option_string (&mips_arch_string
, "4010");
13630 mips_set_option_string (&mips_tune_string
, "4010");
13633 case OPTION_NO_M4010
:
13637 mips_set_option_string (&mips_arch_string
, "4100");
13638 mips_set_option_string (&mips_tune_string
, "4100");
13641 case OPTION_NO_M4100
:
13645 mips_set_option_string (&mips_arch_string
, "3900");
13646 mips_set_option_string (&mips_tune_string
, "3900");
13649 case OPTION_NO_M3900
:
13652 case OPTION_MICROMIPS
:
13653 if (mips_opts
.mips16
== 1)
13655 as_bad (_("-mmicromips cannot be used with -mips16"));
13658 mips_opts
.micromips
= 1;
13659 mips_no_prev_insn ();
13662 case OPTION_NO_MICROMIPS
:
13663 mips_opts
.micromips
= 0;
13664 mips_no_prev_insn ();
13667 case OPTION_MIPS16
:
13668 if (mips_opts
.micromips
== 1)
13670 as_bad (_("-mips16 cannot be used with -micromips"));
13673 mips_opts
.mips16
= 1;
13674 mips_no_prev_insn ();
13677 case OPTION_NO_MIPS16
:
13678 mips_opts
.mips16
= 0;
13679 mips_no_prev_insn ();
13682 case OPTION_FIX_24K
:
13686 case OPTION_NO_FIX_24K
:
13690 case OPTION_FIX_LOONGSON2F_JUMP
:
13691 mips_fix_loongson2f_jump
= TRUE
;
13694 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
13695 mips_fix_loongson2f_jump
= FALSE
;
13698 case OPTION_FIX_LOONGSON2F_NOP
:
13699 mips_fix_loongson2f_nop
= TRUE
;
13702 case OPTION_NO_FIX_LOONGSON2F_NOP
:
13703 mips_fix_loongson2f_nop
= FALSE
;
13706 case OPTION_FIX_VR4120
:
13707 mips_fix_vr4120
= 1;
13710 case OPTION_NO_FIX_VR4120
:
13711 mips_fix_vr4120
= 0;
13714 case OPTION_FIX_VR4130
:
13715 mips_fix_vr4130
= 1;
13718 case OPTION_NO_FIX_VR4130
:
13719 mips_fix_vr4130
= 0;
13722 case OPTION_FIX_CN63XXP1
:
13723 mips_fix_cn63xxp1
= TRUE
;
13726 case OPTION_NO_FIX_CN63XXP1
:
13727 mips_fix_cn63xxp1
= FALSE
;
13730 case OPTION_RELAX_BRANCH
:
13731 mips_relax_branch
= 1;
13734 case OPTION_NO_RELAX_BRANCH
:
13735 mips_relax_branch
= 0;
13738 case OPTION_INSN32
:
13739 mips_opts
.insn32
= TRUE
;
13742 case OPTION_NO_INSN32
:
13743 mips_opts
.insn32
= FALSE
;
13746 case OPTION_MSHARED
:
13747 mips_in_shared
= TRUE
;
13750 case OPTION_MNO_SHARED
:
13751 mips_in_shared
= FALSE
;
13754 case OPTION_MSYM32
:
13755 mips_opts
.sym32
= TRUE
;
13758 case OPTION_MNO_SYM32
:
13759 mips_opts
.sym32
= FALSE
;
13762 /* When generating ELF code, we permit -KPIC and -call_shared to
13763 select SVR4_PIC, and -non_shared to select no PIC. This is
13764 intended to be compatible with Irix 5. */
13765 case OPTION_CALL_SHARED
:
13766 mips_pic
= SVR4_PIC
;
13767 mips_abicalls
= TRUE
;
13770 case OPTION_CALL_NONPIC
:
13772 mips_abicalls
= TRUE
;
13775 case OPTION_NON_SHARED
:
13777 mips_abicalls
= FALSE
;
13780 /* The -xgot option tells the assembler to use 32 bit offsets
13781 when accessing the got in SVR4_PIC mode. It is for Irix
13788 g_switch_value
= atoi (arg
);
13792 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13795 mips_abi
= O32_ABI
;
13799 mips_abi
= N32_ABI
;
13803 mips_abi
= N64_ABI
;
13804 if (!support_64bit_objects())
13805 as_fatal (_("No compiled in support for 64 bit object file format"));
13809 file_mips_gp32
= 1;
13813 file_mips_gp32
= 0;
13817 file_mips_fp32
= 1;
13821 file_mips_fp32
= 0;
13824 case OPTION_SINGLE_FLOAT
:
13825 file_mips_single_float
= 1;
13828 case OPTION_DOUBLE_FLOAT
:
13829 file_mips_single_float
= 0;
13832 case OPTION_SOFT_FLOAT
:
13833 file_mips_soft_float
= 1;
13836 case OPTION_HARD_FLOAT
:
13837 file_mips_soft_float
= 0;
13841 if (strcmp (arg
, "32") == 0)
13842 mips_abi
= O32_ABI
;
13843 else if (strcmp (arg
, "o64") == 0)
13844 mips_abi
= O64_ABI
;
13845 else if (strcmp (arg
, "n32") == 0)
13846 mips_abi
= N32_ABI
;
13847 else if (strcmp (arg
, "64") == 0)
13849 mips_abi
= N64_ABI
;
13850 if (! support_64bit_objects())
13851 as_fatal (_("No compiled in support for 64 bit object file "
13854 else if (strcmp (arg
, "eabi") == 0)
13855 mips_abi
= EABI_ABI
;
13858 as_fatal (_("invalid abi -mabi=%s"), arg
);
13863 case OPTION_M7000_HILO_FIX
:
13864 mips_7000_hilo_fix
= TRUE
;
13867 case OPTION_MNO_7000_HILO_FIX
:
13868 mips_7000_hilo_fix
= FALSE
;
13871 case OPTION_MDEBUG
:
13872 mips_flag_mdebug
= TRUE
;
13875 case OPTION_NO_MDEBUG
:
13876 mips_flag_mdebug
= FALSE
;
13880 mips_flag_pdr
= TRUE
;
13883 case OPTION_NO_PDR
:
13884 mips_flag_pdr
= FALSE
;
13887 case OPTION_MVXWORKS_PIC
:
13888 mips_pic
= VXWORKS_PIC
;
13892 if (strcmp (arg
, "2008") == 0)
13893 mips_flag_nan2008
= TRUE
;
13894 else if (strcmp (arg
, "legacy") == 0)
13895 mips_flag_nan2008
= FALSE
;
13898 as_fatal (_("Invalid NaN setting -mnan=%s"), arg
);
13907 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
13912 /* Set up globals to generate code for the ISA or processor
13913 described by INFO. */
13916 mips_set_architecture (const struct mips_cpu_info
*info
)
13920 file_mips_arch
= info
->cpu
;
13921 mips_opts
.arch
= info
->cpu
;
13922 mips_opts
.isa
= info
->isa
;
13927 /* Likewise for tuning. */
13930 mips_set_tune (const struct mips_cpu_info
*info
)
13933 mips_tune
= info
->cpu
;
13938 mips_after_parse_args (void)
13940 const struct mips_cpu_info
*arch_info
= 0;
13941 const struct mips_cpu_info
*tune_info
= 0;
13943 /* GP relative stuff not working for PE */
13944 if (strncmp (TARGET_OS
, "pe", 2) == 0)
13946 if (g_switch_seen
&& g_switch_value
!= 0)
13947 as_bad (_("-G not supported in this configuration."));
13948 g_switch_value
= 0;
13951 if (mips_abi
== NO_ABI
)
13952 mips_abi
= MIPS_DEFAULT_ABI
;
13954 /* The following code determines the architecture and register size.
13955 Similar code was added to GCC 3.3 (see override_options() in
13956 config/mips/mips.c). The GAS and GCC code should be kept in sync
13957 as much as possible. */
13959 if (mips_arch_string
!= 0)
13960 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
13962 if (file_mips_isa
!= ISA_UNKNOWN
)
13964 /* Handle -mipsN. At this point, file_mips_isa contains the
13965 ISA level specified by -mipsN, while arch_info->isa contains
13966 the -march selection (if any). */
13967 if (arch_info
!= 0)
13969 /* -march takes precedence over -mipsN, since it is more descriptive.
13970 There's no harm in specifying both as long as the ISA levels
13972 if (file_mips_isa
!= arch_info
->isa
)
13973 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13974 mips_cpu_info_from_isa (file_mips_isa
)->name
,
13975 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
13978 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
13981 if (arch_info
== 0)
13983 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
13984 gas_assert (arch_info
);
13987 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
13988 as_bad (_("-march=%s is not compatible with the selected ABI"),
13991 mips_set_architecture (arch_info
);
13993 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13994 if (mips_tune_string
!= 0)
13995 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
13997 if (tune_info
== 0)
13998 mips_set_tune (arch_info
);
14000 mips_set_tune (tune_info
);
14002 if (file_mips_gp32
>= 0)
14004 /* The user specified the size of the integer registers. Make sure
14005 it agrees with the ABI and ISA. */
14006 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
14007 as_bad (_("-mgp64 used with a 32-bit processor"));
14008 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
14009 as_bad (_("-mgp32 used with a 64-bit ABI"));
14010 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
14011 as_bad (_("-mgp64 used with a 32-bit ABI"));
14015 /* Infer the integer register size from the ABI and processor.
14016 Restrict ourselves to 32-bit registers if that's all the
14017 processor has, or if the ABI cannot handle 64-bit registers. */
14018 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
14019 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
14022 switch (file_mips_fp32
)
14026 /* No user specified float register size.
14027 ??? GAS treats single-float processors as though they had 64-bit
14028 float registers (although it complains when double-precision
14029 instructions are used). As things stand, saying they have 32-bit
14030 registers would lead to spurious "register must be even" messages.
14031 So here we assume float registers are never smaller than the
14033 if (file_mips_gp32
== 0)
14034 /* 64-bit integer registers implies 64-bit float registers. */
14035 file_mips_fp32
= 0;
14036 else if ((mips_opts
.ase
& FP64_ASES
)
14037 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14038 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14039 file_mips_fp32
= 0;
14041 /* 32-bit float registers. */
14042 file_mips_fp32
= 1;
14045 /* The user specified the size of the float registers. Check if it
14046 agrees with the ABI and ISA. */
14048 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
14049 as_bad (_("-mfp64 used with a 32-bit fpu"));
14050 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
14051 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
14052 as_warn (_("-mfp64 used with a 32-bit ABI"));
14055 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14056 as_warn (_("-mfp32 used with a 64-bit ABI"));
14060 /* End of GCC-shared inference code. */
14062 /* This flag is set when we have a 64-bit capable CPU but use only
14063 32-bit wide registers. Note that EABI does not use it. */
14064 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
14065 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
14066 || mips_abi
== O32_ABI
))
14067 mips_32bitmode
= 1;
14069 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
14070 as_bad (_("trap exception not supported at ISA 1"));
14072 /* If the selected architecture includes support for ASEs, enable
14073 generation of code for them. */
14074 if (mips_opts
.mips16
== -1)
14075 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
14076 if (mips_opts
.micromips
== -1)
14077 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
14079 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14080 ASEs from being selected implicitly. */
14081 if (file_mips_fp32
== 1)
14082 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
14084 /* If the user didn't explicitly select or deselect a particular ASE,
14085 use the default setting for the CPU. */
14086 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
14088 file_mips_isa
= mips_opts
.isa
;
14089 file_ase
= mips_opts
.ase
;
14090 mips_opts
.gp32
= file_mips_gp32
;
14091 mips_opts
.fp32
= file_mips_fp32
;
14092 mips_opts
.soft_float
= file_mips_soft_float
;
14093 mips_opts
.single_float
= file_mips_single_float
;
14095 mips_check_isa_supports_ases ();
14097 if (mips_flag_mdebug
< 0)
14098 mips_flag_mdebug
= 0;
14102 mips_init_after_args (void)
14104 /* initialize opcodes */
14105 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
14106 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
14110 md_pcrel_from (fixS
*fixP
)
14112 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
14113 switch (fixP
->fx_r_type
)
14115 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14116 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14117 /* Return the address of the delay slot. */
14120 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14121 case BFD_RELOC_MICROMIPS_JMP
:
14122 case BFD_RELOC_16_PCREL_S2
:
14123 case BFD_RELOC_MIPS_JMP
:
14124 /* Return the address of the delay slot. */
14127 case BFD_RELOC_32_PCREL
:
14131 /* We have no relocation type for PC relative MIPS16 instructions. */
14132 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
14133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14134 _("PC relative MIPS16 instruction references a different section"));
14139 /* This is called before the symbol table is processed. In order to
14140 work with gcc when using mips-tfile, we must keep all local labels.
14141 However, in other cases, we want to discard them. If we were
14142 called with -g, but we didn't see any debugging information, it may
14143 mean that gcc is smuggling debugging information through to
14144 mips-tfile, in which case we must generate all local labels. */
14147 mips_frob_file_before_adjust (void)
14149 #ifndef NO_ECOFF_DEBUGGING
14150 if (ECOFF_DEBUGGING
14152 && ! ecoff_debugging_seen
)
14153 flag_keep_locals
= 1;
14157 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14158 the corresponding LO16 reloc. This is called before md_apply_fix and
14159 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14160 relocation operators.
14162 For our purposes, a %lo() expression matches a %got() or %hi()
14165 (a) it refers to the same symbol; and
14166 (b) the offset applied in the %lo() expression is no lower than
14167 the offset applied in the %got() or %hi().
14169 (b) allows us to cope with code like:
14172 lh $4,%lo(foo+2)($4)
14174 ...which is legal on RELA targets, and has a well-defined behaviour
14175 if the user knows that adding 2 to "foo" will not induce a carry to
14178 When several %lo()s match a particular %got() or %hi(), we use the
14179 following rules to distinguish them:
14181 (1) %lo()s with smaller offsets are a better match than %lo()s with
14184 (2) %lo()s with no matching %got() or %hi() are better than those
14185 that already have a matching %got() or %hi().
14187 (3) later %lo()s are better than earlier %lo()s.
14189 These rules are applied in order.
14191 (1) means, among other things, that %lo()s with identical offsets are
14192 chosen if they exist.
14194 (2) means that we won't associate several high-part relocations with
14195 the same low-part relocation unless there's no alternative. Having
14196 several high parts for the same low part is a GNU extension; this rule
14197 allows careful users to avoid it.
14199 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14200 with the last high-part relocation being at the front of the list.
14201 It therefore makes sense to choose the last matching low-part
14202 relocation, all other things being equal. It's also easier
14203 to code that way. */
14206 mips_frob_file (void)
14208 struct mips_hi_fixup
*l
;
14209 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
14211 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
14213 segment_info_type
*seginfo
;
14214 bfd_boolean matched_lo_p
;
14215 fixS
**hi_pos
, **lo_pos
, **pos
;
14217 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
14219 /* If a GOT16 relocation turns out to be against a global symbol,
14220 there isn't supposed to be a matching LO. Ignore %gots against
14221 constants; we'll report an error for those later. */
14222 if (got16_reloc_p (l
->fixp
->fx_r_type
)
14223 && !(l
->fixp
->fx_addsy
14224 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
14227 /* Check quickly whether the next fixup happens to be a matching %lo. */
14228 if (fixup_has_matching_lo_p (l
->fixp
))
14231 seginfo
= seg_info (l
->seg
);
14233 /* Set HI_POS to the position of this relocation in the chain.
14234 Set LO_POS to the position of the chosen low-part relocation.
14235 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14236 relocation that matches an immediately-preceding high-part
14240 matched_lo_p
= FALSE
;
14241 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
14243 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
14245 if (*pos
== l
->fixp
)
14248 if ((*pos
)->fx_r_type
== looking_for_rtype
14249 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
14250 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
14252 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
14254 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
14257 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
14258 && fixup_has_matching_lo_p (*pos
));
14261 /* If we found a match, remove the high-part relocation from its
14262 current position and insert it before the low-part relocation.
14263 Make the offsets match so that fixup_has_matching_lo_p()
14266 We don't warn about unmatched high-part relocations since some
14267 versions of gcc have been known to emit dead "lui ...%hi(...)"
14269 if (lo_pos
!= NULL
)
14271 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
14272 if (l
->fixp
->fx_next
!= *lo_pos
)
14274 *hi_pos
= l
->fixp
->fx_next
;
14275 l
->fixp
->fx_next
= *lo_pos
;
14283 mips_force_relocation (fixS
*fixp
)
14285 if (generic_force_reloc (fixp
))
14288 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14289 so that the linker relaxation can update targets. */
14290 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14291 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14292 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
14298 /* Read the instruction associated with RELOC from BUF. */
14300 static unsigned int
14301 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
14303 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14304 return read_compressed_insn (buf
, 4);
14306 return read_insn (buf
);
14309 /* Write instruction INSN to BUF, given that it has been relocated
14313 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
14314 unsigned long insn
)
14316 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
14317 write_compressed_insn (buf
, insn
, 4);
14319 write_insn (buf
, insn
);
14322 /* Apply a fixup to the object file. */
14325 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
14328 unsigned long insn
;
14329 reloc_howto_type
*howto
;
14331 /* We ignore generic BFD relocations we don't know about. */
14332 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
14336 gas_assert (fixP
->fx_size
== 2
14337 || fixP
->fx_size
== 4
14338 || fixP
->fx_r_type
== BFD_RELOC_16
14339 || fixP
->fx_r_type
== BFD_RELOC_64
14340 || fixP
->fx_r_type
== BFD_RELOC_CTOR
14341 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
14342 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
14343 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14344 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
14345 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
14347 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
14349 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
14350 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
14351 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
14352 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
14353 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
14355 /* Don't treat parts of a composite relocation as done. There are two
14358 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14359 should nevertheless be emitted if the first part is.
14361 (2) In normal usage, composite relocations are never assembly-time
14362 constants. The easiest way of dealing with the pathological
14363 exceptions is to generate a relocation against STN_UNDEF and
14364 leave everything up to the linker. */
14365 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
14368 switch (fixP
->fx_r_type
)
14370 case BFD_RELOC_MIPS_TLS_GD
:
14371 case BFD_RELOC_MIPS_TLS_LDM
:
14372 case BFD_RELOC_MIPS_TLS_DTPREL32
:
14373 case BFD_RELOC_MIPS_TLS_DTPREL64
:
14374 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
14375 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
14376 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
14377 case BFD_RELOC_MIPS_TLS_TPREL32
:
14378 case BFD_RELOC_MIPS_TLS_TPREL64
:
14379 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
14380 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
14381 case BFD_RELOC_MICROMIPS_TLS_GD
:
14382 case BFD_RELOC_MICROMIPS_TLS_LDM
:
14383 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
14384 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
14385 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
14386 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
14387 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
14388 case BFD_RELOC_MIPS16_TLS_GD
:
14389 case BFD_RELOC_MIPS16_TLS_LDM
:
14390 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
14391 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
14392 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
14393 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
14394 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
14395 if (!fixP
->fx_addsy
)
14397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14398 _("TLS relocation against a constant"));
14401 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
14404 case BFD_RELOC_MIPS_JMP
:
14405 case BFD_RELOC_MIPS_SHIFT5
:
14406 case BFD_RELOC_MIPS_SHIFT6
:
14407 case BFD_RELOC_MIPS_GOT_DISP
:
14408 case BFD_RELOC_MIPS_GOT_PAGE
:
14409 case BFD_RELOC_MIPS_GOT_OFST
:
14410 case BFD_RELOC_MIPS_SUB
:
14411 case BFD_RELOC_MIPS_INSERT_A
:
14412 case BFD_RELOC_MIPS_INSERT_B
:
14413 case BFD_RELOC_MIPS_DELETE
:
14414 case BFD_RELOC_MIPS_HIGHEST
:
14415 case BFD_RELOC_MIPS_HIGHER
:
14416 case BFD_RELOC_MIPS_SCN_DISP
:
14417 case BFD_RELOC_MIPS_REL16
:
14418 case BFD_RELOC_MIPS_RELGOT
:
14419 case BFD_RELOC_MIPS_JALR
:
14420 case BFD_RELOC_HI16
:
14421 case BFD_RELOC_HI16_S
:
14422 case BFD_RELOC_LO16
:
14423 case BFD_RELOC_GPREL16
:
14424 case BFD_RELOC_MIPS_LITERAL
:
14425 case BFD_RELOC_MIPS_CALL16
:
14426 case BFD_RELOC_MIPS_GOT16
:
14427 case BFD_RELOC_GPREL32
:
14428 case BFD_RELOC_MIPS_GOT_HI16
:
14429 case BFD_RELOC_MIPS_GOT_LO16
:
14430 case BFD_RELOC_MIPS_CALL_HI16
:
14431 case BFD_RELOC_MIPS_CALL_LO16
:
14432 case BFD_RELOC_MIPS16_GPREL
:
14433 case BFD_RELOC_MIPS16_GOT16
:
14434 case BFD_RELOC_MIPS16_CALL16
:
14435 case BFD_RELOC_MIPS16_HI16
:
14436 case BFD_RELOC_MIPS16_HI16_S
:
14437 case BFD_RELOC_MIPS16_LO16
:
14438 case BFD_RELOC_MIPS16_JMP
:
14439 case BFD_RELOC_MICROMIPS_JMP
:
14440 case BFD_RELOC_MICROMIPS_GOT_DISP
:
14441 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
14442 case BFD_RELOC_MICROMIPS_GOT_OFST
:
14443 case BFD_RELOC_MICROMIPS_SUB
:
14444 case BFD_RELOC_MICROMIPS_HIGHEST
:
14445 case BFD_RELOC_MICROMIPS_HIGHER
:
14446 case BFD_RELOC_MICROMIPS_SCN_DISP
:
14447 case BFD_RELOC_MICROMIPS_JALR
:
14448 case BFD_RELOC_MICROMIPS_HI16
:
14449 case BFD_RELOC_MICROMIPS_HI16_S
:
14450 case BFD_RELOC_MICROMIPS_LO16
:
14451 case BFD_RELOC_MICROMIPS_GPREL16
:
14452 case BFD_RELOC_MICROMIPS_LITERAL
:
14453 case BFD_RELOC_MICROMIPS_CALL16
:
14454 case BFD_RELOC_MICROMIPS_GOT16
:
14455 case BFD_RELOC_MICROMIPS_GOT_HI16
:
14456 case BFD_RELOC_MICROMIPS_GOT_LO16
:
14457 case BFD_RELOC_MICROMIPS_CALL_HI16
:
14458 case BFD_RELOC_MICROMIPS_CALL_LO16
:
14459 case BFD_RELOC_MIPS_EH
:
14464 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
14466 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
14467 if (mips16_reloc_p (fixP
->fx_r_type
))
14468 insn
|= mips16_immed_extend (value
, 16);
14470 insn
|= (value
& 0xffff);
14471 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
14474 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14475 _("Unsupported constant in relocation"));
14480 /* This is handled like BFD_RELOC_32, but we output a sign
14481 extended value if we are only 32 bits. */
14484 if (8 <= sizeof (valueT
))
14485 md_number_to_chars (buf
, *valP
, 8);
14490 if ((*valP
& 0x80000000) != 0)
14494 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
14495 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
14500 case BFD_RELOC_RVA
:
14502 case BFD_RELOC_32_PCREL
:
14504 /* If we are deleting this reloc entry, we must fill in the
14505 value now. This can happen if we have a .word which is not
14506 resolved when it appears but is later defined. */
14508 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
14511 case BFD_RELOC_16_PCREL_S2
:
14512 if ((*valP
& 0x3) != 0)
14513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14514 _("Branch to misaligned address (%lx)"), (long) *valP
);
14516 /* We need to save the bits in the instruction since fixup_segment()
14517 might be deleting the relocation entry (i.e., a branch within
14518 the current segment). */
14519 if (! fixP
->fx_done
)
14522 /* Update old instruction data. */
14523 insn
= read_insn (buf
);
14525 if (*valP
+ 0x20000 <= 0x3ffff)
14527 insn
|= (*valP
>> 2) & 0xffff;
14528 write_insn (buf
, insn
);
14530 else if (mips_pic
== NO_PIC
14532 && fixP
->fx_frag
->fr_address
>= text_section
->vma
14533 && (fixP
->fx_frag
->fr_address
14534 < text_section
->vma
+ bfd_get_section_size (text_section
))
14535 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
14536 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
14537 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
14539 /* The branch offset is too large. If this is an
14540 unconditional branch, and we are not generating PIC code,
14541 we can convert it to an absolute jump instruction. */
14542 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
14543 insn
= 0x0c000000; /* jal */
14545 insn
= 0x08000000; /* j */
14546 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
14548 fixP
->fx_addsy
= section_symbol (text_section
);
14549 *valP
+= md_pcrel_from (fixP
);
14550 write_insn (buf
, insn
);
14554 /* If we got here, we have branch-relaxation disabled,
14555 and there's nothing we can do to fix this instruction
14556 without turning it into a longer sequence. */
14557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
14558 _("Branch out of range"));
14562 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
14563 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
14564 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
14565 /* We adjust the offset back to even. */
14566 if ((*valP
& 0x1) != 0)
14569 if (! fixP
->fx_done
)
14572 /* Should never visit here, because we keep the relocation. */
14576 case BFD_RELOC_VTABLE_INHERIT
:
14579 && !S_IS_DEFINED (fixP
->fx_addsy
)
14580 && !S_IS_WEAK (fixP
->fx_addsy
))
14581 S_SET_WEAK (fixP
->fx_addsy
);
14584 case BFD_RELOC_VTABLE_ENTRY
:
14592 /* Remember value for tc_gen_reloc. */
14593 fixP
->fx_addnumber
= *valP
;
14603 name
= input_line_pointer
;
14604 c
= get_symbol_end ();
14605 p
= (symbolS
*) symbol_find_or_make (name
);
14606 *input_line_pointer
= c
;
14610 /* Align the current frag to a given power of two. If a particular
14611 fill byte should be used, FILL points to an integer that contains
14612 that byte, otherwise FILL is null.
14614 This function used to have the comment:
14616 The MIPS assembler also automatically adjusts any preceding label.
14618 The implementation therefore applied the adjustment to a maximum of
14619 one label. However, other label adjustments are applied to batches
14620 of labels, and adjusting just one caused problems when new labels
14621 were added for the sake of debugging or unwind information.
14622 We therefore adjust all preceding labels (given as LABELS) instead. */
14625 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
14627 mips_emit_delays ();
14628 mips_record_compressed_mode ();
14629 if (fill
== NULL
&& subseg_text_p (now_seg
))
14630 frag_align_code (to
, 0);
14632 frag_align (to
, fill
? *fill
: 0, 0);
14633 record_alignment (now_seg
, to
);
14634 mips_move_labels (labels
, FALSE
);
14637 /* Align to a given power of two. .align 0 turns off the automatic
14638 alignment used by the data creating pseudo-ops. */
14641 s_align (int x ATTRIBUTE_UNUSED
)
14643 int temp
, fill_value
, *fill_ptr
;
14644 long max_alignment
= 28;
14646 /* o Note that the assembler pulls down any immediately preceding label
14647 to the aligned address.
14648 o It's not documented but auto alignment is reinstated by
14649 a .align pseudo instruction.
14650 o Note also that after auto alignment is turned off the mips assembler
14651 issues an error on attempt to assemble an improperly aligned data item.
14654 temp
= get_absolute_expression ();
14655 if (temp
> max_alignment
)
14656 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
14659 as_warn (_("Alignment negative: 0 assumed."));
14662 if (*input_line_pointer
== ',')
14664 ++input_line_pointer
;
14665 fill_value
= get_absolute_expression ();
14666 fill_ptr
= &fill_value
;
14672 segment_info_type
*si
= seg_info (now_seg
);
14673 struct insn_label_list
*l
= si
->label_list
;
14674 /* Auto alignment should be switched on by next section change. */
14676 mips_align (temp
, fill_ptr
, l
);
14683 demand_empty_rest_of_line ();
14687 s_change_sec (int sec
)
14691 /* The ELF backend needs to know that we are changing sections, so
14692 that .previous works correctly. We could do something like check
14693 for an obj_section_change_hook macro, but that might be confusing
14694 as it would not be appropriate to use it in the section changing
14695 functions in read.c, since obj-elf.c intercepts those. FIXME:
14696 This should be cleaner, somehow. */
14697 obj_elf_section_change_hook ();
14699 mips_emit_delays ();
14710 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
14711 demand_empty_rest_of_line ();
14715 seg
= subseg_new (RDATA_SECTION_NAME
,
14716 (subsegT
) get_absolute_expression ());
14717 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
14718 | SEC_READONLY
| SEC_RELOC
14720 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14721 record_alignment (seg
, 4);
14722 demand_empty_rest_of_line ();
14726 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
14727 bfd_set_section_flags (stdoutput
, seg
,
14728 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
14729 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14730 record_alignment (seg
, 4);
14731 demand_empty_rest_of_line ();
14735 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
14736 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
14737 if (strncmp (TARGET_OS
, "elf", 3) != 0)
14738 record_alignment (seg
, 4);
14739 demand_empty_rest_of_line ();
14747 s_change_section (int ignore ATTRIBUTE_UNUSED
)
14749 char *section_name
;
14754 int section_entry_size
;
14755 int section_alignment
;
14757 section_name
= input_line_pointer
;
14758 c
= get_symbol_end ();
14760 next_c
= *(input_line_pointer
+ 1);
14762 /* Do we have .section Name<,"flags">? */
14763 if (c
!= ',' || (c
== ',' && next_c
== '"'))
14765 /* just after name is now '\0'. */
14766 *input_line_pointer
= c
;
14767 input_line_pointer
= section_name
;
14768 obj_elf_section (ignore
);
14771 input_line_pointer
++;
14773 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14775 section_type
= get_absolute_expression ();
14778 if (*input_line_pointer
++ == ',')
14779 section_flag
= get_absolute_expression ();
14782 if (*input_line_pointer
++ == ',')
14783 section_entry_size
= get_absolute_expression ();
14785 section_entry_size
= 0;
14786 if (*input_line_pointer
++ == ',')
14787 section_alignment
= get_absolute_expression ();
14789 section_alignment
= 0;
14790 /* FIXME: really ignore? */
14791 (void) section_alignment
;
14793 section_name
= xstrdup (section_name
);
14795 /* When using the generic form of .section (as implemented by obj-elf.c),
14796 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14797 traditionally had to fall back on the more common @progbits instead.
14799 There's nothing really harmful in this, since bfd will correct
14800 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14801 means that, for backwards compatibility, the special_section entries
14802 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14804 Even so, we shouldn't force users of the MIPS .section syntax to
14805 incorrectly label the sections as SHT_PROGBITS. The best compromise
14806 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14807 generic type-checking code. */
14808 if (section_type
== SHT_MIPS_DWARF
)
14809 section_type
= SHT_PROGBITS
;
14811 obj_elf_change_section (section_name
, section_type
, section_flag
,
14812 section_entry_size
, 0, 0, 0);
14814 if (now_seg
->name
!= section_name
)
14815 free (section_name
);
14819 mips_enable_auto_align (void)
14825 s_cons (int log_size
)
14827 segment_info_type
*si
= seg_info (now_seg
);
14828 struct insn_label_list
*l
= si
->label_list
;
14830 mips_emit_delays ();
14831 if (log_size
> 0 && auto_align
)
14832 mips_align (log_size
, 0, l
);
14833 cons (1 << log_size
);
14834 mips_clear_insn_labels ();
14838 s_float_cons (int type
)
14840 segment_info_type
*si
= seg_info (now_seg
);
14841 struct insn_label_list
*l
= si
->label_list
;
14843 mips_emit_delays ();
14848 mips_align (3, 0, l
);
14850 mips_align (2, 0, l
);
14854 mips_clear_insn_labels ();
14857 /* Handle .globl. We need to override it because on Irix 5 you are
14860 where foo is an undefined symbol, to mean that foo should be
14861 considered to be the address of a function. */
14864 s_mips_globl (int x ATTRIBUTE_UNUSED
)
14873 name
= input_line_pointer
;
14874 c
= get_symbol_end ();
14875 symbolP
= symbol_find_or_make (name
);
14876 S_SET_EXTERNAL (symbolP
);
14878 *input_line_pointer
= c
;
14879 SKIP_WHITESPACE ();
14881 /* On Irix 5, every global symbol that is not explicitly labelled as
14882 being a function is apparently labelled as being an object. */
14885 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
14886 && (*input_line_pointer
!= ','))
14891 secname
= input_line_pointer
;
14892 c
= get_symbol_end ();
14893 sec
= bfd_get_section_by_name (stdoutput
, secname
);
14895 as_bad (_("%s: no such section"), secname
);
14896 *input_line_pointer
= c
;
14898 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
14899 flag
= BSF_FUNCTION
;
14902 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
14904 c
= *input_line_pointer
;
14907 input_line_pointer
++;
14908 SKIP_WHITESPACE ();
14909 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
14915 demand_empty_rest_of_line ();
14919 s_option (int x ATTRIBUTE_UNUSED
)
14924 opt
= input_line_pointer
;
14925 c
= get_symbol_end ();
14929 /* FIXME: What does this mean? */
14931 else if (strncmp (opt
, "pic", 3) == 0)
14935 i
= atoi (opt
+ 3);
14940 mips_pic
= SVR4_PIC
;
14941 mips_abicalls
= TRUE
;
14944 as_bad (_(".option pic%d not supported"), i
);
14946 if (mips_pic
== SVR4_PIC
)
14948 if (g_switch_seen
&& g_switch_value
!= 0)
14949 as_warn (_("-G may not be used with SVR4 PIC code"));
14950 g_switch_value
= 0;
14951 bfd_set_gp_size (stdoutput
, 0);
14955 as_warn (_("Unrecognized option \"%s\""), opt
);
14957 *input_line_pointer
= c
;
14958 demand_empty_rest_of_line ();
14961 /* This structure is used to hold a stack of .set values. */
14963 struct mips_option_stack
14965 struct mips_option_stack
*next
;
14966 struct mips_set_options options
;
14969 static struct mips_option_stack
*mips_opts_stack
;
14971 /* Handle the .set pseudo-op. */
14974 s_mipsset (int x ATTRIBUTE_UNUSED
)
14976 char *name
= input_line_pointer
, ch
;
14977 const struct mips_ase
*ase
;
14979 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14980 ++input_line_pointer
;
14981 ch
= *input_line_pointer
;
14982 *input_line_pointer
= '\0';
14984 if (strcmp (name
, "reorder") == 0)
14986 if (mips_opts
.noreorder
)
14989 else if (strcmp (name
, "noreorder") == 0)
14991 if (!mips_opts
.noreorder
)
14992 start_noreorder ();
14994 else if (strncmp (name
, "at=", 3) == 0)
14996 char *s
= name
+ 3;
14998 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
14999 as_bad (_("Unrecognized register name `%s'"), s
);
15001 else if (strcmp (name
, "at") == 0)
15003 mips_opts
.at
= ATREG
;
15005 else if (strcmp (name
, "noat") == 0)
15007 mips_opts
.at
= ZERO
;
15009 else if (strcmp (name
, "macro") == 0)
15011 mips_opts
.warn_about_macros
= 0;
15013 else if (strcmp (name
, "nomacro") == 0)
15015 if (mips_opts
.noreorder
== 0)
15016 as_bad (_("`noreorder' must be set before `nomacro'"));
15017 mips_opts
.warn_about_macros
= 1;
15019 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
15021 mips_opts
.nomove
= 0;
15023 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
15025 mips_opts
.nomove
= 1;
15027 else if (strcmp (name
, "bopt") == 0)
15029 mips_opts
.nobopt
= 0;
15031 else if (strcmp (name
, "nobopt") == 0)
15033 mips_opts
.nobopt
= 1;
15035 else if (strcmp (name
, "gp=default") == 0)
15036 mips_opts
.gp32
= file_mips_gp32
;
15037 else if (strcmp (name
, "gp=32") == 0)
15038 mips_opts
.gp32
= 1;
15039 else if (strcmp (name
, "gp=64") == 0)
15041 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15042 as_warn (_("%s isa does not support 64-bit registers"),
15043 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15044 mips_opts
.gp32
= 0;
15046 else if (strcmp (name
, "fp=default") == 0)
15047 mips_opts
.fp32
= file_mips_fp32
;
15048 else if (strcmp (name
, "fp=32") == 0)
15049 mips_opts
.fp32
= 1;
15050 else if (strcmp (name
, "fp=64") == 0)
15052 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15053 as_warn (_("%s isa does not support 64-bit floating point registers"),
15054 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
15055 mips_opts
.fp32
= 0;
15057 else if (strcmp (name
, "softfloat") == 0)
15058 mips_opts
.soft_float
= 1;
15059 else if (strcmp (name
, "hardfloat") == 0)
15060 mips_opts
.soft_float
= 0;
15061 else if (strcmp (name
, "singlefloat") == 0)
15062 mips_opts
.single_float
= 1;
15063 else if (strcmp (name
, "doublefloat") == 0)
15064 mips_opts
.single_float
= 0;
15065 else if (strcmp (name
, "mips16") == 0
15066 || strcmp (name
, "MIPS-16") == 0)
15068 if (mips_opts
.micromips
== 1)
15069 as_fatal (_("`mips16' cannot be used with `micromips'"));
15070 mips_opts
.mips16
= 1;
15072 else if (strcmp (name
, "nomips16") == 0
15073 || strcmp (name
, "noMIPS-16") == 0)
15074 mips_opts
.mips16
= 0;
15075 else if (strcmp (name
, "micromips") == 0)
15077 if (mips_opts
.mips16
== 1)
15078 as_fatal (_("`micromips' cannot be used with `mips16'"));
15079 mips_opts
.micromips
= 1;
15081 else if (strcmp (name
, "nomicromips") == 0)
15082 mips_opts
.micromips
= 0;
15083 else if (name
[0] == 'n'
15085 && (ase
= mips_lookup_ase (name
+ 2)))
15086 mips_set_ase (ase
, FALSE
);
15087 else if ((ase
= mips_lookup_ase (name
)))
15088 mips_set_ase (ase
, TRUE
);
15089 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
15093 /* Permit the user to change the ISA and architecture on the fly.
15094 Needless to say, misuse can cause serious problems. */
15095 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
15098 mips_opts
.isa
= file_mips_isa
;
15099 mips_opts
.arch
= file_mips_arch
;
15101 else if (strncmp (name
, "arch=", 5) == 0)
15103 const struct mips_cpu_info
*p
;
15105 p
= mips_parse_cpu("internal use", name
+ 5);
15107 as_bad (_("unknown architecture %s"), name
+ 5);
15110 mips_opts
.arch
= p
->cpu
;
15111 mips_opts
.isa
= p
->isa
;
15114 else if (strncmp (name
, "mips", 4) == 0)
15116 const struct mips_cpu_info
*p
;
15118 p
= mips_parse_cpu("internal use", name
);
15120 as_bad (_("unknown ISA level %s"), name
+ 4);
15123 mips_opts
.arch
= p
->cpu
;
15124 mips_opts
.isa
= p
->isa
;
15128 as_bad (_("unknown ISA or architecture %s"), name
);
15130 switch (mips_opts
.isa
)
15138 mips_opts
.gp32
= 1;
15139 mips_opts
.fp32
= 1;
15146 mips_opts
.gp32
= 0;
15147 if (mips_opts
.arch
== CPU_R5900
)
15149 mips_opts
.fp32
= 1;
15153 mips_opts
.fp32
= 0;
15157 as_bad (_("unknown ISA level %s"), name
+ 4);
15162 mips_opts
.gp32
= file_mips_gp32
;
15163 mips_opts
.fp32
= file_mips_fp32
;
15166 else if (strcmp (name
, "autoextend") == 0)
15167 mips_opts
.noautoextend
= 0;
15168 else if (strcmp (name
, "noautoextend") == 0)
15169 mips_opts
.noautoextend
= 1;
15170 else if (strcmp (name
, "insn32") == 0)
15171 mips_opts
.insn32
= TRUE
;
15172 else if (strcmp (name
, "noinsn32") == 0)
15173 mips_opts
.insn32
= FALSE
;
15174 else if (strcmp (name
, "push") == 0)
15176 struct mips_option_stack
*s
;
15178 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
15179 s
->next
= mips_opts_stack
;
15180 s
->options
= mips_opts
;
15181 mips_opts_stack
= s
;
15183 else if (strcmp (name
, "pop") == 0)
15185 struct mips_option_stack
*s
;
15187 s
= mips_opts_stack
;
15189 as_bad (_(".set pop with no .set push"));
15192 /* If we're changing the reorder mode we need to handle
15193 delay slots correctly. */
15194 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
15195 start_noreorder ();
15196 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
15199 mips_opts
= s
->options
;
15200 mips_opts_stack
= s
->next
;
15204 else if (strcmp (name
, "sym32") == 0)
15205 mips_opts
.sym32
= TRUE
;
15206 else if (strcmp (name
, "nosym32") == 0)
15207 mips_opts
.sym32
= FALSE
;
15208 else if (strchr (name
, ','))
15210 /* Generic ".set" directive; use the generic handler. */
15211 *input_line_pointer
= ch
;
15212 input_line_pointer
= name
;
15218 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
15220 mips_check_isa_supports_ases ();
15221 *input_line_pointer
= ch
;
15222 demand_empty_rest_of_line ();
15225 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15226 .option pic2. It means to generate SVR4 PIC calls. */
15229 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
15231 mips_pic
= SVR4_PIC
;
15232 mips_abicalls
= TRUE
;
15234 if (g_switch_seen
&& g_switch_value
!= 0)
15235 as_warn (_("-G may not be used with SVR4 PIC code"));
15236 g_switch_value
= 0;
15238 bfd_set_gp_size (stdoutput
, 0);
15239 demand_empty_rest_of_line ();
15242 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15243 PIC code. It sets the $gp register for the function based on the
15244 function address, which is in the register named in the argument.
15245 This uses a relocation against _gp_disp, which is handled specially
15246 by the linker. The result is:
15247 lui $gp,%hi(_gp_disp)
15248 addiu $gp,$gp,%lo(_gp_disp)
15249 addu $gp,$gp,.cpload argument
15250 The .cpload argument is normally $25 == $t9.
15252 The -mno-shared option changes this to:
15253 lui $gp,%hi(__gnu_local_gp)
15254 addiu $gp,$gp,%lo(__gnu_local_gp)
15255 and the argument is ignored. This saves an instruction, but the
15256 resulting code is not position independent; it uses an absolute
15257 address for __gnu_local_gp. Thus code assembled with -mno-shared
15258 can go into an ordinary executable, but not into a shared library. */
15261 s_cpload (int ignore ATTRIBUTE_UNUSED
)
15267 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15268 .cpload is ignored. */
15269 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15275 if (mips_opts
.mips16
)
15277 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15278 ignore_rest_of_line ();
15282 /* .cpload should be in a .set noreorder section. */
15283 if (mips_opts
.noreorder
== 0)
15284 as_warn (_(".cpload not in noreorder section"));
15286 reg
= tc_get_register (0);
15288 /* If we need to produce a 64-bit address, we are better off using
15289 the default instruction sequence. */
15290 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
15292 ex
.X_op
= O_symbol
;
15293 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
15295 ex
.X_op_symbol
= NULL
;
15296 ex
.X_add_number
= 0;
15298 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15299 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15301 mips_mark_labels ();
15302 mips_assembling_insn
= TRUE
;
15305 macro_build_lui (&ex
, mips_gp_register
);
15306 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15307 mips_gp_register
, BFD_RELOC_LO16
);
15309 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
15310 mips_gp_register
, reg
);
15313 mips_assembling_insn
= FALSE
;
15314 demand_empty_rest_of_line ();
15317 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15318 .cpsetup $reg1, offset|$reg2, label
15320 If offset is given, this results in:
15321 sd $gp, offset($sp)
15322 lui $gp, %hi(%neg(%gp_rel(label)))
15323 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15324 daddu $gp, $gp, $reg1
15326 If $reg2 is given, this results in:
15327 daddu $reg2, $gp, $0
15328 lui $gp, %hi(%neg(%gp_rel(label)))
15329 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15330 daddu $gp, $gp, $reg1
15331 $reg1 is normally $25 == $t9.
15333 The -mno-shared option replaces the last three instructions with
15335 addiu $gp,$gp,%lo(_gp) */
15338 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
15340 expressionS ex_off
;
15341 expressionS ex_sym
;
15344 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15345 We also need NewABI support. */
15346 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15352 if (mips_opts
.mips16
)
15354 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15355 ignore_rest_of_line ();
15359 reg1
= tc_get_register (0);
15360 SKIP_WHITESPACE ();
15361 if (*input_line_pointer
!= ',')
15363 as_bad (_("missing argument separator ',' for .cpsetup"));
15367 ++input_line_pointer
;
15368 SKIP_WHITESPACE ();
15369 if (*input_line_pointer
== '$')
15371 mips_cpreturn_register
= tc_get_register (0);
15372 mips_cpreturn_offset
= -1;
15376 mips_cpreturn_offset
= get_absolute_expression ();
15377 mips_cpreturn_register
= -1;
15379 SKIP_WHITESPACE ();
15380 if (*input_line_pointer
!= ',')
15382 as_bad (_("missing argument separator ',' for .cpsetup"));
15386 ++input_line_pointer
;
15387 SKIP_WHITESPACE ();
15388 expression (&ex_sym
);
15390 mips_mark_labels ();
15391 mips_assembling_insn
= TRUE
;
15394 if (mips_cpreturn_register
== -1)
15396 ex_off
.X_op
= O_constant
;
15397 ex_off
.X_add_symbol
= NULL
;
15398 ex_off
.X_op_symbol
= NULL
;
15399 ex_off
.X_add_number
= mips_cpreturn_offset
;
15401 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
15402 BFD_RELOC_LO16
, SP
);
15405 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
15406 mips_gp_register
, 0);
15408 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
15410 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
15411 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
15414 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
15415 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
15416 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
15418 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
15419 mips_gp_register
, reg1
);
15425 ex
.X_op
= O_symbol
;
15426 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
15427 ex
.X_op_symbol
= NULL
;
15428 ex
.X_add_number
= 0;
15430 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15431 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
15433 macro_build_lui (&ex
, mips_gp_register
);
15434 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
15435 mips_gp_register
, BFD_RELOC_LO16
);
15440 mips_assembling_insn
= FALSE
;
15441 demand_empty_rest_of_line ();
15445 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
15447 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15448 .cplocal is ignored. */
15449 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15455 if (mips_opts
.mips16
)
15457 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15458 ignore_rest_of_line ();
15462 mips_gp_register
= tc_get_register (0);
15463 demand_empty_rest_of_line ();
15466 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15467 offset from $sp. The offset is remembered, and after making a PIC
15468 call $gp is restored from that location. */
15471 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
15475 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15476 .cprestore is ignored. */
15477 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
15483 if (mips_opts
.mips16
)
15485 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15486 ignore_rest_of_line ();
15490 mips_cprestore_offset
= get_absolute_expression ();
15491 mips_cprestore_valid
= 1;
15493 ex
.X_op
= O_constant
;
15494 ex
.X_add_symbol
= NULL
;
15495 ex
.X_op_symbol
= NULL
;
15496 ex
.X_add_number
= mips_cprestore_offset
;
15498 mips_mark_labels ();
15499 mips_assembling_insn
= TRUE
;
15502 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
15503 SP
, HAVE_64BIT_ADDRESSES
);
15506 mips_assembling_insn
= FALSE
;
15507 demand_empty_rest_of_line ();
15510 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15511 was given in the preceding .cpsetup, it results in:
15512 ld $gp, offset($sp)
15514 If a register $reg2 was given there, it results in:
15515 daddu $gp, $reg2, $0 */
15518 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
15522 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15523 We also need NewABI support. */
15524 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15530 if (mips_opts
.mips16
)
15532 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15533 ignore_rest_of_line ();
15537 mips_mark_labels ();
15538 mips_assembling_insn
= TRUE
;
15541 if (mips_cpreturn_register
== -1)
15543 ex
.X_op
= O_constant
;
15544 ex
.X_add_symbol
= NULL
;
15545 ex
.X_op_symbol
= NULL
;
15546 ex
.X_add_number
= mips_cpreturn_offset
;
15548 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
15551 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
15552 mips_cpreturn_register
, 0);
15555 mips_assembling_insn
= FALSE
;
15556 demand_empty_rest_of_line ();
15559 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15560 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15561 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15562 debug information or MIPS16 TLS. */
15565 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
15566 bfd_reloc_code_real_type rtype
)
15573 if (ex
.X_op
!= O_symbol
)
15575 as_bad (_("Unsupported use of %s"), dirstr
);
15576 ignore_rest_of_line ();
15579 p
= frag_more (bytes
);
15580 md_number_to_chars (p
, 0, bytes
);
15581 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
15582 demand_empty_rest_of_line ();
15583 mips_clear_insn_labels ();
15586 /* Handle .dtprelword. */
15589 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
15591 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
15594 /* Handle .dtpreldword. */
15597 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
15599 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
15602 /* Handle .tprelword. */
15605 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
15607 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
15610 /* Handle .tpreldword. */
15613 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
15615 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
15618 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15619 code. It sets the offset to use in gp_rel relocations. */
15622 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
15624 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15625 We also need NewABI support. */
15626 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
15632 mips_gprel_offset
= get_absolute_expression ();
15634 demand_empty_rest_of_line ();
15637 /* Handle the .gpword pseudo-op. This is used when generating PIC
15638 code. It generates a 32 bit GP relative reloc. */
15641 s_gpword (int ignore ATTRIBUTE_UNUSED
)
15643 segment_info_type
*si
;
15644 struct insn_label_list
*l
;
15648 /* When not generating PIC code, this is treated as .word. */
15649 if (mips_pic
!= SVR4_PIC
)
15655 si
= seg_info (now_seg
);
15656 l
= si
->label_list
;
15657 mips_emit_delays ();
15659 mips_align (2, 0, l
);
15662 mips_clear_insn_labels ();
15664 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15666 as_bad (_("Unsupported use of .gpword"));
15667 ignore_rest_of_line ();
15671 md_number_to_chars (p
, 0, 4);
15672 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15673 BFD_RELOC_GPREL32
);
15675 demand_empty_rest_of_line ();
15679 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
15681 segment_info_type
*si
;
15682 struct insn_label_list
*l
;
15686 /* When not generating PIC code, this is treated as .dword. */
15687 if (mips_pic
!= SVR4_PIC
)
15693 si
= seg_info (now_seg
);
15694 l
= si
->label_list
;
15695 mips_emit_delays ();
15697 mips_align (3, 0, l
);
15700 mips_clear_insn_labels ();
15702 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15704 as_bad (_("Unsupported use of .gpdword"));
15705 ignore_rest_of_line ();
15709 md_number_to_chars (p
, 0, 8);
15710 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15711 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
15713 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15714 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
15715 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
15717 demand_empty_rest_of_line ();
15720 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15721 tables. It generates a R_MIPS_EH reloc. */
15724 s_ehword (int ignore ATTRIBUTE_UNUSED
)
15729 mips_emit_delays ();
15732 mips_clear_insn_labels ();
15734 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
15736 as_bad (_("Unsupported use of .ehword"));
15737 ignore_rest_of_line ();
15741 md_number_to_chars (p
, 0, 4);
15742 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
15743 BFD_RELOC_MIPS_EH
);
15745 demand_empty_rest_of_line ();
15748 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15749 tables in SVR4 PIC code. */
15752 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
15756 /* This is ignored when not generating SVR4 PIC code. */
15757 if (mips_pic
!= SVR4_PIC
)
15763 mips_mark_labels ();
15764 mips_assembling_insn
= TRUE
;
15766 /* Add $gp to the register named as an argument. */
15768 reg
= tc_get_register (0);
15769 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
15772 mips_assembling_insn
= FALSE
;
15773 demand_empty_rest_of_line ();
15776 /* Handle the .insn pseudo-op. This marks instruction labels in
15777 mips16/micromips mode. This permits the linker to handle them specially,
15778 such as generating jalx instructions when needed. We also make
15779 them odd for the duration of the assembly, in order to generate the
15780 right sort of code. We will make them even in the adjust_symtab
15781 routine, while leaving them marked. This is convenient for the
15782 debugger and the disassembler. The linker knows to make them odd
15786 s_insn (int ignore ATTRIBUTE_UNUSED
)
15788 mips_mark_labels ();
15790 demand_empty_rest_of_line ();
15793 /* Handle the .nan pseudo-op. */
15796 s_nan (int ignore ATTRIBUTE_UNUSED
)
15798 static const char str_legacy
[] = "legacy";
15799 static const char str_2008
[] = "2008";
15802 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
15804 if (i
== sizeof (str_2008
) - 1
15805 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
15806 mips_flag_nan2008
= TRUE
;
15807 else if (i
== sizeof (str_legacy
) - 1
15808 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
15809 mips_flag_nan2008
= FALSE
;
15811 as_bad (_("Bad .nan directive"));
15813 input_line_pointer
+= i
;
15814 demand_empty_rest_of_line ();
15817 /* Handle a .stab[snd] directive. Ideally these directives would be
15818 implemented in a transparent way, so that removing them would not
15819 have any effect on the generated instructions. However, s_stab
15820 internally changes the section, so in practice we need to decide
15821 now whether the preceding label marks compressed code. We do not
15822 support changing the compression mode of a label after a .stab*
15823 directive, such as in:
15829 so the current mode wins. */
15832 s_mips_stab (int type
)
15834 mips_mark_labels ();
15838 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15841 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
15848 name
= input_line_pointer
;
15849 c
= get_symbol_end ();
15850 symbolP
= symbol_find_or_make (name
);
15851 S_SET_WEAK (symbolP
);
15852 *input_line_pointer
= c
;
15854 SKIP_WHITESPACE ();
15856 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
15858 if (S_IS_DEFINED (symbolP
))
15860 as_bad (_("ignoring attempt to redefine symbol %s"),
15861 S_GET_NAME (symbolP
));
15862 ignore_rest_of_line ();
15866 if (*input_line_pointer
== ',')
15868 ++input_line_pointer
;
15869 SKIP_WHITESPACE ();
15873 if (exp
.X_op
!= O_symbol
)
15875 as_bad (_("bad .weakext directive"));
15876 ignore_rest_of_line ();
15879 symbol_set_value_expression (symbolP
, &exp
);
15882 demand_empty_rest_of_line ();
15885 /* Parse a register string into a number. Called from the ECOFF code
15886 to parse .frame. The argument is non-zero if this is the frame
15887 register, so that we can record it in mips_frame_reg. */
15890 tc_get_register (int frame
)
15894 SKIP_WHITESPACE ();
15895 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
15899 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
15900 mips_frame_reg_valid
= 1;
15901 mips_cprestore_valid
= 0;
15907 md_section_align (asection
*seg
, valueT addr
)
15909 int align
= bfd_get_section_alignment (stdoutput
, seg
);
15911 /* We don't need to align ELF sections to the full alignment.
15912 However, Irix 5 may prefer that we align them at least to a 16
15913 byte boundary. We don't bother to align the sections if we
15914 are targeted for an embedded system. */
15915 if (strncmp (TARGET_OS
, "elf", 3) == 0)
15920 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
15923 /* Utility routine, called from above as well. If called while the
15924 input file is still being read, it's only an approximation. (For
15925 example, a symbol may later become defined which appeared to be
15926 undefined earlier.) */
15929 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
15934 if (g_switch_value
> 0)
15936 const char *symname
;
15939 /* Find out whether this symbol can be referenced off the $gp
15940 register. It can be if it is smaller than the -G size or if
15941 it is in the .sdata or .sbss section. Certain symbols can
15942 not be referenced off the $gp, although it appears as though
15944 symname
= S_GET_NAME (sym
);
15945 if (symname
!= (const char *) NULL
15946 && (strcmp (symname
, "eprol") == 0
15947 || strcmp (symname
, "etext") == 0
15948 || strcmp (symname
, "_gp") == 0
15949 || strcmp (symname
, "edata") == 0
15950 || strcmp (symname
, "_fbss") == 0
15951 || strcmp (symname
, "_fdata") == 0
15952 || strcmp (symname
, "_ftext") == 0
15953 || strcmp (symname
, "end") == 0
15954 || strcmp (symname
, "_gp_disp") == 0))
15956 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
15958 #ifndef NO_ECOFF_DEBUGGING
15959 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
15960 && (symbol_get_obj (sym
)->ecoff_extern_size
15961 <= g_switch_value
))
15963 /* We must defer this decision until after the whole
15964 file has been read, since there might be a .extern
15965 after the first use of this symbol. */
15966 || (before_relaxing
15967 #ifndef NO_ECOFF_DEBUGGING
15968 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
15970 && S_GET_VALUE (sym
) == 0)
15971 || (S_GET_VALUE (sym
) != 0
15972 && S_GET_VALUE (sym
) <= g_switch_value
)))
15976 const char *segname
;
15978 segname
= segment_name (S_GET_SEGMENT (sym
));
15979 gas_assert (strcmp (segname
, ".lit8") != 0
15980 && strcmp (segname
, ".lit4") != 0);
15981 change
= (strcmp (segname
, ".sdata") != 0
15982 && strcmp (segname
, ".sbss") != 0
15983 && strncmp (segname
, ".sdata.", 7) != 0
15984 && strncmp (segname
, ".sbss.", 6) != 0
15985 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
15986 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
15991 /* We are not optimizing for the $gp register. */
15996 /* Return true if the given symbol should be considered local for SVR4 PIC. */
15999 pic_need_relax (symbolS
*sym
, asection
*segtype
)
16003 /* Handle the case of a symbol equated to another symbol. */
16004 while (symbol_equated_reloc_p (sym
))
16008 /* It's possible to get a loop here in a badly written program. */
16009 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
16015 if (symbol_section_p (sym
))
16018 symsec
= S_GET_SEGMENT (sym
);
16020 /* This must duplicate the test in adjust_reloc_syms. */
16021 return (!bfd_is_und_section (symsec
)
16022 && !bfd_is_abs_section (symsec
)
16023 && !bfd_is_com_section (symsec
)
16024 && !s_is_linkonce (sym
, segtype
)
16025 /* A global or weak symbol is treated as external. */
16026 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
16030 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16031 extended opcode. SEC is the section the frag is in. */
16034 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
16037 const struct mips_int_operand
*operand
;
16042 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
16044 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
16047 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
16048 operand
= mips16_immed_operand (type
, FALSE
);
16050 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
16051 val
= S_GET_VALUE (fragp
->fr_symbol
);
16052 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
16054 if (operand
->root
.type
== OP_PCREL
)
16056 const struct mips_pcrel_operand
*pcrel_op
;
16060 /* We won't have the section when we are called from
16061 mips_relax_frag. However, we will always have been called
16062 from md_estimate_size_before_relax first. If this is a
16063 branch to a different section, we mark it as such. If SEC is
16064 NULL, and the frag is not marked, then it must be a branch to
16065 the same section. */
16066 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
16069 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
16074 /* Must have been called from md_estimate_size_before_relax. */
16077 fragp
->fr_subtype
=
16078 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16080 /* FIXME: We should support this, and let the linker
16081 catch branches and loads that are out of range. */
16082 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
16083 _("unsupported PC relative reference to different section"));
16087 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
16088 /* Assume non-extended on the first relaxation pass.
16089 The address we have calculated will be bogus if this is
16090 a forward branch to another frag, as the forward frag
16091 will have fr_address == 0. */
16095 /* In this case, we know for sure that the symbol fragment is in
16096 the same section. If the relax_marker of the symbol fragment
16097 differs from the relax_marker of this fragment, we have not
16098 yet adjusted the symbol fragment fr_address. We want to add
16099 in STRETCH in order to get a better estimate of the address.
16100 This particularly matters because of the shift bits. */
16102 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16106 /* Adjust stretch for any alignment frag. Note that if have
16107 been expanding the earlier code, the symbol may be
16108 defined in what appears to be an earlier frag. FIXME:
16109 This doesn't handle the fr_subtype field, which specifies
16110 a maximum number of bytes to skip when doing an
16112 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16114 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16117 stretch
= - ((- stretch
)
16118 & ~ ((1 << (int) f
->fr_offset
) - 1));
16120 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16129 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16131 /* The base address rules are complicated. The base address of
16132 a branch is the following instruction. The base address of a
16133 PC relative load or add is the instruction itself, but if it
16134 is in a delay slot (in which case it can not be extended) use
16135 the address of the instruction whose delay slot it is in. */
16136 if (pcrel_op
->include_isa_bit
)
16140 /* If we are currently assuming that this frag should be
16141 extended, then, the current address is two bytes
16143 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16146 /* Ignore the low bit in the target, since it will be set
16147 for a text label. */
16150 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
16152 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
16155 val
-= addr
& -(1 << pcrel_op
->align_log2
);
16157 /* If any of the shifted bits are set, we must use an extended
16158 opcode. If the address depends on the size of this
16159 instruction, this can lead to a loop, so we arrange to always
16160 use an extended opcode. We only check this when we are in
16161 the main relaxation loop, when SEC is NULL. */
16162 if ((val
& ((1 << operand
->shift
) - 1)) != 0 && sec
== NULL
)
16164 fragp
->fr_subtype
=
16165 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16169 /* If we are about to mark a frag as extended because the value
16170 is precisely the next value above maxtiny, then there is a
16171 chance of an infinite loop as in the following code:
16176 In this case when the la is extended, foo is 0x3fc bytes
16177 away, so the la can be shrunk, but then foo is 0x400 away, so
16178 the la must be extended. To avoid this loop, we mark the
16179 frag as extended if it was small, and is about to become
16180 extended with the next value above maxtiny. */
16181 maxtiny
= mips_int_operand_max (operand
);
16182 if (val
== maxtiny
+ (1 << operand
->shift
)
16183 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
16186 fragp
->fr_subtype
=
16187 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
16191 else if (symsec
!= absolute_section
&& sec
!= NULL
)
16192 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
16194 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
16197 /* Compute the length of a branch sequence, and adjust the
16198 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16199 worst-case length is computed, with UPDATE being used to indicate
16200 whether an unconditional (-1), branch-likely (+1) or regular (0)
16201 branch is to be computed. */
16203 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16205 bfd_boolean toofar
;
16209 && S_IS_DEFINED (fragp
->fr_symbol
)
16210 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16215 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16217 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16221 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
16224 /* If the symbol is not defined or it's in a different segment,
16225 assume the user knows what's going on and emit a short
16231 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16233 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
16234 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
16235 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
16236 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
16242 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
16245 if (mips_pic
!= NO_PIC
)
16247 /* Additional space for PIC loading of target address. */
16249 if (mips_opts
.isa
== ISA_MIPS1
)
16250 /* Additional space for $at-stabilizing nop. */
16254 /* If branch is conditional. */
16255 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
16262 /* Compute the length of a branch sequence, and adjust the
16263 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16264 worst-case length is computed, with UPDATE being used to indicate
16265 whether an unconditional (-1), or regular (0) branch is to be
16269 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16271 bfd_boolean toofar
;
16275 && S_IS_DEFINED (fragp
->fr_symbol
)
16276 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16281 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16282 /* Ignore the low bit in the target, since it will be set
16283 for a text label. */
16284 if ((val
& 1) != 0)
16287 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16291 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
16294 /* If the symbol is not defined or it's in a different segment,
16295 assume the user knows what's going on and emit a short
16301 if (fragp
&& update
16302 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16303 fragp
->fr_subtype
= (toofar
16304 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
16305 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
16310 bfd_boolean compact_known
= fragp
!= NULL
;
16311 bfd_boolean compact
= FALSE
;
16312 bfd_boolean uncond
;
16315 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16317 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
16319 uncond
= update
< 0;
16321 /* If label is out of range, we turn branch <br>:
16323 <br> label # 4 bytes
16329 nop # 2 bytes if compact && !PIC
16332 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
16335 /* If assembling PIC code, we further turn:
16341 lw/ld at, %got(label)(gp) # 4 bytes
16342 d/addiu at, %lo(label) # 4 bytes
16345 if (mips_pic
!= NO_PIC
)
16348 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16350 <brneg> 0f # 4 bytes
16351 nop # 2 bytes if !compact
16354 length
+= (compact_known
&& compact
) ? 4 : 6;
16360 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16361 bit accordingly. */
16364 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
16366 bfd_boolean toofar
;
16369 && S_IS_DEFINED (fragp
->fr_symbol
)
16370 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
16376 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
16377 /* Ignore the low bit in the target, since it will be set
16378 for a text label. */
16379 if ((val
& 1) != 0)
16382 /* Assume this is a 2-byte branch. */
16383 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
16385 /* We try to avoid the infinite loop by not adding 2 more bytes for
16390 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16392 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
16393 else if (type
== 'E')
16394 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
16399 /* If the symbol is not defined or it's in a different segment,
16400 we emit a normal 32-bit branch. */
16403 if (fragp
&& update
16404 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16406 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
16407 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
16415 /* Estimate the size of a frag before relaxing. Unless this is the
16416 mips16, we are not really relaxing here, and the final size is
16417 encoded in the subtype information. For the mips16, we have to
16418 decide whether we are using an extended opcode or not. */
16421 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
16425 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16428 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
16430 return fragp
->fr_var
;
16433 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
16434 /* We don't want to modify the EXTENDED bit here; it might get us
16435 into infinite loops. We change it only in mips_relax_frag(). */
16436 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
16438 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16442 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16443 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
16444 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16445 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
16446 fragp
->fr_var
= length
;
16451 if (mips_pic
== NO_PIC
)
16452 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
16453 else if (mips_pic
== SVR4_PIC
)
16454 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
16455 else if (mips_pic
== VXWORKS_PIC
)
16456 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16463 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
16464 return -RELAX_FIRST (fragp
->fr_subtype
);
16467 return -RELAX_SECOND (fragp
->fr_subtype
);
16470 /* This is called to see whether a reloc against a defined symbol
16471 should be converted into a reloc against a section. */
16474 mips_fix_adjustable (fixS
*fixp
)
16476 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
16477 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16480 if (fixp
->fx_addsy
== NULL
)
16483 /* If symbol SYM is in a mergeable section, relocations of the form
16484 SYM + 0 can usually be made section-relative. The mergeable data
16485 is then identified by the section offset rather than by the symbol.
16487 However, if we're generating REL LO16 relocations, the offset is split
16488 between the LO16 and parterning high part relocation. The linker will
16489 need to recalculate the complete offset in order to correctly identify
16492 The linker has traditionally not looked for the parterning high part
16493 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16494 placed anywhere. Rather than break backwards compatibility by changing
16495 this, it seems better not to force the issue, and instead keep the
16496 original symbol. This will work with either linker behavior. */
16497 if ((lo16_reloc_p (fixp
->fx_r_type
)
16498 || reloc_needs_lo_p (fixp
->fx_r_type
))
16499 && HAVE_IN_PLACE_ADDENDS
16500 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
16503 /* There is no place to store an in-place offset for JALR relocations.
16504 Likewise an in-range offset of limited PC-relative relocations may
16505 overflow the in-place relocatable field if recalculated against the
16506 start address of the symbol's containing section. */
16507 if (HAVE_IN_PLACE_ADDENDS
16508 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
16509 || jalr_reloc_p (fixp
->fx_r_type
)))
16512 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16513 to a floating-point stub. The same is true for non-R_MIPS16_26
16514 relocations against MIPS16 functions; in this case, the stub becomes
16515 the function's canonical address.
16517 Floating-point stubs are stored in unique .mips16.call.* or
16518 .mips16.fn.* sections. If a stub T for function F is in section S,
16519 the first relocation in section S must be against F; this is how the
16520 linker determines the target function. All relocations that might
16521 resolve to T must also be against F. We therefore have the following
16522 restrictions, which are given in an intentionally-redundant way:
16524 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16527 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16528 if that stub might be used.
16530 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16533 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16534 that stub might be used.
16536 There is a further restriction:
16538 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16539 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16540 targets with in-place addends; the relocation field cannot
16541 encode the low bit.
16543 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16544 against a MIPS16 symbol. We deal with (5) by by not reducing any
16545 such relocations on REL targets.
16547 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16548 relocation against some symbol R, no relocation against R may be
16549 reduced. (Note that this deals with (2) as well as (1) because
16550 relocations against global symbols will never be reduced on ELF
16551 targets.) This approach is a little simpler than trying to detect
16552 stub sections, and gives the "all or nothing" per-symbol consistency
16553 that we have for MIPS16 symbols. */
16554 if (fixp
->fx_subsy
== NULL
16555 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
16556 || *symbol_get_tc (fixp
->fx_addsy
)
16557 || (HAVE_IN_PLACE_ADDENDS
16558 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
16559 && jmp_reloc_p (fixp
->fx_r_type
))))
16565 /* Translate internal representation of relocation info to BFD target
16569 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
16571 static arelent
*retval
[4];
16573 bfd_reloc_code_real_type code
;
16575 memset (retval
, 0, sizeof(retval
));
16576 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
16577 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
16578 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
16579 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
16581 if (fixp
->fx_pcrel
)
16583 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
16584 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
16585 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
16586 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
16587 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
16589 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16590 Relocations want only the symbol offset. */
16591 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
16594 reloc
->addend
= fixp
->fx_addnumber
;
16596 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16597 entry to be used in the relocation's section offset. */
16598 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
16600 reloc
->address
= reloc
->addend
;
16604 code
= fixp
->fx_r_type
;
16606 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
16607 if (reloc
->howto
== NULL
)
16609 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
16610 _("Can not represent %s relocation in this object file format"),
16611 bfd_get_reloc_code_name (code
));
16618 /* Relax a machine dependent frag. This returns the amount by which
16619 the current size of the frag should change. */
16622 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16624 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16626 offsetT old_var
= fragp
->fr_var
;
16628 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
16630 return fragp
->fr_var
- old_var
;
16633 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16635 offsetT old_var
= fragp
->fr_var
;
16636 offsetT new_var
= 4;
16638 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
16639 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
16640 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
16641 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
16642 fragp
->fr_var
= new_var
;
16644 return new_var
- old_var
;
16647 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
16650 if (mips16_extended_frag (fragp
, NULL
, stretch
))
16652 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16654 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
16659 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
16661 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
16668 /* Convert a machine dependent frag. */
16671 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
16673 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
16676 unsigned long insn
;
16680 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16681 insn
= read_insn (buf
);
16683 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
16685 /* We generate a fixup instead of applying it right now
16686 because, if there are linker relaxations, we're going to
16687 need the relocations. */
16688 exp
.X_op
= O_symbol
;
16689 exp
.X_add_symbol
= fragp
->fr_symbol
;
16690 exp
.X_add_number
= fragp
->fr_offset
;
16692 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16693 BFD_RELOC_16_PCREL_S2
);
16694 fixp
->fx_file
= fragp
->fr_file
;
16695 fixp
->fx_line
= fragp
->fr_line
;
16697 buf
= write_insn (buf
, insn
);
16703 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16704 _("Relaxed out-of-range branch into a jump"));
16706 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
16709 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16711 /* Reverse the branch. */
16712 switch ((insn
>> 28) & 0xf)
16715 /* bc[0-3][tf]l? instructions can have the condition
16716 reversed by tweaking a single TF bit, and their
16717 opcodes all have 0x4???????. */
16718 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
16719 insn
^= 0x00010000;
16723 /* bltz 0x04000000 bgez 0x04010000
16724 bltzal 0x04100000 bgezal 0x04110000 */
16725 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
16726 insn
^= 0x00010000;
16730 /* beq 0x10000000 bne 0x14000000
16731 blez 0x18000000 bgtz 0x1c000000 */
16732 insn
^= 0x04000000;
16740 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16742 /* Clear the and-link bit. */
16743 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
16745 /* bltzal 0x04100000 bgezal 0x04110000
16746 bltzall 0x04120000 bgezall 0x04130000 */
16747 insn
&= ~0x00100000;
16750 /* Branch over the branch (if the branch was likely) or the
16751 full jump (not likely case). Compute the offset from the
16752 current instruction to branch to. */
16753 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16757 /* How many bytes in instructions we've already emitted? */
16758 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16759 /* How many bytes in instructions from here to the end? */
16760 i
= fragp
->fr_var
- i
;
16762 /* Convert to instruction count. */
16764 /* Branch counts from the next instruction. */
16767 /* Branch over the jump. */
16768 buf
= write_insn (buf
, insn
);
16771 buf
= write_insn (buf
, 0);
16773 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
16775 /* beql $0, $0, 2f */
16777 /* Compute the PC offset from the current instruction to
16778 the end of the variable frag. */
16779 /* How many bytes in instructions we've already emitted? */
16780 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
16781 /* How many bytes in instructions from here to the end? */
16782 i
= fragp
->fr_var
- i
;
16783 /* Convert to instruction count. */
16785 /* Don't decrement i, because we want to branch over the
16789 buf
= write_insn (buf
, insn
);
16790 buf
= write_insn (buf
, 0);
16794 if (mips_pic
== NO_PIC
)
16797 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
16798 ? 0x0c000000 : 0x08000000);
16799 exp
.X_op
= O_symbol
;
16800 exp
.X_add_symbol
= fragp
->fr_symbol
;
16801 exp
.X_add_number
= fragp
->fr_offset
;
16803 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16804 FALSE
, BFD_RELOC_MIPS_JMP
);
16805 fixp
->fx_file
= fragp
->fr_file
;
16806 fixp
->fx_line
= fragp
->fr_line
;
16808 buf
= write_insn (buf
, insn
);
16812 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
16814 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16815 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
16816 insn
|= at
<< OP_SH_RT
;
16817 exp
.X_op
= O_symbol
;
16818 exp
.X_add_symbol
= fragp
->fr_symbol
;
16819 exp
.X_add_number
= fragp
->fr_offset
;
16821 if (fragp
->fr_offset
)
16823 exp
.X_add_symbol
= make_expr_symbol (&exp
);
16824 exp
.X_add_number
= 0;
16827 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16828 FALSE
, BFD_RELOC_MIPS_GOT16
);
16829 fixp
->fx_file
= fragp
->fr_file
;
16830 fixp
->fx_line
= fragp
->fr_line
;
16832 buf
= write_insn (buf
, insn
);
16834 if (mips_opts
.isa
== ISA_MIPS1
)
16836 buf
= write_insn (buf
, 0);
16838 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16839 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
16840 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
16842 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
16843 FALSE
, BFD_RELOC_LO16
);
16844 fixp
->fx_file
= fragp
->fr_file
;
16845 fixp
->fx_line
= fragp
->fr_line
;
16847 buf
= write_insn (buf
, insn
);
16850 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
16854 insn
|= at
<< OP_SH_RS
;
16856 buf
= write_insn (buf
, insn
);
16860 fragp
->fr_fix
+= fragp
->fr_var
;
16861 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16865 /* Relax microMIPS branches. */
16866 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
16868 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16869 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
16870 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
16871 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
16872 bfd_boolean short_ds
;
16873 unsigned long insn
;
16877 exp
.X_op
= O_symbol
;
16878 exp
.X_add_symbol
= fragp
->fr_symbol
;
16879 exp
.X_add_number
= fragp
->fr_offset
;
16881 fragp
->fr_fix
+= fragp
->fr_var
;
16883 /* Handle 16-bit branches that fit or are forced to fit. */
16884 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
16886 /* We generate a fixup instead of applying it right now,
16887 because if there is linker relaxation, we're going to
16888 need the relocations. */
16890 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16891 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
16892 else if (type
== 'E')
16893 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
16894 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
16898 fixp
->fx_file
= fragp
->fr_file
;
16899 fixp
->fx_line
= fragp
->fr_line
;
16901 /* These relocations can have an addend that won't fit in
16903 fixp
->fx_no_overflow
= 1;
16908 /* Handle 32-bit branches that fit or are forced to fit. */
16909 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16910 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16912 /* We generate a fixup instead of applying it right now,
16913 because if there is linker relaxation, we're going to
16914 need the relocations. */
16915 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
16916 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
16917 fixp
->fx_file
= fragp
->fr_file
;
16918 fixp
->fx_line
= fragp
->fr_line
;
16924 /* Relax 16-bit branches to 32-bit branches. */
16927 insn
= read_compressed_insn (buf
, 2);
16929 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
16930 insn
= 0x94000000; /* beq */
16931 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16933 unsigned long regno
;
16935 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
16936 regno
= micromips_to_32_reg_d_map
[regno
];
16937 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
16938 insn
|= regno
<< MICROMIPSOP_SH_RS
;
16943 /* Nothing else to do, just write it out. */
16944 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
16945 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
16947 buf
= write_compressed_insn (buf
, insn
, 4);
16948 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
16953 insn
= read_compressed_insn (buf
, 4);
16955 /* Relax 32-bit branches to a sequence of instructions. */
16956 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
16957 _("Relaxed out-of-range branch into a jump"));
16959 /* Set the short-delay-slot bit. */
16960 short_ds
= al
&& (insn
& 0x02000000) != 0;
16962 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
16966 /* Reverse the branch. */
16967 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
16968 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
16969 insn
^= 0x20000000;
16970 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
16971 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
16972 || (insn
& 0xffe00000) == 0x40800000 /* blez */
16973 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
16974 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
16975 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
16976 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
16977 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
16978 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
16979 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
16980 insn
^= 0x00400000;
16981 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
16982 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
16983 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
16984 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
16985 insn
^= 0x00200000;
16991 /* Clear the and-link and short-delay-slot bits. */
16992 gas_assert ((insn
& 0xfda00000) == 0x40200000);
16994 /* bltzal 0x40200000 bgezal 0x40600000 */
16995 /* bltzals 0x42200000 bgezals 0x42600000 */
16996 insn
&= ~0x02200000;
16999 /* Make a label at the end for use with the branch. */
17000 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
17001 micromips_label_inc ();
17002 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
17005 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
17006 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
17007 fixp
->fx_file
= fragp
->fr_file
;
17008 fixp
->fx_line
= fragp
->fr_line
;
17010 /* Branch over the jump. */
17011 buf
= write_compressed_insn (buf
, insn
, 4);
17014 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17017 if (mips_pic
== NO_PIC
)
17019 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
17021 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17022 insn
= al
? jal
: 0xd4000000;
17024 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17025 BFD_RELOC_MICROMIPS_JMP
);
17026 fixp
->fx_file
= fragp
->fr_file
;
17027 fixp
->fx_line
= fragp
->fr_line
;
17029 buf
= write_compressed_insn (buf
, insn
, 4);
17032 buf
= write_compressed_insn (buf
, 0x0c00, 2);
17036 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
17037 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
17038 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
17040 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17041 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
17042 insn
|= at
<< MICROMIPSOP_SH_RT
;
17044 if (exp
.X_add_number
)
17046 exp
.X_add_symbol
= make_expr_symbol (&exp
);
17047 exp
.X_add_number
= 0;
17050 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17051 BFD_RELOC_MICROMIPS_GOT16
);
17052 fixp
->fx_file
= fragp
->fr_file
;
17053 fixp
->fx_line
= fragp
->fr_line
;
17055 buf
= write_compressed_insn (buf
, insn
, 4);
17057 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17058 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
17059 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
17061 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
17062 BFD_RELOC_MICROMIPS_LO16
);
17063 fixp
->fx_file
= fragp
->fr_file
;
17064 fixp
->fx_line
= fragp
->fr_line
;
17066 buf
= write_compressed_insn (buf
, insn
, 4);
17068 /* jr/jrc/jalr/jalrs $at */
17069 insn
= al
? jalr
: jr
;
17070 insn
|= at
<< MICROMIPSOP_SH_MJ
;
17072 buf
= write_compressed_insn (buf
, insn
, 2);
17075 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
17079 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17082 const struct mips_int_operand
*operand
;
17085 unsigned int user_length
, length
;
17086 unsigned long insn
;
17089 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17090 operand
= mips16_immed_operand (type
, FALSE
);
17092 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
17093 val
= resolve_symbol_value (fragp
->fr_symbol
);
17094 if (operand
->root
.type
== OP_PCREL
)
17096 const struct mips_pcrel_operand
*pcrel_op
;
17099 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17100 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17102 /* The rules for the base address of a PC relative reloc are
17103 complicated; see mips16_extended_frag. */
17104 if (pcrel_op
->include_isa_bit
)
17109 /* Ignore the low bit in the target, since it will be
17110 set for a text label. */
17113 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17115 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17118 addr
&= -(1 << pcrel_op
->align_log2
);
17121 /* Make sure the section winds up with the alignment we have
17123 if (operand
->shift
> 0)
17124 record_alignment (asec
, operand
->shift
);
17128 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
17129 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
17130 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
17131 _("extended instruction in delay slot"));
17133 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17135 insn
= read_compressed_insn (buf
, 2);
17137 insn
|= MIPS16_EXTEND
;
17139 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17141 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17146 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
17147 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
17149 length
= (ext
? 4 : 2);
17150 gas_assert (mips16_opcode_length (insn
) == length
);
17151 write_compressed_insn (buf
, insn
, length
);
17152 fragp
->fr_fix
+= length
;
17156 relax_substateT subtype
= fragp
->fr_subtype
;
17157 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
17158 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
17162 first
= RELAX_FIRST (subtype
);
17163 second
= RELAX_SECOND (subtype
);
17164 fixp
= (fixS
*) fragp
->fr_opcode
;
17166 /* If the delay slot chosen does not match the size of the instruction,
17167 then emit a warning. */
17168 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
17169 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
17174 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
17175 | RELAX_DELAY_SLOT_SIZE_FIRST
17176 | RELAX_DELAY_SLOT_SIZE_SECOND
);
17177 msg
= macro_warning (s
);
17179 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17183 /* Possibly emit a warning if we've chosen the longer option. */
17184 if (use_second
== second_longer
)
17190 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
17191 msg
= macro_warning (s
);
17193 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
17197 /* Go through all the fixups for the first sequence. Disable them
17198 (by marking them as done) if we're going to use the second
17199 sequence instead. */
17201 && fixp
->fx_frag
== fragp
17202 && fixp
->fx_where
< fragp
->fr_fix
- second
)
17204 if (subtype
& RELAX_USE_SECOND
)
17206 fixp
= fixp
->fx_next
;
17209 /* Go through the fixups for the second sequence. Disable them if
17210 we're going to use the first sequence, otherwise adjust their
17211 addresses to account for the relaxation. */
17212 while (fixp
&& fixp
->fx_frag
== fragp
)
17214 if (subtype
& RELAX_USE_SECOND
)
17215 fixp
->fx_where
-= first
;
17218 fixp
= fixp
->fx_next
;
17221 /* Now modify the frag contents. */
17222 if (subtype
& RELAX_USE_SECOND
)
17226 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
17227 memmove (start
, start
+ first
, second
);
17228 fragp
->fr_fix
-= first
;
17231 fragp
->fr_fix
-= second
;
17235 /* This function is called after the relocs have been generated.
17236 We've been storing mips16 text labels as odd. Here we convert them
17237 back to even for the convenience of the debugger. */
17240 mips_frob_file_after_relocs (void)
17243 unsigned int count
, i
;
17245 syms
= bfd_get_outsymbols (stdoutput
);
17246 count
= bfd_get_symcount (stdoutput
);
17247 for (i
= 0; i
< count
; i
++, syms
++)
17248 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
17249 && ((*syms
)->value
& 1) != 0)
17251 (*syms
)->value
&= ~1;
17252 /* If the symbol has an odd size, it was probably computed
17253 incorrectly, so adjust that as well. */
17254 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
17255 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
17259 /* This function is called whenever a label is defined, including fake
17260 labels instantiated off the dot special symbol. It is used when
17261 handling branch delays; if a branch has a label, we assume we cannot
17262 move it. This also bumps the value of the symbol by 1 in compressed
17266 mips_record_label (symbolS
*sym
)
17268 segment_info_type
*si
= seg_info (now_seg
);
17269 struct insn_label_list
*l
;
17271 if (free_insn_labels
== NULL
)
17272 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
17275 l
= free_insn_labels
;
17276 free_insn_labels
= l
->next
;
17280 l
->next
= si
->label_list
;
17281 si
->label_list
= l
;
17284 /* This function is called as tc_frob_label() whenever a label is defined
17285 and adds a DWARF-2 record we only want for true labels. */
17288 mips_define_label (symbolS
*sym
)
17290 mips_record_label (sym
);
17291 dwarf2_emit_label (sym
);
17294 /* This function is called by tc_new_dot_label whenever a new dot symbol
17298 mips_add_dot_label (symbolS
*sym
)
17300 mips_record_label (sym
);
17301 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
17302 mips_compressed_mark_label (sym
);
17305 /* Some special processing for a MIPS ELF file. */
17308 mips_elf_final_processing (void)
17310 /* Write out the register information. */
17311 if (mips_abi
!= N64_ABI
)
17315 s
.ri_gprmask
= mips_gprmask
;
17316 s
.ri_cprmask
[0] = mips_cprmask
[0];
17317 s
.ri_cprmask
[1] = mips_cprmask
[1];
17318 s
.ri_cprmask
[2] = mips_cprmask
[2];
17319 s
.ri_cprmask
[3] = mips_cprmask
[3];
17320 /* The gp_value field is set by the MIPS ELF backend. */
17322 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
17323 ((Elf32_External_RegInfo
*)
17324 mips_regmask_frag
));
17328 Elf64_Internal_RegInfo s
;
17330 s
.ri_gprmask
= mips_gprmask
;
17332 s
.ri_cprmask
[0] = mips_cprmask
[0];
17333 s
.ri_cprmask
[1] = mips_cprmask
[1];
17334 s
.ri_cprmask
[2] = mips_cprmask
[2];
17335 s
.ri_cprmask
[3] = mips_cprmask
[3];
17336 /* The gp_value field is set by the MIPS ELF backend. */
17338 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
17339 ((Elf64_External_RegInfo
*)
17340 mips_regmask_frag
));
17343 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17344 sort of BFD interface for this. */
17345 if (mips_any_noreorder
)
17346 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
17347 if (mips_pic
!= NO_PIC
)
17349 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
17350 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17353 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
17355 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17356 defined at present; this might need to change in future. */
17357 if (file_ase_mips16
)
17358 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
17359 if (file_ase_micromips
)
17360 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
17361 if (file_ase
& ASE_MDMX
)
17362 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
17364 /* Set the MIPS ELF ABI flags. */
17365 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
17366 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
17367 else if (mips_abi
== O64_ABI
)
17368 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
17369 else if (mips_abi
== EABI_ABI
)
17371 if (!file_mips_gp32
)
17372 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
17374 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
17376 else if (mips_abi
== N32_ABI
)
17377 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
17379 /* Nothing to do for N64_ABI. */
17381 if (mips_32bitmode
)
17382 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
17384 if (mips_flag_nan2008
)
17385 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
17387 #if 0 /* XXX FIXME */
17388 /* 32 bit code with 64 bit FP registers. */
17389 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
17390 elf_elfheader (stdoutput
)->e_flags
|= ???;
17394 typedef struct proc
{
17396 symbolS
*func_end_sym
;
17397 unsigned long reg_mask
;
17398 unsigned long reg_offset
;
17399 unsigned long fpreg_mask
;
17400 unsigned long fpreg_offset
;
17401 unsigned long frame_offset
;
17402 unsigned long frame_reg
;
17403 unsigned long pc_reg
;
17406 static procS cur_proc
;
17407 static procS
*cur_proc_ptr
;
17408 static int numprocs
;
17410 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17411 as "2", and a normal nop as "0". */
17413 #define NOP_OPCODE_MIPS 0
17414 #define NOP_OPCODE_MIPS16 1
17415 #define NOP_OPCODE_MICROMIPS 2
17418 mips_nop_opcode (void)
17420 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
17421 return NOP_OPCODE_MICROMIPS
;
17422 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
17423 return NOP_OPCODE_MIPS16
;
17425 return NOP_OPCODE_MIPS
;
17428 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17429 32-bit microMIPS NOPs here (if applicable). */
17432 mips_handle_align (fragS
*fragp
)
17436 int bytes
, size
, excess
;
17439 if (fragp
->fr_type
!= rs_align_code
)
17442 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
17444 switch (nop_opcode
)
17446 case NOP_OPCODE_MICROMIPS
:
17447 opcode
= micromips_nop32_insn
.insn_opcode
;
17450 case NOP_OPCODE_MIPS16
:
17451 opcode
= mips16_nop_insn
.insn_opcode
;
17454 case NOP_OPCODE_MIPS
:
17456 opcode
= nop_insn
.insn_opcode
;
17461 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
17462 excess
= bytes
% size
;
17464 /* Handle the leading part if we're not inserting a whole number of
17465 instructions, and make it the end of the fixed part of the frag.
17466 Try to fit in a short microMIPS NOP if applicable and possible,
17467 and use zeroes otherwise. */
17468 gas_assert (excess
< 4);
17469 fragp
->fr_fix
+= excess
;
17474 /* Fall through. */
17476 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
17478 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
17482 /* Fall through. */
17485 /* Fall through. */
17490 md_number_to_chars (p
, opcode
, size
);
17491 fragp
->fr_var
= size
;
17495 md_obj_begin (void)
17502 /* Check for premature end, nesting errors, etc. */
17504 as_warn (_("missing .end at end of assembly"));
17513 if (*input_line_pointer
== '-')
17515 ++input_line_pointer
;
17518 if (!ISDIGIT (*input_line_pointer
))
17519 as_bad (_("expected simple number"));
17520 if (input_line_pointer
[0] == '0')
17522 if (input_line_pointer
[1] == 'x')
17524 input_line_pointer
+= 2;
17525 while (ISXDIGIT (*input_line_pointer
))
17528 val
|= hex_value (*input_line_pointer
++);
17530 return negative
? -val
: val
;
17534 ++input_line_pointer
;
17535 while (ISDIGIT (*input_line_pointer
))
17538 val
|= *input_line_pointer
++ - '0';
17540 return negative
? -val
: val
;
17543 if (!ISDIGIT (*input_line_pointer
))
17545 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17546 *input_line_pointer
, *input_line_pointer
);
17547 as_warn (_("invalid number"));
17550 while (ISDIGIT (*input_line_pointer
))
17553 val
+= *input_line_pointer
++ - '0';
17555 return negative
? -val
: val
;
17558 /* The .file directive; just like the usual .file directive, but there
17559 is an initial number which is the ECOFF file index. In the non-ECOFF
17560 case .file implies DWARF-2. */
17563 s_mips_file (int x ATTRIBUTE_UNUSED
)
17565 static int first_file_directive
= 0;
17567 if (ECOFF_DEBUGGING
)
17576 filename
= dwarf2_directive_file (0);
17578 /* Versions of GCC up to 3.1 start files with a ".file"
17579 directive even for stabs output. Make sure that this
17580 ".file" is handled. Note that you need a version of GCC
17581 after 3.1 in order to support DWARF-2 on MIPS. */
17582 if (filename
!= NULL
&& ! first_file_directive
)
17584 (void) new_logical_line (filename
, -1);
17585 s_app_file_string (filename
, 0);
17587 first_file_directive
= 1;
17591 /* The .loc directive, implying DWARF-2. */
17594 s_mips_loc (int x ATTRIBUTE_UNUSED
)
17596 if (!ECOFF_DEBUGGING
)
17597 dwarf2_directive_loc (0);
17600 /* The .end directive. */
17603 s_mips_end (int x ATTRIBUTE_UNUSED
)
17607 /* Following functions need their own .frame and .cprestore directives. */
17608 mips_frame_reg_valid
= 0;
17609 mips_cprestore_valid
= 0;
17611 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
17614 demand_empty_rest_of_line ();
17619 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17620 as_warn (_(".end not in text section"));
17624 as_warn (_(".end directive without a preceding .ent directive."));
17625 demand_empty_rest_of_line ();
17631 gas_assert (S_GET_NAME (p
));
17632 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
17633 as_warn (_(".end symbol does not match .ent symbol."));
17635 if (debug_type
== DEBUG_STABS
)
17636 stabs_generate_asm_endfunc (S_GET_NAME (p
),
17640 as_warn (_(".end directive missing or unknown symbol"));
17642 /* Create an expression to calculate the size of the function. */
17643 if (p
&& cur_proc_ptr
)
17645 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
17646 expressionS
*exp
= xmalloc (sizeof (expressionS
));
17649 exp
->X_op
= O_subtract
;
17650 exp
->X_add_symbol
= symbol_temp_new_now ();
17651 exp
->X_op_symbol
= p
;
17652 exp
->X_add_number
= 0;
17654 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
17657 /* Generate a .pdr section. */
17658 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
17660 segT saved_seg
= now_seg
;
17661 subsegT saved_subseg
= now_subseg
;
17665 #ifdef md_flush_pending_output
17666 md_flush_pending_output ();
17669 gas_assert (pdr_seg
);
17670 subseg_set (pdr_seg
, 0);
17672 /* Write the symbol. */
17673 exp
.X_op
= O_symbol
;
17674 exp
.X_add_symbol
= p
;
17675 exp
.X_add_number
= 0;
17676 emit_expr (&exp
, 4);
17678 fragp
= frag_more (7 * 4);
17680 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
17681 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
17682 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
17683 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
17684 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
17685 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
17686 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
17688 subseg_set (saved_seg
, saved_subseg
);
17691 cur_proc_ptr
= NULL
;
17694 /* The .aent and .ent directives. */
17697 s_mips_ent (int aent
)
17701 symbolP
= get_symbol ();
17702 if (*input_line_pointer
== ',')
17703 ++input_line_pointer
;
17704 SKIP_WHITESPACE ();
17705 if (ISDIGIT (*input_line_pointer
)
17706 || *input_line_pointer
== '-')
17709 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
17710 as_warn (_(".ent or .aent not in text section."));
17712 if (!aent
&& cur_proc_ptr
)
17713 as_warn (_("missing .end"));
17717 /* This function needs its own .frame and .cprestore directives. */
17718 mips_frame_reg_valid
= 0;
17719 mips_cprestore_valid
= 0;
17721 cur_proc_ptr
= &cur_proc
;
17722 memset (cur_proc_ptr
, '\0', sizeof (procS
));
17724 cur_proc_ptr
->func_sym
= symbolP
;
17728 if (debug_type
== DEBUG_STABS
)
17729 stabs_generate_asm_func (S_GET_NAME (symbolP
),
17730 S_GET_NAME (symbolP
));
17733 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
17735 demand_empty_rest_of_line ();
17738 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17739 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17740 s_mips_frame is used so that we can set the PDR information correctly.
17741 We can't use the ecoff routines because they make reference to the ecoff
17742 symbol table (in the mdebug section). */
17745 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
17747 if (ECOFF_DEBUGGING
)
17753 if (cur_proc_ptr
== (procS
*) NULL
)
17755 as_warn (_(".frame outside of .ent"));
17756 demand_empty_rest_of_line ();
17760 cur_proc_ptr
->frame_reg
= tc_get_register (1);
17762 SKIP_WHITESPACE ();
17763 if (*input_line_pointer
++ != ','
17764 || get_absolute_expression_and_terminator (&val
) != ',')
17766 as_warn (_("Bad .frame directive"));
17767 --input_line_pointer
;
17768 demand_empty_rest_of_line ();
17772 cur_proc_ptr
->frame_offset
= val
;
17773 cur_proc_ptr
->pc_reg
= tc_get_register (0);
17775 demand_empty_rest_of_line ();
17779 /* The .fmask and .mask directives. If the mdebug section is present
17780 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17781 embedded targets, s_mips_mask is used so that we can set the PDR
17782 information correctly. We can't use the ecoff routines because they
17783 make reference to the ecoff symbol table (in the mdebug section). */
17786 s_mips_mask (int reg_type
)
17788 if (ECOFF_DEBUGGING
)
17789 s_ignore (reg_type
);
17794 if (cur_proc_ptr
== (procS
*) NULL
)
17796 as_warn (_(".mask/.fmask outside of .ent"));
17797 demand_empty_rest_of_line ();
17801 if (get_absolute_expression_and_terminator (&mask
) != ',')
17803 as_warn (_("Bad .mask/.fmask directive"));
17804 --input_line_pointer
;
17805 demand_empty_rest_of_line ();
17809 off
= get_absolute_expression ();
17811 if (reg_type
== 'F')
17813 cur_proc_ptr
->fpreg_mask
= mask
;
17814 cur_proc_ptr
->fpreg_offset
= off
;
17818 cur_proc_ptr
->reg_mask
= mask
;
17819 cur_proc_ptr
->reg_offset
= off
;
17822 demand_empty_rest_of_line ();
17826 /* A table describing all the processors gas knows about. Names are
17827 matched in the order listed.
17829 To ease comparison, please keep this table in the same order as
17830 gcc's mips_cpu_info_table[]. */
17831 static const struct mips_cpu_info mips_cpu_info_table
[] =
17833 /* Entries for generic ISAs */
17834 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
17835 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
17836 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
17837 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
17838 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
17839 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
17840 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17841 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
17842 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
17845 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17846 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
17847 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
17850 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
17853 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
17854 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
17855 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
17856 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
17857 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17858 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
17859 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
17860 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
17861 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
17862 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
17863 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
17864 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
17865 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
17866 /* ST Microelectronics Loongson 2E and 2F cores */
17867 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
17868 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
17871 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
17872 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
17873 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
17874 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
17875 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
17876 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
17877 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
17878 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
17879 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
17880 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
17881 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
17882 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
17883 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
17884 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
17885 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
17888 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17889 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17890 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
17891 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
17893 /* MIPS 32 Release 2 */
17894 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17895 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17896 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17897 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17898 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17899 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17900 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17901 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17902 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17903 ISA_MIPS32R2
, CPU_MIPS32R2
},
17904 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
17905 ISA_MIPS32R2
, CPU_MIPS32R2
},
17906 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17907 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17908 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17909 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17910 /* Deprecated forms of the above. */
17911 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17912 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
17913 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17914 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17915 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17916 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17917 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17918 /* Deprecated forms of the above. */
17919 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17920 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17921 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17922 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17923 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17924 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17925 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17926 /* Deprecated forms of the above. */
17927 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17928 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17929 /* 34Kn is a 34kc without DSP. */
17930 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17931 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17932 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17933 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17934 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17935 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17936 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17937 /* Deprecated forms of the above. */
17938 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17939 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17940 /* 1004K cores are multiprocessor versions of the 34K. */
17941 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17942 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17943 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17944 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
17947 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17948 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
17949 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17950 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
17952 /* Broadcom SB-1 CPU core */
17953 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17954 /* Broadcom SB-1A CPU core */
17955 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
17957 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
17959 /* MIPS 64 Release 2 */
17961 /* Cavium Networks Octeon CPU core */
17962 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
17963 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
17964 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
17967 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
17970 XLP is mostly like XLR, with the prominent exception that it is
17971 MIPS64R2 rather than MIPS64. */
17972 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
17975 { NULL
, 0, 0, 0, 0 }
17979 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17980 with a final "000" replaced by "k". Ignore case.
17982 Note: this function is shared between GCC and GAS. */
17985 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
17987 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
17988 given
++, canonical
++;
17990 return ((*given
== 0 && *canonical
== 0)
17991 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
17995 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17996 CPU name. We've traditionally allowed a lot of variation here.
17998 Note: this function is shared between GCC and GAS. */
18001 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
18003 /* First see if the name matches exactly, or with a final "000"
18004 turned into "k". */
18005 if (mips_strict_matching_cpu_name_p (canonical
, given
))
18008 /* If not, try comparing based on numerical designation alone.
18009 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18010 if (TOLOWER (*given
) == 'r')
18012 if (!ISDIGIT (*given
))
18015 /* Skip over some well-known prefixes in the canonical name,
18016 hoping to find a number there too. */
18017 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
18019 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
18021 else if (TOLOWER (canonical
[0]) == 'r')
18024 return mips_strict_matching_cpu_name_p (canonical
, given
);
18028 /* Parse an option that takes the name of a processor as its argument.
18029 OPTION is the name of the option and CPU_STRING is the argument.
18030 Return the corresponding processor enumeration if the CPU_STRING is
18031 recognized, otherwise report an error and return null.
18033 A similar function exists in GCC. */
18035 static const struct mips_cpu_info
*
18036 mips_parse_cpu (const char *option
, const char *cpu_string
)
18038 const struct mips_cpu_info
*p
;
18040 /* 'from-abi' selects the most compatible architecture for the given
18041 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18042 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18043 version. Look first at the -mgp options, if given, otherwise base
18044 the choice on MIPS_DEFAULT_64BIT.
18046 Treat NO_ABI like the EABIs. One reason to do this is that the
18047 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18048 architecture. This code picks MIPS I for 'mips' and MIPS III for
18049 'mips64', just as we did in the days before 'from-abi'. */
18050 if (strcasecmp (cpu_string
, "from-abi") == 0)
18052 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
18053 return mips_cpu_info_from_isa (ISA_MIPS1
);
18055 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
18056 return mips_cpu_info_from_isa (ISA_MIPS3
);
18058 if (file_mips_gp32
>= 0)
18059 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
18061 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18066 /* 'default' has traditionally been a no-op. Probably not very useful. */
18067 if (strcasecmp (cpu_string
, "default") == 0)
18070 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
18071 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
18074 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
18078 /* Return the canonical processor information for ISA (a member of the
18079 ISA_MIPS* enumeration). */
18081 static const struct mips_cpu_info
*
18082 mips_cpu_info_from_isa (int isa
)
18086 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18087 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
18088 && isa
== mips_cpu_info_table
[i
].isa
)
18089 return (&mips_cpu_info_table
[i
]);
18094 static const struct mips_cpu_info
*
18095 mips_cpu_info_from_arch (int arch
)
18099 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18100 if (arch
== mips_cpu_info_table
[i
].cpu
)
18101 return (&mips_cpu_info_table
[i
]);
18107 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
18111 fprintf (stream
, "%24s", "");
18116 fprintf (stream
, ", ");
18120 if (*col_p
+ strlen (string
) > 72)
18122 fprintf (stream
, "\n%24s", "");
18126 fprintf (stream
, "%s", string
);
18127 *col_p
+= strlen (string
);
18133 md_show_usage (FILE *stream
)
18138 fprintf (stream
, _("\
18140 -EB generate big endian output\n\
18141 -EL generate little endian output\n\
18142 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18143 -G NUM allow referencing objects up to NUM bytes\n\
18144 implicitly with the gp register [default 8]\n"));
18145 fprintf (stream
, _("\
18146 -mips1 generate MIPS ISA I instructions\n\
18147 -mips2 generate MIPS ISA II instructions\n\
18148 -mips3 generate MIPS ISA III instructions\n\
18149 -mips4 generate MIPS ISA IV instructions\n\
18150 -mips5 generate MIPS ISA V instructions\n\
18151 -mips32 generate MIPS32 ISA instructions\n\
18152 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18153 -mips64 generate MIPS64 ISA instructions\n\
18154 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18155 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18159 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
18160 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
18161 show (stream
, "from-abi", &column
, &first
);
18162 fputc ('\n', stream
);
18164 fprintf (stream
, _("\
18165 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18166 -no-mCPU don't generate code specific to CPU.\n\
18167 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18171 show (stream
, "3900", &column
, &first
);
18172 show (stream
, "4010", &column
, &first
);
18173 show (stream
, "4100", &column
, &first
);
18174 show (stream
, "4650", &column
, &first
);
18175 fputc ('\n', stream
);
18177 fprintf (stream
, _("\
18178 -mips16 generate mips16 instructions\n\
18179 -no-mips16 do not generate mips16 instructions\n"));
18180 fprintf (stream
, _("\
18181 -mmicromips generate microMIPS instructions\n\
18182 -mno-micromips do not generate microMIPS instructions\n"));
18183 fprintf (stream
, _("\
18184 -msmartmips generate smartmips instructions\n\
18185 -mno-smartmips do not generate smartmips instructions\n"));
18186 fprintf (stream
, _("\
18187 -mdsp generate DSP instructions\n\
18188 -mno-dsp do not generate DSP instructions\n"));
18189 fprintf (stream
, _("\
18190 -mdspr2 generate DSP R2 instructions\n\
18191 -mno-dspr2 do not generate DSP R2 instructions\n"));
18192 fprintf (stream
, _("\
18193 -mmt generate MT instructions\n\
18194 -mno-mt do not generate MT instructions\n"));
18195 fprintf (stream
, _("\
18196 -mmcu generate MCU instructions\n\
18197 -mno-mcu do not generate MCU instructions\n"));
18198 fprintf (stream
, _("\
18199 -mvirt generate Virtualization instructions\n\
18200 -mno-virt do not generate Virtualization instructions\n"));
18201 fprintf (stream
, _("\
18202 -minsn32 only generate 32-bit microMIPS instructions\n\
18203 -mno-insn32 generate all microMIPS instructions\n"));
18204 fprintf (stream
, _("\
18205 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18206 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18207 -mfix-vr4120 work around certain VR4120 errata\n\
18208 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18209 -mfix-24k insert a nop after ERET and DERET instructions\n\
18210 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18211 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18212 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18213 -msym32 assume all symbols have 32-bit values\n\
18214 -O0 remove unneeded NOPs, do not swap branches\n\
18215 -O remove unneeded NOPs and swap branches\n\
18216 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18217 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18218 fprintf (stream
, _("\
18219 -mhard-float allow floating-point instructions\n\
18220 -msoft-float do not allow floating-point instructions\n\
18221 -msingle-float only allow 32-bit floating-point operations\n\
18222 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18223 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18224 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18225 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18229 show (stream
, "legacy", &column
, &first
);
18230 show (stream
, "2008", &column
, &first
);
18232 fputc ('\n', stream
);
18234 fprintf (stream
, _("\
18235 -KPIC, -call_shared generate SVR4 position independent code\n\
18236 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18237 -mvxworks-pic generate VxWorks position independent code\n\
18238 -non_shared do not generate code that can operate with DSOs\n\
18239 -xgot assume a 32 bit GOT\n\
18240 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18241 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18242 position dependent (non shared) code\n\
18243 -mabi=ABI create ABI conformant object file for:\n"));
18247 show (stream
, "32", &column
, &first
);
18248 show (stream
, "o64", &column
, &first
);
18249 show (stream
, "n32", &column
, &first
);
18250 show (stream
, "64", &column
, &first
);
18251 show (stream
, "eabi", &column
, &first
);
18253 fputc ('\n', stream
);
18255 fprintf (stream
, _("\
18256 -32 create o32 ABI object file (default)\n\
18257 -n32 create n32 ABI object file\n\
18258 -64 create 64 ABI object file\n"));
18263 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
18265 if (HAVE_64BIT_SYMBOLS
)
18266 return dwarf2_format_64bit_irix
;
18268 return dwarf2_format_32bit
;
18273 mips_dwarf2_addr_size (void)
18275 if (HAVE_64BIT_OBJECTS
)
18281 /* Standard calling conventions leave the CFA at SP on entry. */
18283 mips_cfi_frame_initial_instructions (void)
18285 cfi_add_CFA_def_cfa_register (SP
);
18289 tc_mips_regname_to_dw2regnum (char *regname
)
18291 unsigned int regnum
= -1;
18294 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))