1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float
;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float
;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32
= -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32
= -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float
= 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float
= 0;
265 static struct mips_set_options mips_opts
=
267 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
272 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask
;
279 unsigned long mips_cprmask
[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa
= ISA_UNKNOWN
;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d
;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx
;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips
;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp
;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2
;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt
;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_R14000 \
476 || mips_opts.arch == CPU_R16000 \
477 || mips_opts.arch == CPU_RM7000 \
478 || mips_opts.arch == CPU_VR5500 \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900)
490 /* Whether the processor uses hardware interlocks to avoid delays
491 required by coprocessor instructions, and thus does not require
492 nops to be inserted. This applies to instructions marked
493 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
494 between instructions marked INSN_WRITE_COND_CODE and ones marked
495 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
496 levels I, II, and III. */
497 /* Itbl support may require additional care here. */
498 #define cop_interlocks \
499 ((mips_opts.isa != ISA_MIPS1 \
500 && mips_opts.isa != ISA_MIPS2 \
501 && mips_opts.isa != ISA_MIPS3) \
502 || mips_opts.arch == CPU_R4300 \
505 /* Whether the processor uses hardware interlocks to protect reads
506 from coprocessor registers after they are loaded from memory, and
507 thus does not require nops to be inserted. This applies to
508 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
509 requires at MIPS ISA level I. */
510 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
512 /* Is this a mfhi or mflo instruction? */
513 #define MF_HILO_INSN(PINFO) \
514 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
516 /* Returns true for a (non floating-point) coprocessor instruction. Reading
517 or writing the condition code is only possible on the coprocessors and
518 these insns are not marked with INSN_COP. Thus for these insns use the
519 condition-code flags. */
520 #define COP_INSN(PINFO) \
521 (PINFO != INSN_MACRO \
522 && ((PINFO) & (FP_S | FP_D)) == 0 \
523 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
525 /* MIPS PIC level. */
527 enum mips_pic_level mips_pic
;
529 /* 1 if we should generate 32 bit offsets from the $gp register in
530 SVR4_PIC mode. Currently has no meaning in other modes. */
531 static int mips_big_got
= 0;
533 /* 1 if trap instructions should used for overflow rather than break
535 static int mips_trap
= 0;
537 /* 1 if double width floating point constants should not be constructed
538 by assembling two single width halves into two single width floating
539 point registers which just happen to alias the double width destination
540 register. On some architectures this aliasing can be disabled by a bit
541 in the status register, and the setting of this bit cannot be determined
542 automatically at assemble time. */
543 static int mips_disable_float_construction
;
545 /* Non-zero if any .set noreorder directives were used. */
547 static int mips_any_noreorder
;
549 /* Non-zero if nops should be inserted when the register referenced in
550 an mfhi/mflo instruction is read in the next two instructions. */
551 static int mips_7000_hilo_fix
;
553 /* The size of objects in the small data section. */
554 static unsigned int g_switch_value
= 8;
555 /* Whether the -G option was used. */
556 static int g_switch_seen
= 0;
561 /* If we can determine in advance that GP optimization won't be
562 possible, we can skip the relaxation stuff that tries to produce
563 GP-relative references. This makes delay slot optimization work
566 This function can only provide a guess, but it seems to work for
567 gcc output. It needs to guess right for gcc, otherwise gcc
568 will put what it thinks is a GP-relative instruction in a branch
571 I don't know if a fix is needed for the SVR4_PIC mode. I've only
572 fixed it for the non-PIC mode. KR 95/04/07 */
573 static int nopic_need_relax (symbolS
*, int);
575 /* handle of the OPCODE hash table */
576 static struct hash_control
*op_hash
= NULL
;
578 /* The opcode hash table we use for the mips16. */
579 static struct hash_control
*mips16_op_hash
= NULL
;
581 /* This array holds the chars that always start a comment. If the
582 pre-processor is disabled, these aren't very useful */
583 const char comment_chars
[] = "#";
585 /* This array holds the chars that only start a comment at the beginning of
586 a line. If the line seems to have the form '# 123 filename'
587 .line and .file directives will appear in the pre-processed output */
588 /* Note that input_file.c hand checks for '#' at the beginning of the
589 first line of the input file. This is because the compiler outputs
590 #NO_APP at the beginning of its output. */
591 /* Also note that C style comments are always supported. */
592 const char line_comment_chars
[] = "#";
594 /* This array holds machine specific line separator characters. */
595 const char line_separator_chars
[] = ";";
597 /* Chars that can be used to separate mant from exp in floating point nums */
598 const char EXP_CHARS
[] = "eE";
600 /* Chars that mean this number is a floating point constant */
603 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
605 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
606 changed in read.c . Ideally it shouldn't have to know about it at all,
607 but nothing is ideal around here.
610 static char *insn_error
;
612 static int auto_align
= 1;
614 /* When outputting SVR4 PIC code, the assembler needs to know the
615 offset in the stack frame from which to restore the $gp register.
616 This is set by the .cprestore pseudo-op, and saved in this
618 static offsetT mips_cprestore_offset
= -1;
620 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
621 more optimizations, it can use a register value instead of a memory-saved
622 offset and even an other register than $gp as global pointer. */
623 static offsetT mips_cpreturn_offset
= -1;
624 static int mips_cpreturn_register
= -1;
625 static int mips_gp_register
= GP
;
626 static int mips_gprel_offset
= 0;
628 /* Whether mips_cprestore_offset has been set in the current function
629 (or whether it has already been warned about, if not). */
630 static int mips_cprestore_valid
= 0;
632 /* This is the register which holds the stack frame, as set by the
633 .frame pseudo-op. This is needed to implement .cprestore. */
634 static int mips_frame_reg
= SP
;
636 /* Whether mips_frame_reg has been set in the current function
637 (or whether it has already been warned about, if not). */
638 static int mips_frame_reg_valid
= 0;
640 /* To output NOP instructions correctly, we need to keep information
641 about the previous two instructions. */
643 /* Whether we are optimizing. The default value of 2 means to remove
644 unneeded NOPs and swap branch instructions when possible. A value
645 of 1 means to not swap branches. A value of 0 means to always
647 static int mips_optimize
= 2;
649 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
650 equivalent to seeing no -g option at all. */
651 static int mips_debug
= 0;
653 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
654 #define MAX_VR4130_NOPS 4
656 /* The maximum number of NOPs needed to fill delay slots. */
657 #define MAX_DELAY_NOPS 2
659 /* The maximum number of NOPs needed for any purpose. */
662 /* A list of previous instructions, with index 0 being the most recent.
663 We need to look back MAX_NOPS instructions when filling delay slots
664 or working around processor errata. We need to look back one
665 instruction further if we're thinking about using history[0] to
666 fill a branch delay slot. */
667 static struct mips_cl_insn history
[1 + MAX_NOPS
];
669 /* Nop instructions used by emit_nop. */
670 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
672 /* The appropriate nop for the current mode. */
673 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
675 /* If this is set, it points to a frag holding nop instructions which
676 were inserted before the start of a noreorder section. If those
677 nops turn out to be unnecessary, the size of the frag can be
679 static fragS
*prev_nop_frag
;
681 /* The number of nop instructions we created in prev_nop_frag. */
682 static int prev_nop_frag_holds
;
684 /* The number of nop instructions that we know we need in
686 static int prev_nop_frag_required
;
688 /* The number of instructions we've seen since prev_nop_frag. */
689 static int prev_nop_frag_since
;
691 /* For ECOFF and ELF, relocations against symbols are done in two
692 parts, with a HI relocation and a LO relocation. Each relocation
693 has only 16 bits of space to store an addend. This means that in
694 order for the linker to handle carries correctly, it must be able
695 to locate both the HI and the LO relocation. This means that the
696 relocations must appear in order in the relocation table.
698 In order to implement this, we keep track of each unmatched HI
699 relocation. We then sort them so that they immediately precede the
700 corresponding LO relocation. */
705 struct mips_hi_fixup
*next
;
708 /* The section this fixup is in. */
712 /* The list of unmatched HI relocs. */
714 static struct mips_hi_fixup
*mips_hi_fixup_list
;
716 /* The frag containing the last explicit relocation operator.
717 Null if explicit relocations have not been used. */
719 static fragS
*prev_reloc_op_frag
;
721 /* Map normal MIPS register numbers to mips16 register numbers. */
723 #define X ILLEGAL_REG
724 static const int mips32_to_16_reg_map
[] =
726 X
, X
, 2, 3, 4, 5, 6, 7,
727 X
, X
, X
, X
, X
, X
, X
, X
,
728 0, 1, X
, X
, X
, X
, X
, X
,
729 X
, X
, X
, X
, X
, X
, X
, X
733 /* Map mips16 register numbers to normal MIPS register numbers. */
735 static const unsigned int mips16_to_32_reg_map
[] =
737 16, 17, 2, 3, 4, 5, 6, 7
740 /* Classifies the kind of instructions we're interested in when
741 implementing -mfix-vr4120. */
742 enum fix_vr4120_class
{
749 NUM_FIX_VR4120_CLASSES
752 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
753 there must be at least one other instruction between an instruction
754 of type X and an instruction of type Y. */
755 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
757 /* True if -mfix-vr4120 is in force. */
758 static int mips_fix_vr4120
;
760 /* ...likewise -mfix-vr4130. */
761 static int mips_fix_vr4130
;
763 /* We don't relax branches by default, since this causes us to expand
764 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
765 fail to compute the offset before expanding the macro to the most
766 efficient expansion. */
768 static int mips_relax_branch
;
770 /* The expansion of many macros depends on the type of symbol that
771 they refer to. For example, when generating position-dependent code,
772 a macro that refers to a symbol may have two different expansions,
773 one which uses GP-relative addresses and one which uses absolute
774 addresses. When generating SVR4-style PIC, a macro may have
775 different expansions for local and global symbols.
777 We handle these situations by generating both sequences and putting
778 them in variant frags. In position-dependent code, the first sequence
779 will be the GP-relative one and the second sequence will be the
780 absolute one. In SVR4 PIC, the first sequence will be for global
781 symbols and the second will be for local symbols.
783 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
784 SECOND are the lengths of the two sequences in bytes. These fields
785 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
786 the subtype has the following flags:
789 Set if it has been decided that we should use the second
790 sequence instead of the first.
793 Set in the first variant frag if the macro's second implementation
794 is longer than its first. This refers to the macro as a whole,
795 not an individual relaxation.
798 Set in the first variant frag if the macro appeared in a .set nomacro
799 block and if one alternative requires a warning but the other does not.
802 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
805 The frag's "opcode" points to the first fixup for relaxable code.
807 Relaxable macros are generated using a sequence such as:
809 relax_start (SYMBOL);
810 ... generate first expansion ...
812 ... generate second expansion ...
815 The code and fixups for the unwanted alternative are discarded
816 by md_convert_frag. */
817 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
819 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
820 #define RELAX_SECOND(X) ((X) & 0xff)
821 #define RELAX_USE_SECOND 0x10000
822 #define RELAX_SECOND_LONGER 0x20000
823 #define RELAX_NOMACRO 0x40000
824 #define RELAX_DELAY_SLOT 0x80000
826 /* Branch without likely bit. If label is out of range, we turn:
828 beq reg1, reg2, label
838 with the following opcode replacements:
845 bltzal <-> bgezal (with jal label instead of j label)
847 Even though keeping the delay slot instruction in the delay slot of
848 the branch would be more efficient, it would be very tricky to do
849 correctly, because we'd have to introduce a variable frag *after*
850 the delay slot instruction, and expand that instead. Let's do it
851 the easy way for now, even if the branch-not-taken case now costs
852 one additional instruction. Out-of-range branches are not supposed
853 to be common, anyway.
855 Branch likely. If label is out of range, we turn:
857 beql reg1, reg2, label
858 delay slot (annulled if branch not taken)
867 delay slot (executed only if branch taken)
870 It would be possible to generate a shorter sequence by losing the
871 likely bit, generating something like:
876 delay slot (executed only if branch taken)
888 bltzall -> bgezal (with jal label instead of j label)
889 bgezall -> bltzal (ditto)
892 but it's not clear that it would actually improve performance. */
893 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
896 | ((toofar) ? 1 : 0) \
898 | ((likely) ? 4 : 0) \
899 | ((uncond) ? 8 : 0)))
900 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
901 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
902 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
903 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
904 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
906 /* For mips16 code, we use an entirely different form of relaxation.
907 mips16 supports two versions of most instructions which take
908 immediate values: a small one which takes some small value, and a
909 larger one which takes a 16 bit value. Since branches also follow
910 this pattern, relaxing these values is required.
912 We can assemble both mips16 and normal MIPS code in a single
913 object. Therefore, we need to support this type of relaxation at
914 the same time that we support the relaxation described above. We
915 use the high bit of the subtype field to distinguish these cases.
917 The information we store for this type of relaxation is the
918 argument code found in the opcode file for this relocation, whether
919 the user explicitly requested a small or extended form, and whether
920 the relocation is in a jump or jal delay slot. That tells us the
921 size of the value, and how it should be stored. We also store
922 whether the fragment is considered to be extended or not. We also
923 store whether this is known to be a branch to a different section,
924 whether we have tried to relax this frag yet, and whether we have
925 ever extended a PC relative fragment because of a shift count. */
926 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
929 | ((small) ? 0x100 : 0) \
930 | ((ext) ? 0x200 : 0) \
931 | ((dslot) ? 0x400 : 0) \
932 | ((jal_dslot) ? 0x800 : 0))
933 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
934 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
935 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
936 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
937 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
938 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
939 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
940 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
941 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
942 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
943 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
944 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
946 /* Is the given value a sign-extended 32-bit value? */
947 #define IS_SEXT_32BIT_NUM(x) \
948 (((x) &~ (offsetT) 0x7fffffff) == 0 \
949 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
951 /* Is the given value a sign-extended 16-bit value? */
952 #define IS_SEXT_16BIT_NUM(x) \
953 (((x) &~ (offsetT) 0x7fff) == 0 \
954 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
956 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
957 #define IS_ZEXT_32BIT_NUM(x) \
958 (((x) &~ (offsetT) 0xffffffff) == 0 \
959 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
961 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
962 VALUE << SHIFT. VALUE is evaluated exactly once. */
963 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
964 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
965 | (((VALUE) & (MASK)) << (SHIFT)))
967 /* Extract bits MASK << SHIFT from STRUCT and shift them right
969 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
970 (((STRUCT) >> (SHIFT)) & (MASK))
972 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
973 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
975 include/opcode/mips.h specifies operand fields using the macros
976 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
977 with "MIPS16OP" instead of "OP". */
978 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
979 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
980 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
981 INSERT_BITS ((INSN).insn_opcode, VALUE, \
982 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
984 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
985 #define EXTRACT_OPERAND(FIELD, INSN) \
986 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
987 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
988 EXTRACT_BITS ((INSN).insn_opcode, \
989 MIPS16OP_MASK_##FIELD, \
992 /* Global variables used when generating relaxable macros. See the
993 comment above RELAX_ENCODE for more details about how relaxation
996 /* 0 if we're not emitting a relaxable macro.
997 1 if we're emitting the first of the two relaxation alternatives.
998 2 if we're emitting the second alternative. */
1001 /* The first relaxable fixup in the current frag. (In other words,
1002 the first fixup that refers to relaxable code.) */
1005 /* sizes[0] says how many bytes of the first alternative are stored in
1006 the current frag. Likewise sizes[1] for the second alternative. */
1007 unsigned int sizes
[2];
1009 /* The symbol on which the choice of sequence depends. */
1013 /* Global variables used to decide whether a macro needs a warning. */
1015 /* True if the macro is in a branch delay slot. */
1016 bfd_boolean delay_slot_p
;
1018 /* For relaxable macros, sizes[0] is the length of the first alternative
1019 in bytes and sizes[1] is the length of the second alternative.
1020 For non-relaxable macros, both elements give the length of the
1022 unsigned int sizes
[2];
1024 /* The first variant frag for this macro. */
1026 } mips_macro_warning
;
1028 /* Prototypes for static functions. */
1030 #define internalError() \
1031 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1033 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1035 static void append_insn
1036 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
1037 static void mips_no_prev_insn (void);
1038 static void mips16_macro_build
1039 (expressionS
*, const char *, const char *, va_list);
1040 static void load_register (int, expressionS
*, int);
1041 static void macro_start (void);
1042 static void macro_end (void);
1043 static void macro (struct mips_cl_insn
* ip
);
1044 static void mips16_macro (struct mips_cl_insn
* ip
);
1045 #ifdef LOSING_COMPILER
1046 static void macro2 (struct mips_cl_insn
* ip
);
1048 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1049 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1050 static void mips16_immed
1051 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1052 unsigned long *, bfd_boolean
*, unsigned short *);
1053 static size_t my_getSmallExpression
1054 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1055 static void my_getExpression (expressionS
*, char *);
1056 static void s_align (int);
1057 static void s_change_sec (int);
1058 static void s_change_section (int);
1059 static void s_cons (int);
1060 static void s_float_cons (int);
1061 static void s_mips_globl (int);
1062 static void s_option (int);
1063 static void s_mipsset (int);
1064 static void s_abicalls (int);
1065 static void s_cpload (int);
1066 static void s_cpsetup (int);
1067 static void s_cplocal (int);
1068 static void s_cprestore (int);
1069 static void s_cpreturn (int);
1070 static void s_dtprelword (int);
1071 static void s_dtpreldword (int);
1072 static void s_gpvalue (int);
1073 static void s_gpword (int);
1074 static void s_gpdword (int);
1075 static void s_cpadd (int);
1076 static void s_insn (int);
1077 static void md_obj_begin (void);
1078 static void md_obj_end (void);
1079 static void s_mips_ent (int);
1080 static void s_mips_end (int);
1081 static void s_mips_frame (int);
1082 static void s_mips_mask (int reg_type
);
1083 static void s_mips_stab (int);
1084 static void s_mips_weakext (int);
1085 static void s_mips_file (int);
1086 static void s_mips_loc (int);
1087 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1088 static int relaxed_branch_length (fragS
*, asection
*, int);
1089 static int validate_mips_insn (const struct mips_opcode
*);
1091 /* Table and functions used to map between CPU/ISA names, and
1092 ISA levels, and CPU numbers. */
1094 struct mips_cpu_info
1096 const char *name
; /* CPU or ISA name. */
1097 int flags
; /* ASEs available, or ISA flag. */
1098 int isa
; /* ISA level. */
1099 int cpu
; /* CPU number (default CPU if ISA). */
1102 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1103 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1104 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1105 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1106 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1107 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1108 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1110 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1111 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1112 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1116 The following pseudo-ops from the Kane and Heinrich MIPS book
1117 should be defined here, but are currently unsupported: .alias,
1118 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1120 The following pseudo-ops from the Kane and Heinrich MIPS book are
1121 specific to the type of debugging information being generated, and
1122 should be defined by the object format: .aent, .begin, .bend,
1123 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1126 The following pseudo-ops from the Kane and Heinrich MIPS book are
1127 not MIPS CPU specific, but are also not specific to the object file
1128 format. This file is probably the best place to define them, but
1129 they are not currently supported: .asm0, .endr, .lab, .struct. */
1131 static const pseudo_typeS mips_pseudo_table
[] =
1133 /* MIPS specific pseudo-ops. */
1134 {"option", s_option
, 0},
1135 {"set", s_mipsset
, 0},
1136 {"rdata", s_change_sec
, 'r'},
1137 {"sdata", s_change_sec
, 's'},
1138 {"livereg", s_ignore
, 0},
1139 {"abicalls", s_abicalls
, 0},
1140 {"cpload", s_cpload
, 0},
1141 {"cpsetup", s_cpsetup
, 0},
1142 {"cplocal", s_cplocal
, 0},
1143 {"cprestore", s_cprestore
, 0},
1144 {"cpreturn", s_cpreturn
, 0},
1145 {"dtprelword", s_dtprelword
, 0},
1146 {"dtpreldword", s_dtpreldword
, 0},
1147 {"gpvalue", s_gpvalue
, 0},
1148 {"gpword", s_gpword
, 0},
1149 {"gpdword", s_gpdword
, 0},
1150 {"cpadd", s_cpadd
, 0},
1151 {"insn", s_insn
, 0},
1153 /* Relatively generic pseudo-ops that happen to be used on MIPS
1155 {"asciiz", stringer
, 8 + 1},
1156 {"bss", s_change_sec
, 'b'},
1158 {"half", s_cons
, 1},
1159 {"dword", s_cons
, 3},
1160 {"weakext", s_mips_weakext
, 0},
1161 {"origin", s_org
, 0},
1162 {"repeat", s_rept
, 0},
1164 /* These pseudo-ops are defined in read.c, but must be overridden
1165 here for one reason or another. */
1166 {"align", s_align
, 0},
1167 {"byte", s_cons
, 0},
1168 {"data", s_change_sec
, 'd'},
1169 {"double", s_float_cons
, 'd'},
1170 {"float", s_float_cons
, 'f'},
1171 {"globl", s_mips_globl
, 0},
1172 {"global", s_mips_globl
, 0},
1173 {"hword", s_cons
, 1},
1175 {"long", s_cons
, 2},
1176 {"octa", s_cons
, 4},
1177 {"quad", s_cons
, 3},
1178 {"section", s_change_section
, 0},
1179 {"short", s_cons
, 1},
1180 {"single", s_float_cons
, 'f'},
1181 {"stabn", s_mips_stab
, 'n'},
1182 {"text", s_change_sec
, 't'},
1183 {"word", s_cons
, 2},
1185 { "extern", ecoff_directive_extern
, 0},
1190 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1192 /* These pseudo-ops should be defined by the object file format.
1193 However, a.out doesn't support them, so we have versions here. */
1194 {"aent", s_mips_ent
, 1},
1195 {"bgnb", s_ignore
, 0},
1196 {"end", s_mips_end
, 0},
1197 {"endb", s_ignore
, 0},
1198 {"ent", s_mips_ent
, 0},
1199 {"file", s_mips_file
, 0},
1200 {"fmask", s_mips_mask
, 'F'},
1201 {"frame", s_mips_frame
, 0},
1202 {"loc", s_mips_loc
, 0},
1203 {"mask", s_mips_mask
, 'R'},
1204 {"verstamp", s_ignore
, 0},
1208 extern void pop_insert (const pseudo_typeS
*);
1211 mips_pop_insert (void)
1213 pop_insert (mips_pseudo_table
);
1214 if (! ECOFF_DEBUGGING
)
1215 pop_insert (mips_nonecoff_pseudo_table
);
1218 /* Symbols labelling the current insn. */
1220 struct insn_label_list
1222 struct insn_label_list
*next
;
1226 static struct insn_label_list
*free_insn_labels
;
1227 #define label_list tc_segment_info_data.labels
1229 static void mips_clear_insn_labels (void);
1232 mips_clear_insn_labels (void)
1234 register struct insn_label_list
**pl
;
1235 segment_info_type
*si
;
1239 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1242 si
= seg_info (now_seg
);
1243 *pl
= si
->label_list
;
1244 si
->label_list
= NULL
;
1249 static char *expr_end
;
1251 /* Expressions which appear in instructions. These are set by
1254 static expressionS imm_expr
;
1255 static expressionS imm2_expr
;
1256 static expressionS offset_expr
;
1258 /* Relocs associated with imm_expr and offset_expr. */
1260 static bfd_reloc_code_real_type imm_reloc
[3]
1261 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1262 static bfd_reloc_code_real_type offset_reloc
[3]
1263 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1265 /* These are set by mips16_ip if an explicit extension is used. */
1267 static bfd_boolean mips16_small
, mips16_ext
;
1270 /* The pdr segment for per procedure frame/regmask info. Not used for
1273 static segT pdr_seg
;
1276 /* The default target format to use. */
1279 mips_target_format (void)
1281 switch (OUTPUT_FLAVOR
)
1283 case bfd_target_ecoff_flavour
:
1284 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1285 case bfd_target_coff_flavour
:
1287 case bfd_target_elf_flavour
:
1289 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1290 return (target_big_endian
1291 ? "elf32-bigmips-vxworks"
1292 : "elf32-littlemips-vxworks");
1295 /* This is traditional mips. */
1296 return (target_big_endian
1297 ? (HAVE_64BIT_OBJECTS
1298 ? "elf64-tradbigmips"
1300 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1301 : (HAVE_64BIT_OBJECTS
1302 ? "elf64-tradlittlemips"
1304 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1306 return (target_big_endian
1307 ? (HAVE_64BIT_OBJECTS
1310 ? "elf32-nbigmips" : "elf32-bigmips"))
1311 : (HAVE_64BIT_OBJECTS
1312 ? "elf64-littlemips"
1314 ? "elf32-nlittlemips" : "elf32-littlemips")));
1322 /* Return the length of instruction INSN. */
1324 static inline unsigned int
1325 insn_length (const struct mips_cl_insn
*insn
)
1327 if (!mips_opts
.mips16
)
1329 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1332 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1335 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1340 insn
->use_extend
= FALSE
;
1342 insn
->insn_opcode
= mo
->match
;
1345 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1346 insn
->fixp
[i
] = NULL
;
1347 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1348 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1349 insn
->mips16_absolute_jump_p
= 0;
1352 /* Record the current MIPS16 mode in now_seg. */
1355 mips_record_mips16_mode (void)
1357 segment_info_type
*si
;
1359 si
= seg_info (now_seg
);
1360 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1361 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1364 /* Install INSN at the location specified by its "frag" and "where" fields. */
1367 install_insn (const struct mips_cl_insn
*insn
)
1369 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1370 if (!mips_opts
.mips16
)
1371 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1372 else if (insn
->mips16_absolute_jump_p
)
1374 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1375 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1379 if (insn
->use_extend
)
1381 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1384 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1386 mips_record_mips16_mode ();
1389 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1390 and install the opcode in the new location. */
1393 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1398 insn
->where
= where
;
1399 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1400 if (insn
->fixp
[i
] != NULL
)
1402 insn
->fixp
[i
]->fx_frag
= frag
;
1403 insn
->fixp
[i
]->fx_where
= where
;
1405 install_insn (insn
);
1408 /* Add INSN to the end of the output. */
1411 add_fixed_insn (struct mips_cl_insn
*insn
)
1413 char *f
= frag_more (insn_length (insn
));
1414 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1417 /* Start a variant frag and move INSN to the start of the variant part,
1418 marking it as fixed. The other arguments are as for frag_var. */
1421 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1422 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1424 frag_grow (max_chars
);
1425 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1427 frag_var (rs_machine_dependent
, max_chars
, var
,
1428 subtype
, symbol
, offset
, NULL
);
1431 /* Insert N copies of INSN into the history buffer, starting at
1432 position FIRST. Neither FIRST nor N need to be clipped. */
1435 insert_into_history (unsigned int first
, unsigned int n
,
1436 const struct mips_cl_insn
*insn
)
1438 if (mips_relax
.sequence
!= 2)
1442 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1444 history
[i
] = history
[i
- n
];
1450 /* Emit a nop instruction, recording it in the history buffer. */
1455 add_fixed_insn (NOP_INSN
);
1456 insert_into_history (0, 1, NOP_INSN
);
1459 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1460 the idea is to make it obvious at a glance that each errata is
1464 init_vr4120_conflicts (void)
1466 #define CONFLICT(FIRST, SECOND) \
1467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1469 /* Errata 21 - [D]DIV[U] after [D]MACC */
1470 CONFLICT (MACC
, DIV
);
1471 CONFLICT (DMACC
, DIV
);
1473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1474 CONFLICT (DMULT
, DMULT
);
1475 CONFLICT (DMULT
, DMACC
);
1476 CONFLICT (DMACC
, DMULT
);
1477 CONFLICT (DMACC
, DMACC
);
1479 /* Errata 24 - MT{LO,HI} after [D]MACC */
1480 CONFLICT (MACC
, MTHILO
);
1481 CONFLICT (DMACC
, MTHILO
);
1483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1484 instruction is executed immediately after a MACC or DMACC
1485 instruction, the result of [either instruction] is incorrect." */
1486 CONFLICT (MACC
, MULT
);
1487 CONFLICT (MACC
, DMULT
);
1488 CONFLICT (DMACC
, MULT
);
1489 CONFLICT (DMACC
, DMULT
);
1491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1493 DDIV or DDIVU instruction, the result of the MACC or
1494 DMACC instruction is incorrect.". */
1495 CONFLICT (DMULT
, MACC
);
1496 CONFLICT (DMULT
, DMACC
);
1497 CONFLICT (DIV
, MACC
);
1498 CONFLICT (DIV
, DMACC
);
1508 #define RTYPE_MASK 0x1ff00
1509 #define RTYPE_NUM 0x00100
1510 #define RTYPE_FPU 0x00200
1511 #define RTYPE_FCC 0x00400
1512 #define RTYPE_VEC 0x00800
1513 #define RTYPE_GP 0x01000
1514 #define RTYPE_CP0 0x02000
1515 #define RTYPE_PC 0x04000
1516 #define RTYPE_ACC 0x08000
1517 #define RTYPE_CCC 0x10000
1518 #define RNUM_MASK 0x000ff
1519 #define RWARN 0x80000
1521 #define GENERIC_REGISTER_NUMBERS \
1522 {"$0", RTYPE_NUM | 0}, \
1523 {"$1", RTYPE_NUM | 1}, \
1524 {"$2", RTYPE_NUM | 2}, \
1525 {"$3", RTYPE_NUM | 3}, \
1526 {"$4", RTYPE_NUM | 4}, \
1527 {"$5", RTYPE_NUM | 5}, \
1528 {"$6", RTYPE_NUM | 6}, \
1529 {"$7", RTYPE_NUM | 7}, \
1530 {"$8", RTYPE_NUM | 8}, \
1531 {"$9", RTYPE_NUM | 9}, \
1532 {"$10", RTYPE_NUM | 10}, \
1533 {"$11", RTYPE_NUM | 11}, \
1534 {"$12", RTYPE_NUM | 12}, \
1535 {"$13", RTYPE_NUM | 13}, \
1536 {"$14", RTYPE_NUM | 14}, \
1537 {"$15", RTYPE_NUM | 15}, \
1538 {"$16", RTYPE_NUM | 16}, \
1539 {"$17", RTYPE_NUM | 17}, \
1540 {"$18", RTYPE_NUM | 18}, \
1541 {"$19", RTYPE_NUM | 19}, \
1542 {"$20", RTYPE_NUM | 20}, \
1543 {"$21", RTYPE_NUM | 21}, \
1544 {"$22", RTYPE_NUM | 22}, \
1545 {"$23", RTYPE_NUM | 23}, \
1546 {"$24", RTYPE_NUM | 24}, \
1547 {"$25", RTYPE_NUM | 25}, \
1548 {"$26", RTYPE_NUM | 26}, \
1549 {"$27", RTYPE_NUM | 27}, \
1550 {"$28", RTYPE_NUM | 28}, \
1551 {"$29", RTYPE_NUM | 29}, \
1552 {"$30", RTYPE_NUM | 30}, \
1553 {"$31", RTYPE_NUM | 31}
1555 #define FPU_REGISTER_NAMES \
1556 {"$f0", RTYPE_FPU | 0}, \
1557 {"$f1", RTYPE_FPU | 1}, \
1558 {"$f2", RTYPE_FPU | 2}, \
1559 {"$f3", RTYPE_FPU | 3}, \
1560 {"$f4", RTYPE_FPU | 4}, \
1561 {"$f5", RTYPE_FPU | 5}, \
1562 {"$f6", RTYPE_FPU | 6}, \
1563 {"$f7", RTYPE_FPU | 7}, \
1564 {"$f8", RTYPE_FPU | 8}, \
1565 {"$f9", RTYPE_FPU | 9}, \
1566 {"$f10", RTYPE_FPU | 10}, \
1567 {"$f11", RTYPE_FPU | 11}, \
1568 {"$f12", RTYPE_FPU | 12}, \
1569 {"$f13", RTYPE_FPU | 13}, \
1570 {"$f14", RTYPE_FPU | 14}, \
1571 {"$f15", RTYPE_FPU | 15}, \
1572 {"$f16", RTYPE_FPU | 16}, \
1573 {"$f17", RTYPE_FPU | 17}, \
1574 {"$f18", RTYPE_FPU | 18}, \
1575 {"$f19", RTYPE_FPU | 19}, \
1576 {"$f20", RTYPE_FPU | 20}, \
1577 {"$f21", RTYPE_FPU | 21}, \
1578 {"$f22", RTYPE_FPU | 22}, \
1579 {"$f23", RTYPE_FPU | 23}, \
1580 {"$f24", RTYPE_FPU | 24}, \
1581 {"$f25", RTYPE_FPU | 25}, \
1582 {"$f26", RTYPE_FPU | 26}, \
1583 {"$f27", RTYPE_FPU | 27}, \
1584 {"$f28", RTYPE_FPU | 28}, \
1585 {"$f29", RTYPE_FPU | 29}, \
1586 {"$f30", RTYPE_FPU | 30}, \
1587 {"$f31", RTYPE_FPU | 31}
1589 #define FPU_CONDITION_CODE_NAMES \
1590 {"$fcc0", RTYPE_FCC | 0}, \
1591 {"$fcc1", RTYPE_FCC | 1}, \
1592 {"$fcc2", RTYPE_FCC | 2}, \
1593 {"$fcc3", RTYPE_FCC | 3}, \
1594 {"$fcc4", RTYPE_FCC | 4}, \
1595 {"$fcc5", RTYPE_FCC | 5}, \
1596 {"$fcc6", RTYPE_FCC | 6}, \
1597 {"$fcc7", RTYPE_FCC | 7}
1599 #define COPROC_CONDITION_CODE_NAMES \
1600 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1601 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1602 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1603 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1604 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1605 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1606 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1607 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1609 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1610 {"$a4", RTYPE_GP | 8}, \
1611 {"$a5", RTYPE_GP | 9}, \
1612 {"$a6", RTYPE_GP | 10}, \
1613 {"$a7", RTYPE_GP | 11}, \
1614 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1615 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1616 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1617 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1618 {"$t0", RTYPE_GP | 12}, \
1619 {"$t1", RTYPE_GP | 13}, \
1620 {"$t2", RTYPE_GP | 14}, \
1621 {"$t3", RTYPE_GP | 15}
1623 #define O32_SYMBOLIC_REGISTER_NAMES \
1624 {"$t0", RTYPE_GP | 8}, \
1625 {"$t1", RTYPE_GP | 9}, \
1626 {"$t2", RTYPE_GP | 10}, \
1627 {"$t3", RTYPE_GP | 11}, \
1628 {"$t4", RTYPE_GP | 12}, \
1629 {"$t5", RTYPE_GP | 13}, \
1630 {"$t6", RTYPE_GP | 14}, \
1631 {"$t7", RTYPE_GP | 15}, \
1632 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1633 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1634 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1635 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1637 /* Remaining symbolic register names */
1638 #define SYMBOLIC_REGISTER_NAMES \
1639 {"$zero", RTYPE_GP | 0}, \
1640 {"$at", RTYPE_GP | 1}, \
1641 {"$AT", RTYPE_GP | 1}, \
1642 {"$v0", RTYPE_GP | 2}, \
1643 {"$v1", RTYPE_GP | 3}, \
1644 {"$a0", RTYPE_GP | 4}, \
1645 {"$a1", RTYPE_GP | 5}, \
1646 {"$a2", RTYPE_GP | 6}, \
1647 {"$a3", RTYPE_GP | 7}, \
1648 {"$s0", RTYPE_GP | 16}, \
1649 {"$s1", RTYPE_GP | 17}, \
1650 {"$s2", RTYPE_GP | 18}, \
1651 {"$s3", RTYPE_GP | 19}, \
1652 {"$s4", RTYPE_GP | 20}, \
1653 {"$s5", RTYPE_GP | 21}, \
1654 {"$s6", RTYPE_GP | 22}, \
1655 {"$s7", RTYPE_GP | 23}, \
1656 {"$t8", RTYPE_GP | 24}, \
1657 {"$t9", RTYPE_GP | 25}, \
1658 {"$k0", RTYPE_GP | 26}, \
1659 {"$kt0", RTYPE_GP | 26}, \
1660 {"$k1", RTYPE_GP | 27}, \
1661 {"$kt1", RTYPE_GP | 27}, \
1662 {"$gp", RTYPE_GP | 28}, \
1663 {"$sp", RTYPE_GP | 29}, \
1664 {"$s8", RTYPE_GP | 30}, \
1665 {"$fp", RTYPE_GP | 30}, \
1666 {"$ra", RTYPE_GP | 31}
1668 #define MIPS16_SPECIAL_REGISTER_NAMES \
1669 {"$pc", RTYPE_PC | 0}
1671 #define MDMX_VECTOR_REGISTER_NAMES \
1672 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1673 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1674 {"$v2", RTYPE_VEC | 2}, \
1675 {"$v3", RTYPE_VEC | 3}, \
1676 {"$v4", RTYPE_VEC | 4}, \
1677 {"$v5", RTYPE_VEC | 5}, \
1678 {"$v6", RTYPE_VEC | 6}, \
1679 {"$v7", RTYPE_VEC | 7}, \
1680 {"$v8", RTYPE_VEC | 8}, \
1681 {"$v9", RTYPE_VEC | 9}, \
1682 {"$v10", RTYPE_VEC | 10}, \
1683 {"$v11", RTYPE_VEC | 11}, \
1684 {"$v12", RTYPE_VEC | 12}, \
1685 {"$v13", RTYPE_VEC | 13}, \
1686 {"$v14", RTYPE_VEC | 14}, \
1687 {"$v15", RTYPE_VEC | 15}, \
1688 {"$v16", RTYPE_VEC | 16}, \
1689 {"$v17", RTYPE_VEC | 17}, \
1690 {"$v18", RTYPE_VEC | 18}, \
1691 {"$v19", RTYPE_VEC | 19}, \
1692 {"$v20", RTYPE_VEC | 20}, \
1693 {"$v21", RTYPE_VEC | 21}, \
1694 {"$v22", RTYPE_VEC | 22}, \
1695 {"$v23", RTYPE_VEC | 23}, \
1696 {"$v24", RTYPE_VEC | 24}, \
1697 {"$v25", RTYPE_VEC | 25}, \
1698 {"$v26", RTYPE_VEC | 26}, \
1699 {"$v27", RTYPE_VEC | 27}, \
1700 {"$v28", RTYPE_VEC | 28}, \
1701 {"$v29", RTYPE_VEC | 29}, \
1702 {"$v30", RTYPE_VEC | 30}, \
1703 {"$v31", RTYPE_VEC | 31}
1705 #define MIPS_DSP_ACCUMULATOR_NAMES \
1706 {"$ac0", RTYPE_ACC | 0}, \
1707 {"$ac1", RTYPE_ACC | 1}, \
1708 {"$ac2", RTYPE_ACC | 2}, \
1709 {"$ac3", RTYPE_ACC | 3}
1711 static const struct regname reg_names
[] = {
1712 GENERIC_REGISTER_NUMBERS
,
1714 FPU_CONDITION_CODE_NAMES
,
1715 COPROC_CONDITION_CODE_NAMES
,
1717 /* The $txx registers depends on the abi,
1718 these will be added later into the symbol table from
1719 one of the tables below once mips_abi is set after
1720 parsing of arguments from the command line. */
1721 SYMBOLIC_REGISTER_NAMES
,
1723 MIPS16_SPECIAL_REGISTER_NAMES
,
1724 MDMX_VECTOR_REGISTER_NAMES
,
1725 MIPS_DSP_ACCUMULATOR_NAMES
,
1729 static const struct regname reg_names_o32
[] = {
1730 O32_SYMBOLIC_REGISTER_NAMES
,
1734 static const struct regname reg_names_n32n64
[] = {
1735 N32N64_SYMBOLIC_REGISTER_NAMES
,
1740 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1747 /* Find end of name. */
1749 if (is_name_beginner (*e
))
1751 while (is_part_of_name (*e
))
1754 /* Terminate name. */
1758 /* Look for a register symbol. */
1759 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1761 int r
= S_GET_VALUE (symbolP
);
1763 reg
= r
& RNUM_MASK
;
1764 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1765 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1766 reg
= (r
& RNUM_MASK
) - 2;
1768 /* Else see if this is a register defined in an itbl entry. */
1769 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1776 if (itbl_get_reg_val (n
, &r
))
1777 reg
= r
& RNUM_MASK
;
1780 /* Advance to next token if a register was recognised. */
1783 else if (types
& RWARN
)
1784 as_warn ("Unrecognized register name `%s'", *s
);
1792 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1793 architecture. If EXPANSIONP is TRUE then this check is done while
1794 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1797 is_opcode_valid (const struct mips_opcode
*mo
, bfd_boolean expansionp
)
1799 int isa
= mips_opts
.isa
;
1802 if (mips_opts
.ase_mdmx
)
1804 if (mips_opts
.ase_dsp
)
1806 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1808 if (mips_opts
.ase_dspr2
)
1810 if (mips_opts
.ase_mt
)
1812 if (mips_opts
.ase_mips3d
)
1814 if (mips_opts
.ase_smartmips
)
1815 isa
|= INSN_SMARTMIPS
;
1817 /* For user code we don't check for mips_opts.mips16 since we want
1818 to allow jalx if -mips16 was specified on the command line. */
1819 if (expansionp
? mips_opts
.mips16
: file_ase_mips16
)
1822 /* Don't accept instructions based on the ISA if the CPU does not implement
1823 all the coprocessor insns. */
1824 if (NO_ISA_COP (mips_opts
.arch
)
1825 && COP_INSN (mo
->pinfo
))
1828 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1831 /* Check whether the instruction or macro requires single-precision or
1832 double-precision floating-point support. Note that this information is
1833 stored differently in the opcode table for insns and macros. */
1834 if (mo
->pinfo
== INSN_MACRO
)
1836 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1837 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1841 fp_s
= mo
->pinfo
& FP_S
;
1842 fp_d
= mo
->pinfo
& FP_D
;
1845 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1848 if (fp_s
&& mips_opts
.soft_float
)
1854 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1855 selected ISA and architecture. */
1858 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1860 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1863 /* This function is called once, at assembler startup time. It should set up
1864 all the tables, etc. that the MD part of the assembler will need. */
1869 const char *retval
= NULL
;
1873 if (mips_pic
!= NO_PIC
)
1875 if (g_switch_seen
&& g_switch_value
!= 0)
1876 as_bad (_("-G may not be used in position-independent code"));
1880 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1881 as_warn (_("Could not set architecture and machine"));
1883 op_hash
= hash_new ();
1885 for (i
= 0; i
< NUMOPCODES
;)
1887 const char *name
= mips_opcodes
[i
].name
;
1889 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1892 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1893 mips_opcodes
[i
].name
, retval
);
1894 /* Probably a memory allocation problem? Give up now. */
1895 as_fatal (_("Broken assembler. No assembly attempted."));
1899 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1901 if (!validate_mips_insn (&mips_opcodes
[i
]))
1903 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1905 create_insn (&nop_insn
, mips_opcodes
+ i
);
1906 nop_insn
.fixed_p
= 1;
1911 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1914 mips16_op_hash
= hash_new ();
1917 while (i
< bfd_mips16_num_opcodes
)
1919 const char *name
= mips16_opcodes
[i
].name
;
1921 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1923 as_fatal (_("internal: can't hash `%s': %s"),
1924 mips16_opcodes
[i
].name
, retval
);
1927 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1928 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1929 != mips16_opcodes
[i
].match
))
1931 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1932 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1935 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1937 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1938 mips16_nop_insn
.fixed_p
= 1;
1942 while (i
< bfd_mips16_num_opcodes
1943 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1947 as_fatal (_("Broken assembler. No assembly attempted."));
1949 /* We add all the general register names to the symbol table. This
1950 helps us detect invalid uses of them. */
1951 for (i
= 0; reg_names
[i
].name
; i
++)
1952 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1953 reg_names
[i
].num
, /* & RNUM_MASK, */
1954 &zero_address_frag
));
1956 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1957 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1958 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1959 &zero_address_frag
));
1961 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1962 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1963 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1964 &zero_address_frag
));
1966 mips_no_prev_insn ();
1969 mips_cprmask
[0] = 0;
1970 mips_cprmask
[1] = 0;
1971 mips_cprmask
[2] = 0;
1972 mips_cprmask
[3] = 0;
1974 /* set the default alignment for the text section (2**2) */
1975 record_alignment (text_section
, 2);
1977 bfd_set_gp_size (stdoutput
, g_switch_value
);
1982 /* On a native system other than VxWorks, sections must be aligned
1983 to 16 byte boundaries. When configured for an embedded ELF
1984 target, we don't bother. */
1985 if (strncmp (TARGET_OS
, "elf", 3) != 0
1986 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
1988 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1989 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1990 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1993 /* Create a .reginfo section for register masks and a .mdebug
1994 section for debugging information. */
2002 subseg
= now_subseg
;
2004 /* The ABI says this section should be loaded so that the
2005 running program can access it. However, we don't load it
2006 if we are configured for an embedded target */
2007 flags
= SEC_READONLY
| SEC_DATA
;
2008 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2009 flags
|= SEC_ALLOC
| SEC_LOAD
;
2011 if (mips_abi
!= N64_ABI
)
2013 sec
= subseg_new (".reginfo", (subsegT
) 0);
2015 bfd_set_section_flags (stdoutput
, sec
, flags
);
2016 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2018 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2022 /* The 64-bit ABI uses a .MIPS.options section rather than
2023 .reginfo section. */
2024 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2025 bfd_set_section_flags (stdoutput
, sec
, flags
);
2026 bfd_set_section_alignment (stdoutput
, sec
, 3);
2028 /* Set up the option header. */
2030 Elf_Internal_Options opthdr
;
2033 opthdr
.kind
= ODK_REGINFO
;
2034 opthdr
.size
= (sizeof (Elf_External_Options
)
2035 + sizeof (Elf64_External_RegInfo
));
2038 f
= frag_more (sizeof (Elf_External_Options
));
2039 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2040 (Elf_External_Options
*) f
);
2042 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2046 if (ECOFF_DEBUGGING
)
2048 sec
= subseg_new (".mdebug", (subsegT
) 0);
2049 (void) bfd_set_section_flags (stdoutput
, sec
,
2050 SEC_HAS_CONTENTS
| SEC_READONLY
);
2051 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2053 else if (mips_flag_pdr
)
2055 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2056 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2057 SEC_READONLY
| SEC_RELOC
2059 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2062 subseg_set (seg
, subseg
);
2065 #endif /* OBJ_ELF */
2067 if (! ECOFF_DEBUGGING
)
2070 if (mips_fix_vr4120
)
2071 init_vr4120_conflicts ();
2077 if (! ECOFF_DEBUGGING
)
2082 md_assemble (char *str
)
2084 struct mips_cl_insn insn
;
2085 bfd_reloc_code_real_type unused_reloc
[3]
2086 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2088 imm_expr
.X_op
= O_absent
;
2089 imm2_expr
.X_op
= O_absent
;
2090 offset_expr
.X_op
= O_absent
;
2091 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2092 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2093 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2094 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2095 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2096 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2098 if (mips_opts
.mips16
)
2099 mips16_ip (str
, &insn
);
2102 mips_ip (str
, &insn
);
2103 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2104 str
, insn
.insn_opcode
));
2109 as_bad ("%s `%s'", insn_error
, str
);
2113 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2116 if (mips_opts
.mips16
)
2117 mips16_macro (&insn
);
2124 if (imm_expr
.X_op
!= O_absent
)
2125 append_insn (&insn
, &imm_expr
, imm_reloc
);
2126 else if (offset_expr
.X_op
!= O_absent
)
2127 append_insn (&insn
, &offset_expr
, offset_reloc
);
2129 append_insn (&insn
, NULL
, unused_reloc
);
2133 /* Convenience functions for abstracting away the differences between
2134 MIPS16 and non-MIPS16 relocations. */
2136 static inline bfd_boolean
2137 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2141 case BFD_RELOC_MIPS16_JMP
:
2142 case BFD_RELOC_MIPS16_GPREL
:
2143 case BFD_RELOC_MIPS16_GOT16
:
2144 case BFD_RELOC_MIPS16_CALL16
:
2145 case BFD_RELOC_MIPS16_HI16_S
:
2146 case BFD_RELOC_MIPS16_HI16
:
2147 case BFD_RELOC_MIPS16_LO16
:
2155 static inline bfd_boolean
2156 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2158 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2161 static inline bfd_boolean
2162 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2164 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2167 static inline bfd_boolean
2168 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2170 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2173 /* Return true if the given relocation might need a matching %lo().
2174 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2175 need a matching %lo() when applied to local symbols. */
2177 static inline bfd_boolean
2178 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2180 return (HAVE_IN_PLACE_ADDENDS
2181 && (hi16_reloc_p (reloc
)
2182 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2183 all GOT16 relocations evaluate to "G". */
2184 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2187 /* Return the type of %lo() reloc needed by RELOC, given that
2188 reloc_needs_lo_p. */
2190 static inline bfd_reloc_code_real_type
2191 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2193 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2196 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2199 static inline bfd_boolean
2200 fixup_has_matching_lo_p (fixS
*fixp
)
2202 return (fixp
->fx_next
!= NULL
2203 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2204 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2205 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2208 /* See whether instruction IP reads register REG. CLASS is the type
2212 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2213 enum mips_regclass
class)
2215 if (class == MIPS16_REG
)
2217 assert (mips_opts
.mips16
);
2218 reg
= mips16_to_32_reg_map
[reg
];
2219 class = MIPS_GR_REG
;
2222 /* Don't report on general register ZERO, since it never changes. */
2223 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2226 if (class == MIPS_FP_REG
)
2228 assert (! mips_opts
.mips16
);
2229 /* If we are called with either $f0 or $f1, we must check $f0.
2230 This is not optimal, because it will introduce an unnecessary
2231 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2232 need to distinguish reading both $f0 and $f1 or just one of
2233 them. Note that we don't have to check the other way,
2234 because there is no instruction that sets both $f0 and $f1
2235 and requires a delay. */
2236 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2237 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2238 == (reg
&~ (unsigned) 1)))
2240 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2241 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2242 == (reg
&~ (unsigned) 1)))
2245 else if (! mips_opts
.mips16
)
2247 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2248 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2250 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2251 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2256 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2257 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2259 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2260 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2262 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2263 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2266 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2268 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2270 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2272 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2273 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2280 /* This function returns true if modifying a register requires a
2284 reg_needs_delay (unsigned int reg
)
2286 unsigned long prev_pinfo
;
2288 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2289 if (! mips_opts
.noreorder
2290 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2291 && ! gpr_interlocks
)
2292 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2293 && ! cop_interlocks
)))
2295 /* A load from a coprocessor or from memory. All load delays
2296 delay the use of general register rt for one instruction. */
2297 /* Itbl support may require additional care here. */
2298 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2299 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2306 /* Move all labels in insn_labels to the current insertion point. */
2309 mips_move_labels (void)
2311 segment_info_type
*si
= seg_info (now_seg
);
2312 struct insn_label_list
*l
;
2315 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2317 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2318 symbol_set_frag (l
->label
, frag_now
);
2319 val
= (valueT
) frag_now_fix ();
2320 /* mips16 text labels are stored as odd. */
2321 if (mips_opts
.mips16
)
2323 S_SET_VALUE (l
->label
, val
);
2328 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2330 bfd_boolean linkonce
= FALSE
;
2331 segT symseg
= S_GET_SEGMENT (sym
);
2333 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2335 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2338 /* The GNU toolchain uses an extension for ELF: a section
2339 beginning with the magic string .gnu.linkonce is a
2340 linkonce section. */
2341 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2342 sizeof ".gnu.linkonce" - 1) == 0)
2349 /* Mark instruction labels in mips16 mode. This permits the linker to
2350 handle them specially, such as generating jalx instructions when
2351 needed. We also make them odd for the duration of the assembly, in
2352 order to generate the right sort of code. We will make them even
2353 in the adjust_symtab routine, while leaving them marked. This is
2354 convenient for the debugger and the disassembler. The linker knows
2355 to make them odd again. */
2358 mips16_mark_labels (void)
2360 segment_info_type
*si
= seg_info (now_seg
);
2361 struct insn_label_list
*l
;
2363 if (!mips_opts
.mips16
)
2366 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2368 symbolS
*label
= l
->label
;
2370 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2372 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2374 if ((S_GET_VALUE (label
) & 1) == 0
2375 /* Don't adjust the address if the label is global or weak, or
2376 in a link-once section, since we'll be emitting symbol reloc
2377 references to it which will be patched up by the linker, and
2378 the final value of the symbol may or may not be MIPS16. */
2379 && ! S_IS_WEAK (label
)
2380 && ! S_IS_EXTERNAL (label
)
2381 && ! s_is_linkonce (label
, now_seg
))
2382 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2386 /* End the current frag. Make it a variant frag and record the
2390 relax_close_frag (void)
2392 mips_macro_warning
.first_frag
= frag_now
;
2393 frag_var (rs_machine_dependent
, 0, 0,
2394 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2395 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2397 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2398 mips_relax
.first_fixup
= 0;
2401 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2402 See the comment above RELAX_ENCODE for more details. */
2405 relax_start (symbolS
*symbol
)
2407 assert (mips_relax
.sequence
== 0);
2408 mips_relax
.sequence
= 1;
2409 mips_relax
.symbol
= symbol
;
2412 /* Start generating the second version of a relaxable sequence.
2413 See the comment above RELAX_ENCODE for more details. */
2418 assert (mips_relax
.sequence
== 1);
2419 mips_relax
.sequence
= 2;
2422 /* End the current relaxable sequence. */
2427 assert (mips_relax
.sequence
== 2);
2428 relax_close_frag ();
2429 mips_relax
.sequence
= 0;
2432 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2433 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2434 by VR4120 errata. */
2437 classify_vr4120_insn (const char *name
)
2439 if (strncmp (name
, "macc", 4) == 0)
2440 return FIX_VR4120_MACC
;
2441 if (strncmp (name
, "dmacc", 5) == 0)
2442 return FIX_VR4120_DMACC
;
2443 if (strncmp (name
, "mult", 4) == 0)
2444 return FIX_VR4120_MULT
;
2445 if (strncmp (name
, "dmult", 5) == 0)
2446 return FIX_VR4120_DMULT
;
2447 if (strstr (name
, "div"))
2448 return FIX_VR4120_DIV
;
2449 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2450 return FIX_VR4120_MTHILO
;
2451 return NUM_FIX_VR4120_CLASSES
;
2454 /* Return the number of instructions that must separate INSN1 and INSN2,
2455 where INSN1 is the earlier instruction. Return the worst-case value
2456 for any INSN2 if INSN2 is null. */
2459 insns_between (const struct mips_cl_insn
*insn1
,
2460 const struct mips_cl_insn
*insn2
)
2462 unsigned long pinfo1
, pinfo2
;
2464 /* This function needs to know which pinfo flags are set for INSN2
2465 and which registers INSN2 uses. The former is stored in PINFO2 and
2466 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2467 will have every flag set and INSN2_USES_REG will always return true. */
2468 pinfo1
= insn1
->insn_mo
->pinfo
;
2469 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2471 #define INSN2_USES_REG(REG, CLASS) \
2472 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2474 /* For most targets, write-after-read dependencies on the HI and LO
2475 registers must be separated by at least two instructions. */
2476 if (!hilo_interlocks
)
2478 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2480 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2484 /* If we're working around r7000 errata, there must be two instructions
2485 between an mfhi or mflo and any instruction that uses the result. */
2486 if (mips_7000_hilo_fix
2487 && MF_HILO_INSN (pinfo1
)
2488 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2491 /* If working around VR4120 errata, check for combinations that need
2492 a single intervening instruction. */
2493 if (mips_fix_vr4120
)
2495 unsigned int class1
, class2
;
2497 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2498 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2502 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2503 if (vr4120_conflicts
[class1
] & (1 << class2
))
2508 if (!mips_opts
.mips16
)
2510 /* Check for GPR or coprocessor load delays. All such delays
2511 are on the RT register. */
2512 /* Itbl support may require additional care here. */
2513 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2514 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2516 know (pinfo1
& INSN_WRITE_GPR_T
);
2517 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2521 /* Check for generic coprocessor hazards.
2523 This case is not handled very well. There is no special
2524 knowledge of CP0 handling, and the coprocessors other than
2525 the floating point unit are not distinguished at all. */
2526 /* Itbl support may require additional care here. FIXME!
2527 Need to modify this to include knowledge about
2528 user specified delays! */
2529 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2530 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2532 /* Handle cases where INSN1 writes to a known general coprocessor
2533 register. There must be a one instruction delay before INSN2
2534 if INSN2 reads that register, otherwise no delay is needed. */
2535 if (pinfo1
& INSN_WRITE_FPR_T
)
2537 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2540 else if (pinfo1
& INSN_WRITE_FPR_S
)
2542 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2547 /* Read-after-write dependencies on the control registers
2548 require a two-instruction gap. */
2549 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2550 && (pinfo2
& INSN_READ_COND_CODE
))
2553 /* We don't know exactly what INSN1 does. If INSN2 is
2554 also a coprocessor instruction, assume there must be
2555 a one instruction gap. */
2556 if (pinfo2
& INSN_COP
)
2561 /* Check for read-after-write dependencies on the coprocessor
2562 control registers in cases where INSN1 does not need a general
2563 coprocessor delay. This means that INSN1 is a floating point
2564 comparison instruction. */
2565 /* Itbl support may require additional care here. */
2566 else if (!cop_interlocks
2567 && (pinfo1
& INSN_WRITE_COND_CODE
)
2568 && (pinfo2
& INSN_READ_COND_CODE
))
2572 #undef INSN2_USES_REG
2577 /* Return the number of nops that would be needed to work around the
2578 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2579 the MAX_VR4130_NOPS instructions described by HISTORY. */
2582 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2583 const struct mips_cl_insn
*insn
)
2587 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2588 are not affected by the errata. */
2590 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2591 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2592 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2595 /* Search for the first MFLO or MFHI. */
2596 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2597 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2599 /* Extract the destination register. */
2600 if (mips_opts
.mips16
)
2601 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2603 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2605 /* No nops are needed if INSN reads that register. */
2606 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2609 /* ...or if any of the intervening instructions do. */
2610 for (j
= 0; j
< i
; j
++)
2611 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2614 return MAX_VR4130_NOPS
- i
;
2619 /* Return the number of nops that would be needed if instruction INSN
2620 immediately followed the MAX_NOPS instructions given by HISTORY,
2621 where HISTORY[0] is the most recent instruction. If INSN is null,
2622 return the worse-case number of nops for any instruction. */
2625 nops_for_insn (const struct mips_cl_insn
*history
,
2626 const struct mips_cl_insn
*insn
)
2628 int i
, nops
, tmp_nops
;
2631 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2632 if (!history
[i
].noreorder_p
)
2634 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2635 if (tmp_nops
> nops
)
2639 if (mips_fix_vr4130
)
2641 tmp_nops
= nops_for_vr4130 (history
, insn
);
2642 if (tmp_nops
> nops
)
2649 /* The variable arguments provide NUM_INSNS extra instructions that
2650 might be added to HISTORY. Return the largest number of nops that
2651 would be needed after the extended sequence. */
2654 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2657 struct mips_cl_insn buffer
[MAX_NOPS
];
2658 struct mips_cl_insn
*cursor
;
2661 va_start (args
, history
);
2662 cursor
= buffer
+ num_insns
;
2663 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2664 while (cursor
> buffer
)
2665 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2667 nops
= nops_for_insn (buffer
, NULL
);
2672 /* Like nops_for_insn, but if INSN is a branch, take into account the
2673 worst-case delay for the branch target. */
2676 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2677 const struct mips_cl_insn
*insn
)
2681 nops
= nops_for_insn (history
, insn
);
2682 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2683 | INSN_COND_BRANCH_DELAY
2684 | INSN_COND_BRANCH_LIKELY
))
2686 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2687 if (tmp_nops
> nops
)
2690 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2692 tmp_nops
= nops_for_sequence (1, history
, insn
);
2693 if (tmp_nops
> nops
)
2699 /* Output an instruction. IP is the instruction information.
2700 ADDRESS_EXPR is an operand of the instruction to be used with
2704 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2705 bfd_reloc_code_real_type
*reloc_type
)
2707 unsigned long prev_pinfo
, pinfo
;
2708 relax_stateT prev_insn_frag_type
= 0;
2709 bfd_boolean relaxed_branch
= FALSE
;
2710 segment_info_type
*si
= seg_info (now_seg
);
2712 /* Mark instruction labels in mips16 mode. */
2713 mips16_mark_labels ();
2715 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2716 pinfo
= ip
->insn_mo
->pinfo
;
2718 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2720 /* There are a lot of optimizations we could do that we don't.
2721 In particular, we do not, in general, reorder instructions.
2722 If you use gcc with optimization, it will reorder
2723 instructions and generally do much more optimization then we
2724 do here; repeating all that work in the assembler would only
2725 benefit hand written assembly code, and does not seem worth
2727 int nops
= (mips_optimize
== 0
2728 ? nops_for_insn (history
, NULL
)
2729 : nops_for_insn_or_target (history
, ip
));
2733 unsigned long old_frag_offset
;
2736 old_frag
= frag_now
;
2737 old_frag_offset
= frag_now_fix ();
2739 for (i
= 0; i
< nops
; i
++)
2744 listing_prev_line ();
2745 /* We may be at the start of a variant frag. In case we
2746 are, make sure there is enough space for the frag
2747 after the frags created by listing_prev_line. The
2748 argument to frag_grow here must be at least as large
2749 as the argument to all other calls to frag_grow in
2750 this file. We don't have to worry about being in the
2751 middle of a variant frag, because the variants insert
2752 all needed nop instructions themselves. */
2756 mips_move_labels ();
2758 #ifndef NO_ECOFF_DEBUGGING
2759 if (ECOFF_DEBUGGING
)
2760 ecoff_fix_loc (old_frag
, old_frag_offset
);
2764 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2766 /* Work out how many nops in prev_nop_frag are needed by IP. */
2767 int nops
= nops_for_insn_or_target (history
, ip
);
2768 assert (nops
<= prev_nop_frag_holds
);
2770 /* Enforce NOPS as a minimum. */
2771 if (nops
> prev_nop_frag_required
)
2772 prev_nop_frag_required
= nops
;
2774 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2776 /* Settle for the current number of nops. Update the history
2777 accordingly (for the benefit of any future .set reorder code). */
2778 prev_nop_frag
= NULL
;
2779 insert_into_history (prev_nop_frag_since
,
2780 prev_nop_frag_holds
, NOP_INSN
);
2784 /* Allow this instruction to replace one of the nops that was
2785 tentatively added to prev_nop_frag. */
2786 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2787 prev_nop_frag_holds
--;
2788 prev_nop_frag_since
++;
2793 /* The value passed to dwarf2_emit_insn is the distance between
2794 the beginning of the current instruction and the address that
2795 should be recorded in the debug tables. For MIPS16 debug info
2796 we want to use ISA-encoded addresses, so we pass -1 for an
2797 address higher by one than the current. */
2798 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2801 /* Record the frag type before frag_var. */
2802 if (history
[0].frag
)
2803 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2806 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2807 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2808 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2809 && mips_relax_branch
2810 /* Don't try branch relaxation within .set nomacro, or within
2811 .set noat if we use $at for PIC computations. If it turns
2812 out that the branch was out-of-range, we'll get an error. */
2813 && !mips_opts
.warn_about_macros
2814 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2815 && !mips_opts
.mips16
)
2817 relaxed_branch
= TRUE
;
2818 add_relaxed_insn (ip
, (relaxed_branch_length
2820 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2821 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2824 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2825 pinfo
& INSN_COND_BRANCH_LIKELY
,
2826 pinfo
& INSN_WRITE_GPR_31
,
2828 address_expr
->X_add_symbol
,
2829 address_expr
->X_add_number
);
2830 *reloc_type
= BFD_RELOC_UNUSED
;
2832 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2834 /* We need to set up a variant frag. */
2835 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2836 add_relaxed_insn (ip
, 4, 0,
2838 (*reloc_type
- BFD_RELOC_UNUSED
,
2839 mips16_small
, mips16_ext
,
2840 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2841 history
[0].mips16_absolute_jump_p
),
2842 make_expr_symbol (address_expr
), 0);
2844 else if (mips_opts
.mips16
2846 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2848 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2849 /* Make sure there is enough room to swap this instruction with
2850 a following jump instruction. */
2852 add_fixed_insn (ip
);
2856 if (mips_opts
.mips16
2857 && mips_opts
.noreorder
2858 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2859 as_warn (_("extended instruction in delay slot"));
2861 if (mips_relax
.sequence
)
2863 /* If we've reached the end of this frag, turn it into a variant
2864 frag and record the information for the instructions we've
2866 if (frag_room () < 4)
2867 relax_close_frag ();
2868 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2871 if (mips_relax
.sequence
!= 2)
2872 mips_macro_warning
.sizes
[0] += 4;
2873 if (mips_relax
.sequence
!= 1)
2874 mips_macro_warning
.sizes
[1] += 4;
2876 if (mips_opts
.mips16
)
2879 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2881 add_fixed_insn (ip
);
2884 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2886 if (address_expr
->X_op
== O_constant
)
2890 switch (*reloc_type
)
2893 ip
->insn_opcode
|= address_expr
->X_add_number
;
2896 case BFD_RELOC_MIPS_HIGHEST
:
2897 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2898 ip
->insn_opcode
|= tmp
& 0xffff;
2901 case BFD_RELOC_MIPS_HIGHER
:
2902 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2903 ip
->insn_opcode
|= tmp
& 0xffff;
2906 case BFD_RELOC_HI16_S
:
2907 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2908 ip
->insn_opcode
|= tmp
& 0xffff;
2911 case BFD_RELOC_HI16
:
2912 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2915 case BFD_RELOC_UNUSED
:
2916 case BFD_RELOC_LO16
:
2917 case BFD_RELOC_MIPS_GOT_DISP
:
2918 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2921 case BFD_RELOC_MIPS_JMP
:
2922 if ((address_expr
->X_add_number
& 3) != 0)
2923 as_bad (_("jump to misaligned address (0x%lx)"),
2924 (unsigned long) address_expr
->X_add_number
);
2925 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2928 case BFD_RELOC_MIPS16_JMP
:
2929 if ((address_expr
->X_add_number
& 3) != 0)
2930 as_bad (_("jump to misaligned address (0x%lx)"),
2931 (unsigned long) address_expr
->X_add_number
);
2933 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2934 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2935 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2938 case BFD_RELOC_16_PCREL_S2
:
2939 if ((address_expr
->X_add_number
& 3) != 0)
2940 as_bad (_("branch to misaligned address (0x%lx)"),
2941 (unsigned long) address_expr
->X_add_number
);
2942 if (mips_relax_branch
)
2944 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2945 as_bad (_("branch address range overflow (0x%lx)"),
2946 (unsigned long) address_expr
->X_add_number
);
2947 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2954 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2957 reloc_howto_type
*howto
;
2960 /* In a compound relocation, it is the final (outermost)
2961 operator that determines the relocated field. */
2962 for (i
= 1; i
< 3; i
++)
2963 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2966 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2967 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2968 bfd_get_reloc_size (howto
),
2970 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2973 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2974 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2975 && ip
->fixp
[0]->fx_addsy
)
2976 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2978 /* These relocations can have an addend that won't fit in
2979 4 octets for 64bit assembly. */
2981 && ! howto
->partial_inplace
2982 && (reloc_type
[0] == BFD_RELOC_16
2983 || reloc_type
[0] == BFD_RELOC_32
2984 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2985 || reloc_type
[0] == BFD_RELOC_GPREL16
2986 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2987 || reloc_type
[0] == BFD_RELOC_GPREL32
2988 || reloc_type
[0] == BFD_RELOC_64
2989 || reloc_type
[0] == BFD_RELOC_CTOR
2990 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2991 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2992 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2993 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2994 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2995 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2996 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2997 || hi16_reloc_p (reloc_type
[0])
2998 || lo16_reloc_p (reloc_type
[0])))
2999 ip
->fixp
[0]->fx_no_overflow
= 1;
3001 if (mips_relax
.sequence
)
3003 if (mips_relax
.first_fixup
== 0)
3004 mips_relax
.first_fixup
= ip
->fixp
[0];
3006 else if (reloc_needs_lo_p (*reloc_type
))
3008 struct mips_hi_fixup
*hi_fixup
;
3010 /* Reuse the last entry if it already has a matching %lo. */
3011 hi_fixup
= mips_hi_fixup_list
;
3013 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3015 hi_fixup
= ((struct mips_hi_fixup
*)
3016 xmalloc (sizeof (struct mips_hi_fixup
)));
3017 hi_fixup
->next
= mips_hi_fixup_list
;
3018 mips_hi_fixup_list
= hi_fixup
;
3020 hi_fixup
->fixp
= ip
->fixp
[0];
3021 hi_fixup
->seg
= now_seg
;
3024 /* Add fixups for the second and third relocations, if given.
3025 Note that the ABI allows the second relocation to be
3026 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3027 moment we only use RSS_UNDEF, but we could add support
3028 for the others if it ever becomes necessary. */
3029 for (i
= 1; i
< 3; i
++)
3030 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3032 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3033 ip
->fixp
[0]->fx_size
, NULL
, 0,
3034 FALSE
, reloc_type
[i
]);
3036 /* Use fx_tcbit to mark compound relocs. */
3037 ip
->fixp
[0]->fx_tcbit
= 1;
3038 ip
->fixp
[i
]->fx_tcbit
= 1;
3044 /* Update the register mask information. */
3045 if (! mips_opts
.mips16
)
3047 if (pinfo
& INSN_WRITE_GPR_D
)
3048 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3049 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3050 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3051 if (pinfo
& INSN_READ_GPR_S
)
3052 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3053 if (pinfo
& INSN_WRITE_GPR_31
)
3054 mips_gprmask
|= 1 << RA
;
3055 if (pinfo
& INSN_WRITE_FPR_D
)
3056 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3057 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3058 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3059 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3060 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3061 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3062 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3063 if (pinfo
& INSN_COP
)
3065 /* We don't keep enough information to sort these cases out.
3066 The itbl support does keep this information however, although
3067 we currently don't support itbl fprmats as part of the cop
3068 instruction. May want to add this support in the future. */
3070 /* Never set the bit for $0, which is always zero. */
3071 mips_gprmask
&= ~1 << 0;
3075 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3076 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3077 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3078 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3079 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3080 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3081 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3082 mips_gprmask
|= 1 << TREG
;
3083 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3084 mips_gprmask
|= 1 << SP
;
3085 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3086 mips_gprmask
|= 1 << RA
;
3087 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3088 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3089 if (pinfo
& MIPS16_INSN_READ_Z
)
3090 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3091 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3092 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3095 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3097 /* Filling the branch delay slot is more complex. We try to
3098 switch the branch with the previous instruction, which we can
3099 do if the previous instruction does not set up a condition
3100 that the branch tests and if the branch is not itself the
3101 target of any branch. */
3102 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3103 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3105 if (mips_optimize
< 2
3106 /* If we have seen .set volatile or .set nomove, don't
3108 || mips_opts
.nomove
!= 0
3109 /* We can't swap if the previous instruction's position
3111 || history
[0].fixed_p
3112 /* If the previous previous insn was in a .set
3113 noreorder, we can't swap. Actually, the MIPS
3114 assembler will swap in this situation. However, gcc
3115 configured -with-gnu-as will generate code like
3121 in which we can not swap the bne and INSN. If gcc is
3122 not configured -with-gnu-as, it does not output the
3124 || history
[1].noreorder_p
3125 /* If the branch is itself the target of a branch, we
3126 can not swap. We cheat on this; all we check for is
3127 whether there is a label on this instruction. If
3128 there are any branches to anything other than a
3129 label, users must use .set noreorder. */
3130 || si
->label_list
!= NULL
3131 /* If the previous instruction is in a variant frag
3132 other than this branch's one, we cannot do the swap.
3133 This does not apply to the mips16, which uses variant
3134 frags for different purposes. */
3135 || (! mips_opts
.mips16
3136 && prev_insn_frag_type
== rs_machine_dependent
)
3137 /* Check for conflicts between the branch and the instructions
3138 before the candidate delay slot. */
3139 || nops_for_insn (history
+ 1, ip
) > 0
3140 /* Check for conflicts between the swapped sequence and the
3141 target of the branch. */
3142 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3143 /* We do not swap with a trap instruction, since it
3144 complicates trap handlers to have the trap
3145 instruction be in a delay slot. */
3146 || (prev_pinfo
& INSN_TRAP
)
3147 /* If the branch reads a register that the previous
3148 instruction sets, we can not swap. */
3149 || (! mips_opts
.mips16
3150 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3151 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3153 || (! mips_opts
.mips16
3154 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3155 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3157 || (mips_opts
.mips16
3158 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3160 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3162 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3164 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3166 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3168 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3170 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3171 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3172 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3173 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3174 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3175 && insn_uses_reg (ip
,
3176 MIPS16OP_EXTRACT_REG32R
3177 (history
[0].insn_opcode
),
3179 /* If the branch writes a register that the previous
3180 instruction sets, we can not swap (we know that
3181 branches write only to RD or to $31). */
3182 || (! mips_opts
.mips16
3183 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3184 && (((pinfo
& INSN_WRITE_GPR_D
)
3185 && (EXTRACT_OPERAND (RT
, history
[0])
3186 == EXTRACT_OPERAND (RD
, *ip
)))
3187 || ((pinfo
& INSN_WRITE_GPR_31
)
3188 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3189 || (! mips_opts
.mips16
3190 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3191 && (((pinfo
& INSN_WRITE_GPR_D
)
3192 && (EXTRACT_OPERAND (RD
, history
[0])
3193 == EXTRACT_OPERAND (RD
, *ip
)))
3194 || ((pinfo
& INSN_WRITE_GPR_31
)
3195 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3196 || (mips_opts
.mips16
3197 && (pinfo
& MIPS16_INSN_WRITE_31
)
3198 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3199 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3200 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3202 /* If the branch writes a register that the previous
3203 instruction reads, we can not swap (we know that
3204 branches only write to RD or to $31). */
3205 || (! mips_opts
.mips16
3206 && (pinfo
& INSN_WRITE_GPR_D
)
3207 && insn_uses_reg (&history
[0],
3208 EXTRACT_OPERAND (RD
, *ip
),
3210 || (! mips_opts
.mips16
3211 && (pinfo
& INSN_WRITE_GPR_31
)
3212 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3213 || (mips_opts
.mips16
3214 && (pinfo
& MIPS16_INSN_WRITE_31
)
3215 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3216 /* If one instruction sets a condition code and the
3217 other one uses a condition code, we can not swap. */
3218 || ((pinfo
& INSN_READ_COND_CODE
)
3219 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3220 || ((pinfo
& INSN_WRITE_COND_CODE
)
3221 && (prev_pinfo
& INSN_READ_COND_CODE
))
3222 /* If the previous instruction uses the PC, we can not
3224 || (mips_opts
.mips16
3225 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3226 /* If the previous instruction had a fixup in mips16
3227 mode, we can not swap. This normally means that the
3228 previous instruction was a 4 byte branch anyhow. */
3229 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3230 /* If the previous instruction is a sync, sync.l, or
3231 sync.p, we can not swap. */
3232 || (prev_pinfo
& INSN_SYNC
))
3234 if (mips_opts
.mips16
3235 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3236 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3237 && ISA_SUPPORTS_MIPS16E
)
3239 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3240 ip
->insn_opcode
|= 0x0080;
3242 insert_into_history (0, 1, ip
);
3246 /* We could do even better for unconditional branches to
3247 portions of this object file; we could pick up the
3248 instruction at the destination, put it in the delay
3249 slot, and bump the destination address. */
3250 insert_into_history (0, 1, ip
);
3254 if (mips_relax
.sequence
)
3255 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3259 /* It looks like we can actually do the swap. */
3260 struct mips_cl_insn delay
= history
[0];
3261 if (mips_opts
.mips16
)
3263 know (delay
.frag
== ip
->frag
);
3264 move_insn (ip
, delay
.frag
, delay
.where
);
3265 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3267 else if (relaxed_branch
)
3269 /* Add the delay slot instruction to the end of the
3270 current frag and shrink the fixed part of the
3271 original frag. If the branch occupies the tail of
3272 the latter, move it backwards to cover the gap. */
3273 delay
.frag
->fr_fix
-= 4;
3274 if (delay
.frag
== ip
->frag
)
3275 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3276 add_fixed_insn (&delay
);
3280 move_insn (&delay
, ip
->frag
, ip
->where
);
3281 move_insn (ip
, history
[0].frag
, history
[0].where
);
3285 insert_into_history (0, 1, &delay
);
3288 /* If that was an unconditional branch, forget the previous
3289 insn information. */
3290 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3291 mips_no_prev_insn ();
3293 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3295 /* We don't yet optimize a branch likely. What we should do
3296 is look at the target, copy the instruction found there
3297 into the delay slot, and increment the branch to jump to
3298 the next instruction. */
3299 insert_into_history (0, 1, ip
);
3303 insert_into_history (0, 1, ip
);
3306 insert_into_history (0, 1, ip
);
3308 /* We just output an insn, so the next one doesn't have a label. */
3309 mips_clear_insn_labels ();
3312 /* Forget that there was any previous instruction or label. */
3315 mips_no_prev_insn (void)
3317 prev_nop_frag
= NULL
;
3318 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3319 mips_clear_insn_labels ();
3322 /* This function must be called before we emit something other than
3323 instructions. It is like mips_no_prev_insn except that it inserts
3324 any NOPS that might be needed by previous instructions. */
3327 mips_emit_delays (void)
3329 if (! mips_opts
.noreorder
)
3331 int nops
= nops_for_insn (history
, NULL
);
3335 add_fixed_insn (NOP_INSN
);
3336 mips_move_labels ();
3339 mips_no_prev_insn ();
3342 /* Start a (possibly nested) noreorder block. */
3345 start_noreorder (void)
3347 if (mips_opts
.noreorder
== 0)
3352 /* None of the instructions before the .set noreorder can be moved. */
3353 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3354 history
[i
].fixed_p
= 1;
3356 /* Insert any nops that might be needed between the .set noreorder
3357 block and the previous instructions. We will later remove any
3358 nops that turn out not to be needed. */
3359 nops
= nops_for_insn (history
, NULL
);
3362 if (mips_optimize
!= 0)
3364 /* Record the frag which holds the nop instructions, so
3365 that we can remove them if we don't need them. */
3366 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3367 prev_nop_frag
= frag_now
;
3368 prev_nop_frag_holds
= nops
;
3369 prev_nop_frag_required
= 0;
3370 prev_nop_frag_since
= 0;
3373 for (; nops
> 0; --nops
)
3374 add_fixed_insn (NOP_INSN
);
3376 /* Move on to a new frag, so that it is safe to simply
3377 decrease the size of prev_nop_frag. */
3378 frag_wane (frag_now
);
3380 mips_move_labels ();
3382 mips16_mark_labels ();
3383 mips_clear_insn_labels ();
3385 mips_opts
.noreorder
++;
3386 mips_any_noreorder
= 1;
3389 /* End a nested noreorder block. */
3392 end_noreorder (void)
3394 mips_opts
.noreorder
--;
3395 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3397 /* Commit to inserting prev_nop_frag_required nops and go back to
3398 handling nop insertion the .set reorder way. */
3399 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3400 * (mips_opts
.mips16
? 2 : 4));
3401 insert_into_history (prev_nop_frag_since
,
3402 prev_nop_frag_required
, NOP_INSN
);
3403 prev_nop_frag
= NULL
;
3407 /* Set up global variables for the start of a new macro. */
3412 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3413 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3414 && (history
[0].insn_mo
->pinfo
3415 & (INSN_UNCOND_BRANCH_DELAY
3416 | INSN_COND_BRANCH_DELAY
3417 | INSN_COND_BRANCH_LIKELY
)) != 0);
3420 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3421 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3422 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3425 macro_warning (relax_substateT subtype
)
3427 if (subtype
& RELAX_DELAY_SLOT
)
3428 return _("Macro instruction expanded into multiple instructions"
3429 " in a branch delay slot");
3430 else if (subtype
& RELAX_NOMACRO
)
3431 return _("Macro instruction expanded into multiple instructions");
3436 /* Finish up a macro. Emit warnings as appropriate. */
3441 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3443 relax_substateT subtype
;
3445 /* Set up the relaxation warning flags. */
3447 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3448 subtype
|= RELAX_SECOND_LONGER
;
3449 if (mips_opts
.warn_about_macros
)
3450 subtype
|= RELAX_NOMACRO
;
3451 if (mips_macro_warning
.delay_slot_p
)
3452 subtype
|= RELAX_DELAY_SLOT
;
3454 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3456 /* Either the macro has a single implementation or both
3457 implementations are longer than 4 bytes. Emit the
3459 const char *msg
= macro_warning (subtype
);
3465 /* One implementation might need a warning but the other
3466 definitely doesn't. */
3467 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3472 /* Read a macro's relocation codes from *ARGS and store them in *R.
3473 The first argument in *ARGS will be either the code for a single
3474 relocation or -1 followed by the three codes that make up a
3475 composite relocation. */
3478 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3482 next
= va_arg (*args
, int);
3484 r
[0] = (bfd_reloc_code_real_type
) next
;
3486 for (i
= 0; i
< 3; i
++)
3487 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3490 /* Build an instruction created by a macro expansion. This is passed
3491 a pointer to the count of instructions created so far, an
3492 expression, the name of the instruction to build, an operand format
3493 string, and corresponding arguments. */
3496 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3498 const struct mips_opcode
*mo
;
3499 struct mips_cl_insn insn
;
3500 bfd_reloc_code_real_type r
[3];
3503 va_start (args
, fmt
);
3505 if (mips_opts
.mips16
)
3507 mips16_macro_build (ep
, name
, fmt
, args
);
3512 r
[0] = BFD_RELOC_UNUSED
;
3513 r
[1] = BFD_RELOC_UNUSED
;
3514 r
[2] = BFD_RELOC_UNUSED
;
3515 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3517 assert (strcmp (name
, mo
->name
) == 0);
3521 /* Search until we get a match for NAME. It is assumed here that
3522 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3523 if (strcmp (fmt
, mo
->args
) == 0
3524 && mo
->pinfo
!= INSN_MACRO
3525 && is_opcode_valid (mo
, TRUE
))
3530 assert (strcmp (name
, mo
->name
) == 0);
3533 create_insn (&insn
, mo
);
3551 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3556 /* Note that in the macro case, these arguments are already
3557 in MSB form. (When handling the instruction in the
3558 non-macro case, these arguments are sizes from which
3559 MSB values must be calculated.) */
3560 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3566 /* Note that in the macro case, these arguments are already
3567 in MSBD form. (When handling the instruction in the
3568 non-macro case, these arguments are sizes from which
3569 MSBD values must be calculated.) */
3570 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3574 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3583 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3589 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3593 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3598 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3604 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3609 int tmp
= va_arg (args
, int);
3611 INSERT_OPERAND (RT
, insn
, tmp
);
3612 INSERT_OPERAND (RD
, insn
, tmp
);
3618 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3625 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3629 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3633 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3637 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3641 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3648 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3654 macro_read_relocs (&args
, r
);
3655 assert (*r
== BFD_RELOC_GPREL16
3656 || *r
== BFD_RELOC_MIPS_LITERAL
3657 || *r
== BFD_RELOC_MIPS_HIGHER
3658 || *r
== BFD_RELOC_HI16_S
3659 || *r
== BFD_RELOC_LO16
3660 || *r
== BFD_RELOC_MIPS_GOT16
3661 || *r
== BFD_RELOC_MIPS_CALL16
3662 || *r
== BFD_RELOC_MIPS_GOT_DISP
3663 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3664 || *r
== BFD_RELOC_MIPS_GOT_OFST
3665 || *r
== BFD_RELOC_MIPS_GOT_LO16
3666 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3670 macro_read_relocs (&args
, r
);
3672 && (ep
->X_op
== O_constant
3673 || (ep
->X_op
== O_symbol
3674 && (*r
== BFD_RELOC_MIPS_HIGHEST
3675 || *r
== BFD_RELOC_HI16_S
3676 || *r
== BFD_RELOC_HI16
3677 || *r
== BFD_RELOC_GPREL16
3678 || *r
== BFD_RELOC_MIPS_GOT_HI16
3679 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3683 assert (ep
!= NULL
);
3686 * This allows macro() to pass an immediate expression for
3687 * creating short branches without creating a symbol.
3689 * We don't allow branch relaxation for these branches, as
3690 * they should only appear in ".set nomacro" anyway.
3692 if (ep
->X_op
== O_constant
)
3694 if ((ep
->X_add_number
& 3) != 0)
3695 as_bad (_("branch to misaligned address (0x%lx)"),
3696 (unsigned long) ep
->X_add_number
);
3697 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3698 as_bad (_("branch address range overflow (0x%lx)"),
3699 (unsigned long) ep
->X_add_number
);
3700 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3704 *r
= BFD_RELOC_16_PCREL_S2
;
3708 assert (ep
!= NULL
);
3709 *r
= BFD_RELOC_MIPS_JMP
;
3713 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3717 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3726 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3728 append_insn (&insn
, ep
, r
);
3732 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3735 struct mips_opcode
*mo
;
3736 struct mips_cl_insn insn
;
3737 bfd_reloc_code_real_type r
[3]
3738 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3740 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3742 assert (strcmp (name
, mo
->name
) == 0);
3744 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3748 assert (strcmp (name
, mo
->name
) == 0);
3751 create_insn (&insn
, mo
);
3769 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3774 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3778 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3782 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3792 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3799 regno
= va_arg (args
, int);
3800 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3801 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3822 assert (ep
!= NULL
);
3824 if (ep
->X_op
!= O_constant
)
3825 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3828 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3829 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3832 *r
= BFD_RELOC_UNUSED
;
3838 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3845 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3847 append_insn (&insn
, ep
, r
);
3851 * Sign-extend 32-bit mode constants that have bit 31 set and all
3852 * higher bits unset.
3855 normalize_constant_expr (expressionS
*ex
)
3857 if (ex
->X_op
== O_constant
3858 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3859 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3864 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3865 * all higher bits unset.
3868 normalize_address_expr (expressionS
*ex
)
3870 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3871 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3872 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3873 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3878 * Generate a "jalr" instruction with a relocation hint to the called
3879 * function. This occurs in NewABI PIC code.
3882 macro_build_jalr (expressionS
*ep
)
3891 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3893 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3894 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3898 * Generate a "lui" instruction.
3901 macro_build_lui (expressionS
*ep
, int regnum
)
3903 expressionS high_expr
;
3904 const struct mips_opcode
*mo
;
3905 struct mips_cl_insn insn
;
3906 bfd_reloc_code_real_type r
[3]
3907 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3908 const char *name
= "lui";
3909 const char *fmt
= "t,u";
3911 assert (! mips_opts
.mips16
);
3915 if (high_expr
.X_op
== O_constant
)
3917 /* We can compute the instruction now without a relocation entry. */
3918 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3920 *r
= BFD_RELOC_UNUSED
;
3924 assert (ep
->X_op
== O_symbol
);
3925 /* _gp_disp is a special case, used from s_cpload.
3926 __gnu_local_gp is used if mips_no_shared. */
3927 assert (mips_pic
== NO_PIC
3929 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3930 || (! mips_in_shared
3931 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3932 "__gnu_local_gp") == 0));
3933 *r
= BFD_RELOC_HI16_S
;
3936 mo
= hash_find (op_hash
, name
);
3937 assert (strcmp (name
, mo
->name
) == 0);
3938 assert (strcmp (fmt
, mo
->args
) == 0);
3939 create_insn (&insn
, mo
);
3941 insn
.insn_opcode
= insn
.insn_mo
->match
;
3942 INSERT_OPERAND (RT
, insn
, regnum
);
3943 if (*r
== BFD_RELOC_UNUSED
)
3945 insn
.insn_opcode
|= high_expr
.X_add_number
;
3946 append_insn (&insn
, NULL
, r
);
3949 append_insn (&insn
, &high_expr
, r
);
3952 /* Generate a sequence of instructions to do a load or store from a constant
3953 offset off of a base register (breg) into/from a target register (treg),
3954 using AT if necessary. */
3956 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3957 int treg
, int breg
, int dbl
)
3959 assert (ep
->X_op
== O_constant
);
3961 /* Sign-extending 32-bit constants makes their handling easier. */
3963 normalize_constant_expr (ep
);
3965 /* Right now, this routine can only handle signed 32-bit constants. */
3966 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3967 as_warn (_("operand overflow"));
3969 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3971 /* Signed 16-bit offset will fit in the op. Easy! */
3972 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3976 /* 32-bit offset, need multiple instructions and AT, like:
3977 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3978 addu $tempreg,$tempreg,$breg
3979 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3980 to handle the complete offset. */
3981 macro_build_lui (ep
, AT
);
3982 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3983 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3986 as_bad (_("Macro used $at after \".set noat\""));
3991 * Generates code to set the $at register to true (one)
3992 * if reg is less than the immediate expression.
3995 set_at (int reg
, int unsignedp
)
3997 if (imm_expr
.X_op
== O_constant
3998 && imm_expr
.X_add_number
>= -0x8000
3999 && imm_expr
.X_add_number
< 0x8000)
4000 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4001 AT
, reg
, BFD_RELOC_LO16
);
4004 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4005 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4009 /* Warn if an expression is not a constant. */
4012 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4014 if (ex
->X_op
== O_big
)
4015 as_bad (_("unsupported large constant"));
4016 else if (ex
->X_op
!= O_constant
)
4017 as_bad (_("Instruction %s requires absolute expression"),
4020 if (HAVE_32BIT_GPRS
)
4021 normalize_constant_expr (ex
);
4024 /* Count the leading zeroes by performing a binary chop. This is a
4025 bulky bit of source, but performance is a LOT better for the
4026 majority of values than a simple loop to count the bits:
4027 for (lcnt = 0; (lcnt < 32); lcnt++)
4028 if ((v) & (1 << (31 - lcnt)))
4030 However it is not code size friendly, and the gain will drop a bit
4031 on certain cached systems.
4033 #define COUNT_TOP_ZEROES(v) \
4034 (((v) & ~0xffff) == 0 \
4035 ? ((v) & ~0xff) == 0 \
4036 ? ((v) & ~0xf) == 0 \
4037 ? ((v) & ~0x3) == 0 \
4038 ? ((v) & ~0x1) == 0 \
4043 : ((v) & ~0x7) == 0 \
4046 : ((v) & ~0x3f) == 0 \
4047 ? ((v) & ~0x1f) == 0 \
4050 : ((v) & ~0x7f) == 0 \
4053 : ((v) & ~0xfff) == 0 \
4054 ? ((v) & ~0x3ff) == 0 \
4055 ? ((v) & ~0x1ff) == 0 \
4058 : ((v) & ~0x7ff) == 0 \
4061 : ((v) & ~0x3fff) == 0 \
4062 ? ((v) & ~0x1fff) == 0 \
4065 : ((v) & ~0x7fff) == 0 \
4068 : ((v) & ~0xffffff) == 0 \
4069 ? ((v) & ~0xfffff) == 0 \
4070 ? ((v) & ~0x3ffff) == 0 \
4071 ? ((v) & ~0x1ffff) == 0 \
4074 : ((v) & ~0x7ffff) == 0 \
4077 : ((v) & ~0x3fffff) == 0 \
4078 ? ((v) & ~0x1fffff) == 0 \
4081 : ((v) & ~0x7fffff) == 0 \
4084 : ((v) & ~0xfffffff) == 0 \
4085 ? ((v) & ~0x3ffffff) == 0 \
4086 ? ((v) & ~0x1ffffff) == 0 \
4089 : ((v) & ~0x7ffffff) == 0 \
4092 : ((v) & ~0x3fffffff) == 0 \
4093 ? ((v) & ~0x1fffffff) == 0 \
4096 : ((v) & ~0x7fffffff) == 0 \
4101 * This routine generates the least number of instructions necessary to load
4102 * an absolute expression value into a register.
4105 load_register (int reg
, expressionS
*ep
, int dbl
)
4108 expressionS hi32
, lo32
;
4110 if (ep
->X_op
!= O_big
)
4112 assert (ep
->X_op
== O_constant
);
4114 /* Sign-extending 32-bit constants makes their handling easier. */
4116 normalize_constant_expr (ep
);
4118 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4120 /* We can handle 16 bit signed values with an addiu to
4121 $zero. No need to ever use daddiu here, since $zero and
4122 the result are always correct in 32 bit mode. */
4123 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4126 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4128 /* We can handle 16 bit unsigned values with an ori to
4130 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4133 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4135 /* 32 bit values require an lui. */
4136 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4137 if ((ep
->X_add_number
& 0xffff) != 0)
4138 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4143 /* The value is larger than 32 bits. */
4145 if (!dbl
|| HAVE_32BIT_GPRS
)
4149 sprintf_vma (value
, ep
->X_add_number
);
4150 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4151 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4155 if (ep
->X_op
!= O_big
)
4158 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4159 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4160 hi32
.X_add_number
&= 0xffffffff;
4162 lo32
.X_add_number
&= 0xffffffff;
4166 assert (ep
->X_add_number
> 2);
4167 if (ep
->X_add_number
== 3)
4168 generic_bignum
[3] = 0;
4169 else if (ep
->X_add_number
> 4)
4170 as_bad (_("Number larger than 64 bits"));
4171 lo32
.X_op
= O_constant
;
4172 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4173 hi32
.X_op
= O_constant
;
4174 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4177 if (hi32
.X_add_number
== 0)
4182 unsigned long hi
, lo
;
4184 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4186 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4188 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4191 if (lo32
.X_add_number
& 0x80000000)
4193 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4194 if (lo32
.X_add_number
& 0xffff)
4195 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4200 /* Check for 16bit shifted constant. We know that hi32 is
4201 non-zero, so start the mask on the first bit of the hi32
4206 unsigned long himask
, lomask
;
4210 himask
= 0xffff >> (32 - shift
);
4211 lomask
= (0xffff << shift
) & 0xffffffff;
4215 himask
= 0xffff << (shift
- 32);
4218 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4219 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4223 tmp
.X_op
= O_constant
;
4225 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4226 | (lo32
.X_add_number
>> shift
));
4228 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4229 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4230 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4231 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4236 while (shift
<= (64 - 16));
4238 /* Find the bit number of the lowest one bit, and store the
4239 shifted value in hi/lo. */
4240 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4241 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4245 while ((lo
& 1) == 0)
4250 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4256 while ((hi
& 1) == 0)
4265 /* Optimize if the shifted value is a (power of 2) - 1. */
4266 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4267 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4269 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4274 /* This instruction will set the register to be all
4276 tmp
.X_op
= O_constant
;
4277 tmp
.X_add_number
= (offsetT
) -1;
4278 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4282 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4283 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4285 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4286 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4291 /* Sign extend hi32 before calling load_register, because we can
4292 generally get better code when we load a sign extended value. */
4293 if ((hi32
.X_add_number
& 0x80000000) != 0)
4294 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4295 load_register (reg
, &hi32
, 0);
4298 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4302 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4310 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4312 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4313 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4319 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4323 mid16
.X_add_number
>>= 16;
4324 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4325 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4328 if ((lo32
.X_add_number
& 0xffff) != 0)
4329 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4333 load_delay_nop (void)
4335 if (!gpr_interlocks
)
4336 macro_build (NULL
, "nop", "");
4339 /* Load an address into a register. */
4342 load_address (int reg
, expressionS
*ep
, int *used_at
)
4344 if (ep
->X_op
!= O_constant
4345 && ep
->X_op
!= O_symbol
)
4347 as_bad (_("expression too complex"));
4348 ep
->X_op
= O_constant
;
4351 if (ep
->X_op
== O_constant
)
4353 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4357 if (mips_pic
== NO_PIC
)
4359 /* If this is a reference to a GP relative symbol, we want
4360 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4362 lui $reg,<sym> (BFD_RELOC_HI16_S)
4363 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4364 If we have an addend, we always use the latter form.
4366 With 64bit address space and a usable $at we want
4367 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4368 lui $at,<sym> (BFD_RELOC_HI16_S)
4369 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4370 daddiu $at,<sym> (BFD_RELOC_LO16)
4374 If $at is already in use, we use a path which is suboptimal
4375 on superscalar processors.
4376 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4377 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4379 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4381 daddiu $reg,<sym> (BFD_RELOC_LO16)
4383 For GP relative symbols in 64bit address space we can use
4384 the same sequence as in 32bit address space. */
4385 if (HAVE_64BIT_SYMBOLS
)
4387 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4388 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4390 relax_start (ep
->X_add_symbol
);
4391 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4392 mips_gp_register
, BFD_RELOC_GPREL16
);
4396 if (*used_at
== 0 && mips_opts
.at
)
4398 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4399 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4400 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4401 BFD_RELOC_MIPS_HIGHER
);
4402 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4403 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4404 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4409 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4410 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4411 BFD_RELOC_MIPS_HIGHER
);
4412 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4413 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4414 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4415 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4418 if (mips_relax
.sequence
)
4423 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4424 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4426 relax_start (ep
->X_add_symbol
);
4427 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4428 mips_gp_register
, BFD_RELOC_GPREL16
);
4431 macro_build_lui (ep
, reg
);
4432 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4433 reg
, reg
, BFD_RELOC_LO16
);
4434 if (mips_relax
.sequence
)
4438 else if (!mips_big_got
)
4442 /* If this is a reference to an external symbol, we want
4443 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4445 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4447 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4448 If there is a constant, it must be added in after.
4450 If we have NewABI, we want
4451 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4452 unless we're referencing a global symbol with a non-zero
4453 offset, in which case cst must be added separately. */
4456 if (ep
->X_add_number
)
4458 ex
.X_add_number
= ep
->X_add_number
;
4459 ep
->X_add_number
= 0;
4460 relax_start (ep
->X_add_symbol
);
4461 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4462 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4463 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4464 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4465 ex
.X_op
= O_constant
;
4466 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4467 reg
, reg
, BFD_RELOC_LO16
);
4468 ep
->X_add_number
= ex
.X_add_number
;
4471 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4472 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4473 if (mips_relax
.sequence
)
4478 ex
.X_add_number
= ep
->X_add_number
;
4479 ep
->X_add_number
= 0;
4480 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4481 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4483 relax_start (ep
->X_add_symbol
);
4485 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4489 if (ex
.X_add_number
!= 0)
4491 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4492 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4493 ex
.X_op
= O_constant
;
4494 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4495 reg
, reg
, BFD_RELOC_LO16
);
4499 else if (mips_big_got
)
4503 /* This is the large GOT case. If this is a reference to an
4504 external symbol, we want
4505 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4507 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4509 Otherwise, for a reference to a local symbol in old ABI, we want
4510 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4512 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4513 If there is a constant, it must be added in after.
4515 In the NewABI, for local symbols, with or without offsets, we want:
4516 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4517 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4521 ex
.X_add_number
= ep
->X_add_number
;
4522 ep
->X_add_number
= 0;
4523 relax_start (ep
->X_add_symbol
);
4524 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4525 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4526 reg
, reg
, mips_gp_register
);
4527 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4528 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4529 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4530 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4531 else if (ex
.X_add_number
)
4533 ex
.X_op
= O_constant
;
4534 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4538 ep
->X_add_number
= ex
.X_add_number
;
4540 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4541 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4542 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4543 BFD_RELOC_MIPS_GOT_OFST
);
4548 ex
.X_add_number
= ep
->X_add_number
;
4549 ep
->X_add_number
= 0;
4550 relax_start (ep
->X_add_symbol
);
4551 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4552 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4553 reg
, reg
, mips_gp_register
);
4554 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4555 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4557 if (reg_needs_delay (mips_gp_register
))
4559 /* We need a nop before loading from $gp. This special
4560 check is required because the lui which starts the main
4561 instruction stream does not refer to $gp, and so will not
4562 insert the nop which may be required. */
4563 macro_build (NULL
, "nop", "");
4565 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4566 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4568 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4572 if (ex
.X_add_number
!= 0)
4574 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4575 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4576 ex
.X_op
= O_constant
;
4577 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4585 if (!mips_opts
.at
&& *used_at
== 1)
4586 as_bad (_("Macro used $at after \".set noat\""));
4589 /* Move the contents of register SOURCE into register DEST. */
4592 move_register (int dest
, int source
)
4594 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4598 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4599 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4600 The two alternatives are:
4602 Global symbol Local sybmol
4603 ------------- ------------
4604 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4606 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4608 load_got_offset emits the first instruction and add_got_offset
4609 emits the second for a 16-bit offset or add_got_offset_hilo emits
4610 a sequence to add a 32-bit offset using a scratch register. */
4613 load_got_offset (int dest
, expressionS
*local
)
4618 global
.X_add_number
= 0;
4620 relax_start (local
->X_add_symbol
);
4621 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4622 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4624 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4625 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4630 add_got_offset (int dest
, expressionS
*local
)
4634 global
.X_op
= O_constant
;
4635 global
.X_op_symbol
= NULL
;
4636 global
.X_add_symbol
= NULL
;
4637 global
.X_add_number
= local
->X_add_number
;
4639 relax_start (local
->X_add_symbol
);
4640 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4641 dest
, dest
, BFD_RELOC_LO16
);
4643 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4648 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4651 int hold_mips_optimize
;
4653 global
.X_op
= O_constant
;
4654 global
.X_op_symbol
= NULL
;
4655 global
.X_add_symbol
= NULL
;
4656 global
.X_add_number
= local
->X_add_number
;
4658 relax_start (local
->X_add_symbol
);
4659 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4661 /* Set mips_optimize around the lui instruction to avoid
4662 inserting an unnecessary nop after the lw. */
4663 hold_mips_optimize
= mips_optimize
;
4665 macro_build_lui (&global
, tmp
);
4666 mips_optimize
= hold_mips_optimize
;
4667 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4670 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4675 * This routine implements the seemingly endless macro or synthesized
4676 * instructions and addressing modes in the mips assembly language. Many
4677 * of these macros are simple and are similar to each other. These could
4678 * probably be handled by some kind of table or grammar approach instead of
4679 * this verbose method. Others are not simple macros but are more like
4680 * optimizing code generation.
4681 * One interesting optimization is when several store macros appear
4682 * consecutively that would load AT with the upper half of the same address.
4683 * The ensuing load upper instructions are ommited. This implies some kind
4684 * of global optimization. We currently only optimize within a single macro.
4685 * For many of the load and store macros if the address is specified as a
4686 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4687 * first load register 'at' with zero and use it as the base register. The
4688 * mips assembler simply uses register $zero. Just one tiny optimization
4692 macro (struct mips_cl_insn
*ip
)
4694 unsigned int treg
, sreg
, dreg
, breg
;
4695 unsigned int tempreg
;
4710 bfd_reloc_code_real_type r
;
4711 int hold_mips_optimize
;
4713 assert (! mips_opts
.mips16
);
4715 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4716 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4717 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4718 mask
= ip
->insn_mo
->mask
;
4720 expr1
.X_op
= O_constant
;
4721 expr1
.X_op_symbol
= NULL
;
4722 expr1
.X_add_symbol
= NULL
;
4723 expr1
.X_add_number
= 1;
4737 expr1
.X_add_number
= 8;
4738 macro_build (&expr1
, "bgez", "s,p", sreg
);
4740 macro_build (NULL
, "nop", "", 0);
4742 move_register (dreg
, sreg
);
4743 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4766 if (imm_expr
.X_op
== O_constant
4767 && imm_expr
.X_add_number
>= -0x8000
4768 && imm_expr
.X_add_number
< 0x8000)
4770 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4774 load_register (AT
, &imm_expr
, dbl
);
4775 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4794 if (imm_expr
.X_op
== O_constant
4795 && imm_expr
.X_add_number
>= 0
4796 && imm_expr
.X_add_number
< 0x10000)
4798 if (mask
!= M_NOR_I
)
4799 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4802 macro_build (&imm_expr
, "ori", "t,r,i",
4803 treg
, sreg
, BFD_RELOC_LO16
);
4804 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4810 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4811 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4815 switch (imm_expr
.X_add_number
)
4818 macro_build (NULL
, "nop", "");
4821 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4824 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4825 (int)imm_expr
.X_add_number
);
4844 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4846 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4850 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4851 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4859 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4864 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4868 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4869 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4875 /* check for > max integer */
4876 maxnum
= 0x7fffffff;
4877 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4884 if (imm_expr
.X_op
== O_constant
4885 && imm_expr
.X_add_number
>= maxnum
4886 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4889 /* result is always false */
4891 macro_build (NULL
, "nop", "", 0);
4893 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4896 if (imm_expr
.X_op
!= O_constant
)
4897 as_bad (_("Unsupported large constant"));
4898 ++imm_expr
.X_add_number
;
4902 if (mask
== M_BGEL_I
)
4904 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4906 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4909 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4911 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4914 maxnum
= 0x7fffffff;
4915 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4922 maxnum
= - maxnum
- 1;
4923 if (imm_expr
.X_op
== O_constant
4924 && imm_expr
.X_add_number
<= maxnum
4925 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4928 /* result is always true */
4929 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4930 macro_build (&offset_expr
, "b", "p");
4935 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4945 macro_build (&offset_expr
, likely
? "beql" : "beq",
4950 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4951 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4959 && imm_expr
.X_op
== O_constant
4960 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4962 if (imm_expr
.X_op
!= O_constant
)
4963 as_bad (_("Unsupported large constant"));
4964 ++imm_expr
.X_add_number
;
4968 if (mask
== M_BGEUL_I
)
4970 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4972 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4974 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4980 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4988 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4993 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4997 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4998 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5006 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5013 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5014 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5022 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5027 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5031 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5032 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5038 maxnum
= 0x7fffffff;
5039 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5046 if (imm_expr
.X_op
== O_constant
5047 && imm_expr
.X_add_number
>= maxnum
5048 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5050 if (imm_expr
.X_op
!= O_constant
)
5051 as_bad (_("Unsupported large constant"));
5052 ++imm_expr
.X_add_number
;
5056 if (mask
== M_BLTL_I
)
5058 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5060 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5063 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5065 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5070 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5078 macro_build (&offset_expr
, likely
? "beql" : "beq",
5085 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5086 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5094 && imm_expr
.X_op
== O_constant
5095 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5097 if (imm_expr
.X_op
!= O_constant
)
5098 as_bad (_("Unsupported large constant"));
5099 ++imm_expr
.X_add_number
;
5103 if (mask
== M_BLTUL_I
)
5105 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5107 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5109 macro_build (&offset_expr
, likely
? "beql" : "beq",
5115 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5123 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5128 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5132 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5133 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5143 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5148 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5149 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5157 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5159 as_bad (_("Unsupported large constant"));
5164 pos
= (unsigned long) imm_expr
.X_add_number
;
5165 size
= (unsigned long) imm2_expr
.X_add_number
;
5170 as_bad (_("Improper position (%lu)"), pos
);
5173 if (size
== 0 || size
> 64
5174 || (pos
+ size
- 1) > 63)
5176 as_bad (_("Improper extract size (%lu, position %lu)"),
5181 if (size
<= 32 && pos
< 32)
5186 else if (size
<= 32)
5196 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5205 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5207 as_bad (_("Unsupported large constant"));
5212 pos
= (unsigned long) imm_expr
.X_add_number
;
5213 size
= (unsigned long) imm2_expr
.X_add_number
;
5218 as_bad (_("Improper position (%lu)"), pos
);
5221 if (size
== 0 || size
> 64
5222 || (pos
+ size
- 1) > 63)
5224 as_bad (_("Improper insert size (%lu, position %lu)"),
5229 if (pos
< 32 && (pos
+ size
- 1) < 32)
5244 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5245 (int) (pos
+ size
- 1));
5261 as_warn (_("Divide by zero."));
5263 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5265 macro_build (NULL
, "break", "c", 7);
5272 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5273 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5277 expr1
.X_add_number
= 8;
5278 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5279 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5280 macro_build (NULL
, "break", "c", 7);
5282 expr1
.X_add_number
= -1;
5284 load_register (AT
, &expr1
, dbl
);
5285 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5286 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5289 expr1
.X_add_number
= 1;
5290 load_register (AT
, &expr1
, dbl
);
5291 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5295 expr1
.X_add_number
= 0x80000000;
5296 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5300 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5301 /* We want to close the noreorder block as soon as possible, so
5302 that later insns are available for delay slot filling. */
5307 expr1
.X_add_number
= 8;
5308 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5309 macro_build (NULL
, "nop", "", 0);
5311 /* We want to close the noreorder block as soon as possible, so
5312 that later insns are available for delay slot filling. */
5315 macro_build (NULL
, "break", "c", 6);
5317 macro_build (NULL
, s
, "d", dreg
);
5356 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5358 as_warn (_("Divide by zero."));
5360 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5362 macro_build (NULL
, "break", "c", 7);
5365 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5367 if (strcmp (s2
, "mflo") == 0)
5368 move_register (dreg
, sreg
);
5370 move_register (dreg
, 0);
5373 if (imm_expr
.X_op
== O_constant
5374 && imm_expr
.X_add_number
== -1
5375 && s
[strlen (s
) - 1] != 'u')
5377 if (strcmp (s2
, "mflo") == 0)
5379 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5382 move_register (dreg
, 0);
5387 load_register (AT
, &imm_expr
, dbl
);
5388 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5389 macro_build (NULL
, s2
, "d", dreg
);
5411 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5412 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5413 /* We want to close the noreorder block as soon as possible, so
5414 that later insns are available for delay slot filling. */
5419 expr1
.X_add_number
= 8;
5420 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5421 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5423 /* We want to close the noreorder block as soon as possible, so
5424 that later insns are available for delay slot filling. */
5426 macro_build (NULL
, "break", "c", 7);
5428 macro_build (NULL
, s2
, "d", dreg
);
5440 /* Load the address of a symbol into a register. If breg is not
5441 zero, we then add a base register to it. */
5443 if (dbl
&& HAVE_32BIT_GPRS
)
5444 as_warn (_("dla used to load 32-bit register"));
5446 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5447 as_warn (_("la used to load 64-bit address"));
5449 if (offset_expr
.X_op
== O_constant
5450 && offset_expr
.X_add_number
>= -0x8000
5451 && offset_expr
.X_add_number
< 0x8000)
5453 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5454 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5458 if (mips_opts
.at
&& (treg
== breg
))
5468 if (offset_expr
.X_op
!= O_symbol
5469 && offset_expr
.X_op
!= O_constant
)
5471 as_bad (_("expression too complex"));
5472 offset_expr
.X_op
= O_constant
;
5475 if (offset_expr
.X_op
== O_constant
)
5476 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5477 else if (mips_pic
== NO_PIC
)
5479 /* If this is a reference to a GP relative symbol, we want
5480 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5482 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5483 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5484 If we have a constant, we need two instructions anyhow,
5485 so we may as well always use the latter form.
5487 With 64bit address space and a usable $at we want
5488 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5489 lui $at,<sym> (BFD_RELOC_HI16_S)
5490 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5491 daddiu $at,<sym> (BFD_RELOC_LO16)
5493 daddu $tempreg,$tempreg,$at
5495 If $at is already in use, we use a path which is suboptimal
5496 on superscalar processors.
5497 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5498 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5500 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5502 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5504 For GP relative symbols in 64bit address space we can use
5505 the same sequence as in 32bit address space. */
5506 if (HAVE_64BIT_SYMBOLS
)
5508 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5509 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5511 relax_start (offset_expr
.X_add_symbol
);
5512 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5513 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5517 if (used_at
== 0 && mips_opts
.at
)
5519 macro_build (&offset_expr
, "lui", "t,u",
5520 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5521 macro_build (&offset_expr
, "lui", "t,u",
5522 AT
, BFD_RELOC_HI16_S
);
5523 macro_build (&offset_expr
, "daddiu", "t,r,j",
5524 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5525 macro_build (&offset_expr
, "daddiu", "t,r,j",
5526 AT
, AT
, BFD_RELOC_LO16
);
5527 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5528 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5533 macro_build (&offset_expr
, "lui", "t,u",
5534 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5535 macro_build (&offset_expr
, "daddiu", "t,r,j",
5536 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5537 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5538 macro_build (&offset_expr
, "daddiu", "t,r,j",
5539 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5540 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5541 macro_build (&offset_expr
, "daddiu", "t,r,j",
5542 tempreg
, tempreg
, BFD_RELOC_LO16
);
5545 if (mips_relax
.sequence
)
5550 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5551 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5553 relax_start (offset_expr
.X_add_symbol
);
5554 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5555 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5558 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5559 as_bad (_("offset too large"));
5560 macro_build_lui (&offset_expr
, tempreg
);
5561 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5562 tempreg
, tempreg
, BFD_RELOC_LO16
);
5563 if (mips_relax
.sequence
)
5567 else if (!mips_big_got
&& !HAVE_NEWABI
)
5569 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5571 /* If this is a reference to an external symbol, and there
5572 is no constant, we want
5573 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5574 or for lca or if tempreg is PIC_CALL_REG
5575 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5576 For a local symbol, we want
5577 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5579 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5581 If we have a small constant, and this is a reference to
5582 an external symbol, we want
5583 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5585 addiu $tempreg,$tempreg,<constant>
5586 For a local symbol, we want the same instruction
5587 sequence, but we output a BFD_RELOC_LO16 reloc on the
5590 If we have a large constant, and this is a reference to
5591 an external symbol, we want
5592 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5593 lui $at,<hiconstant>
5594 addiu $at,$at,<loconstant>
5595 addu $tempreg,$tempreg,$at
5596 For a local symbol, we want the same instruction
5597 sequence, but we output a BFD_RELOC_LO16 reloc on the
5601 if (offset_expr
.X_add_number
== 0)
5603 if (mips_pic
== SVR4_PIC
5605 && (call
|| tempreg
== PIC_CALL_REG
))
5606 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5608 relax_start (offset_expr
.X_add_symbol
);
5609 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5610 lw_reloc_type
, mips_gp_register
);
5613 /* We're going to put in an addu instruction using
5614 tempreg, so we may as well insert the nop right
5619 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5620 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5622 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5623 tempreg
, tempreg
, BFD_RELOC_LO16
);
5625 /* FIXME: If breg == 0, and the next instruction uses
5626 $tempreg, then if this variant case is used an extra
5627 nop will be generated. */
5629 else if (offset_expr
.X_add_number
>= -0x8000
5630 && offset_expr
.X_add_number
< 0x8000)
5632 load_got_offset (tempreg
, &offset_expr
);
5634 add_got_offset (tempreg
, &offset_expr
);
5638 expr1
.X_add_number
= offset_expr
.X_add_number
;
5639 offset_expr
.X_add_number
=
5640 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5641 load_got_offset (tempreg
, &offset_expr
);
5642 offset_expr
.X_add_number
= expr1
.X_add_number
;
5643 /* If we are going to add in a base register, and the
5644 target register and the base register are the same,
5645 then we are using AT as a temporary register. Since
5646 we want to load the constant into AT, we add our
5647 current AT (from the global offset table) and the
5648 register into the register now, and pretend we were
5649 not using a base register. */
5653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5658 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5662 else if (!mips_big_got
&& HAVE_NEWABI
)
5664 int add_breg_early
= 0;
5666 /* If this is a reference to an external, and there is no
5667 constant, or local symbol (*), with or without a
5669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5670 or for lca or if tempreg is PIC_CALL_REG
5671 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5673 If we have a small constant, and this is a reference to
5674 an external symbol, we want
5675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5676 addiu $tempreg,$tempreg,<constant>
5678 If we have a large constant, and this is a reference to
5679 an external symbol, we want
5680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5681 lui $at,<hiconstant>
5682 addiu $at,$at,<loconstant>
5683 addu $tempreg,$tempreg,$at
5685 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5686 local symbols, even though it introduces an additional
5689 if (offset_expr
.X_add_number
)
5691 expr1
.X_add_number
= offset_expr
.X_add_number
;
5692 offset_expr
.X_add_number
= 0;
5694 relax_start (offset_expr
.X_add_symbol
);
5695 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5696 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5698 if (expr1
.X_add_number
>= -0x8000
5699 && expr1
.X_add_number
< 0x8000)
5701 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5702 tempreg
, tempreg
, BFD_RELOC_LO16
);
5704 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5708 /* If we are going to add in a base register, and the
5709 target register and the base register are the same,
5710 then we are using AT as a temporary register. Since
5711 we want to load the constant into AT, we add our
5712 current AT (from the global offset table) and the
5713 register into the register now, and pretend we were
5714 not using a base register. */
5719 assert (tempreg
== AT
);
5720 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5726 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5727 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5733 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5736 offset_expr
.X_add_number
= expr1
.X_add_number
;
5738 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5739 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5742 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5743 treg
, tempreg
, breg
);
5749 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5751 relax_start (offset_expr
.X_add_symbol
);
5752 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5753 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5755 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5756 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5761 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5762 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5765 else if (mips_big_got
&& !HAVE_NEWABI
)
5768 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5769 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5770 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5772 /* This is the large GOT case. If this is a reference to an
5773 external symbol, and there is no constant, we want
5774 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5775 addu $tempreg,$tempreg,$gp
5776 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5777 or for lca or if tempreg is PIC_CALL_REG
5778 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5779 addu $tempreg,$tempreg,$gp
5780 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5781 For a local symbol, we want
5782 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5784 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5786 If we have a small constant, and this is a reference to
5787 an external symbol, we want
5788 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5789 addu $tempreg,$tempreg,$gp
5790 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5792 addiu $tempreg,$tempreg,<constant>
5793 For a local symbol, we want
5794 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5796 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5798 If we have a large constant, and this is a reference to
5799 an external symbol, we want
5800 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5801 addu $tempreg,$tempreg,$gp
5802 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5803 lui $at,<hiconstant>
5804 addiu $at,$at,<loconstant>
5805 addu $tempreg,$tempreg,$at
5806 For a local symbol, we want
5807 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5808 lui $at,<hiconstant>
5809 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5810 addu $tempreg,$tempreg,$at
5813 expr1
.X_add_number
= offset_expr
.X_add_number
;
5814 offset_expr
.X_add_number
= 0;
5815 relax_start (offset_expr
.X_add_symbol
);
5816 gpdelay
= reg_needs_delay (mips_gp_register
);
5817 if (expr1
.X_add_number
== 0 && breg
== 0
5818 && (call
|| tempreg
== PIC_CALL_REG
))
5820 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5821 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5823 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5824 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5825 tempreg
, tempreg
, mips_gp_register
);
5826 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5827 tempreg
, lw_reloc_type
, tempreg
);
5828 if (expr1
.X_add_number
== 0)
5832 /* We're going to put in an addu instruction using
5833 tempreg, so we may as well insert the nop right
5838 else if (expr1
.X_add_number
>= -0x8000
5839 && expr1
.X_add_number
< 0x8000)
5842 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5843 tempreg
, tempreg
, BFD_RELOC_LO16
);
5849 /* If we are going to add in a base register, and the
5850 target register and the base register are the same,
5851 then we are using AT as a temporary register. Since
5852 we want to load the constant into AT, we add our
5853 current AT (from the global offset table) and the
5854 register into the register now, and pretend we were
5855 not using a base register. */
5860 assert (tempreg
== AT
);
5862 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5867 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5868 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5872 offset_expr
.X_add_number
=
5873 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5878 /* This is needed because this instruction uses $gp, but
5879 the first instruction on the main stream does not. */
5880 macro_build (NULL
, "nop", "");
5883 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5884 local_reloc_type
, mips_gp_register
);
5885 if (expr1
.X_add_number
>= -0x8000
5886 && expr1
.X_add_number
< 0x8000)
5889 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5890 tempreg
, tempreg
, BFD_RELOC_LO16
);
5891 /* FIXME: If add_number is 0, and there was no base
5892 register, the external symbol case ended with a load,
5893 so if the symbol turns out to not be external, and
5894 the next instruction uses tempreg, an unnecessary nop
5895 will be inserted. */
5901 /* We must add in the base register now, as in the
5902 external symbol case. */
5903 assert (tempreg
== AT
);
5905 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5908 /* We set breg to 0 because we have arranged to add
5909 it in in both cases. */
5913 macro_build_lui (&expr1
, AT
);
5914 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5915 AT
, AT
, BFD_RELOC_LO16
);
5916 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5917 tempreg
, tempreg
, AT
);
5922 else if (mips_big_got
&& HAVE_NEWABI
)
5924 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5925 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5926 int add_breg_early
= 0;
5928 /* This is the large GOT case. If this is a reference to an
5929 external symbol, and there is no constant, we want
5930 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5931 add $tempreg,$tempreg,$gp
5932 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5933 or for lca or if tempreg is PIC_CALL_REG
5934 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5935 add $tempreg,$tempreg,$gp
5936 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5938 If we have a small constant, and this is a reference to
5939 an external symbol, we want
5940 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5941 add $tempreg,$tempreg,$gp
5942 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5943 addi $tempreg,$tempreg,<constant>
5945 If we have a large constant, and this is a reference to
5946 an external symbol, we want
5947 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5948 addu $tempreg,$tempreg,$gp
5949 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5950 lui $at,<hiconstant>
5951 addi $at,$at,<loconstant>
5952 add $tempreg,$tempreg,$at
5954 If we have NewABI, and we know it's a local symbol, we want
5955 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5956 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5957 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5959 relax_start (offset_expr
.X_add_symbol
);
5961 expr1
.X_add_number
= offset_expr
.X_add_number
;
5962 offset_expr
.X_add_number
= 0;
5964 if (expr1
.X_add_number
== 0 && breg
== 0
5965 && (call
|| tempreg
== PIC_CALL_REG
))
5967 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5968 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5970 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5971 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5972 tempreg
, tempreg
, mips_gp_register
);
5973 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5974 tempreg
, lw_reloc_type
, tempreg
);
5976 if (expr1
.X_add_number
== 0)
5978 else if (expr1
.X_add_number
>= -0x8000
5979 && expr1
.X_add_number
< 0x8000)
5981 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5982 tempreg
, tempreg
, BFD_RELOC_LO16
);
5984 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5988 /* If we are going to add in a base register, and the
5989 target register and the base register are the same,
5990 then we are using AT as a temporary register. Since
5991 we want to load the constant into AT, we add our
5992 current AT (from the global offset table) and the
5993 register into the register now, and pretend we were
5994 not using a base register. */
5999 assert (tempreg
== AT
);
6000 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6006 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6007 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6012 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6015 offset_expr
.X_add_number
= expr1
.X_add_number
;
6016 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6017 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6018 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6019 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6022 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6023 treg
, tempreg
, breg
);
6033 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6037 /* The j instruction may not be used in PIC code, since it
6038 requires an absolute address. We convert it to a b
6040 if (mips_pic
== NO_PIC
)
6041 macro_build (&offset_expr
, "j", "a");
6043 macro_build (&offset_expr
, "b", "p");
6046 /* The jal instructions must be handled as macros because when
6047 generating PIC code they expand to multi-instruction
6048 sequences. Normally they are simple instructions. */
6053 if (mips_pic
== NO_PIC
)
6054 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6057 if (sreg
!= PIC_CALL_REG
)
6058 as_warn (_("MIPS PIC call to register other than $25"));
6060 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6061 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6063 if (mips_cprestore_offset
< 0)
6064 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6067 if (! mips_frame_reg_valid
)
6069 as_warn (_("No .frame pseudo-op used in PIC code"));
6070 /* Quiet this warning. */
6071 mips_frame_reg_valid
= 1;
6073 if (! mips_cprestore_valid
)
6075 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6076 /* Quiet this warning. */
6077 mips_cprestore_valid
= 1;
6079 expr1
.X_add_number
= mips_cprestore_offset
;
6080 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6083 HAVE_64BIT_ADDRESSES
);
6091 if (mips_pic
== NO_PIC
)
6092 macro_build (&offset_expr
, "jal", "a");
6093 else if (mips_pic
== SVR4_PIC
)
6095 /* If this is a reference to an external symbol, and we are
6096 using a small GOT, we want
6097 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6101 lw $gp,cprestore($sp)
6102 The cprestore value is set using the .cprestore
6103 pseudo-op. If we are using a big GOT, we want
6104 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6106 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6110 lw $gp,cprestore($sp)
6111 If the symbol is not external, we want
6112 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6114 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6117 lw $gp,cprestore($sp)
6119 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6120 sequences above, minus nops, unless the symbol is local,
6121 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6127 relax_start (offset_expr
.X_add_symbol
);
6128 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6129 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6132 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6133 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6139 relax_start (offset_expr
.X_add_symbol
);
6140 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6141 BFD_RELOC_MIPS_CALL_HI16
);
6142 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6143 PIC_CALL_REG
, mips_gp_register
);
6144 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6145 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6148 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6149 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6151 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6152 PIC_CALL_REG
, PIC_CALL_REG
,
6153 BFD_RELOC_MIPS_GOT_OFST
);
6157 macro_build_jalr (&offset_expr
);
6161 relax_start (offset_expr
.X_add_symbol
);
6164 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6165 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6174 gpdelay
= reg_needs_delay (mips_gp_register
);
6175 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6176 BFD_RELOC_MIPS_CALL_HI16
);
6177 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6178 PIC_CALL_REG
, mips_gp_register
);
6179 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6180 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6185 macro_build (NULL
, "nop", "");
6187 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6188 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6191 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6192 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6194 macro_build_jalr (&offset_expr
);
6196 if (mips_cprestore_offset
< 0)
6197 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6200 if (! mips_frame_reg_valid
)
6202 as_warn (_("No .frame pseudo-op used in PIC code"));
6203 /* Quiet this warning. */
6204 mips_frame_reg_valid
= 1;
6206 if (! mips_cprestore_valid
)
6208 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6209 /* Quiet this warning. */
6210 mips_cprestore_valid
= 1;
6212 if (mips_opts
.noreorder
)
6213 macro_build (NULL
, "nop", "");
6214 expr1
.X_add_number
= mips_cprestore_offset
;
6215 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6218 HAVE_64BIT_ADDRESSES
);
6222 else if (mips_pic
== VXWORKS_PIC
)
6223 as_bad (_("Non-PIC jump used in PIC library"));
6246 /* Itbl support may require additional care here. */
6251 /* Itbl support may require additional care here. */
6256 /* Itbl support may require additional care here. */
6261 /* Itbl support may require additional care here. */
6274 /* Itbl support may require additional care here. */
6279 /* Itbl support may require additional care here. */
6284 /* Itbl support may require additional care here. */
6304 if (breg
== treg
|| coproc
|| lr
)
6325 /* Itbl support may require additional care here. */
6330 /* Itbl support may require additional care here. */
6335 /* Itbl support may require additional care here. */
6340 /* Itbl support may require additional care here. */
6361 /* Itbl support may require additional care here. */
6365 /* Itbl support may require additional care here. */
6370 /* Itbl support may require additional care here. */
6383 && NO_ISA_COP (mips_opts
.arch
)
6384 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6386 as_bad (_("opcode not supported on this processor: %s"),
6387 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6391 /* Itbl support may require additional care here. */
6392 if (mask
== M_LWC1_AB
6393 || mask
== M_SWC1_AB
6394 || mask
== M_LDC1_AB
6395 || mask
== M_SDC1_AB
6399 else if (mask
== M_CACHE_AB
)
6406 if (offset_expr
.X_op
!= O_constant
6407 && offset_expr
.X_op
!= O_symbol
)
6409 as_bad (_("expression too complex"));
6410 offset_expr
.X_op
= O_constant
;
6413 if (HAVE_32BIT_ADDRESSES
6414 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6418 sprintf_vma (value
, offset_expr
.X_add_number
);
6419 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6422 /* A constant expression in PIC code can be handled just as it
6423 is in non PIC code. */
6424 if (offset_expr
.X_op
== O_constant
)
6426 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6427 & ~(bfd_vma
) 0xffff);
6428 normalize_address_expr (&expr1
);
6429 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6431 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6432 tempreg
, tempreg
, breg
);
6433 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6435 else if (mips_pic
== NO_PIC
)
6437 /* If this is a reference to a GP relative symbol, and there
6438 is no base register, we want
6439 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6440 Otherwise, if there is no base register, we want
6441 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6442 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6443 If we have a constant, we need two instructions anyhow,
6444 so we always use the latter form.
6446 If we have a base register, and this is a reference to a
6447 GP relative symbol, we want
6448 addu $tempreg,$breg,$gp
6449 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6451 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6452 addu $tempreg,$tempreg,$breg
6453 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6454 With a constant we always use the latter case.
6456 With 64bit address space and no base register and $at usable,
6458 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6459 lui $at,<sym> (BFD_RELOC_HI16_S)
6460 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6463 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6464 If we have a base register, we want
6465 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6466 lui $at,<sym> (BFD_RELOC_HI16_S)
6467 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6471 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6473 Without $at we can't generate the optimal path for superscalar
6474 processors here since this would require two temporary registers.
6475 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6476 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6478 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6480 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6481 If we have a base register, we want
6482 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6483 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6485 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6487 daddu $tempreg,$tempreg,$breg
6488 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6490 For GP relative symbols in 64bit address space we can use
6491 the same sequence as in 32bit address space. */
6492 if (HAVE_64BIT_SYMBOLS
)
6494 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6495 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6497 relax_start (offset_expr
.X_add_symbol
);
6500 macro_build (&offset_expr
, s
, fmt
, treg
,
6501 BFD_RELOC_GPREL16
, mips_gp_register
);
6505 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6506 tempreg
, breg
, mips_gp_register
);
6507 macro_build (&offset_expr
, s
, fmt
, treg
,
6508 BFD_RELOC_GPREL16
, tempreg
);
6513 if (used_at
== 0 && mips_opts
.at
)
6515 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6516 BFD_RELOC_MIPS_HIGHEST
);
6517 macro_build (&offset_expr
, "lui", "t,u", AT
,
6519 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6520 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6522 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6523 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6524 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6525 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6531 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6532 BFD_RELOC_MIPS_HIGHEST
);
6533 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6534 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6535 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6536 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6537 tempreg
, BFD_RELOC_HI16_S
);
6538 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6540 macro_build (NULL
, "daddu", "d,v,t",
6541 tempreg
, tempreg
, breg
);
6542 macro_build (&offset_expr
, s
, fmt
, treg
,
6543 BFD_RELOC_LO16
, tempreg
);
6546 if (mips_relax
.sequence
)
6553 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6554 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6556 relax_start (offset_expr
.X_add_symbol
);
6557 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6561 macro_build_lui (&offset_expr
, tempreg
);
6562 macro_build (&offset_expr
, s
, fmt
, treg
,
6563 BFD_RELOC_LO16
, tempreg
);
6564 if (mips_relax
.sequence
)
6569 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6570 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6572 relax_start (offset_expr
.X_add_symbol
);
6573 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6574 tempreg
, breg
, mips_gp_register
);
6575 macro_build (&offset_expr
, s
, fmt
, treg
,
6576 BFD_RELOC_GPREL16
, tempreg
);
6579 macro_build_lui (&offset_expr
, tempreg
);
6580 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6581 tempreg
, tempreg
, breg
);
6582 macro_build (&offset_expr
, s
, fmt
, treg
,
6583 BFD_RELOC_LO16
, tempreg
);
6584 if (mips_relax
.sequence
)
6588 else if (!mips_big_got
)
6590 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6592 /* If this is a reference to an external symbol, we want
6593 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6595 <op> $treg,0($tempreg)
6597 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6599 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6600 <op> $treg,0($tempreg)
6603 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6604 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6606 If there is a base register, we add it to $tempreg before
6607 the <op>. If there is a constant, we stick it in the
6608 <op> instruction. We don't handle constants larger than
6609 16 bits, because we have no way to load the upper 16 bits
6610 (actually, we could handle them for the subset of cases
6611 in which we are not using $at). */
6612 assert (offset_expr
.X_op
== O_symbol
);
6615 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6616 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6618 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6619 tempreg
, tempreg
, breg
);
6620 macro_build (&offset_expr
, s
, fmt
, treg
,
6621 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6624 expr1
.X_add_number
= offset_expr
.X_add_number
;
6625 offset_expr
.X_add_number
= 0;
6626 if (expr1
.X_add_number
< -0x8000
6627 || expr1
.X_add_number
>= 0x8000)
6628 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6629 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6630 lw_reloc_type
, mips_gp_register
);
6632 relax_start (offset_expr
.X_add_symbol
);
6634 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6635 tempreg
, BFD_RELOC_LO16
);
6638 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6639 tempreg
, tempreg
, breg
);
6640 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6642 else if (mips_big_got
&& !HAVE_NEWABI
)
6646 /* If this is a reference to an external symbol, we want
6647 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6648 addu $tempreg,$tempreg,$gp
6649 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6650 <op> $treg,0($tempreg)
6652 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6654 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6655 <op> $treg,0($tempreg)
6656 If there is a base register, we add it to $tempreg before
6657 the <op>. If there is a constant, we stick it in the
6658 <op> instruction. We don't handle constants larger than
6659 16 bits, because we have no way to load the upper 16 bits
6660 (actually, we could handle them for the subset of cases
6661 in which we are not using $at). */
6662 assert (offset_expr
.X_op
== O_symbol
);
6663 expr1
.X_add_number
= offset_expr
.X_add_number
;
6664 offset_expr
.X_add_number
= 0;
6665 if (expr1
.X_add_number
< -0x8000
6666 || expr1
.X_add_number
>= 0x8000)
6667 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6668 gpdelay
= reg_needs_delay (mips_gp_register
);
6669 relax_start (offset_expr
.X_add_symbol
);
6670 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6671 BFD_RELOC_MIPS_GOT_HI16
);
6672 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6674 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6675 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6678 macro_build (NULL
, "nop", "");
6679 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6680 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6682 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6683 tempreg
, BFD_RELOC_LO16
);
6687 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6688 tempreg
, tempreg
, breg
);
6689 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6691 else if (mips_big_got
&& HAVE_NEWABI
)
6693 /* If this is a reference to an external symbol, we want
6694 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6695 add $tempreg,$tempreg,$gp
6696 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6697 <op> $treg,<ofst>($tempreg)
6698 Otherwise, for local symbols, we want:
6699 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6700 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6701 assert (offset_expr
.X_op
== O_symbol
);
6702 expr1
.X_add_number
= offset_expr
.X_add_number
;
6703 offset_expr
.X_add_number
= 0;
6704 if (expr1
.X_add_number
< -0x8000
6705 || expr1
.X_add_number
>= 0x8000)
6706 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6707 relax_start (offset_expr
.X_add_symbol
);
6708 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6709 BFD_RELOC_MIPS_GOT_HI16
);
6710 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6712 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6713 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6715 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6716 tempreg
, tempreg
, breg
);
6717 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6720 offset_expr
.X_add_number
= expr1
.X_add_number
;
6721 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6722 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6724 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6725 tempreg
, tempreg
, breg
);
6726 macro_build (&offset_expr
, s
, fmt
, treg
,
6727 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6737 load_register (treg
, &imm_expr
, 0);
6741 load_register (treg
, &imm_expr
, 1);
6745 if (imm_expr
.X_op
== O_constant
)
6748 load_register (AT
, &imm_expr
, 0);
6749 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6754 assert (offset_expr
.X_op
== O_symbol
6755 && strcmp (segment_name (S_GET_SEGMENT
6756 (offset_expr
.X_add_symbol
)),
6758 && offset_expr
.X_add_number
== 0);
6759 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6760 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6765 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6766 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6767 order 32 bits of the value and the low order 32 bits are either
6768 zero or in OFFSET_EXPR. */
6769 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6771 if (HAVE_64BIT_GPRS
)
6772 load_register (treg
, &imm_expr
, 1);
6777 if (target_big_endian
)
6789 load_register (hreg
, &imm_expr
, 0);
6792 if (offset_expr
.X_op
== O_absent
)
6793 move_register (lreg
, 0);
6796 assert (offset_expr
.X_op
== O_constant
);
6797 load_register (lreg
, &offset_expr
, 0);
6804 /* We know that sym is in the .rdata section. First we get the
6805 upper 16 bits of the address. */
6806 if (mips_pic
== NO_PIC
)
6808 macro_build_lui (&offset_expr
, AT
);
6813 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6814 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6818 /* Now we load the register(s). */
6819 if (HAVE_64BIT_GPRS
)
6822 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6827 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6830 /* FIXME: How in the world do we deal with the possible
6832 offset_expr
.X_add_number
+= 4;
6833 macro_build (&offset_expr
, "lw", "t,o(b)",
6834 treg
+ 1, BFD_RELOC_LO16
, AT
);
6840 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6841 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6842 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6843 the value and the low order 32 bits are either zero or in
6845 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6848 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6849 if (HAVE_64BIT_FPRS
)
6851 assert (HAVE_64BIT_GPRS
);
6852 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6856 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6857 if (offset_expr
.X_op
== O_absent
)
6858 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6861 assert (offset_expr
.X_op
== O_constant
);
6862 load_register (AT
, &offset_expr
, 0);
6863 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6869 assert (offset_expr
.X_op
== O_symbol
6870 && offset_expr
.X_add_number
== 0);
6871 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6872 if (strcmp (s
, ".lit8") == 0)
6874 if (mips_opts
.isa
!= ISA_MIPS1
)
6876 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6877 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6880 breg
= mips_gp_register
;
6881 r
= BFD_RELOC_MIPS_LITERAL
;
6886 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6888 if (mips_pic
!= NO_PIC
)
6889 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6890 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6893 /* FIXME: This won't work for a 64 bit address. */
6894 macro_build_lui (&offset_expr
, AT
);
6897 if (mips_opts
.isa
!= ISA_MIPS1
)
6899 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6900 treg
, BFD_RELOC_LO16
, AT
);
6909 /* Even on a big endian machine $fn comes before $fn+1. We have
6910 to adjust when loading from memory. */
6913 assert (mips_opts
.isa
== ISA_MIPS1
);
6914 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6915 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6916 /* FIXME: A possible overflow which I don't know how to deal
6918 offset_expr
.X_add_number
+= 4;
6919 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6920 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6925 * The MIPS assembler seems to check for X_add_number not
6926 * being double aligned and generating:
6929 * addiu at,at,%lo(foo+1)
6932 * But, the resulting address is the same after relocation so why
6933 * generate the extra instruction?
6935 /* Itbl support may require additional care here. */
6937 if (mips_opts
.isa
!= ISA_MIPS1
)
6948 if (mips_opts
.isa
!= ISA_MIPS1
)
6956 /* Itbl support may require additional care here. */
6961 if (HAVE_64BIT_GPRS
)
6972 if (HAVE_64BIT_GPRS
)
6982 if (offset_expr
.X_op
!= O_symbol
6983 && offset_expr
.X_op
!= O_constant
)
6985 as_bad (_("expression too complex"));
6986 offset_expr
.X_op
= O_constant
;
6989 if (HAVE_32BIT_ADDRESSES
6990 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6994 sprintf_vma (value
, offset_expr
.X_add_number
);
6995 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6998 /* Even on a big endian machine $fn comes before $fn+1. We have
6999 to adjust when loading from memory. We set coproc if we must
7000 load $fn+1 first. */
7001 /* Itbl support may require additional care here. */
7002 if (! target_big_endian
)
7005 if (mips_pic
== NO_PIC
7006 || offset_expr
.X_op
== O_constant
)
7008 /* If this is a reference to a GP relative symbol, we want
7009 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7010 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7011 If we have a base register, we use this
7013 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7014 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7015 If this is not a GP relative symbol, we want
7016 lui $at,<sym> (BFD_RELOC_HI16_S)
7017 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7018 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7019 If there is a base register, we add it to $at after the
7020 lui instruction. If there is a constant, we always use
7022 if (offset_expr
.X_op
== O_symbol
7023 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7024 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7026 relax_start (offset_expr
.X_add_symbol
);
7029 tempreg
= mips_gp_register
;
7033 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7034 AT
, breg
, mips_gp_register
);
7039 /* Itbl support may require additional care here. */
7040 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7041 BFD_RELOC_GPREL16
, tempreg
);
7042 offset_expr
.X_add_number
+= 4;
7044 /* Set mips_optimize to 2 to avoid inserting an
7046 hold_mips_optimize
= mips_optimize
;
7048 /* Itbl support may require additional care here. */
7049 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7050 BFD_RELOC_GPREL16
, tempreg
);
7051 mips_optimize
= hold_mips_optimize
;
7055 /* We just generated two relocs. When tc_gen_reloc
7056 handles this case, it will skip the first reloc and
7057 handle the second. The second reloc already has an
7058 extra addend of 4, which we added above. We must
7059 subtract it out, and then subtract another 4 to make
7060 the first reloc come out right. The second reloc
7061 will come out right because we are going to add 4 to
7062 offset_expr when we build its instruction below.
7064 If we have a symbol, then we don't want to include
7065 the offset, because it will wind up being included
7066 when we generate the reloc. */
7068 if (offset_expr
.X_op
== O_constant
)
7069 offset_expr
.X_add_number
-= 8;
7072 offset_expr
.X_add_number
= -4;
7073 offset_expr
.X_op
= O_constant
;
7077 macro_build_lui (&offset_expr
, AT
);
7079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7080 /* Itbl support may require additional care here. */
7081 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7082 BFD_RELOC_LO16
, AT
);
7083 /* FIXME: How do we handle overflow here? */
7084 offset_expr
.X_add_number
+= 4;
7085 /* Itbl support may require additional care here. */
7086 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7087 BFD_RELOC_LO16
, AT
);
7088 if (mips_relax
.sequence
)
7091 else if (!mips_big_got
)
7093 /* If this is a reference to an external symbol, we want
7094 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7099 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7101 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7102 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7103 If there is a base register we add it to $at before the
7104 lwc1 instructions. If there is a constant we include it
7105 in the lwc1 instructions. */
7107 expr1
.X_add_number
= offset_expr
.X_add_number
;
7108 if (expr1
.X_add_number
< -0x8000
7109 || expr1
.X_add_number
>= 0x8000 - 4)
7110 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7111 load_got_offset (AT
, &offset_expr
);
7114 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7116 /* Set mips_optimize to 2 to avoid inserting an undesired
7118 hold_mips_optimize
= mips_optimize
;
7121 /* Itbl support may require additional care here. */
7122 relax_start (offset_expr
.X_add_symbol
);
7123 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7124 BFD_RELOC_LO16
, AT
);
7125 expr1
.X_add_number
+= 4;
7126 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7127 BFD_RELOC_LO16
, AT
);
7129 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7130 BFD_RELOC_LO16
, AT
);
7131 offset_expr
.X_add_number
+= 4;
7132 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7133 BFD_RELOC_LO16
, AT
);
7136 mips_optimize
= hold_mips_optimize
;
7138 else if (mips_big_got
)
7142 /* If this is a reference to an external symbol, we want
7143 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7145 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7150 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7152 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7153 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7154 If there is a base register we add it to $at before the
7155 lwc1 instructions. If there is a constant we include it
7156 in the lwc1 instructions. */
7158 expr1
.X_add_number
= offset_expr
.X_add_number
;
7159 offset_expr
.X_add_number
= 0;
7160 if (expr1
.X_add_number
< -0x8000
7161 || expr1
.X_add_number
>= 0x8000 - 4)
7162 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7163 gpdelay
= reg_needs_delay (mips_gp_register
);
7164 relax_start (offset_expr
.X_add_symbol
);
7165 macro_build (&offset_expr
, "lui", "t,u",
7166 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7167 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7168 AT
, AT
, mips_gp_register
);
7169 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7170 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7174 /* Itbl support may require additional care here. */
7175 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7176 BFD_RELOC_LO16
, AT
);
7177 expr1
.X_add_number
+= 4;
7179 /* Set mips_optimize to 2 to avoid inserting an undesired
7181 hold_mips_optimize
= mips_optimize
;
7183 /* Itbl support may require additional care here. */
7184 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7185 BFD_RELOC_LO16
, AT
);
7186 mips_optimize
= hold_mips_optimize
;
7187 expr1
.X_add_number
-= 4;
7190 offset_expr
.X_add_number
= expr1
.X_add_number
;
7192 macro_build (NULL
, "nop", "");
7193 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7194 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7197 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7198 /* Itbl support may require additional care here. */
7199 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7200 BFD_RELOC_LO16
, AT
);
7201 offset_expr
.X_add_number
+= 4;
7203 /* Set mips_optimize to 2 to avoid inserting an undesired
7205 hold_mips_optimize
= mips_optimize
;
7207 /* Itbl support may require additional care here. */
7208 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7209 BFD_RELOC_LO16
, AT
);
7210 mips_optimize
= hold_mips_optimize
;
7224 assert (HAVE_32BIT_ADDRESSES
);
7225 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7226 offset_expr
.X_add_number
+= 4;
7227 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7230 /* New code added to support COPZ instructions.
7231 This code builds table entries out of the macros in mip_opcodes.
7232 R4000 uses interlocks to handle coproc delays.
7233 Other chips (like the R3000) require nops to be inserted for delays.
7235 FIXME: Currently, we require that the user handle delays.
7236 In order to fill delay slots for non-interlocked chips,
7237 we must have a way to specify delays based on the coprocessor.
7238 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7239 What are the side-effects of the cop instruction?
7240 What cache support might we have and what are its effects?
7241 Both coprocessor & memory require delays. how long???
7242 What registers are read/set/modified?
7244 If an itbl is provided to interpret cop instructions,
7245 this knowledge can be encoded in the itbl spec. */
7259 if (NO_ISA_COP (mips_opts
.arch
)
7260 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7262 as_bad (_("opcode not supported on this processor: %s"),
7263 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7267 /* For now we just do C (same as Cz). The parameter will be
7268 stored in insn_opcode by mips_ip. */
7269 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7273 move_register (dreg
, sreg
);
7276 #ifdef LOSING_COMPILER
7278 /* Try and see if this is a new itbl instruction.
7279 This code builds table entries out of the macros in mip_opcodes.
7280 FIXME: For now we just assemble the expression and pass it's
7281 value along as a 32-bit immediate.
7282 We may want to have the assembler assemble this value,
7283 so that we gain the assembler's knowledge of delay slots,
7285 Would it be more efficient to use mask (id) here? */
7286 if (itbl_have_entries
7287 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7289 s
= ip
->insn_mo
->name
;
7291 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7292 macro_build (&immed_expr
, s
, "C");
7298 if (!mips_opts
.at
&& used_at
)
7299 as_bad (_("Macro used $at after \".set noat\""));
7303 macro2 (struct mips_cl_insn
*ip
)
7305 unsigned int treg
, sreg
, dreg
, breg
;
7306 unsigned int tempreg
;
7320 bfd_reloc_code_real_type r
;
7322 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7323 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7324 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7325 mask
= ip
->insn_mo
->mask
;
7327 expr1
.X_op
= O_constant
;
7328 expr1
.X_op_symbol
= NULL
;
7329 expr1
.X_add_symbol
= NULL
;
7330 expr1
.X_add_number
= 1;
7334 #endif /* LOSING_COMPILER */
7339 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7340 macro_build (NULL
, "mflo", "d", dreg
);
7346 /* The MIPS assembler some times generates shifts and adds. I'm
7347 not trying to be that fancy. GCC should do this for us
7350 load_register (AT
, &imm_expr
, dbl
);
7351 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7352 macro_build (NULL
, "mflo", "d", dreg
);
7368 load_register (AT
, &imm_expr
, dbl
);
7369 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7370 macro_build (NULL
, "mflo", "d", dreg
);
7371 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7372 macro_build (NULL
, "mfhi", "d", AT
);
7374 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7377 expr1
.X_add_number
= 8;
7378 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7379 macro_build (NULL
, "nop", "", 0);
7380 macro_build (NULL
, "break", "c", 6);
7383 macro_build (NULL
, "mflo", "d", dreg
);
7399 load_register (AT
, &imm_expr
, dbl
);
7400 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7401 sreg
, imm
? AT
: treg
);
7402 macro_build (NULL
, "mfhi", "d", AT
);
7403 macro_build (NULL
, "mflo", "d", dreg
);
7405 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7408 expr1
.X_add_number
= 8;
7409 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7410 macro_build (NULL
, "nop", "", 0);
7411 macro_build (NULL
, "break", "c", 6);
7417 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7428 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7429 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7433 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7434 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7435 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7436 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7440 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7451 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7452 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7456 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7457 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7458 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7459 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7467 if (imm_expr
.X_op
!= O_constant
)
7468 as_bad (_("Improper rotate count"));
7469 rot
= imm_expr
.X_add_number
& 0x3f;
7470 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7472 rot
= (64 - rot
) & 0x3f;
7474 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7476 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7481 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7484 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7485 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7488 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7489 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7490 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7498 if (imm_expr
.X_op
!= O_constant
)
7499 as_bad (_("Improper rotate count"));
7500 rot
= imm_expr
.X_add_number
& 0x1f;
7501 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7503 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7508 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7512 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7513 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7514 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7519 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7521 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7525 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7526 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7527 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7528 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7532 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7534 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7538 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7539 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7540 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7541 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7549 if (imm_expr
.X_op
!= O_constant
)
7550 as_bad (_("Improper rotate count"));
7551 rot
= imm_expr
.X_add_number
& 0x3f;
7552 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7555 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7557 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7562 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7565 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7566 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7569 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7570 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7571 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7579 if (imm_expr
.X_op
!= O_constant
)
7580 as_bad (_("Improper rotate count"));
7581 rot
= imm_expr
.X_add_number
& 0x1f;
7582 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7584 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7589 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7593 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7594 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7595 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7600 assert (mips_opts
.isa
== ISA_MIPS1
);
7601 /* Even on a big endian machine $fn comes before $fn+1. We have
7602 to adjust when storing to memory. */
7603 macro_build (&offset_expr
, "swc1", "T,o(b)",
7604 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7605 offset_expr
.X_add_number
+= 4;
7606 macro_build (&offset_expr
, "swc1", "T,o(b)",
7607 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7612 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7614 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7617 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7618 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7623 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7625 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7630 as_warn (_("Instruction %s: result is always false"),
7632 move_register (dreg
, 0);
7635 if (CPU_HAS_SEQ (mips_opts
.arch
)
7636 && -512 <= imm_expr
.X_add_number
7637 && imm_expr
.X_add_number
< 512)
7639 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7640 (int) imm_expr
.X_add_number
);
7643 if (imm_expr
.X_op
== O_constant
7644 && imm_expr
.X_add_number
>= 0
7645 && imm_expr
.X_add_number
< 0x10000)
7647 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7649 else if (imm_expr
.X_op
== O_constant
7650 && imm_expr
.X_add_number
> -0x8000
7651 && imm_expr
.X_add_number
< 0)
7653 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7654 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7655 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7657 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7660 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7661 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7666 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7667 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7670 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7673 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7679 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7680 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7683 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7685 if (imm_expr
.X_op
== O_constant
7686 && imm_expr
.X_add_number
>= -0x8000
7687 && imm_expr
.X_add_number
< 0x8000)
7689 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7690 dreg
, sreg
, BFD_RELOC_LO16
);
7694 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7695 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7699 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7702 case M_SGT
: /* sreg > treg <==> treg < sreg */
7708 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7711 case M_SGT_I
: /* sreg > I <==> I < sreg */
7718 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7719 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7722 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7728 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7729 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7732 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7739 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7740 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7741 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7745 if (imm_expr
.X_op
== O_constant
7746 && imm_expr
.X_add_number
>= -0x8000
7747 && imm_expr
.X_add_number
< 0x8000)
7749 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7753 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7754 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7758 if (imm_expr
.X_op
== O_constant
7759 && imm_expr
.X_add_number
>= -0x8000
7760 && imm_expr
.X_add_number
< 0x8000)
7762 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7767 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7768 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7773 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7775 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7778 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7779 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7784 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7786 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7791 as_warn (_("Instruction %s: result is always true"),
7793 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7794 dreg
, 0, BFD_RELOC_LO16
);
7797 if (CPU_HAS_SEQ (mips_opts
.arch
)
7798 && -512 <= imm_expr
.X_add_number
7799 && imm_expr
.X_add_number
< 512)
7801 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7802 (int) imm_expr
.X_add_number
);
7805 if (imm_expr
.X_op
== O_constant
7806 && imm_expr
.X_add_number
>= 0
7807 && imm_expr
.X_add_number
< 0x10000)
7809 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7811 else if (imm_expr
.X_op
== O_constant
7812 && imm_expr
.X_add_number
> -0x8000
7813 && imm_expr
.X_add_number
< 0)
7815 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7816 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7817 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7819 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7822 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7823 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7828 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7829 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7832 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7838 if (imm_expr
.X_op
== O_constant
7839 && imm_expr
.X_add_number
> -0x8000
7840 && imm_expr
.X_add_number
<= 0x8000)
7842 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7843 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7844 dreg
, sreg
, BFD_RELOC_LO16
);
7848 load_register (AT
, &imm_expr
, dbl
);
7849 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7855 if (imm_expr
.X_op
== O_constant
7856 && imm_expr
.X_add_number
> -0x8000
7857 && imm_expr
.X_add_number
<= 0x8000)
7859 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7860 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7861 dreg
, sreg
, BFD_RELOC_LO16
);
7865 load_register (AT
, &imm_expr
, dbl
);
7866 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7888 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7889 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7894 assert (mips_opts
.isa
== ISA_MIPS1
);
7896 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7897 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7900 * Is the double cfc1 instruction a bug in the mips assembler;
7901 * or is there a reason for it?
7904 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7905 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7906 macro_build (NULL
, "nop", "");
7907 expr1
.X_add_number
= 3;
7908 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7909 expr1
.X_add_number
= 2;
7910 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7911 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7912 macro_build (NULL
, "nop", "");
7913 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7915 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7916 macro_build (NULL
, "nop", "");
7927 if (offset_expr
.X_add_number
>= 0x7fff)
7928 as_bad (_("operand overflow"));
7929 if (! target_big_endian
)
7930 ++offset_expr
.X_add_number
;
7931 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7932 if (! target_big_endian
)
7933 --offset_expr
.X_add_number
;
7935 ++offset_expr
.X_add_number
;
7936 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7937 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7938 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7951 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7952 as_bad (_("operand overflow"));
7960 if (! target_big_endian
)
7961 offset_expr
.X_add_number
+= off
;
7962 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7963 if (! target_big_endian
)
7964 offset_expr
.X_add_number
-= off
;
7966 offset_expr
.X_add_number
+= off
;
7967 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7969 /* If necessary, move the result in tempreg the final destination. */
7970 if (treg
== tempreg
)
7972 /* Protect second load's delay slot. */
7974 move_register (treg
, tempreg
);
7988 load_address (AT
, &offset_expr
, &used_at
);
7990 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7991 if (! target_big_endian
)
7992 expr1
.X_add_number
= off
;
7994 expr1
.X_add_number
= 0;
7995 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7996 if (! target_big_endian
)
7997 expr1
.X_add_number
= 0;
7999 expr1
.X_add_number
= off
;
8000 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8006 load_address (AT
, &offset_expr
, &used_at
);
8008 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8009 if (target_big_endian
)
8010 expr1
.X_add_number
= 0;
8011 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8012 treg
, BFD_RELOC_LO16
, AT
);
8013 if (target_big_endian
)
8014 expr1
.X_add_number
= 1;
8016 expr1
.X_add_number
= 0;
8017 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8018 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8019 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8024 if (offset_expr
.X_add_number
>= 0x7fff)
8025 as_bad (_("operand overflow"));
8026 if (target_big_endian
)
8027 ++offset_expr
.X_add_number
;
8028 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8029 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8030 if (target_big_endian
)
8031 --offset_expr
.X_add_number
;
8033 ++offset_expr
.X_add_number
;
8034 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8047 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8048 as_bad (_("operand overflow"));
8049 if (! target_big_endian
)
8050 offset_expr
.X_add_number
+= off
;
8051 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8052 if (! target_big_endian
)
8053 offset_expr
.X_add_number
-= off
;
8055 offset_expr
.X_add_number
+= off
;
8056 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8070 load_address (AT
, &offset_expr
, &used_at
);
8072 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8073 if (! target_big_endian
)
8074 expr1
.X_add_number
= off
;
8076 expr1
.X_add_number
= 0;
8077 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8078 if (! target_big_endian
)
8079 expr1
.X_add_number
= 0;
8081 expr1
.X_add_number
= off
;
8082 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8087 load_address (AT
, &offset_expr
, &used_at
);
8089 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8090 if (! target_big_endian
)
8091 expr1
.X_add_number
= 0;
8092 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8093 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8094 if (! target_big_endian
)
8095 expr1
.X_add_number
= 1;
8097 expr1
.X_add_number
= 0;
8098 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8099 if (! target_big_endian
)
8100 expr1
.X_add_number
= 0;
8102 expr1
.X_add_number
= 1;
8103 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8104 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8105 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8109 /* FIXME: Check if this is one of the itbl macros, since they
8110 are added dynamically. */
8111 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8114 if (!mips_opts
.at
&& used_at
)
8115 as_bad (_("Macro used $at after \".set noat\""));
8118 /* Implement macros in mips16 mode. */
8121 mips16_macro (struct mips_cl_insn
*ip
)
8124 int xreg
, yreg
, zreg
, tmp
;
8127 const char *s
, *s2
, *s3
;
8129 mask
= ip
->insn_mo
->mask
;
8131 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8132 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8133 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8135 expr1
.X_op
= O_constant
;
8136 expr1
.X_op_symbol
= NULL
;
8137 expr1
.X_add_symbol
= NULL
;
8138 expr1
.X_add_number
= 1;
8158 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8159 expr1
.X_add_number
= 2;
8160 macro_build (&expr1
, "bnez", "x,p", yreg
);
8161 macro_build (NULL
, "break", "6", 7);
8163 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8164 since that causes an overflow. We should do that as well,
8165 but I don't see how to do the comparisons without a temporary
8168 macro_build (NULL
, s
, "x", zreg
);
8188 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8189 expr1
.X_add_number
= 2;
8190 macro_build (&expr1
, "bnez", "x,p", yreg
);
8191 macro_build (NULL
, "break", "6", 7);
8193 macro_build (NULL
, s2
, "x", zreg
);
8199 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8200 macro_build (NULL
, "mflo", "x", zreg
);
8208 if (imm_expr
.X_op
!= O_constant
)
8209 as_bad (_("Unsupported large constant"));
8210 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8211 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8215 if (imm_expr
.X_op
!= O_constant
)
8216 as_bad (_("Unsupported large constant"));
8217 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8218 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8222 if (imm_expr
.X_op
!= O_constant
)
8223 as_bad (_("Unsupported large constant"));
8224 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8225 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8247 goto do_reverse_branch
;
8251 goto do_reverse_branch
;
8263 goto do_reverse_branch
;
8274 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8275 macro_build (&offset_expr
, s2
, "p");
8302 goto do_addone_branch_i
;
8307 goto do_addone_branch_i
;
8322 goto do_addone_branch_i
;
8329 if (imm_expr
.X_op
!= O_constant
)
8330 as_bad (_("Unsupported large constant"));
8331 ++imm_expr
.X_add_number
;
8334 macro_build (&imm_expr
, s
, s3
, xreg
);
8335 macro_build (&offset_expr
, s2
, "p");
8339 expr1
.X_add_number
= 0;
8340 macro_build (&expr1
, "slti", "x,8", yreg
);
8342 move_register (xreg
, yreg
);
8343 expr1
.X_add_number
= 2;
8344 macro_build (&expr1
, "bteqz", "p");
8345 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8349 /* For consistency checking, verify that all bits are specified either
8350 by the match/mask part of the instruction definition, or by the
8353 validate_mips_insn (const struct mips_opcode
*opc
)
8355 const char *p
= opc
->args
;
8357 unsigned long used_bits
= opc
->mask
;
8359 if ((used_bits
& opc
->match
) != opc
->match
)
8361 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8362 opc
->name
, opc
->args
);
8365 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8375 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8376 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8377 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8378 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8379 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8380 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8381 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8382 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8383 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8384 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8385 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8386 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8387 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8389 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8390 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8391 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8392 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8393 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8394 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8395 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8396 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8397 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8398 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8401 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8402 c
, opc
->name
, opc
->args
);
8406 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8407 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8409 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8410 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8411 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8412 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8414 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8415 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8417 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8418 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8420 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8421 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8422 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8423 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8424 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8425 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8426 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8427 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8428 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8429 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8430 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8431 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8432 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8433 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8434 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8435 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8436 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8438 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8439 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8440 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8441 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8443 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8444 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8445 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8446 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8447 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8448 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8449 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8450 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8451 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8454 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8455 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8456 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8457 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8458 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8461 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8462 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8463 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8464 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8465 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8466 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8467 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8468 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8469 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8470 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8471 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8472 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8473 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8474 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8475 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8476 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8477 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8478 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8480 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8481 c
, opc
->name
, opc
->args
);
8485 if (used_bits
!= 0xffffffff)
8487 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8488 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8494 /* UDI immediates. */
8502 static const struct mips_immed mips_immed
[] = {
8503 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8504 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8505 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8506 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8510 /* Check whether an odd floating-point register is allowed. */
8512 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8514 const char *s
= insn
->name
;
8516 if (insn
->pinfo
== INSN_MACRO
)
8517 /* Let a macro pass, we'll catch it later when it is expanded. */
8520 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8522 /* Allow odd registers for single-precision ops. */
8523 switch (insn
->pinfo
& (FP_S
| FP_D
))
8527 return 1; /* both single precision - ok */
8529 return 0; /* both double precision - fail */
8534 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8535 s
= strchr (insn
->name
, '.');
8537 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8538 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8541 /* Single-precision coprocessor loads and moves are OK too. */
8542 if ((insn
->pinfo
& FP_S
)
8543 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8544 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8550 /* This routine assembles an instruction into its binary format. As a
8551 side effect, it sets one of the global variables imm_reloc or
8552 offset_reloc to the type of relocation to do if one of the operands
8553 is an address expression. */
8556 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8561 struct mips_opcode
*insn
;
8564 unsigned int lastregno
= 0;
8565 unsigned int lastpos
= 0;
8566 unsigned int limlo
, limhi
;
8569 offsetT min_range
, max_range
;
8575 /* If the instruction contains a '.', we first try to match an instruction
8576 including the '.'. Then we try again without the '.'. */
8578 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8581 /* If we stopped on whitespace, then replace the whitespace with null for
8582 the call to hash_find. Save the character we replaced just in case we
8583 have to re-parse the instruction. */
8590 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8592 /* If we didn't find the instruction in the opcode table, try again, but
8593 this time with just the instruction up to, but not including the
8597 /* Restore the character we overwrite above (if any). */
8601 /* Scan up to the first '.' or whitespace. */
8603 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8607 /* If we did not find a '.', then we can quit now. */
8610 insn_error
= "unrecognized opcode";
8614 /* Lookup the instruction in the hash table. */
8616 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8618 insn_error
= "unrecognized opcode";
8628 assert (strcmp (insn
->name
, str
) == 0);
8630 ok
= is_opcode_valid (insn
, FALSE
);
8633 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8634 && strcmp (insn
->name
, insn
[1].name
) == 0)
8643 static char buf
[100];
8645 _("opcode not supported on this processor: %s (%s)"),
8646 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8647 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8656 create_insn (ip
, insn
);
8659 lastregno
= 0xffffffff;
8660 for (args
= insn
->args
;; ++args
)
8664 s
+= strspn (s
, " \t");
8668 case '\0': /* end of args */
8673 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8674 my_getExpression (&imm_expr
, s
);
8675 check_absolute_expr (ip
, &imm_expr
);
8676 if ((unsigned long) imm_expr
.X_add_number
!= 1
8677 && (unsigned long) imm_expr
.X_add_number
!= 3)
8679 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8680 (unsigned long) imm_expr
.X_add_number
);
8682 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8683 imm_expr
.X_op
= O_absent
;
8687 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8688 my_getExpression (&imm_expr
, s
);
8689 check_absolute_expr (ip
, &imm_expr
);
8690 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8692 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8693 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8695 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8696 imm_expr
.X_op
= O_absent
;
8700 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8701 my_getExpression (&imm_expr
, s
);
8702 check_absolute_expr (ip
, &imm_expr
);
8703 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8705 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8706 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8708 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8709 imm_expr
.X_op
= O_absent
;
8713 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8714 my_getExpression (&imm_expr
, s
);
8715 check_absolute_expr (ip
, &imm_expr
);
8716 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8718 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8719 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8721 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8722 imm_expr
.X_op
= O_absent
;
8726 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8727 my_getExpression (&imm_expr
, s
);
8728 check_absolute_expr (ip
, &imm_expr
);
8729 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8731 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8732 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8734 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8735 imm_expr
.X_op
= O_absent
;
8739 case '7': /* four dsp accumulators in bits 11,12 */
8740 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8741 s
[3] >= '0' && s
[3] <= '3')
8745 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8749 as_bad (_("Invalid dsp acc register"));
8752 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8753 my_getExpression (&imm_expr
, s
);
8754 check_absolute_expr (ip
, &imm_expr
);
8755 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8757 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8759 (unsigned long) imm_expr
.X_add_number
);
8761 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8762 imm_expr
.X_op
= O_absent
;
8766 case '9': /* four dsp accumulators in bits 21,22 */
8767 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8768 s
[3] >= '0' && s
[3] <= '3')
8772 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8776 as_bad (_("Invalid dsp acc register"));
8779 case '0': /* dsp 6-bit signed immediate in bit 20 */
8780 my_getExpression (&imm_expr
, s
);
8781 check_absolute_expr (ip
, &imm_expr
);
8782 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8783 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8784 if (imm_expr
.X_add_number
< min_range
||
8785 imm_expr
.X_add_number
> max_range
)
8787 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8788 (long) min_range
, (long) max_range
,
8789 (long) imm_expr
.X_add_number
);
8791 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8792 imm_expr
.X_op
= O_absent
;
8796 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8797 my_getExpression (&imm_expr
, s
);
8798 check_absolute_expr (ip
, &imm_expr
);
8799 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8801 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8803 (unsigned long) imm_expr
.X_add_number
);
8805 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8806 imm_expr
.X_op
= O_absent
;
8810 case ':': /* dsp 7-bit signed immediate in bit 19 */
8811 my_getExpression (&imm_expr
, s
);
8812 check_absolute_expr (ip
, &imm_expr
);
8813 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8814 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8815 if (imm_expr
.X_add_number
< min_range
||
8816 imm_expr
.X_add_number
> max_range
)
8818 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8819 (long) min_range
, (long) max_range
,
8820 (long) imm_expr
.X_add_number
);
8822 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8823 imm_expr
.X_op
= O_absent
;
8827 case '@': /* dsp 10-bit signed immediate in bit 16 */
8828 my_getExpression (&imm_expr
, s
);
8829 check_absolute_expr (ip
, &imm_expr
);
8830 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8831 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8832 if (imm_expr
.X_add_number
< min_range
||
8833 imm_expr
.X_add_number
> max_range
)
8835 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8836 (long) min_range
, (long) max_range
,
8837 (long) imm_expr
.X_add_number
);
8839 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8840 imm_expr
.X_op
= O_absent
;
8844 case '!': /* MT usermode flag bit. */
8845 my_getExpression (&imm_expr
, s
);
8846 check_absolute_expr (ip
, &imm_expr
);
8847 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8848 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8849 (unsigned long) imm_expr
.X_add_number
);
8850 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8851 imm_expr
.X_op
= O_absent
;
8855 case '$': /* MT load high flag bit. */
8856 my_getExpression (&imm_expr
, s
);
8857 check_absolute_expr (ip
, &imm_expr
);
8858 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8859 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8860 (unsigned long) imm_expr
.X_add_number
);
8861 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8862 imm_expr
.X_op
= O_absent
;
8866 case '*': /* four dsp accumulators in bits 18,19 */
8867 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8868 s
[3] >= '0' && s
[3] <= '3')
8872 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8876 as_bad (_("Invalid dsp/smartmips acc register"));
8879 case '&': /* four dsp accumulators in bits 13,14 */
8880 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8881 s
[3] >= '0' && s
[3] <= '3')
8885 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8889 as_bad (_("Invalid dsp/smartmips acc register"));
8901 INSERT_OPERAND (RS
, *ip
, lastregno
);
8905 INSERT_OPERAND (RT
, *ip
, lastregno
);
8909 INSERT_OPERAND (FT
, *ip
, lastregno
);
8913 INSERT_OPERAND (FS
, *ip
, lastregno
);
8919 /* Handle optional base register.
8920 Either the base register is omitted or
8921 we must have a left paren. */
8922 /* This is dependent on the next operand specifier
8923 is a base register specification. */
8924 assert (args
[1] == 'b' || args
[1] == '5'
8925 || args
[1] == '-' || args
[1] == '4');
8929 case ')': /* these must match exactly */
8936 case '+': /* Opcode extension character. */
8939 case '1': /* UDI immediates. */
8944 const struct mips_immed
*imm
= mips_immed
;
8946 while (imm
->type
&& imm
->type
!= *args
)
8950 my_getExpression (&imm_expr
, s
);
8951 check_absolute_expr (ip
, &imm_expr
);
8952 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8954 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8955 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8956 (unsigned long) imm_expr
.X_add_number
,
8957 (unsigned long) imm_expr
.X_add_number
);
8958 imm_expr
.X_add_number
&= imm
->mask
;
8960 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8962 imm_expr
.X_op
= O_absent
;
8967 case 'A': /* ins/ext position, becomes LSB. */
8976 my_getExpression (&imm_expr
, s
);
8977 check_absolute_expr (ip
, &imm_expr
);
8978 if ((unsigned long) imm_expr
.X_add_number
< limlo
8979 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8981 as_bad (_("Improper position (%lu)"),
8982 (unsigned long) imm_expr
.X_add_number
);
8983 imm_expr
.X_add_number
= limlo
;
8985 lastpos
= imm_expr
.X_add_number
;
8986 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8987 imm_expr
.X_op
= O_absent
;
8991 case 'B': /* ins size, becomes MSB. */
9000 my_getExpression (&imm_expr
, s
);
9001 check_absolute_expr (ip
, &imm_expr
);
9002 /* Check for negative input so that small negative numbers
9003 will not succeed incorrectly. The checks against
9004 (pos+size) transitively check "size" itself,
9005 assuming that "pos" is reasonable. */
9006 if ((long) imm_expr
.X_add_number
< 0
9007 || ((unsigned long) imm_expr
.X_add_number
9009 || ((unsigned long) imm_expr
.X_add_number
9012 as_bad (_("Improper insert size (%lu, position %lu)"),
9013 (unsigned long) imm_expr
.X_add_number
,
9014 (unsigned long) lastpos
);
9015 imm_expr
.X_add_number
= limlo
- lastpos
;
9017 INSERT_OPERAND (INSMSB
, *ip
,
9018 lastpos
+ imm_expr
.X_add_number
- 1);
9019 imm_expr
.X_op
= O_absent
;
9023 case 'C': /* ext size, becomes MSBD. */
9036 my_getExpression (&imm_expr
, s
);
9037 check_absolute_expr (ip
, &imm_expr
);
9038 /* Check for negative input so that small negative numbers
9039 will not succeed incorrectly. The checks against
9040 (pos+size) transitively check "size" itself,
9041 assuming that "pos" is reasonable. */
9042 if ((long) imm_expr
.X_add_number
< 0
9043 || ((unsigned long) imm_expr
.X_add_number
9045 || ((unsigned long) imm_expr
.X_add_number
9048 as_bad (_("Improper extract size (%lu, position %lu)"),
9049 (unsigned long) imm_expr
.X_add_number
,
9050 (unsigned long) lastpos
);
9051 imm_expr
.X_add_number
= limlo
- lastpos
;
9053 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9054 imm_expr
.X_op
= O_absent
;
9059 /* +D is for disassembly only; never match. */
9063 /* "+I" is like "I", except that imm2_expr is used. */
9064 my_getExpression (&imm2_expr
, s
);
9065 if (imm2_expr
.X_op
!= O_big
9066 && imm2_expr
.X_op
!= O_constant
)
9067 insn_error
= _("absolute expression required");
9068 if (HAVE_32BIT_GPRS
)
9069 normalize_constant_expr (&imm2_expr
);
9073 case 'T': /* Coprocessor register. */
9074 /* +T is for disassembly only; never match. */
9077 case 't': /* Coprocessor register number. */
9078 if (s
[0] == '$' && ISDIGIT (s
[1]))
9088 while (ISDIGIT (*s
));
9090 as_bad (_("Invalid register number (%d)"), regno
);
9093 INSERT_OPERAND (RT
, *ip
, regno
);
9098 as_bad (_("Invalid coprocessor 0 register number"));
9102 /* bbit[01] and bbit[01]32 bit index. Give error if index
9103 is not in the valid range. */
9104 my_getExpression (&imm_expr
, s
);
9105 check_absolute_expr (ip
, &imm_expr
);
9106 if ((unsigned) imm_expr
.X_add_number
> 31)
9108 as_bad (_("Improper bit index (%lu)"),
9109 (unsigned long) imm_expr
.X_add_number
);
9110 imm_expr
.X_add_number
= 0;
9112 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9113 imm_expr
.X_op
= O_absent
;
9118 /* bbit[01] bit index when bbit is used but we generate
9119 bbit[01]32 because the index is over 32. Move to the
9120 next candidate if index is not in the valid range. */
9121 my_getExpression (&imm_expr
, s
);
9122 check_absolute_expr (ip
, &imm_expr
);
9123 if ((unsigned) imm_expr
.X_add_number
< 32
9124 || (unsigned) imm_expr
.X_add_number
> 63)
9126 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9127 imm_expr
.X_op
= O_absent
;
9132 /* cins, cins32, exts and exts32 position field. Give error
9133 if it's not in the valid range. */
9134 my_getExpression (&imm_expr
, s
);
9135 check_absolute_expr (ip
, &imm_expr
);
9136 if ((unsigned) imm_expr
.X_add_number
> 31)
9138 as_bad (_("Improper position (%lu)"),
9139 (unsigned long) imm_expr
.X_add_number
);
9140 imm_expr
.X_add_number
= 0;
9142 /* Make the pos explicit to simplify +S. */
9143 lastpos
= imm_expr
.X_add_number
+ 32;
9144 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9145 imm_expr
.X_op
= O_absent
;
9150 /* cins, cins32, exts and exts32 position field. Move to
9151 the next candidate if it's not in the valid range. */
9152 my_getExpression (&imm_expr
, s
);
9153 check_absolute_expr (ip
, &imm_expr
);
9154 if ((unsigned) imm_expr
.X_add_number
< 32
9155 || (unsigned) imm_expr
.X_add_number
> 63)
9157 lastpos
= imm_expr
.X_add_number
;
9158 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9159 imm_expr
.X_op
= O_absent
;
9164 /* cins and exts length-minus-one field. */
9165 my_getExpression (&imm_expr
, s
);
9166 check_absolute_expr (ip
, &imm_expr
);
9167 if ((unsigned long) imm_expr
.X_add_number
> 31)
9169 as_bad (_("Improper size (%lu)"),
9170 (unsigned long) imm_expr
.X_add_number
);
9171 imm_expr
.X_add_number
= 0;
9173 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9174 imm_expr
.X_op
= O_absent
;
9179 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9180 length-minus-one field. */
9181 my_getExpression (&imm_expr
, s
);
9182 check_absolute_expr (ip
, &imm_expr
);
9183 if ((long) imm_expr
.X_add_number
< 0
9184 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9186 as_bad (_("Improper size (%lu)"),
9187 (unsigned long) imm_expr
.X_add_number
);
9188 imm_expr
.X_add_number
= 0;
9190 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9191 imm_expr
.X_op
= O_absent
;
9196 /* seqi/snei immediate field. */
9197 my_getExpression (&imm_expr
, s
);
9198 check_absolute_expr (ip
, &imm_expr
);
9199 if ((long) imm_expr
.X_add_number
< -512
9200 || (long) imm_expr
.X_add_number
>= 512)
9202 as_bad (_("Improper immediate (%ld)"),
9203 (long) imm_expr
.X_add_number
);
9204 imm_expr
.X_add_number
= 0;
9206 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9207 imm_expr
.X_op
= O_absent
;
9212 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9213 *args
, insn
->name
, insn
->args
);
9214 /* Further processing is fruitless. */
9219 case '<': /* must be at least one digit */
9221 * According to the manual, if the shift amount is greater
9222 * than 31 or less than 0, then the shift amount should be
9223 * mod 32. In reality the mips assembler issues an error.
9224 * We issue a warning and mask out all but the low 5 bits.
9226 my_getExpression (&imm_expr
, s
);
9227 check_absolute_expr (ip
, &imm_expr
);
9228 if ((unsigned long) imm_expr
.X_add_number
> 31)
9229 as_warn (_("Improper shift amount (%lu)"),
9230 (unsigned long) imm_expr
.X_add_number
);
9231 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9232 imm_expr
.X_op
= O_absent
;
9236 case '>': /* shift amount minus 32 */
9237 my_getExpression (&imm_expr
, s
);
9238 check_absolute_expr (ip
, &imm_expr
);
9239 if ((unsigned long) imm_expr
.X_add_number
< 32
9240 || (unsigned long) imm_expr
.X_add_number
> 63)
9242 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9243 imm_expr
.X_op
= O_absent
;
9247 case 'k': /* cache code */
9248 case 'h': /* prefx code */
9249 case '1': /* sync type */
9250 my_getExpression (&imm_expr
, s
);
9251 check_absolute_expr (ip
, &imm_expr
);
9252 if ((unsigned long) imm_expr
.X_add_number
> 31)
9253 as_warn (_("Invalid value for `%s' (%lu)"),
9255 (unsigned long) imm_expr
.X_add_number
);
9257 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9258 else if (*args
== 'h')
9259 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9261 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9262 imm_expr
.X_op
= O_absent
;
9266 case 'c': /* break code */
9267 my_getExpression (&imm_expr
, s
);
9268 check_absolute_expr (ip
, &imm_expr
);
9269 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9270 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9272 (unsigned long) imm_expr
.X_add_number
);
9273 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9274 imm_expr
.X_op
= O_absent
;
9278 case 'q': /* lower break code */
9279 my_getExpression (&imm_expr
, s
);
9280 check_absolute_expr (ip
, &imm_expr
);
9281 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9282 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9284 (unsigned long) imm_expr
.X_add_number
);
9285 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9286 imm_expr
.X_op
= O_absent
;
9290 case 'B': /* 20-bit syscall/break code. */
9291 my_getExpression (&imm_expr
, s
);
9292 check_absolute_expr (ip
, &imm_expr
);
9293 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9294 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9296 (unsigned long) imm_expr
.X_add_number
);
9297 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9298 imm_expr
.X_op
= O_absent
;
9302 case 'C': /* Coprocessor code */
9303 my_getExpression (&imm_expr
, s
);
9304 check_absolute_expr (ip
, &imm_expr
);
9305 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9307 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9308 (unsigned long) imm_expr
.X_add_number
);
9309 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9311 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9312 imm_expr
.X_op
= O_absent
;
9316 case 'J': /* 19-bit wait code. */
9317 my_getExpression (&imm_expr
, s
);
9318 check_absolute_expr (ip
, &imm_expr
);
9319 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9321 as_warn (_("Illegal 19-bit code (%lu)"),
9322 (unsigned long) imm_expr
.X_add_number
);
9323 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9325 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9326 imm_expr
.X_op
= O_absent
;
9330 case 'P': /* Performance register. */
9331 my_getExpression (&imm_expr
, s
);
9332 check_absolute_expr (ip
, &imm_expr
);
9333 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9334 as_warn (_("Invalid performance register (%lu)"),
9335 (unsigned long) imm_expr
.X_add_number
);
9336 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9337 imm_expr
.X_op
= O_absent
;
9341 case 'G': /* Coprocessor destination register. */
9342 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9343 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9345 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9346 INSERT_OPERAND (RD
, *ip
, regno
);
9355 case 'b': /* base register */
9356 case 'd': /* destination register */
9357 case 's': /* source register */
9358 case 't': /* target register */
9359 case 'r': /* both target and source */
9360 case 'v': /* both dest and source */
9361 case 'w': /* both dest and target */
9362 case 'E': /* coprocessor target register */
9363 case 'K': /* 'rdhwr' destination register */
9364 case 'x': /* ignore register name */
9365 case 'z': /* must be zero register */
9366 case 'U': /* destination register (clo/clz). */
9367 case 'g': /* coprocessor destination register */
9369 if (*args
== 'E' || *args
== 'K')
9370 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9373 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9374 if (regno
== AT
&& mips_opts
.at
)
9376 if (mips_opts
.at
== ATREG
)
9377 as_warn (_("used $at without \".set noat\""));
9379 as_warn (_("used $%u with \".set at=$%u\""),
9380 regno
, mips_opts
.at
);
9390 if (c
== 'r' || c
== 'v' || c
== 'w')
9397 /* 'z' only matches $0. */
9398 if (c
== 'z' && regno
!= 0)
9401 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9403 if (regno
== lastregno
)
9405 insn_error
= _("source and destination must be different");
9408 if (regno
== 31 && lastregno
== 0xffffffff)
9410 insn_error
= _("a destination register must be supplied");
9414 /* Now that we have assembled one operand, we use the args string
9415 * to figure out where it goes in the instruction. */
9422 INSERT_OPERAND (RS
, *ip
, regno
);
9428 INSERT_OPERAND (RD
, *ip
, regno
);
9431 INSERT_OPERAND (RD
, *ip
, regno
);
9432 INSERT_OPERAND (RT
, *ip
, regno
);
9437 INSERT_OPERAND (RT
, *ip
, regno
);
9440 /* This case exists because on the r3000 trunc
9441 expands into a macro which requires a gp
9442 register. On the r6000 or r4000 it is
9443 assembled into a single instruction which
9444 ignores the register. Thus the insn version
9445 is MIPS_ISA2 and uses 'x', and the macro
9446 version is MIPS_ISA1 and uses 't'. */
9449 /* This case is for the div instruction, which
9450 acts differently if the destination argument
9451 is $0. This only matches $0, and is checked
9452 outside the switch. */
9455 /* Itbl operand; not yet implemented. FIXME ?? */
9457 /* What about all other operands like 'i', which
9458 can be specified in the opcode table? */
9467 INSERT_OPERAND (RS
, *ip
, lastregno
);
9470 INSERT_OPERAND (RT
, *ip
, lastregno
);
9475 case 'O': /* MDMX alignment immediate constant. */
9476 my_getExpression (&imm_expr
, s
);
9477 check_absolute_expr (ip
, &imm_expr
);
9478 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9479 as_warn ("Improper align amount (%ld), using low bits",
9480 (long) imm_expr
.X_add_number
);
9481 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9482 imm_expr
.X_op
= O_absent
;
9486 case 'Q': /* MDMX vector, element sel, or const. */
9489 /* MDMX Immediate. */
9490 my_getExpression (&imm_expr
, s
);
9491 check_absolute_expr (ip
, &imm_expr
);
9492 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9493 as_warn (_("Invalid MDMX Immediate (%ld)"),
9494 (long) imm_expr
.X_add_number
);
9495 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9496 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9497 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9499 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9500 imm_expr
.X_op
= O_absent
;
9504 /* Not MDMX Immediate. Fall through. */
9505 case 'X': /* MDMX destination register. */
9506 case 'Y': /* MDMX source register. */
9507 case 'Z': /* MDMX target register. */
9509 case 'D': /* floating point destination register */
9510 case 'S': /* floating point source register */
9511 case 'T': /* floating point target register */
9512 case 'R': /* floating point source register */
9517 || (mips_opts
.ase_mdmx
9518 && (ip
->insn_mo
->pinfo
& FP_D
)
9519 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9520 | INSN_COPROC_MEMORY_DELAY
9521 | INSN_LOAD_COPROC_DELAY
9522 | INSN_LOAD_MEMORY_DELAY
9523 | INSN_STORE_MEMORY
))))
9526 if (reg_lookup (&s
, rtype
, ®no
))
9528 if ((regno
& 1) != 0
9530 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9531 as_warn (_("Float register should be even, was %d"),
9539 if (c
== 'V' || c
== 'W')
9550 INSERT_OPERAND (FD
, *ip
, regno
);
9555 INSERT_OPERAND (FS
, *ip
, regno
);
9558 /* This is like 'Z', but also needs to fix the MDMX
9559 vector/scalar select bits. Note that the
9560 scalar immediate case is handled above. */
9563 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9564 int max_el
= (is_qh
? 3 : 7);
9566 my_getExpression(&imm_expr
, s
);
9567 check_absolute_expr (ip
, &imm_expr
);
9569 if (imm_expr
.X_add_number
> max_el
)
9570 as_bad(_("Bad element selector %ld"),
9571 (long) imm_expr
.X_add_number
);
9572 imm_expr
.X_add_number
&= max_el
;
9573 ip
->insn_opcode
|= (imm_expr
.X_add_number
9576 imm_expr
.X_op
= O_absent
;
9578 as_warn(_("Expecting ']' found '%s'"), s
);
9584 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9585 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9588 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9595 INSERT_OPERAND (FT
, *ip
, regno
);
9598 INSERT_OPERAND (FR
, *ip
, regno
);
9608 INSERT_OPERAND (FS
, *ip
, lastregno
);
9611 INSERT_OPERAND (FT
, *ip
, lastregno
);
9617 my_getExpression (&imm_expr
, s
);
9618 if (imm_expr
.X_op
!= O_big
9619 && imm_expr
.X_op
!= O_constant
)
9620 insn_error
= _("absolute expression required");
9621 if (HAVE_32BIT_GPRS
)
9622 normalize_constant_expr (&imm_expr
);
9627 my_getExpression (&offset_expr
, s
);
9628 normalize_address_expr (&offset_expr
);
9629 *imm_reloc
= BFD_RELOC_32
;
9642 unsigned char temp
[8];
9644 unsigned int length
;
9649 /* These only appear as the last operand in an
9650 instruction, and every instruction that accepts
9651 them in any variant accepts them in all variants.
9652 This means we don't have to worry about backing out
9653 any changes if the instruction does not match.
9655 The difference between them is the size of the
9656 floating point constant and where it goes. For 'F'
9657 and 'L' the constant is 64 bits; for 'f' and 'l' it
9658 is 32 bits. Where the constant is placed is based
9659 on how the MIPS assembler does things:
9662 f -- immediate value
9665 The .lit4 and .lit8 sections are only used if
9666 permitted by the -G argument.
9668 The code below needs to know whether the target register
9669 is 32 or 64 bits wide. It relies on the fact 'f' and
9670 'F' are used with GPR-based instructions and 'l' and
9671 'L' are used with FPR-based instructions. */
9673 f64
= *args
== 'F' || *args
== 'L';
9674 using_gprs
= *args
== 'F' || *args
== 'f';
9676 save_in
= input_line_pointer
;
9677 input_line_pointer
= s
;
9678 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9680 s
= input_line_pointer
;
9681 input_line_pointer
= save_in
;
9682 if (err
!= NULL
&& *err
!= '\0')
9684 as_bad (_("Bad floating point constant: %s"), err
);
9685 memset (temp
, '\0', sizeof temp
);
9686 length
= f64
? 8 : 4;
9689 assert (length
== (unsigned) (f64
? 8 : 4));
9693 && (g_switch_value
< 4
9694 || (temp
[0] == 0 && temp
[1] == 0)
9695 || (temp
[2] == 0 && temp
[3] == 0))))
9697 imm_expr
.X_op
= O_constant
;
9698 if (! target_big_endian
)
9699 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9701 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9704 && ! mips_disable_float_construction
9705 /* Constants can only be constructed in GPRs and
9706 copied to FPRs if the GPRs are at least as wide
9707 as the FPRs. Force the constant into memory if
9708 we are using 64-bit FPRs but the GPRs are only
9711 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9712 && ((temp
[0] == 0 && temp
[1] == 0)
9713 || (temp
[2] == 0 && temp
[3] == 0))
9714 && ((temp
[4] == 0 && temp
[5] == 0)
9715 || (temp
[6] == 0 && temp
[7] == 0)))
9717 /* The value is simple enough to load with a couple of
9718 instructions. If using 32-bit registers, set
9719 imm_expr to the high order 32 bits and offset_expr to
9720 the low order 32 bits. Otherwise, set imm_expr to
9721 the entire 64 bit constant. */
9722 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9724 imm_expr
.X_op
= O_constant
;
9725 offset_expr
.X_op
= O_constant
;
9726 if (! target_big_endian
)
9728 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9729 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9733 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9734 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9736 if (offset_expr
.X_add_number
== 0)
9737 offset_expr
.X_op
= O_absent
;
9739 else if (sizeof (imm_expr
.X_add_number
) > 4)
9741 imm_expr
.X_op
= O_constant
;
9742 if (! target_big_endian
)
9743 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9745 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9749 imm_expr
.X_op
= O_big
;
9750 imm_expr
.X_add_number
= 4;
9751 if (! target_big_endian
)
9753 generic_bignum
[0] = bfd_getl16 (temp
);
9754 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9755 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9756 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9760 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9761 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9762 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9763 generic_bignum
[3] = bfd_getb16 (temp
);
9769 const char *newname
;
9772 /* Switch to the right section. */
9774 subseg
= now_subseg
;
9777 default: /* unused default case avoids warnings. */
9779 newname
= RDATA_SECTION_NAME
;
9780 if (g_switch_value
>= 8)
9784 newname
= RDATA_SECTION_NAME
;
9787 assert (g_switch_value
>= 4);
9791 new_seg
= subseg_new (newname
, (subsegT
) 0);
9793 bfd_set_section_flags (stdoutput
, new_seg
,
9798 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9799 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9800 record_alignment (new_seg
, 4);
9802 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9804 as_bad (_("Can't use floating point insn in this section"));
9806 /* Set the argument to the current address in the
9808 offset_expr
.X_op
= O_symbol
;
9809 offset_expr
.X_add_symbol
=
9810 symbol_new ("L0\001", now_seg
,
9811 (valueT
) frag_now_fix (), frag_now
);
9812 offset_expr
.X_add_number
= 0;
9814 /* Put the floating point number into the section. */
9815 p
= frag_more ((int) length
);
9816 memcpy (p
, temp
, length
);
9818 /* Switch back to the original section. */
9819 subseg_set (seg
, subseg
);
9824 case 'i': /* 16 bit unsigned immediate */
9825 case 'j': /* 16 bit signed immediate */
9826 *imm_reloc
= BFD_RELOC_LO16
;
9827 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9830 offsetT minval
, maxval
;
9832 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9833 && strcmp (insn
->name
, insn
[1].name
) == 0);
9835 /* If the expression was written as an unsigned number,
9836 only treat it as signed if there are no more
9840 && sizeof (imm_expr
.X_add_number
) <= 4
9841 && imm_expr
.X_op
== O_constant
9842 && imm_expr
.X_add_number
< 0
9843 && imm_expr
.X_unsigned
9847 /* For compatibility with older assemblers, we accept
9848 0x8000-0xffff as signed 16-bit numbers when only
9849 signed numbers are allowed. */
9851 minval
= 0, maxval
= 0xffff;
9853 minval
= -0x8000, maxval
= 0x7fff;
9855 minval
= -0x8000, maxval
= 0xffff;
9857 if (imm_expr
.X_op
!= O_constant
9858 || imm_expr
.X_add_number
< minval
9859 || imm_expr
.X_add_number
> maxval
)
9863 if (imm_expr
.X_op
== O_constant
9864 || imm_expr
.X_op
== O_big
)
9865 as_bad (_("expression out of range"));
9871 case 'o': /* 16 bit offset */
9872 /* Check whether there is only a single bracketed expression
9873 left. If so, it must be the base register and the
9874 constant must be zero. */
9875 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9877 offset_expr
.X_op
= O_constant
;
9878 offset_expr
.X_add_number
= 0;
9882 /* If this value won't fit into a 16 bit offset, then go
9883 find a macro that will generate the 32 bit offset
9885 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9886 && (offset_expr
.X_op
!= O_constant
9887 || offset_expr
.X_add_number
>= 0x8000
9888 || offset_expr
.X_add_number
< -0x8000))
9894 case 'p': /* pc relative offset */
9895 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9896 my_getExpression (&offset_expr
, s
);
9900 case 'u': /* upper 16 bits */
9901 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9902 && imm_expr
.X_op
== O_constant
9903 && (imm_expr
.X_add_number
< 0
9904 || imm_expr
.X_add_number
>= 0x10000))
9905 as_bad (_("lui expression not in range 0..65535"));
9909 case 'a': /* 26 bit address */
9910 my_getExpression (&offset_expr
, s
);
9912 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9915 case 'N': /* 3 bit branch condition code */
9916 case 'M': /* 3 bit compare condition code */
9918 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9920 if (!reg_lookup (&s
, rtype
, ®no
))
9922 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9923 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9924 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9925 && (regno
& 1) != 0)
9926 as_warn(_("Condition code register should be even for %s, was %d"),
9928 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9929 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9930 && (regno
& 3) != 0)
9931 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9934 INSERT_OPERAND (BCC
, *ip
, regno
);
9936 INSERT_OPERAND (CCC
, *ip
, regno
);
9940 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9951 while (ISDIGIT (*s
));
9954 c
= 8; /* Invalid sel value. */
9957 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9958 ip
->insn_opcode
|= c
;
9962 /* Must be at least one digit. */
9963 my_getExpression (&imm_expr
, s
);
9964 check_absolute_expr (ip
, &imm_expr
);
9966 if ((unsigned long) imm_expr
.X_add_number
9967 > (unsigned long) OP_MASK_VECBYTE
)
9969 as_bad (_("bad byte vector index (%ld)"),
9970 (long) imm_expr
.X_add_number
);
9971 imm_expr
.X_add_number
= 0;
9974 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9975 imm_expr
.X_op
= O_absent
;
9980 my_getExpression (&imm_expr
, s
);
9981 check_absolute_expr (ip
, &imm_expr
);
9983 if ((unsigned long) imm_expr
.X_add_number
9984 > (unsigned long) OP_MASK_VECALIGN
)
9986 as_bad (_("bad byte vector index (%ld)"),
9987 (long) imm_expr
.X_add_number
);
9988 imm_expr
.X_add_number
= 0;
9991 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9992 imm_expr
.X_op
= O_absent
;
9997 as_bad (_("bad char = '%c'\n"), *args
);
10002 /* Args don't match. */
10003 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10004 !strcmp (insn
->name
, insn
[1].name
))
10008 insn_error
= _("illegal operands");
10012 *(--argsStart
) = save_c
;
10013 insn_error
= _("illegal operands");
10018 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10020 /* This routine assembles an instruction into its binary format when
10021 assembling for the mips16. As a side effect, it sets one of the
10022 global variables imm_reloc or offset_reloc to the type of
10023 relocation to do if one of the operands is an address expression.
10024 It also sets mips16_small and mips16_ext if the user explicitly
10025 requested a small or extended instruction. */
10028 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10032 struct mips_opcode
*insn
;
10034 unsigned int regno
;
10035 unsigned int lastregno
= 0;
10041 mips16_small
= FALSE
;
10042 mips16_ext
= FALSE
;
10044 for (s
= str
; ISLOWER (*s
); ++s
)
10056 if (s
[1] == 't' && s
[2] == ' ')
10059 mips16_small
= TRUE
;
10063 else if (s
[1] == 'e' && s
[2] == ' ')
10070 /* Fall through. */
10072 insn_error
= _("unknown opcode");
10076 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10077 mips16_small
= TRUE
;
10079 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10081 insn_error
= _("unrecognized opcode");
10090 assert (strcmp (insn
->name
, str
) == 0);
10092 ok
= is_opcode_valid_16 (insn
);
10095 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10096 && strcmp (insn
->name
, insn
[1].name
) == 0)
10105 static char buf
[100];
10107 _("opcode not supported on this processor: %s (%s)"),
10108 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10109 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10116 create_insn (ip
, insn
);
10117 imm_expr
.X_op
= O_absent
;
10118 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10119 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10120 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10121 imm2_expr
.X_op
= O_absent
;
10122 offset_expr
.X_op
= O_absent
;
10123 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10124 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10125 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10126 for (args
= insn
->args
; 1; ++args
)
10133 /* In this switch statement we call break if we did not find
10134 a match, continue if we did find a match, or return if we
10143 /* Stuff the immediate value in now, if we can. */
10144 if (imm_expr
.X_op
== O_constant
10145 && *imm_reloc
> BFD_RELOC_UNUSED
10146 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10147 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10148 && insn
->pinfo
!= INSN_MACRO
)
10152 switch (*offset_reloc
)
10154 case BFD_RELOC_MIPS16_HI16_S
:
10155 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10158 case BFD_RELOC_MIPS16_HI16
:
10159 tmp
= imm_expr
.X_add_number
>> 16;
10162 case BFD_RELOC_MIPS16_LO16
:
10163 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10167 case BFD_RELOC_UNUSED
:
10168 tmp
= imm_expr
.X_add_number
;
10174 *offset_reloc
= BFD_RELOC_UNUSED
;
10176 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10177 tmp
, TRUE
, mips16_small
,
10178 mips16_ext
, &ip
->insn_opcode
,
10179 &ip
->use_extend
, &ip
->extend
);
10180 imm_expr
.X_op
= O_absent
;
10181 *imm_reloc
= BFD_RELOC_UNUSED
;
10195 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10198 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10214 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10216 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10220 /* Fall through. */
10231 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10233 if (c
== 'v' || c
== 'w')
10236 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10238 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10249 if (c
== 'v' || c
== 'w')
10251 regno
= mips16_to_32_reg_map
[lastregno
];
10265 regno
= mips32_to_16_reg_map
[regno
];
10270 regno
= ILLEGAL_REG
;
10275 regno
= ILLEGAL_REG
;
10280 regno
= ILLEGAL_REG
;
10285 if (regno
== AT
&& mips_opts
.at
)
10287 if (mips_opts
.at
== ATREG
)
10288 as_warn (_("used $at without \".set noat\""));
10290 as_warn (_("used $%u with \".set at=$%u\""),
10291 regno
, mips_opts
.at
);
10299 if (regno
== ILLEGAL_REG
)
10306 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10310 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10313 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10316 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10322 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10325 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10326 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10336 if (strncmp (s
, "$pc", 3) == 0)
10353 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10356 if (imm_expr
.X_op
!= O_constant
)
10359 ip
->use_extend
= TRUE
;
10364 /* We need to relax this instruction. */
10365 *offset_reloc
= *imm_reloc
;
10366 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10371 *imm_reloc
= BFD_RELOC_UNUSED
;
10372 /* Fall through. */
10379 my_getExpression (&imm_expr
, s
);
10380 if (imm_expr
.X_op
== O_register
)
10382 /* What we thought was an expression turned out to
10385 if (s
[0] == '(' && args
[1] == '(')
10387 /* It looks like the expression was omitted
10388 before a register indirection, which means
10389 that the expression is implicitly zero. We
10390 still set up imm_expr, so that we handle
10391 explicit extensions correctly. */
10392 imm_expr
.X_op
= O_constant
;
10393 imm_expr
.X_add_number
= 0;
10394 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10401 /* We need to relax this instruction. */
10402 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10411 /* We use offset_reloc rather than imm_reloc for the PC
10412 relative operands. This lets macros with both
10413 immediate and address operands work correctly. */
10414 my_getExpression (&offset_expr
, s
);
10416 if (offset_expr
.X_op
== O_register
)
10419 /* We need to relax this instruction. */
10420 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10424 case '6': /* break code */
10425 my_getExpression (&imm_expr
, s
);
10426 check_absolute_expr (ip
, &imm_expr
);
10427 if ((unsigned long) imm_expr
.X_add_number
> 63)
10428 as_warn (_("Invalid value for `%s' (%lu)"),
10430 (unsigned long) imm_expr
.X_add_number
);
10431 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10432 imm_expr
.X_op
= O_absent
;
10436 case 'a': /* 26 bit address */
10437 my_getExpression (&offset_expr
, s
);
10439 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10440 ip
->insn_opcode
<<= 16;
10443 case 'l': /* register list for entry macro */
10444 case 'L': /* register list for exit macro */
10454 unsigned int freg
, reg1
, reg2
;
10456 while (*s
== ' ' || *s
== ',')
10458 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10460 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10464 as_bad (_("can't parse register list"));
10474 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10475 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10477 as_bad (_("invalid register list"));
10481 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10483 mask
&= ~ (7 << 3);
10486 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10488 mask
&= ~ (7 << 3);
10491 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10492 mask
|= (reg2
- 3) << 3;
10493 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10494 mask
|= (reg2
- 15) << 1;
10495 else if (reg1
== RA
&& reg2
== RA
)
10499 as_bad (_("invalid register list"));
10503 /* The mask is filled in in the opcode table for the
10504 benefit of the disassembler. We remove it before
10505 applying the actual mask. */
10506 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10507 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10511 case 'm': /* Register list for save insn. */
10512 case 'M': /* Register list for restore insn. */
10515 int framesz
= 0, seen_framesz
= 0;
10516 int args
= 0, statics
= 0, sregs
= 0;
10520 unsigned int reg1
, reg2
;
10522 SKIP_SPACE_TABS (s
);
10525 SKIP_SPACE_TABS (s
);
10527 my_getExpression (&imm_expr
, s
);
10528 if (imm_expr
.X_op
== O_constant
)
10530 /* Handle the frame size. */
10533 as_bad (_("more than one frame size in list"));
10537 framesz
= imm_expr
.X_add_number
;
10538 imm_expr
.X_op
= O_absent
;
10543 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10545 as_bad (_("can't parse register list"));
10557 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10560 as_bad (_("can't parse register list"));
10565 while (reg1
<= reg2
)
10567 if (reg1
>= 4 && reg1
<= 7)
10571 args
|= 1 << (reg1
- 4);
10573 /* statics $a0-$a3 */
10574 statics
|= 1 << (reg1
- 4);
10576 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10579 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10581 else if (reg1
== 31)
10583 /* Add $ra to insn. */
10588 as_bad (_("unexpected register in list"));
10596 /* Encode args/statics combination. */
10597 if (args
& statics
)
10598 as_bad (_("arg/static registers overlap"));
10599 else if (args
== 0xf)
10600 /* All $a0-$a3 are args. */
10601 opcode
|= MIPS16_ALL_ARGS
<< 16;
10602 else if (statics
== 0xf)
10603 /* All $a0-$a3 are statics. */
10604 opcode
|= MIPS16_ALL_STATICS
<< 16;
10607 int narg
= 0, nstat
= 0;
10609 /* Count arg registers. */
10616 as_bad (_("invalid arg register list"));
10618 /* Count static registers. */
10619 while (statics
& 0x8)
10621 statics
= (statics
<< 1) & 0xf;
10625 as_bad (_("invalid static register list"));
10627 /* Encode args/statics. */
10628 opcode
|= ((narg
<< 2) | nstat
) << 16;
10631 /* Encode $s0/$s1. */
10632 if (sregs
& (1 << 0)) /* $s0 */
10634 if (sregs
& (1 << 1)) /* $s1 */
10640 /* Count regs $s2-$s8. */
10648 as_bad (_("invalid static register list"));
10649 /* Encode $s2-$s8. */
10650 opcode
|= nsreg
<< 24;
10653 /* Encode frame size. */
10655 as_bad (_("missing frame size"));
10656 else if ((framesz
& 7) != 0 || framesz
< 0
10657 || framesz
> 0xff * 8)
10658 as_bad (_("invalid frame size"));
10659 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10662 opcode
|= (((framesz
& 0xf0) << 16)
10663 | (framesz
& 0x0f));
10666 /* Finally build the instruction. */
10667 if ((opcode
>> 16) != 0 || framesz
== 0)
10669 ip
->use_extend
= TRUE
;
10670 ip
->extend
= opcode
>> 16;
10672 ip
->insn_opcode
|= opcode
& 0x7f;
10676 case 'e': /* extend code */
10677 my_getExpression (&imm_expr
, s
);
10678 check_absolute_expr (ip
, &imm_expr
);
10679 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10681 as_warn (_("Invalid value for `%s' (%lu)"),
10683 (unsigned long) imm_expr
.X_add_number
);
10684 imm_expr
.X_add_number
&= 0x7ff;
10686 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10687 imm_expr
.X_op
= O_absent
;
10697 /* Args don't match. */
10698 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10699 strcmp (insn
->name
, insn
[1].name
) == 0)
10706 insn_error
= _("illegal operands");
10712 /* This structure holds information we know about a mips16 immediate
10715 struct mips16_immed_operand
10717 /* The type code used in the argument string in the opcode table. */
10719 /* The number of bits in the short form of the opcode. */
10721 /* The number of bits in the extended form of the opcode. */
10723 /* The amount by which the short form is shifted when it is used;
10724 for example, the sw instruction has a shift count of 2. */
10726 /* The amount by which the short form is shifted when it is stored
10727 into the instruction code. */
10729 /* Non-zero if the short form is unsigned. */
10731 /* Non-zero if the extended form is unsigned. */
10733 /* Non-zero if the value is PC relative. */
10737 /* The mips16 immediate operand types. */
10739 static const struct mips16_immed_operand mips16_immed_operands
[] =
10741 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10742 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10743 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10744 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10745 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10746 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10747 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10748 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10749 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10750 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10751 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10752 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10753 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10754 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10755 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10756 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10757 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10758 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10759 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10760 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10761 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10764 #define MIPS16_NUM_IMMED \
10765 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10767 /* Handle a mips16 instruction with an immediate value. This or's the
10768 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10769 whether an extended value is needed; if one is needed, it sets
10770 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10771 If SMALL is true, an unextended opcode was explicitly requested.
10772 If EXT is true, an extended opcode was explicitly requested. If
10773 WARN is true, warn if EXT does not match reality. */
10776 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10777 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10778 unsigned long *insn
, bfd_boolean
*use_extend
,
10779 unsigned short *extend
)
10781 const struct mips16_immed_operand
*op
;
10782 int mintiny
, maxtiny
;
10783 bfd_boolean needext
;
10785 op
= mips16_immed_operands
;
10786 while (op
->type
!= type
)
10789 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10794 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10797 maxtiny
= 1 << op
->nbits
;
10802 maxtiny
= (1 << op
->nbits
) - 1;
10807 mintiny
= - (1 << (op
->nbits
- 1));
10808 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10811 /* Branch offsets have an implicit 0 in the lowest bit. */
10812 if (type
== 'p' || type
== 'q')
10815 if ((val
& ((1 << op
->shift
) - 1)) != 0
10816 || val
< (mintiny
<< op
->shift
)
10817 || val
> (maxtiny
<< op
->shift
))
10822 if (warn
&& ext
&& ! needext
)
10823 as_warn_where (file
, line
,
10824 _("extended operand requested but not required"));
10825 if (small
&& needext
)
10826 as_bad_where (file
, line
, _("invalid unextended operand value"));
10828 if (small
|| (! ext
&& ! needext
))
10832 *use_extend
= FALSE
;
10833 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10834 insnval
<<= op
->op_shift
;
10839 long minext
, maxext
;
10845 maxext
= (1 << op
->extbits
) - 1;
10849 minext
= - (1 << (op
->extbits
- 1));
10850 maxext
= (1 << (op
->extbits
- 1)) - 1;
10852 if (val
< minext
|| val
> maxext
)
10853 as_bad_where (file
, line
,
10854 _("operand value out of range for instruction"));
10856 *use_extend
= TRUE
;
10857 if (op
->extbits
== 16)
10859 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10862 else if (op
->extbits
== 15)
10864 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10869 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10873 *extend
= (unsigned short) extval
;
10878 struct percent_op_match
10881 bfd_reloc_code_real_type reloc
;
10884 static const struct percent_op_match mips_percent_op
[] =
10886 {"%lo", BFD_RELOC_LO16
},
10888 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10889 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10890 {"%call16", BFD_RELOC_MIPS_CALL16
},
10891 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10892 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10893 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10894 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10895 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10896 {"%got", BFD_RELOC_MIPS_GOT16
},
10897 {"%gp_rel", BFD_RELOC_GPREL16
},
10898 {"%half", BFD_RELOC_16
},
10899 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10900 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10901 {"%neg", BFD_RELOC_MIPS_SUB
},
10902 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10903 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10904 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10905 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10906 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10907 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10908 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10910 {"%hi", BFD_RELOC_HI16_S
}
10913 static const struct percent_op_match mips16_percent_op
[] =
10915 {"%lo", BFD_RELOC_MIPS16_LO16
},
10916 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10917 {"%got", BFD_RELOC_MIPS16_GOT16
},
10918 {"%call16", BFD_RELOC_MIPS16_CALL16
},
10919 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10923 /* Return true if *STR points to a relocation operator. When returning true,
10924 move *STR over the operator and store its relocation code in *RELOC.
10925 Leave both *STR and *RELOC alone when returning false. */
10928 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10930 const struct percent_op_match
*percent_op
;
10933 if (mips_opts
.mips16
)
10935 percent_op
= mips16_percent_op
;
10936 limit
= ARRAY_SIZE (mips16_percent_op
);
10940 percent_op
= mips_percent_op
;
10941 limit
= ARRAY_SIZE (mips_percent_op
);
10944 for (i
= 0; i
< limit
; i
++)
10945 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10947 int len
= strlen (percent_op
[i
].str
);
10949 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10952 *str
+= strlen (percent_op
[i
].str
);
10953 *reloc
= percent_op
[i
].reloc
;
10955 /* Check whether the output BFD supports this relocation.
10956 If not, issue an error and fall back on something safe. */
10957 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10959 as_bad ("relocation %s isn't supported by the current ABI",
10960 percent_op
[i
].str
);
10961 *reloc
= BFD_RELOC_UNUSED
;
10969 /* Parse string STR as a 16-bit relocatable operand. Store the
10970 expression in *EP and the relocations in the array starting
10971 at RELOC. Return the number of relocation operators used.
10973 On exit, EXPR_END points to the first character after the expression. */
10976 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10979 bfd_reloc_code_real_type reversed_reloc
[3];
10980 size_t reloc_index
, i
;
10981 int crux_depth
, str_depth
;
10984 /* Search for the start of the main expression, recoding relocations
10985 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10986 of the main expression and with CRUX_DEPTH containing the number
10987 of open brackets at that point. */
10994 crux_depth
= str_depth
;
10996 /* Skip over whitespace and brackets, keeping count of the number
10998 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11003 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11004 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11006 my_getExpression (ep
, crux
);
11009 /* Match every open bracket. */
11010 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11014 if (crux_depth
> 0)
11015 as_bad ("unclosed '('");
11019 if (reloc_index
!= 0)
11021 prev_reloc_op_frag
= frag_now
;
11022 for (i
= 0; i
< reloc_index
; i
++)
11023 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11026 return reloc_index
;
11030 my_getExpression (expressionS
*ep
, char *str
)
11035 save_in
= input_line_pointer
;
11036 input_line_pointer
= str
;
11038 expr_end
= input_line_pointer
;
11039 input_line_pointer
= save_in
;
11041 /* If we are in mips16 mode, and this is an expression based on `.',
11042 then we bump the value of the symbol by 1 since that is how other
11043 text symbols are handled. We don't bother to handle complex
11044 expressions, just `.' plus or minus a constant. */
11045 if (mips_opts
.mips16
11046 && ep
->X_op
== O_symbol
11047 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
11048 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
11049 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
11050 && symbol_constant_p (ep
->X_add_symbol
)
11051 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
11052 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
11056 md_atof (int type
, char *litP
, int *sizeP
)
11058 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11062 md_number_to_chars (char *buf
, valueT val
, int n
)
11064 if (target_big_endian
)
11065 number_to_chars_bigendian (buf
, val
, n
);
11067 number_to_chars_littleendian (buf
, val
, n
);
11071 static int support_64bit_objects(void)
11073 const char **list
, **l
;
11076 list
= bfd_target_list ();
11077 for (l
= list
; *l
!= NULL
; l
++)
11079 /* This is traditional mips */
11080 if (strcmp (*l
, "elf64-tradbigmips") == 0
11081 || strcmp (*l
, "elf64-tradlittlemips") == 0)
11083 if (strcmp (*l
, "elf64-bigmips") == 0
11084 || strcmp (*l
, "elf64-littlemips") == 0)
11087 yes
= (*l
!= NULL
);
11091 #endif /* OBJ_ELF */
11093 const char *md_shortopts
= "O::g::G:";
11095 struct option md_longopts
[] =
11097 /* Options which specify architecture. */
11098 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
11099 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
11100 {"march", required_argument
, NULL
, OPTION_MARCH
},
11101 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
11102 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11103 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
11104 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11105 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11106 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
11107 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11108 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
11109 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11110 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
11111 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11112 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
11113 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11114 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
11115 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11116 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
11117 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11118 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
11119 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11120 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
11121 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11123 /* Options which specify Application Specific Extensions (ASEs). */
11124 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
11125 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
11126 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11127 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
11128 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11129 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
11130 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11131 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
11132 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11133 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
11134 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11135 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
11136 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11137 #define OPTION_DSP (OPTION_ASE_BASE + 6)
11138 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11139 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
11140 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11141 #define OPTION_MT (OPTION_ASE_BASE + 8)
11142 {"mmt", no_argument
, NULL
, OPTION_MT
},
11143 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
11144 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11145 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
11146 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11147 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
11148 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11149 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
11150 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11151 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
11152 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11154 /* Old-style architecture options. Don't add more of these. */
11155 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
11156 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
11157 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11158 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
11159 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11160 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
11161 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11162 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
11163 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11164 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
11165 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11166 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
11167 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11168 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
11169 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11170 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
11171 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11173 /* Options which enable bug fixes. */
11174 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
11175 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
11176 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11177 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
11178 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11179 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11180 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
11181 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
11182 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11183 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11184 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
11185 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
11186 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11187 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11189 /* Miscellaneous options. */
11190 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
11191 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
11192 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11193 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11194 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
11195 {"break", no_argument
, NULL
, OPTION_BREAK
},
11196 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11197 #define OPTION_EB (OPTION_MISC_BASE + 2)
11198 {"EB", no_argument
, NULL
, OPTION_EB
},
11199 #define OPTION_EL (OPTION_MISC_BASE + 3)
11200 {"EL", no_argument
, NULL
, OPTION_EL
},
11201 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
11202 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11203 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
11204 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11205 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
11206 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11207 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
11208 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11209 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
11210 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11211 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
11212 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11213 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
11214 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
11215 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11216 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11217 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
11218 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
11219 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11220 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11221 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
11222 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
11223 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11224 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11225 #define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16)
11226 #define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17)
11227 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11228 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11229 #define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18)
11230 #define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19)
11231 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11232 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11234 /* ELF-specific options. */
11236 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 20)
11237 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
11238 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11239 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11240 #define OPTION_CALL_NONPIC (OPTION_ELF_BASE + 1)
11241 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11242 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 2)
11243 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11244 #define OPTION_XGOT (OPTION_ELF_BASE + 3)
11245 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11246 #define OPTION_MABI (OPTION_ELF_BASE + 4)
11247 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11248 #define OPTION_32 (OPTION_ELF_BASE + 5)
11249 {"32", no_argument
, NULL
, OPTION_32
},
11250 #define OPTION_N32 (OPTION_ELF_BASE + 6)
11251 {"n32", no_argument
, NULL
, OPTION_N32
},
11252 #define OPTION_64 (OPTION_ELF_BASE + 7)
11253 {"64", no_argument
, NULL
, OPTION_64
},
11254 #define OPTION_MDEBUG (OPTION_ELF_BASE + 8)
11255 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11256 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 9)
11257 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11258 #define OPTION_PDR (OPTION_ELF_BASE + 10)
11259 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11260 #define OPTION_NO_PDR (OPTION_ELF_BASE + 11)
11261 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11262 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 12)
11263 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11264 #endif /* OBJ_ELF */
11266 {NULL
, no_argument
, NULL
, 0}
11268 size_t md_longopts_size
= sizeof (md_longopts
);
11270 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11271 NEW_VALUE. Warn if another value was already specified. Note:
11272 we have to defer parsing the -march and -mtune arguments in order
11273 to handle 'from-abi' correctly, since the ABI might be specified
11274 in a later argument. */
11277 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11279 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11280 as_warn (_("A different %s was already specified, is now %s"),
11281 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11284 *string_ptr
= new_value
;
11288 md_parse_option (int c
, char *arg
)
11292 case OPTION_CONSTRUCT_FLOATS
:
11293 mips_disable_float_construction
= 0;
11296 case OPTION_NO_CONSTRUCT_FLOATS
:
11297 mips_disable_float_construction
= 1;
11309 target_big_endian
= 1;
11313 target_big_endian
= 0;
11319 else if (arg
[0] == '0')
11321 else if (arg
[0] == '1')
11331 mips_debug
= atoi (arg
);
11335 file_mips_isa
= ISA_MIPS1
;
11339 file_mips_isa
= ISA_MIPS2
;
11343 file_mips_isa
= ISA_MIPS3
;
11347 file_mips_isa
= ISA_MIPS4
;
11351 file_mips_isa
= ISA_MIPS5
;
11354 case OPTION_MIPS32
:
11355 file_mips_isa
= ISA_MIPS32
;
11358 case OPTION_MIPS32R2
:
11359 file_mips_isa
= ISA_MIPS32R2
;
11362 case OPTION_MIPS64R2
:
11363 file_mips_isa
= ISA_MIPS64R2
;
11366 case OPTION_MIPS64
:
11367 file_mips_isa
= ISA_MIPS64
;
11371 mips_set_option_string (&mips_tune_string
, arg
);
11375 mips_set_option_string (&mips_arch_string
, arg
);
11379 mips_set_option_string (&mips_arch_string
, "4650");
11380 mips_set_option_string (&mips_tune_string
, "4650");
11383 case OPTION_NO_M4650
:
11387 mips_set_option_string (&mips_arch_string
, "4010");
11388 mips_set_option_string (&mips_tune_string
, "4010");
11391 case OPTION_NO_M4010
:
11395 mips_set_option_string (&mips_arch_string
, "4100");
11396 mips_set_option_string (&mips_tune_string
, "4100");
11399 case OPTION_NO_M4100
:
11403 mips_set_option_string (&mips_arch_string
, "3900");
11404 mips_set_option_string (&mips_tune_string
, "3900");
11407 case OPTION_NO_M3900
:
11411 mips_opts
.ase_mdmx
= 1;
11414 case OPTION_NO_MDMX
:
11415 mips_opts
.ase_mdmx
= 0;
11419 mips_opts
.ase_dsp
= 1;
11420 mips_opts
.ase_dspr2
= 0;
11423 case OPTION_NO_DSP
:
11424 mips_opts
.ase_dsp
= 0;
11425 mips_opts
.ase_dspr2
= 0;
11429 mips_opts
.ase_dspr2
= 1;
11430 mips_opts
.ase_dsp
= 1;
11433 case OPTION_NO_DSPR2
:
11434 mips_opts
.ase_dspr2
= 0;
11435 mips_opts
.ase_dsp
= 0;
11439 mips_opts
.ase_mt
= 1;
11443 mips_opts
.ase_mt
= 0;
11446 case OPTION_MIPS16
:
11447 mips_opts
.mips16
= 1;
11448 mips_no_prev_insn ();
11451 case OPTION_NO_MIPS16
:
11452 mips_opts
.mips16
= 0;
11453 mips_no_prev_insn ();
11456 case OPTION_MIPS3D
:
11457 mips_opts
.ase_mips3d
= 1;
11460 case OPTION_NO_MIPS3D
:
11461 mips_opts
.ase_mips3d
= 0;
11464 case OPTION_SMARTMIPS
:
11465 mips_opts
.ase_smartmips
= 1;
11468 case OPTION_NO_SMARTMIPS
:
11469 mips_opts
.ase_smartmips
= 0;
11472 case OPTION_FIX_VR4120
:
11473 mips_fix_vr4120
= 1;
11476 case OPTION_NO_FIX_VR4120
:
11477 mips_fix_vr4120
= 0;
11480 case OPTION_FIX_VR4130
:
11481 mips_fix_vr4130
= 1;
11484 case OPTION_NO_FIX_VR4130
:
11485 mips_fix_vr4130
= 0;
11488 case OPTION_RELAX_BRANCH
:
11489 mips_relax_branch
= 1;
11492 case OPTION_NO_RELAX_BRANCH
:
11493 mips_relax_branch
= 0;
11496 case OPTION_MSHARED
:
11497 mips_in_shared
= TRUE
;
11500 case OPTION_MNO_SHARED
:
11501 mips_in_shared
= FALSE
;
11504 case OPTION_MSYM32
:
11505 mips_opts
.sym32
= TRUE
;
11508 case OPTION_MNO_SYM32
:
11509 mips_opts
.sym32
= FALSE
;
11513 /* When generating ELF code, we permit -KPIC and -call_shared to
11514 select SVR4_PIC, and -non_shared to select no PIC. This is
11515 intended to be compatible with Irix 5. */
11516 case OPTION_CALL_SHARED
:
11519 as_bad (_("-call_shared is supported only for ELF format"));
11522 mips_pic
= SVR4_PIC
;
11523 mips_abicalls
= TRUE
;
11526 case OPTION_CALL_NONPIC
:
11529 as_bad (_("-call_nonpic is supported only for ELF format"));
11533 mips_abicalls
= TRUE
;
11536 case OPTION_NON_SHARED
:
11539 as_bad (_("-non_shared is supported only for ELF format"));
11543 mips_abicalls
= FALSE
;
11546 /* The -xgot option tells the assembler to use 32 bit offsets
11547 when accessing the got in SVR4_PIC mode. It is for Irix
11552 #endif /* OBJ_ELF */
11555 g_switch_value
= atoi (arg
);
11560 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11565 as_bad (_("-32 is supported for ELF format only"));
11568 mips_abi
= O32_ABI
;
11574 as_bad (_("-n32 is supported for ELF format only"));
11577 mips_abi
= N32_ABI
;
11583 as_bad (_("-64 is supported for ELF format only"));
11586 mips_abi
= N64_ABI
;
11587 if (!support_64bit_objects())
11588 as_fatal (_("No compiled in support for 64 bit object file format"));
11590 #endif /* OBJ_ELF */
11593 file_mips_gp32
= 1;
11597 file_mips_gp32
= 0;
11601 file_mips_fp32
= 1;
11605 file_mips_fp32
= 0;
11608 case OPTION_SINGLE_FLOAT
:
11609 file_mips_single_float
= 1;
11612 case OPTION_DOUBLE_FLOAT
:
11613 file_mips_single_float
= 0;
11616 case OPTION_SOFT_FLOAT
:
11617 file_mips_soft_float
= 1;
11620 case OPTION_HARD_FLOAT
:
11621 file_mips_soft_float
= 0;
11628 as_bad (_("-mabi is supported for ELF format only"));
11631 if (strcmp (arg
, "32") == 0)
11632 mips_abi
= O32_ABI
;
11633 else if (strcmp (arg
, "o64") == 0)
11634 mips_abi
= O64_ABI
;
11635 else if (strcmp (arg
, "n32") == 0)
11636 mips_abi
= N32_ABI
;
11637 else if (strcmp (arg
, "64") == 0)
11639 mips_abi
= N64_ABI
;
11640 if (! support_64bit_objects())
11641 as_fatal (_("No compiled in support for 64 bit object file "
11644 else if (strcmp (arg
, "eabi") == 0)
11645 mips_abi
= EABI_ABI
;
11648 as_fatal (_("invalid abi -mabi=%s"), arg
);
11652 #endif /* OBJ_ELF */
11654 case OPTION_M7000_HILO_FIX
:
11655 mips_7000_hilo_fix
= TRUE
;
11658 case OPTION_MNO_7000_HILO_FIX
:
11659 mips_7000_hilo_fix
= FALSE
;
11663 case OPTION_MDEBUG
:
11664 mips_flag_mdebug
= TRUE
;
11667 case OPTION_NO_MDEBUG
:
11668 mips_flag_mdebug
= FALSE
;
11672 mips_flag_pdr
= TRUE
;
11675 case OPTION_NO_PDR
:
11676 mips_flag_pdr
= FALSE
;
11679 case OPTION_MVXWORKS_PIC
:
11680 mips_pic
= VXWORKS_PIC
;
11682 #endif /* OBJ_ELF */
11691 /* Set up globals to generate code for the ISA or processor
11692 described by INFO. */
11695 mips_set_architecture (const struct mips_cpu_info
*info
)
11699 file_mips_arch
= info
->cpu
;
11700 mips_opts
.arch
= info
->cpu
;
11701 mips_opts
.isa
= info
->isa
;
11706 /* Likewise for tuning. */
11709 mips_set_tune (const struct mips_cpu_info
*info
)
11712 mips_tune
= info
->cpu
;
11717 mips_after_parse_args (void)
11719 const struct mips_cpu_info
*arch_info
= 0;
11720 const struct mips_cpu_info
*tune_info
= 0;
11722 /* GP relative stuff not working for PE */
11723 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11725 if (g_switch_seen
&& g_switch_value
!= 0)
11726 as_bad (_("-G not supported in this configuration."));
11727 g_switch_value
= 0;
11730 if (mips_abi
== NO_ABI
)
11731 mips_abi
= MIPS_DEFAULT_ABI
;
11733 /* The following code determines the architecture and register size.
11734 Similar code was added to GCC 3.3 (see override_options() in
11735 config/mips/mips.c). The GAS and GCC code should be kept in sync
11736 as much as possible. */
11738 if (mips_arch_string
!= 0)
11739 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11741 if (file_mips_isa
!= ISA_UNKNOWN
)
11743 /* Handle -mipsN. At this point, file_mips_isa contains the
11744 ISA level specified by -mipsN, while arch_info->isa contains
11745 the -march selection (if any). */
11746 if (arch_info
!= 0)
11748 /* -march takes precedence over -mipsN, since it is more descriptive.
11749 There's no harm in specifying both as long as the ISA levels
11751 if (file_mips_isa
!= arch_info
->isa
)
11752 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11753 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11754 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11757 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11760 if (arch_info
== 0)
11761 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11763 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11764 as_bad ("-march=%s is not compatible with the selected ABI",
11767 mips_set_architecture (arch_info
);
11769 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11770 if (mips_tune_string
!= 0)
11771 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11773 if (tune_info
== 0)
11774 mips_set_tune (arch_info
);
11776 mips_set_tune (tune_info
);
11778 if (file_mips_gp32
>= 0)
11780 /* The user specified the size of the integer registers. Make sure
11781 it agrees with the ABI and ISA. */
11782 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11783 as_bad (_("-mgp64 used with a 32-bit processor"));
11784 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11785 as_bad (_("-mgp32 used with a 64-bit ABI"));
11786 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11787 as_bad (_("-mgp64 used with a 32-bit ABI"));
11791 /* Infer the integer register size from the ABI and processor.
11792 Restrict ourselves to 32-bit registers if that's all the
11793 processor has, or if the ABI cannot handle 64-bit registers. */
11794 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11795 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11798 switch (file_mips_fp32
)
11802 /* No user specified float register size.
11803 ??? GAS treats single-float processors as though they had 64-bit
11804 float registers (although it complains when double-precision
11805 instructions are used). As things stand, saying they have 32-bit
11806 registers would lead to spurious "register must be even" messages.
11807 So here we assume float registers are never smaller than the
11809 if (file_mips_gp32
== 0)
11810 /* 64-bit integer registers implies 64-bit float registers. */
11811 file_mips_fp32
= 0;
11812 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11813 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11814 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11815 file_mips_fp32
= 0;
11817 /* 32-bit float registers. */
11818 file_mips_fp32
= 1;
11821 /* The user specified the size of the float registers. Check if it
11822 agrees with the ABI and ISA. */
11824 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11825 as_bad (_("-mfp64 used with a 32-bit fpu"));
11826 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11827 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11828 as_warn (_("-mfp64 used with a 32-bit ABI"));
11831 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11832 as_warn (_("-mfp32 used with a 64-bit ABI"));
11836 /* End of GCC-shared inference code. */
11838 /* This flag is set when we have a 64-bit capable CPU but use only
11839 32-bit wide registers. Note that EABI does not use it. */
11840 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11841 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11842 || mips_abi
== O32_ABI
))
11843 mips_32bitmode
= 1;
11845 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11846 as_bad (_("trap exception not supported at ISA 1"));
11848 /* If the selected architecture includes support for ASEs, enable
11849 generation of code for them. */
11850 if (mips_opts
.mips16
== -1)
11851 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11852 if (mips_opts
.ase_mips3d
== -1)
11853 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11854 && file_mips_fp32
== 0) ? 1 : 0;
11855 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11856 as_bad (_("-mfp32 used with -mips3d"));
11858 if (mips_opts
.ase_mdmx
== -1)
11859 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11860 && file_mips_fp32
== 0) ? 1 : 0;
11861 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11862 as_bad (_("-mfp32 used with -mdmx"));
11864 if (mips_opts
.ase_smartmips
== -1)
11865 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11866 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11867 as_warn ("%s ISA does not support SmartMIPS",
11868 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11870 if (mips_opts
.ase_dsp
== -1)
11871 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11872 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11873 as_warn ("%s ISA does not support DSP ASE",
11874 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11876 if (mips_opts
.ase_dspr2
== -1)
11878 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11879 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11881 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11882 as_warn ("%s ISA does not support DSP R2 ASE",
11883 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11885 if (mips_opts
.ase_mt
== -1)
11886 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11887 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11888 as_warn ("%s ISA does not support MT ASE",
11889 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11891 file_mips_isa
= mips_opts
.isa
;
11892 file_ase_mips16
= mips_opts
.mips16
;
11893 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11894 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11895 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11896 file_ase_dsp
= mips_opts
.ase_dsp
;
11897 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11898 file_ase_mt
= mips_opts
.ase_mt
;
11899 mips_opts
.gp32
= file_mips_gp32
;
11900 mips_opts
.fp32
= file_mips_fp32
;
11901 mips_opts
.soft_float
= file_mips_soft_float
;
11902 mips_opts
.single_float
= file_mips_single_float
;
11904 if (mips_flag_mdebug
< 0)
11906 #ifdef OBJ_MAYBE_ECOFF
11907 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11908 mips_flag_mdebug
= 1;
11910 #endif /* OBJ_MAYBE_ECOFF */
11911 mips_flag_mdebug
= 0;
11916 mips_init_after_args (void)
11918 /* initialize opcodes */
11919 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11920 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11924 md_pcrel_from (fixS
*fixP
)
11926 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11927 switch (fixP
->fx_r_type
)
11929 case BFD_RELOC_16_PCREL_S2
:
11930 case BFD_RELOC_MIPS_JMP
:
11931 /* Return the address of the delay slot. */
11934 /* We have no relocation type for PC relative MIPS16 instructions. */
11935 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11937 _("PC relative MIPS16 instruction references a different section"));
11942 /* This is called before the symbol table is processed. In order to
11943 work with gcc when using mips-tfile, we must keep all local labels.
11944 However, in other cases, we want to discard them. If we were
11945 called with -g, but we didn't see any debugging information, it may
11946 mean that gcc is smuggling debugging information through to
11947 mips-tfile, in which case we must generate all local labels. */
11950 mips_frob_file_before_adjust (void)
11952 #ifndef NO_ECOFF_DEBUGGING
11953 if (ECOFF_DEBUGGING
11955 && ! ecoff_debugging_seen
)
11956 flag_keep_locals
= 1;
11960 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11961 the corresponding LO16 reloc. This is called before md_apply_fix and
11962 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11963 relocation operators.
11965 For our purposes, a %lo() expression matches a %got() or %hi()
11968 (a) it refers to the same symbol; and
11969 (b) the offset applied in the %lo() expression is no lower than
11970 the offset applied in the %got() or %hi().
11972 (b) allows us to cope with code like:
11975 lh $4,%lo(foo+2)($4)
11977 ...which is legal on RELA targets, and has a well-defined behaviour
11978 if the user knows that adding 2 to "foo" will not induce a carry to
11981 When several %lo()s match a particular %got() or %hi(), we use the
11982 following rules to distinguish them:
11984 (1) %lo()s with smaller offsets are a better match than %lo()s with
11987 (2) %lo()s with no matching %got() or %hi() are better than those
11988 that already have a matching %got() or %hi().
11990 (3) later %lo()s are better than earlier %lo()s.
11992 These rules are applied in order.
11994 (1) means, among other things, that %lo()s with identical offsets are
11995 chosen if they exist.
11997 (2) means that we won't associate several high-part relocations with
11998 the same low-part relocation unless there's no alternative. Having
11999 several high parts for the same low part is a GNU extension; this rule
12000 allows careful users to avoid it.
12002 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12003 with the last high-part relocation being at the front of the list.
12004 It therefore makes sense to choose the last matching low-part
12005 relocation, all other things being equal. It's also easier
12006 to code that way. */
12009 mips_frob_file (void)
12011 struct mips_hi_fixup
*l
;
12012 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12014 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12016 segment_info_type
*seginfo
;
12017 bfd_boolean matched_lo_p
;
12018 fixS
**hi_pos
, **lo_pos
, **pos
;
12020 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12022 /* If a GOT16 relocation turns out to be against a global symbol,
12023 there isn't supposed to be a matching LO. */
12024 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12025 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12028 /* Check quickly whether the next fixup happens to be a matching %lo. */
12029 if (fixup_has_matching_lo_p (l
->fixp
))
12032 seginfo
= seg_info (l
->seg
);
12034 /* Set HI_POS to the position of this relocation in the chain.
12035 Set LO_POS to the position of the chosen low-part relocation.
12036 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12037 relocation that matches an immediately-preceding high-part
12041 matched_lo_p
= FALSE
;
12042 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12044 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12046 if (*pos
== l
->fixp
)
12049 if ((*pos
)->fx_r_type
== looking_for_rtype
12050 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
12051 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12053 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12055 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12058 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12059 && fixup_has_matching_lo_p (*pos
));
12062 /* If we found a match, remove the high-part relocation from its
12063 current position and insert it before the low-part relocation.
12064 Make the offsets match so that fixup_has_matching_lo_p()
12067 We don't warn about unmatched high-part relocations since some
12068 versions of gcc have been known to emit dead "lui ...%hi(...)"
12070 if (lo_pos
!= NULL
)
12072 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12073 if (l
->fixp
->fx_next
!= *lo_pos
)
12075 *hi_pos
= l
->fixp
->fx_next
;
12076 l
->fixp
->fx_next
= *lo_pos
;
12083 /* We may have combined relocations without symbols in the N32/N64 ABI.
12084 We have to prevent gas from dropping them. */
12087 mips_force_relocation (fixS
*fixp
)
12089 if (generic_force_reloc (fixp
))
12093 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12094 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12095 || hi16_reloc_p (fixp
->fx_r_type
)
12096 || lo16_reloc_p (fixp
->fx_r_type
)))
12102 /* Apply a fixup to the object file. */
12105 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12109 reloc_howto_type
*howto
;
12111 /* We ignore generic BFD relocations we don't know about. */
12112 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12116 assert (fixP
->fx_size
== 4
12117 || fixP
->fx_r_type
== BFD_RELOC_16
12118 || fixP
->fx_r_type
== BFD_RELOC_64
12119 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12120 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12121 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12122 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12123 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12125 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12127 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12129 /* Don't treat parts of a composite relocation as done. There are two
12132 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12133 should nevertheless be emitted if the first part is.
12135 (2) In normal usage, composite relocations are never assembly-time
12136 constants. The easiest way of dealing with the pathological
12137 exceptions is to generate a relocation against STN_UNDEF and
12138 leave everything up to the linker. */
12139 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12142 switch (fixP
->fx_r_type
)
12144 case BFD_RELOC_MIPS_TLS_GD
:
12145 case BFD_RELOC_MIPS_TLS_LDM
:
12146 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12147 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12148 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12149 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12150 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12151 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12152 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12153 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12156 case BFD_RELOC_MIPS_JMP
:
12157 case BFD_RELOC_MIPS_SHIFT5
:
12158 case BFD_RELOC_MIPS_SHIFT6
:
12159 case BFD_RELOC_MIPS_GOT_DISP
:
12160 case BFD_RELOC_MIPS_GOT_PAGE
:
12161 case BFD_RELOC_MIPS_GOT_OFST
:
12162 case BFD_RELOC_MIPS_SUB
:
12163 case BFD_RELOC_MIPS_INSERT_A
:
12164 case BFD_RELOC_MIPS_INSERT_B
:
12165 case BFD_RELOC_MIPS_DELETE
:
12166 case BFD_RELOC_MIPS_HIGHEST
:
12167 case BFD_RELOC_MIPS_HIGHER
:
12168 case BFD_RELOC_MIPS_SCN_DISP
:
12169 case BFD_RELOC_MIPS_REL16
:
12170 case BFD_RELOC_MIPS_RELGOT
:
12171 case BFD_RELOC_MIPS_JALR
:
12172 case BFD_RELOC_HI16
:
12173 case BFD_RELOC_HI16_S
:
12174 case BFD_RELOC_GPREL16
:
12175 case BFD_RELOC_MIPS_LITERAL
:
12176 case BFD_RELOC_MIPS_CALL16
:
12177 case BFD_RELOC_MIPS_GOT16
:
12178 case BFD_RELOC_GPREL32
:
12179 case BFD_RELOC_MIPS_GOT_HI16
:
12180 case BFD_RELOC_MIPS_GOT_LO16
:
12181 case BFD_RELOC_MIPS_CALL_HI16
:
12182 case BFD_RELOC_MIPS_CALL_LO16
:
12183 case BFD_RELOC_MIPS16_GPREL
:
12184 case BFD_RELOC_MIPS16_GOT16
:
12185 case BFD_RELOC_MIPS16_CALL16
:
12186 case BFD_RELOC_MIPS16_HI16
:
12187 case BFD_RELOC_MIPS16_HI16_S
:
12188 case BFD_RELOC_MIPS16_JMP
:
12189 /* Nothing needed to do. The value comes from the reloc entry. */
12193 /* This is handled like BFD_RELOC_32, but we output a sign
12194 extended value if we are only 32 bits. */
12197 if (8 <= sizeof (valueT
))
12198 md_number_to_chars ((char *) buf
, *valP
, 8);
12203 if ((*valP
& 0x80000000) != 0)
12207 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12209 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12215 case BFD_RELOC_RVA
:
12218 /* If we are deleting this reloc entry, we must fill in the
12219 value now. This can happen if we have a .word which is not
12220 resolved when it appears but is later defined. */
12222 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12225 case BFD_RELOC_LO16
:
12226 case BFD_RELOC_MIPS16_LO16
:
12227 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12228 may be safe to remove, but if so it's not obvious. */
12229 /* When handling an embedded PIC switch statement, we can wind
12230 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12233 if (*valP
+ 0x8000 > 0xffff)
12234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12235 _("relocation overflow"));
12236 if (target_big_endian
)
12238 md_number_to_chars ((char *) buf
, *valP
, 2);
12242 case BFD_RELOC_16_PCREL_S2
:
12243 if ((*valP
& 0x3) != 0)
12244 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12245 _("Branch to misaligned address (%lx)"), (long) *valP
);
12247 /* We need to save the bits in the instruction since fixup_segment()
12248 might be deleting the relocation entry (i.e., a branch within
12249 the current segment). */
12250 if (! fixP
->fx_done
)
12253 /* Update old instruction data. */
12254 if (target_big_endian
)
12255 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12257 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12259 if (*valP
+ 0x20000 <= 0x3ffff)
12261 insn
|= (*valP
>> 2) & 0xffff;
12262 md_number_to_chars ((char *) buf
, insn
, 4);
12264 else if (mips_pic
== NO_PIC
12266 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12267 && (fixP
->fx_frag
->fr_address
12268 < text_section
->vma
+ bfd_get_section_size (text_section
))
12269 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12270 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12271 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12273 /* The branch offset is too large. If this is an
12274 unconditional branch, and we are not generating PIC code,
12275 we can convert it to an absolute jump instruction. */
12276 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12277 insn
= 0x0c000000; /* jal */
12279 insn
= 0x08000000; /* j */
12280 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12282 fixP
->fx_addsy
= section_symbol (text_section
);
12283 *valP
+= md_pcrel_from (fixP
);
12284 md_number_to_chars ((char *) buf
, insn
, 4);
12288 /* If we got here, we have branch-relaxation disabled,
12289 and there's nothing we can do to fix this instruction
12290 without turning it into a longer sequence. */
12291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12292 _("Branch out of range"));
12296 case BFD_RELOC_VTABLE_INHERIT
:
12299 && !S_IS_DEFINED (fixP
->fx_addsy
)
12300 && !S_IS_WEAK (fixP
->fx_addsy
))
12301 S_SET_WEAK (fixP
->fx_addsy
);
12304 case BFD_RELOC_VTABLE_ENTRY
:
12312 /* Remember value for tc_gen_reloc. */
12313 fixP
->fx_addnumber
= *valP
;
12323 name
= input_line_pointer
;
12324 c
= get_symbol_end ();
12325 p
= (symbolS
*) symbol_find_or_make (name
);
12326 *input_line_pointer
= c
;
12330 /* Align the current frag to a given power of two. If a particular
12331 fill byte should be used, FILL points to an integer that contains
12332 that byte, otherwise FILL is null.
12334 The MIPS assembler also automatically adjusts any preceding
12338 mips_align (int to
, int *fill
, symbolS
*label
)
12340 mips_emit_delays ();
12341 mips_record_mips16_mode ();
12342 if (fill
== NULL
&& subseg_text_p (now_seg
))
12343 frag_align_code (to
, 0);
12345 frag_align (to
, fill
? *fill
: 0, 0);
12346 record_alignment (now_seg
, to
);
12349 assert (S_GET_SEGMENT (label
) == now_seg
);
12350 symbol_set_frag (label
, frag_now
);
12351 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12355 /* Align to a given power of two. .align 0 turns off the automatic
12356 alignment used by the data creating pseudo-ops. */
12359 s_align (int x ATTRIBUTE_UNUSED
)
12361 int temp
, fill_value
, *fill_ptr
;
12362 long max_alignment
= 28;
12364 /* o Note that the assembler pulls down any immediately preceding label
12365 to the aligned address.
12366 o It's not documented but auto alignment is reinstated by
12367 a .align pseudo instruction.
12368 o Note also that after auto alignment is turned off the mips assembler
12369 issues an error on attempt to assemble an improperly aligned data item.
12372 temp
= get_absolute_expression ();
12373 if (temp
> max_alignment
)
12374 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12377 as_warn (_("Alignment negative: 0 assumed."));
12380 if (*input_line_pointer
== ',')
12382 ++input_line_pointer
;
12383 fill_value
= get_absolute_expression ();
12384 fill_ptr
= &fill_value
;
12390 segment_info_type
*si
= seg_info (now_seg
);
12391 struct insn_label_list
*l
= si
->label_list
;
12392 /* Auto alignment should be switched on by next section change. */
12394 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12401 demand_empty_rest_of_line ();
12405 s_change_sec (int sec
)
12410 /* The ELF backend needs to know that we are changing sections, so
12411 that .previous works correctly. We could do something like check
12412 for an obj_section_change_hook macro, but that might be confusing
12413 as it would not be appropriate to use it in the section changing
12414 functions in read.c, since obj-elf.c intercepts those. FIXME:
12415 This should be cleaner, somehow. */
12417 obj_elf_section_change_hook ();
12420 mips_emit_delays ();
12430 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12431 demand_empty_rest_of_line ();
12435 seg
= subseg_new (RDATA_SECTION_NAME
,
12436 (subsegT
) get_absolute_expression ());
12439 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12440 | SEC_READONLY
| SEC_RELOC
12442 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12443 record_alignment (seg
, 4);
12445 demand_empty_rest_of_line ();
12449 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12452 bfd_set_section_flags (stdoutput
, seg
,
12453 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12454 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12455 record_alignment (seg
, 4);
12457 demand_empty_rest_of_line ();
12465 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12468 char *section_name
;
12473 int section_entry_size
;
12474 int section_alignment
;
12479 section_name
= input_line_pointer
;
12480 c
= get_symbol_end ();
12482 next_c
= *(input_line_pointer
+ 1);
12484 /* Do we have .section Name<,"flags">? */
12485 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12487 /* just after name is now '\0'. */
12488 *input_line_pointer
= c
;
12489 input_line_pointer
= section_name
;
12490 obj_elf_section (ignore
);
12493 input_line_pointer
++;
12495 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12497 section_type
= get_absolute_expression ();
12500 if (*input_line_pointer
++ == ',')
12501 section_flag
= get_absolute_expression ();
12504 if (*input_line_pointer
++ == ',')
12505 section_entry_size
= get_absolute_expression ();
12507 section_entry_size
= 0;
12508 if (*input_line_pointer
++ == ',')
12509 section_alignment
= get_absolute_expression ();
12511 section_alignment
= 0;
12513 section_name
= xstrdup (section_name
);
12515 /* When using the generic form of .section (as implemented by obj-elf.c),
12516 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12517 traditionally had to fall back on the more common @progbits instead.
12519 There's nothing really harmful in this, since bfd will correct
12520 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12521 means that, for backwards compatibility, the special_section entries
12522 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12524 Even so, we shouldn't force users of the MIPS .section syntax to
12525 incorrectly label the sections as SHT_PROGBITS. The best compromise
12526 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12527 generic type-checking code. */
12528 if (section_type
== SHT_MIPS_DWARF
)
12529 section_type
= SHT_PROGBITS
;
12531 obj_elf_change_section (section_name
, section_type
, section_flag
,
12532 section_entry_size
, 0, 0, 0);
12534 if (now_seg
->name
!= section_name
)
12535 free (section_name
);
12536 #endif /* OBJ_ELF */
12540 mips_enable_auto_align (void)
12546 s_cons (int log_size
)
12548 segment_info_type
*si
= seg_info (now_seg
);
12549 struct insn_label_list
*l
= si
->label_list
;
12552 label
= l
!= NULL
? l
->label
: NULL
;
12553 mips_emit_delays ();
12554 if (log_size
> 0 && auto_align
)
12555 mips_align (log_size
, 0, label
);
12556 mips_clear_insn_labels ();
12557 cons (1 << log_size
);
12561 s_float_cons (int type
)
12563 segment_info_type
*si
= seg_info (now_seg
);
12564 struct insn_label_list
*l
= si
->label_list
;
12567 label
= l
!= NULL
? l
->label
: NULL
;
12569 mips_emit_delays ();
12574 mips_align (3, 0, label
);
12576 mips_align (2, 0, label
);
12579 mips_clear_insn_labels ();
12584 /* Handle .globl. We need to override it because on Irix 5 you are
12587 where foo is an undefined symbol, to mean that foo should be
12588 considered to be the address of a function. */
12591 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12600 name
= input_line_pointer
;
12601 c
= get_symbol_end ();
12602 symbolP
= symbol_find_or_make (name
);
12603 S_SET_EXTERNAL (symbolP
);
12605 *input_line_pointer
= c
;
12606 SKIP_WHITESPACE ();
12608 /* On Irix 5, every global symbol that is not explicitly labelled as
12609 being a function is apparently labelled as being an object. */
12612 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12613 && (*input_line_pointer
!= ','))
12618 secname
= input_line_pointer
;
12619 c
= get_symbol_end ();
12620 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12622 as_bad (_("%s: no such section"), secname
);
12623 *input_line_pointer
= c
;
12625 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12626 flag
= BSF_FUNCTION
;
12629 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12631 c
= *input_line_pointer
;
12634 input_line_pointer
++;
12635 SKIP_WHITESPACE ();
12636 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12642 demand_empty_rest_of_line ();
12646 s_option (int x ATTRIBUTE_UNUSED
)
12651 opt
= input_line_pointer
;
12652 c
= get_symbol_end ();
12656 /* FIXME: What does this mean? */
12658 else if (strncmp (opt
, "pic", 3) == 0)
12662 i
= atoi (opt
+ 3);
12667 mips_pic
= SVR4_PIC
;
12668 mips_abicalls
= TRUE
;
12671 as_bad (_(".option pic%d not supported"), i
);
12673 if (mips_pic
== SVR4_PIC
)
12675 if (g_switch_seen
&& g_switch_value
!= 0)
12676 as_warn (_("-G may not be used with SVR4 PIC code"));
12677 g_switch_value
= 0;
12678 bfd_set_gp_size (stdoutput
, 0);
12682 as_warn (_("Unrecognized option \"%s\""), opt
);
12684 *input_line_pointer
= c
;
12685 demand_empty_rest_of_line ();
12688 /* This structure is used to hold a stack of .set values. */
12690 struct mips_option_stack
12692 struct mips_option_stack
*next
;
12693 struct mips_set_options options
;
12696 static struct mips_option_stack
*mips_opts_stack
;
12698 /* Handle the .set pseudo-op. */
12701 s_mipsset (int x ATTRIBUTE_UNUSED
)
12703 char *name
= input_line_pointer
, ch
;
12705 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12706 ++input_line_pointer
;
12707 ch
= *input_line_pointer
;
12708 *input_line_pointer
= '\0';
12710 if (strcmp (name
, "reorder") == 0)
12712 if (mips_opts
.noreorder
)
12715 else if (strcmp (name
, "noreorder") == 0)
12717 if (!mips_opts
.noreorder
)
12718 start_noreorder ();
12720 else if (strncmp (name
, "at=", 3) == 0)
12722 char *s
= name
+ 3;
12724 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12725 as_bad (_("Unrecognized register name `%s'"), s
);
12727 else if (strcmp (name
, "at") == 0)
12729 mips_opts
.at
= ATREG
;
12731 else if (strcmp (name
, "noat") == 0)
12733 mips_opts
.at
= ZERO
;
12735 else if (strcmp (name
, "macro") == 0)
12737 mips_opts
.warn_about_macros
= 0;
12739 else if (strcmp (name
, "nomacro") == 0)
12741 if (mips_opts
.noreorder
== 0)
12742 as_bad (_("`noreorder' must be set before `nomacro'"));
12743 mips_opts
.warn_about_macros
= 1;
12745 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12747 mips_opts
.nomove
= 0;
12749 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12751 mips_opts
.nomove
= 1;
12753 else if (strcmp (name
, "bopt") == 0)
12755 mips_opts
.nobopt
= 0;
12757 else if (strcmp (name
, "nobopt") == 0)
12759 mips_opts
.nobopt
= 1;
12761 else if (strcmp (name
, "gp=default") == 0)
12762 mips_opts
.gp32
= file_mips_gp32
;
12763 else if (strcmp (name
, "gp=32") == 0)
12764 mips_opts
.gp32
= 1;
12765 else if (strcmp (name
, "gp=64") == 0)
12767 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12768 as_warn ("%s isa does not support 64-bit registers",
12769 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12770 mips_opts
.gp32
= 0;
12772 else if (strcmp (name
, "fp=default") == 0)
12773 mips_opts
.fp32
= file_mips_fp32
;
12774 else if (strcmp (name
, "fp=32") == 0)
12775 mips_opts
.fp32
= 1;
12776 else if (strcmp (name
, "fp=64") == 0)
12778 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12779 as_warn ("%s isa does not support 64-bit floating point registers",
12780 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12781 mips_opts
.fp32
= 0;
12783 else if (strcmp (name
, "softfloat") == 0)
12784 mips_opts
.soft_float
= 1;
12785 else if (strcmp (name
, "hardfloat") == 0)
12786 mips_opts
.soft_float
= 0;
12787 else if (strcmp (name
, "singlefloat") == 0)
12788 mips_opts
.single_float
= 1;
12789 else if (strcmp (name
, "doublefloat") == 0)
12790 mips_opts
.single_float
= 0;
12791 else if (strcmp (name
, "mips16") == 0
12792 || strcmp (name
, "MIPS-16") == 0)
12793 mips_opts
.mips16
= 1;
12794 else if (strcmp (name
, "nomips16") == 0
12795 || strcmp (name
, "noMIPS-16") == 0)
12796 mips_opts
.mips16
= 0;
12797 else if (strcmp (name
, "smartmips") == 0)
12799 if (!ISA_SUPPORTS_SMARTMIPS
)
12800 as_warn ("%s ISA does not support SmartMIPS ASE",
12801 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12802 mips_opts
.ase_smartmips
= 1;
12804 else if (strcmp (name
, "nosmartmips") == 0)
12805 mips_opts
.ase_smartmips
= 0;
12806 else if (strcmp (name
, "mips3d") == 0)
12807 mips_opts
.ase_mips3d
= 1;
12808 else if (strcmp (name
, "nomips3d") == 0)
12809 mips_opts
.ase_mips3d
= 0;
12810 else if (strcmp (name
, "mdmx") == 0)
12811 mips_opts
.ase_mdmx
= 1;
12812 else if (strcmp (name
, "nomdmx") == 0)
12813 mips_opts
.ase_mdmx
= 0;
12814 else if (strcmp (name
, "dsp") == 0)
12816 if (!ISA_SUPPORTS_DSP_ASE
)
12817 as_warn ("%s ISA does not support DSP ASE",
12818 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12819 mips_opts
.ase_dsp
= 1;
12820 mips_opts
.ase_dspr2
= 0;
12822 else if (strcmp (name
, "nodsp") == 0)
12824 mips_opts
.ase_dsp
= 0;
12825 mips_opts
.ase_dspr2
= 0;
12827 else if (strcmp (name
, "dspr2") == 0)
12829 if (!ISA_SUPPORTS_DSPR2_ASE
)
12830 as_warn ("%s ISA does not support DSP R2 ASE",
12831 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12832 mips_opts
.ase_dspr2
= 1;
12833 mips_opts
.ase_dsp
= 1;
12835 else if (strcmp (name
, "nodspr2") == 0)
12837 mips_opts
.ase_dspr2
= 0;
12838 mips_opts
.ase_dsp
= 0;
12840 else if (strcmp (name
, "mt") == 0)
12842 if (!ISA_SUPPORTS_MT_ASE
)
12843 as_warn ("%s ISA does not support MT ASE",
12844 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12845 mips_opts
.ase_mt
= 1;
12847 else if (strcmp (name
, "nomt") == 0)
12848 mips_opts
.ase_mt
= 0;
12849 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12853 /* Permit the user to change the ISA and architecture on the fly.
12854 Needless to say, misuse can cause serious problems. */
12855 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12858 mips_opts
.isa
= file_mips_isa
;
12859 mips_opts
.arch
= file_mips_arch
;
12861 else if (strncmp (name
, "arch=", 5) == 0)
12863 const struct mips_cpu_info
*p
;
12865 p
= mips_parse_cpu("internal use", name
+ 5);
12867 as_bad (_("unknown architecture %s"), name
+ 5);
12870 mips_opts
.arch
= p
->cpu
;
12871 mips_opts
.isa
= p
->isa
;
12874 else if (strncmp (name
, "mips", 4) == 0)
12876 const struct mips_cpu_info
*p
;
12878 p
= mips_parse_cpu("internal use", name
);
12880 as_bad (_("unknown ISA level %s"), name
+ 4);
12883 mips_opts
.arch
= p
->cpu
;
12884 mips_opts
.isa
= p
->isa
;
12888 as_bad (_("unknown ISA or architecture %s"), name
);
12890 switch (mips_opts
.isa
)
12898 mips_opts
.gp32
= 1;
12899 mips_opts
.fp32
= 1;
12906 mips_opts
.gp32
= 0;
12907 mips_opts
.fp32
= 0;
12910 as_bad (_("unknown ISA level %s"), name
+ 4);
12915 mips_opts
.gp32
= file_mips_gp32
;
12916 mips_opts
.fp32
= file_mips_fp32
;
12919 else if (strcmp (name
, "autoextend") == 0)
12920 mips_opts
.noautoextend
= 0;
12921 else if (strcmp (name
, "noautoextend") == 0)
12922 mips_opts
.noautoextend
= 1;
12923 else if (strcmp (name
, "push") == 0)
12925 struct mips_option_stack
*s
;
12927 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12928 s
->next
= mips_opts_stack
;
12929 s
->options
= mips_opts
;
12930 mips_opts_stack
= s
;
12932 else if (strcmp (name
, "pop") == 0)
12934 struct mips_option_stack
*s
;
12936 s
= mips_opts_stack
;
12938 as_bad (_(".set pop with no .set push"));
12941 /* If we're changing the reorder mode we need to handle
12942 delay slots correctly. */
12943 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12944 start_noreorder ();
12945 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12948 mips_opts
= s
->options
;
12949 mips_opts_stack
= s
->next
;
12953 else if (strcmp (name
, "sym32") == 0)
12954 mips_opts
.sym32
= TRUE
;
12955 else if (strcmp (name
, "nosym32") == 0)
12956 mips_opts
.sym32
= FALSE
;
12957 else if (strchr (name
, ','))
12959 /* Generic ".set" directive; use the generic handler. */
12960 *input_line_pointer
= ch
;
12961 input_line_pointer
= name
;
12967 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12969 *input_line_pointer
= ch
;
12970 demand_empty_rest_of_line ();
12973 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12974 .option pic2. It means to generate SVR4 PIC calls. */
12977 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12979 mips_pic
= SVR4_PIC
;
12980 mips_abicalls
= TRUE
;
12982 if (g_switch_seen
&& g_switch_value
!= 0)
12983 as_warn (_("-G may not be used with SVR4 PIC code"));
12984 g_switch_value
= 0;
12986 bfd_set_gp_size (stdoutput
, 0);
12987 demand_empty_rest_of_line ();
12990 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12991 PIC code. It sets the $gp register for the function based on the
12992 function address, which is in the register named in the argument.
12993 This uses a relocation against _gp_disp, which is handled specially
12994 by the linker. The result is:
12995 lui $gp,%hi(_gp_disp)
12996 addiu $gp,$gp,%lo(_gp_disp)
12997 addu $gp,$gp,.cpload argument
12998 The .cpload argument is normally $25 == $t9.
13000 The -mno-shared option changes this to:
13001 lui $gp,%hi(__gnu_local_gp)
13002 addiu $gp,$gp,%lo(__gnu_local_gp)
13003 and the argument is ignored. This saves an instruction, but the
13004 resulting code is not position independent; it uses an absolute
13005 address for __gnu_local_gp. Thus code assembled with -mno-shared
13006 can go into an ordinary executable, but not into a shared library. */
13009 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13015 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13016 .cpload is ignored. */
13017 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13023 /* .cpload should be in a .set noreorder section. */
13024 if (mips_opts
.noreorder
== 0)
13025 as_warn (_(".cpload not in noreorder section"));
13027 reg
= tc_get_register (0);
13029 /* If we need to produce a 64-bit address, we are better off using
13030 the default instruction sequence. */
13031 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13033 ex
.X_op
= O_symbol
;
13034 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13036 ex
.X_op_symbol
= NULL
;
13037 ex
.X_add_number
= 0;
13039 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13040 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13043 macro_build_lui (&ex
, mips_gp_register
);
13044 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13045 mips_gp_register
, BFD_RELOC_LO16
);
13047 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13048 mips_gp_register
, reg
);
13051 demand_empty_rest_of_line ();
13054 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13055 .cpsetup $reg1, offset|$reg2, label
13057 If offset is given, this results in:
13058 sd $gp, offset($sp)
13059 lui $gp, %hi(%neg(%gp_rel(label)))
13060 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13061 daddu $gp, $gp, $reg1
13063 If $reg2 is given, this results in:
13064 daddu $reg2, $gp, $0
13065 lui $gp, %hi(%neg(%gp_rel(label)))
13066 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13067 daddu $gp, $gp, $reg1
13068 $reg1 is normally $25 == $t9.
13070 The -mno-shared option replaces the last three instructions with
13072 addiu $gp,$gp,%lo(_gp) */
13075 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13077 expressionS ex_off
;
13078 expressionS ex_sym
;
13081 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13082 We also need NewABI support. */
13083 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13089 reg1
= tc_get_register (0);
13090 SKIP_WHITESPACE ();
13091 if (*input_line_pointer
!= ',')
13093 as_bad (_("missing argument separator ',' for .cpsetup"));
13097 ++input_line_pointer
;
13098 SKIP_WHITESPACE ();
13099 if (*input_line_pointer
== '$')
13101 mips_cpreturn_register
= tc_get_register (0);
13102 mips_cpreturn_offset
= -1;
13106 mips_cpreturn_offset
= get_absolute_expression ();
13107 mips_cpreturn_register
= -1;
13109 SKIP_WHITESPACE ();
13110 if (*input_line_pointer
!= ',')
13112 as_bad (_("missing argument separator ',' for .cpsetup"));
13116 ++input_line_pointer
;
13117 SKIP_WHITESPACE ();
13118 expression (&ex_sym
);
13121 if (mips_cpreturn_register
== -1)
13123 ex_off
.X_op
= O_constant
;
13124 ex_off
.X_add_symbol
= NULL
;
13125 ex_off
.X_op_symbol
= NULL
;
13126 ex_off
.X_add_number
= mips_cpreturn_offset
;
13128 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13129 BFD_RELOC_LO16
, SP
);
13132 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13133 mips_gp_register
, 0);
13135 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13137 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13138 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13141 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13142 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13143 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13145 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13146 mips_gp_register
, reg1
);
13152 ex
.X_op
= O_symbol
;
13153 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13154 ex
.X_op_symbol
= NULL
;
13155 ex
.X_add_number
= 0;
13157 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13158 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13160 macro_build_lui (&ex
, mips_gp_register
);
13161 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13162 mips_gp_register
, BFD_RELOC_LO16
);
13167 demand_empty_rest_of_line ();
13171 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13173 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13174 .cplocal is ignored. */
13175 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13181 mips_gp_register
= tc_get_register (0);
13182 demand_empty_rest_of_line ();
13185 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13186 offset from $sp. The offset is remembered, and after making a PIC
13187 call $gp is restored from that location. */
13190 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13194 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13195 .cprestore is ignored. */
13196 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13202 mips_cprestore_offset
= get_absolute_expression ();
13203 mips_cprestore_valid
= 1;
13205 ex
.X_op
= O_constant
;
13206 ex
.X_add_symbol
= NULL
;
13207 ex
.X_op_symbol
= NULL
;
13208 ex
.X_add_number
= mips_cprestore_offset
;
13211 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13212 SP
, HAVE_64BIT_ADDRESSES
);
13215 demand_empty_rest_of_line ();
13218 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13219 was given in the preceding .cpsetup, it results in:
13220 ld $gp, offset($sp)
13222 If a register $reg2 was given there, it results in:
13223 daddu $gp, $reg2, $0 */
13226 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13230 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13231 We also need NewABI support. */
13232 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13239 if (mips_cpreturn_register
== -1)
13241 ex
.X_op
= O_constant
;
13242 ex
.X_add_symbol
= NULL
;
13243 ex
.X_op_symbol
= NULL
;
13244 ex
.X_add_number
= mips_cpreturn_offset
;
13246 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13249 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13250 mips_cpreturn_register
, 0);
13253 demand_empty_rest_of_line ();
13256 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13257 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13258 use in DWARF debug information. */
13261 s_dtprel_internal (size_t bytes
)
13268 if (ex
.X_op
!= O_symbol
)
13270 as_bad (_("Unsupported use of %s"), (bytes
== 8
13273 ignore_rest_of_line ();
13276 p
= frag_more (bytes
);
13277 md_number_to_chars (p
, 0, bytes
);
13278 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13280 ? BFD_RELOC_MIPS_TLS_DTPREL64
13281 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13283 demand_empty_rest_of_line ();
13286 /* Handle .dtprelword. */
13289 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13291 s_dtprel_internal (4);
13294 /* Handle .dtpreldword. */
13297 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13299 s_dtprel_internal (8);
13302 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13303 code. It sets the offset to use in gp_rel relocations. */
13306 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13308 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13309 We also need NewABI support. */
13310 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13316 mips_gprel_offset
= get_absolute_expression ();
13318 demand_empty_rest_of_line ();
13321 /* Handle the .gpword pseudo-op. This is used when generating PIC
13322 code. It generates a 32 bit GP relative reloc. */
13325 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13327 segment_info_type
*si
;
13328 struct insn_label_list
*l
;
13333 /* When not generating PIC code, this is treated as .word. */
13334 if (mips_pic
!= SVR4_PIC
)
13340 si
= seg_info (now_seg
);
13341 l
= si
->label_list
;
13342 label
= l
!= NULL
? l
->label
: NULL
;
13343 mips_emit_delays ();
13345 mips_align (2, 0, label
);
13346 mips_clear_insn_labels ();
13350 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13352 as_bad (_("Unsupported use of .gpword"));
13353 ignore_rest_of_line ();
13357 md_number_to_chars (p
, 0, 4);
13358 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13359 BFD_RELOC_GPREL32
);
13361 demand_empty_rest_of_line ();
13365 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13367 segment_info_type
*si
;
13368 struct insn_label_list
*l
;
13373 /* When not generating PIC code, this is treated as .dword. */
13374 if (mips_pic
!= SVR4_PIC
)
13380 si
= seg_info (now_seg
);
13381 l
= si
->label_list
;
13382 label
= l
!= NULL
? l
->label
: NULL
;
13383 mips_emit_delays ();
13385 mips_align (3, 0, label
);
13386 mips_clear_insn_labels ();
13390 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13392 as_bad (_("Unsupported use of .gpdword"));
13393 ignore_rest_of_line ();
13397 md_number_to_chars (p
, 0, 8);
13398 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13399 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13401 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13402 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13403 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13405 demand_empty_rest_of_line ();
13408 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13409 tables in SVR4 PIC code. */
13412 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13416 /* This is ignored when not generating SVR4 PIC code. */
13417 if (mips_pic
!= SVR4_PIC
)
13423 /* Add $gp to the register named as an argument. */
13425 reg
= tc_get_register (0);
13426 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13429 demand_empty_rest_of_line ();
13432 /* Handle the .insn pseudo-op. This marks instruction labels in
13433 mips16 mode. This permits the linker to handle them specially,
13434 such as generating jalx instructions when needed. We also make
13435 them odd for the duration of the assembly, in order to generate the
13436 right sort of code. We will make them even in the adjust_symtab
13437 routine, while leaving them marked. This is convenient for the
13438 debugger and the disassembler. The linker knows to make them odd
13442 s_insn (int ignore ATTRIBUTE_UNUSED
)
13444 mips16_mark_labels ();
13446 demand_empty_rest_of_line ();
13449 /* Handle a .stabn directive. We need these in order to mark a label
13450 as being a mips16 text label correctly. Sometimes the compiler
13451 will emit a label, followed by a .stabn, and then switch sections.
13452 If the label and .stabn are in mips16 mode, then the label is
13453 really a mips16 text label. */
13456 s_mips_stab (int type
)
13459 mips16_mark_labels ();
13464 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13467 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13474 name
= input_line_pointer
;
13475 c
= get_symbol_end ();
13476 symbolP
= symbol_find_or_make (name
);
13477 S_SET_WEAK (symbolP
);
13478 *input_line_pointer
= c
;
13480 SKIP_WHITESPACE ();
13482 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13484 if (S_IS_DEFINED (symbolP
))
13486 as_bad ("ignoring attempt to redefine symbol %s",
13487 S_GET_NAME (symbolP
));
13488 ignore_rest_of_line ();
13492 if (*input_line_pointer
== ',')
13494 ++input_line_pointer
;
13495 SKIP_WHITESPACE ();
13499 if (exp
.X_op
!= O_symbol
)
13501 as_bad ("bad .weakext directive");
13502 ignore_rest_of_line ();
13505 symbol_set_value_expression (symbolP
, &exp
);
13508 demand_empty_rest_of_line ();
13511 /* Parse a register string into a number. Called from the ECOFF code
13512 to parse .frame. The argument is non-zero if this is the frame
13513 register, so that we can record it in mips_frame_reg. */
13516 tc_get_register (int frame
)
13520 SKIP_WHITESPACE ();
13521 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13525 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13526 mips_frame_reg_valid
= 1;
13527 mips_cprestore_valid
= 0;
13533 md_section_align (asection
*seg
, valueT addr
)
13535 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13539 /* We don't need to align ELF sections to the full alignment.
13540 However, Irix 5 may prefer that we align them at least to a 16
13541 byte boundary. We don't bother to align the sections if we
13542 are targeted for an embedded system. */
13543 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13549 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13552 /* Utility routine, called from above as well. If called while the
13553 input file is still being read, it's only an approximation. (For
13554 example, a symbol may later become defined which appeared to be
13555 undefined earlier.) */
13558 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13563 if (g_switch_value
> 0)
13565 const char *symname
;
13568 /* Find out whether this symbol can be referenced off the $gp
13569 register. It can be if it is smaller than the -G size or if
13570 it is in the .sdata or .sbss section. Certain symbols can
13571 not be referenced off the $gp, although it appears as though
13573 symname
= S_GET_NAME (sym
);
13574 if (symname
!= (const char *) NULL
13575 && (strcmp (symname
, "eprol") == 0
13576 || strcmp (symname
, "etext") == 0
13577 || strcmp (symname
, "_gp") == 0
13578 || strcmp (symname
, "edata") == 0
13579 || strcmp (symname
, "_fbss") == 0
13580 || strcmp (symname
, "_fdata") == 0
13581 || strcmp (symname
, "_ftext") == 0
13582 || strcmp (symname
, "end") == 0
13583 || strcmp (symname
, "_gp_disp") == 0))
13585 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13587 #ifndef NO_ECOFF_DEBUGGING
13588 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13589 && (symbol_get_obj (sym
)->ecoff_extern_size
13590 <= g_switch_value
))
13592 /* We must defer this decision until after the whole
13593 file has been read, since there might be a .extern
13594 after the first use of this symbol. */
13595 || (before_relaxing
13596 #ifndef NO_ECOFF_DEBUGGING
13597 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13599 && S_GET_VALUE (sym
) == 0)
13600 || (S_GET_VALUE (sym
) != 0
13601 && S_GET_VALUE (sym
) <= g_switch_value
)))
13605 const char *segname
;
13607 segname
= segment_name (S_GET_SEGMENT (sym
));
13608 assert (strcmp (segname
, ".lit8") != 0
13609 && strcmp (segname
, ".lit4") != 0);
13610 change
= (strcmp (segname
, ".sdata") != 0
13611 && strcmp (segname
, ".sbss") != 0
13612 && strncmp (segname
, ".sdata.", 7) != 0
13613 && strncmp (segname
, ".sbss.", 6) != 0
13614 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13615 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13620 /* We are not optimizing for the $gp register. */
13625 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13628 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13632 /* Handle the case of a symbol equated to another symbol. */
13633 while (symbol_equated_reloc_p (sym
))
13637 /* It's possible to get a loop here in a badly written program. */
13638 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13644 if (symbol_section_p (sym
))
13647 symsec
= S_GET_SEGMENT (sym
);
13649 /* This must duplicate the test in adjust_reloc_syms. */
13650 return (symsec
!= &bfd_und_section
13651 && symsec
!= &bfd_abs_section
13652 && !bfd_is_com_section (symsec
)
13653 && !s_is_linkonce (sym
, segtype
)
13655 /* A global or weak symbol is treated as external. */
13656 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13662 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13663 extended opcode. SEC is the section the frag is in. */
13666 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13669 const struct mips16_immed_operand
*op
;
13671 int mintiny
, maxtiny
;
13675 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13677 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13680 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13681 op
= mips16_immed_operands
;
13682 while (op
->type
!= type
)
13685 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13690 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13693 maxtiny
= 1 << op
->nbits
;
13698 maxtiny
= (1 << op
->nbits
) - 1;
13703 mintiny
= - (1 << (op
->nbits
- 1));
13704 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13707 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13708 val
= S_GET_VALUE (fragp
->fr_symbol
);
13709 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13715 /* We won't have the section when we are called from
13716 mips_relax_frag. However, we will always have been called
13717 from md_estimate_size_before_relax first. If this is a
13718 branch to a different section, we mark it as such. If SEC is
13719 NULL, and the frag is not marked, then it must be a branch to
13720 the same section. */
13723 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13728 /* Must have been called from md_estimate_size_before_relax. */
13731 fragp
->fr_subtype
=
13732 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13734 /* FIXME: We should support this, and let the linker
13735 catch branches and loads that are out of range. */
13736 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13737 _("unsupported PC relative reference to different section"));
13741 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13742 /* Assume non-extended on the first relaxation pass.
13743 The address we have calculated will be bogus if this is
13744 a forward branch to another frag, as the forward frag
13745 will have fr_address == 0. */
13749 /* In this case, we know for sure that the symbol fragment is in
13750 the same section. If the relax_marker of the symbol fragment
13751 differs from the relax_marker of this fragment, we have not
13752 yet adjusted the symbol fragment fr_address. We want to add
13753 in STRETCH in order to get a better estimate of the address.
13754 This particularly matters because of the shift bits. */
13756 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13760 /* Adjust stretch for any alignment frag. Note that if have
13761 been expanding the earlier code, the symbol may be
13762 defined in what appears to be an earlier frag. FIXME:
13763 This doesn't handle the fr_subtype field, which specifies
13764 a maximum number of bytes to skip when doing an
13766 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13768 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13771 stretch
= - ((- stretch
)
13772 & ~ ((1 << (int) f
->fr_offset
) - 1));
13774 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13783 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13785 /* The base address rules are complicated. The base address of
13786 a branch is the following instruction. The base address of a
13787 PC relative load or add is the instruction itself, but if it
13788 is in a delay slot (in which case it can not be extended) use
13789 the address of the instruction whose delay slot it is in. */
13790 if (type
== 'p' || type
== 'q')
13794 /* If we are currently assuming that this frag should be
13795 extended, then, the current address is two bytes
13797 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13800 /* Ignore the low bit in the target, since it will be set
13801 for a text label. */
13802 if ((val
& 1) != 0)
13805 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13807 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13810 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13812 /* Branch offsets have an implicit 0 in the lowest bit. */
13813 if (type
== 'p' || type
== 'q')
13816 /* If any of the shifted bits are set, we must use an extended
13817 opcode. If the address depends on the size of this
13818 instruction, this can lead to a loop, so we arrange to always
13819 use an extended opcode. We only check this when we are in
13820 the main relaxation loop, when SEC is NULL. */
13821 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13823 fragp
->fr_subtype
=
13824 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13828 /* If we are about to mark a frag as extended because the value
13829 is precisely maxtiny + 1, then there is a chance of an
13830 infinite loop as in the following code:
13835 In this case when the la is extended, foo is 0x3fc bytes
13836 away, so the la can be shrunk, but then foo is 0x400 away, so
13837 the la must be extended. To avoid this loop, we mark the
13838 frag as extended if it was small, and is about to become
13839 extended with a value of maxtiny + 1. */
13840 if (val
== ((maxtiny
+ 1) << op
->shift
)
13841 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13844 fragp
->fr_subtype
=
13845 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13849 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13850 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13852 if ((val
& ((1 << op
->shift
) - 1)) != 0
13853 || val
< (mintiny
<< op
->shift
)
13854 || val
> (maxtiny
<< op
->shift
))
13860 /* Compute the length of a branch sequence, and adjust the
13861 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13862 worst-case length is computed, with UPDATE being used to indicate
13863 whether an unconditional (-1), branch-likely (+1) or regular (0)
13864 branch is to be computed. */
13866 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13868 bfd_boolean toofar
;
13872 && S_IS_DEFINED (fragp
->fr_symbol
)
13873 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13878 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13880 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13884 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13887 /* If the symbol is not defined or it's in a different segment,
13888 assume the user knows what's going on and emit a short
13894 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13896 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13897 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13898 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13904 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13907 if (mips_pic
!= NO_PIC
)
13909 /* Additional space for PIC loading of target address. */
13911 if (mips_opts
.isa
== ISA_MIPS1
)
13912 /* Additional space for $at-stabilizing nop. */
13916 /* If branch is conditional. */
13917 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13924 /* Estimate the size of a frag before relaxing. Unless this is the
13925 mips16, we are not really relaxing here, and the final size is
13926 encoded in the subtype information. For the mips16, we have to
13927 decide whether we are using an extended opcode or not. */
13930 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13934 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13937 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13939 return fragp
->fr_var
;
13942 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13943 /* We don't want to modify the EXTENDED bit here; it might get us
13944 into infinite loops. We change it only in mips_relax_frag(). */
13945 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13947 if (mips_pic
== NO_PIC
)
13948 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13949 else if (mips_pic
== SVR4_PIC
)
13950 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13951 else if (mips_pic
== VXWORKS_PIC
)
13952 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13959 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13960 return -RELAX_FIRST (fragp
->fr_subtype
);
13963 return -RELAX_SECOND (fragp
->fr_subtype
);
13966 /* This is called to see whether a reloc against a defined symbol
13967 should be converted into a reloc against a section. */
13970 mips_fix_adjustable (fixS
*fixp
)
13972 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13973 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13976 if (fixp
->fx_addsy
== NULL
)
13979 /* If symbol SYM is in a mergeable section, relocations of the form
13980 SYM + 0 can usually be made section-relative. The mergeable data
13981 is then identified by the section offset rather than by the symbol.
13983 However, if we're generating REL LO16 relocations, the offset is split
13984 between the LO16 and parterning high part relocation. The linker will
13985 need to recalculate the complete offset in order to correctly identify
13988 The linker has traditionally not looked for the parterning high part
13989 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13990 placed anywhere. Rather than break backwards compatibility by changing
13991 this, it seems better not to force the issue, and instead keep the
13992 original symbol. This will work with either linker behavior. */
13993 if ((lo16_reloc_p (fixp
->fx_r_type
)
13994 || reloc_needs_lo_p (fixp
->fx_r_type
))
13995 && HAVE_IN_PLACE_ADDENDS
13996 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14000 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14001 to a floating-point stub. The same is true for non-R_MIPS16_26
14002 relocations against MIPS16 functions; in this case, the stub becomes
14003 the function's canonical address.
14005 Floating-point stubs are stored in unique .mips16.call.* or
14006 .mips16.fn.* sections. If a stub T for function F is in section S,
14007 the first relocation in section S must be against F; this is how the
14008 linker determines the target function. All relocations that might
14009 resolve to T must also be against F. We therefore have the following
14010 restrictions, which are given in an intentionally-redundant way:
14012 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14015 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14016 if that stub might be used.
14018 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14021 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14022 that stub might be used.
14024 There is a further restriction:
14026 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14027 on targets with in-place addends; the relocation field cannot
14028 encode the low bit.
14030 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14031 against a MIPS16 symbol.
14033 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14034 relocation against some symbol R, no relocation against R may be
14035 reduced. (Note that this deals with (2) as well as (1) because
14036 relocations against global symbols will never be reduced on ELF
14037 targets.) This approach is a little simpler than trying to detect
14038 stub sections, and gives the "all or nothing" per-symbol consistency
14039 that we have for MIPS16 symbols. */
14041 && fixp
->fx_subsy
== NULL
14042 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14043 || *symbol_get_tc (fixp
->fx_addsy
)))
14050 /* Translate internal representation of relocation info to BFD target
14054 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14056 static arelent
*retval
[4];
14058 bfd_reloc_code_real_type code
;
14060 memset (retval
, 0, sizeof(retval
));
14061 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14062 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14063 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14064 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14066 if (fixp
->fx_pcrel
)
14068 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14070 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14071 Relocations want only the symbol offset. */
14072 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14075 /* A gruesome hack which is a result of the gruesome gas
14076 reloc handling. What's worse, for COFF (as opposed to
14077 ECOFF), we might need yet another copy of reloc->address.
14078 See bfd_install_relocation. */
14079 reloc
->addend
+= reloc
->address
;
14083 reloc
->addend
= fixp
->fx_addnumber
;
14085 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14086 entry to be used in the relocation's section offset. */
14087 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14089 reloc
->address
= reloc
->addend
;
14093 code
= fixp
->fx_r_type
;
14095 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14096 if (reloc
->howto
== NULL
)
14098 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14099 _("Can not represent %s relocation in this object file format"),
14100 bfd_get_reloc_code_name (code
));
14107 /* Relax a machine dependent frag. This returns the amount by which
14108 the current size of the frag should change. */
14111 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14113 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14115 offsetT old_var
= fragp
->fr_var
;
14117 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14119 return fragp
->fr_var
- old_var
;
14122 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14125 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14127 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14129 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14134 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14136 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14143 /* Convert a machine dependent frag. */
14146 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14148 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14151 unsigned long insn
;
14155 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14157 if (target_big_endian
)
14158 insn
= bfd_getb32 (buf
);
14160 insn
= bfd_getl32 (buf
);
14162 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14164 /* We generate a fixup instead of applying it right now
14165 because, if there are linker relaxations, we're going to
14166 need the relocations. */
14167 exp
.X_op
= O_symbol
;
14168 exp
.X_add_symbol
= fragp
->fr_symbol
;
14169 exp
.X_add_number
= fragp
->fr_offset
;
14171 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14172 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14173 fixp
->fx_file
= fragp
->fr_file
;
14174 fixp
->fx_line
= fragp
->fr_line
;
14176 md_number_to_chars ((char *) buf
, insn
, 4);
14183 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14184 _("relaxed out-of-range branch into a jump"));
14186 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14189 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14191 /* Reverse the branch. */
14192 switch ((insn
>> 28) & 0xf)
14195 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14196 have the condition reversed by tweaking a single
14197 bit, and their opcodes all have 0x4???????. */
14198 assert ((insn
& 0xf1000000) == 0x41000000);
14199 insn
^= 0x00010000;
14203 /* bltz 0x04000000 bgez 0x04010000
14204 bltzal 0x04100000 bgezal 0x04110000 */
14205 assert ((insn
& 0xfc0e0000) == 0x04000000);
14206 insn
^= 0x00010000;
14210 /* beq 0x10000000 bne 0x14000000
14211 blez 0x18000000 bgtz 0x1c000000 */
14212 insn
^= 0x04000000;
14220 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14222 /* Clear the and-link bit. */
14223 assert ((insn
& 0xfc1c0000) == 0x04100000);
14225 /* bltzal 0x04100000 bgezal 0x04110000
14226 bltzall 0x04120000 bgezall 0x04130000 */
14227 insn
&= ~0x00100000;
14230 /* Branch over the branch (if the branch was likely) or the
14231 full jump (not likely case). Compute the offset from the
14232 current instruction to branch to. */
14233 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14237 /* How many bytes in instructions we've already emitted? */
14238 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14239 /* How many bytes in instructions from here to the end? */
14240 i
= fragp
->fr_var
- i
;
14242 /* Convert to instruction count. */
14244 /* Branch counts from the next instruction. */
14247 /* Branch over the jump. */
14248 md_number_to_chars ((char *) buf
, insn
, 4);
14252 md_number_to_chars ((char *) buf
, 0, 4);
14255 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14257 /* beql $0, $0, 2f */
14259 /* Compute the PC offset from the current instruction to
14260 the end of the variable frag. */
14261 /* How many bytes in instructions we've already emitted? */
14262 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14263 /* How many bytes in instructions from here to the end? */
14264 i
= fragp
->fr_var
- i
;
14265 /* Convert to instruction count. */
14267 /* Don't decrement i, because we want to branch over the
14271 md_number_to_chars ((char *) buf
, insn
, 4);
14274 md_number_to_chars ((char *) buf
, 0, 4);
14279 if (mips_pic
== NO_PIC
)
14282 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14283 ? 0x0c000000 : 0x08000000);
14284 exp
.X_op
= O_symbol
;
14285 exp
.X_add_symbol
= fragp
->fr_symbol
;
14286 exp
.X_add_number
= fragp
->fr_offset
;
14288 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14289 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14290 fixp
->fx_file
= fragp
->fr_file
;
14291 fixp
->fx_line
= fragp
->fr_line
;
14293 md_number_to_chars ((char *) buf
, insn
, 4);
14298 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14299 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14300 exp
.X_op
= O_symbol
;
14301 exp
.X_add_symbol
= fragp
->fr_symbol
;
14302 exp
.X_add_number
= fragp
->fr_offset
;
14304 if (fragp
->fr_offset
)
14306 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14307 exp
.X_add_number
= 0;
14310 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14311 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14312 fixp
->fx_file
= fragp
->fr_file
;
14313 fixp
->fx_line
= fragp
->fr_line
;
14315 md_number_to_chars ((char *) buf
, insn
, 4);
14318 if (mips_opts
.isa
== ISA_MIPS1
)
14321 md_number_to_chars ((char *) buf
, 0, 4);
14325 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14326 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14328 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14329 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14330 fixp
->fx_file
= fragp
->fr_file
;
14331 fixp
->fx_line
= fragp
->fr_line
;
14333 md_number_to_chars ((char *) buf
, insn
, 4);
14337 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14342 md_number_to_chars ((char *) buf
, insn
, 4);
14347 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14348 + fragp
->fr_fix
+ fragp
->fr_var
);
14350 fragp
->fr_fix
+= fragp
->fr_var
;
14355 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14358 const struct mips16_immed_operand
*op
;
14359 bfd_boolean small
, ext
;
14362 unsigned long insn
;
14363 bfd_boolean use_extend
;
14364 unsigned short extend
;
14366 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14367 op
= mips16_immed_operands
;
14368 while (op
->type
!= type
)
14371 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14382 resolve_symbol_value (fragp
->fr_symbol
);
14383 val
= S_GET_VALUE (fragp
->fr_symbol
);
14388 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14390 /* The rules for the base address of a PC relative reloc are
14391 complicated; see mips16_extended_frag. */
14392 if (type
== 'p' || type
== 'q')
14397 /* Ignore the low bit in the target, since it will be
14398 set for a text label. */
14399 if ((val
& 1) != 0)
14402 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14404 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14407 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14410 /* Make sure the section winds up with the alignment we have
14413 record_alignment (asec
, op
->shift
);
14417 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14418 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14419 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14420 _("extended instruction in delay slot"));
14422 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14424 if (target_big_endian
)
14425 insn
= bfd_getb16 (buf
);
14427 insn
= bfd_getl16 (buf
);
14429 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14430 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14431 small
, ext
, &insn
, &use_extend
, &extend
);
14435 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14436 fragp
->fr_fix
+= 2;
14440 md_number_to_chars ((char *) buf
, insn
, 2);
14441 fragp
->fr_fix
+= 2;
14449 first
= RELAX_FIRST (fragp
->fr_subtype
);
14450 second
= RELAX_SECOND (fragp
->fr_subtype
);
14451 fixp
= (fixS
*) fragp
->fr_opcode
;
14453 /* Possibly emit a warning if we've chosen the longer option. */
14454 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14455 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14457 const char *msg
= macro_warning (fragp
->fr_subtype
);
14459 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14462 /* Go through all the fixups for the first sequence. Disable them
14463 (by marking them as done) if we're going to use the second
14464 sequence instead. */
14466 && fixp
->fx_frag
== fragp
14467 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14469 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14471 fixp
= fixp
->fx_next
;
14474 /* Go through the fixups for the second sequence. Disable them if
14475 we're going to use the first sequence, otherwise adjust their
14476 addresses to account for the relaxation. */
14477 while (fixp
&& fixp
->fx_frag
== fragp
)
14479 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14480 fixp
->fx_where
-= first
;
14483 fixp
= fixp
->fx_next
;
14486 /* Now modify the frag contents. */
14487 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14491 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14492 memmove (start
, start
+ first
, second
);
14493 fragp
->fr_fix
-= first
;
14496 fragp
->fr_fix
-= second
;
14502 /* This function is called after the relocs have been generated.
14503 We've been storing mips16 text labels as odd. Here we convert them
14504 back to even for the convenience of the debugger. */
14507 mips_frob_file_after_relocs (void)
14510 unsigned int count
, i
;
14515 syms
= bfd_get_outsymbols (stdoutput
);
14516 count
= bfd_get_symcount (stdoutput
);
14517 for (i
= 0; i
< count
; i
++, syms
++)
14519 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14520 && ((*syms
)->value
& 1) != 0)
14522 (*syms
)->value
&= ~1;
14523 /* If the symbol has an odd size, it was probably computed
14524 incorrectly, so adjust that as well. */
14525 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14526 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14533 /* This function is called whenever a label is defined. It is used
14534 when handling branch delays; if a branch has a label, we assume we
14535 can not move it. */
14538 mips_define_label (symbolS
*sym
)
14540 segment_info_type
*si
= seg_info (now_seg
);
14541 struct insn_label_list
*l
;
14543 if (free_insn_labels
== NULL
)
14544 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14547 l
= free_insn_labels
;
14548 free_insn_labels
= l
->next
;
14552 l
->next
= si
->label_list
;
14553 si
->label_list
= l
;
14556 dwarf2_emit_label (sym
);
14560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14562 /* Some special processing for a MIPS ELF file. */
14565 mips_elf_final_processing (void)
14567 /* Write out the register information. */
14568 if (mips_abi
!= N64_ABI
)
14572 s
.ri_gprmask
= mips_gprmask
;
14573 s
.ri_cprmask
[0] = mips_cprmask
[0];
14574 s
.ri_cprmask
[1] = mips_cprmask
[1];
14575 s
.ri_cprmask
[2] = mips_cprmask
[2];
14576 s
.ri_cprmask
[3] = mips_cprmask
[3];
14577 /* The gp_value field is set by the MIPS ELF backend. */
14579 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14580 ((Elf32_External_RegInfo
*)
14581 mips_regmask_frag
));
14585 Elf64_Internal_RegInfo s
;
14587 s
.ri_gprmask
= mips_gprmask
;
14589 s
.ri_cprmask
[0] = mips_cprmask
[0];
14590 s
.ri_cprmask
[1] = mips_cprmask
[1];
14591 s
.ri_cprmask
[2] = mips_cprmask
[2];
14592 s
.ri_cprmask
[3] = mips_cprmask
[3];
14593 /* The gp_value field is set by the MIPS ELF backend. */
14595 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14596 ((Elf64_External_RegInfo
*)
14597 mips_regmask_frag
));
14600 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14601 sort of BFD interface for this. */
14602 if (mips_any_noreorder
)
14603 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14604 if (mips_pic
!= NO_PIC
)
14606 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14607 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14610 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14612 /* Set MIPS ELF flags for ASEs. */
14613 /* We may need to define a new flag for DSP ASE, and set this flag when
14614 file_ase_dsp is true. */
14615 /* Same for DSP R2. */
14616 /* We may need to define a new flag for MT ASE, and set this flag when
14617 file_ase_mt is true. */
14618 if (file_ase_mips16
)
14619 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14620 #if 0 /* XXX FIXME */
14621 if (file_ase_mips3d
)
14622 elf_elfheader (stdoutput
)->e_flags
|= ???;
14625 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14627 /* Set the MIPS ELF ABI flags. */
14628 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14629 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14630 else if (mips_abi
== O64_ABI
)
14631 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14632 else if (mips_abi
== EABI_ABI
)
14634 if (!file_mips_gp32
)
14635 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14637 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14639 else if (mips_abi
== N32_ABI
)
14640 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14642 /* Nothing to do for N64_ABI. */
14644 if (mips_32bitmode
)
14645 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14647 #if 0 /* XXX FIXME */
14648 /* 32 bit code with 64 bit FP registers. */
14649 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14650 elf_elfheader (stdoutput
)->e_flags
|= ???;
14654 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14656 typedef struct proc
{
14658 symbolS
*func_end_sym
;
14659 unsigned long reg_mask
;
14660 unsigned long reg_offset
;
14661 unsigned long fpreg_mask
;
14662 unsigned long fpreg_offset
;
14663 unsigned long frame_offset
;
14664 unsigned long frame_reg
;
14665 unsigned long pc_reg
;
14668 static procS cur_proc
;
14669 static procS
*cur_proc_ptr
;
14670 static int numprocs
;
14672 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14676 mips_nop_opcode (void)
14678 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14681 /* Fill in an rs_align_code fragment. This only needs to do something
14682 for MIPS16 code, where 0 is not a nop. */
14685 mips_handle_align (fragS
*fragp
)
14689 if (fragp
->fr_type
!= rs_align_code
)
14692 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14697 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14703 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14709 md_obj_begin (void)
14716 /* Check for premature end, nesting errors, etc. */
14718 as_warn (_("missing .end at end of assembly"));
14727 if (*input_line_pointer
== '-')
14729 ++input_line_pointer
;
14732 if (!ISDIGIT (*input_line_pointer
))
14733 as_bad (_("expected simple number"));
14734 if (input_line_pointer
[0] == '0')
14736 if (input_line_pointer
[1] == 'x')
14738 input_line_pointer
+= 2;
14739 while (ISXDIGIT (*input_line_pointer
))
14742 val
|= hex_value (*input_line_pointer
++);
14744 return negative
? -val
: val
;
14748 ++input_line_pointer
;
14749 while (ISDIGIT (*input_line_pointer
))
14752 val
|= *input_line_pointer
++ - '0';
14754 return negative
? -val
: val
;
14757 if (!ISDIGIT (*input_line_pointer
))
14759 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14760 *input_line_pointer
, *input_line_pointer
);
14761 as_warn (_("invalid number"));
14764 while (ISDIGIT (*input_line_pointer
))
14767 val
+= *input_line_pointer
++ - '0';
14769 return negative
? -val
: val
;
14772 /* The .file directive; just like the usual .file directive, but there
14773 is an initial number which is the ECOFF file index. In the non-ECOFF
14774 case .file implies DWARF-2. */
14777 s_mips_file (int x ATTRIBUTE_UNUSED
)
14779 static int first_file_directive
= 0;
14781 if (ECOFF_DEBUGGING
)
14790 filename
= dwarf2_directive_file (0);
14792 /* Versions of GCC up to 3.1 start files with a ".file"
14793 directive even for stabs output. Make sure that this
14794 ".file" is handled. Note that you need a version of GCC
14795 after 3.1 in order to support DWARF-2 on MIPS. */
14796 if (filename
!= NULL
&& ! first_file_directive
)
14798 (void) new_logical_line (filename
, -1);
14799 s_app_file_string (filename
, 0);
14801 first_file_directive
= 1;
14805 /* The .loc directive, implying DWARF-2. */
14808 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14810 if (!ECOFF_DEBUGGING
)
14811 dwarf2_directive_loc (0);
14814 /* The .end directive. */
14817 s_mips_end (int x ATTRIBUTE_UNUSED
)
14821 /* Following functions need their own .frame and .cprestore directives. */
14822 mips_frame_reg_valid
= 0;
14823 mips_cprestore_valid
= 0;
14825 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14828 demand_empty_rest_of_line ();
14833 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14834 as_warn (_(".end not in text section"));
14838 as_warn (_(".end directive without a preceding .ent directive."));
14839 demand_empty_rest_of_line ();
14845 assert (S_GET_NAME (p
));
14846 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14847 as_warn (_(".end symbol does not match .ent symbol."));
14849 if (debug_type
== DEBUG_STABS
)
14850 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14854 as_warn (_(".end directive missing or unknown symbol"));
14857 /* Create an expression to calculate the size of the function. */
14858 if (p
&& cur_proc_ptr
)
14860 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14861 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14864 exp
->X_op
= O_subtract
;
14865 exp
->X_add_symbol
= symbol_temp_new_now ();
14866 exp
->X_op_symbol
= p
;
14867 exp
->X_add_number
= 0;
14869 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14872 /* Generate a .pdr section. */
14873 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14875 segT saved_seg
= now_seg
;
14876 subsegT saved_subseg
= now_subseg
;
14881 dot
= frag_now_fix ();
14883 #ifdef md_flush_pending_output
14884 md_flush_pending_output ();
14888 subseg_set (pdr_seg
, 0);
14890 /* Write the symbol. */
14891 exp
.X_op
= O_symbol
;
14892 exp
.X_add_symbol
= p
;
14893 exp
.X_add_number
= 0;
14894 emit_expr (&exp
, 4);
14896 fragp
= frag_more (7 * 4);
14898 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14899 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14900 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14901 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14902 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14903 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14904 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14906 subseg_set (saved_seg
, saved_subseg
);
14908 #endif /* OBJ_ELF */
14910 cur_proc_ptr
= NULL
;
14913 /* The .aent and .ent directives. */
14916 s_mips_ent (int aent
)
14920 symbolP
= get_symbol ();
14921 if (*input_line_pointer
== ',')
14922 ++input_line_pointer
;
14923 SKIP_WHITESPACE ();
14924 if (ISDIGIT (*input_line_pointer
)
14925 || *input_line_pointer
== '-')
14928 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14929 as_warn (_(".ent or .aent not in text section."));
14931 if (!aent
&& cur_proc_ptr
)
14932 as_warn (_("missing .end"));
14936 /* This function needs its own .frame and .cprestore directives. */
14937 mips_frame_reg_valid
= 0;
14938 mips_cprestore_valid
= 0;
14940 cur_proc_ptr
= &cur_proc
;
14941 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14943 cur_proc_ptr
->func_sym
= symbolP
;
14945 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14949 if (debug_type
== DEBUG_STABS
)
14950 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14951 S_GET_NAME (symbolP
));
14954 demand_empty_rest_of_line ();
14957 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14958 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14959 s_mips_frame is used so that we can set the PDR information correctly.
14960 We can't use the ecoff routines because they make reference to the ecoff
14961 symbol table (in the mdebug section). */
14964 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14967 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14971 if (cur_proc_ptr
== (procS
*) NULL
)
14973 as_warn (_(".frame outside of .ent"));
14974 demand_empty_rest_of_line ();
14978 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14980 SKIP_WHITESPACE ();
14981 if (*input_line_pointer
++ != ','
14982 || get_absolute_expression_and_terminator (&val
) != ',')
14984 as_warn (_("Bad .frame directive"));
14985 --input_line_pointer
;
14986 demand_empty_rest_of_line ();
14990 cur_proc_ptr
->frame_offset
= val
;
14991 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14993 demand_empty_rest_of_line ();
14996 #endif /* OBJ_ELF */
15000 /* The .fmask and .mask directives. If the mdebug section is present
15001 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15002 embedded targets, s_mips_mask is used so that we can set the PDR
15003 information correctly. We can't use the ecoff routines because they
15004 make reference to the ecoff symbol table (in the mdebug section). */
15007 s_mips_mask (int reg_type
)
15010 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15014 if (cur_proc_ptr
== (procS
*) NULL
)
15016 as_warn (_(".mask/.fmask outside of .ent"));
15017 demand_empty_rest_of_line ();
15021 if (get_absolute_expression_and_terminator (&mask
) != ',')
15023 as_warn (_("Bad .mask/.fmask directive"));
15024 --input_line_pointer
;
15025 demand_empty_rest_of_line ();
15029 off
= get_absolute_expression ();
15031 if (reg_type
== 'F')
15033 cur_proc_ptr
->fpreg_mask
= mask
;
15034 cur_proc_ptr
->fpreg_offset
= off
;
15038 cur_proc_ptr
->reg_mask
= mask
;
15039 cur_proc_ptr
->reg_offset
= off
;
15042 demand_empty_rest_of_line ();
15045 #endif /* OBJ_ELF */
15046 s_ignore (reg_type
);
15049 /* A table describing all the processors gas knows about. Names are
15050 matched in the order listed.
15052 To ease comparison, please keep this table in the same order as
15053 gcc's mips_cpu_info_table[]. */
15054 static const struct mips_cpu_info mips_cpu_info_table
[] =
15056 /* Entries for generic ISAs */
15057 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15058 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15059 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15060 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15061 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15062 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15063 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15064 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15065 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15068 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15069 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15070 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15073 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15076 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15077 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15078 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15079 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15080 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15081 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15082 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15083 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15084 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15085 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15086 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15087 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15088 /* ST Microelectronics Loongson 2E and 2F cores */
15089 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15090 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15093 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15094 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15095 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15096 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15097 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15098 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15099 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15100 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15101 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15102 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15103 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15104 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15105 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15106 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15107 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15110 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15111 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15112 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15113 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15115 /* MIPS 32 Release 2 */
15116 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15117 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15118 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15119 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15120 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15121 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15122 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15123 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15124 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15125 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15126 /* Deprecated forms of the above. */
15127 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15128 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15129 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15130 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15131 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15132 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15133 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15134 /* Deprecated forms of the above. */
15135 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15136 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15137 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15138 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15139 ISA_MIPS32R2
, CPU_MIPS32R2
},
15140 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15141 ISA_MIPS32R2
, CPU_MIPS32R2
},
15142 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15143 ISA_MIPS32R2
, CPU_MIPS32R2
},
15144 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15145 ISA_MIPS32R2
, CPU_MIPS32R2
},
15146 /* Deprecated forms of the above. */
15147 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15148 ISA_MIPS32R2
, CPU_MIPS32R2
},
15149 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15150 ISA_MIPS32R2
, CPU_MIPS32R2
},
15151 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15152 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15153 ISA_MIPS32R2
, CPU_MIPS32R2
},
15154 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15155 ISA_MIPS32R2
, CPU_MIPS32R2
},
15156 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15157 ISA_MIPS32R2
, CPU_MIPS32R2
},
15158 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15159 ISA_MIPS32R2
, CPU_MIPS32R2
},
15160 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15161 ISA_MIPS32R2
, CPU_MIPS32R2
},
15162 /* Deprecated forms of the above. */
15163 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15164 ISA_MIPS32R2
, CPU_MIPS32R2
},
15165 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15166 ISA_MIPS32R2
, CPU_MIPS32R2
},
15169 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15170 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15171 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15172 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15174 /* Broadcom SB-1 CPU core */
15175 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15176 ISA_MIPS64
, CPU_SB1
},
15177 /* Broadcom SB-1A CPU core */
15178 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15179 ISA_MIPS64
, CPU_SB1
},
15181 /* MIPS 64 Release 2 */
15183 /* Cavium Networks Octeon CPU core */
15184 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15191 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15192 with a final "000" replaced by "k". Ignore case.
15194 Note: this function is shared between GCC and GAS. */
15197 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15199 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15200 given
++, canonical
++;
15202 return ((*given
== 0 && *canonical
== 0)
15203 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15207 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15208 CPU name. We've traditionally allowed a lot of variation here.
15210 Note: this function is shared between GCC and GAS. */
15213 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15215 /* First see if the name matches exactly, or with a final "000"
15216 turned into "k". */
15217 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15220 /* If not, try comparing based on numerical designation alone.
15221 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15222 if (TOLOWER (*given
) == 'r')
15224 if (!ISDIGIT (*given
))
15227 /* Skip over some well-known prefixes in the canonical name,
15228 hoping to find a number there too. */
15229 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15231 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15233 else if (TOLOWER (canonical
[0]) == 'r')
15236 return mips_strict_matching_cpu_name_p (canonical
, given
);
15240 /* Parse an option that takes the name of a processor as its argument.
15241 OPTION is the name of the option and CPU_STRING is the argument.
15242 Return the corresponding processor enumeration if the CPU_STRING is
15243 recognized, otherwise report an error and return null.
15245 A similar function exists in GCC. */
15247 static const struct mips_cpu_info
*
15248 mips_parse_cpu (const char *option
, const char *cpu_string
)
15250 const struct mips_cpu_info
*p
;
15252 /* 'from-abi' selects the most compatible architecture for the given
15253 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15254 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15255 version. Look first at the -mgp options, if given, otherwise base
15256 the choice on MIPS_DEFAULT_64BIT.
15258 Treat NO_ABI like the EABIs. One reason to do this is that the
15259 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15260 architecture. This code picks MIPS I for 'mips' and MIPS III for
15261 'mips64', just as we did in the days before 'from-abi'. */
15262 if (strcasecmp (cpu_string
, "from-abi") == 0)
15264 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15265 return mips_cpu_info_from_isa (ISA_MIPS1
);
15267 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15268 return mips_cpu_info_from_isa (ISA_MIPS3
);
15270 if (file_mips_gp32
>= 0)
15271 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15273 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15278 /* 'default' has traditionally been a no-op. Probably not very useful. */
15279 if (strcasecmp (cpu_string
, "default") == 0)
15282 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15283 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15286 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15290 /* Return the canonical processor information for ISA (a member of the
15291 ISA_MIPS* enumeration). */
15293 static const struct mips_cpu_info
*
15294 mips_cpu_info_from_isa (int isa
)
15298 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15299 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15300 && isa
== mips_cpu_info_table
[i
].isa
)
15301 return (&mips_cpu_info_table
[i
]);
15306 static const struct mips_cpu_info
*
15307 mips_cpu_info_from_arch (int arch
)
15311 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15312 if (arch
== mips_cpu_info_table
[i
].cpu
)
15313 return (&mips_cpu_info_table
[i
]);
15319 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15323 fprintf (stream
, "%24s", "");
15328 fprintf (stream
, ", ");
15332 if (*col_p
+ strlen (string
) > 72)
15334 fprintf (stream
, "\n%24s", "");
15338 fprintf (stream
, "%s", string
);
15339 *col_p
+= strlen (string
);
15345 md_show_usage (FILE *stream
)
15350 fprintf (stream
, _("\
15352 -EB generate big endian output\n\
15353 -EL generate little endian output\n\
15354 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15355 -G NUM allow referencing objects up to NUM bytes\n\
15356 implicitly with the gp register [default 8]\n"));
15357 fprintf (stream
, _("\
15358 -mips1 generate MIPS ISA I instructions\n\
15359 -mips2 generate MIPS ISA II instructions\n\
15360 -mips3 generate MIPS ISA III instructions\n\
15361 -mips4 generate MIPS ISA IV instructions\n\
15362 -mips5 generate MIPS ISA V instructions\n\
15363 -mips32 generate MIPS32 ISA instructions\n\
15364 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15365 -mips64 generate MIPS64 ISA instructions\n\
15366 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15367 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15371 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15372 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15373 show (stream
, "from-abi", &column
, &first
);
15374 fputc ('\n', stream
);
15376 fprintf (stream
, _("\
15377 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15378 -no-mCPU don't generate code specific to CPU.\n\
15379 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15383 show (stream
, "3900", &column
, &first
);
15384 show (stream
, "4010", &column
, &first
);
15385 show (stream
, "4100", &column
, &first
);
15386 show (stream
, "4650", &column
, &first
);
15387 fputc ('\n', stream
);
15389 fprintf (stream
, _("\
15390 -mips16 generate mips16 instructions\n\
15391 -no-mips16 do not generate mips16 instructions\n"));
15392 fprintf (stream
, _("\
15393 -msmartmips generate smartmips instructions\n\
15394 -mno-smartmips do not generate smartmips instructions\n"));
15395 fprintf (stream
, _("\
15396 -mdsp generate DSP instructions\n\
15397 -mno-dsp do not generate DSP instructions\n"));
15398 fprintf (stream
, _("\
15399 -mdspr2 generate DSP R2 instructions\n\
15400 -mno-dspr2 do not generate DSP R2 instructions\n"));
15401 fprintf (stream
, _("\
15402 -mmt generate MT instructions\n\
15403 -mno-mt do not generate MT instructions\n"));
15404 fprintf (stream
, _("\
15405 -mfix-vr4120 work around certain VR4120 errata\n\
15406 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15407 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15408 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15409 -msym32 assume all symbols have 32-bit values\n\
15410 -O0 remove unneeded NOPs, do not swap branches\n\
15411 -O remove unneeded NOPs and swap branches\n\
15412 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15413 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15414 fprintf (stream
, _("\
15415 -mhard-float allow floating-point instructions\n\
15416 -msoft-float do not allow floating-point instructions\n\
15417 -msingle-float only allow 32-bit floating-point operations\n\
15418 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15419 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15422 fprintf (stream
, _("\
15423 -KPIC, -call_shared generate SVR4 position independent code\n\
15424 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15425 -mvxworks-pic generate VxWorks position independent code\n\
15426 -non_shared do not generate code that can operate with DSOs\n\
15427 -xgot assume a 32 bit GOT\n\
15428 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15429 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15430 position dependent (non shared) code\n\
15431 -mabi=ABI create ABI conformant object file for:\n"));
15435 show (stream
, "32", &column
, &first
);
15436 show (stream
, "o64", &column
, &first
);
15437 show (stream
, "n32", &column
, &first
);
15438 show (stream
, "64", &column
, &first
);
15439 show (stream
, "eabi", &column
, &first
);
15441 fputc ('\n', stream
);
15443 fprintf (stream
, _("\
15444 -32 create o32 ABI object file (default)\n\
15445 -n32 create n32 ABI object file\n\
15446 -64 create 64 ABI object file\n"));
15451 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15453 if (HAVE_64BIT_SYMBOLS
)
15456 return dwarf2_format_64bit_irix
;
15458 return dwarf2_format_64bit
;
15462 return dwarf2_format_32bit
;
15466 mips_dwarf2_addr_size (void)
15468 if (HAVE_64BIT_SYMBOLS
)
15474 /* Standard calling conventions leave the CFA at SP on entry. */
15476 mips_cfi_frame_initial_instructions (void)
15478 cfi_add_CFA_def_cfa_register (SP
);
15482 tc_mips_regname_to_dw2regnum (char *regname
)
15484 unsigned int regnum
= -1;
15487 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))