1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* This is the set of options which may be modified by the .set
117 pseudo-op. We use a struct so that .set push and .set pop are more
120 struct mips_set_options
122 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
123 if it has not been initialized. Changed by `.set mipsN', and the
124 -mipsN command line option, and the default CPU. */
126 /* Whether we are assembling for the mips16 processor. 0 if we are
127 not, 1 if we are, and -1 if the value has not been initialized.
128 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
129 -nomips16 command line options, and the default CPU. */
131 /* Non-zero if we should not reorder instructions. Changed by `.set
132 reorder' and `.set noreorder'. */
134 /* Non-zero if we should not permit the $at ($1) register to be used
135 in instructions. Changed by `.set at' and `.set noat'. */
137 /* Non-zero if we should warn when a macro instruction expands into
138 more than one machine instruction. Changed by `.set nomacro' and
140 int warn_about_macros
;
141 /* Non-zero if we should not move instructions. Changed by `.set
142 move', `.set volatile', `.set nomove', and `.set novolatile'. */
144 /* Non-zero if we should not optimize branches by moving the target
145 of the branch into the delay slot. Actually, we don't perform
146 this optimization anyhow. Changed by `.set bopt' and `.set
149 /* Non-zero if we should not autoextend mips16 instructions.
150 Changed by `.set autoextend' and `.set noautoextend'. */
154 /* This is the struct we use to hold the current set of options. Note
155 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
156 -1 to indicate that they have not been initialized. */
158 static struct mips_set_options mips_opts
=
160 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
163 /* These variables are filled in with the masks of registers used.
164 The object format code reads them and puts them in the appropriate
166 unsigned long mips_gprmask
;
167 unsigned long mips_cprmask
[4];
169 /* MIPS ISA we are using for this output file. */
170 static int file_mips_isa
= ISA_UNKNOWN
;
172 /* The argument of the -mcpu= flag. Historical for code generation. */
173 static int mips_cpu
= CPU_UNKNOWN
;
175 /* The argument of the -march= flag. The architecture we are assembling. */
176 static int mips_arch
= CPU_UNKNOWN
;
178 /* The argument of the -mtune= flag. The architecture for which we
180 static int mips_tune
= CPU_UNKNOWN
;
182 /* The ABI to use. */
193 static enum mips_abi_level mips_abi
= NO_ABI
;
195 /* Whether we should mark the file EABI64 or EABI32. */
196 static int mips_eabi64
= 0;
198 /* If they asked for mips1 or mips2 and a cpu that is
199 mips3 or greater, then mark the object file 32BITMODE. */
200 static int mips_32bitmode
= 0;
202 /* True if -mgp32 was passed. */
203 static int mips_gp32
= 0;
205 /* True if -mfp32 was passed. */
206 static int mips_fp32
= 0;
208 /* Some ISA's have delay slots for instructions which read or write
209 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
210 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
211 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
212 delay slot in this ISA. The uses of this macro assume that any
213 ISA that has delay slots for one of these, has them for all. They
214 also assume that ISAs which don't have delays for these insns, don't
215 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
216 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
218 || (ISA) == ISA_MIPS2 \
219 || (ISA) == ISA_MIPS3 \
222 /* Return true if ISA supports 64 bit gp register instructions. */
223 #define ISA_HAS_64BIT_REGS(ISA) ( \
225 || (ISA) == ISA_MIPS4 \
226 || (ISA) == ISA_MIPS5 \
227 || (ISA) == ISA_MIPS64 \
230 #define HAVE_32BIT_GPRS \
232 || mips_abi == O32_ABI \
233 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
235 #define HAVE_32BIT_FPRS \
237 || mips_abi == O32_ABI \
238 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
240 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
241 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
243 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
245 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
247 /* We can only have 64bit addresses if the object file format
249 #define HAVE_32BIT_ADDRESSES \
251 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
252 || ! HAVE_64BIT_OBJECTS) \
253 && mips_pic != EMBEDDED_PIC))
255 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
257 /* Whether the processor uses hardware interlocks to protect
258 reads from the HI and LO registers, and thus does not
259 require nops to be inserted. */
261 #define hilo_interlocks (mips_arch == CPU_R4010 \
262 || mips_arch == CPU_SB1 \
265 /* Whether the processor uses hardware interlocks to protect reads
266 from the GPRs, and thus does not require nops to be inserted. */
267 #define gpr_interlocks \
268 (mips_opts.isa != ISA_MIPS1 \
269 || mips_arch == CPU_R3900)
271 /* As with other "interlocks" this is used by hardware that has FP
272 (co-processor) interlocks. */
273 /* Itbl support may require additional care here. */
274 #define cop_interlocks (mips_arch == CPU_R4300 \
275 || mips_arch == CPU_SB1 \
278 /* Is this a mfhi or mflo instruction? */
279 #define MF_HILO_INSN(PINFO) \
280 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
282 /* MIPS PIC level. */
286 /* Do not generate PIC code. */
289 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
290 not sure what it is supposed to do. */
293 /* Generate PIC code as in the SVR4 MIPS ABI. */
296 /* Generate PIC code without using a global offset table: the data
297 segment has a maximum size of 64K, all data references are off
298 the $gp register, and all text references are PC relative. This
299 is used on some embedded systems. */
303 static enum mips_pic_level mips_pic
;
305 /* Warn about all NOPS that the assembler generates. */
306 static int warn_nops
= 0;
308 /* 1 if we should generate 32 bit offsets from the GP register in
309 SVR4_PIC mode. Currently has no meaning in other modes. */
310 static int mips_big_got
;
312 /* 1 if trap instructions should used for overflow rather than break
314 static int mips_trap
;
316 /* 1 if double width floating point constants should not be constructed
317 by assembling two single width halves into two single width floating
318 point registers which just happen to alias the double width destination
319 register. On some architectures this aliasing can be disabled by a bit
320 in the status register, and the setting of this bit cannot be determined
321 automatically at assemble time. */
322 static int mips_disable_float_construction
;
324 /* Non-zero if any .set noreorder directives were used. */
326 static int mips_any_noreorder
;
328 /* Non-zero if nops should be inserted when the register referenced in
329 an mfhi/mflo instruction is read in the next two instructions. */
330 static int mips_7000_hilo_fix
;
332 /* The size of the small data section. */
333 static unsigned int g_switch_value
= 8;
334 /* Whether the -G option was used. */
335 static int g_switch_seen
= 0;
340 /* If we can determine in advance that GP optimization won't be
341 possible, we can skip the relaxation stuff that tries to produce
342 GP-relative references. This makes delay slot optimization work
345 This function can only provide a guess, but it seems to work for
346 gcc output. It needs to guess right for gcc, otherwise gcc
347 will put what it thinks is a GP-relative instruction in a branch
350 I don't know if a fix is needed for the SVR4_PIC mode. I've only
351 fixed it for the non-PIC mode. KR 95/04/07 */
352 static int nopic_need_relax
PARAMS ((symbolS
*, int));
354 /* handle of the OPCODE hash table */
355 static struct hash_control
*op_hash
= NULL
;
357 /* The opcode hash table we use for the mips16. */
358 static struct hash_control
*mips16_op_hash
= NULL
;
360 /* This array holds the chars that always start a comment. If the
361 pre-processor is disabled, these aren't very useful */
362 const char comment_chars
[] = "#";
364 /* This array holds the chars that only start a comment at the beginning of
365 a line. If the line seems to have the form '# 123 filename'
366 .line and .file directives will appear in the pre-processed output */
367 /* Note that input_file.c hand checks for '#' at the beginning of the
368 first line of the input file. This is because the compiler outputs
369 #NO_APP at the beginning of its output. */
370 /* Also note that C style comments are always supported. */
371 const char line_comment_chars
[] = "#";
373 /* This array holds machine specific line separator characters. */
374 const char line_separator_chars
[] = ";";
376 /* Chars that can be used to separate mant from exp in floating point nums */
377 const char EXP_CHARS
[] = "eE";
379 /* Chars that mean this number is a floating point constant */
382 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
384 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
385 changed in read.c . Ideally it shouldn't have to know about it at all,
386 but nothing is ideal around here.
389 static char *insn_error
;
391 static int auto_align
= 1;
393 /* When outputting SVR4 PIC code, the assembler needs to know the
394 offset in the stack frame from which to restore the $gp register.
395 This is set by the .cprestore pseudo-op, and saved in this
397 static offsetT mips_cprestore_offset
= -1;
399 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
400 more optimizations, it can use a register value instead of a memory-saved
401 offset and even an other than GP as global pointer. */
402 static offsetT mips_cpreturn_offset
= -1;
403 static int mips_cpreturn_register
= -1;
404 static int mips_gp_register
= GP
;
406 /* This is the register which holds the stack frame, as set by the
407 .frame pseudo-op. This is needed to implement .cprestore. */
408 static int mips_frame_reg
= SP
;
410 /* To output NOP instructions correctly, we need to keep information
411 about the previous two instructions. */
413 /* Whether we are optimizing. The default value of 2 means to remove
414 unneeded NOPs and swap branch instructions when possible. A value
415 of 1 means to not swap branches. A value of 0 means to always
417 static int mips_optimize
= 2;
419 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
420 equivalent to seeing no -g option at all. */
421 static int mips_debug
= 0;
423 /* The previous instruction. */
424 static struct mips_cl_insn prev_insn
;
426 /* The instruction before prev_insn. */
427 static struct mips_cl_insn prev_prev_insn
;
429 /* If we don't want information for prev_insn or prev_prev_insn, we
430 point the insn_mo field at this dummy integer. */
431 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
433 /* Non-zero if prev_insn is valid. */
434 static int prev_insn_valid
;
436 /* The frag for the previous instruction. */
437 static struct frag
*prev_insn_frag
;
439 /* The offset into prev_insn_frag for the previous instruction. */
440 static long prev_insn_where
;
442 /* The reloc type for the previous instruction, if any. */
443 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
445 /* The reloc for the previous instruction, if any. */
446 static fixS
*prev_insn_fixp
[3];
448 /* Non-zero if the previous instruction was in a delay slot. */
449 static int prev_insn_is_delay_slot
;
451 /* Non-zero if the previous instruction was in a .set noreorder. */
452 static int prev_insn_unreordered
;
454 /* Non-zero if the previous instruction uses an extend opcode (if
456 static int prev_insn_extended
;
458 /* Non-zero if the previous previous instruction was in a .set
460 static int prev_prev_insn_unreordered
;
462 /* If this is set, it points to a frag holding nop instructions which
463 were inserted before the start of a noreorder section. If those
464 nops turn out to be unnecessary, the size of the frag can be
466 static fragS
*prev_nop_frag
;
468 /* The number of nop instructions we created in prev_nop_frag. */
469 static int prev_nop_frag_holds
;
471 /* The number of nop instructions that we know we need in
473 static int prev_nop_frag_required
;
475 /* The number of instructions we've seen since prev_nop_frag. */
476 static int prev_nop_frag_since
;
478 /* For ECOFF and ELF, relocations against symbols are done in two
479 parts, with a HI relocation and a LO relocation. Each relocation
480 has only 16 bits of space to store an addend. This means that in
481 order for the linker to handle carries correctly, it must be able
482 to locate both the HI and the LO relocation. This means that the
483 relocations must appear in order in the relocation table.
485 In order to implement this, we keep track of each unmatched HI
486 relocation. We then sort them so that they immediately precede the
487 corresponding LO relocation. */
492 struct mips_hi_fixup
*next
;
495 /* The section this fixup is in. */
499 /* The list of unmatched HI relocs. */
501 static struct mips_hi_fixup
*mips_hi_fixup_list
;
503 /* Map normal MIPS register numbers to mips16 register numbers. */
505 #define X ILLEGAL_REG
506 static const int mips32_to_16_reg_map
[] =
508 X
, X
, 2, 3, 4, 5, 6, 7,
509 X
, X
, X
, X
, X
, X
, X
, X
,
510 0, 1, X
, X
, X
, X
, X
, X
,
511 X
, X
, X
, X
, X
, X
, X
, X
515 /* Map mips16 register numbers to normal MIPS register numbers. */
517 static const unsigned int mips16_to_32_reg_map
[] =
519 16, 17, 2, 3, 4, 5, 6, 7
522 /* Since the MIPS does not have multiple forms of PC relative
523 instructions, we do not have to do relaxing as is done on other
524 platforms. However, we do have to handle GP relative addressing
525 correctly, which turns out to be a similar problem.
527 Every macro that refers to a symbol can occur in (at least) two
528 forms, one with GP relative addressing and one without. For
529 example, loading a global variable into a register generally uses
530 a macro instruction like this:
532 If i can be addressed off the GP register (this is true if it is in
533 the .sbss or .sdata section, or if it is known to be smaller than
534 the -G argument) this will generate the following instruction:
536 This instruction will use a GPREL reloc. If i can not be addressed
537 off the GP register, the following instruction sequence will be used:
540 In this case the first instruction will have a HI16 reloc, and the
541 second reloc will have a LO16 reloc. Both relocs will be against
544 The issue here is that we may not know whether i is GP addressable
545 until after we see the instruction that uses it. Therefore, we
546 want to be able to choose the final instruction sequence only at
547 the end of the assembly. This is similar to the way other
548 platforms choose the size of a PC relative instruction only at the
551 When generating position independent code we do not use GP
552 addressing in quite the same way, but the issue still arises as
553 external symbols and local symbols must be handled differently.
555 We handle these issues by actually generating both possible
556 instruction sequences. The longer one is put in a frag_var with
557 type rs_machine_dependent. We encode what to do with the frag in
558 the subtype field. We encode (1) the number of existing bytes to
559 replace, (2) the number of new bytes to use, (3) the offset from
560 the start of the existing bytes to the first reloc we must generate
561 (that is, the offset is applied from the start of the existing
562 bytes after they are replaced by the new bytes, if any), (4) the
563 offset from the start of the existing bytes to the second reloc,
564 (5) whether a third reloc is needed (the third reloc is always four
565 bytes after the second reloc), and (6) whether to warn if this
566 variant is used (this is sometimes needed if .set nomacro or .set
567 noat is in effect). All these numbers are reasonably small.
569 Generating two instruction sequences must be handled carefully to
570 ensure that delay slots are handled correctly. Fortunately, there
571 are a limited number of cases. When the second instruction
572 sequence is generated, append_insn is directed to maintain the
573 existing delay slot information, so it continues to apply to any
574 code after the second instruction sequence. This means that the
575 second instruction sequence must not impose any requirements not
576 required by the first instruction sequence.
578 These variant frags are then handled in functions called by the
579 machine independent code. md_estimate_size_before_relax returns
580 the final size of the frag. md_convert_frag sets up the final form
581 of the frag. tc_gen_reloc adjust the first reloc and adds a second
583 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
587 | (((reloc1) + 64) << 9) \
588 | (((reloc2) + 64) << 2) \
589 | ((reloc3) ? (1 << 1) : 0) \
591 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
592 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
593 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
594 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
595 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
596 #define RELAX_WARN(i) ((i) & 1)
598 /* For mips16 code, we use an entirely different form of relaxation.
599 mips16 supports two versions of most instructions which take
600 immediate values: a small one which takes some small value, and a
601 larger one which takes a 16 bit value. Since branches also follow
602 this pattern, relaxing these values is required.
604 We can assemble both mips16 and normal MIPS code in a single
605 object. Therefore, we need to support this type of relaxation at
606 the same time that we support the relaxation described above. We
607 use the high bit of the subtype field to distinguish these cases.
609 The information we store for this type of relaxation is the
610 argument code found in the opcode file for this relocation, whether
611 the user explicitly requested a small or extended form, and whether
612 the relocation is in a jump or jal delay slot. That tells us the
613 size of the value, and how it should be stored. We also store
614 whether the fragment is considered to be extended or not. We also
615 store whether this is known to be a branch to a different section,
616 whether we have tried to relax this frag yet, and whether we have
617 ever extended a PC relative fragment because of a shift count. */
618 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
621 | ((small) ? 0x100 : 0) \
622 | ((ext) ? 0x200 : 0) \
623 | ((dslot) ? 0x400 : 0) \
624 | ((jal_dslot) ? 0x800 : 0))
625 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
626 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
627 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
628 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
629 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
630 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
631 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
632 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
633 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
634 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
635 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
636 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
638 /* Prototypes for static functions. */
641 #define internalError() \
642 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
644 #define internalError() as_fatal (_("MIPS internal Error"));
647 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
649 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
650 unsigned int reg
, enum mips_regclass
class));
651 static int reg_needs_delay
PARAMS ((unsigned int));
652 static void mips16_mark_labels
PARAMS ((void));
653 static void append_insn
PARAMS ((char *place
,
654 struct mips_cl_insn
* ip
,
656 bfd_reloc_code_real_type
*r
,
658 static void mips_no_prev_insn
PARAMS ((int));
659 static void mips_emit_delays
PARAMS ((boolean
));
661 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
662 const char *name
, const char *fmt
,
665 static void macro_build ();
667 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
668 const char *, const char *,
670 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
671 expressionS
* ep
, int regnum
));
672 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
673 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
675 static void load_register
PARAMS ((int *, int, expressionS
*, int));
676 static void load_address
PARAMS ((int *, int, expressionS
*, int, int *));
677 static void move_register
PARAMS ((int *, int, int));
678 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
679 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
680 #ifdef LOSING_COMPILER
681 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
683 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
684 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
685 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
686 boolean
, boolean
, unsigned long *,
687 boolean
*, unsigned short *));
688 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
689 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
690 static void my_getExpression
PARAMS ((expressionS
*, char *));
691 static int support_64bit_objects
PARAMS((void));
692 static symbolS
*get_symbol
PARAMS ((void));
693 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
694 static void s_align
PARAMS ((int));
695 static void s_change_sec
PARAMS ((int));
696 static void s_cons
PARAMS ((int));
697 static void s_float_cons
PARAMS ((int));
698 static void s_mips_globl
PARAMS ((int));
699 static void s_option
PARAMS ((int));
700 static void s_mipsset
PARAMS ((int));
701 static void s_abicalls
PARAMS ((int));
702 static void s_cpload
PARAMS ((int));
703 static void s_cpsetup
PARAMS ((int));
704 static void s_cplocal
PARAMS ((int));
705 static void s_cprestore
PARAMS ((int));
706 static void s_cpreturn
PARAMS ((int));
707 static void s_gpvalue
PARAMS ((int));
708 static void s_gpword
PARAMS ((int));
709 static void s_cpadd
PARAMS ((int));
710 static void s_insn
PARAMS ((int));
711 static void md_obj_begin
PARAMS ((void));
712 static void md_obj_end
PARAMS ((void));
713 static long get_number
PARAMS ((void));
714 static void s_mips_ent
PARAMS ((int));
715 static void s_mips_end
PARAMS ((int));
716 static void s_mips_frame
PARAMS ((int));
717 static void s_mips_mask
PARAMS ((int));
718 static void s_mips_stab
PARAMS ((int));
719 static void s_mips_weakext
PARAMS ((int));
720 static void s_file
PARAMS ((int));
721 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
722 static const char *mips_isa_to_str
PARAMS ((int));
723 static const char *mips_cpu_to_str
PARAMS ((int));
724 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
725 static void show
PARAMS ((FILE *, char *, int *, int *));
727 /* Return values of my_getSmallExpression(). */
734 /* Direct relocation creation by %percent_op(). */
753 /* Table and functions used to map between CPU/ISA names, and
754 ISA levels, and CPU numbers. */
758 const char *name
; /* CPU or ISA name. */
759 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
760 int isa
; /* ISA level. */
761 int cpu
; /* CPU number (default CPU if ISA). */
764 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
765 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
766 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
770 The following pseudo-ops from the Kane and Heinrich MIPS book
771 should be defined here, but are currently unsupported: .alias,
772 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
774 The following pseudo-ops from the Kane and Heinrich MIPS book are
775 specific to the type of debugging information being generated, and
776 should be defined by the object format: .aent, .begin, .bend,
777 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
780 The following pseudo-ops from the Kane and Heinrich MIPS book are
781 not MIPS CPU specific, but are also not specific to the object file
782 format. This file is probably the best place to define them, but
783 they are not currently supported: .asm0, .endr, .lab, .repeat,
786 static const pseudo_typeS mips_pseudo_table
[] =
788 /* MIPS specific pseudo-ops. */
789 {"option", s_option
, 0},
790 {"set", s_mipsset
, 0},
791 {"rdata", s_change_sec
, 'r'},
792 {"sdata", s_change_sec
, 's'},
793 {"livereg", s_ignore
, 0},
794 {"abicalls", s_abicalls
, 0},
795 {"cpload", s_cpload
, 0},
796 {"cpsetup", s_cpsetup
, 0},
797 {"cplocal", s_cplocal
, 0},
798 {"cprestore", s_cprestore
, 0},
799 {"cpreturn", s_cpreturn
, 0},
800 {"gpvalue", s_gpvalue
, 0},
801 {"gpword", s_gpword
, 0},
802 {"cpadd", s_cpadd
, 0},
805 /* Relatively generic pseudo-ops that happen to be used on MIPS
807 {"asciiz", stringer
, 1},
808 {"bss", s_change_sec
, 'b'},
811 {"dword", s_cons
, 3},
812 {"weakext", s_mips_weakext
, 0},
814 /* These pseudo-ops are defined in read.c, but must be overridden
815 here for one reason or another. */
816 {"align", s_align
, 0},
818 {"data", s_change_sec
, 'd'},
819 {"double", s_float_cons
, 'd'},
820 {"float", s_float_cons
, 'f'},
821 {"globl", s_mips_globl
, 0},
822 {"global", s_mips_globl
, 0},
823 {"hword", s_cons
, 1},
828 {"short", s_cons
, 1},
829 {"single", s_float_cons
, 'f'},
830 {"stabn", s_mips_stab
, 'n'},
831 {"text", s_change_sec
, 't'},
834 #ifdef MIPS_STABS_ELF
835 { "extern", ecoff_directive_extern
, 0},
841 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
843 /* These pseudo-ops should be defined by the object file format.
844 However, a.out doesn't support them, so we have versions here. */
845 {"aent", s_mips_ent
, 1},
846 {"bgnb", s_ignore
, 0},
847 {"end", s_mips_end
, 0},
848 {"endb", s_ignore
, 0},
849 {"ent", s_mips_ent
, 0},
851 {"fmask", s_mips_mask
, 'F'},
852 {"frame", s_mips_frame
, 0},
853 {"loc", s_ignore
, 0},
854 {"mask", s_mips_mask
, 'R'},
855 {"verstamp", s_ignore
, 0},
859 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
864 pop_insert (mips_pseudo_table
);
865 if (! ECOFF_DEBUGGING
)
866 pop_insert (mips_nonecoff_pseudo_table
);
869 /* Symbols labelling the current insn. */
871 struct insn_label_list
873 struct insn_label_list
*next
;
877 static struct insn_label_list
*insn_labels
;
878 static struct insn_label_list
*free_insn_labels
;
880 static void mips_clear_insn_labels
PARAMS ((void));
883 mips_clear_insn_labels ()
885 register struct insn_label_list
**pl
;
887 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
893 static char *expr_end
;
895 /* Expressions which appear in instructions. These are set by
898 static expressionS imm_expr
;
899 static expressionS offset_expr
;
901 /* Relocs associated with imm_expr and offset_expr. */
903 static bfd_reloc_code_real_type imm_reloc
[3]
904 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
905 static bfd_reloc_code_real_type offset_reloc
[3]
906 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
908 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
910 static boolean imm_unmatched_hi
;
912 /* These are set by mips16_ip if an explicit extension is used. */
914 static boolean mips16_small
, mips16_ext
;
916 #ifdef MIPS_STABS_ELF
917 /* The pdr segment for per procedure frame/regmask info */
923 mips_isa_to_str (isa
)
926 const struct mips_cpu_info
*ci
;
929 ci
= mips_cpu_info_from_isa (isa
);
933 sprintf (s
, "ISA#%d", isa
);
938 mips_cpu_to_str (cpu
)
941 const struct mips_cpu_info
*ci
;
944 ci
= mips_cpu_info_from_cpu (cpu
);
948 sprintf (s
, "CPU#%d", cpu
);
952 /* The default target format to use. */
955 mips_target_format ()
957 switch (OUTPUT_FLAVOR
)
959 case bfd_target_aout_flavour
:
960 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
961 case bfd_target_ecoff_flavour
:
962 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
963 case bfd_target_coff_flavour
:
965 case bfd_target_elf_flavour
:
967 /* This is traditional mips */
968 return (target_big_endian
969 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
970 : "elf32-tradbigmips")
971 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
972 : "elf32-tradlittlemips"));
974 return (target_big_endian
975 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
976 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
977 : "elf32-littlemips"));
985 /* This function is called once, at assembler startup time. It should
986 set up all the tables, etc. that the MD part of the assembler will need. */
991 register const char *retval
= NULL
;
996 int mips_isa_from_cpu
;
997 int target_cpu_had_mips16
= 0;
998 const struct mips_cpu_info
*ci
;
1000 /* GP relative stuff not working for PE */
1001 if (strncmp (TARGET_OS
, "pe", 2) == 0
1002 && g_switch_value
!= 0)
1005 as_bad (_("-G not supported in this configuration."));
1010 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1012 a
= xmalloc (sizeof TARGET_CPU
);
1013 strcpy (a
, TARGET_CPU
);
1014 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1018 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1020 target_cpu_had_mips16
= 1;
1021 cpu
+= sizeof "mips16" - 1;
1024 if (mips_opts
.mips16
< 0)
1025 mips_opts
.mips16
= target_cpu_had_mips16
;
1027 /* Backward compatibility for historic -mcpu= option. Check for
1028 incompatible options, warn if -mcpu is used. */
1029 if (mips_cpu
!= CPU_UNKNOWN
1030 && mips_arch
!= CPU_UNKNOWN
1031 && mips_cpu
!= mips_arch
)
1033 as_fatal (_("The -mcpu option can't be used together with -march. "
1034 "Use -mtune instead of -mcpu."));
1037 if (mips_cpu
!= CPU_UNKNOWN
1038 && mips_tune
!= CPU_UNKNOWN
1039 && mips_cpu
!= mips_tune
)
1041 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1042 "Use -march instead of -mcpu."));
1045 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1047 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1048 assert (ci
!= NULL
);
1049 mips_arch
= ci
->cpu
;
1050 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1051 "-mtune instead."));
1054 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1055 specified on the command line, or some other value if one was.
1056 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1057 the command line, or will be set otherwise if one was. */
1058 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1060 /* We have to check if the isa is the default isa of arch. Otherwise
1061 we'll get invalid object file headers. */
1062 ci
= mips_cpu_info_from_cpu (mips_arch
);
1063 assert (ci
!= NULL
);
1064 if (mips_opts
.isa
!= ci
->isa
)
1066 /* This really should be an error instead of a warning, but old
1067 compilers only have -mcpu which sets both arch and tune. For
1068 now, we discard arch and preserve tune. */
1069 as_warn (_("The -march option is incompatible to -mipsN and "
1070 "therefore ignored."));
1071 if (mips_tune
== CPU_UNKNOWN
)
1072 mips_tune
= mips_arch
;
1073 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1074 assert (ci
!= NULL
);
1075 mips_arch
= ci
->cpu
;
1078 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1080 /* We have ARCH, we need ISA. */
1081 ci
= mips_cpu_info_from_cpu (mips_arch
);
1082 assert (ci
!= NULL
);
1083 mips_opts
.isa
= ci
->isa
;
1085 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1087 /* We have ISA, we need default ARCH. */
1088 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1089 assert (ci
!= NULL
);
1090 mips_arch
= ci
->cpu
;
1094 /* We need to set both ISA and ARCH from target cpu. */
1095 ci
= mips_cpu_info_from_name (cpu
);
1097 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1098 assert (ci
!= NULL
);
1099 mips_opts
.isa
= ci
->isa
;
1100 mips_arch
= ci
->cpu
;
1103 if (mips_tune
== CPU_UNKNOWN
)
1104 mips_tune
= mips_arch
;
1106 ci
= mips_cpu_info_from_cpu (mips_arch
);
1107 assert (ci
!= NULL
);
1108 mips_isa_from_cpu
= ci
->isa
;
1110 /* End of TARGET_CPU processing, get rid of malloced memory
1119 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1120 as_bad (_("trap exception not supported at ISA 1"));
1122 /* Set the EABI kind based on the ISA before the user gets
1123 to change the ISA with directives. This isn't really
1124 the best, but then neither is basing the abi on the isa. */
1125 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1126 && mips_abi
== EABI_ABI
)
1129 /* If they asked for mips1 or mips2 and a cpu that is
1130 mips3 or greater, then mark the object file 32BITMODE. */
1131 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1132 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1133 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1136 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1137 as_warn (_("Could not set architecture and machine"));
1139 file_mips_isa
= mips_opts
.isa
;
1141 op_hash
= hash_new ();
1143 for (i
= 0; i
< NUMOPCODES
;)
1145 const char *name
= mips_opcodes
[i
].name
;
1147 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1150 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1151 mips_opcodes
[i
].name
, retval
);
1152 /* Probably a memory allocation problem? Give up now. */
1153 as_fatal (_("Broken assembler. No assembly attempted."));
1157 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1159 if (!validate_mips_insn (&mips_opcodes
[i
]))
1164 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1167 mips16_op_hash
= hash_new ();
1170 while (i
< bfd_mips16_num_opcodes
)
1172 const char *name
= mips16_opcodes
[i
].name
;
1174 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1176 as_fatal (_("internal: can't hash `%s': %s"),
1177 mips16_opcodes
[i
].name
, retval
);
1180 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1181 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1182 != mips16_opcodes
[i
].match
))
1184 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1185 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1190 while (i
< bfd_mips16_num_opcodes
1191 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1195 as_fatal (_("Broken assembler. No assembly attempted."));
1197 /* We add all the general register names to the symbol table. This
1198 helps us detect invalid uses of them. */
1199 for (i
= 0; i
< 32; i
++)
1203 sprintf (buf
, "$%d", i
);
1204 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1205 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1218 &zero_address_frag
));
1219 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1220 &zero_address_frag
));
1222 mips_no_prev_insn (false);
1225 mips_cprmask
[0] = 0;
1226 mips_cprmask
[1] = 0;
1227 mips_cprmask
[2] = 0;
1228 mips_cprmask
[3] = 0;
1230 /* set the default alignment for the text section (2**2) */
1231 record_alignment (text_section
, 2);
1233 if (USE_GLOBAL_POINTER_OPT
)
1234 bfd_set_gp_size (stdoutput
, g_switch_value
);
1236 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1238 /* On a native system, sections must be aligned to 16 byte
1239 boundaries. When configured for an embedded ELF target, we
1241 if (strcmp (TARGET_OS
, "elf") != 0)
1243 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1244 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1245 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1248 /* Create a .reginfo section for register masks and a .mdebug
1249 section for debugging information. */
1257 subseg
= now_subseg
;
1259 /* The ABI says this section should be loaded so that the
1260 running program can access it. However, we don't load it
1261 if we are configured for an embedded target */
1262 flags
= SEC_READONLY
| SEC_DATA
;
1263 if (strcmp (TARGET_OS
, "elf") != 0)
1264 flags
|= SEC_ALLOC
| SEC_LOAD
;
1268 sec
= subseg_new (".reginfo", (subsegT
) 0);
1270 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1271 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1274 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1279 /* The 64-bit ABI uses a .MIPS.options section rather than
1280 .reginfo section. */
1281 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1282 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1283 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1286 /* Set up the option header. */
1288 Elf_Internal_Options opthdr
;
1291 opthdr
.kind
= ODK_REGINFO
;
1292 opthdr
.size
= (sizeof (Elf_External_Options
)
1293 + sizeof (Elf64_External_RegInfo
));
1296 f
= frag_more (sizeof (Elf_External_Options
));
1297 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1298 (Elf_External_Options
*) f
);
1300 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1305 if (ECOFF_DEBUGGING
)
1307 sec
= subseg_new (".mdebug", (subsegT
) 0);
1308 (void) bfd_set_section_flags (stdoutput
, sec
,
1309 SEC_HAS_CONTENTS
| SEC_READONLY
);
1310 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1313 #ifdef MIPS_STABS_ELF
1314 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1315 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1316 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1317 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1320 subseg_set (seg
, subseg
);
1324 if (! ECOFF_DEBUGGING
)
1331 if (! ECOFF_DEBUGGING
)
1339 struct mips_cl_insn insn
;
1340 bfd_reloc_code_real_type unused_reloc
[3]
1341 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1343 imm_expr
.X_op
= O_absent
;
1344 imm_unmatched_hi
= false;
1345 offset_expr
.X_op
= O_absent
;
1346 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1347 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1348 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1349 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1350 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1351 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1353 if (mips_opts
.mips16
)
1354 mips16_ip (str
, &insn
);
1357 mips_ip (str
, &insn
);
1358 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1359 str
, insn
.insn_opcode
));
1364 as_bad ("%s `%s'", insn_error
, str
);
1368 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1370 if (mips_opts
.mips16
)
1371 mips16_macro (&insn
);
1377 if (imm_expr
.X_op
!= O_absent
)
1378 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1380 else if (offset_expr
.X_op
!= O_absent
)
1381 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1383 append_insn ((char *) NULL
, &insn
, NULL
, unused_reloc
, false);
1387 /* See whether instruction IP reads register REG. CLASS is the type
1391 insn_uses_reg (ip
, reg
, class)
1392 struct mips_cl_insn
*ip
;
1394 enum mips_regclass
class;
1396 if (class == MIPS16_REG
)
1398 assert (mips_opts
.mips16
);
1399 reg
= mips16_to_32_reg_map
[reg
];
1400 class = MIPS_GR_REG
;
1403 /* Don't report on general register 0, since it never changes. */
1404 if (class == MIPS_GR_REG
&& reg
== 0)
1407 if (class == MIPS_FP_REG
)
1409 assert (! mips_opts
.mips16
);
1410 /* If we are called with either $f0 or $f1, we must check $f0.
1411 This is not optimal, because it will introduce an unnecessary
1412 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1413 need to distinguish reading both $f0 and $f1 or just one of
1414 them. Note that we don't have to check the other way,
1415 because there is no instruction that sets both $f0 and $f1
1416 and requires a delay. */
1417 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1418 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1419 == (reg
&~ (unsigned) 1)))
1421 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1422 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1423 == (reg
&~ (unsigned) 1)))
1426 else if (! mips_opts
.mips16
)
1428 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1429 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1431 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1432 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1437 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1438 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1439 & MIPS16OP_MASK_RX
)]
1442 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1443 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1444 & MIPS16OP_MASK_RY
)]
1447 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1448 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1449 & MIPS16OP_MASK_MOVE32Z
)]
1452 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1454 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1456 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1458 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1459 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1460 & MIPS16OP_MASK_REGR32
) == reg
)
1467 /* This function returns true if modifying a register requires a
1471 reg_needs_delay (reg
)
1474 unsigned long prev_pinfo
;
1476 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1477 if (! mips_opts
.noreorder
1478 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1479 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1480 || (! gpr_interlocks
1481 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1483 /* A load from a coprocessor or from memory. All load
1484 delays delay the use of general register rt for one
1485 instruction on the r3000. The r6000 and r4000 use
1487 /* Itbl support may require additional care here. */
1488 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1489 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1496 /* Mark instruction labels in mips16 mode. This permits the linker to
1497 handle them specially, such as generating jalx instructions when
1498 needed. We also make them odd for the duration of the assembly, in
1499 order to generate the right sort of code. We will make them even
1500 in the adjust_symtab routine, while leaving them marked. This is
1501 convenient for the debugger and the disassembler. The linker knows
1502 to make them odd again. */
1505 mips16_mark_labels ()
1507 if (mips_opts
.mips16
)
1509 struct insn_label_list
*l
;
1512 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1515 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1516 S_SET_OTHER (l
->label
, STO_MIPS16
);
1518 val
= S_GET_VALUE (l
->label
);
1520 S_SET_VALUE (l
->label
, val
+ 1);
1525 /* Output an instruction. PLACE is where to put the instruction; if
1526 it is NULL, this uses frag_more to get room. IP is the instruction
1527 information. ADDRESS_EXPR is an operand of the instruction to be
1528 used with RELOC_TYPE. */
1531 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1533 struct mips_cl_insn
*ip
;
1534 expressionS
*address_expr
;
1535 bfd_reloc_code_real_type
*reloc_type
;
1536 boolean unmatched_hi
;
1538 register unsigned long prev_pinfo
, pinfo
;
1543 /* Mark instruction labels in mips16 mode. */
1544 if (mips_opts
.mips16
)
1545 mips16_mark_labels ();
1547 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1548 pinfo
= ip
->insn_mo
->pinfo
;
1550 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1554 /* If the previous insn required any delay slots, see if we need
1555 to insert a NOP or two. There are eight kinds of possible
1556 hazards, of which an instruction can have at most one type.
1557 (1) a load from memory delay
1558 (2) a load from a coprocessor delay
1559 (3) an unconditional branch delay
1560 (4) a conditional branch delay
1561 (5) a move to coprocessor register delay
1562 (6) a load coprocessor register from memory delay
1563 (7) a coprocessor condition code delay
1564 (8) a HI/LO special register delay
1566 There are a lot of optimizations we could do that we don't.
1567 In particular, we do not, in general, reorder instructions.
1568 If you use gcc with optimization, it will reorder
1569 instructions and generally do much more optimization then we
1570 do here; repeating all that work in the assembler would only
1571 benefit hand written assembly code, and does not seem worth
1574 /* This is how a NOP is emitted. */
1575 #define emit_nop() \
1577 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1578 : md_number_to_chars (frag_more (4), 0, 4))
1580 /* The previous insn might require a delay slot, depending upon
1581 the contents of the current insn. */
1582 if (! mips_opts
.mips16
1583 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1584 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1585 && ! cop_interlocks
)
1586 || (! gpr_interlocks
1587 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1589 /* A load from a coprocessor or from memory. All load
1590 delays delay the use of general register rt for one
1591 instruction on the r3000. The r6000 and r4000 use
1593 /* Itbl support may require additional care here. */
1594 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1595 if (mips_optimize
== 0
1596 || insn_uses_reg (ip
,
1597 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1602 else if (! mips_opts
.mips16
1603 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1604 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1605 && ! cop_interlocks
)
1606 || (mips_opts
.isa
== ISA_MIPS1
1607 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1609 /* A generic coprocessor delay. The previous instruction
1610 modified a coprocessor general or control register. If
1611 it modified a control register, we need to avoid any
1612 coprocessor instruction (this is probably not always
1613 required, but it sometimes is). If it modified a general
1614 register, we avoid using that register.
1616 On the r6000 and r4000 loading a coprocessor register
1617 from memory is interlocked, and does not require a delay.
1619 This case is not handled very well. There is no special
1620 knowledge of CP0 handling, and the coprocessors other
1621 than the floating point unit are not distinguished at
1623 /* Itbl support may require additional care here. FIXME!
1624 Need to modify this to include knowledge about
1625 user specified delays! */
1626 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1628 if (mips_optimize
== 0
1629 || insn_uses_reg (ip
,
1630 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1635 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1637 if (mips_optimize
== 0
1638 || insn_uses_reg (ip
,
1639 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1646 /* We don't know exactly what the previous instruction
1647 does. If the current instruction uses a coprocessor
1648 register, we must insert a NOP. If previous
1649 instruction may set the condition codes, and the
1650 current instruction uses them, we must insert two
1652 /* Itbl support may require additional care here. */
1653 if (mips_optimize
== 0
1654 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1655 && (pinfo
& INSN_READ_COND_CODE
)))
1657 else if (pinfo
& INSN_COP
)
1661 else if (! mips_opts
.mips16
1662 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1663 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1664 && ! cop_interlocks
)
1666 /* The previous instruction sets the coprocessor condition
1667 codes, but does not require a general coprocessor delay
1668 (this means it is a floating point comparison
1669 instruction). If this instruction uses the condition
1670 codes, we need to insert a single NOP. */
1671 /* Itbl support may require additional care here. */
1672 if (mips_optimize
== 0
1673 || (pinfo
& INSN_READ_COND_CODE
))
1677 /* If we're fixing up mfhi/mflo for the r7000 and the
1678 previous insn was an mfhi/mflo and the current insn
1679 reads the register that the mfhi/mflo wrote to, then
1682 else if (mips_7000_hilo_fix
1683 && MF_HILO_INSN (prev_pinfo
)
1684 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1691 /* If we're fixing up mfhi/mflo for the r7000 and the
1692 2nd previous insn was an mfhi/mflo and the current insn
1693 reads the register that the mfhi/mflo wrote to, then
1696 else if (mips_7000_hilo_fix
1697 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1698 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1706 else if (prev_pinfo
& INSN_READ_LO
)
1708 /* The previous instruction reads the LO register; if the
1709 current instruction writes to the LO register, we must
1710 insert two NOPS. Some newer processors have interlocks.
1711 Also the tx39's multiply instructions can be exectuted
1712 immediatly after a read from HI/LO (without the delay),
1713 though the tx39's divide insns still do require the
1715 if (! (hilo_interlocks
1716 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1717 && (mips_optimize
== 0
1718 || (pinfo
& INSN_WRITE_LO
)))
1720 /* Most mips16 branch insns don't have a delay slot.
1721 If a read from LO is immediately followed by a branch
1722 to a write to LO we have a read followed by a write
1723 less than 2 insns away. We assume the target of
1724 a branch might be a write to LO, and insert a nop
1725 between a read and an immediately following branch. */
1726 else if (mips_opts
.mips16
1727 && (mips_optimize
== 0
1728 || (pinfo
& MIPS16_INSN_BRANCH
)))
1731 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1733 /* The previous instruction reads the HI register; if the
1734 current instruction writes to the HI register, we must
1735 insert a NOP. Some newer processors have interlocks.
1736 Also the note tx39's multiply above. */
1737 if (! (hilo_interlocks
1738 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1739 && (mips_optimize
== 0
1740 || (pinfo
& INSN_WRITE_HI
)))
1742 /* Most mips16 branch insns don't have a delay slot.
1743 If a read from HI is immediately followed by a branch
1744 to a write to HI we have a read followed by a write
1745 less than 2 insns away. We assume the target of
1746 a branch might be a write to HI, and insert a nop
1747 between a read and an immediately following branch. */
1748 else if (mips_opts
.mips16
1749 && (mips_optimize
== 0
1750 || (pinfo
& MIPS16_INSN_BRANCH
)))
1754 /* If the previous instruction was in a noreorder section, then
1755 we don't want to insert the nop after all. */
1756 /* Itbl support may require additional care here. */
1757 if (prev_insn_unreordered
)
1760 /* There are two cases which require two intervening
1761 instructions: 1) setting the condition codes using a move to
1762 coprocessor instruction which requires a general coprocessor
1763 delay and then reading the condition codes 2) reading the HI
1764 or LO register and then writing to it (except on processors
1765 which have interlocks). If we are not already emitting a NOP
1766 instruction, we must check for these cases compared to the
1767 instruction previous to the previous instruction. */
1768 if ((! mips_opts
.mips16
1769 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1770 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1771 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1772 && (pinfo
& INSN_READ_COND_CODE
)
1773 && ! cop_interlocks
)
1774 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1775 && (pinfo
& INSN_WRITE_LO
)
1776 && ! (hilo_interlocks
1777 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1778 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1779 && (pinfo
& INSN_WRITE_HI
)
1780 && ! (hilo_interlocks
1781 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1786 if (prev_prev_insn_unreordered
)
1789 if (prev_prev_nop
&& nops
== 0)
1792 /* If we are being given a nop instruction, don't bother with
1793 one of the nops we would otherwise output. This will only
1794 happen when a nop instruction is used with mips_optimize set
1797 && ! mips_opts
.noreorder
1798 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1801 /* Now emit the right number of NOP instructions. */
1802 if (nops
> 0 && ! mips_opts
.noreorder
)
1805 unsigned long old_frag_offset
;
1807 struct insn_label_list
*l
;
1809 old_frag
= frag_now
;
1810 old_frag_offset
= frag_now_fix ();
1812 for (i
= 0; i
< nops
; i
++)
1817 listing_prev_line ();
1818 /* We may be at the start of a variant frag. In case we
1819 are, make sure there is enough space for the frag
1820 after the frags created by listing_prev_line. The
1821 argument to frag_grow here must be at least as large
1822 as the argument to all other calls to frag_grow in
1823 this file. We don't have to worry about being in the
1824 middle of a variant frag, because the variants insert
1825 all needed nop instructions themselves. */
1829 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1833 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1834 symbol_set_frag (l
->label
, frag_now
);
1835 val
= (valueT
) frag_now_fix ();
1836 /* mips16 text labels are stored as odd. */
1837 if (mips_opts
.mips16
)
1839 S_SET_VALUE (l
->label
, val
);
1842 #ifndef NO_ECOFF_DEBUGGING
1843 if (ECOFF_DEBUGGING
)
1844 ecoff_fix_loc (old_frag
, old_frag_offset
);
1847 else if (prev_nop_frag
!= NULL
)
1849 /* We have a frag holding nops we may be able to remove. If
1850 we don't need any nops, we can decrease the size of
1851 prev_nop_frag by the size of one instruction. If we do
1852 need some nops, we count them in prev_nops_required. */
1853 if (prev_nop_frag_since
== 0)
1857 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1858 --prev_nop_frag_holds
;
1861 prev_nop_frag_required
+= nops
;
1865 if (prev_prev_nop
== 0)
1867 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1868 --prev_nop_frag_holds
;
1871 ++prev_nop_frag_required
;
1874 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1875 prev_nop_frag
= NULL
;
1877 ++prev_nop_frag_since
;
1879 /* Sanity check: by the time we reach the second instruction
1880 after prev_nop_frag, we should have used up all the nops
1881 one way or another. */
1882 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1886 if (*reloc_type
> BFD_RELOC_UNUSED
)
1888 /* We need to set up a variant frag. */
1889 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1890 f
= frag_var (rs_machine_dependent
, 4, 0,
1891 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1892 mips16_small
, mips16_ext
,
1894 & INSN_UNCOND_BRANCH_DELAY
),
1895 (*prev_insn_reloc_type
1896 == BFD_RELOC_MIPS16_JMP
)),
1897 make_expr_symbol (address_expr
), (offsetT
) 0,
1900 else if (place
!= NULL
)
1902 else if (mips_opts
.mips16
1904 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1906 /* Make sure there is enough room to swap this instruction with
1907 a following jump instruction. */
1913 if (mips_opts
.mips16
1914 && mips_opts
.noreorder
1915 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1916 as_warn (_("extended instruction in delay slot"));
1921 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
1922 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
1924 if (address_expr
->X_op
== O_constant
)
1928 switch (*reloc_type
)
1931 ip
->insn_opcode
|= address_expr
->X_add_number
;
1934 case BFD_RELOC_MIPS_HIGHEST
:
1935 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
1937 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1940 case BFD_RELOC_MIPS_HIGHER
:
1941 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
1942 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
1945 case BFD_RELOC_HI16_S
:
1946 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
1950 case BFD_RELOC_HI16
:
1951 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
1954 case BFD_RELOC_LO16
:
1955 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1958 case BFD_RELOC_MIPS_JMP
:
1959 if ((address_expr
->X_add_number
& 3) != 0)
1960 as_bad (_("jump to misaligned address (0x%lx)"),
1961 (unsigned long) address_expr
->X_add_number
);
1962 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1965 case BFD_RELOC_MIPS16_JMP
:
1966 if ((address_expr
->X_add_number
& 3) != 0)
1967 as_bad (_("jump to misaligned address (0x%lx)"),
1968 (unsigned long) address_expr
->X_add_number
);
1970 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1971 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1972 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1975 case BFD_RELOC_16_PCREL
:
1976 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1979 case BFD_RELOC_16_PCREL_S2
:
1989 /* Don't generate a reloc if we are writing into a variant frag. */
1992 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1994 (*reloc_type
== BFD_RELOC_16_PCREL
1995 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
1998 /* These relocations can have an addend that won't fit in
1999 4 octets for 64bit assembly. */
2000 if (HAVE_64BIT_GPRS
&&
2001 (*reloc_type
== BFD_RELOC_16
2002 || *reloc_type
== BFD_RELOC_32
2003 || *reloc_type
== BFD_RELOC_MIPS_JMP
2004 || *reloc_type
== BFD_RELOC_HI16_S
2005 || *reloc_type
== BFD_RELOC_LO16
2006 || *reloc_type
== BFD_RELOC_GPREL16
2007 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2008 || *reloc_type
== BFD_RELOC_GPREL32
2009 || *reloc_type
== BFD_RELOC_64
2010 || *reloc_type
== BFD_RELOC_CTOR
2011 || *reloc_type
== BFD_RELOC_MIPS_SUB
2012 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2013 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2014 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2015 || *reloc_type
== BFD_RELOC_MIPS_REL16
2016 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2017 fixp
[0]->fx_no_overflow
= 1;
2021 struct mips_hi_fixup
*hi_fixup
;
2023 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2024 hi_fixup
= ((struct mips_hi_fixup
*)
2025 xmalloc (sizeof (struct mips_hi_fixup
)));
2026 hi_fixup
->fixp
= fixp
[0];
2027 hi_fixup
->seg
= now_seg
;
2028 hi_fixup
->next
= mips_hi_fixup_list
;
2029 mips_hi_fixup_list
= hi_fixup
;
2032 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2034 /* FIXME: This symbol can be one of
2035 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2036 address_expr
->X_op
= O_absent
;
2037 address_expr
->X_add_symbol
= 0;
2038 address_expr
->X_add_number
= 0;
2040 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2041 4, address_expr
, false,
2044 /* These relocations can have an addend that won't fit in
2045 4 octets for 64bit assembly. */
2046 if (HAVE_64BIT_GPRS
&&
2047 (*reloc_type
== BFD_RELOC_16
2048 || *reloc_type
== BFD_RELOC_32
2049 || *reloc_type
== BFD_RELOC_MIPS_JMP
2050 || *reloc_type
== BFD_RELOC_HI16_S
2051 || *reloc_type
== BFD_RELOC_LO16
2052 || *reloc_type
== BFD_RELOC_GPREL16
2053 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2054 || *reloc_type
== BFD_RELOC_GPREL32
2055 || *reloc_type
== BFD_RELOC_64
2056 || *reloc_type
== BFD_RELOC_CTOR
2057 || *reloc_type
== BFD_RELOC_MIPS_SUB
2058 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2059 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2060 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2061 || *reloc_type
== BFD_RELOC_MIPS_REL16
2062 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2063 fixp
[1]->fx_no_overflow
= 1;
2065 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2067 address_expr
->X_op
= O_absent
;
2068 address_expr
->X_add_symbol
= 0;
2069 address_expr
->X_add_number
= 0;
2071 fixp
[2] = fix_new_exp (frag_now
,
2072 f
- frag_now
->fr_literal
, 4,
2073 address_expr
, false,
2076 /* These relocations can have an addend that won't fit in
2077 4 octets for 64bit assembly. */
2078 if (HAVE_64BIT_GPRS
&&
2079 (*reloc_type
== BFD_RELOC_16
2080 || *reloc_type
== BFD_RELOC_32
2081 || *reloc_type
== BFD_RELOC_MIPS_JMP
2082 || *reloc_type
== BFD_RELOC_HI16_S
2083 || *reloc_type
== BFD_RELOC_LO16
2084 || *reloc_type
== BFD_RELOC_GPREL16
2085 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2086 || *reloc_type
== BFD_RELOC_GPREL32
2087 || *reloc_type
== BFD_RELOC_64
2088 || *reloc_type
== BFD_RELOC_CTOR
2089 || *reloc_type
== BFD_RELOC_MIPS_SUB
2090 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2091 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2092 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2093 || *reloc_type
== BFD_RELOC_MIPS_REL16
2094 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2095 fixp
[2]->fx_no_overflow
= 1;
2102 if (! mips_opts
.mips16
)
2103 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2104 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2106 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2107 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2113 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2116 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2119 /* Update the register mask information. */
2120 if (! mips_opts
.mips16
)
2122 if (pinfo
& INSN_WRITE_GPR_D
)
2123 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2124 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2125 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2126 if (pinfo
& INSN_READ_GPR_S
)
2127 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2128 if (pinfo
& INSN_WRITE_GPR_31
)
2129 mips_gprmask
|= 1 << 31;
2130 if (pinfo
& INSN_WRITE_FPR_D
)
2131 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2132 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2133 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2134 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2135 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2136 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2137 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2138 if (pinfo
& INSN_COP
)
2140 /* We don't keep enough information to sort these cases out.
2141 The itbl support does keep this information however, although
2142 we currently don't support itbl fprmats as part of the cop
2143 instruction. May want to add this support in the future. */
2145 /* Never set the bit for $0, which is always zero. */
2146 mips_gprmask
&= ~1 << 0;
2150 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2151 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2152 & MIPS16OP_MASK_RX
);
2153 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2154 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2155 & MIPS16OP_MASK_RY
);
2156 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2157 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2158 & MIPS16OP_MASK_RZ
);
2159 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2160 mips_gprmask
|= 1 << TREG
;
2161 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2162 mips_gprmask
|= 1 << SP
;
2163 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2164 mips_gprmask
|= 1 << RA
;
2165 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2166 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2167 if (pinfo
& MIPS16_INSN_READ_Z
)
2168 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2169 & MIPS16OP_MASK_MOVE32Z
);
2170 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2171 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2172 & MIPS16OP_MASK_REGR32
);
2175 if (place
== NULL
&& ! mips_opts
.noreorder
)
2177 /* Filling the branch delay slot is more complex. We try to
2178 switch the branch with the previous instruction, which we can
2179 do if the previous instruction does not set up a condition
2180 that the branch tests and if the branch is not itself the
2181 target of any branch. */
2182 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2183 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2185 if (mips_optimize
< 2
2186 /* If we have seen .set volatile or .set nomove, don't
2188 || mips_opts
.nomove
!= 0
2189 /* If we had to emit any NOP instructions, then we
2190 already know we can not swap. */
2192 /* If we don't even know the previous insn, we can not
2194 || ! prev_insn_valid
2195 /* If the previous insn is already in a branch delay
2196 slot, then we can not swap. */
2197 || prev_insn_is_delay_slot
2198 /* If the previous previous insn was in a .set
2199 noreorder, we can't swap. Actually, the MIPS
2200 assembler will swap in this situation. However, gcc
2201 configured -with-gnu-as will generate code like
2207 in which we can not swap the bne and INSN. If gcc is
2208 not configured -with-gnu-as, it does not output the
2209 .set pseudo-ops. We don't have to check
2210 prev_insn_unreordered, because prev_insn_valid will
2211 be 0 in that case. We don't want to use
2212 prev_prev_insn_valid, because we do want to be able
2213 to swap at the start of a function. */
2214 || prev_prev_insn_unreordered
2215 /* If the branch is itself the target of a branch, we
2216 can not swap. We cheat on this; all we check for is
2217 whether there is a label on this instruction. If
2218 there are any branches to anything other than a
2219 label, users must use .set noreorder. */
2220 || insn_labels
!= NULL
2221 /* If the previous instruction is in a variant frag, we
2222 can not do the swap. This does not apply to the
2223 mips16, which uses variant frags for different
2225 || (! mips_opts
.mips16
2226 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2227 /* If the branch reads the condition codes, we don't
2228 even try to swap, because in the sequence
2233 we can not swap, and I don't feel like handling that
2235 || (! mips_opts
.mips16
2236 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2237 && (pinfo
& INSN_READ_COND_CODE
))
2238 /* We can not swap with an instruction that requires a
2239 delay slot, becase the target of the branch might
2240 interfere with that instruction. */
2241 || (! mips_opts
.mips16
2242 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2244 /* Itbl support may require additional care here. */
2245 & (INSN_LOAD_COPROC_DELAY
2246 | INSN_COPROC_MOVE_DELAY
2247 | INSN_WRITE_COND_CODE
)))
2248 || (! (hilo_interlocks
2249 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2253 || (! mips_opts
.mips16
2255 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2256 || (! mips_opts
.mips16
2257 && mips_opts
.isa
== ISA_MIPS1
2258 /* Itbl support may require additional care here. */
2259 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2260 /* We can not swap with a branch instruction. */
2262 & (INSN_UNCOND_BRANCH_DELAY
2263 | INSN_COND_BRANCH_DELAY
2264 | INSN_COND_BRANCH_LIKELY
))
2265 /* We do not swap with a trap instruction, since it
2266 complicates trap handlers to have the trap
2267 instruction be in a delay slot. */
2268 || (prev_pinfo
& INSN_TRAP
)
2269 /* If the branch reads a register that the previous
2270 instruction sets, we can not swap. */
2271 || (! mips_opts
.mips16
2272 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2273 && insn_uses_reg (ip
,
2274 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2277 || (! mips_opts
.mips16
2278 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2279 && insn_uses_reg (ip
,
2280 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2283 || (mips_opts
.mips16
2284 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2285 && insn_uses_reg (ip
,
2286 ((prev_insn
.insn_opcode
2288 & MIPS16OP_MASK_RX
),
2290 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2291 && insn_uses_reg (ip
,
2292 ((prev_insn
.insn_opcode
2294 & MIPS16OP_MASK_RY
),
2296 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2297 && insn_uses_reg (ip
,
2298 ((prev_insn
.insn_opcode
2300 & MIPS16OP_MASK_RZ
),
2302 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2303 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2304 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2305 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2306 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2307 && insn_uses_reg (ip
,
2308 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2311 /* If the branch writes a register that the previous
2312 instruction sets, we can not swap (we know that
2313 branches write only to RD or to $31). */
2314 || (! mips_opts
.mips16
2315 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2316 && (((pinfo
& INSN_WRITE_GPR_D
)
2317 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2318 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2319 || ((pinfo
& INSN_WRITE_GPR_31
)
2320 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2323 || (! mips_opts
.mips16
2324 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2325 && (((pinfo
& INSN_WRITE_GPR_D
)
2326 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2327 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2328 || ((pinfo
& INSN_WRITE_GPR_31
)
2329 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2332 || (mips_opts
.mips16
2333 && (pinfo
& MIPS16_INSN_WRITE_31
)
2334 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2335 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2336 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2338 /* If the branch writes a register that the previous
2339 instruction reads, we can not swap (we know that
2340 branches only write to RD or to $31). */
2341 || (! mips_opts
.mips16
2342 && (pinfo
& INSN_WRITE_GPR_D
)
2343 && insn_uses_reg (&prev_insn
,
2344 ((ip
->insn_opcode
>> OP_SH_RD
)
2347 || (! mips_opts
.mips16
2348 && (pinfo
& INSN_WRITE_GPR_31
)
2349 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2350 || (mips_opts
.mips16
2351 && (pinfo
& MIPS16_INSN_WRITE_31
)
2352 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2353 /* If we are generating embedded PIC code, the branch
2354 might be expanded into a sequence which uses $at, so
2355 we can't swap with an instruction which reads it. */
2356 || (mips_pic
== EMBEDDED_PIC
2357 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2358 /* If the previous previous instruction has a load
2359 delay, and sets a register that the branch reads, we
2361 || (! mips_opts
.mips16
2362 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2363 /* Itbl support may require additional care here. */
2364 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2365 || (! gpr_interlocks
2366 && (prev_prev_insn
.insn_mo
->pinfo
2367 & INSN_LOAD_MEMORY_DELAY
)))
2368 && insn_uses_reg (ip
,
2369 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2372 /* If one instruction sets a condition code and the
2373 other one uses a condition code, we can not swap. */
2374 || ((pinfo
& INSN_READ_COND_CODE
)
2375 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2376 || ((pinfo
& INSN_WRITE_COND_CODE
)
2377 && (prev_pinfo
& INSN_READ_COND_CODE
))
2378 /* If the previous instruction uses the PC, we can not
2380 || (mips_opts
.mips16
2381 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2382 /* If the previous instruction was extended, we can not
2384 || (mips_opts
.mips16
&& prev_insn_extended
)
2385 /* If the previous instruction had a fixup in mips16
2386 mode, we can not swap. This normally means that the
2387 previous instruction was a 4 byte branch anyhow. */
2388 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2389 /* If the previous instruction is a sync, sync.l, or
2390 sync.p, we can not swap. */
2391 || (prev_pinfo
& INSN_SYNC
))
2393 /* We could do even better for unconditional branches to
2394 portions of this object file; we could pick up the
2395 instruction at the destination, put it in the delay
2396 slot, and bump the destination address. */
2398 /* Update the previous insn information. */
2399 prev_prev_insn
= *ip
;
2400 prev_insn
.insn_mo
= &dummy_opcode
;
2404 /* It looks like we can actually do the swap. */
2405 if (! mips_opts
.mips16
)
2410 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2411 memcpy (temp
, prev_f
, 4);
2412 memcpy (prev_f
, f
, 4);
2413 memcpy (f
, temp
, 4);
2414 if (prev_insn_fixp
[0])
2416 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2417 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2419 if (prev_insn_fixp
[1])
2421 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2422 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2424 if (prev_insn_fixp
[2])
2426 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2427 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2431 fixp
[0]->fx_frag
= prev_insn_frag
;
2432 fixp
[0]->fx_where
= prev_insn_where
;
2436 fixp
[1]->fx_frag
= prev_insn_frag
;
2437 fixp
[1]->fx_where
= prev_insn_where
;
2441 fixp
[2]->fx_frag
= prev_insn_frag
;
2442 fixp
[2]->fx_where
= prev_insn_where
;
2450 assert (prev_insn_fixp
[0] == NULL
);
2451 assert (prev_insn_fixp
[1] == NULL
);
2452 assert (prev_insn_fixp
[2] == NULL
);
2453 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2454 memcpy (temp
, prev_f
, 2);
2455 memcpy (prev_f
, f
, 2);
2456 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2458 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2459 memcpy (f
, temp
, 2);
2463 memcpy (f
, f
+ 2, 2);
2464 memcpy (f
+ 2, temp
, 2);
2468 fixp
[0]->fx_frag
= prev_insn_frag
;
2469 fixp
[0]->fx_where
= prev_insn_where
;
2473 fixp
[1]->fx_frag
= prev_insn_frag
;
2474 fixp
[1]->fx_where
= prev_insn_where
;
2478 fixp
[2]->fx_frag
= prev_insn_frag
;
2479 fixp
[2]->fx_where
= prev_insn_where
;
2483 /* Update the previous insn information; leave prev_insn
2485 prev_prev_insn
= *ip
;
2487 prev_insn_is_delay_slot
= 1;
2489 /* If that was an unconditional branch, forget the previous
2490 insn information. */
2491 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2493 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2494 prev_insn
.insn_mo
= &dummy_opcode
;
2497 prev_insn_fixp
[0] = NULL
;
2498 prev_insn_fixp
[1] = NULL
;
2499 prev_insn_fixp
[2] = NULL
;
2500 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2501 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2502 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2503 prev_insn_extended
= 0;
2505 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2507 /* We don't yet optimize a branch likely. What we should do
2508 is look at the target, copy the instruction found there
2509 into the delay slot, and increment the branch to jump to
2510 the next instruction. */
2512 /* Update the previous insn information. */
2513 prev_prev_insn
= *ip
;
2514 prev_insn
.insn_mo
= &dummy_opcode
;
2515 prev_insn_fixp
[0] = NULL
;
2516 prev_insn_fixp
[1] = NULL
;
2517 prev_insn_fixp
[2] = NULL
;
2518 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2519 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2520 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2521 prev_insn_extended
= 0;
2525 /* Update the previous insn information. */
2527 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2529 prev_prev_insn
= prev_insn
;
2532 /* Any time we see a branch, we always fill the delay slot
2533 immediately; since this insn is not a branch, we know it
2534 is not in a delay slot. */
2535 prev_insn_is_delay_slot
= 0;
2537 prev_insn_fixp
[0] = fixp
[0];
2538 prev_insn_fixp
[1] = fixp
[1];
2539 prev_insn_fixp
[2] = fixp
[2];
2540 prev_insn_reloc_type
[0] = reloc_type
[0];
2541 prev_insn_reloc_type
[1] = reloc_type
[1];
2542 prev_insn_reloc_type
[2] = reloc_type
[2];
2543 if (mips_opts
.mips16
)
2544 prev_insn_extended
= (ip
->use_extend
2545 || *reloc_type
> BFD_RELOC_UNUSED
);
2548 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2549 prev_insn_unreordered
= 0;
2550 prev_insn_frag
= frag_now
;
2551 prev_insn_where
= f
- frag_now
->fr_literal
;
2552 prev_insn_valid
= 1;
2554 else if (place
== NULL
)
2556 /* We need to record a bit of information even when we are not
2557 reordering, in order to determine the base address for mips16
2558 PC relative relocs. */
2559 prev_prev_insn
= prev_insn
;
2561 prev_insn_reloc_type
[0] = reloc_type
[0];
2562 prev_insn_reloc_type
[1] = reloc_type
[1];
2563 prev_insn_reloc_type
[2] = reloc_type
[2];
2564 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2565 prev_insn_unreordered
= 1;
2568 /* We just output an insn, so the next one doesn't have a label. */
2569 mips_clear_insn_labels ();
2571 /* We must ensure that a fixup associated with an unmatched %hi
2572 reloc does not become a variant frag. Otherwise, the
2573 rearrangement of %hi relocs in frob_file may confuse
2577 frag_wane (frag_now
);
2582 /* This function forgets that there was any previous instruction or
2583 label. If PRESERVE is non-zero, it remembers enough information to
2584 know whether nops are needed before a noreorder section. */
2587 mips_no_prev_insn (preserve
)
2592 prev_insn
.insn_mo
= &dummy_opcode
;
2593 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2594 prev_nop_frag
= NULL
;
2595 prev_nop_frag_holds
= 0;
2596 prev_nop_frag_required
= 0;
2597 prev_nop_frag_since
= 0;
2599 prev_insn_valid
= 0;
2600 prev_insn_is_delay_slot
= 0;
2601 prev_insn_unreordered
= 0;
2602 prev_insn_extended
= 0;
2603 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2604 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2605 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2606 prev_prev_insn_unreordered
= 0;
2607 mips_clear_insn_labels ();
2610 /* This function must be called whenever we turn on noreorder or emit
2611 something other than instructions. It inserts any NOPS which might
2612 be needed by the previous instruction, and clears the information
2613 kept for the previous instructions. The INSNS parameter is true if
2614 instructions are to follow. */
2617 mips_emit_delays (insns
)
2620 if (! mips_opts
.noreorder
)
2625 if ((! mips_opts
.mips16
2626 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2627 && (! cop_interlocks
2628 && (prev_insn
.insn_mo
->pinfo
2629 & (INSN_LOAD_COPROC_DELAY
2630 | INSN_COPROC_MOVE_DELAY
2631 | INSN_WRITE_COND_CODE
))))
2632 || (! hilo_interlocks
2633 && (prev_insn
.insn_mo
->pinfo
2636 || (! mips_opts
.mips16
2638 && (prev_insn
.insn_mo
->pinfo
2639 & INSN_LOAD_MEMORY_DELAY
))
2640 || (! mips_opts
.mips16
2641 && mips_opts
.isa
== ISA_MIPS1
2642 && (prev_insn
.insn_mo
->pinfo
2643 & INSN_COPROC_MEMORY_DELAY
)))
2645 /* Itbl support may require additional care here. */
2647 if ((! mips_opts
.mips16
2648 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2649 && (! cop_interlocks
2650 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2651 || (! hilo_interlocks
2652 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2653 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2656 if (prev_insn_unreordered
)
2659 else if ((! mips_opts
.mips16
2660 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2661 && (! cop_interlocks
2662 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2663 || (! hilo_interlocks
2664 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2665 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2667 /* Itbl support may require additional care here. */
2668 if (! prev_prev_insn_unreordered
)
2674 struct insn_label_list
*l
;
2678 /* Record the frag which holds the nop instructions, so
2679 that we can remove them if we don't need them. */
2680 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2681 prev_nop_frag
= frag_now
;
2682 prev_nop_frag_holds
= nops
;
2683 prev_nop_frag_required
= 0;
2684 prev_nop_frag_since
= 0;
2687 for (; nops
> 0; --nops
)
2692 /* Move on to a new frag, so that it is safe to simply
2693 decrease the size of prev_nop_frag. */
2694 frag_wane (frag_now
);
2698 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2702 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2703 symbol_set_frag (l
->label
, frag_now
);
2704 val
= (valueT
) frag_now_fix ();
2705 /* mips16 text labels are stored as odd. */
2706 if (mips_opts
.mips16
)
2708 S_SET_VALUE (l
->label
, val
);
2713 /* Mark instruction labels in mips16 mode. */
2714 if (mips_opts
.mips16
&& insns
)
2715 mips16_mark_labels ();
2717 mips_no_prev_insn (insns
);
2720 /* Build an instruction created by a macro expansion. This is passed
2721 a pointer to the count of instructions created so far, an
2722 expression, the name of the instruction to build, an operand format
2723 string, and corresponding arguments. */
2727 macro_build (char *place
,
2735 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2744 struct mips_cl_insn insn
;
2745 bfd_reloc_code_real_type r
[3];
2749 va_start (args
, fmt
);
2755 * If the macro is about to expand into a second instruction,
2756 * print a warning if needed. We need to pass ip as a parameter
2757 * to generate a better warning message here...
2759 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2760 as_warn (_("Macro instruction expanded into multiple instructions"));
2763 *counter
+= 1; /* bump instruction counter */
2765 if (mips_opts
.mips16
)
2767 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2772 r
[0] = BFD_RELOC_UNUSED
;
2773 r
[1] = BFD_RELOC_UNUSED
;
2774 r
[2] = BFD_RELOC_UNUSED
;
2775 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2776 assert (insn
.insn_mo
);
2777 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2779 /* Search until we get a match for NAME. */
2782 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2783 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2784 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2785 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2789 assert (insn
.insn_mo
->name
);
2790 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2793 insn
.insn_opcode
= insn
.insn_mo
->match
;
2809 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2813 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2818 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2823 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2828 int tmp
= va_arg (args
, int);
2830 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2831 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2837 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2844 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2848 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2852 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2856 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2860 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2867 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2873 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2874 assert (*r
== BFD_RELOC_MIPS_GPREL
2875 || *r
== BFD_RELOC_MIPS_LITERAL
2876 || *r
== BFD_RELOC_MIPS_HIGHER
2877 || *r
== BFD_RELOC_HI16_S
2878 || *r
== BFD_RELOC_LO16
2879 || *r
== BFD_RELOC_MIPS_GOT16
2880 || *r
== BFD_RELOC_MIPS_CALL16
2881 || *r
== BFD_RELOC_MIPS_GOT_LO16
2882 || *r
== BFD_RELOC_MIPS_CALL_LO16
2883 || (ep
->X_op
== O_subtract
2884 && *r
== BFD_RELOC_PCREL_LO16
));
2888 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2890 && (ep
->X_op
== O_constant
2891 || (ep
->X_op
== O_symbol
2892 && (*r
== BFD_RELOC_MIPS_HIGHEST
2893 || *r
== BFD_RELOC_HI16_S
2894 || *r
== BFD_RELOC_HI16
2895 || *r
== BFD_RELOC_GPREL16
2896 || *r
== BFD_RELOC_MIPS_GOT_HI16
2897 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
2898 || (ep
->X_op
== O_subtract
2899 && *r
== BFD_RELOC_PCREL_HI16_S
)));
2903 assert (ep
!= NULL
);
2905 * This allows macro() to pass an immediate expression for
2906 * creating short branches without creating a symbol.
2907 * Note that the expression still might come from the assembly
2908 * input, in which case the value is not checked for range nor
2909 * is a relocation entry generated (yuck).
2911 if (ep
->X_op
== O_constant
)
2913 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2917 if (mips_pic
== EMBEDDED_PIC
)
2918 *r
= BFD_RELOC_16_PCREL_S2
;
2920 *r
= BFD_RELOC_16_PCREL
;
2924 assert (ep
!= NULL
);
2925 *r
= BFD_RELOC_MIPS_JMP
;
2929 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2938 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2940 append_insn (place
, &insn
, ep
, r
, false);
2944 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2946 int *counter ATTRIBUTE_UNUSED
;
2952 struct mips_cl_insn insn
;
2953 bfd_reloc_code_real_type r
[3]
2954 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2956 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2957 assert (insn
.insn_mo
);
2958 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2960 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2961 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2964 assert (insn
.insn_mo
->name
);
2965 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2968 insn
.insn_opcode
= insn
.insn_mo
->match
;
2969 insn
.use_extend
= false;
2988 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2993 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2997 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3001 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3011 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3018 regno
= va_arg (args
, int);
3019 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3020 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3041 assert (ep
!= NULL
);
3043 if (ep
->X_op
!= O_constant
)
3044 *r
= BFD_RELOC_UNUSED
+ c
;
3047 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
3048 false, false, &insn
.insn_opcode
,
3049 &insn
.use_extend
, &insn
.extend
);
3051 *r
= BFD_RELOC_UNUSED
;
3057 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3064 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3066 append_insn (place
, &insn
, ep
, r
, false);
3070 * Generate a "lui" instruction.
3073 macro_build_lui (place
, counter
, ep
, regnum
)
3079 expressionS high_expr
;
3080 struct mips_cl_insn insn
;
3081 bfd_reloc_code_real_type r
[3]
3082 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3083 CONST
char *name
= "lui";
3084 CONST
char *fmt
= "t,u";
3086 assert (! mips_opts
.mips16
);
3092 high_expr
.X_op
= O_constant
;
3093 high_expr
.X_add_number
= ep
->X_add_number
;
3096 if (high_expr
.X_op
== O_constant
)
3098 /* we can compute the instruction now without a relocation entry */
3099 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3101 *r
= BFD_RELOC_UNUSED
;
3103 else if (! HAVE_NEWABI
)
3105 assert (ep
->X_op
== O_symbol
);
3106 /* _gp_disp is a special case, used from s_cpload. */
3107 assert (mips_pic
== NO_PIC
3108 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3109 *r
= BFD_RELOC_HI16_S
;
3113 * If the macro is about to expand into a second instruction,
3114 * print a warning if needed. We need to pass ip as a parameter
3115 * to generate a better warning message here...
3117 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3118 as_warn (_("Macro instruction expanded into multiple instructions"));
3121 *counter
+= 1; /* bump instruction counter */
3123 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3124 assert (insn
.insn_mo
);
3125 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3126 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3128 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3129 if (*r
== BFD_RELOC_UNUSED
)
3131 insn
.insn_opcode
|= high_expr
.X_add_number
;
3132 append_insn (place
, &insn
, NULL
, r
, false);
3135 append_insn (place
, &insn
, &high_expr
, r
, false);
3139 * Generates code to set the $at register to true (one)
3140 * if reg is less than the immediate expression.
3143 set_at (counter
, reg
, unsignedp
)
3148 if (imm_expr
.X_op
== O_constant
3149 && imm_expr
.X_add_number
>= -0x8000
3150 && imm_expr
.X_add_number
< 0x8000)
3151 macro_build ((char *) NULL
, counter
, &imm_expr
,
3152 unsignedp
? "sltiu" : "slti",
3153 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3156 load_register (counter
, AT
, &imm_expr
, 0);
3157 macro_build ((char *) NULL
, counter
, NULL
,
3158 unsignedp
? "sltu" : "slt",
3159 "d,v,t", AT
, reg
, AT
);
3163 /* Warn if an expression is not a constant. */
3166 check_absolute_expr (ip
, ex
)
3167 struct mips_cl_insn
*ip
;
3170 if (ex
->X_op
== O_big
)
3171 as_bad (_("unsupported large constant"));
3172 else if (ex
->X_op
!= O_constant
)
3173 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3176 /* Count the leading zeroes by performing a binary chop. This is a
3177 bulky bit of source, but performance is a LOT better for the
3178 majority of values than a simple loop to count the bits:
3179 for (lcnt = 0; (lcnt < 32); lcnt++)
3180 if ((v) & (1 << (31 - lcnt)))
3182 However it is not code size friendly, and the gain will drop a bit
3183 on certain cached systems.
3185 #define COUNT_TOP_ZEROES(v) \
3186 (((v) & ~0xffff) == 0 \
3187 ? ((v) & ~0xff) == 0 \
3188 ? ((v) & ~0xf) == 0 \
3189 ? ((v) & ~0x3) == 0 \
3190 ? ((v) & ~0x1) == 0 \
3195 : ((v) & ~0x7) == 0 \
3198 : ((v) & ~0x3f) == 0 \
3199 ? ((v) & ~0x1f) == 0 \
3202 : ((v) & ~0x7f) == 0 \
3205 : ((v) & ~0xfff) == 0 \
3206 ? ((v) & ~0x3ff) == 0 \
3207 ? ((v) & ~0x1ff) == 0 \
3210 : ((v) & ~0x7ff) == 0 \
3213 : ((v) & ~0x3fff) == 0 \
3214 ? ((v) & ~0x1fff) == 0 \
3217 : ((v) & ~0x7fff) == 0 \
3220 : ((v) & ~0xffffff) == 0 \
3221 ? ((v) & ~0xfffff) == 0 \
3222 ? ((v) & ~0x3ffff) == 0 \
3223 ? ((v) & ~0x1ffff) == 0 \
3226 : ((v) & ~0x7ffff) == 0 \
3229 : ((v) & ~0x3fffff) == 0 \
3230 ? ((v) & ~0x1fffff) == 0 \
3233 : ((v) & ~0x7fffff) == 0 \
3236 : ((v) & ~0xfffffff) == 0 \
3237 ? ((v) & ~0x3ffffff) == 0 \
3238 ? ((v) & ~0x1ffffff) == 0 \
3241 : ((v) & ~0x7ffffff) == 0 \
3244 : ((v) & ~0x3fffffff) == 0 \
3245 ? ((v) & ~0x1fffffff) == 0 \
3248 : ((v) & ~0x7fffffff) == 0 \
3253 * This routine generates the least number of instructions neccessary to load
3254 * an absolute expression value into a register.
3257 load_register (counter
, reg
, ep
, dbl
)
3264 expressionS hi32
, lo32
;
3266 if (ep
->X_op
!= O_big
)
3268 assert (ep
->X_op
== O_constant
);
3269 if (ep
->X_add_number
< 0x8000
3270 && (ep
->X_add_number
>= 0
3271 || (ep
->X_add_number
>= -0x8000
3274 || sizeof (ep
->X_add_number
) > 4))))
3276 /* We can handle 16 bit signed values with an addiu to
3277 $zero. No need to ever use daddiu here, since $zero and
3278 the result are always correct in 32 bit mode. */
3279 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3280 (int) BFD_RELOC_LO16
);
3283 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3285 /* We can handle 16 bit unsigned values with an ori to
3287 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3288 (int) BFD_RELOC_LO16
);
3291 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3292 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3293 == ~ (offsetT
) 0x7fffffff))
3296 || sizeof (ep
->X_add_number
) > 4
3297 || (ep
->X_add_number
& 0x80000000) == 0))
3298 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3299 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3302 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3303 == ~ (offsetT
) 0xffffffff)))
3305 /* 32 bit values require an lui. */
3306 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3307 (int) BFD_RELOC_HI16
);
3308 if ((ep
->X_add_number
& 0xffff) != 0)
3309 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3310 (int) BFD_RELOC_LO16
);
3315 /* The value is larger than 32 bits. */
3317 if (HAVE_32BIT_GPRS
)
3319 as_bad (_("Number larger than 32 bits"));
3320 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3321 (int) BFD_RELOC_LO16
);
3325 if (ep
->X_op
!= O_big
)
3328 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3329 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3330 hi32
.X_add_number
&= 0xffffffff;
3332 lo32
.X_add_number
&= 0xffffffff;
3336 assert (ep
->X_add_number
> 2);
3337 if (ep
->X_add_number
== 3)
3338 generic_bignum
[3] = 0;
3339 else if (ep
->X_add_number
> 4)
3340 as_bad (_("Number larger than 64 bits"));
3341 lo32
.X_op
= O_constant
;
3342 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3343 hi32
.X_op
= O_constant
;
3344 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3347 if (hi32
.X_add_number
== 0)
3352 unsigned long hi
, lo
;
3354 if (hi32
.X_add_number
== 0xffffffff)
3356 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3358 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3359 reg
, 0, (int) BFD_RELOC_LO16
);
3362 if (lo32
.X_add_number
& 0x80000000)
3364 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3365 (int) BFD_RELOC_HI16
);
3366 if (lo32
.X_add_number
& 0xffff)
3367 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3368 reg
, reg
, (int) BFD_RELOC_LO16
);
3373 /* Check for 16bit shifted constant. We know that hi32 is
3374 non-zero, so start the mask on the first bit of the hi32
3379 unsigned long himask
, lomask
;
3383 himask
= 0xffff >> (32 - shift
);
3384 lomask
= (0xffff << shift
) & 0xffffffff;
3388 himask
= 0xffff << (shift
- 32);
3391 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3392 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3396 tmp
.X_op
= O_constant
;
3398 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3399 | (lo32
.X_add_number
>> shift
));
3401 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3402 macro_build ((char *) NULL
, counter
, &tmp
,
3403 "ori", "t,r,i", reg
, 0,
3404 (int) BFD_RELOC_LO16
);
3405 macro_build ((char *) NULL
, counter
, NULL
,
3406 (shift
>= 32) ? "dsll32" : "dsll",
3408 (shift
>= 32) ? shift
- 32 : shift
);
3413 while (shift
<= (64 - 16));
3415 /* Find the bit number of the lowest one bit, and store the
3416 shifted value in hi/lo. */
3417 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3418 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3422 while ((lo
& 1) == 0)
3427 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3433 while ((hi
& 1) == 0)
3442 /* Optimize if the shifted value is a (power of 2) - 1. */
3443 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3444 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3446 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3451 /* This instruction will set the register to be all
3453 tmp
.X_op
= O_constant
;
3454 tmp
.X_add_number
= (offsetT
) -1;
3455 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3456 reg
, 0, (int) BFD_RELOC_LO16
);
3460 macro_build ((char *) NULL
, counter
, NULL
,
3461 (bit
>= 32) ? "dsll32" : "dsll",
3463 (bit
>= 32) ? bit
- 32 : bit
);
3465 macro_build ((char *) NULL
, counter
, NULL
,
3466 (shift
>= 32) ? "dsrl32" : "dsrl",
3468 (shift
>= 32) ? shift
- 32 : shift
);
3473 /* Sign extend hi32 before calling load_register, because we can
3474 generally get better code when we load a sign extended value. */
3475 if ((hi32
.X_add_number
& 0x80000000) != 0)
3476 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3477 load_register (counter
, reg
, &hi32
, 0);
3480 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3484 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3493 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3495 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3496 (int) BFD_RELOC_HI16
);
3497 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3504 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3509 mid16
.X_add_number
>>= 16;
3510 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3511 freg
, (int) BFD_RELOC_LO16
);
3512 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3516 if ((lo32
.X_add_number
& 0xffff) != 0)
3517 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3518 (int) BFD_RELOC_LO16
);
3521 /* Load an address into a register. */
3524 load_address (counter
, reg
, ep
, dbl
, used_at
)
3533 if (ep
->X_op
!= O_constant
3534 && ep
->X_op
!= O_symbol
)
3536 as_bad (_("expression too complex"));
3537 ep
->X_op
= O_constant
;
3540 if (ep
->X_op
== O_constant
)
3542 load_register (counter
, reg
, ep
, dbl
);
3546 if (mips_pic
== NO_PIC
)
3548 /* If this is a reference to a GP relative symbol, we want
3549 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3551 lui $reg,<sym> (BFD_RELOC_HI16_S)
3552 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3553 If we have an addend, we always use the latter form.
3555 With 64bit address space and a usable $at we want
3556 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3557 lui $at,<sym> (BFD_RELOC_HI16_S)
3558 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3559 daddiu $at,<sym> (BFD_RELOC_LO16)
3563 If $at is already in use, we use an path which is suboptimal
3564 on superscalar processors.
3565 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3566 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3568 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3570 daddiu $reg,<sym> (BFD_RELOC_LO16)
3572 if (HAVE_64BIT_ADDRESSES
)
3576 /* We don't do GP optimization for now because RELAX_ENCODE can't
3577 hold the data for such large chunks. */
3581 macro_build (p
, counter
, ep
, "lui", "t,u",
3582 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3583 macro_build (p
, counter
, ep
, "lui", "t,u",
3584 AT
, (int) BFD_RELOC_HI16_S
);
3585 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3586 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3587 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3588 AT
, AT
, (int) BFD_RELOC_LO16
);
3589 macro_build (p
, counter
, NULL
, "dsll32", "d,w,<",
3591 macro_build (p
, counter
, NULL
, "dadd", "d,v,t",
3597 macro_build (p
, counter
, ep
, "lui", "t,u",
3598 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3599 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3600 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3601 macro_build (p
, counter
, NULL
, "dsll", "d,w,<",
3603 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3604 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3605 macro_build (p
, counter
, NULL
, "dsll", "d,w,<",
3607 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3608 reg
, reg
, (int) BFD_RELOC_LO16
);
3614 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3615 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3618 macro_build ((char *) NULL
, counter
, ep
,
3619 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3620 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3621 p
= frag_var (rs_machine_dependent
, 8, 0,
3622 RELAX_ENCODE (4, 8, 0, 4, 0,
3623 mips_opts
.warn_about_macros
),
3624 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3626 macro_build_lui (p
, counter
, ep
, reg
);
3629 macro_build (p
, counter
, ep
,
3630 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3631 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3634 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3638 /* If this is a reference to an external symbol, we want
3639 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3641 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3643 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3644 If there is a constant, it must be added in after. */
3645 ex
.X_add_number
= ep
->X_add_number
;
3646 ep
->X_add_number
= 0;
3648 macro_build ((char *) NULL
, counter
, ep
,
3649 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3650 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3651 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3652 p
= frag_var (rs_machine_dependent
, 4, 0,
3653 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3654 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3655 macro_build (p
, counter
, ep
,
3656 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3657 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3658 if (ex
.X_add_number
!= 0)
3660 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3661 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3662 ex
.X_op
= O_constant
;
3663 macro_build ((char *) NULL
, counter
, &ex
,
3664 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3665 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3668 else if (mips_pic
== SVR4_PIC
)
3673 /* This is the large GOT case. If this is a reference to an
3674 external symbol, we want
3675 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3677 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3678 Otherwise, for a reference to a local symbol, we want
3679 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3681 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3682 If there is a constant, it must be added in after. */
3683 ex
.X_add_number
= ep
->X_add_number
;
3684 ep
->X_add_number
= 0;
3685 if (reg_needs_delay (GP
))
3690 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3691 (int) BFD_RELOC_MIPS_GOT_HI16
);
3692 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3693 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3694 "d,v,t", reg
, reg
, GP
);
3695 macro_build ((char *) NULL
, counter
, ep
,
3696 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3697 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3698 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3699 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3700 mips_opts
.warn_about_macros
),
3701 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3704 /* We need a nop before loading from $gp. This special
3705 check is required because the lui which starts the main
3706 instruction stream does not refer to $gp, and so will not
3707 insert the nop which may be required. */
3708 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3711 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3712 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3714 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3716 macro_build (p
, counter
, ep
, HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3717 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3718 if (ex
.X_add_number
!= 0)
3720 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3721 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3722 ex
.X_op
= O_constant
;
3723 macro_build ((char *) NULL
, counter
, &ex
,
3724 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3725 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3728 else if (mips_pic
== EMBEDDED_PIC
)
3731 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3733 macro_build ((char *) NULL
, counter
, ep
,
3734 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3735 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3741 /* Move the contents of register SOURCE into register DEST. */
3744 move_register (counter
, dest
, source
)
3749 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3750 HAVE_32BIT_GPRS
? "addu" : "daddu",
3751 "d,v,t", dest
, source
, 0);
3756 * This routine implements the seemingly endless macro or synthesized
3757 * instructions and addressing modes in the mips assembly language. Many
3758 * of these macros are simple and are similar to each other. These could
3759 * probably be handled by some kind of table or grammer aproach instead of
3760 * this verbose method. Others are not simple macros but are more like
3761 * optimizing code generation.
3762 * One interesting optimization is when several store macros appear
3763 * consecutivly that would load AT with the upper half of the same address.
3764 * The ensuing load upper instructions are ommited. This implies some kind
3765 * of global optimization. We currently only optimize within a single macro.
3766 * For many of the load and store macros if the address is specified as a
3767 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3768 * first load register 'at' with zero and use it as the base register. The
3769 * mips assembler simply uses register $zero. Just one tiny optimization
3774 struct mips_cl_insn
*ip
;
3776 register int treg
, sreg
, dreg
, breg
;
3792 bfd_reloc_code_real_type r
;
3794 int hold_mips_optimize
;
3796 assert (! mips_opts
.mips16
);
3798 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3799 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3800 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3801 mask
= ip
->insn_mo
->mask
;
3803 expr1
.X_op
= O_constant
;
3804 expr1
.X_op_symbol
= NULL
;
3805 expr1
.X_add_symbol
= NULL
;
3806 expr1
.X_add_number
= 1;
3818 mips_emit_delays (true);
3819 ++mips_opts
.noreorder
;
3820 mips_any_noreorder
= 1;
3822 expr1
.X_add_number
= 8;
3823 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3825 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3827 move_register (&icnt
, dreg
, sreg
);
3828 macro_build ((char *) NULL
, &icnt
, NULL
,
3829 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3831 --mips_opts
.noreorder
;
3852 if (imm_expr
.X_op
== O_constant
3853 && imm_expr
.X_add_number
>= -0x8000
3854 && imm_expr
.X_add_number
< 0x8000)
3856 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3857 (int) BFD_RELOC_LO16
);
3860 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3861 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3880 if (imm_expr
.X_op
== O_constant
3881 && imm_expr
.X_add_number
>= 0
3882 && imm_expr
.X_add_number
< 0x10000)
3884 if (mask
!= M_NOR_I
)
3885 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3886 sreg
, (int) BFD_RELOC_LO16
);
3889 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3890 treg
, sreg
, (int) BFD_RELOC_LO16
);
3891 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3897 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3898 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3915 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3921 load_register (&icnt
, AT
, &imm_expr
, 0);
3922 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3930 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3931 likely
? "bgezl" : "bgez",
3937 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3938 likely
? "blezl" : "blez",
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3943 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3944 likely
? "beql" : "beq", "s,t,p", AT
, 0);
3950 /* check for > max integer */
3951 maxnum
= 0x7fffffff;
3952 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
3959 if (imm_expr
.X_op
== O_constant
3960 && imm_expr
.X_add_number
>= maxnum
3961 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
3964 /* result is always false */
3968 as_warn (_("Branch %s is always false (nop)"),
3970 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3975 as_warn (_("Branch likely %s is always false"),
3977 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3982 if (imm_expr
.X_op
!= O_constant
)
3983 as_bad (_("Unsupported large constant"));
3984 imm_expr
.X_add_number
++;
3988 if (mask
== M_BGEL_I
)
3990 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3992 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3993 likely
? "bgezl" : "bgez", "s,p", sreg
);
3996 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3998 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3999 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4002 maxnum
= 0x7fffffff;
4003 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4010 maxnum
= - maxnum
- 1;
4011 if (imm_expr
.X_op
== O_constant
4012 && imm_expr
.X_add_number
<= maxnum
4013 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4016 /* result is always true */
4017 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4021 set_at (&icnt
, sreg
, 0);
4022 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4023 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4033 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4034 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4037 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4039 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4040 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4048 && imm_expr
.X_op
== O_constant
4049 && imm_expr
.X_add_number
== 0xffffffff))
4051 if (imm_expr
.X_op
!= O_constant
)
4052 as_bad (_("Unsupported large constant"));
4053 imm_expr
.X_add_number
++;
4057 if (mask
== M_BGEUL_I
)
4059 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4061 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4063 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4064 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4067 set_at (&icnt
, sreg
, 1);
4068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4069 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4078 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4083 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4084 likely
? "bltzl" : "bltz", "s,p", treg
);
4087 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4088 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4089 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4098 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4105 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4106 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4115 likely
? "blezl" : "blez", "s,p", sreg
);
4120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4121 likely
? "bgezl" : "bgez", "s,p", treg
);
4124 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4125 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4126 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4132 maxnum
= 0x7fffffff;
4133 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4140 if (imm_expr
.X_op
== O_constant
4141 && imm_expr
.X_add_number
>= maxnum
4142 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4144 if (imm_expr
.X_op
!= O_constant
)
4145 as_bad (_("Unsupported large constant"));
4146 imm_expr
.X_add_number
++;
4150 if (mask
== M_BLTL_I
)
4152 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4154 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4155 likely
? "bltzl" : "bltz", "s,p", sreg
);
4158 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 likely
? "blezl" : "blez", "s,p", sreg
);
4164 set_at (&icnt
, sreg
, 0);
4165 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4166 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4174 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4175 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4180 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
4182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4183 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4191 && imm_expr
.X_op
== O_constant
4192 && imm_expr
.X_add_number
== 0xffffffff))
4194 if (imm_expr
.X_op
!= O_constant
)
4195 as_bad (_("Unsupported large constant"));
4196 imm_expr
.X_add_number
++;
4200 if (mask
== M_BLTUL_I
)
4202 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4204 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4206 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4207 likely
? "beql" : "beq",
4211 set_at (&icnt
, sreg
, 1);
4212 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4213 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4221 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4222 likely
? "bltzl" : "bltz", "s,p", sreg
);
4227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4228 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4231 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4232 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4233 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4243 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4244 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4247 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4249 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4250 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4265 as_warn (_("Divide by zero."));
4267 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4269 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4273 mips_emit_delays (true);
4274 ++mips_opts
.noreorder
;
4275 mips_any_noreorder
= 1;
4278 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4279 macro_build ((char *) NULL
, &icnt
, NULL
,
4280 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4284 expr1
.X_add_number
= 8;
4285 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4286 macro_build ((char *) NULL
, &icnt
, NULL
,
4287 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4288 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4290 expr1
.X_add_number
= -1;
4291 macro_build ((char *) NULL
, &icnt
, &expr1
,
4292 dbl
? "daddiu" : "addiu",
4293 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4294 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4295 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4298 expr1
.X_add_number
= 1;
4299 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4300 (int) BFD_RELOC_LO16
);
4301 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4306 expr1
.X_add_number
= 0x80000000;
4307 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4308 (int) BFD_RELOC_HI16
);
4312 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4313 /* We want to close the noreorder block as soon as possible, so
4314 that later insns are available for delay slot filling. */
4315 --mips_opts
.noreorder
;
4319 expr1
.X_add_number
= 8;
4320 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4321 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4323 /* We want to close the noreorder block as soon as possible, so
4324 that later insns are available for delay slot filling. */
4325 --mips_opts
.noreorder
;
4327 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4329 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4368 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4370 as_warn (_("Divide by zero."));
4372 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4374 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4377 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4379 if (strcmp (s2
, "mflo") == 0)
4380 move_register (&icnt
, dreg
, sreg
);
4382 move_register (&icnt
, dreg
, 0);
4385 if (imm_expr
.X_op
== O_constant
4386 && imm_expr
.X_add_number
== -1
4387 && s
[strlen (s
) - 1] != 'u')
4389 if (strcmp (s2
, "mflo") == 0)
4391 macro_build ((char *) NULL
, &icnt
, NULL
, dbl
? "dneg" : "neg",
4395 move_register (&icnt
, dreg
, 0);
4399 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4400 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4401 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4420 mips_emit_delays (true);
4421 ++mips_opts
.noreorder
;
4422 mips_any_noreorder
= 1;
4425 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4426 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4427 /* We want to close the noreorder block as soon as possible, so
4428 that later insns are available for delay slot filling. */
4429 --mips_opts
.noreorder
;
4433 expr1
.X_add_number
= 8;
4434 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4435 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4437 /* We want to close the noreorder block as soon as possible, so
4438 that later insns are available for delay slot filling. */
4439 --mips_opts
.noreorder
;
4440 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4442 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4448 /* Load the address of a symbol into a register. If breg is not
4449 zero, we then add a base register to it. */
4462 /* When generating embedded PIC code, we permit expressions of
4465 la $treg,foo-bar($breg)
4466 where bar is an address in the current section. These are used
4467 when getting the addresses of functions. We don't permit
4468 X_add_number to be non-zero, because if the symbol is
4469 external the relaxing code needs to know that any addend is
4470 purely the offset to X_op_symbol. */
4471 if (mips_pic
== EMBEDDED_PIC
4472 && offset_expr
.X_op
== O_subtract
4473 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4474 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4475 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4477 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4480 && (offset_expr
.X_add_number
== 0
4481 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4487 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4488 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4492 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4493 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4495 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4496 "d,v,t", tempreg
, tempreg
, breg
);
4498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4499 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4500 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4506 if (offset_expr
.X_op
!= O_symbol
4507 && offset_expr
.X_op
!= O_constant
)
4509 as_bad (_("expression too complex"));
4510 offset_expr
.X_op
= O_constant
;
4513 if (offset_expr
.X_op
== O_constant
)
4514 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4515 else if (mips_pic
== NO_PIC
)
4517 /* If this is a reference to a GP relative symbol, we want
4518 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4520 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4521 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4522 If we have a constant, we need two instructions anyhow,
4523 so we may as well always use the latter form.
4525 With 64bit address space and a usable $at we want
4526 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4527 lui $at,<sym> (BFD_RELOC_HI16_S)
4528 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4529 daddiu $at,<sym> (BFD_RELOC_LO16)
4531 dadd $tempreg,$tempreg,$at
4533 If $at is already in use, we use an path which is suboptimal
4534 on superscalar processors.
4535 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4536 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4538 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4540 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4543 if (HAVE_64BIT_ADDRESSES
)
4545 /* We don't do GP optimization for now because RELAX_ENCODE can't
4546 hold the data for such large chunks. */
4550 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4551 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4552 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4553 AT
, (int) BFD_RELOC_HI16_S
);
4554 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4555 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4556 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4557 AT
, AT
, (int) BFD_RELOC_LO16
);
4558 macro_build (p
, &icnt
, NULL
, "dsll32", "d,w,<",
4559 tempreg
, tempreg
, 0);
4560 macro_build (p
, &icnt
, NULL
, "dadd", "d,v,t",
4561 tempreg
, tempreg
, AT
);
4566 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4567 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4568 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4569 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4570 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
4571 tempreg
, tempreg
, 16);
4572 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4573 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4574 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
4575 tempreg
, tempreg
, 16);
4576 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4577 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4582 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4583 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4586 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4587 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4588 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4589 p
= frag_var (rs_machine_dependent
, 8, 0,
4590 RELAX_ENCODE (4, 8, 0, 4, 0,
4591 mips_opts
.warn_about_macros
),
4592 offset_expr
.X_add_symbol
, (offsetT
) 0,
4595 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4598 macro_build (p
, &icnt
, &offset_expr
,
4599 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4600 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4603 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4605 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4607 /* If this is a reference to an external symbol, and there
4608 is no constant, we want
4609 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4610 or if tempreg is PIC_CALL_REG
4611 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4612 For a local symbol, we want
4613 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4615 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4617 If we have a small constant, and this is a reference to
4618 an external symbol, we want
4619 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4621 addiu $tempreg,$tempreg,<constant>
4622 For a local symbol, we want the same instruction
4623 sequence, but we output a BFD_RELOC_LO16 reloc on the
4626 If we have a large constant, and this is a reference to
4627 an external symbol, we want
4628 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4629 lui $at,<hiconstant>
4630 addiu $at,$at,<loconstant>
4631 addu $tempreg,$tempreg,$at
4632 For a local symbol, we want the same instruction
4633 sequence, but we output a BFD_RELOC_LO16 reloc on the
4634 addiu instruction. */
4635 expr1
.X_add_number
= offset_expr
.X_add_number
;
4636 offset_expr
.X_add_number
= 0;
4638 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4639 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4640 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4642 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4643 if (expr1
.X_add_number
== 0)
4651 /* We're going to put in an addu instruction using
4652 tempreg, so we may as well insert the nop right
4654 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4658 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4659 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4661 ? mips_opts
.warn_about_macros
4663 offset_expr
.X_add_symbol
, (offsetT
) 0,
4667 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4670 macro_build (p
, &icnt
, &expr1
,
4671 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4672 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4673 /* FIXME: If breg == 0, and the next instruction uses
4674 $tempreg, then if this variant case is used an extra
4675 nop will be generated. */
4677 else if (expr1
.X_add_number
>= -0x8000
4678 && expr1
.X_add_number
< 0x8000)
4680 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4682 macro_build ((char *) NULL
, &icnt
, &expr1
,
4683 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4684 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4685 (void) frag_var (rs_machine_dependent
, 0, 0,
4686 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4687 offset_expr
.X_add_symbol
, (offsetT
) 0,
4694 /* If we are going to add in a base register, and the
4695 target register and the base register are the same,
4696 then we are using AT as a temporary register. Since
4697 we want to load the constant into AT, we add our
4698 current AT (from the global offset table) and the
4699 register into the register now, and pretend we were
4700 not using a base register. */
4705 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4707 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4708 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4709 "d,v,t", treg
, AT
, breg
);
4715 /* Set mips_optimize around the lui instruction to avoid
4716 inserting an unnecessary nop after the lw. */
4717 hold_mips_optimize
= mips_optimize
;
4719 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4720 mips_optimize
= hold_mips_optimize
;
4722 macro_build ((char *) NULL
, &icnt
, &expr1
,
4723 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4724 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4726 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4727 "d,v,t", tempreg
, tempreg
, AT
);
4728 (void) frag_var (rs_machine_dependent
, 0, 0,
4729 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4730 offset_expr
.X_add_symbol
, (offsetT
) 0,
4735 else if (mips_pic
== SVR4_PIC
)
4738 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4739 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4741 /* This is the large GOT case. If this is a reference to an
4742 external symbol, and there is no constant, we want
4743 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4744 addu $tempreg,$tempreg,$gp
4745 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4746 or if tempreg is PIC_CALL_REG
4747 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4748 addu $tempreg,$tempreg,$gp
4749 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4750 For a local symbol, we want
4751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4753 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4755 If we have a small constant, and this is a reference to
4756 an external symbol, we want
4757 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4758 addu $tempreg,$tempreg,$gp
4759 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4761 addiu $tempreg,$tempreg,<constant>
4762 For a local symbol, we want
4763 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4765 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4767 If we have a large constant, and this is a reference to
4768 an external symbol, we want
4769 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4770 addu $tempreg,$tempreg,$gp
4771 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4772 lui $at,<hiconstant>
4773 addiu $at,$at,<loconstant>
4774 addu $tempreg,$tempreg,$at
4775 For a local symbol, we want
4776 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4777 lui $at,<hiconstant>
4778 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4779 addu $tempreg,$tempreg,$at
4781 expr1
.X_add_number
= offset_expr
.X_add_number
;
4782 offset_expr
.X_add_number
= 0;
4784 if (reg_needs_delay (GP
))
4788 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4790 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4791 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4794 tempreg
, lui_reloc_type
);
4795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4796 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4797 "d,v,t", tempreg
, tempreg
, GP
);
4798 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4800 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4801 if (expr1
.X_add_number
== 0)
4809 /* We're going to put in an addu instruction using
4810 tempreg, so we may as well insert the nop right
4812 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4817 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4818 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4821 ? mips_opts
.warn_about_macros
4823 offset_expr
.X_add_symbol
, (offsetT
) 0,
4826 else if (expr1
.X_add_number
>= -0x8000
4827 && expr1
.X_add_number
< 0x8000)
4829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4831 macro_build ((char *) NULL
, &icnt
, &expr1
,
4832 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4833 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4835 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4836 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4838 ? mips_opts
.warn_about_macros
4840 offset_expr
.X_add_symbol
, (offsetT
) 0,
4847 /* If we are going to add in a base register, and the
4848 target register and the base register are the same,
4849 then we are using AT as a temporary register. Since
4850 we want to load the constant into AT, we add our
4851 current AT (from the global offset table) and the
4852 register into the register now, and pretend we were
4853 not using a base register. */
4861 assert (tempreg
== AT
);
4862 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4864 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4865 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4866 "d,v,t", treg
, AT
, breg
);
4871 /* Set mips_optimize around the lui instruction to avoid
4872 inserting an unnecessary nop after the lw. */
4873 hold_mips_optimize
= mips_optimize
;
4875 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4876 mips_optimize
= hold_mips_optimize
;
4878 macro_build ((char *) NULL
, &icnt
, &expr1
,
4879 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4880 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4881 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4882 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4883 "d,v,t", dreg
, dreg
, AT
);
4885 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4886 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4889 ? mips_opts
.warn_about_macros
4891 offset_expr
.X_add_symbol
, (offsetT
) 0,
4899 /* This is needed because this instruction uses $gp, but
4900 the first instruction on the main stream does not. */
4901 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4904 macro_build (p
, &icnt
, &offset_expr
,
4906 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4908 if (expr1
.X_add_number
>= -0x8000
4909 && expr1
.X_add_number
< 0x8000)
4911 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4913 macro_build (p
, &icnt
, &expr1
,
4914 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4915 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4916 /* FIXME: If add_number is 0, and there was no base
4917 register, the external symbol case ended with a load,
4918 so if the symbol turns out to not be external, and
4919 the next instruction uses tempreg, an unnecessary nop
4920 will be inserted. */
4926 /* We must add in the base register now, as in the
4927 external symbol case. */
4928 assert (tempreg
== AT
);
4929 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4931 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4932 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4933 "d,v,t", treg
, AT
, breg
);
4936 /* We set breg to 0 because we have arranged to add
4937 it in in both cases. */
4941 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4943 macro_build (p
, &icnt
, &expr1
,
4944 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4945 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4947 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4948 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4949 "d,v,t", tempreg
, tempreg
, AT
);
4953 else if (mips_pic
== EMBEDDED_PIC
)
4956 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4958 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4959 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4960 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4966 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4967 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4968 "d,v,t", treg
, tempreg
, breg
);
4976 /* The j instruction may not be used in PIC code, since it
4977 requires an absolute address. We convert it to a b
4979 if (mips_pic
== NO_PIC
)
4980 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4982 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4985 /* The jal instructions must be handled as macros because when
4986 generating PIC code they expand to multi-instruction
4987 sequences. Normally they are simple instructions. */
4992 if (mips_pic
== NO_PIC
4993 || mips_pic
== EMBEDDED_PIC
)
4994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4996 else if (mips_pic
== SVR4_PIC
)
4998 if (sreg
!= PIC_CALL_REG
)
4999 as_warn (_("MIPS PIC call to register other than $25"));
5001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5005 if (mips_cprestore_offset
< 0)
5006 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5009 expr1
.X_add_number
= mips_cprestore_offset
;
5010 macro_build ((char *) NULL
, &icnt
, &expr1
,
5011 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5012 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5022 if (mips_pic
== NO_PIC
)
5023 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5024 else if (mips_pic
== SVR4_PIC
)
5026 /* If this is a reference to an external symbol, and we are
5027 using a small GOT, we want
5028 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5032 lw $gp,cprestore($sp)
5033 The cprestore value is set using the .cprestore
5034 pseudo-op. If we are using a big GOT, we want
5035 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5037 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5041 lw $gp,cprestore($sp)
5042 If the symbol is not external, we want
5043 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5045 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5048 lw $gp,cprestore($sp) */
5052 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5053 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5054 "t,o(b)", PIC_CALL_REG
,
5055 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5056 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5058 p
= frag_var (rs_machine_dependent
, 4, 0,
5059 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5060 offset_expr
.X_add_symbol
, (offsetT
) 0,
5067 if (reg_needs_delay (GP
))
5071 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5072 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5074 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5075 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5076 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5077 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5078 "t,o(b)", PIC_CALL_REG
,
5079 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5082 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5083 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5085 offset_expr
.X_add_symbol
, (offsetT
) 0,
5089 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5092 macro_build (p
, &icnt
, &offset_expr
,
5093 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5094 "t,o(b)", PIC_CALL_REG
,
5095 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5097 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5100 macro_build (p
, &icnt
, &offset_expr
,
5101 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5102 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5103 (int) BFD_RELOC_LO16
);
5104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5105 "jalr", "s", PIC_CALL_REG
);
5108 if (mips_cprestore_offset
< 0)
5109 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5112 if (mips_opts
.noreorder
)
5113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5115 expr1
.X_add_number
= mips_cprestore_offset
;
5116 macro_build ((char *) NULL
, &icnt
, &expr1
,
5117 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5118 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5122 else if (mips_pic
== EMBEDDED_PIC
)
5124 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5125 /* The linker may expand the call to a longer sequence which
5126 uses $at, so we must break rather than return. */
5151 /* Itbl support may require additional care here. */
5156 /* Itbl support may require additional care here. */
5161 /* Itbl support may require additional care here. */
5166 /* Itbl support may require additional care here. */
5178 if (mips_arch
== CPU_R4650
)
5180 as_bad (_("opcode not supported on this processor"));
5184 /* Itbl support may require additional care here. */
5189 /* Itbl support may require additional care here. */
5194 /* Itbl support may require additional care here. */
5214 if (breg
== treg
|| coproc
|| lr
)
5236 /* Itbl support may require additional care here. */
5241 /* Itbl support may require additional care here. */
5246 /* Itbl support may require additional care here. */
5251 /* Itbl support may require additional care here. */
5267 if (mips_arch
== CPU_R4650
)
5269 as_bad (_("opcode not supported on this processor"));
5274 /* Itbl support may require additional care here. */
5278 /* Itbl support may require additional care here. */
5283 /* Itbl support may require additional care here. */
5295 /* Itbl support may require additional care here. */
5296 if (mask
== M_LWC1_AB
5297 || mask
== M_SWC1_AB
5298 || mask
== M_LDC1_AB
5299 || mask
== M_SDC1_AB
5308 /* For embedded PIC, we allow loads where the offset is calculated
5309 by subtracting a symbol in the current segment from an unknown
5310 symbol, relative to a base register, e.g.:
5311 <op> $treg, <sym>-<localsym>($breg)
5312 This is used by the compiler for switch statements. */
5313 if (mips_pic
== EMBEDDED_PIC
5314 && offset_expr
.X_op
== O_subtract
5315 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5316 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5317 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5319 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5323 && (offset_expr
.X_add_number
== 0
5324 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5326 /* For this case, we output the instructions:
5327 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5328 addiu $tempreg,$tempreg,$breg
5329 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5330 If the relocation would fit entirely in 16 bits, it would be
5332 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5333 instead, but that seems quite difficult. */
5334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5335 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5337 ((bfd_arch_bits_per_address (stdoutput
) == 32
5338 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5339 ? "addu" : "daddu"),
5340 "d,v,t", tempreg
, tempreg
, breg
);
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5342 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5348 if (offset_expr
.X_op
!= O_constant
5349 && offset_expr
.X_op
!= O_symbol
)
5351 as_bad (_("expression too complex"));
5352 offset_expr
.X_op
= O_constant
;
5355 /* A constant expression in PIC code can be handled just as it
5356 is in non PIC code. */
5357 if (mips_pic
== NO_PIC
5358 || offset_expr
.X_op
== O_constant
)
5360 /* If this is a reference to a GP relative symbol, and there
5361 is no base register, we want
5362 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5363 Otherwise, if there is no base register, we want
5364 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5365 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5366 If we have a constant, we need two instructions anyhow,
5367 so we always use the latter form.
5369 If we have a base register, and this is a reference to a
5370 GP relative symbol, we want
5371 addu $tempreg,$breg,$gp
5372 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5374 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5375 addu $tempreg,$tempreg,$breg
5376 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5377 With a constant we always use the latter case.
5379 With 64bit address space and no base register and $at usable,
5381 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5382 lui $at,<sym> (BFD_RELOC_HI16_S)
5383 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5386 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5387 If we have a base register, we want
5388 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5389 lui $at,<sym> (BFD_RELOC_HI16_S)
5390 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5394 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5396 Without $at we can't generate the optimal path for superscalar
5397 processors here since this would require two temporary registers.
5398 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5399 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5401 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5403 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5404 If we have a base register, we want
5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5406 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5408 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5410 daddu $tempreg,$tempreg,$breg
5411 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5413 if (HAVE_64BIT_ADDRESSES
)
5417 /* We don't do GP optimization for now because RELAX_ENCODE can't
5418 hold the data for such large chunks. */
5422 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5423 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5424 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5425 AT
, (int) BFD_RELOC_HI16_S
);
5426 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5427 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5429 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
5431 macro_build (p
, &icnt
, NULL
, "dsll32", "d,w,<",
5432 tempreg
, tempreg
, 0);
5433 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
5434 tempreg
, tempreg
, AT
);
5435 macro_build (p
, &icnt
, &offset_expr
, s
,
5436 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5441 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5442 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5443 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5444 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5445 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
5446 tempreg
, tempreg
, 16);
5447 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5448 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5449 macro_build (p
, &icnt
, NULL
, "dsll", "d,w,<",
5450 tempreg
, tempreg
, 16);
5452 macro_build (p
, &icnt
, NULL
, "daddu", "d,v,t",
5453 tempreg
, tempreg
, breg
);
5454 macro_build (p
, &icnt
, &offset_expr
, s
,
5455 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5463 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5464 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5470 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5471 p
= frag_var (rs_machine_dependent
, 8, 0,
5472 RELAX_ENCODE (4, 8, 0, 4, 0,
5473 (mips_opts
.warn_about_macros
5475 && mips_opts
.noat
))),
5476 offset_expr
.X_add_symbol
, (offsetT
) 0,
5480 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5483 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5484 (int) BFD_RELOC_LO16
, tempreg
);
5488 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5489 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5495 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5496 "d,v,t", tempreg
, breg
, GP
);
5497 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5498 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5499 p
= frag_var (rs_machine_dependent
, 12, 0,
5500 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5501 offset_expr
.X_add_symbol
, (offsetT
) 0,
5504 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5507 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5508 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5509 "d,v,t", tempreg
, tempreg
, breg
);
5512 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5513 (int) BFD_RELOC_LO16
, tempreg
);
5516 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5518 /* If this is a reference to an external symbol, we want
5519 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5521 <op> $treg,0($tempreg)
5523 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5525 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5526 <op> $treg,0($tempreg)
5527 If there is a base register, we add it to $tempreg before
5528 the <op>. If there is a constant, we stick it in the
5529 <op> instruction. We don't handle constants larger than
5530 16 bits, because we have no way to load the upper 16 bits
5531 (actually, we could handle them for the subset of cases
5532 in which we are not using $at). */
5533 assert (offset_expr
.X_op
== O_symbol
);
5534 expr1
.X_add_number
= offset_expr
.X_add_number
;
5535 offset_expr
.X_add_number
= 0;
5536 if (expr1
.X_add_number
< -0x8000
5537 || expr1
.X_add_number
>= 0x8000)
5538 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5541 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5542 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5544 p
= frag_var (rs_machine_dependent
, 4, 0,
5545 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5546 offset_expr
.X_add_symbol
, (offsetT
) 0,
5548 macro_build (p
, &icnt
, &offset_expr
,
5549 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5550 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5552 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5553 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5554 "d,v,t", tempreg
, tempreg
, breg
);
5555 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5556 (int) BFD_RELOC_LO16
, tempreg
);
5558 else if (mips_pic
== SVR4_PIC
)
5562 /* If this is a reference to an external symbol, we want
5563 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5564 addu $tempreg,$tempreg,$gp
5565 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5566 <op> $treg,0($tempreg)
5568 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5570 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5571 <op> $treg,0($tempreg)
5572 If there is a base register, we add it to $tempreg before
5573 the <op>. If there is a constant, we stick it in the
5574 <op> instruction. We don't handle constants larger than
5575 16 bits, because we have no way to load the upper 16 bits
5576 (actually, we could handle them for the subset of cases
5577 in which we are not using $at). */
5578 assert (offset_expr
.X_op
== O_symbol
);
5579 expr1
.X_add_number
= offset_expr
.X_add_number
;
5580 offset_expr
.X_add_number
= 0;
5581 if (expr1
.X_add_number
< -0x8000
5582 || expr1
.X_add_number
>= 0x8000)
5583 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5584 if (reg_needs_delay (GP
))
5589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5590 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5591 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5592 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5593 "d,v,t", tempreg
, tempreg
, GP
);
5594 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5595 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5596 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5598 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5599 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5600 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5603 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5606 macro_build (p
, &icnt
, &offset_expr
,
5607 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5608 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5610 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5612 macro_build (p
, &icnt
, &offset_expr
,
5613 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5614 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5616 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5617 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5618 "d,v,t", tempreg
, tempreg
, breg
);
5619 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5620 (int) BFD_RELOC_LO16
, tempreg
);
5622 else if (mips_pic
== EMBEDDED_PIC
)
5624 /* If there is no base register, we want
5625 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5626 If there is a base register, we want
5627 addu $tempreg,$breg,$gp
5628 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5630 assert (offset_expr
.X_op
== O_symbol
);
5633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5634 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5640 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5641 "d,v,t", tempreg
, breg
, GP
);
5642 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5643 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5656 load_register (&icnt
, treg
, &imm_expr
, 0);
5660 load_register (&icnt
, treg
, &imm_expr
, 1);
5664 if (imm_expr
.X_op
== O_constant
)
5666 load_register (&icnt
, AT
, &imm_expr
, 0);
5667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5668 "mtc1", "t,G", AT
, treg
);
5673 assert (offset_expr
.X_op
== O_symbol
5674 && strcmp (segment_name (S_GET_SEGMENT
5675 (offset_expr
.X_add_symbol
)),
5677 && offset_expr
.X_add_number
== 0);
5678 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5679 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5684 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5685 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5686 order 32 bits of the value and the low order 32 bits are either
5687 zero or in OFFSET_EXPR. */
5688 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5690 if (HAVE_64BIT_GPRS
)
5691 load_register (&icnt
, treg
, &imm_expr
, 1);
5696 if (target_big_endian
)
5708 load_register (&icnt
, hreg
, &imm_expr
, 0);
5711 if (offset_expr
.X_op
== O_absent
)
5712 move_register (&icnt
, lreg
, 0);
5715 assert (offset_expr
.X_op
== O_constant
);
5716 load_register (&icnt
, lreg
, &offset_expr
, 0);
5723 /* We know that sym is in the .rdata section. First we get the
5724 upper 16 bits of the address. */
5725 if (mips_pic
== NO_PIC
)
5727 /* FIXME: This won't work for a 64 bit address. */
5728 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5730 else if (mips_pic
== SVR4_PIC
)
5732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5733 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5734 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5736 else if (mips_pic
== EMBEDDED_PIC
)
5738 /* For embedded PIC we pick up the entire address off $gp in
5739 a single instruction. */
5740 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5741 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5742 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5743 offset_expr
.X_op
= O_constant
;
5744 offset_expr
.X_add_number
= 0;
5749 /* Now we load the register(s). */
5750 if (HAVE_64BIT_GPRS
)
5751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5752 treg
, (int) BFD_RELOC_LO16
, AT
);
5755 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5756 treg
, (int) BFD_RELOC_LO16
, AT
);
5759 /* FIXME: How in the world do we deal with the possible
5761 offset_expr
.X_add_number
+= 4;
5762 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5763 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5767 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5768 does not become a variant frag. */
5769 frag_wane (frag_now
);
5775 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5776 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5777 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5778 the value and the low order 32 bits are either zero or in
5780 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5782 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5783 if (HAVE_64BIT_FPRS
)
5785 assert (HAVE_64BIT_GPRS
);
5786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5787 "dmtc1", "t,S", AT
, treg
);
5791 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5792 "mtc1", "t,G", AT
, treg
+ 1);
5793 if (offset_expr
.X_op
== O_absent
)
5794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5795 "mtc1", "t,G", 0, treg
);
5798 assert (offset_expr
.X_op
== O_constant
);
5799 load_register (&icnt
, AT
, &offset_expr
, 0);
5800 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5801 "mtc1", "t,G", AT
, treg
);
5807 assert (offset_expr
.X_op
== O_symbol
5808 && offset_expr
.X_add_number
== 0);
5809 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5810 if (strcmp (s
, ".lit8") == 0)
5812 if (mips_opts
.isa
!= ISA_MIPS1
)
5814 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5815 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5819 r
= BFD_RELOC_MIPS_LITERAL
;
5824 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5825 if (mips_pic
== SVR4_PIC
)
5826 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5827 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5828 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5831 /* FIXME: This won't work for a 64 bit address. */
5832 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5835 if (mips_opts
.isa
!= ISA_MIPS1
)
5837 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5838 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5840 /* To avoid confusion in tc_gen_reloc, we must ensure
5841 that this does not become a variant frag. */
5842 frag_wane (frag_now
);
5853 if (mips_arch
== CPU_R4650
)
5855 as_bad (_("opcode not supported on this processor"));
5858 /* Even on a big endian machine $fn comes before $fn+1. We have
5859 to adjust when loading from memory. */
5862 assert (mips_opts
.isa
== ISA_MIPS1
);
5863 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5864 target_big_endian
? treg
+ 1 : treg
,
5866 /* FIXME: A possible overflow which I don't know how to deal
5868 offset_expr
.X_add_number
+= 4;
5869 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5870 target_big_endian
? treg
: treg
+ 1,
5873 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5874 does not become a variant frag. */
5875 frag_wane (frag_now
);
5884 * The MIPS assembler seems to check for X_add_number not
5885 * being double aligned and generating:
5888 * addiu at,at,%lo(foo+1)
5891 * But, the resulting address is the same after relocation so why
5892 * generate the extra instruction?
5894 if (mips_arch
== CPU_R4650
)
5896 as_bad (_("opcode not supported on this processor"));
5899 /* Itbl support may require additional care here. */
5901 if (mips_opts
.isa
!= ISA_MIPS1
)
5912 if (mips_arch
== CPU_R4650
)
5914 as_bad (_("opcode not supported on this processor"));
5918 if (mips_opts
.isa
!= ISA_MIPS1
)
5926 /* Itbl support may require additional care here. */
5931 if (HAVE_64BIT_GPRS
)
5942 if (HAVE_64BIT_GPRS
)
5952 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
5953 loads for the case of doing a pair of loads to simulate an 'ld'.
5954 This is not currently done by the compiler, and assembly coders
5955 writing embedded-pic code can cope. */
5957 if (offset_expr
.X_op
!= O_symbol
5958 && offset_expr
.X_op
!= O_constant
)
5960 as_bad (_("expression too complex"));
5961 offset_expr
.X_op
= O_constant
;
5964 /* Even on a big endian machine $fn comes before $fn+1. We have
5965 to adjust when loading from memory. We set coproc if we must
5966 load $fn+1 first. */
5967 /* Itbl support may require additional care here. */
5968 if (! target_big_endian
)
5971 if (mips_pic
== NO_PIC
5972 || offset_expr
.X_op
== O_constant
)
5974 /* If this is a reference to a GP relative symbol, we want
5975 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5976 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5977 If we have a base register, we use this
5979 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5980 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5981 If this is not a GP relative symbol, we want
5982 lui $at,<sym> (BFD_RELOC_HI16_S)
5983 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5984 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5985 If there is a base register, we add it to $at after the
5986 lui instruction. If there is a constant, we always use
5988 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5989 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6008 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6009 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6010 "d,v,t", AT
, breg
, GP
);
6016 /* Itbl support may require additional care here. */
6017 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6018 coproc
? treg
+ 1 : treg
,
6019 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6020 offset_expr
.X_add_number
+= 4;
6022 /* Set mips_optimize to 2 to avoid inserting an
6024 hold_mips_optimize
= mips_optimize
;
6026 /* Itbl support may require additional care here. */
6027 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6028 coproc
? treg
: treg
+ 1,
6029 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6030 mips_optimize
= hold_mips_optimize
;
6032 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6033 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6034 used_at
&& mips_opts
.noat
),
6035 offset_expr
.X_add_symbol
, (offsetT
) 0,
6038 /* We just generated two relocs. When tc_gen_reloc
6039 handles this case, it will skip the first reloc and
6040 handle the second. The second reloc already has an
6041 extra addend of 4, which we added above. We must
6042 subtract it out, and then subtract another 4 to make
6043 the first reloc come out right. The second reloc
6044 will come out right because we are going to add 4 to
6045 offset_expr when we build its instruction below.
6047 If we have a symbol, then we don't want to include
6048 the offset, because it will wind up being included
6049 when we generate the reloc. */
6051 if (offset_expr
.X_op
== O_constant
)
6052 offset_expr
.X_add_number
-= 8;
6055 offset_expr
.X_add_number
= -4;
6056 offset_expr
.X_op
= O_constant
;
6059 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6064 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6065 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6066 "d,v,t", AT
, breg
, AT
);
6070 /* Itbl support may require additional care here. */
6071 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6072 coproc
? treg
+ 1 : treg
,
6073 (int) BFD_RELOC_LO16
, AT
);
6076 /* FIXME: How do we handle overflow here? */
6077 offset_expr
.X_add_number
+= 4;
6078 /* Itbl support may require additional care here. */
6079 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6080 coproc
? treg
: treg
+ 1,
6081 (int) BFD_RELOC_LO16
, AT
);
6083 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6087 /* If this is a reference to an external symbol, we want
6088 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6093 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6095 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6096 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6097 If there is a base register we add it to $at before the
6098 lwc1 instructions. If there is a constant we include it
6099 in the lwc1 instructions. */
6101 expr1
.X_add_number
= offset_expr
.X_add_number
;
6102 offset_expr
.X_add_number
= 0;
6103 if (expr1
.X_add_number
< -0x8000
6104 || expr1
.X_add_number
>= 0x8000 - 4)
6105 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6110 frag_grow (24 + off
);
6111 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6112 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6113 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6116 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6117 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6118 "d,v,t", AT
, breg
, AT
);
6119 /* Itbl support may require additional care here. */
6120 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6121 coproc
? treg
+ 1 : treg
,
6122 (int) BFD_RELOC_LO16
, AT
);
6123 expr1
.X_add_number
+= 4;
6125 /* Set mips_optimize to 2 to avoid inserting an undesired
6127 hold_mips_optimize
= mips_optimize
;
6129 /* Itbl support may require additional care here. */
6130 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6131 coproc
? treg
: treg
+ 1,
6132 (int) BFD_RELOC_LO16
, AT
);
6133 mips_optimize
= hold_mips_optimize
;
6135 (void) frag_var (rs_machine_dependent
, 0, 0,
6136 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6137 offset_expr
.X_add_symbol
, (offsetT
) 0,
6140 else if (mips_pic
== SVR4_PIC
)
6144 /* If this is a reference to an external symbol, we want
6145 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6147 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6152 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6154 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6155 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6156 If there is a base register we add it to $at before the
6157 lwc1 instructions. If there is a constant we include it
6158 in the lwc1 instructions. */
6160 expr1
.X_add_number
= offset_expr
.X_add_number
;
6161 offset_expr
.X_add_number
= 0;
6162 if (expr1
.X_add_number
< -0x8000
6163 || expr1
.X_add_number
>= 0x8000 - 4)
6164 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6165 if (reg_needs_delay (GP
))
6174 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6175 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6177 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6178 "d,v,t", AT
, AT
, GP
);
6179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6180 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6181 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6182 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6185 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6186 "d,v,t", AT
, breg
, AT
);
6187 /* Itbl support may require additional care here. */
6188 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6189 coproc
? treg
+ 1 : treg
,
6190 (int) BFD_RELOC_LO16
, AT
);
6191 expr1
.X_add_number
+= 4;
6193 /* Set mips_optimize to 2 to avoid inserting an undesired
6195 hold_mips_optimize
= mips_optimize
;
6197 /* Itbl support may require additional care here. */
6198 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6199 coproc
? treg
: treg
+ 1,
6200 (int) BFD_RELOC_LO16
, AT
);
6201 mips_optimize
= hold_mips_optimize
;
6202 expr1
.X_add_number
-= 4;
6204 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6205 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6206 8 + gpdel
+ off
, 1, 0),
6207 offset_expr
.X_add_symbol
, (offsetT
) 0,
6211 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6214 macro_build (p
, &icnt
, &offset_expr
,
6215 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6216 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6218 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6222 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6223 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6224 "d,v,t", AT
, breg
, AT
);
6227 /* Itbl support may require additional care here. */
6228 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6229 coproc
? treg
+ 1 : treg
,
6230 (int) BFD_RELOC_LO16
, AT
);
6232 expr1
.X_add_number
+= 4;
6234 /* Set mips_optimize to 2 to avoid inserting an undesired
6236 hold_mips_optimize
= mips_optimize
;
6238 /* Itbl support may require additional care here. */
6239 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6240 coproc
? treg
: treg
+ 1,
6241 (int) BFD_RELOC_LO16
, AT
);
6242 mips_optimize
= hold_mips_optimize
;
6244 else if (mips_pic
== EMBEDDED_PIC
)
6246 /* If there is no base register, we use
6247 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
6248 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
6249 If we have a base register, we use
6251 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
6252 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
6261 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6262 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6263 "d,v,t", AT
, breg
, GP
);
6268 /* Itbl support may require additional care here. */
6269 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6270 coproc
? treg
+ 1 : treg
,
6271 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6272 offset_expr
.X_add_number
+= 4;
6273 /* Itbl support may require additional care here. */
6274 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6275 coproc
? treg
: treg
+ 1,
6276 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6292 assert (HAVE_32BIT_ADDRESSES
);
6293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6294 (int) BFD_RELOC_LO16
, breg
);
6295 offset_expr
.X_add_number
+= 4;
6296 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6297 (int) BFD_RELOC_LO16
, breg
);
6300 /* New code added to support COPZ instructions.
6301 This code builds table entries out of the macros in mip_opcodes.
6302 R4000 uses interlocks to handle coproc delays.
6303 Other chips (like the R3000) require nops to be inserted for delays.
6305 FIXME: Currently, we require that the user handle delays.
6306 In order to fill delay slots for non-interlocked chips,
6307 we must have a way to specify delays based on the coprocessor.
6308 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6309 What are the side-effects of the cop instruction?
6310 What cache support might we have and what are its effects?
6311 Both coprocessor & memory require delays. how long???
6312 What registers are read/set/modified?
6314 If an itbl is provided to interpret cop instructions,
6315 this knowledge can be encoded in the itbl spec. */
6329 /* For now we just do C (same as Cz). The parameter will be
6330 stored in insn_opcode by mips_ip. */
6331 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6336 move_register (&icnt
, dreg
, sreg
);
6339 #ifdef LOSING_COMPILER
6341 /* Try and see if this is a new itbl instruction.
6342 This code builds table entries out of the macros in mip_opcodes.
6343 FIXME: For now we just assemble the expression and pass it's
6344 value along as a 32-bit immediate.
6345 We may want to have the assembler assemble this value,
6346 so that we gain the assembler's knowledge of delay slots,
6348 Would it be more efficient to use mask (id) here? */
6349 if (itbl_have_entries
6350 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6352 s
= ip
->insn_mo
->name
;
6354 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6355 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6362 as_warn (_("Macro used $at after \".set noat\""));
6367 struct mips_cl_insn
*ip
;
6369 register int treg
, sreg
, dreg
, breg
;
6385 bfd_reloc_code_real_type r
;
6388 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6389 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6390 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6391 mask
= ip
->insn_mo
->mask
;
6393 expr1
.X_op
= O_constant
;
6394 expr1
.X_op_symbol
= NULL
;
6395 expr1
.X_add_symbol
= NULL
;
6396 expr1
.X_add_number
= 1;
6400 #endif /* LOSING_COMPILER */
6405 macro_build ((char *) NULL
, &icnt
, NULL
,
6406 dbl
? "dmultu" : "multu",
6408 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6414 /* The MIPS assembler some times generates shifts and adds. I'm
6415 not trying to be that fancy. GCC should do this for us
6417 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6418 macro_build ((char *) NULL
, &icnt
, NULL
,
6419 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6420 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6433 mips_emit_delays (true);
6434 ++mips_opts
.noreorder
;
6435 mips_any_noreorder
= 1;
6437 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6438 macro_build ((char *) NULL
, &icnt
, NULL
,
6439 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6440 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6441 macro_build ((char *) NULL
, &icnt
, NULL
,
6442 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6443 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6445 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6448 expr1
.X_add_number
= 8;
6449 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6450 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6451 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6453 --mips_opts
.noreorder
;
6454 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6467 mips_emit_delays (true);
6468 ++mips_opts
.noreorder
;
6469 mips_any_noreorder
= 1;
6471 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6472 macro_build ((char *) NULL
, &icnt
, NULL
,
6473 dbl
? "dmultu" : "multu",
6474 "s,t", sreg
, imm
? AT
: treg
);
6475 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6476 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6478 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6481 expr1
.X_add_number
= 8;
6482 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6483 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6484 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6486 --mips_opts
.noreorder
;
6490 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6491 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6492 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6494 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6498 if (imm_expr
.X_op
!= O_constant
)
6499 as_bad (_("rotate count too large"));
6500 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6501 (int) (imm_expr
.X_add_number
& 0x1f));
6502 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6503 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6504 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6508 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6509 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6510 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6512 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6516 if (imm_expr
.X_op
!= O_constant
)
6517 as_bad (_("rotate count too large"));
6518 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6519 (int) (imm_expr
.X_add_number
& 0x1f));
6520 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6521 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6522 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6526 if (mips_arch
== CPU_R4650
)
6528 as_bad (_("opcode not supported on this processor"));
6531 assert (mips_opts
.isa
== ISA_MIPS1
);
6532 /* Even on a big endian machine $fn comes before $fn+1. We have
6533 to adjust when storing to memory. */
6534 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6535 target_big_endian
? treg
+ 1 : treg
,
6536 (int) BFD_RELOC_LO16
, breg
);
6537 offset_expr
.X_add_number
+= 4;
6538 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6539 target_big_endian
? treg
: treg
+ 1,
6540 (int) BFD_RELOC_LO16
, breg
);
6545 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6546 treg
, (int) BFD_RELOC_LO16
);
6548 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6549 sreg
, (int) BFD_RELOC_LO16
);
6552 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6554 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6555 dreg
, (int) BFD_RELOC_LO16
);
6560 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6562 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6563 sreg
, (int) BFD_RELOC_LO16
);
6568 as_warn (_("Instruction %s: result is always false"),
6570 move_register (&icnt
, dreg
, 0);
6573 if (imm_expr
.X_op
== O_constant
6574 && imm_expr
.X_add_number
>= 0
6575 && imm_expr
.X_add_number
< 0x10000)
6577 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6578 sreg
, (int) BFD_RELOC_LO16
);
6581 else if (imm_expr
.X_op
== O_constant
6582 && imm_expr
.X_add_number
> -0x8000
6583 && imm_expr
.X_add_number
< 0)
6585 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6586 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6587 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6588 "t,r,j", dreg
, sreg
,
6589 (int) BFD_RELOC_LO16
);
6594 load_register (&icnt
, AT
, &imm_expr
, 0);
6595 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6599 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6600 (int) BFD_RELOC_LO16
);
6605 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6611 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6612 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6613 (int) BFD_RELOC_LO16
);
6616 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6618 if (imm_expr
.X_op
== O_constant
6619 && imm_expr
.X_add_number
>= -0x8000
6620 && imm_expr
.X_add_number
< 0x8000)
6622 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6623 mask
== M_SGE_I
? "slti" : "sltiu",
6624 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6629 load_register (&icnt
, AT
, &imm_expr
, 0);
6630 macro_build ((char *) NULL
, &icnt
, NULL
,
6631 mask
== M_SGE_I
? "slt" : "sltu",
6632 "d,v,t", dreg
, sreg
, AT
);
6635 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6636 (int) BFD_RELOC_LO16
);
6641 case M_SGT
: /* sreg > treg <==> treg < sreg */
6647 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6650 case M_SGT_I
: /* sreg > I <==> I < sreg */
6656 load_register (&icnt
, AT
, &imm_expr
, 0);
6657 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6660 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6666 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6667 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6668 (int) BFD_RELOC_LO16
);
6671 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6677 load_register (&icnt
, AT
, &imm_expr
, 0);
6678 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6679 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6680 (int) BFD_RELOC_LO16
);
6684 if (imm_expr
.X_op
== O_constant
6685 && imm_expr
.X_add_number
>= -0x8000
6686 && imm_expr
.X_add_number
< 0x8000)
6688 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6689 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6692 load_register (&icnt
, AT
, &imm_expr
, 0);
6693 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6697 if (imm_expr
.X_op
== O_constant
6698 && imm_expr
.X_add_number
>= -0x8000
6699 && imm_expr
.X_add_number
< 0x8000)
6701 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6702 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6705 load_register (&icnt
, AT
, &imm_expr
, 0);
6706 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6712 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6715 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6719 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6721 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6727 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6729 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6735 as_warn (_("Instruction %s: result is always true"),
6737 macro_build ((char *) NULL
, &icnt
, &expr1
,
6738 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6739 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6742 if (imm_expr
.X_op
== O_constant
6743 && imm_expr
.X_add_number
>= 0
6744 && imm_expr
.X_add_number
< 0x10000)
6746 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6747 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6750 else if (imm_expr
.X_op
== O_constant
6751 && imm_expr
.X_add_number
> -0x8000
6752 && imm_expr
.X_add_number
< 0)
6754 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6755 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6756 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6757 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6762 load_register (&icnt
, AT
, &imm_expr
, 0);
6763 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6767 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6775 if (imm_expr
.X_op
== O_constant
6776 && imm_expr
.X_add_number
> -0x8000
6777 && imm_expr
.X_add_number
<= 0x8000)
6779 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6780 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6781 dbl
? "daddi" : "addi",
6782 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6785 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6786 macro_build ((char *) NULL
, &icnt
, NULL
,
6787 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6793 if (imm_expr
.X_op
== O_constant
6794 && imm_expr
.X_add_number
> -0x8000
6795 && imm_expr
.X_add_number
<= 0x8000)
6797 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6798 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6799 dbl
? "daddiu" : "addiu",
6800 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6803 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6804 macro_build ((char *) NULL
, &icnt
, NULL
,
6805 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6826 load_register (&icnt
, AT
, &imm_expr
, 0);
6827 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6832 assert (mips_opts
.isa
== ISA_MIPS1
);
6833 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6834 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6837 * Is the double cfc1 instruction a bug in the mips assembler;
6838 * or is there a reason for it?
6840 mips_emit_delays (true);
6841 ++mips_opts
.noreorder
;
6842 mips_any_noreorder
= 1;
6843 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6844 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6845 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6846 expr1
.X_add_number
= 3;
6847 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6848 (int) BFD_RELOC_LO16
);
6849 expr1
.X_add_number
= 2;
6850 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6851 (int) BFD_RELOC_LO16
);
6852 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6853 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6854 macro_build ((char *) NULL
, &icnt
, NULL
,
6855 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6856 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6857 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6858 --mips_opts
.noreorder
;
6867 if (offset_expr
.X_add_number
>= 0x7fff)
6868 as_bad (_("operand overflow"));
6869 /* avoid load delay */
6870 if (! target_big_endian
)
6871 offset_expr
.X_add_number
+= 1;
6872 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6873 (int) BFD_RELOC_LO16
, breg
);
6874 if (! target_big_endian
)
6875 offset_expr
.X_add_number
-= 1;
6877 offset_expr
.X_add_number
+= 1;
6878 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6879 (int) BFD_RELOC_LO16
, breg
);
6880 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6881 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6894 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6895 as_bad (_("operand overflow"));
6896 if (! target_big_endian
)
6897 offset_expr
.X_add_number
+= off
;
6898 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6899 (int) BFD_RELOC_LO16
, breg
);
6900 if (! target_big_endian
)
6901 offset_expr
.X_add_number
-= off
;
6903 offset_expr
.X_add_number
+= off
;
6904 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6905 (int) BFD_RELOC_LO16
, breg
);
6919 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6921 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6922 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6923 "d,v,t", AT
, AT
, breg
);
6924 if (! target_big_endian
)
6925 expr1
.X_add_number
= off
;
6927 expr1
.X_add_number
= 0;
6928 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6929 (int) BFD_RELOC_LO16
, AT
);
6930 if (! target_big_endian
)
6931 expr1
.X_add_number
= 0;
6933 expr1
.X_add_number
= off
;
6934 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6935 (int) BFD_RELOC_LO16
, AT
);
6941 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
6943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6944 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6945 "d,v,t", AT
, AT
, breg
);
6946 if (target_big_endian
)
6947 expr1
.X_add_number
= 0;
6948 macro_build ((char *) NULL
, &icnt
, &expr1
,
6949 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6950 (int) BFD_RELOC_LO16
, AT
);
6951 if (target_big_endian
)
6952 expr1
.X_add_number
= 1;
6954 expr1
.X_add_number
= 0;
6955 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6956 (int) BFD_RELOC_LO16
, AT
);
6957 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6959 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6964 if (offset_expr
.X_add_number
>= 0x7fff)
6965 as_bad (_("operand overflow"));
6966 if (target_big_endian
)
6967 offset_expr
.X_add_number
+= 1;
6968 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6969 (int) BFD_RELOC_LO16
, breg
);
6970 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6971 if (target_big_endian
)
6972 offset_expr
.X_add_number
-= 1;
6974 offset_expr
.X_add_number
+= 1;
6975 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6976 (int) BFD_RELOC_LO16
, breg
);
6989 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6990 as_bad (_("operand overflow"));
6991 if (! target_big_endian
)
6992 offset_expr
.X_add_number
+= off
;
6993 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6994 (int) BFD_RELOC_LO16
, breg
);
6995 if (! target_big_endian
)
6996 offset_expr
.X_add_number
-= off
;
6998 offset_expr
.X_add_number
+= off
;
6999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7000 (int) BFD_RELOC_LO16
, breg
);
7014 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7017 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7018 "d,v,t", AT
, AT
, breg
);
7019 if (! target_big_endian
)
7020 expr1
.X_add_number
= off
;
7022 expr1
.X_add_number
= 0;
7023 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7024 (int) BFD_RELOC_LO16
, AT
);
7025 if (! target_big_endian
)
7026 expr1
.X_add_number
= 0;
7028 expr1
.X_add_number
= off
;
7029 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7030 (int) BFD_RELOC_LO16
, AT
);
7035 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7038 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7039 "d,v,t", AT
, AT
, breg
);
7040 if (! target_big_endian
)
7041 expr1
.X_add_number
= 0;
7042 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7043 (int) BFD_RELOC_LO16
, AT
);
7044 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
7046 if (! target_big_endian
)
7047 expr1
.X_add_number
= 1;
7049 expr1
.X_add_number
= 0;
7050 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7051 (int) BFD_RELOC_LO16
, AT
);
7052 if (! target_big_endian
)
7053 expr1
.X_add_number
= 0;
7055 expr1
.X_add_number
= 1;
7056 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7057 (int) BFD_RELOC_LO16
, AT
);
7058 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
7060 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
7065 /* FIXME: Check if this is one of the itbl macros, since they
7066 are added dynamically. */
7067 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7071 as_warn (_("Macro used $at after \".set noat\""));
7074 /* Implement macros in mips16 mode. */
7078 struct mips_cl_insn
*ip
;
7081 int xreg
, yreg
, zreg
, tmp
;
7085 const char *s
, *s2
, *s3
;
7087 mask
= ip
->insn_mo
->mask
;
7089 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7090 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7091 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7095 expr1
.X_op
= O_constant
;
7096 expr1
.X_op_symbol
= NULL
;
7097 expr1
.X_add_symbol
= NULL
;
7098 expr1
.X_add_number
= 1;
7117 mips_emit_delays (true);
7118 ++mips_opts
.noreorder
;
7119 mips_any_noreorder
= 1;
7120 macro_build ((char *) NULL
, &icnt
, NULL
,
7121 dbl
? "ddiv" : "div",
7122 "0,x,y", xreg
, yreg
);
7123 expr1
.X_add_number
= 2;
7124 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7125 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
7127 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7128 since that causes an overflow. We should do that as well,
7129 but I don't see how to do the comparisons without a temporary
7131 --mips_opts
.noreorder
;
7132 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
7151 mips_emit_delays (true);
7152 ++mips_opts
.noreorder
;
7153 mips_any_noreorder
= 1;
7154 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
7155 expr1
.X_add_number
= 2;
7156 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7157 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
7158 --mips_opts
.noreorder
;
7159 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
7165 macro_build ((char *) NULL
, &icnt
, NULL
,
7166 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7167 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
7175 if (imm_expr
.X_op
!= O_constant
)
7176 as_bad (_("Unsupported large constant"));
7177 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7178 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7179 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7183 if (imm_expr
.X_op
!= O_constant
)
7184 as_bad (_("Unsupported large constant"));
7185 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7186 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7191 if (imm_expr
.X_op
!= O_constant
)
7192 as_bad (_("Unsupported large constant"));
7193 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7194 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7217 goto do_reverse_branch
;
7221 goto do_reverse_branch
;
7233 goto do_reverse_branch
;
7244 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7246 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7273 goto do_addone_branch_i
;
7278 goto do_addone_branch_i
;
7293 goto do_addone_branch_i
;
7300 if (imm_expr
.X_op
!= O_constant
)
7301 as_bad (_("Unsupported large constant"));
7302 ++imm_expr
.X_add_number
;
7305 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7306 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7310 expr1
.X_add_number
= 0;
7311 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7313 move_register (&icnt
, xreg
, yreg
);
7314 expr1
.X_add_number
= 2;
7315 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7317 "neg", "x,w", xreg
, xreg
);
7321 /* For consistency checking, verify that all bits are specified either
7322 by the match/mask part of the instruction definition, or by the
7325 validate_mips_insn (opc
)
7326 const struct mips_opcode
*opc
;
7328 const char *p
= opc
->args
;
7330 unsigned long used_bits
= opc
->mask
;
7332 if ((used_bits
& opc
->match
) != opc
->match
)
7334 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7335 opc
->name
, opc
->args
);
7338 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7345 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7346 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7348 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7349 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7350 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7351 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7353 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7354 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7356 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7358 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7359 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7360 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7361 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7362 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7363 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7364 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7365 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7366 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7367 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7368 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7370 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7371 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7372 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7373 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7375 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7376 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7377 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7378 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7379 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7380 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7381 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7382 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7383 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7386 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7387 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7388 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7390 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7391 c
, opc
->name
, opc
->args
);
7395 if (used_bits
!= 0xffffffff)
7397 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7398 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7404 /* This routine assembles an instruction into its binary format. As a
7405 side effect, it sets one of the global variables imm_reloc or
7406 offset_reloc to the type of relocation to do if one of the operands
7407 is an address expression. */
7412 struct mips_cl_insn
*ip
;
7417 struct mips_opcode
*insn
;
7420 unsigned int lastregno
= 0;
7423 int full_opcode_match
= 1;
7427 /* If the instruction contains a '.', we first try to match an instruction
7428 including the '.'. Then we try again without the '.'. */
7430 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7433 /* If we stopped on whitespace, then replace the whitespace with null for
7434 the call to hash_find. Save the character we replaced just in case we
7435 have to re-parse the instruction. */
7442 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7444 /* If we didn't find the instruction in the opcode table, try again, but
7445 this time with just the instruction up to, but not including the
7449 /* Restore the character we overwrite above (if any). */
7453 /* Scan up to the first '.' or whitespace. */
7455 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7459 /* If we did not find a '.', then we can quit now. */
7462 insn_error
= "unrecognized opcode";
7466 /* Lookup the instruction in the hash table. */
7468 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7470 insn_error
= "unrecognized opcode";
7474 full_opcode_match
= 0;
7482 assert (strcmp (insn
->name
, str
) == 0);
7484 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7489 if (insn
->pinfo
!= INSN_MACRO
)
7491 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7497 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7498 && strcmp (insn
->name
, insn
[1].name
) == 0)
7507 static char buf
[100];
7509 _("opcode not supported on this processor: %s (%s)"),
7510 mips_cpu_to_str (mips_arch
),
7511 mips_isa_to_str (mips_opts
.isa
));
7522 ip
->insn_opcode
= insn
->match
;
7524 for (args
= insn
->args
;; ++args
)
7526 s
+= strspn (s
, " \t");
7529 case '\0': /* end of args */
7542 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7546 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7550 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7554 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7560 /* Handle optional base register.
7561 Either the base register is omitted or
7562 we must have a left paren. */
7563 /* This is dependent on the next operand specifier
7564 is a base register specification. */
7565 assert (args
[1] == 'b' || args
[1] == '5'
7566 || args
[1] == '-' || args
[1] == '4');
7570 case ')': /* these must match exactly */
7575 case '<': /* must be at least one digit */
7577 * According to the manual, if the shift amount is greater
7578 * than 31 or less than 0, then the shift amount should be
7579 * mod 32. In reality the mips assembler issues an error.
7580 * We issue a warning and mask out all but the low 5 bits.
7582 my_getExpression (&imm_expr
, s
);
7583 check_absolute_expr (ip
, &imm_expr
);
7584 if ((unsigned long) imm_expr
.X_add_number
> 31)
7586 as_warn (_("Improper shift amount (%ld)"),
7587 (long) imm_expr
.X_add_number
);
7588 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7590 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7591 imm_expr
.X_op
= O_absent
;
7595 case '>': /* shift amount minus 32 */
7596 my_getExpression (&imm_expr
, s
);
7597 check_absolute_expr (ip
, &imm_expr
);
7598 if ((unsigned long) imm_expr
.X_add_number
< 32
7599 || (unsigned long) imm_expr
.X_add_number
> 63)
7601 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7602 imm_expr
.X_op
= O_absent
;
7606 case 'k': /* cache code */
7607 case 'h': /* prefx code */
7608 my_getExpression (&imm_expr
, s
);
7609 check_absolute_expr (ip
, &imm_expr
);
7610 if ((unsigned long) imm_expr
.X_add_number
> 31)
7612 as_warn (_("Invalid value for `%s' (%lu)"),
7614 (unsigned long) imm_expr
.X_add_number
);
7615 imm_expr
.X_add_number
&= 0x1f;
7618 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7620 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7621 imm_expr
.X_op
= O_absent
;
7625 case 'c': /* break code */
7626 my_getExpression (&imm_expr
, s
);
7627 check_absolute_expr (ip
, &imm_expr
);
7628 if ((unsigned) imm_expr
.X_add_number
> 1023)
7630 as_warn (_("Illegal break code (%ld)"),
7631 (long) imm_expr
.X_add_number
);
7632 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7634 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7635 imm_expr
.X_op
= O_absent
;
7639 case 'q': /* lower break code */
7640 my_getExpression (&imm_expr
, s
);
7641 check_absolute_expr (ip
, &imm_expr
);
7642 if ((unsigned) imm_expr
.X_add_number
> 1023)
7644 as_warn (_("Illegal lower break code (%ld)"),
7645 (long) imm_expr
.X_add_number
);
7646 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7648 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7649 imm_expr
.X_op
= O_absent
;
7653 case 'B': /* 20-bit syscall/break code. */
7654 my_getExpression (&imm_expr
, s
);
7655 check_absolute_expr (ip
, &imm_expr
);
7656 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7657 as_warn (_("Illegal 20-bit code (%ld)"),
7658 (long) imm_expr
.X_add_number
);
7659 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7660 imm_expr
.X_op
= O_absent
;
7664 case 'C': /* Coprocessor code */
7665 my_getExpression (&imm_expr
, s
);
7666 check_absolute_expr (ip
, &imm_expr
);
7667 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7669 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7670 (long) imm_expr
.X_add_number
);
7671 imm_expr
.X_add_number
&= ((1<<25) - 1);
7673 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7674 imm_expr
.X_op
= O_absent
;
7678 case 'J': /* 19-bit wait code. */
7679 my_getExpression (&imm_expr
, s
);
7680 check_absolute_expr (ip
, &imm_expr
);
7681 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7682 as_warn (_("Illegal 19-bit code (%ld)"),
7683 (long) imm_expr
.X_add_number
);
7684 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7685 imm_expr
.X_op
= O_absent
;
7689 case 'P': /* Performance register */
7690 my_getExpression (&imm_expr
, s
);
7691 check_absolute_expr (ip
, &imm_expr
);
7692 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7694 as_warn (_("Invalid performance register (%ld)"),
7695 (long) imm_expr
.X_add_number
);
7696 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7698 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7699 imm_expr
.X_op
= O_absent
;
7703 case 'b': /* base register */
7704 case 'd': /* destination register */
7705 case 's': /* source register */
7706 case 't': /* target register */
7707 case 'r': /* both target and source */
7708 case 'v': /* both dest and source */
7709 case 'w': /* both dest and target */
7710 case 'E': /* coprocessor target register */
7711 case 'G': /* coprocessor destination register */
7712 case 'x': /* ignore register name */
7713 case 'z': /* must be zero register */
7714 case 'U': /* destination register (clo/clz). */
7729 while (ISDIGIT (*s
));
7731 as_bad (_("Invalid register number (%d)"), regno
);
7733 else if (*args
== 'E' || *args
== 'G')
7737 if (s
[1] == 'f' && s
[2] == 'p')
7742 else if (s
[1] == 's' && s
[2] == 'p')
7747 else if (s
[1] == 'g' && s
[2] == 'p')
7752 else if (s
[1] == 'a' && s
[2] == 't')
7757 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7762 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7767 else if (itbl_have_entries
)
7772 p
= s
+ 1; /* advance past '$' */
7773 n
= itbl_get_field (&p
); /* n is name */
7775 /* See if this is a register defined in an
7777 if (itbl_get_reg_val (n
, &r
))
7779 /* Get_field advances to the start of
7780 the next field, so we need to back
7781 rack to the end of the last field. */
7785 s
= strchr (s
, '\0');
7798 as_warn (_("Used $at without \".set noat\""));
7804 if (c
== 'r' || c
== 'v' || c
== 'w')
7811 /* 'z' only matches $0. */
7812 if (c
== 'z' && regno
!= 0)
7815 /* Now that we have assembled one operand, we use the args string
7816 * to figure out where it goes in the instruction. */
7823 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7827 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7830 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7831 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7836 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
7839 /* This case exists because on the r3000 trunc
7840 expands into a macro which requires a gp
7841 register. On the r6000 or r4000 it is
7842 assembled into a single instruction which
7843 ignores the register. Thus the insn version
7844 is MIPS_ISA2 and uses 'x', and the macro
7845 version is MIPS_ISA1 and uses 't'. */
7848 /* This case is for the div instruction, which
7849 acts differently if the destination argument
7850 is $0. This only matches $0, and is checked
7851 outside the switch. */
7854 /* Itbl operand; not yet implemented. FIXME ?? */
7856 /* What about all other operands like 'i', which
7857 can be specified in the opcode table? */
7867 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7870 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7875 case 'D': /* floating point destination register */
7876 case 'S': /* floating point source register */
7877 case 'T': /* floating point target register */
7878 case 'R': /* floating point source register */
7882 if (s
[0] == '$' && s
[1] == 'f'
7893 while (ISDIGIT (*s
));
7896 as_bad (_("Invalid float register number (%d)"), regno
);
7898 if ((regno
& 1) != 0
7900 && ! (strcmp (str
, "mtc1") == 0
7901 || strcmp (str
, "mfc1") == 0
7902 || strcmp (str
, "lwc1") == 0
7903 || strcmp (str
, "swc1") == 0
7904 || strcmp (str
, "l.s") == 0
7905 || strcmp (str
, "s.s") == 0))
7906 as_warn (_("Float register should be even, was %d"),
7914 if (c
== 'V' || c
== 'W')
7924 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
7928 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
7932 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
7935 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
7945 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7948 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7954 my_getExpression (&imm_expr
, s
);
7955 if (imm_expr
.X_op
!= O_big
7956 && imm_expr
.X_op
!= O_constant
)
7957 insn_error
= _("absolute expression required");
7962 my_getExpression (&offset_expr
, s
);
7963 *imm_reloc
= BFD_RELOC_32
;
7976 unsigned char temp
[8];
7978 unsigned int length
;
7983 /* These only appear as the last operand in an
7984 instruction, and every instruction that accepts
7985 them in any variant accepts them in all variants.
7986 This means we don't have to worry about backing out
7987 any changes if the instruction does not match.
7989 The difference between them is the size of the
7990 floating point constant and where it goes. For 'F'
7991 and 'L' the constant is 64 bits; for 'f' and 'l' it
7992 is 32 bits. Where the constant is placed is based
7993 on how the MIPS assembler does things:
7996 f -- immediate value
7999 The .lit4 and .lit8 sections are only used if
8000 permitted by the -G argument.
8002 When generating embedded PIC code, we use the
8003 .lit8 section but not the .lit4 section (we can do
8004 .lit4 inline easily; we need to put .lit8
8005 somewhere in the data segment, and using .lit8
8006 permits the linker to eventually combine identical
8009 The code below needs to know whether the target register
8010 is 32 or 64 bits wide. It relies on the fact 'f' and
8011 'F' are used with GPR-based instructions and 'l' and
8012 'L' are used with FPR-based instructions. */
8014 f64
= *args
== 'F' || *args
== 'L';
8015 using_gprs
= *args
== 'F' || *args
== 'f';
8017 save_in
= input_line_pointer
;
8018 input_line_pointer
= s
;
8019 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8021 s
= input_line_pointer
;
8022 input_line_pointer
= save_in
;
8023 if (err
!= NULL
&& *err
!= '\0')
8025 as_bad (_("Bad floating point constant: %s"), err
);
8026 memset (temp
, '\0', sizeof temp
);
8027 length
= f64
? 8 : 4;
8030 assert (length
== (unsigned) (f64
? 8 : 4));
8034 && (! USE_GLOBAL_POINTER_OPT
8035 || mips_pic
== EMBEDDED_PIC
8036 || g_switch_value
< 4
8037 || (temp
[0] == 0 && temp
[1] == 0)
8038 || (temp
[2] == 0 && temp
[3] == 0))))
8040 imm_expr
.X_op
= O_constant
;
8041 if (! target_big_endian
)
8042 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8044 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8047 && ! mips_disable_float_construction
8048 /* Constants can only be constructed in GPRs and
8049 copied to FPRs if the GPRs are at least as wide
8050 as the FPRs. Force the constant into memory if
8051 we are using 64-bit FPRs but the GPRs are only
8054 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8055 && ((temp
[0] == 0 && temp
[1] == 0)
8056 || (temp
[2] == 0 && temp
[3] == 0))
8057 && ((temp
[4] == 0 && temp
[5] == 0)
8058 || (temp
[6] == 0 && temp
[7] == 0)))
8060 /* The value is simple enough to load with a couple of
8061 instructions. If using 32-bit registers, set
8062 imm_expr to the high order 32 bits and offset_expr to
8063 the low order 32 bits. Otherwise, set imm_expr to
8064 the entire 64 bit constant. */
8065 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8067 imm_expr
.X_op
= O_constant
;
8068 offset_expr
.X_op
= O_constant
;
8069 if (! target_big_endian
)
8071 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8072 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8076 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8077 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8079 if (offset_expr
.X_add_number
== 0)
8080 offset_expr
.X_op
= O_absent
;
8082 else if (sizeof (imm_expr
.X_add_number
) > 4)
8084 imm_expr
.X_op
= O_constant
;
8085 if (! target_big_endian
)
8086 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8088 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8092 imm_expr
.X_op
= O_big
;
8093 imm_expr
.X_add_number
= 4;
8094 if (! target_big_endian
)
8096 generic_bignum
[0] = bfd_getl16 (temp
);
8097 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8098 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8099 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8103 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8104 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8105 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8106 generic_bignum
[3] = bfd_getb16 (temp
);
8112 const char *newname
;
8115 /* Switch to the right section. */
8117 subseg
= now_subseg
;
8120 default: /* unused default case avoids warnings. */
8122 newname
= RDATA_SECTION_NAME
;
8123 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8124 || mips_pic
== EMBEDDED_PIC
)
8128 if (mips_pic
== EMBEDDED_PIC
)
8131 newname
= RDATA_SECTION_NAME
;
8134 assert (!USE_GLOBAL_POINTER_OPT
8135 || g_switch_value
>= 4);
8139 new_seg
= subseg_new (newname
, (subsegT
) 0);
8140 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8141 bfd_set_section_flags (stdoutput
, new_seg
,
8146 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8147 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8148 && strcmp (TARGET_OS
, "elf") != 0)
8149 record_alignment (new_seg
, 4);
8151 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8153 as_bad (_("Can't use floating point insn in this section"));
8155 /* Set the argument to the current address in the
8157 offset_expr
.X_op
= O_symbol
;
8158 offset_expr
.X_add_symbol
=
8159 symbol_new ("L0\001", now_seg
,
8160 (valueT
) frag_now_fix (), frag_now
);
8161 offset_expr
.X_add_number
= 0;
8163 /* Put the floating point number into the section. */
8164 p
= frag_more ((int) length
);
8165 memcpy (p
, temp
, length
);
8167 /* Switch back to the original section. */
8168 subseg_set (seg
, subseg
);
8173 case 'i': /* 16 bit unsigned immediate */
8174 case 'j': /* 16 bit signed immediate */
8175 *imm_reloc
= BFD_RELOC_LO16
;
8176 c
= my_getSmallExpression (&imm_expr
, s
);
8181 if (imm_expr
.X_op
== O_constant
)
8182 imm_expr
.X_add_number
=
8183 (imm_expr
.X_add_number
>> 16) & 0xffff;
8185 else if (c
== S_EX_HIGHEST
)
8186 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8187 else if (c
== S_EX_HIGHER
)
8188 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8189 else if (c
== S_EX_GP_REL
)
8191 /* This occurs in NewABI only. */
8192 c
= my_getSmallExpression (&imm_expr
, s
);
8194 as_bad (_("bad composition of relocations"));
8197 c
= my_getSmallExpression (&imm_expr
, s
);
8199 as_bad (_("bad composition of relocations"));
8202 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8203 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8204 imm_reloc
[2] = BFD_RELOC_LO16
;
8209 else if (c
== S_EX_HI
)
8211 *imm_reloc
= BFD_RELOC_HI16_S
;
8212 imm_unmatched_hi
= true;
8215 *imm_reloc
= BFD_RELOC_HI16
;
8217 else if (imm_expr
.X_op
== O_constant
)
8218 imm_expr
.X_add_number
&= 0xffff;
8222 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8223 || ((imm_expr
.X_add_number
< 0
8224 || imm_expr
.X_add_number
>= 0x10000)
8225 && imm_expr
.X_op
== O_constant
))
8227 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8228 !strcmp (insn
->name
, insn
[1].name
))
8230 if (imm_expr
.X_op
== O_constant
8231 || imm_expr
.X_op
== O_big
)
8232 as_bad (_("16 bit expression not in range 0..65535"));
8240 /* The upper bound should be 0x8000, but
8241 unfortunately the MIPS assembler accepts numbers
8242 from 0x8000 to 0xffff and sign extends them, and
8243 we want to be compatible. We only permit this
8244 extended range for an instruction which does not
8245 provide any further alternates, since those
8246 alternates may handle other cases. People should
8247 use the numbers they mean, rather than relying on
8248 a mysterious sign extension. */
8249 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8250 strcmp (insn
->name
, insn
[1].name
) == 0);
8255 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8256 || ((imm_expr
.X_add_number
< -0x8000
8257 || imm_expr
.X_add_number
>= max
)
8258 && imm_expr
.X_op
== O_constant
)
8260 && imm_expr
.X_add_number
< 0
8262 && imm_expr
.X_unsigned
8263 && sizeof (imm_expr
.X_add_number
) <= 4))
8267 if (imm_expr
.X_op
== O_constant
8268 || imm_expr
.X_op
== O_big
)
8269 as_bad (_("16 bit expression not in range -32768..32767"));
8275 case 'o': /* 16 bit offset */
8276 c
= my_getSmallExpression (&offset_expr
, s
);
8278 /* If this value won't fit into a 16 bit offset, then go
8279 find a macro that will generate the 32 bit offset
8282 && (offset_expr
.X_op
!= O_constant
8283 || offset_expr
.X_add_number
>= 0x8000
8284 || offset_expr
.X_add_number
< -0x8000))
8289 if (offset_expr
.X_op
!= O_constant
)
8291 offset_expr
.X_add_number
=
8292 (offset_expr
.X_add_number
>> 16) & 0xffff;
8294 *offset_reloc
= BFD_RELOC_LO16
;
8298 case 'p': /* pc relative offset */
8299 if (mips_pic
== EMBEDDED_PIC
)
8300 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8302 *offset_reloc
= BFD_RELOC_16_PCREL
;
8303 my_getExpression (&offset_expr
, s
);
8307 case 'u': /* upper 16 bits */
8308 c
= my_getSmallExpression (&imm_expr
, s
);
8309 *imm_reloc
= BFD_RELOC_LO16
;
8314 if (imm_expr
.X_op
== O_constant
)
8315 imm_expr
.X_add_number
=
8316 (imm_expr
.X_add_number
>> 16) & 0xffff;
8318 else if (c
== S_EX_HIGHEST
)
8319 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8320 else if (c
== S_EX_HI
)
8322 *imm_reloc
= BFD_RELOC_HI16_S
;
8323 imm_unmatched_hi
= true;
8325 else if (c
== S_EX_GP_REL
)
8327 /* This occurs in NewABI only. */
8328 c
= my_getSmallExpression (&imm_expr
, s
);
8330 as_bad (_("bad composition of relocations"));
8333 c
= my_getSmallExpression (&imm_expr
, s
);
8335 as_bad (_("bad composition of relocations"));
8338 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8339 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8340 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8346 *imm_reloc
= BFD_RELOC_HI16
;
8348 else if (imm_expr
.X_op
== O_constant
)
8349 imm_expr
.X_add_number
&= 0xffff;
8351 if (imm_expr
.X_op
== O_constant
8352 && (imm_expr
.X_add_number
< 0
8353 || imm_expr
.X_add_number
>= 0x10000))
8354 as_bad (_("lui expression not in range 0..65535"));
8358 case 'a': /* 26 bit address */
8359 my_getExpression (&offset_expr
, s
);
8361 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8364 case 'N': /* 3 bit branch condition code */
8365 case 'M': /* 3 bit compare condition code */
8366 if (strncmp (s
, "$fcc", 4) != 0)
8376 while (ISDIGIT (*s
));
8378 as_bad (_("invalid condition code register $fcc%d"), regno
);
8380 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8382 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8386 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8397 while (ISDIGIT (*s
));
8400 c
= 8; /* Invalid sel value. */
8403 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8404 ip
->insn_opcode
|= c
;
8408 as_bad (_("bad char = '%c'\n"), *args
);
8413 /* Args don't match. */
8414 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8415 !strcmp (insn
->name
, insn
[1].name
))
8419 insn_error
= _("illegal operands");
8424 insn_error
= _("illegal operands");
8429 /* This routine assembles an instruction into its binary format when
8430 assembling for the mips16. As a side effect, it sets one of the
8431 global variables imm_reloc or offset_reloc to the type of
8432 relocation to do if one of the operands is an address expression.
8433 It also sets mips16_small and mips16_ext if the user explicitly
8434 requested a small or extended instruction. */
8439 struct mips_cl_insn
*ip
;
8443 struct mips_opcode
*insn
;
8446 unsigned int lastregno
= 0;
8451 mips16_small
= false;
8454 for (s
= str
; ISLOWER (*s
); ++s
)
8466 if (s
[1] == 't' && s
[2] == ' ')
8469 mips16_small
= true;
8473 else if (s
[1] == 'e' && s
[2] == ' ')
8482 insn_error
= _("unknown opcode");
8486 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8487 mips16_small
= true;
8489 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8491 insn_error
= _("unrecognized opcode");
8498 assert (strcmp (insn
->name
, str
) == 0);
8501 ip
->insn_opcode
= insn
->match
;
8502 ip
->use_extend
= false;
8503 imm_expr
.X_op
= O_absent
;
8504 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8505 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8506 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8507 offset_expr
.X_op
= O_absent
;
8508 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8509 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8510 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8511 for (args
= insn
->args
; 1; ++args
)
8518 /* In this switch statement we call break if we did not find
8519 a match, continue if we did find a match, or return if we
8528 /* Stuff the immediate value in now, if we can. */
8529 if (imm_expr
.X_op
== O_constant
8530 && *imm_reloc
> BFD_RELOC_UNUSED
8531 && insn
->pinfo
!= INSN_MACRO
)
8533 mips16_immed ((char *) NULL
, 0,
8534 *imm_reloc
- BFD_RELOC_UNUSED
,
8535 imm_expr
.X_add_number
, true, mips16_small
,
8536 mips16_ext
, &ip
->insn_opcode
,
8537 &ip
->use_extend
, &ip
->extend
);
8538 imm_expr
.X_op
= O_absent
;
8539 *imm_reloc
= BFD_RELOC_UNUSED
;
8553 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8556 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8572 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8574 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8601 while (ISDIGIT (*s
));
8604 as_bad (_("invalid register number (%d)"), regno
);
8610 if (s
[1] == 'f' && s
[2] == 'p')
8615 else if (s
[1] == 's' && s
[2] == 'p')
8620 else if (s
[1] == 'g' && s
[2] == 'p')
8625 else if (s
[1] == 'a' && s
[2] == 't')
8630 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8635 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8648 if (c
== 'v' || c
== 'w')
8650 regno
= mips16_to_32_reg_map
[lastregno
];
8664 regno
= mips32_to_16_reg_map
[regno
];
8669 regno
= ILLEGAL_REG
;
8674 regno
= ILLEGAL_REG
;
8679 regno
= ILLEGAL_REG
;
8684 if (regno
== AT
&& ! mips_opts
.noat
)
8685 as_warn (_("used $at without \".set noat\""));
8692 if (regno
== ILLEGAL_REG
)
8699 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8703 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8706 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8709 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8715 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8718 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8719 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8729 if (strncmp (s
, "$pc", 3) == 0)
8753 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8755 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8756 and generate the appropriate reloc. If the text
8757 inside %gprel is not a symbol name with an
8758 optional offset, then we generate a normal reloc
8759 and will probably fail later. */
8760 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8761 if (imm_expr
.X_op
== O_symbol
)
8764 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8766 ip
->use_extend
= true;
8773 /* Just pick up a normal expression. */
8774 my_getExpression (&imm_expr
, s
);
8777 if (imm_expr
.X_op
== O_register
)
8779 /* What we thought was an expression turned out to
8782 if (s
[0] == '(' && args
[1] == '(')
8784 /* It looks like the expression was omitted
8785 before a register indirection, which means
8786 that the expression is implicitly zero. We
8787 still set up imm_expr, so that we handle
8788 explicit extensions correctly. */
8789 imm_expr
.X_op
= O_constant
;
8790 imm_expr
.X_add_number
= 0;
8791 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8798 /* We need to relax this instruction. */
8799 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8808 /* We use offset_reloc rather than imm_reloc for the PC
8809 relative operands. This lets macros with both
8810 immediate and address operands work correctly. */
8811 my_getExpression (&offset_expr
, s
);
8813 if (offset_expr
.X_op
== O_register
)
8816 /* We need to relax this instruction. */
8817 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8821 case '6': /* break code */
8822 my_getExpression (&imm_expr
, s
);
8823 check_absolute_expr (ip
, &imm_expr
);
8824 if ((unsigned long) imm_expr
.X_add_number
> 63)
8826 as_warn (_("Invalid value for `%s' (%lu)"),
8828 (unsigned long) imm_expr
.X_add_number
);
8829 imm_expr
.X_add_number
&= 0x3f;
8831 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8832 imm_expr
.X_op
= O_absent
;
8836 case 'a': /* 26 bit address */
8837 my_getExpression (&offset_expr
, s
);
8839 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8840 ip
->insn_opcode
<<= 16;
8843 case 'l': /* register list for entry macro */
8844 case 'L': /* register list for exit macro */
8854 int freg
, reg1
, reg2
;
8856 while (*s
== ' ' || *s
== ',')
8860 as_bad (_("can't parse register list"));
8872 while (ISDIGIT (*s
))
8894 as_bad (_("invalid register list"));
8899 while (ISDIGIT (*s
))
8906 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8911 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8916 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8917 mask
|= (reg2
- 3) << 3;
8918 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8919 mask
|= (reg2
- 15) << 1;
8920 else if (reg1
== 31 && reg2
== 31)
8924 as_bad (_("invalid register list"));
8928 /* The mask is filled in in the opcode table for the
8929 benefit of the disassembler. We remove it before
8930 applying the actual mask. */
8931 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8932 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8936 case 'e': /* extend code */
8937 my_getExpression (&imm_expr
, s
);
8938 check_absolute_expr (ip
, &imm_expr
);
8939 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8941 as_warn (_("Invalid value for `%s' (%lu)"),
8943 (unsigned long) imm_expr
.X_add_number
);
8944 imm_expr
.X_add_number
&= 0x7ff;
8946 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8947 imm_expr
.X_op
= O_absent
;
8957 /* Args don't match. */
8958 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8959 strcmp (insn
->name
, insn
[1].name
) == 0)
8966 insn_error
= _("illegal operands");
8972 /* This structure holds information we know about a mips16 immediate
8975 struct mips16_immed_operand
8977 /* The type code used in the argument string in the opcode table. */
8979 /* The number of bits in the short form of the opcode. */
8981 /* The number of bits in the extended form of the opcode. */
8983 /* The amount by which the short form is shifted when it is used;
8984 for example, the sw instruction has a shift count of 2. */
8986 /* The amount by which the short form is shifted when it is stored
8987 into the instruction code. */
8989 /* Non-zero if the short form is unsigned. */
8991 /* Non-zero if the extended form is unsigned. */
8993 /* Non-zero if the value is PC relative. */
8997 /* The mips16 immediate operand types. */
8999 static const struct mips16_immed_operand mips16_immed_operands
[] =
9001 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9002 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9003 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9004 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9005 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9006 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9007 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9008 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9009 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9010 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9011 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9012 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9013 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9014 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9015 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9016 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9017 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9018 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9019 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9020 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9021 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9024 #define MIPS16_NUM_IMMED \
9025 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9027 /* Handle a mips16 instruction with an immediate value. This or's the
9028 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9029 whether an extended value is needed; if one is needed, it sets
9030 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9031 If SMALL is true, an unextended opcode was explicitly requested.
9032 If EXT is true, an extended opcode was explicitly requested. If
9033 WARN is true, warn if EXT does not match reality. */
9036 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9045 unsigned long *insn
;
9046 boolean
*use_extend
;
9047 unsigned short *extend
;
9049 register const struct mips16_immed_operand
*op
;
9050 int mintiny
, maxtiny
;
9053 op
= mips16_immed_operands
;
9054 while (op
->type
!= type
)
9057 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9062 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9065 maxtiny
= 1 << op
->nbits
;
9070 maxtiny
= (1 << op
->nbits
) - 1;
9075 mintiny
= - (1 << (op
->nbits
- 1));
9076 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9079 /* Branch offsets have an implicit 0 in the lowest bit. */
9080 if (type
== 'p' || type
== 'q')
9083 if ((val
& ((1 << op
->shift
) - 1)) != 0
9084 || val
< (mintiny
<< op
->shift
)
9085 || val
> (maxtiny
<< op
->shift
))
9090 if (warn
&& ext
&& ! needext
)
9091 as_warn_where (file
, line
,
9092 _("extended operand requested but not required"));
9093 if (small
&& needext
)
9094 as_bad_where (file
, line
, _("invalid unextended operand value"));
9096 if (small
|| (! ext
&& ! needext
))
9100 *use_extend
= false;
9101 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9102 insnval
<<= op
->op_shift
;
9107 long minext
, maxext
;
9113 maxext
= (1 << op
->extbits
) - 1;
9117 minext
= - (1 << (op
->extbits
- 1));
9118 maxext
= (1 << (op
->extbits
- 1)) - 1;
9120 if (val
< minext
|| val
> maxext
)
9121 as_bad_where (file
, line
,
9122 _("operand value out of range for instruction"));
9125 if (op
->extbits
== 16)
9127 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9130 else if (op
->extbits
== 15)
9132 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9137 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9141 *extend
= (unsigned short) extval
;
9146 static struct percent_op_match
9149 const enum small_ex_type type
;
9153 {"%half", S_EX_HALF
},
9158 {"%gp_rel", S_EX_GP_REL
},
9160 {"%call16", S_EX_CALL16
},
9161 {"%got_disp", S_EX_GOT_DISP
},
9162 {"%got_page", S_EX_GOT_PAGE
},
9163 {"%got_ofst", S_EX_GOT_OFST
},
9164 {"%got_hi", S_EX_GOT_HI
},
9165 {"%got_lo", S_EX_GOT_LO
},
9167 {"%higher", S_EX_HIGHER
},
9168 {"%highest", S_EX_HIGHEST
},
9169 {"%call_hi", S_EX_CALL_HI
},
9170 {"%call_lo", S_EX_CALL_LO
}
9174 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9175 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9176 can be nested, this is handled by blanking the innermost, parsing the
9177 rest by subsequent calls. */
9180 my_getSmallParser (str
, len
, nestlevel
)
9185 int type
= S_EX_NONE
;
9188 *str
+= strspn (*str
, " \t");
9191 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9194 /* Check for base register. */
9198 && (e
= b
+ strcspn (b
, ") \t"))
9199 && e
- b
> 1 && e
- b
< 4)
9202 && ((b
[1] == 'f' && b
[2] == 'p')
9203 || (b
[1] == 's' && b
[2] == 'p')
9204 || (b
[1] == 'g' && b
[2] == 'p')
9205 || (b
[1] == 'a' && b
[2] == 't')
9207 && ISDIGIT (b
[2]))))
9208 || (ISDIGIT (b
[1])))
9210 *len
= strcspn (*str
, ")") + 1;
9211 return S_EX_REGISTER
;
9215 else if (b
[0] == '%')
9221 /* Some other expression in the braces. */
9222 *len
= strcspn (*str
, ")") + 1;
9224 /* Check for percent_op. */
9225 else if (*str
[0] == '%')
9234 while (ISALPHA (*tmp
) || *tmp
== '_')
9236 *tmp
= TOLOWER (*tmp
);
9239 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9241 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9245 type
= percent_op
[i
].type
;
9247 /* Only %hi and %lo are allowed for OldABI. */
9248 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9251 *len
= strlen (percent_op
[i
].str
);
9258 /* Any other expression. */
9263 my_getSmallExpression (ep
, str
)
9267 static char *oldstr
= NULL
;
9273 /* Don't update oldstr if the last call had nested percent_op's. */
9280 c
= my_getSmallParser (&str
, &len
, &nest_level
);
9281 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9284 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9286 /* A percent_op was encountered. */
9289 /* Don't try to get an expression if it is already blanked out. */
9290 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9294 save
= *(str
+ len
);
9295 *(str
+ len
) = '\0';
9296 my_getExpression (ep
, str
);
9297 *(str
+ len
) = save
;
9301 /* blank out including the % sign. */
9302 char *p
= strrchr (oldstr
, '%');
9303 memset (p
, ' ', str
- p
+ len
);
9308 expr_end
= strchr (str
, ')') + 1;
9312 else if (c
== S_EX_NONE
)
9314 my_getExpression (ep
, str
);
9316 else if (c
== S_EX_REGISTER
)
9318 ep
->X_op
= O_constant
;
9320 ep
->X_add_symbol
= NULL
;
9321 ep
->X_op_symbol
= NULL
;
9322 ep
->X_add_number
= 0;
9326 as_fatal(_("internal error"));
9329 if (nest_level
<= 1)
9336 my_getExpression (ep
, str
)
9343 save_in
= input_line_pointer
;
9344 input_line_pointer
= str
;
9346 expr_end
= input_line_pointer
;
9347 input_line_pointer
= save_in
;
9349 /* If we are in mips16 mode, and this is an expression based on `.',
9350 then we bump the value of the symbol by 1 since that is how other
9351 text symbols are handled. We don't bother to handle complex
9352 expressions, just `.' plus or minus a constant. */
9353 if (mips_opts
.mips16
9354 && ep
->X_op
== O_symbol
9355 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9356 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9357 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9358 && symbol_constant_p (ep
->X_add_symbol
)
9359 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9360 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9363 /* Turn a string in input_line_pointer into a floating point constant
9364 of type TYPE, and store the appropriate bytes in *LITP. The number
9365 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9366 returned, or NULL on OK. */
9369 md_atof (type
, litP
, sizeP
)
9375 LITTLENUM_TYPE words
[4];
9391 return _("bad call to md_atof");
9394 t
= atof_ieee (input_line_pointer
, type
, words
);
9396 input_line_pointer
= t
;
9400 if (! target_big_endian
)
9402 for (i
= prec
- 1; i
>= 0; i
--)
9404 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9410 for (i
= 0; i
< prec
; i
++)
9412 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9421 md_number_to_chars (buf
, val
, n
)
9426 if (target_big_endian
)
9427 number_to_chars_bigendian (buf
, val
, n
);
9429 number_to_chars_littleendian (buf
, val
, n
);
9432 static int support_64bit_objects(void)
9434 const char **list
, **l
;
9436 list
= bfd_target_list ();
9437 for (l
= list
; *l
!= NULL
; l
++)
9439 /* This is traditional mips */
9440 if (strcmp (*l
, "elf64-tradbigmips") == 0
9441 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9443 if (strcmp (*l
, "elf64-bigmips") == 0
9444 || strcmp (*l
, "elf64-littlemips") == 0)
9448 return (*l
!= NULL
);
9451 CONST
char *md_shortopts
= "nO::g::G:";
9453 struct option md_longopts
[] =
9455 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9456 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9457 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9458 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9459 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9460 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9461 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9462 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9463 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9464 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9465 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9466 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9467 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9468 #define OPTION_TRAP (OPTION_MD_BASE + 7)
9469 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9470 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9471 #define OPTION_BREAK (OPTION_MD_BASE + 8)
9472 {"break", no_argument
, NULL
, OPTION_BREAK
},
9473 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9474 #define OPTION_EB (OPTION_MD_BASE + 9)
9475 {"EB", no_argument
, NULL
, OPTION_EB
},
9476 #define OPTION_EL (OPTION_MD_BASE + 10)
9477 {"EL", no_argument
, NULL
, OPTION_EL
},
9478 #define OPTION_M4650 (OPTION_MD_BASE + 11)
9479 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9480 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
9481 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9482 #define OPTION_M4010 (OPTION_MD_BASE + 13)
9483 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9484 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
9485 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9486 #define OPTION_M4100 (OPTION_MD_BASE + 15)
9487 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9488 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
9489 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9490 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
9491 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9492 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
9493 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9494 #define OPTION_M3900 (OPTION_MD_BASE + 19)
9495 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9496 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
9497 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9498 #define OPTION_MABI (OPTION_MD_BASE + 21)
9499 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9500 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
9501 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9502 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
9503 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9504 #define OPTION_GP32 (OPTION_MD_BASE + 24)
9505 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9506 #define OPTION_GP64 (OPTION_MD_BASE + 25)
9507 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9508 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
9509 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9510 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
9511 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9512 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
9513 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9514 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
9515 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9516 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
9517 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9518 #define OPTION_MARCH (OPTION_MD_BASE + 31)
9519 {"march", required_argument
, NULL
, OPTION_MARCH
},
9520 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
9521 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9522 #define OPTION_FP32 (OPTION_MD_BASE + 33)
9523 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9525 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
9526 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9527 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9528 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9529 #define OPTION_32 (OPTION_ELF_BASE + 3)
9530 #define OPTION_N32 (OPTION_ELF_BASE + 4)
9531 #define OPTION_64 (OPTION_ELF_BASE + 5)
9532 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9533 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9534 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9535 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9536 {"32", no_argument
, NULL
, OPTION_32
},
9537 {"n32", no_argument
, NULL
, OPTION_N32
},
9538 {"64", no_argument
, NULL
, OPTION_64
},
9541 {NULL
, no_argument
, NULL
, 0}
9543 size_t md_longopts_size
= sizeof (md_longopts
);
9546 md_parse_option (c
, arg
)
9552 case OPTION_CONSTRUCT_FLOATS
:
9553 mips_disable_float_construction
= 0;
9556 case OPTION_NO_CONSTRUCT_FLOATS
:
9557 mips_disable_float_construction
= 1;
9569 target_big_endian
= 1;
9573 target_big_endian
= 0;
9581 if (arg
&& arg
[1] == '0')
9591 mips_debug
= atoi (arg
);
9592 /* When the MIPS assembler sees -g or -g2, it does not do
9593 optimizations which limit full symbolic debugging. We take
9594 that to be equivalent to -O0. */
9595 if (mips_debug
== 2)
9600 mips_opts
.isa
= ISA_MIPS1
;
9604 mips_opts
.isa
= ISA_MIPS2
;
9608 mips_opts
.isa
= ISA_MIPS3
;
9612 mips_opts
.isa
= ISA_MIPS4
;
9616 mips_opts
.isa
= ISA_MIPS5
;
9620 mips_opts
.isa
= ISA_MIPS32
;
9624 mips_opts
.isa
= ISA_MIPS64
;
9631 int cpu
= CPU_UNKNOWN
;
9633 /* Identify the processor type. */
9634 if (strcasecmp (arg
, "default") != 0)
9636 const struct mips_cpu_info
*ci
;
9638 ci
= mips_cpu_info_from_name (arg
);
9639 if (ci
== NULL
|| ci
->is_isa
)
9644 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9647 as_fatal (_("invalid architecture -march=%s"), arg
);
9650 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9661 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9662 as_warn(_("A different -mtune= was already specified, is now "
9667 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9668 as_warn(_("A different -march= was already specified, is now "
9673 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9674 as_warn(_("A different -mcpu= was already specified, is now "
9682 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9683 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9684 as_warn(_("A different -march= or -mtune= was already specified, "
9686 mips_arch
= CPU_R4650
;
9687 mips_tune
= CPU_R4650
;
9690 case OPTION_NO_M4650
:
9694 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9695 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9696 as_warn(_("A different -march= or -mtune= was already specified, "
9698 mips_arch
= CPU_R4010
;
9699 mips_tune
= CPU_R4010
;
9702 case OPTION_NO_M4010
:
9706 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9707 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9708 as_warn(_("A different -march= or -mtune= was already specified, "
9710 mips_arch
= CPU_VR4100
;
9711 mips_tune
= CPU_VR4100
;
9714 case OPTION_NO_M4100
:
9718 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9719 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9720 as_warn(_("A different -march= or -mtune= was already specified, "
9722 mips_arch
= CPU_R3900
;
9723 mips_tune
= CPU_R3900
;
9726 case OPTION_NO_M3900
:
9730 mips_opts
.mips16
= 1;
9731 mips_no_prev_insn (false);
9734 case OPTION_NO_MIPS16
:
9735 mips_opts
.mips16
= 0;
9736 mips_no_prev_insn (false);
9739 case OPTION_MEMBEDDED_PIC
:
9740 mips_pic
= EMBEDDED_PIC
;
9741 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9743 as_bad (_("-G may not be used with embedded PIC code"));
9746 g_switch_value
= 0x7fffffff;
9750 /* When generating ELF code, we permit -KPIC and -call_shared to
9751 select SVR4_PIC, and -non_shared to select no PIC. This is
9752 intended to be compatible with Irix 5. */
9753 case OPTION_CALL_SHARED
:
9754 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9756 as_bad (_("-call_shared is supported only for ELF format"));
9759 mips_pic
= SVR4_PIC
;
9760 if (g_switch_seen
&& g_switch_value
!= 0)
9762 as_bad (_("-G may not be used with SVR4 PIC code"));
9768 case OPTION_NON_SHARED
:
9769 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9771 as_bad (_("-non_shared is supported only for ELF format"));
9777 /* The -xgot option tells the assembler to use 32 offsets when
9778 accessing the got in SVR4_PIC mode. It is for Irix
9783 #endif /* OBJ_ELF */
9786 if (! USE_GLOBAL_POINTER_OPT
)
9788 as_bad (_("-G is not supported for this configuration"));
9791 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9793 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9797 g_switch_value
= atoi (arg
);
9802 /* The -32 and -64 options tell the assembler to output the 32
9803 bit or the 64 bit MIPS ELF format. */
9814 if (! support_64bit_objects())
9815 as_fatal (_("No compiled in support for 64 bit object file format"));
9820 if (mips_abi
!= O32_ABI
)
9826 if (mips_abi
== O32_ABI
)
9832 if (mips_abi
!= O32_ABI
)
9837 if (strcmp (arg
, "32") == 0)
9839 else if (strcmp (arg
, "o64") == 0)
9841 else if (strcmp (arg
, "n32") == 0)
9843 else if (strcmp (arg
, "64") == 0)
9846 if (! support_64bit_objects())
9847 as_fatal (_("No compiled in support for 64 bit object file "
9850 else if (strcmp (arg
, "eabi") == 0)
9851 mips_abi
= EABI_ABI
;
9855 #endif /* OBJ_ELF */
9857 case OPTION_M7000_HILO_FIX
:
9858 mips_7000_hilo_fix
= true;
9861 case OPTION_NO_M7000_HILO_FIX
:
9862 mips_7000_hilo_fix
= false;
9873 show (stream
, string
, col_p
, first_p
)
9881 fprintf (stream
, "%24s", "");
9886 fprintf (stream
, ", ");
9890 if (*col_p
+ strlen (string
) > 72)
9892 fprintf (stream
, "\n%24s", "");
9896 fprintf (stream
, "%s", string
);
9897 *col_p
+= strlen (string
);
9903 md_show_usage (stream
)
9908 fprintf (stream
, _("\
9910 -membedded-pic generate embedded position independent code\n\
9911 -EB generate big endian output\n\
9912 -EL generate little endian output\n\
9913 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9914 -G NUM allow referencing objects up to NUM bytes\n\
9915 implicitly with the gp register [default 8]\n"));
9916 fprintf (stream
, _("\
9917 -mips1 generate MIPS ISA I instructions\n\
9918 -mips2 generate MIPS ISA II instructions\n\
9919 -mips3 generate MIPS ISA III instructions\n\
9920 -mips4 generate MIPS ISA IV instructions\n\
9921 -mips5 generate MIPS ISA V instructions\n\
9922 -mips32 generate MIPS32 ISA instructions\n\
9923 -mips64 generate MIPS64 ISA instructions\n\
9924 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9928 show (stream
, "2000", &column
, &first
);
9929 show (stream
, "3000", &column
, &first
);
9930 show (stream
, "3900", &column
, &first
);
9931 show (stream
, "4000", &column
, &first
);
9932 show (stream
, "4010", &column
, &first
);
9933 show (stream
, "4100", &column
, &first
);
9934 show (stream
, "4111", &column
, &first
);
9935 show (stream
, "4300", &column
, &first
);
9936 show (stream
, "4400", &column
, &first
);
9937 show (stream
, "4600", &column
, &first
);
9938 show (stream
, "4650", &column
, &first
);
9939 show (stream
, "5000", &column
, &first
);
9940 show (stream
, "5200", &column
, &first
);
9941 show (stream
, "5230", &column
, &first
);
9942 show (stream
, "5231", &column
, &first
);
9943 show (stream
, "5261", &column
, &first
);
9944 show (stream
, "5721", &column
, &first
);
9945 show (stream
, "6000", &column
, &first
);
9946 show (stream
, "8000", &column
, &first
);
9947 show (stream
, "10000", &column
, &first
);
9948 show (stream
, "12000", &column
, &first
);
9949 show (stream
, "sb1", &column
, &first
);
9950 fputc ('\n', stream
);
9952 fprintf (stream
, _("\
9953 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9954 -no-mCPU don't generate code specific to CPU.\n\
9955 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9959 show (stream
, "3900", &column
, &first
);
9960 show (stream
, "4010", &column
, &first
);
9961 show (stream
, "4100", &column
, &first
);
9962 show (stream
, "4650", &column
, &first
);
9963 fputc ('\n', stream
);
9965 fprintf (stream
, _("\
9966 -mips16 generate mips16 instructions\n\
9967 -no-mips16 do not generate mips16 instructions\n"));
9968 fprintf (stream
, _("\
9969 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9970 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9971 -O0 remove unneeded NOPs, do not swap branches\n\
9972 -O remove unneeded NOPs and swap branches\n\
9973 -n warn about NOPs generated from macros\n\
9974 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9975 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9976 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9978 fprintf (stream
, _("\
9979 -KPIC, -call_shared generate SVR4 position independent code\n\
9980 -non_shared do not generate position independent code\n\
9981 -xgot assume a 32 bit GOT\n\
9982 -32 create o32 ABI object file (default)\n\
9983 -n32 create n32 ABI object file\n\
9984 -64 create 64 ABI object file\n"));
9989 mips_init_after_args ()
9991 /* initialize opcodes */
9992 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9993 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9997 md_pcrel_from (fixP
)
10000 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10001 && fixP
->fx_addsy
!= (symbolS
*) NULL
10002 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10004 /* This makes a branch to an undefined symbol be a branch to the
10005 current location. */
10006 if (mips_pic
== EMBEDDED_PIC
)
10012 /* return the address of the delay slot */
10013 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10016 /* This is called before the symbol table is processed. In order to
10017 work with gcc when using mips-tfile, we must keep all local labels.
10018 However, in other cases, we want to discard them. If we were
10019 called with -g, but we didn't see any debugging information, it may
10020 mean that gcc is smuggling debugging information through to
10021 mips-tfile, in which case we must generate all local labels. */
10024 mips_frob_file_before_adjust ()
10026 #ifndef NO_ECOFF_DEBUGGING
10027 if (ECOFF_DEBUGGING
10029 && ! ecoff_debugging_seen
)
10030 flag_keep_locals
= 1;
10034 /* Sort any unmatched HI16_S relocs so that they immediately precede
10035 the corresponding LO reloc. This is called before md_apply_fix and
10036 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10037 explicit use of the %hi modifier. */
10042 struct mips_hi_fixup
*l
;
10044 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10046 segment_info_type
*seginfo
;
10049 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10051 /* Check quickly whether the next fixup happens to be a matching
10053 if (l
->fixp
->fx_next
!= NULL
10054 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10055 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10056 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10059 /* Look through the fixups for this segment for a matching %lo.
10060 When we find one, move the %hi just in front of it. We do
10061 this in two passes. In the first pass, we try to find a
10062 unique %lo. In the second pass, we permit multiple %hi
10063 relocs for a single %lo (this is a GNU extension). */
10064 seginfo
= seg_info (l
->seg
);
10065 for (pass
= 0; pass
< 2; pass
++)
10070 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10072 /* Check whether this is a %lo fixup which matches l->fixp. */
10073 if (f
->fx_r_type
== BFD_RELOC_LO16
10074 && f
->fx_addsy
== l
->fixp
->fx_addsy
10075 && f
->fx_offset
== l
->fixp
->fx_offset
10078 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10079 || prev
->fx_addsy
!= f
->fx_addsy
10080 || prev
->fx_offset
!= f
->fx_offset
))
10084 /* Move l->fixp before f. */
10085 for (pf
= &seginfo
->fix_root
;
10087 pf
= &(*pf
)->fx_next
)
10088 assert (*pf
!= NULL
);
10090 *pf
= l
->fixp
->fx_next
;
10092 l
->fixp
->fx_next
= f
;
10094 seginfo
->fix_root
= l
->fixp
;
10096 prev
->fx_next
= l
->fixp
;
10107 #if 0 /* GCC code motion plus incomplete dead code elimination
10108 can leave a %hi without a %lo. */
10110 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10111 _("Unmatched %%hi reloc"));
10117 /* When generating embedded PIC code we need to use a special
10118 relocation to represent the difference of two symbols in the .text
10119 section (switch tables use a difference of this sort). See
10120 include/coff/mips.h for details. This macro checks whether this
10121 fixup requires the special reloc. */
10122 #define SWITCH_TABLE(fixp) \
10123 ((fixp)->fx_r_type == BFD_RELOC_32 \
10124 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10125 && (fixp)->fx_addsy != NULL \
10126 && (fixp)->fx_subsy != NULL \
10127 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10128 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10130 /* When generating embedded PIC code we must keep all PC relative
10131 relocations, in case the linker has to relax a call. We also need
10132 to keep relocations for switch table entries.
10134 We may have combined relocations without symbols in the N32/N64 ABI.
10135 We have to prevent gas from dropping them. */
10138 mips_force_relocation (fixp
)
10141 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10142 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10146 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10147 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10148 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10149 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10153 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10154 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10155 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10156 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10159 return (mips_pic
== EMBEDDED_PIC
10161 || SWITCH_TABLE (fixp
)
10162 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10163 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10166 /* Apply a fixup to the object file. */
10169 md_apply_fix (fixP
, valueP
)
10173 unsigned char *buf
;
10177 assert (fixP
->fx_size
== 4
10178 || fixP
->fx_r_type
== BFD_RELOC_16
10179 || fixP
->fx_r_type
== BFD_RELOC_32
10180 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10181 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10182 || fixP
->fx_r_type
== BFD_RELOC_LO16
10183 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10184 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10185 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10186 || fixP
->fx_r_type
== BFD_RELOC_64
10187 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10188 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10189 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10190 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10191 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10192 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10193 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10194 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10195 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10199 /* If we aren't adjusting this fixup to be against the section
10200 symbol, we need to adjust the value. */
10202 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10204 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10205 || ((S_IS_WEAK (fixP
->fx_addsy
)
10206 || S_IS_EXTERN (fixP
->fx_addsy
))
10207 && !S_IS_COMMON (fixP
->fx_addsy
))
10208 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10209 && (((bfd_get_section_flags (stdoutput
,
10210 S_GET_SEGMENT (fixP
->fx_addsy
))
10211 & SEC_LINK_ONCE
) != 0)
10212 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10214 sizeof (".gnu.linkonce") - 1))))
10217 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10220 && ! fixP
->fx_pcrel
10221 && fixP
->fx_r_type
!= BFD_RELOC_MIPS_GPREL
)
10223 /* In this case, the bfd_install_relocation routine will
10224 incorrectly add the symbol value back in. We just want
10225 the addend to appear in the object file. */
10228 /* Make sure the addend is still non-zero. If it became zero
10229 after the last operation, set it to a spurious value and
10230 subtract the same value from the object file's contents. */
10235 /* The in-place addends for LO16 relocations are signed;
10236 leave the matching HI16 in-place addends as zero. */
10237 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10239 reloc_howto_type
*howto
;
10240 bfd_vma contents
, mask
, field
;
10242 howto
= bfd_reloc_type_lookup (stdoutput
,
10245 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10248 target_big_endian
);
10250 /* MASK has bits set where the relocation should go.
10251 FIELD is -value, shifted into the appropriate place
10252 for this relocation. */
10253 mask
= 1 << (howto
->bitsize
- 1);
10254 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10255 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10257 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10258 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10260 target_big_endian
);
10266 /* This code was generated using trial and error and so is
10267 fragile and not trustworthy. If you change it, you should
10268 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10269 they still pass. */
10270 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10272 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10274 /* BFD's REL handling, for MIPS, is _very_ weird.
10275 This gives the right results, but it can't possibly
10276 be the way things are supposed to work. */
10277 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10278 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10279 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10280 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10285 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10287 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10290 switch (fixP
->fx_r_type
)
10292 case BFD_RELOC_MIPS_JMP
:
10293 case BFD_RELOC_MIPS_SHIFT5
:
10294 case BFD_RELOC_MIPS_SHIFT6
:
10295 case BFD_RELOC_MIPS_GOT_DISP
:
10296 case BFD_RELOC_MIPS_GOT_PAGE
:
10297 case BFD_RELOC_MIPS_GOT_OFST
:
10298 case BFD_RELOC_MIPS_SUB
:
10299 case BFD_RELOC_MIPS_INSERT_A
:
10300 case BFD_RELOC_MIPS_INSERT_B
:
10301 case BFD_RELOC_MIPS_DELETE
:
10302 case BFD_RELOC_MIPS_HIGHEST
:
10303 case BFD_RELOC_MIPS_HIGHER
:
10304 case BFD_RELOC_MIPS_SCN_DISP
:
10305 case BFD_RELOC_MIPS_REL16
:
10306 case BFD_RELOC_MIPS_RELGOT
:
10307 case BFD_RELOC_MIPS_JALR
:
10308 case BFD_RELOC_HI16
:
10309 case BFD_RELOC_HI16_S
:
10310 case BFD_RELOC_MIPS_GPREL
:
10311 case BFD_RELOC_MIPS_LITERAL
:
10312 case BFD_RELOC_MIPS_CALL16
:
10313 case BFD_RELOC_MIPS_GOT16
:
10314 case BFD_RELOC_MIPS_GPREL32
:
10315 case BFD_RELOC_MIPS_GOT_HI16
:
10316 case BFD_RELOC_MIPS_GOT_LO16
:
10317 case BFD_RELOC_MIPS_CALL_HI16
:
10318 case BFD_RELOC_MIPS_CALL_LO16
:
10319 case BFD_RELOC_MIPS16_GPREL
:
10320 if (fixP
->fx_pcrel
)
10321 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10322 _("Invalid PC relative reloc"));
10323 /* Nothing needed to do. The value comes from the reloc entry */
10326 case BFD_RELOC_MIPS16_JMP
:
10327 /* We currently always generate a reloc against a symbol, which
10328 means that we don't want an addend even if the symbol is
10330 fixP
->fx_addnumber
= 0;
10333 case BFD_RELOC_PCREL_HI16_S
:
10334 /* The addend for this is tricky if it is internal, so we just
10335 do everything here rather than in bfd_install_relocation. */
10336 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10341 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10343 /* For an external symbol adjust by the address to make it
10344 pcrel_offset. We use the address of the RELLO reloc
10345 which follows this one. */
10346 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10347 + fixP
->fx_next
->fx_where
);
10349 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10350 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10351 if (target_big_endian
)
10353 md_number_to_chars (buf
, value
, 2);
10356 case BFD_RELOC_PCREL_LO16
:
10357 /* The addend for this is tricky if it is internal, so we just
10358 do everything here rather than in bfd_install_relocation. */
10359 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10364 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10365 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10366 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10367 if (target_big_endian
)
10369 md_number_to_chars (buf
, value
, 2);
10373 /* This is handled like BFD_RELOC_32, but we output a sign
10374 extended value if we are only 32 bits. */
10376 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10378 if (8 <= sizeof (valueT
))
10379 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10386 w1
= w2
= fixP
->fx_where
;
10387 if (target_big_endian
)
10391 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10392 if ((value
& 0x80000000) != 0)
10396 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10401 case BFD_RELOC_RVA
:
10403 /* If we are deleting this reloc entry, we must fill in the
10404 value now. This can happen if we have a .word which is not
10405 resolved when it appears but is later defined. We also need
10406 to fill in the value if this is an embedded PIC switch table
10409 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10410 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10415 /* If we are deleting this reloc entry, we must fill in the
10417 assert (fixP
->fx_size
== 2);
10419 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10423 case BFD_RELOC_LO16
:
10424 /* When handling an embedded PIC switch statement, we can wind
10425 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10428 if (value
+ 0x8000 > 0xffff)
10429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10430 _("relocation overflow"));
10431 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10432 if (target_big_endian
)
10434 md_number_to_chars (buf
, value
, 2);
10438 case BFD_RELOC_16_PCREL_S2
:
10439 if ((value
& 0x3) != 0)
10440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10441 _("Branch to odd address (%lx)"), (long) value
);
10443 /* Fall through. */
10445 case BFD_RELOC_16_PCREL
:
10447 * We need to save the bits in the instruction since fixup_segment()
10448 * might be deleting the relocation entry (i.e., a branch within
10449 * the current segment).
10451 if (!fixP
->fx_done
&& value
!= 0)
10453 /* If 'value' is zero, the remaining reloc code won't actually
10454 do the store, so it must be done here. This is probably
10455 a bug somewhere. */
10456 if (!fixP
->fx_done
)
10457 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10459 value
= (offsetT
) value
>> 2;
10461 /* update old instruction data */
10462 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10463 if (target_big_endian
)
10464 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10466 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10468 if (value
+ 0x8000 <= 0xffff)
10469 insn
|= value
& 0xffff;
10472 /* The branch offset is too large. If this is an
10473 unconditional branch, and we are not generating PIC code,
10474 we can convert it to an absolute jump instruction. */
10475 if (mips_pic
== NO_PIC
10477 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10478 && (fixP
->fx_frag
->fr_address
10479 < text_section
->vma
+ text_section
->_raw_size
)
10480 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10481 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10482 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10484 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10485 insn
= 0x0c000000; /* jal */
10487 insn
= 0x08000000; /* j */
10488 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10490 fixP
->fx_addsy
= section_symbol (text_section
);
10491 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10495 /* FIXME. It would be possible in principle to handle
10496 conditional branches which overflow. They could be
10497 transformed into a branch around a jump. This would
10498 require setting up variant frags for each different
10499 branch type. The native MIPS assembler attempts to
10500 handle these cases, but it appears to do it
10502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10503 _("Branch out of range"));
10507 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10510 case BFD_RELOC_VTABLE_INHERIT
:
10513 && !S_IS_DEFINED (fixP
->fx_addsy
)
10514 && !S_IS_WEAK (fixP
->fx_addsy
))
10515 S_SET_WEAK (fixP
->fx_addsy
);
10518 case BFD_RELOC_VTABLE_ENTRY
:
10534 const struct mips_opcode
*p
;
10535 int treg
, sreg
, dreg
, shamt
;
10540 for (i
= 0; i
< NUMOPCODES
; ++i
)
10542 p
= &mips_opcodes
[i
];
10543 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10545 printf ("%08lx %s\t", oc
, p
->name
);
10546 treg
= (oc
>> 16) & 0x1f;
10547 sreg
= (oc
>> 21) & 0x1f;
10548 dreg
= (oc
>> 11) & 0x1f;
10549 shamt
= (oc
>> 6) & 0x1f;
10551 for (args
= p
->args
;; ++args
)
10562 printf ("%c", *args
);
10566 assert (treg
== sreg
);
10567 printf ("$%d,$%d", treg
, sreg
);
10572 printf ("$%d", dreg
);
10577 printf ("$%d", treg
);
10581 printf ("0x%x", treg
);
10586 printf ("$%d", sreg
);
10590 printf ("0x%08lx", oc
& 0x1ffffff);
10597 printf ("%d", imm
);
10602 printf ("$%d", shamt
);
10613 printf (_("%08lx UNDEFINED\n"), oc
);
10624 name
= input_line_pointer
;
10625 c
= get_symbol_end ();
10626 p
= (symbolS
*) symbol_find_or_make (name
);
10627 *input_line_pointer
= c
;
10631 /* Align the current frag to a given power of two. The MIPS assembler
10632 also automatically adjusts any preceding label. */
10635 mips_align (to
, fill
, label
)
10640 mips_emit_delays (false);
10641 frag_align (to
, fill
, 0);
10642 record_alignment (now_seg
, to
);
10645 assert (S_GET_SEGMENT (label
) == now_seg
);
10646 symbol_set_frag (label
, frag_now
);
10647 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10651 /* Align to a given power of two. .align 0 turns off the automatic
10652 alignment used by the data creating pseudo-ops. */
10656 int x ATTRIBUTE_UNUSED
;
10659 register long temp_fill
;
10660 long max_alignment
= 15;
10664 o Note that the assembler pulls down any immediately preceeding label
10665 to the aligned address.
10666 o It's not documented but auto alignment is reinstated by
10667 a .align pseudo instruction.
10668 o Note also that after auto alignment is turned off the mips assembler
10669 issues an error on attempt to assemble an improperly aligned data item.
10674 temp
= get_absolute_expression ();
10675 if (temp
> max_alignment
)
10676 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10679 as_warn (_("Alignment negative: 0 assumed."));
10682 if (*input_line_pointer
== ',')
10684 input_line_pointer
++;
10685 temp_fill
= get_absolute_expression ();
10692 mips_align (temp
, (int) temp_fill
,
10693 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10700 demand_empty_rest_of_line ();
10704 mips_flush_pending_output ()
10706 mips_emit_delays (false);
10707 mips_clear_insn_labels ();
10716 /* When generating embedded PIC code, we only use the .text, .lit8,
10717 .sdata and .sbss sections. We change the .data and .rdata
10718 pseudo-ops to use .sdata. */
10719 if (mips_pic
== EMBEDDED_PIC
10720 && (sec
== 'd' || sec
== 'r'))
10724 /* The ELF backend needs to know that we are changing sections, so
10725 that .previous works correctly. We could do something like check
10726 for an obj_section_change_hook macro, but that might be confusing
10727 as it would not be appropriate to use it in the section changing
10728 functions in read.c, since obj-elf.c intercepts those. FIXME:
10729 This should be cleaner, somehow. */
10730 obj_elf_section_change_hook ();
10733 mips_emit_delays (false);
10743 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10744 demand_empty_rest_of_line ();
10748 if (USE_GLOBAL_POINTER_OPT
)
10750 seg
= subseg_new (RDATA_SECTION_NAME
,
10751 (subsegT
) get_absolute_expression ());
10752 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10754 bfd_set_section_flags (stdoutput
, seg
,
10760 if (strcmp (TARGET_OS
, "elf") != 0)
10761 record_alignment (seg
, 4);
10763 demand_empty_rest_of_line ();
10767 as_bad (_("No read only data section in this object file format"));
10768 demand_empty_rest_of_line ();
10774 if (USE_GLOBAL_POINTER_OPT
)
10776 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10777 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10779 bfd_set_section_flags (stdoutput
, seg
,
10780 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10782 if (strcmp (TARGET_OS
, "elf") != 0)
10783 record_alignment (seg
, 4);
10785 demand_empty_rest_of_line ();
10790 as_bad (_("Global pointers not supported; recompile -G 0"));
10791 demand_empty_rest_of_line ();
10800 mips_enable_auto_align ()
10811 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10812 mips_emit_delays (false);
10813 if (log_size
> 0 && auto_align
)
10814 mips_align (log_size
, 0, label
);
10815 mips_clear_insn_labels ();
10816 cons (1 << log_size
);
10820 s_float_cons (type
)
10825 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10827 mips_emit_delays (false);
10832 mips_align (3, 0, label
);
10834 mips_align (2, 0, label
);
10837 mips_clear_insn_labels ();
10842 /* Handle .globl. We need to override it because on Irix 5 you are
10845 where foo is an undefined symbol, to mean that foo should be
10846 considered to be the address of a function. */
10850 int x ATTRIBUTE_UNUSED
;
10857 name
= input_line_pointer
;
10858 c
= get_symbol_end ();
10859 symbolP
= symbol_find_or_make (name
);
10860 *input_line_pointer
= c
;
10861 SKIP_WHITESPACE ();
10863 /* On Irix 5, every global symbol that is not explicitly labelled as
10864 being a function is apparently labelled as being an object. */
10867 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10872 secname
= input_line_pointer
;
10873 c
= get_symbol_end ();
10874 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10876 as_bad (_("%s: no such section"), secname
);
10877 *input_line_pointer
= c
;
10879 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10880 flag
= BSF_FUNCTION
;
10883 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10885 S_SET_EXTERNAL (symbolP
);
10886 demand_empty_rest_of_line ();
10891 int x ATTRIBUTE_UNUSED
;
10896 opt
= input_line_pointer
;
10897 c
= get_symbol_end ();
10901 /* FIXME: What does this mean? */
10903 else if (strncmp (opt
, "pic", 3) == 0)
10907 i
= atoi (opt
+ 3);
10911 mips_pic
= SVR4_PIC
;
10913 as_bad (_(".option pic%d not supported"), i
);
10915 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10917 if (g_switch_seen
&& g_switch_value
!= 0)
10918 as_warn (_("-G may not be used with SVR4 PIC code"));
10919 g_switch_value
= 0;
10920 bfd_set_gp_size (stdoutput
, 0);
10924 as_warn (_("Unrecognized option \"%s\""), opt
);
10926 *input_line_pointer
= c
;
10927 demand_empty_rest_of_line ();
10930 /* This structure is used to hold a stack of .set values. */
10932 struct mips_option_stack
10934 struct mips_option_stack
*next
;
10935 struct mips_set_options options
;
10938 static struct mips_option_stack
*mips_opts_stack
;
10940 /* Handle the .set pseudo-op. */
10944 int x ATTRIBUTE_UNUSED
;
10946 char *name
= input_line_pointer
, ch
;
10948 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10949 input_line_pointer
++;
10950 ch
= *input_line_pointer
;
10951 *input_line_pointer
= '\0';
10953 if (strcmp (name
, "reorder") == 0)
10955 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10957 /* If we still have pending nops, we can discard them. The
10958 usual nop handling will insert any that are still
10960 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10961 * (mips_opts
.mips16
? 2 : 4));
10962 prev_nop_frag
= NULL
;
10964 mips_opts
.noreorder
= 0;
10966 else if (strcmp (name
, "noreorder") == 0)
10968 mips_emit_delays (true);
10969 mips_opts
.noreorder
= 1;
10970 mips_any_noreorder
= 1;
10972 else if (strcmp (name
, "at") == 0)
10974 mips_opts
.noat
= 0;
10976 else if (strcmp (name
, "noat") == 0)
10978 mips_opts
.noat
= 1;
10980 else if (strcmp (name
, "macro") == 0)
10982 mips_opts
.warn_about_macros
= 0;
10984 else if (strcmp (name
, "nomacro") == 0)
10986 if (mips_opts
.noreorder
== 0)
10987 as_bad (_("`noreorder' must be set before `nomacro'"));
10988 mips_opts
.warn_about_macros
= 1;
10990 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10992 mips_opts
.nomove
= 0;
10994 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10996 mips_opts
.nomove
= 1;
10998 else if (strcmp (name
, "bopt") == 0)
11000 mips_opts
.nobopt
= 0;
11002 else if (strcmp (name
, "nobopt") == 0)
11004 mips_opts
.nobopt
= 1;
11006 else if (strcmp (name
, "mips16") == 0
11007 || strcmp (name
, "MIPS-16") == 0)
11008 mips_opts
.mips16
= 1;
11009 else if (strcmp (name
, "nomips16") == 0
11010 || strcmp (name
, "noMIPS-16") == 0)
11011 mips_opts
.mips16
= 0;
11012 else if (strncmp (name
, "mips", 4) == 0)
11015 static int saved_mips_gp32
;
11016 static int saved_mips_fp32
;
11017 static enum mips_abi_level saved_mips_abi
;
11018 static int is_saved
;
11020 /* Permit the user to change the ISA on the fly. Needless to
11021 say, misuse can cause serious problems. */
11022 isa
= atoi (name
+ 4);
11026 mips_gp32
= saved_mips_gp32
;
11027 mips_fp32
= saved_mips_fp32
;
11028 mips_abi
= saved_mips_abi
;
11036 saved_mips_gp32
= mips_gp32
;
11037 saved_mips_fp32
= mips_fp32
;
11038 saved_mips_abi
= mips_abi
;
11050 saved_mips_gp32
= mips_gp32
;
11051 saved_mips_fp32
= mips_fp32
;
11052 saved_mips_abi
= mips_abi
;
11060 as_bad (_("unknown ISA level"));
11066 case 0: mips_opts
.isa
= file_mips_isa
; break;
11067 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11068 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11069 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11070 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11071 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11072 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11073 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11074 default: as_bad (_("unknown ISA level")); break;
11077 else if (strcmp (name
, "autoextend") == 0)
11078 mips_opts
.noautoextend
= 0;
11079 else if (strcmp (name
, "noautoextend") == 0)
11080 mips_opts
.noautoextend
= 1;
11081 else if (strcmp (name
, "push") == 0)
11083 struct mips_option_stack
*s
;
11085 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11086 s
->next
= mips_opts_stack
;
11087 s
->options
= mips_opts
;
11088 mips_opts_stack
= s
;
11090 else if (strcmp (name
, "pop") == 0)
11092 struct mips_option_stack
*s
;
11094 s
= mips_opts_stack
;
11096 as_bad (_(".set pop with no .set push"));
11099 /* If we're changing the reorder mode we need to handle
11100 delay slots correctly. */
11101 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11102 mips_emit_delays (true);
11103 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11105 if (prev_nop_frag
!= NULL
)
11107 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11108 * (mips_opts
.mips16
? 2 : 4));
11109 prev_nop_frag
= NULL
;
11113 mips_opts
= s
->options
;
11114 mips_opts_stack
= s
->next
;
11120 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11122 *input_line_pointer
= ch
;
11123 demand_empty_rest_of_line ();
11126 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11127 .option pic2. It means to generate SVR4 PIC calls. */
11130 s_abicalls (ignore
)
11131 int ignore ATTRIBUTE_UNUSED
;
11133 mips_pic
= SVR4_PIC
;
11134 if (USE_GLOBAL_POINTER_OPT
)
11136 if (g_switch_seen
&& g_switch_value
!= 0)
11137 as_warn (_("-G may not be used with SVR4 PIC code"));
11138 g_switch_value
= 0;
11140 bfd_set_gp_size (stdoutput
, 0);
11141 demand_empty_rest_of_line ();
11144 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11145 PIC code. It sets the $gp register for the function based on the
11146 function address, which is in the register named in the argument.
11147 This uses a relocation against _gp_disp, which is handled specially
11148 by the linker. The result is:
11149 lui $gp,%hi(_gp_disp)
11150 addiu $gp,$gp,%lo(_gp_disp)
11151 addu $gp,$gp,.cpload argument
11152 The .cpload argument is normally $25 == $t9. */
11156 int ignore ATTRIBUTE_UNUSED
;
11161 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11162 .cpload is ignored. */
11163 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11169 /* .cpload should be in a .set noreorder section. */
11170 if (mips_opts
.noreorder
== 0)
11171 as_warn (_(".cpload not in noreorder section"));
11173 ex
.X_op
= O_symbol
;
11174 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11175 ex
.X_op_symbol
= NULL
;
11176 ex
.X_add_number
= 0;
11178 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11179 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11181 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
11182 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
11183 (int) BFD_RELOC_LO16
);
11185 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11186 GP
, GP
, tc_get_register (0));
11188 demand_empty_rest_of_line ();
11191 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11192 .cpsetup $reg1, offset|$reg2, label
11194 If offset is given, this results in:
11195 sd $gp, offset($sp)
11196 lui $gp, %gp_rel(%neg(%hi(label)))
11197 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11198 addu $gp, $gp, $reg1
11200 If $reg2 is given, this results in:
11201 daddu $reg2, $gp, $0
11202 lui $gp, %gp_rel(%neg(%hi(label)))
11203 daddiu $gp, $gp, %gp_rel(%neg(%lo(label)))
11204 addu $gp, $gp, $reg1
11208 int ignore ATTRIBUTE_UNUSED
;
11210 expressionS ex_off
;
11211 expressionS ex_sym
;
11216 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11217 We also need NewABI support. */
11218 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11224 reg1
= tc_get_register (0);
11225 SKIP_WHITESPACE ();
11226 if (*input_line_pointer
!= ',')
11228 as_bad (_("missing argument separator ',' for .cpsetup"));
11232 input_line_pointer
++;
11233 SKIP_WHITESPACE ();
11234 if (*input_line_pointer
== '$')
11235 mips_cpreturn_register
= tc_get_register (0);
11237 mips_cpreturn_offset
= get_absolute_expression ();
11238 SKIP_WHITESPACE ();
11239 if (*input_line_pointer
!= ',')
11241 as_bad (_("missing argument separator ',' for .cpsetup"));
11245 input_line_pointer
++;
11246 SKIP_WHITESPACE ();
11247 sym
= input_line_pointer
;
11248 while (ISALNUM (*input_line_pointer
))
11249 input_line_pointer
++;
11250 *input_line_pointer
= 0;
11252 ex_sym
.X_op
= O_symbol
;
11253 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11254 ex_sym
.X_op_symbol
= NULL
;
11255 ex_sym
.X_add_number
= 0;
11257 if (mips_cpreturn_register
== -1)
11259 ex_off
.X_op
= O_constant
;
11260 ex_off
.X_add_symbol
= NULL
;
11261 ex_off
.X_op_symbol
= NULL
;
11262 ex_off
.X_add_number
= mips_cpreturn_offset
;
11264 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11265 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11268 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11269 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11271 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11272 (int) BFD_RELOC_GPREL16
);
11273 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11274 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11275 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11276 NULL
, 0, 0, BFD_RELOC_HI16_S
);
11277 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11278 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11279 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11280 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11281 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11282 NULL
, 0, 0, BFD_RELOC_LO16
);
11283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11284 "d,v,t", mips_gp_register
, mips_gp_register
, reg1
);
11286 demand_empty_rest_of_line ();
11291 int ignore ATTRIBUTE_UNUSED
;
11293 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11294 .cplocal is ignored. */
11295 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11301 mips_gp_register
= tc_get_register (0);
11304 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11305 offset from $sp. The offset is remembered, and after making a PIC
11306 call $gp is restored from that location. */
11309 s_cprestore (ignore
)
11310 int ignore ATTRIBUTE_UNUSED
;
11315 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11316 .cprestore is ignored. */
11317 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11323 mips_cprestore_offset
= get_absolute_expression ();
11325 ex
.X_op
= O_constant
;
11326 ex
.X_add_symbol
= NULL
;
11327 ex
.X_op_symbol
= NULL
;
11328 ex
.X_add_number
= mips_cprestore_offset
;
11330 macro_build ((char *) NULL
, &icnt
, &ex
,
11331 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11332 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11334 demand_empty_rest_of_line ();
11337 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11338 was given in the preceeding .gpsetup, it results in:
11339 ld $gp, offset($sp)
11341 If a register $reg2 was given there, it results in:
11342 daddiu $gp, $gp, $reg2
11345 s_cpreturn (ignore
)
11346 int ignore ATTRIBUTE_UNUSED
;
11351 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11352 We also need NewABI support. */
11353 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11359 if (mips_cpreturn_register
== -1)
11361 ex
.X_op
= O_constant
;
11362 ex
.X_add_symbol
= NULL
;
11363 ex
.X_op_symbol
= NULL
;
11364 ex
.X_add_number
= mips_cpreturn_offset
;
11366 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11367 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11370 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11371 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11373 demand_empty_rest_of_line ();
11376 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11377 code. It sets the offset to use in gp_rel relocations. */
11381 int ignore ATTRIBUTE_UNUSED
;
11383 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11384 We also need NewABI support. */
11385 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11391 mips_cpreturn_offset
= get_absolute_expression ();
11393 demand_empty_rest_of_line ();
11396 /* Handle the .gpword pseudo-op. This is used when generating PIC
11397 code. It generates a 32 bit GP relative reloc. */
11401 int ignore ATTRIBUTE_UNUSED
;
11407 /* When not generating PIC code, this is treated as .word. */
11408 if (mips_pic
!= SVR4_PIC
)
11414 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11415 mips_emit_delays (true);
11417 mips_align (2, 0, label
);
11418 mips_clear_insn_labels ();
11422 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11424 as_bad (_("Unsupported use of .gpword"));
11425 ignore_rest_of_line ();
11429 md_number_to_chars (p
, (valueT
) 0, 4);
11430 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11431 BFD_RELOC_MIPS_GPREL32
);
11433 demand_empty_rest_of_line ();
11436 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11437 tables in SVR4 PIC code. */
11441 int ignore ATTRIBUTE_UNUSED
;
11446 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11448 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11454 /* Add $gp to the register named as an argument. */
11455 reg
= tc_get_register (0);
11456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11457 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11458 "d,v,t", reg
, reg
, GP
);
11460 demand_empty_rest_of_line ();
11463 /* Handle the .insn pseudo-op. This marks instruction labels in
11464 mips16 mode. This permits the linker to handle them specially,
11465 such as generating jalx instructions when needed. We also make
11466 them odd for the duration of the assembly, in order to generate the
11467 right sort of code. We will make them even in the adjust_symtab
11468 routine, while leaving them marked. This is convenient for the
11469 debugger and the disassembler. The linker knows to make them odd
11474 int ignore ATTRIBUTE_UNUSED
;
11476 if (mips_opts
.mips16
)
11477 mips16_mark_labels ();
11479 demand_empty_rest_of_line ();
11482 /* Handle a .stabn directive. We need these in order to mark a label
11483 as being a mips16 text label correctly. Sometimes the compiler
11484 will emit a label, followed by a .stabn, and then switch sections.
11485 If the label and .stabn are in mips16 mode, then the label is
11486 really a mips16 text label. */
11492 if (type
== 'n' && mips_opts
.mips16
)
11493 mips16_mark_labels ();
11498 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11502 s_mips_weakext (ignore
)
11503 int ignore ATTRIBUTE_UNUSED
;
11510 name
= input_line_pointer
;
11511 c
= get_symbol_end ();
11512 symbolP
= symbol_find_or_make (name
);
11513 S_SET_WEAK (symbolP
);
11514 *input_line_pointer
= c
;
11516 SKIP_WHITESPACE ();
11518 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11520 if (S_IS_DEFINED (symbolP
))
11522 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11523 S_GET_NAME (symbolP
));
11524 ignore_rest_of_line ();
11528 if (*input_line_pointer
== ',')
11530 ++input_line_pointer
;
11531 SKIP_WHITESPACE ();
11535 if (exp
.X_op
!= O_symbol
)
11537 as_bad ("bad .weakext directive");
11538 ignore_rest_of_line();
11541 symbol_set_value_expression (symbolP
, &exp
);
11544 demand_empty_rest_of_line ();
11547 /* Parse a register string into a number. Called from the ECOFF code
11548 to parse .frame. The argument is non-zero if this is the frame
11549 register, so that we can record it in mips_frame_reg. */
11552 tc_get_register (frame
)
11557 SKIP_WHITESPACE ();
11558 if (*input_line_pointer
++ != '$')
11560 as_warn (_("expected `$'"));
11563 else if (ISDIGIT (*input_line_pointer
))
11565 reg
= get_absolute_expression ();
11566 if (reg
< 0 || reg
>= 32)
11568 as_warn (_("Bad register number"));
11574 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11576 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11578 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11580 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11584 as_warn (_("Unrecognized register name"));
11587 input_line_pointer
+= 2;
11590 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11595 md_section_align (seg
, addr
)
11599 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11602 /* We don't need to align ELF sections to the full alignment.
11603 However, Irix 5 may prefer that we align them at least to a 16
11604 byte boundary. We don't bother to align the sections if we are
11605 targeted for an embedded system. */
11606 if (strcmp (TARGET_OS
, "elf") == 0)
11612 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11615 /* Utility routine, called from above as well. If called while the
11616 input file is still being read, it's only an approximation. (For
11617 example, a symbol may later become defined which appeared to be
11618 undefined earlier.) */
11621 nopic_need_relax (sym
, before_relaxing
)
11623 int before_relaxing
;
11628 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
11630 const char *symname
;
11633 /* Find out whether this symbol can be referenced off the GP
11634 register. It can be if it is smaller than the -G size or if
11635 it is in the .sdata or .sbss section. Certain symbols can
11636 not be referenced off the GP, although it appears as though
11638 symname
= S_GET_NAME (sym
);
11639 if (symname
!= (const char *) NULL
11640 && (strcmp (symname
, "eprol") == 0
11641 || strcmp (symname
, "etext") == 0
11642 || strcmp (symname
, "_gp") == 0
11643 || strcmp (symname
, "edata") == 0
11644 || strcmp (symname
, "_fbss") == 0
11645 || strcmp (symname
, "_fdata") == 0
11646 || strcmp (symname
, "_ftext") == 0
11647 || strcmp (symname
, "end") == 0
11648 || strcmp (symname
, "_gp_disp") == 0))
11650 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11652 #ifndef NO_ECOFF_DEBUGGING
11653 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11654 && (symbol_get_obj (sym
)->ecoff_extern_size
11655 <= g_switch_value
))
11657 /* We must defer this decision until after the whole
11658 file has been read, since there might be a .extern
11659 after the first use of this symbol. */
11660 || (before_relaxing
11661 #ifndef NO_ECOFF_DEBUGGING
11662 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11664 && S_GET_VALUE (sym
) == 0)
11665 || (S_GET_VALUE (sym
) != 0
11666 && S_GET_VALUE (sym
) <= g_switch_value
)))
11670 const char *segname
;
11672 segname
= segment_name (S_GET_SEGMENT (sym
));
11673 assert (strcmp (segname
, ".lit8") != 0
11674 && strcmp (segname
, ".lit4") != 0);
11675 change
= (strcmp (segname
, ".sdata") != 0
11676 && strcmp (segname
, ".sbss") != 0
11677 && strncmp (segname
, ".sdata.", 7) != 0
11678 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11683 /* We are not optimizing for the GP register. */
11687 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11688 extended opcode. SEC is the section the frag is in. */
11691 mips16_extended_frag (fragp
, sec
, stretch
)
11697 register const struct mips16_immed_operand
*op
;
11699 int mintiny
, maxtiny
;
11703 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11705 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11708 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11709 op
= mips16_immed_operands
;
11710 while (op
->type
!= type
)
11713 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11718 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11721 maxtiny
= 1 << op
->nbits
;
11726 maxtiny
= (1 << op
->nbits
) - 1;
11731 mintiny
= - (1 << (op
->nbits
- 1));
11732 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11735 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
11736 val
= S_GET_VALUE (fragp
->fr_symbol
);
11737 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11743 /* We won't have the section when we are called from
11744 mips_relax_frag. However, we will always have been called
11745 from md_estimate_size_before_relax first. If this is a
11746 branch to a different section, we mark it as such. If SEC is
11747 NULL, and the frag is not marked, then it must be a branch to
11748 the same section. */
11751 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11756 /* Must have been called from md_estimate_size_before_relax. */
11759 fragp
->fr_subtype
=
11760 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11762 /* FIXME: We should support this, and let the linker
11763 catch branches and loads that are out of range. */
11764 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11765 _("unsupported PC relative reference to different section"));
11769 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
11770 /* Assume non-extended on the first relaxation pass.
11771 The address we have calculated will be bogus if this is
11772 a forward branch to another frag, as the forward frag
11773 will have fr_address == 0. */
11777 /* In this case, we know for sure that the symbol fragment is in
11778 the same section. If the relax_marker of the symbol fragment
11779 differs from the relax_marker of this fragment, we have not
11780 yet adjusted the symbol fragment fr_address. We want to add
11781 in STRETCH in order to get a better estimate of the address.
11782 This particularly matters because of the shift bits. */
11784 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11788 /* Adjust stretch for any alignment frag. Note that if have
11789 been expanding the earlier code, the symbol may be
11790 defined in what appears to be an earlier frag. FIXME:
11791 This doesn't handle the fr_subtype field, which specifies
11792 a maximum number of bytes to skip when doing an
11794 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11796 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11799 stretch
= - ((- stretch
)
11800 & ~ ((1 << (int) f
->fr_offset
) - 1));
11802 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11811 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11813 /* The base address rules are complicated. The base address of
11814 a branch is the following instruction. The base address of a
11815 PC relative load or add is the instruction itself, but if it
11816 is in a delay slot (in which case it can not be extended) use
11817 the address of the instruction whose delay slot it is in. */
11818 if (type
== 'p' || type
== 'q')
11822 /* If we are currently assuming that this frag should be
11823 extended, then, the current address is two bytes
11825 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11828 /* Ignore the low bit in the target, since it will be set
11829 for a text label. */
11830 if ((val
& 1) != 0)
11833 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11835 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11838 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11840 /* Branch offsets have an implicit 0 in the lowest bit. */
11841 if (type
== 'p' || type
== 'q')
11844 /* If any of the shifted bits are set, we must use an extended
11845 opcode. If the address depends on the size of this
11846 instruction, this can lead to a loop, so we arrange to always
11847 use an extended opcode. We only check this when we are in
11848 the main relaxation loop, when SEC is NULL. */
11849 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11851 fragp
->fr_subtype
=
11852 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11856 /* If we are about to mark a frag as extended because the value
11857 is precisely maxtiny + 1, then there is a chance of an
11858 infinite loop as in the following code:
11863 In this case when the la is extended, foo is 0x3fc bytes
11864 away, so the la can be shrunk, but then foo is 0x400 away, so
11865 the la must be extended. To avoid this loop, we mark the
11866 frag as extended if it was small, and is about to become
11867 extended with a value of maxtiny + 1. */
11868 if (val
== ((maxtiny
+ 1) << op
->shift
)
11869 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11872 fragp
->fr_subtype
=
11873 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11877 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11878 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11880 if ((val
& ((1 << op
->shift
) - 1)) != 0
11881 || val
< (mintiny
<< op
->shift
)
11882 || val
> (maxtiny
<< op
->shift
))
11888 /* Estimate the size of a frag before relaxing. Unless this is the
11889 mips16, we are not really relaxing here, and the final size is
11890 encoded in the subtype information. For the mips16, we have to
11891 decide whether we are using an extended opcode or not. */
11894 md_estimate_size_before_relax (fragp
, segtype
)
11899 boolean linkonce
= false;
11901 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11903 if (mips16_extended_frag (fragp
, segtype
, 0))
11905 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11910 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11915 if (mips_pic
== NO_PIC
)
11917 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11919 else if (mips_pic
== SVR4_PIC
)
11924 sym
= fragp
->fr_symbol
;
11926 /* Handle the case of a symbol equated to another symbol. */
11927 while (symbol_equated_reloc_p (sym
))
11931 /* It's possible to get a loop here in a badly written
11933 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11939 symsec
= S_GET_SEGMENT (sym
);
11941 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11942 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
11944 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
11948 /* The GNU toolchain uses an extension for ELF: a section
11949 beginning with the magic string .gnu.linkonce is a linkonce
11951 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
11952 sizeof ".gnu.linkonce" - 1) == 0)
11956 /* This must duplicate the test in adjust_reloc_syms. */
11957 change
= (symsec
!= &bfd_und_section
11958 && symsec
!= &bfd_abs_section
11959 && ! bfd_is_com_section (symsec
)
11962 /* A global or weak symbol is treated as external. */
11963 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11964 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
11973 /* Record the offset to the first reloc in the fr_opcode field.
11974 This lets md_convert_frag and tc_gen_reloc know that the code
11975 must be expanded. */
11976 fragp
->fr_opcode
= (fragp
->fr_literal
11978 - RELAX_OLD (fragp
->fr_subtype
)
11979 + RELAX_RELOC1 (fragp
->fr_subtype
));
11980 /* FIXME: This really needs as_warn_where. */
11981 if (RELAX_WARN (fragp
->fr_subtype
))
11982 as_warn (_("AT used after \".set noat\" or macro used after "
11983 "\".set nomacro\""));
11985 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11991 /* This is called to see whether a reloc against a defined symbol
11992 should be converted into a reloc against a section. Don't adjust
11993 MIPS16 jump relocations, so we don't have to worry about the format
11994 of the offset in the .o file. Don't adjust relocations against
11995 mips16 symbols, so that the linker can find them if it needs to set
11999 mips_fix_adjustable (fixp
)
12003 /* Prevent all adjustments to global symbols. */
12004 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12005 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12008 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12010 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12011 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12013 if (fixp
->fx_addsy
== NULL
)
12016 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12017 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12018 && fixp
->fx_subsy
== NULL
)
12024 /* Translate internal representation of relocation info to BFD target
12028 tc_gen_reloc (section
, fixp
)
12029 asection
*section ATTRIBUTE_UNUSED
;
12032 static arelent
*retval
[4];
12034 bfd_reloc_code_real_type code
;
12036 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12039 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12040 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12041 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12043 if (mips_pic
== EMBEDDED_PIC
12044 && SWITCH_TABLE (fixp
))
12046 /* For a switch table entry we use a special reloc. The addend
12047 is actually the difference between the reloc address and the
12049 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12050 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12051 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12052 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12054 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12055 reloc
->addend
= fixp
->fx_addnumber
;
12056 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12058 /* We use a special addend for an internal RELLO reloc. */
12059 if (symbol_section_p (fixp
->fx_addsy
))
12060 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12062 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12064 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12066 assert (fixp
->fx_next
!= NULL
12067 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12068 /* We use a special addend for an internal RELHI reloc. The
12069 reloc is relative to the RELLO; adjust the addend
12071 if (symbol_section_p (fixp
->fx_addsy
))
12072 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12073 + fixp
->fx_next
->fx_where
12074 - S_GET_VALUE (fixp
->fx_subsy
));
12076 reloc
->addend
= (fixp
->fx_addnumber
12077 + fixp
->fx_next
->fx_frag
->fr_address
12078 + fixp
->fx_next
->fx_where
);
12082 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12083 /* A gruesome hack which is a result of the gruesome gas reloc
12085 reloc
->addend
= reloc
->address
;
12087 reloc
->addend
= -reloc
->address
;
12090 /* If this is a variant frag, we may need to adjust the existing
12091 reloc and generate a new one. */
12092 if (fixp
->fx_frag
->fr_opcode
!= NULL
12093 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
12094 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12095 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12096 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12097 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12098 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12099 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12104 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12106 /* If this is not the last reloc in this frag, then we have two
12107 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12108 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12109 the second one handle all of them. */
12110 if (fixp
->fx_next
!= NULL
12111 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12113 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
12114 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
12115 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12116 && (fixp
->fx_next
->fx_r_type
12117 == BFD_RELOC_MIPS_GOT_LO16
))
12118 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12119 && (fixp
->fx_next
->fx_r_type
12120 == BFD_RELOC_MIPS_CALL_LO16
)));
12125 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12126 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12127 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12129 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12130 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12131 reloc2
->address
= (reloc
->address
12132 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12133 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12134 reloc2
->addend
= fixp
->fx_addnumber
;
12135 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12136 assert (reloc2
->howto
!= NULL
);
12138 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12142 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12145 reloc3
->address
+= 4;
12148 if (mips_pic
== NO_PIC
)
12150 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
12151 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12153 else if (mips_pic
== SVR4_PIC
)
12155 switch (fixp
->fx_r_type
)
12159 case BFD_RELOC_MIPS_GOT16
:
12161 case BFD_RELOC_MIPS_CALL16
:
12162 case BFD_RELOC_MIPS_GOT_LO16
:
12163 case BFD_RELOC_MIPS_CALL_LO16
:
12164 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12172 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12173 to be used in the relocation's section offset. */
12174 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12176 reloc
->address
= reloc
->addend
;
12180 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12181 fixup_segment converted a non-PC relative reloc into a PC
12182 relative reloc. In such a case, we need to convert the reloc
12184 code
= fixp
->fx_r_type
;
12185 if (fixp
->fx_pcrel
)
12190 code
= BFD_RELOC_8_PCREL
;
12193 code
= BFD_RELOC_16_PCREL
;
12196 code
= BFD_RELOC_32_PCREL
;
12199 code
= BFD_RELOC_64_PCREL
;
12201 case BFD_RELOC_8_PCREL
:
12202 case BFD_RELOC_16_PCREL
:
12203 case BFD_RELOC_32_PCREL
:
12204 case BFD_RELOC_64_PCREL
:
12205 case BFD_RELOC_16_PCREL_S2
:
12206 case BFD_RELOC_PCREL_HI16_S
:
12207 case BFD_RELOC_PCREL_LO16
:
12210 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12211 _("Cannot make %s relocation PC relative"),
12212 bfd_get_reloc_code_name (code
));
12216 /* To support a PC relative reloc when generating embedded PIC code
12217 for ECOFF, we use a Cygnus extension. We check for that here to
12218 make sure that we don't let such a reloc escape normally. */
12219 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12220 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12221 && code
== BFD_RELOC_16_PCREL_S2
12222 && mips_pic
!= EMBEDDED_PIC
)
12223 reloc
->howto
= NULL
;
12225 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12227 if (reloc
->howto
== NULL
)
12229 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12230 _("Can not represent %s relocation in this object file format"),
12231 bfd_get_reloc_code_name (code
));
12238 /* Relax a machine dependent frag. This returns the amount by which
12239 the current size of the frag should change. */
12242 mips_relax_frag (fragp
, stretch
)
12246 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12249 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
12251 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12253 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12258 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12260 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12267 /* Convert a machine dependent frag. */
12270 md_convert_frag (abfd
, asec
, fragp
)
12271 bfd
*abfd ATTRIBUTE_UNUSED
;
12278 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12281 register const struct mips16_immed_operand
*op
;
12282 boolean small
, ext
;
12285 unsigned long insn
;
12286 boolean use_extend
;
12287 unsigned short extend
;
12289 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12290 op
= mips16_immed_operands
;
12291 while (op
->type
!= type
)
12294 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12305 resolve_symbol_value (fragp
->fr_symbol
);
12306 val
= S_GET_VALUE (fragp
->fr_symbol
);
12311 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12313 /* The rules for the base address of a PC relative reloc are
12314 complicated; see mips16_extended_frag. */
12315 if (type
== 'p' || type
== 'q')
12320 /* Ignore the low bit in the target, since it will be
12321 set for a text label. */
12322 if ((val
& 1) != 0)
12325 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12327 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12330 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12333 /* Make sure the section winds up with the alignment we have
12336 record_alignment (asec
, op
->shift
);
12340 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12341 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12342 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12343 _("extended instruction in delay slot"));
12345 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12347 if (target_big_endian
)
12348 insn
= bfd_getb16 (buf
);
12350 insn
= bfd_getl16 (buf
);
12352 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12353 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12354 small
, ext
, &insn
, &use_extend
, &extend
);
12358 md_number_to_chars (buf
, 0xf000 | extend
, 2);
12359 fragp
->fr_fix
+= 2;
12363 md_number_to_chars (buf
, insn
, 2);
12364 fragp
->fr_fix
+= 2;
12369 if (fragp
->fr_opcode
== NULL
)
12372 old
= RELAX_OLD (fragp
->fr_subtype
);
12373 new = RELAX_NEW (fragp
->fr_subtype
);
12374 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12377 memcpy (fixptr
- old
, fixptr
, new);
12379 fragp
->fr_fix
+= new - old
;
12385 /* This function is called after the relocs have been generated.
12386 We've been storing mips16 text labels as odd. Here we convert them
12387 back to even for the convenience of the debugger. */
12390 mips_frob_file_after_relocs ()
12393 unsigned int count
, i
;
12395 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12398 syms
= bfd_get_outsymbols (stdoutput
);
12399 count
= bfd_get_symcount (stdoutput
);
12400 for (i
= 0; i
< count
; i
++, syms
++)
12402 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12403 && ((*syms
)->value
& 1) != 0)
12405 (*syms
)->value
&= ~1;
12406 /* If the symbol has an odd size, it was probably computed
12407 incorrectly, so adjust that as well. */
12408 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12409 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12416 /* This function is called whenever a label is defined. It is used
12417 when handling branch delays; if a branch has a label, we assume we
12418 can not move it. */
12421 mips_define_label (sym
)
12424 struct insn_label_list
*l
;
12426 if (free_insn_labels
== NULL
)
12427 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12430 l
= free_insn_labels
;
12431 free_insn_labels
= l
->next
;
12435 l
->next
= insn_labels
;
12439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12441 /* Some special processing for a MIPS ELF file. */
12444 mips_elf_final_processing ()
12446 /* Write out the register information. */
12451 s
.ri_gprmask
= mips_gprmask
;
12452 s
.ri_cprmask
[0] = mips_cprmask
[0];
12453 s
.ri_cprmask
[1] = mips_cprmask
[1];
12454 s
.ri_cprmask
[2] = mips_cprmask
[2];
12455 s
.ri_cprmask
[3] = mips_cprmask
[3];
12456 /* The gp_value field is set by the MIPS ELF backend. */
12458 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12459 ((Elf32_External_RegInfo
*)
12460 mips_regmask_frag
));
12464 Elf64_Internal_RegInfo s
;
12466 s
.ri_gprmask
= mips_gprmask
;
12468 s
.ri_cprmask
[0] = mips_cprmask
[0];
12469 s
.ri_cprmask
[1] = mips_cprmask
[1];
12470 s
.ri_cprmask
[2] = mips_cprmask
[2];
12471 s
.ri_cprmask
[3] = mips_cprmask
[3];
12472 /* The gp_value field is set by the MIPS ELF backend. */
12474 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12475 ((Elf64_External_RegInfo
*)
12476 mips_regmask_frag
));
12479 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12480 sort of BFD interface for this. */
12481 if (mips_any_noreorder
)
12482 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12483 if (mips_pic
!= NO_PIC
)
12484 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12486 /* Set the MIPS ELF ABI flags. */
12487 if (mips_abi
== NO_ABI
)
12489 else if (mips_abi
== O32_ABI
)
12490 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12491 else if (mips_abi
== O64_ABI
)
12492 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12493 else if (mips_abi
== EABI_ABI
)
12496 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12498 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12500 else if (mips_abi
== N32_ABI
)
12501 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12503 /* Nothing to do for "64". */
12505 if (mips_32bitmode
)
12506 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12509 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12511 typedef struct proc
{
12513 unsigned long reg_mask
;
12514 unsigned long reg_offset
;
12515 unsigned long fpreg_mask
;
12516 unsigned long fpreg_offset
;
12517 unsigned long frame_offset
;
12518 unsigned long frame_reg
;
12519 unsigned long pc_reg
;
12522 static procS cur_proc
;
12523 static procS
*cur_proc_ptr
;
12524 static int numprocs
;
12526 /* Fill in an rs_align_code fragment. */
12529 mips_handle_align (fragp
)
12532 if (fragp
->fr_type
!= rs_align_code
)
12535 if (mips_opts
.mips16
)
12537 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12538 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12543 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12544 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12549 fragp
->fr_fix
+= 1;
12552 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12556 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12567 /* check for premature end, nesting errors, etc */
12569 as_warn (_("missing .end at end of assembly"));
12578 if (*input_line_pointer
== '-')
12580 ++input_line_pointer
;
12583 if (!ISDIGIT (*input_line_pointer
))
12584 as_bad (_("Expected simple number."));
12585 if (input_line_pointer
[0] == '0')
12587 if (input_line_pointer
[1] == 'x')
12589 input_line_pointer
+= 2;
12590 while (ISXDIGIT (*input_line_pointer
))
12593 val
|= hex_value (*input_line_pointer
++);
12595 return negative
? -val
: val
;
12599 ++input_line_pointer
;
12600 while (ISDIGIT (*input_line_pointer
))
12603 val
|= *input_line_pointer
++ - '0';
12605 return negative
? -val
: val
;
12608 if (!ISDIGIT (*input_line_pointer
))
12610 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12611 *input_line_pointer
, *input_line_pointer
);
12612 as_warn (_("Invalid number"));
12615 while (ISDIGIT (*input_line_pointer
))
12618 val
+= *input_line_pointer
++ - '0';
12620 return negative
? -val
: val
;
12623 /* The .file directive; just like the usual .file directive, but there
12624 is an initial number which is the ECOFF file index. */
12628 int x ATTRIBUTE_UNUSED
;
12632 line
= get_number ();
12636 /* The .end directive. */
12640 int x ATTRIBUTE_UNUSED
;
12645 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12648 demand_empty_rest_of_line ();
12653 #ifdef BFD_ASSEMBLER
12654 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12659 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12666 as_warn (_(".end not in text section"));
12670 as_warn (_(".end directive without a preceding .ent directive."));
12671 demand_empty_rest_of_line ();
12677 assert (S_GET_NAME (p
));
12678 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12679 as_warn (_(".end symbol does not match .ent symbol."));
12682 as_warn (_(".end directive missing or unknown symbol"));
12684 #ifdef MIPS_STABS_ELF
12686 segT saved_seg
= now_seg
;
12687 subsegT saved_subseg
= now_subseg
;
12692 dot
= frag_now_fix ();
12694 #ifdef md_flush_pending_output
12695 md_flush_pending_output ();
12699 subseg_set (pdr_seg
, 0);
12701 /* Write the symbol. */
12702 exp
.X_op
= O_symbol
;
12703 exp
.X_add_symbol
= p
;
12704 exp
.X_add_number
= 0;
12705 emit_expr (&exp
, 4);
12707 fragp
= frag_more (7 * 4);
12709 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12710 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12711 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12712 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12713 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12714 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12715 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12717 subseg_set (saved_seg
, saved_subseg
);
12721 cur_proc_ptr
= NULL
;
12724 /* The .aent and .ent directives. */
12734 symbolP
= get_symbol ();
12735 if (*input_line_pointer
== ',')
12736 input_line_pointer
++;
12737 SKIP_WHITESPACE ();
12738 if (ISDIGIT (*input_line_pointer
)
12739 || *input_line_pointer
== '-')
12740 number
= get_number ();
12742 #ifdef BFD_ASSEMBLER
12743 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12748 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12755 as_warn (_(".ent or .aent not in text section."));
12757 if (!aent
&& cur_proc_ptr
)
12758 as_warn (_("missing .end"));
12762 cur_proc_ptr
= &cur_proc
;
12763 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12765 cur_proc_ptr
->isym
= symbolP
;
12767 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
12772 demand_empty_rest_of_line ();
12775 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12776 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12777 s_mips_frame is used so that we can set the PDR information correctly.
12778 We can't use the ecoff routines because they make reference to the ecoff
12779 symbol table (in the mdebug section). */
12782 s_mips_frame (ignore
)
12783 int ignore ATTRIBUTE_UNUSED
;
12785 #ifdef MIPS_STABS_ELF
12789 if (cur_proc_ptr
== (procS
*) NULL
)
12791 as_warn (_(".frame outside of .ent"));
12792 demand_empty_rest_of_line ();
12796 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12798 SKIP_WHITESPACE ();
12799 if (*input_line_pointer
++ != ','
12800 || get_absolute_expression_and_terminator (&val
) != ',')
12802 as_warn (_("Bad .frame directive"));
12803 --input_line_pointer
;
12804 demand_empty_rest_of_line ();
12808 cur_proc_ptr
->frame_offset
= val
;
12809 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12811 demand_empty_rest_of_line ();
12814 #endif /* MIPS_STABS_ELF */
12817 /* The .fmask and .mask directives. If the mdebug section is present
12818 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12819 embedded targets, s_mips_mask is used so that we can set the PDR
12820 information correctly. We can't use the ecoff routines because they
12821 make reference to the ecoff symbol table (in the mdebug section). */
12824 s_mips_mask (reg_type
)
12827 #ifdef MIPS_STABS_ELF
12830 if (cur_proc_ptr
== (procS
*) NULL
)
12832 as_warn (_(".mask/.fmask outside of .ent"));
12833 demand_empty_rest_of_line ();
12837 if (get_absolute_expression_and_terminator (&mask
) != ',')
12839 as_warn (_("Bad .mask/.fmask directive"));
12840 --input_line_pointer
;
12841 demand_empty_rest_of_line ();
12845 off
= get_absolute_expression ();
12847 if (reg_type
== 'F')
12849 cur_proc_ptr
->fpreg_mask
= mask
;
12850 cur_proc_ptr
->fpreg_offset
= off
;
12854 cur_proc_ptr
->reg_mask
= mask
;
12855 cur_proc_ptr
->reg_offset
= off
;
12858 demand_empty_rest_of_line ();
12860 s_ignore (reg_type
);
12861 #endif /* MIPS_STABS_ELF */
12864 /* The .loc directive. */
12875 assert (now_seg
== text_section
);
12877 lineno
= get_number ();
12878 addroff
= frag_now_fix ();
12880 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12881 S_SET_TYPE (symbolP
, N_SLINE
);
12882 S_SET_OTHER (symbolP
, 0);
12883 S_SET_DESC (symbolP
, lineno
);
12884 symbolP
->sy_segment
= now_seg
;
12888 /* CPU name/ISA/number mapping table.
12890 Entries are grouped by type. The first matching CPU or ISA entry
12891 gets chosen by CPU or ISA, so it should be the 'canonical' name
12892 for that type. Entries after that within the type are sorted
12895 Case is ignored in comparison, so put the canonical entry in the
12896 appropriate case but everything else in lower case to ease eye pain. */
12897 static const struct mips_cpu_info mips_cpu_info_table
[] =
12900 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
12901 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
12904 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
12907 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
12910 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
12913 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
12914 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
12917 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
12918 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12919 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
12920 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
12921 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
12922 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
12924 /* For historical reasons. */
12925 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
12928 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
12929 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
12930 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12931 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
12934 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
12935 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
12936 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
12937 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
12940 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
12941 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
12942 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
12943 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
12946 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
12947 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
12948 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
12951 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
12952 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
12953 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
12954 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
12957 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
12958 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
12961 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
12962 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
12965 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
12966 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
12967 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
12968 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
12971 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
12972 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
12975 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
12976 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
12977 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
12978 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
12981 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
12982 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
12983 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
12984 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
12987 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
12988 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
12989 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12990 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12993 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
12994 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
12995 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
12996 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
12999 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13000 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13001 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13002 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13005 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13006 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13007 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13008 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13011 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13012 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13013 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13014 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13017 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13018 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13019 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13020 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13021 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13022 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13023 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13024 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13025 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13026 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13027 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13028 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13029 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13030 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13031 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13032 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13033 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13035 /* Broadcom SB-1 CPU */
13036 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13037 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13038 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13039 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13042 { NULL
, 0, 0, 0, },
13045 static const struct mips_cpu_info
*
13046 mips_cpu_info_from_name (name
)
13051 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13052 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13053 return (&mips_cpu_info_table
[i
]);
13058 static const struct mips_cpu_info
*
13059 mips_cpu_info_from_isa (isa
)
13064 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13065 if (mips_cpu_info_table
[i
].is_isa
13066 && isa
== mips_cpu_info_table
[i
].isa
)
13067 return (&mips_cpu_info_table
[i
]);
13072 static const struct mips_cpu_info
*
13073 mips_cpu_info_from_cpu (cpu
)
13078 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13079 if (!mips_cpu_info_table
[i
].is_isa
13080 && cpu
== mips_cpu_info_table
[i
].cpu
)
13081 return (&mips_cpu_info_table
[i
]);