1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug
= -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag
;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi
= NO_ABI
;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros
;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32
= -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32
= -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts
=
194 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16
;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d
;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx
;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch
= CPU_UNKNOWN
;
220 static const char *mips_arch_string
;
221 static const struct mips_cpu_info
*mips_arch_info
;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune
= CPU_UNKNOWN
;
226 static const char *mips_tune_string
;
227 static const struct mips_cpu_info
*mips_tune_info
;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode
= 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
289 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
291 /* Return true if the given CPU supports the MIPS3D ASE. */
292 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
295 /* Return true if the given CPU supports the MDMX ASE. */
296 #define CPU_HAS_MDMX(cpu) (FALSE \
299 /* True if CPU has a dror instruction. */
300 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
302 /* True if CPU has a ror instruction. */
303 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
305 /* Whether the processor uses hardware interlocks to protect
306 reads from the HI and LO registers, and thus does not
307 require nops to be inserted. */
309 #define hilo_interlocks (mips_arch == CPU_R4010 \
310 || mips_arch == CPU_VR5500 \
311 || mips_arch == CPU_SB1 \
314 /* Whether the processor uses hardware interlocks to protect reads
315 from the GPRs, and thus does not require nops to be inserted. */
316 #define gpr_interlocks \
317 (mips_opts.isa != ISA_MIPS1 \
318 || mips_arch == CPU_VR5400 \
319 || mips_arch == CPU_VR5500 \
320 || mips_arch == CPU_R3900)
322 /* As with other "interlocks" this is used by hardware that has FP
323 (co-processor) interlocks. */
324 /* Itbl support may require additional care here. */
325 #define cop_interlocks (mips_arch == CPU_R4300 \
326 || mips_arch == CPU_VR5400 \
327 || mips_arch == CPU_VR5500 \
328 || mips_arch == CPU_SB1 \
331 /* Is this a mfhi or mflo instruction? */
332 #define MF_HILO_INSN(PINFO) \
333 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
335 /* MIPS PIC level. */
337 enum mips_pic_level mips_pic
;
339 /* Warn about all NOPS that the assembler generates. */
340 static int warn_nops
= 0;
342 /* 1 if we should generate 32 bit offsets from the $gp register in
343 SVR4_PIC mode. Currently has no meaning in other modes. */
344 static int mips_big_got
= 0;
346 /* 1 if trap instructions should used for overflow rather than break
348 static int mips_trap
= 0;
350 /* 1 if double width floating point constants should not be constructed
351 by assembling two single width halves into two single width floating
352 point registers which just happen to alias the double width destination
353 register. On some architectures this aliasing can be disabled by a bit
354 in the status register, and the setting of this bit cannot be determined
355 automatically at assemble time. */
356 static int mips_disable_float_construction
;
358 /* Non-zero if any .set noreorder directives were used. */
360 static int mips_any_noreorder
;
362 /* Non-zero if nops should be inserted when the register referenced in
363 an mfhi/mflo instruction is read in the next two instructions. */
364 static int mips_7000_hilo_fix
;
366 /* The size of the small data section. */
367 static unsigned int g_switch_value
= 8;
368 /* Whether the -G option was used. */
369 static int g_switch_seen
= 0;
374 /* If we can determine in advance that GP optimization won't be
375 possible, we can skip the relaxation stuff that tries to produce
376 GP-relative references. This makes delay slot optimization work
379 This function can only provide a guess, but it seems to work for
380 gcc output. It needs to guess right for gcc, otherwise gcc
381 will put what it thinks is a GP-relative instruction in a branch
384 I don't know if a fix is needed for the SVR4_PIC mode. I've only
385 fixed it for the non-PIC mode. KR 95/04/07 */
386 static int nopic_need_relax
PARAMS ((symbolS
*, int));
388 /* handle of the OPCODE hash table */
389 static struct hash_control
*op_hash
= NULL
;
391 /* The opcode hash table we use for the mips16. */
392 static struct hash_control
*mips16_op_hash
= NULL
;
394 /* This array holds the chars that always start a comment. If the
395 pre-processor is disabled, these aren't very useful */
396 const char comment_chars
[] = "#";
398 /* This array holds the chars that only start a comment at the beginning of
399 a line. If the line seems to have the form '# 123 filename'
400 .line and .file directives will appear in the pre-processed output */
401 /* Note that input_file.c hand checks for '#' at the beginning of the
402 first line of the input file. This is because the compiler outputs
403 #NO_APP at the beginning of its output. */
404 /* Also note that C style comments are always supported. */
405 const char line_comment_chars
[] = "#";
407 /* This array holds machine specific line separator characters. */
408 const char line_separator_chars
[] = ";";
410 /* Chars that can be used to separate mant from exp in floating point nums */
411 const char EXP_CHARS
[] = "eE";
413 /* Chars that mean this number is a floating point constant */
416 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
418 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
419 changed in read.c . Ideally it shouldn't have to know about it at all,
420 but nothing is ideal around here.
423 static char *insn_error
;
425 static int auto_align
= 1;
427 /* When outputting SVR4 PIC code, the assembler needs to know the
428 offset in the stack frame from which to restore the $gp register.
429 This is set by the .cprestore pseudo-op, and saved in this
431 static offsetT mips_cprestore_offset
= -1;
433 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
434 more optimizations, it can use a register value instead of a memory-saved
435 offset and even an other register than $gp as global pointer. */
436 static offsetT mips_cpreturn_offset
= -1;
437 static int mips_cpreturn_register
= -1;
438 static int mips_gp_register
= GP
;
439 static int mips_gprel_offset
= 0;
441 /* Whether mips_cprestore_offset has been set in the current function
442 (or whether it has already been warned about, if not). */
443 static int mips_cprestore_valid
= 0;
445 /* This is the register which holds the stack frame, as set by the
446 .frame pseudo-op. This is needed to implement .cprestore. */
447 static int mips_frame_reg
= SP
;
449 /* Whether mips_frame_reg has been set in the current function
450 (or whether it has already been warned about, if not). */
451 static int mips_frame_reg_valid
= 0;
453 /* To output NOP instructions correctly, we need to keep information
454 about the previous two instructions. */
456 /* Whether we are optimizing. The default value of 2 means to remove
457 unneeded NOPs and swap branch instructions when possible. A value
458 of 1 means to not swap branches. A value of 0 means to always
460 static int mips_optimize
= 2;
462 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
463 equivalent to seeing no -g option at all. */
464 static int mips_debug
= 0;
466 /* The previous instruction. */
467 static struct mips_cl_insn prev_insn
;
469 /* The instruction before prev_insn. */
470 static struct mips_cl_insn prev_prev_insn
;
472 /* If we don't want information for prev_insn or prev_prev_insn, we
473 point the insn_mo field at this dummy integer. */
474 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
476 /* Non-zero if prev_insn is valid. */
477 static int prev_insn_valid
;
479 /* The frag for the previous instruction. */
480 static struct frag
*prev_insn_frag
;
482 /* The offset into prev_insn_frag for the previous instruction. */
483 static long prev_insn_where
;
485 /* The reloc type for the previous instruction, if any. */
486 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
488 /* The reloc for the previous instruction, if any. */
489 static fixS
*prev_insn_fixp
[3];
491 /* Non-zero if the previous instruction was in a delay slot. */
492 static int prev_insn_is_delay_slot
;
494 /* Non-zero if the previous instruction was in a .set noreorder. */
495 static int prev_insn_unreordered
;
497 /* Non-zero if the previous instruction uses an extend opcode (if
499 static int prev_insn_extended
;
501 /* Non-zero if the previous previous instruction was in a .set
503 static int prev_prev_insn_unreordered
;
505 /* If this is set, it points to a frag holding nop instructions which
506 were inserted before the start of a noreorder section. If those
507 nops turn out to be unnecessary, the size of the frag can be
509 static fragS
*prev_nop_frag
;
511 /* The number of nop instructions we created in prev_nop_frag. */
512 static int prev_nop_frag_holds
;
514 /* The number of nop instructions that we know we need in
516 static int prev_nop_frag_required
;
518 /* The number of instructions we've seen since prev_nop_frag. */
519 static int prev_nop_frag_since
;
521 /* For ECOFF and ELF, relocations against symbols are done in two
522 parts, with a HI relocation and a LO relocation. Each relocation
523 has only 16 bits of space to store an addend. This means that in
524 order for the linker to handle carries correctly, it must be able
525 to locate both the HI and the LO relocation. This means that the
526 relocations must appear in order in the relocation table.
528 In order to implement this, we keep track of each unmatched HI
529 relocation. We then sort them so that they immediately precede the
530 corresponding LO relocation. */
535 struct mips_hi_fixup
*next
;
538 /* The section this fixup is in. */
542 /* The list of unmatched HI relocs. */
544 static struct mips_hi_fixup
*mips_hi_fixup_list
;
546 /* Map normal MIPS register numbers to mips16 register numbers. */
548 #define X ILLEGAL_REG
549 static const int mips32_to_16_reg_map
[] =
551 X
, X
, 2, 3, 4, 5, 6, 7,
552 X
, X
, X
, X
, X
, X
, X
, X
,
553 0, 1, X
, X
, X
, X
, X
, X
,
554 X
, X
, X
, X
, X
, X
, X
, X
558 /* Map mips16 register numbers to normal MIPS register numbers. */
560 static const unsigned int mips16_to_32_reg_map
[] =
562 16, 17, 2, 3, 4, 5, 6, 7
565 static int mips_fix_4122_bugs
;
567 /* We don't relax branches by default, since this causes us to expand
568 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
569 fail to compute the offset before expanding the macro to the most
570 efficient expansion. */
572 static int mips_relax_branch
;
574 /* Since the MIPS does not have multiple forms of PC relative
575 instructions, we do not have to do relaxing as is done on other
576 platforms. However, we do have to handle GP relative addressing
577 correctly, which turns out to be a similar problem.
579 Every macro that refers to a symbol can occur in (at least) two
580 forms, one with GP relative addressing and one without. For
581 example, loading a global variable into a register generally uses
582 a macro instruction like this:
584 If i can be addressed off the GP register (this is true if it is in
585 the .sbss or .sdata section, or if it is known to be smaller than
586 the -G argument) this will generate the following instruction:
588 This instruction will use a GPREL reloc. If i can not be addressed
589 off the GP register, the following instruction sequence will be used:
592 In this case the first instruction will have a HI16 reloc, and the
593 second reloc will have a LO16 reloc. Both relocs will be against
596 The issue here is that we may not know whether i is GP addressable
597 until after we see the instruction that uses it. Therefore, we
598 want to be able to choose the final instruction sequence only at
599 the end of the assembly. This is similar to the way other
600 platforms choose the size of a PC relative instruction only at the
603 When generating position independent code we do not use GP
604 addressing in quite the same way, but the issue still arises as
605 external symbols and local symbols must be handled differently.
607 We handle these issues by actually generating both possible
608 instruction sequences. The longer one is put in a frag_var with
609 type rs_machine_dependent. We encode what to do with the frag in
610 the subtype field. We encode (1) the number of existing bytes to
611 replace, (2) the number of new bytes to use, (3) the offset from
612 the start of the existing bytes to the first reloc we must generate
613 (that is, the offset is applied from the start of the existing
614 bytes after they are replaced by the new bytes, if any), (4) the
615 offset from the start of the existing bytes to the second reloc,
616 (5) whether a third reloc is needed (the third reloc is always four
617 bytes after the second reloc), and (6) whether to warn if this
618 variant is used (this is sometimes needed if .set nomacro or .set
619 noat is in effect). All these numbers are reasonably small.
621 Generating two instruction sequences must be handled carefully to
622 ensure that delay slots are handled correctly. Fortunately, there
623 are a limited number of cases. When the second instruction
624 sequence is generated, append_insn is directed to maintain the
625 existing delay slot information, so it continues to apply to any
626 code after the second instruction sequence. This means that the
627 second instruction sequence must not impose any requirements not
628 required by the first instruction sequence.
630 These variant frags are then handled in functions called by the
631 machine independent code. md_estimate_size_before_relax returns
632 the final size of the frag. md_convert_frag sets up the final form
633 of the frag. tc_gen_reloc adjust the first reloc and adds a second
635 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
639 | (((reloc1) + 64) << 9) \
640 | (((reloc2) + 64) << 2) \
641 | ((reloc3) ? (1 << 1) : 0) \
643 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
644 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
645 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
646 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
647 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
648 #define RELAX_WARN(i) ((i) & 1)
650 /* Branch without likely bit. If label is out of range, we turn:
652 beq reg1, reg2, label
662 with the following opcode replacements:
669 bltzal <-> bgezal (with jal label instead of j label)
671 Even though keeping the delay slot instruction in the delay slot of
672 the branch would be more efficient, it would be very tricky to do
673 correctly, because we'd have to introduce a variable frag *after*
674 the delay slot instruction, and expand that instead. Let's do it
675 the easy way for now, even if the branch-not-taken case now costs
676 one additional instruction. Out-of-range branches are not supposed
677 to be common, anyway.
679 Branch likely. If label is out of range, we turn:
681 beql reg1, reg2, label
682 delay slot (annulled if branch not taken)
691 delay slot (executed only if branch taken)
694 It would be possible to generate a shorter sequence by losing the
695 likely bit, generating something like:
700 delay slot (executed only if branch taken)
712 bltzall -> bgezal (with jal label instead of j label)
713 bgezall -> bltzal (ditto)
716 but it's not clear that it would actually improve performance. */
717 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
720 | ((toofar) ? 1 : 0) \
722 | ((likely) ? 4 : 0) \
723 | ((uncond) ? 8 : 0)))
724 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
725 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
726 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
727 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
728 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1))
730 /* For mips16 code, we use an entirely different form of relaxation.
731 mips16 supports two versions of most instructions which take
732 immediate values: a small one which takes some small value, and a
733 larger one which takes a 16 bit value. Since branches also follow
734 this pattern, relaxing these values is required.
736 We can assemble both mips16 and normal MIPS code in a single
737 object. Therefore, we need to support this type of relaxation at
738 the same time that we support the relaxation described above. We
739 use the high bit of the subtype field to distinguish these cases.
741 The information we store for this type of relaxation is the
742 argument code found in the opcode file for this relocation, whether
743 the user explicitly requested a small or extended form, and whether
744 the relocation is in a jump or jal delay slot. That tells us the
745 size of the value, and how it should be stored. We also store
746 whether the fragment is considered to be extended or not. We also
747 store whether this is known to be a branch to a different section,
748 whether we have tried to relax this frag yet, and whether we have
749 ever extended a PC relative fragment because of a shift count. */
750 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
753 | ((small) ? 0x100 : 0) \
754 | ((ext) ? 0x200 : 0) \
755 | ((dslot) ? 0x400 : 0) \
756 | ((jal_dslot) ? 0x800 : 0))
757 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
758 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
759 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
760 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
761 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
762 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
763 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
764 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
765 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
766 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
767 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
768 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
770 /* Is the given value a sign-extended 32-bit value? */
771 #define IS_SEXT_32BIT_NUM(x) \
772 (((x) &~ (offsetT) 0x7fffffff) == 0 \
773 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
775 /* Is the given value a sign-extended 16-bit value? */
776 #define IS_SEXT_16BIT_NUM(x) \
777 (((x) &~ (offsetT) 0x7fff) == 0 \
778 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
781 /* Prototypes for static functions. */
784 #define internalError() \
785 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
787 #define internalError() as_fatal (_("MIPS internal Error"));
790 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
792 static int insn_uses_reg
793 PARAMS ((struct mips_cl_insn
*ip
, unsigned int reg
,
794 enum mips_regclass
class));
795 static int reg_needs_delay
796 PARAMS ((unsigned int));
797 static void mips16_mark_labels
799 static void append_insn
800 PARAMS ((char *place
, struct mips_cl_insn
* ip
, expressionS
* p
,
801 bfd_reloc_code_real_type
*r
, bfd_boolean
));
802 static void mips_no_prev_insn
804 static void mips_emit_delays
805 PARAMS ((bfd_boolean
));
807 static void macro_build
808 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *name
,
809 const char *fmt
, ...));
811 static void macro_build ();
813 static void mips16_macro_build
814 PARAMS ((char *, int *, expressionS
*, const char *, const char *, va_list));
815 static void macro_build_jalr
816 PARAMS ((int, expressionS
*));
817 static void macro_build_lui
818 PARAMS ((char *place
, int *counter
, expressionS
* ep
, int regnum
));
819 static void macro_build_ldst_constoffset
820 PARAMS ((char *place
, int *counter
, expressionS
* ep
, const char *op
,
821 int valreg
, int breg
));
823 PARAMS ((int *counter
, int reg
, int unsignedp
));
824 static void check_absolute_expr
825 PARAMS ((struct mips_cl_insn
* ip
, expressionS
*));
826 static void load_register
827 PARAMS ((int *, int, expressionS
*, int));
828 static void load_address
829 PARAMS ((int *, int, expressionS
*, int *));
830 static void move_register
831 PARAMS ((int *, int, int));
833 PARAMS ((struct mips_cl_insn
* ip
));
834 static void mips16_macro
835 PARAMS ((struct mips_cl_insn
* ip
));
836 #ifdef LOSING_COMPILER
838 PARAMS ((struct mips_cl_insn
* ip
));
841 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
842 static void mips16_ip
843 PARAMS ((char *str
, struct mips_cl_insn
* ip
));
844 static void mips16_immed
845 PARAMS ((char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
,
846 bfd_boolean
, unsigned long *, bfd_boolean
*, unsigned short *));
847 static int my_getPercentOp
848 PARAMS ((char **, unsigned int *, int *));
849 static int my_getSmallParser
850 PARAMS ((char **, unsigned int *, int *));
851 static int my_getSmallExpression
852 PARAMS ((expressionS
*, char *));
853 static void my_getExpression
854 PARAMS ((expressionS
*, char *));
856 static int support_64bit_objects
859 static void mips_set_option_string
860 PARAMS ((const char **, const char *));
861 static symbolS
*get_symbol
863 static void mips_align
864 PARAMS ((int to
, int fill
, symbolS
*label
));
867 static void s_change_sec
869 static void s_change_section
873 static void s_float_cons
875 static void s_mips_globl
879 static void s_mipsset
881 static void s_abicalls
885 static void s_cpsetup
887 static void s_cplocal
889 static void s_cprestore
891 static void s_cpreturn
893 static void s_gpvalue
897 static void s_gpdword
903 static void md_obj_begin
905 static void md_obj_end
907 static long get_number
909 static void s_mips_ent
911 static void s_mips_end
913 static void s_mips_frame
915 static void s_mips_mask
917 static void s_mips_stab
919 static void s_mips_weakext
921 static void s_mips_file
923 static void s_mips_loc
925 static int mips16_extended_frag
926 PARAMS ((fragS
*, asection
*, long));
927 static int relaxed_branch_length (fragS
*, asection
*, int);
928 static int validate_mips_insn
929 PARAMS ((const struct mips_opcode
*));
931 PARAMS ((FILE *, const char *, int *, int *));
933 static int mips_need_elf_addend_fixup
937 /* Return values of my_getSmallExpression(). */
944 /* Direct relocation creation by %percent_op(). */
963 /* Table and functions used to map between CPU/ISA names, and
964 ISA levels, and CPU numbers. */
968 const char *name
; /* CPU or ISA name. */
969 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
970 int isa
; /* ISA level. */
971 int cpu
; /* CPU number (default CPU if ISA). */
974 static void mips_set_architecture
975 PARAMS ((const struct mips_cpu_info
*));
976 static void mips_set_tune
977 PARAMS ((const struct mips_cpu_info
*));
978 static bfd_boolean mips_strict_matching_cpu_name_p
979 PARAMS ((const char *, const char *));
980 static bfd_boolean mips_matching_cpu_name_p
981 PARAMS ((const char *, const char *));
982 static const struct mips_cpu_info
*mips_parse_cpu
983 PARAMS ((const char *, const char *));
984 static const struct mips_cpu_info
*mips_cpu_info_from_isa
989 The following pseudo-ops from the Kane and Heinrich MIPS book
990 should be defined here, but are currently unsupported: .alias,
991 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
993 The following pseudo-ops from the Kane and Heinrich MIPS book are
994 specific to the type of debugging information being generated, and
995 should be defined by the object format: .aent, .begin, .bend,
996 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
999 The following pseudo-ops from the Kane and Heinrich MIPS book are
1000 not MIPS CPU specific, but are also not specific to the object file
1001 format. This file is probably the best place to define them, but
1002 they are not currently supported: .asm0, .endr, .lab, .repeat,
1005 static const pseudo_typeS mips_pseudo_table
[] =
1007 /* MIPS specific pseudo-ops. */
1008 {"option", s_option
, 0},
1009 {"set", s_mipsset
, 0},
1010 {"rdata", s_change_sec
, 'r'},
1011 {"sdata", s_change_sec
, 's'},
1012 {"livereg", s_ignore
, 0},
1013 {"abicalls", s_abicalls
, 0},
1014 {"cpload", s_cpload
, 0},
1015 {"cpsetup", s_cpsetup
, 0},
1016 {"cplocal", s_cplocal
, 0},
1017 {"cprestore", s_cprestore
, 0},
1018 {"cpreturn", s_cpreturn
, 0},
1019 {"gpvalue", s_gpvalue
, 0},
1020 {"gpword", s_gpword
, 0},
1021 {"gpdword", s_gpdword
, 0},
1022 {"cpadd", s_cpadd
, 0},
1023 {"insn", s_insn
, 0},
1025 /* Relatively generic pseudo-ops that happen to be used on MIPS
1027 {"asciiz", stringer
, 1},
1028 {"bss", s_change_sec
, 'b'},
1030 {"half", s_cons
, 1},
1031 {"dword", s_cons
, 3},
1032 {"weakext", s_mips_weakext
, 0},
1034 /* These pseudo-ops are defined in read.c, but must be overridden
1035 here for one reason or another. */
1036 {"align", s_align
, 0},
1037 {"byte", s_cons
, 0},
1038 {"data", s_change_sec
, 'd'},
1039 {"double", s_float_cons
, 'd'},
1040 {"float", s_float_cons
, 'f'},
1041 {"globl", s_mips_globl
, 0},
1042 {"global", s_mips_globl
, 0},
1043 {"hword", s_cons
, 1},
1045 {"long", s_cons
, 2},
1046 {"octa", s_cons
, 4},
1047 {"quad", s_cons
, 3},
1048 {"section", s_change_section
, 0},
1049 {"short", s_cons
, 1},
1050 {"single", s_float_cons
, 'f'},
1051 {"stabn", s_mips_stab
, 'n'},
1052 {"text", s_change_sec
, 't'},
1053 {"word", s_cons
, 2},
1055 { "extern", ecoff_directive_extern
, 0},
1060 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1062 /* These pseudo-ops should be defined by the object file format.
1063 However, a.out doesn't support them, so we have versions here. */
1064 {"aent", s_mips_ent
, 1},
1065 {"bgnb", s_ignore
, 0},
1066 {"end", s_mips_end
, 0},
1067 {"endb", s_ignore
, 0},
1068 {"ent", s_mips_ent
, 0},
1069 {"file", s_mips_file
, 0},
1070 {"fmask", s_mips_mask
, 'F'},
1071 {"frame", s_mips_frame
, 0},
1072 {"loc", s_mips_loc
, 0},
1073 {"mask", s_mips_mask
, 'R'},
1074 {"verstamp", s_ignore
, 0},
1078 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
1083 pop_insert (mips_pseudo_table
);
1084 if (! ECOFF_DEBUGGING
)
1085 pop_insert (mips_nonecoff_pseudo_table
);
1088 /* Symbols labelling the current insn. */
1090 struct insn_label_list
1092 struct insn_label_list
*next
;
1096 static struct insn_label_list
*insn_labels
;
1097 static struct insn_label_list
*free_insn_labels
;
1099 static void mips_clear_insn_labels
PARAMS ((void));
1102 mips_clear_insn_labels ()
1104 register struct insn_label_list
**pl
;
1106 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1112 static char *expr_end
;
1114 /* Expressions which appear in instructions. These are set by
1117 static expressionS imm_expr
;
1118 static expressionS offset_expr
;
1120 /* Relocs associated with imm_expr and offset_expr. */
1122 static bfd_reloc_code_real_type imm_reloc
[3]
1123 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1124 static bfd_reloc_code_real_type offset_reloc
[3]
1125 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1127 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
1129 static bfd_boolean imm_unmatched_hi
;
1131 /* These are set by mips16_ip if an explicit extension is used. */
1133 static bfd_boolean mips16_small
, mips16_ext
;
1136 /* The pdr segment for per procedure frame/regmask info. Not used for
1139 static segT pdr_seg
;
1142 /* The default target format to use. */
1145 mips_target_format ()
1147 switch (OUTPUT_FLAVOR
)
1149 case bfd_target_aout_flavour
:
1150 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1151 case bfd_target_ecoff_flavour
:
1152 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1153 case bfd_target_coff_flavour
:
1155 case bfd_target_elf_flavour
:
1157 /* This is traditional mips. */
1158 return (target_big_endian
1159 ? (HAVE_64BIT_OBJECTS
1160 ? "elf64-tradbigmips"
1162 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1163 : (HAVE_64BIT_OBJECTS
1164 ? "elf64-tradlittlemips"
1166 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1168 return (target_big_endian
1169 ? (HAVE_64BIT_OBJECTS
1172 ? "elf32-nbigmips" : "elf32-bigmips"))
1173 : (HAVE_64BIT_OBJECTS
1174 ? "elf64-littlemips"
1176 ? "elf32-nlittlemips" : "elf32-littlemips")));
1184 /* This function is called once, at assembler startup time. It should
1185 set up all the tables, etc. that the MD part of the assembler will need. */
1190 register const char *retval
= NULL
;
1194 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1195 as_warn (_("Could not set architecture and machine"));
1197 op_hash
= hash_new ();
1199 for (i
= 0; i
< NUMOPCODES
;)
1201 const char *name
= mips_opcodes
[i
].name
;
1203 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1206 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1207 mips_opcodes
[i
].name
, retval
);
1208 /* Probably a memory allocation problem? Give up now. */
1209 as_fatal (_("Broken assembler. No assembly attempted."));
1213 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1215 if (!validate_mips_insn (&mips_opcodes
[i
]))
1220 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1223 mips16_op_hash
= hash_new ();
1226 while (i
< bfd_mips16_num_opcodes
)
1228 const char *name
= mips16_opcodes
[i
].name
;
1230 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1232 as_fatal (_("internal: can't hash `%s': %s"),
1233 mips16_opcodes
[i
].name
, retval
);
1236 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1237 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1238 != mips16_opcodes
[i
].match
))
1240 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1241 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1246 while (i
< bfd_mips16_num_opcodes
1247 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1251 as_fatal (_("Broken assembler. No assembly attempted."));
1253 /* We add all the general register names to the symbol table. This
1254 helps us detect invalid uses of them. */
1255 for (i
= 0; i
< 32; i
++)
1259 sprintf (buf
, "$%d", i
);
1260 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1261 &zero_address_frag
));
1263 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1264 &zero_address_frag
));
1265 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1266 &zero_address_frag
));
1267 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1268 &zero_address_frag
));
1269 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1270 &zero_address_frag
));
1271 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1272 &zero_address_frag
));
1273 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1274 &zero_address_frag
));
1275 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1276 &zero_address_frag
));
1277 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1278 &zero_address_frag
));
1279 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1280 &zero_address_frag
));
1282 /* If we don't add these register names to the symbol table, they
1283 may end up being added as regular symbols by operand(), and then
1284 make it to the object file as undefined in case they're not
1285 regarded as local symbols. They're local in o32, since `$' is a
1286 local symbol prefix, but not in n32 or n64. */
1287 for (i
= 0; i
< 8; i
++)
1291 sprintf (buf
, "$fcc%i", i
);
1292 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1293 &zero_address_frag
));
1296 mips_no_prev_insn (FALSE
);
1299 mips_cprmask
[0] = 0;
1300 mips_cprmask
[1] = 0;
1301 mips_cprmask
[2] = 0;
1302 mips_cprmask
[3] = 0;
1304 /* set the default alignment for the text section (2**2) */
1305 record_alignment (text_section
, 2);
1307 if (USE_GLOBAL_POINTER_OPT
)
1308 bfd_set_gp_size (stdoutput
, g_switch_value
);
1310 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1312 /* On a native system, sections must be aligned to 16 byte
1313 boundaries. When configured for an embedded ELF target, we
1315 if (strcmp (TARGET_OS
, "elf") != 0)
1317 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1318 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1319 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1322 /* Create a .reginfo section for register masks and a .mdebug
1323 section for debugging information. */
1331 subseg
= now_subseg
;
1333 /* The ABI says this section should be loaded so that the
1334 running program can access it. However, we don't load it
1335 if we are configured for an embedded target */
1336 flags
= SEC_READONLY
| SEC_DATA
;
1337 if (strcmp (TARGET_OS
, "elf") != 0)
1338 flags
|= SEC_ALLOC
| SEC_LOAD
;
1340 if (mips_abi
!= N64_ABI
)
1342 sec
= subseg_new (".reginfo", (subsegT
) 0);
1344 bfd_set_section_flags (stdoutput
, sec
, flags
);
1345 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1348 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1353 /* The 64-bit ABI uses a .MIPS.options section rather than
1354 .reginfo section. */
1355 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1356 bfd_set_section_flags (stdoutput
, sec
, flags
);
1357 bfd_set_section_alignment (stdoutput
, sec
, 3);
1360 /* Set up the option header. */
1362 Elf_Internal_Options opthdr
;
1365 opthdr
.kind
= ODK_REGINFO
;
1366 opthdr
.size
= (sizeof (Elf_External_Options
)
1367 + sizeof (Elf64_External_RegInfo
));
1370 f
= frag_more (sizeof (Elf_External_Options
));
1371 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1372 (Elf_External_Options
*) f
);
1374 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1379 if (ECOFF_DEBUGGING
)
1381 sec
= subseg_new (".mdebug", (subsegT
) 0);
1382 (void) bfd_set_section_flags (stdoutput
, sec
,
1383 SEC_HAS_CONTENTS
| SEC_READONLY
);
1384 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1387 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1389 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1390 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1391 SEC_READONLY
| SEC_RELOC
1393 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1397 subseg_set (seg
, subseg
);
1401 if (! ECOFF_DEBUGGING
)
1408 if (! ECOFF_DEBUGGING
)
1416 struct mips_cl_insn insn
;
1417 bfd_reloc_code_real_type unused_reloc
[3]
1418 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1420 imm_expr
.X_op
= O_absent
;
1421 imm_unmatched_hi
= FALSE
;
1422 offset_expr
.X_op
= O_absent
;
1423 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1424 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1425 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1426 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1427 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1428 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1430 if (mips_opts
.mips16
)
1431 mips16_ip (str
, &insn
);
1434 mips_ip (str
, &insn
);
1435 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1436 str
, insn
.insn_opcode
));
1441 as_bad ("%s `%s'", insn_error
, str
);
1445 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1447 if (mips_opts
.mips16
)
1448 mips16_macro (&insn
);
1454 if (imm_expr
.X_op
!= O_absent
)
1455 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1456 else if (offset_expr
.X_op
!= O_absent
)
1457 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, FALSE
);
1459 append_insn (NULL
, &insn
, NULL
, unused_reloc
, FALSE
);
1463 /* See whether instruction IP reads register REG. CLASS is the type
1467 insn_uses_reg (ip
, reg
, class)
1468 struct mips_cl_insn
*ip
;
1470 enum mips_regclass
class;
1472 if (class == MIPS16_REG
)
1474 assert (mips_opts
.mips16
);
1475 reg
= mips16_to_32_reg_map
[reg
];
1476 class = MIPS_GR_REG
;
1479 /* Don't report on general register ZERO, since it never changes. */
1480 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1483 if (class == MIPS_FP_REG
)
1485 assert (! mips_opts
.mips16
);
1486 /* If we are called with either $f0 or $f1, we must check $f0.
1487 This is not optimal, because it will introduce an unnecessary
1488 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1489 need to distinguish reading both $f0 and $f1 or just one of
1490 them. Note that we don't have to check the other way,
1491 because there is no instruction that sets both $f0 and $f1
1492 and requires a delay. */
1493 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1494 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1495 == (reg
&~ (unsigned) 1)))
1497 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1498 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1499 == (reg
&~ (unsigned) 1)))
1502 else if (! mips_opts
.mips16
)
1504 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1505 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1507 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1508 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1513 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1514 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1515 & MIPS16OP_MASK_RX
)]
1518 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1519 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1520 & MIPS16OP_MASK_RY
)]
1523 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1524 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1525 & MIPS16OP_MASK_MOVE32Z
)]
1528 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1530 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1532 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1534 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1535 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1536 & MIPS16OP_MASK_REGR32
) == reg
)
1543 /* This function returns true if modifying a register requires a
1547 reg_needs_delay (reg
)
1550 unsigned long prev_pinfo
;
1552 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1553 if (! mips_opts
.noreorder
1554 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1555 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1556 || (! gpr_interlocks
1557 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1559 /* A load from a coprocessor or from memory. All load
1560 delays delay the use of general register rt for one
1561 instruction on the r3000. The r6000 and r4000 use
1563 /* Itbl support may require additional care here. */
1564 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1565 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1572 /* Mark instruction labels in mips16 mode. This permits the linker to
1573 handle them specially, such as generating jalx instructions when
1574 needed. We also make them odd for the duration of the assembly, in
1575 order to generate the right sort of code. We will make them even
1576 in the adjust_symtab routine, while leaving them marked. This is
1577 convenient for the debugger and the disassembler. The linker knows
1578 to make them odd again. */
1581 mips16_mark_labels ()
1583 if (mips_opts
.mips16
)
1585 struct insn_label_list
*l
;
1588 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1591 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1592 S_SET_OTHER (l
->label
, STO_MIPS16
);
1594 val
= S_GET_VALUE (l
->label
);
1596 S_SET_VALUE (l
->label
, val
+ 1);
1601 /* Output an instruction. PLACE is where to put the instruction; if
1602 it is NULL, this uses frag_more to get room. IP is the instruction
1603 information. ADDRESS_EXPR is an operand of the instruction to be
1604 used with RELOC_TYPE. */
1607 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1609 struct mips_cl_insn
*ip
;
1610 expressionS
*address_expr
;
1611 bfd_reloc_code_real_type
*reloc_type
;
1612 bfd_boolean unmatched_hi
;
1614 register unsigned long prev_pinfo
, pinfo
;
1619 /* Mark instruction labels in mips16 mode. */
1620 mips16_mark_labels ();
1622 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1623 pinfo
= ip
->insn_mo
->pinfo
;
1625 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1629 /* If the previous insn required any delay slots, see if we need
1630 to insert a NOP or two. There are eight kinds of possible
1631 hazards, of which an instruction can have at most one type.
1632 (1) a load from memory delay
1633 (2) a load from a coprocessor delay
1634 (3) an unconditional branch delay
1635 (4) a conditional branch delay
1636 (5) a move to coprocessor register delay
1637 (6) a load coprocessor register from memory delay
1638 (7) a coprocessor condition code delay
1639 (8) a HI/LO special register delay
1641 There are a lot of optimizations we could do that we don't.
1642 In particular, we do not, in general, reorder instructions.
1643 If you use gcc with optimization, it will reorder
1644 instructions and generally do much more optimization then we
1645 do here; repeating all that work in the assembler would only
1646 benefit hand written assembly code, and does not seem worth
1649 /* This is how a NOP is emitted. */
1650 #define emit_nop() \
1652 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1653 : md_number_to_chars (frag_more (4), 0, 4))
1655 /* The previous insn might require a delay slot, depending upon
1656 the contents of the current insn. */
1657 if (! mips_opts
.mips16
1658 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1659 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1660 && ! cop_interlocks
)
1661 || (! gpr_interlocks
1662 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1664 /* A load from a coprocessor or from memory. All load
1665 delays delay the use of general register rt for one
1666 instruction on the r3000. The r6000 and r4000 use
1668 /* Itbl support may require additional care here. */
1669 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1670 if (mips_optimize
== 0
1671 || insn_uses_reg (ip
,
1672 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1677 else if (! mips_opts
.mips16
1678 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1679 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1680 && ! cop_interlocks
)
1681 || (mips_opts
.isa
== ISA_MIPS1
1682 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1684 /* A generic coprocessor delay. The previous instruction
1685 modified a coprocessor general or control register. If
1686 it modified a control register, we need to avoid any
1687 coprocessor instruction (this is probably not always
1688 required, but it sometimes is). If it modified a general
1689 register, we avoid using that register.
1691 On the r6000 and r4000 loading a coprocessor register
1692 from memory is interlocked, and does not require a delay.
1694 This case is not handled very well. There is no special
1695 knowledge of CP0 handling, and the coprocessors other
1696 than the floating point unit are not distinguished at
1698 /* Itbl support may require additional care here. FIXME!
1699 Need to modify this to include knowledge about
1700 user specified delays! */
1701 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1703 if (mips_optimize
== 0
1704 || insn_uses_reg (ip
,
1705 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1710 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1712 if (mips_optimize
== 0
1713 || insn_uses_reg (ip
,
1714 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1721 /* We don't know exactly what the previous instruction
1722 does. If the current instruction uses a coprocessor
1723 register, we must insert a NOP. If previous
1724 instruction may set the condition codes, and the
1725 current instruction uses them, we must insert two
1727 /* Itbl support may require additional care here. */
1728 if (mips_optimize
== 0
1729 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1730 && (pinfo
& INSN_READ_COND_CODE
)))
1732 else if (pinfo
& INSN_COP
)
1736 else if (! mips_opts
.mips16
1737 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1738 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1739 && ! cop_interlocks
)
1741 /* The previous instruction sets the coprocessor condition
1742 codes, but does not require a general coprocessor delay
1743 (this means it is a floating point comparison
1744 instruction). If this instruction uses the condition
1745 codes, we need to insert a single NOP. */
1746 /* Itbl support may require additional care here. */
1747 if (mips_optimize
== 0
1748 || (pinfo
& INSN_READ_COND_CODE
))
1752 /* If we're fixing up mfhi/mflo for the r7000 and the
1753 previous insn was an mfhi/mflo and the current insn
1754 reads the register that the mfhi/mflo wrote to, then
1757 else if (mips_7000_hilo_fix
1758 && MF_HILO_INSN (prev_pinfo
)
1759 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1766 /* If we're fixing up mfhi/mflo for the r7000 and the
1767 2nd previous insn was an mfhi/mflo and the current insn
1768 reads the register that the mfhi/mflo wrote to, then
1771 else if (mips_7000_hilo_fix
1772 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1773 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1781 else if (prev_pinfo
& INSN_READ_LO
)
1783 /* The previous instruction reads the LO register; if the
1784 current instruction writes to the LO register, we must
1785 insert two NOPS. Some newer processors have interlocks.
1786 Also the tx39's multiply instructions can be exectuted
1787 immediatly after a read from HI/LO (without the delay),
1788 though the tx39's divide insns still do require the
1790 if (! (hilo_interlocks
1791 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1792 && (mips_optimize
== 0
1793 || (pinfo
& INSN_WRITE_LO
)))
1795 /* Most mips16 branch insns don't have a delay slot.
1796 If a read from LO is immediately followed by a branch
1797 to a write to LO we have a read followed by a write
1798 less than 2 insns away. We assume the target of
1799 a branch might be a write to LO, and insert a nop
1800 between a read and an immediately following branch. */
1801 else if (mips_opts
.mips16
1802 && (mips_optimize
== 0
1803 || (pinfo
& MIPS16_INSN_BRANCH
)))
1806 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1808 /* The previous instruction reads the HI register; if the
1809 current instruction writes to the HI register, we must
1810 insert a NOP. Some newer processors have interlocks.
1811 Also the note tx39's multiply above. */
1812 if (! (hilo_interlocks
1813 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1814 && (mips_optimize
== 0
1815 || (pinfo
& INSN_WRITE_HI
)))
1817 /* Most mips16 branch insns don't have a delay slot.
1818 If a read from HI is immediately followed by a branch
1819 to a write to HI we have a read followed by a write
1820 less than 2 insns away. We assume the target of
1821 a branch might be a write to HI, and insert a nop
1822 between a read and an immediately following branch. */
1823 else if (mips_opts
.mips16
1824 && (mips_optimize
== 0
1825 || (pinfo
& MIPS16_INSN_BRANCH
)))
1829 /* If the previous instruction was in a noreorder section, then
1830 we don't want to insert the nop after all. */
1831 /* Itbl support may require additional care here. */
1832 if (prev_insn_unreordered
)
1835 /* There are two cases which require two intervening
1836 instructions: 1) setting the condition codes using a move to
1837 coprocessor instruction which requires a general coprocessor
1838 delay and then reading the condition codes 2) reading the HI
1839 or LO register and then writing to it (except on processors
1840 which have interlocks). If we are not already emitting a NOP
1841 instruction, we must check for these cases compared to the
1842 instruction previous to the previous instruction. */
1843 if ((! mips_opts
.mips16
1844 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1845 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1846 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1847 && (pinfo
& INSN_READ_COND_CODE
)
1848 && ! cop_interlocks
)
1849 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1850 && (pinfo
& INSN_WRITE_LO
)
1851 && ! (hilo_interlocks
1852 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1853 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1854 && (pinfo
& INSN_WRITE_HI
)
1855 && ! (hilo_interlocks
1856 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1861 if (prev_prev_insn_unreordered
)
1864 if (prev_prev_nop
&& nops
== 0)
1867 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
1869 /* We're out of bits in pinfo, so we must resort to string
1870 ops here. Shortcuts are selected based on opcodes being
1871 limited to the VR4122 instruction set. */
1873 const char *pn
= prev_insn
.insn_mo
->name
;
1874 const char *tn
= ip
->insn_mo
->name
;
1875 if (strncmp(pn
, "macc", 4) == 0
1876 || strncmp(pn
, "dmacc", 5) == 0)
1878 /* Errata 21 - [D]DIV[U] after [D]MACC */
1879 if (strstr (tn
, "div"))
1884 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1885 if (pn
[0] == 'd' /* dmacc */
1886 && (strncmp(tn
, "dmult", 5) == 0
1887 || strncmp(tn
, "dmacc", 5) == 0))
1892 /* Errata 24 - MT{LO,HI} after [D]MACC */
1893 if (strcmp (tn
, "mtlo") == 0
1894 || strcmp (tn
, "mthi") == 0)
1900 else if (strncmp(pn
, "dmult", 5) == 0
1901 && (strncmp(tn
, "dmult", 5) == 0
1902 || strncmp(tn
, "dmacc", 5) == 0))
1904 /* Here is the rest of errata 23. */
1907 if (nops
< min_nops
)
1911 /* If we are being given a nop instruction, don't bother with
1912 one of the nops we would otherwise output. This will only
1913 happen when a nop instruction is used with mips_optimize set
1916 && ! mips_opts
.noreorder
1917 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1920 /* Now emit the right number of NOP instructions. */
1921 if (nops
> 0 && ! mips_opts
.noreorder
)
1924 unsigned long old_frag_offset
;
1926 struct insn_label_list
*l
;
1928 old_frag
= frag_now
;
1929 old_frag_offset
= frag_now_fix ();
1931 for (i
= 0; i
< nops
; i
++)
1936 listing_prev_line ();
1937 /* We may be at the start of a variant frag. In case we
1938 are, make sure there is enough space for the frag
1939 after the frags created by listing_prev_line. The
1940 argument to frag_grow here must be at least as large
1941 as the argument to all other calls to frag_grow in
1942 this file. We don't have to worry about being in the
1943 middle of a variant frag, because the variants insert
1944 all needed nop instructions themselves. */
1948 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1952 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1953 symbol_set_frag (l
->label
, frag_now
);
1954 val
= (valueT
) frag_now_fix ();
1955 /* mips16 text labels are stored as odd. */
1956 if (mips_opts
.mips16
)
1958 S_SET_VALUE (l
->label
, val
);
1961 #ifndef NO_ECOFF_DEBUGGING
1962 if (ECOFF_DEBUGGING
)
1963 ecoff_fix_loc (old_frag
, old_frag_offset
);
1966 else if (prev_nop_frag
!= NULL
)
1968 /* We have a frag holding nops we may be able to remove. If
1969 we don't need any nops, we can decrease the size of
1970 prev_nop_frag by the size of one instruction. If we do
1971 need some nops, we count them in prev_nops_required. */
1972 if (prev_nop_frag_since
== 0)
1976 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1977 --prev_nop_frag_holds
;
1980 prev_nop_frag_required
+= nops
;
1984 if (prev_prev_nop
== 0)
1986 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1987 --prev_nop_frag_holds
;
1990 ++prev_nop_frag_required
;
1993 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1994 prev_nop_frag
= NULL
;
1996 ++prev_nop_frag_since
;
1998 /* Sanity check: by the time we reach the second instruction
1999 after prev_nop_frag, we should have used up all the nops
2000 one way or another. */
2001 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2007 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2008 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2009 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2010 && mips_relax_branch
2011 /* Don't try branch relaxation within .set nomacro, or within
2012 .set noat if we use $at for PIC computations. If it turns
2013 out that the branch was out-of-range, we'll get an error. */
2014 && !mips_opts
.warn_about_macros
2015 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2016 && !mips_opts
.mips16
)
2018 f
= frag_var (rs_machine_dependent
,
2019 relaxed_branch_length
2021 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2022 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2024 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2025 pinfo
& INSN_COND_BRANCH_LIKELY
,
2026 pinfo
& INSN_WRITE_GPR_31
,
2028 address_expr
->X_add_symbol
,
2029 address_expr
->X_add_number
,
2031 *reloc_type
= BFD_RELOC_UNUSED
;
2033 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2035 /* We need to set up a variant frag. */
2036 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2037 f
= frag_var (rs_machine_dependent
, 4, 0,
2038 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2039 mips16_small
, mips16_ext
,
2041 & INSN_UNCOND_BRANCH_DELAY
),
2042 (*prev_insn_reloc_type
2043 == BFD_RELOC_MIPS16_JMP
)),
2044 make_expr_symbol (address_expr
), 0, NULL
);
2046 else if (place
!= NULL
)
2048 else if (mips_opts
.mips16
2050 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2052 /* Make sure there is enough room to swap this instruction with
2053 a following jump instruction. */
2059 if (mips_opts
.mips16
2060 && mips_opts
.noreorder
2061 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2062 as_warn (_("extended instruction in delay slot"));
2067 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2068 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2070 if (address_expr
->X_op
== O_constant
)
2074 switch (*reloc_type
)
2077 ip
->insn_opcode
|= address_expr
->X_add_number
;
2080 case BFD_RELOC_MIPS_HIGHEST
:
2081 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2083 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2086 case BFD_RELOC_MIPS_HIGHER
:
2087 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2088 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2091 case BFD_RELOC_HI16_S
:
2092 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2096 case BFD_RELOC_HI16
:
2097 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2100 case BFD_RELOC_LO16
:
2101 case BFD_RELOC_MIPS_GOT_DISP
:
2102 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2105 case BFD_RELOC_MIPS_JMP
:
2106 if ((address_expr
->X_add_number
& 3) != 0)
2107 as_bad (_("jump to misaligned address (0x%lx)"),
2108 (unsigned long) address_expr
->X_add_number
);
2109 if (address_expr
->X_add_number
& ~0xfffffff)
2110 as_bad (_("jump address range overflow (0x%lx)"),
2111 (unsigned long) address_expr
->X_add_number
);
2112 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2115 case BFD_RELOC_MIPS16_JMP
:
2116 if ((address_expr
->X_add_number
& 3) != 0)
2117 as_bad (_("jump to misaligned address (0x%lx)"),
2118 (unsigned long) address_expr
->X_add_number
);
2119 if (address_expr
->X_add_number
& ~0xfffffff)
2120 as_bad (_("jump address range overflow (0x%lx)"),
2121 (unsigned long) address_expr
->X_add_number
);
2123 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2124 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2125 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2128 case BFD_RELOC_16_PCREL_S2
:
2138 /* Don't generate a reloc if we are writing into a variant frag. */
2141 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2143 *reloc_type
== BFD_RELOC_16_PCREL_S2
,
2146 /* These relocations can have an addend that won't fit in
2147 4 octets for 64bit assembly. */
2148 if (HAVE_64BIT_GPRS
&&
2149 (*reloc_type
== BFD_RELOC_16
2150 || *reloc_type
== BFD_RELOC_32
2151 || *reloc_type
== BFD_RELOC_MIPS_JMP
2152 || *reloc_type
== BFD_RELOC_HI16_S
2153 || *reloc_type
== BFD_RELOC_LO16
2154 || *reloc_type
== BFD_RELOC_GPREL16
2155 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2156 || *reloc_type
== BFD_RELOC_GPREL32
2157 || *reloc_type
== BFD_RELOC_64
2158 || *reloc_type
== BFD_RELOC_CTOR
2159 || *reloc_type
== BFD_RELOC_MIPS_SUB
2160 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2161 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2162 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2163 || *reloc_type
== BFD_RELOC_MIPS_REL16
2164 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2165 fixp
[0]->fx_no_overflow
= 1;
2169 struct mips_hi_fixup
*hi_fixup
;
2171 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2172 hi_fixup
= ((struct mips_hi_fixup
*)
2173 xmalloc (sizeof (struct mips_hi_fixup
)));
2174 hi_fixup
->fixp
= fixp
[0];
2175 hi_fixup
->seg
= now_seg
;
2176 hi_fixup
->next
= mips_hi_fixup_list
;
2177 mips_hi_fixup_list
= hi_fixup
;
2180 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2182 /* FIXME: This symbol can be one of
2183 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2184 address_expr
->X_op
= O_absent
;
2185 address_expr
->X_add_symbol
= 0;
2186 address_expr
->X_add_number
= 0;
2188 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2189 4, address_expr
, FALSE
,
2192 /* These relocations can have an addend that won't fit in
2193 4 octets for 64bit assembly. */
2194 if (HAVE_64BIT_GPRS
&&
2195 (*reloc_type
== BFD_RELOC_16
2196 || *reloc_type
== BFD_RELOC_32
2197 || *reloc_type
== BFD_RELOC_MIPS_JMP
2198 || *reloc_type
== BFD_RELOC_HI16_S
2199 || *reloc_type
== BFD_RELOC_LO16
2200 || *reloc_type
== BFD_RELOC_GPREL16
2201 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2202 || *reloc_type
== BFD_RELOC_GPREL32
2203 || *reloc_type
== BFD_RELOC_64
2204 || *reloc_type
== BFD_RELOC_CTOR
2205 || *reloc_type
== BFD_RELOC_MIPS_SUB
2206 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2207 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2208 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2209 || *reloc_type
== BFD_RELOC_MIPS_REL16
2210 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2211 fixp
[1]->fx_no_overflow
= 1;
2213 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2215 address_expr
->X_op
= O_absent
;
2216 address_expr
->X_add_symbol
= 0;
2217 address_expr
->X_add_number
= 0;
2219 fixp
[2] = fix_new_exp (frag_now
,
2220 f
- frag_now
->fr_literal
, 4,
2221 address_expr
, FALSE
,
2224 /* These relocations can have an addend that won't fit in
2225 4 octets for 64bit assembly. */
2226 if (HAVE_64BIT_GPRS
&&
2227 (*reloc_type
== BFD_RELOC_16
2228 || *reloc_type
== BFD_RELOC_32
2229 || *reloc_type
== BFD_RELOC_MIPS_JMP
2230 || *reloc_type
== BFD_RELOC_HI16_S
2231 || *reloc_type
== BFD_RELOC_LO16
2232 || *reloc_type
== BFD_RELOC_GPREL16
2233 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2234 || *reloc_type
== BFD_RELOC_GPREL32
2235 || *reloc_type
== BFD_RELOC_64
2236 || *reloc_type
== BFD_RELOC_CTOR
2237 || *reloc_type
== BFD_RELOC_MIPS_SUB
2238 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2239 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2240 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2241 || *reloc_type
== BFD_RELOC_MIPS_REL16
2242 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2243 fixp
[2]->fx_no_overflow
= 1;
2250 if (! mips_opts
.mips16
)
2252 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2254 dwarf2_emit_insn (4);
2257 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2259 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2260 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2262 dwarf2_emit_insn (4);
2269 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2272 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2274 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2278 /* Update the register mask information. */
2279 if (! mips_opts
.mips16
)
2281 if (pinfo
& INSN_WRITE_GPR_D
)
2282 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2283 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2284 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2285 if (pinfo
& INSN_READ_GPR_S
)
2286 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2287 if (pinfo
& INSN_WRITE_GPR_31
)
2288 mips_gprmask
|= 1 << RA
;
2289 if (pinfo
& INSN_WRITE_FPR_D
)
2290 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2291 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2292 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2293 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2294 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2295 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2296 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2297 if (pinfo
& INSN_COP
)
2299 /* We don't keep enough information to sort these cases out.
2300 The itbl support does keep this information however, although
2301 we currently don't support itbl fprmats as part of the cop
2302 instruction. May want to add this support in the future. */
2304 /* Never set the bit for $0, which is always zero. */
2305 mips_gprmask
&= ~1 << 0;
2309 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2310 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2311 & MIPS16OP_MASK_RX
);
2312 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2313 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2314 & MIPS16OP_MASK_RY
);
2315 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2316 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2317 & MIPS16OP_MASK_RZ
);
2318 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2319 mips_gprmask
|= 1 << TREG
;
2320 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2321 mips_gprmask
|= 1 << SP
;
2322 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2323 mips_gprmask
|= 1 << RA
;
2324 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2325 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2326 if (pinfo
& MIPS16_INSN_READ_Z
)
2327 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2328 & MIPS16OP_MASK_MOVE32Z
);
2329 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2330 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2331 & MIPS16OP_MASK_REGR32
);
2334 if (place
== NULL
&& ! mips_opts
.noreorder
)
2336 /* Filling the branch delay slot is more complex. We try to
2337 switch the branch with the previous instruction, which we can
2338 do if the previous instruction does not set up a condition
2339 that the branch tests and if the branch is not itself the
2340 target of any branch. */
2341 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2342 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2344 if (mips_optimize
< 2
2345 /* If we have seen .set volatile or .set nomove, don't
2347 || mips_opts
.nomove
!= 0
2348 /* If we had to emit any NOP instructions, then we
2349 already know we can not swap. */
2351 /* If we don't even know the previous insn, we can not
2353 || ! prev_insn_valid
2354 /* If the previous insn is already in a branch delay
2355 slot, then we can not swap. */
2356 || prev_insn_is_delay_slot
2357 /* If the previous previous insn was in a .set
2358 noreorder, we can't swap. Actually, the MIPS
2359 assembler will swap in this situation. However, gcc
2360 configured -with-gnu-as will generate code like
2366 in which we can not swap the bne and INSN. If gcc is
2367 not configured -with-gnu-as, it does not output the
2368 .set pseudo-ops. We don't have to check
2369 prev_insn_unreordered, because prev_insn_valid will
2370 be 0 in that case. We don't want to use
2371 prev_prev_insn_valid, because we do want to be able
2372 to swap at the start of a function. */
2373 || prev_prev_insn_unreordered
2374 /* If the branch is itself the target of a branch, we
2375 can not swap. We cheat on this; all we check for is
2376 whether there is a label on this instruction. If
2377 there are any branches to anything other than a
2378 label, users must use .set noreorder. */
2379 || insn_labels
!= NULL
2380 /* If the previous instruction is in a variant frag, we
2381 can not do the swap. This does not apply to the
2382 mips16, which uses variant frags for different
2384 || (! mips_opts
.mips16
2385 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2386 /* If the branch reads the condition codes, we don't
2387 even try to swap, because in the sequence
2392 we can not swap, and I don't feel like handling that
2394 || (! mips_opts
.mips16
2395 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2396 && (pinfo
& INSN_READ_COND_CODE
))
2397 /* We can not swap with an instruction that requires a
2398 delay slot, becase the target of the branch might
2399 interfere with that instruction. */
2400 || (! mips_opts
.mips16
2401 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2403 /* Itbl support may require additional care here. */
2404 & (INSN_LOAD_COPROC_DELAY
2405 | INSN_COPROC_MOVE_DELAY
2406 | INSN_WRITE_COND_CODE
)))
2407 || (! (hilo_interlocks
2408 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2412 || (! mips_opts
.mips16
2414 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2415 || (! mips_opts
.mips16
2416 && mips_opts
.isa
== ISA_MIPS1
2417 /* Itbl support may require additional care here. */
2418 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2419 /* We can not swap with a branch instruction. */
2421 & (INSN_UNCOND_BRANCH_DELAY
2422 | INSN_COND_BRANCH_DELAY
2423 | INSN_COND_BRANCH_LIKELY
))
2424 /* We do not swap with a trap instruction, since it
2425 complicates trap handlers to have the trap
2426 instruction be in a delay slot. */
2427 || (prev_pinfo
& INSN_TRAP
)
2428 /* If the branch reads a register that the previous
2429 instruction sets, we can not swap. */
2430 || (! mips_opts
.mips16
2431 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2432 && insn_uses_reg (ip
,
2433 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2436 || (! mips_opts
.mips16
2437 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2438 && insn_uses_reg (ip
,
2439 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2442 || (mips_opts
.mips16
2443 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2444 && insn_uses_reg (ip
,
2445 ((prev_insn
.insn_opcode
2447 & MIPS16OP_MASK_RX
),
2449 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2450 && insn_uses_reg (ip
,
2451 ((prev_insn
.insn_opcode
2453 & MIPS16OP_MASK_RY
),
2455 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2456 && insn_uses_reg (ip
,
2457 ((prev_insn
.insn_opcode
2459 & MIPS16OP_MASK_RZ
),
2461 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2462 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2463 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2464 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2465 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2466 && insn_uses_reg (ip
,
2467 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2470 /* If the branch writes a register that the previous
2471 instruction sets, we can not swap (we know that
2472 branches write only to RD or to $31). */
2473 || (! mips_opts
.mips16
2474 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2475 && (((pinfo
& INSN_WRITE_GPR_D
)
2476 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2477 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2478 || ((pinfo
& INSN_WRITE_GPR_31
)
2479 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2482 || (! mips_opts
.mips16
2483 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2484 && (((pinfo
& INSN_WRITE_GPR_D
)
2485 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2486 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2487 || ((pinfo
& INSN_WRITE_GPR_31
)
2488 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2491 || (mips_opts
.mips16
2492 && (pinfo
& MIPS16_INSN_WRITE_31
)
2493 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2494 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2495 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2497 /* If the branch writes a register that the previous
2498 instruction reads, we can not swap (we know that
2499 branches only write to RD or to $31). */
2500 || (! mips_opts
.mips16
2501 && (pinfo
& INSN_WRITE_GPR_D
)
2502 && insn_uses_reg (&prev_insn
,
2503 ((ip
->insn_opcode
>> OP_SH_RD
)
2506 || (! mips_opts
.mips16
2507 && (pinfo
& INSN_WRITE_GPR_31
)
2508 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2509 || (mips_opts
.mips16
2510 && (pinfo
& MIPS16_INSN_WRITE_31
)
2511 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2512 /* If we are generating embedded PIC code, the branch
2513 might be expanded into a sequence which uses $at, so
2514 we can't swap with an instruction which reads it. */
2515 || (mips_pic
== EMBEDDED_PIC
2516 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2517 /* If the previous previous instruction has a load
2518 delay, and sets a register that the branch reads, we
2520 || (! mips_opts
.mips16
2521 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2522 /* Itbl support may require additional care here. */
2523 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2524 || (! gpr_interlocks
2525 && (prev_prev_insn
.insn_mo
->pinfo
2526 & INSN_LOAD_MEMORY_DELAY
)))
2527 && insn_uses_reg (ip
,
2528 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2531 /* If one instruction sets a condition code and the
2532 other one uses a condition code, we can not swap. */
2533 || ((pinfo
& INSN_READ_COND_CODE
)
2534 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2535 || ((pinfo
& INSN_WRITE_COND_CODE
)
2536 && (prev_pinfo
& INSN_READ_COND_CODE
))
2537 /* If the previous instruction uses the PC, we can not
2539 || (mips_opts
.mips16
2540 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2541 /* If the previous instruction was extended, we can not
2543 || (mips_opts
.mips16
&& prev_insn_extended
)
2544 /* If the previous instruction had a fixup in mips16
2545 mode, we can not swap. This normally means that the
2546 previous instruction was a 4 byte branch anyhow. */
2547 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2548 /* If the previous instruction is a sync, sync.l, or
2549 sync.p, we can not swap. */
2550 || (prev_pinfo
& INSN_SYNC
))
2552 /* We could do even better for unconditional branches to
2553 portions of this object file; we could pick up the
2554 instruction at the destination, put it in the delay
2555 slot, and bump the destination address. */
2557 /* Update the previous insn information. */
2558 prev_prev_insn
= *ip
;
2559 prev_insn
.insn_mo
= &dummy_opcode
;
2563 /* It looks like we can actually do the swap. */
2564 if (! mips_opts
.mips16
)
2569 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2570 memcpy (temp
, prev_f
, 4);
2571 memcpy (prev_f
, f
, 4);
2572 memcpy (f
, temp
, 4);
2573 if (prev_insn_fixp
[0])
2575 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2576 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2578 if (prev_insn_fixp
[1])
2580 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2581 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2583 if (prev_insn_fixp
[2])
2585 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2586 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2590 fixp
[0]->fx_frag
= prev_insn_frag
;
2591 fixp
[0]->fx_where
= prev_insn_where
;
2595 fixp
[1]->fx_frag
= prev_insn_frag
;
2596 fixp
[1]->fx_where
= prev_insn_where
;
2600 fixp
[2]->fx_frag
= prev_insn_frag
;
2601 fixp
[2]->fx_where
= prev_insn_where
;
2609 assert (prev_insn_fixp
[0] == NULL
);
2610 assert (prev_insn_fixp
[1] == NULL
);
2611 assert (prev_insn_fixp
[2] == NULL
);
2612 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2613 memcpy (temp
, prev_f
, 2);
2614 memcpy (prev_f
, f
, 2);
2615 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2617 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2618 memcpy (f
, temp
, 2);
2622 memcpy (f
, f
+ 2, 2);
2623 memcpy (f
+ 2, temp
, 2);
2627 fixp
[0]->fx_frag
= prev_insn_frag
;
2628 fixp
[0]->fx_where
= prev_insn_where
;
2632 fixp
[1]->fx_frag
= prev_insn_frag
;
2633 fixp
[1]->fx_where
= prev_insn_where
;
2637 fixp
[2]->fx_frag
= prev_insn_frag
;
2638 fixp
[2]->fx_where
= prev_insn_where
;
2642 /* Update the previous insn information; leave prev_insn
2644 prev_prev_insn
= *ip
;
2646 prev_insn_is_delay_slot
= 1;
2648 /* If that was an unconditional branch, forget the previous
2649 insn information. */
2650 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2652 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2653 prev_insn
.insn_mo
= &dummy_opcode
;
2656 prev_insn_fixp
[0] = NULL
;
2657 prev_insn_fixp
[1] = NULL
;
2658 prev_insn_fixp
[2] = NULL
;
2659 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2660 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2661 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2662 prev_insn_extended
= 0;
2664 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2666 /* We don't yet optimize a branch likely. What we should do
2667 is look at the target, copy the instruction found there
2668 into the delay slot, and increment the branch to jump to
2669 the next instruction. */
2671 /* Update the previous insn information. */
2672 prev_prev_insn
= *ip
;
2673 prev_insn
.insn_mo
= &dummy_opcode
;
2674 prev_insn_fixp
[0] = NULL
;
2675 prev_insn_fixp
[1] = NULL
;
2676 prev_insn_fixp
[2] = NULL
;
2677 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2678 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2679 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2680 prev_insn_extended
= 0;
2684 /* Update the previous insn information. */
2686 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2688 prev_prev_insn
= prev_insn
;
2691 /* Any time we see a branch, we always fill the delay slot
2692 immediately; since this insn is not a branch, we know it
2693 is not in a delay slot. */
2694 prev_insn_is_delay_slot
= 0;
2696 prev_insn_fixp
[0] = fixp
[0];
2697 prev_insn_fixp
[1] = fixp
[1];
2698 prev_insn_fixp
[2] = fixp
[2];
2699 prev_insn_reloc_type
[0] = reloc_type
[0];
2700 prev_insn_reloc_type
[1] = reloc_type
[1];
2701 prev_insn_reloc_type
[2] = reloc_type
[2];
2702 if (mips_opts
.mips16
)
2703 prev_insn_extended
= (ip
->use_extend
2704 || *reloc_type
> BFD_RELOC_UNUSED
);
2707 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2708 prev_insn_unreordered
= 0;
2709 prev_insn_frag
= frag_now
;
2710 prev_insn_where
= f
- frag_now
->fr_literal
;
2711 prev_insn_valid
= 1;
2713 else if (place
== NULL
)
2715 /* We need to record a bit of information even when we are not
2716 reordering, in order to determine the base address for mips16
2717 PC relative relocs. */
2718 prev_prev_insn
= prev_insn
;
2720 prev_insn_reloc_type
[0] = reloc_type
[0];
2721 prev_insn_reloc_type
[1] = reloc_type
[1];
2722 prev_insn_reloc_type
[2] = reloc_type
[2];
2723 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2724 prev_insn_unreordered
= 1;
2727 /* We just output an insn, so the next one doesn't have a label. */
2728 mips_clear_insn_labels ();
2730 /* We must ensure that a fixup associated with an unmatched %hi
2731 reloc does not become a variant frag. Otherwise, the
2732 rearrangement of %hi relocs in frob_file may confuse
2736 frag_wane (frag_now
);
2741 /* This function forgets that there was any previous instruction or
2742 label. If PRESERVE is non-zero, it remembers enough information to
2743 know whether nops are needed before a noreorder section. */
2746 mips_no_prev_insn (preserve
)
2751 prev_insn
.insn_mo
= &dummy_opcode
;
2752 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2753 prev_nop_frag
= NULL
;
2754 prev_nop_frag_holds
= 0;
2755 prev_nop_frag_required
= 0;
2756 prev_nop_frag_since
= 0;
2758 prev_insn_valid
= 0;
2759 prev_insn_is_delay_slot
= 0;
2760 prev_insn_unreordered
= 0;
2761 prev_insn_extended
= 0;
2762 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2763 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2764 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2765 prev_prev_insn_unreordered
= 0;
2766 mips_clear_insn_labels ();
2769 /* This function must be called whenever we turn on noreorder or emit
2770 something other than instructions. It inserts any NOPS which might
2771 be needed by the previous instruction, and clears the information
2772 kept for the previous instructions. The INSNS parameter is true if
2773 instructions are to follow. */
2776 mips_emit_delays (insns
)
2779 if (! mips_opts
.noreorder
)
2784 if ((! mips_opts
.mips16
2785 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2786 && (! cop_interlocks
2787 && (prev_insn
.insn_mo
->pinfo
2788 & (INSN_LOAD_COPROC_DELAY
2789 | INSN_COPROC_MOVE_DELAY
2790 | INSN_WRITE_COND_CODE
))))
2791 || (! hilo_interlocks
2792 && (prev_insn
.insn_mo
->pinfo
2795 || (! mips_opts
.mips16
2797 && (prev_insn
.insn_mo
->pinfo
2798 & INSN_LOAD_MEMORY_DELAY
))
2799 || (! mips_opts
.mips16
2800 && mips_opts
.isa
== ISA_MIPS1
2801 && (prev_insn
.insn_mo
->pinfo
2802 & INSN_COPROC_MEMORY_DELAY
)))
2804 /* Itbl support may require additional care here. */
2806 if ((! mips_opts
.mips16
2807 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2808 && (! cop_interlocks
2809 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2810 || (! hilo_interlocks
2811 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2812 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2815 if (prev_insn_unreordered
)
2818 else if ((! mips_opts
.mips16
2819 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2820 && (! cop_interlocks
2821 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2822 || (! hilo_interlocks
2823 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2824 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2826 /* Itbl support may require additional care here. */
2827 if (! prev_prev_insn_unreordered
)
2831 if (mips_fix_4122_bugs
&& prev_insn
.insn_mo
->name
)
2834 const char *pn
= prev_insn
.insn_mo
->name
;
2835 if (strncmp(pn
, "macc", 4) == 0
2836 || strncmp(pn
, "dmacc", 5) == 0
2837 || strncmp(pn
, "dmult", 5) == 0)
2841 if (nops
< min_nops
)
2847 struct insn_label_list
*l
;
2851 /* Record the frag which holds the nop instructions, so
2852 that we can remove them if we don't need them. */
2853 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2854 prev_nop_frag
= frag_now
;
2855 prev_nop_frag_holds
= nops
;
2856 prev_nop_frag_required
= 0;
2857 prev_nop_frag_since
= 0;
2860 for (; nops
> 0; --nops
)
2865 /* Move on to a new frag, so that it is safe to simply
2866 decrease the size of prev_nop_frag. */
2867 frag_wane (frag_now
);
2871 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2875 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2876 symbol_set_frag (l
->label
, frag_now
);
2877 val
= (valueT
) frag_now_fix ();
2878 /* mips16 text labels are stored as odd. */
2879 if (mips_opts
.mips16
)
2881 S_SET_VALUE (l
->label
, val
);
2886 /* Mark instruction labels in mips16 mode. */
2888 mips16_mark_labels ();
2890 mips_no_prev_insn (insns
);
2893 /* Build an instruction created by a macro expansion. This is passed
2894 a pointer to the count of instructions created so far, an
2895 expression, the name of the instruction to build, an operand format
2896 string, and corresponding arguments. */
2900 macro_build (char *place
,
2908 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2917 struct mips_cl_insn insn
;
2918 bfd_reloc_code_real_type r
[3];
2922 va_start (args
, fmt
);
2928 * If the macro is about to expand into a second instruction,
2929 * print a warning if needed. We need to pass ip as a parameter
2930 * to generate a better warning message here...
2932 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2933 as_warn (_("Macro instruction expanded into multiple instructions"));
2936 * If the macro is about to expand into a second instruction,
2937 * and it is in a delay slot, print a warning.
2941 && mips_opts
.noreorder
2942 && (prev_prev_insn
.insn_mo
->pinfo
2943 & (INSN_UNCOND_BRANCH_DELAY
| INSN_COND_BRANCH_DELAY
2944 | INSN_COND_BRANCH_LIKELY
)) != 0)
2945 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2948 ++*counter
; /* bump instruction counter */
2950 if (mips_opts
.mips16
)
2952 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2957 r
[0] = BFD_RELOC_UNUSED
;
2958 r
[1] = BFD_RELOC_UNUSED
;
2959 r
[2] = BFD_RELOC_UNUSED
;
2960 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2961 assert (insn
.insn_mo
);
2962 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2964 /* Search until we get a match for NAME. */
2967 /* It is assumed here that macros will never generate
2968 MDMX or MIPS-3D instructions. */
2969 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2970 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2971 && OPCODE_IS_MEMBER (insn
.insn_mo
,
2973 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2975 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2979 assert (insn
.insn_mo
->name
);
2980 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2983 insn
.insn_opcode
= insn
.insn_mo
->match
;
2999 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3003 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3008 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3013 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3018 int tmp
= va_arg (args
, int);
3020 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3021 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3027 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3034 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3038 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3042 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3046 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3050 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3057 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3063 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3064 assert (*r
== BFD_RELOC_GPREL16
3065 || *r
== BFD_RELOC_MIPS_LITERAL
3066 || *r
== BFD_RELOC_MIPS_HIGHER
3067 || *r
== BFD_RELOC_HI16_S
3068 || *r
== BFD_RELOC_LO16
3069 || *r
== BFD_RELOC_MIPS_GOT16
3070 || *r
== BFD_RELOC_MIPS_CALL16
3071 || *r
== BFD_RELOC_MIPS_GOT_DISP
3072 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3073 || *r
== BFD_RELOC_MIPS_GOT_OFST
3074 || *r
== BFD_RELOC_MIPS_GOT_LO16
3075 || *r
== BFD_RELOC_MIPS_CALL_LO16
3076 || (ep
->X_op
== O_subtract
3077 && *r
== BFD_RELOC_PCREL_LO16
));
3081 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3083 && (ep
->X_op
== O_constant
3084 || (ep
->X_op
== O_symbol
3085 && (*r
== BFD_RELOC_MIPS_HIGHEST
3086 || *r
== BFD_RELOC_HI16_S
3087 || *r
== BFD_RELOC_HI16
3088 || *r
== BFD_RELOC_GPREL16
3089 || *r
== BFD_RELOC_MIPS_GOT_HI16
3090 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3091 || (ep
->X_op
== O_subtract
3092 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3096 assert (ep
!= NULL
);
3098 * This allows macro() to pass an immediate expression for
3099 * creating short branches without creating a symbol.
3100 * Note that the expression still might come from the assembly
3101 * input, in which case the value is not checked for range nor
3102 * is a relocation entry generated (yuck).
3104 if (ep
->X_op
== O_constant
)
3106 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3110 *r
= BFD_RELOC_16_PCREL_S2
;
3114 assert (ep
!= NULL
);
3115 *r
= BFD_RELOC_MIPS_JMP
;
3119 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3128 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3130 append_insn (place
, &insn
, ep
, r
, FALSE
);
3134 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3136 int *counter ATTRIBUTE_UNUSED
;
3142 struct mips_cl_insn insn
;
3143 bfd_reloc_code_real_type r
[3]
3144 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3146 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3147 assert (insn
.insn_mo
);
3148 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3150 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3151 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3154 assert (insn
.insn_mo
->name
);
3155 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3158 insn
.insn_opcode
= insn
.insn_mo
->match
;
3159 insn
.use_extend
= FALSE
;
3178 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3183 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3187 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3191 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3201 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3208 regno
= va_arg (args
, int);
3209 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3210 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3231 assert (ep
!= NULL
);
3233 if (ep
->X_op
!= O_constant
)
3234 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3237 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3238 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3241 *r
= BFD_RELOC_UNUSED
;
3247 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3254 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3256 append_insn (place
, &insn
, ep
, r
, FALSE
);
3260 * Generate a "jalr" instruction with a relocation hint to the called
3261 * function. This occurs in NewABI PIC code.
3264 macro_build_jalr (icnt
, ep
)
3275 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
3278 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3279 0, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3283 * Generate a "lui" instruction.
3286 macro_build_lui (place
, counter
, ep
, regnum
)
3292 expressionS high_expr
;
3293 struct mips_cl_insn insn
;
3294 bfd_reloc_code_real_type r
[3]
3295 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3296 const char *name
= "lui";
3297 const char *fmt
= "t,u";
3299 assert (! mips_opts
.mips16
);
3305 high_expr
.X_op
= O_constant
;
3306 high_expr
.X_add_number
= ep
->X_add_number
;
3309 if (high_expr
.X_op
== O_constant
)
3311 /* we can compute the instruction now without a relocation entry */
3312 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3314 *r
= BFD_RELOC_UNUSED
;
3318 assert (ep
->X_op
== O_symbol
);
3319 /* _gp_disp is a special case, used from s_cpload. */
3320 assert (mips_pic
== NO_PIC
3322 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3323 *r
= BFD_RELOC_HI16_S
;
3327 * If the macro is about to expand into a second instruction,
3328 * print a warning if needed. We need to pass ip as a parameter
3329 * to generate a better warning message here...
3331 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3332 as_warn (_("Macro instruction expanded into multiple instructions"));
3335 ++*counter
; /* bump instruction counter */
3337 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3338 assert (insn
.insn_mo
);
3339 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3340 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3342 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3343 if (*r
== BFD_RELOC_UNUSED
)
3345 insn
.insn_opcode
|= high_expr
.X_add_number
;
3346 append_insn (place
, &insn
, NULL
, r
, FALSE
);
3349 append_insn (place
, &insn
, &high_expr
, r
, FALSE
);
3352 /* Generate a sequence of instructions to do a load or store from a constant
3353 offset off of a base register (breg) into/from a target register (treg),
3354 using AT if necessary. */
3356 macro_build_ldst_constoffset (place
, counter
, ep
, op
, treg
, breg
)
3363 assert (ep
->X_op
== O_constant
);
3365 /* Right now, this routine can only handle signed 32-bit contants. */
3366 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
))
3367 as_warn (_("operand overflow"));
3369 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3371 /* Signed 16-bit offset will fit in the op. Easy! */
3372 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3373 (int) BFD_RELOC_LO16
, breg
);
3377 /* 32-bit offset, need multiple instructions and AT, like:
3378 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3379 addu $tempreg,$tempreg,$breg
3380 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3381 to handle the complete offset. */
3382 macro_build_lui (place
, counter
, ep
, AT
);
3385 macro_build (place
, counter
, (expressionS
*) NULL
,
3386 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
3387 "d,v,t", AT
, AT
, breg
);
3390 macro_build (place
, counter
, ep
, op
, "t,o(b)", treg
,
3391 (int) BFD_RELOC_LO16
, AT
);
3394 as_warn (_("Macro used $at after \".set noat\""));
3399 * Generates code to set the $at register to true (one)
3400 * if reg is less than the immediate expression.
3403 set_at (counter
, reg
, unsignedp
)
3408 if (imm_expr
.X_op
== O_constant
3409 && imm_expr
.X_add_number
>= -0x8000
3410 && imm_expr
.X_add_number
< 0x8000)
3411 macro_build ((char *) NULL
, counter
, &imm_expr
,
3412 unsignedp
? "sltiu" : "slti",
3413 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3416 load_register (counter
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3417 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3418 unsignedp
? "sltu" : "slt",
3419 "d,v,t", AT
, reg
, AT
);
3423 /* Warn if an expression is not a constant. */
3426 check_absolute_expr (ip
, ex
)
3427 struct mips_cl_insn
*ip
;
3430 if (ex
->X_op
== O_big
)
3431 as_bad (_("unsupported large constant"));
3432 else if (ex
->X_op
!= O_constant
)
3433 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3436 /* Count the leading zeroes by performing a binary chop. This is a
3437 bulky bit of source, but performance is a LOT better for the
3438 majority of values than a simple loop to count the bits:
3439 for (lcnt = 0; (lcnt < 32); lcnt++)
3440 if ((v) & (1 << (31 - lcnt)))
3442 However it is not code size friendly, and the gain will drop a bit
3443 on certain cached systems.
3445 #define COUNT_TOP_ZEROES(v) \
3446 (((v) & ~0xffff) == 0 \
3447 ? ((v) & ~0xff) == 0 \
3448 ? ((v) & ~0xf) == 0 \
3449 ? ((v) & ~0x3) == 0 \
3450 ? ((v) & ~0x1) == 0 \
3455 : ((v) & ~0x7) == 0 \
3458 : ((v) & ~0x3f) == 0 \
3459 ? ((v) & ~0x1f) == 0 \
3462 : ((v) & ~0x7f) == 0 \
3465 : ((v) & ~0xfff) == 0 \
3466 ? ((v) & ~0x3ff) == 0 \
3467 ? ((v) & ~0x1ff) == 0 \
3470 : ((v) & ~0x7ff) == 0 \
3473 : ((v) & ~0x3fff) == 0 \
3474 ? ((v) & ~0x1fff) == 0 \
3477 : ((v) & ~0x7fff) == 0 \
3480 : ((v) & ~0xffffff) == 0 \
3481 ? ((v) & ~0xfffff) == 0 \
3482 ? ((v) & ~0x3ffff) == 0 \
3483 ? ((v) & ~0x1ffff) == 0 \
3486 : ((v) & ~0x7ffff) == 0 \
3489 : ((v) & ~0x3fffff) == 0 \
3490 ? ((v) & ~0x1fffff) == 0 \
3493 : ((v) & ~0x7fffff) == 0 \
3496 : ((v) & ~0xfffffff) == 0 \
3497 ? ((v) & ~0x3ffffff) == 0 \
3498 ? ((v) & ~0x1ffffff) == 0 \
3501 : ((v) & ~0x7ffffff) == 0 \
3504 : ((v) & ~0x3fffffff) == 0 \
3505 ? ((v) & ~0x1fffffff) == 0 \
3508 : ((v) & ~0x7fffffff) == 0 \
3513 * This routine generates the least number of instructions neccessary to load
3514 * an absolute expression value into a register.
3517 load_register (counter
, reg
, ep
, dbl
)
3524 expressionS hi32
, lo32
;
3526 if (ep
->X_op
!= O_big
)
3528 assert (ep
->X_op
== O_constant
);
3529 if (ep
->X_add_number
< 0x8000
3530 && (ep
->X_add_number
>= 0
3531 || (ep
->X_add_number
>= -0x8000
3534 || sizeof (ep
->X_add_number
) > 4))))
3536 /* We can handle 16 bit signed values with an addiu to
3537 $zero. No need to ever use daddiu here, since $zero and
3538 the result are always correct in 32 bit mode. */
3539 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3540 (int) BFD_RELOC_LO16
);
3543 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3545 /* We can handle 16 bit unsigned values with an ori to
3547 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3548 (int) BFD_RELOC_LO16
);
3551 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)
3554 || sizeof (ep
->X_add_number
) > 4
3555 || (ep
->X_add_number
& 0x80000000) == 0))
3556 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3557 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3560 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3561 == ~ (offsetT
) 0xffffffff)))
3563 /* 32 bit values require an lui. */
3564 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3565 (int) BFD_RELOC_HI16
);
3566 if ((ep
->X_add_number
& 0xffff) != 0)
3567 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3568 (int) BFD_RELOC_LO16
);
3573 /* The value is larger than 32 bits. */
3575 if (HAVE_32BIT_GPRS
)
3577 as_bad (_("Number (0x%lx) larger than 32 bits"),
3578 (unsigned long) ep
->X_add_number
);
3579 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3580 (int) BFD_RELOC_LO16
);
3584 if (ep
->X_op
!= O_big
)
3587 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3588 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3589 hi32
.X_add_number
&= 0xffffffff;
3591 lo32
.X_add_number
&= 0xffffffff;
3595 assert (ep
->X_add_number
> 2);
3596 if (ep
->X_add_number
== 3)
3597 generic_bignum
[3] = 0;
3598 else if (ep
->X_add_number
> 4)
3599 as_bad (_("Number larger than 64 bits"));
3600 lo32
.X_op
= O_constant
;
3601 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3602 hi32
.X_op
= O_constant
;
3603 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3606 if (hi32
.X_add_number
== 0)
3611 unsigned long hi
, lo
;
3613 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3615 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3617 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3618 reg
, 0, (int) BFD_RELOC_LO16
);
3621 if (lo32
.X_add_number
& 0x80000000)
3623 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3624 (int) BFD_RELOC_HI16
);
3625 if (lo32
.X_add_number
& 0xffff)
3626 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3627 reg
, reg
, (int) BFD_RELOC_LO16
);
3632 /* Check for 16bit shifted constant. We know that hi32 is
3633 non-zero, so start the mask on the first bit of the hi32
3638 unsigned long himask
, lomask
;
3642 himask
= 0xffff >> (32 - shift
);
3643 lomask
= (0xffff << shift
) & 0xffffffff;
3647 himask
= 0xffff << (shift
- 32);
3650 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3651 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3655 tmp
.X_op
= O_constant
;
3657 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3658 | (lo32
.X_add_number
>> shift
));
3660 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3661 macro_build ((char *) NULL
, counter
, &tmp
,
3662 "ori", "t,r,i", reg
, 0,
3663 (int) BFD_RELOC_LO16
);
3664 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3665 (shift
>= 32) ? "dsll32" : "dsll",
3667 (shift
>= 32) ? shift
- 32 : shift
);
3672 while (shift
<= (64 - 16));
3674 /* Find the bit number of the lowest one bit, and store the
3675 shifted value in hi/lo. */
3676 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3677 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3681 while ((lo
& 1) == 0)
3686 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3692 while ((hi
& 1) == 0)
3701 /* Optimize if the shifted value is a (power of 2) - 1. */
3702 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3703 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3705 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3710 /* This instruction will set the register to be all
3712 tmp
.X_op
= O_constant
;
3713 tmp
.X_add_number
= (offsetT
) -1;
3714 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3715 reg
, 0, (int) BFD_RELOC_LO16
);
3719 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3720 (bit
>= 32) ? "dsll32" : "dsll",
3722 (bit
>= 32) ? bit
- 32 : bit
);
3724 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3725 (shift
>= 32) ? "dsrl32" : "dsrl",
3727 (shift
>= 32) ? shift
- 32 : shift
);
3732 /* Sign extend hi32 before calling load_register, because we can
3733 generally get better code when we load a sign extended value. */
3734 if ((hi32
.X_add_number
& 0x80000000) != 0)
3735 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3736 load_register (counter
, reg
, &hi32
, 0);
3739 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3743 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3744 "dsll32", "d,w,<", reg
, freg
, 0);
3752 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3754 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3755 (int) BFD_RELOC_HI16
);
3756 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3757 "dsrl32", "d,w,<", reg
, reg
, 0);
3763 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3764 "d,w,<", reg
, freg
, 16);
3768 mid16
.X_add_number
>>= 16;
3769 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3770 freg
, (int) BFD_RELOC_LO16
);
3771 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3772 "d,w,<", reg
, reg
, 16);
3775 if ((lo32
.X_add_number
& 0xffff) != 0)
3776 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3777 (int) BFD_RELOC_LO16
);
3780 /* Load an address into a register. */
3783 load_address (counter
, reg
, ep
, used_at
)
3791 if (ep
->X_op
!= O_constant
3792 && ep
->X_op
!= O_symbol
)
3794 as_bad (_("expression too complex"));
3795 ep
->X_op
= O_constant
;
3798 if (ep
->X_op
== O_constant
)
3800 load_register (counter
, reg
, ep
, HAVE_64BIT_ADDRESSES
);
3804 if (mips_pic
== NO_PIC
)
3806 /* If this is a reference to a GP relative symbol, we want
3807 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3809 lui $reg,<sym> (BFD_RELOC_HI16_S)
3810 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3811 If we have an addend, we always use the latter form.
3813 With 64bit address space and a usable $at we want
3814 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3815 lui $at,<sym> (BFD_RELOC_HI16_S)
3816 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3817 daddiu $at,<sym> (BFD_RELOC_LO16)
3821 If $at is already in use, we use a path which is suboptimal
3822 on superscalar processors.
3823 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3824 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3826 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3828 daddiu $reg,<sym> (BFD_RELOC_LO16)
3830 if (HAVE_64BIT_ADDRESSES
)
3832 /* We don't do GP optimization for now because RELAX_ENCODE can't
3833 hold the data for such large chunks. */
3835 if (*used_at
== 0 && ! mips_opts
.noat
)
3837 macro_build (p
, counter
, ep
, "lui", "t,u",
3838 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3839 macro_build (p
, counter
, ep
, "lui", "t,u",
3840 AT
, (int) BFD_RELOC_HI16_S
);
3841 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3842 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3843 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3844 AT
, AT
, (int) BFD_RELOC_LO16
);
3845 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3846 "d,w,<", reg
, reg
, 0);
3847 macro_build (p
, counter
, (expressionS
*) NULL
, "daddu",
3848 "d,v,t", reg
, reg
, AT
);
3853 macro_build (p
, counter
, ep
, "lui", "t,u",
3854 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3855 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3856 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3857 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3858 "d,w,<", reg
, reg
, 16);
3859 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3860 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3861 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3862 "d,w,<", reg
, reg
, 16);
3863 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3864 reg
, reg
, (int) BFD_RELOC_LO16
);
3869 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3870 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3873 macro_build ((char *) NULL
, counter
, ep
,
3874 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3875 reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
3876 p
= frag_var (rs_machine_dependent
, 8, 0,
3877 RELAX_ENCODE (4, 8, 0, 4, 0,
3878 mips_opts
.warn_about_macros
),
3879 ep
->X_add_symbol
, 0, NULL
);
3881 macro_build_lui (p
, counter
, ep
, reg
);
3884 macro_build (p
, counter
, ep
,
3885 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3886 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3889 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3893 /* If this is a reference to an external symbol, we want
3894 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3896 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3898 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3899 If we have NewABI, we want
3900 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3901 If there is a constant, it must be added in after. */
3902 ex
.X_add_number
= ep
->X_add_number
;
3903 ep
->X_add_number
= 0;
3907 macro_build ((char *) NULL
, counter
, ep
,
3908 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3909 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3913 macro_build ((char *) NULL
, counter
, ep
,
3914 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
3915 reg
, (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3916 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3917 p
= frag_var (rs_machine_dependent
, 4, 0,
3918 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3919 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3920 macro_build (p
, counter
, ep
,
3921 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3922 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3925 if (ex
.X_add_number
!= 0)
3927 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3928 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3929 ex
.X_op
= O_constant
;
3930 macro_build ((char *) NULL
, counter
, &ex
,
3931 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3932 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3935 else if (mips_pic
== SVR4_PIC
)
3940 /* This is the large GOT case. If this is a reference to an
3941 external symbol, we want
3942 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3944 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3945 Otherwise, for a reference to a local symbol, we want
3946 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3948 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3949 If we have NewABI, we want
3950 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3951 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3952 If there is a constant, it must be added in after. */
3953 ex
.X_add_number
= ep
->X_add_number
;
3954 ep
->X_add_number
= 0;
3957 macro_build ((char *) NULL
, counter
, ep
,
3958 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3959 (int) BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3960 macro_build (p
, counter
, ep
,
3961 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
3962 reg
, reg
, (int) BFD_RELOC_MIPS_GOT_OFST
);
3966 if (reg_needs_delay (mips_gp_register
))
3971 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3972 (int) BFD_RELOC_MIPS_GOT_HI16
);
3973 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3974 HAVE_32BIT_ADDRESSES
? "addu" : "daddu", "d,v,t", reg
,
3975 reg
, mips_gp_register
);
3976 macro_build ((char *) NULL
, counter
, ep
,
3977 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3978 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3979 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3980 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3981 mips_opts
.warn_about_macros
),
3982 ep
->X_add_symbol
, 0, NULL
);
3985 /* We need a nop before loading from $gp. This special
3986 check is required because the lui which starts the main
3987 instruction stream does not refer to $gp, and so will not
3988 insert the nop which may be required. */
3989 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3992 macro_build (p
, counter
, ep
,
3993 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", reg
,
3994 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3996 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3998 macro_build (p
, counter
, ep
,
3999 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4000 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4003 if (ex
.X_add_number
!= 0)
4005 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4006 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4007 ex
.X_op
= O_constant
;
4008 macro_build ((char *) NULL
, counter
, &ex
,
4009 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4010 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
4013 else if (mips_pic
== EMBEDDED_PIC
)
4016 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4018 macro_build ((char *) NULL
, counter
, ep
,
4019 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4020 "t,r,j", reg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
4026 /* Move the contents of register SOURCE into register DEST. */
4029 move_register (counter
, dest
, source
)
4034 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
4035 HAVE_32BIT_GPRS
? "addu" : "daddu",
4036 "d,v,t", dest
, source
, 0);
4041 * This routine implements the seemingly endless macro or synthesized
4042 * instructions and addressing modes in the mips assembly language. Many
4043 * of these macros are simple and are similar to each other. These could
4044 * probably be handled by some kind of table or grammer aproach instead of
4045 * this verbose method. Others are not simple macros but are more like
4046 * optimizing code generation.
4047 * One interesting optimization is when several store macros appear
4048 * consecutivly that would load AT with the upper half of the same address.
4049 * The ensuing load upper instructions are ommited. This implies some kind
4050 * of global optimization. We currently only optimize within a single macro.
4051 * For many of the load and store macros if the address is specified as a
4052 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4053 * first load register 'at' with zero and use it as the base register. The
4054 * mips assembler simply uses register $zero. Just one tiny optimization
4059 struct mips_cl_insn
*ip
;
4061 register int treg
, sreg
, dreg
, breg
;
4077 bfd_reloc_code_real_type r
;
4078 int hold_mips_optimize
;
4080 assert (! mips_opts
.mips16
);
4082 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4083 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4084 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4085 mask
= ip
->insn_mo
->mask
;
4087 expr1
.X_op
= O_constant
;
4088 expr1
.X_op_symbol
= NULL
;
4089 expr1
.X_add_symbol
= NULL
;
4090 expr1
.X_add_number
= 1;
4102 mips_emit_delays (TRUE
);
4103 ++mips_opts
.noreorder
;
4104 mips_any_noreorder
= 1;
4106 expr1
.X_add_number
= 8;
4107 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
4109 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4112 move_register (&icnt
, dreg
, sreg
);
4113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4114 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4116 --mips_opts
.noreorder
;
4137 if (imm_expr
.X_op
== O_constant
4138 && imm_expr
.X_add_number
>= -0x8000
4139 && imm_expr
.X_add_number
< 0x8000)
4141 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
4142 (int) BFD_RELOC_LO16
);
4145 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4146 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4166 if (imm_expr
.X_op
== O_constant
4167 && imm_expr
.X_add_number
>= 0
4168 && imm_expr
.X_add_number
< 0x10000)
4170 if (mask
!= M_NOR_I
)
4171 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
4172 sreg
, (int) BFD_RELOC_LO16
);
4175 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
4176 treg
, sreg
, (int) BFD_RELOC_LO16
);
4177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
4178 "d,v,t", treg
, treg
, 0);
4183 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4184 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4202 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4204 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4208 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4209 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4217 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4218 likely
? "bgezl" : "bgez", "s,p", sreg
);
4223 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4224 likely
? "blezl" : "blez", "s,p", treg
);
4227 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4229 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4230 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4236 /* check for > max integer */
4237 maxnum
= 0x7fffffff;
4238 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4245 if (imm_expr
.X_op
== O_constant
4246 && imm_expr
.X_add_number
>= maxnum
4247 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4250 /* result is always false */
4254 as_warn (_("Branch %s is always false (nop)"),
4256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4262 as_warn (_("Branch likely %s is always false"),
4264 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4269 if (imm_expr
.X_op
!= O_constant
)
4270 as_bad (_("Unsupported large constant"));
4271 ++imm_expr
.X_add_number
;
4275 if (mask
== M_BGEL_I
)
4277 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4279 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4280 likely
? "bgezl" : "bgez", "s,p", sreg
);
4283 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4285 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4286 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4289 maxnum
= 0x7fffffff;
4290 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4297 maxnum
= - maxnum
- 1;
4298 if (imm_expr
.X_op
== O_constant
4299 && imm_expr
.X_add_number
<= maxnum
4300 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4303 /* result is always true */
4304 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4308 set_at (&icnt
, sreg
, 0);
4309 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4310 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4320 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4321 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4325 "d,v,t", AT
, sreg
, treg
);
4326 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4327 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4335 && imm_expr
.X_op
== O_constant
4336 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4338 if (imm_expr
.X_op
!= O_constant
)
4339 as_bad (_("Unsupported large constant"));
4340 ++imm_expr
.X_add_number
;
4344 if (mask
== M_BGEUL_I
)
4346 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4348 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4350 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4351 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4354 set_at (&icnt
, sreg
, 1);
4355 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4356 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4364 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4365 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4371 likely
? "bltzl" : "bltz", "s,p", treg
);
4374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4377 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4385 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4386 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4391 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4392 "d,v,t", AT
, treg
, sreg
);
4393 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4394 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4402 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4403 likely
? "blezl" : "blez", "s,p", sreg
);
4408 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4409 likely
? "bgezl" : "bgez", "s,p", treg
);
4412 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4414 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4415 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4421 maxnum
= 0x7fffffff;
4422 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4429 if (imm_expr
.X_op
== O_constant
4430 && imm_expr
.X_add_number
>= maxnum
4431 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4433 if (imm_expr
.X_op
!= O_constant
)
4434 as_bad (_("Unsupported large constant"));
4435 ++imm_expr
.X_add_number
;
4439 if (mask
== M_BLTL_I
)
4441 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4443 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4444 likely
? "bltzl" : "bltz", "s,p", sreg
);
4447 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4449 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4450 likely
? "blezl" : "blez", "s,p", sreg
);
4453 set_at (&icnt
, sreg
, 0);
4454 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4455 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4463 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4464 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4469 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4470 "d,v,t", AT
, treg
, sreg
);
4471 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4472 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4480 && imm_expr
.X_op
== O_constant
4481 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4483 if (imm_expr
.X_op
!= O_constant
)
4484 as_bad (_("Unsupported large constant"));
4485 ++imm_expr
.X_add_number
;
4489 if (mask
== M_BLTUL_I
)
4491 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4493 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4495 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4496 likely
? "beql" : "beq",
4500 set_at (&icnt
, sreg
, 1);
4501 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4502 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4511 likely
? "bltzl" : "bltz", "s,p", sreg
);
4516 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4517 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4520 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4522 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4523 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4533 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4534 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4537 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4541 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4556 as_warn (_("Divide by zero."));
4558 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4561 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4566 mips_emit_delays (TRUE
);
4567 ++mips_opts
.noreorder
;
4568 mips_any_noreorder
= 1;
4571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4572 "s,t,q", treg
, 0, 7);
4573 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4574 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4578 expr1
.X_add_number
= 8;
4579 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4581 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4585 expr1
.X_add_number
= -1;
4586 macro_build ((char *) NULL
, &icnt
, &expr1
,
4587 dbl
? "daddiu" : "addiu",
4588 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4589 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4590 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4593 expr1
.X_add_number
= 1;
4594 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4595 (int) BFD_RELOC_LO16
);
4596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4597 "d,w,<", AT
, AT
, 31);
4601 expr1
.X_add_number
= 0x80000000;
4602 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4603 (int) BFD_RELOC_HI16
);
4607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4608 "s,t,q", sreg
, AT
, 6);
4609 /* We want to close the noreorder block as soon as possible, so
4610 that later insns are available for delay slot filling. */
4611 --mips_opts
.noreorder
;
4615 expr1
.X_add_number
= 8;
4616 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4620 /* We want to close the noreorder block as soon as possible, so
4621 that later insns are available for delay slot filling. */
4622 --mips_opts
.noreorder
;
4624 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4627 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4666 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4668 as_warn (_("Divide by zero."));
4670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4673 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4677 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4679 if (strcmp (s2
, "mflo") == 0)
4680 move_register (&icnt
, dreg
, sreg
);
4682 move_register (&icnt
, dreg
, 0);
4685 if (imm_expr
.X_op
== O_constant
4686 && imm_expr
.X_add_number
== -1
4687 && s
[strlen (s
) - 1] != 'u')
4689 if (strcmp (s2
, "mflo") == 0)
4691 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4692 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4695 move_register (&icnt
, dreg
, 0);
4699 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4700 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4721 mips_emit_delays (TRUE
);
4722 ++mips_opts
.noreorder
;
4723 mips_any_noreorder
= 1;
4726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4727 "s,t,q", treg
, 0, 7);
4728 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4730 /* We want to close the noreorder block as soon as possible, so
4731 that later insns are available for delay slot filling. */
4732 --mips_opts
.noreorder
;
4736 expr1
.X_add_number
= 8;
4737 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4738 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4741 /* We want to close the noreorder block as soon as possible, so
4742 that later insns are available for delay slot filling. */
4743 --mips_opts
.noreorder
;
4744 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4753 /* Load the address of a symbol into a register. If breg is not
4754 zero, we then add a base register to it. */
4756 if (dbl
&& HAVE_32BIT_GPRS
)
4757 as_warn (_("dla used to load 32-bit register"));
4759 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4760 as_warn (_("la used to load 64-bit address"));
4762 if (offset_expr
.X_op
== O_constant
4763 && offset_expr
.X_add_number
>= -0x8000
4764 && offset_expr
.X_add_number
< 0x8000)
4766 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4767 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4768 "t,r,j", treg
, sreg
, (int) BFD_RELOC_LO16
);
4783 /* When generating embedded PIC code, we permit expressions of
4786 la $treg,foo-bar($breg)
4787 where bar is an address in the current section. These are used
4788 when getting the addresses of functions. We don't permit
4789 X_add_number to be non-zero, because if the symbol is
4790 external the relaxing code needs to know that any addend is
4791 purely the offset to X_op_symbol. */
4792 if (mips_pic
== EMBEDDED_PIC
4793 && offset_expr
.X_op
== O_subtract
4794 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4795 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4796 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4798 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4801 && (offset_expr
.X_add_number
== 0
4802 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4808 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4809 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4813 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4814 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4815 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4816 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4817 "d,v,t", tempreg
, tempreg
, breg
);
4819 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4820 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4821 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4827 if (offset_expr
.X_op
!= O_symbol
4828 && offset_expr
.X_op
!= O_constant
)
4830 as_bad (_("expression too complex"));
4831 offset_expr
.X_op
= O_constant
;
4834 if (offset_expr
.X_op
== O_constant
)
4835 load_register (&icnt
, tempreg
, &offset_expr
,
4836 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4837 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4838 : HAVE_64BIT_ADDRESSES
));
4839 else if (mips_pic
== NO_PIC
)
4841 /* If this is a reference to a GP relative symbol, we want
4842 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4844 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4845 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4846 If we have a constant, we need two instructions anyhow,
4847 so we may as well always use the latter form.
4849 With 64bit address space and a usable $at we want
4850 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4851 lui $at,<sym> (BFD_RELOC_HI16_S)
4852 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4853 daddiu $at,<sym> (BFD_RELOC_LO16)
4855 daddu $tempreg,$tempreg,$at
4857 If $at is already in use, we use a path which is suboptimal
4858 on superscalar processors.
4859 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4860 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4862 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4864 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4867 if (HAVE_64BIT_ADDRESSES
)
4869 /* We don't do GP optimization for now because RELAX_ENCODE can't
4870 hold the data for such large chunks. */
4872 if (used_at
== 0 && ! mips_opts
.noat
)
4874 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4875 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4876 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4877 AT
, (int) BFD_RELOC_HI16_S
);
4878 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4879 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4880 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4881 AT
, AT
, (int) BFD_RELOC_LO16
);
4882 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4883 "d,w,<", tempreg
, tempreg
, 0);
4884 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
4885 "d,v,t", tempreg
, tempreg
, AT
);
4890 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4891 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4892 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4893 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4894 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4895 tempreg
, tempreg
, 16);
4896 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4897 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4898 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4899 tempreg
, tempreg
, 16);
4900 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4901 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4906 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4907 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4910 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "addiu",
4911 "t,r,j", tempreg
, mips_gp_register
,
4912 (int) BFD_RELOC_GPREL16
);
4913 p
= frag_var (rs_machine_dependent
, 8, 0,
4914 RELAX_ENCODE (4, 8, 0, 4, 0,
4915 mips_opts
.warn_about_macros
),
4916 offset_expr
.X_add_symbol
, 0, NULL
);
4918 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4921 macro_build (p
, &icnt
, &offset_expr
, "addiu",
4922 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4925 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4927 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4929 /* If this is a reference to an external symbol, and there
4930 is no constant, we want
4931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4932 or if tempreg is PIC_CALL_REG
4933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4934 For a local symbol, we want
4935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4937 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4939 If we have a small constant, and this is a reference to
4940 an external symbol, we want
4941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4943 addiu $tempreg,$tempreg,<constant>
4944 For a local symbol, we want the same instruction
4945 sequence, but we output a BFD_RELOC_LO16 reloc on the
4948 If we have a large constant, and this is a reference to
4949 an external symbol, we want
4950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4951 lui $at,<hiconstant>
4952 addiu $at,$at,<loconstant>
4953 addu $tempreg,$tempreg,$at
4954 For a local symbol, we want the same instruction
4955 sequence, but we output a BFD_RELOC_LO16 reloc on the
4958 For NewABI, we want for local or external data addresses
4959 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4960 For a local function symbol, we want
4961 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4963 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4966 expr1
.X_add_number
= offset_expr
.X_add_number
;
4967 offset_expr
.X_add_number
= 0;
4969 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4970 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4971 else if (HAVE_NEWABI
)
4972 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
4973 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4974 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
4975 "t,o(b)", tempreg
, lw_reloc_type
, mips_gp_register
);
4976 if (expr1
.X_add_number
== 0)
4985 /* We're going to put in an addu instruction using
4986 tempreg, so we may as well insert the nop right
4988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4992 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4993 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4995 ? mips_opts
.warn_about_macros
4997 offset_expr
.X_add_symbol
, 0, NULL
);
5000 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5003 macro_build (p
, &icnt
, &expr1
,
5004 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5005 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5006 /* FIXME: If breg == 0, and the next instruction uses
5007 $tempreg, then if this variant case is used an extra
5008 nop will be generated. */
5010 else if (expr1
.X_add_number
>= -0x8000
5011 && expr1
.X_add_number
< 0x8000)
5013 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5015 macro_build ((char *) NULL
, &icnt
, &expr1
,
5016 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5017 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5018 frag_var (rs_machine_dependent
, 0, 0,
5019 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
5020 offset_expr
.X_add_symbol
, 0, NULL
);
5026 /* If we are going to add in a base register, and the
5027 target register and the base register are the same,
5028 then we are using AT as a temporary register. Since
5029 we want to load the constant into AT, we add our
5030 current AT (from the global offset table) and the
5031 register into the register now, and pretend we were
5032 not using a base register. */
5037 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5040 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5041 "d,v,t", treg
, AT
, breg
);
5047 /* Set mips_optimize around the lui instruction to avoid
5048 inserting an unnecessary nop after the lw. */
5049 hold_mips_optimize
= mips_optimize
;
5051 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5052 mips_optimize
= hold_mips_optimize
;
5054 macro_build ((char *) NULL
, &icnt
, &expr1
,
5055 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5056 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5057 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5058 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5059 "d,v,t", tempreg
, tempreg
, AT
);
5060 frag_var (rs_machine_dependent
, 0, 0,
5061 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
5062 offset_expr
.X_add_symbol
, 0, NULL
);
5066 else if (mips_pic
== SVR4_PIC
)
5070 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5071 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5072 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5074 /* This is the large GOT case. If this is a reference to an
5075 external symbol, and there is no constant, we want
5076 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5077 addu $tempreg,$tempreg,$gp
5078 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5079 or if tempreg is PIC_CALL_REG
5080 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5081 addu $tempreg,$tempreg,$gp
5082 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5083 For a local symbol, we want
5084 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5086 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5088 If we have a small constant, and this is a reference to
5089 an external symbol, we want
5090 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5091 addu $tempreg,$tempreg,$gp
5092 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5094 addiu $tempreg,$tempreg,<constant>
5095 For a local symbol, we want
5096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5098 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5100 If we have a large constant, and this is a reference to
5101 an external symbol, we want
5102 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5103 addu $tempreg,$tempreg,$gp
5104 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5105 lui $at,<hiconstant>
5106 addiu $at,$at,<loconstant>
5107 addu $tempreg,$tempreg,$at
5108 For a local symbol, we want
5109 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5110 lui $at,<hiconstant>
5111 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5112 addu $tempreg,$tempreg,$at
5114 For NewABI, we want for local data addresses
5115 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5118 expr1
.X_add_number
= offset_expr
.X_add_number
;
5119 offset_expr
.X_add_number
= 0;
5121 if (reg_needs_delay (mips_gp_register
))
5125 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
5127 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5128 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5130 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5131 tempreg
, lui_reloc_type
);
5132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5133 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5134 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
5135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5136 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5137 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
5138 if (expr1
.X_add_number
== 0)
5146 /* We're going to put in an addu instruction using
5147 tempreg, so we may as well insert the nop right
5149 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5154 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5155 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
5158 ? mips_opts
.warn_about_macros
5160 offset_expr
.X_add_symbol
, 0, NULL
);
5162 else if (expr1
.X_add_number
>= -0x8000
5163 && expr1
.X_add_number
< 0x8000)
5165 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5167 macro_build ((char *) NULL
, &icnt
, &expr1
,
5168 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5169 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5171 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5172 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
5174 ? mips_opts
.warn_about_macros
5176 offset_expr
.X_add_symbol
, 0, NULL
);
5182 /* If we are going to add in a base register, and the
5183 target register and the base register are the same,
5184 then we are using AT as a temporary register. Since
5185 we want to load the constant into AT, we add our
5186 current AT (from the global offset table) and the
5187 register into the register now, and pretend we were
5188 not using a base register. */
5196 assert (tempreg
== AT
);
5197 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5200 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5201 "d,v,t", treg
, AT
, breg
);
5206 /* Set mips_optimize around the lui instruction to avoid
5207 inserting an unnecessary nop after the lw. */
5208 hold_mips_optimize
= mips_optimize
;
5210 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
5211 mips_optimize
= hold_mips_optimize
;
5213 macro_build ((char *) NULL
, &icnt
, &expr1
,
5214 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5215 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5216 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5217 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5218 "d,v,t", dreg
, dreg
, AT
);
5220 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
5221 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5224 ? mips_opts
.warn_about_macros
5226 offset_expr
.X_add_symbol
, 0, NULL
);
5233 /* This is needed because this instruction uses $gp, but
5234 the first instruction on the main stream does not. */
5235 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5240 local_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5241 macro_build (p
, &icnt
, &offset_expr
,
5242 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5247 if (expr1
.X_add_number
== 0 && HAVE_NEWABI
)
5249 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
5252 if (expr1
.X_add_number
>= -0x8000
5253 && expr1
.X_add_number
< 0x8000)
5255 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5257 macro_build (p
, &icnt
, &expr1
,
5258 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5259 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5260 /* FIXME: If add_number is 0, and there was no base
5261 register, the external symbol case ended with a load,
5262 so if the symbol turns out to not be external, and
5263 the next instruction uses tempreg, an unnecessary nop
5264 will be inserted. */
5270 /* We must add in the base register now, as in the
5271 external symbol case. */
5272 assert (tempreg
== AT
);
5273 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5275 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5276 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5277 "d,v,t", treg
, AT
, breg
);
5280 /* We set breg to 0 because we have arranged to add
5281 it in in both cases. */
5285 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5287 macro_build (p
, &icnt
, &expr1
,
5288 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5289 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5291 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5292 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5293 "d,v,t", tempreg
, tempreg
, AT
);
5297 else if (mips_pic
== EMBEDDED_PIC
)
5300 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5303 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j",
5304 tempreg
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
5313 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5314 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5316 s
= HAVE_64BIT_ADDRESSES
? "daddu" : "addu";
5318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
,
5319 "d,v,t", treg
, tempreg
, breg
);
5328 /* The j instruction may not be used in PIC code, since it
5329 requires an absolute address. We convert it to a b
5331 if (mips_pic
== NO_PIC
)
5332 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5337 /* The jal instructions must be handled as macros because when
5338 generating PIC code they expand to multi-instruction
5339 sequences. Normally they are simple instructions. */
5344 if (mips_pic
== NO_PIC
5345 || mips_pic
== EMBEDDED_PIC
)
5346 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5348 else if (mips_pic
== SVR4_PIC
)
5350 if (sreg
!= PIC_CALL_REG
)
5351 as_warn (_("MIPS PIC call to register other than $25"));
5353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5357 if (mips_cprestore_offset
< 0)
5358 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5361 if (! mips_frame_reg_valid
)
5363 as_warn (_("No .frame pseudo-op used in PIC code"));
5364 /* Quiet this warning. */
5365 mips_frame_reg_valid
= 1;
5367 if (! mips_cprestore_valid
)
5369 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5370 /* Quiet this warning. */
5371 mips_cprestore_valid
= 1;
5373 expr1
.X_add_number
= mips_cprestore_offset
;
5374 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5375 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5376 mips_gp_register
, mips_frame_reg
);
5386 if (mips_pic
== NO_PIC
)
5387 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5388 else if (mips_pic
== SVR4_PIC
)
5392 /* If this is a reference to an external symbol, and we are
5393 using a small GOT, we want
5394 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5398 lw $gp,cprestore($sp)
5399 The cprestore value is set using the .cprestore
5400 pseudo-op. If we are using a big GOT, we want
5401 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5403 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5407 lw $gp,cprestore($sp)
5408 If the symbol is not external, we want
5409 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5411 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5414 lw $gp,cprestore($sp)
5416 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5417 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5422 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5423 "t,o(b)", PIC_CALL_REG
,
5424 (int) BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5425 macro_build_jalr (icnt
, &offset_expr
);
5432 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5433 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5434 "t,o(b)", PIC_CALL_REG
,
5435 (int) BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5436 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5438 p
= frag_var (rs_machine_dependent
, 4, 0,
5439 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5440 offset_expr
.X_add_symbol
, 0, NULL
);
5446 if (reg_needs_delay (mips_gp_register
))
5450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui",
5451 "t,u", PIC_CALL_REG
,
5452 (int) BFD_RELOC_MIPS_CALL_HI16
);
5453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5454 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5455 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
,
5457 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5458 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5459 "t,o(b)", PIC_CALL_REG
,
5460 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5461 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5463 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5464 RELAX_ENCODE (16, 12 + gpdel
, gpdel
,
5466 offset_expr
.X_add_symbol
, 0, NULL
);
5469 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5472 macro_build (p
, &icnt
, &offset_expr
,
5473 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5474 "t,o(b)", PIC_CALL_REG
,
5475 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5477 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5480 macro_build (p
, &icnt
, &offset_expr
,
5481 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5482 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5483 (int) BFD_RELOC_LO16
);
5484 macro_build_jalr (icnt
, &offset_expr
);
5486 if (mips_cprestore_offset
< 0)
5487 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5490 if (! mips_frame_reg_valid
)
5492 as_warn (_("No .frame pseudo-op used in PIC code"));
5493 /* Quiet this warning. */
5494 mips_frame_reg_valid
= 1;
5496 if (! mips_cprestore_valid
)
5498 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5499 /* Quiet this warning. */
5500 mips_cprestore_valid
= 1;
5502 if (mips_opts
.noreorder
)
5503 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5505 expr1
.X_add_number
= mips_cprestore_offset
;
5506 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &expr1
,
5507 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5508 mips_gp_register
, mips_frame_reg
);
5512 else if (mips_pic
== EMBEDDED_PIC
)
5514 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5515 /* The linker may expand the call to a longer sequence which
5516 uses $at, so we must break rather than return. */
5541 /* Itbl support may require additional care here. */
5546 /* Itbl support may require additional care here. */
5551 /* Itbl support may require additional care here. */
5556 /* Itbl support may require additional care here. */
5568 if (mips_arch
== CPU_R4650
)
5570 as_bad (_("opcode not supported on this processor"));
5574 /* Itbl support may require additional care here. */
5579 /* Itbl support may require additional care here. */
5584 /* Itbl support may require additional care here. */
5604 if (breg
== treg
|| coproc
|| lr
)
5626 /* Itbl support may require additional care here. */
5631 /* Itbl support may require additional care here. */
5636 /* Itbl support may require additional care here. */
5641 /* Itbl support may require additional care here. */
5657 if (mips_arch
== CPU_R4650
)
5659 as_bad (_("opcode not supported on this processor"));
5664 /* Itbl support may require additional care here. */
5668 /* Itbl support may require additional care here. */
5673 /* Itbl support may require additional care here. */
5685 /* Itbl support may require additional care here. */
5686 if (mask
== M_LWC1_AB
5687 || mask
== M_SWC1_AB
5688 || mask
== M_LDC1_AB
5689 || mask
== M_SDC1_AB
5698 /* For embedded PIC, we allow loads where the offset is calculated
5699 by subtracting a symbol in the current segment from an unknown
5700 symbol, relative to a base register, e.g.:
5701 <op> $treg, <sym>-<localsym>($breg)
5702 This is used by the compiler for switch statements. */
5703 if (mips_pic
== EMBEDDED_PIC
5704 && offset_expr
.X_op
== O_subtract
5705 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5706 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5707 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5709 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5713 && (offset_expr
.X_add_number
== 0
5714 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5716 /* For this case, we output the instructions:
5717 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5718 addiu $tempreg,$tempreg,$breg
5719 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5720 If the relocation would fit entirely in 16 bits, it would be
5722 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5723 instead, but that seems quite difficult. */
5724 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5725 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5727 ((bfd_arch_bits_per_address (stdoutput
) == 32
5728 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5729 ? "addu" : "daddu"),
5730 "d,v,t", tempreg
, tempreg
, breg
);
5731 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5732 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5738 if (offset_expr
.X_op
!= O_constant
5739 && offset_expr
.X_op
!= O_symbol
)
5741 as_bad (_("expression too complex"));
5742 offset_expr
.X_op
= O_constant
;
5745 /* A constant expression in PIC code can be handled just as it
5746 is in non PIC code. */
5747 if (mips_pic
== NO_PIC
5748 || offset_expr
.X_op
== O_constant
)
5752 /* If this is a reference to a GP relative symbol, and there
5753 is no base register, we want
5754 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5755 Otherwise, if there is no base register, we want
5756 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5757 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5758 If we have a constant, we need two instructions anyhow,
5759 so we always use the latter form.
5761 If we have a base register, and this is a reference to a
5762 GP relative symbol, we want
5763 addu $tempreg,$breg,$gp
5764 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5766 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5767 addu $tempreg,$tempreg,$breg
5768 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5769 With a constant we always use the latter case.
5771 With 64bit address space and no base register and $at usable,
5773 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5774 lui $at,<sym> (BFD_RELOC_HI16_S)
5775 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5778 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5779 If we have a base register, we want
5780 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5781 lui $at,<sym> (BFD_RELOC_HI16_S)
5782 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5786 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5788 Without $at we can't generate the optimal path for superscalar
5789 processors here since this would require two temporary registers.
5790 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5791 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5793 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5795 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5796 If we have a base register, we want
5797 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5798 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5800 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5802 daddu $tempreg,$tempreg,$breg
5803 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5805 If we have 64-bit addresses, as an optimization, for
5806 addresses which are 32-bit constants (e.g. kseg0/kseg1
5807 addresses) we fall back to the 32-bit address generation
5808 mechanism since it is more efficient. Note that due to
5809 the signed offset used by memory operations, the 32-bit
5810 range is shifted down by 32768 here. This code should
5811 probably attempt to generate 64-bit constants more
5812 efficiently in general.
5814 if (HAVE_64BIT_ADDRESSES
5815 && !(offset_expr
.X_op
== O_constant
5816 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5820 /* We don't do GP optimization for now because RELAX_ENCODE can't
5821 hold the data for such large chunks. */
5823 if (used_at
== 0 && ! mips_opts
.noat
)
5825 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5826 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5827 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5828 AT
, (int) BFD_RELOC_HI16_S
);
5829 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5830 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5832 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5833 "d,v,t", AT
, AT
, breg
);
5834 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5835 "d,w,<", tempreg
, tempreg
, 0);
5836 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5837 "d,v,t", tempreg
, tempreg
, AT
);
5838 macro_build (p
, &icnt
, &offset_expr
, s
,
5839 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5844 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5845 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5846 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5847 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5848 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5849 "d,w,<", tempreg
, tempreg
, 16);
5850 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5851 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5852 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5853 "d,w,<", tempreg
, tempreg
, 16);
5855 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5856 "d,v,t", tempreg
, tempreg
, breg
);
5857 macro_build (p
, &icnt
, &offset_expr
, s
,
5858 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5866 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5867 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5872 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5873 treg
, (int) BFD_RELOC_GPREL16
,
5875 p
= frag_var (rs_machine_dependent
, 8, 0,
5876 RELAX_ENCODE (4, 8, 0, 4, 0,
5877 (mips_opts
.warn_about_macros
5879 && mips_opts
.noat
))),
5880 offset_expr
.X_add_symbol
, 0, NULL
);
5883 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5886 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5887 (int) BFD_RELOC_LO16
, tempreg
);
5891 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5892 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5897 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5898 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5899 "d,v,t", tempreg
, breg
, mips_gp_register
);
5900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5901 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5902 p
= frag_var (rs_machine_dependent
, 12, 0,
5903 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5904 offset_expr
.X_add_symbol
, 0, NULL
);
5906 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5909 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5910 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5911 "d,v,t", tempreg
, tempreg
, breg
);
5914 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5915 (int) BFD_RELOC_LO16
, tempreg
);
5918 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5921 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5923 /* If this is a reference to an external symbol, we want
5924 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5926 <op> $treg,0($tempreg)
5928 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5930 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5931 <op> $treg,0($tempreg)
5932 If we have NewABI, we want
5933 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5934 If there is a base register, we add it to $tempreg before
5935 the <op>. If there is a constant, we stick it in the
5936 <op> instruction. We don't handle constants larger than
5937 16 bits, because we have no way to load the upper 16 bits
5938 (actually, we could handle them for the subset of cases
5939 in which we are not using $at). */
5940 assert (offset_expr
.X_op
== O_symbol
);
5941 expr1
.X_add_number
= offset_expr
.X_add_number
;
5942 offset_expr
.X_add_number
= 0;
5944 lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_DISP
;
5945 if (expr1
.X_add_number
< -0x8000
5946 || expr1
.X_add_number
>= 0x8000)
5947 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5949 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5950 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", tempreg
,
5951 (int) lw_reloc_type
, mips_gp_register
);
5952 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5953 p
= frag_var (rs_machine_dependent
, 4, 0,
5954 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5955 offset_expr
.X_add_symbol
, 0, NULL
);
5956 macro_build (p
, &icnt
, &offset_expr
,
5957 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5958 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5960 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5961 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5962 "d,v,t", tempreg
, tempreg
, breg
);
5963 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5964 (int) BFD_RELOC_LO16
, tempreg
);
5966 else if (mips_pic
== SVR4_PIC
)
5971 /* If this is a reference to an external symbol, we want
5972 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5973 addu $tempreg,$tempreg,$gp
5974 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5975 <op> $treg,0($tempreg)
5977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5979 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5980 <op> $treg,0($tempreg)
5981 If there is a base register, we add it to $tempreg before
5982 the <op>. If there is a constant, we stick it in the
5983 <op> instruction. We don't handle constants larger than
5984 16 bits, because we have no way to load the upper 16 bits
5985 (actually, we could handle them for the subset of cases
5986 in which we are not using $at).
5989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5990 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5991 <op> $treg,0($tempreg)
5993 assert (offset_expr
.X_op
== O_symbol
);
5994 expr1
.X_add_number
= offset_expr
.X_add_number
;
5995 offset_expr
.X_add_number
= 0;
5996 if (expr1
.X_add_number
< -0x8000
5997 || expr1
.X_add_number
>= 0x8000)
5998 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6001 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6002 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6003 "t,o(b)", tempreg
, BFD_RELOC_MIPS_GOT_PAGE
,
6005 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6006 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6007 "t,r,j", tempreg
, tempreg
,
6008 BFD_RELOC_MIPS_GOT_OFST
);
6010 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6011 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6012 "d,v,t", tempreg
, tempreg
, breg
);
6013 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6014 (int) BFD_RELOC_LO16
, tempreg
);
6021 if (reg_needs_delay (mips_gp_register
))
6026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6027 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6029 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6030 "d,v,t", tempreg
, tempreg
, mips_gp_register
);
6031 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6032 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6033 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
6035 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
6036 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
6037 offset_expr
.X_add_symbol
, 0, NULL
);
6040 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6043 macro_build (p
, &icnt
, &offset_expr
,
6044 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6045 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
,
6048 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6050 macro_build (p
, &icnt
, &offset_expr
,
6051 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
6052 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
6054 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6055 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6056 "d,v,t", tempreg
, tempreg
, breg
);
6057 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
6058 (int) BFD_RELOC_LO16
, tempreg
);
6060 else if (mips_pic
== EMBEDDED_PIC
)
6062 /* If there is no base register, we want
6063 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6064 If there is a base register, we want
6065 addu $tempreg,$breg,$gp
6066 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6068 assert (offset_expr
.X_op
== O_symbol
);
6071 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6072 treg
, (int) BFD_RELOC_GPREL16
, mips_gp_register
);
6077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6078 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6079 "d,v,t", tempreg
, breg
, mips_gp_register
);
6080 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6081 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
6094 load_register (&icnt
, treg
, &imm_expr
, 0);
6098 load_register (&icnt
, treg
, &imm_expr
, 1);
6102 if (imm_expr
.X_op
== O_constant
)
6104 load_register (&icnt
, AT
, &imm_expr
, 0);
6105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6106 "mtc1", "t,G", AT
, treg
);
6111 assert (offset_expr
.X_op
== O_symbol
6112 && strcmp (segment_name (S_GET_SEGMENT
6113 (offset_expr
.X_add_symbol
)),
6115 && offset_expr
.X_add_number
== 0);
6116 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6117 treg
, (int) BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6122 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6123 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6124 order 32 bits of the value and the low order 32 bits are either
6125 zero or in OFFSET_EXPR. */
6126 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6128 if (HAVE_64BIT_GPRS
)
6129 load_register (&icnt
, treg
, &imm_expr
, 1);
6134 if (target_big_endian
)
6146 load_register (&icnt
, hreg
, &imm_expr
, 0);
6149 if (offset_expr
.X_op
== O_absent
)
6150 move_register (&icnt
, lreg
, 0);
6153 assert (offset_expr
.X_op
== O_constant
);
6154 load_register (&icnt
, lreg
, &offset_expr
, 0);
6161 /* We know that sym is in the .rdata section. First we get the
6162 upper 16 bits of the address. */
6163 if (mips_pic
== NO_PIC
)
6165 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6167 else if (mips_pic
== SVR4_PIC
)
6169 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6170 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6171 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6174 else if (mips_pic
== EMBEDDED_PIC
)
6176 /* For embedded PIC we pick up the entire address off $gp in
6177 a single instruction. */
6178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6179 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu", "t,r,j", AT
,
6180 mips_gp_register
, (int) BFD_RELOC_GPREL16
);
6181 offset_expr
.X_op
= O_constant
;
6182 offset_expr
.X_add_number
= 0;
6187 /* Now we load the register(s). */
6188 if (HAVE_64BIT_GPRS
)
6189 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
6190 treg
, (int) BFD_RELOC_LO16
, AT
);
6193 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6194 treg
, (int) BFD_RELOC_LO16
, AT
);
6197 /* FIXME: How in the world do we deal with the possible
6199 offset_expr
.X_add_number
+= 4;
6200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
6201 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
6205 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6206 does not become a variant frag. */
6207 frag_wane (frag_now
);
6213 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6214 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6215 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6216 the value and the low order 32 bits are either zero or in
6218 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6220 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6221 if (HAVE_64BIT_FPRS
)
6223 assert (HAVE_64BIT_GPRS
);
6224 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6225 "dmtc1", "t,S", AT
, treg
);
6229 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6230 "mtc1", "t,G", AT
, treg
+ 1);
6231 if (offset_expr
.X_op
== O_absent
)
6232 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6233 "mtc1", "t,G", 0, treg
);
6236 assert (offset_expr
.X_op
== O_constant
);
6237 load_register (&icnt
, AT
, &offset_expr
, 0);
6238 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6239 "mtc1", "t,G", AT
, treg
);
6245 assert (offset_expr
.X_op
== O_symbol
6246 && offset_expr
.X_add_number
== 0);
6247 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6248 if (strcmp (s
, ".lit8") == 0)
6250 if (mips_opts
.isa
!= ISA_MIPS1
)
6252 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6253 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
,
6257 breg
= mips_gp_register
;
6258 r
= BFD_RELOC_MIPS_LITERAL
;
6263 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6264 if (mips_pic
== SVR4_PIC
)
6265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6266 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6267 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6271 /* FIXME: This won't work for a 64 bit address. */
6272 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
6275 if (mips_opts
.isa
!= ISA_MIPS1
)
6277 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
6278 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
6280 /* To avoid confusion in tc_gen_reloc, we must ensure
6281 that this does not become a variant frag. */
6282 frag_wane (frag_now
);
6293 if (mips_arch
== CPU_R4650
)
6295 as_bad (_("opcode not supported on this processor"));
6298 /* Even on a big endian machine $fn comes before $fn+1. We have
6299 to adjust when loading from memory. */
6302 assert (mips_opts
.isa
== ISA_MIPS1
);
6303 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6304 target_big_endian
? treg
+ 1 : treg
,
6306 /* FIXME: A possible overflow which I don't know how to deal
6308 offset_expr
.X_add_number
+= 4;
6309 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6310 target_big_endian
? treg
: treg
+ 1,
6313 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6314 does not become a variant frag. */
6315 frag_wane (frag_now
);
6324 * The MIPS assembler seems to check for X_add_number not
6325 * being double aligned and generating:
6328 * addiu at,at,%lo(foo+1)
6331 * But, the resulting address is the same after relocation so why
6332 * generate the extra instruction?
6334 if (mips_arch
== CPU_R4650
)
6336 as_bad (_("opcode not supported on this processor"));
6339 /* Itbl support may require additional care here. */
6341 if (mips_opts
.isa
!= ISA_MIPS1
)
6352 if (mips_arch
== CPU_R4650
)
6354 as_bad (_("opcode not supported on this processor"));
6358 if (mips_opts
.isa
!= ISA_MIPS1
)
6366 /* Itbl support may require additional care here. */
6371 if (HAVE_64BIT_GPRS
)
6382 if (HAVE_64BIT_GPRS
)
6392 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6393 loads for the case of doing a pair of loads to simulate an 'ld'.
6394 This is not currently done by the compiler, and assembly coders
6395 writing embedded-pic code can cope. */
6397 if (offset_expr
.X_op
!= O_symbol
6398 && offset_expr
.X_op
!= O_constant
)
6400 as_bad (_("expression too complex"));
6401 offset_expr
.X_op
= O_constant
;
6404 /* Even on a big endian machine $fn comes before $fn+1. We have
6405 to adjust when loading from memory. We set coproc if we must
6406 load $fn+1 first. */
6407 /* Itbl support may require additional care here. */
6408 if (! target_big_endian
)
6411 if (mips_pic
== NO_PIC
6412 || offset_expr
.X_op
== O_constant
)
6416 /* If this is a reference to a GP relative symbol, we want
6417 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6418 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6419 If we have a base register, we use this
6421 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6422 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6423 If this is not a GP relative symbol, we want
6424 lui $at,<sym> (BFD_RELOC_HI16_S)
6425 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6426 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6427 If there is a base register, we add it to $at after the
6428 lui instruction. If there is a constant, we always use
6430 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6431 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6443 tempreg
= mips_gp_register
;
6450 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6451 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6452 "d,v,t", AT
, breg
, mips_gp_register
);
6458 /* Itbl support may require additional care here. */
6459 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6460 coproc
? treg
+ 1 : treg
,
6461 (int) BFD_RELOC_GPREL16
, tempreg
);
6462 offset_expr
.X_add_number
+= 4;
6464 /* Set mips_optimize to 2 to avoid inserting an
6466 hold_mips_optimize
= mips_optimize
;
6468 /* Itbl support may require additional care here. */
6469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6470 coproc
? treg
: treg
+ 1,
6471 (int) BFD_RELOC_GPREL16
, tempreg
);
6472 mips_optimize
= hold_mips_optimize
;
6474 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6475 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6476 used_at
&& mips_opts
.noat
),
6477 offset_expr
.X_add_symbol
, 0, NULL
);
6479 /* We just generated two relocs. When tc_gen_reloc
6480 handles this case, it will skip the first reloc and
6481 handle the second. The second reloc already has an
6482 extra addend of 4, which we added above. We must
6483 subtract it out, and then subtract another 4 to make
6484 the first reloc come out right. The second reloc
6485 will come out right because we are going to add 4 to
6486 offset_expr when we build its instruction below.
6488 If we have a symbol, then we don't want to include
6489 the offset, because it will wind up being included
6490 when we generate the reloc. */
6492 if (offset_expr
.X_op
== O_constant
)
6493 offset_expr
.X_add_number
-= 8;
6496 offset_expr
.X_add_number
= -4;
6497 offset_expr
.X_op
= O_constant
;
6500 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6505 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6506 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6507 "d,v,t", AT
, breg
, AT
);
6511 /* Itbl support may require additional care here. */
6512 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6513 coproc
? treg
+ 1 : treg
,
6514 (int) BFD_RELOC_LO16
, AT
);
6517 /* FIXME: How do we handle overflow here? */
6518 offset_expr
.X_add_number
+= 4;
6519 /* Itbl support may require additional care here. */
6520 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6521 coproc
? treg
: treg
+ 1,
6522 (int) BFD_RELOC_LO16
, AT
);
6524 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6528 /* If this is a reference to an external symbol, we want
6529 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6534 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6536 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6537 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6538 If there is a base register we add it to $at before the
6539 lwc1 instructions. If there is a constant we include it
6540 in the lwc1 instructions. */
6542 expr1
.X_add_number
= offset_expr
.X_add_number
;
6543 offset_expr
.X_add_number
= 0;
6544 if (expr1
.X_add_number
< -0x8000
6545 || expr1
.X_add_number
>= 0x8000 - 4)
6546 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6551 frag_grow (24 + off
);
6552 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6553 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)", AT
,
6554 (int) BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6555 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6557 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6558 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6559 "d,v,t", AT
, breg
, AT
);
6560 /* Itbl support may require additional care here. */
6561 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6562 coproc
? treg
+ 1 : treg
,
6563 (int) BFD_RELOC_LO16
, AT
);
6564 expr1
.X_add_number
+= 4;
6566 /* Set mips_optimize to 2 to avoid inserting an undesired
6568 hold_mips_optimize
= mips_optimize
;
6570 /* Itbl support may require additional care here. */
6571 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6572 coproc
? treg
: treg
+ 1,
6573 (int) BFD_RELOC_LO16
, AT
);
6574 mips_optimize
= hold_mips_optimize
;
6576 (void) frag_var (rs_machine_dependent
, 0, 0,
6577 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6578 offset_expr
.X_add_symbol
, 0, NULL
);
6580 else if (mips_pic
== SVR4_PIC
)
6585 /* If this is a reference to an external symbol, we want
6586 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6588 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6593 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6595 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6596 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6597 If there is a base register we add it to $at before the
6598 lwc1 instructions. If there is a constant we include it
6599 in the lwc1 instructions. */
6601 expr1
.X_add_number
= offset_expr
.X_add_number
;
6602 offset_expr
.X_add_number
= 0;
6603 if (expr1
.X_add_number
< -0x8000
6604 || expr1
.X_add_number
>= 0x8000 - 4)
6605 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6606 if (reg_needs_delay (mips_gp_register
))
6615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6616 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6617 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6618 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6619 "d,v,t", AT
, AT
, mips_gp_register
);
6620 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6621 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6622 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6623 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6625 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6626 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6627 "d,v,t", AT
, breg
, AT
);
6628 /* Itbl support may require additional care here. */
6629 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6630 coproc
? treg
+ 1 : treg
,
6631 (int) BFD_RELOC_LO16
, AT
);
6632 expr1
.X_add_number
+= 4;
6634 /* Set mips_optimize to 2 to avoid inserting an undesired
6636 hold_mips_optimize
= mips_optimize
;
6638 /* Itbl support may require additional care here. */
6639 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6640 coproc
? treg
: treg
+ 1,
6641 (int) BFD_RELOC_LO16
, AT
);
6642 mips_optimize
= hold_mips_optimize
;
6643 expr1
.X_add_number
-= 4;
6645 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6646 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6647 8 + gpdel
+ off
, 1, 0),
6648 offset_expr
.X_add_symbol
, 0, NULL
);
6651 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6654 macro_build (p
, &icnt
, &offset_expr
,
6655 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6656 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
,
6659 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6663 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6664 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6665 "d,v,t", AT
, breg
, AT
);
6668 /* Itbl support may require additional care here. */
6669 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6670 coproc
? treg
+ 1 : treg
,
6671 (int) BFD_RELOC_LO16
, AT
);
6673 expr1
.X_add_number
+= 4;
6675 /* Set mips_optimize to 2 to avoid inserting an undesired
6677 hold_mips_optimize
= mips_optimize
;
6679 /* Itbl support may require additional care here. */
6680 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6681 coproc
? treg
: treg
+ 1,
6682 (int) BFD_RELOC_LO16
, AT
);
6683 mips_optimize
= hold_mips_optimize
;
6685 else if (mips_pic
== EMBEDDED_PIC
)
6687 /* If there is no base register, we use
6688 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6689 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6690 If we have a base register, we use
6692 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6693 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6697 tempreg
= mips_gp_register
;
6702 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6703 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6704 "d,v,t", AT
, breg
, mips_gp_register
);
6709 /* Itbl support may require additional care here. */
6710 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6711 coproc
? treg
+ 1 : treg
,
6712 (int) BFD_RELOC_GPREL16
, tempreg
);
6713 offset_expr
.X_add_number
+= 4;
6714 /* Itbl support may require additional care here. */
6715 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6716 coproc
? treg
: treg
+ 1,
6717 (int) BFD_RELOC_GPREL16
, tempreg
);
6733 assert (HAVE_32BIT_ADDRESSES
);
6734 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6735 (int) BFD_RELOC_LO16
, breg
);
6736 offset_expr
.X_add_number
+= 4;
6737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6738 (int) BFD_RELOC_LO16
, breg
);
6741 /* New code added to support COPZ instructions.
6742 This code builds table entries out of the macros in mip_opcodes.
6743 R4000 uses interlocks to handle coproc delays.
6744 Other chips (like the R3000) require nops to be inserted for delays.
6746 FIXME: Currently, we require that the user handle delays.
6747 In order to fill delay slots for non-interlocked chips,
6748 we must have a way to specify delays based on the coprocessor.
6749 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6750 What are the side-effects of the cop instruction?
6751 What cache support might we have and what are its effects?
6752 Both coprocessor & memory require delays. how long???
6753 What registers are read/set/modified?
6755 If an itbl is provided to interpret cop instructions,
6756 this knowledge can be encoded in the itbl spec. */
6770 /* For now we just do C (same as Cz). The parameter will be
6771 stored in insn_opcode by mips_ip. */
6772 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6777 move_register (&icnt
, dreg
, sreg
);
6780 #ifdef LOSING_COMPILER
6782 /* Try and see if this is a new itbl instruction.
6783 This code builds table entries out of the macros in mip_opcodes.
6784 FIXME: For now we just assemble the expression and pass it's
6785 value along as a 32-bit immediate.
6786 We may want to have the assembler assemble this value,
6787 so that we gain the assembler's knowledge of delay slots,
6789 Would it be more efficient to use mask (id) here? */
6790 if (itbl_have_entries
6791 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6793 s
= ip
->insn_mo
->name
;
6795 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6796 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6803 as_warn (_("Macro used $at after \".set noat\""));
6808 struct mips_cl_insn
*ip
;
6810 register int treg
, sreg
, dreg
, breg
;
6826 bfd_reloc_code_real_type r
;
6829 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6830 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6831 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6832 mask
= ip
->insn_mo
->mask
;
6834 expr1
.X_op
= O_constant
;
6835 expr1
.X_op_symbol
= NULL
;
6836 expr1
.X_add_symbol
= NULL
;
6837 expr1
.X_add_number
= 1;
6841 #endif /* LOSING_COMPILER */
6846 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6847 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6848 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6855 /* The MIPS assembler some times generates shifts and adds. I'm
6856 not trying to be that fancy. GCC should do this for us
6858 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6860 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6861 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6875 mips_emit_delays (TRUE
);
6876 ++mips_opts
.noreorder
;
6877 mips_any_noreorder
= 1;
6879 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6880 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6881 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6882 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6884 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6885 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6889 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6890 "s,t,q", dreg
, AT
, 6);
6893 expr1
.X_add_number
= 8;
6894 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6898 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6901 --mips_opts
.noreorder
;
6902 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6915 mips_emit_delays (TRUE
);
6916 ++mips_opts
.noreorder
;
6917 mips_any_noreorder
= 1;
6919 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6920 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6921 dbl
? "dmultu" : "multu",
6922 "s,t", sreg
, imm
? AT
: treg
);
6923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6925 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne",
6932 expr1
.X_add_number
= 8;
6933 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6934 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6936 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6939 --mips_opts
.noreorder
;
6943 if (CPU_HAS_DROR (mips_arch
))
6955 macro_build ((char *) NULL
, &icnt
, NULL
, "dnegu",
6956 "d,w", tempreg
, treg
);
6957 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
6958 "d,t,s", dreg
, sreg
, tempreg
);
6963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
6964 "d,v,t", AT
, 0, treg
);
6965 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
6966 "d,t,s", AT
, sreg
, AT
);
6967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
6968 "d,t,s", dreg
, sreg
, treg
);
6969 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6970 "d,v,t", dreg
, dreg
, AT
);
6974 if (CPU_HAS_ROR (mips_arch
))
6986 macro_build ((char *) NULL
, &icnt
, NULL
, "negu",
6987 "d,w", tempreg
, treg
);
6988 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
6989 "d,t,s", dreg
, sreg
, tempreg
);
6994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6995 "d,v,t", AT
, 0, treg
);
6996 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6997 "d,t,s", AT
, sreg
, AT
);
6998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6999 "d,t,s", dreg
, sreg
, treg
);
7000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7001 "d,v,t", dreg
, dreg
, AT
);
7009 if (imm_expr
.X_op
!= O_constant
)
7010 as_bad (_("Improper rotate count"));
7011 rot
= imm_expr
.X_add_number
& 0x3f;
7012 if (CPU_HAS_DROR (mips_arch
))
7014 rot
= (64 - rot
) & 0x3f;
7016 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7017 "d,w,<", dreg
, sreg
, rot
- 32);
7019 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7020 "d,w,<", dreg
, sreg
, rot
);
7025 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7026 "d,w,<", dreg
, sreg
, 0);
7029 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7030 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7032 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7033 "d,w,<", AT
, sreg
, rot
);
7034 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7035 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7036 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7037 "d,v,t", dreg
, dreg
, AT
);
7045 if (imm_expr
.X_op
!= O_constant
)
7046 as_bad (_("Improper rotate count"));
7047 rot
= imm_expr
.X_add_number
& 0x1f;
7048 if (CPU_HAS_ROR (mips_arch
))
7050 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7051 "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7056 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7057 "d,w,<", dreg
, sreg
, 0);
7060 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7061 "d,w,<", AT
, sreg
, rot
);
7062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7063 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7064 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7065 "d,v,t", dreg
, dreg
, AT
);
7070 if (CPU_HAS_DROR (mips_arch
))
7072 macro_build ((char *) NULL
, &icnt
, NULL
, "drorv",
7073 "d,t,s", dreg
, sreg
, treg
);
7076 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsubu",
7077 "d,v,t", AT
, 0, treg
);
7078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsllv",
7079 "d,t,s", AT
, sreg
, AT
);
7080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrlv",
7081 "d,t,s", dreg
, sreg
, treg
);
7082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7083 "d,v,t", dreg
, dreg
, AT
);
7087 if (CPU_HAS_ROR (mips_arch
))
7089 macro_build ((char *) NULL
, &icnt
, NULL
, "rorv",
7090 "d,t,s", dreg
, sreg
, treg
);
7093 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
7094 "d,v,t", AT
, 0, treg
);
7095 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
7096 "d,t,s", AT
, sreg
, AT
);
7097 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
7098 "d,t,s", dreg
, sreg
, treg
);
7099 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7100 "d,v,t", dreg
, dreg
, AT
);
7108 if (imm_expr
.X_op
!= O_constant
)
7109 as_bad (_("Improper rotate count"));
7110 rot
= imm_expr
.X_add_number
& 0x3f;
7111 if (CPU_HAS_DROR (mips_arch
))
7114 macro_build ((char *) NULL
, &icnt
, NULL
, "dror32",
7115 "d,w,<", dreg
, sreg
, rot
- 32);
7117 macro_build ((char *) NULL
, &icnt
, NULL
, "dror",
7118 "d,w,<", dreg
, sreg
, rot
);
7123 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsrl",
7124 "d,w,<", dreg
, sreg
, 0);
7127 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7128 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, r
,
7131 "d,w,<", AT
, sreg
, rot
);
7132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, l
,
7133 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7134 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7135 "d,v,t", dreg
, dreg
, AT
);
7143 if (imm_expr
.X_op
!= O_constant
)
7144 as_bad (_("Improper rotate count"));
7145 rot
= imm_expr
.X_add_number
& 0x1f;
7146 if (CPU_HAS_ROR (mips_arch
))
7148 macro_build ((char *) NULL
, &icnt
, NULL
, "ror",
7149 "d,w,<", dreg
, sreg
, rot
);
7154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7155 "d,w,<", dreg
, sreg
, 0);
7158 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl",
7159 "d,w,<", AT
, sreg
, rot
);
7160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll",
7161 "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
7163 "d,v,t", dreg
, dreg
, AT
);
7168 if (mips_arch
== CPU_R4650
)
7170 as_bad (_("opcode not supported on this processor"));
7173 assert (mips_opts
.isa
== ISA_MIPS1
);
7174 /* Even on a big endian machine $fn comes before $fn+1. We have
7175 to adjust when storing to memory. */
7176 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7177 target_big_endian
? treg
+ 1 : treg
,
7178 (int) BFD_RELOC_LO16
, breg
);
7179 offset_expr
.X_add_number
+= 4;
7180 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
7181 target_big_endian
? treg
: treg
+ 1,
7182 (int) BFD_RELOC_LO16
, breg
);
7187 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7188 treg
, (int) BFD_RELOC_LO16
);
7190 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7191 sreg
, (int) BFD_RELOC_LO16
);
7194 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7195 "d,v,t", dreg
, sreg
, treg
);
7196 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7197 dreg
, (int) BFD_RELOC_LO16
);
7202 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7204 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
7205 sreg
, (int) BFD_RELOC_LO16
);
7210 as_warn (_("Instruction %s: result is always false"),
7212 move_register (&icnt
, dreg
, 0);
7215 if (imm_expr
.X_op
== O_constant
7216 && imm_expr
.X_add_number
>= 0
7217 && imm_expr
.X_add_number
< 0x10000)
7219 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
7220 sreg
, (int) BFD_RELOC_LO16
);
7223 else if (imm_expr
.X_op
== O_constant
7224 && imm_expr
.X_add_number
> -0x8000
7225 && imm_expr
.X_add_number
< 0)
7227 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7228 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7229 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7230 "t,r,j", dreg
, sreg
,
7231 (int) BFD_RELOC_LO16
);
7236 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7237 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7238 "d,v,t", dreg
, sreg
, AT
);
7241 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
7242 (int) BFD_RELOC_LO16
);
7247 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7255 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7256 (int) BFD_RELOC_LO16
);
7259 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7261 if (imm_expr
.X_op
== O_constant
7262 && imm_expr
.X_add_number
>= -0x8000
7263 && imm_expr
.X_add_number
< 0x8000)
7265 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7266 mask
== M_SGE_I
? "slti" : "sltiu",
7267 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7272 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7274 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
7278 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7279 (int) BFD_RELOC_LO16
);
7284 case M_SGT
: /* sreg > treg <==> treg < sreg */
7290 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7294 case M_SGT_I
: /* sreg > I <==> I < sreg */
7300 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7305 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7311 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7313 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7314 (int) BFD_RELOC_LO16
);
7317 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7323 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
7326 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
7327 (int) BFD_RELOC_LO16
);
7331 if (imm_expr
.X_op
== O_constant
7332 && imm_expr
.X_add_number
>= -0x8000
7333 && imm_expr
.X_add_number
< 0x8000)
7335 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
7336 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7339 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7340 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
7345 if (imm_expr
.X_op
== O_constant
7346 && imm_expr
.X_add_number
>= -0x8000
7347 && imm_expr
.X_add_number
< 0x8000)
7349 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
7350 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7353 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7354 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7355 "d,v,t", dreg
, sreg
, AT
);
7360 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7361 "d,v,t", dreg
, 0, treg
);
7363 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7364 "d,v,t", dreg
, 0, sreg
);
7367 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7368 "d,v,t", dreg
, sreg
, treg
);
7369 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7370 "d,v,t", dreg
, 0, dreg
);
7375 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7377 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7378 "d,v,t", dreg
, 0, sreg
);
7383 as_warn (_("Instruction %s: result is always true"),
7385 macro_build ((char *) NULL
, &icnt
, &expr1
,
7386 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7387 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
7390 if (imm_expr
.X_op
== O_constant
7391 && imm_expr
.X_add_number
>= 0
7392 && imm_expr
.X_add_number
< 0x10000)
7394 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
7395 dreg
, sreg
, (int) BFD_RELOC_LO16
);
7398 else if (imm_expr
.X_op
== O_constant
7399 && imm_expr
.X_add_number
> -0x8000
7400 && imm_expr
.X_add_number
< 0)
7402 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7403 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7404 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7405 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7410 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7411 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
7412 "d,v,t", dreg
, sreg
, AT
);
7415 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
7416 "d,v,t", dreg
, 0, dreg
);
7424 if (imm_expr
.X_op
== O_constant
7425 && imm_expr
.X_add_number
> -0x8000
7426 && imm_expr
.X_add_number
<= 0x8000)
7428 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7429 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7430 dbl
? "daddi" : "addi",
7431 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7434 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7435 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7436 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7442 if (imm_expr
.X_op
== O_constant
7443 && imm_expr
.X_add_number
> -0x8000
7444 && imm_expr
.X_add_number
<= 0x8000)
7446 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7447 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7448 dbl
? "daddiu" : "addiu",
7449 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
7452 load_register (&icnt
, AT
, &imm_expr
, dbl
);
7453 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7454 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7475 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7476 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
7482 assert (mips_opts
.isa
== ISA_MIPS1
);
7483 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7484 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7487 * Is the double cfc1 instruction a bug in the mips assembler;
7488 * or is there a reason for it?
7490 mips_emit_delays (TRUE
);
7491 ++mips_opts
.noreorder
;
7492 mips_any_noreorder
= 1;
7493 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7497 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7498 expr1
.X_add_number
= 3;
7499 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7500 (int) BFD_RELOC_LO16
);
7501 expr1
.X_add_number
= 2;
7502 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7503 (int) BFD_RELOC_LO16
);
7504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7508 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7509 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7511 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7512 --mips_opts
.noreorder
;
7521 if (offset_expr
.X_add_number
>= 0x7fff)
7522 as_bad (_("operand overflow"));
7523 /* avoid load delay */
7524 if (! target_big_endian
)
7525 ++offset_expr
.X_add_number
;
7526 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7527 (int) BFD_RELOC_LO16
, breg
);
7528 if (! target_big_endian
)
7529 --offset_expr
.X_add_number
;
7531 ++offset_expr
.X_add_number
;
7532 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7533 (int) BFD_RELOC_LO16
, breg
);
7534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7550 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7551 as_bad (_("operand overflow"));
7552 if (! target_big_endian
)
7553 offset_expr
.X_add_number
+= off
;
7554 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7555 (int) BFD_RELOC_LO16
, breg
);
7556 if (! target_big_endian
)
7557 offset_expr
.X_add_number
-= off
;
7559 offset_expr
.X_add_number
+= off
;
7560 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7561 (int) BFD_RELOC_LO16
, breg
);
7575 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7577 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7578 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7579 "d,v,t", AT
, AT
, breg
);
7580 if (! target_big_endian
)
7581 expr1
.X_add_number
= off
;
7583 expr1
.X_add_number
= 0;
7584 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7585 (int) BFD_RELOC_LO16
, AT
);
7586 if (! target_big_endian
)
7587 expr1
.X_add_number
= 0;
7589 expr1
.X_add_number
= off
;
7590 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7591 (int) BFD_RELOC_LO16
, AT
);
7597 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7599 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7600 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7601 "d,v,t", AT
, AT
, breg
);
7602 if (target_big_endian
)
7603 expr1
.X_add_number
= 0;
7604 macro_build ((char *) NULL
, &icnt
, &expr1
,
7605 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7606 (int) BFD_RELOC_LO16
, AT
);
7607 if (target_big_endian
)
7608 expr1
.X_add_number
= 1;
7610 expr1
.X_add_number
= 0;
7611 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7612 (int) BFD_RELOC_LO16
, AT
);
7613 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7615 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7620 if (offset_expr
.X_add_number
>= 0x7fff)
7621 as_bad (_("operand overflow"));
7622 if (target_big_endian
)
7623 ++offset_expr
.X_add_number
;
7624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7625 (int) BFD_RELOC_LO16
, breg
);
7626 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7628 if (target_big_endian
)
7629 --offset_expr
.X_add_number
;
7631 ++offset_expr
.X_add_number
;
7632 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7633 (int) BFD_RELOC_LO16
, breg
);
7646 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7647 as_bad (_("operand overflow"));
7648 if (! target_big_endian
)
7649 offset_expr
.X_add_number
+= off
;
7650 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7651 (int) BFD_RELOC_LO16
, breg
);
7652 if (! target_big_endian
)
7653 offset_expr
.X_add_number
-= off
;
7655 offset_expr
.X_add_number
+= off
;
7656 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7657 (int) BFD_RELOC_LO16
, breg
);
7671 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7673 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7674 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7675 "d,v,t", AT
, AT
, breg
);
7676 if (! target_big_endian
)
7677 expr1
.X_add_number
= off
;
7679 expr1
.X_add_number
= 0;
7680 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7681 (int) BFD_RELOC_LO16
, AT
);
7682 if (! target_big_endian
)
7683 expr1
.X_add_number
= 0;
7685 expr1
.X_add_number
= off
;
7686 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7687 (int) BFD_RELOC_LO16
, AT
);
7692 load_address (&icnt
, AT
, &offset_expr
, &used_at
);
7694 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7695 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7696 "d,v,t", AT
, AT
, breg
);
7697 if (! target_big_endian
)
7698 expr1
.X_add_number
= 0;
7699 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7700 (int) BFD_RELOC_LO16
, AT
);
7701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7703 if (! target_big_endian
)
7704 expr1
.X_add_number
= 1;
7706 expr1
.X_add_number
= 0;
7707 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7708 (int) BFD_RELOC_LO16
, AT
);
7709 if (! target_big_endian
)
7710 expr1
.X_add_number
= 0;
7712 expr1
.X_add_number
= 1;
7713 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7714 (int) BFD_RELOC_LO16
, AT
);
7715 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7722 /* FIXME: Check if this is one of the itbl macros, since they
7723 are added dynamically. */
7724 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7728 as_warn (_("Macro used $at after \".set noat\""));
7731 /* Implement macros in mips16 mode. */
7735 struct mips_cl_insn
*ip
;
7738 int xreg
, yreg
, zreg
, tmp
;
7742 const char *s
, *s2
, *s3
;
7744 mask
= ip
->insn_mo
->mask
;
7746 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7747 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7748 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7752 expr1
.X_op
= O_constant
;
7753 expr1
.X_op_symbol
= NULL
;
7754 expr1
.X_add_symbol
= NULL
;
7755 expr1
.X_add_number
= 1;
7774 mips_emit_delays (TRUE
);
7775 ++mips_opts
.noreorder
;
7776 mips_any_noreorder
= 1;
7777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7778 dbl
? "ddiv" : "div",
7779 "0,x,y", xreg
, yreg
);
7780 expr1
.X_add_number
= 2;
7781 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7782 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7785 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7786 since that causes an overflow. We should do that as well,
7787 but I don't see how to do the comparisons without a temporary
7789 --mips_opts
.noreorder
;
7790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7809 mips_emit_delays (TRUE
);
7810 ++mips_opts
.noreorder
;
7811 mips_any_noreorder
= 1;
7812 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7814 expr1
.X_add_number
= 2;
7815 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7818 --mips_opts
.noreorder
;
7819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7826 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7827 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7836 if (imm_expr
.X_op
!= O_constant
)
7837 as_bad (_("Unsupported large constant"));
7838 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7839 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7840 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7844 if (imm_expr
.X_op
!= O_constant
)
7845 as_bad (_("Unsupported large constant"));
7846 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7847 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7852 if (imm_expr
.X_op
!= O_constant
)
7853 as_bad (_("Unsupported large constant"));
7854 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7855 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7878 goto do_reverse_branch
;
7882 goto do_reverse_branch
;
7894 goto do_reverse_branch
;
7905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7907 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7934 goto do_addone_branch_i
;
7939 goto do_addone_branch_i
;
7954 goto do_addone_branch_i
;
7961 if (imm_expr
.X_op
!= O_constant
)
7962 as_bad (_("Unsupported large constant"));
7963 ++imm_expr
.X_add_number
;
7966 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7971 expr1
.X_add_number
= 0;
7972 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7974 move_register (&icnt
, xreg
, yreg
);
7975 expr1
.X_add_number
= 2;
7976 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7978 "neg", "x,w", xreg
, xreg
);
7982 /* For consistency checking, verify that all bits are specified either
7983 by the match/mask part of the instruction definition, or by the
7986 validate_mips_insn (opc
)
7987 const struct mips_opcode
*opc
;
7989 const char *p
= opc
->args
;
7991 unsigned long used_bits
= opc
->mask
;
7993 if ((used_bits
& opc
->match
) != opc
->match
)
7995 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7996 opc
->name
, opc
->args
);
7999 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8006 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8007 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8009 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8010 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8011 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8012 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8014 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8015 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8017 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8019 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8020 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8021 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8022 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8023 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8024 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8025 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8026 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8027 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8028 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8029 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8030 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8031 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8032 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8033 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8034 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8035 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8037 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8038 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8039 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8040 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8042 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8043 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8044 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8045 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8046 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8047 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8048 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8049 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8050 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8053 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8054 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8055 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8056 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8057 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8061 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8062 c
, opc
->name
, opc
->args
);
8066 if (used_bits
!= 0xffffffff)
8068 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8069 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8075 /* This routine assembles an instruction into its binary format. As a
8076 side effect, it sets one of the global variables imm_reloc or
8077 offset_reloc to the type of relocation to do if one of the operands
8078 is an address expression. */
8083 struct mips_cl_insn
*ip
;
8088 struct mips_opcode
*insn
;
8091 unsigned int lastregno
= 0;
8097 /* If the instruction contains a '.', we first try to match an instruction
8098 including the '.'. Then we try again without the '.'. */
8100 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8103 /* If we stopped on whitespace, then replace the whitespace with null for
8104 the call to hash_find. Save the character we replaced just in case we
8105 have to re-parse the instruction. */
8112 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8114 /* If we didn't find the instruction in the opcode table, try again, but
8115 this time with just the instruction up to, but not including the
8119 /* Restore the character we overwrite above (if any). */
8123 /* Scan up to the first '.' or whitespace. */
8125 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8129 /* If we did not find a '.', then we can quit now. */
8132 insn_error
= "unrecognized opcode";
8136 /* Lookup the instruction in the hash table. */
8138 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8140 insn_error
= "unrecognized opcode";
8150 assert (strcmp (insn
->name
, str
) == 0);
8152 if (OPCODE_IS_MEMBER (insn
,
8154 | (file_ase_mips16
? INSN_MIPS16
: 0)
8155 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8156 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8162 if (insn
->pinfo
!= INSN_MACRO
)
8164 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8170 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8171 && strcmp (insn
->name
, insn
[1].name
) == 0)
8180 static char buf
[100];
8181 if (mips_arch_info
->is_isa
)
8183 _("opcode not supported at this ISA level (%s)"),
8184 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8187 _("opcode not supported on this processor: %s (%s)"),
8188 mips_arch_info
->name
,
8189 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8199 ip
->insn_opcode
= insn
->match
;
8201 for (args
= insn
->args
;; ++args
)
8205 s
+= strspn (s
, " \t");
8209 case '\0': /* end of args */
8222 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8226 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8230 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8234 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8240 /* Handle optional base register.
8241 Either the base register is omitted or
8242 we must have a left paren. */
8243 /* This is dependent on the next operand specifier
8244 is a base register specification. */
8245 assert (args
[1] == 'b' || args
[1] == '5'
8246 || args
[1] == '-' || args
[1] == '4');
8250 case ')': /* these must match exactly */
8257 case '<': /* must be at least one digit */
8259 * According to the manual, if the shift amount is greater
8260 * than 31 or less than 0, then the shift amount should be
8261 * mod 32. In reality the mips assembler issues an error.
8262 * We issue a warning and mask out all but the low 5 bits.
8264 my_getExpression (&imm_expr
, s
);
8265 check_absolute_expr (ip
, &imm_expr
);
8266 if ((unsigned long) imm_expr
.X_add_number
> 31)
8268 as_warn (_("Improper shift amount (%lu)"),
8269 (unsigned long) imm_expr
.X_add_number
);
8270 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8272 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8273 imm_expr
.X_op
= O_absent
;
8277 case '>': /* shift amount minus 32 */
8278 my_getExpression (&imm_expr
, s
);
8279 check_absolute_expr (ip
, &imm_expr
);
8280 if ((unsigned long) imm_expr
.X_add_number
< 32
8281 || (unsigned long) imm_expr
.X_add_number
> 63)
8283 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8284 imm_expr
.X_op
= O_absent
;
8288 case 'k': /* cache code */
8289 case 'h': /* prefx code */
8290 my_getExpression (&imm_expr
, s
);
8291 check_absolute_expr (ip
, &imm_expr
);
8292 if ((unsigned long) imm_expr
.X_add_number
> 31)
8294 as_warn (_("Invalid value for `%s' (%lu)"),
8296 (unsigned long) imm_expr
.X_add_number
);
8297 imm_expr
.X_add_number
&= 0x1f;
8300 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8302 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8303 imm_expr
.X_op
= O_absent
;
8307 case 'c': /* break code */
8308 my_getExpression (&imm_expr
, s
);
8309 check_absolute_expr (ip
, &imm_expr
);
8310 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8312 as_warn (_("Illegal break code (%lu)"),
8313 (unsigned long) imm_expr
.X_add_number
);
8314 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8316 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8317 imm_expr
.X_op
= O_absent
;
8321 case 'q': /* lower break code */
8322 my_getExpression (&imm_expr
, s
);
8323 check_absolute_expr (ip
, &imm_expr
);
8324 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8326 as_warn (_("Illegal lower break code (%lu)"),
8327 (unsigned long) imm_expr
.X_add_number
);
8328 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8330 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8331 imm_expr
.X_op
= O_absent
;
8335 case 'B': /* 20-bit syscall/break code. */
8336 my_getExpression (&imm_expr
, s
);
8337 check_absolute_expr (ip
, &imm_expr
);
8338 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8339 as_warn (_("Illegal 20-bit code (%lu)"),
8340 (unsigned long) imm_expr
.X_add_number
);
8341 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8342 imm_expr
.X_op
= O_absent
;
8346 case 'C': /* Coprocessor code */
8347 my_getExpression (&imm_expr
, s
);
8348 check_absolute_expr (ip
, &imm_expr
);
8349 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8351 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8352 (unsigned long) imm_expr
.X_add_number
);
8353 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8355 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8356 imm_expr
.X_op
= O_absent
;
8360 case 'J': /* 19-bit wait code. */
8361 my_getExpression (&imm_expr
, s
);
8362 check_absolute_expr (ip
, &imm_expr
);
8363 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8364 as_warn (_("Illegal 19-bit code (%lu)"),
8365 (unsigned long) imm_expr
.X_add_number
);
8366 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8367 imm_expr
.X_op
= O_absent
;
8371 case 'P': /* Performance register */
8372 my_getExpression (&imm_expr
, s
);
8373 check_absolute_expr (ip
, &imm_expr
);
8374 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8376 as_warn (_("Invalid performance register (%lu)"),
8377 (unsigned long) imm_expr
.X_add_number
);
8378 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8380 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8381 imm_expr
.X_op
= O_absent
;
8385 case 'b': /* base register */
8386 case 'd': /* destination register */
8387 case 's': /* source register */
8388 case 't': /* target register */
8389 case 'r': /* both target and source */
8390 case 'v': /* both dest and source */
8391 case 'w': /* both dest and target */
8392 case 'E': /* coprocessor target register */
8393 case 'G': /* coprocessor destination register */
8394 case 'x': /* ignore register name */
8395 case 'z': /* must be zero register */
8396 case 'U': /* destination register (clo/clz). */
8411 while (ISDIGIT (*s
));
8413 as_bad (_("Invalid register number (%d)"), regno
);
8415 else if (*args
== 'E' || *args
== 'G')
8419 if (s
[1] == 'r' && s
[2] == 'a')
8424 else if (s
[1] == 'f' && s
[2] == 'p')
8429 else if (s
[1] == 's' && s
[2] == 'p')
8434 else if (s
[1] == 'g' && s
[2] == 'p')
8439 else if (s
[1] == 'a' && s
[2] == 't')
8444 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8449 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8454 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8459 else if (itbl_have_entries
)
8464 p
= s
+ 1; /* advance past '$' */
8465 n
= itbl_get_field (&p
); /* n is name */
8467 /* See if this is a register defined in an
8469 if (itbl_get_reg_val (n
, &r
))
8471 /* Get_field advances to the start of
8472 the next field, so we need to back
8473 rack to the end of the last field. */
8477 s
= strchr (s
, '\0');
8490 as_warn (_("Used $at without \".set noat\""));
8496 if (c
== 'r' || c
== 'v' || c
== 'w')
8503 /* 'z' only matches $0. */
8504 if (c
== 'z' && regno
!= 0)
8507 /* Now that we have assembled one operand, we use the args string
8508 * to figure out where it goes in the instruction. */
8515 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8519 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8522 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8523 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8528 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8531 /* This case exists because on the r3000 trunc
8532 expands into a macro which requires a gp
8533 register. On the r6000 or r4000 it is
8534 assembled into a single instruction which
8535 ignores the register. Thus the insn version
8536 is MIPS_ISA2 and uses 'x', and the macro
8537 version is MIPS_ISA1 and uses 't'. */
8540 /* This case is for the div instruction, which
8541 acts differently if the destination argument
8542 is $0. This only matches $0, and is checked
8543 outside the switch. */
8546 /* Itbl operand; not yet implemented. FIXME ?? */
8548 /* What about all other operands like 'i', which
8549 can be specified in the opcode table? */
8559 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8562 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8567 case 'O': /* MDMX alignment immediate constant. */
8568 my_getExpression (&imm_expr
, s
);
8569 check_absolute_expr (ip
, &imm_expr
);
8570 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8572 as_warn ("Improper align amount (%ld), using low bits",
8573 (long) imm_expr
.X_add_number
);
8574 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8576 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8577 imm_expr
.X_op
= O_absent
;
8581 case 'Q': /* MDMX vector, element sel, or const. */
8584 /* MDMX Immediate. */
8585 my_getExpression (&imm_expr
, s
);
8586 check_absolute_expr (ip
, &imm_expr
);
8587 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8589 as_warn (_("Invalid MDMX Immediate (%ld)"),
8590 (long) imm_expr
.X_add_number
);
8591 imm_expr
.X_add_number
&= OP_MASK_FT
;
8593 imm_expr
.X_add_number
&= OP_MASK_FT
;
8594 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8595 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8597 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8598 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8599 imm_expr
.X_op
= O_absent
;
8603 /* Not MDMX Immediate. Fall through. */
8604 case 'X': /* MDMX destination register. */
8605 case 'Y': /* MDMX source register. */
8606 case 'Z': /* MDMX target register. */
8608 case 'D': /* floating point destination register */
8609 case 'S': /* floating point source register */
8610 case 'T': /* floating point target register */
8611 case 'R': /* floating point source register */
8615 /* Accept $fN for FP and MDMX register numbers, and in
8616 addition accept $vN for MDMX register numbers. */
8617 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8618 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8629 while (ISDIGIT (*s
));
8632 as_bad (_("Invalid float register number (%d)"), regno
);
8634 if ((regno
& 1) != 0
8636 && ! (strcmp (str
, "mtc1") == 0
8637 || strcmp (str
, "mfc1") == 0
8638 || strcmp (str
, "lwc1") == 0
8639 || strcmp (str
, "swc1") == 0
8640 || strcmp (str
, "l.s") == 0
8641 || strcmp (str
, "s.s") == 0))
8642 as_warn (_("Float register should be even, was %d"),
8650 if (c
== 'V' || c
== 'W')
8661 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8666 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8669 /* This is like 'Z', but also needs to fix the MDMX
8670 vector/scalar select bits. Note that the
8671 scalar immediate case is handled above. */
8674 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8675 int max_el
= (is_qh
? 3 : 7);
8677 my_getExpression(&imm_expr
, s
);
8678 check_absolute_expr (ip
, &imm_expr
);
8680 if (imm_expr
.X_add_number
> max_el
)
8681 as_bad(_("Bad element selector %ld"),
8682 (long) imm_expr
.X_add_number
);
8683 imm_expr
.X_add_number
&= max_el
;
8684 ip
->insn_opcode
|= (imm_expr
.X_add_number
8688 as_warn(_("Expecting ']' found '%s'"), s
);
8694 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8695 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8698 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8705 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8708 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8718 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8721 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8727 my_getExpression (&imm_expr
, s
);
8728 if (imm_expr
.X_op
!= O_big
8729 && imm_expr
.X_op
!= O_constant
)
8730 insn_error
= _("absolute expression required");
8735 my_getExpression (&offset_expr
, s
);
8736 *imm_reloc
= BFD_RELOC_32
;
8749 unsigned char temp
[8];
8751 unsigned int length
;
8756 /* These only appear as the last operand in an
8757 instruction, and every instruction that accepts
8758 them in any variant accepts them in all variants.
8759 This means we don't have to worry about backing out
8760 any changes if the instruction does not match.
8762 The difference between them is the size of the
8763 floating point constant and where it goes. For 'F'
8764 and 'L' the constant is 64 bits; for 'f' and 'l' it
8765 is 32 bits. Where the constant is placed is based
8766 on how the MIPS assembler does things:
8769 f -- immediate value
8772 The .lit4 and .lit8 sections are only used if
8773 permitted by the -G argument.
8775 When generating embedded PIC code, we use the
8776 .lit8 section but not the .lit4 section (we can do
8777 .lit4 inline easily; we need to put .lit8
8778 somewhere in the data segment, and using .lit8
8779 permits the linker to eventually combine identical
8782 The code below needs to know whether the target register
8783 is 32 or 64 bits wide. It relies on the fact 'f' and
8784 'F' are used with GPR-based instructions and 'l' and
8785 'L' are used with FPR-based instructions. */
8787 f64
= *args
== 'F' || *args
== 'L';
8788 using_gprs
= *args
== 'F' || *args
== 'f';
8790 save_in
= input_line_pointer
;
8791 input_line_pointer
= s
;
8792 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8794 s
= input_line_pointer
;
8795 input_line_pointer
= save_in
;
8796 if (err
!= NULL
&& *err
!= '\0')
8798 as_bad (_("Bad floating point constant: %s"), err
);
8799 memset (temp
, '\0', sizeof temp
);
8800 length
= f64
? 8 : 4;
8803 assert (length
== (unsigned) (f64
? 8 : 4));
8807 && (! USE_GLOBAL_POINTER_OPT
8808 || mips_pic
== EMBEDDED_PIC
8809 || g_switch_value
< 4
8810 || (temp
[0] == 0 && temp
[1] == 0)
8811 || (temp
[2] == 0 && temp
[3] == 0))))
8813 imm_expr
.X_op
= O_constant
;
8814 if (! target_big_endian
)
8815 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8817 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8820 && ! mips_disable_float_construction
8821 /* Constants can only be constructed in GPRs and
8822 copied to FPRs if the GPRs are at least as wide
8823 as the FPRs. Force the constant into memory if
8824 we are using 64-bit FPRs but the GPRs are only
8827 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8828 && ((temp
[0] == 0 && temp
[1] == 0)
8829 || (temp
[2] == 0 && temp
[3] == 0))
8830 && ((temp
[4] == 0 && temp
[5] == 0)
8831 || (temp
[6] == 0 && temp
[7] == 0)))
8833 /* The value is simple enough to load with a couple of
8834 instructions. If using 32-bit registers, set
8835 imm_expr to the high order 32 bits and offset_expr to
8836 the low order 32 bits. Otherwise, set imm_expr to
8837 the entire 64 bit constant. */
8838 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8840 imm_expr
.X_op
= O_constant
;
8841 offset_expr
.X_op
= O_constant
;
8842 if (! target_big_endian
)
8844 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8845 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8849 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8850 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8852 if (offset_expr
.X_add_number
== 0)
8853 offset_expr
.X_op
= O_absent
;
8855 else if (sizeof (imm_expr
.X_add_number
) > 4)
8857 imm_expr
.X_op
= O_constant
;
8858 if (! target_big_endian
)
8859 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8861 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8865 imm_expr
.X_op
= O_big
;
8866 imm_expr
.X_add_number
= 4;
8867 if (! target_big_endian
)
8869 generic_bignum
[0] = bfd_getl16 (temp
);
8870 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8871 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8872 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8876 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8877 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8878 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8879 generic_bignum
[3] = bfd_getb16 (temp
);
8885 const char *newname
;
8888 /* Switch to the right section. */
8890 subseg
= now_subseg
;
8893 default: /* unused default case avoids warnings. */
8895 newname
= RDATA_SECTION_NAME
;
8896 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8897 || mips_pic
== EMBEDDED_PIC
)
8901 if (mips_pic
== EMBEDDED_PIC
)
8904 newname
= RDATA_SECTION_NAME
;
8907 assert (!USE_GLOBAL_POINTER_OPT
8908 || g_switch_value
>= 4);
8912 new_seg
= subseg_new (newname
, (subsegT
) 0);
8913 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8914 bfd_set_section_flags (stdoutput
, new_seg
,
8919 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8920 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8921 && strcmp (TARGET_OS
, "elf") != 0)
8922 record_alignment (new_seg
, 4);
8924 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8926 as_bad (_("Can't use floating point insn in this section"));
8928 /* Set the argument to the current address in the
8930 offset_expr
.X_op
= O_symbol
;
8931 offset_expr
.X_add_symbol
=
8932 symbol_new ("L0\001", now_seg
,
8933 (valueT
) frag_now_fix (), frag_now
);
8934 offset_expr
.X_add_number
= 0;
8936 /* Put the floating point number into the section. */
8937 p
= frag_more ((int) length
);
8938 memcpy (p
, temp
, length
);
8940 /* Switch back to the original section. */
8941 subseg_set (seg
, subseg
);
8946 case 'i': /* 16 bit unsigned immediate */
8947 case 'j': /* 16 bit signed immediate */
8948 *imm_reloc
= BFD_RELOC_LO16
;
8949 c
= my_getSmallExpression (&imm_expr
, s
);
8956 *imm_reloc
= BFD_RELOC_HI16_S
;
8957 imm_unmatched_hi
= TRUE
;
8960 else if (c
== S_EX_HIGHEST
)
8961 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8962 else if (c
== S_EX_HIGHER
)
8963 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8964 else if (c
== S_EX_GP_REL
)
8966 /* This occurs in NewABI only. */
8967 c
= my_getSmallExpression (&imm_expr
, s
);
8969 as_bad (_("bad composition of relocations"));
8972 c
= my_getSmallExpression (&imm_expr
, s
);
8974 as_bad (_("bad composition of relocations"));
8977 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8978 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8979 imm_reloc
[2] = BFD_RELOC_LO16
;
8985 *imm_reloc
= BFD_RELOC_HI16
;
8987 else if (imm_expr
.X_op
== O_constant
)
8988 imm_expr
.X_add_number
&= 0xffff;
8992 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8993 || ((imm_expr
.X_add_number
< 0
8994 || imm_expr
.X_add_number
>= 0x10000)
8995 && imm_expr
.X_op
== O_constant
))
8997 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8998 !strcmp (insn
->name
, insn
[1].name
))
9000 if (imm_expr
.X_op
== O_constant
9001 || imm_expr
.X_op
== O_big
)
9002 as_bad (_("16 bit expression not in range 0..65535"));
9010 /* The upper bound should be 0x8000, but
9011 unfortunately the MIPS assembler accepts numbers
9012 from 0x8000 to 0xffff and sign extends them, and
9013 we want to be compatible. We only permit this
9014 extended range for an instruction which does not
9015 provide any further alternates, since those
9016 alternates may handle other cases. People should
9017 use the numbers they mean, rather than relying on
9018 a mysterious sign extension. */
9019 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9020 strcmp (insn
->name
, insn
[1].name
) == 0);
9025 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
9026 || ((imm_expr
.X_add_number
< -0x8000
9027 || imm_expr
.X_add_number
>= max
)
9028 && imm_expr
.X_op
== O_constant
)
9030 && imm_expr
.X_add_number
< 0
9032 && imm_expr
.X_unsigned
9033 && sizeof (imm_expr
.X_add_number
) <= 4))
9037 if (imm_expr
.X_op
== O_constant
9038 || imm_expr
.X_op
== O_big
)
9039 as_bad (_("16 bit expression not in range -32768..32767"));
9045 case 'o': /* 16 bit offset */
9046 c
= my_getSmallExpression (&offset_expr
, s
);
9048 /* If this value won't fit into a 16 bit offset, then go
9049 find a macro that will generate the 32 bit offset
9052 && (offset_expr
.X_op
!= O_constant
9053 || offset_expr
.X_add_number
>= 0x8000
9054 || offset_expr
.X_add_number
< -0x8000))
9059 if (offset_expr
.X_op
!= O_constant
)
9061 offset_expr
.X_add_number
=
9062 (offset_expr
.X_add_number
>> 16) & 0xffff;
9064 *offset_reloc
= BFD_RELOC_LO16
;
9068 case 'p': /* pc relative offset */
9069 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9070 my_getExpression (&offset_expr
, s
);
9074 case 'u': /* upper 16 bits */
9075 c
= my_getSmallExpression (&imm_expr
, s
);
9076 *imm_reloc
= BFD_RELOC_LO16
;
9083 *imm_reloc
= BFD_RELOC_HI16_S
;
9084 imm_unmatched_hi
= TRUE
;
9087 else if (c
== S_EX_HIGHEST
)
9088 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
9089 else if (c
== S_EX_GP_REL
)
9091 /* This occurs in NewABI only. */
9092 c
= my_getSmallExpression (&imm_expr
, s
);
9094 as_bad (_("bad composition of relocations"));
9097 c
= my_getSmallExpression (&imm_expr
, s
);
9099 as_bad (_("bad composition of relocations"));
9102 imm_reloc
[0] = BFD_RELOC_GPREL16
;
9103 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
9104 imm_reloc
[2] = BFD_RELOC_HI16_S
;
9110 *imm_reloc
= BFD_RELOC_HI16
;
9112 else if (imm_expr
.X_op
== O_constant
)
9113 imm_expr
.X_add_number
&= 0xffff;
9115 else if (imm_expr
.X_op
== O_constant
9116 && (imm_expr
.X_add_number
< 0
9117 || imm_expr
.X_add_number
>= 0x10000))
9118 as_bad (_("lui expression not in range 0..65535"));
9122 case 'a': /* 26 bit address */
9123 my_getExpression (&offset_expr
, s
);
9125 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9128 case 'N': /* 3 bit branch condition code */
9129 case 'M': /* 3 bit compare condition code */
9130 if (strncmp (s
, "$fcc", 4) != 0)
9140 while (ISDIGIT (*s
));
9142 as_bad (_("invalid condition code register $fcc%d"), regno
);
9144 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9146 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9150 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9161 while (ISDIGIT (*s
));
9164 c
= 8; /* Invalid sel value. */
9167 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9168 ip
->insn_opcode
|= c
;
9172 /* Must be at least one digit. */
9173 my_getExpression (&imm_expr
, s
);
9174 check_absolute_expr (ip
, &imm_expr
);
9176 if ((unsigned long) imm_expr
.X_add_number
9177 > (unsigned long) OP_MASK_VECBYTE
)
9179 as_bad (_("bad byte vector index (%ld)"),
9180 (long) imm_expr
.X_add_number
);
9181 imm_expr
.X_add_number
= 0;
9184 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9185 imm_expr
.X_op
= O_absent
;
9190 my_getExpression (&imm_expr
, s
);
9191 check_absolute_expr (ip
, &imm_expr
);
9193 if ((unsigned long) imm_expr
.X_add_number
9194 > (unsigned long) OP_MASK_VECALIGN
)
9196 as_bad (_("bad byte vector index (%ld)"),
9197 (long) imm_expr
.X_add_number
);
9198 imm_expr
.X_add_number
= 0;
9201 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9202 imm_expr
.X_op
= O_absent
;
9207 as_bad (_("bad char = '%c'\n"), *args
);
9212 /* Args don't match. */
9213 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9214 !strcmp (insn
->name
, insn
[1].name
))
9218 insn_error
= _("illegal operands");
9223 insn_error
= _("illegal operands");
9228 /* This routine assembles an instruction into its binary format when
9229 assembling for the mips16. As a side effect, it sets one of the
9230 global variables imm_reloc or offset_reloc to the type of
9231 relocation to do if one of the operands is an address expression.
9232 It also sets mips16_small and mips16_ext if the user explicitly
9233 requested a small or extended instruction. */
9238 struct mips_cl_insn
*ip
;
9242 struct mips_opcode
*insn
;
9245 unsigned int lastregno
= 0;
9250 mips16_small
= FALSE
;
9253 for (s
= str
; ISLOWER (*s
); ++s
)
9265 if (s
[1] == 't' && s
[2] == ' ')
9268 mips16_small
= TRUE
;
9272 else if (s
[1] == 'e' && s
[2] == ' ')
9281 insn_error
= _("unknown opcode");
9285 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9286 mips16_small
= TRUE
;
9288 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9290 insn_error
= _("unrecognized opcode");
9297 assert (strcmp (insn
->name
, str
) == 0);
9300 ip
->insn_opcode
= insn
->match
;
9301 ip
->use_extend
= FALSE
;
9302 imm_expr
.X_op
= O_absent
;
9303 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9304 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9305 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9306 offset_expr
.X_op
= O_absent
;
9307 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9308 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9309 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9310 for (args
= insn
->args
; 1; ++args
)
9317 /* In this switch statement we call break if we did not find
9318 a match, continue if we did find a match, or return if we
9327 /* Stuff the immediate value in now, if we can. */
9328 if (imm_expr
.X_op
== O_constant
9329 && *imm_reloc
> BFD_RELOC_UNUSED
9330 && insn
->pinfo
!= INSN_MACRO
)
9332 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9333 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9334 mips16_ext
, &ip
->insn_opcode
,
9335 &ip
->use_extend
, &ip
->extend
);
9336 imm_expr
.X_op
= O_absent
;
9337 *imm_reloc
= BFD_RELOC_UNUSED
;
9351 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9354 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9370 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9372 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9399 while (ISDIGIT (*s
));
9402 as_bad (_("invalid register number (%d)"), regno
);
9408 if (s
[1] == 'r' && s
[2] == 'a')
9413 else if (s
[1] == 'f' && s
[2] == 'p')
9418 else if (s
[1] == 's' && s
[2] == 'p')
9423 else if (s
[1] == 'g' && s
[2] == 'p')
9428 else if (s
[1] == 'a' && s
[2] == 't')
9433 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9438 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9443 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9456 if (c
== 'v' || c
== 'w')
9458 regno
= mips16_to_32_reg_map
[lastregno
];
9472 regno
= mips32_to_16_reg_map
[regno
];
9477 regno
= ILLEGAL_REG
;
9482 regno
= ILLEGAL_REG
;
9487 regno
= ILLEGAL_REG
;
9492 if (regno
== AT
&& ! mips_opts
.noat
)
9493 as_warn (_("used $at without \".set noat\""));
9500 if (regno
== ILLEGAL_REG
)
9507 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9511 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9514 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9517 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9523 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9526 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9527 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9537 if (strncmp (s
, "$pc", 3) == 0)
9561 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9563 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9564 and generate the appropriate reloc. If the text
9565 inside %gprel is not a symbol name with an
9566 optional offset, then we generate a normal reloc
9567 and will probably fail later. */
9568 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9569 if (imm_expr
.X_op
== O_symbol
)
9572 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9574 ip
->use_extend
= TRUE
;
9581 /* Just pick up a normal expression. */
9582 my_getExpression (&imm_expr
, s
);
9585 if (imm_expr
.X_op
== O_register
)
9587 /* What we thought was an expression turned out to
9590 if (s
[0] == '(' && args
[1] == '(')
9592 /* It looks like the expression was omitted
9593 before a register indirection, which means
9594 that the expression is implicitly zero. We
9595 still set up imm_expr, so that we handle
9596 explicit extensions correctly. */
9597 imm_expr
.X_op
= O_constant
;
9598 imm_expr
.X_add_number
= 0;
9599 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9606 /* We need to relax this instruction. */
9607 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9616 /* We use offset_reloc rather than imm_reloc for the PC
9617 relative operands. This lets macros with both
9618 immediate and address operands work correctly. */
9619 my_getExpression (&offset_expr
, s
);
9621 if (offset_expr
.X_op
== O_register
)
9624 /* We need to relax this instruction. */
9625 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9629 case '6': /* break code */
9630 my_getExpression (&imm_expr
, s
);
9631 check_absolute_expr (ip
, &imm_expr
);
9632 if ((unsigned long) imm_expr
.X_add_number
> 63)
9634 as_warn (_("Invalid value for `%s' (%lu)"),
9636 (unsigned long) imm_expr
.X_add_number
);
9637 imm_expr
.X_add_number
&= 0x3f;
9639 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9640 imm_expr
.X_op
= O_absent
;
9644 case 'a': /* 26 bit address */
9645 my_getExpression (&offset_expr
, s
);
9647 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9648 ip
->insn_opcode
<<= 16;
9651 case 'l': /* register list for entry macro */
9652 case 'L': /* register list for exit macro */
9662 int freg
, reg1
, reg2
;
9664 while (*s
== ' ' || *s
== ',')
9668 as_bad (_("can't parse register list"));
9680 while (ISDIGIT (*s
))
9702 as_bad (_("invalid register list"));
9707 while (ISDIGIT (*s
))
9714 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9719 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9724 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9725 mask
|= (reg2
- 3) << 3;
9726 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9727 mask
|= (reg2
- 15) << 1;
9728 else if (reg1
== RA
&& reg2
== RA
)
9732 as_bad (_("invalid register list"));
9736 /* The mask is filled in in the opcode table for the
9737 benefit of the disassembler. We remove it before
9738 applying the actual mask. */
9739 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9740 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9744 case 'e': /* extend code */
9745 my_getExpression (&imm_expr
, s
);
9746 check_absolute_expr (ip
, &imm_expr
);
9747 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9749 as_warn (_("Invalid value for `%s' (%lu)"),
9751 (unsigned long) imm_expr
.X_add_number
);
9752 imm_expr
.X_add_number
&= 0x7ff;
9754 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9755 imm_expr
.X_op
= O_absent
;
9765 /* Args don't match. */
9766 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9767 strcmp (insn
->name
, insn
[1].name
) == 0)
9774 insn_error
= _("illegal operands");
9780 /* This structure holds information we know about a mips16 immediate
9783 struct mips16_immed_operand
9785 /* The type code used in the argument string in the opcode table. */
9787 /* The number of bits in the short form of the opcode. */
9789 /* The number of bits in the extended form of the opcode. */
9791 /* The amount by which the short form is shifted when it is used;
9792 for example, the sw instruction has a shift count of 2. */
9794 /* The amount by which the short form is shifted when it is stored
9795 into the instruction code. */
9797 /* Non-zero if the short form is unsigned. */
9799 /* Non-zero if the extended form is unsigned. */
9801 /* Non-zero if the value is PC relative. */
9805 /* The mips16 immediate operand types. */
9807 static const struct mips16_immed_operand mips16_immed_operands
[] =
9809 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9810 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9811 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9812 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9813 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9814 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9815 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9816 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9817 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9818 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9819 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9820 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9821 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9822 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9823 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9824 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9825 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9826 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9827 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9828 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9829 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9832 #define MIPS16_NUM_IMMED \
9833 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9835 /* Handle a mips16 instruction with an immediate value. This or's the
9836 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9837 whether an extended value is needed; if one is needed, it sets
9838 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9839 If SMALL is true, an unextended opcode was explicitly requested.
9840 If EXT is true, an extended opcode was explicitly requested. If
9841 WARN is true, warn if EXT does not match reality. */
9844 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9853 unsigned long *insn
;
9854 bfd_boolean
*use_extend
;
9855 unsigned short *extend
;
9857 register const struct mips16_immed_operand
*op
;
9858 int mintiny
, maxtiny
;
9859 bfd_boolean needext
;
9861 op
= mips16_immed_operands
;
9862 while (op
->type
!= type
)
9865 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9870 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9873 maxtiny
= 1 << op
->nbits
;
9878 maxtiny
= (1 << op
->nbits
) - 1;
9883 mintiny
= - (1 << (op
->nbits
- 1));
9884 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9887 /* Branch offsets have an implicit 0 in the lowest bit. */
9888 if (type
== 'p' || type
== 'q')
9891 if ((val
& ((1 << op
->shift
) - 1)) != 0
9892 || val
< (mintiny
<< op
->shift
)
9893 || val
> (maxtiny
<< op
->shift
))
9898 if (warn
&& ext
&& ! needext
)
9899 as_warn_where (file
, line
,
9900 _("extended operand requested but not required"));
9901 if (small
&& needext
)
9902 as_bad_where (file
, line
, _("invalid unextended operand value"));
9904 if (small
|| (! ext
&& ! needext
))
9908 *use_extend
= FALSE
;
9909 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9910 insnval
<<= op
->op_shift
;
9915 long minext
, maxext
;
9921 maxext
= (1 << op
->extbits
) - 1;
9925 minext
= - (1 << (op
->extbits
- 1));
9926 maxext
= (1 << (op
->extbits
- 1)) - 1;
9928 if (val
< minext
|| val
> maxext
)
9929 as_bad_where (file
, line
,
9930 _("operand value out of range for instruction"));
9933 if (op
->extbits
== 16)
9935 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9938 else if (op
->extbits
== 15)
9940 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9945 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9949 *extend
= (unsigned short) extval
;
9954 static struct percent_op_match
9957 const enum small_ex_type type
;
9962 {"%call_hi", S_EX_CALL_HI
},
9963 {"%call_lo", S_EX_CALL_LO
},
9964 {"%call16", S_EX_CALL16
},
9965 {"%got_disp", S_EX_GOT_DISP
},
9966 {"%got_page", S_EX_GOT_PAGE
},
9967 {"%got_ofst", S_EX_GOT_OFST
},
9968 {"%got_hi", S_EX_GOT_HI
},
9969 {"%got_lo", S_EX_GOT_LO
},
9971 {"%gp_rel", S_EX_GP_REL
},
9972 {"%half", S_EX_HALF
},
9973 {"%highest", S_EX_HIGHEST
},
9974 {"%higher", S_EX_HIGHER
},
9980 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9981 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9982 can be nested, this is handled by blanking the innermost, parsing the
9983 rest by subsequent calls. */
9986 my_getSmallParser (str
, len
, nestlevel
)
9992 *str
+= strspn (*str
, " \t");
9993 /* Check for expression in parentheses. */
9996 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9999 /* Check for base register. */
10002 if (strchr (b
, ')')
10003 && (e
= b
+ strcspn (b
, ") \t"))
10004 && e
- b
> 1 && e
- b
< 4)
10007 && ((b
[1] == 'f' && b
[2] == 'p')
10008 || (b
[1] == 's' && b
[2] == 'p')
10009 || (b
[1] == 'g' && b
[2] == 'p')
10010 || (b
[1] == 'a' && b
[2] == 't')
10012 && ISDIGIT (b
[2]))))
10013 || (ISDIGIT (b
[1])))
10015 *len
= strcspn (*str
, ")") + 1;
10016 return S_EX_REGISTER
;
10020 /* Check for percent_op (in parentheses). */
10021 else if (b
[0] == '%')
10024 return my_getPercentOp (str
, len
, nestlevel
);
10027 /* Some other expression in the parentheses, which can contain
10028 parentheses itself. Attempt to find the matching one. */
10034 for (s
= *str
+ 1; *s
&& pcnt
; s
++, (*len
)++)
10038 else if (*s
== ')')
10043 /* Check for percent_op (outside of parentheses). */
10044 else if (*str
[0] == '%')
10045 return my_getPercentOp (str
, len
, nestlevel
);
10047 /* Any other expression. */
10052 my_getPercentOp (str
, len
, nestlevel
)
10057 char *tmp
= *str
+ 1;
10058 unsigned int i
= 0;
10060 while (ISALPHA (*tmp
) || *tmp
== '_')
10062 *tmp
= TOLOWER (*tmp
);
10065 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
10067 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
10071 int type
= percent_op
[i
].type
;
10073 /* Only %hi and %lo are allowed for OldABI. */
10074 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
10077 *len
= strlen (percent_op
[i
].str
);
10086 my_getSmallExpression (ep
, str
)
10090 static char *oldstr
= NULL
;
10093 int nestlevel
= -1;
10096 /* Don't update oldstr if the last call had nested percent_op's. We need
10097 it to parse the outer ones later. */
10104 c
= my_getSmallParser (&str
, &len
, &nestlevel
);
10105 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
10108 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
10110 if (nestlevel
>= 0)
10112 /* A percent_op was encountered. Don't try to get an expression if
10113 it is already blanked out. */
10114 if (*(str
+ strspn (str
+ 1, " )")) != ')')
10118 /* Let my_getExpression() stop at the closing parenthesis. */
10119 save
= *(str
+ len
);
10120 *(str
+ len
) = '\0';
10121 my_getExpression (ep
, str
);
10122 *(str
+ len
) = save
;
10126 /* Blank out including the % sign and the proper matching
10129 char *s
= strrchr (oldstr
, '%');
10132 for (end
= strchr (s
, '(') + 1; *end
&& pcnt
; end
++)
10136 else if (*end
== ')')
10140 memset (s
, ' ', end
- s
);
10144 expr_end
= str
+ len
;
10148 else if (c
== S_EX_NONE
)
10150 my_getExpression (ep
, str
);
10152 else if (c
== S_EX_REGISTER
)
10154 ep
->X_op
= O_constant
;
10156 ep
->X_add_symbol
= NULL
;
10157 ep
->X_op_symbol
= NULL
;
10158 ep
->X_add_number
= 0;
10162 as_fatal (_("internal error"));
10165 if (nestlevel
<= 0)
10166 /* All percent_op's have been handled. */
10173 my_getExpression (ep
, str
)
10180 save_in
= input_line_pointer
;
10181 input_line_pointer
= str
;
10183 expr_end
= input_line_pointer
;
10184 input_line_pointer
= save_in
;
10186 /* If we are in mips16 mode, and this is an expression based on `.',
10187 then we bump the value of the symbol by 1 since that is how other
10188 text symbols are handled. We don't bother to handle complex
10189 expressions, just `.' plus or minus a constant. */
10190 if (mips_opts
.mips16
10191 && ep
->X_op
== O_symbol
10192 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10193 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10194 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10195 && symbol_constant_p (ep
->X_add_symbol
)
10196 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10197 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10200 /* Turn a string in input_line_pointer into a floating point constant
10201 of type TYPE, and store the appropriate bytes in *LITP. The number
10202 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10203 returned, or NULL on OK. */
10206 md_atof (type
, litP
, sizeP
)
10212 LITTLENUM_TYPE words
[4];
10228 return _("bad call to md_atof");
10231 t
= atof_ieee (input_line_pointer
, type
, words
);
10233 input_line_pointer
= t
;
10237 if (! target_big_endian
)
10239 for (i
= prec
- 1; i
>= 0; i
--)
10241 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10247 for (i
= 0; i
< prec
; i
++)
10249 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
10258 md_number_to_chars (buf
, val
, n
)
10263 if (target_big_endian
)
10264 number_to_chars_bigendian (buf
, val
, n
);
10266 number_to_chars_littleendian (buf
, val
, n
);
10270 static int support_64bit_objects(void)
10272 const char **list
, **l
;
10275 list
= bfd_target_list ();
10276 for (l
= list
; *l
!= NULL
; l
++)
10278 /* This is traditional mips */
10279 if (strcmp (*l
, "elf64-tradbigmips") == 0
10280 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10282 if (strcmp (*l
, "elf64-bigmips") == 0
10283 || strcmp (*l
, "elf64-littlemips") == 0)
10286 yes
= (*l
!= NULL
);
10290 #endif /* OBJ_ELF */
10292 const char *md_shortopts
= "nO::g::G:";
10294 struct option md_longopts
[] =
10296 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
10297 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10298 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10299 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
10300 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10301 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
10302 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10303 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
10304 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10305 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
10306 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10307 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
10308 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10309 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
10310 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10311 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
10312 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10313 #define OPTION_TRAP (OPTION_MD_BASE + 9)
10314 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10315 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10316 #define OPTION_BREAK (OPTION_MD_BASE + 10)
10317 {"break", no_argument
, NULL
, OPTION_BREAK
},
10318 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10319 #define OPTION_EB (OPTION_MD_BASE + 11)
10320 {"EB", no_argument
, NULL
, OPTION_EB
},
10321 #define OPTION_EL (OPTION_MD_BASE + 12)
10322 {"EL", no_argument
, NULL
, OPTION_EL
},
10323 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
10324 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10325 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
10326 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10327 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
10328 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10329 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
10330 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10331 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10332 #define OPTION_FP32 (OPTION_MD_BASE + 17)
10333 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10334 #define OPTION_GP32 (OPTION_MD_BASE + 18)
10335 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10336 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
10337 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10338 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
10339 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10340 #define OPTION_MARCH (OPTION_MD_BASE + 21)
10341 {"march", required_argument
, NULL
, OPTION_MARCH
},
10342 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
10343 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10344 #define OPTION_FP64 (OPTION_MD_BASE + 23)
10345 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10346 #define OPTION_M4650 (OPTION_MD_BASE + 24)
10347 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10348 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
10349 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10350 #define OPTION_M4010 (OPTION_MD_BASE + 26)
10351 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10352 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
10353 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10354 #define OPTION_M4100 (OPTION_MD_BASE + 28)
10355 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10356 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
10357 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10358 #define OPTION_M3900 (OPTION_MD_BASE + 30)
10359 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10360 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
10361 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10362 #define OPTION_GP64 (OPTION_MD_BASE + 32)
10363 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10364 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
10365 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10366 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
10367 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10368 #define OPTION_MDMX (OPTION_MD_BASE + 35)
10369 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10370 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
10371 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10372 #define OPTION_FIX_VR4122 (OPTION_MD_BASE + 37)
10373 #define OPTION_NO_FIX_VR4122 (OPTION_MD_BASE + 38)
10374 {"mfix-vr4122-bugs", no_argument
, NULL
, OPTION_FIX_VR4122
},
10375 {"no-mfix-vr4122-bugs", no_argument
, NULL
, OPTION_NO_FIX_VR4122
},
10376 #define OPTION_RELAX_BRANCH (OPTION_MD_BASE + 39)
10377 #define OPTION_NO_RELAX_BRANCH (OPTION_MD_BASE + 40)
10378 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10379 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10381 #define OPTION_ELF_BASE (OPTION_MD_BASE + 41)
10382 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10383 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10384 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10385 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10386 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10387 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10388 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10389 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10390 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10391 #define OPTION_32 (OPTION_ELF_BASE + 4)
10392 {"32", no_argument
, NULL
, OPTION_32
},
10393 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10394 {"n32", no_argument
, NULL
, OPTION_N32
},
10395 #define OPTION_64 (OPTION_ELF_BASE + 6)
10396 {"64", no_argument
, NULL
, OPTION_64
},
10397 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10398 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10399 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10400 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10401 #endif /* OBJ_ELF */
10402 {NULL
, no_argument
, NULL
, 0}
10404 size_t md_longopts_size
= sizeof (md_longopts
);
10406 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10407 NEW_VALUE. Warn if another value was already specified. Note:
10408 we have to defer parsing the -march and -mtune arguments in order
10409 to handle 'from-abi' correctly, since the ABI might be specified
10410 in a later argument. */
10413 mips_set_option_string (string_ptr
, new_value
)
10414 const char **string_ptr
, *new_value
;
10416 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10417 as_warn (_("A different %s was already specified, is now %s"),
10418 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10421 *string_ptr
= new_value
;
10425 md_parse_option (c
, arg
)
10431 case OPTION_CONSTRUCT_FLOATS
:
10432 mips_disable_float_construction
= 0;
10435 case OPTION_NO_CONSTRUCT_FLOATS
:
10436 mips_disable_float_construction
= 1;
10448 target_big_endian
= 1;
10452 target_big_endian
= 0;
10460 if (arg
&& arg
[1] == '0')
10470 mips_debug
= atoi (arg
);
10471 /* When the MIPS assembler sees -g or -g2, it does not do
10472 optimizations which limit full symbolic debugging. We take
10473 that to be equivalent to -O0. */
10474 if (mips_debug
== 2)
10479 file_mips_isa
= ISA_MIPS1
;
10483 file_mips_isa
= ISA_MIPS2
;
10487 file_mips_isa
= ISA_MIPS3
;
10491 file_mips_isa
= ISA_MIPS4
;
10495 file_mips_isa
= ISA_MIPS5
;
10498 case OPTION_MIPS32
:
10499 file_mips_isa
= ISA_MIPS32
;
10502 case OPTION_MIPS64
:
10503 file_mips_isa
= ISA_MIPS64
;
10507 mips_set_option_string (&mips_tune_string
, arg
);
10511 mips_set_option_string (&mips_arch_string
, arg
);
10515 mips_set_option_string (&mips_arch_string
, "4650");
10516 mips_set_option_string (&mips_tune_string
, "4650");
10519 case OPTION_NO_M4650
:
10523 mips_set_option_string (&mips_arch_string
, "4010");
10524 mips_set_option_string (&mips_tune_string
, "4010");
10527 case OPTION_NO_M4010
:
10531 mips_set_option_string (&mips_arch_string
, "4100");
10532 mips_set_option_string (&mips_tune_string
, "4100");
10535 case OPTION_NO_M4100
:
10539 mips_set_option_string (&mips_arch_string
, "3900");
10540 mips_set_option_string (&mips_tune_string
, "3900");
10543 case OPTION_NO_M3900
:
10547 mips_opts
.ase_mdmx
= 1;
10550 case OPTION_NO_MDMX
:
10551 mips_opts
.ase_mdmx
= 0;
10554 case OPTION_MIPS16
:
10555 mips_opts
.mips16
= 1;
10556 mips_no_prev_insn (FALSE
);
10559 case OPTION_NO_MIPS16
:
10560 mips_opts
.mips16
= 0;
10561 mips_no_prev_insn (FALSE
);
10564 case OPTION_MIPS3D
:
10565 mips_opts
.ase_mips3d
= 1;
10568 case OPTION_NO_MIPS3D
:
10569 mips_opts
.ase_mips3d
= 0;
10572 case OPTION_MEMBEDDED_PIC
:
10573 mips_pic
= EMBEDDED_PIC
;
10574 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10576 as_bad (_("-G may not be used with embedded PIC code"));
10579 g_switch_value
= 0x7fffffff;
10582 case OPTION_FIX_VR4122
:
10583 mips_fix_4122_bugs
= 1;
10586 case OPTION_NO_FIX_VR4122
:
10587 mips_fix_4122_bugs
= 0;
10590 case OPTION_RELAX_BRANCH
:
10591 mips_relax_branch
= 1;
10594 case OPTION_NO_RELAX_BRANCH
:
10595 mips_relax_branch
= 0;
10599 /* When generating ELF code, we permit -KPIC and -call_shared to
10600 select SVR4_PIC, and -non_shared to select no PIC. This is
10601 intended to be compatible with Irix 5. */
10602 case OPTION_CALL_SHARED
:
10603 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10605 as_bad (_("-call_shared is supported only for ELF format"));
10608 mips_pic
= SVR4_PIC
;
10609 if (g_switch_seen
&& g_switch_value
!= 0)
10611 as_bad (_("-G may not be used with SVR4 PIC code"));
10614 g_switch_value
= 0;
10617 case OPTION_NON_SHARED
:
10618 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10620 as_bad (_("-non_shared is supported only for ELF format"));
10626 /* The -xgot option tells the assembler to use 32 offsets when
10627 accessing the got in SVR4_PIC mode. It is for Irix
10632 #endif /* OBJ_ELF */
10635 if (! USE_GLOBAL_POINTER_OPT
)
10637 as_bad (_("-G is not supported for this configuration"));
10640 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10642 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10646 g_switch_value
= atoi (arg
);
10651 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10654 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10656 as_bad (_("-32 is supported for ELF format only"));
10659 mips_abi
= O32_ABI
;
10663 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10665 as_bad (_("-n32 is supported for ELF format only"));
10668 mips_abi
= N32_ABI
;
10672 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10674 as_bad (_("-64 is supported for ELF format only"));
10677 mips_abi
= N64_ABI
;
10678 if (! support_64bit_objects())
10679 as_fatal (_("No compiled in support for 64 bit object file format"));
10681 #endif /* OBJ_ELF */
10684 file_mips_gp32
= 1;
10688 file_mips_gp32
= 0;
10692 file_mips_fp32
= 1;
10696 file_mips_fp32
= 0;
10701 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10703 as_bad (_("-mabi is supported for ELF format only"));
10706 if (strcmp (arg
, "32") == 0)
10707 mips_abi
= O32_ABI
;
10708 else if (strcmp (arg
, "o64") == 0)
10709 mips_abi
= O64_ABI
;
10710 else if (strcmp (arg
, "n32") == 0)
10711 mips_abi
= N32_ABI
;
10712 else if (strcmp (arg
, "64") == 0)
10714 mips_abi
= N64_ABI
;
10715 if (! support_64bit_objects())
10716 as_fatal (_("No compiled in support for 64 bit object file "
10719 else if (strcmp (arg
, "eabi") == 0)
10720 mips_abi
= EABI_ABI
;
10723 as_fatal (_("invalid abi -mabi=%s"), arg
);
10727 #endif /* OBJ_ELF */
10729 case OPTION_M7000_HILO_FIX
:
10730 mips_7000_hilo_fix
= TRUE
;
10733 case OPTION_MNO_7000_HILO_FIX
:
10734 mips_7000_hilo_fix
= FALSE
;
10738 case OPTION_MDEBUG
:
10739 mips_flag_mdebug
= TRUE
;
10742 case OPTION_NO_MDEBUG
:
10743 mips_flag_mdebug
= FALSE
;
10745 #endif /* OBJ_ELF */
10754 /* Set up globals to generate code for the ISA or processor
10755 described by INFO. */
10758 mips_set_architecture (info
)
10759 const struct mips_cpu_info
*info
;
10763 mips_arch_info
= info
;
10764 mips_arch
= info
->cpu
;
10765 mips_opts
.isa
= info
->isa
;
10770 /* Likewise for tuning. */
10773 mips_set_tune (info
)
10774 const struct mips_cpu_info
*info
;
10778 mips_tune_info
= info
;
10779 mips_tune
= info
->cpu
;
10785 mips_after_parse_args ()
10787 /* GP relative stuff not working for PE */
10788 if (strncmp (TARGET_OS
, "pe", 2) == 0
10789 && g_switch_value
!= 0)
10792 as_bad (_("-G not supported in this configuration."));
10793 g_switch_value
= 0;
10796 /* The following code determines the architecture and register size.
10797 Similar code was added to GCC 3.3 (see override_options() in
10798 config/mips/mips.c). The GAS and GCC code should be kept in sync
10799 as much as possible. */
10801 if (mips_arch_string
!= 0)
10802 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
10804 if (mips_tune_string
!= 0)
10805 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
10807 if (file_mips_isa
!= ISA_UNKNOWN
)
10809 /* Handle -mipsN. At this point, file_mips_isa contains the
10810 ISA level specified by -mipsN, while mips_opts.isa contains
10811 the -march selection (if any). */
10812 if (mips_arch_info
!= 0)
10814 /* -march takes precedence over -mipsN, since it is more descriptive.
10815 There's no harm in specifying both as long as the ISA levels
10817 if (file_mips_isa
!= mips_opts
.isa
)
10818 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10819 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10820 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10823 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa
));
10826 if (mips_arch_info
== 0)
10827 mips_set_architecture (mips_parse_cpu ("default CPU",
10828 MIPS_CPU_STRING_DEFAULT
));
10830 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10831 as_bad ("-march=%s is not compatible with the selected ABI",
10832 mips_arch_info
->name
);
10834 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10835 if (mips_tune_info
== 0)
10836 mips_set_tune (mips_arch_info
);
10838 if (file_mips_gp32
>= 0)
10840 /* The user specified the size of the integer registers. Make sure
10841 it agrees with the ABI and ISA. */
10842 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10843 as_bad (_("-mgp64 used with a 32-bit processor"));
10844 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10845 as_bad (_("-mgp32 used with a 64-bit ABI"));
10846 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10847 as_bad (_("-mgp64 used with a 32-bit ABI"));
10851 /* Infer the integer register size from the ABI and processor.
10852 Restrict ourselves to 32-bit registers if that's all the
10853 processor has, or if the ABI cannot handle 64-bit registers. */
10854 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10855 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10858 /* ??? GAS treats single-float processors as though they had 64-bit
10859 float registers (although it complains when double-precision
10860 instructions are used). As things stand, saying they have 32-bit
10861 registers would lead to spurious "register must be even" messages.
10862 So here we assume float registers are always the same size as
10863 integer ones, unless the user says otherwise. */
10864 if (file_mips_fp32
< 0)
10865 file_mips_fp32
= file_mips_gp32
;
10867 /* End of GCC-shared inference code. */
10869 /* ??? When do we want this flag to be set? Who uses it? */
10870 if (file_mips_gp32
== 1
10871 && mips_abi
== NO_ABI
10872 && ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10873 mips_32bitmode
= 1;
10875 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10876 as_bad (_("trap exception not supported at ISA 1"));
10878 /* If the selected architecture includes support for ASEs, enable
10879 generation of code for them. */
10880 if (mips_opts
.mips16
== -1)
10881 mips_opts
.mips16
= (CPU_HAS_MIPS16 (mips_arch
)) ? 1 : 0;
10882 if (mips_opts
.ase_mips3d
== -1)
10883 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (mips_arch
)) ? 1 : 0;
10884 if (mips_opts
.ase_mdmx
== -1)
10885 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (mips_arch
)) ? 1 : 0;
10887 file_mips_isa
= mips_opts
.isa
;
10888 file_ase_mips16
= mips_opts
.mips16
;
10889 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10890 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10891 mips_opts
.gp32
= file_mips_gp32
;
10892 mips_opts
.fp32
= file_mips_fp32
;
10894 if (mips_flag_mdebug
< 0)
10896 #ifdef OBJ_MAYBE_ECOFF
10897 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10898 mips_flag_mdebug
= 1;
10900 #endif /* OBJ_MAYBE_ECOFF */
10901 mips_flag_mdebug
= 0;
10906 mips_init_after_args ()
10908 /* initialize opcodes */
10909 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10910 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10914 md_pcrel_from (fixP
)
10917 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10918 && fixP
->fx_addsy
!= (symbolS
*) NULL
10919 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10922 /* Return the address of the delay slot. */
10923 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10926 /* This is called before the symbol table is processed. In order to
10927 work with gcc when using mips-tfile, we must keep all local labels.
10928 However, in other cases, we want to discard them. If we were
10929 called with -g, but we didn't see any debugging information, it may
10930 mean that gcc is smuggling debugging information through to
10931 mips-tfile, in which case we must generate all local labels. */
10934 mips_frob_file_before_adjust ()
10936 #ifndef NO_ECOFF_DEBUGGING
10937 if (ECOFF_DEBUGGING
10939 && ! ecoff_debugging_seen
)
10940 flag_keep_locals
= 1;
10944 /* Sort any unmatched HI16_S relocs so that they immediately precede
10945 the corresponding LO reloc. This is called before md_apply_fix3 and
10946 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10947 explicit use of the %hi modifier. */
10952 struct mips_hi_fixup
*l
;
10954 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10956 segment_info_type
*seginfo
;
10959 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10961 /* Check quickly whether the next fixup happens to be a matching
10963 if (l
->fixp
->fx_next
!= NULL
10964 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10965 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10966 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10969 /* Look through the fixups for this segment for a matching %lo.
10970 When we find one, move the %hi just in front of it. We do
10971 this in two passes. In the first pass, we try to find a
10972 unique %lo. In the second pass, we permit multiple %hi
10973 relocs for a single %lo (this is a GNU extension). */
10974 seginfo
= seg_info (l
->seg
);
10975 for (pass
= 0; pass
< 2; pass
++)
10980 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10982 /* Check whether this is a %lo fixup which matches l->fixp. */
10983 if (f
->fx_r_type
== BFD_RELOC_LO16
10984 && f
->fx_addsy
== l
->fixp
->fx_addsy
10985 && f
->fx_offset
== l
->fixp
->fx_offset
10988 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10989 || prev
->fx_addsy
!= f
->fx_addsy
10990 || prev
->fx_offset
!= f
->fx_offset
))
10994 /* Move l->fixp before f. */
10995 for (pf
= &seginfo
->fix_root
;
10997 pf
= &(*pf
)->fx_next
)
10998 assert (*pf
!= NULL
);
11000 *pf
= l
->fixp
->fx_next
;
11002 l
->fixp
->fx_next
= f
;
11004 seginfo
->fix_root
= l
->fixp
;
11006 prev
->fx_next
= l
->fixp
;
11017 #if 0 /* GCC code motion plus incomplete dead code elimination
11018 can leave a %hi without a %lo. */
11020 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
11021 _("Unmatched %%hi reloc"));
11027 /* When generating embedded PIC code we need to use a special
11028 relocation to represent the difference of two symbols in the .text
11029 section (switch tables use a difference of this sort). See
11030 include/coff/mips.h for details. This macro checks whether this
11031 fixup requires the special reloc. */
11032 #define SWITCH_TABLE(fixp) \
11033 ((fixp)->fx_r_type == BFD_RELOC_32 \
11034 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
11035 && (fixp)->fx_addsy != NULL \
11036 && (fixp)->fx_subsy != NULL \
11037 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
11038 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
11040 /* When generating embedded PIC code we must keep all PC relative
11041 relocations, in case the linker has to relax a call. We also need
11042 to keep relocations for switch table entries.
11044 We may have combined relocations without symbols in the N32/N64 ABI.
11045 We have to prevent gas from dropping them. */
11048 mips_force_relocation (fixp
)
11051 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11052 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11053 || S_FORCE_RELOC (fixp
->fx_addsy
))
11057 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11058 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11059 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11060 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11063 return (mips_pic
== EMBEDDED_PIC
11065 || SWITCH_TABLE (fixp
)
11066 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
11067 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
11072 mips_need_elf_addend_fixup (fixP
)
11075 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
11077 if (mips_pic
== EMBEDDED_PIC
11078 && S_IS_WEAK (fixP
->fx_addsy
))
11080 if (mips_pic
!= EMBEDDED_PIC
11081 && (S_IS_WEAK (fixP
->fx_addsy
)
11082 || S_IS_EXTERNAL (fixP
->fx_addsy
))
11083 && !S_IS_COMMON (fixP
->fx_addsy
))
11085 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
11086 && (((bfd_get_section_flags (stdoutput
,
11087 S_GET_SEGMENT (fixP
->fx_addsy
))
11088 & (SEC_LINK_ONCE
| SEC_MERGE
)) != 0)
11089 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
11091 sizeof (".gnu.linkonce") - 1)))
11097 /* Apply a fixup to the object file. */
11100 md_apply_fix3 (fixP
, valP
, seg
)
11103 segT seg ATTRIBUTE_UNUSED
;
11108 static int previous_fx_r_type
= 0;
11110 /* FIXME: Maybe just return for all reloc types not listed below?
11111 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
11112 if (fixP
->fx_r_type
== BFD_RELOC_8
)
11115 assert (fixP
->fx_size
== 4
11116 || fixP
->fx_r_type
== BFD_RELOC_16
11117 || fixP
->fx_r_type
== BFD_RELOC_32
11118 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
11119 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
11120 || fixP
->fx_r_type
== BFD_RELOC_LO16
11121 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
11122 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
11123 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
11124 || fixP
->fx_r_type
== BFD_RELOC_64
11125 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11126 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11127 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
11128 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
11129 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
11130 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
11131 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
11132 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11133 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
11134 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JALR
);
11138 /* If we aren't adjusting this fixup to be against the section
11139 symbol, we need to adjust the value. */
11141 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11143 if (mips_need_elf_addend_fixup (fixP
))
11145 reloc_howto_type
*howto
;
11146 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
11150 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11151 if (value
!= 0 && howto
&& howto
->partial_inplace
11152 && (! fixP
->fx_pcrel
|| howto
->pcrel_offset
))
11154 /* In this case, the bfd_install_relocation routine will
11155 incorrectly add the symbol value back in. We just want
11156 the addend to appear in the object file.
11158 howto->pcrel_offset is added for R_MIPS_PC16, which is
11159 generated for code like
11170 /* Make sure the addend is still non-zero. If it became zero
11171 after the last operation, set it to a spurious value and
11172 subtract the same value from the object file's contents. */
11177 /* The in-place addends for LO16 relocations are signed;
11178 leave the matching HI16 in-place addends as zero. */
11179 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
11181 bfd_vma contents
, mask
, field
;
11183 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
11186 target_big_endian
);
11188 /* MASK has bits set where the relocation should go.
11189 FIELD is -value, shifted into the appropriate place
11190 for this relocation. */
11191 mask
= 1 << (howto
->bitsize
- 1);
11192 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
11193 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
11195 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
11196 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11198 target_big_endian
);
11204 /* This code was generated using trial and error and so is
11205 fragile and not trustworthy. If you change it, you should
11206 rerun the elf-rel, elf-rel2, and empic testcases and ensure
11207 they still pass. */
11208 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
11210 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11212 /* BFD's REL handling, for MIPS, is _very_ weird.
11213 This gives the right results, but it can't possibly
11214 be the way things are supposed to work. */
11215 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11216 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
11217 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11222 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
11224 /* We are not done if this is a composite relocation to set up gp. */
11225 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11226 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11227 || (fixP
->fx_r_type
== BFD_RELOC_64
11228 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11229 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11230 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11231 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11232 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11234 previous_fx_r_type
= fixP
->fx_r_type
;
11236 switch (fixP
->fx_r_type
)
11238 case BFD_RELOC_MIPS_JMP
:
11239 case BFD_RELOC_MIPS_SHIFT5
:
11240 case BFD_RELOC_MIPS_SHIFT6
:
11241 case BFD_RELOC_MIPS_GOT_DISP
:
11242 case BFD_RELOC_MIPS_GOT_PAGE
:
11243 case BFD_RELOC_MIPS_GOT_OFST
:
11244 case BFD_RELOC_MIPS_SUB
:
11245 case BFD_RELOC_MIPS_INSERT_A
:
11246 case BFD_RELOC_MIPS_INSERT_B
:
11247 case BFD_RELOC_MIPS_DELETE
:
11248 case BFD_RELOC_MIPS_HIGHEST
:
11249 case BFD_RELOC_MIPS_HIGHER
:
11250 case BFD_RELOC_MIPS_SCN_DISP
:
11251 case BFD_RELOC_MIPS_REL16
:
11252 case BFD_RELOC_MIPS_RELGOT
:
11253 case BFD_RELOC_MIPS_JALR
:
11254 case BFD_RELOC_HI16
:
11255 case BFD_RELOC_HI16_S
:
11256 case BFD_RELOC_GPREL16
:
11257 case BFD_RELOC_MIPS_LITERAL
:
11258 case BFD_RELOC_MIPS_CALL16
:
11259 case BFD_RELOC_MIPS_GOT16
:
11260 case BFD_RELOC_GPREL32
:
11261 case BFD_RELOC_MIPS_GOT_HI16
:
11262 case BFD_RELOC_MIPS_GOT_LO16
:
11263 case BFD_RELOC_MIPS_CALL_HI16
:
11264 case BFD_RELOC_MIPS_CALL_LO16
:
11265 case BFD_RELOC_MIPS16_GPREL
:
11266 if (fixP
->fx_pcrel
)
11267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11268 _("Invalid PC relative reloc"));
11269 /* Nothing needed to do. The value comes from the reloc entry */
11272 case BFD_RELOC_MIPS16_JMP
:
11273 /* We currently always generate a reloc against a symbol, which
11274 means that we don't want an addend even if the symbol is
11276 fixP
->fx_addnumber
= 0;
11279 case BFD_RELOC_PCREL_HI16_S
:
11280 /* The addend for this is tricky if it is internal, so we just
11281 do everything here rather than in bfd_install_relocation. */
11282 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11287 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11289 /* For an external symbol adjust by the address to make it
11290 pcrel_offset. We use the address of the RELLO reloc
11291 which follows this one. */
11292 value
+= (fixP
->fx_next
->fx_frag
->fr_address
11293 + fixP
->fx_next
->fx_where
);
11295 value
= ((value
+ 0x8000) >> 16) & 0xffff;
11296 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11297 if (target_big_endian
)
11299 md_number_to_chars ((char *) buf
, value
, 2);
11302 case BFD_RELOC_PCREL_LO16
:
11303 /* The addend for this is tricky if it is internal, so we just
11304 do everything here rather than in bfd_install_relocation. */
11305 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11310 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11311 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11312 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11313 if (target_big_endian
)
11315 md_number_to_chars ((char *) buf
, value
, 2);
11319 /* This is handled like BFD_RELOC_32, but we output a sign
11320 extended value if we are only 32 bits. */
11322 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11324 if (8 <= sizeof (valueT
))
11325 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11332 w1
= w2
= fixP
->fx_where
;
11333 if (target_big_endian
)
11337 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
11338 if ((value
& 0x80000000) != 0)
11342 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
11347 case BFD_RELOC_RVA
:
11349 /* If we are deleting this reloc entry, we must fill in the
11350 value now. This can happen if we have a .word which is not
11351 resolved when it appears but is later defined. We also need
11352 to fill in the value if this is an embedded PIC switch table
11355 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11356 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11361 /* If we are deleting this reloc entry, we must fill in the
11363 assert (fixP
->fx_size
== 2);
11365 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
11369 case BFD_RELOC_LO16
:
11370 /* When handling an embedded PIC switch statement, we can wind
11371 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11374 if (value
+ 0x8000 > 0xffff)
11375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11376 _("relocation overflow"));
11377 buf
= (bfd_byte
*) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
11378 if (target_big_endian
)
11380 md_number_to_chars ((char *) buf
, value
, 2);
11384 case BFD_RELOC_16_PCREL_S2
:
11385 if ((value
& 0x3) != 0)
11386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11387 _("Branch to odd address (%lx)"), (long) value
);
11390 * We need to save the bits in the instruction since fixup_segment()
11391 * might be deleting the relocation entry (i.e., a branch within
11392 * the current segment).
11394 if (!fixP
->fx_done
&& (value
!= 0 || HAVE_NEWABI
))
11396 /* If 'value' is zero, the remaining reloc code won't actually
11397 do the store, so it must be done here. This is probably
11398 a bug somewhere. */
11400 && (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
11401 || fixP
->fx_addsy
== NULL
/* ??? */
11402 || ! S_IS_DEFINED (fixP
->fx_addsy
)))
11403 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11405 value
= (offsetT
) value
>> 2;
11407 /* update old instruction data */
11408 buf
= (bfd_byte
*) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
11409 if (target_big_endian
)
11410 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11412 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11414 if (value
+ 0x8000 <= 0xffff)
11415 insn
|= value
& 0xffff;
11418 /* The branch offset is too large. If this is an
11419 unconditional branch, and we are not generating PIC code,
11420 we can convert it to an absolute jump instruction. */
11421 if (mips_pic
== NO_PIC
11423 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11424 && (fixP
->fx_frag
->fr_address
11425 < text_section
->vma
+ text_section
->_raw_size
)
11426 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11427 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11428 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11430 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11431 insn
= 0x0c000000; /* jal */
11433 insn
= 0x08000000; /* j */
11434 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11436 fixP
->fx_addsy
= section_symbol (text_section
);
11437 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
11441 /* If we got here, we have branch-relaxation disabled,
11442 and there's nothing we can do to fix this instruction
11443 without turning it into a longer sequence. */
11444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11445 _("Branch out of range"));
11449 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
11452 case BFD_RELOC_VTABLE_INHERIT
:
11455 && !S_IS_DEFINED (fixP
->fx_addsy
)
11456 && !S_IS_WEAK (fixP
->fx_addsy
))
11457 S_SET_WEAK (fixP
->fx_addsy
);
11460 case BFD_RELOC_VTABLE_ENTRY
:
11474 const struct mips_opcode
*p
;
11475 int treg
, sreg
, dreg
, shamt
;
11480 for (i
= 0; i
< NUMOPCODES
; ++i
)
11482 p
= &mips_opcodes
[i
];
11483 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11485 printf ("%08lx %s\t", oc
, p
->name
);
11486 treg
= (oc
>> 16) & 0x1f;
11487 sreg
= (oc
>> 21) & 0x1f;
11488 dreg
= (oc
>> 11) & 0x1f;
11489 shamt
= (oc
>> 6) & 0x1f;
11491 for (args
= p
->args
;; ++args
)
11502 printf ("%c", *args
);
11506 assert (treg
== sreg
);
11507 printf ("$%d,$%d", treg
, sreg
);
11512 printf ("$%d", dreg
);
11517 printf ("$%d", treg
);
11521 printf ("0x%x", treg
);
11526 printf ("$%d", sreg
);
11530 printf ("0x%08lx", oc
& 0x1ffffff);
11537 printf ("%d", imm
);
11542 printf ("$%d", shamt
);
11553 printf (_("%08lx UNDEFINED\n"), oc
);
11564 name
= input_line_pointer
;
11565 c
= get_symbol_end ();
11566 p
= (symbolS
*) symbol_find_or_make (name
);
11567 *input_line_pointer
= c
;
11571 /* Align the current frag to a given power of two. The MIPS assembler
11572 also automatically adjusts any preceding label. */
11575 mips_align (to
, fill
, label
)
11580 mips_emit_delays (FALSE
);
11581 frag_align (to
, fill
, 0);
11582 record_alignment (now_seg
, to
);
11585 assert (S_GET_SEGMENT (label
) == now_seg
);
11586 symbol_set_frag (label
, frag_now
);
11587 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11591 /* Align to a given power of two. .align 0 turns off the automatic
11592 alignment used by the data creating pseudo-ops. */
11596 int x ATTRIBUTE_UNUSED
;
11599 register long temp_fill
;
11600 long max_alignment
= 15;
11604 o Note that the assembler pulls down any immediately preceeding label
11605 to the aligned address.
11606 o It's not documented but auto alignment is reinstated by
11607 a .align pseudo instruction.
11608 o Note also that after auto alignment is turned off the mips assembler
11609 issues an error on attempt to assemble an improperly aligned data item.
11614 temp
= get_absolute_expression ();
11615 if (temp
> max_alignment
)
11616 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11619 as_warn (_("Alignment negative: 0 assumed."));
11622 if (*input_line_pointer
== ',')
11624 ++input_line_pointer
;
11625 temp_fill
= get_absolute_expression ();
11632 mips_align (temp
, (int) temp_fill
,
11633 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11640 demand_empty_rest_of_line ();
11644 mips_flush_pending_output ()
11646 mips_emit_delays (FALSE
);
11647 mips_clear_insn_labels ();
11656 /* When generating embedded PIC code, we only use the .text, .lit8,
11657 .sdata and .sbss sections. We change the .data and .rdata
11658 pseudo-ops to use .sdata. */
11659 if (mips_pic
== EMBEDDED_PIC
11660 && (sec
== 'd' || sec
== 'r'))
11664 /* The ELF backend needs to know that we are changing sections, so
11665 that .previous works correctly. We could do something like check
11666 for an obj_section_change_hook macro, but that might be confusing
11667 as it would not be appropriate to use it in the section changing
11668 functions in read.c, since obj-elf.c intercepts those. FIXME:
11669 This should be cleaner, somehow. */
11670 obj_elf_section_change_hook ();
11673 mips_emit_delays (FALSE
);
11683 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11684 demand_empty_rest_of_line ();
11688 if (USE_GLOBAL_POINTER_OPT
)
11690 seg
= subseg_new (RDATA_SECTION_NAME
,
11691 (subsegT
) get_absolute_expression ());
11692 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11694 bfd_set_section_flags (stdoutput
, seg
,
11700 if (strcmp (TARGET_OS
, "elf") != 0)
11701 record_alignment (seg
, 4);
11703 demand_empty_rest_of_line ();
11707 as_bad (_("No read only data section in this object file format"));
11708 demand_empty_rest_of_line ();
11714 if (USE_GLOBAL_POINTER_OPT
)
11716 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11717 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11719 bfd_set_section_flags (stdoutput
, seg
,
11720 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11722 if (strcmp (TARGET_OS
, "elf") != 0)
11723 record_alignment (seg
, 4);
11725 demand_empty_rest_of_line ();
11730 as_bad (_("Global pointers not supported; recompile -G 0"));
11731 demand_empty_rest_of_line ();
11740 s_change_section (ignore
)
11741 int ignore ATTRIBUTE_UNUSED
;
11744 char *section_name
;
11749 int section_entry_size
;
11750 int section_alignment
;
11752 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11755 section_name
= input_line_pointer
;
11756 c
= get_symbol_end ();
11758 next_c
= *(input_line_pointer
+ 1);
11760 /* Do we have .section Name<,"flags">? */
11761 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11763 /* just after name is now '\0'. */
11764 *input_line_pointer
= c
;
11765 input_line_pointer
= section_name
;
11766 obj_elf_section (ignore
);
11769 input_line_pointer
++;
11771 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11773 section_type
= get_absolute_expression ();
11776 if (*input_line_pointer
++ == ',')
11777 section_flag
= get_absolute_expression ();
11780 if (*input_line_pointer
++ == ',')
11781 section_entry_size
= get_absolute_expression ();
11783 section_entry_size
= 0;
11784 if (*input_line_pointer
++ == ',')
11785 section_alignment
= get_absolute_expression ();
11787 section_alignment
= 0;
11789 section_name
= xstrdup (section_name
);
11791 obj_elf_change_section (section_name
, section_type
, section_flag
,
11792 section_entry_size
, 0, 0, 0);
11794 if (now_seg
->name
!= section_name
)
11795 free (section_name
);
11796 #endif /* OBJ_ELF */
11800 mips_enable_auto_align ()
11811 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11812 mips_emit_delays (FALSE
);
11813 if (log_size
> 0 && auto_align
)
11814 mips_align (log_size
, 0, label
);
11815 mips_clear_insn_labels ();
11816 cons (1 << log_size
);
11820 s_float_cons (type
)
11825 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11827 mips_emit_delays (FALSE
);
11832 mips_align (3, 0, label
);
11834 mips_align (2, 0, label
);
11837 mips_clear_insn_labels ();
11842 /* Handle .globl. We need to override it because on Irix 5 you are
11845 where foo is an undefined symbol, to mean that foo should be
11846 considered to be the address of a function. */
11850 int x ATTRIBUTE_UNUSED
;
11857 name
= input_line_pointer
;
11858 c
= get_symbol_end ();
11859 symbolP
= symbol_find_or_make (name
);
11860 *input_line_pointer
= c
;
11861 SKIP_WHITESPACE ();
11863 /* On Irix 5, every global symbol that is not explicitly labelled as
11864 being a function is apparently labelled as being an object. */
11867 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11872 secname
= input_line_pointer
;
11873 c
= get_symbol_end ();
11874 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11876 as_bad (_("%s: no such section"), secname
);
11877 *input_line_pointer
= c
;
11879 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11880 flag
= BSF_FUNCTION
;
11883 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11885 S_SET_EXTERNAL (symbolP
);
11886 demand_empty_rest_of_line ();
11891 int x ATTRIBUTE_UNUSED
;
11896 opt
= input_line_pointer
;
11897 c
= get_symbol_end ();
11901 /* FIXME: What does this mean? */
11903 else if (strncmp (opt
, "pic", 3) == 0)
11907 i
= atoi (opt
+ 3);
11911 mips_pic
= SVR4_PIC
;
11913 as_bad (_(".option pic%d not supported"), i
);
11915 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11917 if (g_switch_seen
&& g_switch_value
!= 0)
11918 as_warn (_("-G may not be used with SVR4 PIC code"));
11919 g_switch_value
= 0;
11920 bfd_set_gp_size (stdoutput
, 0);
11924 as_warn (_("Unrecognized option \"%s\""), opt
);
11926 *input_line_pointer
= c
;
11927 demand_empty_rest_of_line ();
11930 /* This structure is used to hold a stack of .set values. */
11932 struct mips_option_stack
11934 struct mips_option_stack
*next
;
11935 struct mips_set_options options
;
11938 static struct mips_option_stack
*mips_opts_stack
;
11940 /* Handle the .set pseudo-op. */
11944 int x ATTRIBUTE_UNUSED
;
11946 char *name
= input_line_pointer
, ch
;
11948 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11949 ++input_line_pointer
;
11950 ch
= *input_line_pointer
;
11951 *input_line_pointer
= '\0';
11953 if (strcmp (name
, "reorder") == 0)
11955 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11957 /* If we still have pending nops, we can discard them. The
11958 usual nop handling will insert any that are still
11960 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11961 * (mips_opts
.mips16
? 2 : 4));
11962 prev_nop_frag
= NULL
;
11964 mips_opts
.noreorder
= 0;
11966 else if (strcmp (name
, "noreorder") == 0)
11968 mips_emit_delays (TRUE
);
11969 mips_opts
.noreorder
= 1;
11970 mips_any_noreorder
= 1;
11972 else if (strcmp (name
, "at") == 0)
11974 mips_opts
.noat
= 0;
11976 else if (strcmp (name
, "noat") == 0)
11978 mips_opts
.noat
= 1;
11980 else if (strcmp (name
, "macro") == 0)
11982 mips_opts
.warn_about_macros
= 0;
11984 else if (strcmp (name
, "nomacro") == 0)
11986 if (mips_opts
.noreorder
== 0)
11987 as_bad (_("`noreorder' must be set before `nomacro'"));
11988 mips_opts
.warn_about_macros
= 1;
11990 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11992 mips_opts
.nomove
= 0;
11994 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11996 mips_opts
.nomove
= 1;
11998 else if (strcmp (name
, "bopt") == 0)
12000 mips_opts
.nobopt
= 0;
12002 else if (strcmp (name
, "nobopt") == 0)
12004 mips_opts
.nobopt
= 1;
12006 else if (strcmp (name
, "mips16") == 0
12007 || strcmp (name
, "MIPS-16") == 0)
12008 mips_opts
.mips16
= 1;
12009 else if (strcmp (name
, "nomips16") == 0
12010 || strcmp (name
, "noMIPS-16") == 0)
12011 mips_opts
.mips16
= 0;
12012 else if (strcmp (name
, "mips3d") == 0)
12013 mips_opts
.ase_mips3d
= 1;
12014 else if (strcmp (name
, "nomips3d") == 0)
12015 mips_opts
.ase_mips3d
= 0;
12016 else if (strcmp (name
, "mdmx") == 0)
12017 mips_opts
.ase_mdmx
= 1;
12018 else if (strcmp (name
, "nomdmx") == 0)
12019 mips_opts
.ase_mdmx
= 0;
12020 else if (strncmp (name
, "mips", 4) == 0)
12024 /* Permit the user to change the ISA on the fly. Needless to
12025 say, misuse can cause serious problems. */
12026 isa
= atoi (name
+ 4);
12030 mips_opts
.gp32
= file_mips_gp32
;
12031 mips_opts
.fp32
= file_mips_fp32
;
12036 mips_opts
.gp32
= 1;
12037 mips_opts
.fp32
= 1;
12043 mips_opts
.gp32
= 0;
12044 mips_opts
.fp32
= 0;
12047 as_bad (_("unknown ISA level %s"), name
+ 4);
12053 case 0: mips_opts
.isa
= file_mips_isa
; break;
12054 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
12055 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
12056 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
12057 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
12058 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
12059 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
12060 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
12061 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
12064 else if (strcmp (name
, "autoextend") == 0)
12065 mips_opts
.noautoextend
= 0;
12066 else if (strcmp (name
, "noautoextend") == 0)
12067 mips_opts
.noautoextend
= 1;
12068 else if (strcmp (name
, "push") == 0)
12070 struct mips_option_stack
*s
;
12072 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12073 s
->next
= mips_opts_stack
;
12074 s
->options
= mips_opts
;
12075 mips_opts_stack
= s
;
12077 else if (strcmp (name
, "pop") == 0)
12079 struct mips_option_stack
*s
;
12081 s
= mips_opts_stack
;
12083 as_bad (_(".set pop with no .set push"));
12086 /* If we're changing the reorder mode we need to handle
12087 delay slots correctly. */
12088 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12089 mips_emit_delays (TRUE
);
12090 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12092 if (prev_nop_frag
!= NULL
)
12094 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
12095 * (mips_opts
.mips16
? 2 : 4));
12096 prev_nop_frag
= NULL
;
12100 mips_opts
= s
->options
;
12101 mips_opts_stack
= s
->next
;
12107 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12109 *input_line_pointer
= ch
;
12110 demand_empty_rest_of_line ();
12113 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12114 .option pic2. It means to generate SVR4 PIC calls. */
12117 s_abicalls (ignore
)
12118 int ignore ATTRIBUTE_UNUSED
;
12120 mips_pic
= SVR4_PIC
;
12121 if (USE_GLOBAL_POINTER_OPT
)
12123 if (g_switch_seen
&& g_switch_value
!= 0)
12124 as_warn (_("-G may not be used with SVR4 PIC code"));
12125 g_switch_value
= 0;
12127 bfd_set_gp_size (stdoutput
, 0);
12128 demand_empty_rest_of_line ();
12131 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12132 PIC code. It sets the $gp register for the function based on the
12133 function address, which is in the register named in the argument.
12134 This uses a relocation against _gp_disp, which is handled specially
12135 by the linker. The result is:
12136 lui $gp,%hi(_gp_disp)
12137 addiu $gp,$gp,%lo(_gp_disp)
12138 addu $gp,$gp,.cpload argument
12139 The .cpload argument is normally $25 == $t9. */
12143 int ignore ATTRIBUTE_UNUSED
;
12148 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12149 .cpload is ignored. */
12150 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12156 /* .cpload should be in a .set noreorder section. */
12157 if (mips_opts
.noreorder
== 0)
12158 as_warn (_(".cpload not in noreorder section"));
12160 ex
.X_op
= O_symbol
;
12161 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12162 ex
.X_op_symbol
= NULL
;
12163 ex
.X_add_number
= 0;
12165 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12166 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12168 macro_build_lui (NULL
, &icnt
, &ex
, mips_gp_register
);
12169 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j",
12170 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_LO16
);
12172 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
12173 mips_gp_register
, mips_gp_register
, tc_get_register (0));
12175 demand_empty_rest_of_line ();
12178 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12179 .cpsetup $reg1, offset|$reg2, label
12181 If offset is given, this results in:
12182 sd $gp, offset($sp)
12183 lui $gp, %hi(%neg(%gp_rel(label)))
12184 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12185 daddu $gp, $gp, $reg1
12187 If $reg2 is given, this results in:
12188 daddu $reg2, $gp, $0
12189 lui $gp, %hi(%neg(%gp_rel(label)))
12190 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12191 daddu $gp, $gp, $reg1
12192 $reg1 is normally $25 == $t9. */
12195 int ignore ATTRIBUTE_UNUSED
;
12197 expressionS ex_off
;
12198 expressionS ex_sym
;
12203 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12204 We also need NewABI support. */
12205 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12211 reg1
= tc_get_register (0);
12212 SKIP_WHITESPACE ();
12213 if (*input_line_pointer
!= ',')
12215 as_bad (_("missing argument separator ',' for .cpsetup"));
12219 ++input_line_pointer
;
12220 SKIP_WHITESPACE ();
12221 if (*input_line_pointer
== '$')
12223 mips_cpreturn_register
= tc_get_register (0);
12224 mips_cpreturn_offset
= -1;
12228 mips_cpreturn_offset
= get_absolute_expression ();
12229 mips_cpreturn_register
= -1;
12231 SKIP_WHITESPACE ();
12232 if (*input_line_pointer
!= ',')
12234 as_bad (_("missing argument separator ',' for .cpsetup"));
12238 ++input_line_pointer
;
12239 SKIP_WHITESPACE ();
12240 expression (&ex_sym
);
12242 if (mips_cpreturn_register
== -1)
12244 ex_off
.X_op
= O_constant
;
12245 ex_off
.X_add_symbol
= NULL
;
12246 ex_off
.X_op_symbol
= NULL
;
12247 ex_off
.X_add_number
= mips_cpreturn_offset
;
12249 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
12250 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12254 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
12256 /* Ensure there's room for the next two instructions, so that `f'
12257 doesn't end up with an address in the wrong frag. */
12260 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
12261 (int) BFD_RELOC_GPREL16
);
12262 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12263 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12264 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12265 0, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12268 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
12269 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
12270 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12271 0, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12272 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12273 0, NULL
, 0, 0, BFD_RELOC_LO16
);
12275 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12276 HAVE_64BIT_ADDRESSES
? "daddu" : "addu", "d,v,t",
12277 mips_gp_register
, mips_gp_register
, reg1
);
12279 demand_empty_rest_of_line ();
12284 int ignore ATTRIBUTE_UNUSED
;
12286 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12287 .cplocal is ignored. */
12288 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12294 mips_gp_register
= tc_get_register (0);
12295 demand_empty_rest_of_line ();
12298 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12299 offset from $sp. The offset is remembered, and after making a PIC
12300 call $gp is restored from that location. */
12303 s_cprestore (ignore
)
12304 int ignore ATTRIBUTE_UNUSED
;
12309 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12310 .cprestore is ignored. */
12311 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12317 mips_cprestore_offset
= get_absolute_expression ();
12318 mips_cprestore_valid
= 1;
12320 ex
.X_op
= O_constant
;
12321 ex
.X_add_symbol
= NULL
;
12322 ex
.X_op_symbol
= NULL
;
12323 ex
.X_add_number
= mips_cprestore_offset
;
12325 macro_build_ldst_constoffset ((char *) NULL
, &icnt
, &ex
,
12326 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
12327 mips_gp_register
, SP
);
12329 demand_empty_rest_of_line ();
12332 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12333 was given in the preceeding .gpsetup, it results in:
12334 ld $gp, offset($sp)
12336 If a register $reg2 was given there, it results in:
12337 daddiu $gp, $gp, $reg2
12340 s_cpreturn (ignore
)
12341 int ignore ATTRIBUTE_UNUSED
;
12346 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12347 We also need NewABI support. */
12348 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12354 if (mips_cpreturn_register
== -1)
12356 ex
.X_op
= O_constant
;
12357 ex
.X_add_symbol
= NULL
;
12358 ex
.X_op_symbol
= NULL
;
12359 ex
.X_add_number
= mips_cpreturn_offset
;
12361 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
12362 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
12365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
12366 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
12368 demand_empty_rest_of_line ();
12371 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12372 code. It sets the offset to use in gp_rel relocations. */
12376 int ignore ATTRIBUTE_UNUSED
;
12378 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12379 We also need NewABI support. */
12380 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12386 mips_gprel_offset
= get_absolute_expression ();
12388 demand_empty_rest_of_line ();
12391 /* Handle the .gpword pseudo-op. This is used when generating PIC
12392 code. It generates a 32 bit GP relative reloc. */
12396 int ignore ATTRIBUTE_UNUSED
;
12402 /* When not generating PIC code, this is treated as .word. */
12403 if (mips_pic
!= SVR4_PIC
)
12409 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12410 mips_emit_delays (TRUE
);
12412 mips_align (2, 0, label
);
12413 mips_clear_insn_labels ();
12417 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12419 as_bad (_("Unsupported use of .gpword"));
12420 ignore_rest_of_line ();
12424 md_number_to_chars (p
, (valueT
) 0, 4);
12425 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12426 BFD_RELOC_GPREL32
);
12428 demand_empty_rest_of_line ();
12433 int ignore ATTRIBUTE_UNUSED
;
12439 /* When not generating PIC code, this is treated as .dword. */
12440 if (mips_pic
!= SVR4_PIC
)
12446 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12447 mips_emit_delays (TRUE
);
12449 mips_align (3, 0, label
);
12450 mips_clear_insn_labels ();
12454 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12456 as_bad (_("Unsupported use of .gpdword"));
12457 ignore_rest_of_line ();
12461 md_number_to_chars (p
, (valueT
) 0, 8);
12462 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12463 BFD_RELOC_GPREL32
);
12465 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12466 ex
.X_op
= O_absent
;
12467 ex
.X_add_symbol
= 0;
12468 ex
.X_add_number
= 0;
12469 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12472 demand_empty_rest_of_line ();
12475 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12476 tables in SVR4 PIC code. */
12480 int ignore ATTRIBUTE_UNUSED
;
12485 /* This is ignored when not generating SVR4 PIC code. */
12486 if (mips_pic
!= SVR4_PIC
)
12492 /* Add $gp to the register named as an argument. */
12493 reg
= tc_get_register (0);
12494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
12495 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
12496 "d,v,t", reg
, reg
, mips_gp_register
);
12498 demand_empty_rest_of_line ();
12501 /* Handle the .insn pseudo-op. This marks instruction labels in
12502 mips16 mode. This permits the linker to handle them specially,
12503 such as generating jalx instructions when needed. We also make
12504 them odd for the duration of the assembly, in order to generate the
12505 right sort of code. We will make them even in the adjust_symtab
12506 routine, while leaving them marked. This is convenient for the
12507 debugger and the disassembler. The linker knows to make them odd
12512 int ignore ATTRIBUTE_UNUSED
;
12514 mips16_mark_labels ();
12516 demand_empty_rest_of_line ();
12519 /* Handle a .stabn directive. We need these in order to mark a label
12520 as being a mips16 text label correctly. Sometimes the compiler
12521 will emit a label, followed by a .stabn, and then switch sections.
12522 If the label and .stabn are in mips16 mode, then the label is
12523 really a mips16 text label. */
12530 mips16_mark_labels ();
12535 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12539 s_mips_weakext (ignore
)
12540 int ignore ATTRIBUTE_UNUSED
;
12547 name
= input_line_pointer
;
12548 c
= get_symbol_end ();
12549 symbolP
= symbol_find_or_make (name
);
12550 S_SET_WEAK (symbolP
);
12551 *input_line_pointer
= c
;
12553 SKIP_WHITESPACE ();
12555 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12557 if (S_IS_DEFINED (symbolP
))
12559 as_bad ("ignoring attempt to redefine symbol %s",
12560 S_GET_NAME (symbolP
));
12561 ignore_rest_of_line ();
12565 if (*input_line_pointer
== ',')
12567 ++input_line_pointer
;
12568 SKIP_WHITESPACE ();
12572 if (exp
.X_op
!= O_symbol
)
12574 as_bad ("bad .weakext directive");
12575 ignore_rest_of_line ();
12578 symbol_set_value_expression (symbolP
, &exp
);
12581 demand_empty_rest_of_line ();
12584 /* Parse a register string into a number. Called from the ECOFF code
12585 to parse .frame. The argument is non-zero if this is the frame
12586 register, so that we can record it in mips_frame_reg. */
12589 tc_get_register (frame
)
12594 SKIP_WHITESPACE ();
12595 if (*input_line_pointer
++ != '$')
12597 as_warn (_("expected `$'"));
12600 else if (ISDIGIT (*input_line_pointer
))
12602 reg
= get_absolute_expression ();
12603 if (reg
< 0 || reg
>= 32)
12605 as_warn (_("Bad register number"));
12611 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12614 input_line_pointer
+= 2;
12616 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12619 input_line_pointer
+= 2;
12621 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12624 input_line_pointer
+= 2;
12626 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12629 input_line_pointer
+= 2;
12631 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12634 input_line_pointer
+= 2;
12636 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12639 input_line_pointer
+= 3;
12641 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12644 input_line_pointer
+= 3;
12646 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12649 input_line_pointer
+= 4;
12653 as_warn (_("Unrecognized register name"));
12655 while (ISALNUM(*input_line_pointer
))
12656 input_line_pointer
++;
12661 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12662 mips_frame_reg_valid
= 1;
12663 mips_cprestore_valid
= 0;
12669 md_section_align (seg
, addr
)
12673 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12676 /* We don't need to align ELF sections to the full alignment.
12677 However, Irix 5 may prefer that we align them at least to a 16
12678 byte boundary. We don't bother to align the sections if we are
12679 targeted for an embedded system. */
12680 if (strcmp (TARGET_OS
, "elf") == 0)
12686 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12689 /* Utility routine, called from above as well. If called while the
12690 input file is still being read, it's only an approximation. (For
12691 example, a symbol may later become defined which appeared to be
12692 undefined earlier.) */
12695 nopic_need_relax (sym
, before_relaxing
)
12697 int before_relaxing
;
12702 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12704 const char *symname
;
12707 /* Find out whether this symbol can be referenced off the $gp
12708 register. It can be if it is smaller than the -G size or if
12709 it is in the .sdata or .sbss section. Certain symbols can
12710 not be referenced off the $gp, although it appears as though
12712 symname
= S_GET_NAME (sym
);
12713 if (symname
!= (const char *) NULL
12714 && (strcmp (symname
, "eprol") == 0
12715 || strcmp (symname
, "etext") == 0
12716 || strcmp (symname
, "_gp") == 0
12717 || strcmp (symname
, "edata") == 0
12718 || strcmp (symname
, "_fbss") == 0
12719 || strcmp (symname
, "_fdata") == 0
12720 || strcmp (symname
, "_ftext") == 0
12721 || strcmp (symname
, "end") == 0
12722 || strcmp (symname
, "_gp_disp") == 0))
12724 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12726 #ifndef NO_ECOFF_DEBUGGING
12727 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12728 && (symbol_get_obj (sym
)->ecoff_extern_size
12729 <= g_switch_value
))
12731 /* We must defer this decision until after the whole
12732 file has been read, since there might be a .extern
12733 after the first use of this symbol. */
12734 || (before_relaxing
12735 #ifndef NO_ECOFF_DEBUGGING
12736 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12738 && S_GET_VALUE (sym
) == 0)
12739 || (S_GET_VALUE (sym
) != 0
12740 && S_GET_VALUE (sym
) <= g_switch_value
)))
12744 const char *segname
;
12746 segname
= segment_name (S_GET_SEGMENT (sym
));
12747 assert (strcmp (segname
, ".lit8") != 0
12748 && strcmp (segname
, ".lit4") != 0);
12749 change
= (strcmp (segname
, ".sdata") != 0
12750 && strcmp (segname
, ".sbss") != 0
12751 && strncmp (segname
, ".sdata.", 7) != 0
12752 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12757 /* We are not optimizing for the $gp register. */
12761 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12762 extended opcode. SEC is the section the frag is in. */
12765 mips16_extended_frag (fragp
, sec
, stretch
)
12771 register const struct mips16_immed_operand
*op
;
12773 int mintiny
, maxtiny
;
12777 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12779 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12782 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12783 op
= mips16_immed_operands
;
12784 while (op
->type
!= type
)
12787 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12792 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12795 maxtiny
= 1 << op
->nbits
;
12800 maxtiny
= (1 << op
->nbits
) - 1;
12805 mintiny
= - (1 << (op
->nbits
- 1));
12806 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12809 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12810 val
= S_GET_VALUE (fragp
->fr_symbol
);
12811 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12817 /* We won't have the section when we are called from
12818 mips_relax_frag. However, we will always have been called
12819 from md_estimate_size_before_relax first. If this is a
12820 branch to a different section, we mark it as such. If SEC is
12821 NULL, and the frag is not marked, then it must be a branch to
12822 the same section. */
12825 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12830 /* Must have been called from md_estimate_size_before_relax. */
12833 fragp
->fr_subtype
=
12834 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12836 /* FIXME: We should support this, and let the linker
12837 catch branches and loads that are out of range. */
12838 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12839 _("unsupported PC relative reference to different section"));
12843 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12844 /* Assume non-extended on the first relaxation pass.
12845 The address we have calculated will be bogus if this is
12846 a forward branch to another frag, as the forward frag
12847 will have fr_address == 0. */
12851 /* In this case, we know for sure that the symbol fragment is in
12852 the same section. If the relax_marker of the symbol fragment
12853 differs from the relax_marker of this fragment, we have not
12854 yet adjusted the symbol fragment fr_address. We want to add
12855 in STRETCH in order to get a better estimate of the address.
12856 This particularly matters because of the shift bits. */
12858 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12862 /* Adjust stretch for any alignment frag. Note that if have
12863 been expanding the earlier code, the symbol may be
12864 defined in what appears to be an earlier frag. FIXME:
12865 This doesn't handle the fr_subtype field, which specifies
12866 a maximum number of bytes to skip when doing an
12868 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12870 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12873 stretch
= - ((- stretch
)
12874 & ~ ((1 << (int) f
->fr_offset
) - 1));
12876 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12885 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12887 /* The base address rules are complicated. The base address of
12888 a branch is the following instruction. The base address of a
12889 PC relative load or add is the instruction itself, but if it
12890 is in a delay slot (in which case it can not be extended) use
12891 the address of the instruction whose delay slot it is in. */
12892 if (type
== 'p' || type
== 'q')
12896 /* If we are currently assuming that this frag should be
12897 extended, then, the current address is two bytes
12899 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12902 /* Ignore the low bit in the target, since it will be set
12903 for a text label. */
12904 if ((val
& 1) != 0)
12907 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12909 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12912 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12914 /* Branch offsets have an implicit 0 in the lowest bit. */
12915 if (type
== 'p' || type
== 'q')
12918 /* If any of the shifted bits are set, we must use an extended
12919 opcode. If the address depends on the size of this
12920 instruction, this can lead to a loop, so we arrange to always
12921 use an extended opcode. We only check this when we are in
12922 the main relaxation loop, when SEC is NULL. */
12923 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12925 fragp
->fr_subtype
=
12926 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12930 /* If we are about to mark a frag as extended because the value
12931 is precisely maxtiny + 1, then there is a chance of an
12932 infinite loop as in the following code:
12937 In this case when the la is extended, foo is 0x3fc bytes
12938 away, so the la can be shrunk, but then foo is 0x400 away, so
12939 the la must be extended. To avoid this loop, we mark the
12940 frag as extended if it was small, and is about to become
12941 extended with a value of maxtiny + 1. */
12942 if (val
== ((maxtiny
+ 1) << op
->shift
)
12943 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12946 fragp
->fr_subtype
=
12947 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12951 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12952 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12954 if ((val
& ((1 << op
->shift
) - 1)) != 0
12955 || val
< (mintiny
<< op
->shift
)
12956 || val
> (maxtiny
<< op
->shift
))
12962 /* Compute the length of a branch sequence, and adjust the
12963 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12964 worst-case length is computed, with UPDATE being used to indicate
12965 whether an unconditional (-1), branch-likely (+1) or regular (0)
12966 branch is to be computed. */
12968 relaxed_branch_length (fragp
, sec
, update
)
12973 bfd_boolean toofar
;
12977 && S_IS_DEFINED (fragp
->fr_symbol
)
12978 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12983 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12985 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12989 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12992 /* If the symbol is not defined or it's in a different segment,
12993 assume the user knows what's going on and emit a short
12999 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13001 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13002 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13003 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13009 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13012 if (mips_pic
!= NO_PIC
)
13014 /* Additional space for PIC loading of target address. */
13016 if (mips_opts
.isa
== ISA_MIPS1
)
13017 /* Additional space for $at-stabilizing nop. */
13021 /* If branch is conditional. */
13022 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13029 /* Estimate the size of a frag before relaxing. Unless this is the
13030 mips16, we are not really relaxing here, and the final size is
13031 encoded in the subtype information. For the mips16, we have to
13032 decide whether we are using an extended opcode or not. */
13035 md_estimate_size_before_relax (fragp
, segtype
)
13040 bfd_boolean linkonce
= FALSE
;
13042 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13045 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13047 return fragp
->fr_var
;
13050 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13051 /* We don't want to modify the EXTENDED bit here; it might get us
13052 into infinite loops. We change it only in mips_relax_frag(). */
13053 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13055 if (mips_pic
== NO_PIC
)
13057 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13059 else if (mips_pic
== SVR4_PIC
)
13064 sym
= fragp
->fr_symbol
;
13066 /* Handle the case of a symbol equated to another symbol. */
13067 while (symbol_equated_reloc_p (sym
))
13071 /* It's possible to get a loop here in a badly written
13073 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13079 symsec
= S_GET_SEGMENT (sym
);
13081 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13082 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13084 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13088 /* The GNU toolchain uses an extension for ELF: a section
13089 beginning with the magic string .gnu.linkonce is a linkonce
13091 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13092 sizeof ".gnu.linkonce" - 1) == 0)
13096 /* This must duplicate the test in adjust_reloc_syms. */
13097 change
= (symsec
!= &bfd_und_section
13098 && symsec
!= &bfd_abs_section
13099 && ! bfd_is_com_section (symsec
)
13102 /* A global or weak symbol is treated as external. */
13103 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13104 || (! S_IS_WEAK (sym
)
13105 && (! S_IS_EXTERNAL (sym
)
13106 || mips_pic
== EMBEDDED_PIC
)))
13115 /* Record the offset to the first reloc in the fr_opcode field.
13116 This lets md_convert_frag and tc_gen_reloc know that the code
13117 must be expanded. */
13118 fragp
->fr_opcode
= (fragp
->fr_literal
13120 - RELAX_OLD (fragp
->fr_subtype
)
13121 + RELAX_RELOC1 (fragp
->fr_subtype
));
13122 /* FIXME: This really needs as_warn_where. */
13123 if (RELAX_WARN (fragp
->fr_subtype
))
13124 as_warn (_("AT used after \".set noat\" or macro used after "
13125 "\".set nomacro\""));
13127 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
13133 /* This is called to see whether a reloc against a defined symbol
13134 should be converted into a reloc against a section. Don't adjust
13135 MIPS16 jump relocations, so we don't have to worry about the format
13136 of the offset in the .o file. Don't adjust relocations against
13137 mips16 symbols, so that the linker can find them if it needs to set
13141 mips_fix_adjustable (fixp
)
13144 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13147 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13148 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13151 if (fixp
->fx_addsy
== NULL
)
13155 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13156 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13157 && fixp
->fx_subsy
== NULL
)
13164 /* Translate internal representation of relocation info to BFD target
13168 tc_gen_reloc (section
, fixp
)
13169 asection
*section ATTRIBUTE_UNUSED
;
13172 static arelent
*retval
[4];
13174 bfd_reloc_code_real_type code
;
13176 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
13179 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13180 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13181 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13183 if (mips_pic
== EMBEDDED_PIC
13184 && SWITCH_TABLE (fixp
))
13186 /* For a switch table entry we use a special reloc. The addend
13187 is actually the difference between the reloc address and the
13189 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13190 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13191 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13192 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13194 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
13196 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13197 reloc
->addend
= fixp
->fx_addnumber
;
13200 /* We use a special addend for an internal RELLO reloc. */
13201 if (symbol_section_p (fixp
->fx_addsy
))
13202 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13204 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13207 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13209 assert (fixp
->fx_next
!= NULL
13210 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13212 /* The reloc is relative to the RELLO; adjust the addend
13214 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13215 reloc
->addend
= fixp
->fx_next
->fx_addnumber
;
13218 /* We use a special addend for an internal RELHI reloc. */
13219 if (symbol_section_p (fixp
->fx_addsy
))
13220 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
13221 + fixp
->fx_next
->fx_where
13222 - S_GET_VALUE (fixp
->fx_subsy
));
13224 reloc
->addend
= (fixp
->fx_addnumber
13225 + fixp
->fx_next
->fx_frag
->fr_address
13226 + fixp
->fx_next
->fx_where
);
13229 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13230 reloc
->addend
= fixp
->fx_addnumber
;
13233 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13234 /* A gruesome hack which is a result of the gruesome gas reloc
13236 reloc
->addend
= reloc
->address
;
13238 reloc
->addend
= -reloc
->address
;
13241 /* If this is a variant frag, we may need to adjust the existing
13242 reloc and generate a new one. */
13243 if (fixp
->fx_frag
->fr_opcode
!= NULL
13244 && ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13246 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
13247 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
13248 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13249 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
13250 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13251 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
13256 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
13258 /* If this is not the last reloc in this frag, then we have two
13259 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
13260 CALL_HI16/CALL_LO16, both of which are being replaced. Let
13261 the second one handle all of them. */
13262 if (fixp
->fx_next
!= NULL
13263 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
13265 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
13266 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
13267 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
13268 && (fixp
->fx_next
->fx_r_type
13269 == BFD_RELOC_MIPS_GOT_LO16
))
13270 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
13271 && (fixp
->fx_next
->fx_r_type
13272 == BFD_RELOC_MIPS_CALL_LO16
)));
13277 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
13278 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13279 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
13281 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13282 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13283 reloc2
->address
= (reloc
->address
13284 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
13285 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
13286 reloc2
->addend
= fixp
->fx_addnumber
;
13287 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
13288 assert (reloc2
->howto
!= NULL
);
13290 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
13294 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
13297 reloc3
->address
+= 4;
13300 if (mips_pic
== NO_PIC
)
13302 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
13303 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
13305 else if (mips_pic
== SVR4_PIC
)
13307 switch (fixp
->fx_r_type
)
13311 case BFD_RELOC_MIPS_GOT16
:
13313 case BFD_RELOC_MIPS_GOT_LO16
:
13314 case BFD_RELOC_MIPS_CALL_LO16
:
13315 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13317 case BFD_RELOC_MIPS_CALL16
:
13320 /* BFD_RELOC_MIPS_GOT16;*/
13321 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_PAGE
;
13322 reloc2
->howto
= bfd_reloc_type_lookup
13323 (stdoutput
, BFD_RELOC_MIPS_GOT_OFST
);
13326 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
13333 /* newabi uses R_MIPS_GOT_DISP for local symbols */
13334 if (HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
)
13336 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT_DISP
;
13341 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13342 entry to be used in the relocation's section offset. */
13343 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13345 reloc
->address
= reloc
->addend
;
13349 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13350 fixup_segment converted a non-PC relative reloc into a PC
13351 relative reloc. In such a case, we need to convert the reloc
13353 code
= fixp
->fx_r_type
;
13354 if (fixp
->fx_pcrel
)
13359 code
= BFD_RELOC_8_PCREL
;
13362 code
= BFD_RELOC_16_PCREL
;
13365 code
= BFD_RELOC_32_PCREL
;
13368 code
= BFD_RELOC_64_PCREL
;
13370 case BFD_RELOC_8_PCREL
:
13371 case BFD_RELOC_16_PCREL
:
13372 case BFD_RELOC_32_PCREL
:
13373 case BFD_RELOC_64_PCREL
:
13374 case BFD_RELOC_16_PCREL_S2
:
13375 case BFD_RELOC_PCREL_HI16_S
:
13376 case BFD_RELOC_PCREL_LO16
:
13379 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13380 _("Cannot make %s relocation PC relative"),
13381 bfd_get_reloc_code_name (code
));
13386 /* md_apply_fix3 has a double-subtraction hack to get
13387 bfd_install_relocation to behave nicely. GPREL relocations are
13388 handled correctly without this hack, so undo it here. We can't
13389 stop md_apply_fix3 from subtracting twice in the first place since
13390 the fake addend is required for variant frags above. */
13391 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
13392 && (code
== BFD_RELOC_GPREL16
|| code
== BFD_RELOC_MIPS16_GPREL
)
13393 && reloc
->addend
!= 0
13394 && mips_need_elf_addend_fixup (fixp
))
13395 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
13398 /* To support a PC relative reloc when generating embedded PIC code
13399 for ECOFF, we use a Cygnus extension. We check for that here to
13400 make sure that we don't let such a reloc escape normally. */
13401 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13402 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13403 && code
== BFD_RELOC_16_PCREL_S2
13404 && mips_pic
!= EMBEDDED_PIC
)
13405 reloc
->howto
= NULL
;
13407 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13409 if (reloc
->howto
== NULL
)
13411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13412 _("Can not represent %s relocation in this object file format"),
13413 bfd_get_reloc_code_name (code
));
13420 /* Relax a machine dependent frag. This returns the amount by which
13421 the current size of the frag should change. */
13424 mips_relax_frag (sec
, fragp
, stretch
)
13429 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13431 offsetT old_var
= fragp
->fr_var
;
13433 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13435 return fragp
->fr_var
- old_var
;
13438 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13441 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13443 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13445 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13450 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13452 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13459 /* Convert a machine dependent frag. */
13462 md_convert_frag (abfd
, asec
, fragp
)
13463 bfd
*abfd ATTRIBUTE_UNUSED
;
13470 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13473 unsigned long insn
;
13477 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13479 if (target_big_endian
)
13480 insn
= bfd_getb32 (buf
);
13482 insn
= bfd_getl32 (buf
);
13484 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13486 /* We generate a fixup instead of applying it right now
13487 because, if there are linker relaxations, we're going to
13488 need the relocations. */
13489 exp
.X_op
= O_symbol
;
13490 exp
.X_add_symbol
= fragp
->fr_symbol
;
13491 exp
.X_add_number
= fragp
->fr_offset
;
13493 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13495 BFD_RELOC_16_PCREL_S2
);
13496 fixp
->fx_file
= fragp
->fr_file
;
13497 fixp
->fx_line
= fragp
->fr_line
;
13499 md_number_to_chars ((char *)buf
, insn
, 4);
13506 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13507 _("relaxed out-of-range branch into a jump"));
13509 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13512 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13514 /* Reverse the branch. */
13515 switch ((insn
>> 28) & 0xf)
13518 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13519 have the condition reversed by tweaking a single
13520 bit, and their opcodes all have 0x4???????. */
13521 assert ((insn
& 0xf1000000) == 0x41000000);
13522 insn
^= 0x00010000;
13526 /* bltz 0x04000000 bgez 0x04010000
13527 bltzal 0x04100000 bgezal 0x04110000 */
13528 assert ((insn
& 0xfc0e0000) == 0x04000000);
13529 insn
^= 0x00010000;
13533 /* beq 0x10000000 bne 0x14000000
13534 blez 0x18000000 bgtz 0x1c000000 */
13535 insn
^= 0x04000000;
13543 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13545 /* Clear the and-link bit. */
13546 assert ((insn
& 0xfc1c0000) == 0x04100000);
13548 /* bltzal 0x04100000 bgezal 0x04110000
13549 bltzall 0x04120000 bgezall 0x04130000 */
13550 insn
&= ~0x00100000;
13553 /* Branch over the branch (if the branch was likely) or the
13554 full jump (not likely case). Compute the offset from the
13555 current instruction to branch to. */
13556 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13560 /* How many bytes in instructions we've already emitted? */
13561 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13562 /* How many bytes in instructions from here to the end? */
13563 i
= fragp
->fr_var
- i
;
13565 /* Convert to instruction count. */
13567 /* Branch counts from the next instruction. */
13570 /* Branch over the jump. */
13571 md_number_to_chars ((char *)buf
, insn
, 4);
13575 md_number_to_chars ((char*)buf
, 0, 4);
13578 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13580 /* beql $0, $0, 2f */
13582 /* Compute the PC offset from the current instruction to
13583 the end of the variable frag. */
13584 /* How many bytes in instructions we've already emitted? */
13585 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13586 /* How many bytes in instructions from here to the end? */
13587 i
= fragp
->fr_var
- i
;
13588 /* Convert to instruction count. */
13590 /* Don't decrement i, because we want to branch over the
13594 md_number_to_chars ((char *)buf
, insn
, 4);
13597 md_number_to_chars ((char *)buf
, 0, 4);
13602 if (mips_pic
== NO_PIC
)
13605 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13606 ? 0x0c000000 : 0x08000000);
13607 exp
.X_op
= O_symbol
;
13608 exp
.X_add_symbol
= fragp
->fr_symbol
;
13609 exp
.X_add_number
= fragp
->fr_offset
;
13611 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13612 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13613 fixp
->fx_file
= fragp
->fr_file
;
13614 fixp
->fx_line
= fragp
->fr_line
;
13616 md_number_to_chars ((char*)buf
, insn
, 4);
13621 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13622 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13623 exp
.X_op
= O_symbol
;
13624 exp
.X_add_symbol
= fragp
->fr_symbol
;
13625 exp
.X_add_number
= fragp
->fr_offset
;
13627 if (fragp
->fr_offset
)
13629 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13630 exp
.X_add_number
= 0;
13633 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13634 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13635 fixp
->fx_file
= fragp
->fr_file
;
13636 fixp
->fx_line
= fragp
->fr_line
;
13638 md_number_to_chars ((char*)buf
, insn
, 4);
13641 if (mips_opts
.isa
== ISA_MIPS1
)
13644 md_number_to_chars ((char*)buf
, 0, 4);
13648 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13649 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13651 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13652 4, &exp
, 0, BFD_RELOC_LO16
);
13653 fixp
->fx_file
= fragp
->fr_file
;
13654 fixp
->fx_line
= fragp
->fr_line
;
13656 md_number_to_chars ((char*)buf
, insn
, 4);
13660 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13665 md_number_to_chars ((char*)buf
, insn
, 4);
13670 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13671 + fragp
->fr_fix
+ fragp
->fr_var
);
13673 fragp
->fr_fix
+= fragp
->fr_var
;
13678 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13681 register const struct mips16_immed_operand
*op
;
13682 bfd_boolean small
, ext
;
13685 unsigned long insn
;
13686 bfd_boolean use_extend
;
13687 unsigned short extend
;
13689 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13690 op
= mips16_immed_operands
;
13691 while (op
->type
!= type
)
13694 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13705 resolve_symbol_value (fragp
->fr_symbol
);
13706 val
= S_GET_VALUE (fragp
->fr_symbol
);
13711 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13713 /* The rules for the base address of a PC relative reloc are
13714 complicated; see mips16_extended_frag. */
13715 if (type
== 'p' || type
== 'q')
13720 /* Ignore the low bit in the target, since it will be
13721 set for a text label. */
13722 if ((val
& 1) != 0)
13725 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13727 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13730 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13733 /* Make sure the section winds up with the alignment we have
13736 record_alignment (asec
, op
->shift
);
13740 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13741 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13742 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13743 _("extended instruction in delay slot"));
13745 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13747 if (target_big_endian
)
13748 insn
= bfd_getb16 (buf
);
13750 insn
= bfd_getl16 (buf
);
13752 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13753 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13754 small
, ext
, &insn
, &use_extend
, &extend
);
13758 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13759 fragp
->fr_fix
+= 2;
13763 md_number_to_chars ((char *) buf
, insn
, 2);
13764 fragp
->fr_fix
+= 2;
13769 if (fragp
->fr_opcode
== NULL
)
13772 old
= RELAX_OLD (fragp
->fr_subtype
);
13773 new = RELAX_NEW (fragp
->fr_subtype
);
13774 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
13777 memcpy (fixptr
- old
, fixptr
, new);
13779 fragp
->fr_fix
+= new - old
;
13785 /* This function is called after the relocs have been generated.
13786 We've been storing mips16 text labels as odd. Here we convert them
13787 back to even for the convenience of the debugger. */
13790 mips_frob_file_after_relocs ()
13793 unsigned int count
, i
;
13795 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13798 syms
= bfd_get_outsymbols (stdoutput
);
13799 count
= bfd_get_symcount (stdoutput
);
13800 for (i
= 0; i
< count
; i
++, syms
++)
13802 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13803 && ((*syms
)->value
& 1) != 0)
13805 (*syms
)->value
&= ~1;
13806 /* If the symbol has an odd size, it was probably computed
13807 incorrectly, so adjust that as well. */
13808 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13809 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13816 /* This function is called whenever a label is defined. It is used
13817 when handling branch delays; if a branch has a label, we assume we
13818 can not move it. */
13821 mips_define_label (sym
)
13824 struct insn_label_list
*l
;
13826 if (free_insn_labels
== NULL
)
13827 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13830 l
= free_insn_labels
;
13831 free_insn_labels
= l
->next
;
13835 l
->next
= insn_labels
;
13839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13841 /* Some special processing for a MIPS ELF file. */
13844 mips_elf_final_processing ()
13846 /* Write out the register information. */
13847 if (mips_abi
!= N64_ABI
)
13851 s
.ri_gprmask
= mips_gprmask
;
13852 s
.ri_cprmask
[0] = mips_cprmask
[0];
13853 s
.ri_cprmask
[1] = mips_cprmask
[1];
13854 s
.ri_cprmask
[2] = mips_cprmask
[2];
13855 s
.ri_cprmask
[3] = mips_cprmask
[3];
13856 /* The gp_value field is set by the MIPS ELF backend. */
13858 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13859 ((Elf32_External_RegInfo
*)
13860 mips_regmask_frag
));
13864 Elf64_Internal_RegInfo s
;
13866 s
.ri_gprmask
= mips_gprmask
;
13868 s
.ri_cprmask
[0] = mips_cprmask
[0];
13869 s
.ri_cprmask
[1] = mips_cprmask
[1];
13870 s
.ri_cprmask
[2] = mips_cprmask
[2];
13871 s
.ri_cprmask
[3] = mips_cprmask
[3];
13872 /* The gp_value field is set by the MIPS ELF backend. */
13874 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13875 ((Elf64_External_RegInfo
*)
13876 mips_regmask_frag
));
13879 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13880 sort of BFD interface for this. */
13881 if (mips_any_noreorder
)
13882 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13883 if (mips_pic
!= NO_PIC
)
13884 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13886 /* Set MIPS ELF flags for ASEs. */
13887 if (file_ase_mips16
)
13888 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13889 #if 0 /* XXX FIXME */
13890 if (file_ase_mips3d
)
13891 elf_elfheader (stdoutput
)->e_flags
|= ???;
13894 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13896 /* Set the MIPS ELF ABI flags. */
13897 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13898 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13899 else if (mips_abi
== O64_ABI
)
13900 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13901 else if (mips_abi
== EABI_ABI
)
13903 if (!file_mips_gp32
)
13904 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13906 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13908 else if (mips_abi
== N32_ABI
)
13909 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13911 /* Nothing to do for N64_ABI. */
13913 if (mips_32bitmode
)
13914 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13917 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13919 typedef struct proc
{
13921 unsigned long reg_mask
;
13922 unsigned long reg_offset
;
13923 unsigned long fpreg_mask
;
13924 unsigned long fpreg_offset
;
13925 unsigned long frame_offset
;
13926 unsigned long frame_reg
;
13927 unsigned long pc_reg
;
13930 static procS cur_proc
;
13931 static procS
*cur_proc_ptr
;
13932 static int numprocs
;
13934 /* Fill in an rs_align_code fragment. */
13937 mips_handle_align (fragp
)
13940 if (fragp
->fr_type
!= rs_align_code
)
13943 if (mips_opts
.mips16
)
13945 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13946 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13951 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13952 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13960 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13964 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13975 /* check for premature end, nesting errors, etc */
13977 as_warn (_("missing .end at end of assembly"));
13986 if (*input_line_pointer
== '-')
13988 ++input_line_pointer
;
13991 if (!ISDIGIT (*input_line_pointer
))
13992 as_bad (_("expected simple number"));
13993 if (input_line_pointer
[0] == '0')
13995 if (input_line_pointer
[1] == 'x')
13997 input_line_pointer
+= 2;
13998 while (ISXDIGIT (*input_line_pointer
))
14001 val
|= hex_value (*input_line_pointer
++);
14003 return negative
? -val
: val
;
14007 ++input_line_pointer
;
14008 while (ISDIGIT (*input_line_pointer
))
14011 val
|= *input_line_pointer
++ - '0';
14013 return negative
? -val
: val
;
14016 if (!ISDIGIT (*input_line_pointer
))
14018 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14019 *input_line_pointer
, *input_line_pointer
);
14020 as_warn (_("invalid number"));
14023 while (ISDIGIT (*input_line_pointer
))
14026 val
+= *input_line_pointer
++ - '0';
14028 return negative
? -val
: val
;
14031 /* The .file directive; just like the usual .file directive, but there
14032 is an initial number which is the ECOFF file index. In the non-ECOFF
14033 case .file implies DWARF-2. */
14037 int x ATTRIBUTE_UNUSED
;
14039 static int first_file_directive
= 0;
14041 if (ECOFF_DEBUGGING
)
14050 filename
= dwarf2_directive_file (0);
14052 /* Versions of GCC up to 3.1 start files with a ".file"
14053 directive even for stabs output. Make sure that this
14054 ".file" is handled. Note that you need a version of GCC
14055 after 3.1 in order to support DWARF-2 on MIPS. */
14056 if (filename
!= NULL
&& ! first_file_directive
)
14058 (void) new_logical_line (filename
, -1);
14059 s_app_file_string (filename
);
14061 first_file_directive
= 1;
14065 /* The .loc directive, implying DWARF-2. */
14069 int x ATTRIBUTE_UNUSED
;
14071 if (!ECOFF_DEBUGGING
)
14072 dwarf2_directive_loc (0);
14075 /* The .end directive. */
14079 int x ATTRIBUTE_UNUSED
;
14084 /* Following functions need their own .frame and .cprestore directives. */
14085 mips_frame_reg_valid
= 0;
14086 mips_cprestore_valid
= 0;
14088 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14091 demand_empty_rest_of_line ();
14096 #ifdef BFD_ASSEMBLER
14097 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14102 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14109 as_warn (_(".end not in text section"));
14113 as_warn (_(".end directive without a preceding .ent directive."));
14114 demand_empty_rest_of_line ();
14120 assert (S_GET_NAME (p
));
14121 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
14122 as_warn (_(".end symbol does not match .ent symbol."));
14124 if (debug_type
== DEBUG_STABS
)
14125 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14129 as_warn (_(".end directive missing or unknown symbol"));
14132 /* Generate a .pdr section. */
14133 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14135 segT saved_seg
= now_seg
;
14136 subsegT saved_subseg
= now_subseg
;
14141 dot
= frag_now_fix ();
14143 #ifdef md_flush_pending_output
14144 md_flush_pending_output ();
14148 subseg_set (pdr_seg
, 0);
14150 /* Write the symbol. */
14151 exp
.X_op
= O_symbol
;
14152 exp
.X_add_symbol
= p
;
14153 exp
.X_add_number
= 0;
14154 emit_expr (&exp
, 4);
14156 fragp
= frag_more (7 * 4);
14158 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
14159 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
14160 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
14161 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
14162 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
14163 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
14164 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
14166 subseg_set (saved_seg
, saved_subseg
);
14168 #endif /* OBJ_ELF */
14170 cur_proc_ptr
= NULL
;
14173 /* The .aent and .ent directives. */
14182 symbolP
= get_symbol ();
14183 if (*input_line_pointer
== ',')
14184 ++input_line_pointer
;
14185 SKIP_WHITESPACE ();
14186 if (ISDIGIT (*input_line_pointer
)
14187 || *input_line_pointer
== '-')
14190 #ifdef BFD_ASSEMBLER
14191 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14196 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
14203 as_warn (_(".ent or .aent not in text section."));
14205 if (!aent
&& cur_proc_ptr
)
14206 as_warn (_("missing .end"));
14210 /* This function needs its own .frame and .cprestore directives. */
14211 mips_frame_reg_valid
= 0;
14212 mips_cprestore_valid
= 0;
14214 cur_proc_ptr
= &cur_proc
;
14215 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14217 cur_proc_ptr
->isym
= symbolP
;
14219 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14223 if (debug_type
== DEBUG_STABS
)
14224 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14225 S_GET_NAME (symbolP
));
14228 demand_empty_rest_of_line ();
14231 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14232 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14233 s_mips_frame is used so that we can set the PDR information correctly.
14234 We can't use the ecoff routines because they make reference to the ecoff
14235 symbol table (in the mdebug section). */
14238 s_mips_frame (ignore
)
14239 int ignore ATTRIBUTE_UNUSED
;
14242 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14246 if (cur_proc_ptr
== (procS
*) NULL
)
14248 as_warn (_(".frame outside of .ent"));
14249 demand_empty_rest_of_line ();
14253 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14255 SKIP_WHITESPACE ();
14256 if (*input_line_pointer
++ != ','
14257 || get_absolute_expression_and_terminator (&val
) != ',')
14259 as_warn (_("Bad .frame directive"));
14260 --input_line_pointer
;
14261 demand_empty_rest_of_line ();
14265 cur_proc_ptr
->frame_offset
= val
;
14266 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14268 demand_empty_rest_of_line ();
14271 #endif /* OBJ_ELF */
14275 /* The .fmask and .mask directives. If the mdebug section is present
14276 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14277 embedded targets, s_mips_mask is used so that we can set the PDR
14278 information correctly. We can't use the ecoff routines because they
14279 make reference to the ecoff symbol table (in the mdebug section). */
14282 s_mips_mask (reg_type
)
14286 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14290 if (cur_proc_ptr
== (procS
*) NULL
)
14292 as_warn (_(".mask/.fmask outside of .ent"));
14293 demand_empty_rest_of_line ();
14297 if (get_absolute_expression_and_terminator (&mask
) != ',')
14299 as_warn (_("Bad .mask/.fmask directive"));
14300 --input_line_pointer
;
14301 demand_empty_rest_of_line ();
14305 off
= get_absolute_expression ();
14307 if (reg_type
== 'F')
14309 cur_proc_ptr
->fpreg_mask
= mask
;
14310 cur_proc_ptr
->fpreg_offset
= off
;
14314 cur_proc_ptr
->reg_mask
= mask
;
14315 cur_proc_ptr
->reg_offset
= off
;
14318 demand_empty_rest_of_line ();
14321 #endif /* OBJ_ELF */
14322 s_ignore (reg_type
);
14325 /* The .loc directive. */
14336 assert (now_seg
== text_section
);
14338 lineno
= get_number ();
14339 addroff
= frag_now_fix ();
14341 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14342 S_SET_TYPE (symbolP
, N_SLINE
);
14343 S_SET_OTHER (symbolP
, 0);
14344 S_SET_DESC (symbolP
, lineno
);
14345 symbolP
->sy_segment
= now_seg
;
14349 /* A table describing all the processors gas knows about. Names are
14350 matched in the order listed.
14352 To ease comparison, please keep this table in the same order as
14353 gcc's mips_cpu_info_table[]. */
14354 static const struct mips_cpu_info mips_cpu_info_table
[] =
14356 /* Entries for generic ISAs */
14357 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14358 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14359 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14360 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14361 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14362 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14363 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14366 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14367 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14368 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14371 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14374 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14375 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14376 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14377 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14378 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14379 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14380 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14381 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14382 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14383 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14384 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14385 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14388 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14389 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14390 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14391 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14392 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14393 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14394 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14395 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14396 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14397 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14398 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14399 { "r7000", 0, ISA_MIPS4
, CPU_R5000
},
14402 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
14403 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14404 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14407 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14408 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14410 /* Broadcom SB-1 CPU core */
14411 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14418 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14419 with a final "000" replaced by "k". Ignore case.
14421 Note: this function is shared between GCC and GAS. */
14424 mips_strict_matching_cpu_name_p (canonical
, given
)
14425 const char *canonical
, *given
;
14427 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14428 given
++, canonical
++;
14430 return ((*given
== 0 && *canonical
== 0)
14431 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14435 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14436 CPU name. We've traditionally allowed a lot of variation here.
14438 Note: this function is shared between GCC and GAS. */
14441 mips_matching_cpu_name_p (canonical
, given
)
14442 const char *canonical
, *given
;
14444 /* First see if the name matches exactly, or with a final "000"
14445 turned into "k". */
14446 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14449 /* If not, try comparing based on numerical designation alone.
14450 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14451 if (TOLOWER (*given
) == 'r')
14453 if (!ISDIGIT (*given
))
14456 /* Skip over some well-known prefixes in the canonical name,
14457 hoping to find a number there too. */
14458 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14460 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14462 else if (TOLOWER (canonical
[0]) == 'r')
14465 return mips_strict_matching_cpu_name_p (canonical
, given
);
14469 /* Parse an option that takes the name of a processor as its argument.
14470 OPTION is the name of the option and CPU_STRING is the argument.
14471 Return the corresponding processor enumeration if the CPU_STRING is
14472 recognized, otherwise report an error and return null.
14474 A similar function exists in GCC. */
14476 static const struct mips_cpu_info
*
14477 mips_parse_cpu (option
, cpu_string
)
14478 const char *option
, *cpu_string
;
14480 const struct mips_cpu_info
*p
;
14482 /* 'from-abi' selects the most compatible architecture for the given
14483 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14484 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14485 version. Look first at the -mgp options, if given, otherwise base
14486 the choice on MIPS_DEFAULT_64BIT.
14488 Treat NO_ABI like the EABIs. One reason to do this is that the
14489 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14490 architecture. This code picks MIPS I for 'mips' and MIPS III for
14491 'mips64', just as we did in the days before 'from-abi'. */
14492 if (strcasecmp (cpu_string
, "from-abi") == 0)
14494 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14495 return mips_cpu_info_from_isa (ISA_MIPS1
);
14497 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14498 return mips_cpu_info_from_isa (ISA_MIPS3
);
14500 if (file_mips_gp32
>= 0)
14501 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14503 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14508 /* 'default' has traditionally been a no-op. Probably not very useful. */
14509 if (strcasecmp (cpu_string
, "default") == 0)
14512 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14513 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14516 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14520 /* Return the canonical processor information for ISA (a member of the
14521 ISA_MIPS* enumeration). */
14523 static const struct mips_cpu_info
*
14524 mips_cpu_info_from_isa (isa
)
14529 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14530 if (mips_cpu_info_table
[i
].is_isa
14531 && isa
== mips_cpu_info_table
[i
].isa
)
14532 return (&mips_cpu_info_table
[i
]);
14538 show (stream
, string
, col_p
, first_p
)
14540 const char *string
;
14546 fprintf (stream
, "%24s", "");
14551 fprintf (stream
, ", ");
14555 if (*col_p
+ strlen (string
) > 72)
14557 fprintf (stream
, "\n%24s", "");
14561 fprintf (stream
, "%s", string
);
14562 *col_p
+= strlen (string
);
14568 md_show_usage (stream
)
14574 fprintf (stream
, _("\
14576 -membedded-pic generate embedded position independent code\n\
14577 -EB generate big endian output\n\
14578 -EL generate little endian output\n\
14579 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14580 -G NUM allow referencing objects up to NUM bytes\n\
14581 implicitly with the gp register [default 8]\n"));
14582 fprintf (stream
, _("\
14583 -mips1 generate MIPS ISA I instructions\n\
14584 -mips2 generate MIPS ISA II instructions\n\
14585 -mips3 generate MIPS ISA III instructions\n\
14586 -mips4 generate MIPS ISA IV instructions\n\
14587 -mips5 generate MIPS ISA V instructions\n\
14588 -mips32 generate MIPS32 ISA instructions\n\
14589 -mips64 generate MIPS64 ISA instructions\n\
14590 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14594 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14595 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14596 show (stream
, "from-abi", &column
, &first
);
14597 fputc ('\n', stream
);
14599 fprintf (stream
, _("\
14600 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14601 -no-mCPU don't generate code specific to CPU.\n\
14602 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14606 show (stream
, "3900", &column
, &first
);
14607 show (stream
, "4010", &column
, &first
);
14608 show (stream
, "4100", &column
, &first
);
14609 show (stream
, "4650", &column
, &first
);
14610 fputc ('\n', stream
);
14612 fprintf (stream
, _("\
14613 -mips16 generate mips16 instructions\n\
14614 -no-mips16 do not generate mips16 instructions\n"));
14615 fprintf (stream
, _("\
14616 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14617 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14618 -O0 remove unneeded NOPs, do not swap branches\n\
14619 -O remove unneeded NOPs and swap branches\n\
14620 -n warn about NOPs generated from macros\n\
14621 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14622 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14623 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14625 fprintf (stream
, _("\
14626 -KPIC, -call_shared generate SVR4 position independent code\n\
14627 -non_shared do not generate position independent code\n\
14628 -xgot assume a 32 bit GOT\n\
14629 -mabi=ABI create ABI conformant object file for:\n"));
14633 show (stream
, "32", &column
, &first
);
14634 show (stream
, "o64", &column
, &first
);
14635 show (stream
, "n32", &column
, &first
);
14636 show (stream
, "64", &column
, &first
);
14637 show (stream
, "eabi", &column
, &first
);
14639 fputc ('\n', stream
);
14641 fprintf (stream
, _("\
14642 -32 create o32 ABI object file (default)\n\
14643 -n32 create n32 ABI object file\n\
14644 -64 create 64 ABI object file\n"));
14649 mips_dwarf2_format ()
14651 if (mips_abi
== N64_ABI
)
14652 return dwarf2_format_64bit_irix
;
14654 return dwarf2_format_32bit
;