1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
39 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian
;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode
*insn_mo
;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p
: 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p
: 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi
= NO_ABI
;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls
= FALSE
;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared
= TRUE
;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros
;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float
;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float
;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32
= -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32
= -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float
= 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float
= 0;
275 static struct mips_set_options mips_opts
=
277 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
278 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
279 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
280 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
281 /* soft_float */ FALSE
, /* single_float */ FALSE
284 /* The set of ASEs that were selected on the command line, either
285 explicitly via ASE options or implicitly through things like -march. */
286 static unsigned int file_ase
;
288 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
289 static unsigned int file_ase_explicit
;
291 /* These variables are filled in with the masks of registers used.
292 The object format code reads them and puts them in the appropriate
294 unsigned long mips_gprmask
;
295 unsigned long mips_cprmask
[4];
297 /* MIPS ISA we are using for this output file. */
298 static int file_mips_isa
= ISA_UNKNOWN
;
300 /* True if any MIPS16 code was produced. */
301 static int file_ase_mips16
;
303 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
304 || mips_opts.isa == ISA_MIPS32R2 \
305 || mips_opts.isa == ISA_MIPS64 \
306 || mips_opts.isa == ISA_MIPS64R2)
308 /* True if any microMIPS code was produced. */
309 static int file_ase_micromips
;
311 /* True if we want to create R_MIPS_JALR for jalr $25. */
313 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
315 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318 #define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
323 /* The argument of the -march= flag. The architecture we are assembling. */
324 static int file_mips_arch
= CPU_UNKNOWN
;
325 static const char *mips_arch_string
;
327 /* The argument of the -mtune= flag. The architecture for which we
329 static int mips_tune
= CPU_UNKNOWN
;
330 static const char *mips_tune_string
;
332 /* True when generating 32-bit code for a 64-bit processor. */
333 static int mips_32bitmode
= 0;
335 /* True if the given ABI requires 32-bit registers. */
336 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
338 /* Likewise 64-bit registers. */
339 #define ABI_NEEDS_64BIT_REGS(ABI) \
341 || (ABI) == N64_ABI \
344 /* Return true if ISA supports 64 bit wide gp registers. */
345 #define ISA_HAS_64BIT_REGS(ISA) \
346 ((ISA) == ISA_MIPS3 \
347 || (ISA) == ISA_MIPS4 \
348 || (ISA) == ISA_MIPS5 \
349 || (ISA) == ISA_MIPS64 \
350 || (ISA) == ISA_MIPS64R2)
352 /* Return true if ISA supports 64 bit wide float registers. */
353 #define ISA_HAS_64BIT_FPRS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS32R2 \
358 || (ISA) == ISA_MIPS64 \
359 || (ISA) == ISA_MIPS64R2)
361 /* Return true if ISA supports 64-bit right rotate (dror et al.)
363 #define ISA_HAS_DROR(ISA) \
364 ((ISA) == ISA_MIPS64R2 \
365 || (mips_opts.micromips \
366 && ISA_HAS_64BIT_REGS (ISA)) \
369 /* Return true if ISA supports 32-bit right rotate (ror et al.)
371 #define ISA_HAS_ROR(ISA) \
372 ((ISA) == ISA_MIPS32R2 \
373 || (ISA) == ISA_MIPS64R2 \
374 || (mips_opts.ase & ASE_SMARTMIPS) \
375 || mips_opts.micromips \
378 /* Return true if ISA supports single-precision floats in odd registers. */
379 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
380 ((ISA) == ISA_MIPS32 \
381 || (ISA) == ISA_MIPS32R2 \
382 || (ISA) == ISA_MIPS64 \
383 || (ISA) == ISA_MIPS64R2)
385 /* Return true if ISA supports move to/from high part of a 64-bit
386 floating-point register. */
387 #define ISA_HAS_MXHC1(ISA) \
388 ((ISA) == ISA_MIPS32R2 \
389 || (ISA) == ISA_MIPS64R2)
391 #define HAVE_32BIT_GPRS \
392 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
394 #define HAVE_32BIT_FPRS \
395 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
397 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
398 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
400 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
402 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
404 /* True if relocations are stored in-place. */
405 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
407 /* The ABI-derived address size. */
408 #define HAVE_64BIT_ADDRESSES \
409 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
410 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
412 /* The size of symbolic constants (i.e., expressions of the form
413 "SYMBOL" or "SYMBOL + OFFSET"). */
414 #define HAVE_32BIT_SYMBOLS \
415 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
416 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
418 /* Addresses are loaded in different ways, depending on the address size
419 in use. The n32 ABI Documentation also mandates the use of additions
420 with overflow checking, but existing implementations don't follow it. */
421 #define ADDRESS_ADD_INSN \
422 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
424 #define ADDRESS_ADDI_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
427 #define ADDRESS_LOAD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
430 #define ADDRESS_STORE_INSN \
431 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
433 /* Return true if the given CPU supports the MIPS16 ASE. */
434 #define CPU_HAS_MIPS16(cpu) \
435 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
436 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
438 /* Return true if the given CPU supports the microMIPS ASE. */
439 #define CPU_HAS_MICROMIPS(cpu) 0
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU is in the Octeon family */
448 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
450 /* True if CPU has seq/sne and seqi/snei instructions. */
451 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
453 /* True, if CPU has support for ldc1 and sdc1. */
454 #define CPU_HAS_LDC1_SDC1(CPU) \
455 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
457 /* True if mflo and mfhi can be immediately followed by instructions
458 which write to the HI and LO registers.
460 According to MIPS specifications, MIPS ISAs I, II, and III need
461 (at least) two instructions between the reads of HI/LO and
462 instructions which write them, and later ISAs do not. Contradicting
463 the MIPS specifications, some MIPS IV processor user manuals (e.g.
464 the UM for the NEC Vr5000) document needing the instructions between
465 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
466 MIPS64 and later ISAs to have the interlocks, plus any specific
467 earlier-ISA CPUs for which CPU documentation declares that the
468 instructions are really interlocked. */
469 #define hilo_interlocks \
470 (mips_opts.isa == ISA_MIPS32 \
471 || mips_opts.isa == ISA_MIPS32R2 \
472 || mips_opts.isa == ISA_MIPS64 \
473 || mips_opts.isa == ISA_MIPS64R2 \
474 || mips_opts.arch == CPU_R4010 \
475 || mips_opts.arch == CPU_R5900 \
476 || mips_opts.arch == CPU_R10000 \
477 || mips_opts.arch == CPU_R12000 \
478 || mips_opts.arch == CPU_R14000 \
479 || mips_opts.arch == CPU_R16000 \
480 || mips_opts.arch == CPU_RM7000 \
481 || mips_opts.arch == CPU_VR5500 \
482 || mips_opts.micromips \
485 /* Whether the processor uses hardware interlocks to protect reads
486 from the GPRs after they are loaded from memory, and thus does not
487 require nops to be inserted. This applies to instructions marked
488 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
489 level I and microMIPS mode instructions are always interlocked. */
490 #define gpr_interlocks \
491 (mips_opts.isa != ISA_MIPS1 \
492 || mips_opts.arch == CPU_R3900 \
493 || mips_opts.arch == CPU_R5900 \
494 || mips_opts.micromips \
497 /* Whether the processor uses hardware interlocks to avoid delays
498 required by coprocessor instructions, and thus does not require
499 nops to be inserted. This applies to instructions marked
500 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
501 between instructions marked INSN_WRITE_COND_CODE and ones marked
502 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
503 levels I, II, and III and microMIPS mode instructions are always
505 /* Itbl support may require additional care here. */
506 #define cop_interlocks \
507 ((mips_opts.isa != ISA_MIPS1 \
508 && mips_opts.isa != ISA_MIPS2 \
509 && mips_opts.isa != ISA_MIPS3) \
510 || mips_opts.arch == CPU_R4300 \
511 || mips_opts.micromips \
514 /* Whether the processor uses hardware interlocks to protect reads
515 from coprocessor registers after they are loaded from memory, and
516 thus does not require nops to be inserted. This applies to
517 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
518 requires at MIPS ISA level I and microMIPS mode instructions are
519 always interlocked. */
520 #define cop_mem_interlocks \
521 (mips_opts.isa != ISA_MIPS1 \
522 || mips_opts.micromips \
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
530 has been selected. This implies, in particular, that addresses of text
531 labels have their LSB set. */
532 #define HAVE_CODE_COMPRESSION \
533 ((mips_opts.mips16 | mips_opts.micromips) != 0)
535 /* The minimum and maximum signed values that can be stored in a GPR. */
536 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
537 #define GPR_SMIN (-GPR_SMAX - 1)
539 /* MIPS PIC level. */
541 enum mips_pic_level mips_pic
;
543 /* 1 if we should generate 32 bit offsets from the $gp register in
544 SVR4_PIC mode. Currently has no meaning in other modes. */
545 static int mips_big_got
= 0;
547 /* 1 if trap instructions should used for overflow rather than break
549 static int mips_trap
= 0;
551 /* 1 if double width floating point constants should not be constructed
552 by assembling two single width halves into two single width floating
553 point registers which just happen to alias the double width destination
554 register. On some architectures this aliasing can be disabled by a bit
555 in the status register, and the setting of this bit cannot be determined
556 automatically at assemble time. */
557 static int mips_disable_float_construction
;
559 /* Non-zero if any .set noreorder directives were used. */
561 static int mips_any_noreorder
;
563 /* Non-zero if nops should be inserted when the register referenced in
564 an mfhi/mflo instruction is read in the next two instructions. */
565 static int mips_7000_hilo_fix
;
567 /* The size of objects in the small data section. */
568 static unsigned int g_switch_value
= 8;
569 /* Whether the -G option was used. */
570 static int g_switch_seen
= 0;
575 /* If we can determine in advance that GP optimization won't be
576 possible, we can skip the relaxation stuff that tries to produce
577 GP-relative references. This makes delay slot optimization work
580 This function can only provide a guess, but it seems to work for
581 gcc output. It needs to guess right for gcc, otherwise gcc
582 will put what it thinks is a GP-relative instruction in a branch
585 I don't know if a fix is needed for the SVR4_PIC mode. I've only
586 fixed it for the non-PIC mode. KR 95/04/07 */
587 static int nopic_need_relax (symbolS
*, int);
589 /* handle of the OPCODE hash table */
590 static struct hash_control
*op_hash
= NULL
;
592 /* The opcode hash table we use for the mips16. */
593 static struct hash_control
*mips16_op_hash
= NULL
;
595 /* The opcode hash table we use for the microMIPS ASE. */
596 static struct hash_control
*micromips_op_hash
= NULL
;
598 /* This array holds the chars that always start a comment. If the
599 pre-processor is disabled, these aren't very useful */
600 const char comment_chars
[] = "#";
602 /* This array holds the chars that only start a comment at the beginning of
603 a line. If the line seems to have the form '# 123 filename'
604 .line and .file directives will appear in the pre-processed output */
605 /* Note that input_file.c hand checks for '#' at the beginning of the
606 first line of the input file. This is because the compiler outputs
607 #NO_APP at the beginning of its output. */
608 /* Also note that C style comments are always supported. */
609 const char line_comment_chars
[] = "#";
611 /* This array holds machine specific line separator characters. */
612 const char line_separator_chars
[] = ";";
614 /* Chars that can be used to separate mant from exp in floating point nums */
615 const char EXP_CHARS
[] = "eE";
617 /* Chars that mean this number is a floating point constant */
620 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
622 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
623 changed in read.c . Ideally it shouldn't have to know about it at all,
624 but nothing is ideal around here.
627 static char *insn_error
;
629 static int auto_align
= 1;
631 /* When outputting SVR4 PIC code, the assembler needs to know the
632 offset in the stack frame from which to restore the $gp register.
633 This is set by the .cprestore pseudo-op, and saved in this
635 static offsetT mips_cprestore_offset
= -1;
637 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
638 more optimizations, it can use a register value instead of a memory-saved
639 offset and even an other register than $gp as global pointer. */
640 static offsetT mips_cpreturn_offset
= -1;
641 static int mips_cpreturn_register
= -1;
642 static int mips_gp_register
= GP
;
643 static int mips_gprel_offset
= 0;
645 /* Whether mips_cprestore_offset has been set in the current function
646 (or whether it has already been warned about, if not). */
647 static int mips_cprestore_valid
= 0;
649 /* This is the register which holds the stack frame, as set by the
650 .frame pseudo-op. This is needed to implement .cprestore. */
651 static int mips_frame_reg
= SP
;
653 /* Whether mips_frame_reg has been set in the current function
654 (or whether it has already been warned about, if not). */
655 static int mips_frame_reg_valid
= 0;
657 /* To output NOP instructions correctly, we need to keep information
658 about the previous two instructions. */
660 /* Whether we are optimizing. The default value of 2 means to remove
661 unneeded NOPs and swap branch instructions when possible. A value
662 of 1 means to not swap branches. A value of 0 means to always
664 static int mips_optimize
= 2;
666 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
667 equivalent to seeing no -g option at all. */
668 static int mips_debug
= 0;
670 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
671 #define MAX_VR4130_NOPS 4
673 /* The maximum number of NOPs needed to fill delay slots. */
674 #define MAX_DELAY_NOPS 2
676 /* The maximum number of NOPs needed for any purpose. */
679 /* A list of previous instructions, with index 0 being the most recent.
680 We need to look back MAX_NOPS instructions when filling delay slots
681 or working around processor errata. We need to look back one
682 instruction further if we're thinking about using history[0] to
683 fill a branch delay slot. */
684 static struct mips_cl_insn history
[1 + MAX_NOPS
];
686 /* Nop instructions used by emit_nop. */
687 static struct mips_cl_insn nop_insn
;
688 static struct mips_cl_insn mips16_nop_insn
;
689 static struct mips_cl_insn micromips_nop16_insn
;
690 static struct mips_cl_insn micromips_nop32_insn
;
692 /* The appropriate nop for the current mode. */
693 #define NOP_INSN (mips_opts.mips16 \
695 : (mips_opts.micromips \
696 ? (mips_opts.insn32 \
697 ? µmips_nop32_insn \
698 : µmips_nop16_insn) \
701 /* The size of NOP_INSN in bytes. */
702 #define NOP_INSN_SIZE ((mips_opts.mips16 \
703 || (mips_opts.micromips && !mips_opts.insn32)) \
706 /* If this is set, it points to a frag holding nop instructions which
707 were inserted before the start of a noreorder section. If those
708 nops turn out to be unnecessary, the size of the frag can be
710 static fragS
*prev_nop_frag
;
712 /* The number of nop instructions we created in prev_nop_frag. */
713 static int prev_nop_frag_holds
;
715 /* The number of nop instructions that we know we need in
717 static int prev_nop_frag_required
;
719 /* The number of instructions we've seen since prev_nop_frag. */
720 static int prev_nop_frag_since
;
722 /* Relocations against symbols are sometimes done in two parts, with a HI
723 relocation and a LO relocation. Each relocation has only 16 bits of
724 space to store an addend. This means that in order for the linker to
725 handle carries correctly, it must be able to locate both the HI and
726 the LO relocation. This means that the relocations must appear in
727 order in the relocation table.
729 In order to implement this, we keep track of each unmatched HI
730 relocation. We then sort them so that they immediately precede the
731 corresponding LO relocation. */
736 struct mips_hi_fixup
*next
;
739 /* The section this fixup is in. */
743 /* The list of unmatched HI relocs. */
745 static struct mips_hi_fixup
*mips_hi_fixup_list
;
747 /* The frag containing the last explicit relocation operator.
748 Null if explicit relocations have not been used. */
750 static fragS
*prev_reloc_op_frag
;
752 /* Map normal MIPS register numbers to mips16 register numbers. */
754 #define X ILLEGAL_REG
755 static const int mips32_to_16_reg_map
[] =
757 X
, X
, 2, 3, 4, 5, 6, 7,
758 X
, X
, X
, X
, X
, X
, X
, X
,
759 0, 1, X
, X
, X
, X
, X
, X
,
760 X
, X
, X
, X
, X
, X
, X
, X
764 /* Map mips16 register numbers to normal MIPS register numbers. */
766 static const unsigned int mips16_to_32_reg_map
[] =
768 16, 17, 2, 3, 4, 5, 6, 7
771 /* Map normal MIPS register numbers to microMIPS register numbers. */
773 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
774 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
775 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
776 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
781 #define X ILLEGAL_REG
782 /* reg type h: 4, 5, 6. */
783 static const int mips32_to_micromips_reg_h_map
[] =
785 X
, X
, X
, X
, 4, 5, 6, X
,
786 X
, X
, X
, X
, X
, X
, X
, X
,
787 X
, X
, X
, X
, X
, X
, X
, X
,
788 X
, X
, X
, X
, X
, X
, X
, X
791 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
792 static const int mips32_to_micromips_reg_m_map
[] =
794 0, X
, 2, 3, X
, X
, X
, X
,
795 X
, X
, X
, X
, X
, X
, X
, X
,
796 4, 1, 5, 6, 7, X
, X
, X
,
797 X
, X
, X
, X
, X
, X
, X
, X
800 /* reg type q: 0, 2-7. 17. */
801 static const int mips32_to_micromips_reg_q_map
[] =
803 0, X
, 2, 3, 4, 5, 6, 7,
804 X
, X
, X
, X
, X
, X
, X
, X
,
805 X
, 1, X
, X
, X
, X
, X
, X
,
806 X
, X
, X
, X
, X
, X
, X
, X
809 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
812 /* Map microMIPS register numbers to normal MIPS register numbers. */
814 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
815 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
816 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
817 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
818 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
819 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
821 /* The microMIPS registers with type h. */
822 static const unsigned int micromips_to_32_reg_h_map
[] =
824 5, 5, 6, 4, 4, 4, 4, 4
827 /* The microMIPS registers with type i. */
828 static const unsigned int micromips_to_32_reg_i_map
[] =
830 6, 7, 7, 21, 22, 5, 6, 7
833 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
835 /* The microMIPS registers with type m. */
836 static const unsigned int micromips_to_32_reg_m_map
[] =
838 0, 17, 2, 3, 16, 18, 19, 20
841 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
843 /* The microMIPS registers with type q. */
844 static const unsigned int micromips_to_32_reg_q_map
[] =
846 0, 17, 2, 3, 4, 5, 6, 7
849 /* microMIPS imm type B. */
850 static const int micromips_imm_b_map
[] =
852 1, 4, 8, 12, 16, 20, 24, -1
855 /* microMIPS imm type C. */
856 static const int micromips_imm_c_map
[] =
858 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
861 /* Classifies the kind of instructions we're interested in when
862 implementing -mfix-vr4120. */
863 enum fix_vr4120_class
871 NUM_FIX_VR4120_CLASSES
874 /* ...likewise -mfix-loongson2f-jump. */
875 static bfd_boolean mips_fix_loongson2f_jump
;
877 /* ...likewise -mfix-loongson2f-nop. */
878 static bfd_boolean mips_fix_loongson2f_nop
;
880 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
881 static bfd_boolean mips_fix_loongson2f
;
883 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
884 there must be at least one other instruction between an instruction
885 of type X and an instruction of type Y. */
886 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
888 /* True if -mfix-vr4120 is in force. */
889 static int mips_fix_vr4120
;
891 /* ...likewise -mfix-vr4130. */
892 static int mips_fix_vr4130
;
894 /* ...likewise -mfix-24k. */
895 static int mips_fix_24k
;
897 /* ...likewise -mfix-cn63xxp1 */
898 static bfd_boolean mips_fix_cn63xxp1
;
900 /* We don't relax branches by default, since this causes us to expand
901 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
902 fail to compute the offset before expanding the macro to the most
903 efficient expansion. */
905 static int mips_relax_branch
;
907 /* The expansion of many macros depends on the type of symbol that
908 they refer to. For example, when generating position-dependent code,
909 a macro that refers to a symbol may have two different expansions,
910 one which uses GP-relative addresses and one which uses absolute
911 addresses. When generating SVR4-style PIC, a macro may have
912 different expansions for local and global symbols.
914 We handle these situations by generating both sequences and putting
915 them in variant frags. In position-dependent code, the first sequence
916 will be the GP-relative one and the second sequence will be the
917 absolute one. In SVR4 PIC, the first sequence will be for global
918 symbols and the second will be for local symbols.
920 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
921 SECOND are the lengths of the two sequences in bytes. These fields
922 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
923 the subtype has the following flags:
926 Set if it has been decided that we should use the second
927 sequence instead of the first.
930 Set in the first variant frag if the macro's second implementation
931 is longer than its first. This refers to the macro as a whole,
932 not an individual relaxation.
935 Set in the first variant frag if the macro appeared in a .set nomacro
936 block and if one alternative requires a warning but the other does not.
939 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
942 RELAX_DELAY_SLOT_16BIT
943 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
946 RELAX_DELAY_SLOT_SIZE_FIRST
947 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
948 the macro is of the wrong size for the branch delay slot.
950 RELAX_DELAY_SLOT_SIZE_SECOND
951 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
952 the macro is of the wrong size for the branch delay slot.
954 The frag's "opcode" points to the first fixup for relaxable code.
956 Relaxable macros are generated using a sequence such as:
958 relax_start (SYMBOL);
959 ... generate first expansion ...
961 ... generate second expansion ...
964 The code and fixups for the unwanted alternative are discarded
965 by md_convert_frag. */
966 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
968 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
969 #define RELAX_SECOND(X) ((X) & 0xff)
970 #define RELAX_USE_SECOND 0x10000
971 #define RELAX_SECOND_LONGER 0x20000
972 #define RELAX_NOMACRO 0x40000
973 #define RELAX_DELAY_SLOT 0x80000
974 #define RELAX_DELAY_SLOT_16BIT 0x100000
975 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
976 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
978 /* Branch without likely bit. If label is out of range, we turn:
980 beq reg1, reg2, label
990 with the following opcode replacements:
997 bltzal <-> bgezal (with jal label instead of j label)
999 Even though keeping the delay slot instruction in the delay slot of
1000 the branch would be more efficient, it would be very tricky to do
1001 correctly, because we'd have to introduce a variable frag *after*
1002 the delay slot instruction, and expand that instead. Let's do it
1003 the easy way for now, even if the branch-not-taken case now costs
1004 one additional instruction. Out-of-range branches are not supposed
1005 to be common, anyway.
1007 Branch likely. If label is out of range, we turn:
1009 beql reg1, reg2, label
1010 delay slot (annulled if branch not taken)
1019 delay slot (executed only if branch taken)
1022 It would be possible to generate a shorter sequence by losing the
1023 likely bit, generating something like:
1028 delay slot (executed only if branch taken)
1040 bltzall -> bgezal (with jal label instead of j label)
1041 bgezall -> bltzal (ditto)
1044 but it's not clear that it would actually improve performance. */
1045 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1046 ((relax_substateT) \
1049 | ((toofar) ? 0x20 : 0) \
1050 | ((link) ? 0x40 : 0) \
1051 | ((likely) ? 0x80 : 0) \
1052 | ((uncond) ? 0x100 : 0)))
1053 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1054 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1055 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1056 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1057 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1058 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1060 /* For mips16 code, we use an entirely different form of relaxation.
1061 mips16 supports two versions of most instructions which take
1062 immediate values: a small one which takes some small value, and a
1063 larger one which takes a 16 bit value. Since branches also follow
1064 this pattern, relaxing these values is required.
1066 We can assemble both mips16 and normal MIPS code in a single
1067 object. Therefore, we need to support this type of relaxation at
1068 the same time that we support the relaxation described above. We
1069 use the high bit of the subtype field to distinguish these cases.
1071 The information we store for this type of relaxation is the
1072 argument code found in the opcode file for this relocation, whether
1073 the user explicitly requested a small or extended form, and whether
1074 the relocation is in a jump or jal delay slot. That tells us the
1075 size of the value, and how it should be stored. We also store
1076 whether the fragment is considered to be extended or not. We also
1077 store whether this is known to be a branch to a different section,
1078 whether we have tried to relax this frag yet, and whether we have
1079 ever extended a PC relative fragment because of a shift count. */
1080 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1083 | ((small) ? 0x100 : 0) \
1084 | ((ext) ? 0x200 : 0) \
1085 | ((dslot) ? 0x400 : 0) \
1086 | ((jal_dslot) ? 0x800 : 0))
1087 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1088 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1089 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1090 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1091 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1092 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1093 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1094 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1095 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1096 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1097 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1098 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1100 /* For microMIPS code, we use relaxation similar to one we use for
1101 MIPS16 code. Some instructions that take immediate values support
1102 two encodings: a small one which takes some small value, and a
1103 larger one which takes a 16 bit value. As some branches also follow
1104 this pattern, relaxing these values is required.
1106 We can assemble both microMIPS and normal MIPS code in a single
1107 object. Therefore, we need to support this type of relaxation at
1108 the same time that we support the relaxation described above. We
1109 use one of the high bits of the subtype field to distinguish these
1112 The information we store for this type of relaxation is the argument
1113 code found in the opcode file for this relocation, the register
1114 selected as the assembler temporary, whether the branch is
1115 unconditional, whether it is compact, whether it stores the link
1116 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1117 branches to a sequence of instructions is enabled, and whether the
1118 displacement of a branch is too large to fit as an immediate argument
1119 of a 16-bit and a 32-bit branch, respectively. */
1120 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1121 relax32, toofar16, toofar32) \
1124 | (((at) & 0x1f) << 8) \
1125 | ((uncond) ? 0x2000 : 0) \
1126 | ((compact) ? 0x4000 : 0) \
1127 | ((link) ? 0x8000 : 0) \
1128 | ((relax32) ? 0x10000 : 0) \
1129 | ((toofar16) ? 0x20000 : 0) \
1130 | ((toofar32) ? 0x40000 : 0))
1131 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1132 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1133 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1134 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1135 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1136 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1137 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1139 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1140 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1141 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1142 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1143 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1144 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1146 /* Sign-extend 16-bit value X. */
1147 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1149 /* Is the given value a sign-extended 32-bit value? */
1150 #define IS_SEXT_32BIT_NUM(x) \
1151 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1152 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1154 /* Is the given value a sign-extended 16-bit value? */
1155 #define IS_SEXT_16BIT_NUM(x) \
1156 (((x) &~ (offsetT) 0x7fff) == 0 \
1157 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1159 /* Is the given value a sign-extended 12-bit value? */
1160 #define IS_SEXT_12BIT_NUM(x) \
1161 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1163 /* Is the given value a sign-extended 9-bit value? */
1164 #define IS_SEXT_9BIT_NUM(x) \
1165 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1167 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1168 #define IS_ZEXT_32BIT_NUM(x) \
1169 (((x) &~ (offsetT) 0xffffffff) == 0 \
1170 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1172 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1173 VALUE << SHIFT. VALUE is evaluated exactly once. */
1174 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1175 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1176 | (((VALUE) & (MASK)) << (SHIFT)))
1178 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1180 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1181 (((STRUCT) >> (SHIFT)) & (MASK))
1183 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1184 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1186 include/opcode/mips.h specifies operand fields using the macros
1187 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1188 with "MIPS16OP" instead of "OP". */
1189 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1192 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1193 OP_MASK_##FIELD, OP_SH_##FIELD); \
1195 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1196 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1198 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1199 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1200 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1202 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1203 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1205 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1206 : EXTRACT_BITS ((INSN).insn_opcode, \
1207 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1208 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1209 EXTRACT_BITS ((INSN).insn_opcode, \
1210 MIPS16OP_MASK_##FIELD, \
1211 MIPS16OP_SH_##FIELD)
1213 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1214 #define MIPS16_EXTEND (0xf000U << 16)
1216 /* Whether or not we are emitting a branch-likely macro. */
1217 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1219 /* Global variables used when generating relaxable macros. See the
1220 comment above RELAX_ENCODE for more details about how relaxation
1223 /* 0 if we're not emitting a relaxable macro.
1224 1 if we're emitting the first of the two relaxation alternatives.
1225 2 if we're emitting the second alternative. */
1228 /* The first relaxable fixup in the current frag. (In other words,
1229 the first fixup that refers to relaxable code.) */
1232 /* sizes[0] says how many bytes of the first alternative are stored in
1233 the current frag. Likewise sizes[1] for the second alternative. */
1234 unsigned int sizes
[2];
1236 /* The symbol on which the choice of sequence depends. */
1240 /* Global variables used to decide whether a macro needs a warning. */
1242 /* True if the macro is in a branch delay slot. */
1243 bfd_boolean delay_slot_p
;
1245 /* Set to the length in bytes required if the macro is in a delay slot
1246 that requires a specific length of instruction, otherwise zero. */
1247 unsigned int delay_slot_length
;
1249 /* For relaxable macros, sizes[0] is the length of the first alternative
1250 in bytes and sizes[1] is the length of the second alternative.
1251 For non-relaxable macros, both elements give the length of the
1253 unsigned int sizes
[2];
1255 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1256 instruction of the first alternative in bytes and first_insn_sizes[1]
1257 is the length of the first instruction of the second alternative.
1258 For non-relaxable macros, both elements give the length of the first
1259 instruction in bytes.
1261 Set to zero if we haven't yet seen the first instruction. */
1262 unsigned int first_insn_sizes
[2];
1264 /* For relaxable macros, insns[0] is the number of instructions for the
1265 first alternative and insns[1] is the number of instructions for the
1268 For non-relaxable macros, both elements give the number of
1269 instructions for the macro. */
1270 unsigned int insns
[2];
1272 /* The first variant frag for this macro. */
1274 } mips_macro_warning
;
1276 /* Prototypes for static functions. */
1278 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1280 static void append_insn
1281 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1282 bfd_boolean expansionp
);
1283 static void mips_no_prev_insn (void);
1284 static void macro_build (expressionS
*, const char *, const char *, ...);
1285 static void mips16_macro_build
1286 (expressionS
*, const char *, const char *, va_list *);
1287 static void load_register (int, expressionS
*, int);
1288 static void macro_start (void);
1289 static void macro_end (void);
1290 static void macro (struct mips_cl_insn
*ip
, char *str
);
1291 static void mips16_macro (struct mips_cl_insn
* ip
);
1292 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1293 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1294 static void mips16_immed
1295 (char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1296 unsigned int, unsigned long *);
1297 static size_t my_getSmallExpression
1298 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1299 static void my_getExpression (expressionS
*, char *);
1300 static void s_align (int);
1301 static void s_change_sec (int);
1302 static void s_change_section (int);
1303 static void s_cons (int);
1304 static void s_float_cons (int);
1305 static void s_mips_globl (int);
1306 static void s_option (int);
1307 static void s_mipsset (int);
1308 static void s_abicalls (int);
1309 static void s_cpload (int);
1310 static void s_cpsetup (int);
1311 static void s_cplocal (int);
1312 static void s_cprestore (int);
1313 static void s_cpreturn (int);
1314 static void s_dtprelword (int);
1315 static void s_dtpreldword (int);
1316 static void s_tprelword (int);
1317 static void s_tpreldword (int);
1318 static void s_gpvalue (int);
1319 static void s_gpword (int);
1320 static void s_gpdword (int);
1321 static void s_ehword (int);
1322 static void s_cpadd (int);
1323 static void s_insn (int);
1324 static void md_obj_begin (void);
1325 static void md_obj_end (void);
1326 static void s_mips_ent (int);
1327 static void s_mips_end (int);
1328 static void s_mips_frame (int);
1329 static void s_mips_mask (int reg_type
);
1330 static void s_mips_stab (int);
1331 static void s_mips_weakext (int);
1332 static void s_mips_file (int);
1333 static void s_mips_loc (int);
1334 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1335 static int relaxed_branch_length (fragS
*, asection
*, int);
1336 static int validate_mips_insn (const struct mips_opcode
*);
1337 static int validate_micromips_insn (const struct mips_opcode
*);
1338 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1339 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1341 /* Table and functions used to map between CPU/ISA names, and
1342 ISA levels, and CPU numbers. */
1344 struct mips_cpu_info
1346 const char *name
; /* CPU or ISA name. */
1347 int flags
; /* MIPS_CPU_* flags. */
1348 int ase
; /* Set of ASEs implemented by the CPU. */
1349 int isa
; /* ISA level. */
1350 int cpu
; /* CPU number (default CPU if ISA). */
1353 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1355 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1356 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1357 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1359 /* Command-line options. */
1360 const char *md_shortopts
= "O::g::G:";
1364 OPTION_MARCH
= OPTION_MD_BASE
,
1388 OPTION_NO_SMARTMIPS
,
1394 OPTION_NO_MICROMIPS
,
1397 OPTION_COMPAT_ARCH_BASE
,
1406 OPTION_M7000_HILO_FIX
,
1407 OPTION_MNO_7000_HILO_FIX
,
1410 OPTION_FIX_LOONGSON2F_JUMP
,
1411 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1412 OPTION_FIX_LOONGSON2F_NOP
,
1413 OPTION_NO_FIX_LOONGSON2F_NOP
,
1415 OPTION_NO_FIX_VR4120
,
1417 OPTION_NO_FIX_VR4130
,
1418 OPTION_FIX_CN63XXP1
,
1419 OPTION_NO_FIX_CN63XXP1
,
1426 OPTION_CONSTRUCT_FLOATS
,
1427 OPTION_NO_CONSTRUCT_FLOATS
,
1430 OPTION_RELAX_BRANCH
,
1431 OPTION_NO_RELAX_BRANCH
,
1440 OPTION_SINGLE_FLOAT
,
1441 OPTION_DOUBLE_FLOAT
,
1454 OPTION_MVXWORKS_PIC
,
1458 struct option md_longopts
[] =
1460 /* Options which specify architecture. */
1461 {"march", required_argument
, NULL
, OPTION_MARCH
},
1462 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1463 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1464 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1465 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1466 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1467 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1468 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1469 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1470 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1471 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1472 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1474 /* Options which specify Application Specific Extensions (ASEs). */
1475 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1476 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1477 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1478 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1479 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1480 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1481 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1482 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1483 {"mmt", no_argument
, NULL
, OPTION_MT
},
1484 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1485 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1486 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1487 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1488 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1489 {"meva", no_argument
, NULL
, OPTION_EVA
},
1490 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1491 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1492 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1493 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1494 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1495 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1496 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1498 /* Old-style architecture options. Don't add more of these. */
1499 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1500 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1501 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1502 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1503 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1504 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1505 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1506 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1508 /* Options which enable bug fixes. */
1509 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1510 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1511 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1512 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1513 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1514 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1515 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1516 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1517 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1518 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1519 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1520 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1521 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1522 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1523 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1525 /* Miscellaneous options. */
1526 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1527 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1528 {"break", no_argument
, NULL
, OPTION_BREAK
},
1529 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1530 {"EB", no_argument
, NULL
, OPTION_EB
},
1531 {"EL", no_argument
, NULL
, OPTION_EL
},
1532 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1533 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1534 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1535 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1536 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1537 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1538 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1539 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1540 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1541 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1542 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1543 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1544 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1545 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1546 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1547 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1548 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1549 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1551 /* Strictly speaking this next option is ELF specific,
1552 but we allow it for other ports as well in order to
1553 make testing easier. */
1554 {"32", no_argument
, NULL
, OPTION_32
},
1556 /* ELF-specific options. */
1557 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1558 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1559 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1560 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1561 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1562 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1563 {"n32", no_argument
, NULL
, OPTION_N32
},
1564 {"64", no_argument
, NULL
, OPTION_64
},
1565 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1566 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1567 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1568 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1569 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1571 {NULL
, no_argument
, NULL
, 0}
1573 size_t md_longopts_size
= sizeof (md_longopts
);
1575 /* Information about either an Application Specific Extension or an
1576 optional architecture feature that, for simplicity, we treat in the
1577 same way as an ASE. */
1580 /* The name of the ASE, used in both the command-line and .set options. */
1583 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1584 and 64-bit architectures, the flags here refer to the subset that
1585 is available on both. */
1588 /* The ASE_* flag used for instructions that are available on 64-bit
1589 architectures but that are not included in FLAGS. */
1590 unsigned int flags64
;
1592 /* The command-line options that turn the ASE on and off. */
1596 /* The minimum required architecture revisions for MIPS32, MIPS64,
1597 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1600 int micromips32_rev
;
1601 int micromips64_rev
;
1604 /* A table of all supported ASEs. */
1605 static const struct mips_ase mips_ases
[] = {
1606 { "dsp", ASE_DSP
, ASE_DSP64
,
1607 OPTION_DSP
, OPTION_NO_DSP
,
1610 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1611 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1614 { "eva", ASE_EVA
, 0,
1615 OPTION_EVA
, OPTION_NO_EVA
,
1618 { "mcu", ASE_MCU
, 0,
1619 OPTION_MCU
, OPTION_NO_MCU
,
1622 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1623 { "mdmx", ASE_MDMX
, 0,
1624 OPTION_MDMX
, OPTION_NO_MDMX
,
1627 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1628 { "mips3d", ASE_MIPS3D
, 0,
1629 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1633 OPTION_MT
, OPTION_NO_MT
,
1636 { "smartmips", ASE_SMARTMIPS
, 0,
1637 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1640 { "virt", ASE_VIRT
, ASE_VIRT64
,
1641 OPTION_VIRT
, OPTION_NO_VIRT
,
1645 /* The set of ASEs that require -mfp64. */
1646 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1648 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1649 static const unsigned int mips_ase_groups
[] = {
1655 The following pseudo-ops from the Kane and Heinrich MIPS book
1656 should be defined here, but are currently unsupported: .alias,
1657 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1659 The following pseudo-ops from the Kane and Heinrich MIPS book are
1660 specific to the type of debugging information being generated, and
1661 should be defined by the object format: .aent, .begin, .bend,
1662 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1665 The following pseudo-ops from the Kane and Heinrich MIPS book are
1666 not MIPS CPU specific, but are also not specific to the object file
1667 format. This file is probably the best place to define them, but
1668 they are not currently supported: .asm0, .endr, .lab, .struct. */
1670 static const pseudo_typeS mips_pseudo_table
[] =
1672 /* MIPS specific pseudo-ops. */
1673 {"option", s_option
, 0},
1674 {"set", s_mipsset
, 0},
1675 {"rdata", s_change_sec
, 'r'},
1676 {"sdata", s_change_sec
, 's'},
1677 {"livereg", s_ignore
, 0},
1678 {"abicalls", s_abicalls
, 0},
1679 {"cpload", s_cpload
, 0},
1680 {"cpsetup", s_cpsetup
, 0},
1681 {"cplocal", s_cplocal
, 0},
1682 {"cprestore", s_cprestore
, 0},
1683 {"cpreturn", s_cpreturn
, 0},
1684 {"dtprelword", s_dtprelword
, 0},
1685 {"dtpreldword", s_dtpreldword
, 0},
1686 {"tprelword", s_tprelword
, 0},
1687 {"tpreldword", s_tpreldword
, 0},
1688 {"gpvalue", s_gpvalue
, 0},
1689 {"gpword", s_gpword
, 0},
1690 {"gpdword", s_gpdword
, 0},
1691 {"ehword", s_ehword
, 0},
1692 {"cpadd", s_cpadd
, 0},
1693 {"insn", s_insn
, 0},
1695 /* Relatively generic pseudo-ops that happen to be used on MIPS
1697 {"asciiz", stringer
, 8 + 1},
1698 {"bss", s_change_sec
, 'b'},
1700 {"half", s_cons
, 1},
1701 {"dword", s_cons
, 3},
1702 {"weakext", s_mips_weakext
, 0},
1703 {"origin", s_org
, 0},
1704 {"repeat", s_rept
, 0},
1706 /* For MIPS this is non-standard, but we define it for consistency. */
1707 {"sbss", s_change_sec
, 'B'},
1709 /* These pseudo-ops are defined in read.c, but must be overridden
1710 here for one reason or another. */
1711 {"align", s_align
, 0},
1712 {"byte", s_cons
, 0},
1713 {"data", s_change_sec
, 'd'},
1714 {"double", s_float_cons
, 'd'},
1715 {"float", s_float_cons
, 'f'},
1716 {"globl", s_mips_globl
, 0},
1717 {"global", s_mips_globl
, 0},
1718 {"hword", s_cons
, 1},
1720 {"long", s_cons
, 2},
1721 {"octa", s_cons
, 4},
1722 {"quad", s_cons
, 3},
1723 {"section", s_change_section
, 0},
1724 {"short", s_cons
, 1},
1725 {"single", s_float_cons
, 'f'},
1726 {"stabd", s_mips_stab
, 'd'},
1727 {"stabn", s_mips_stab
, 'n'},
1728 {"stabs", s_mips_stab
, 's'},
1729 {"text", s_change_sec
, 't'},
1730 {"word", s_cons
, 2},
1732 { "extern", ecoff_directive_extern
, 0},
1737 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1739 /* These pseudo-ops should be defined by the object file format.
1740 However, a.out doesn't support them, so we have versions here. */
1741 {"aent", s_mips_ent
, 1},
1742 {"bgnb", s_ignore
, 0},
1743 {"end", s_mips_end
, 0},
1744 {"endb", s_ignore
, 0},
1745 {"ent", s_mips_ent
, 0},
1746 {"file", s_mips_file
, 0},
1747 {"fmask", s_mips_mask
, 'F'},
1748 {"frame", s_mips_frame
, 0},
1749 {"loc", s_mips_loc
, 0},
1750 {"mask", s_mips_mask
, 'R'},
1751 {"verstamp", s_ignore
, 0},
1755 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1756 purpose of the `.dc.a' internal pseudo-op. */
1759 mips_address_bytes (void)
1761 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1764 extern void pop_insert (const pseudo_typeS
*);
1767 mips_pop_insert (void)
1769 pop_insert (mips_pseudo_table
);
1770 if (! ECOFF_DEBUGGING
)
1771 pop_insert (mips_nonecoff_pseudo_table
);
1774 /* Symbols labelling the current insn. */
1776 struct insn_label_list
1778 struct insn_label_list
*next
;
1782 static struct insn_label_list
*free_insn_labels
;
1783 #define label_list tc_segment_info_data.labels
1785 static void mips_clear_insn_labels (void);
1786 static void mips_mark_labels (void);
1787 static void mips_compressed_mark_labels (void);
1790 mips_clear_insn_labels (void)
1792 register struct insn_label_list
**pl
;
1793 segment_info_type
*si
;
1797 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1800 si
= seg_info (now_seg
);
1801 *pl
= si
->label_list
;
1802 si
->label_list
= NULL
;
1806 /* Mark instruction labels in MIPS16/microMIPS mode. */
1809 mips_mark_labels (void)
1811 if (HAVE_CODE_COMPRESSION
)
1812 mips_compressed_mark_labels ();
1815 static char *expr_end
;
1817 /* Expressions which appear in instructions. These are set by
1820 static expressionS imm_expr
;
1821 static expressionS imm2_expr
;
1822 static expressionS offset_expr
;
1824 /* Relocs associated with imm_expr and offset_expr. */
1826 static bfd_reloc_code_real_type imm_reloc
[3]
1827 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1828 static bfd_reloc_code_real_type offset_reloc
[3]
1829 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1831 /* This is set to the resulting size of the instruction to be produced
1832 by mips16_ip if an explicit extension is used or by mips_ip if an
1833 explicit size is supplied. */
1835 static unsigned int forced_insn_length
;
1837 /* True if we are assembling an instruction. All dot symbols defined during
1838 this time should be treated as code labels. */
1840 static bfd_boolean mips_assembling_insn
;
1842 /* The pdr segment for per procedure frame/regmask info. Not used for
1845 static segT pdr_seg
;
1847 /* The default target format to use. */
1849 #if defined (TE_FreeBSD)
1850 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1851 #elif defined (TE_TMIPS)
1852 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1854 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1858 mips_target_format (void)
1860 switch (OUTPUT_FLAVOR
)
1862 case bfd_target_elf_flavour
:
1864 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1865 return (target_big_endian
1866 ? "elf32-bigmips-vxworks"
1867 : "elf32-littlemips-vxworks");
1869 return (target_big_endian
1870 ? (HAVE_64BIT_OBJECTS
1871 ? ELF_TARGET ("elf64-", "big")
1873 ? ELF_TARGET ("elf32-n", "big")
1874 : ELF_TARGET ("elf32-", "big")))
1875 : (HAVE_64BIT_OBJECTS
1876 ? ELF_TARGET ("elf64-", "little")
1878 ? ELF_TARGET ("elf32-n", "little")
1879 : ELF_TARGET ("elf32-", "little"))));
1886 /* Return the ISA revision that is currently in use, or 0 if we are
1887 generating code for MIPS V or below. */
1892 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
1895 /* microMIPS implies revision 2 or above. */
1896 if (mips_opts
.micromips
)
1899 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
1905 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1908 mips_ase_mask (unsigned int flags
)
1912 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
1913 if (flags
& mips_ase_groups
[i
])
1914 flags
|= mips_ase_groups
[i
];
1918 /* Check whether the current ISA supports ASE. Issue a warning if
1922 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
1926 static unsigned int warned_isa
;
1927 static unsigned int warned_fp32
;
1929 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1930 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
1932 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
1933 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
1934 && (warned_isa
& ase
->flags
) != ase
->flags
)
1936 warned_isa
|= ase
->flags
;
1937 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
1938 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
1940 as_warn (_("The %d-bit %s architecture does not support the"
1941 " `%s' extension"), size
, base
, ase
->name
);
1943 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1944 ase
->name
, base
, size
, min_rev
);
1946 if ((ase
->flags
& FP64_ASES
)
1948 && (warned_fp32
& ase
->flags
) != ase
->flags
)
1950 warned_fp32
|= ase
->flags
;
1951 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase
->name
);
1955 /* Check all enabled ASEs to see whether they are supported by the
1956 chosen architecture. */
1959 mips_check_isa_supports_ases (void)
1961 unsigned int i
, mask
;
1963 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1965 mask
= mips_ase_mask (mips_ases
[i
].flags
);
1966 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
1967 mips_check_isa_supports_ase (&mips_ases
[i
]);
1971 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1972 that were affected. */
1975 mips_set_ase (const struct mips_ase
*ase
, bfd_boolean enabled_p
)
1979 mask
= mips_ase_mask (ase
->flags
);
1980 mips_opts
.ase
&= ~mask
;
1982 mips_opts
.ase
|= ase
->flags
;
1986 /* Return the ASE called NAME, or null if none. */
1988 static const struct mips_ase
*
1989 mips_lookup_ase (const char *name
)
1993 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
1994 if (strcmp (name
, mips_ases
[i
].name
) == 0)
1995 return &mips_ases
[i
];
1999 /* Return the length of a microMIPS instruction in bytes. If bits of
2000 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
2001 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
2002 major opcode) will require further modifications to the opcode
2005 static inline unsigned int
2006 micromips_insn_length (const struct mips_opcode
*mo
)
2008 return (mo
->mask
>> 16) == 0 ? 2 : 4;
2011 /* Return the length of MIPS16 instruction OPCODE. */
2013 static inline unsigned int
2014 mips16_opcode_length (unsigned long opcode
)
2016 return (opcode
>> 16) == 0 ? 2 : 4;
2019 /* Return the length of instruction INSN. */
2021 static inline unsigned int
2022 insn_length (const struct mips_cl_insn
*insn
)
2024 if (mips_opts
.micromips
)
2025 return micromips_insn_length (insn
->insn_mo
);
2026 else if (mips_opts
.mips16
)
2027 return mips16_opcode_length (insn
->insn_opcode
);
2032 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2035 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2040 insn
->insn_opcode
= mo
->match
;
2043 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2044 insn
->fixp
[i
] = NULL
;
2045 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2046 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2047 insn
->mips16_absolute_jump_p
= 0;
2048 insn
->complete_p
= 0;
2049 insn
->cleared_p
= 0;
2052 /* Record the current MIPS16/microMIPS mode in now_seg. */
2055 mips_record_compressed_mode (void)
2057 segment_info_type
*si
;
2059 si
= seg_info (now_seg
);
2060 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2061 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2062 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2063 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2066 /* Read a standard MIPS instruction from BUF. */
2068 static unsigned long
2069 read_insn (char *buf
)
2071 if (target_big_endian
)
2072 return bfd_getb32 ((bfd_byte
*) buf
);
2074 return bfd_getl32 ((bfd_byte
*) buf
);
2077 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2081 write_insn (char *buf
, unsigned int insn
)
2083 md_number_to_chars (buf
, insn
, 4);
2087 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2088 has length LENGTH. */
2090 static unsigned long
2091 read_compressed_insn (char *buf
, unsigned int length
)
2097 for (i
= 0; i
< length
; i
+= 2)
2100 if (target_big_endian
)
2101 insn
|= bfd_getb16 ((char *) buf
);
2103 insn
|= bfd_getl16 ((char *) buf
);
2109 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2110 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2113 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2117 for (i
= 0; i
< length
; i
+= 2)
2118 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2119 return buf
+ length
;
2122 /* Install INSN at the location specified by its "frag" and "where" fields. */
2125 install_insn (const struct mips_cl_insn
*insn
)
2127 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2128 if (HAVE_CODE_COMPRESSION
)
2129 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2131 write_insn (f
, insn
->insn_opcode
);
2132 mips_record_compressed_mode ();
2135 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2136 and install the opcode in the new location. */
2139 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2144 insn
->where
= where
;
2145 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2146 if (insn
->fixp
[i
] != NULL
)
2148 insn
->fixp
[i
]->fx_frag
= frag
;
2149 insn
->fixp
[i
]->fx_where
= where
;
2151 install_insn (insn
);
2154 /* Add INSN to the end of the output. */
2157 add_fixed_insn (struct mips_cl_insn
*insn
)
2159 char *f
= frag_more (insn_length (insn
));
2160 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2163 /* Start a variant frag and move INSN to the start of the variant part,
2164 marking it as fixed. The other arguments are as for frag_var. */
2167 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2168 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2170 frag_grow (max_chars
);
2171 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2173 frag_var (rs_machine_dependent
, max_chars
, var
,
2174 subtype
, symbol
, offset
, NULL
);
2177 /* Insert N copies of INSN into the history buffer, starting at
2178 position FIRST. Neither FIRST nor N need to be clipped. */
2181 insert_into_history (unsigned int first
, unsigned int n
,
2182 const struct mips_cl_insn
*insn
)
2184 if (mips_relax
.sequence
!= 2)
2188 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2190 history
[i
] = history
[i
- n
];
2196 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2197 the idea is to make it obvious at a glance that each errata is
2201 init_vr4120_conflicts (void)
2203 #define CONFLICT(FIRST, SECOND) \
2204 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2206 /* Errata 21 - [D]DIV[U] after [D]MACC */
2207 CONFLICT (MACC
, DIV
);
2208 CONFLICT (DMACC
, DIV
);
2210 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2211 CONFLICT (DMULT
, DMULT
);
2212 CONFLICT (DMULT
, DMACC
);
2213 CONFLICT (DMACC
, DMULT
);
2214 CONFLICT (DMACC
, DMACC
);
2216 /* Errata 24 - MT{LO,HI} after [D]MACC */
2217 CONFLICT (MACC
, MTHILO
);
2218 CONFLICT (DMACC
, MTHILO
);
2220 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2221 instruction is executed immediately after a MACC or DMACC
2222 instruction, the result of [either instruction] is incorrect." */
2223 CONFLICT (MACC
, MULT
);
2224 CONFLICT (MACC
, DMULT
);
2225 CONFLICT (DMACC
, MULT
);
2226 CONFLICT (DMACC
, DMULT
);
2228 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2229 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2230 DDIV or DDIVU instruction, the result of the MACC or
2231 DMACC instruction is incorrect.". */
2232 CONFLICT (DMULT
, MACC
);
2233 CONFLICT (DMULT
, DMACC
);
2234 CONFLICT (DIV
, MACC
);
2235 CONFLICT (DIV
, DMACC
);
2245 #define RTYPE_MASK 0x1ff00
2246 #define RTYPE_NUM 0x00100
2247 #define RTYPE_FPU 0x00200
2248 #define RTYPE_FCC 0x00400
2249 #define RTYPE_VEC 0x00800
2250 #define RTYPE_GP 0x01000
2251 #define RTYPE_CP0 0x02000
2252 #define RTYPE_PC 0x04000
2253 #define RTYPE_ACC 0x08000
2254 #define RTYPE_CCC 0x10000
2255 #define RNUM_MASK 0x000ff
2256 #define RWARN 0x80000
2258 #define GENERIC_REGISTER_NUMBERS \
2259 {"$0", RTYPE_NUM | 0}, \
2260 {"$1", RTYPE_NUM | 1}, \
2261 {"$2", RTYPE_NUM | 2}, \
2262 {"$3", RTYPE_NUM | 3}, \
2263 {"$4", RTYPE_NUM | 4}, \
2264 {"$5", RTYPE_NUM | 5}, \
2265 {"$6", RTYPE_NUM | 6}, \
2266 {"$7", RTYPE_NUM | 7}, \
2267 {"$8", RTYPE_NUM | 8}, \
2268 {"$9", RTYPE_NUM | 9}, \
2269 {"$10", RTYPE_NUM | 10}, \
2270 {"$11", RTYPE_NUM | 11}, \
2271 {"$12", RTYPE_NUM | 12}, \
2272 {"$13", RTYPE_NUM | 13}, \
2273 {"$14", RTYPE_NUM | 14}, \
2274 {"$15", RTYPE_NUM | 15}, \
2275 {"$16", RTYPE_NUM | 16}, \
2276 {"$17", RTYPE_NUM | 17}, \
2277 {"$18", RTYPE_NUM | 18}, \
2278 {"$19", RTYPE_NUM | 19}, \
2279 {"$20", RTYPE_NUM | 20}, \
2280 {"$21", RTYPE_NUM | 21}, \
2281 {"$22", RTYPE_NUM | 22}, \
2282 {"$23", RTYPE_NUM | 23}, \
2283 {"$24", RTYPE_NUM | 24}, \
2284 {"$25", RTYPE_NUM | 25}, \
2285 {"$26", RTYPE_NUM | 26}, \
2286 {"$27", RTYPE_NUM | 27}, \
2287 {"$28", RTYPE_NUM | 28}, \
2288 {"$29", RTYPE_NUM | 29}, \
2289 {"$30", RTYPE_NUM | 30}, \
2290 {"$31", RTYPE_NUM | 31}
2292 #define FPU_REGISTER_NAMES \
2293 {"$f0", RTYPE_FPU | 0}, \
2294 {"$f1", RTYPE_FPU | 1}, \
2295 {"$f2", RTYPE_FPU | 2}, \
2296 {"$f3", RTYPE_FPU | 3}, \
2297 {"$f4", RTYPE_FPU | 4}, \
2298 {"$f5", RTYPE_FPU | 5}, \
2299 {"$f6", RTYPE_FPU | 6}, \
2300 {"$f7", RTYPE_FPU | 7}, \
2301 {"$f8", RTYPE_FPU | 8}, \
2302 {"$f9", RTYPE_FPU | 9}, \
2303 {"$f10", RTYPE_FPU | 10}, \
2304 {"$f11", RTYPE_FPU | 11}, \
2305 {"$f12", RTYPE_FPU | 12}, \
2306 {"$f13", RTYPE_FPU | 13}, \
2307 {"$f14", RTYPE_FPU | 14}, \
2308 {"$f15", RTYPE_FPU | 15}, \
2309 {"$f16", RTYPE_FPU | 16}, \
2310 {"$f17", RTYPE_FPU | 17}, \
2311 {"$f18", RTYPE_FPU | 18}, \
2312 {"$f19", RTYPE_FPU | 19}, \
2313 {"$f20", RTYPE_FPU | 20}, \
2314 {"$f21", RTYPE_FPU | 21}, \
2315 {"$f22", RTYPE_FPU | 22}, \
2316 {"$f23", RTYPE_FPU | 23}, \
2317 {"$f24", RTYPE_FPU | 24}, \
2318 {"$f25", RTYPE_FPU | 25}, \
2319 {"$f26", RTYPE_FPU | 26}, \
2320 {"$f27", RTYPE_FPU | 27}, \
2321 {"$f28", RTYPE_FPU | 28}, \
2322 {"$f29", RTYPE_FPU | 29}, \
2323 {"$f30", RTYPE_FPU | 30}, \
2324 {"$f31", RTYPE_FPU | 31}
2326 #define FPU_CONDITION_CODE_NAMES \
2327 {"$fcc0", RTYPE_FCC | 0}, \
2328 {"$fcc1", RTYPE_FCC | 1}, \
2329 {"$fcc2", RTYPE_FCC | 2}, \
2330 {"$fcc3", RTYPE_FCC | 3}, \
2331 {"$fcc4", RTYPE_FCC | 4}, \
2332 {"$fcc5", RTYPE_FCC | 5}, \
2333 {"$fcc6", RTYPE_FCC | 6}, \
2334 {"$fcc7", RTYPE_FCC | 7}
2336 #define COPROC_CONDITION_CODE_NAMES \
2337 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2338 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2339 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2340 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2341 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2342 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2343 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2344 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2346 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2347 {"$a4", RTYPE_GP | 8}, \
2348 {"$a5", RTYPE_GP | 9}, \
2349 {"$a6", RTYPE_GP | 10}, \
2350 {"$a7", RTYPE_GP | 11}, \
2351 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2352 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2353 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2354 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2355 {"$t0", RTYPE_GP | 12}, \
2356 {"$t1", RTYPE_GP | 13}, \
2357 {"$t2", RTYPE_GP | 14}, \
2358 {"$t3", RTYPE_GP | 15}
2360 #define O32_SYMBOLIC_REGISTER_NAMES \
2361 {"$t0", RTYPE_GP | 8}, \
2362 {"$t1", RTYPE_GP | 9}, \
2363 {"$t2", RTYPE_GP | 10}, \
2364 {"$t3", RTYPE_GP | 11}, \
2365 {"$t4", RTYPE_GP | 12}, \
2366 {"$t5", RTYPE_GP | 13}, \
2367 {"$t6", RTYPE_GP | 14}, \
2368 {"$t7", RTYPE_GP | 15}, \
2369 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2370 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2371 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2372 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2374 /* Remaining symbolic register names */
2375 #define SYMBOLIC_REGISTER_NAMES \
2376 {"$zero", RTYPE_GP | 0}, \
2377 {"$at", RTYPE_GP | 1}, \
2378 {"$AT", RTYPE_GP | 1}, \
2379 {"$v0", RTYPE_GP | 2}, \
2380 {"$v1", RTYPE_GP | 3}, \
2381 {"$a0", RTYPE_GP | 4}, \
2382 {"$a1", RTYPE_GP | 5}, \
2383 {"$a2", RTYPE_GP | 6}, \
2384 {"$a3", RTYPE_GP | 7}, \
2385 {"$s0", RTYPE_GP | 16}, \
2386 {"$s1", RTYPE_GP | 17}, \
2387 {"$s2", RTYPE_GP | 18}, \
2388 {"$s3", RTYPE_GP | 19}, \
2389 {"$s4", RTYPE_GP | 20}, \
2390 {"$s5", RTYPE_GP | 21}, \
2391 {"$s6", RTYPE_GP | 22}, \
2392 {"$s7", RTYPE_GP | 23}, \
2393 {"$t8", RTYPE_GP | 24}, \
2394 {"$t9", RTYPE_GP | 25}, \
2395 {"$k0", RTYPE_GP | 26}, \
2396 {"$kt0", RTYPE_GP | 26}, \
2397 {"$k1", RTYPE_GP | 27}, \
2398 {"$kt1", RTYPE_GP | 27}, \
2399 {"$gp", RTYPE_GP | 28}, \
2400 {"$sp", RTYPE_GP | 29}, \
2401 {"$s8", RTYPE_GP | 30}, \
2402 {"$fp", RTYPE_GP | 30}, \
2403 {"$ra", RTYPE_GP | 31}
2405 #define MIPS16_SPECIAL_REGISTER_NAMES \
2406 {"$pc", RTYPE_PC | 0}
2408 #define MDMX_VECTOR_REGISTER_NAMES \
2409 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2410 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2411 {"$v2", RTYPE_VEC | 2}, \
2412 {"$v3", RTYPE_VEC | 3}, \
2413 {"$v4", RTYPE_VEC | 4}, \
2414 {"$v5", RTYPE_VEC | 5}, \
2415 {"$v6", RTYPE_VEC | 6}, \
2416 {"$v7", RTYPE_VEC | 7}, \
2417 {"$v8", RTYPE_VEC | 8}, \
2418 {"$v9", RTYPE_VEC | 9}, \
2419 {"$v10", RTYPE_VEC | 10}, \
2420 {"$v11", RTYPE_VEC | 11}, \
2421 {"$v12", RTYPE_VEC | 12}, \
2422 {"$v13", RTYPE_VEC | 13}, \
2423 {"$v14", RTYPE_VEC | 14}, \
2424 {"$v15", RTYPE_VEC | 15}, \
2425 {"$v16", RTYPE_VEC | 16}, \
2426 {"$v17", RTYPE_VEC | 17}, \
2427 {"$v18", RTYPE_VEC | 18}, \
2428 {"$v19", RTYPE_VEC | 19}, \
2429 {"$v20", RTYPE_VEC | 20}, \
2430 {"$v21", RTYPE_VEC | 21}, \
2431 {"$v22", RTYPE_VEC | 22}, \
2432 {"$v23", RTYPE_VEC | 23}, \
2433 {"$v24", RTYPE_VEC | 24}, \
2434 {"$v25", RTYPE_VEC | 25}, \
2435 {"$v26", RTYPE_VEC | 26}, \
2436 {"$v27", RTYPE_VEC | 27}, \
2437 {"$v28", RTYPE_VEC | 28}, \
2438 {"$v29", RTYPE_VEC | 29}, \
2439 {"$v30", RTYPE_VEC | 30}, \
2440 {"$v31", RTYPE_VEC | 31}
2442 #define MIPS_DSP_ACCUMULATOR_NAMES \
2443 {"$ac0", RTYPE_ACC | 0}, \
2444 {"$ac1", RTYPE_ACC | 1}, \
2445 {"$ac2", RTYPE_ACC | 2}, \
2446 {"$ac3", RTYPE_ACC | 3}
2448 static const struct regname reg_names
[] = {
2449 GENERIC_REGISTER_NUMBERS
,
2451 FPU_CONDITION_CODE_NAMES
,
2452 COPROC_CONDITION_CODE_NAMES
,
2454 /* The $txx registers depends on the abi,
2455 these will be added later into the symbol table from
2456 one of the tables below once mips_abi is set after
2457 parsing of arguments from the command line. */
2458 SYMBOLIC_REGISTER_NAMES
,
2460 MIPS16_SPECIAL_REGISTER_NAMES
,
2461 MDMX_VECTOR_REGISTER_NAMES
,
2462 MIPS_DSP_ACCUMULATOR_NAMES
,
2466 static const struct regname reg_names_o32
[] = {
2467 O32_SYMBOLIC_REGISTER_NAMES
,
2471 static const struct regname reg_names_n32n64
[] = {
2472 N32N64_SYMBOLIC_REGISTER_NAMES
,
2476 /* Check if S points at a valid register specifier according to TYPES.
2477 If so, then return 1, advance S to consume the specifier and store
2478 the register's number in REGNOP, otherwise return 0. */
2481 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
2488 /* Find end of name. */
2490 if (is_name_beginner (*e
))
2492 while (is_part_of_name (*e
))
2495 /* Terminate name. */
2499 /* Look for a register symbol. */
2500 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
2502 int r
= S_GET_VALUE (symbolP
);
2504 reg
= r
& RNUM_MASK
;
2505 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
2506 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2507 reg
= (r
& RNUM_MASK
) - 2;
2509 /* Else see if this is a register defined in an itbl entry. */
2510 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
2517 if (itbl_get_reg_val (n
, &r
))
2518 reg
= r
& RNUM_MASK
;
2521 /* Advance to next token if a register was recognised. */
2524 else if (types
& RWARN
)
2525 as_warn (_("Unrecognized register name `%s'"), *s
);
2533 /* Check if S points at a valid register list according to TYPES.
2534 If so, then return 1, advance S to consume the list and store
2535 the registers present on the list as a bitmask of ones in REGLISTP,
2536 otherwise return 0. A valid list comprises a comma-separated
2537 enumeration of valid single registers and/or dash-separated
2538 contiguous register ranges as determined by their numbers.
2540 As a special exception if one of s0-s7 registers is specified as
2541 the range's lower delimiter and s8 (fp) is its upper one, then no
2542 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2543 are selected; they have to be listed separately if needed. */
2546 reglist_lookup (char **s
, unsigned int types
, unsigned int *reglistp
)
2548 unsigned int reglist
= 0;
2549 unsigned int lastregno
;
2550 bfd_boolean ok
= TRUE
;
2551 unsigned int regmask
;
2552 char *s_endlist
= *s
;
2556 while (reg_lookup (s
, types
, ®no
))
2562 ok
= reg_lookup (s
, types
, &lastregno
);
2563 if (ok
&& lastregno
< regno
)
2569 if (lastregno
== FP
&& regno
>= S0
&& regno
<= S7
)
2574 regmask
= 1 << lastregno
;
2575 regmask
= (regmask
<< 1) - 1;
2576 regmask
^= (1 << regno
) - 1;
2590 *reglistp
= reglist
;
2591 return ok
&& reglist
!= 0;
2594 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2595 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2598 is_opcode_valid (const struct mips_opcode
*mo
)
2600 int isa
= mips_opts
.isa
;
2601 int ase
= mips_opts
.ase
;
2605 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2606 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2607 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
2608 ase
|= mips_ases
[i
].flags64
;
2610 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
2613 /* Check whether the instruction or macro requires single-precision or
2614 double-precision floating-point support. Note that this information is
2615 stored differently in the opcode table for insns and macros. */
2616 if (mo
->pinfo
== INSN_MACRO
)
2618 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
2619 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
2623 fp_s
= mo
->pinfo
& FP_S
;
2624 fp_d
= mo
->pinfo
& FP_D
;
2627 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
2630 if (fp_s
&& mips_opts
.soft_float
)
2636 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2637 selected ISA and architecture. */
2640 is_opcode_valid_16 (const struct mips_opcode
*mo
)
2642 return opcode_is_member (mo
, mips_opts
.isa
, 0, mips_opts
.arch
);
2645 /* Return TRUE if the size of the microMIPS opcode MO matches one
2646 explicitly requested. Always TRUE in the standard MIPS mode. */
2649 is_size_valid (const struct mips_opcode
*mo
)
2651 if (!mips_opts
.micromips
)
2654 if (mips_opts
.insn32
)
2656 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
2658 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
2661 if (!forced_insn_length
)
2663 if (mo
->pinfo
== INSN_MACRO
)
2665 return forced_insn_length
== micromips_insn_length (mo
);
2668 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2669 of the preceding instruction. Always TRUE in the standard MIPS mode.
2671 We don't accept macros in 16-bit delay slots to avoid a case where
2672 a macro expansion fails because it relies on a preceding 32-bit real
2673 instruction to have matched and does not handle the operands correctly.
2674 The only macros that may expand to 16-bit instructions are JAL that
2675 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2676 and BGT (that likewise cannot be placed in a delay slot) that decay to
2677 a NOP. In all these cases the macros precede any corresponding real
2678 instruction definitions in the opcode table, so they will match in the
2679 second pass where the size of the delay slot is ignored and therefore
2680 produce correct code. */
2683 is_delay_slot_valid (const struct mips_opcode
*mo
)
2685 if (!mips_opts
.micromips
)
2688 if (mo
->pinfo
== INSN_MACRO
)
2689 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
2690 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
2691 && micromips_insn_length (mo
) != 4)
2693 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
2694 && micromips_insn_length (mo
) != 2)
2700 /* This function is called once, at assembler startup time. It should set up
2701 all the tables, etc. that the MD part of the assembler will need. */
2706 const char *retval
= NULL
;
2710 if (mips_pic
!= NO_PIC
)
2712 if (g_switch_seen
&& g_switch_value
!= 0)
2713 as_bad (_("-G may not be used in position-independent code"));
2717 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
2718 as_warn (_("Could not set architecture and machine"));
2720 op_hash
= hash_new ();
2722 for (i
= 0; i
< NUMOPCODES
;)
2724 const char *name
= mips_opcodes
[i
].name
;
2726 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
2729 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
2730 mips_opcodes
[i
].name
, retval
);
2731 /* Probably a memory allocation problem? Give up now. */
2732 as_fatal (_("Broken assembler. No assembly attempted."));
2736 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2738 if (!validate_mips_insn (&mips_opcodes
[i
]))
2740 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2742 create_insn (&nop_insn
, mips_opcodes
+ i
);
2743 if (mips_fix_loongson2f_nop
)
2744 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
2745 nop_insn
.fixed_p
= 1;
2750 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
2753 mips16_op_hash
= hash_new ();
2756 while (i
< bfd_mips16_num_opcodes
)
2758 const char *name
= mips16_opcodes
[i
].name
;
2760 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
2762 as_fatal (_("internal: can't hash `%s': %s"),
2763 mips16_opcodes
[i
].name
, retval
);
2766 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
2767 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
2768 != mips16_opcodes
[i
].match
))
2770 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
2771 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
2774 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
2776 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
2777 mips16_nop_insn
.fixed_p
= 1;
2781 while (i
< bfd_mips16_num_opcodes
2782 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
2785 micromips_op_hash
= hash_new ();
2788 while (i
< bfd_micromips_num_opcodes
)
2790 const char *name
= micromips_opcodes
[i
].name
;
2792 retval
= hash_insert (micromips_op_hash
, name
,
2793 (void *) µmips_opcodes
[i
]);
2795 as_fatal (_("internal: can't hash `%s': %s"),
2796 micromips_opcodes
[i
].name
, retval
);
2798 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
2800 struct mips_cl_insn
*micromips_nop_insn
;
2802 if (!validate_micromips_insn (µmips_opcodes
[i
]))
2805 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
2806 micromips_nop_insn
= µmips_nop16_insn
;
2807 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
2808 micromips_nop_insn
= µmips_nop32_insn
;
2812 if (micromips_nop_insn
->insn_mo
== NULL
2813 && strcmp (name
, "nop") == 0)
2815 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
2816 micromips_nop_insn
->fixed_p
= 1;
2819 while (++i
< bfd_micromips_num_opcodes
2820 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
2824 as_fatal (_("Broken assembler. No assembly attempted."));
2826 /* We add all the general register names to the symbol table. This
2827 helps us detect invalid uses of them. */
2828 for (i
= 0; reg_names
[i
].name
; i
++)
2829 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
2830 reg_names
[i
].num
, /* & RNUM_MASK, */
2831 &zero_address_frag
));
2833 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
2834 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
2835 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
2836 &zero_address_frag
));
2838 for (i
= 0; reg_names_o32
[i
].name
; i
++)
2839 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
2840 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
2841 &zero_address_frag
));
2843 mips_no_prev_insn ();
2846 mips_cprmask
[0] = 0;
2847 mips_cprmask
[1] = 0;
2848 mips_cprmask
[2] = 0;
2849 mips_cprmask
[3] = 0;
2851 /* set the default alignment for the text section (2**2) */
2852 record_alignment (text_section
, 2);
2854 bfd_set_gp_size (stdoutput
, g_switch_value
);
2856 /* On a native system other than VxWorks, sections must be aligned
2857 to 16 byte boundaries. When configured for an embedded ELF
2858 target, we don't bother. */
2859 if (strncmp (TARGET_OS
, "elf", 3) != 0
2860 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2862 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2863 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2864 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2867 /* Create a .reginfo section for register masks and a .mdebug
2868 section for debugging information. */
2876 subseg
= now_subseg
;
2878 /* The ABI says this section should be loaded so that the
2879 running program can access it. However, we don't load it
2880 if we are configured for an embedded target */
2881 flags
= SEC_READONLY
| SEC_DATA
;
2882 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2883 flags
|= SEC_ALLOC
| SEC_LOAD
;
2885 if (mips_abi
!= N64_ABI
)
2887 sec
= subseg_new (".reginfo", (subsegT
) 0);
2889 bfd_set_section_flags (stdoutput
, sec
, flags
);
2890 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2892 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2896 /* The 64-bit ABI uses a .MIPS.options section rather than
2897 .reginfo section. */
2898 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2899 bfd_set_section_flags (stdoutput
, sec
, flags
);
2900 bfd_set_section_alignment (stdoutput
, sec
, 3);
2902 /* Set up the option header. */
2904 Elf_Internal_Options opthdr
;
2907 opthdr
.kind
= ODK_REGINFO
;
2908 opthdr
.size
= (sizeof (Elf_External_Options
)
2909 + sizeof (Elf64_External_RegInfo
));
2912 f
= frag_more (sizeof (Elf_External_Options
));
2913 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2914 (Elf_External_Options
*) f
);
2916 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2920 if (ECOFF_DEBUGGING
)
2922 sec
= subseg_new (".mdebug", (subsegT
) 0);
2923 (void) bfd_set_section_flags (stdoutput
, sec
,
2924 SEC_HAS_CONTENTS
| SEC_READONLY
);
2925 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2927 else if (mips_flag_pdr
)
2929 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2930 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2931 SEC_READONLY
| SEC_RELOC
2933 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2936 subseg_set (seg
, subseg
);
2939 if (! ECOFF_DEBUGGING
)
2942 if (mips_fix_vr4120
)
2943 init_vr4120_conflicts ();
2949 mips_emit_delays ();
2950 if (! ECOFF_DEBUGGING
)
2955 md_assemble (char *str
)
2957 struct mips_cl_insn insn
;
2958 bfd_reloc_code_real_type unused_reloc
[3]
2959 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2961 imm_expr
.X_op
= O_absent
;
2962 imm2_expr
.X_op
= O_absent
;
2963 offset_expr
.X_op
= O_absent
;
2964 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2965 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2966 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2967 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2968 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2969 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2971 mips_mark_labels ();
2972 mips_assembling_insn
= TRUE
;
2974 if (mips_opts
.mips16
)
2975 mips16_ip (str
, &insn
);
2978 mips_ip (str
, &insn
);
2979 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2980 str
, insn
.insn_opcode
));
2984 as_bad ("%s `%s'", insn_error
, str
);
2985 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2988 if (mips_opts
.mips16
)
2989 mips16_macro (&insn
);
2996 if (imm_expr
.X_op
!= O_absent
)
2997 append_insn (&insn
, &imm_expr
, imm_reloc
, FALSE
);
2998 else if (offset_expr
.X_op
!= O_absent
)
2999 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
3001 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
3004 mips_assembling_insn
= FALSE
;
3007 /* Convenience functions for abstracting away the differences between
3008 MIPS16 and non-MIPS16 relocations. */
3010 static inline bfd_boolean
3011 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
3015 case BFD_RELOC_MIPS16_JMP
:
3016 case BFD_RELOC_MIPS16_GPREL
:
3017 case BFD_RELOC_MIPS16_GOT16
:
3018 case BFD_RELOC_MIPS16_CALL16
:
3019 case BFD_RELOC_MIPS16_HI16_S
:
3020 case BFD_RELOC_MIPS16_HI16
:
3021 case BFD_RELOC_MIPS16_LO16
:
3029 static inline bfd_boolean
3030 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
3034 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3035 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3036 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3037 case BFD_RELOC_MICROMIPS_GPREL16
:
3038 case BFD_RELOC_MICROMIPS_JMP
:
3039 case BFD_RELOC_MICROMIPS_HI16
:
3040 case BFD_RELOC_MICROMIPS_HI16_S
:
3041 case BFD_RELOC_MICROMIPS_LO16
:
3042 case BFD_RELOC_MICROMIPS_LITERAL
:
3043 case BFD_RELOC_MICROMIPS_GOT16
:
3044 case BFD_RELOC_MICROMIPS_CALL16
:
3045 case BFD_RELOC_MICROMIPS_GOT_HI16
:
3046 case BFD_RELOC_MICROMIPS_GOT_LO16
:
3047 case BFD_RELOC_MICROMIPS_CALL_HI16
:
3048 case BFD_RELOC_MICROMIPS_CALL_LO16
:
3049 case BFD_RELOC_MICROMIPS_SUB
:
3050 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
3051 case BFD_RELOC_MICROMIPS_GOT_OFST
:
3052 case BFD_RELOC_MICROMIPS_GOT_DISP
:
3053 case BFD_RELOC_MICROMIPS_HIGHEST
:
3054 case BFD_RELOC_MICROMIPS_HIGHER
:
3055 case BFD_RELOC_MICROMIPS_SCN_DISP
:
3056 case BFD_RELOC_MICROMIPS_JALR
:
3064 static inline bfd_boolean
3065 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
3067 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
3070 static inline bfd_boolean
3071 got16_reloc_p (bfd_reloc_code_real_type reloc
)
3073 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
3074 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
3077 static inline bfd_boolean
3078 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
3080 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
3081 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
3084 static inline bfd_boolean
3085 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
3087 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
3088 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
3091 static inline bfd_boolean
3092 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
3094 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
3097 /* Return true if RELOC is a PC-relative relocation that does not have
3098 full address range. */
3100 static inline bfd_boolean
3101 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
3105 case BFD_RELOC_16_PCREL_S2
:
3106 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
3107 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
3108 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
3111 case BFD_RELOC_32_PCREL
:
3112 return HAVE_64BIT_ADDRESSES
;
3119 /* Return true if the given relocation might need a matching %lo().
3120 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3121 need a matching %lo() when applied to local symbols. */
3123 static inline bfd_boolean
3124 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
3126 return (HAVE_IN_PLACE_ADDENDS
3127 && (hi16_reloc_p (reloc
)
3128 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3129 all GOT16 relocations evaluate to "G". */
3130 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
3133 /* Return the type of %lo() reloc needed by RELOC, given that
3134 reloc_needs_lo_p. */
3136 static inline bfd_reloc_code_real_type
3137 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
3139 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
3140 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
3144 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3147 static inline bfd_boolean
3148 fixup_has_matching_lo_p (fixS
*fixp
)
3150 return (fixp
->fx_next
!= NULL
3151 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
3152 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
3153 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
3156 /* This function returns true if modifying a register requires a
3160 reg_needs_delay (unsigned int reg
)
3162 unsigned long prev_pinfo
;
3164 prev_pinfo
= history
[0].insn_mo
->pinfo
;
3165 if (! mips_opts
.noreorder
3166 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
3167 && ! gpr_interlocks
)
3168 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
3169 && ! cop_interlocks
)))
3171 /* A load from a coprocessor or from memory. All load delays
3172 delay the use of general register rt for one instruction. */
3173 /* Itbl support may require additional care here. */
3174 know (prev_pinfo
& INSN_WRITE_GPR_T
);
3175 if (reg
== EXTRACT_OPERAND (mips_opts
.micromips
, RT
, history
[0]))
3182 /* Move all labels in LABELS to the current insertion point. TEXT_P
3183 says whether the labels refer to text or data. */
3186 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
3188 struct insn_label_list
*l
;
3191 for (l
= labels
; l
!= NULL
; l
= l
->next
)
3193 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
3194 symbol_set_frag (l
->label
, frag_now
);
3195 val
= (valueT
) frag_now_fix ();
3196 /* MIPS16/microMIPS text labels are stored as odd. */
3197 if (text_p
&& HAVE_CODE_COMPRESSION
)
3199 S_SET_VALUE (l
->label
, val
);
3203 /* Move all labels in insn_labels to the current insertion point
3204 and treat them as text labels. */
3207 mips_move_text_labels (void)
3209 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
3213 s_is_linkonce (symbolS
*sym
, segT from_seg
)
3215 bfd_boolean linkonce
= FALSE
;
3216 segT symseg
= S_GET_SEGMENT (sym
);
3218 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
3220 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
3222 /* The GNU toolchain uses an extension for ELF: a section
3223 beginning with the magic string .gnu.linkonce is a
3224 linkonce section. */
3225 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
3226 sizeof ".gnu.linkonce" - 1) == 0)
3232 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3233 linker to handle them specially, such as generating jalx instructions
3234 when needed. We also make them odd for the duration of the assembly,
3235 in order to generate the right sort of code. We will make them even
3236 in the adjust_symtab routine, while leaving them marked. This is
3237 convenient for the debugger and the disassembler. The linker knows
3238 to make them odd again. */
3241 mips_compressed_mark_label (symbolS
*label
)
3243 gas_assert (HAVE_CODE_COMPRESSION
);
3245 if (mips_opts
.mips16
)
3246 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
3248 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
3249 if ((S_GET_VALUE (label
) & 1) == 0
3250 /* Don't adjust the address if the label is global or weak, or
3251 in a link-once section, since we'll be emitting symbol reloc
3252 references to it which will be patched up by the linker, and
3253 the final value of the symbol may or may not be MIPS16/microMIPS. */
3254 && !S_IS_WEAK (label
)
3255 && !S_IS_EXTERNAL (label
)
3256 && !s_is_linkonce (label
, now_seg
))
3257 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
3260 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3263 mips_compressed_mark_labels (void)
3265 struct insn_label_list
*l
;
3267 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
3268 mips_compressed_mark_label (l
->label
);
3271 /* End the current frag. Make it a variant frag and record the
3275 relax_close_frag (void)
3277 mips_macro_warning
.first_frag
= frag_now
;
3278 frag_var (rs_machine_dependent
, 0, 0,
3279 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
3280 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
3282 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
3283 mips_relax
.first_fixup
= 0;
3286 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3287 See the comment above RELAX_ENCODE for more details. */
3290 relax_start (symbolS
*symbol
)
3292 gas_assert (mips_relax
.sequence
== 0);
3293 mips_relax
.sequence
= 1;
3294 mips_relax
.symbol
= symbol
;
3297 /* Start generating the second version of a relaxable sequence.
3298 See the comment above RELAX_ENCODE for more details. */
3303 gas_assert (mips_relax
.sequence
== 1);
3304 mips_relax
.sequence
= 2;
3307 /* End the current relaxable sequence. */
3312 gas_assert (mips_relax
.sequence
== 2);
3313 relax_close_frag ();
3314 mips_relax
.sequence
= 0;
3317 /* Return true if IP is a delayed branch or jump. */
3319 static inline bfd_boolean
3320 delayed_branch_p (const struct mips_cl_insn
*ip
)
3322 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
3323 | INSN_COND_BRANCH_DELAY
3324 | INSN_COND_BRANCH_LIKELY
)) != 0;
3327 /* Return true if IP is a compact branch or jump. */
3329 static inline bfd_boolean
3330 compact_branch_p (const struct mips_cl_insn
*ip
)
3332 if (mips_opts
.mips16
)
3333 return (ip
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
3334 | MIPS16_INSN_COND_BRANCH
)) != 0;
3336 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
3337 | INSN2_COND_BRANCH
)) != 0;
3340 /* Return true if IP is an unconditional branch or jump. */
3342 static inline bfd_boolean
3343 uncond_branch_p (const struct mips_cl_insn
*ip
)
3345 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
3346 || (mips_opts
.mips16
3347 ? (ip
->insn_mo
->pinfo
& MIPS16_INSN_UNCOND_BRANCH
) != 0
3348 : (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0));
3351 /* Return true if IP is a branch-likely instruction. */
3353 static inline bfd_boolean
3354 branch_likely_p (const struct mips_cl_insn
*ip
)
3356 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
3359 /* Return the type of nop that should be used to fill the delay slot
3360 of delayed branch IP. */
3362 static struct mips_cl_insn
*
3363 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
3365 if (mips_opts
.micromips
3366 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
3367 return µmips_nop32_insn
;
3371 /* Return the mask of core registers that IP reads or writes. */
3374 gpr_mod_mask (const struct mips_cl_insn
*ip
)
3376 unsigned long pinfo2
;
3380 pinfo2
= ip
->insn_mo
->pinfo2
;
3381 if (mips_opts
.micromips
)
3383 if (pinfo2
& INSN2_MOD_GPR_MD
)
3384 mask
|= 1 << micromips_to_32_reg_d_map
[EXTRACT_OPERAND (1, MD
, *ip
)];
3385 if (pinfo2
& INSN2_MOD_GPR_MF
)
3386 mask
|= 1 << micromips_to_32_reg_f_map
[EXTRACT_OPERAND (1, MF
, *ip
)];
3387 if (pinfo2
& INSN2_MOD_SP
)
3393 /* Return the mask of core registers that IP reads. */
3396 gpr_read_mask (const struct mips_cl_insn
*ip
)
3398 unsigned long pinfo
, pinfo2
;
3401 mask
= gpr_mod_mask (ip
);
3402 pinfo
= ip
->insn_mo
->pinfo
;
3403 pinfo2
= ip
->insn_mo
->pinfo2
;
3404 if (mips_opts
.mips16
)
3406 if (pinfo
& MIPS16_INSN_READ_X
)
3407 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3408 if (pinfo
& MIPS16_INSN_READ_Y
)
3409 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3410 if (pinfo
& MIPS16_INSN_READ_T
)
3412 if (pinfo
& MIPS16_INSN_READ_SP
)
3414 if (pinfo
& MIPS16_INSN_READ_31
)
3416 if (pinfo
& MIPS16_INSN_READ_Z
)
3417 mask
|= 1 << (mips16_to_32_reg_map
3418 [MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]);
3419 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3420 mask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3424 if (pinfo2
& INSN2_READ_GPR_D
)
3425 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3426 if (pinfo
& INSN_READ_GPR_T
)
3427 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3428 if (pinfo
& INSN_READ_GPR_S
)
3429 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3430 if (pinfo2
& INSN2_READ_GP
)
3432 if (pinfo2
& INSN2_READ_GPR_31
)
3434 if (pinfo2
& INSN2_READ_GPR_Z
)
3435 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3437 if (mips_opts
.micromips
)
3439 if (pinfo2
& INSN2_READ_GPR_MC
)
3440 mask
|= 1 << micromips_to_32_reg_c_map
[EXTRACT_OPERAND (1, MC
, *ip
)];
3441 if (pinfo2
& INSN2_READ_GPR_ME
)
3442 mask
|= 1 << micromips_to_32_reg_e_map
[EXTRACT_OPERAND (1, ME
, *ip
)];
3443 if (pinfo2
& INSN2_READ_GPR_MG
)
3444 mask
|= 1 << micromips_to_32_reg_g_map
[EXTRACT_OPERAND (1, MG
, *ip
)];
3445 if (pinfo2
& INSN2_READ_GPR_MJ
)
3446 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3447 if (pinfo2
& INSN2_READ_GPR_MMN
)
3449 mask
|= 1 << micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
3450 mask
|= 1 << micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
3452 if (pinfo2
& INSN2_READ_GPR_MP
)
3453 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3454 if (pinfo2
& INSN2_READ_GPR_MQ
)
3455 mask
|= 1 << micromips_to_32_reg_q_map
[EXTRACT_OPERAND (1, MQ
, *ip
)];
3457 /* Don't include register 0. */
3461 /* Return the mask of core registers that IP writes. */
3464 gpr_write_mask (const struct mips_cl_insn
*ip
)
3466 unsigned long pinfo
, pinfo2
;
3469 mask
= gpr_mod_mask (ip
);
3470 pinfo
= ip
->insn_mo
->pinfo
;
3471 pinfo2
= ip
->insn_mo
->pinfo2
;
3472 if (mips_opts
.mips16
)
3474 if (pinfo
& MIPS16_INSN_WRITE_X
)
3475 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)];
3476 if (pinfo
& MIPS16_INSN_WRITE_Y
)
3477 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)];
3478 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3479 mask
|= 1 << mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RZ
, *ip
)];
3480 if (pinfo
& MIPS16_INSN_WRITE_T
)
3482 if (pinfo
& MIPS16_INSN_WRITE_SP
)
3484 if (pinfo
& MIPS16_INSN_WRITE_31
)
3486 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3487 mask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3491 if (pinfo
& INSN_WRITE_GPR_D
)
3492 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
3493 if (pinfo
& INSN_WRITE_GPR_T
)
3494 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
3495 if (pinfo
& INSN_WRITE_GPR_S
)
3496 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
3497 if (pinfo
& INSN_WRITE_GPR_31
)
3499 if (pinfo2
& INSN2_WRITE_GPR_Z
)
3500 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RZ
, *ip
);
3502 if (mips_opts
.micromips
)
3504 if (pinfo2
& INSN2_WRITE_GPR_MB
)
3505 mask
|= 1 << micromips_to_32_reg_b_map
[EXTRACT_OPERAND (1, MB
, *ip
)];
3506 if (pinfo2
& INSN2_WRITE_GPR_MHI
)
3508 mask
|= 1 << micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
3509 mask
|= 1 << micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
3511 if (pinfo2
& INSN2_WRITE_GPR_MJ
)
3512 mask
|= 1 << EXTRACT_OPERAND (1, MJ
, *ip
);
3513 if (pinfo2
& INSN2_WRITE_GPR_MP
)
3514 mask
|= 1 << EXTRACT_OPERAND (1, MP
, *ip
);
3516 /* Don't include register 0. */
3520 /* Return the mask of floating-point registers that IP reads. */
3523 fpr_read_mask (const struct mips_cl_insn
*ip
)
3525 unsigned long pinfo
, pinfo2
;
3529 pinfo
= ip
->insn_mo
->pinfo
;
3530 pinfo2
= ip
->insn_mo
->pinfo2
;
3531 if (!mips_opts
.mips16
)
3533 if (pinfo2
& INSN2_READ_FPR_D
)
3534 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3535 if (pinfo
& INSN_READ_FPR_S
)
3536 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3537 if (pinfo
& INSN_READ_FPR_T
)
3538 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3539 if (pinfo
& INSN_READ_FPR_R
)
3540 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FR
, *ip
);
3541 if (pinfo2
& INSN2_READ_FPR_Z
)
3542 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3544 /* Conservatively treat all operands to an FP_D instruction are doubles.
3545 (This is overly pessimistic for things like cvt.d.s.) */
3546 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3551 /* Return the mask of floating-point registers that IP writes. */
3554 fpr_write_mask (const struct mips_cl_insn
*ip
)
3556 unsigned long pinfo
, pinfo2
;
3560 pinfo
= ip
->insn_mo
->pinfo
;
3561 pinfo2
= ip
->insn_mo
->pinfo2
;
3562 if (!mips_opts
.mips16
)
3564 if (pinfo
& INSN_WRITE_FPR_D
)
3565 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FD
, *ip
);
3566 if (pinfo
& INSN_WRITE_FPR_S
)
3567 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FS
, *ip
);
3568 if (pinfo
& INSN_WRITE_FPR_T
)
3569 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FT
, *ip
);
3570 if (pinfo2
& INSN2_WRITE_FPR_Z
)
3571 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, FZ
, *ip
);
3573 /* Conservatively treat all operands to an FP_D instruction are doubles.
3574 (This is overly pessimistic for things like cvt.s.d.) */
3575 if (HAVE_32BIT_FPRS
&& (pinfo
& FP_D
))
3580 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3581 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3582 by VR4120 errata. */
3585 classify_vr4120_insn (const char *name
)
3587 if (strncmp (name
, "macc", 4) == 0)
3588 return FIX_VR4120_MACC
;
3589 if (strncmp (name
, "dmacc", 5) == 0)
3590 return FIX_VR4120_DMACC
;
3591 if (strncmp (name
, "mult", 4) == 0)
3592 return FIX_VR4120_MULT
;
3593 if (strncmp (name
, "dmult", 5) == 0)
3594 return FIX_VR4120_DMULT
;
3595 if (strstr (name
, "div"))
3596 return FIX_VR4120_DIV
;
3597 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
3598 return FIX_VR4120_MTHILO
;
3599 return NUM_FIX_VR4120_CLASSES
;
3602 #define INSN_ERET 0x42000018
3603 #define INSN_DERET 0x4200001f
3605 /* Return the number of instructions that must separate INSN1 and INSN2,
3606 where INSN1 is the earlier instruction. Return the worst-case value
3607 for any INSN2 if INSN2 is null. */
3610 insns_between (const struct mips_cl_insn
*insn1
,
3611 const struct mips_cl_insn
*insn2
)
3613 unsigned long pinfo1
, pinfo2
;
3616 /* This function needs to know which pinfo flags are set for INSN2
3617 and which registers INSN2 uses. The former is stored in PINFO2 and
3618 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3619 will have every flag set and INSN2_USES_GPR will always return true. */
3620 pinfo1
= insn1
->insn_mo
->pinfo
;
3621 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
3623 #define INSN2_USES_GPR(REG) \
3624 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3626 /* For most targets, write-after-read dependencies on the HI and LO
3627 registers must be separated by at least two instructions. */
3628 if (!hilo_interlocks
)
3630 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
3632 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
3636 /* If we're working around r7000 errata, there must be two instructions
3637 between an mfhi or mflo and any instruction that uses the result. */
3638 if (mips_7000_hilo_fix
3639 && !mips_opts
.micromips
3640 && MF_HILO_INSN (pinfo1
)
3641 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD
, *insn1
)))
3644 /* If we're working around 24K errata, one instruction is required
3645 if an ERET or DERET is followed by a branch instruction. */
3646 if (mips_fix_24k
&& !mips_opts
.micromips
)
3648 if (insn1
->insn_opcode
== INSN_ERET
3649 || insn1
->insn_opcode
== INSN_DERET
)
3652 || insn2
->insn_opcode
== INSN_ERET
3653 || insn2
->insn_opcode
== INSN_DERET
3654 || delayed_branch_p (insn2
))
3659 /* If working around VR4120 errata, check for combinations that need
3660 a single intervening instruction. */
3661 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
3663 unsigned int class1
, class2
;
3665 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
3666 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
3670 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
3671 if (vr4120_conflicts
[class1
] & (1 << class2
))
3676 if (!HAVE_CODE_COMPRESSION
)
3678 /* Check for GPR or coprocessor load delays. All such delays
3679 are on the RT register. */
3680 /* Itbl support may require additional care here. */
3681 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
3682 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
3684 know (pinfo1
& INSN_WRITE_GPR_T
);
3685 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT
, *insn1
)))
3689 /* Check for generic coprocessor hazards.
3691 This case is not handled very well. There is no special
3692 knowledge of CP0 handling, and the coprocessors other than
3693 the floating point unit are not distinguished at all. */
3694 /* Itbl support may require additional care here. FIXME!
3695 Need to modify this to include knowledge about
3696 user specified delays! */
3697 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
3698 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
3700 /* Handle cases where INSN1 writes to a known general coprocessor
3701 register. There must be a one instruction delay before INSN2
3702 if INSN2 reads that register, otherwise no delay is needed. */
3703 mask
= fpr_write_mask (insn1
);
3706 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
3711 /* Read-after-write dependencies on the control registers
3712 require a two-instruction gap. */
3713 if ((pinfo1
& INSN_WRITE_COND_CODE
)
3714 && (pinfo2
& INSN_READ_COND_CODE
))
3717 /* We don't know exactly what INSN1 does. If INSN2 is
3718 also a coprocessor instruction, assume there must be
3719 a one instruction gap. */
3720 if (pinfo2
& INSN_COP
)
3725 /* Check for read-after-write dependencies on the coprocessor
3726 control registers in cases where INSN1 does not need a general
3727 coprocessor delay. This means that INSN1 is a floating point
3728 comparison instruction. */
3729 /* Itbl support may require additional care here. */
3730 else if (!cop_interlocks
3731 && (pinfo1
& INSN_WRITE_COND_CODE
)
3732 && (pinfo2
& INSN_READ_COND_CODE
))
3736 #undef INSN2_USES_GPR
3741 /* Return the number of nops that would be needed to work around the
3742 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3743 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3744 that are contained within the first IGNORE instructions of HIST. */
3747 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
3748 const struct mips_cl_insn
*insn
)
3753 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3754 are not affected by the errata. */
3756 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
3757 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
3758 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
3761 /* Search for the first MFLO or MFHI. */
3762 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
3763 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
3765 /* Extract the destination register. */
3766 mask
= gpr_write_mask (&hist
[i
]);
3768 /* No nops are needed if INSN reads that register. */
3769 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
3772 /* ...or if any of the intervening instructions do. */
3773 for (j
= 0; j
< i
; j
++)
3774 if (gpr_read_mask (&hist
[j
]) & mask
)
3778 return MAX_VR4130_NOPS
- i
;
3783 #define BASE_REG_EQ(INSN1, INSN2) \
3784 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3785 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3787 /* Return the minimum alignment for this store instruction. */
3790 fix_24k_align_to (const struct mips_opcode
*mo
)
3792 if (strcmp (mo
->name
, "sh") == 0)
3795 if (strcmp (mo
->name
, "swc1") == 0
3796 || strcmp (mo
->name
, "swc2") == 0
3797 || strcmp (mo
->name
, "sw") == 0
3798 || strcmp (mo
->name
, "sc") == 0
3799 || strcmp (mo
->name
, "s.s") == 0)
3802 if (strcmp (mo
->name
, "sdc1") == 0
3803 || strcmp (mo
->name
, "sdc2") == 0
3804 || strcmp (mo
->name
, "s.d") == 0)
3811 struct fix_24k_store_info
3813 /* Immediate offset, if any, for this store instruction. */
3815 /* Alignment required by this store instruction. */
3817 /* True for register offsets. */
3818 int register_offset
;
3821 /* Comparison function used by qsort. */
3824 fix_24k_sort (const void *a
, const void *b
)
3826 const struct fix_24k_store_info
*pos1
= a
;
3827 const struct fix_24k_store_info
*pos2
= b
;
3829 return (pos1
->off
- pos2
->off
);
3832 /* INSN is a store instruction. Try to record the store information
3833 in STINFO. Return false if the information isn't known. */
3836 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
3837 const struct mips_cl_insn
*insn
)
3839 /* The instruction must have a known offset. */
3840 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
3843 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
3844 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
3848 /* Return the number of nops that would be needed to work around the 24k
3849 "lost data on stores during refill" errata if instruction INSN
3850 immediately followed the 2 instructions described by HIST.
3851 Ignore hazards that are contained within the first IGNORE
3852 instructions of HIST.
3854 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3855 for the data cache refills and store data. The following describes
3856 the scenario where the store data could be lost.
3858 * A data cache miss, due to either a load or a store, causing fill
3859 data to be supplied by the memory subsystem
3860 * The first three doublewords of fill data are returned and written
3862 * A sequence of four stores occurs in consecutive cycles around the
3863 final doubleword of the fill:
3867 * Zero, One or more instructions
3870 The four stores A-D must be to different doublewords of the line that
3871 is being filled. The fourth instruction in the sequence above permits
3872 the fill of the final doubleword to be transferred from the FSB into
3873 the cache. In the sequence above, the stores may be either integer
3874 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3875 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3876 different doublewords on the line. If the floating point unit is
3877 running in 1:2 mode, it is not possible to create the sequence above
3878 using only floating point store instructions.
3880 In this case, the cache line being filled is incorrectly marked
3881 invalid, thereby losing the data from any store to the line that
3882 occurs between the original miss and the completion of the five
3883 cycle sequence shown above.
3885 The workarounds are:
3887 * Run the data cache in write-through mode.
3888 * Insert a non-store instruction between
3889 Store A and Store B or Store B and Store C. */
3892 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
3893 const struct mips_cl_insn
*insn
)
3895 struct fix_24k_store_info pos
[3];
3896 int align
, i
, base_offset
;
3901 /* If the previous instruction wasn't a store, there's nothing to
3903 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3906 /* If the instructions after the previous one are unknown, we have
3907 to assume the worst. */
3911 /* Check whether we are dealing with three consecutive stores. */
3912 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
3913 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
3916 /* If we don't know the relationship between the store addresses,
3917 assume the worst. */
3918 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
3919 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
3922 if (!fix_24k_record_store_info (&pos
[0], insn
)
3923 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
3924 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
3927 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
3929 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3930 X bytes and such that the base register + X is known to be aligned
3933 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
3937 align
= pos
[0].align_to
;
3938 base_offset
= pos
[0].off
;
3939 for (i
= 1; i
< 3; i
++)
3940 if (align
< pos
[i
].align_to
)
3942 align
= pos
[i
].align_to
;
3943 base_offset
= pos
[i
].off
;
3945 for (i
= 0; i
< 3; i
++)
3946 pos
[i
].off
-= base_offset
;
3949 pos
[0].off
&= ~align
+ 1;
3950 pos
[1].off
&= ~align
+ 1;
3951 pos
[2].off
&= ~align
+ 1;
3953 /* If any two stores write to the same chunk, they also write to the
3954 same doubleword. The offsets are still sorted at this point. */
3955 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
3958 /* A range of at least 9 bytes is needed for the stores to be in
3959 non-overlapping doublewords. */
3960 if (pos
[2].off
- pos
[0].off
<= 8)
3963 if (pos
[2].off
- pos
[1].off
>= 24
3964 || pos
[1].off
- pos
[0].off
>= 24
3965 || pos
[2].off
- pos
[0].off
>= 32)
3971 /* Return the number of nops that would be needed if instruction INSN
3972 immediately followed the MAX_NOPS instructions given by HIST,
3973 where HIST[0] is the most recent instruction. Ignore hazards
3974 between INSN and the first IGNORE instructions in HIST.
3976 If INSN is null, return the worse-case number of nops for any
3980 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
3981 const struct mips_cl_insn
*insn
)
3983 int i
, nops
, tmp_nops
;
3986 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
3988 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
3989 if (tmp_nops
> nops
)
3993 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
3995 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
3996 if (tmp_nops
> nops
)
4000 if (mips_fix_24k
&& !mips_opts
.micromips
)
4002 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
4003 if (tmp_nops
> nops
)
4010 /* The variable arguments provide NUM_INSNS extra instructions that
4011 might be added to HIST. Return the largest number of nops that
4012 would be needed after the extended sequence, ignoring hazards
4013 in the first IGNORE instructions. */
4016 nops_for_sequence (int num_insns
, int ignore
,
4017 const struct mips_cl_insn
*hist
, ...)
4020 struct mips_cl_insn buffer
[MAX_NOPS
];
4021 struct mips_cl_insn
*cursor
;
4024 va_start (args
, hist
);
4025 cursor
= buffer
+ num_insns
;
4026 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
4027 while (cursor
> buffer
)
4028 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
4030 nops
= nops_for_insn (ignore
, buffer
, NULL
);
4035 /* Like nops_for_insn, but if INSN is a branch, take into account the
4036 worst-case delay for the branch target. */
4039 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
4040 const struct mips_cl_insn
*insn
)
4044 nops
= nops_for_insn (ignore
, hist
, insn
);
4045 if (delayed_branch_p (insn
))
4047 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
4048 hist
, insn
, get_delay_slot_nop (insn
));
4049 if (tmp_nops
> nops
)
4052 else if (compact_branch_p (insn
))
4054 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
4055 if (tmp_nops
> nops
)
4061 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4064 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
4066 gas_assert (!HAVE_CODE_COMPRESSION
);
4067 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
4068 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
4071 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4072 jr target pc &= 'hffff_ffff_cfff_ffff. */
4075 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
4077 gas_assert (!HAVE_CODE_COMPRESSION
);
4078 if (strcmp (ip
->insn_mo
->name
, "j") == 0
4079 || strcmp (ip
->insn_mo
->name
, "jr") == 0
4080 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
4088 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
4089 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
4092 ep
.X_op
= O_constant
;
4093 ep
.X_add_number
= 0xcfff0000;
4094 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
4095 ep
.X_add_number
= 0xffff;
4096 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
4097 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
4102 fix_loongson2f (struct mips_cl_insn
* ip
)
4104 if (mips_fix_loongson2f_nop
)
4105 fix_loongson2f_nop (ip
);
4107 if (mips_fix_loongson2f_jump
)
4108 fix_loongson2f_jump (ip
);
4111 /* IP is a branch that has a delay slot, and we need to fill it
4112 automatically. Return true if we can do that by swapping IP
4113 with the previous instruction.
4114 ADDRESS_EXPR is an operand of the instruction to be used with
4118 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4119 bfd_reloc_code_real_type
*reloc_type
)
4121 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
4122 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
4124 /* -O2 and above is required for this optimization. */
4125 if (mips_optimize
< 2)
4128 /* If we have seen .set volatile or .set nomove, don't optimize. */
4129 if (mips_opts
.nomove
)
4132 /* We can't swap if the previous instruction's position is fixed. */
4133 if (history
[0].fixed_p
)
4136 /* If the previous previous insn was in a .set noreorder, we can't
4137 swap. Actually, the MIPS assembler will swap in this situation.
4138 However, gcc configured -with-gnu-as will generate code like
4146 in which we can not swap the bne and INSN. If gcc is not configured
4147 -with-gnu-as, it does not output the .set pseudo-ops. */
4148 if (history
[1].noreorder_p
)
4151 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4152 This means that the previous instruction was a 4-byte one anyhow. */
4153 if (mips_opts
.mips16
&& history
[0].fixp
[0])
4156 /* If the branch is itself the target of a branch, we can not swap.
4157 We cheat on this; all we check for is whether there is a label on
4158 this instruction. If there are any branches to anything other than
4159 a label, users must use .set noreorder. */
4160 if (seg_info (now_seg
)->label_list
)
4163 /* If the previous instruction is in a variant frag other than this
4164 branch's one, we cannot do the swap. This does not apply to
4165 MIPS16 code, which uses variant frags for different purposes. */
4166 if (!mips_opts
.mips16
4168 && history
[0].frag
->fr_type
== rs_machine_dependent
)
4171 /* We do not swap with instructions that cannot architecturally
4172 be placed in a branch delay slot, such as SYNC or ERET. We
4173 also refrain from swapping with a trap instruction, since it
4174 complicates trap handlers to have the trap instruction be in
4176 prev_pinfo
= history
[0].insn_mo
->pinfo
;
4177 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
4180 /* Check for conflicts between the branch and the instructions
4181 before the candidate delay slot. */
4182 if (nops_for_insn (0, history
+ 1, ip
) > 0)
4185 /* Check for conflicts between the swapped sequence and the
4186 target of the branch. */
4187 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
4190 /* If the branch reads a register that the previous
4191 instruction sets, we can not swap. */
4192 gpr_read
= gpr_read_mask (ip
);
4193 prev_gpr_write
= gpr_write_mask (&history
[0]);
4194 if (gpr_read
& prev_gpr_write
)
4197 /* If the branch writes a register that the previous
4198 instruction sets, we can not swap. */
4199 gpr_write
= gpr_write_mask (ip
);
4200 if (gpr_write
& prev_gpr_write
)
4203 /* If the branch writes a register that the previous
4204 instruction reads, we can not swap. */
4205 prev_gpr_read
= gpr_read_mask (&history
[0]);
4206 if (gpr_write
& prev_gpr_read
)
4209 /* If one instruction sets a condition code and the
4210 other one uses a condition code, we can not swap. */
4211 pinfo
= ip
->insn_mo
->pinfo
;
4212 if ((pinfo
& INSN_READ_COND_CODE
)
4213 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
4215 if ((pinfo
& INSN_WRITE_COND_CODE
)
4216 && (prev_pinfo
& INSN_READ_COND_CODE
))
4219 /* If the previous instruction uses the PC, we can not swap. */
4220 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4221 if (mips_opts
.mips16
&& (prev_pinfo
& MIPS16_INSN_READ_PC
))
4223 if (mips_opts
.micromips
&& (prev_pinfo2
& INSN2_READ_PC
))
4226 /* If the previous instruction has an incorrect size for a fixed
4227 branch delay slot in microMIPS mode, we cannot swap. */
4228 pinfo2
= ip
->insn_mo
->pinfo2
;
4229 if (mips_opts
.micromips
4230 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
4231 && insn_length (history
) != 2)
4233 if (mips_opts
.micromips
4234 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
4235 && insn_length (history
) != 4)
4238 /* On R5900 short loops need to be fixed by inserting a nop in
4239 the branch delay slots.
4240 A short loop can be terminated too early. */
4241 if (mips_opts
.arch
== CPU_R5900
4242 /* Check if instruction has a parameter, ignore "j $31". */
4243 && (address_expr
!= NULL
)
4244 /* Parameter must be 16 bit. */
4245 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
4246 /* Branch to same segment. */
4247 && (S_GET_SEGMENT(address_expr
->X_add_symbol
) == now_seg
)
4248 /* Branch to same code fragment. */
4249 && (symbol_get_frag(address_expr
->X_add_symbol
) == frag_now
)
4250 /* Can only calculate branch offset if value is known. */
4251 && symbol_constant_p(address_expr
->X_add_symbol
)
4252 /* Check if branch is really conditional. */
4253 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
4254 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
4255 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
4258 /* Check if loop is shorter than 6 instructions including
4259 branch and delay slot. */
4260 distance
= frag_now_fix() - S_GET_VALUE(address_expr
->X_add_symbol
);
4267 /* When the loop includes branches or jumps,
4268 it is not a short loop. */
4269 for (i
= 0; i
< (distance
/ 4); i
++)
4271 if ((history
[i
].cleared_p
)
4272 || delayed_branch_p(&history
[i
]))
4280 /* Insert nop after branch to fix short loop. */
4289 /* Decide how we should add IP to the instruction stream.
4290 ADDRESS_EXPR is an operand of the instruction to be used with
4293 static enum append_method
4294 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4295 bfd_reloc_code_real_type
*reloc_type
)
4297 unsigned long pinfo
;
4299 /* The relaxed version of a macro sequence must be inherently
4301 if (mips_relax
.sequence
== 2)
4304 /* We must not dabble with instructions in a ".set norerorder" block. */
4305 if (mips_opts
.noreorder
)
4308 /* Otherwise, it's our responsibility to fill branch delay slots. */
4309 if (delayed_branch_p (ip
))
4311 if (!branch_likely_p (ip
)
4312 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
4315 pinfo
= ip
->insn_mo
->pinfo
;
4316 if (mips_opts
.mips16
4317 && ISA_SUPPORTS_MIPS16E
4318 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
)))
4319 return APPEND_ADD_COMPACT
;
4321 return APPEND_ADD_WITH_NOP
;
4327 /* IP is a MIPS16 instruction whose opcode we have just changed.
4328 Point IP->insn_mo to the new opcode's definition. */
4331 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
4333 const struct mips_opcode
*mo
, *end
;
4335 end
= &mips16_opcodes
[bfd_mips16_num_opcodes
];
4336 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
4337 if ((ip
->insn_opcode
& mo
->mask
) == mo
->match
)
4345 /* For microMIPS macros, we need to generate a local number label
4346 as the target of branches. */
4347 #define MICROMIPS_LABEL_CHAR '\037'
4348 static unsigned long micromips_target_label
;
4349 static char micromips_target_name
[32];
4352 micromips_label_name (void)
4354 char *p
= micromips_target_name
;
4355 char symbol_name_temporary
[24];
4363 l
= micromips_target_label
;
4364 #ifdef LOCAL_LABEL_PREFIX
4365 *p
++ = LOCAL_LABEL_PREFIX
;
4368 *p
++ = MICROMIPS_LABEL_CHAR
;
4371 symbol_name_temporary
[i
++] = l
% 10 + '0';
4376 *p
++ = symbol_name_temporary
[--i
];
4379 return micromips_target_name
;
4383 micromips_label_expr (expressionS
*label_expr
)
4385 label_expr
->X_op
= O_symbol
;
4386 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
4387 label_expr
->X_add_number
= 0;
4391 micromips_label_inc (void)
4393 micromips_target_label
++;
4394 *micromips_target_name
= '\0';
4398 micromips_add_label (void)
4402 s
= colon (micromips_label_name ());
4403 micromips_label_inc ();
4404 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
4407 /* If assembling microMIPS code, then return the microMIPS reloc
4408 corresponding to the requested one if any. Otherwise return
4409 the reloc unchanged. */
4411 static bfd_reloc_code_real_type
4412 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
4414 static const bfd_reloc_code_real_type relocs
[][2] =
4416 /* Keep sorted incrementally by the left-hand key. */
4417 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
4418 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
4419 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
4420 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
4421 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
4422 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
4423 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
4424 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
4425 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
4426 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
4427 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
4428 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
4429 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
4430 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
4431 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
4432 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
4433 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
4434 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
4435 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
4436 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
4437 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
4438 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
4439 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
4440 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
4441 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
4442 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
4443 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
4445 bfd_reloc_code_real_type r
;
4448 if (!mips_opts
.micromips
)
4450 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
4456 return relocs
[i
][1];
4461 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4462 Return true on success, storing the resolved value in RESULT. */
4465 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
4470 case BFD_RELOC_MIPS_HIGHEST
:
4471 case BFD_RELOC_MICROMIPS_HIGHEST
:
4472 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
4475 case BFD_RELOC_MIPS_HIGHER
:
4476 case BFD_RELOC_MICROMIPS_HIGHER
:
4477 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
4480 case BFD_RELOC_HI16_S
:
4481 case BFD_RELOC_MICROMIPS_HI16_S
:
4482 case BFD_RELOC_MIPS16_HI16_S
:
4483 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
4486 case BFD_RELOC_HI16
:
4487 case BFD_RELOC_MICROMIPS_HI16
:
4488 case BFD_RELOC_MIPS16_HI16
:
4489 *result
= (operand
>> 16) & 0xffff;
4492 case BFD_RELOC_LO16
:
4493 case BFD_RELOC_MICROMIPS_LO16
:
4494 case BFD_RELOC_MIPS16_LO16
:
4495 *result
= operand
& 0xffff;
4498 case BFD_RELOC_UNUSED
:
4507 /* Output an instruction. IP is the instruction information.
4508 ADDRESS_EXPR is an operand of the instruction to be used with
4509 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4510 a macro expansion. */
4513 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
4514 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
4516 unsigned long prev_pinfo2
, pinfo
;
4517 bfd_boolean relaxed_branch
= FALSE
;
4518 enum append_method method
;
4519 bfd_boolean relax32
;
4522 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
4523 fix_loongson2f (ip
);
4525 file_ase_mips16
|= mips_opts
.mips16
;
4526 file_ase_micromips
|= mips_opts
.micromips
;
4528 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
4529 pinfo
= ip
->insn_mo
->pinfo
;
4531 if (mips_opts
.micromips
4533 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
4534 && micromips_insn_length (ip
->insn_mo
) != 2)
4535 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
4536 && micromips_insn_length (ip
->insn_mo
) != 4)))
4537 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4538 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
4540 if (address_expr
== NULL
)
4542 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
4543 && reloc_type
[1] == BFD_RELOC_UNUSED
4544 && reloc_type
[2] == BFD_RELOC_UNUSED
4545 && address_expr
->X_op
== O_constant
)
4547 switch (*reloc_type
)
4549 case BFD_RELOC_MIPS_JMP
:
4553 shift
= mips_opts
.micromips
? 1 : 2;
4554 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4555 as_bad (_("jump to misaligned address (0x%lx)"),
4556 (unsigned long) address_expr
->X_add_number
);
4557 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4563 case BFD_RELOC_MIPS16_JMP
:
4564 if ((address_expr
->X_add_number
& 3) != 0)
4565 as_bad (_("jump to misaligned address (0x%lx)"),
4566 (unsigned long) address_expr
->X_add_number
);
4568 (((address_expr
->X_add_number
& 0x7c0000) << 3)
4569 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
4570 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
4574 case BFD_RELOC_16_PCREL_S2
:
4578 shift
= mips_opts
.micromips
? 1 : 2;
4579 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
4580 as_bad (_("branch to misaligned address (0x%lx)"),
4581 (unsigned long) address_expr
->X_add_number
);
4582 if (!mips_relax_branch
)
4584 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
4585 & ~((1 << (shift
+ 16)) - 1))
4586 as_bad (_("branch address range overflow (0x%lx)"),
4587 (unsigned long) address_expr
->X_add_number
);
4588 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
4598 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
4601 ip
->insn_opcode
|= value
& 0xffff;
4609 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
4611 /* There are a lot of optimizations we could do that we don't.
4612 In particular, we do not, in general, reorder instructions.
4613 If you use gcc with optimization, it will reorder
4614 instructions and generally do much more optimization then we
4615 do here; repeating all that work in the assembler would only
4616 benefit hand written assembly code, and does not seem worth
4618 int nops
= (mips_optimize
== 0
4619 ? nops_for_insn (0, history
, NULL
)
4620 : nops_for_insn_or_target (0, history
, ip
));
4624 unsigned long old_frag_offset
;
4627 old_frag
= frag_now
;
4628 old_frag_offset
= frag_now_fix ();
4630 for (i
= 0; i
< nops
; i
++)
4631 add_fixed_insn (NOP_INSN
);
4632 insert_into_history (0, nops
, NOP_INSN
);
4636 listing_prev_line ();
4637 /* We may be at the start of a variant frag. In case we
4638 are, make sure there is enough space for the frag
4639 after the frags created by listing_prev_line. The
4640 argument to frag_grow here must be at least as large
4641 as the argument to all other calls to frag_grow in
4642 this file. We don't have to worry about being in the
4643 middle of a variant frag, because the variants insert
4644 all needed nop instructions themselves. */
4648 mips_move_text_labels ();
4650 #ifndef NO_ECOFF_DEBUGGING
4651 if (ECOFF_DEBUGGING
)
4652 ecoff_fix_loc (old_frag
, old_frag_offset
);
4656 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
4660 /* Work out how many nops in prev_nop_frag are needed by IP,
4661 ignoring hazards generated by the first prev_nop_frag_since
4663 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
4664 gas_assert (nops
<= prev_nop_frag_holds
);
4666 /* Enforce NOPS as a minimum. */
4667 if (nops
> prev_nop_frag_required
)
4668 prev_nop_frag_required
= nops
;
4670 if (prev_nop_frag_holds
== prev_nop_frag_required
)
4672 /* Settle for the current number of nops. Update the history
4673 accordingly (for the benefit of any future .set reorder code). */
4674 prev_nop_frag
= NULL
;
4675 insert_into_history (prev_nop_frag_since
,
4676 prev_nop_frag_holds
, NOP_INSN
);
4680 /* Allow this instruction to replace one of the nops that was
4681 tentatively added to prev_nop_frag. */
4682 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
4683 prev_nop_frag_holds
--;
4684 prev_nop_frag_since
++;
4688 method
= get_append_method (ip
, address_expr
, reloc_type
);
4689 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
4691 dwarf2_emit_insn (0);
4692 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4693 so "move" the instruction address accordingly.
4695 Also, it doesn't seem appropriate for the assembler to reorder .loc
4696 entries. If this instruction is a branch that we are going to swap
4697 with the previous instruction, the two instructions should be
4698 treated as a unit, and the debug information for both instructions
4699 should refer to the start of the branch sequence. Using the
4700 current position is certainly wrong when swapping a 32-bit branch
4701 and a 16-bit delay slot, since the current position would then be
4702 in the middle of a branch. */
4703 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
4705 relax32
= (mips_relax_branch
4706 /* Don't try branch relaxation within .set nomacro, or within
4707 .set noat if we use $at for PIC computations. If it turns
4708 out that the branch was out-of-range, we'll get an error. */
4709 && !mips_opts
.warn_about_macros
4710 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
4711 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4712 as they have no complementing branches. */
4713 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
4715 if (!HAVE_CODE_COMPRESSION
4718 && *reloc_type
== BFD_RELOC_16_PCREL_S2
4719 && delayed_branch_p (ip
))
4721 relaxed_branch
= TRUE
;
4722 add_relaxed_insn (ip
, (relaxed_branch_length
4724 uncond_branch_p (ip
) ? -1
4725 : branch_likely_p (ip
) ? 1
4729 uncond_branch_p (ip
),
4730 branch_likely_p (ip
),
4731 pinfo
& INSN_WRITE_GPR_31
,
4733 address_expr
->X_add_symbol
,
4734 address_expr
->X_add_number
);
4735 *reloc_type
= BFD_RELOC_UNUSED
;
4737 else if (mips_opts
.micromips
4739 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
4740 || *reloc_type
> BFD_RELOC_UNUSED
)
4741 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
4742 /* Don't try branch relaxation when users specify
4743 16-bit/32-bit instructions. */
4744 && !forced_insn_length
)
4746 bfd_boolean relax16
= *reloc_type
> BFD_RELOC_UNUSED
;
4747 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
4748 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
4749 int compact
= compact_branch_p (ip
);
4750 int al
= pinfo
& INSN_WRITE_GPR_31
;
4753 gas_assert (address_expr
!= NULL
);
4754 gas_assert (!mips_relax
.sequence
);
4756 relaxed_branch
= TRUE
;
4757 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
4758 add_relaxed_insn (ip
, relax32
? length32
: 4, relax16
? 2 : 4,
4759 RELAX_MICROMIPS_ENCODE (type
, AT
, uncond
, compact
, al
,
4761 address_expr
->X_add_symbol
,
4762 address_expr
->X_add_number
);
4763 *reloc_type
= BFD_RELOC_UNUSED
;
4765 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
4767 /* We need to set up a variant frag. */
4768 gas_assert (address_expr
!= NULL
);
4769 add_relaxed_insn (ip
, 4, 0,
4771 (*reloc_type
- BFD_RELOC_UNUSED
,
4772 forced_insn_length
== 2, forced_insn_length
== 4,
4773 delayed_branch_p (&history
[0]),
4774 history
[0].mips16_absolute_jump_p
),
4775 make_expr_symbol (address_expr
), 0);
4777 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
4779 if (!delayed_branch_p (ip
))
4780 /* Make sure there is enough room to swap this instruction with
4781 a following jump instruction. */
4783 add_fixed_insn (ip
);
4787 if (mips_opts
.mips16
4788 && mips_opts
.noreorder
4789 && delayed_branch_p (&history
[0]))
4790 as_warn (_("extended instruction in delay slot"));
4792 if (mips_relax
.sequence
)
4794 /* If we've reached the end of this frag, turn it into a variant
4795 frag and record the information for the instructions we've
4797 if (frag_room () < 4)
4798 relax_close_frag ();
4799 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
4802 if (mips_relax
.sequence
!= 2)
4804 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
4805 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
4806 mips_macro_warning
.sizes
[0] += insn_length (ip
);
4807 mips_macro_warning
.insns
[0]++;
4809 if (mips_relax
.sequence
!= 1)
4811 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
4812 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
4813 mips_macro_warning
.sizes
[1] += insn_length (ip
);
4814 mips_macro_warning
.insns
[1]++;
4817 if (mips_opts
.mips16
)
4820 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
4822 add_fixed_insn (ip
);
4825 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
4827 bfd_reloc_code_real_type final_type
[3];
4828 reloc_howto_type
*howto0
;
4829 reloc_howto_type
*howto
;
4832 /* Perform any necessary conversion to microMIPS relocations
4833 and find out how many relocations there actually are. */
4834 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
4835 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
4837 /* In a compound relocation, it is the final (outermost)
4838 operator that determines the relocated field. */
4839 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
4844 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
4845 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
4846 bfd_get_reloc_size (howto
),
4848 howto0
&& howto0
->pc_relative
,
4851 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4852 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
4853 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
4855 /* These relocations can have an addend that won't fit in
4856 4 octets for 64bit assembly. */
4858 && ! howto
->partial_inplace
4859 && (reloc_type
[0] == BFD_RELOC_16
4860 || reloc_type
[0] == BFD_RELOC_32
4861 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
4862 || reloc_type
[0] == BFD_RELOC_GPREL16
4863 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
4864 || reloc_type
[0] == BFD_RELOC_GPREL32
4865 || reloc_type
[0] == BFD_RELOC_64
4866 || reloc_type
[0] == BFD_RELOC_CTOR
4867 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
4868 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
4869 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
4870 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
4871 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
4872 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
4873 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
4874 || hi16_reloc_p (reloc_type
[0])
4875 || lo16_reloc_p (reloc_type
[0])))
4876 ip
->fixp
[0]->fx_no_overflow
= 1;
4878 /* These relocations can have an addend that won't fit in 2 octets. */
4879 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4880 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
4881 ip
->fixp
[0]->fx_no_overflow
= 1;
4883 if (mips_relax
.sequence
)
4885 if (mips_relax
.first_fixup
== 0)
4886 mips_relax
.first_fixup
= ip
->fixp
[0];
4888 else if (reloc_needs_lo_p (*reloc_type
))
4890 struct mips_hi_fixup
*hi_fixup
;
4892 /* Reuse the last entry if it already has a matching %lo. */
4893 hi_fixup
= mips_hi_fixup_list
;
4895 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
4897 hi_fixup
= ((struct mips_hi_fixup
*)
4898 xmalloc (sizeof (struct mips_hi_fixup
)));
4899 hi_fixup
->next
= mips_hi_fixup_list
;
4900 mips_hi_fixup_list
= hi_fixup
;
4902 hi_fixup
->fixp
= ip
->fixp
[0];
4903 hi_fixup
->seg
= now_seg
;
4906 /* Add fixups for the second and third relocations, if given.
4907 Note that the ABI allows the second relocation to be
4908 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4909 moment we only use RSS_UNDEF, but we could add support
4910 for the others if it ever becomes necessary. */
4911 for (i
= 1; i
< 3; i
++)
4912 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
4914 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
4915 ip
->fixp
[0]->fx_size
, NULL
, 0,
4916 FALSE
, final_type
[i
]);
4918 /* Use fx_tcbit to mark compound relocs. */
4919 ip
->fixp
[0]->fx_tcbit
= 1;
4920 ip
->fixp
[i
]->fx_tcbit
= 1;
4925 /* Update the register mask information. */
4926 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
4927 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
4932 insert_into_history (0, 1, ip
);
4935 case APPEND_ADD_WITH_NOP
:
4937 struct mips_cl_insn
*nop
;
4939 insert_into_history (0, 1, ip
);
4940 nop
= get_delay_slot_nop (ip
);
4941 add_fixed_insn (nop
);
4942 insert_into_history (0, 1, nop
);
4943 if (mips_relax
.sequence
)
4944 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
4948 case APPEND_ADD_COMPACT
:
4949 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4950 gas_assert (mips_opts
.mips16
);
4951 ip
->insn_opcode
|= 0x0080;
4952 find_altered_mips16_opcode (ip
);
4954 insert_into_history (0, 1, ip
);
4959 struct mips_cl_insn delay
= history
[0];
4960 if (mips_opts
.mips16
)
4962 know (delay
.frag
== ip
->frag
);
4963 move_insn (ip
, delay
.frag
, delay
.where
);
4964 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
4966 else if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
4968 /* Add the delay slot instruction to the end of the
4969 current frag and shrink the fixed part of the
4970 original frag. If the branch occupies the tail of
4971 the latter, move it backwards to cover the gap. */
4972 delay
.frag
->fr_fix
-= branch_disp
;
4973 if (delay
.frag
== ip
->frag
)
4974 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
4975 add_fixed_insn (&delay
);
4979 move_insn (&delay
, ip
->frag
,
4980 ip
->where
- branch_disp
+ insn_length (ip
));
4981 move_insn (ip
, history
[0].frag
, history
[0].where
);
4985 insert_into_history (0, 1, &delay
);
4990 /* If we have just completed an unconditional branch, clear the history. */
4991 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
4992 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
4996 mips_no_prev_insn ();
4998 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
4999 history
[i
].cleared_p
= 1;
5002 /* We need to emit a label at the end of branch-likely macros. */
5003 if (emit_branch_likely_macro
)
5005 emit_branch_likely_macro
= FALSE
;
5006 micromips_add_label ();
5009 /* We just output an insn, so the next one doesn't have a label. */
5010 mips_clear_insn_labels ();
5013 /* Forget that there was any previous instruction or label.
5014 When BRANCH is true, the branch history is also flushed. */
5017 mips_no_prev_insn (void)
5019 prev_nop_frag
= NULL
;
5020 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
5021 mips_clear_insn_labels ();
5024 /* This function must be called before we emit something other than
5025 instructions. It is like mips_no_prev_insn except that it inserts
5026 any NOPS that might be needed by previous instructions. */
5029 mips_emit_delays (void)
5031 if (! mips_opts
.noreorder
)
5033 int nops
= nops_for_insn (0, history
, NULL
);
5037 add_fixed_insn (NOP_INSN
);
5038 mips_move_text_labels ();
5041 mips_no_prev_insn ();
5044 /* Start a (possibly nested) noreorder block. */
5047 start_noreorder (void)
5049 if (mips_opts
.noreorder
== 0)
5054 /* None of the instructions before the .set noreorder can be moved. */
5055 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
5056 history
[i
].fixed_p
= 1;
5058 /* Insert any nops that might be needed between the .set noreorder
5059 block and the previous instructions. We will later remove any
5060 nops that turn out not to be needed. */
5061 nops
= nops_for_insn (0, history
, NULL
);
5064 if (mips_optimize
!= 0)
5066 /* Record the frag which holds the nop instructions, so
5067 that we can remove them if we don't need them. */
5068 frag_grow (nops
* NOP_INSN_SIZE
);
5069 prev_nop_frag
= frag_now
;
5070 prev_nop_frag_holds
= nops
;
5071 prev_nop_frag_required
= 0;
5072 prev_nop_frag_since
= 0;
5075 for (; nops
> 0; --nops
)
5076 add_fixed_insn (NOP_INSN
);
5078 /* Move on to a new frag, so that it is safe to simply
5079 decrease the size of prev_nop_frag. */
5080 frag_wane (frag_now
);
5082 mips_move_text_labels ();
5084 mips_mark_labels ();
5085 mips_clear_insn_labels ();
5087 mips_opts
.noreorder
++;
5088 mips_any_noreorder
= 1;
5091 /* End a nested noreorder block. */
5094 end_noreorder (void)
5096 mips_opts
.noreorder
--;
5097 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
5099 /* Commit to inserting prev_nop_frag_required nops and go back to
5100 handling nop insertion the .set reorder way. */
5101 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
5103 insert_into_history (prev_nop_frag_since
,
5104 prev_nop_frag_required
, NOP_INSN
);
5105 prev_nop_frag
= NULL
;
5109 /* Set up global variables for the start of a new macro. */
5114 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
5115 memset (&mips_macro_warning
.first_insn_sizes
, 0,
5116 sizeof (mips_macro_warning
.first_insn_sizes
));
5117 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
5118 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
5119 && delayed_branch_p (&history
[0]));
5120 switch (history
[0].insn_mo
->pinfo2
5121 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
5123 case INSN2_BRANCH_DELAY_32BIT
:
5124 mips_macro_warning
.delay_slot_length
= 4;
5126 case INSN2_BRANCH_DELAY_16BIT
:
5127 mips_macro_warning
.delay_slot_length
= 2;
5130 mips_macro_warning
.delay_slot_length
= 0;
5133 mips_macro_warning
.first_frag
= NULL
;
5136 /* Given that a macro is longer than one instruction or of the wrong size,
5137 return the appropriate warning for it. Return null if no warning is
5138 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5139 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5140 and RELAX_NOMACRO. */
5143 macro_warning (relax_substateT subtype
)
5145 if (subtype
& RELAX_DELAY_SLOT
)
5146 return _("Macro instruction expanded into multiple instructions"
5147 " in a branch delay slot");
5148 else if (subtype
& RELAX_NOMACRO
)
5149 return _("Macro instruction expanded into multiple instructions");
5150 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
5151 | RELAX_DELAY_SLOT_SIZE_SECOND
))
5152 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
5153 ? _("Macro instruction expanded into a wrong size instruction"
5154 " in a 16-bit branch delay slot")
5155 : _("Macro instruction expanded into a wrong size instruction"
5156 " in a 32-bit branch delay slot"));
5161 /* Finish up a macro. Emit warnings as appropriate. */
5166 /* Relaxation warning flags. */
5167 relax_substateT subtype
= 0;
5169 /* Check delay slot size requirements. */
5170 if (mips_macro_warning
.delay_slot_length
== 2)
5171 subtype
|= RELAX_DELAY_SLOT_16BIT
;
5172 if (mips_macro_warning
.delay_slot_length
!= 0)
5174 if (mips_macro_warning
.delay_slot_length
5175 != mips_macro_warning
.first_insn_sizes
[0])
5176 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
5177 if (mips_macro_warning
.delay_slot_length
5178 != mips_macro_warning
.first_insn_sizes
[1])
5179 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
5182 /* Check instruction count requirements. */
5183 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
5185 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
5186 subtype
|= RELAX_SECOND_LONGER
;
5187 if (mips_opts
.warn_about_macros
)
5188 subtype
|= RELAX_NOMACRO
;
5189 if (mips_macro_warning
.delay_slot_p
)
5190 subtype
|= RELAX_DELAY_SLOT
;
5193 /* If both alternatives fail to fill a delay slot correctly,
5194 emit the warning now. */
5195 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
5196 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
5201 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
5202 | RELAX_DELAY_SLOT_SIZE_FIRST
5203 | RELAX_DELAY_SLOT_SIZE_SECOND
);
5204 msg
= macro_warning (s
);
5206 as_warn ("%s", msg
);
5210 /* If both implementations are longer than 1 instruction, then emit the
5212 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
5217 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
5218 msg
= macro_warning (s
);
5220 as_warn ("%s", msg
);
5224 /* If any flags still set, then one implementation might need a warning
5225 and the other either will need one of a different kind or none at all.
5226 Pass any remaining flags over to relaxation. */
5227 if (mips_macro_warning
.first_frag
!= NULL
)
5228 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
5231 /* Instruction operand formats used in macros that vary between
5232 standard MIPS and microMIPS code. */
5234 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
5235 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
5236 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
5237 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
5238 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
5239 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
5240 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
5241 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
5243 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5244 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5245 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5246 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5247 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5248 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5249 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5250 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5252 /* Read a macro's relocation codes from *ARGS and store them in *R.
5253 The first argument in *ARGS will be either the code for a single
5254 relocation or -1 followed by the three codes that make up a
5255 composite relocation. */
5258 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
5262 next
= va_arg (*args
, int);
5264 r
[0] = (bfd_reloc_code_real_type
) next
;
5266 for (i
= 0; i
< 3; i
++)
5267 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
5270 /* Build an instruction created by a macro expansion. This is passed
5271 a pointer to the count of instructions created so far, an
5272 expression, the name of the instruction to build, an operand format
5273 string, and corresponding arguments. */
5276 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
5278 const struct mips_opcode
*mo
= NULL
;
5279 bfd_reloc_code_real_type r
[3];
5280 const struct mips_opcode
*amo
;
5281 struct hash_control
*hash
;
5282 struct mips_cl_insn insn
;
5285 va_start (args
, fmt
);
5287 if (mips_opts
.mips16
)
5289 mips16_macro_build (ep
, name
, fmt
, &args
);
5294 r
[0] = BFD_RELOC_UNUSED
;
5295 r
[1] = BFD_RELOC_UNUSED
;
5296 r
[2] = BFD_RELOC_UNUSED
;
5297 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
5298 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
5300 gas_assert (strcmp (name
, amo
->name
) == 0);
5304 /* Search until we get a match for NAME. It is assumed here that
5305 macros will never generate MDMX, MIPS-3D, or MT instructions.
5306 We try to match an instruction that fulfils the branch delay
5307 slot instruction length requirement (if any) of the previous
5308 instruction. While doing this we record the first instruction
5309 seen that matches all the other conditions and use it anyway
5310 if the requirement cannot be met; we will issue an appropriate
5311 warning later on. */
5312 if (strcmp (fmt
, amo
->args
) == 0
5313 && amo
->pinfo
!= INSN_MACRO
5314 && is_opcode_valid (amo
)
5315 && is_size_valid (amo
))
5317 if (is_delay_slot_valid (amo
))
5327 gas_assert (amo
->name
);
5329 while (strcmp (name
, amo
->name
) == 0);
5332 create_insn (&insn
, mo
);
5350 INSERT_OPERAND (mips_opts
.micromips
,
5351 EXTLSB
, insn
, va_arg (args
, int));
5356 /* Note that in the macro case, these arguments are already
5357 in MSB form. (When handling the instruction in the
5358 non-macro case, these arguments are sizes from which
5359 MSB values must be calculated.) */
5360 INSERT_OPERAND (mips_opts
.micromips
,
5361 INSMSB
, insn
, va_arg (args
, int));
5365 gas_assert (!mips_opts
.micromips
);
5366 INSERT_OPERAND (0, CODE10
, insn
, va_arg (args
, int));
5372 /* Note that in the macro case, these arguments are already
5373 in MSBD form. (When handling the instruction in the
5374 non-macro case, these arguments are sizes from which
5375 MSBD values must be calculated.) */
5376 INSERT_OPERAND (mips_opts
.micromips
,
5377 EXTMSBD
, insn
, va_arg (args
, int));
5381 gas_assert (!mips_opts
.micromips
);
5382 INSERT_OPERAND (0, SEQI
, insn
, va_arg (args
, int));
5386 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, insn
, va_arg (args
, int));
5395 INSERT_OPERAND (mips_opts
.micromips
, BP
, insn
, va_arg (args
, int));
5399 gas_assert (mips_opts
.micromips
);
5403 INSERT_OPERAND (mips_opts
.micromips
, RT
, insn
, va_arg (args
, int));
5407 INSERT_OPERAND (mips_opts
.micromips
, CODE
, insn
, va_arg (args
, int));
5411 gas_assert (!mips_opts
.micromips
);
5413 INSERT_OPERAND (mips_opts
.micromips
, FT
, insn
, va_arg (args
, int));
5417 if (mips_opts
.micromips
)
5418 INSERT_OPERAND (1, RS
, insn
, va_arg (args
, int));
5420 INSERT_OPERAND (0, RD
, insn
, va_arg (args
, int));
5424 gas_assert (!mips_opts
.micromips
);
5426 INSERT_OPERAND (mips_opts
.micromips
, RD
, insn
, va_arg (args
, int));
5430 gas_assert (!mips_opts
.micromips
);
5432 int tmp
= va_arg (args
, int);
5434 INSERT_OPERAND (0, RT
, insn
, tmp
);
5435 INSERT_OPERAND (0, RD
, insn
, tmp
);
5441 gas_assert (!mips_opts
.micromips
);
5442 INSERT_OPERAND (0, FS
, insn
, va_arg (args
, int));
5449 INSERT_OPERAND (mips_opts
.micromips
,
5450 SHAMT
, insn
, va_arg (args
, int));
5454 gas_assert (!mips_opts
.micromips
);
5455 INSERT_OPERAND (0, FD
, insn
, va_arg (args
, int));
5459 gas_assert (!mips_opts
.micromips
);
5460 INSERT_OPERAND (0, CODE20
, insn
, va_arg (args
, int));
5464 gas_assert (!mips_opts
.micromips
);
5465 INSERT_OPERAND (0, CODE19
, insn
, va_arg (args
, int));
5469 gas_assert (!mips_opts
.micromips
);
5470 INSERT_OPERAND (0, CODE2
, insn
, va_arg (args
, int));
5477 INSERT_OPERAND (mips_opts
.micromips
, RS
, insn
, va_arg (args
, int));
5482 macro_read_relocs (&args
, r
);
5483 gas_assert (*r
== BFD_RELOC_GPREL16
5484 || *r
== BFD_RELOC_MIPS_HIGHER
5485 || *r
== BFD_RELOC_HI16_S
5486 || *r
== BFD_RELOC_LO16
5487 || *r
== BFD_RELOC_MIPS_GOT_OFST
);
5491 macro_read_relocs (&args
, r
);
5495 macro_read_relocs (&args
, r
);
5496 gas_assert (ep
!= NULL
5497 && (ep
->X_op
== O_constant
5498 || (ep
->X_op
== O_symbol
5499 && (*r
== BFD_RELOC_MIPS_HIGHEST
5500 || *r
== BFD_RELOC_HI16_S
5501 || *r
== BFD_RELOC_HI16
5502 || *r
== BFD_RELOC_GPREL16
5503 || *r
== BFD_RELOC_MIPS_GOT_HI16
5504 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
5508 gas_assert (ep
!= NULL
);
5511 * This allows macro() to pass an immediate expression for
5512 * creating short branches without creating a symbol.
5514 * We don't allow branch relaxation for these branches, as
5515 * they should only appear in ".set nomacro" anyway.
5517 if (ep
->X_op
== O_constant
)
5519 /* For microMIPS we always use relocations for branches.
5520 So we should not resolve immediate values. */
5521 gas_assert (!mips_opts
.micromips
);
5523 if ((ep
->X_add_number
& 3) != 0)
5524 as_bad (_("branch to misaligned address (0x%lx)"),
5525 (unsigned long) ep
->X_add_number
);
5526 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
5527 as_bad (_("branch address range overflow (0x%lx)"),
5528 (unsigned long) ep
->X_add_number
);
5529 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
5533 *r
= BFD_RELOC_16_PCREL_S2
;
5537 gas_assert (ep
!= NULL
);
5538 *r
= BFD_RELOC_MIPS_JMP
;
5542 gas_assert (!mips_opts
.micromips
);
5543 INSERT_OPERAND (0, COPZ
, insn
, va_arg (args
, unsigned long));
5547 INSERT_OPERAND (mips_opts
.micromips
,
5548 CACHE
, insn
, va_arg (args
, unsigned long));
5552 gas_assert (mips_opts
.micromips
);
5553 INSERT_OPERAND (1, TRAP
, insn
, va_arg (args
, int));
5557 gas_assert (mips_opts
.micromips
);
5558 INSERT_OPERAND (1, OFFSET10
, insn
, va_arg (args
, int));
5562 INSERT_OPERAND (mips_opts
.micromips
,
5563 3BITPOS
, insn
, va_arg (args
, unsigned int));
5567 INSERT_OPERAND (mips_opts
.micromips
,
5568 OFFSET12
, insn
, va_arg (args
, unsigned long));
5572 gas_assert (mips_opts
.micromips
);
5573 INSERT_OPERAND (1, BCC
, insn
, va_arg (args
, int));
5576 case 'm': /* Opcode extension character. */
5577 gas_assert (mips_opts
.micromips
);
5581 INSERT_OPERAND (1, MJ
, insn
, va_arg (args
, int));
5585 INSERT_OPERAND (1, MP
, insn
, va_arg (args
, int));
5589 INSERT_OPERAND (1, IMMF
, insn
, va_arg (args
, int));
5603 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5605 append_insn (&insn
, ep
, r
, TRUE
);
5609 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
5612 struct mips_opcode
*mo
;
5613 struct mips_cl_insn insn
;
5614 bfd_reloc_code_real_type r
[3]
5615 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
5617 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
5619 gas_assert (strcmp (name
, mo
->name
) == 0);
5621 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
5624 gas_assert (mo
->name
);
5625 gas_assert (strcmp (name
, mo
->name
) == 0);
5628 create_insn (&insn
, mo
);
5646 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
5651 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
5655 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
5659 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
5669 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
5676 regno
= va_arg (*args
, int);
5677 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
5678 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
5701 gas_assert (ep
!= NULL
);
5703 if (ep
->X_op
!= O_constant
)
5704 *r
= (int) BFD_RELOC_UNUSED
+ c
;
5705 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
5707 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
5709 *r
= BFD_RELOC_UNUSED
;
5715 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
5722 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
5724 append_insn (&insn
, ep
, r
, TRUE
);
5728 * Sign-extend 32-bit mode constants that have bit 31 set and all
5729 * higher bits unset.
5732 normalize_constant_expr (expressionS
*ex
)
5734 if (ex
->X_op
== O_constant
5735 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5736 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5741 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5742 * all higher bits unset.
5745 normalize_address_expr (expressionS
*ex
)
5747 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
5748 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
5749 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
5750 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
5755 * Generate a "jalr" instruction with a relocation hint to the called
5756 * function. This occurs in NewABI PIC code.
5759 macro_build_jalr (expressionS
*ep
, int cprestore
)
5761 static const bfd_reloc_code_real_type jalr_relocs
[2]
5762 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
5763 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
5767 if (MIPS_JALR_HINT_P (ep
))
5772 if (mips_opts
.micromips
)
5774 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
5775 ? "jalr" : "jalrs");
5776 if (MIPS_JALR_HINT_P (ep
)
5778 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
5779 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
5781 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
5784 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
5785 if (MIPS_JALR_HINT_P (ep
))
5786 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
5790 * Generate a "lui" instruction.
5793 macro_build_lui (expressionS
*ep
, int regnum
)
5795 gas_assert (! mips_opts
.mips16
);
5797 if (ep
->X_op
!= O_constant
)
5799 gas_assert (ep
->X_op
== O_symbol
);
5800 /* _gp_disp is a special case, used from s_cpload.
5801 __gnu_local_gp is used if mips_no_shared. */
5802 gas_assert (mips_pic
== NO_PIC
5804 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
5805 || (! mips_in_shared
5806 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
5807 "__gnu_local_gp") == 0));
5810 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
5813 /* Generate a sequence of instructions to do a load or store from a constant
5814 offset off of a base register (breg) into/from a target register (treg),
5815 using AT if necessary. */
5817 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
5818 int treg
, int breg
, int dbl
)
5820 gas_assert (ep
->X_op
== O_constant
);
5822 /* Sign-extending 32-bit constants makes their handling easier. */
5824 normalize_constant_expr (ep
);
5826 /* Right now, this routine can only handle signed 32-bit constants. */
5827 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
5828 as_warn (_("operand overflow"));
5830 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
5832 /* Signed 16-bit offset will fit in the op. Easy! */
5833 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
5837 /* 32-bit offset, need multiple instructions and AT, like:
5838 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5839 addu $tempreg,$tempreg,$breg
5840 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5841 to handle the complete offset. */
5842 macro_build_lui (ep
, AT
);
5843 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
5844 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
5847 as_bad (_("Macro used $at after \".set noat\""));
5852 * Generates code to set the $at register to true (one)
5853 * if reg is less than the immediate expression.
5856 set_at (int reg
, int unsignedp
)
5858 if (imm_expr
.X_op
== O_constant
5859 && imm_expr
.X_add_number
>= -0x8000
5860 && imm_expr
.X_add_number
< 0x8000)
5861 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
5862 AT
, reg
, BFD_RELOC_LO16
);
5865 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
5866 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
5870 /* Warn if an expression is not a constant. */
5873 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
5875 if (ex
->X_op
== O_big
)
5876 as_bad (_("unsupported large constant"));
5877 else if (ex
->X_op
!= O_constant
)
5878 as_bad (_("Instruction %s requires absolute expression"),
5881 if (HAVE_32BIT_GPRS
)
5882 normalize_constant_expr (ex
);
5885 /* Count the leading zeroes by performing a binary chop. This is a
5886 bulky bit of source, but performance is a LOT better for the
5887 majority of values than a simple loop to count the bits:
5888 for (lcnt = 0; (lcnt < 32); lcnt++)
5889 if ((v) & (1 << (31 - lcnt)))
5891 However it is not code size friendly, and the gain will drop a bit
5892 on certain cached systems.
5894 #define COUNT_TOP_ZEROES(v) \
5895 (((v) & ~0xffff) == 0 \
5896 ? ((v) & ~0xff) == 0 \
5897 ? ((v) & ~0xf) == 0 \
5898 ? ((v) & ~0x3) == 0 \
5899 ? ((v) & ~0x1) == 0 \
5904 : ((v) & ~0x7) == 0 \
5907 : ((v) & ~0x3f) == 0 \
5908 ? ((v) & ~0x1f) == 0 \
5911 : ((v) & ~0x7f) == 0 \
5914 : ((v) & ~0xfff) == 0 \
5915 ? ((v) & ~0x3ff) == 0 \
5916 ? ((v) & ~0x1ff) == 0 \
5919 : ((v) & ~0x7ff) == 0 \
5922 : ((v) & ~0x3fff) == 0 \
5923 ? ((v) & ~0x1fff) == 0 \
5926 : ((v) & ~0x7fff) == 0 \
5929 : ((v) & ~0xffffff) == 0 \
5930 ? ((v) & ~0xfffff) == 0 \
5931 ? ((v) & ~0x3ffff) == 0 \
5932 ? ((v) & ~0x1ffff) == 0 \
5935 : ((v) & ~0x7ffff) == 0 \
5938 : ((v) & ~0x3fffff) == 0 \
5939 ? ((v) & ~0x1fffff) == 0 \
5942 : ((v) & ~0x7fffff) == 0 \
5945 : ((v) & ~0xfffffff) == 0 \
5946 ? ((v) & ~0x3ffffff) == 0 \
5947 ? ((v) & ~0x1ffffff) == 0 \
5950 : ((v) & ~0x7ffffff) == 0 \
5953 : ((v) & ~0x3fffffff) == 0 \
5954 ? ((v) & ~0x1fffffff) == 0 \
5957 : ((v) & ~0x7fffffff) == 0 \
5962 * This routine generates the least number of instructions necessary to load
5963 * an absolute expression value into a register.
5966 load_register (int reg
, expressionS
*ep
, int dbl
)
5969 expressionS hi32
, lo32
;
5971 if (ep
->X_op
!= O_big
)
5973 gas_assert (ep
->X_op
== O_constant
);
5975 /* Sign-extending 32-bit constants makes their handling easier. */
5977 normalize_constant_expr (ep
);
5979 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
5981 /* We can handle 16 bit signed values with an addiu to
5982 $zero. No need to ever use daddiu here, since $zero and
5983 the result are always correct in 32 bit mode. */
5984 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
5987 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
5989 /* We can handle 16 bit unsigned values with an ori to
5991 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
5994 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
5996 /* 32 bit values require an lui. */
5997 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
5998 if ((ep
->X_add_number
& 0xffff) != 0)
5999 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6004 /* The value is larger than 32 bits. */
6006 if (!dbl
|| HAVE_32BIT_GPRS
)
6010 sprintf_vma (value
, ep
->X_add_number
);
6011 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6012 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6016 if (ep
->X_op
!= O_big
)
6019 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6020 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
6021 hi32
.X_add_number
&= 0xffffffff;
6023 lo32
.X_add_number
&= 0xffffffff;
6027 gas_assert (ep
->X_add_number
> 2);
6028 if (ep
->X_add_number
== 3)
6029 generic_bignum
[3] = 0;
6030 else if (ep
->X_add_number
> 4)
6031 as_bad (_("Number larger than 64 bits"));
6032 lo32
.X_op
= O_constant
;
6033 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
6034 hi32
.X_op
= O_constant
;
6035 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
6038 if (hi32
.X_add_number
== 0)
6043 unsigned long hi
, lo
;
6045 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
6047 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
6049 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6052 if (lo32
.X_add_number
& 0x80000000)
6054 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6055 if (lo32
.X_add_number
& 0xffff)
6056 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
6061 /* Check for 16bit shifted constant. We know that hi32 is
6062 non-zero, so start the mask on the first bit of the hi32
6067 unsigned long himask
, lomask
;
6071 himask
= 0xffff >> (32 - shift
);
6072 lomask
= (0xffff << shift
) & 0xffffffff;
6076 himask
= 0xffff << (shift
- 32);
6079 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
6080 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
6084 tmp
.X_op
= O_constant
;
6086 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
6087 | (lo32
.X_add_number
>> shift
));
6089 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
6090 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
6091 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6092 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6097 while (shift
<= (64 - 16));
6099 /* Find the bit number of the lowest one bit, and store the
6100 shifted value in hi/lo. */
6101 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
6102 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
6106 while ((lo
& 1) == 0)
6111 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
6117 while ((hi
& 1) == 0)
6126 /* Optimize if the shifted value is a (power of 2) - 1. */
6127 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
6128 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
6130 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
6135 /* This instruction will set the register to be all
6137 tmp
.X_op
= O_constant
;
6138 tmp
.X_add_number
= (offsetT
) -1;
6139 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
6143 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
6144 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
6146 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
6147 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
6152 /* Sign extend hi32 before calling load_register, because we can
6153 generally get better code when we load a sign extended value. */
6154 if ((hi32
.X_add_number
& 0x80000000) != 0)
6155 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
6156 load_register (reg
, &hi32
, 0);
6159 if ((lo32
.X_add_number
& 0xffff0000) == 0)
6163 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
6171 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
6173 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
6174 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
6180 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
6184 mid16
.X_add_number
>>= 16;
6185 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6186 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6189 if ((lo32
.X_add_number
& 0xffff) != 0)
6190 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
6194 load_delay_nop (void)
6196 if (!gpr_interlocks
)
6197 macro_build (NULL
, "nop", "");
6200 /* Load an address into a register. */
6203 load_address (int reg
, expressionS
*ep
, int *used_at
)
6205 if (ep
->X_op
!= O_constant
6206 && ep
->X_op
!= O_symbol
)
6208 as_bad (_("expression too complex"));
6209 ep
->X_op
= O_constant
;
6212 if (ep
->X_op
== O_constant
)
6214 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
6218 if (mips_pic
== NO_PIC
)
6220 /* If this is a reference to a GP relative symbol, we want
6221 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6223 lui $reg,<sym> (BFD_RELOC_HI16_S)
6224 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6225 If we have an addend, we always use the latter form.
6227 With 64bit address space and a usable $at we want
6228 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6229 lui $at,<sym> (BFD_RELOC_HI16_S)
6230 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6231 daddiu $at,<sym> (BFD_RELOC_LO16)
6235 If $at is already in use, we use a path which is suboptimal
6236 on superscalar processors.
6237 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6238 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6240 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6242 daddiu $reg,<sym> (BFD_RELOC_LO16)
6244 For GP relative symbols in 64bit address space we can use
6245 the same sequence as in 32bit address space. */
6246 if (HAVE_64BIT_SYMBOLS
)
6248 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6249 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6251 relax_start (ep
->X_add_symbol
);
6252 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6253 mips_gp_register
, BFD_RELOC_GPREL16
);
6257 if (*used_at
== 0 && mips_opts
.at
)
6259 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6260 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
6261 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6262 BFD_RELOC_MIPS_HIGHER
);
6263 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
6264 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
6265 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
6270 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
6271 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
6272 BFD_RELOC_MIPS_HIGHER
);
6273 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6274 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
6275 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
6276 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
6279 if (mips_relax
.sequence
)
6284 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
6285 && !nopic_need_relax (ep
->X_add_symbol
, 1))
6287 relax_start (ep
->X_add_symbol
);
6288 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
6289 mips_gp_register
, BFD_RELOC_GPREL16
);
6292 macro_build_lui (ep
, reg
);
6293 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
6294 reg
, reg
, BFD_RELOC_LO16
);
6295 if (mips_relax
.sequence
)
6299 else if (!mips_big_got
)
6303 /* If this is a reference to an external symbol, we want
6304 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6306 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6308 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6309 If there is a constant, it must be added in after.
6311 If we have NewABI, we want
6312 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6313 unless we're referencing a global symbol with a non-zero
6314 offset, in which case cst must be added separately. */
6317 if (ep
->X_add_number
)
6319 ex
.X_add_number
= ep
->X_add_number
;
6320 ep
->X_add_number
= 0;
6321 relax_start (ep
->X_add_symbol
);
6322 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6323 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6324 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6325 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6326 ex
.X_op
= O_constant
;
6327 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6328 reg
, reg
, BFD_RELOC_LO16
);
6329 ep
->X_add_number
= ex
.X_add_number
;
6332 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6333 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
6334 if (mips_relax
.sequence
)
6339 ex
.X_add_number
= ep
->X_add_number
;
6340 ep
->X_add_number
= 0;
6341 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6342 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6344 relax_start (ep
->X_add_symbol
);
6346 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6350 if (ex
.X_add_number
!= 0)
6352 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6353 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6354 ex
.X_op
= O_constant
;
6355 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
6356 reg
, reg
, BFD_RELOC_LO16
);
6360 else if (mips_big_got
)
6364 /* This is the large GOT case. If this is a reference to an
6365 external symbol, we want
6366 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6368 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6370 Otherwise, for a reference to a local symbol in old ABI, we want
6371 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6373 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6374 If there is a constant, it must be added in after.
6376 In the NewABI, for local symbols, with or without offsets, we want:
6377 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6378 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6382 ex
.X_add_number
= ep
->X_add_number
;
6383 ep
->X_add_number
= 0;
6384 relax_start (ep
->X_add_symbol
);
6385 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6386 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6387 reg
, reg
, mips_gp_register
);
6388 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6389 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6390 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6391 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6392 else if (ex
.X_add_number
)
6394 ex
.X_op
= O_constant
;
6395 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6399 ep
->X_add_number
= ex
.X_add_number
;
6401 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6402 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6403 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6404 BFD_RELOC_MIPS_GOT_OFST
);
6409 ex
.X_add_number
= ep
->X_add_number
;
6410 ep
->X_add_number
= 0;
6411 relax_start (ep
->X_add_symbol
);
6412 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
6413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6414 reg
, reg
, mips_gp_register
);
6415 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
6416 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
6418 if (reg_needs_delay (mips_gp_register
))
6420 /* We need a nop before loading from $gp. This special
6421 check is required because the lui which starts the main
6422 instruction stream does not refer to $gp, and so will not
6423 insert the nop which may be required. */
6424 macro_build (NULL
, "nop", "");
6426 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
6427 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6429 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6433 if (ex
.X_add_number
!= 0)
6435 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
6436 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6437 ex
.X_op
= O_constant
;
6438 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
6446 if (!mips_opts
.at
&& *used_at
== 1)
6447 as_bad (_("Macro used $at after \".set noat\""));
6450 /* Move the contents of register SOURCE into register DEST. */
6453 move_register (int dest
, int source
)
6455 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6456 instruction specifically requires a 32-bit one. */
6457 if (mips_opts
.micromips
6458 && !mips_opts
.insn32
6459 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
6460 macro_build (NULL
, "move", "mp,mj", dest
, source
);
6462 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
6466 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6467 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6468 The two alternatives are:
6470 Global symbol Local sybmol
6471 ------------- ------------
6472 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6474 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6476 load_got_offset emits the first instruction and add_got_offset
6477 emits the second for a 16-bit offset or add_got_offset_hilo emits
6478 a sequence to add a 32-bit offset using a scratch register. */
6481 load_got_offset (int dest
, expressionS
*local
)
6486 global
.X_add_number
= 0;
6488 relax_start (local
->X_add_symbol
);
6489 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6490 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6492 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
6493 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6498 add_got_offset (int dest
, expressionS
*local
)
6502 global
.X_op
= O_constant
;
6503 global
.X_op_symbol
= NULL
;
6504 global
.X_add_symbol
= NULL
;
6505 global
.X_add_number
= local
->X_add_number
;
6507 relax_start (local
->X_add_symbol
);
6508 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
6509 dest
, dest
, BFD_RELOC_LO16
);
6511 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
6516 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
6519 int hold_mips_optimize
;
6521 global
.X_op
= O_constant
;
6522 global
.X_op_symbol
= NULL
;
6523 global
.X_add_symbol
= NULL
;
6524 global
.X_add_number
= local
->X_add_number
;
6526 relax_start (local
->X_add_symbol
);
6527 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
6529 /* Set mips_optimize around the lui instruction to avoid
6530 inserting an unnecessary nop after the lw. */
6531 hold_mips_optimize
= mips_optimize
;
6533 macro_build_lui (&global
, tmp
);
6534 mips_optimize
= hold_mips_optimize
;
6535 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
6538 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
6541 /* Emit a sequence of instructions to emulate a branch likely operation.
6542 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6543 is its complementing branch with the original condition negated.
6544 CALL is set if the original branch specified the link operation.
6545 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6547 Code like this is produced in the noreorder mode:
6552 delay slot (executed only if branch taken)
6560 delay slot (executed only if branch taken)
6563 In the reorder mode the delay slot would be filled with a nop anyway,
6564 so code produced is simply:
6569 This function is used when producing code for the microMIPS ASE that
6570 does not implement branch likely instructions in hardware. */
6573 macro_build_branch_likely (const char *br
, const char *brneg
,
6574 int call
, expressionS
*ep
, const char *fmt
,
6575 unsigned int sreg
, unsigned int treg
)
6577 int noreorder
= mips_opts
.noreorder
;
6580 gas_assert (mips_opts
.micromips
);
6584 micromips_label_expr (&expr1
);
6585 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
6586 macro_build (NULL
, "nop", "");
6587 macro_build (ep
, call
? "bal" : "b", "p");
6589 /* Set to true so that append_insn adds a label. */
6590 emit_branch_likely_macro
= TRUE
;
6594 macro_build (ep
, br
, fmt
, sreg
, treg
);
6595 macro_build (NULL
, "nop", "");
6600 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6601 the condition code tested. EP specifies the branch target. */
6604 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
6631 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
6634 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6635 the register tested. EP specifies the branch target. */
6638 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
6640 const char *brneg
= NULL
;
6650 br
= mips_opts
.micromips
? "bgez" : "bgezl";
6654 gas_assert (mips_opts
.micromips
);
6655 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
6663 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
6670 br
= mips_opts
.micromips
? "blez" : "blezl";
6677 br
= mips_opts
.micromips
? "bltz" : "bltzl";
6681 gas_assert (mips_opts
.micromips
);
6682 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
6689 if (mips_opts
.micromips
&& brneg
)
6690 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
6692 macro_build (ep
, br
, "s,p", sreg
);
6695 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6696 TREG as the registers tested. EP specifies the branch target. */
6699 macro_build_branch_rsrt (int type
, expressionS
*ep
,
6700 unsigned int sreg
, unsigned int treg
)
6702 const char *brneg
= NULL
;
6714 br
= mips_opts
.micromips
? "beq" : "beql";
6723 br
= mips_opts
.micromips
? "bne" : "bnel";
6729 if (mips_opts
.micromips
&& brneg
)
6730 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
6732 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
6737 * This routine implements the seemingly endless macro or synthesized
6738 * instructions and addressing modes in the mips assembly language. Many
6739 * of these macros are simple and are similar to each other. These could
6740 * probably be handled by some kind of table or grammar approach instead of
6741 * this verbose method. Others are not simple macros but are more like
6742 * optimizing code generation.
6743 * One interesting optimization is when several store macros appear
6744 * consecutively that would load AT with the upper half of the same address.
6745 * The ensuing load upper instructions are ommited. This implies some kind
6746 * of global optimization. We currently only optimize within a single macro.
6747 * For many of the load and store macros if the address is specified as a
6748 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6749 * first load register 'at' with zero and use it as the base register. The
6750 * mips assembler simply uses register $zero. Just one tiny optimization
6754 macro (struct mips_cl_insn
*ip
, char *str
)
6756 unsigned int treg
, sreg
, dreg
, breg
;
6757 unsigned int tempreg
;
6760 expressionS label_expr
;
6777 bfd_reloc_code_real_type r
;
6778 int hold_mips_optimize
;
6780 gas_assert (! mips_opts
.mips16
);
6782 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
6783 dreg
= EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
6784 sreg
= breg
= EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
6785 mask
= ip
->insn_mo
->mask
;
6787 label_expr
.X_op
= O_constant
;
6788 label_expr
.X_op_symbol
= NULL
;
6789 label_expr
.X_add_symbol
= NULL
;
6790 label_expr
.X_add_number
= 0;
6792 expr1
.X_op
= O_constant
;
6793 expr1
.X_op_symbol
= NULL
;
6794 expr1
.X_add_symbol
= NULL
;
6795 expr1
.X_add_number
= 1;
6810 if (mips_opts
.micromips
)
6811 micromips_label_expr (&label_expr
);
6813 label_expr
.X_add_number
= 8;
6814 macro_build (&label_expr
, "bgez", "s,p", sreg
);
6816 macro_build (NULL
, "nop", "");
6818 move_register (dreg
, sreg
);
6819 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
6820 if (mips_opts
.micromips
)
6821 micromips_add_label ();
6838 if (!mips_opts
.micromips
)
6840 if (imm_expr
.X_op
== O_constant
6841 && imm_expr
.X_add_number
>= -0x200
6842 && imm_expr
.X_add_number
< 0x200)
6844 macro_build (NULL
, s
, "t,r,.", treg
, sreg
, imm_expr
.X_add_number
);
6853 if (imm_expr
.X_op
== O_constant
6854 && imm_expr
.X_add_number
>= -0x8000
6855 && imm_expr
.X_add_number
< 0x8000)
6857 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
6862 load_register (AT
, &imm_expr
, dbl
);
6863 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6882 if (imm_expr
.X_op
== O_constant
6883 && imm_expr
.X_add_number
>= 0
6884 && imm_expr
.X_add_number
< 0x10000)
6886 if (mask
!= M_NOR_I
)
6887 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
6890 macro_build (&imm_expr
, "ori", "t,r,i",
6891 treg
, sreg
, BFD_RELOC_LO16
);
6892 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
6898 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
6899 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
6903 switch (imm_expr
.X_add_number
)
6906 macro_build (NULL
, "nop", "");
6909 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
6913 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
6914 (int) imm_expr
.X_add_number
);
6917 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6918 (unsigned long) imm_expr
.X_add_number
);
6927 gas_assert (mips_opts
.micromips
);
6928 macro_build_branch_ccl (mask
, &offset_expr
,
6929 EXTRACT_OPERAND (1, BCC
, *ip
));
6936 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6942 load_register (treg
, &imm_expr
, HAVE_64BIT_GPRS
);
6947 macro_build_branch_rsrt (mask
, &offset_expr
, sreg
, treg
);
6954 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, sreg
);
6956 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, treg
);
6960 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
6961 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
6962 &offset_expr
, AT
, ZERO
);
6972 macro_build_branch_rs (mask
, &offset_expr
, sreg
);
6978 /* Check for > max integer. */
6979 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
6982 /* Result is always false. */
6984 macro_build (NULL
, "nop", "");
6986 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
6989 if (imm_expr
.X_op
!= O_constant
)
6990 as_bad (_("Unsupported large constant"));
6991 ++imm_expr
.X_add_number
;
6995 if (mask
== M_BGEL_I
)
6997 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6999 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
7000 &offset_expr
, sreg
);
7003 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7005 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
7006 &offset_expr
, sreg
);
7009 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
<= GPR_SMIN
)
7012 /* result is always true */
7013 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
7014 macro_build (&offset_expr
, "b", "p");
7019 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7020 &offset_expr
, AT
, ZERO
);
7029 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7030 &offset_expr
, ZERO
, treg
);
7034 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7035 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7036 &offset_expr
, AT
, ZERO
);
7045 && imm_expr
.X_op
== O_constant
7046 && imm_expr
.X_add_number
== -1))
7048 if (imm_expr
.X_op
!= O_constant
)
7049 as_bad (_("Unsupported large constant"));
7050 ++imm_expr
.X_add_number
;
7054 if (mask
== M_BGEUL_I
)
7056 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7058 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7059 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7060 &offset_expr
, sreg
, ZERO
);
7065 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7066 &offset_expr
, AT
, ZERO
);
7074 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, sreg
);
7076 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, treg
);
7080 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7081 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7082 &offset_expr
, AT
, ZERO
);
7090 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7091 &offset_expr
, sreg
, ZERO
);
7097 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7098 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7099 &offset_expr
, AT
, ZERO
);
7107 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7109 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, treg
);
7113 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
7114 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7115 &offset_expr
, AT
, ZERO
);
7122 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
>= GPR_SMAX
)
7124 if (imm_expr
.X_op
!= O_constant
)
7125 as_bad (_("Unsupported large constant"));
7126 ++imm_expr
.X_add_number
;
7130 if (mask
== M_BLTL_I
)
7132 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7133 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7134 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7135 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, sreg
);
7140 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7141 &offset_expr
, AT
, ZERO
);
7149 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7150 &offset_expr
, sreg
, ZERO
);
7156 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
7157 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7158 &offset_expr
, AT
, ZERO
);
7167 && imm_expr
.X_op
== O_constant
7168 && imm_expr
.X_add_number
== -1))
7170 if (imm_expr
.X_op
!= O_constant
)
7171 as_bad (_("Unsupported large constant"));
7172 ++imm_expr
.X_add_number
;
7176 if (mask
== M_BLTUL_I
)
7178 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7180 else if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7181 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
7182 &offset_expr
, sreg
, ZERO
);
7187 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7188 &offset_expr
, AT
, ZERO
);
7196 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, sreg
);
7198 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, treg
);
7202 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
7203 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7204 &offset_expr
, AT
, ZERO
);
7214 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7215 &offset_expr
, ZERO
, treg
);
7219 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
7220 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
7221 &offset_expr
, AT
, ZERO
);
7227 /* Use unsigned arithmetic. */
7231 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7233 as_bad (_("Unsupported large constant"));
7238 pos
= imm_expr
.X_add_number
;
7239 size
= imm2_expr
.X_add_number
;
7244 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7247 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7249 as_bad (_("Improper extract size (%lu, position %lu)"),
7250 (unsigned long) size
, (unsigned long) pos
);
7254 if (size
<= 32 && pos
< 32)
7259 else if (size
<= 32)
7269 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7276 /* Use unsigned arithmetic. */
7280 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
7282 as_bad (_("Unsupported large constant"));
7287 pos
= imm_expr
.X_add_number
;
7288 size
= imm2_expr
.X_add_number
;
7293 as_bad (_("Improper position (%lu)"), (unsigned long) pos
);
7296 if (size
== 0 || size
> 64 || (pos
+ size
- 1) > 63)
7298 as_bad (_("Improper insert size (%lu, position %lu)"),
7299 (unsigned long) size
, (unsigned long) pos
);
7303 if (pos
< 32 && (pos
+ size
- 1) < 32)
7318 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
7319 (int) (pos
+ size
- 1));
7335 as_warn (_("Divide by zero."));
7337 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7339 macro_build (NULL
, "break", BRK_FMT
, 7);
7346 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7347 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7351 if (mips_opts
.micromips
)
7352 micromips_label_expr (&label_expr
);
7354 label_expr
.X_add_number
= 8;
7355 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7356 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
7357 macro_build (NULL
, "break", BRK_FMT
, 7);
7358 if (mips_opts
.micromips
)
7359 micromips_add_label ();
7361 expr1
.X_add_number
= -1;
7363 load_register (AT
, &expr1
, dbl
);
7364 if (mips_opts
.micromips
)
7365 micromips_label_expr (&label_expr
);
7367 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
7368 macro_build (&label_expr
, "bne", "s,t,p", treg
, AT
);
7371 expr1
.X_add_number
= 1;
7372 load_register (AT
, &expr1
, dbl
);
7373 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
7377 expr1
.X_add_number
= 0x80000000;
7378 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
7382 macro_build (NULL
, "teq", TRAP_FMT
, sreg
, AT
, 6);
7383 /* We want to close the noreorder block as soon as possible, so
7384 that later insns are available for delay slot filling. */
7389 if (mips_opts
.micromips
)
7390 micromips_label_expr (&label_expr
);
7392 label_expr
.X_add_number
= 8;
7393 macro_build (&label_expr
, "bne", "s,t,p", sreg
, AT
);
7394 macro_build (NULL
, "nop", "");
7396 /* We want to close the noreorder block as soon as possible, so
7397 that later insns are available for delay slot filling. */
7400 macro_build (NULL
, "break", BRK_FMT
, 6);
7402 if (mips_opts
.micromips
)
7403 micromips_add_label ();
7404 macro_build (NULL
, s
, MFHL_FMT
, dreg
);
7443 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7445 as_warn (_("Divide by zero."));
7447 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
7449 macro_build (NULL
, "break", BRK_FMT
, 7);
7452 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
7454 if (strcmp (s2
, "mflo") == 0)
7455 move_register (dreg
, sreg
);
7457 move_register (dreg
, ZERO
);
7460 if (imm_expr
.X_op
== O_constant
7461 && imm_expr
.X_add_number
== -1
7462 && s
[strlen (s
) - 1] != 'u')
7464 if (strcmp (s2
, "mflo") == 0)
7466 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
7469 move_register (dreg
, ZERO
);
7474 load_register (AT
, &imm_expr
, dbl
);
7475 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
7476 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7498 macro_build (NULL
, "teq", TRAP_FMT
, treg
, ZERO
, 7);
7499 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7500 /* We want to close the noreorder block as soon as possible, so
7501 that later insns are available for delay slot filling. */
7506 if (mips_opts
.micromips
)
7507 micromips_label_expr (&label_expr
);
7509 label_expr
.X_add_number
= 8;
7510 macro_build (&label_expr
, "bne", "s,t,p", treg
, ZERO
);
7511 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
7513 /* We want to close the noreorder block as soon as possible, so
7514 that later insns are available for delay slot filling. */
7516 macro_build (NULL
, "break", BRK_FMT
, 7);
7517 if (mips_opts
.micromips
)
7518 micromips_add_label ();
7520 macro_build (NULL
, s2
, MFHL_FMT
, dreg
);
7532 /* Load the address of a symbol into a register. If breg is not
7533 zero, we then add a base register to it. */
7535 if (dbl
&& HAVE_32BIT_GPRS
)
7536 as_warn (_("dla used to load 32-bit register"));
7538 if (!dbl
&& HAVE_64BIT_OBJECTS
)
7539 as_warn (_("la used to load 64-bit address"));
7541 if (offset_expr
.X_op
== O_constant
7542 && offset_expr
.X_add_number
>= -0x8000
7543 && offset_expr
.X_add_number
< 0x8000)
7545 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
7546 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
7550 if (mips_opts
.at
&& (treg
== breg
))
7560 if (offset_expr
.X_op
!= O_symbol
7561 && offset_expr
.X_op
!= O_constant
)
7563 as_bad (_("Expression too complex"));
7564 offset_expr
.X_op
= O_constant
;
7567 if (offset_expr
.X_op
== O_constant
)
7568 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
7569 else if (mips_pic
== NO_PIC
)
7571 /* If this is a reference to a GP relative symbol, we want
7572 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7574 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7575 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7576 If we have a constant, we need two instructions anyhow,
7577 so we may as well always use the latter form.
7579 With 64bit address space and a usable $at we want
7580 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7581 lui $at,<sym> (BFD_RELOC_HI16_S)
7582 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7583 daddiu $at,<sym> (BFD_RELOC_LO16)
7585 daddu $tempreg,$tempreg,$at
7587 If $at is already in use, we use a path which is suboptimal
7588 on superscalar processors.
7589 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7590 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7592 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7594 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7596 For GP relative symbols in 64bit address space we can use
7597 the same sequence as in 32bit address space. */
7598 if (HAVE_64BIT_SYMBOLS
)
7600 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7601 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7603 relax_start (offset_expr
.X_add_symbol
);
7604 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7605 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7609 if (used_at
== 0 && mips_opts
.at
)
7611 macro_build (&offset_expr
, "lui", LUI_FMT
,
7612 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7613 macro_build (&offset_expr
, "lui", LUI_FMT
,
7614 AT
, BFD_RELOC_HI16_S
);
7615 macro_build (&offset_expr
, "daddiu", "t,r,j",
7616 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7617 macro_build (&offset_expr
, "daddiu", "t,r,j",
7618 AT
, AT
, BFD_RELOC_LO16
);
7619 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
7620 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
7625 macro_build (&offset_expr
, "lui", LUI_FMT
,
7626 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
7627 macro_build (&offset_expr
, "daddiu", "t,r,j",
7628 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
7629 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7630 macro_build (&offset_expr
, "daddiu", "t,r,j",
7631 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
7632 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
7633 macro_build (&offset_expr
, "daddiu", "t,r,j",
7634 tempreg
, tempreg
, BFD_RELOC_LO16
);
7637 if (mips_relax
.sequence
)
7642 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7643 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7645 relax_start (offset_expr
.X_add_symbol
);
7646 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7647 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
7650 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7651 as_bad (_("Offset too large"));
7652 macro_build_lui (&offset_expr
, tempreg
);
7653 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7654 tempreg
, tempreg
, BFD_RELOC_LO16
);
7655 if (mips_relax
.sequence
)
7659 else if (!mips_big_got
&& !HAVE_NEWABI
)
7661 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7663 /* If this is a reference to an external symbol, and there
7664 is no constant, we want
7665 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7666 or for lca or if tempreg is PIC_CALL_REG
7667 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7668 For a local symbol, we want
7669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7671 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7673 If we have a small constant, and this is a reference to
7674 an external symbol, we want
7675 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7677 addiu $tempreg,$tempreg,<constant>
7678 For a local symbol, we want the same instruction
7679 sequence, but we output a BFD_RELOC_LO16 reloc on the
7682 If we have a large constant, and this is a reference to
7683 an external symbol, we want
7684 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7685 lui $at,<hiconstant>
7686 addiu $at,$at,<loconstant>
7687 addu $tempreg,$tempreg,$at
7688 For a local symbol, we want the same instruction
7689 sequence, but we output a BFD_RELOC_LO16 reloc on the
7693 if (offset_expr
.X_add_number
== 0)
7695 if (mips_pic
== SVR4_PIC
7697 && (call
|| tempreg
== PIC_CALL_REG
))
7698 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
7700 relax_start (offset_expr
.X_add_symbol
);
7701 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7702 lw_reloc_type
, mips_gp_register
);
7705 /* We're going to put in an addu instruction using
7706 tempreg, so we may as well insert the nop right
7711 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7712 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7714 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7715 tempreg
, tempreg
, BFD_RELOC_LO16
);
7717 /* FIXME: If breg == 0, and the next instruction uses
7718 $tempreg, then if this variant case is used an extra
7719 nop will be generated. */
7721 else if (offset_expr
.X_add_number
>= -0x8000
7722 && offset_expr
.X_add_number
< 0x8000)
7724 load_got_offset (tempreg
, &offset_expr
);
7726 add_got_offset (tempreg
, &offset_expr
);
7730 expr1
.X_add_number
= offset_expr
.X_add_number
;
7731 offset_expr
.X_add_number
=
7732 SEXT_16BIT (offset_expr
.X_add_number
);
7733 load_got_offset (tempreg
, &offset_expr
);
7734 offset_expr
.X_add_number
= expr1
.X_add_number
;
7735 /* If we are going to add in a base register, and the
7736 target register and the base register are the same,
7737 then we are using AT as a temporary register. Since
7738 we want to load the constant into AT, we add our
7739 current AT (from the global offset table) and the
7740 register into the register now, and pretend we were
7741 not using a base register. */
7745 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7750 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
7754 else if (!mips_big_got
&& HAVE_NEWABI
)
7756 int add_breg_early
= 0;
7758 /* If this is a reference to an external, and there is no
7759 constant, or local symbol (*), with or without a
7761 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7762 or for lca or if tempreg is PIC_CALL_REG
7763 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7765 If we have a small constant, and this is a reference to
7766 an external symbol, we want
7767 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7768 addiu $tempreg,$tempreg,<constant>
7770 If we have a large constant, and this is a reference to
7771 an external symbol, we want
7772 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7773 lui $at,<hiconstant>
7774 addiu $at,$at,<loconstant>
7775 addu $tempreg,$tempreg,$at
7777 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7778 local symbols, even though it introduces an additional
7781 if (offset_expr
.X_add_number
)
7783 expr1
.X_add_number
= offset_expr
.X_add_number
;
7784 offset_expr
.X_add_number
= 0;
7786 relax_start (offset_expr
.X_add_symbol
);
7787 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7788 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7790 if (expr1
.X_add_number
>= -0x8000
7791 && expr1
.X_add_number
< 0x8000)
7793 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7794 tempreg
, tempreg
, BFD_RELOC_LO16
);
7796 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
7798 /* If we are going to add in a base register, and the
7799 target register and the base register are the same,
7800 then we are using AT as a temporary register. Since
7801 we want to load the constant into AT, we add our
7802 current AT (from the global offset table) and the
7803 register into the register now, and pretend we were
7804 not using a base register. */
7809 gas_assert (tempreg
== AT
);
7810 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7816 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7817 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7823 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7826 offset_expr
.X_add_number
= expr1
.X_add_number
;
7828 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7829 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7832 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7833 treg
, tempreg
, breg
);
7839 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
7841 relax_start (offset_expr
.X_add_symbol
);
7842 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7843 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
7845 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7846 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7851 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7852 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
7855 else if (mips_big_got
&& !HAVE_NEWABI
)
7858 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
7859 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
7860 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
7862 /* This is the large GOT case. If this is a reference to an
7863 external symbol, and there is no constant, we want
7864 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7865 addu $tempreg,$tempreg,$gp
7866 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7867 or for lca or if tempreg is PIC_CALL_REG
7868 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7869 addu $tempreg,$tempreg,$gp
7870 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7871 For a local symbol, we want
7872 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7874 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7876 If we have a small constant, and this is a reference to
7877 an external symbol, we want
7878 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7879 addu $tempreg,$tempreg,$gp
7880 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7882 addiu $tempreg,$tempreg,<constant>
7883 For a local symbol, we want
7884 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7886 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7888 If we have a large constant, and this is a reference to
7889 an external symbol, we want
7890 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7891 addu $tempreg,$tempreg,$gp
7892 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7893 lui $at,<hiconstant>
7894 addiu $at,$at,<loconstant>
7895 addu $tempreg,$tempreg,$at
7896 For a local symbol, we want
7897 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7898 lui $at,<hiconstant>
7899 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7900 addu $tempreg,$tempreg,$at
7903 expr1
.X_add_number
= offset_expr
.X_add_number
;
7904 offset_expr
.X_add_number
= 0;
7905 relax_start (offset_expr
.X_add_symbol
);
7906 gpdelay
= reg_needs_delay (mips_gp_register
);
7907 if (expr1
.X_add_number
== 0 && breg
== 0
7908 && (call
|| tempreg
== PIC_CALL_REG
))
7910 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
7911 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
7913 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
7914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7915 tempreg
, tempreg
, mips_gp_register
);
7916 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7917 tempreg
, lw_reloc_type
, tempreg
);
7918 if (expr1
.X_add_number
== 0)
7922 /* We're going to put in an addu instruction using
7923 tempreg, so we may as well insert the nop right
7928 else if (expr1
.X_add_number
>= -0x8000
7929 && expr1
.X_add_number
< 0x8000)
7932 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
7933 tempreg
, tempreg
, BFD_RELOC_LO16
);
7937 /* If we are going to add in a base register, and the
7938 target register and the base register are the same,
7939 then we are using AT as a temporary register. Since
7940 we want to load the constant into AT, we add our
7941 current AT (from the global offset table) and the
7942 register into the register now, and pretend we were
7943 not using a base register. */
7948 gas_assert (tempreg
== AT
);
7950 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7955 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
7956 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
7960 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
7965 /* This is needed because this instruction uses $gp, but
7966 the first instruction on the main stream does not. */
7967 macro_build (NULL
, "nop", "");
7970 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
7971 local_reloc_type
, mips_gp_register
);
7972 if (expr1
.X_add_number
>= -0x8000
7973 && expr1
.X_add_number
< 0x8000)
7976 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
7977 tempreg
, tempreg
, BFD_RELOC_LO16
);
7978 /* FIXME: If add_number is 0, and there was no base
7979 register, the external symbol case ended with a load,
7980 so if the symbol turns out to not be external, and
7981 the next instruction uses tempreg, an unnecessary nop
7982 will be inserted. */
7988 /* We must add in the base register now, as in the
7989 external symbol case. */
7990 gas_assert (tempreg
== AT
);
7992 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7995 /* We set breg to 0 because we have arranged to add
7996 it in in both cases. */
8000 macro_build_lui (&expr1
, AT
);
8001 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8002 AT
, AT
, BFD_RELOC_LO16
);
8003 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8004 tempreg
, tempreg
, AT
);
8009 else if (mips_big_got
&& HAVE_NEWABI
)
8011 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
8012 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
8013 int add_breg_early
= 0;
8015 /* This is the large GOT case. If this is a reference to an
8016 external symbol, and there is no constant, we want
8017 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8018 add $tempreg,$tempreg,$gp
8019 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8020 or for lca or if tempreg is PIC_CALL_REG
8021 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8022 add $tempreg,$tempreg,$gp
8023 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8025 If we have a small constant, and this is a reference to
8026 an external symbol, we want
8027 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8028 add $tempreg,$tempreg,$gp
8029 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8030 addi $tempreg,$tempreg,<constant>
8032 If we have a large constant, and this is a reference to
8033 an external symbol, we want
8034 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8035 addu $tempreg,$tempreg,$gp
8036 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8037 lui $at,<hiconstant>
8038 addi $at,$at,<loconstant>
8039 add $tempreg,$tempreg,$at
8041 If we have NewABI, and we know it's a local symbol, we want
8042 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8043 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8044 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8046 relax_start (offset_expr
.X_add_symbol
);
8048 expr1
.X_add_number
= offset_expr
.X_add_number
;
8049 offset_expr
.X_add_number
= 0;
8051 if (expr1
.X_add_number
== 0 && breg
== 0
8052 && (call
|| tempreg
== PIC_CALL_REG
))
8054 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
8055 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
8057 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
8058 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8059 tempreg
, tempreg
, mips_gp_register
);
8060 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8061 tempreg
, lw_reloc_type
, tempreg
);
8063 if (expr1
.X_add_number
== 0)
8065 else if (expr1
.X_add_number
>= -0x8000
8066 && expr1
.X_add_number
< 0x8000)
8068 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
8069 tempreg
, tempreg
, BFD_RELOC_LO16
);
8071 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
8073 /* If we are going to add in a base register, and the
8074 target register and the base register are the same,
8075 then we are using AT as a temporary register. Since
8076 we want to load the constant into AT, we add our
8077 current AT (from the global offset table) and the
8078 register into the register now, and pretend we were
8079 not using a base register. */
8084 gas_assert (tempreg
== AT
);
8085 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8091 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
8092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
8097 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8100 offset_expr
.X_add_number
= expr1
.X_add_number
;
8101 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
8102 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
8103 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
8104 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
8107 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8108 treg
, tempreg
, breg
);
8118 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
8122 gas_assert (!mips_opts
.micromips
);
8124 unsigned long temp
= (treg
<< 16) | (0x01);
8125 macro_build (NULL
, "c2", "C", temp
);
8130 gas_assert (!mips_opts
.micromips
);
8132 unsigned long temp
= (0x02);
8133 macro_build (NULL
, "c2", "C", temp
);
8138 gas_assert (!mips_opts
.micromips
);
8140 unsigned long temp
= (treg
<< 16) | (0x02);
8141 macro_build (NULL
, "c2", "C", temp
);
8146 gas_assert (!mips_opts
.micromips
);
8147 macro_build (NULL
, "c2", "C", 3);
8151 gas_assert (!mips_opts
.micromips
);
8153 unsigned long temp
= (treg
<< 16) | 0x03;
8154 macro_build (NULL
, "c2", "C", temp
);
8159 /* The j instruction may not be used in PIC code, since it
8160 requires an absolute address. We convert it to a b
8162 if (mips_pic
== NO_PIC
)
8163 macro_build (&offset_expr
, "j", "a");
8165 macro_build (&offset_expr
, "b", "p");
8168 /* The jal instructions must be handled as macros because when
8169 generating PIC code they expand to multi-instruction
8170 sequences. Normally they are simple instructions. */
8175 gas_assert (mips_opts
.micromips
);
8176 if (mips_opts
.insn32
)
8178 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8188 if (mips_pic
== NO_PIC
)
8190 s
= jals
? "jalrs" : "jalr";
8191 if (mips_opts
.micromips
8192 && !mips_opts
.insn32
8194 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8195 macro_build (NULL
, s
, "mj", sreg
);
8197 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8201 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
8202 && mips_cprestore_offset
>= 0);
8204 if (sreg
!= PIC_CALL_REG
)
8205 as_warn (_("MIPS PIC call to register other than $25"));
8207 s
= ((mips_opts
.micromips
8208 && !mips_opts
.insn32
8209 && (!mips_opts
.noreorder
|| cprestore
))
8210 ? "jalrs" : "jalr");
8211 if (mips_opts
.micromips
8212 && !mips_opts
.insn32
8214 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
8215 macro_build (NULL
, s
, "mj", sreg
);
8217 macro_build (NULL
, s
, JALR_FMT
, dreg
, sreg
);
8218 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
8220 if (mips_cprestore_offset
< 0)
8221 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8224 if (!mips_frame_reg_valid
)
8226 as_warn (_("No .frame pseudo-op used in PIC code"));
8227 /* Quiet this warning. */
8228 mips_frame_reg_valid
= 1;
8230 if (!mips_cprestore_valid
)
8232 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8233 /* Quiet this warning. */
8234 mips_cprestore_valid
= 1;
8236 if (mips_opts
.noreorder
)
8237 macro_build (NULL
, "nop", "");
8238 expr1
.X_add_number
= mips_cprestore_offset
;
8239 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8242 HAVE_64BIT_ADDRESSES
);
8250 gas_assert (mips_opts
.micromips
);
8251 if (mips_opts
.insn32
)
8253 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str
);
8259 if (mips_pic
== NO_PIC
)
8260 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
8261 else if (mips_pic
== SVR4_PIC
)
8263 /* If this is a reference to an external symbol, and we are
8264 using a small GOT, we want
8265 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8269 lw $gp,cprestore($sp)
8270 The cprestore value is set using the .cprestore
8271 pseudo-op. If we are using a big GOT, we want
8272 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8274 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8278 lw $gp,cprestore($sp)
8279 If the symbol is not external, we want
8280 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8282 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8285 lw $gp,cprestore($sp)
8287 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8288 sequences above, minus nops, unless the symbol is local,
8289 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8295 relax_start (offset_expr
.X_add_symbol
);
8296 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8297 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8300 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8301 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
8307 relax_start (offset_expr
.X_add_symbol
);
8308 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8309 BFD_RELOC_MIPS_CALL_HI16
);
8310 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8311 PIC_CALL_REG
, mips_gp_register
);
8312 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8313 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8316 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8317 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
8319 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8320 PIC_CALL_REG
, PIC_CALL_REG
,
8321 BFD_RELOC_MIPS_GOT_OFST
);
8325 macro_build_jalr (&offset_expr
, 0);
8329 relax_start (offset_expr
.X_add_symbol
);
8332 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8333 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
8342 gpdelay
= reg_needs_delay (mips_gp_register
);
8343 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
8344 BFD_RELOC_MIPS_CALL_HI16
);
8345 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
8346 PIC_CALL_REG
, mips_gp_register
);
8347 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8348 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
8353 macro_build (NULL
, "nop", "");
8355 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
8356 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
8359 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8360 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
8362 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
8364 if (mips_cprestore_offset
< 0)
8365 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8368 if (!mips_frame_reg_valid
)
8370 as_warn (_("No .frame pseudo-op used in PIC code"));
8371 /* Quiet this warning. */
8372 mips_frame_reg_valid
= 1;
8374 if (!mips_cprestore_valid
)
8376 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8377 /* Quiet this warning. */
8378 mips_cprestore_valid
= 1;
8380 if (mips_opts
.noreorder
)
8381 macro_build (NULL
, "nop", "");
8382 expr1
.X_add_number
= mips_cprestore_offset
;
8383 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
8386 HAVE_64BIT_ADDRESSES
);
8390 else if (mips_pic
== VXWORKS_PIC
)
8391 as_bad (_("Non-PIC jump used in PIC library"));
8499 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8507 treg
= EXTRACT_OPERAND (mips_opts
.micromips
, 3BITPOS
, *ip
);
8538 gas_assert (!mips_opts
.micromips
);
8541 /* Itbl support may require additional care here. */
8548 /* Itbl support may require additional care here. */
8556 offbits
= (mips_opts
.micromips
? 12 : 16);
8557 /* Itbl support may require additional care here. */
8562 gas_assert (!mips_opts
.micromips
);
8565 /* Itbl support may require additional care here. */
8573 offbits
= (mips_opts
.micromips
? 12 : 16);
8580 offbits
= (mips_opts
.micromips
? 12 : 16);
8586 /* Itbl support may require additional care here. */
8594 offbits
= (mips_opts
.micromips
? 12 : 16);
8595 /* Itbl support may require additional care here. */
8602 /* Itbl support may require additional care here. */
8609 /* Itbl support may require additional care here. */
8617 offbits
= (mips_opts
.micromips
? 12 : 16);
8624 offbits
= (mips_opts
.micromips
? 12 : 16);
8631 offbits
= (mips_opts
.micromips
? 12 : 16);
8638 offbits
= (mips_opts
.micromips
? 12 : 16);
8645 offbits
= (mips_opts
.micromips
? 12 : 16);
8650 gas_assert (mips_opts
.micromips
);
8659 gas_assert (mips_opts
.micromips
);
8668 gas_assert (mips_opts
.micromips
);
8676 gas_assert (mips_opts
.micromips
);
8683 /* We don't want to use $0 as tempreg. */
8684 if (breg
== treg
+ lp
|| treg
+ lp
== ZERO
)
8687 tempreg
= treg
+ lp
;
8707 gas_assert (!mips_opts
.micromips
);
8710 /* Itbl support may require additional care here. */
8717 /* Itbl support may require additional care here. */
8725 offbits
= (mips_opts
.micromips
? 12 : 16);
8726 /* Itbl support may require additional care here. */
8731 gas_assert (!mips_opts
.micromips
);
8734 /* Itbl support may require additional care here. */
8742 offbits
= (mips_opts
.micromips
? 12 : 16);
8749 offbits
= (mips_opts
.micromips
? 12 : 16);
8756 offbits
= (mips_opts
.micromips
? 12 : 16);
8763 offbits
= (mips_opts
.micromips
? 12 : 16);
8769 fmt
= mips_opts
.micromips
? "k,~(b)" : "k,o(b)";
8770 offbits
= (mips_opts
.micromips
? 12 : 16);
8783 fmt
= !mips_opts
.micromips
? "k,o(b)" : "k,~(b)";
8784 offbits
= (mips_opts
.micromips
? 12 : 16);
8798 /* Itbl support may require additional care here. */
8805 offbits
= (mips_opts
.micromips
? 12 : 16);
8806 /* Itbl support may require additional care here. */
8813 /* Itbl support may require additional care here. */
8818 gas_assert (!mips_opts
.micromips
);
8821 /* Itbl support may require additional care here. */
8829 offbits
= (mips_opts
.micromips
? 12 : 16);
8836 offbits
= (mips_opts
.micromips
? 12 : 16);
8841 gas_assert (mips_opts
.micromips
);
8849 gas_assert (mips_opts
.micromips
);
8857 gas_assert (mips_opts
.micromips
);
8865 gas_assert (mips_opts
.micromips
);
8874 if (offset_expr
.X_op
!= O_constant
8875 && offset_expr
.X_op
!= O_symbol
)
8877 as_bad (_("Expression too complex"));
8878 offset_expr
.X_op
= O_constant
;
8881 if (HAVE_32BIT_ADDRESSES
8882 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
8886 sprintf_vma (value
, offset_expr
.X_add_number
);
8887 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
8890 /* A constant expression in PIC code can be handled just as it
8891 is in non PIC code. */
8892 if (offset_expr
.X_op
== O_constant
)
8896 expr1
.X_add_number
= offset_expr
.X_add_number
;
8897 normalize_address_expr (&expr1
);
8898 if ((offbits
== 0 || offbits
== 16)
8899 && !IS_SEXT_16BIT_NUM (expr1
.X_add_number
))
8901 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x8000)
8902 & ~(bfd_vma
) 0xffff);
8905 else if (offbits
== 12 && !IS_SEXT_12BIT_NUM (expr1
.X_add_number
))
8907 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x800)
8908 & ~(bfd_vma
) 0xfff);
8911 else if (offbits
== 9 && !IS_SEXT_9BIT_NUM (expr1
.X_add_number
))
8913 expr1
.X_add_number
= ((expr1
.X_add_number
+ 0x100)
8914 & ~(bfd_vma
) 0x1ff);
8919 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
8921 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8922 tempreg
, tempreg
, breg
);
8927 if (offset_expr
.X_add_number
== 0)
8930 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
8931 "t,r,j", tempreg
, breg
, BFD_RELOC_LO16
);
8932 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8934 else if (offbits
== 16)
8935 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, breg
);
8937 macro_build (NULL
, s
, fmt
,
8938 treg
, (unsigned long) offset_expr
.X_add_number
, breg
);
8940 else if (offbits
!= 16)
8942 /* The offset field is too narrow to be used for a low-part
8943 relocation, so load the whole address into the auxillary
8944 register. In the case of "A(b)" addresses, we first load
8945 absolute address "A" into the register and then add base
8946 register "b". In the case of "o(b)" addresses, we simply
8947 need to add 16-bit offset "o" to base register "b", and
8948 offset_reloc already contains the relocations associated
8952 load_address (tempreg
, &offset_expr
, &used_at
);
8954 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
8955 tempreg
, tempreg
, breg
);
8958 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
8960 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
8961 expr1
.X_add_number
= 0;
8963 macro_build (NULL
, s
, fmt
, treg
, tempreg
);
8965 macro_build (NULL
, s
, fmt
,
8966 treg
, (unsigned long) expr1
.X_add_number
, tempreg
);
8968 else if (mips_pic
== NO_PIC
)
8970 /* If this is a reference to a GP relative symbol, and there
8971 is no base register, we want
8972 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8973 Otherwise, if there is no base register, we want
8974 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8975 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8976 If we have a constant, we need two instructions anyhow,
8977 so we always use the latter form.
8979 If we have a base register, and this is a reference to a
8980 GP relative symbol, we want
8981 addu $tempreg,$breg,$gp
8982 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8984 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8985 addu $tempreg,$tempreg,$breg
8986 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8987 With a constant we always use the latter case.
8989 With 64bit address space and no base register and $at usable,
8991 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8992 lui $at,<sym> (BFD_RELOC_HI16_S)
8993 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8996 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8997 If we have a base register, we want
8998 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8999 lui $at,<sym> (BFD_RELOC_HI16_S)
9000 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9004 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9006 Without $at we can't generate the optimal path for superscalar
9007 processors here since this would require two temporary registers.
9008 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9009 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9011 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9013 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9014 If we have a base register, we want
9015 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9016 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9018 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9020 daddu $tempreg,$tempreg,$breg
9021 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
9023 For GP relative symbols in 64bit address space we can use
9024 the same sequence as in 32bit address space. */
9025 if (HAVE_64BIT_SYMBOLS
)
9027 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9028 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9030 relax_start (offset_expr
.X_add_symbol
);
9033 macro_build (&offset_expr
, s
, fmt
, treg
,
9034 BFD_RELOC_GPREL16
, mips_gp_register
);
9038 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9039 tempreg
, breg
, mips_gp_register
);
9040 macro_build (&offset_expr
, s
, fmt
, treg
,
9041 BFD_RELOC_GPREL16
, tempreg
);
9046 if (used_at
== 0 && mips_opts
.at
)
9048 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9049 BFD_RELOC_MIPS_HIGHEST
);
9050 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
9052 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9053 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9055 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
9056 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
9057 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
9058 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
9064 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9065 BFD_RELOC_MIPS_HIGHEST
);
9066 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9067 tempreg
, BFD_RELOC_MIPS_HIGHER
);
9068 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9069 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
9070 tempreg
, BFD_RELOC_HI16_S
);
9071 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
9073 macro_build (NULL
, "daddu", "d,v,t",
9074 tempreg
, tempreg
, breg
);
9075 macro_build (&offset_expr
, s
, fmt
, treg
,
9076 BFD_RELOC_LO16
, tempreg
);
9079 if (mips_relax
.sequence
)
9086 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9087 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9089 relax_start (offset_expr
.X_add_symbol
);
9090 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
9094 macro_build_lui (&offset_expr
, tempreg
);
9095 macro_build (&offset_expr
, s
, fmt
, treg
,
9096 BFD_RELOC_LO16
, tempreg
);
9097 if (mips_relax
.sequence
)
9102 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9103 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9105 relax_start (offset_expr
.X_add_symbol
);
9106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9107 tempreg
, breg
, mips_gp_register
);
9108 macro_build (&offset_expr
, s
, fmt
, treg
,
9109 BFD_RELOC_GPREL16
, tempreg
);
9112 macro_build_lui (&offset_expr
, tempreg
);
9113 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9114 tempreg
, tempreg
, breg
);
9115 macro_build (&offset_expr
, s
, fmt
, treg
,
9116 BFD_RELOC_LO16
, tempreg
);
9117 if (mips_relax
.sequence
)
9121 else if (!mips_big_got
)
9123 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
9125 /* If this is a reference to an external symbol, we want
9126 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9128 <op> $treg,0($tempreg)
9130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9132 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9133 <op> $treg,0($tempreg)
9136 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9137 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9139 If there is a base register, we add it to $tempreg before
9140 the <op>. If there is a constant, we stick it in the
9141 <op> instruction. We don't handle constants larger than
9142 16 bits, because we have no way to load the upper 16 bits
9143 (actually, we could handle them for the subset of cases
9144 in which we are not using $at). */
9145 gas_assert (offset_expr
.X_op
== O_symbol
);
9148 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9149 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9151 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9152 tempreg
, tempreg
, breg
);
9153 macro_build (&offset_expr
, s
, fmt
, treg
,
9154 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9157 expr1
.X_add_number
= offset_expr
.X_add_number
;
9158 offset_expr
.X_add_number
= 0;
9159 if (expr1
.X_add_number
< -0x8000
9160 || expr1
.X_add_number
>= 0x8000)
9161 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9162 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9163 lw_reloc_type
, mips_gp_register
);
9165 relax_start (offset_expr
.X_add_symbol
);
9167 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9168 tempreg
, BFD_RELOC_LO16
);
9171 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9172 tempreg
, tempreg
, breg
);
9173 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9175 else if (mips_big_got
&& !HAVE_NEWABI
)
9179 /* If this is a reference to an external symbol, we want
9180 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9181 addu $tempreg,$tempreg,$gp
9182 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9183 <op> $treg,0($tempreg)
9185 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9187 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9188 <op> $treg,0($tempreg)
9189 If there is a base register, we add it to $tempreg before
9190 the <op>. If there is a constant, we stick it in the
9191 <op> instruction. We don't handle constants larger than
9192 16 bits, because we have no way to load the upper 16 bits
9193 (actually, we could handle them for the subset of cases
9194 in which we are not using $at). */
9195 gas_assert (offset_expr
.X_op
== O_symbol
);
9196 expr1
.X_add_number
= offset_expr
.X_add_number
;
9197 offset_expr
.X_add_number
= 0;
9198 if (expr1
.X_add_number
< -0x8000
9199 || expr1
.X_add_number
>= 0x8000)
9200 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9201 gpdelay
= reg_needs_delay (mips_gp_register
);
9202 relax_start (offset_expr
.X_add_symbol
);
9203 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9204 BFD_RELOC_MIPS_GOT_HI16
);
9205 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9207 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9208 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9211 macro_build (NULL
, "nop", "");
9212 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9213 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9215 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
9216 tempreg
, BFD_RELOC_LO16
);
9220 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9221 tempreg
, tempreg
, breg
);
9222 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9224 else if (mips_big_got
&& HAVE_NEWABI
)
9226 /* If this is a reference to an external symbol, we want
9227 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9228 add $tempreg,$tempreg,$gp
9229 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9230 <op> $treg,<ofst>($tempreg)
9231 Otherwise, for local symbols, we want:
9232 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9233 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9234 gas_assert (offset_expr
.X_op
== O_symbol
);
9235 expr1
.X_add_number
= offset_expr
.X_add_number
;
9236 offset_expr
.X_add_number
= 0;
9237 if (expr1
.X_add_number
< -0x8000
9238 || expr1
.X_add_number
>= 0x8000)
9239 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9240 relax_start (offset_expr
.X_add_symbol
);
9241 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
9242 BFD_RELOC_MIPS_GOT_HI16
);
9243 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
9245 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9246 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
9248 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9249 tempreg
, tempreg
, breg
);
9250 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
9253 offset_expr
.X_add_number
= expr1
.X_add_number
;
9254 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
9255 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9257 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9258 tempreg
, tempreg
, breg
);
9259 macro_build (&offset_expr
, s
, fmt
, treg
,
9260 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
9269 gas_assert (mips_opts
.micromips
);
9270 gas_assert (mips_opts
.insn32
);
9272 macro_build (NULL
, "jr", "s", RA
);
9273 expr1
.X_add_number
= EXTRACT_OPERAND (1, IMMP
, *ip
) << 2;
9274 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
9279 gas_assert (mips_opts
.micromips
);
9280 gas_assert (mips_opts
.insn32
);
9281 macro_build (NULL
, "jr", "s", sreg
);
9282 if (mips_opts
.noreorder
)
9283 macro_build (NULL
, "nop", "");
9288 load_register (treg
, &imm_expr
, 0);
9292 load_register (treg
, &imm_expr
, 1);
9296 if (imm_expr
.X_op
== O_constant
)
9299 load_register (AT
, &imm_expr
, 0);
9300 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9305 gas_assert (offset_expr
.X_op
== O_symbol
9306 && strcmp (segment_name (S_GET_SEGMENT
9307 (offset_expr
.X_add_symbol
)),
9309 && offset_expr
.X_add_number
== 0);
9310 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
9311 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9316 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9317 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9318 order 32 bits of the value and the low order 32 bits are either
9319 zero or in OFFSET_EXPR. */
9320 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9322 if (HAVE_64BIT_GPRS
)
9323 load_register (treg
, &imm_expr
, 1);
9328 if (target_big_endian
)
9340 load_register (hreg
, &imm_expr
, 0);
9343 if (offset_expr
.X_op
== O_absent
)
9344 move_register (lreg
, 0);
9347 gas_assert (offset_expr
.X_op
== O_constant
);
9348 load_register (lreg
, &offset_expr
, 0);
9355 /* We know that sym is in the .rdata section. First we get the
9356 upper 16 bits of the address. */
9357 if (mips_pic
== NO_PIC
)
9359 macro_build_lui (&offset_expr
, AT
);
9364 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9365 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9369 /* Now we load the register(s). */
9370 if (HAVE_64BIT_GPRS
)
9373 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9378 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9381 /* FIXME: How in the world do we deal with the possible
9383 offset_expr
.X_add_number
+= 4;
9384 macro_build (&offset_expr
, "lw", "t,o(b)",
9385 treg
+ 1, BFD_RELOC_LO16
, AT
);
9391 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9392 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9393 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9394 the value and the low order 32 bits are either zero or in
9396 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
9399 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
9400 if (HAVE_64BIT_FPRS
)
9402 gas_assert (HAVE_64BIT_GPRS
);
9403 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
9407 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
9408 if (offset_expr
.X_op
== O_absent
)
9409 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
9412 gas_assert (offset_expr
.X_op
== O_constant
);
9413 load_register (AT
, &offset_expr
, 0);
9414 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
9420 gas_assert (offset_expr
.X_op
== O_symbol
9421 && offset_expr
.X_add_number
== 0);
9422 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
9423 if (strcmp (s
, ".lit8") == 0)
9425 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9427 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
9428 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
9431 breg
= mips_gp_register
;
9432 r
= BFD_RELOC_MIPS_LITERAL
;
9437 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
9439 if (mips_pic
!= NO_PIC
)
9440 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9441 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9444 /* FIXME: This won't work for a 64 bit address. */
9445 macro_build_lui (&offset_expr
, AT
);
9448 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
) || mips_opts
.micromips
)
9450 macro_build (&offset_expr
, "ldc1", "T,o(b)",
9451 treg
, BFD_RELOC_LO16
, AT
);
9460 /* Even on a big endian machine $fn comes before $fn+1. We have
9461 to adjust when loading from memory. */
9464 gas_assert (!mips_opts
.micromips
);
9465 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9466 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9467 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
9468 /* FIXME: A possible overflow which I don't know how to deal
9470 offset_expr
.X_add_number
+= 4;
9471 macro_build (&offset_expr
, "lwc1", "T,o(b)",
9472 target_big_endian
? treg
: treg
+ 1, r
, breg
);
9476 gas_assert (!mips_opts
.micromips
);
9477 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts
.arch
));
9478 /* Even on a big endian machine $fn comes before $fn+1. We have
9479 to adjust when storing to memory. */
9480 macro_build (&offset_expr
, "swc1", "T,o(b)",
9481 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
9482 offset_expr
.X_add_number
+= 4;
9483 macro_build (&offset_expr
, "swc1", "T,o(b)",
9484 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
9488 gas_assert (!mips_opts
.micromips
);
9490 * The MIPS assembler seems to check for X_add_number not
9491 * being double aligned and generating:
9494 * addiu at,at,%lo(foo+1)
9497 * But, the resulting address is the same after relocation so why
9498 * generate the extra instruction?
9500 /* Itbl support may require additional care here. */
9503 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9512 gas_assert (!mips_opts
.micromips
);
9513 /* Itbl support may require additional care here. */
9516 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
9536 if (HAVE_64BIT_GPRS
)
9546 if (HAVE_64BIT_GPRS
)
9554 if (offset_expr
.X_op
!= O_symbol
9555 && offset_expr
.X_op
!= O_constant
)
9557 as_bad (_("Expression too complex"));
9558 offset_expr
.X_op
= O_constant
;
9561 if (HAVE_32BIT_ADDRESSES
9562 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
9566 sprintf_vma (value
, offset_expr
.X_add_number
);
9567 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
9570 /* Even on a big endian machine $fn comes before $fn+1. We have
9571 to adjust when loading from memory. We set coproc if we must
9572 load $fn+1 first. */
9573 /* Itbl support may require additional care here. */
9574 if (!target_big_endian
)
9577 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
9579 /* If this is a reference to a GP relative symbol, we want
9580 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9581 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9582 If we have a base register, we use this
9584 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9585 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9586 If this is not a GP relative symbol, we want
9587 lui $at,<sym> (BFD_RELOC_HI16_S)
9588 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9589 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9590 If there is a base register, we add it to $at after the
9591 lui instruction. If there is a constant, we always use
9593 if (offset_expr
.X_op
== O_symbol
9594 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
9595 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
9597 relax_start (offset_expr
.X_add_symbol
);
9600 tempreg
= mips_gp_register
;
9604 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9605 AT
, breg
, mips_gp_register
);
9610 /* Itbl support may require additional care here. */
9611 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9612 BFD_RELOC_GPREL16
, tempreg
);
9613 offset_expr
.X_add_number
+= 4;
9615 /* Set mips_optimize to 2 to avoid inserting an
9617 hold_mips_optimize
= mips_optimize
;
9619 /* Itbl support may require additional care here. */
9620 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9621 BFD_RELOC_GPREL16
, tempreg
);
9622 mips_optimize
= hold_mips_optimize
;
9626 offset_expr
.X_add_number
-= 4;
9629 macro_build_lui (&offset_expr
, AT
);
9631 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9632 /* Itbl support may require additional care here. */
9633 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9634 BFD_RELOC_LO16
, AT
);
9635 /* FIXME: How do we handle overflow here? */
9636 offset_expr
.X_add_number
+= 4;
9637 /* Itbl support may require additional care here. */
9638 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9639 BFD_RELOC_LO16
, AT
);
9640 if (mips_relax
.sequence
)
9643 else if (!mips_big_got
)
9645 /* If this is a reference to an external symbol, we want
9646 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9651 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9653 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9654 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9655 If there is a base register we add it to $at before the
9656 lwc1 instructions. If there is a constant we include it
9657 in the lwc1 instructions. */
9659 expr1
.X_add_number
= offset_expr
.X_add_number
;
9660 if (expr1
.X_add_number
< -0x8000
9661 || expr1
.X_add_number
>= 0x8000 - 4)
9662 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9663 load_got_offset (AT
, &offset_expr
);
9666 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9668 /* Set mips_optimize to 2 to avoid inserting an undesired
9670 hold_mips_optimize
= mips_optimize
;
9673 /* Itbl support may require additional care here. */
9674 relax_start (offset_expr
.X_add_symbol
);
9675 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9676 BFD_RELOC_LO16
, AT
);
9677 expr1
.X_add_number
+= 4;
9678 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9679 BFD_RELOC_LO16
, AT
);
9681 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9682 BFD_RELOC_LO16
, AT
);
9683 offset_expr
.X_add_number
+= 4;
9684 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9685 BFD_RELOC_LO16
, AT
);
9688 mips_optimize
= hold_mips_optimize
;
9690 else if (mips_big_got
)
9694 /* If this is a reference to an external symbol, we want
9695 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9697 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9702 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9704 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9705 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9706 If there is a base register we add it to $at before the
9707 lwc1 instructions. If there is a constant we include it
9708 in the lwc1 instructions. */
9710 expr1
.X_add_number
= offset_expr
.X_add_number
;
9711 offset_expr
.X_add_number
= 0;
9712 if (expr1
.X_add_number
< -0x8000
9713 || expr1
.X_add_number
>= 0x8000 - 4)
9714 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9715 gpdelay
= reg_needs_delay (mips_gp_register
);
9716 relax_start (offset_expr
.X_add_symbol
);
9717 macro_build (&offset_expr
, "lui", LUI_FMT
,
9718 AT
, BFD_RELOC_MIPS_GOT_HI16
);
9719 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9720 AT
, AT
, mips_gp_register
);
9721 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
9722 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
9725 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9726 /* Itbl support may require additional care here. */
9727 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9728 BFD_RELOC_LO16
, AT
);
9729 expr1
.X_add_number
+= 4;
9731 /* Set mips_optimize to 2 to avoid inserting an undesired
9733 hold_mips_optimize
= mips_optimize
;
9735 /* Itbl support may require additional care here. */
9736 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
9737 BFD_RELOC_LO16
, AT
);
9738 mips_optimize
= hold_mips_optimize
;
9739 expr1
.X_add_number
-= 4;
9742 offset_expr
.X_add_number
= expr1
.X_add_number
;
9744 macro_build (NULL
, "nop", "");
9745 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
9746 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9749 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
9750 /* Itbl support may require additional care here. */
9751 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
9752 BFD_RELOC_LO16
, AT
);
9753 offset_expr
.X_add_number
+= 4;
9755 /* Set mips_optimize to 2 to avoid inserting an undesired
9757 hold_mips_optimize
= mips_optimize
;
9759 /* Itbl support may require additional care here. */
9760 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
9761 BFD_RELOC_LO16
, AT
);
9762 mips_optimize
= hold_mips_optimize
;
9771 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
9774 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
9776 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
9777 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9779 if (!HAVE_64BIT_GPRS
)
9781 offset_expr
.X_add_number
+= 4;
9782 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
9783 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
9804 /* New code added to support COPZ instructions.
9805 This code builds table entries out of the macros in mip_opcodes.
9806 R4000 uses interlocks to handle coproc delays.
9807 Other chips (like the R3000) require nops to be inserted for delays.
9809 FIXME: Currently, we require that the user handle delays.
9810 In order to fill delay slots for non-interlocked chips,
9811 we must have a way to specify delays based on the coprocessor.
9812 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9813 What are the side-effects of the cop instruction?
9814 What cache support might we have and what are its effects?
9815 Both coprocessor & memory require delays. how long???
9816 What registers are read/set/modified?
9818 If an itbl is provided to interpret cop instructions,
9819 this knowledge can be encoded in the itbl spec. */
9833 gas_assert (!mips_opts
.micromips
);
9834 /* For now we just do C (same as Cz). The parameter will be
9835 stored in insn_opcode by mips_ip. */
9836 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
9840 move_register (dreg
, sreg
);
9844 gas_assert (mips_opts
.micromips
);
9845 gas_assert (mips_opts
.insn32
);
9846 dreg
= micromips_to_32_reg_h_map
[EXTRACT_OPERAND (1, MH
, *ip
)];
9847 breg
= micromips_to_32_reg_i_map
[EXTRACT_OPERAND (1, MI
, *ip
)];
9848 sreg
= micromips_to_32_reg_m_map
[EXTRACT_OPERAND (1, MM
, *ip
)];
9849 treg
= micromips_to_32_reg_n_map
[EXTRACT_OPERAND (1, MN
, *ip
)];
9850 move_register (dreg
, sreg
);
9851 move_register (breg
, treg
);
9857 if (mips_opts
.arch
== CPU_R5900
)
9859 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", dreg
, sreg
, treg
);
9863 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
9864 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9871 /* The MIPS assembler some times generates shifts and adds. I'm
9872 not trying to be that fancy. GCC should do this for us
9875 load_register (AT
, &imm_expr
, dbl
);
9876 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
9877 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9893 load_register (AT
, &imm_expr
, dbl
);
9894 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
9895 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9896 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, dreg
, dreg
, RA
);
9897 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9899 macro_build (NULL
, "tne", TRAP_FMT
, dreg
, AT
, 6);
9902 if (mips_opts
.micromips
)
9903 micromips_label_expr (&label_expr
);
9905 label_expr
.X_add_number
= 8;
9906 macro_build (&label_expr
, "beq", "s,t,p", dreg
, AT
);
9907 macro_build (NULL
, "nop", "");
9908 macro_build (NULL
, "break", BRK_FMT
, 6);
9909 if (mips_opts
.micromips
)
9910 micromips_add_label ();
9913 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9929 load_register (AT
, &imm_expr
, dbl
);
9930 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
9931 sreg
, imm
? AT
: treg
);
9932 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
9933 macro_build (NULL
, "mflo", MFHL_FMT
, dreg
);
9935 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
9938 if (mips_opts
.micromips
)
9939 micromips_label_expr (&label_expr
);
9941 label_expr
.X_add_number
= 8;
9942 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
9943 macro_build (NULL
, "nop", "");
9944 macro_build (NULL
, "break", BRK_FMT
, 6);
9945 if (mips_opts
.micromips
)
9946 micromips_add_label ();
9952 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
9963 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
9964 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
9968 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
9969 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
9970 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
9971 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
9975 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
9986 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
9987 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
9991 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
9992 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
9993 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
9994 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10003 if (imm_expr
.X_op
!= O_constant
)
10004 as_bad (_("Improper rotate count"));
10005 rot
= imm_expr
.X_add_number
& 0x3f;
10006 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10008 rot
= (64 - rot
) & 0x3f;
10010 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10012 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10017 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10020 l
= (rot
< 0x20) ? "dsll" : "dsll32";
10021 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
10024 macro_build (NULL
, l
, SHFT_FMT
, AT
, sreg
, rot
);
10025 macro_build (NULL
, rr
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10026 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10034 if (imm_expr
.X_op
!= O_constant
)
10035 as_bad (_("Improper rotate count"));
10036 rot
= imm_expr
.X_add_number
& 0x1f;
10037 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10039 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, (32 - rot
) & 0x1f);
10044 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10048 macro_build (NULL
, "sll", SHFT_FMT
, AT
, sreg
, rot
);
10049 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10050 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10055 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10057 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
10061 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, treg
);
10062 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
10063 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
10064 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10068 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10070 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
10074 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, treg
);
10075 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
10076 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
10077 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10086 if (imm_expr
.X_op
!= O_constant
)
10087 as_bad (_("Improper rotate count"));
10088 rot
= imm_expr
.X_add_number
& 0x3f;
10089 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
10092 macro_build (NULL
, "dror32", SHFT_FMT
, dreg
, sreg
, rot
- 32);
10094 macro_build (NULL
, "dror", SHFT_FMT
, dreg
, sreg
, rot
);
10099 macro_build (NULL
, "dsrl", SHFT_FMT
, dreg
, sreg
, 0);
10102 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
10103 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
10106 macro_build (NULL
, rr
, SHFT_FMT
, AT
, sreg
, rot
);
10107 macro_build (NULL
, l
, SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10108 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10116 if (imm_expr
.X_op
!= O_constant
)
10117 as_bad (_("Improper rotate count"));
10118 rot
= imm_expr
.X_add_number
& 0x1f;
10119 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
10121 macro_build (NULL
, "ror", SHFT_FMT
, dreg
, sreg
, rot
);
10126 macro_build (NULL
, "srl", SHFT_FMT
, dreg
, sreg
, 0);
10130 macro_build (NULL
, "srl", SHFT_FMT
, AT
, sreg
, rot
);
10131 macro_build (NULL
, "sll", SHFT_FMT
, dreg
, sreg
, (0x20 - rot
) & 0x1f);
10132 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
10138 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
10139 else if (treg
== 0)
10140 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10143 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10144 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10149 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10151 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10156 as_warn (_("Instruction %s: result is always false"),
10157 ip
->insn_mo
->name
);
10158 move_register (dreg
, 0);
10161 if (CPU_HAS_SEQ (mips_opts
.arch
)
10162 && -512 <= imm_expr
.X_add_number
10163 && imm_expr
.X_add_number
< 512)
10165 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
10166 (int) imm_expr
.X_add_number
);
10169 if (imm_expr
.X_op
== O_constant
10170 && imm_expr
.X_add_number
>= 0
10171 && imm_expr
.X_add_number
< 0x10000)
10173 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10175 else if (imm_expr
.X_op
== O_constant
10176 && imm_expr
.X_add_number
> -0x8000
10177 && imm_expr
.X_add_number
< 0)
10179 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10180 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10181 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10183 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10186 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10187 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
10192 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10193 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10196 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
10199 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
10205 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
10206 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10209 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
10211 if (imm_expr
.X_op
== O_constant
10212 && imm_expr
.X_add_number
>= -0x8000
10213 && imm_expr
.X_add_number
< 0x8000)
10215 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
10216 dreg
, sreg
, BFD_RELOC_LO16
);
10220 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10221 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
10225 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10228 case M_SGT
: /* sreg > treg <==> treg < sreg */
10234 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10237 case M_SGT_I
: /* sreg > I <==> I < sreg */
10244 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10245 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10248 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10254 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
10255 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10258 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10265 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10266 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
10267 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
10271 if (imm_expr
.X_op
== O_constant
10272 && imm_expr
.X_add_number
>= -0x8000
10273 && imm_expr
.X_add_number
< 0x8000)
10275 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10279 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10280 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
10284 if (imm_expr
.X_op
== O_constant
10285 && imm_expr
.X_add_number
>= -0x8000
10286 && imm_expr
.X_add_number
< 0x8000)
10288 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
10293 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10294 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
10299 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
10300 else if (treg
== 0)
10301 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10304 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
10305 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10310 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
10312 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
10317 as_warn (_("Instruction %s: result is always true"),
10318 ip
->insn_mo
->name
);
10319 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
10320 dreg
, 0, BFD_RELOC_LO16
);
10323 if (CPU_HAS_SEQ (mips_opts
.arch
)
10324 && -512 <= imm_expr
.X_add_number
10325 && imm_expr
.X_add_number
< 512)
10327 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
10328 (int) imm_expr
.X_add_number
);
10331 if (imm_expr
.X_op
== O_constant
10332 && imm_expr
.X_add_number
>= 0
10333 && imm_expr
.X_add_number
< 0x10000)
10335 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
10337 else if (imm_expr
.X_op
== O_constant
10338 && imm_expr
.X_add_number
> -0x8000
10339 && imm_expr
.X_add_number
< 0)
10341 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10342 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
10343 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10345 else if (CPU_HAS_SEQ (mips_opts
.arch
))
10348 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10349 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
10354 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10355 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
10358 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
10373 if (!mips_opts
.micromips
)
10375 if (imm_expr
.X_op
== O_constant
10376 && imm_expr
.X_add_number
> -0x200
10377 && imm_expr
.X_add_number
<= 0x200)
10379 macro_build (NULL
, s
, "t,r,.", dreg
, sreg
, -imm_expr
.X_add_number
);
10388 if (imm_expr
.X_op
== O_constant
10389 && imm_expr
.X_add_number
> -0x8000
10390 && imm_expr
.X_add_number
<= 0x8000)
10392 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10393 macro_build (&imm_expr
, s
, "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
10398 load_register (AT
, &imm_expr
, dbl
);
10399 macro_build (NULL
, s2
, "d,v,t", dreg
, sreg
, AT
);
10421 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
10422 macro_build (NULL
, s
, "s,t", sreg
, AT
);
10427 gas_assert (!mips_opts
.micromips
);
10428 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
10430 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
10431 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
10434 * Is the double cfc1 instruction a bug in the mips assembler;
10435 * or is there a reason for it?
10437 start_noreorder ();
10438 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10439 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
10440 macro_build (NULL
, "nop", "");
10441 expr1
.X_add_number
= 3;
10442 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
10443 expr1
.X_add_number
= 2;
10444 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
10445 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
10446 macro_build (NULL
, "nop", "");
10447 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
10449 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
10450 macro_build (NULL
, "nop", "");
10473 offbits
= (mips_opts
.micromips
? 12 : 16);
10481 offbits
= (mips_opts
.micromips
? 12 : 16);
10497 offbits
= (mips_opts
.micromips
? 12 : 16);
10506 offbits
= (mips_opts
.micromips
? 12 : 16);
10511 if (!ab
&& offset_expr
.X_add_number
>= 0x8000 - off
)
10512 as_bad (_("Operand overflow"));
10515 expr1
.X_add_number
= 0;
10520 load_address (tempreg
, ep
, &used_at
);
10522 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
10523 tempreg
, tempreg
, breg
);
10528 else if (offbits
== 12
10529 && (offset_expr
.X_op
!= O_constant
10530 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
)
10531 || !IS_SEXT_12BIT_NUM (offset_expr
.X_add_number
+ off
)))
10535 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
,
10536 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10541 else if (!ust
&& treg
== breg
)
10552 if (!target_big_endian
)
10553 ep
->X_add_number
+= off
;
10555 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10557 macro_build (NULL
, s
, "t,~(b)",
10558 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10560 if (!target_big_endian
)
10561 ep
->X_add_number
-= off
;
10563 ep
->X_add_number
+= off
;
10565 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10567 macro_build (NULL
, s2
, "t,~(b)",
10568 tempreg
, (unsigned long) ep
->X_add_number
, breg
);
10570 /* If necessary, move the result in tempreg to the final destination. */
10571 if (!ust
&& treg
!= tempreg
)
10573 /* Protect second load's delay slot. */
10575 move_register (treg
, tempreg
);
10581 if (target_big_endian
== ust
)
10582 ep
->X_add_number
+= off
;
10583 tempreg
= ust
|| ab
? treg
: AT
;
10584 macro_build (ep
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10586 /* For halfword transfers we need a temporary register to shuffle
10587 bytes. Unfortunately for M_USH_A we have none available before
10588 the next store as AT holds the base address. We deal with this
10589 case by clobbering TREG and then restoring it as with ULH. */
10590 tempreg
= ust
== ab
? treg
: AT
;
10592 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, treg
, 8);
10594 if (target_big_endian
== ust
)
10595 ep
->X_add_number
-= off
;
10597 ep
->X_add_number
+= off
;
10598 macro_build (ep
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
10600 /* For M_USH_A re-retrieve the LSB. */
10603 if (target_big_endian
)
10604 ep
->X_add_number
+= off
;
10606 ep
->X_add_number
-= off
;
10607 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
10609 /* For ULH and M_USH_A OR the LSB in. */
10612 tempreg
= !ab
? AT
: treg
;
10613 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
10614 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
10619 /* FIXME: Check if this is one of the itbl macros, since they
10620 are added dynamically. */
10621 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
10624 if (!mips_opts
.at
&& used_at
)
10625 as_bad (_("Macro used $at after \".set noat\""));
10628 /* Implement macros in mips16 mode. */
10631 mips16_macro (struct mips_cl_insn
*ip
)
10634 int xreg
, yreg
, zreg
, tmp
;
10637 const char *s
, *s2
, *s3
;
10639 mask
= ip
->insn_mo
->mask
;
10641 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
10642 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
10643 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
10645 expr1
.X_op
= O_constant
;
10646 expr1
.X_op_symbol
= NULL
;
10647 expr1
.X_add_symbol
= NULL
;
10648 expr1
.X_add_number
= 1;
10667 start_noreorder ();
10668 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
10669 expr1
.X_add_number
= 2;
10670 macro_build (&expr1
, "bnez", "x,p", yreg
);
10671 macro_build (NULL
, "break", "6", 7);
10673 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10674 since that causes an overflow. We should do that as well,
10675 but I don't see how to do the comparisons without a temporary
10678 macro_build (NULL
, s
, "x", zreg
);
10697 start_noreorder ();
10698 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
10699 expr1
.X_add_number
= 2;
10700 macro_build (&expr1
, "bnez", "x,p", yreg
);
10701 macro_build (NULL
, "break", "6", 7);
10703 macro_build (NULL
, s2
, "x", zreg
);
10709 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
10710 macro_build (NULL
, "mflo", "x", zreg
);
10718 if (imm_expr
.X_op
!= O_constant
)
10719 as_bad (_("Unsupported large constant"));
10720 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10721 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
10725 if (imm_expr
.X_op
!= O_constant
)
10726 as_bad (_("Unsupported large constant"));
10727 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10728 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
10732 if (imm_expr
.X_op
!= O_constant
)
10733 as_bad (_("Unsupported large constant"));
10734 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
10735 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
10757 goto do_reverse_branch
;
10761 goto do_reverse_branch
;
10773 goto do_reverse_branch
;
10784 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
10785 macro_build (&offset_expr
, s2
, "p");
10812 goto do_addone_branch_i
;
10817 goto do_addone_branch_i
;
10832 goto do_addone_branch_i
;
10838 do_addone_branch_i
:
10839 if (imm_expr
.X_op
!= O_constant
)
10840 as_bad (_("Unsupported large constant"));
10841 ++imm_expr
.X_add_number
;
10844 macro_build (&imm_expr
, s
, s3
, xreg
);
10845 macro_build (&offset_expr
, s2
, "p");
10849 expr1
.X_add_number
= 0;
10850 macro_build (&expr1
, "slti", "x,8", yreg
);
10852 move_register (xreg
, yreg
);
10853 expr1
.X_add_number
= 2;
10854 macro_build (&expr1
, "bteqz", "p");
10855 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
10859 /* For consistency checking, verify that all bits are specified either
10860 by the match/mask part of the instruction definition, or by the
10863 validate_mips_insn (const struct mips_opcode
*opc
)
10865 const char *p
= opc
->args
;
10867 unsigned long used_bits
= opc
->mask
;
10869 if ((used_bits
& opc
->match
) != opc
->match
)
10871 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10872 opc
->name
, opc
->args
);
10875 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10885 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
10886 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
10887 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
10888 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
10889 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10890 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10891 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10892 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10893 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10894 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10895 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
10896 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10897 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
10899 case 'J': USE_BITS (OP_MASK_CODE10
, OP_SH_CODE10
); break;
10900 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10901 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
10902 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10903 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10904 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
10905 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10906 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
10907 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
10908 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10909 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
10910 case 'z': USE_BITS (OP_MASK_RZ
, OP_SH_RZ
); break;
10911 case 'Z': USE_BITS (OP_MASK_FZ
, OP_SH_FZ
); break;
10912 case 'a': USE_BITS (OP_MASK_OFFSET_A
, OP_SH_OFFSET_A
); break;
10913 case 'b': USE_BITS (OP_MASK_OFFSET_B
, OP_SH_OFFSET_B
); break;
10914 case 'c': USE_BITS (OP_MASK_OFFSET_C
, OP_SH_OFFSET_C
); break;
10915 case 'j': USE_BITS (OP_MASK_EVAOFFSET
, OP_SH_EVAOFFSET
); break;
10918 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10919 c
, opc
->name
, opc
->args
);
10923 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10924 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10926 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
10927 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
10928 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10929 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10931 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10932 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
10934 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
10935 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10937 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
10938 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
10939 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
10940 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
10941 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10942 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
10943 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10944 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10945 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10946 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10947 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
10948 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
10949 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
10950 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
10951 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10952 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
10953 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10955 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
10956 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10957 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10958 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
10960 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10961 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
10962 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
10963 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10964 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10965 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10966 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
10967 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10968 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10971 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
10972 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
10973 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
10974 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
10975 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
10978 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
10979 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
10980 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
10981 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
10982 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
10983 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
10984 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
10985 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
10986 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
10987 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
10988 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
10989 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
10990 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
10991 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
10992 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
10993 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
10994 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
10995 case '\\': USE_BITS (OP_MASK_3BITPOS
, OP_SH_3BITPOS
); break;
10996 case '~': USE_BITS (OP_MASK_OFFSET12
, OP_SH_OFFSET12
); break;
10997 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
10999 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
11000 c
, opc
->name
, opc
->args
);
11004 if (used_bits
!= 0xffffffff)
11006 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
11007 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
11013 /* For consistency checking, verify that the length implied matches the
11014 major opcode and that all bits are specified either by the match/mask
11015 part of the instruction definition, or by the operand list. */
11018 validate_micromips_insn (const struct mips_opcode
*opc
)
11020 unsigned long match
= opc
->match
;
11021 unsigned long mask
= opc
->mask
;
11022 const char *p
= opc
->args
;
11023 unsigned long insn_bits
;
11024 unsigned long used_bits
;
11025 unsigned long major
;
11026 unsigned int length
;
11030 if ((mask
& match
) != match
)
11032 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
11033 opc
->name
, opc
->args
);
11036 length
= micromips_insn_length (opc
);
11037 if (length
!= 2 && length
!= 4)
11039 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
11040 "%s %s"), length
, opc
->name
, opc
->args
);
11043 major
= match
>> (10 + 8 * (length
- 2));
11044 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
11045 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
11047 as_bad (_("Internal error: bad microMIPS opcode "
11048 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
11052 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
11053 insn_bits
= 1 << 4 * length
;
11054 insn_bits
<<= 4 * length
;
11057 #define USE_BITS(field) \
11058 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
11069 case 'A': USE_BITS (EXTLSB
); break;
11070 case 'B': USE_BITS (INSMSB
); break;
11071 case 'C': USE_BITS (EXTMSBD
); break;
11072 case 'D': USE_BITS (RS
); USE_BITS (SEL
); break;
11073 case 'E': USE_BITS (EXTLSB
); break;
11074 case 'F': USE_BITS (INSMSB
); break;
11075 case 'G': USE_BITS (EXTMSBD
); break;
11076 case 'H': USE_BITS (EXTMSBD
); break;
11077 case 'j': USE_BITS (EVAOFFSET
); break;
11079 as_bad (_("Internal error: bad mips opcode "
11080 "(unknown extension operand type `%c%c'): %s %s"),
11081 e
, c
, opc
->name
, opc
->args
);
11089 case 'A': USE_BITS (IMMA
); break;
11090 case 'B': USE_BITS (IMMB
); break;
11091 case 'C': USE_BITS (IMMC
); break;
11092 case 'D': USE_BITS (IMMD
); break;
11093 case 'E': USE_BITS (IMME
); break;
11094 case 'F': USE_BITS (IMMF
); break;
11095 case 'G': USE_BITS (IMMG
); break;
11096 case 'H': USE_BITS (IMMH
); break;
11097 case 'I': USE_BITS (IMMI
); break;
11098 case 'J': USE_BITS (IMMJ
); break;
11099 case 'L': USE_BITS (IMML
); break;
11100 case 'M': USE_BITS (IMMM
); break;
11101 case 'N': USE_BITS (IMMN
); break;
11102 case 'O': USE_BITS (IMMO
); break;
11103 case 'P': USE_BITS (IMMP
); break;
11104 case 'Q': USE_BITS (IMMQ
); break;
11105 case 'U': USE_BITS (IMMU
); break;
11106 case 'W': USE_BITS (IMMW
); break;
11107 case 'X': USE_BITS (IMMX
); break;
11108 case 'Y': USE_BITS (IMMY
); break;
11111 case 'b': USE_BITS (MB
); break;
11112 case 'c': USE_BITS (MC
); break;
11113 case 'd': USE_BITS (MD
); break;
11114 case 'e': USE_BITS (ME
); break;
11115 case 'f': USE_BITS (MF
); break;
11116 case 'g': USE_BITS (MG
); break;
11117 case 'h': USE_BITS (MH
); break;
11118 case 'i': USE_BITS (MI
); break;
11119 case 'j': USE_BITS (MJ
); break;
11120 case 'l': USE_BITS (ML
); break;
11121 case 'm': USE_BITS (MM
); break;
11122 case 'n': USE_BITS (MN
); break;
11123 case 'p': USE_BITS (MP
); break;
11124 case 'q': USE_BITS (MQ
); break;
11132 as_bad (_("Internal error: bad mips opcode "
11133 "(unknown extension operand type `%c%c'): %s %s"),
11134 e
, c
, opc
->name
, opc
->args
);
11138 case '.': USE_BITS (OFFSET10
); break;
11139 case '1': USE_BITS (STYPE
); break;
11140 case '2': USE_BITS (BP
); break;
11141 case '3': USE_BITS (SA3
); break;
11142 case '4': USE_BITS (SA4
); break;
11143 case '5': USE_BITS (IMM8
); break;
11144 case '6': USE_BITS (RS
); break;
11145 case '7': USE_BITS (DSPACC
); break;
11146 case '8': USE_BITS (WRDSP
); break;
11147 case '0': USE_BITS (DSPSFT
); break;
11148 case '<': USE_BITS (SHAMT
); break;
11149 case '>': USE_BITS (SHAMT
); break;
11150 case '@': USE_BITS (IMM10
); break;
11151 case 'B': USE_BITS (CODE10
); break;
11152 case 'C': USE_BITS (COPZ
); break;
11153 case 'D': USE_BITS (FD
); break;
11154 case 'E': USE_BITS (RT
); break;
11155 case 'G': USE_BITS (RS
); break;
11156 case 'H': USE_BITS (SEL
); break;
11157 case 'K': USE_BITS (RS
); break;
11158 case 'M': USE_BITS (CCC
); break;
11159 case 'N': USE_BITS (BCC
); break;
11160 case 'R': USE_BITS (FR
); break;
11161 case 'S': USE_BITS (FS
); break;
11162 case 'T': USE_BITS (FT
); break;
11163 case 'V': USE_BITS (FS
); break;
11164 case '\\': USE_BITS (3BITPOS
); break;
11165 case '^': USE_BITS (RD
); break;
11166 case 'a': USE_BITS (TARGET
); break;
11167 case 'b': USE_BITS (RS
); break;
11168 case 'c': USE_BITS (CODE
); break;
11169 case 'd': USE_BITS (RD
); break;
11170 case 'h': USE_BITS (PREFX
); break;
11171 case 'i': USE_BITS (IMMEDIATE
); break;
11172 case 'j': USE_BITS (DELTA
); break;
11173 case 'k': USE_BITS (CACHE
); break;
11174 case 'n': USE_BITS (RT
); break;
11175 case 'o': USE_BITS (DELTA
); break;
11176 case 'p': USE_BITS (DELTA
); break;
11177 case 'q': USE_BITS (CODE2
); break;
11178 case 'r': USE_BITS (RS
); break;
11179 case 's': USE_BITS (RS
); break;
11180 case 't': USE_BITS (RT
); break;
11181 case 'u': USE_BITS (IMMEDIATE
); break;
11182 case 'v': USE_BITS (RS
); break;
11183 case 'w': USE_BITS (RT
); break;
11184 case 'y': USE_BITS (RS3
); break;
11186 case '|': USE_BITS (TRAP
); break;
11187 case '~': USE_BITS (OFFSET12
); break;
11189 as_bad (_("Internal error: bad microMIPS opcode "
11190 "(unknown operand type `%c'): %s %s"),
11191 c
, opc
->name
, opc
->args
);
11195 if (used_bits
!= insn_bits
)
11197 if (~used_bits
& insn_bits
)
11198 as_bad (_("Internal error: bad microMIPS opcode "
11199 "(bits 0x%lx undefined): %s %s"),
11200 ~used_bits
& insn_bits
, opc
->name
, opc
->args
);
11201 if (used_bits
& ~insn_bits
)
11202 as_bad (_("Internal error: bad microMIPS opcode "
11203 "(bits 0x%lx defined): %s %s"),
11204 used_bits
& ~insn_bits
, opc
->name
, opc
->args
);
11210 /* UDI immediates. */
11211 struct mips_immed
{
11213 unsigned int shift
;
11214 unsigned long mask
;
11218 static const struct mips_immed mips_immed
[] = {
11219 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
11220 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
11221 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
11222 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
11226 /* Check whether an odd floating-point register is allowed. */
11228 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
11230 const char *s
= insn
->name
;
11232 if (insn
->pinfo
== INSN_MACRO
)
11233 /* Let a macro pass, we'll catch it later when it is expanded. */
11236 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
) || (mips_opts
.arch
== CPU_R5900
))
11238 /* Allow odd registers for single-precision ops. */
11239 switch (insn
->pinfo
& (FP_S
| FP_D
))
11243 return 1; /* both single precision - ok */
11245 return 0; /* both double precision - fail */
11250 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11251 s
= strchr (insn
->name
, '.');
11253 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
11254 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
11257 /* Single-precision coprocessor loads and moves are OK too. */
11258 if ((insn
->pinfo
& FP_S
)
11259 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
11260 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
11266 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11267 taking bits from BIT up. */
11269 expr_const_in_range (expressionS
*ep
, offsetT min
, offsetT max
, int bit
)
11271 return (ep
->X_op
== O_constant
11272 && (ep
->X_add_number
& ((1 << bit
) - 1)) == 0
11273 && ep
->X_add_number
>= min
<< bit
11274 && ep
->X_add_number
< max
<< bit
);
11277 /* This routine assembles an instruction into its binary format. As a
11278 side effect, it sets one of the global variables imm_reloc or
11279 offset_reloc to the type of relocation to do if one of the operands
11280 is an address expression. */
11283 mips_ip (char *str
, struct mips_cl_insn
*ip
)
11285 bfd_boolean wrong_delay_slot_insns
= FALSE
;
11286 bfd_boolean need_delay_slot_ok
= TRUE
;
11287 struct mips_opcode
*firstinsn
= NULL
;
11288 const struct mips_opcode
*past
;
11289 struct hash_control
*hash
;
11293 struct mips_opcode
*insn
;
11295 unsigned int regno
;
11296 unsigned int lastregno
;
11297 unsigned int destregno
= 0;
11298 unsigned int lastpos
= 0;
11299 unsigned int limlo
, limhi
;
11302 offsetT min_range
, max_range
;
11306 unsigned int rtype
;
11312 if (mips_opts
.micromips
)
11314 hash
= micromips_op_hash
;
11315 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
11320 past
= &mips_opcodes
[NUMOPCODES
];
11322 forced_insn_length
= 0;
11325 /* We first try to match an instruction up to a space or to the end. */
11326 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
11329 /* Make a copy of the instruction so that we can fiddle with it. */
11330 name
= alloca (end
+ 1);
11331 memcpy (name
, str
, end
);
11336 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
11338 if (insn
!= NULL
|| !mips_opts
.micromips
)
11340 if (forced_insn_length
)
11343 /* See if there's an instruction size override suffix,
11344 either `16' or `32', at the end of the mnemonic proper,
11345 that defines the operation, i.e. before the first `.'
11346 character if any. Strip it and retry. */
11347 dot
= strchr (name
, '.');
11348 opend
= dot
!= NULL
? dot
- name
: end
;
11351 if (name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
11352 forced_insn_length
= 2;
11353 else if (name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
11354 forced_insn_length
= 4;
11357 memcpy (name
+ opend
- 2, name
+ opend
, end
- opend
+ 1);
11361 insn_error
= _("Unrecognized opcode");
11365 /* For microMIPS instructions placed in a fixed-length branch delay slot
11366 we make up to two passes over the relevant fragment of the opcode
11367 table. First we try instructions that meet the delay slot's length
11368 requirement. If none matched, then we retry with the remaining ones
11369 and if one matches, then we use it and then issue an appropriate
11370 warning later on. */
11371 argsStart
= s
= str
+ end
;
11374 bfd_boolean delay_slot_ok
;
11375 bfd_boolean size_ok
;
11378 gas_assert (strcmp (insn
->name
, name
) == 0);
11380 ok
= is_opcode_valid (insn
);
11381 size_ok
= is_size_valid (insn
);
11382 delay_slot_ok
= is_delay_slot_valid (insn
);
11383 if (!delay_slot_ok
&& !wrong_delay_slot_insns
)
11386 wrong_delay_slot_insns
= TRUE
;
11388 if (!ok
|| !size_ok
|| delay_slot_ok
!= need_delay_slot_ok
)
11390 static char buf
[256];
11392 if (insn
+ 1 < past
&& strcmp (insn
->name
, insn
[1].name
) == 0)
11397 if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
11399 gas_assert (firstinsn
);
11400 need_delay_slot_ok
= FALSE
;
11410 sprintf (buf
, _("Opcode not supported on this processor: %s (%s)"),
11411 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
11412 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11413 else if (mips_opts
.insn32
)
11414 sprintf (buf
, _("Opcode not supported in the `insn32' mode"));
11416 sprintf (buf
, _("Unrecognized %u-bit version of microMIPS opcode"),
11417 8 * forced_insn_length
);
11423 create_insn (ip
, insn
);
11426 lastregno
= 0xffffffff;
11427 for (args
= insn
->args
;; ++args
)
11431 s
+= strspn (s
, " \t");
11435 case '\0': /* end of args */
11441 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11442 code) or 14 (for microMIPS code). */
11443 my_getExpression (&imm_expr
, s
);
11444 check_absolute_expr (ip
, &imm_expr
);
11445 if ((unsigned long) imm_expr
.X_add_number
!= 1
11446 && (unsigned long) imm_expr
.X_add_number
!= 3)
11448 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11449 (unsigned long) imm_expr
.X_add_number
);
11451 INSERT_OPERAND (mips_opts
.micromips
,
11452 BP
, *ip
, imm_expr
.X_add_number
);
11453 imm_expr
.X_op
= O_absent
;
11458 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11459 code) or 13 (for microMIPS code). */
11461 unsigned long mask
= (mips_opts
.micromips
11462 ? MICROMIPSOP_MASK_SA3
: OP_MASK_SA3
);
11464 my_getExpression (&imm_expr
, s
);
11465 check_absolute_expr (ip
, &imm_expr
);
11466 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11467 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11468 mask
, (unsigned long) imm_expr
.X_add_number
);
11469 INSERT_OPERAND (mips_opts
.micromips
,
11470 SA3
, *ip
, imm_expr
.X_add_number
);
11471 imm_expr
.X_op
= O_absent
;
11477 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11478 code) or 12 (for microMIPS code). */
11480 unsigned long mask
= (mips_opts
.micromips
11481 ? MICROMIPSOP_MASK_SA4
: OP_MASK_SA4
);
11483 my_getExpression (&imm_expr
, s
);
11484 check_absolute_expr (ip
, &imm_expr
);
11485 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11486 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11487 mask
, (unsigned long) imm_expr
.X_add_number
);
11488 INSERT_OPERAND (mips_opts
.micromips
,
11489 SA4
, *ip
, imm_expr
.X_add_number
);
11490 imm_expr
.X_op
= O_absent
;
11496 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11497 code) or 13 (for microMIPS code). */
11499 unsigned long mask
= (mips_opts
.micromips
11500 ? MICROMIPSOP_MASK_IMM8
: OP_MASK_IMM8
);
11502 my_getExpression (&imm_expr
, s
);
11503 check_absolute_expr (ip
, &imm_expr
);
11504 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11505 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11506 mask
, (unsigned long) imm_expr
.X_add_number
);
11507 INSERT_OPERAND (mips_opts
.micromips
,
11508 IMM8
, *ip
, imm_expr
.X_add_number
);
11509 imm_expr
.X_op
= O_absent
;
11515 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11516 code) or 16 (for microMIPS code). */
11518 unsigned long mask
= (mips_opts
.micromips
11519 ? MICROMIPSOP_MASK_RS
: OP_MASK_RS
);
11521 my_getExpression (&imm_expr
, s
);
11522 check_absolute_expr (ip
, &imm_expr
);
11523 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11524 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11525 mask
, (unsigned long) imm_expr
.X_add_number
);
11526 INSERT_OPERAND (mips_opts
.micromips
,
11527 RS
, *ip
, imm_expr
.X_add_number
);
11528 imm_expr
.X_op
= O_absent
;
11534 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11535 or 14 (for microMIPS code). */
11536 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11537 && s
[3] >= '0' && s
[3] <= '3')
11539 regno
= s
[3] - '0';
11541 INSERT_OPERAND (mips_opts
.micromips
, DSPACC
, *ip
, regno
);
11545 as_bad (_("Invalid dsp acc register"));
11549 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11550 code) or 14 (for microMIPS code). */
11552 unsigned long mask
= (mips_opts
.micromips
11553 ? MICROMIPSOP_MASK_WRDSP
11556 my_getExpression (&imm_expr
, s
);
11557 check_absolute_expr (ip
, &imm_expr
);
11558 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11559 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11560 mask
, (unsigned long) imm_expr
.X_add_number
);
11561 INSERT_OPERAND (mips_opts
.micromips
,
11562 WRDSP
, *ip
, imm_expr
.X_add_number
);
11563 imm_expr
.X_op
= O_absent
;
11568 case '9': /* Four DSP accumulators in bits 21,22. */
11569 gas_assert (!mips_opts
.micromips
);
11570 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c'
11571 && s
[3] >= '0' && s
[3] <= '3')
11573 regno
= s
[3] - '0';
11575 INSERT_OPERAND (0, DSPACC_S
, *ip
, regno
);
11579 as_bad (_("Invalid dsp acc register"));
11583 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11584 code) or 16 (for microMIPS code). */
11586 long mask
= (mips_opts
.micromips
11587 ? MICROMIPSOP_MASK_DSPSFT
: OP_MASK_DSPSFT
);
11589 my_getExpression (&imm_expr
, s
);
11590 check_absolute_expr (ip
, &imm_expr
);
11591 min_range
= -((mask
+ 1) >> 1);
11592 max_range
= ((mask
+ 1) >> 1) - 1;
11593 if (imm_expr
.X_add_number
< min_range
11594 || imm_expr
.X_add_number
> max_range
)
11595 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11596 (long) min_range
, (long) max_range
,
11597 (long) imm_expr
.X_add_number
);
11598 INSERT_OPERAND (mips_opts
.micromips
,
11599 DSPSFT
, *ip
, imm_expr
.X_add_number
);
11600 imm_expr
.X_op
= O_absent
;
11605 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11606 gas_assert (!mips_opts
.micromips
);
11607 my_getExpression (&imm_expr
, s
);
11608 check_absolute_expr (ip
, &imm_expr
);
11609 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
11611 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11613 (unsigned long) imm_expr
.X_add_number
);
11615 INSERT_OPERAND (0, RDDSP
, *ip
, imm_expr
.X_add_number
);
11616 imm_expr
.X_op
= O_absent
;
11620 case ':': /* DSP 7-bit signed immediate in bit 19. */
11621 gas_assert (!mips_opts
.micromips
);
11622 my_getExpression (&imm_expr
, s
);
11623 check_absolute_expr (ip
, &imm_expr
);
11624 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
11625 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
11626 if (imm_expr
.X_add_number
< min_range
||
11627 imm_expr
.X_add_number
> max_range
)
11629 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11630 (long) min_range
, (long) max_range
,
11631 (long) imm_expr
.X_add_number
);
11633 INSERT_OPERAND (0, DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
11634 imm_expr
.X_op
= O_absent
;
11638 case '@': /* DSP 10-bit signed immediate in bit 16. */
11640 long mask
= (mips_opts
.micromips
11641 ? MICROMIPSOP_MASK_IMM10
: OP_MASK_IMM10
);
11643 my_getExpression (&imm_expr
, s
);
11644 check_absolute_expr (ip
, &imm_expr
);
11645 min_range
= -((mask
+ 1) >> 1);
11646 max_range
= ((mask
+ 1) >> 1) - 1;
11647 if (imm_expr
.X_add_number
< min_range
11648 || imm_expr
.X_add_number
> max_range
)
11649 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11650 (long) min_range
, (long) max_range
,
11651 (long) imm_expr
.X_add_number
);
11652 INSERT_OPERAND (mips_opts
.micromips
,
11653 IMM10
, *ip
, imm_expr
.X_add_number
);
11654 imm_expr
.X_op
= O_absent
;
11659 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11660 gas_assert (mips_opts
.micromips
);
11661 my_getExpression (&imm_expr
, s
);
11662 check_absolute_expr (ip
, &imm_expr
);
11663 if (imm_expr
.X_add_number
& ~MICROMIPSOP_MASK_RD
)
11664 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11665 MICROMIPSOP_MASK_RD
,
11666 (unsigned long) imm_expr
.X_add_number
);
11667 INSERT_OPERAND (1, RD
, *ip
, imm_expr
.X_add_number
);
11668 imm_expr
.X_op
= O_absent
;
11672 case '!': /* MT usermode flag bit. */
11673 gas_assert (!mips_opts
.micromips
);
11674 my_getExpression (&imm_expr
, s
);
11675 check_absolute_expr (ip
, &imm_expr
);
11676 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
11677 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11678 (unsigned long) imm_expr
.X_add_number
);
11679 INSERT_OPERAND (0, MT_U
, *ip
, imm_expr
.X_add_number
);
11680 imm_expr
.X_op
= O_absent
;
11684 case '$': /* MT load high flag bit. */
11685 gas_assert (!mips_opts
.micromips
);
11686 my_getExpression (&imm_expr
, s
);
11687 check_absolute_expr (ip
, &imm_expr
);
11688 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
11689 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11690 (unsigned long) imm_expr
.X_add_number
);
11691 INSERT_OPERAND (0, MT_H
, *ip
, imm_expr
.X_add_number
);
11692 imm_expr
.X_op
= O_absent
;
11696 case '*': /* Four DSP accumulators in bits 18,19. */
11697 gas_assert (!mips_opts
.micromips
);
11698 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11699 s
[3] >= '0' && s
[3] <= '3')
11701 regno
= s
[3] - '0';
11703 INSERT_OPERAND (0, MTACC_T
, *ip
, regno
);
11707 as_bad (_("Invalid dsp/smartmips acc register"));
11710 case '&': /* Four DSP accumulators in bits 13,14. */
11711 gas_assert (!mips_opts
.micromips
);
11712 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
11713 s
[3] >= '0' && s
[3] <= '3')
11715 regno
= s
[3] - '0';
11717 INSERT_OPERAND (0, MTACC_D
, *ip
, regno
);
11721 as_bad (_("Invalid dsp/smartmips acc register"));
11724 case '\\': /* 3-bit bit position. */
11726 unsigned long mask
= (mips_opts
.micromips
11727 ? MICROMIPSOP_MASK_3BITPOS
11728 : OP_MASK_3BITPOS
);
11730 my_getExpression (&imm_expr
, s
);
11731 check_absolute_expr (ip
, &imm_expr
);
11732 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11733 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11735 mask
, (unsigned long) imm_expr
.X_add_number
);
11736 INSERT_OPERAND (mips_opts
.micromips
,
11737 3BITPOS
, *ip
, imm_expr
.X_add_number
);
11738 imm_expr
.X_op
= O_absent
;
11752 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
11756 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
11760 gas_assert (!mips_opts
.micromips
);
11761 INSERT_OPERAND (0, FT
, *ip
, lastregno
);
11765 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
11771 /* Handle optional base register.
11772 Either the base register is omitted or
11773 we must have a left paren. */
11774 /* This is dependent on the next operand specifier
11775 is a base register specification. */
11776 gas_assert (args
[1] == 'b'
11777 || (mips_opts
.micromips
11779 && (args
[2] == 'l' || args
[2] == 'n'
11780 || args
[2] == 's' || args
[2] == 'a')));
11781 if (*s
== '\0' && args
[1] == 'b')
11783 /* Fall through. */
11785 case ')': /* These must match exactly. */
11790 case '[': /* These must match exactly. */
11792 gas_assert (!mips_opts
.micromips
);
11797 case '+': /* Opcode extension character. */
11800 case '1': /* UDI immediates. */
11804 gas_assert (!mips_opts
.micromips
);
11806 const struct mips_immed
*imm
= mips_immed
;
11808 while (imm
->type
&& imm
->type
!= *args
)
11812 my_getExpression (&imm_expr
, s
);
11813 check_absolute_expr (ip
, &imm_expr
);
11814 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
11816 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11817 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
11818 (unsigned long) imm_expr
.X_add_number
,
11819 (unsigned long) imm_expr
.X_add_number
);
11820 imm_expr
.X_add_number
&= imm
->mask
;
11822 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
11824 imm_expr
.X_op
= O_absent
;
11829 case 'J': /* 10-bit hypcall code. */
11830 gas_assert (!mips_opts
.micromips
);
11832 unsigned long mask
= OP_MASK_CODE10
;
11834 my_getExpression (&imm_expr
, s
);
11835 check_absolute_expr (ip
, &imm_expr
);
11836 if ((unsigned long) imm_expr
.X_add_number
> mask
)
11837 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11839 mask
, (unsigned long) imm_expr
.X_add_number
);
11840 INSERT_OPERAND (0, CODE10
, *ip
, imm_expr
.X_add_number
);
11841 imm_expr
.X_op
= O_absent
;
11846 case 'A': /* ins/ext position, becomes LSB. */
11855 my_getExpression (&imm_expr
, s
);
11856 check_absolute_expr (ip
, &imm_expr
);
11857 if ((unsigned long) imm_expr
.X_add_number
< limlo
11858 || (unsigned long) imm_expr
.X_add_number
> limhi
)
11860 as_bad (_("Improper position (%lu)"),
11861 (unsigned long) imm_expr
.X_add_number
);
11862 imm_expr
.X_add_number
= limlo
;
11864 lastpos
= imm_expr
.X_add_number
;
11865 INSERT_OPERAND (mips_opts
.micromips
,
11866 EXTLSB
, *ip
, imm_expr
.X_add_number
);
11867 imm_expr
.X_op
= O_absent
;
11871 case 'B': /* ins size, becomes MSB. */
11880 my_getExpression (&imm_expr
, s
);
11881 check_absolute_expr (ip
, &imm_expr
);
11882 /* Check for negative input so that small negative numbers
11883 will not succeed incorrectly. The checks against
11884 (pos+size) transitively check "size" itself,
11885 assuming that "pos" is reasonable. */
11886 if ((long) imm_expr
.X_add_number
< 0
11887 || ((unsigned long) imm_expr
.X_add_number
11889 || ((unsigned long) imm_expr
.X_add_number
11890 + lastpos
) > limhi
)
11892 as_bad (_("Improper insert size (%lu, position %lu)"),
11893 (unsigned long) imm_expr
.X_add_number
,
11894 (unsigned long) lastpos
);
11895 imm_expr
.X_add_number
= limlo
- lastpos
;
11897 INSERT_OPERAND (mips_opts
.micromips
, INSMSB
, *ip
,
11898 lastpos
+ imm_expr
.X_add_number
- 1);
11899 imm_expr
.X_op
= O_absent
;
11903 case 'C': /* ext size, becomes MSBD. */
11919 my_getExpression (&imm_expr
, s
);
11920 check_absolute_expr (ip
, &imm_expr
);
11921 /* The checks against (pos+size) don't transitively check
11922 "size" itself, assuming that "pos" is reasonable.
11923 We also need to check the lower bound of "size". */
11924 if ((long) imm_expr
.X_add_number
< sizelo
11925 || ((unsigned long) imm_expr
.X_add_number
11927 || ((unsigned long) imm_expr
.X_add_number
11928 + lastpos
) > limhi
)
11930 as_bad (_("Improper extract size (%lu, position %lu)"),
11931 (unsigned long) imm_expr
.X_add_number
,
11932 (unsigned long) lastpos
);
11933 imm_expr
.X_add_number
= limlo
- lastpos
;
11935 INSERT_OPERAND (mips_opts
.micromips
,
11936 EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
11937 imm_expr
.X_op
= O_absent
;
11942 /* +D is for disassembly only; never match. */
11946 /* "+I" is like "I", except that imm2_expr is used. */
11947 my_getExpression (&imm2_expr
, s
);
11948 if (imm2_expr
.X_op
!= O_big
11949 && imm2_expr
.X_op
!= O_constant
)
11950 insn_error
= _("absolute expression required");
11951 if (HAVE_32BIT_GPRS
)
11952 normalize_constant_expr (&imm2_expr
);
11956 case 'T': /* Coprocessor register. */
11957 gas_assert (!mips_opts
.micromips
);
11958 /* +T is for disassembly only; never match. */
11961 case 't': /* Coprocessor register number. */
11962 gas_assert (!mips_opts
.micromips
);
11963 if (s
[0] == '$' && ISDIGIT (s
[1]))
11973 while (ISDIGIT (*s
));
11975 as_bad (_("Invalid register number (%d)"), regno
);
11978 INSERT_OPERAND (0, RT
, *ip
, regno
);
11983 as_bad (_("Invalid coprocessor 0 register number"));
11987 /* bbit[01] and bbit[01]32 bit index. Give error if index
11988 is not in the valid range. */
11989 gas_assert (!mips_opts
.micromips
);
11990 my_getExpression (&imm_expr
, s
);
11991 check_absolute_expr (ip
, &imm_expr
);
11992 if ((unsigned) imm_expr
.X_add_number
> 31)
11994 as_bad (_("Improper bit index (%lu)"),
11995 (unsigned long) imm_expr
.X_add_number
);
11996 imm_expr
.X_add_number
= 0;
11998 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
);
11999 imm_expr
.X_op
= O_absent
;
12004 /* bbit[01] bit index when bbit is used but we generate
12005 bbit[01]32 because the index is over 32. Move to the
12006 next candidate if index is not in the valid range. */
12007 gas_assert (!mips_opts
.micromips
);
12008 my_getExpression (&imm_expr
, s
);
12009 check_absolute_expr (ip
, &imm_expr
);
12010 if ((unsigned) imm_expr
.X_add_number
< 32
12011 || (unsigned) imm_expr
.X_add_number
> 63)
12013 INSERT_OPERAND (0, BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
12014 imm_expr
.X_op
= O_absent
;
12019 /* cins, cins32, exts and exts32 position field. Give error
12020 if it's not in the valid range. */
12021 gas_assert (!mips_opts
.micromips
);
12022 my_getExpression (&imm_expr
, s
);
12023 check_absolute_expr (ip
, &imm_expr
);
12024 if ((unsigned) imm_expr
.X_add_number
> 31)
12026 as_bad (_("Improper position (%lu)"),
12027 (unsigned long) imm_expr
.X_add_number
);
12028 imm_expr
.X_add_number
= 0;
12030 /* Make the pos explicit to simplify +S. */
12031 lastpos
= imm_expr
.X_add_number
+ 32;
12032 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
);
12033 imm_expr
.X_op
= O_absent
;
12038 /* cins, cins32, exts and exts32 position field. Move to
12039 the next candidate if it's not in the valid range. */
12040 gas_assert (!mips_opts
.micromips
);
12041 my_getExpression (&imm_expr
, s
);
12042 check_absolute_expr (ip
, &imm_expr
);
12043 if ((unsigned) imm_expr
.X_add_number
< 32
12044 || (unsigned) imm_expr
.X_add_number
> 63)
12046 lastpos
= imm_expr
.X_add_number
;
12047 INSERT_OPERAND (0, CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
12048 imm_expr
.X_op
= O_absent
;
12053 /* cins and exts length-minus-one field. */
12054 gas_assert (!mips_opts
.micromips
);
12055 my_getExpression (&imm_expr
, s
);
12056 check_absolute_expr (ip
, &imm_expr
);
12057 if ((unsigned long) imm_expr
.X_add_number
> 31)
12059 as_bad (_("Improper size (%lu)"),
12060 (unsigned long) imm_expr
.X_add_number
);
12061 imm_expr
.X_add_number
= 0;
12063 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12064 imm_expr
.X_op
= O_absent
;
12069 /* cins32/exts32 and cins/exts aliasing cint32/exts32
12070 length-minus-one field. */
12071 gas_assert (!mips_opts
.micromips
);
12072 my_getExpression (&imm_expr
, s
);
12073 check_absolute_expr (ip
, &imm_expr
);
12074 if ((long) imm_expr
.X_add_number
< 0
12075 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
12077 as_bad (_("Improper size (%lu)"),
12078 (unsigned long) imm_expr
.X_add_number
);
12079 imm_expr
.X_add_number
= 0;
12081 INSERT_OPERAND (0, CINSLM1
, *ip
, imm_expr
.X_add_number
);
12082 imm_expr
.X_op
= O_absent
;
12087 /* seqi/snei immediate field. */
12088 gas_assert (!mips_opts
.micromips
);
12089 my_getExpression (&imm_expr
, s
);
12090 check_absolute_expr (ip
, &imm_expr
);
12091 if ((long) imm_expr
.X_add_number
< -512
12092 || (long) imm_expr
.X_add_number
>= 512)
12094 as_bad (_("Improper immediate (%ld)"),
12095 (long) imm_expr
.X_add_number
);
12096 imm_expr
.X_add_number
= 0;
12098 INSERT_OPERAND (0, SEQI
, *ip
, imm_expr
.X_add_number
);
12099 imm_expr
.X_op
= O_absent
;
12103 case 'a': /* 8-bit signed offset in bit 6 */
12104 gas_assert (!mips_opts
.micromips
);
12105 my_getExpression (&imm_expr
, s
);
12106 check_absolute_expr (ip
, &imm_expr
);
12107 min_range
= -((OP_MASK_OFFSET_A
+ 1) >> 1);
12108 max_range
= ((OP_MASK_OFFSET_A
+ 1) >> 1) - 1;
12109 if (imm_expr
.X_add_number
< min_range
12110 || imm_expr
.X_add_number
> max_range
)
12112 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12113 (long) min_range
, (long) max_range
,
12114 (long) imm_expr
.X_add_number
);
12116 INSERT_OPERAND (0, OFFSET_A
, *ip
, imm_expr
.X_add_number
);
12117 imm_expr
.X_op
= O_absent
;
12121 case 'b': /* 8-bit signed offset in bit 3 */
12122 gas_assert (!mips_opts
.micromips
);
12123 my_getExpression (&imm_expr
, s
);
12124 check_absolute_expr (ip
, &imm_expr
);
12125 min_range
= -((OP_MASK_OFFSET_B
+ 1) >> 1);
12126 max_range
= ((OP_MASK_OFFSET_B
+ 1) >> 1) - 1;
12127 if (imm_expr
.X_add_number
< min_range
12128 || imm_expr
.X_add_number
> max_range
)
12130 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12131 (long) min_range
, (long) max_range
,
12132 (long) imm_expr
.X_add_number
);
12134 INSERT_OPERAND (0, OFFSET_B
, *ip
, imm_expr
.X_add_number
);
12135 imm_expr
.X_op
= O_absent
;
12139 case 'c': /* 9-bit signed offset in bit 6 */
12140 gas_assert (!mips_opts
.micromips
);
12141 my_getExpression (&imm_expr
, s
);
12142 check_absolute_expr (ip
, &imm_expr
);
12143 min_range
= -((OP_MASK_OFFSET_C
+ 1) >> 1);
12144 max_range
= ((OP_MASK_OFFSET_C
+ 1) >> 1) - 1;
12145 /* We check the offset range before adjusted. */
12148 if (imm_expr
.X_add_number
< min_range
12149 || imm_expr
.X_add_number
> max_range
)
12151 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12152 (long) min_range
, (long) max_range
,
12153 (long) imm_expr
.X_add_number
);
12155 if (imm_expr
.X_add_number
& 0xf)
12157 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12158 (long) imm_expr
.X_add_number
);
12160 /* Right shift 4 bits to adjust the offset operand. */
12161 INSERT_OPERAND (0, OFFSET_C
, *ip
,
12162 imm_expr
.X_add_number
>> 4);
12163 imm_expr
.X_op
= O_absent
;
12168 gas_assert (!mips_opts
.micromips
);
12169 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
12171 if (regno
== AT
&& mips_opts
.at
)
12173 if (mips_opts
.at
== ATREG
)
12174 as_warn (_("used $at without \".set noat\""));
12176 as_warn (_("used $%u with \".set at=$%u\""),
12177 regno
, mips_opts
.at
);
12179 INSERT_OPERAND (0, RZ
, *ip
, regno
);
12183 gas_assert (!mips_opts
.micromips
);
12184 if (!reg_lookup (&s
, RTYPE_FPU
, ®no
))
12186 INSERT_OPERAND (0, FZ
, *ip
, regno
);
12193 /* Check whether there is only a single bracketed expression
12194 left. If so, it must be the base register and the
12195 constant must be zero. */
12196 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12199 /* If this value won't fit into the offset, then go find
12200 a macro that will generate a 16- or 32-bit offset code
12202 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
12203 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12204 || imm_expr
.X_add_number
>= 1 << shift
12205 || imm_expr
.X_add_number
< -1 << shift
))
12208 imm_expr
.X_op
= O_absent
;
12211 INSERT_OPERAND (mips_opts
.micromips
, EVAOFFSET
, *ip
,
12212 imm_expr
.X_add_number
);
12213 imm_expr
.X_op
= O_absent
;
12219 as_bad (_("Internal error: bad %s opcode "
12220 "(unknown extension operand type `+%c'): %s %s"),
12221 mips_opts
.micromips
? "microMIPS" : "MIPS",
12222 *args
, insn
->name
, insn
->args
);
12223 /* Further processing is fruitless. */
12228 case '.': /* 10-bit offset. */
12229 gas_assert (mips_opts
.micromips
);
12230 case '~': /* 12-bit offset. */
12232 int shift
= *args
== '.' ? 9 : 11;
12235 /* Check whether there is only a single bracketed expression
12236 left. If so, it must be the base register and the
12237 constant must be zero. */
12238 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
12241 /* If this value won't fit into the offset, then go find
12242 a macro that will generate a 16- or 32-bit offset code
12244 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
12245 if ((i
== 0 && (imm_expr
.X_op
!= O_constant
12246 || imm_expr
.X_add_number
>= 1 << shift
12247 || imm_expr
.X_add_number
< -1 << shift
))
12250 imm_expr
.X_op
= O_absent
;
12254 INSERT_OPERAND (1, OFFSET10
, *ip
, imm_expr
.X_add_number
);
12256 INSERT_OPERAND (mips_opts
.micromips
,
12257 OFFSET12
, *ip
, imm_expr
.X_add_number
);
12258 imm_expr
.X_op
= O_absent
;
12263 case '<': /* must be at least one digit */
12265 * According to the manual, if the shift amount is greater
12266 * than 31 or less than 0, then the shift amount should be
12267 * mod 32. In reality the mips assembler issues an error.
12268 * We issue a warning and mask out all but the low 5 bits.
12270 my_getExpression (&imm_expr
, s
);
12271 check_absolute_expr (ip
, &imm_expr
);
12272 if ((unsigned long) imm_expr
.X_add_number
> 31)
12273 as_warn (_("Improper shift amount (%lu)"),
12274 (unsigned long) imm_expr
.X_add_number
);
12275 INSERT_OPERAND (mips_opts
.micromips
,
12276 SHAMT
, *ip
, imm_expr
.X_add_number
);
12277 imm_expr
.X_op
= O_absent
;
12281 case '>': /* shift amount minus 32 */
12282 my_getExpression (&imm_expr
, s
);
12283 check_absolute_expr (ip
, &imm_expr
);
12284 if ((unsigned long) imm_expr
.X_add_number
< 32
12285 || (unsigned long) imm_expr
.X_add_number
> 63)
12287 INSERT_OPERAND (mips_opts
.micromips
,
12288 SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
12289 imm_expr
.X_op
= O_absent
;
12293 case 'k': /* CACHE code. */
12294 case 'h': /* PREFX code. */
12295 case '1': /* SYNC type. */
12296 my_getExpression (&imm_expr
, s
);
12297 check_absolute_expr (ip
, &imm_expr
);
12298 if ((unsigned long) imm_expr
.X_add_number
> 31)
12299 as_warn (_("Invalid value for `%s' (%lu)"),
12301 (unsigned long) imm_expr
.X_add_number
);
12305 if (mips_fix_cn63xxp1
12306 && !mips_opts
.micromips
12307 && strcmp ("pref", insn
->name
) == 0)
12308 switch (imm_expr
.X_add_number
)
12317 case 31: /* These are ok. */
12320 default: /* The rest must be changed to 28. */
12321 imm_expr
.X_add_number
= 28;
12324 INSERT_OPERAND (mips_opts
.micromips
,
12325 CACHE
, *ip
, imm_expr
.X_add_number
);
12328 INSERT_OPERAND (mips_opts
.micromips
,
12329 PREFX
, *ip
, imm_expr
.X_add_number
);
12332 INSERT_OPERAND (mips_opts
.micromips
,
12333 STYPE
, *ip
, imm_expr
.X_add_number
);
12336 imm_expr
.X_op
= O_absent
;
12340 case 'c': /* BREAK code. */
12342 unsigned long mask
= (mips_opts
.micromips
12343 ? MICROMIPSOP_MASK_CODE
12346 my_getExpression (&imm_expr
, s
);
12347 check_absolute_expr (ip
, &imm_expr
);
12348 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12349 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12351 mask
, (unsigned long) imm_expr
.X_add_number
);
12352 INSERT_OPERAND (mips_opts
.micromips
,
12353 CODE
, *ip
, imm_expr
.X_add_number
);
12354 imm_expr
.X_op
= O_absent
;
12359 case 'q': /* Lower BREAK code. */
12361 unsigned long mask
= (mips_opts
.micromips
12362 ? MICROMIPSOP_MASK_CODE2
12365 my_getExpression (&imm_expr
, s
);
12366 check_absolute_expr (ip
, &imm_expr
);
12367 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12368 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12370 mask
, (unsigned long) imm_expr
.X_add_number
);
12371 INSERT_OPERAND (mips_opts
.micromips
,
12372 CODE2
, *ip
, imm_expr
.X_add_number
);
12373 imm_expr
.X_op
= O_absent
;
12378 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12380 unsigned long mask
= (mips_opts
.micromips
12381 ? MICROMIPSOP_MASK_CODE10
12384 my_getExpression (&imm_expr
, s
);
12385 check_absolute_expr (ip
, &imm_expr
);
12386 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12387 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12389 mask
, (unsigned long) imm_expr
.X_add_number
);
12390 if (mips_opts
.micromips
)
12391 INSERT_OPERAND (1, CODE10
, *ip
, imm_expr
.X_add_number
);
12393 INSERT_OPERAND (0, CODE20
, *ip
, imm_expr
.X_add_number
);
12394 imm_expr
.X_op
= O_absent
;
12399 case 'C': /* 25- or 23-bit coprocessor code. */
12401 unsigned long mask
= (mips_opts
.micromips
12402 ? MICROMIPSOP_MASK_COPZ
12405 my_getExpression (&imm_expr
, s
);
12406 check_absolute_expr (ip
, &imm_expr
);
12407 if ((unsigned long) imm_expr
.X_add_number
> mask
)
12408 as_warn (_("Coproccesor code > %u bits (%lu)"),
12409 mips_opts
.micromips
? 23U : 25U,
12410 (unsigned long) imm_expr
.X_add_number
);
12411 INSERT_OPERAND (mips_opts
.micromips
,
12412 COPZ
, *ip
, imm_expr
.X_add_number
);
12413 imm_expr
.X_op
= O_absent
;
12418 case 'J': /* 19-bit WAIT code. */
12419 gas_assert (!mips_opts
.micromips
);
12420 my_getExpression (&imm_expr
, s
);
12421 check_absolute_expr (ip
, &imm_expr
);
12422 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
12424 as_warn (_("Illegal 19-bit code (%lu)"),
12425 (unsigned long) imm_expr
.X_add_number
);
12426 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
12428 INSERT_OPERAND (0, CODE19
, *ip
, imm_expr
.X_add_number
);
12429 imm_expr
.X_op
= O_absent
;
12433 case 'P': /* Performance register. */
12434 gas_assert (!mips_opts
.micromips
);
12435 my_getExpression (&imm_expr
, s
);
12436 check_absolute_expr (ip
, &imm_expr
);
12437 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
12438 as_warn (_("Invalid performance register (%lu)"),
12439 (unsigned long) imm_expr
.X_add_number
);
12440 if (imm_expr
.X_add_number
!= 0 && mips_opts
.arch
== CPU_R5900
12441 && (!strcmp(insn
->name
,"mfps") || !strcmp(insn
->name
,"mtps")))
12442 as_warn (_("Invalid performance register (%lu)"),
12443 (unsigned long) imm_expr
.X_add_number
);
12444 INSERT_OPERAND (0, PERFREG
, *ip
, imm_expr
.X_add_number
);
12445 imm_expr
.X_op
= O_absent
;
12449 case 'G': /* Coprocessor destination register. */
12451 unsigned long opcode
= ip
->insn_opcode
;
12452 unsigned long mask
;
12453 unsigned int types
;
12456 if (mips_opts
.micromips
)
12458 mask
= ~((MICROMIPSOP_MASK_RT
<< MICROMIPSOP_SH_RT
)
12459 | (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
)
12460 | (MICROMIPSOP_MASK_SEL
<< MICROMIPSOP_SH_SEL
));
12464 case 0x000000fc: /* mfc0 */
12465 case 0x000002fc: /* mtc0 */
12466 case 0x580000fc: /* dmfc0 */
12467 case 0x580002fc: /* dmtc0 */
12477 opcode
= (opcode
>> OP_SH_OP
) & OP_MASK_OP
;
12478 cop0
= opcode
== OP_OP_COP0
;
12480 types
= RTYPE_NUM
| (cop0
? RTYPE_CP0
: RTYPE_GP
);
12481 ok
= reg_lookup (&s
, types
, ®no
);
12482 if (mips_opts
.micromips
)
12483 INSERT_OPERAND (1, RS
, *ip
, regno
);
12485 INSERT_OPERAND (0, RD
, *ip
, regno
);
12494 case 'y': /* ALNV.PS source register. */
12495 gas_assert (mips_opts
.micromips
);
12497 case 'x': /* Ignore register name. */
12498 case 'U': /* Destination register (CLO/CLZ). */
12499 case 'g': /* Coprocessor destination register. */
12500 gas_assert (!mips_opts
.micromips
);
12501 case 'b': /* Base register. */
12502 case 'd': /* Destination register. */
12503 case 's': /* Source register. */
12504 case 't': /* Target register. */
12505 case 'r': /* Both target and source. */
12506 case 'v': /* Both dest and source. */
12507 case 'w': /* Both dest and target. */
12508 case 'E': /* Coprocessor target register. */
12509 case 'K': /* RDHWR destination register. */
12510 case 'z': /* Must be zero register. */
12513 if (*args
== 'E' || *args
== 'K')
12514 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
12517 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
12518 if (regno
== AT
&& mips_opts
.at
)
12520 if (mips_opts
.at
== ATREG
)
12521 as_warn (_("Used $at without \".set noat\""));
12523 as_warn (_("Used $%u with \".set at=$%u\""),
12524 regno
, mips_opts
.at
);
12534 if (c
== 'r' || c
== 'v' || c
== 'w')
12541 /* 'z' only matches $0. */
12542 if (c
== 'z' && regno
!= 0)
12545 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
12547 if (regno
== lastregno
)
12550 = _("Source and destination must be different");
12553 if (regno
== 31 && lastregno
== 0xffffffff)
12556 = _("A destination register must be supplied");
12560 /* Now that we have assembled one operand, we use the args
12561 string to figure out where it goes in the instruction. */
12568 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, regno
);
12572 if (mips_opts
.micromips
)
12573 INSERT_OPERAND (1, RS
, *ip
, regno
);
12575 INSERT_OPERAND (0, RD
, *ip
, regno
);
12580 INSERT_OPERAND (mips_opts
.micromips
, RD
, *ip
, regno
);
12584 gas_assert (!mips_opts
.micromips
);
12585 INSERT_OPERAND (0, RD
, *ip
, regno
);
12586 INSERT_OPERAND (0, RT
, *ip
, regno
);
12592 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, regno
);
12596 gas_assert (mips_opts
.micromips
);
12597 INSERT_OPERAND (1, RS3
, *ip
, regno
);
12601 /* This case exists because on the r3000 trunc
12602 expands into a macro which requires a gp
12603 register. On the r6000 or r4000 it is
12604 assembled into a single instruction which
12605 ignores the register. Thus the insn version
12606 is MIPS_ISA2 and uses 'x', and the macro
12607 version is MIPS_ISA1 and uses 't'. */
12611 /* This case is for the div instruction, which
12612 acts differently if the destination argument
12613 is $0. This only matches $0, and is checked
12614 outside the switch. */
12624 INSERT_OPERAND (mips_opts
.micromips
, RS
, *ip
, lastregno
);
12628 INSERT_OPERAND (mips_opts
.micromips
, RT
, *ip
, lastregno
);
12633 case 'O': /* MDMX alignment immediate constant. */
12634 gas_assert (!mips_opts
.micromips
);
12635 my_getExpression (&imm_expr
, s
);
12636 check_absolute_expr (ip
, &imm_expr
);
12637 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
12638 as_warn (_("Improper align amount (%ld), using low bits"),
12639 (long) imm_expr
.X_add_number
);
12640 INSERT_OPERAND (0, ALN
, *ip
, imm_expr
.X_add_number
);
12641 imm_expr
.X_op
= O_absent
;
12645 case 'Q': /* MDMX vector, element sel, or const. */
12648 /* MDMX Immediate. */
12649 gas_assert (!mips_opts
.micromips
);
12650 my_getExpression (&imm_expr
, s
);
12651 check_absolute_expr (ip
, &imm_expr
);
12652 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
12653 as_warn (_("Invalid MDMX Immediate (%ld)"),
12654 (long) imm_expr
.X_add_number
);
12655 INSERT_OPERAND (0, FT
, *ip
, imm_expr
.X_add_number
);
12656 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12657 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
12659 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
12660 imm_expr
.X_op
= O_absent
;
12664 /* Not MDMX Immediate. Fall through. */
12665 case 'X': /* MDMX destination register. */
12666 case 'Y': /* MDMX source register. */
12667 case 'Z': /* MDMX target register. */
12670 gas_assert (!mips_opts
.micromips
);
12671 case 'D': /* Floating point destination register. */
12672 case 'S': /* Floating point source register. */
12673 case 'T': /* Floating point target register. */
12674 case 'R': /* Floating point source register. */
12678 || ((mips_opts
.ase
& ASE_MDMX
)
12679 && (ip
->insn_mo
->pinfo
& FP_D
)
12680 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
12681 | INSN_COPROC_MEMORY_DELAY
12682 | INSN_LOAD_COPROC_DELAY
12683 | INSN_LOAD_MEMORY_DELAY
12684 | INSN_STORE_MEMORY
))))
12685 rtype
|= RTYPE_VEC
;
12687 if (reg_lookup (&s
, rtype
, ®no
))
12689 if ((regno
& 1) != 0
12691 && !mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
12692 as_warn (_("Float register should be even, was %d"),
12700 if (c
== 'V' || c
== 'W')
12711 INSERT_OPERAND (mips_opts
.micromips
, FD
, *ip
, regno
);
12717 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, regno
);
12721 /* This is like 'Z', but also needs to fix the MDMX
12722 vector/scalar select bits. Note that the
12723 scalar immediate case is handled above. */
12726 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
12727 int max_el
= (is_qh
? 3 : 7);
12729 my_getExpression(&imm_expr
, s
);
12730 check_absolute_expr (ip
, &imm_expr
);
12732 if (imm_expr
.X_add_number
> max_el
)
12733 as_bad (_("Bad element selector %ld"),
12734 (long) imm_expr
.X_add_number
);
12735 imm_expr
.X_add_number
&= max_el
;
12736 ip
->insn_opcode
|= (imm_expr
.X_add_number
12739 imm_expr
.X_op
= O_absent
;
12741 as_warn (_("Expecting ']' found '%s'"), s
);
12747 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
12748 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
12751 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
12754 /* Fall through. */
12758 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, regno
);
12762 INSERT_OPERAND (mips_opts
.micromips
, FR
, *ip
, regno
);
12772 INSERT_OPERAND (mips_opts
.micromips
, FS
, *ip
, lastregno
);
12776 INSERT_OPERAND (mips_opts
.micromips
, FT
, *ip
, lastregno
);
12782 my_getExpression (&imm_expr
, s
);
12783 if (imm_expr
.X_op
!= O_big
12784 && imm_expr
.X_op
!= O_constant
)
12785 insn_error
= _("absolute expression required");
12786 if (HAVE_32BIT_GPRS
)
12787 normalize_constant_expr (&imm_expr
);
12792 my_getExpression (&offset_expr
, s
);
12793 normalize_address_expr (&offset_expr
);
12794 *imm_reloc
= BFD_RELOC_32
;
12807 unsigned char temp
[8];
12809 unsigned int length
;
12814 /* These only appear as the last operand in an
12815 instruction, and every instruction that accepts
12816 them in any variant accepts them in all variants.
12817 This means we don't have to worry about backing out
12818 any changes if the instruction does not match.
12820 The difference between them is the size of the
12821 floating point constant and where it goes. For 'F'
12822 and 'L' the constant is 64 bits; for 'f' and 'l' it
12823 is 32 bits. Where the constant is placed is based
12824 on how the MIPS assembler does things:
12827 f -- immediate value
12830 The .lit4 and .lit8 sections are only used if
12831 permitted by the -G argument.
12833 The code below needs to know whether the target register
12834 is 32 or 64 bits wide. It relies on the fact 'f' and
12835 'F' are used with GPR-based instructions and 'l' and
12836 'L' are used with FPR-based instructions. */
12838 f64
= *args
== 'F' || *args
== 'L';
12839 using_gprs
= *args
== 'F' || *args
== 'f';
12841 save_in
= input_line_pointer
;
12842 input_line_pointer
= s
;
12843 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
12845 s
= input_line_pointer
;
12846 input_line_pointer
= save_in
;
12847 if (err
!= NULL
&& *err
!= '\0')
12849 as_bad (_("Bad floating point constant: %s"), err
);
12850 memset (temp
, '\0', sizeof temp
);
12851 length
= f64
? 8 : 4;
12854 gas_assert (length
== (unsigned) (f64
? 8 : 4));
12858 && (g_switch_value
< 4
12859 || (temp
[0] == 0 && temp
[1] == 0)
12860 || (temp
[2] == 0 && temp
[3] == 0))))
12862 imm_expr
.X_op
= O_constant
;
12863 if (!target_big_endian
)
12864 imm_expr
.X_add_number
= bfd_getl32 (temp
);
12866 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12868 else if (length
> 4
12869 && !mips_disable_float_construction
12870 /* Constants can only be constructed in GPRs and
12871 copied to FPRs if the GPRs are at least as wide
12872 as the FPRs. Force the constant into memory if
12873 we are using 64-bit FPRs but the GPRs are only
12876 || !(HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
12877 && ((temp
[0] == 0 && temp
[1] == 0)
12878 || (temp
[2] == 0 && temp
[3] == 0))
12879 && ((temp
[4] == 0 && temp
[5] == 0)
12880 || (temp
[6] == 0 && temp
[7] == 0)))
12882 /* The value is simple enough to load with a couple of
12883 instructions. If using 32-bit registers, set
12884 imm_expr to the high order 32 bits and offset_expr to
12885 the low order 32 bits. Otherwise, set imm_expr to
12886 the entire 64 bit constant. */
12887 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
12889 imm_expr
.X_op
= O_constant
;
12890 offset_expr
.X_op
= O_constant
;
12891 if (!target_big_endian
)
12893 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
12894 offset_expr
.X_add_number
= bfd_getl32 (temp
);
12898 imm_expr
.X_add_number
= bfd_getb32 (temp
);
12899 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
12901 if (offset_expr
.X_add_number
== 0)
12902 offset_expr
.X_op
= O_absent
;
12906 imm_expr
.X_op
= O_constant
;
12907 if (!target_big_endian
)
12908 imm_expr
.X_add_number
= bfd_getl64 (temp
);
12910 imm_expr
.X_add_number
= bfd_getb64 (temp
);
12915 const char *newname
;
12918 /* Switch to the right section. */
12920 subseg
= now_subseg
;
12923 default: /* unused default case avoids warnings. */
12925 newname
= RDATA_SECTION_NAME
;
12926 if (g_switch_value
>= 8)
12930 newname
= RDATA_SECTION_NAME
;
12933 gas_assert (g_switch_value
>= 4);
12937 new_seg
= subseg_new (newname
, (subsegT
) 0);
12938 bfd_set_section_flags (stdoutput
, new_seg
,
12943 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
12944 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12945 record_alignment (new_seg
, 4);
12947 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
12948 if (seg
== now_seg
)
12949 as_bad (_("Can't use floating point insn in this section"));
12951 /* Set the argument to the current address in the
12953 offset_expr
.X_op
= O_symbol
;
12954 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
12955 offset_expr
.X_add_number
= 0;
12957 /* Put the floating point number into the section. */
12958 p
= frag_more ((int) length
);
12959 memcpy (p
, temp
, length
);
12961 /* Switch back to the original section. */
12962 subseg_set (seg
, subseg
);
12967 case 'i': /* 16-bit unsigned immediate. */
12968 case 'j': /* 16-bit signed immediate. */
12969 *imm_reloc
= BFD_RELOC_LO16
;
12970 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
12973 offsetT minval
, maxval
;
12975 more
= (insn
+ 1 < past
12976 && strcmp (insn
->name
, insn
[1].name
) == 0);
12978 /* For compatibility with older assemblers, we accept
12979 0x8000-0xffff as signed 16-bit numbers when only
12980 signed numbers are allowed. */
12982 minval
= 0, maxval
= 0xffff;
12984 minval
= -0x8000, maxval
= 0x7fff;
12986 minval
= -0x8000, maxval
= 0xffff;
12988 if (imm_expr
.X_op
!= O_constant
12989 || imm_expr
.X_add_number
< minval
12990 || imm_expr
.X_add_number
> maxval
)
12994 if (imm_expr
.X_op
== O_constant
12995 || imm_expr
.X_op
== O_big
)
12996 as_bad (_("Expression out of range"));
13002 case 'o': /* 16-bit offset. */
13003 offset_reloc
[0] = BFD_RELOC_LO16
;
13004 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13005 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13007 /* Check whether there is only a single bracketed expression
13008 left. If so, it must be the base register and the
13009 constant must be zero. */
13010 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13012 offset_expr
.X_op
= O_constant
;
13013 offset_expr
.X_add_number
= 0;
13017 /* If this value won't fit into a 16 bit offset, then go
13018 find a macro that will generate the 32 bit offset
13020 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
13021 && (offset_expr
.X_op
!= O_constant
13022 || offset_expr
.X_add_number
>= 0x8000
13023 || offset_expr
.X_add_number
< -0x8000))
13029 case 'p': /* PC-relative offset. */
13030 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
13031 my_getExpression (&offset_expr
, s
);
13035 case 'u': /* Upper 16 bits. */
13036 *imm_reloc
= BFD_RELOC_LO16
;
13037 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
13038 && imm_expr
.X_op
== O_constant
13039 && (imm_expr
.X_add_number
< 0
13040 || imm_expr
.X_add_number
>= 0x10000))
13041 as_bad (_("lui expression (%lu) not in range 0..65535"),
13042 (unsigned long) imm_expr
.X_add_number
);
13046 case 'a': /* 26-bit address. */
13047 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
13048 my_getExpression (&offset_expr
, s
);
13052 case 'N': /* 3-bit branch condition code. */
13053 case 'M': /* 3-bit compare condition code. */
13055 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
13056 rtype
|= RTYPE_FCC
;
13057 if (!reg_lookup (&s
, rtype
, ®no
))
13059 if ((strcmp (str
+ strlen (str
) - 3, ".ps") == 0
13060 || strcmp (str
+ strlen (str
) - 5, "any2f") == 0
13061 || strcmp (str
+ strlen (str
) - 5, "any2t") == 0)
13062 && (regno
& 1) != 0)
13063 as_warn (_("Condition code register should be even for %s, "
13066 if ((strcmp (str
+ strlen (str
) - 5, "any4f") == 0
13067 || strcmp (str
+ strlen (str
) - 5, "any4t") == 0)
13068 && (regno
& 3) != 0)
13069 as_warn (_("Condition code register should be 0 or 4 for %s, "
13073 INSERT_OPERAND (mips_opts
.micromips
, BCC
, *ip
, regno
);
13075 INSERT_OPERAND (mips_opts
.micromips
, CCC
, *ip
, regno
);
13079 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
13090 while (ISDIGIT (*s
));
13093 c
= 8; /* Invalid sel value. */
13096 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13097 INSERT_OPERAND (mips_opts
.micromips
, SEL
, *ip
, c
);
13101 gas_assert (!mips_opts
.micromips
);
13102 /* Must be at least one digit. */
13103 my_getExpression (&imm_expr
, s
);
13104 check_absolute_expr (ip
, &imm_expr
);
13106 if ((unsigned long) imm_expr
.X_add_number
13107 > (unsigned long) OP_MASK_VECBYTE
)
13109 as_bad (_("bad byte vector index (%ld)"),
13110 (long) imm_expr
.X_add_number
);
13111 imm_expr
.X_add_number
= 0;
13114 INSERT_OPERAND (0, VECBYTE
, *ip
, imm_expr
.X_add_number
);
13115 imm_expr
.X_op
= O_absent
;
13120 gas_assert (!mips_opts
.micromips
);
13121 my_getExpression (&imm_expr
, s
);
13122 check_absolute_expr (ip
, &imm_expr
);
13124 if ((unsigned long) imm_expr
.X_add_number
13125 > (unsigned long) OP_MASK_VECALIGN
)
13127 as_bad (_("bad byte vector index (%ld)"),
13128 (long) imm_expr
.X_add_number
);
13129 imm_expr
.X_add_number
= 0;
13132 INSERT_OPERAND (0, VECALIGN
, *ip
, imm_expr
.X_add_number
);
13133 imm_expr
.X_op
= O_absent
;
13137 case 'm': /* Opcode extension character. */
13138 gas_assert (mips_opts
.micromips
);
13143 if (strncmp (s
, "$pc", 3) == 0)
13171 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
13172 if (regno
== AT
&& mips_opts
.at
)
13174 if (mips_opts
.at
== ATREG
)
13175 as_warn (_("Used $at without \".set noat\""));
13177 as_warn (_("Used $%u with \".set at=$%u\""),
13178 regno
, mips_opts
.at
);
13184 gas_assert (args
[1] == ',');
13190 gas_assert (args
[1] == ',');
13192 continue; /* Nothing to do. */
13198 if (c
== 'j' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
13200 if (regno
== lastregno
)
13203 = _("Source and destination must be different");
13206 if (regno
== 31 && lastregno
== 0xffffffff)
13209 = _("A destination register must be supplied");
13220 gas_assert (args
[1] == ',');
13227 gas_assert (args
[1] == ',');
13230 continue; /* Nothing to do. */
13234 /* Make sure regno is the same as lastregno. */
13235 if (c
== 't' && regno
!= lastregno
)
13238 /* Make sure regno is the same as destregno. */
13239 if (c
== 'x' && regno
!= destregno
)
13242 /* We need to save regno, before regno maps to the
13243 microMIPS register encoding. */
13253 regno
= ILLEGAL_REG
;
13257 regno
= mips32_to_micromips_reg_b_map
[regno
];
13261 regno
= mips32_to_micromips_reg_c_map
[regno
];
13265 regno
= mips32_to_micromips_reg_d_map
[regno
];
13269 regno
= mips32_to_micromips_reg_e_map
[regno
];
13273 regno
= mips32_to_micromips_reg_f_map
[regno
];
13277 regno
= mips32_to_micromips_reg_g_map
[regno
];
13281 regno
= mips32_to_micromips_reg_h_map
[regno
];
13285 switch (EXTRACT_OPERAND (1, MI
, *ip
))
13290 else if (regno
== 22)
13292 else if (regno
== 5)
13294 else if (regno
== 6)
13296 else if (regno
== 7)
13299 regno
= ILLEGAL_REG
;
13305 else if (regno
== 7)
13308 regno
= ILLEGAL_REG
;
13315 regno
= ILLEGAL_REG
;
13319 regno
= ILLEGAL_REG
;
13325 regno
= mips32_to_micromips_reg_l_map
[regno
];
13329 regno
= mips32_to_micromips_reg_m_map
[regno
];
13333 regno
= mips32_to_micromips_reg_n_map
[regno
];
13337 regno
= mips32_to_micromips_reg_q_map
[regno
];
13342 regno
= ILLEGAL_REG
;
13347 regno
= ILLEGAL_REG
;
13352 regno
= ILLEGAL_REG
;
13355 case 'j': /* Do nothing. */
13365 if (regno
== ILLEGAL_REG
)
13371 INSERT_OPERAND (1, MB
, *ip
, regno
);
13375 INSERT_OPERAND (1, MC
, *ip
, regno
);
13379 INSERT_OPERAND (1, MD
, *ip
, regno
);
13383 INSERT_OPERAND (1, ME
, *ip
, regno
);
13387 INSERT_OPERAND (1, MF
, *ip
, regno
);
13391 INSERT_OPERAND (1, MG
, *ip
, regno
);
13395 INSERT_OPERAND (1, MH
, *ip
, regno
);
13399 INSERT_OPERAND (1, MI
, *ip
, regno
);
13403 INSERT_OPERAND (1, MJ
, *ip
, regno
);
13407 INSERT_OPERAND (1, ML
, *ip
, regno
);
13411 INSERT_OPERAND (1, MM
, *ip
, regno
);
13415 INSERT_OPERAND (1, MN
, *ip
, regno
);
13419 INSERT_OPERAND (1, MP
, *ip
, regno
);
13423 INSERT_OPERAND (1, MQ
, *ip
, regno
);
13426 case 'a': /* Do nothing. */
13427 case 's': /* Do nothing. */
13428 case 't': /* Do nothing. */
13429 case 'x': /* Do nothing. */
13430 case 'y': /* Do nothing. */
13431 case 'z': /* Do nothing. */
13441 bfd_reloc_code_real_type r
[3];
13445 /* Check whether there is only a single bracketed
13446 expression left. If so, it must be the base register
13447 and the constant must be zero. */
13448 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13450 INSERT_OPERAND (1, IMMA
, *ip
, 0);
13454 if (my_getSmallExpression (&ep
, r
, s
) > 0
13455 || !expr_const_in_range (&ep
, -64, 64, 2))
13458 imm
= ep
.X_add_number
>> 2;
13459 INSERT_OPERAND (1, IMMA
, *ip
, imm
);
13466 bfd_reloc_code_real_type r
[3];
13470 if (my_getSmallExpression (&ep
, r
, s
) > 0
13471 || ep
.X_op
!= O_constant
)
13474 for (imm
= 0; imm
< 8; imm
++)
13475 if (micromips_imm_b_map
[imm
] == ep
.X_add_number
)
13480 INSERT_OPERAND (1, IMMB
, *ip
, imm
);
13487 bfd_reloc_code_real_type r
[3];
13491 if (my_getSmallExpression (&ep
, r
, s
) > 0
13492 || ep
.X_op
!= O_constant
)
13495 for (imm
= 0; imm
< 16; imm
++)
13496 if (micromips_imm_c_map
[imm
] == ep
.X_add_number
)
13501 INSERT_OPERAND (1, IMMC
, *ip
, imm
);
13506 case 'D': /* pc relative offset */
13507 case 'E': /* pc relative offset */
13508 my_getExpression (&offset_expr
, s
);
13509 if (offset_expr
.X_op
== O_register
)
13512 if (!forced_insn_length
)
13513 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
13515 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
13517 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
13523 bfd_reloc_code_real_type r
[3];
13527 if (my_getSmallExpression (&ep
, r
, s
) > 0
13528 || !expr_const_in_range (&ep
, 0, 16, 0))
13531 imm
= ep
.X_add_number
;
13532 INSERT_OPERAND (1, IMMF
, *ip
, imm
);
13539 bfd_reloc_code_real_type r
[3];
13543 /* Check whether there is only a single bracketed
13544 expression left. If so, it must be the base register
13545 and the constant must be zero. */
13546 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13548 INSERT_OPERAND (1, IMMG
, *ip
, 0);
13552 if (my_getSmallExpression (&ep
, r
, s
) > 0
13553 || !expr_const_in_range (&ep
, -1, 15, 0))
13556 imm
= ep
.X_add_number
& 15;
13557 INSERT_OPERAND (1, IMMG
, *ip
, imm
);
13564 bfd_reloc_code_real_type r
[3];
13568 /* Check whether there is only a single bracketed
13569 expression left. If so, it must be the base register
13570 and the constant must be zero. */
13571 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13573 INSERT_OPERAND (1, IMMH
, *ip
, 0);
13577 if (my_getSmallExpression (&ep
, r
, s
) > 0
13578 || !expr_const_in_range (&ep
, 0, 16, 1))
13581 imm
= ep
.X_add_number
>> 1;
13582 INSERT_OPERAND (1, IMMH
, *ip
, imm
);
13589 bfd_reloc_code_real_type r
[3];
13593 if (my_getSmallExpression (&ep
, r
, s
) > 0
13594 || !expr_const_in_range (&ep
, -1, 127, 0))
13597 imm
= ep
.X_add_number
& 127;
13598 INSERT_OPERAND (1, IMMI
, *ip
, imm
);
13605 bfd_reloc_code_real_type r
[3];
13609 /* Check whether there is only a single bracketed
13610 expression left. If so, it must be the base register
13611 and the constant must be zero. */
13612 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13614 INSERT_OPERAND (1, IMMJ
, *ip
, 0);
13618 if (my_getSmallExpression (&ep
, r
, s
) > 0
13619 || !expr_const_in_range (&ep
, 0, 16, 2))
13622 imm
= ep
.X_add_number
>> 2;
13623 INSERT_OPERAND (1, IMMJ
, *ip
, imm
);
13630 bfd_reloc_code_real_type r
[3];
13634 /* Check whether there is only a single bracketed
13635 expression left. If so, it must be the base register
13636 and the constant must be zero. */
13637 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13639 INSERT_OPERAND (1, IMML
, *ip
, 0);
13643 if (my_getSmallExpression (&ep
, r
, s
) > 0
13644 || !expr_const_in_range (&ep
, 0, 16, 0))
13647 imm
= ep
.X_add_number
;
13648 INSERT_OPERAND (1, IMML
, *ip
, imm
);
13655 bfd_reloc_code_real_type r
[3];
13659 if (my_getSmallExpression (&ep
, r
, s
) > 0
13660 || !expr_const_in_range (&ep
, 1, 9, 0))
13663 imm
= ep
.X_add_number
& 7;
13664 INSERT_OPERAND (1, IMMM
, *ip
, imm
);
13669 case 'N': /* Register list for lwm and swm. */
13671 /* A comma-separated list of registers and/or
13672 dash-separated contiguous ranges including
13673 both ra and a set of one or more registers
13674 starting at s0 up to s3 which have to be
13681 and any permutations of these. */
13682 unsigned int reglist
;
13685 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13688 if ((reglist
& 0xfff1ffff) != 0x80010000)
13691 reglist
= (reglist
>> 17) & 7;
13693 if ((reglist
& -reglist
) != reglist
)
13696 imm
= ffs (reglist
) - 1;
13697 INSERT_OPERAND (1, IMMN
, *ip
, imm
);
13701 case 'O': /* sdbbp 4-bit code. */
13703 bfd_reloc_code_real_type r
[3];
13707 if (my_getSmallExpression (&ep
, r
, s
) > 0
13708 || !expr_const_in_range (&ep
, 0, 16, 0))
13711 imm
= ep
.X_add_number
;
13712 INSERT_OPERAND (1, IMMO
, *ip
, imm
);
13719 bfd_reloc_code_real_type r
[3];
13723 if (my_getSmallExpression (&ep
, r
, s
) > 0
13724 || !expr_const_in_range (&ep
, 0, 32, 2))
13727 imm
= ep
.X_add_number
>> 2;
13728 INSERT_OPERAND (1, IMMP
, *ip
, imm
);
13735 bfd_reloc_code_real_type r
[3];
13739 if (my_getSmallExpression (&ep
, r
, s
) > 0
13740 || !expr_const_in_range (&ep
, -0x400000, 0x400000, 2))
13743 imm
= ep
.X_add_number
>> 2;
13744 INSERT_OPERAND (1, IMMQ
, *ip
, imm
);
13751 bfd_reloc_code_real_type r
[3];
13755 /* Check whether there is only a single bracketed
13756 expression left. If so, it must be the base register
13757 and the constant must be zero. */
13758 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
13760 INSERT_OPERAND (1, IMMU
, *ip
, 0);
13764 if (my_getSmallExpression (&ep
, r
, s
) > 0
13765 || !expr_const_in_range (&ep
, 0, 32, 2))
13768 imm
= ep
.X_add_number
>> 2;
13769 INSERT_OPERAND (1, IMMU
, *ip
, imm
);
13776 bfd_reloc_code_real_type r
[3];
13780 if (my_getSmallExpression (&ep
, r
, s
) > 0
13781 || !expr_const_in_range (&ep
, 0, 64, 2))
13784 imm
= ep
.X_add_number
>> 2;
13785 INSERT_OPERAND (1, IMMW
, *ip
, imm
);
13792 bfd_reloc_code_real_type r
[3];
13796 if (my_getSmallExpression (&ep
, r
, s
) > 0
13797 || !expr_const_in_range (&ep
, -8, 8, 0))
13800 imm
= ep
.X_add_number
;
13801 INSERT_OPERAND (1, IMMX
, *ip
, imm
);
13808 bfd_reloc_code_real_type r
[3];
13812 if (my_getSmallExpression (&ep
, r
, s
) > 0
13813 || expr_const_in_range (&ep
, -2, 2, 2)
13814 || !expr_const_in_range (&ep
, -258, 258, 2))
13817 imm
= ep
.X_add_number
>> 2;
13818 imm
= ((imm
>> 1) & ~0xff) | (imm
& 0xff);
13819 INSERT_OPERAND (1, IMMY
, *ip
, imm
);
13826 bfd_reloc_code_real_type r
[3];
13829 if (my_getSmallExpression (&ep
, r
, s
) > 0
13830 || !expr_const_in_range (&ep
, 0, 1, 0))
13837 as_bad (_("Internal error: bad microMIPS opcode "
13838 "(unknown extension operand type `m%c'): %s %s"),
13839 *args
, insn
->name
, insn
->args
);
13840 /* Further processing is fruitless. */
13845 case 'n': /* Register list for 32-bit lwm and swm. */
13846 gas_assert (mips_opts
.micromips
);
13848 /* A comma-separated list of registers and/or
13849 dash-separated contiguous ranges including
13850 at least one of ra and a set of one or more
13851 registers starting at s0 up to s7 and then
13852 s8 which have to be consecutive, e.g.:
13860 and any permutations of these. */
13861 unsigned int reglist
;
13865 if (!reglist_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®list
))
13868 if ((reglist
& 0x3f00ffff) != 0)
13871 ra
= (reglist
>> 27) & 0x10;
13872 reglist
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
13874 if ((reglist
& -reglist
) != reglist
)
13877 imm
= (ffs (reglist
) - 1) | ra
;
13878 INSERT_OPERAND (1, RT
, *ip
, imm
);
13879 imm_expr
.X_op
= O_absent
;
13883 case '|': /* 4-bit trap code. */
13884 gas_assert (mips_opts
.micromips
);
13885 my_getExpression (&imm_expr
, s
);
13886 check_absolute_expr (ip
, &imm_expr
);
13887 if ((unsigned long) imm_expr
.X_add_number
13888 > MICROMIPSOP_MASK_TRAP
)
13889 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13890 (unsigned long) imm_expr
.X_add_number
,
13891 ip
->insn_mo
->name
);
13892 INSERT_OPERAND (1, TRAP
, *ip
, imm_expr
.X_add_number
);
13893 imm_expr
.X_op
= O_absent
;
13898 as_bad (_("Bad char = '%c'\n"), *args
);
13903 /* Args don't match. */
13905 insn_error
= _("Illegal operands");
13906 if (insn
+ 1 < past
&& !strcmp (insn
->name
, insn
[1].name
))
13911 else if (wrong_delay_slot_insns
&& need_delay_slot_ok
)
13913 gas_assert (firstinsn
);
13914 need_delay_slot_ok
= FALSE
;
13923 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13925 /* This routine assembles an instruction into its binary format when
13926 assembling for the mips16. As a side effect, it sets one of the
13927 global variables imm_reloc or offset_reloc to the type of relocation
13928 to do if one of the operands is an address expression. It also sets
13929 forced_insn_length to the resulting instruction size in bytes if the
13930 user explicitly requested a small or extended instruction. */
13933 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
13937 struct mips_opcode
*insn
;
13939 unsigned int regno
;
13940 unsigned int lastregno
= 0;
13946 forced_insn_length
= 0;
13948 for (s
= str
; ISLOWER (*s
); ++s
)
13960 if (s
[1] == 't' && s
[2] == ' ')
13963 forced_insn_length
= 2;
13967 else if (s
[1] == 'e' && s
[2] == ' ')
13970 forced_insn_length
= 4;
13974 /* Fall through. */
13976 insn_error
= _("unknown opcode");
13980 if (mips_opts
.noautoextend
&& !forced_insn_length
)
13981 forced_insn_length
= 2;
13983 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
13985 insn_error
= _("unrecognized opcode");
13994 gas_assert (strcmp (insn
->name
, str
) == 0);
13996 ok
= is_opcode_valid_16 (insn
);
13999 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
14000 && strcmp (insn
->name
, insn
[1].name
) == 0)
14009 static char buf
[100];
14011 _("Opcode not supported on this processor: %s (%s)"),
14012 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
14013 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
14020 create_insn (ip
, insn
);
14021 imm_expr
.X_op
= O_absent
;
14022 imm_reloc
[0] = BFD_RELOC_UNUSED
;
14023 imm_reloc
[1] = BFD_RELOC_UNUSED
;
14024 imm_reloc
[2] = BFD_RELOC_UNUSED
;
14025 imm2_expr
.X_op
= O_absent
;
14026 offset_expr
.X_op
= O_absent
;
14027 offset_reloc
[0] = BFD_RELOC_UNUSED
;
14028 offset_reloc
[1] = BFD_RELOC_UNUSED
;
14029 offset_reloc
[2] = BFD_RELOC_UNUSED
;
14030 for (args
= insn
->args
; 1; ++args
)
14037 /* In this switch statement we call break if we did not find
14038 a match, continue if we did find a match, or return if we
14049 /* Stuff the immediate value in now, if we can. */
14050 if (imm_expr
.X_op
== O_constant
14051 && *imm_reloc
> BFD_RELOC_UNUSED
14052 && insn
->pinfo
!= INSN_MACRO
14053 && calculate_reloc (*offset_reloc
,
14054 imm_expr
.X_add_number
, &value
))
14056 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
14057 *offset_reloc
, value
, forced_insn_length
,
14059 imm_expr
.X_op
= O_absent
;
14060 *imm_reloc
= BFD_RELOC_UNUSED
;
14061 *offset_reloc
= BFD_RELOC_UNUSED
;
14075 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14078 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14094 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14096 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14100 /* Fall through. */
14111 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
14113 if (c
== 'v' || c
== 'w')
14116 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
14118 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
14129 if (c
== 'v' || c
== 'w')
14131 regno
= mips16_to_32_reg_map
[lastregno
];
14145 regno
= mips32_to_16_reg_map
[regno
];
14150 regno
= ILLEGAL_REG
;
14155 regno
= ILLEGAL_REG
;
14160 regno
= ILLEGAL_REG
;
14165 if (regno
== AT
&& mips_opts
.at
)
14167 if (mips_opts
.at
== ATREG
)
14168 as_warn (_("used $at without \".set noat\""));
14170 as_warn (_("used $%u with \".set at=$%u\""),
14171 regno
, mips_opts
.at
);
14179 if (regno
== ILLEGAL_REG
)
14186 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
14190 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
14193 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
14196 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
14202 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
14205 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
14206 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
14216 if (strncmp (s
, "$pc", 3) == 0)
14233 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
14236 if (imm_expr
.X_op
!= O_constant
)
14238 forced_insn_length
= 4;
14239 ip
->insn_opcode
|= MIPS16_EXTEND
;
14243 /* We need to relax this instruction. */
14244 *offset_reloc
= *imm_reloc
;
14245 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14250 *imm_reloc
= BFD_RELOC_UNUSED
;
14251 /* Fall through. */
14258 my_getExpression (&imm_expr
, s
);
14259 if (imm_expr
.X_op
== O_register
)
14261 /* What we thought was an expression turned out to
14264 if (s
[0] == '(' && args
[1] == '(')
14266 /* It looks like the expression was omitted
14267 before a register indirection, which means
14268 that the expression is implicitly zero. We
14269 still set up imm_expr, so that we handle
14270 explicit extensions correctly. */
14271 imm_expr
.X_op
= O_constant
;
14272 imm_expr
.X_add_number
= 0;
14273 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14280 /* We need to relax this instruction. */
14281 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14290 /* We use offset_reloc rather than imm_reloc for the PC
14291 relative operands. This lets macros with both
14292 immediate and address operands work correctly. */
14293 my_getExpression (&offset_expr
, s
);
14295 if (offset_expr
.X_op
== O_register
)
14298 /* We need to relax this instruction. */
14299 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
14303 case '6': /* break code */
14304 my_getExpression (&imm_expr
, s
);
14305 check_absolute_expr (ip
, &imm_expr
);
14306 if ((unsigned long) imm_expr
.X_add_number
> 63)
14307 as_warn (_("Invalid value for `%s' (%lu)"),
14309 (unsigned long) imm_expr
.X_add_number
);
14310 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
14311 imm_expr
.X_op
= O_absent
;
14315 case 'a': /* 26 bit address */
14316 my_getExpression (&offset_expr
, s
);
14318 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
14319 ip
->insn_opcode
<<= 16;
14322 case 'l': /* register list for entry macro */
14323 case 'L': /* register list for exit macro */
14333 unsigned int freg
, reg1
, reg2
;
14335 while (*s
== ' ' || *s
== ',')
14337 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14339 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
14343 as_bad (_("can't parse register list"));
14353 if (!reg_lookup (&s
, freg
? RTYPE_FPU
14354 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
14356 as_bad (_("invalid register list"));
14360 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
14362 mask
&= ~ (7 << 3);
14365 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
14367 mask
&= ~ (7 << 3);
14370 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
14371 mask
|= (reg2
- 3) << 3;
14372 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
14373 mask
|= (reg2
- 15) << 1;
14374 else if (reg1
== RA
&& reg2
== RA
)
14378 as_bad (_("invalid register list"));
14382 /* The mask is filled in in the opcode table for the
14383 benefit of the disassembler. We remove it before
14384 applying the actual mask. */
14385 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
14386 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
14390 case 'm': /* Register list for save insn. */
14391 case 'M': /* Register list for restore insn. */
14393 int opcode
= ip
->insn_opcode
;
14394 int framesz
= 0, seen_framesz
= 0;
14395 int nargs
= 0, statics
= 0, sregs
= 0;
14399 unsigned int reg1
, reg2
;
14401 SKIP_SPACE_TABS (s
);
14404 SKIP_SPACE_TABS (s
);
14406 my_getExpression (&imm_expr
, s
);
14407 if (imm_expr
.X_op
== O_constant
)
14409 /* Handle the frame size. */
14412 as_bad (_("more than one frame size in list"));
14416 framesz
= imm_expr
.X_add_number
;
14417 imm_expr
.X_op
= O_absent
;
14422 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
14424 as_bad (_("can't parse register list"));
14436 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
14439 as_bad (_("can't parse register list"));
14444 while (reg1
<= reg2
)
14446 if (reg1
>= 4 && reg1
<= 7)
14450 nargs
|= 1 << (reg1
- 4);
14452 /* statics $a0-$a3 */
14453 statics
|= 1 << (reg1
- 4);
14455 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
14458 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
14460 else if (reg1
== 31)
14462 /* Add $ra to insn. */
14467 as_bad (_("unexpected register in list"));
14475 /* Encode args/statics combination. */
14476 if (nargs
& statics
)
14477 as_bad (_("arg/static registers overlap"));
14478 else if (nargs
== 0xf)
14479 /* All $a0-$a3 are args. */
14480 opcode
|= MIPS16_ALL_ARGS
<< 16;
14481 else if (statics
== 0xf)
14482 /* All $a0-$a3 are statics. */
14483 opcode
|= MIPS16_ALL_STATICS
<< 16;
14486 int narg
= 0, nstat
= 0;
14488 /* Count arg registers. */
14489 while (nargs
& 0x1)
14495 as_bad (_("invalid arg register list"));
14497 /* Count static registers. */
14498 while (statics
& 0x8)
14500 statics
= (statics
<< 1) & 0xf;
14504 as_bad (_("invalid static register list"));
14506 /* Encode args/statics. */
14507 opcode
|= ((narg
<< 2) | nstat
) << 16;
14510 /* Encode $s0/$s1. */
14511 if (sregs
& (1 << 0)) /* $s0 */
14513 if (sregs
& (1 << 1)) /* $s1 */
14519 /* Count regs $s2-$s8. */
14527 as_bad (_("invalid static register list"));
14528 /* Encode $s2-$s8. */
14529 opcode
|= nsreg
<< 24;
14532 /* Encode frame size. */
14534 as_bad (_("missing frame size"));
14535 else if ((framesz
& 7) != 0 || framesz
< 0
14536 || framesz
> 0xff * 8)
14537 as_bad (_("invalid frame size"));
14538 else if (framesz
!= 128 || (opcode
>> 16) != 0)
14541 opcode
|= (((framesz
& 0xf0) << 16)
14542 | (framesz
& 0x0f));
14545 /* Finally build the instruction. */
14546 if ((opcode
>> 16) != 0 || framesz
== 0)
14547 opcode
|= MIPS16_EXTEND
;
14548 ip
->insn_opcode
= opcode
;
14552 case 'e': /* extend code */
14553 my_getExpression (&imm_expr
, s
);
14554 check_absolute_expr (ip
, &imm_expr
);
14555 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
14557 as_warn (_("Invalid value for `%s' (%lu)"),
14559 (unsigned long) imm_expr
.X_add_number
);
14560 imm_expr
.X_add_number
&= 0x7ff;
14562 ip
->insn_opcode
|= imm_expr
.X_add_number
;
14563 imm_expr
.X_op
= O_absent
;
14573 /* Args don't match. */
14574 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
14575 strcmp (insn
->name
, insn
[1].name
) == 0)
14582 insn_error
= _("illegal operands");
14588 /* This structure holds information we know about a mips16 immediate
14591 struct mips16_immed_operand
14593 /* The type code used in the argument string in the opcode table. */
14595 /* The number of bits in the short form of the opcode. */
14597 /* The number of bits in the extended form of the opcode. */
14599 /* The amount by which the short form is shifted when it is used;
14600 for example, the sw instruction has a shift count of 2. */
14602 /* The amount by which the short form is shifted when it is stored
14603 into the instruction code. */
14605 /* Non-zero if the short form is unsigned. */
14607 /* Non-zero if the extended form is unsigned. */
14609 /* Non-zero if the value is PC relative. */
14613 /* The mips16 immediate operand types. */
14615 static const struct mips16_immed_operand mips16_immed_operands
[] =
14617 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14618 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14619 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
14620 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
14621 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
14622 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14623 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14624 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14625 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
14626 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
14627 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14628 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14629 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
14630 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
14631 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14632 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
14633 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14634 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
14635 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
14636 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
14637 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
14640 #define MIPS16_NUM_IMMED \
14641 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14643 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14644 NBITS is the number of significant bits in VAL. */
14646 static unsigned long
14647 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14652 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14655 else if (nbits
== 15)
14657 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14662 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14665 return (extval
<< 16) | val
;
14668 /* Install immediate value VAL into MIPS16 instruction *INSN,
14669 extending it if necessary. The instruction in *INSN may
14670 already be extended.
14672 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14673 if none. In the former case, VAL is a 16-bit number with no
14674 defined signedness.
14676 TYPE is the type of the immediate field. USER_INSN_LENGTH
14677 is the length that the user requested, or 0 if none. */
14680 mips16_immed (char *file
, unsigned int line
, int type
,
14681 bfd_reloc_code_real_type reloc
, offsetT val
,
14682 unsigned int user_insn_length
, unsigned long *insn
)
14684 const struct mips16_immed_operand
*op
;
14685 int mintiny
, maxtiny
;
14687 op
= mips16_immed_operands
;
14688 while (op
->type
!= type
)
14691 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
14696 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
14699 maxtiny
= 1 << op
->nbits
;
14704 maxtiny
= (1 << op
->nbits
) - 1;
14706 if (reloc
!= BFD_RELOC_UNUSED
)
14711 mintiny
= - (1 << (op
->nbits
- 1));
14712 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
14713 if (reloc
!= BFD_RELOC_UNUSED
)
14714 val
= SEXT_16BIT (val
);
14717 /* Branch offsets have an implicit 0 in the lowest bit. */
14718 if (type
== 'p' || type
== 'q')
14721 if ((val
& ((1 << op
->shift
) - 1)) != 0
14722 || val
< (mintiny
<< op
->shift
)
14723 || val
> (maxtiny
<< op
->shift
))
14725 /* We need an extended instruction. */
14726 if (user_insn_length
== 2)
14727 as_bad_where (file
, line
, _("invalid unextended operand value"));
14729 *insn
|= MIPS16_EXTEND
;
14731 else if (user_insn_length
== 4)
14733 /* The operand doesn't force an unextended instruction to be extended.
14734 Warn if the user wanted an extended instruction anyway. */
14735 *insn
|= MIPS16_EXTEND
;
14736 as_warn_where (file
, line
,
14737 _("extended operand requested but not required"));
14740 if (mips16_opcode_length (*insn
) == 2)
14744 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
14745 insnval
<<= op
->op_shift
;
14750 long minext
, maxext
;
14752 if (reloc
== BFD_RELOC_UNUSED
)
14757 maxext
= (1 << op
->extbits
) - 1;
14761 minext
= - (1 << (op
->extbits
- 1));
14762 maxext
= (1 << (op
->extbits
- 1)) - 1;
14764 if (val
< minext
|| val
> maxext
)
14765 as_bad_where (file
, line
,
14766 _("operand value out of range for instruction"));
14769 *insn
|= mips16_immed_extend (val
, op
->extbits
);
14773 struct percent_op_match
14776 bfd_reloc_code_real_type reloc
;
14779 static const struct percent_op_match mips_percent_op
[] =
14781 {"%lo", BFD_RELOC_LO16
},
14782 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14783 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14784 {"%call16", BFD_RELOC_MIPS_CALL16
},
14785 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14786 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14787 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14788 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14789 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14790 {"%got", BFD_RELOC_MIPS_GOT16
},
14791 {"%gp_rel", BFD_RELOC_GPREL16
},
14792 {"%half", BFD_RELOC_16
},
14793 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14794 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14795 {"%neg", BFD_RELOC_MIPS_SUB
},
14796 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14797 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14798 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14799 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14800 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14801 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14802 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14803 {"%hi", BFD_RELOC_HI16_S
}
14806 static const struct percent_op_match mips16_percent_op
[] =
14808 {"%lo", BFD_RELOC_MIPS16_LO16
},
14809 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14810 {"%got", BFD_RELOC_MIPS16_GOT16
},
14811 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14812 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14813 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14814 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14815 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14816 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14817 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14818 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14819 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14823 /* Return true if *STR points to a relocation operator. When returning true,
14824 move *STR over the operator and store its relocation code in *RELOC.
14825 Leave both *STR and *RELOC alone when returning false. */
14828 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14830 const struct percent_op_match
*percent_op
;
14833 if (mips_opts
.mips16
)
14835 percent_op
= mips16_percent_op
;
14836 limit
= ARRAY_SIZE (mips16_percent_op
);
14840 percent_op
= mips_percent_op
;
14841 limit
= ARRAY_SIZE (mips_percent_op
);
14844 for (i
= 0; i
< limit
; i
++)
14845 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14847 int len
= strlen (percent_op
[i
].str
);
14849 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14852 *str
+= strlen (percent_op
[i
].str
);
14853 *reloc
= percent_op
[i
].reloc
;
14855 /* Check whether the output BFD supports this relocation.
14856 If not, issue an error and fall back on something safe. */
14857 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14859 as_bad (_("relocation %s isn't supported by the current ABI"),
14860 percent_op
[i
].str
);
14861 *reloc
= BFD_RELOC_UNUSED
;
14869 /* Parse string STR as a 16-bit relocatable operand. Store the
14870 expression in *EP and the relocations in the array starting
14871 at RELOC. Return the number of relocation operators used.
14873 On exit, EXPR_END points to the first character after the expression. */
14876 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14879 bfd_reloc_code_real_type reversed_reloc
[3];
14880 size_t reloc_index
, i
;
14881 int crux_depth
, str_depth
;
14884 /* Search for the start of the main expression, recoding relocations
14885 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14886 of the main expression and with CRUX_DEPTH containing the number
14887 of open brackets at that point. */
14894 crux_depth
= str_depth
;
14896 /* Skip over whitespace and brackets, keeping count of the number
14898 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14903 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14904 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14906 my_getExpression (ep
, crux
);
14909 /* Match every open bracket. */
14910 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14914 if (crux_depth
> 0)
14915 as_bad (_("unclosed '('"));
14919 if (reloc_index
!= 0)
14921 prev_reloc_op_frag
= frag_now
;
14922 for (i
= 0; i
< reloc_index
; i
++)
14923 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14926 return reloc_index
;
14930 my_getExpression (expressionS
*ep
, char *str
)
14934 save_in
= input_line_pointer
;
14935 input_line_pointer
= str
;
14937 expr_end
= input_line_pointer
;
14938 input_line_pointer
= save_in
;
14942 md_atof (int type
, char *litP
, int *sizeP
)
14944 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14948 md_number_to_chars (char *buf
, valueT val
, int n
)
14950 if (target_big_endian
)
14951 number_to_chars_bigendian (buf
, val
, n
);
14953 number_to_chars_littleendian (buf
, val
, n
);
14956 static int support_64bit_objects(void)
14958 const char **list
, **l
;
14961 list
= bfd_target_list ();
14962 for (l
= list
; *l
!= NULL
; l
++)
14963 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14964 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14966 yes
= (*l
!= NULL
);
14971 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14972 NEW_VALUE. Warn if another value was already specified. Note:
14973 we have to defer parsing the -march and -mtune arguments in order
14974 to handle 'from-abi' correctly, since the ABI might be specified
14975 in a later argument. */
14978 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14980 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14981 as_warn (_("A different %s was already specified, is now %s"),
14982 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14985 *string_ptr
= new_value
;
14989 md_parse_option (int c
, char *arg
)
14993 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14994 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14996 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
],
14997 c
== mips_ases
[i
].option_on
);
15003 case OPTION_CONSTRUCT_FLOATS
:
15004 mips_disable_float_construction
= 0;
15007 case OPTION_NO_CONSTRUCT_FLOATS
:
15008 mips_disable_float_construction
= 1;
15020 target_big_endian
= 1;
15024 target_big_endian
= 0;
15030 else if (arg
[0] == '0')
15032 else if (arg
[0] == '1')
15042 mips_debug
= atoi (arg
);
15046 file_mips_isa
= ISA_MIPS1
;
15050 file_mips_isa
= ISA_MIPS2
;
15054 file_mips_isa
= ISA_MIPS3
;
15058 file_mips_isa
= ISA_MIPS4
;
15062 file_mips_isa
= ISA_MIPS5
;
15065 case OPTION_MIPS32
:
15066 file_mips_isa
= ISA_MIPS32
;
15069 case OPTION_MIPS32R2
:
15070 file_mips_isa
= ISA_MIPS32R2
;
15073 case OPTION_MIPS64R2
:
15074 file_mips_isa
= ISA_MIPS64R2
;
15077 case OPTION_MIPS64
:
15078 file_mips_isa
= ISA_MIPS64
;
15082 mips_set_option_string (&mips_tune_string
, arg
);
15086 mips_set_option_string (&mips_arch_string
, arg
);
15090 mips_set_option_string (&mips_arch_string
, "4650");
15091 mips_set_option_string (&mips_tune_string
, "4650");
15094 case OPTION_NO_M4650
:
15098 mips_set_option_string (&mips_arch_string
, "4010");
15099 mips_set_option_string (&mips_tune_string
, "4010");
15102 case OPTION_NO_M4010
:
15106 mips_set_option_string (&mips_arch_string
, "4100");
15107 mips_set_option_string (&mips_tune_string
, "4100");
15110 case OPTION_NO_M4100
:
15114 mips_set_option_string (&mips_arch_string
, "3900");
15115 mips_set_option_string (&mips_tune_string
, "3900");
15118 case OPTION_NO_M3900
:
15121 case OPTION_MICROMIPS
:
15122 if (mips_opts
.mips16
== 1)
15124 as_bad (_("-mmicromips cannot be used with -mips16"));
15127 mips_opts
.micromips
= 1;
15128 mips_no_prev_insn ();
15131 case OPTION_NO_MICROMIPS
:
15132 mips_opts
.micromips
= 0;
15133 mips_no_prev_insn ();
15136 case OPTION_MIPS16
:
15137 if (mips_opts
.micromips
== 1)
15139 as_bad (_("-mips16 cannot be used with -micromips"));
15142 mips_opts
.mips16
= 1;
15143 mips_no_prev_insn ();
15146 case OPTION_NO_MIPS16
:
15147 mips_opts
.mips16
= 0;
15148 mips_no_prev_insn ();
15151 case OPTION_FIX_24K
:
15155 case OPTION_NO_FIX_24K
:
15159 case OPTION_FIX_LOONGSON2F_JUMP
:
15160 mips_fix_loongson2f_jump
= TRUE
;
15163 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
15164 mips_fix_loongson2f_jump
= FALSE
;
15167 case OPTION_FIX_LOONGSON2F_NOP
:
15168 mips_fix_loongson2f_nop
= TRUE
;
15171 case OPTION_NO_FIX_LOONGSON2F_NOP
:
15172 mips_fix_loongson2f_nop
= FALSE
;
15175 case OPTION_FIX_VR4120
:
15176 mips_fix_vr4120
= 1;
15179 case OPTION_NO_FIX_VR4120
:
15180 mips_fix_vr4120
= 0;
15183 case OPTION_FIX_VR4130
:
15184 mips_fix_vr4130
= 1;
15187 case OPTION_NO_FIX_VR4130
:
15188 mips_fix_vr4130
= 0;
15191 case OPTION_FIX_CN63XXP1
:
15192 mips_fix_cn63xxp1
= TRUE
;
15195 case OPTION_NO_FIX_CN63XXP1
:
15196 mips_fix_cn63xxp1
= FALSE
;
15199 case OPTION_RELAX_BRANCH
:
15200 mips_relax_branch
= 1;
15203 case OPTION_NO_RELAX_BRANCH
:
15204 mips_relax_branch
= 0;
15207 case OPTION_INSN32
:
15208 mips_opts
.insn32
= TRUE
;
15211 case OPTION_NO_INSN32
:
15212 mips_opts
.insn32
= FALSE
;
15215 case OPTION_MSHARED
:
15216 mips_in_shared
= TRUE
;
15219 case OPTION_MNO_SHARED
:
15220 mips_in_shared
= FALSE
;
15223 case OPTION_MSYM32
:
15224 mips_opts
.sym32
= TRUE
;
15227 case OPTION_MNO_SYM32
:
15228 mips_opts
.sym32
= FALSE
;
15231 /* When generating ELF code, we permit -KPIC and -call_shared to
15232 select SVR4_PIC, and -non_shared to select no PIC. This is
15233 intended to be compatible with Irix 5. */
15234 case OPTION_CALL_SHARED
:
15235 mips_pic
= SVR4_PIC
;
15236 mips_abicalls
= TRUE
;
15239 case OPTION_CALL_NONPIC
:
15241 mips_abicalls
= TRUE
;
15244 case OPTION_NON_SHARED
:
15246 mips_abicalls
= FALSE
;
15249 /* The -xgot option tells the assembler to use 32 bit offsets
15250 when accessing the got in SVR4_PIC mode. It is for Irix
15257 g_switch_value
= atoi (arg
);
15261 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15264 mips_abi
= O32_ABI
;
15268 mips_abi
= N32_ABI
;
15272 mips_abi
= N64_ABI
;
15273 if (!support_64bit_objects())
15274 as_fatal (_("No compiled in support for 64 bit object file format"));
15278 file_mips_gp32
= 1;
15282 file_mips_gp32
= 0;
15286 file_mips_fp32
= 1;
15290 file_mips_fp32
= 0;
15293 case OPTION_SINGLE_FLOAT
:
15294 file_mips_single_float
= 1;
15297 case OPTION_DOUBLE_FLOAT
:
15298 file_mips_single_float
= 0;
15301 case OPTION_SOFT_FLOAT
:
15302 file_mips_soft_float
= 1;
15305 case OPTION_HARD_FLOAT
:
15306 file_mips_soft_float
= 0;
15310 if (strcmp (arg
, "32") == 0)
15311 mips_abi
= O32_ABI
;
15312 else if (strcmp (arg
, "o64") == 0)
15313 mips_abi
= O64_ABI
;
15314 else if (strcmp (arg
, "n32") == 0)
15315 mips_abi
= N32_ABI
;
15316 else if (strcmp (arg
, "64") == 0)
15318 mips_abi
= N64_ABI
;
15319 if (! support_64bit_objects())
15320 as_fatal (_("No compiled in support for 64 bit object file "
15323 else if (strcmp (arg
, "eabi") == 0)
15324 mips_abi
= EABI_ABI
;
15327 as_fatal (_("invalid abi -mabi=%s"), arg
);
15332 case OPTION_M7000_HILO_FIX
:
15333 mips_7000_hilo_fix
= TRUE
;
15336 case OPTION_MNO_7000_HILO_FIX
:
15337 mips_7000_hilo_fix
= FALSE
;
15340 case OPTION_MDEBUG
:
15341 mips_flag_mdebug
= TRUE
;
15344 case OPTION_NO_MDEBUG
:
15345 mips_flag_mdebug
= FALSE
;
15349 mips_flag_pdr
= TRUE
;
15352 case OPTION_NO_PDR
:
15353 mips_flag_pdr
= FALSE
;
15356 case OPTION_MVXWORKS_PIC
:
15357 mips_pic
= VXWORKS_PIC
;
15364 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15369 /* Set up globals to generate code for the ISA or processor
15370 described by INFO. */
15373 mips_set_architecture (const struct mips_cpu_info
*info
)
15377 file_mips_arch
= info
->cpu
;
15378 mips_opts
.arch
= info
->cpu
;
15379 mips_opts
.isa
= info
->isa
;
15384 /* Likewise for tuning. */
15387 mips_set_tune (const struct mips_cpu_info
*info
)
15390 mips_tune
= info
->cpu
;
15395 mips_after_parse_args (void)
15397 const struct mips_cpu_info
*arch_info
= 0;
15398 const struct mips_cpu_info
*tune_info
= 0;
15400 /* GP relative stuff not working for PE */
15401 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15403 if (g_switch_seen
&& g_switch_value
!= 0)
15404 as_bad (_("-G not supported in this configuration."));
15405 g_switch_value
= 0;
15408 if (mips_abi
== NO_ABI
)
15409 mips_abi
= MIPS_DEFAULT_ABI
;
15411 /* The following code determines the architecture and register size.
15412 Similar code was added to GCC 3.3 (see override_options() in
15413 config/mips/mips.c). The GAS and GCC code should be kept in sync
15414 as much as possible. */
15416 if (mips_arch_string
!= 0)
15417 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15419 if (file_mips_isa
!= ISA_UNKNOWN
)
15421 /* Handle -mipsN. At this point, file_mips_isa contains the
15422 ISA level specified by -mipsN, while arch_info->isa contains
15423 the -march selection (if any). */
15424 if (arch_info
!= 0)
15426 /* -march takes precedence over -mipsN, since it is more descriptive.
15427 There's no harm in specifying both as long as the ISA levels
15429 if (file_mips_isa
!= arch_info
->isa
)
15430 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15431 mips_cpu_info_from_isa (file_mips_isa
)->name
,
15432 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15435 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
15438 if (arch_info
== 0)
15440 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15441 gas_assert (arch_info
);
15444 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15445 as_bad (_("-march=%s is not compatible with the selected ABI"),
15448 mips_set_architecture (arch_info
);
15450 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15451 if (mips_tune_string
!= 0)
15452 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15454 if (tune_info
== 0)
15455 mips_set_tune (arch_info
);
15457 mips_set_tune (tune_info
);
15459 if (file_mips_gp32
>= 0)
15461 /* The user specified the size of the integer registers. Make sure
15462 it agrees with the ABI and ISA. */
15463 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
15464 as_bad (_("-mgp64 used with a 32-bit processor"));
15465 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
15466 as_bad (_("-mgp32 used with a 64-bit ABI"));
15467 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
15468 as_bad (_("-mgp64 used with a 32-bit ABI"));
15472 /* Infer the integer register size from the ABI and processor.
15473 Restrict ourselves to 32-bit registers if that's all the
15474 processor has, or if the ABI cannot handle 64-bit registers. */
15475 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
15476 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
15479 switch (file_mips_fp32
)
15483 /* No user specified float register size.
15484 ??? GAS treats single-float processors as though they had 64-bit
15485 float registers (although it complains when double-precision
15486 instructions are used). As things stand, saying they have 32-bit
15487 registers would lead to spurious "register must be even" messages.
15488 So here we assume float registers are never smaller than the
15490 if (file_mips_gp32
== 0)
15491 /* 64-bit integer registers implies 64-bit float registers. */
15492 file_mips_fp32
= 0;
15493 else if ((mips_opts
.ase
& FP64_ASES
)
15494 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15495 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15496 file_mips_fp32
= 0;
15498 /* 32-bit float registers. */
15499 file_mips_fp32
= 1;
15502 /* The user specified the size of the float registers. Check if it
15503 agrees with the ABI and ISA. */
15505 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
15506 as_bad (_("-mfp64 used with a 32-bit fpu"));
15507 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
15508 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
15509 as_warn (_("-mfp64 used with a 32-bit ABI"));
15512 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15513 as_warn (_("-mfp32 used with a 64-bit ABI"));
15517 /* End of GCC-shared inference code. */
15519 /* This flag is set when we have a 64-bit capable CPU but use only
15520 32-bit wide registers. Note that EABI does not use it. */
15521 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
15522 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
15523 || mips_abi
== O32_ABI
))
15524 mips_32bitmode
= 1;
15526 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
15527 as_bad (_("trap exception not supported at ISA 1"));
15529 /* If the selected architecture includes support for ASEs, enable
15530 generation of code for them. */
15531 if (mips_opts
.mips16
== -1)
15532 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
15533 if (mips_opts
.micromips
== -1)
15534 mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_arch
)) ? 1 : 0;
15536 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15537 ASEs from being selected implicitly. */
15538 if (file_mips_fp32
== 1)
15539 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
;
15541 /* If the user didn't explicitly select or deselect a particular ASE,
15542 use the default setting for the CPU. */
15543 mips_opts
.ase
|= (arch_info
->ase
& ~file_ase_explicit
);
15545 file_mips_isa
= mips_opts
.isa
;
15546 file_ase
= mips_opts
.ase
;
15547 mips_opts
.gp32
= file_mips_gp32
;
15548 mips_opts
.fp32
= file_mips_fp32
;
15549 mips_opts
.soft_float
= file_mips_soft_float
;
15550 mips_opts
.single_float
= file_mips_single_float
;
15552 mips_check_isa_supports_ases ();
15554 if (mips_flag_mdebug
< 0)
15555 mips_flag_mdebug
= 0;
15559 mips_init_after_args (void)
15561 /* initialize opcodes */
15562 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15563 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15567 md_pcrel_from (fixS
*fixP
)
15569 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15570 switch (fixP
->fx_r_type
)
15572 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15573 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15574 /* Return the address of the delay slot. */
15577 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15578 case BFD_RELOC_MICROMIPS_JMP
:
15579 case BFD_RELOC_16_PCREL_S2
:
15580 case BFD_RELOC_MIPS_JMP
:
15581 /* Return the address of the delay slot. */
15584 case BFD_RELOC_32_PCREL
:
15588 /* We have no relocation type for PC relative MIPS16 instructions. */
15589 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
15590 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15591 _("PC relative MIPS16 instruction references a different section"));
15596 /* This is called before the symbol table is processed. In order to
15597 work with gcc when using mips-tfile, we must keep all local labels.
15598 However, in other cases, we want to discard them. If we were
15599 called with -g, but we didn't see any debugging information, it may
15600 mean that gcc is smuggling debugging information through to
15601 mips-tfile, in which case we must generate all local labels. */
15604 mips_frob_file_before_adjust (void)
15606 #ifndef NO_ECOFF_DEBUGGING
15607 if (ECOFF_DEBUGGING
15609 && ! ecoff_debugging_seen
)
15610 flag_keep_locals
= 1;
15614 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15615 the corresponding LO16 reloc. This is called before md_apply_fix and
15616 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15617 relocation operators.
15619 For our purposes, a %lo() expression matches a %got() or %hi()
15622 (a) it refers to the same symbol; and
15623 (b) the offset applied in the %lo() expression is no lower than
15624 the offset applied in the %got() or %hi().
15626 (b) allows us to cope with code like:
15629 lh $4,%lo(foo+2)($4)
15631 ...which is legal on RELA targets, and has a well-defined behaviour
15632 if the user knows that adding 2 to "foo" will not induce a carry to
15635 When several %lo()s match a particular %got() or %hi(), we use the
15636 following rules to distinguish them:
15638 (1) %lo()s with smaller offsets are a better match than %lo()s with
15641 (2) %lo()s with no matching %got() or %hi() are better than those
15642 that already have a matching %got() or %hi().
15644 (3) later %lo()s are better than earlier %lo()s.
15646 These rules are applied in order.
15648 (1) means, among other things, that %lo()s with identical offsets are
15649 chosen if they exist.
15651 (2) means that we won't associate several high-part relocations with
15652 the same low-part relocation unless there's no alternative. Having
15653 several high parts for the same low part is a GNU extension; this rule
15654 allows careful users to avoid it.
15656 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15657 with the last high-part relocation being at the front of the list.
15658 It therefore makes sense to choose the last matching low-part
15659 relocation, all other things being equal. It's also easier
15660 to code that way. */
15663 mips_frob_file (void)
15665 struct mips_hi_fixup
*l
;
15666 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15668 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15670 segment_info_type
*seginfo
;
15671 bfd_boolean matched_lo_p
;
15672 fixS
**hi_pos
, **lo_pos
, **pos
;
15674 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15676 /* If a GOT16 relocation turns out to be against a global symbol,
15677 there isn't supposed to be a matching LO. Ignore %gots against
15678 constants; we'll report an error for those later. */
15679 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15680 && !(l
->fixp
->fx_addsy
15681 && pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
)))
15684 /* Check quickly whether the next fixup happens to be a matching %lo. */
15685 if (fixup_has_matching_lo_p (l
->fixp
))
15688 seginfo
= seg_info (l
->seg
);
15690 /* Set HI_POS to the position of this relocation in the chain.
15691 Set LO_POS to the position of the chosen low-part relocation.
15692 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15693 relocation that matches an immediately-preceding high-part
15697 matched_lo_p
= FALSE
;
15698 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15700 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15702 if (*pos
== l
->fixp
)
15705 if ((*pos
)->fx_r_type
== looking_for_rtype
15706 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15707 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15709 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15711 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15714 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15715 && fixup_has_matching_lo_p (*pos
));
15718 /* If we found a match, remove the high-part relocation from its
15719 current position and insert it before the low-part relocation.
15720 Make the offsets match so that fixup_has_matching_lo_p()
15723 We don't warn about unmatched high-part relocations since some
15724 versions of gcc have been known to emit dead "lui ...%hi(...)"
15726 if (lo_pos
!= NULL
)
15728 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15729 if (l
->fixp
->fx_next
!= *lo_pos
)
15731 *hi_pos
= l
->fixp
->fx_next
;
15732 l
->fixp
->fx_next
= *lo_pos
;
15740 mips_force_relocation (fixS
*fixp
)
15742 if (generic_force_reloc (fixp
))
15745 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15746 so that the linker relaxation can update targets. */
15747 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15748 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15749 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15755 /* Read the instruction associated with RELOC from BUF. */
15757 static unsigned int
15758 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15760 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15761 return read_compressed_insn (buf
, 4);
15763 return read_insn (buf
);
15766 /* Write instruction INSN to BUF, given that it has been relocated
15770 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15771 unsigned long insn
)
15773 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15774 write_compressed_insn (buf
, insn
, 4);
15776 write_insn (buf
, insn
);
15779 /* Apply a fixup to the object file. */
15782 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15785 unsigned long insn
;
15786 reloc_howto_type
*howto
;
15788 /* We ignore generic BFD relocations we don't know about. */
15789 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15793 gas_assert (fixP
->fx_size
== 2
15794 || fixP
->fx_size
== 4
15795 || fixP
->fx_r_type
== BFD_RELOC_16
15796 || fixP
->fx_r_type
== BFD_RELOC_64
15797 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15798 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15799 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15800 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15801 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15802 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
15804 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15806 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15807 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15808 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15809 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
15810 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
);
15812 /* Don't treat parts of a composite relocation as done. There are two
15815 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15816 should nevertheless be emitted if the first part is.
15818 (2) In normal usage, composite relocations are never assembly-time
15819 constants. The easiest way of dealing with the pathological
15820 exceptions is to generate a relocation against STN_UNDEF and
15821 leave everything up to the linker. */
15822 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15825 switch (fixP
->fx_r_type
)
15827 case BFD_RELOC_MIPS_TLS_GD
:
15828 case BFD_RELOC_MIPS_TLS_LDM
:
15829 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15830 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15831 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15832 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15833 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15834 case BFD_RELOC_MIPS_TLS_TPREL32
:
15835 case BFD_RELOC_MIPS_TLS_TPREL64
:
15836 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15837 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15838 case BFD_RELOC_MICROMIPS_TLS_GD
:
15839 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15840 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15841 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15842 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15843 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15844 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15845 case BFD_RELOC_MIPS16_TLS_GD
:
15846 case BFD_RELOC_MIPS16_TLS_LDM
:
15847 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15848 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15849 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15850 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15851 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15852 if (!fixP
->fx_addsy
)
15854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15855 _("TLS relocation against a constant"));
15858 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15861 case BFD_RELOC_MIPS_JMP
:
15862 case BFD_RELOC_MIPS_SHIFT5
:
15863 case BFD_RELOC_MIPS_SHIFT6
:
15864 case BFD_RELOC_MIPS_GOT_DISP
:
15865 case BFD_RELOC_MIPS_GOT_PAGE
:
15866 case BFD_RELOC_MIPS_GOT_OFST
:
15867 case BFD_RELOC_MIPS_SUB
:
15868 case BFD_RELOC_MIPS_INSERT_A
:
15869 case BFD_RELOC_MIPS_INSERT_B
:
15870 case BFD_RELOC_MIPS_DELETE
:
15871 case BFD_RELOC_MIPS_HIGHEST
:
15872 case BFD_RELOC_MIPS_HIGHER
:
15873 case BFD_RELOC_MIPS_SCN_DISP
:
15874 case BFD_RELOC_MIPS_REL16
:
15875 case BFD_RELOC_MIPS_RELGOT
:
15876 case BFD_RELOC_MIPS_JALR
:
15877 case BFD_RELOC_HI16
:
15878 case BFD_RELOC_HI16_S
:
15879 case BFD_RELOC_LO16
:
15880 case BFD_RELOC_GPREL16
:
15881 case BFD_RELOC_MIPS_LITERAL
:
15882 case BFD_RELOC_MIPS_CALL16
:
15883 case BFD_RELOC_MIPS_GOT16
:
15884 case BFD_RELOC_GPREL32
:
15885 case BFD_RELOC_MIPS_GOT_HI16
:
15886 case BFD_RELOC_MIPS_GOT_LO16
:
15887 case BFD_RELOC_MIPS_CALL_HI16
:
15888 case BFD_RELOC_MIPS_CALL_LO16
:
15889 case BFD_RELOC_MIPS16_GPREL
:
15890 case BFD_RELOC_MIPS16_GOT16
:
15891 case BFD_RELOC_MIPS16_CALL16
:
15892 case BFD_RELOC_MIPS16_HI16
:
15893 case BFD_RELOC_MIPS16_HI16_S
:
15894 case BFD_RELOC_MIPS16_LO16
:
15895 case BFD_RELOC_MIPS16_JMP
:
15896 case BFD_RELOC_MICROMIPS_JMP
:
15897 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15898 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15899 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15900 case BFD_RELOC_MICROMIPS_SUB
:
15901 case BFD_RELOC_MICROMIPS_HIGHEST
:
15902 case BFD_RELOC_MICROMIPS_HIGHER
:
15903 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15904 case BFD_RELOC_MICROMIPS_JALR
:
15905 case BFD_RELOC_MICROMIPS_HI16
:
15906 case BFD_RELOC_MICROMIPS_HI16_S
:
15907 case BFD_RELOC_MICROMIPS_LO16
:
15908 case BFD_RELOC_MICROMIPS_GPREL16
:
15909 case BFD_RELOC_MICROMIPS_LITERAL
:
15910 case BFD_RELOC_MICROMIPS_CALL16
:
15911 case BFD_RELOC_MICROMIPS_GOT16
:
15912 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15913 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15914 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15915 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15916 case BFD_RELOC_MIPS_EH
:
15921 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15923 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15924 if (mips16_reloc_p (fixP
->fx_r_type
))
15925 insn
|= mips16_immed_extend (value
, 16);
15927 insn
|= (value
& 0xffff);
15928 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15932 _("Unsupported constant in relocation"));
15937 /* This is handled like BFD_RELOC_32, but we output a sign
15938 extended value if we are only 32 bits. */
15941 if (8 <= sizeof (valueT
))
15942 md_number_to_chars (buf
, *valP
, 8);
15947 if ((*valP
& 0x80000000) != 0)
15951 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
15952 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
15957 case BFD_RELOC_RVA
:
15959 case BFD_RELOC_32_PCREL
:
15961 /* If we are deleting this reloc entry, we must fill in the
15962 value now. This can happen if we have a .word which is not
15963 resolved when it appears but is later defined. */
15965 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
15968 case BFD_RELOC_16_PCREL_S2
:
15969 if ((*valP
& 0x3) != 0)
15970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15971 _("Branch to misaligned address (%lx)"), (long) *valP
);
15973 /* We need to save the bits in the instruction since fixup_segment()
15974 might be deleting the relocation entry (i.e., a branch within
15975 the current segment). */
15976 if (! fixP
->fx_done
)
15979 /* Update old instruction data. */
15980 insn
= read_insn (buf
);
15982 if (*valP
+ 0x20000 <= 0x3ffff)
15984 insn
|= (*valP
>> 2) & 0xffff;
15985 write_insn (buf
, insn
);
15987 else if (mips_pic
== NO_PIC
15989 && fixP
->fx_frag
->fr_address
>= text_section
->vma
15990 && (fixP
->fx_frag
->fr_address
15991 < text_section
->vma
+ bfd_get_section_size (text_section
))
15992 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
15993 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
15994 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
15996 /* The branch offset is too large. If this is an
15997 unconditional branch, and we are not generating PIC code,
15998 we can convert it to an absolute jump instruction. */
15999 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16000 insn
= 0x0c000000; /* jal */
16002 insn
= 0x08000000; /* j */
16003 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16005 fixP
->fx_addsy
= section_symbol (text_section
);
16006 *valP
+= md_pcrel_from (fixP
);
16007 write_insn (buf
, insn
);
16011 /* If we got here, we have branch-relaxation disabled,
16012 and there's nothing we can do to fix this instruction
16013 without turning it into a longer sequence. */
16014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16015 _("Branch out of range"));
16019 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16020 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16021 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16022 /* We adjust the offset back to even. */
16023 if ((*valP
& 0x1) != 0)
16026 if (! fixP
->fx_done
)
16029 /* Should never visit here, because we keep the relocation. */
16033 case BFD_RELOC_VTABLE_INHERIT
:
16036 && !S_IS_DEFINED (fixP
->fx_addsy
)
16037 && !S_IS_WEAK (fixP
->fx_addsy
))
16038 S_SET_WEAK (fixP
->fx_addsy
);
16041 case BFD_RELOC_VTABLE_ENTRY
:
16049 /* Remember value for tc_gen_reloc. */
16050 fixP
->fx_addnumber
= *valP
;
16060 name
= input_line_pointer
;
16061 c
= get_symbol_end ();
16062 p
= (symbolS
*) symbol_find_or_make (name
);
16063 *input_line_pointer
= c
;
16067 /* Align the current frag to a given power of two. If a particular
16068 fill byte should be used, FILL points to an integer that contains
16069 that byte, otherwise FILL is null.
16071 This function used to have the comment:
16073 The MIPS assembler also automatically adjusts any preceding label.
16075 The implementation therefore applied the adjustment to a maximum of
16076 one label. However, other label adjustments are applied to batches
16077 of labels, and adjusting just one caused problems when new labels
16078 were added for the sake of debugging or unwind information.
16079 We therefore adjust all preceding labels (given as LABELS) instead. */
16082 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16084 mips_emit_delays ();
16085 mips_record_compressed_mode ();
16086 if (fill
== NULL
&& subseg_text_p (now_seg
))
16087 frag_align_code (to
, 0);
16089 frag_align (to
, fill
? *fill
: 0, 0);
16090 record_alignment (now_seg
, to
);
16091 mips_move_labels (labels
, FALSE
);
16094 /* Align to a given power of two. .align 0 turns off the automatic
16095 alignment used by the data creating pseudo-ops. */
16098 s_align (int x ATTRIBUTE_UNUSED
)
16100 int temp
, fill_value
, *fill_ptr
;
16101 long max_alignment
= 28;
16103 /* o Note that the assembler pulls down any immediately preceding label
16104 to the aligned address.
16105 o It's not documented but auto alignment is reinstated by
16106 a .align pseudo instruction.
16107 o Note also that after auto alignment is turned off the mips assembler
16108 issues an error on attempt to assemble an improperly aligned data item.
16111 temp
= get_absolute_expression ();
16112 if (temp
> max_alignment
)
16113 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
16116 as_warn (_("Alignment negative: 0 assumed."));
16119 if (*input_line_pointer
== ',')
16121 ++input_line_pointer
;
16122 fill_value
= get_absolute_expression ();
16123 fill_ptr
= &fill_value
;
16129 segment_info_type
*si
= seg_info (now_seg
);
16130 struct insn_label_list
*l
= si
->label_list
;
16131 /* Auto alignment should be switched on by next section change. */
16133 mips_align (temp
, fill_ptr
, l
);
16140 demand_empty_rest_of_line ();
16144 s_change_sec (int sec
)
16148 /* The ELF backend needs to know that we are changing sections, so
16149 that .previous works correctly. We could do something like check
16150 for an obj_section_change_hook macro, but that might be confusing
16151 as it would not be appropriate to use it in the section changing
16152 functions in read.c, since obj-elf.c intercepts those. FIXME:
16153 This should be cleaner, somehow. */
16154 obj_elf_section_change_hook ();
16156 mips_emit_delays ();
16167 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16168 demand_empty_rest_of_line ();
16172 seg
= subseg_new (RDATA_SECTION_NAME
,
16173 (subsegT
) get_absolute_expression ());
16174 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
16175 | SEC_READONLY
| SEC_RELOC
16177 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16178 record_alignment (seg
, 4);
16179 demand_empty_rest_of_line ();
16183 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16184 bfd_set_section_flags (stdoutput
, seg
,
16185 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16186 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16187 record_alignment (seg
, 4);
16188 demand_empty_rest_of_line ();
16192 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16193 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
16194 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16195 record_alignment (seg
, 4);
16196 demand_empty_rest_of_line ();
16204 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16206 char *section_name
;
16211 int section_entry_size
;
16212 int section_alignment
;
16214 section_name
= input_line_pointer
;
16215 c
= get_symbol_end ();
16217 next_c
= *(input_line_pointer
+ 1);
16219 /* Do we have .section Name<,"flags">? */
16220 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16222 /* just after name is now '\0'. */
16223 *input_line_pointer
= c
;
16224 input_line_pointer
= section_name
;
16225 obj_elf_section (ignore
);
16228 input_line_pointer
++;
16230 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16232 section_type
= get_absolute_expression ();
16235 if (*input_line_pointer
++ == ',')
16236 section_flag
= get_absolute_expression ();
16239 if (*input_line_pointer
++ == ',')
16240 section_entry_size
= get_absolute_expression ();
16242 section_entry_size
= 0;
16243 if (*input_line_pointer
++ == ',')
16244 section_alignment
= get_absolute_expression ();
16246 section_alignment
= 0;
16247 /* FIXME: really ignore? */
16248 (void) section_alignment
;
16250 section_name
= xstrdup (section_name
);
16252 /* When using the generic form of .section (as implemented by obj-elf.c),
16253 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16254 traditionally had to fall back on the more common @progbits instead.
16256 There's nothing really harmful in this, since bfd will correct
16257 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16258 means that, for backwards compatibility, the special_section entries
16259 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16261 Even so, we shouldn't force users of the MIPS .section syntax to
16262 incorrectly label the sections as SHT_PROGBITS. The best compromise
16263 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16264 generic type-checking code. */
16265 if (section_type
== SHT_MIPS_DWARF
)
16266 section_type
= SHT_PROGBITS
;
16268 obj_elf_change_section (section_name
, section_type
, section_flag
,
16269 section_entry_size
, 0, 0, 0);
16271 if (now_seg
->name
!= section_name
)
16272 free (section_name
);
16276 mips_enable_auto_align (void)
16282 s_cons (int log_size
)
16284 segment_info_type
*si
= seg_info (now_seg
);
16285 struct insn_label_list
*l
= si
->label_list
;
16287 mips_emit_delays ();
16288 if (log_size
> 0 && auto_align
)
16289 mips_align (log_size
, 0, l
);
16290 cons (1 << log_size
);
16291 mips_clear_insn_labels ();
16295 s_float_cons (int type
)
16297 segment_info_type
*si
= seg_info (now_seg
);
16298 struct insn_label_list
*l
= si
->label_list
;
16300 mips_emit_delays ();
16305 mips_align (3, 0, l
);
16307 mips_align (2, 0, l
);
16311 mips_clear_insn_labels ();
16314 /* Handle .globl. We need to override it because on Irix 5 you are
16317 where foo is an undefined symbol, to mean that foo should be
16318 considered to be the address of a function. */
16321 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16330 name
= input_line_pointer
;
16331 c
= get_symbol_end ();
16332 symbolP
= symbol_find_or_make (name
);
16333 S_SET_EXTERNAL (symbolP
);
16335 *input_line_pointer
= c
;
16336 SKIP_WHITESPACE ();
16338 /* On Irix 5, every global symbol that is not explicitly labelled as
16339 being a function is apparently labelled as being an object. */
16342 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16343 && (*input_line_pointer
!= ','))
16348 secname
= input_line_pointer
;
16349 c
= get_symbol_end ();
16350 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16352 as_bad (_("%s: no such section"), secname
);
16353 *input_line_pointer
= c
;
16355 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16356 flag
= BSF_FUNCTION
;
16359 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
16361 c
= *input_line_pointer
;
16364 input_line_pointer
++;
16365 SKIP_WHITESPACE ();
16366 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16372 demand_empty_rest_of_line ();
16376 s_option (int x ATTRIBUTE_UNUSED
)
16381 opt
= input_line_pointer
;
16382 c
= get_symbol_end ();
16386 /* FIXME: What does this mean? */
16388 else if (strncmp (opt
, "pic", 3) == 0)
16392 i
= atoi (opt
+ 3);
16397 mips_pic
= SVR4_PIC
;
16398 mips_abicalls
= TRUE
;
16401 as_bad (_(".option pic%d not supported"), i
);
16403 if (mips_pic
== SVR4_PIC
)
16405 if (g_switch_seen
&& g_switch_value
!= 0)
16406 as_warn (_("-G may not be used with SVR4 PIC code"));
16407 g_switch_value
= 0;
16408 bfd_set_gp_size (stdoutput
, 0);
16412 as_warn (_("Unrecognized option \"%s\""), opt
);
16414 *input_line_pointer
= c
;
16415 demand_empty_rest_of_line ();
16418 /* This structure is used to hold a stack of .set values. */
16420 struct mips_option_stack
16422 struct mips_option_stack
*next
;
16423 struct mips_set_options options
;
16426 static struct mips_option_stack
*mips_opts_stack
;
16428 /* Handle the .set pseudo-op. */
16431 s_mipsset (int x ATTRIBUTE_UNUSED
)
16433 char *name
= input_line_pointer
, ch
;
16434 const struct mips_ase
*ase
;
16436 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16437 ++input_line_pointer
;
16438 ch
= *input_line_pointer
;
16439 *input_line_pointer
= '\0';
16441 if (strcmp (name
, "reorder") == 0)
16443 if (mips_opts
.noreorder
)
16446 else if (strcmp (name
, "noreorder") == 0)
16448 if (!mips_opts
.noreorder
)
16449 start_noreorder ();
16451 else if (strncmp (name
, "at=", 3) == 0)
16453 char *s
= name
+ 3;
16455 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16456 as_bad (_("Unrecognized register name `%s'"), s
);
16458 else if (strcmp (name
, "at") == 0)
16460 mips_opts
.at
= ATREG
;
16462 else if (strcmp (name
, "noat") == 0)
16464 mips_opts
.at
= ZERO
;
16466 else if (strcmp (name
, "macro") == 0)
16468 mips_opts
.warn_about_macros
= 0;
16470 else if (strcmp (name
, "nomacro") == 0)
16472 if (mips_opts
.noreorder
== 0)
16473 as_bad (_("`noreorder' must be set before `nomacro'"));
16474 mips_opts
.warn_about_macros
= 1;
16476 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16478 mips_opts
.nomove
= 0;
16480 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16482 mips_opts
.nomove
= 1;
16484 else if (strcmp (name
, "bopt") == 0)
16486 mips_opts
.nobopt
= 0;
16488 else if (strcmp (name
, "nobopt") == 0)
16490 mips_opts
.nobopt
= 1;
16492 else if (strcmp (name
, "gp=default") == 0)
16493 mips_opts
.gp32
= file_mips_gp32
;
16494 else if (strcmp (name
, "gp=32") == 0)
16495 mips_opts
.gp32
= 1;
16496 else if (strcmp (name
, "gp=64") == 0)
16498 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
16499 as_warn (_("%s isa does not support 64-bit registers"),
16500 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16501 mips_opts
.gp32
= 0;
16503 else if (strcmp (name
, "fp=default") == 0)
16504 mips_opts
.fp32
= file_mips_fp32
;
16505 else if (strcmp (name
, "fp=32") == 0)
16506 mips_opts
.fp32
= 1;
16507 else if (strcmp (name
, "fp=64") == 0)
16509 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
16510 as_warn (_("%s isa does not support 64-bit floating point registers"),
16511 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
16512 mips_opts
.fp32
= 0;
16514 else if (strcmp (name
, "softfloat") == 0)
16515 mips_opts
.soft_float
= 1;
16516 else if (strcmp (name
, "hardfloat") == 0)
16517 mips_opts
.soft_float
= 0;
16518 else if (strcmp (name
, "singlefloat") == 0)
16519 mips_opts
.single_float
= 1;
16520 else if (strcmp (name
, "doublefloat") == 0)
16521 mips_opts
.single_float
= 0;
16522 else if (strcmp (name
, "mips16") == 0
16523 || strcmp (name
, "MIPS-16") == 0)
16525 if (mips_opts
.micromips
== 1)
16526 as_fatal (_("`mips16' cannot be used with `micromips'"));
16527 mips_opts
.mips16
= 1;
16529 else if (strcmp (name
, "nomips16") == 0
16530 || strcmp (name
, "noMIPS-16") == 0)
16531 mips_opts
.mips16
= 0;
16532 else if (strcmp (name
, "micromips") == 0)
16534 if (mips_opts
.mips16
== 1)
16535 as_fatal (_("`micromips' cannot be used with `mips16'"));
16536 mips_opts
.micromips
= 1;
16538 else if (strcmp (name
, "nomicromips") == 0)
16539 mips_opts
.micromips
= 0;
16540 else if (name
[0] == 'n'
16542 && (ase
= mips_lookup_ase (name
+ 2)))
16543 mips_set_ase (ase
, FALSE
);
16544 else if ((ase
= mips_lookup_ase (name
)))
16545 mips_set_ase (ase
, TRUE
);
16546 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16550 /* Permit the user to change the ISA and architecture on the fly.
16551 Needless to say, misuse can cause serious problems. */
16552 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16555 mips_opts
.isa
= file_mips_isa
;
16556 mips_opts
.arch
= file_mips_arch
;
16558 else if (strncmp (name
, "arch=", 5) == 0)
16560 const struct mips_cpu_info
*p
;
16562 p
= mips_parse_cpu("internal use", name
+ 5);
16564 as_bad (_("unknown architecture %s"), name
+ 5);
16567 mips_opts
.arch
= p
->cpu
;
16568 mips_opts
.isa
= p
->isa
;
16571 else if (strncmp (name
, "mips", 4) == 0)
16573 const struct mips_cpu_info
*p
;
16575 p
= mips_parse_cpu("internal use", name
);
16577 as_bad (_("unknown ISA level %s"), name
+ 4);
16580 mips_opts
.arch
= p
->cpu
;
16581 mips_opts
.isa
= p
->isa
;
16585 as_bad (_("unknown ISA or architecture %s"), name
);
16587 switch (mips_opts
.isa
)
16595 mips_opts
.gp32
= 1;
16596 mips_opts
.fp32
= 1;
16603 mips_opts
.gp32
= 0;
16604 if (mips_opts
.arch
== CPU_R5900
)
16606 mips_opts
.fp32
= 1;
16610 mips_opts
.fp32
= 0;
16614 as_bad (_("unknown ISA level %s"), name
+ 4);
16619 mips_opts
.gp32
= file_mips_gp32
;
16620 mips_opts
.fp32
= file_mips_fp32
;
16623 else if (strcmp (name
, "autoextend") == 0)
16624 mips_opts
.noautoextend
= 0;
16625 else if (strcmp (name
, "noautoextend") == 0)
16626 mips_opts
.noautoextend
= 1;
16627 else if (strcmp (name
, "insn32") == 0)
16628 mips_opts
.insn32
= TRUE
;
16629 else if (strcmp (name
, "noinsn32") == 0)
16630 mips_opts
.insn32
= FALSE
;
16631 else if (strcmp (name
, "push") == 0)
16633 struct mips_option_stack
*s
;
16635 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
16636 s
->next
= mips_opts_stack
;
16637 s
->options
= mips_opts
;
16638 mips_opts_stack
= s
;
16640 else if (strcmp (name
, "pop") == 0)
16642 struct mips_option_stack
*s
;
16644 s
= mips_opts_stack
;
16646 as_bad (_(".set pop with no .set push"));
16649 /* If we're changing the reorder mode we need to handle
16650 delay slots correctly. */
16651 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16652 start_noreorder ();
16653 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16656 mips_opts
= s
->options
;
16657 mips_opts_stack
= s
->next
;
16661 else if (strcmp (name
, "sym32") == 0)
16662 mips_opts
.sym32
= TRUE
;
16663 else if (strcmp (name
, "nosym32") == 0)
16664 mips_opts
.sym32
= FALSE
;
16665 else if (strchr (name
, ','))
16667 /* Generic ".set" directive; use the generic handler. */
16668 *input_line_pointer
= ch
;
16669 input_line_pointer
= name
;
16675 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
16677 mips_check_isa_supports_ases ();
16678 *input_line_pointer
= ch
;
16679 demand_empty_rest_of_line ();
16682 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16683 .option pic2. It means to generate SVR4 PIC calls. */
16686 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16688 mips_pic
= SVR4_PIC
;
16689 mips_abicalls
= TRUE
;
16691 if (g_switch_seen
&& g_switch_value
!= 0)
16692 as_warn (_("-G may not be used with SVR4 PIC code"));
16693 g_switch_value
= 0;
16695 bfd_set_gp_size (stdoutput
, 0);
16696 demand_empty_rest_of_line ();
16699 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16700 PIC code. It sets the $gp register for the function based on the
16701 function address, which is in the register named in the argument.
16702 This uses a relocation against _gp_disp, which is handled specially
16703 by the linker. The result is:
16704 lui $gp,%hi(_gp_disp)
16705 addiu $gp,$gp,%lo(_gp_disp)
16706 addu $gp,$gp,.cpload argument
16707 The .cpload argument is normally $25 == $t9.
16709 The -mno-shared option changes this to:
16710 lui $gp,%hi(__gnu_local_gp)
16711 addiu $gp,$gp,%lo(__gnu_local_gp)
16712 and the argument is ignored. This saves an instruction, but the
16713 resulting code is not position independent; it uses an absolute
16714 address for __gnu_local_gp. Thus code assembled with -mno-shared
16715 can go into an ordinary executable, but not into a shared library. */
16718 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16724 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16725 .cpload is ignored. */
16726 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16732 if (mips_opts
.mips16
)
16734 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16735 ignore_rest_of_line ();
16739 /* .cpload should be in a .set noreorder section. */
16740 if (mips_opts
.noreorder
== 0)
16741 as_warn (_(".cpload not in noreorder section"));
16743 reg
= tc_get_register (0);
16745 /* If we need to produce a 64-bit address, we are better off using
16746 the default instruction sequence. */
16747 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16749 ex
.X_op
= O_symbol
;
16750 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16752 ex
.X_op_symbol
= NULL
;
16753 ex
.X_add_number
= 0;
16755 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16756 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16758 mips_mark_labels ();
16759 mips_assembling_insn
= TRUE
;
16762 macro_build_lui (&ex
, mips_gp_register
);
16763 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16764 mips_gp_register
, BFD_RELOC_LO16
);
16766 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16767 mips_gp_register
, reg
);
16770 mips_assembling_insn
= FALSE
;
16771 demand_empty_rest_of_line ();
16774 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16775 .cpsetup $reg1, offset|$reg2, label
16777 If offset is given, this results in:
16778 sd $gp, offset($sp)
16779 lui $gp, %hi(%neg(%gp_rel(label)))
16780 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16781 daddu $gp, $gp, $reg1
16783 If $reg2 is given, this results in:
16784 daddu $reg2, $gp, $0
16785 lui $gp, %hi(%neg(%gp_rel(label)))
16786 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16787 daddu $gp, $gp, $reg1
16788 $reg1 is normally $25 == $t9.
16790 The -mno-shared option replaces the last three instructions with
16792 addiu $gp,$gp,%lo(_gp) */
16795 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
16797 expressionS ex_off
;
16798 expressionS ex_sym
;
16801 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16802 We also need NewABI support. */
16803 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16809 if (mips_opts
.mips16
)
16811 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16812 ignore_rest_of_line ();
16816 reg1
= tc_get_register (0);
16817 SKIP_WHITESPACE ();
16818 if (*input_line_pointer
!= ',')
16820 as_bad (_("missing argument separator ',' for .cpsetup"));
16824 ++input_line_pointer
;
16825 SKIP_WHITESPACE ();
16826 if (*input_line_pointer
== '$')
16828 mips_cpreturn_register
= tc_get_register (0);
16829 mips_cpreturn_offset
= -1;
16833 mips_cpreturn_offset
= get_absolute_expression ();
16834 mips_cpreturn_register
= -1;
16836 SKIP_WHITESPACE ();
16837 if (*input_line_pointer
!= ',')
16839 as_bad (_("missing argument separator ',' for .cpsetup"));
16843 ++input_line_pointer
;
16844 SKIP_WHITESPACE ();
16845 expression (&ex_sym
);
16847 mips_mark_labels ();
16848 mips_assembling_insn
= TRUE
;
16851 if (mips_cpreturn_register
== -1)
16853 ex_off
.X_op
= O_constant
;
16854 ex_off
.X_add_symbol
= NULL
;
16855 ex_off
.X_op_symbol
= NULL
;
16856 ex_off
.X_add_number
= mips_cpreturn_offset
;
16858 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
16859 BFD_RELOC_LO16
, SP
);
16862 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
16863 mips_gp_register
, 0);
16865 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
16867 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
16868 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
16871 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
16872 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
16873 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
16875 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
16876 mips_gp_register
, reg1
);
16882 ex
.X_op
= O_symbol
;
16883 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
16884 ex
.X_op_symbol
= NULL
;
16885 ex
.X_add_number
= 0;
16887 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16888 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16890 macro_build_lui (&ex
, mips_gp_register
);
16891 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16892 mips_gp_register
, BFD_RELOC_LO16
);
16897 mips_assembling_insn
= FALSE
;
16898 demand_empty_rest_of_line ();
16902 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
16904 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16905 .cplocal is ignored. */
16906 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16912 if (mips_opts
.mips16
)
16914 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16915 ignore_rest_of_line ();
16919 mips_gp_register
= tc_get_register (0);
16920 demand_empty_rest_of_line ();
16923 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16924 offset from $sp. The offset is remembered, and after making a PIC
16925 call $gp is restored from that location. */
16928 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
16932 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16933 .cprestore is ignored. */
16934 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16940 if (mips_opts
.mips16
)
16942 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16943 ignore_rest_of_line ();
16947 mips_cprestore_offset
= get_absolute_expression ();
16948 mips_cprestore_valid
= 1;
16950 ex
.X_op
= O_constant
;
16951 ex
.X_add_symbol
= NULL
;
16952 ex
.X_op_symbol
= NULL
;
16953 ex
.X_add_number
= mips_cprestore_offset
;
16955 mips_mark_labels ();
16956 mips_assembling_insn
= TRUE
;
16959 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
16960 SP
, HAVE_64BIT_ADDRESSES
);
16963 mips_assembling_insn
= FALSE
;
16964 demand_empty_rest_of_line ();
16967 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16968 was given in the preceding .cpsetup, it results in:
16969 ld $gp, offset($sp)
16971 If a register $reg2 was given there, it results in:
16972 daddu $gp, $reg2, $0 */
16975 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
16979 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16980 We also need NewABI support. */
16981 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
16987 if (mips_opts
.mips16
)
16989 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16990 ignore_rest_of_line ();
16994 mips_mark_labels ();
16995 mips_assembling_insn
= TRUE
;
16998 if (mips_cpreturn_register
== -1)
17000 ex
.X_op
= O_constant
;
17001 ex
.X_add_symbol
= NULL
;
17002 ex
.X_op_symbol
= NULL
;
17003 ex
.X_add_number
= mips_cpreturn_offset
;
17005 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17008 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
17009 mips_cpreturn_register
, 0);
17012 mips_assembling_insn
= FALSE
;
17013 demand_empty_rest_of_line ();
17016 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17017 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17018 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17019 debug information or MIPS16 TLS. */
17022 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17023 bfd_reloc_code_real_type rtype
)
17030 if (ex
.X_op
!= O_symbol
)
17032 as_bad (_("Unsupported use of %s"), dirstr
);
17033 ignore_rest_of_line ();
17036 p
= frag_more (bytes
);
17037 md_number_to_chars (p
, 0, bytes
);
17038 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17039 demand_empty_rest_of_line ();
17040 mips_clear_insn_labels ();
17043 /* Handle .dtprelword. */
17046 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17048 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17051 /* Handle .dtpreldword. */
17054 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17056 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17059 /* Handle .tprelword. */
17062 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17064 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17067 /* Handle .tpreldword. */
17070 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17072 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17075 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17076 code. It sets the offset to use in gp_rel relocations. */
17079 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17081 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17082 We also need NewABI support. */
17083 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17089 mips_gprel_offset
= get_absolute_expression ();
17091 demand_empty_rest_of_line ();
17094 /* Handle the .gpword pseudo-op. This is used when generating PIC
17095 code. It generates a 32 bit GP relative reloc. */
17098 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17100 segment_info_type
*si
;
17101 struct insn_label_list
*l
;
17105 /* When not generating PIC code, this is treated as .word. */
17106 if (mips_pic
!= SVR4_PIC
)
17112 si
= seg_info (now_seg
);
17113 l
= si
->label_list
;
17114 mips_emit_delays ();
17116 mips_align (2, 0, l
);
17119 mips_clear_insn_labels ();
17121 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17123 as_bad (_("Unsupported use of .gpword"));
17124 ignore_rest_of_line ();
17128 md_number_to_chars (p
, 0, 4);
17129 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17130 BFD_RELOC_GPREL32
);
17132 demand_empty_rest_of_line ();
17136 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17138 segment_info_type
*si
;
17139 struct insn_label_list
*l
;
17143 /* When not generating PIC code, this is treated as .dword. */
17144 if (mips_pic
!= SVR4_PIC
)
17150 si
= seg_info (now_seg
);
17151 l
= si
->label_list
;
17152 mips_emit_delays ();
17154 mips_align (3, 0, l
);
17157 mips_clear_insn_labels ();
17159 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17161 as_bad (_("Unsupported use of .gpdword"));
17162 ignore_rest_of_line ();
17166 md_number_to_chars (p
, 0, 8);
17167 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17168 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17170 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17171 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17172 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17174 demand_empty_rest_of_line ();
17177 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17178 tables. It generates a R_MIPS_EH reloc. */
17181 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17186 mips_emit_delays ();
17189 mips_clear_insn_labels ();
17191 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17193 as_bad (_("Unsupported use of .ehword"));
17194 ignore_rest_of_line ();
17198 md_number_to_chars (p
, 0, 4);
17199 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17200 BFD_RELOC_MIPS_EH
);
17202 demand_empty_rest_of_line ();
17205 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17206 tables in SVR4 PIC code. */
17209 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17213 /* This is ignored when not generating SVR4 PIC code. */
17214 if (mips_pic
!= SVR4_PIC
)
17220 mips_mark_labels ();
17221 mips_assembling_insn
= TRUE
;
17223 /* Add $gp to the register named as an argument. */
17225 reg
= tc_get_register (0);
17226 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17229 mips_assembling_insn
= FALSE
;
17230 demand_empty_rest_of_line ();
17233 /* Handle the .insn pseudo-op. This marks instruction labels in
17234 mips16/micromips mode. This permits the linker to handle them specially,
17235 such as generating jalx instructions when needed. We also make
17236 them odd for the duration of the assembly, in order to generate the
17237 right sort of code. We will make them even in the adjust_symtab
17238 routine, while leaving them marked. This is convenient for the
17239 debugger and the disassembler. The linker knows to make them odd
17243 s_insn (int ignore ATTRIBUTE_UNUSED
)
17245 mips_mark_labels ();
17247 demand_empty_rest_of_line ();
17250 /* Handle a .stab[snd] directive. Ideally these directives would be
17251 implemented in a transparent way, so that removing them would not
17252 have any effect on the generated instructions. However, s_stab
17253 internally changes the section, so in practice we need to decide
17254 now whether the preceding label marks compressed code. We do not
17255 support changing the compression mode of a label after a .stab*
17256 directive, such as in:
17262 so the current mode wins. */
17265 s_mips_stab (int type
)
17267 mips_mark_labels ();
17271 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17274 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17281 name
= input_line_pointer
;
17282 c
= get_symbol_end ();
17283 symbolP
= symbol_find_or_make (name
);
17284 S_SET_WEAK (symbolP
);
17285 *input_line_pointer
= c
;
17287 SKIP_WHITESPACE ();
17289 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17291 if (S_IS_DEFINED (symbolP
))
17293 as_bad (_("ignoring attempt to redefine symbol %s"),
17294 S_GET_NAME (symbolP
));
17295 ignore_rest_of_line ();
17299 if (*input_line_pointer
== ',')
17301 ++input_line_pointer
;
17302 SKIP_WHITESPACE ();
17306 if (exp
.X_op
!= O_symbol
)
17308 as_bad (_("bad .weakext directive"));
17309 ignore_rest_of_line ();
17312 symbol_set_value_expression (symbolP
, &exp
);
17315 demand_empty_rest_of_line ();
17318 /* Parse a register string into a number. Called from the ECOFF code
17319 to parse .frame. The argument is non-zero if this is the frame
17320 register, so that we can record it in mips_frame_reg. */
17323 tc_get_register (int frame
)
17327 SKIP_WHITESPACE ();
17328 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17332 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17333 mips_frame_reg_valid
= 1;
17334 mips_cprestore_valid
= 0;
17340 md_section_align (asection
*seg
, valueT addr
)
17342 int align
= bfd_get_section_alignment (stdoutput
, seg
);
17344 /* We don't need to align ELF sections to the full alignment.
17345 However, Irix 5 may prefer that we align them at least to a 16
17346 byte boundary. We don't bother to align the sections if we
17347 are targeted for an embedded system. */
17348 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17353 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
17356 /* Utility routine, called from above as well. If called while the
17357 input file is still being read, it's only an approximation. (For
17358 example, a symbol may later become defined which appeared to be
17359 undefined earlier.) */
17362 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17367 if (g_switch_value
> 0)
17369 const char *symname
;
17372 /* Find out whether this symbol can be referenced off the $gp
17373 register. It can be if it is smaller than the -G size or if
17374 it is in the .sdata or .sbss section. Certain symbols can
17375 not be referenced off the $gp, although it appears as though
17377 symname
= S_GET_NAME (sym
);
17378 if (symname
!= (const char *) NULL
17379 && (strcmp (symname
, "eprol") == 0
17380 || strcmp (symname
, "etext") == 0
17381 || strcmp (symname
, "_gp") == 0
17382 || strcmp (symname
, "edata") == 0
17383 || strcmp (symname
, "_fbss") == 0
17384 || strcmp (symname
, "_fdata") == 0
17385 || strcmp (symname
, "_ftext") == 0
17386 || strcmp (symname
, "end") == 0
17387 || strcmp (symname
, "_gp_disp") == 0))
17389 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17391 #ifndef NO_ECOFF_DEBUGGING
17392 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17393 && (symbol_get_obj (sym
)->ecoff_extern_size
17394 <= g_switch_value
))
17396 /* We must defer this decision until after the whole
17397 file has been read, since there might be a .extern
17398 after the first use of this symbol. */
17399 || (before_relaxing
17400 #ifndef NO_ECOFF_DEBUGGING
17401 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17403 && S_GET_VALUE (sym
) == 0)
17404 || (S_GET_VALUE (sym
) != 0
17405 && S_GET_VALUE (sym
) <= g_switch_value
)))
17409 const char *segname
;
17411 segname
= segment_name (S_GET_SEGMENT (sym
));
17412 gas_assert (strcmp (segname
, ".lit8") != 0
17413 && strcmp (segname
, ".lit4") != 0);
17414 change
= (strcmp (segname
, ".sdata") != 0
17415 && strcmp (segname
, ".sbss") != 0
17416 && strncmp (segname
, ".sdata.", 7) != 0
17417 && strncmp (segname
, ".sbss.", 6) != 0
17418 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17419 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17424 /* We are not optimizing for the $gp register. */
17429 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17432 pic_need_relax (symbolS
*sym
, asection
*segtype
)
17436 /* Handle the case of a symbol equated to another symbol. */
17437 while (symbol_equated_reloc_p (sym
))
17441 /* It's possible to get a loop here in a badly written program. */
17442 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17448 if (symbol_section_p (sym
))
17451 symsec
= S_GET_SEGMENT (sym
);
17453 /* This must duplicate the test in adjust_reloc_syms. */
17454 return (!bfd_is_und_section (symsec
)
17455 && !bfd_is_abs_section (symsec
)
17456 && !bfd_is_com_section (symsec
)
17457 && !s_is_linkonce (sym
, segtype
)
17458 /* A global or weak symbol is treated as external. */
17459 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17463 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17464 extended opcode. SEC is the section the frag is in. */
17467 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17470 const struct mips16_immed_operand
*op
;
17472 int mintiny
, maxtiny
;
17476 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17478 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17481 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17482 op
= mips16_immed_operands
;
17483 while (op
->type
!= type
)
17486 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
17491 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
17494 maxtiny
= 1 << op
->nbits
;
17499 maxtiny
= (1 << op
->nbits
) - 1;
17504 mintiny
= - (1 << (op
->nbits
- 1));
17505 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
17508 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17509 val
= S_GET_VALUE (fragp
->fr_symbol
);
17510 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17516 /* We won't have the section when we are called from
17517 mips_relax_frag. However, we will always have been called
17518 from md_estimate_size_before_relax first. If this is a
17519 branch to a different section, we mark it as such. If SEC is
17520 NULL, and the frag is not marked, then it must be a branch to
17521 the same section. */
17524 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
17529 /* Must have been called from md_estimate_size_before_relax. */
17532 fragp
->fr_subtype
=
17533 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17535 /* FIXME: We should support this, and let the linker
17536 catch branches and loads that are out of range. */
17537 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
17538 _("unsupported PC relative reference to different section"));
17542 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
17543 /* Assume non-extended on the first relaxation pass.
17544 The address we have calculated will be bogus if this is
17545 a forward branch to another frag, as the forward frag
17546 will have fr_address == 0. */
17550 /* In this case, we know for sure that the symbol fragment is in
17551 the same section. If the relax_marker of the symbol fragment
17552 differs from the relax_marker of this fragment, we have not
17553 yet adjusted the symbol fragment fr_address. We want to add
17554 in STRETCH in order to get a better estimate of the address.
17555 This particularly matters because of the shift bits. */
17557 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17561 /* Adjust stretch for any alignment frag. Note that if have
17562 been expanding the earlier code, the symbol may be
17563 defined in what appears to be an earlier frag. FIXME:
17564 This doesn't handle the fr_subtype field, which specifies
17565 a maximum number of bytes to skip when doing an
17567 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17569 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17572 stretch
= - ((- stretch
)
17573 & ~ ((1 << (int) f
->fr_offset
) - 1));
17575 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17584 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17586 /* The base address rules are complicated. The base address of
17587 a branch is the following instruction. The base address of a
17588 PC relative load or add is the instruction itself, but if it
17589 is in a delay slot (in which case it can not be extended) use
17590 the address of the instruction whose delay slot it is in. */
17591 if (type
== 'p' || type
== 'q')
17595 /* If we are currently assuming that this frag should be
17596 extended, then, the current address is two bytes
17598 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17601 /* Ignore the low bit in the target, since it will be set
17602 for a text label. */
17603 if ((val
& 1) != 0)
17606 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17608 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17611 val
-= addr
& ~ ((1 << op
->shift
) - 1);
17613 /* Branch offsets have an implicit 0 in the lowest bit. */
17614 if (type
== 'p' || type
== 'q')
17617 /* If any of the shifted bits are set, we must use an extended
17618 opcode. If the address depends on the size of this
17619 instruction, this can lead to a loop, so we arrange to always
17620 use an extended opcode. We only check this when we are in
17621 the main relaxation loop, when SEC is NULL. */
17622 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
17624 fragp
->fr_subtype
=
17625 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17629 /* If we are about to mark a frag as extended because the value
17630 is precisely maxtiny + 1, then there is a chance of an
17631 infinite loop as in the following code:
17636 In this case when the la is extended, foo is 0x3fc bytes
17637 away, so the la can be shrunk, but then foo is 0x400 away, so
17638 the la must be extended. To avoid this loop, we mark the
17639 frag as extended if it was small, and is about to become
17640 extended with a value of maxtiny + 1. */
17641 if (val
== ((maxtiny
+ 1) << op
->shift
)
17642 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
17645 fragp
->fr_subtype
=
17646 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
17650 else if (symsec
!= absolute_section
&& sec
!= NULL
)
17651 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
17653 if ((val
& ((1 << op
->shift
) - 1)) != 0
17654 || val
< (mintiny
<< op
->shift
)
17655 || val
> (maxtiny
<< op
->shift
))
17661 /* Compute the length of a branch sequence, and adjust the
17662 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17663 worst-case length is computed, with UPDATE being used to indicate
17664 whether an unconditional (-1), branch-likely (+1) or regular (0)
17665 branch is to be computed. */
17667 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17669 bfd_boolean toofar
;
17673 && S_IS_DEFINED (fragp
->fr_symbol
)
17674 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17679 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17681 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17685 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17688 /* If the symbol is not defined or it's in a different segment,
17689 assume the user knows what's going on and emit a short
17695 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17697 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17698 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17699 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17700 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17706 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17709 if (mips_pic
!= NO_PIC
)
17711 /* Additional space for PIC loading of target address. */
17713 if (mips_opts
.isa
== ISA_MIPS1
)
17714 /* Additional space for $at-stabilizing nop. */
17718 /* If branch is conditional. */
17719 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17726 /* Compute the length of a branch sequence, and adjust the
17727 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17728 worst-case length is computed, with UPDATE being used to indicate
17729 whether an unconditional (-1), or regular (0) branch is to be
17733 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17735 bfd_boolean toofar
;
17739 && S_IS_DEFINED (fragp
->fr_symbol
)
17740 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17745 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17746 /* Ignore the low bit in the target, since it will be set
17747 for a text label. */
17748 if ((val
& 1) != 0)
17751 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17755 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
17758 /* If the symbol is not defined or it's in a different segment,
17759 assume the user knows what's going on and emit a short
17765 if (fragp
&& update
17766 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
17767 fragp
->fr_subtype
= (toofar
17768 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
17769 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
17774 bfd_boolean compact_known
= fragp
!= NULL
;
17775 bfd_boolean compact
= FALSE
;
17776 bfd_boolean uncond
;
17779 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
17781 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
17783 uncond
= update
< 0;
17785 /* If label is out of range, we turn branch <br>:
17787 <br> label # 4 bytes
17793 nop # 2 bytes if compact && !PIC
17796 if (mips_pic
== NO_PIC
&& (!compact_known
|| compact
))
17799 /* If assembling PIC code, we further turn:
17805 lw/ld at, %got(label)(gp) # 4 bytes
17806 d/addiu at, %lo(label) # 4 bytes
17809 if (mips_pic
!= NO_PIC
)
17812 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17814 <brneg> 0f # 4 bytes
17815 nop # 2 bytes if !compact
17818 length
+= (compact_known
&& compact
) ? 4 : 6;
17824 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17825 bit accordingly. */
17828 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17830 bfd_boolean toofar
;
17833 && S_IS_DEFINED (fragp
->fr_symbol
)
17834 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17840 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17841 /* Ignore the low bit in the target, since it will be set
17842 for a text label. */
17843 if ((val
& 1) != 0)
17846 /* Assume this is a 2-byte branch. */
17847 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
17849 /* We try to avoid the infinite loop by not adding 2 more bytes for
17854 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
17856 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
17857 else if (type
== 'E')
17858 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
17863 /* If the symbol is not defined or it's in a different segment,
17864 we emit a normal 32-bit branch. */
17867 if (fragp
&& update
17868 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
17870 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
17871 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
17879 /* Estimate the size of a frag before relaxing. Unless this is the
17880 mips16, we are not really relaxing here, and the final size is
17881 encoded in the subtype information. For the mips16, we have to
17882 decide whether we are using an extended opcode or not. */
17885 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
17889 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
17892 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
17894 return fragp
->fr_var
;
17897 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
17898 /* We don't want to modify the EXTENDED bit here; it might get us
17899 into infinite loops. We change it only in mips_relax_frag(). */
17900 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
17902 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
17906 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
17907 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
17908 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
17909 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
17910 fragp
->fr_var
= length
;
17915 if (mips_pic
== NO_PIC
)
17916 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
17917 else if (mips_pic
== SVR4_PIC
)
17918 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
17919 else if (mips_pic
== VXWORKS_PIC
)
17920 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17927 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
17928 return -RELAX_FIRST (fragp
->fr_subtype
);
17931 return -RELAX_SECOND (fragp
->fr_subtype
);
17934 /* This is called to see whether a reloc against a defined symbol
17935 should be converted into a reloc against a section. */
17938 mips_fix_adjustable (fixS
*fixp
)
17940 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
17941 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
17944 if (fixp
->fx_addsy
== NULL
)
17947 /* If symbol SYM is in a mergeable section, relocations of the form
17948 SYM + 0 can usually be made section-relative. The mergeable data
17949 is then identified by the section offset rather than by the symbol.
17951 However, if we're generating REL LO16 relocations, the offset is split
17952 between the LO16 and parterning high part relocation. The linker will
17953 need to recalculate the complete offset in order to correctly identify
17956 The linker has traditionally not looked for the parterning high part
17957 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17958 placed anywhere. Rather than break backwards compatibility by changing
17959 this, it seems better not to force the issue, and instead keep the
17960 original symbol. This will work with either linker behavior. */
17961 if ((lo16_reloc_p (fixp
->fx_r_type
)
17962 || reloc_needs_lo_p (fixp
->fx_r_type
))
17963 && HAVE_IN_PLACE_ADDENDS
17964 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
17967 /* There is no place to store an in-place offset for JALR relocations.
17968 Likewise an in-range offset of limited PC-relative relocations may
17969 overflow the in-place relocatable field if recalculated against the
17970 start address of the symbol's containing section. */
17971 if (HAVE_IN_PLACE_ADDENDS
17972 && (limited_pcrel_reloc_p (fixp
->fx_r_type
)
17973 || jalr_reloc_p (fixp
->fx_r_type
)))
17976 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17977 to a floating-point stub. The same is true for non-R_MIPS16_26
17978 relocations against MIPS16 functions; in this case, the stub becomes
17979 the function's canonical address.
17981 Floating-point stubs are stored in unique .mips16.call.* or
17982 .mips16.fn.* sections. If a stub T for function F is in section S,
17983 the first relocation in section S must be against F; this is how the
17984 linker determines the target function. All relocations that might
17985 resolve to T must also be against F. We therefore have the following
17986 restrictions, which are given in an intentionally-redundant way:
17988 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17991 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17992 if that stub might be used.
17994 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17997 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17998 that stub might be used.
18000 There is a further restriction:
18002 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18003 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
18004 targets with in-place addends; the relocation field cannot
18005 encode the low bit.
18007 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18008 against a MIPS16 symbol. We deal with (5) by by not reducing any
18009 such relocations on REL targets.
18011 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18012 relocation against some symbol R, no relocation against R may be
18013 reduced. (Note that this deals with (2) as well as (1) because
18014 relocations against global symbols will never be reduced on ELF
18015 targets.) This approach is a little simpler than trying to detect
18016 stub sections, and gives the "all or nothing" per-symbol consistency
18017 that we have for MIPS16 symbols. */
18018 if (fixp
->fx_subsy
== NULL
18019 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18020 || *symbol_get_tc (fixp
->fx_addsy
)
18021 || (HAVE_IN_PLACE_ADDENDS
18022 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18023 && jmp_reloc_p (fixp
->fx_r_type
))))
18029 /* Translate internal representation of relocation info to BFD target
18033 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18035 static arelent
*retval
[4];
18037 bfd_reloc_code_real_type code
;
18039 memset (retval
, 0, sizeof(retval
));
18040 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
18041 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
18042 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18043 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18045 if (fixp
->fx_pcrel
)
18047 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18048 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18049 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18050 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18051 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
);
18053 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18054 Relocations want only the symbol offset. */
18055 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18058 reloc
->addend
= fixp
->fx_addnumber
;
18060 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18061 entry to be used in the relocation's section offset. */
18062 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18064 reloc
->address
= reloc
->addend
;
18068 code
= fixp
->fx_r_type
;
18070 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18071 if (reloc
->howto
== NULL
)
18073 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18074 _("Can not represent %s relocation in this object file format"),
18075 bfd_get_reloc_code_name (code
));
18082 /* Relax a machine dependent frag. This returns the amount by which
18083 the current size of the frag should change. */
18086 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18088 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18090 offsetT old_var
= fragp
->fr_var
;
18092 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18094 return fragp
->fr_var
- old_var
;
18097 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18099 offsetT old_var
= fragp
->fr_var
;
18100 offsetT new_var
= 4;
18102 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18103 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18104 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18105 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18106 fragp
->fr_var
= new_var
;
18108 return new_var
- old_var
;
18111 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18114 if (mips16_extended_frag (fragp
, NULL
, stretch
))
18116 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18118 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18123 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18125 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18132 /* Convert a machine dependent frag. */
18135 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18137 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18140 unsigned long insn
;
18144 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18145 insn
= read_insn (buf
);
18147 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18149 /* We generate a fixup instead of applying it right now
18150 because, if there are linker relaxations, we're going to
18151 need the relocations. */
18152 exp
.X_op
= O_symbol
;
18153 exp
.X_add_symbol
= fragp
->fr_symbol
;
18154 exp
.X_add_number
= fragp
->fr_offset
;
18156 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18157 BFD_RELOC_16_PCREL_S2
);
18158 fixp
->fx_file
= fragp
->fr_file
;
18159 fixp
->fx_line
= fragp
->fr_line
;
18161 buf
= write_insn (buf
, insn
);
18167 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18168 _("Relaxed out-of-range branch into a jump"));
18170 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18173 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18175 /* Reverse the branch. */
18176 switch ((insn
>> 28) & 0xf)
18179 /* bc[0-3][tf]l? instructions can have the condition
18180 reversed by tweaking a single TF bit, and their
18181 opcodes all have 0x4???????. */
18182 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18183 insn
^= 0x00010000;
18187 /* bltz 0x04000000 bgez 0x04010000
18188 bltzal 0x04100000 bgezal 0x04110000 */
18189 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18190 insn
^= 0x00010000;
18194 /* beq 0x10000000 bne 0x14000000
18195 blez 0x18000000 bgtz 0x1c000000 */
18196 insn
^= 0x04000000;
18204 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18206 /* Clear the and-link bit. */
18207 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18209 /* bltzal 0x04100000 bgezal 0x04110000
18210 bltzall 0x04120000 bgezall 0x04130000 */
18211 insn
&= ~0x00100000;
18214 /* Branch over the branch (if the branch was likely) or the
18215 full jump (not likely case). Compute the offset from the
18216 current instruction to branch to. */
18217 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18221 /* How many bytes in instructions we've already emitted? */
18222 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18223 /* How many bytes in instructions from here to the end? */
18224 i
= fragp
->fr_var
- i
;
18226 /* Convert to instruction count. */
18228 /* Branch counts from the next instruction. */
18231 /* Branch over the jump. */
18232 buf
= write_insn (buf
, insn
);
18235 buf
= write_insn (buf
, 0);
18237 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18239 /* beql $0, $0, 2f */
18241 /* Compute the PC offset from the current instruction to
18242 the end of the variable frag. */
18243 /* How many bytes in instructions we've already emitted? */
18244 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18245 /* How many bytes in instructions from here to the end? */
18246 i
= fragp
->fr_var
- i
;
18247 /* Convert to instruction count. */
18249 /* Don't decrement i, because we want to branch over the
18253 buf
= write_insn (buf
, insn
);
18254 buf
= write_insn (buf
, 0);
18258 if (mips_pic
== NO_PIC
)
18261 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18262 ? 0x0c000000 : 0x08000000);
18263 exp
.X_op
= O_symbol
;
18264 exp
.X_add_symbol
= fragp
->fr_symbol
;
18265 exp
.X_add_number
= fragp
->fr_offset
;
18267 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18268 FALSE
, BFD_RELOC_MIPS_JMP
);
18269 fixp
->fx_file
= fragp
->fr_file
;
18270 fixp
->fx_line
= fragp
->fr_line
;
18272 buf
= write_insn (buf
, insn
);
18276 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18278 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18279 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18280 insn
|= at
<< OP_SH_RT
;
18281 exp
.X_op
= O_symbol
;
18282 exp
.X_add_symbol
= fragp
->fr_symbol
;
18283 exp
.X_add_number
= fragp
->fr_offset
;
18285 if (fragp
->fr_offset
)
18287 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18288 exp
.X_add_number
= 0;
18291 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18292 FALSE
, BFD_RELOC_MIPS_GOT16
);
18293 fixp
->fx_file
= fragp
->fr_file
;
18294 fixp
->fx_line
= fragp
->fr_line
;
18296 buf
= write_insn (buf
, insn
);
18298 if (mips_opts
.isa
== ISA_MIPS1
)
18300 buf
= write_insn (buf
, 0);
18302 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18303 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18304 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18306 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
,
18307 FALSE
, BFD_RELOC_LO16
);
18308 fixp
->fx_file
= fragp
->fr_file
;
18309 fixp
->fx_line
= fragp
->fr_line
;
18311 buf
= write_insn (buf
, insn
);
18314 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18318 insn
|= at
<< OP_SH_RS
;
18320 buf
= write_insn (buf
, insn
);
18324 fragp
->fr_fix
+= fragp
->fr_var
;
18325 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18329 /* Relax microMIPS branches. */
18330 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18332 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18333 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18334 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18335 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18336 bfd_boolean short_ds
;
18337 unsigned long insn
;
18341 exp
.X_op
= O_symbol
;
18342 exp
.X_add_symbol
= fragp
->fr_symbol
;
18343 exp
.X_add_number
= fragp
->fr_offset
;
18345 fragp
->fr_fix
+= fragp
->fr_var
;
18347 /* Handle 16-bit branches that fit or are forced to fit. */
18348 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18350 /* We generate a fixup instead of applying it right now,
18351 because if there is linker relaxation, we're going to
18352 need the relocations. */
18354 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18355 BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18356 else if (type
== 'E')
18357 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 2, &exp
, TRUE
,
18358 BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18362 fixp
->fx_file
= fragp
->fr_file
;
18363 fixp
->fx_line
= fragp
->fr_line
;
18365 /* These relocations can have an addend that won't fit in
18367 fixp
->fx_no_overflow
= 1;
18372 /* Handle 32-bit branches that fit or are forced to fit. */
18373 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18374 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18376 /* We generate a fixup instead of applying it right now,
18377 because if there is linker relaxation, we're going to
18378 need the relocations. */
18379 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, TRUE
,
18380 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18381 fixp
->fx_file
= fragp
->fr_file
;
18382 fixp
->fx_line
= fragp
->fr_line
;
18388 /* Relax 16-bit branches to 32-bit branches. */
18391 insn
= read_compressed_insn (buf
, 2);
18393 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18394 insn
= 0x94000000; /* beq */
18395 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18397 unsigned long regno
;
18399 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18400 regno
= micromips_to_32_reg_d_map
[regno
];
18401 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18402 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18407 /* Nothing else to do, just write it out. */
18408 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18409 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18411 buf
= write_compressed_insn (buf
, insn
, 4);
18412 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18417 insn
= read_compressed_insn (buf
, 4);
18419 /* Relax 32-bit branches to a sequence of instructions. */
18420 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18421 _("Relaxed out-of-range branch into a jump"));
18423 /* Set the short-delay-slot bit. */
18424 short_ds
= al
&& (insn
& 0x02000000) != 0;
18426 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18430 /* Reverse the branch. */
18431 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18432 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18433 insn
^= 0x20000000;
18434 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18435 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18436 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18437 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18438 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18439 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18440 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18441 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18442 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18443 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18444 insn
^= 0x00400000;
18445 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18446 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18447 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18448 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18449 insn
^= 0x00200000;
18455 /* Clear the and-link and short-delay-slot bits. */
18456 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18458 /* bltzal 0x40200000 bgezal 0x40600000 */
18459 /* bltzals 0x42200000 bgezals 0x42600000 */
18460 insn
&= ~0x02200000;
18463 /* Make a label at the end for use with the branch. */
18464 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18465 micromips_label_inc ();
18466 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18469 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18470 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18471 fixp
->fx_file
= fragp
->fr_file
;
18472 fixp
->fx_line
= fragp
->fr_line
;
18474 /* Branch over the jump. */
18475 buf
= write_compressed_insn (buf
, insn
, 4);
18478 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18481 if (mips_pic
== NO_PIC
)
18483 unsigned long jal
= short_ds
? 0x74000000 : 0xf4000000; /* jal/s */
18485 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18486 insn
= al
? jal
: 0xd4000000;
18488 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18489 BFD_RELOC_MICROMIPS_JMP
);
18490 fixp
->fx_file
= fragp
->fr_file
;
18491 fixp
->fx_line
= fragp
->fr_line
;
18493 buf
= write_compressed_insn (buf
, insn
, 4);
18496 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18500 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18501 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18502 unsigned long jr
= compact
? 0x45a0 : 0x4580; /* jr/c */
18504 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18505 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18506 insn
|= at
<< MICROMIPSOP_SH_RT
;
18508 if (exp
.X_add_number
)
18510 exp
.X_add_symbol
= make_expr_symbol (&exp
);
18511 exp
.X_add_number
= 0;
18514 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18515 BFD_RELOC_MICROMIPS_GOT16
);
18516 fixp
->fx_file
= fragp
->fr_file
;
18517 fixp
->fx_line
= fragp
->fr_line
;
18519 buf
= write_compressed_insn (buf
, insn
, 4);
18521 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18522 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18523 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18525 fixp
= fix_new_exp (fragp
, buf
- fragp
->fr_literal
, 4, &exp
, FALSE
,
18526 BFD_RELOC_MICROMIPS_LO16
);
18527 fixp
->fx_file
= fragp
->fr_file
;
18528 fixp
->fx_line
= fragp
->fr_line
;
18530 buf
= write_compressed_insn (buf
, insn
, 4);
18532 /* jr/jrc/jalr/jalrs $at */
18533 insn
= al
? jalr
: jr
;
18534 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18536 buf
= write_compressed_insn (buf
, insn
, 2);
18539 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18543 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18546 const struct mips16_immed_operand
*op
;
18549 unsigned int user_length
, length
;
18550 unsigned long insn
;
18553 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18554 op
= mips16_immed_operands
;
18555 while (op
->type
!= type
)
18558 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18559 val
= resolve_symbol_value (fragp
->fr_symbol
);
18564 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18566 /* The rules for the base address of a PC relative reloc are
18567 complicated; see mips16_extended_frag. */
18568 if (type
== 'p' || type
== 'q')
18573 /* Ignore the low bit in the target, since it will be
18574 set for a text label. */
18575 if ((val
& 1) != 0)
18578 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
18580 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
18583 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
18586 /* Make sure the section winds up with the alignment we have
18589 record_alignment (asec
, op
->shift
);
18593 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
18594 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
18595 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18596 _("extended instruction in delay slot"));
18598 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18600 insn
= read_compressed_insn (buf
, 2);
18602 insn
|= MIPS16_EXTEND
;
18604 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
18606 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
18611 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
18612 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
18614 length
= (ext
? 4 : 2);
18615 gas_assert (mips16_opcode_length (insn
) == length
);
18616 write_compressed_insn (buf
, insn
, length
);
18617 fragp
->fr_fix
+= length
;
18621 relax_substateT subtype
= fragp
->fr_subtype
;
18622 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
18623 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
18627 first
= RELAX_FIRST (subtype
);
18628 second
= RELAX_SECOND (subtype
);
18629 fixp
= (fixS
*) fragp
->fr_opcode
;
18631 /* If the delay slot chosen does not match the size of the instruction,
18632 then emit a warning. */
18633 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
18634 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
18639 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
18640 | RELAX_DELAY_SLOT_SIZE_FIRST
18641 | RELAX_DELAY_SLOT_SIZE_SECOND
);
18642 msg
= macro_warning (s
);
18644 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18648 /* Possibly emit a warning if we've chosen the longer option. */
18649 if (use_second
== second_longer
)
18655 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
18656 msg
= macro_warning (s
);
18658 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
18662 /* Go through all the fixups for the first sequence. Disable them
18663 (by marking them as done) if we're going to use the second
18664 sequence instead. */
18666 && fixp
->fx_frag
== fragp
18667 && fixp
->fx_where
< fragp
->fr_fix
- second
)
18669 if (subtype
& RELAX_USE_SECOND
)
18671 fixp
= fixp
->fx_next
;
18674 /* Go through the fixups for the second sequence. Disable them if
18675 we're going to use the first sequence, otherwise adjust their
18676 addresses to account for the relaxation. */
18677 while (fixp
&& fixp
->fx_frag
== fragp
)
18679 if (subtype
& RELAX_USE_SECOND
)
18680 fixp
->fx_where
-= first
;
18683 fixp
= fixp
->fx_next
;
18686 /* Now modify the frag contents. */
18687 if (subtype
& RELAX_USE_SECOND
)
18691 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
18692 memmove (start
, start
+ first
, second
);
18693 fragp
->fr_fix
-= first
;
18696 fragp
->fr_fix
-= second
;
18700 /* This function is called after the relocs have been generated.
18701 We've been storing mips16 text labels as odd. Here we convert them
18702 back to even for the convenience of the debugger. */
18705 mips_frob_file_after_relocs (void)
18708 unsigned int count
, i
;
18710 syms
= bfd_get_outsymbols (stdoutput
);
18711 count
= bfd_get_symcount (stdoutput
);
18712 for (i
= 0; i
< count
; i
++, syms
++)
18713 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
18714 && ((*syms
)->value
& 1) != 0)
18716 (*syms
)->value
&= ~1;
18717 /* If the symbol has an odd size, it was probably computed
18718 incorrectly, so adjust that as well. */
18719 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
18720 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
18724 /* This function is called whenever a label is defined, including fake
18725 labels instantiated off the dot special symbol. It is used when
18726 handling branch delays; if a branch has a label, we assume we cannot
18727 move it. This also bumps the value of the symbol by 1 in compressed
18731 mips_record_label (symbolS
*sym
)
18733 segment_info_type
*si
= seg_info (now_seg
);
18734 struct insn_label_list
*l
;
18736 if (free_insn_labels
== NULL
)
18737 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
18740 l
= free_insn_labels
;
18741 free_insn_labels
= l
->next
;
18745 l
->next
= si
->label_list
;
18746 si
->label_list
= l
;
18749 /* This function is called as tc_frob_label() whenever a label is defined
18750 and adds a DWARF-2 record we only want for true labels. */
18753 mips_define_label (symbolS
*sym
)
18755 mips_record_label (sym
);
18756 dwarf2_emit_label (sym
);
18759 /* This function is called by tc_new_dot_label whenever a new dot symbol
18763 mips_add_dot_label (symbolS
*sym
)
18765 mips_record_label (sym
);
18766 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
18767 mips_compressed_mark_label (sym
);
18770 /* Some special processing for a MIPS ELF file. */
18773 mips_elf_final_processing (void)
18775 /* Write out the register information. */
18776 if (mips_abi
!= N64_ABI
)
18780 s
.ri_gprmask
= mips_gprmask
;
18781 s
.ri_cprmask
[0] = mips_cprmask
[0];
18782 s
.ri_cprmask
[1] = mips_cprmask
[1];
18783 s
.ri_cprmask
[2] = mips_cprmask
[2];
18784 s
.ri_cprmask
[3] = mips_cprmask
[3];
18785 /* The gp_value field is set by the MIPS ELF backend. */
18787 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
18788 ((Elf32_External_RegInfo
*)
18789 mips_regmask_frag
));
18793 Elf64_Internal_RegInfo s
;
18795 s
.ri_gprmask
= mips_gprmask
;
18797 s
.ri_cprmask
[0] = mips_cprmask
[0];
18798 s
.ri_cprmask
[1] = mips_cprmask
[1];
18799 s
.ri_cprmask
[2] = mips_cprmask
[2];
18800 s
.ri_cprmask
[3] = mips_cprmask
[3];
18801 /* The gp_value field is set by the MIPS ELF backend. */
18803 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
18804 ((Elf64_External_RegInfo
*)
18805 mips_regmask_frag
));
18808 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18809 sort of BFD interface for this. */
18810 if (mips_any_noreorder
)
18811 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
18812 if (mips_pic
!= NO_PIC
)
18814 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
18815 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18818 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
18820 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18821 defined at present; this might need to change in future. */
18822 if (file_ase_mips16
)
18823 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
18824 if (file_ase_micromips
)
18825 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
18826 if (file_ase
& ASE_MDMX
)
18827 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
18829 /* Set the MIPS ELF ABI flags. */
18830 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
18831 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
18832 else if (mips_abi
== O64_ABI
)
18833 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
18834 else if (mips_abi
== EABI_ABI
)
18836 if (!file_mips_gp32
)
18837 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
18839 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
18841 else if (mips_abi
== N32_ABI
)
18842 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
18844 /* Nothing to do for N64_ABI. */
18846 if (mips_32bitmode
)
18847 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
18849 #if 0 /* XXX FIXME */
18850 /* 32 bit code with 64 bit FP registers. */
18851 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
18852 elf_elfheader (stdoutput
)->e_flags
|= ???;
18856 typedef struct proc
{
18858 symbolS
*func_end_sym
;
18859 unsigned long reg_mask
;
18860 unsigned long reg_offset
;
18861 unsigned long fpreg_mask
;
18862 unsigned long fpreg_offset
;
18863 unsigned long frame_offset
;
18864 unsigned long frame_reg
;
18865 unsigned long pc_reg
;
18868 static procS cur_proc
;
18869 static procS
*cur_proc_ptr
;
18870 static int numprocs
;
18872 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18873 as "2", and a normal nop as "0". */
18875 #define NOP_OPCODE_MIPS 0
18876 #define NOP_OPCODE_MIPS16 1
18877 #define NOP_OPCODE_MICROMIPS 2
18880 mips_nop_opcode (void)
18882 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
18883 return NOP_OPCODE_MICROMIPS
;
18884 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
18885 return NOP_OPCODE_MIPS16
;
18887 return NOP_OPCODE_MIPS
;
18890 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18891 32-bit microMIPS NOPs here (if applicable). */
18894 mips_handle_align (fragS
*fragp
)
18898 int bytes
, size
, excess
;
18901 if (fragp
->fr_type
!= rs_align_code
)
18904 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
18906 switch (nop_opcode
)
18908 case NOP_OPCODE_MICROMIPS
:
18909 opcode
= micromips_nop32_insn
.insn_opcode
;
18912 case NOP_OPCODE_MIPS16
:
18913 opcode
= mips16_nop_insn
.insn_opcode
;
18916 case NOP_OPCODE_MIPS
:
18918 opcode
= nop_insn
.insn_opcode
;
18923 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
18924 excess
= bytes
% size
;
18926 /* Handle the leading part if we're not inserting a whole number of
18927 instructions, and make it the end of the fixed part of the frag.
18928 Try to fit in a short microMIPS NOP if applicable and possible,
18929 and use zeroes otherwise. */
18930 gas_assert (excess
< 4);
18931 fragp
->fr_fix
+= excess
;
18936 /* Fall through. */
18938 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
18940 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
18944 /* Fall through. */
18947 /* Fall through. */
18952 md_number_to_chars (p
, opcode
, size
);
18953 fragp
->fr_var
= size
;
18957 md_obj_begin (void)
18964 /* Check for premature end, nesting errors, etc. */
18966 as_warn (_("missing .end at end of assembly"));
18975 if (*input_line_pointer
== '-')
18977 ++input_line_pointer
;
18980 if (!ISDIGIT (*input_line_pointer
))
18981 as_bad (_("expected simple number"));
18982 if (input_line_pointer
[0] == '0')
18984 if (input_line_pointer
[1] == 'x')
18986 input_line_pointer
+= 2;
18987 while (ISXDIGIT (*input_line_pointer
))
18990 val
|= hex_value (*input_line_pointer
++);
18992 return negative
? -val
: val
;
18996 ++input_line_pointer
;
18997 while (ISDIGIT (*input_line_pointer
))
19000 val
|= *input_line_pointer
++ - '0';
19002 return negative
? -val
: val
;
19005 if (!ISDIGIT (*input_line_pointer
))
19007 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19008 *input_line_pointer
, *input_line_pointer
);
19009 as_warn (_("invalid number"));
19012 while (ISDIGIT (*input_line_pointer
))
19015 val
+= *input_line_pointer
++ - '0';
19017 return negative
? -val
: val
;
19020 /* The .file directive; just like the usual .file directive, but there
19021 is an initial number which is the ECOFF file index. In the non-ECOFF
19022 case .file implies DWARF-2. */
19025 s_mips_file (int x ATTRIBUTE_UNUSED
)
19027 static int first_file_directive
= 0;
19029 if (ECOFF_DEBUGGING
)
19038 filename
= dwarf2_directive_file (0);
19040 /* Versions of GCC up to 3.1 start files with a ".file"
19041 directive even for stabs output. Make sure that this
19042 ".file" is handled. Note that you need a version of GCC
19043 after 3.1 in order to support DWARF-2 on MIPS. */
19044 if (filename
!= NULL
&& ! first_file_directive
)
19046 (void) new_logical_line (filename
, -1);
19047 s_app_file_string (filename
, 0);
19049 first_file_directive
= 1;
19053 /* The .loc directive, implying DWARF-2. */
19056 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19058 if (!ECOFF_DEBUGGING
)
19059 dwarf2_directive_loc (0);
19062 /* The .end directive. */
19065 s_mips_end (int x ATTRIBUTE_UNUSED
)
19069 /* Following functions need their own .frame and .cprestore directives. */
19070 mips_frame_reg_valid
= 0;
19071 mips_cprestore_valid
= 0;
19073 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19076 demand_empty_rest_of_line ();
19081 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19082 as_warn (_(".end not in text section"));
19086 as_warn (_(".end directive without a preceding .ent directive."));
19087 demand_empty_rest_of_line ();
19093 gas_assert (S_GET_NAME (p
));
19094 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19095 as_warn (_(".end symbol does not match .ent symbol."));
19097 if (debug_type
== DEBUG_STABS
)
19098 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19102 as_warn (_(".end directive missing or unknown symbol"));
19104 /* Create an expression to calculate the size of the function. */
19105 if (p
&& cur_proc_ptr
)
19107 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19108 expressionS
*exp
= xmalloc (sizeof (expressionS
));
19111 exp
->X_op
= O_subtract
;
19112 exp
->X_add_symbol
= symbol_temp_new_now ();
19113 exp
->X_op_symbol
= p
;
19114 exp
->X_add_number
= 0;
19116 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19119 /* Generate a .pdr section. */
19120 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19122 segT saved_seg
= now_seg
;
19123 subsegT saved_subseg
= now_subseg
;
19127 #ifdef md_flush_pending_output
19128 md_flush_pending_output ();
19131 gas_assert (pdr_seg
);
19132 subseg_set (pdr_seg
, 0);
19134 /* Write the symbol. */
19135 exp
.X_op
= O_symbol
;
19136 exp
.X_add_symbol
= p
;
19137 exp
.X_add_number
= 0;
19138 emit_expr (&exp
, 4);
19140 fragp
= frag_more (7 * 4);
19142 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19143 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19144 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19145 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19146 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19147 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19148 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19150 subseg_set (saved_seg
, saved_subseg
);
19153 cur_proc_ptr
= NULL
;
19156 /* The .aent and .ent directives. */
19159 s_mips_ent (int aent
)
19163 symbolP
= get_symbol ();
19164 if (*input_line_pointer
== ',')
19165 ++input_line_pointer
;
19166 SKIP_WHITESPACE ();
19167 if (ISDIGIT (*input_line_pointer
)
19168 || *input_line_pointer
== '-')
19171 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
19172 as_warn (_(".ent or .aent not in text section."));
19174 if (!aent
&& cur_proc_ptr
)
19175 as_warn (_("missing .end"));
19179 /* This function needs its own .frame and .cprestore directives. */
19180 mips_frame_reg_valid
= 0;
19181 mips_cprestore_valid
= 0;
19183 cur_proc_ptr
= &cur_proc
;
19184 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19186 cur_proc_ptr
->func_sym
= symbolP
;
19190 if (debug_type
== DEBUG_STABS
)
19191 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19192 S_GET_NAME (symbolP
));
19195 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19197 demand_empty_rest_of_line ();
19200 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19201 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19202 s_mips_frame is used so that we can set the PDR information correctly.
19203 We can't use the ecoff routines because they make reference to the ecoff
19204 symbol table (in the mdebug section). */
19207 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19209 if (ECOFF_DEBUGGING
)
19215 if (cur_proc_ptr
== (procS
*) NULL
)
19217 as_warn (_(".frame outside of .ent"));
19218 demand_empty_rest_of_line ();
19222 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19224 SKIP_WHITESPACE ();
19225 if (*input_line_pointer
++ != ','
19226 || get_absolute_expression_and_terminator (&val
) != ',')
19228 as_warn (_("Bad .frame directive"));
19229 --input_line_pointer
;
19230 demand_empty_rest_of_line ();
19234 cur_proc_ptr
->frame_offset
= val
;
19235 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19237 demand_empty_rest_of_line ();
19241 /* The .fmask and .mask directives. If the mdebug section is present
19242 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19243 embedded targets, s_mips_mask is used so that we can set the PDR
19244 information correctly. We can't use the ecoff routines because they
19245 make reference to the ecoff symbol table (in the mdebug section). */
19248 s_mips_mask (int reg_type
)
19250 if (ECOFF_DEBUGGING
)
19251 s_ignore (reg_type
);
19256 if (cur_proc_ptr
== (procS
*) NULL
)
19258 as_warn (_(".mask/.fmask outside of .ent"));
19259 demand_empty_rest_of_line ();
19263 if (get_absolute_expression_and_terminator (&mask
) != ',')
19265 as_warn (_("Bad .mask/.fmask directive"));
19266 --input_line_pointer
;
19267 demand_empty_rest_of_line ();
19271 off
= get_absolute_expression ();
19273 if (reg_type
== 'F')
19275 cur_proc_ptr
->fpreg_mask
= mask
;
19276 cur_proc_ptr
->fpreg_offset
= off
;
19280 cur_proc_ptr
->reg_mask
= mask
;
19281 cur_proc_ptr
->reg_offset
= off
;
19284 demand_empty_rest_of_line ();
19288 /* A table describing all the processors gas knows about. Names are
19289 matched in the order listed.
19291 To ease comparison, please keep this table in the same order as
19292 gcc's mips_cpu_info_table[]. */
19293 static const struct mips_cpu_info mips_cpu_info_table
[] =
19295 /* Entries for generic ISAs */
19296 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19297 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19298 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19299 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19300 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19301 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19302 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19303 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19304 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19307 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19308 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19309 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19312 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
19315 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
19316 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
19317 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
19318 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
19319 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19320 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
19321 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
19322 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
19323 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
19324 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
19325 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
19326 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
19327 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
19328 /* ST Microelectronics Loongson 2E and 2F cores */
19329 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
19330 { "loongson2f", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
19333 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
19334 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
19335 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
19336 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
19337 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
19338 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
19339 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
19340 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
19341 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
19342 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
19343 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
19344 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
19345 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
19346 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
19347 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
19350 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19351 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19352 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
19353 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
19355 /* MIPS 32 Release 2 */
19356 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19357 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19358 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19359 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19360 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19361 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19362 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19363 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19364 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19365 ISA_MIPS32R2
, CPU_MIPS32R2
},
19366 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
19367 ISA_MIPS32R2
, CPU_MIPS32R2
},
19368 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19369 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19370 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19371 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19372 /* Deprecated forms of the above. */
19373 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19374 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19375 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19376 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19377 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19378 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19379 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19380 /* Deprecated forms of the above. */
19381 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19382 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19383 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19384 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19385 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19386 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19387 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19388 /* Deprecated forms of the above. */
19389 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19390 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19391 /* 34Kn is a 34kc without DSP. */
19392 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19393 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19394 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19395 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19396 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19397 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19398 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19399 /* Deprecated forms of the above. */
19400 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19401 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19402 /* 1004K cores are multiprocessor versions of the 34K. */
19403 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19404 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19405 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19406 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
19409 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19410 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
19411 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19412 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
19414 /* Broadcom SB-1 CPU core */
19415 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19416 /* Broadcom SB-1A CPU core */
19417 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
19419 { "loongson3a", 0, 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
19421 /* MIPS 64 Release 2 */
19423 /* Cavium Networks Octeon CPU core */
19424 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
19425 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
19426 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
19429 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
19432 XLP is mostly like XLR, with the prominent exception that it is
19433 MIPS64R2 rather than MIPS64. */
19434 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
19437 { NULL
, 0, 0, 0, 0 }
19441 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19442 with a final "000" replaced by "k". Ignore case.
19444 Note: this function is shared between GCC and GAS. */
19447 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
19449 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
19450 given
++, canonical
++;
19452 return ((*given
== 0 && *canonical
== 0)
19453 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
19457 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19458 CPU name. We've traditionally allowed a lot of variation here.
19460 Note: this function is shared between GCC and GAS. */
19463 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
19465 /* First see if the name matches exactly, or with a final "000"
19466 turned into "k". */
19467 if (mips_strict_matching_cpu_name_p (canonical
, given
))
19470 /* If not, try comparing based on numerical designation alone.
19471 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19472 if (TOLOWER (*given
) == 'r')
19474 if (!ISDIGIT (*given
))
19477 /* Skip over some well-known prefixes in the canonical name,
19478 hoping to find a number there too. */
19479 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
19481 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
19483 else if (TOLOWER (canonical
[0]) == 'r')
19486 return mips_strict_matching_cpu_name_p (canonical
, given
);
19490 /* Parse an option that takes the name of a processor as its argument.
19491 OPTION is the name of the option and CPU_STRING is the argument.
19492 Return the corresponding processor enumeration if the CPU_STRING is
19493 recognized, otherwise report an error and return null.
19495 A similar function exists in GCC. */
19497 static const struct mips_cpu_info
*
19498 mips_parse_cpu (const char *option
, const char *cpu_string
)
19500 const struct mips_cpu_info
*p
;
19502 /* 'from-abi' selects the most compatible architecture for the given
19503 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19504 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19505 version. Look first at the -mgp options, if given, otherwise base
19506 the choice on MIPS_DEFAULT_64BIT.
19508 Treat NO_ABI like the EABIs. One reason to do this is that the
19509 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19510 architecture. This code picks MIPS I for 'mips' and MIPS III for
19511 'mips64', just as we did in the days before 'from-abi'. */
19512 if (strcasecmp (cpu_string
, "from-abi") == 0)
19514 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
19515 return mips_cpu_info_from_isa (ISA_MIPS1
);
19517 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
19518 return mips_cpu_info_from_isa (ISA_MIPS3
);
19520 if (file_mips_gp32
>= 0)
19521 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
19523 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19528 /* 'default' has traditionally been a no-op. Probably not very useful. */
19529 if (strcasecmp (cpu_string
, "default") == 0)
19532 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
19533 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
19536 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
19540 /* Return the canonical processor information for ISA (a member of the
19541 ISA_MIPS* enumeration). */
19543 static const struct mips_cpu_info
*
19544 mips_cpu_info_from_isa (int isa
)
19548 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19549 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
19550 && isa
== mips_cpu_info_table
[i
].isa
)
19551 return (&mips_cpu_info_table
[i
]);
19556 static const struct mips_cpu_info
*
19557 mips_cpu_info_from_arch (int arch
)
19561 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19562 if (arch
== mips_cpu_info_table
[i
].cpu
)
19563 return (&mips_cpu_info_table
[i
]);
19569 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
19573 fprintf (stream
, "%24s", "");
19578 fprintf (stream
, ", ");
19582 if (*col_p
+ strlen (string
) > 72)
19584 fprintf (stream
, "\n%24s", "");
19588 fprintf (stream
, "%s", string
);
19589 *col_p
+= strlen (string
);
19595 md_show_usage (FILE *stream
)
19600 fprintf (stream
, _("\
19602 -EB generate big endian output\n\
19603 -EL generate little endian output\n\
19604 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19605 -G NUM allow referencing objects up to NUM bytes\n\
19606 implicitly with the gp register [default 8]\n"));
19607 fprintf (stream
, _("\
19608 -mips1 generate MIPS ISA I instructions\n\
19609 -mips2 generate MIPS ISA II instructions\n\
19610 -mips3 generate MIPS ISA III instructions\n\
19611 -mips4 generate MIPS ISA IV instructions\n\
19612 -mips5 generate MIPS ISA V instructions\n\
19613 -mips32 generate MIPS32 ISA instructions\n\
19614 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19615 -mips64 generate MIPS64 ISA instructions\n\
19616 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19617 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19621 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
19622 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
19623 show (stream
, "from-abi", &column
, &first
);
19624 fputc ('\n', stream
);
19626 fprintf (stream
, _("\
19627 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19628 -no-mCPU don't generate code specific to CPU.\n\
19629 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19633 show (stream
, "3900", &column
, &first
);
19634 show (stream
, "4010", &column
, &first
);
19635 show (stream
, "4100", &column
, &first
);
19636 show (stream
, "4650", &column
, &first
);
19637 fputc ('\n', stream
);
19639 fprintf (stream
, _("\
19640 -mips16 generate mips16 instructions\n\
19641 -no-mips16 do not generate mips16 instructions\n"));
19642 fprintf (stream
, _("\
19643 -mmicromips generate microMIPS instructions\n\
19644 -mno-micromips do not generate microMIPS instructions\n"));
19645 fprintf (stream
, _("\
19646 -msmartmips generate smartmips instructions\n\
19647 -mno-smartmips do not generate smartmips instructions\n"));
19648 fprintf (stream
, _("\
19649 -mdsp generate DSP instructions\n\
19650 -mno-dsp do not generate DSP instructions\n"));
19651 fprintf (stream
, _("\
19652 -mdspr2 generate DSP R2 instructions\n\
19653 -mno-dspr2 do not generate DSP R2 instructions\n"));
19654 fprintf (stream
, _("\
19655 -mmt generate MT instructions\n\
19656 -mno-mt do not generate MT instructions\n"));
19657 fprintf (stream
, _("\
19658 -mmcu generate MCU instructions\n\
19659 -mno-mcu do not generate MCU instructions\n"));
19660 fprintf (stream
, _("\
19661 -mvirt generate Virtualization instructions\n\
19662 -mno-virt do not generate Virtualization instructions\n"));
19663 fprintf (stream
, _("\
19664 -minsn32 only generate 32-bit microMIPS instructions\n\
19665 -mno-insn32 generate all microMIPS instructions\n"));
19666 fprintf (stream
, _("\
19667 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19668 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19669 -mfix-vr4120 work around certain VR4120 errata\n\
19670 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19671 -mfix-24k insert a nop after ERET and DERET instructions\n\
19672 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19673 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19674 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19675 -msym32 assume all symbols have 32-bit values\n\
19676 -O0 remove unneeded NOPs, do not swap branches\n\
19677 -O remove unneeded NOPs and swap branches\n\
19678 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19679 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19680 fprintf (stream
, _("\
19681 -mhard-float allow floating-point instructions\n\
19682 -msoft-float do not allow floating-point instructions\n\
19683 -msingle-float only allow 32-bit floating-point operations\n\
19684 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19685 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19686 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19688 fprintf (stream
, _("\
19689 -KPIC, -call_shared generate SVR4 position independent code\n\
19690 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19691 -mvxworks-pic generate VxWorks position independent code\n\
19692 -non_shared do not generate code that can operate with DSOs\n\
19693 -xgot assume a 32 bit GOT\n\
19694 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19695 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19696 position dependent (non shared) code\n\
19697 -mabi=ABI create ABI conformant object file for:\n"));
19701 show (stream
, "32", &column
, &first
);
19702 show (stream
, "o64", &column
, &first
);
19703 show (stream
, "n32", &column
, &first
);
19704 show (stream
, "64", &column
, &first
);
19705 show (stream
, "eabi", &column
, &first
);
19707 fputc ('\n', stream
);
19709 fprintf (stream
, _("\
19710 -32 create o32 ABI object file (default)\n\
19711 -n32 create n32 ABI object file\n\
19712 -64 create 64 ABI object file\n"));
19717 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
19719 if (HAVE_64BIT_SYMBOLS
)
19720 return dwarf2_format_64bit_irix
;
19722 return dwarf2_format_32bit
;
19727 mips_dwarf2_addr_size (void)
19729 if (HAVE_64BIT_OBJECTS
)
19735 /* Standard calling conventions leave the CFA at SP on entry. */
19737 mips_cfi_frame_initial_instructions (void)
19739 cfi_add_CFA_def_cfa_register (SP
);
19743 tc_mips_regname_to_dw2regnum (char *regname
)
19745 unsigned int regnum
= -1;
19748 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))