1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* Information about an instruction, including its format, operands
126 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
127 const struct mips_opcode
*insn_mo
;
129 /* True if this is a mips16 instruction and if we want the extended
131 bfd_boolean use_extend
;
133 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
134 unsigned short extend
;
136 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
137 a copy of INSN_MO->match with the operands filled in. */
138 unsigned long insn_opcode
;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p
: 1;
152 /* True if this instruction occured in a .set noreorder block. */
153 unsigned int noreorder_p
: 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p
: 1;
159 /* The ABI to use. */
170 /* MIPS ABI we are using for this output file. */
171 static enum mips_abi_level mips_abi
= NO_ABI
;
173 /* Whether or not we have code that can call pic code. */
174 int mips_abicalls
= FALSE
;
176 /* Whether or not we have code which can be put into a shared
178 static bfd_boolean mips_in_shared
= TRUE
;
180 /* This is the set of options which may be modified by the .set
181 pseudo-op. We use a struct so that .set push and .set pop are more
184 struct mips_set_options
186 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
187 if it has not been initialized. Changed by `.set mipsN', and the
188 -mipsN command line option, and the default CPU. */
190 /* Enabled Application Specific Extensions (ASEs). These are set to -1
191 if they have not been initialized. Changed by `.set <asename>', by
192 command line options, and based on the default architecture. */
195 /* Whether we are assembling for the mips16 processor. 0 if we are
196 not, 1 if we are, and -1 if the value has not been initialized.
197 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
198 -nomips16 command line options, and the default CPU. */
200 /* Non-zero if we should not reorder instructions. Changed by `.set
201 reorder' and `.set noreorder'. */
203 /* Non-zero if we should not permit the $at ($1) register to be used
204 in instructions. Changed by `.set at' and `.set noat'. */
206 /* Non-zero if we should warn when a macro instruction expands into
207 more than one machine instruction. Changed by `.set nomacro' and
209 int warn_about_macros
;
210 /* Non-zero if we should not move instructions. Changed by `.set
211 move', `.set volatile', `.set nomove', and `.set novolatile'. */
213 /* Non-zero if we should not optimize branches by moving the target
214 of the branch into the delay slot. Actually, we don't perform
215 this optimization anyhow. Changed by `.set bopt' and `.set
218 /* Non-zero if we should not autoextend mips16 instructions.
219 Changed by `.set autoextend' and `.set noautoextend'. */
221 /* Restrict general purpose registers and floating point registers
222 to 32 bit. This is initially determined when -mgp32 or -mfp32
223 is passed but can changed if the assembler code uses .set mipsN. */
226 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
227 command line option, and the default CPU. */
229 /* True if ".set sym32" is in effect. */
233 /* True if -mgp32 was passed. */
234 static int file_mips_gp32
= -1;
236 /* True if -mfp32 was passed. */
237 static int file_mips_fp32
= -1;
239 /* This is the struct we use to hold the current set of options. Note
240 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
241 -1 to indicate that they have not been initialized. */
243 static struct mips_set_options mips_opts
=
245 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
248 /* These variables are filled in with the masks of registers used.
249 The object format code reads them and puts them in the appropriate
251 unsigned long mips_gprmask
;
252 unsigned long mips_cprmask
[4];
254 /* MIPS ISA we are using for this output file. */
255 static int file_mips_isa
= ISA_UNKNOWN
;
257 /* True if -mips16 was passed or implied by arguments passed on the
258 command line (e.g., by -march). */
259 static int file_ase_mips16
;
261 /* True if -mips3d was passed or implied by arguments passed on the
262 command line (e.g., by -march). */
263 static int file_ase_mips3d
;
265 /* True if -mdmx was passed or implied by arguments passed on the
266 command line (e.g., by -march). */
267 static int file_ase_mdmx
;
269 /* The argument of the -march= flag. The architecture we are assembling. */
270 static int file_mips_arch
= CPU_UNKNOWN
;
271 static const char *mips_arch_string
;
273 /* The argument of the -mtune= flag. The architecture for which we
275 static int mips_tune
= CPU_UNKNOWN
;
276 static const char *mips_tune_string
;
278 /* True when generating 32-bit code for a 64-bit processor. */
279 static int mips_32bitmode
= 0;
281 /* True if the given ABI requires 32-bit registers. */
282 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
284 /* Likewise 64-bit registers. */
285 #define ABI_NEEDS_64BIT_REGS(ABI) \
287 || (ABI) == N64_ABI \
290 /* Return true if ISA supports 64 bit gp register instructions. */
291 #define ISA_HAS_64BIT_REGS(ISA) ( \
293 || (ISA) == ISA_MIPS4 \
294 || (ISA) == ISA_MIPS5 \
295 || (ISA) == ISA_MIPS64 \
296 || (ISA) == ISA_MIPS64R2 \
299 /* Return true if ISA supports 64-bit right rotate (dror et al.)
301 #define ISA_HAS_DROR(ISA) ( \
302 (ISA) == ISA_MIPS64R2 \
305 /* Return true if ISA supports 32-bit right rotate (ror et al.)
307 #define ISA_HAS_ROR(ISA) ( \
308 (ISA) == ISA_MIPS32R2 \
309 || (ISA) == ISA_MIPS64R2 \
312 #define HAVE_32BIT_GPRS \
313 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
315 #define HAVE_32BIT_FPRS \
316 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
318 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
319 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
321 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
323 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
325 /* True if relocations are stored in-place. */
326 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
328 /* The ABI-derived address size. */
329 #define HAVE_64BIT_ADDRESSES \
330 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
331 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
333 /* The size of symbolic constants (i.e., expressions of the form
334 "SYMBOL" or "SYMBOL + OFFSET"). */
335 #define HAVE_32BIT_SYMBOLS \
336 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
337 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
339 /* Addresses are loaded in different ways, depending on the address size
340 in use. The n32 ABI Documentation also mandates the use of additions
341 with overflow checking, but existing implementations don't follow it. */
342 #define ADDRESS_ADD_INSN \
343 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
345 #define ADDRESS_ADDI_INSN \
346 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
348 #define ADDRESS_LOAD_INSN \
349 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
351 #define ADDRESS_STORE_INSN \
352 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
354 /* Return true if the given CPU supports the MIPS16 ASE. */
355 #define CPU_HAS_MIPS16(cpu) \
356 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
357 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
359 /* Return true if the given CPU supports the MIPS3D ASE. */
360 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
363 /* Return true if the given CPU supports the MDMX ASE. */
364 #define CPU_HAS_MDMX(cpu) (FALSE \
367 /* True if CPU has a dror instruction. */
368 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
370 /* True if CPU has a ror instruction. */
371 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
373 /* True if mflo and mfhi can be immediately followed by instructions
374 which write to the HI and LO registers.
376 According to MIPS specifications, MIPS ISAs I, II, and III need
377 (at least) two instructions between the reads of HI/LO and
378 instructions which write them, and later ISAs do not. Contradicting
379 the MIPS specifications, some MIPS IV processor user manuals (e.g.
380 the UM for the NEC Vr5000) document needing the instructions between
381 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
382 MIPS64 and later ISAs to have the interlocks, plus any specific
383 earlier-ISA CPUs for which CPU documentation declares that the
384 instructions are really interlocked. */
385 #define hilo_interlocks \
386 (mips_opts.isa == ISA_MIPS32 \
387 || mips_opts.isa == ISA_MIPS32R2 \
388 || mips_opts.isa == ISA_MIPS64 \
389 || mips_opts.isa == ISA_MIPS64R2 \
390 || mips_opts.arch == CPU_R4010 \
391 || mips_opts.arch == CPU_R10000 \
392 || mips_opts.arch == CPU_R12000 \
393 || mips_opts.arch == CPU_RM7000 \
394 || mips_opts.arch == CPU_VR5500 \
397 /* Whether the processor uses hardware interlocks to protect reads
398 from the GPRs after they are loaded from memory, and thus does not
399 require nops to be inserted. This applies to instructions marked
400 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
402 #define gpr_interlocks \
403 (mips_opts.isa != ISA_MIPS1 \
404 || mips_opts.arch == CPU_R3900)
406 /* Whether the processor uses hardware interlocks to avoid delays
407 required by coprocessor instructions, and thus does not require
408 nops to be inserted. This applies to instructions marked
409 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
410 between instructions marked INSN_WRITE_COND_CODE and ones marked
411 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
412 levels I, II, and III. */
413 /* Itbl support may require additional care here. */
414 #define cop_interlocks \
415 ((mips_opts.isa != ISA_MIPS1 \
416 && mips_opts.isa != ISA_MIPS2 \
417 && mips_opts.isa != ISA_MIPS3) \
418 || mips_opts.arch == CPU_R4300 \
421 /* Whether the processor uses hardware interlocks to protect reads
422 from coprocessor registers after they are loaded from memory, and
423 thus does not require nops to be inserted. This applies to
424 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
425 requires at MIPS ISA level I. */
426 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
428 /* Is this a mfhi or mflo instruction? */
429 #define MF_HILO_INSN(PINFO) \
430 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
432 /* MIPS PIC level. */
434 enum mips_pic_level mips_pic
;
436 /* 1 if we should generate 32 bit offsets from the $gp register in
437 SVR4_PIC mode. Currently has no meaning in other modes. */
438 static int mips_big_got
= 0;
440 /* 1 if trap instructions should used for overflow rather than break
442 static int mips_trap
= 0;
444 /* 1 if double width floating point constants should not be constructed
445 by assembling two single width halves into two single width floating
446 point registers which just happen to alias the double width destination
447 register. On some architectures this aliasing can be disabled by a bit
448 in the status register, and the setting of this bit cannot be determined
449 automatically at assemble time. */
450 static int mips_disable_float_construction
;
452 /* Non-zero if any .set noreorder directives were used. */
454 static int mips_any_noreorder
;
456 /* Non-zero if nops should be inserted when the register referenced in
457 an mfhi/mflo instruction is read in the next two instructions. */
458 static int mips_7000_hilo_fix
;
460 /* The size of the small data section. */
461 static unsigned int g_switch_value
= 8;
462 /* Whether the -G option was used. */
463 static int g_switch_seen
= 0;
468 /* If we can determine in advance that GP optimization won't be
469 possible, we can skip the relaxation stuff that tries to produce
470 GP-relative references. This makes delay slot optimization work
473 This function can only provide a guess, but it seems to work for
474 gcc output. It needs to guess right for gcc, otherwise gcc
475 will put what it thinks is a GP-relative instruction in a branch
478 I don't know if a fix is needed for the SVR4_PIC mode. I've only
479 fixed it for the non-PIC mode. KR 95/04/07 */
480 static int nopic_need_relax (symbolS
*, int);
482 /* handle of the OPCODE hash table */
483 static struct hash_control
*op_hash
= NULL
;
485 /* The opcode hash table we use for the mips16. */
486 static struct hash_control
*mips16_op_hash
= NULL
;
488 /* This array holds the chars that always start a comment. If the
489 pre-processor is disabled, these aren't very useful */
490 const char comment_chars
[] = "#";
492 /* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
494 .line and .file directives will appear in the pre-processed output */
495 /* Note that input_file.c hand checks for '#' at the beginning of the
496 first line of the input file. This is because the compiler outputs
497 #NO_APP at the beginning of its output. */
498 /* Also note that C style comments are always supported. */
499 const char line_comment_chars
[] = "#";
501 /* This array holds machine specific line separator characters. */
502 const char line_separator_chars
[] = ";";
504 /* Chars that can be used to separate mant from exp in floating point nums */
505 const char EXP_CHARS
[] = "eE";
507 /* Chars that mean this number is a floating point constant */
510 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
512 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
513 changed in read.c . Ideally it shouldn't have to know about it at all,
514 but nothing is ideal around here.
517 static char *insn_error
;
519 static int auto_align
= 1;
521 /* When outputting SVR4 PIC code, the assembler needs to know the
522 offset in the stack frame from which to restore the $gp register.
523 This is set by the .cprestore pseudo-op, and saved in this
525 static offsetT mips_cprestore_offset
= -1;
527 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
528 more optimizations, it can use a register value instead of a memory-saved
529 offset and even an other register than $gp as global pointer. */
530 static offsetT mips_cpreturn_offset
= -1;
531 static int mips_cpreturn_register
= -1;
532 static int mips_gp_register
= GP
;
533 static int mips_gprel_offset
= 0;
535 /* Whether mips_cprestore_offset has been set in the current function
536 (or whether it has already been warned about, if not). */
537 static int mips_cprestore_valid
= 0;
539 /* This is the register which holds the stack frame, as set by the
540 .frame pseudo-op. This is needed to implement .cprestore. */
541 static int mips_frame_reg
= SP
;
543 /* Whether mips_frame_reg has been set in the current function
544 (or whether it has already been warned about, if not). */
545 static int mips_frame_reg_valid
= 0;
547 /* To output NOP instructions correctly, we need to keep information
548 about the previous two instructions. */
550 /* Whether we are optimizing. The default value of 2 means to remove
551 unneeded NOPs and swap branch instructions when possible. A value
552 of 1 means to not swap branches. A value of 0 means to always
554 static int mips_optimize
= 2;
556 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
557 equivalent to seeing no -g option at all. */
558 static int mips_debug
= 0;
560 /* A list of previous instructions, with index 0 being the most recent. */
561 static struct mips_cl_insn history
[2];
563 /* Nop instructions used by emit_nop. */
564 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
566 /* The appropriate nop for the current mode. */
567 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
569 /* If this is set, it points to a frag holding nop instructions which
570 were inserted before the start of a noreorder section. If those
571 nops turn out to be unnecessary, the size of the frag can be
573 static fragS
*prev_nop_frag
;
575 /* The number of nop instructions we created in prev_nop_frag. */
576 static int prev_nop_frag_holds
;
578 /* The number of nop instructions that we know we need in
580 static int prev_nop_frag_required
;
582 /* The number of instructions we've seen since prev_nop_frag. */
583 static int prev_nop_frag_since
;
585 /* For ECOFF and ELF, relocations against symbols are done in two
586 parts, with a HI relocation and a LO relocation. Each relocation
587 has only 16 bits of space to store an addend. This means that in
588 order for the linker to handle carries correctly, it must be able
589 to locate both the HI and the LO relocation. This means that the
590 relocations must appear in order in the relocation table.
592 In order to implement this, we keep track of each unmatched HI
593 relocation. We then sort them so that they immediately precede the
594 corresponding LO relocation. */
599 struct mips_hi_fixup
*next
;
602 /* The section this fixup is in. */
606 /* The list of unmatched HI relocs. */
608 static struct mips_hi_fixup
*mips_hi_fixup_list
;
610 /* The frag containing the last explicit relocation operator.
611 Null if explicit relocations have not been used. */
613 static fragS
*prev_reloc_op_frag
;
615 /* Map normal MIPS register numbers to mips16 register numbers. */
617 #define X ILLEGAL_REG
618 static const int mips32_to_16_reg_map
[] =
620 X
, X
, 2, 3, 4, 5, 6, 7,
621 X
, X
, X
, X
, X
, X
, X
, X
,
622 0, 1, X
, X
, X
, X
, X
, X
,
623 X
, X
, X
, X
, X
, X
, X
, X
627 /* Map mips16 register numbers to normal MIPS register numbers. */
629 static const unsigned int mips16_to_32_reg_map
[] =
631 16, 17, 2, 3, 4, 5, 6, 7
634 static int mips_fix_vr4120
;
636 /* We don't relax branches by default, since this causes us to expand
637 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
638 fail to compute the offset before expanding the macro to the most
639 efficient expansion. */
641 static int mips_relax_branch
;
643 /* The expansion of many macros depends on the type of symbol that
644 they refer to. For example, when generating position-dependent code,
645 a macro that refers to a symbol may have two different expansions,
646 one which uses GP-relative addresses and one which uses absolute
647 addresses. When generating SVR4-style PIC, a macro may have
648 different expansions for local and global symbols.
650 We handle these situations by generating both sequences and putting
651 them in variant frags. In position-dependent code, the first sequence
652 will be the GP-relative one and the second sequence will be the
653 absolute one. In SVR4 PIC, the first sequence will be for global
654 symbols and the second will be for local symbols.
656 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
657 SECOND are the lengths of the two sequences in bytes. These fields
658 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
659 the subtype has the following flags:
662 Set if it has been decided that we should use the second
663 sequence instead of the first.
666 Set in the first variant frag if the macro's second implementation
667 is longer than its first. This refers to the macro as a whole,
668 not an individual relaxation.
671 Set in the first variant frag if the macro appeared in a .set nomacro
672 block and if one alternative requires a warning but the other does not.
675 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
678 The frag's "opcode" points to the first fixup for relaxable code.
680 Relaxable macros are generated using a sequence such as:
682 relax_start (SYMBOL);
683 ... generate first expansion ...
685 ... generate second expansion ...
688 The code and fixups for the unwanted alternative are discarded
689 by md_convert_frag. */
690 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
692 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
693 #define RELAX_SECOND(X) ((X) & 0xff)
694 #define RELAX_USE_SECOND 0x10000
695 #define RELAX_SECOND_LONGER 0x20000
696 #define RELAX_NOMACRO 0x40000
697 #define RELAX_DELAY_SLOT 0x80000
699 /* Branch without likely bit. If label is out of range, we turn:
701 beq reg1, reg2, label
711 with the following opcode replacements:
718 bltzal <-> bgezal (with jal label instead of j label)
720 Even though keeping the delay slot instruction in the delay slot of
721 the branch would be more efficient, it would be very tricky to do
722 correctly, because we'd have to introduce a variable frag *after*
723 the delay slot instruction, and expand that instead. Let's do it
724 the easy way for now, even if the branch-not-taken case now costs
725 one additional instruction. Out-of-range branches are not supposed
726 to be common, anyway.
728 Branch likely. If label is out of range, we turn:
730 beql reg1, reg2, label
731 delay slot (annulled if branch not taken)
740 delay slot (executed only if branch taken)
743 It would be possible to generate a shorter sequence by losing the
744 likely bit, generating something like:
749 delay slot (executed only if branch taken)
761 bltzall -> bgezal (with jal label instead of j label)
762 bgezall -> bltzal (ditto)
765 but it's not clear that it would actually improve performance. */
766 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
769 | ((toofar) ? 1 : 0) \
771 | ((likely) ? 4 : 0) \
772 | ((uncond) ? 8 : 0)))
773 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
774 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
775 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
776 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
777 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
779 /* For mips16 code, we use an entirely different form of relaxation.
780 mips16 supports two versions of most instructions which take
781 immediate values: a small one which takes some small value, and a
782 larger one which takes a 16 bit value. Since branches also follow
783 this pattern, relaxing these values is required.
785 We can assemble both mips16 and normal MIPS code in a single
786 object. Therefore, we need to support this type of relaxation at
787 the same time that we support the relaxation described above. We
788 use the high bit of the subtype field to distinguish these cases.
790 The information we store for this type of relaxation is the
791 argument code found in the opcode file for this relocation, whether
792 the user explicitly requested a small or extended form, and whether
793 the relocation is in a jump or jal delay slot. That tells us the
794 size of the value, and how it should be stored. We also store
795 whether the fragment is considered to be extended or not. We also
796 store whether this is known to be a branch to a different section,
797 whether we have tried to relax this frag yet, and whether we have
798 ever extended a PC relative fragment because of a shift count. */
799 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
802 | ((small) ? 0x100 : 0) \
803 | ((ext) ? 0x200 : 0) \
804 | ((dslot) ? 0x400 : 0) \
805 | ((jal_dslot) ? 0x800 : 0))
806 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
807 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
808 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
809 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
810 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
811 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
812 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
813 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
814 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
815 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
816 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
817 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
819 /* Is the given value a sign-extended 32-bit value? */
820 #define IS_SEXT_32BIT_NUM(x) \
821 (((x) &~ (offsetT) 0x7fffffff) == 0 \
822 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
824 /* Is the given value a sign-extended 16-bit value? */
825 #define IS_SEXT_16BIT_NUM(x) \
826 (((x) &~ (offsetT) 0x7fff) == 0 \
827 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
829 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
830 VALUE << SHIFT. VALUE is evaluated exactly once. */
831 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
832 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
833 | (((VALUE) & (MASK)) << (SHIFT)))
835 /* Extract bits MASK << SHIFT from STRUCT and shift them right
837 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
838 (((STRUCT) >> (SHIFT)) & (MASK))
840 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
841 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
843 include/opcode/mips.h specifies operand fields using the macros
844 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
845 with "MIPS16OP" instead of "OP". */
846 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
847 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
848 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
849 INSERT_BITS ((INSN).insn_opcode, VALUE, \
850 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
852 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
853 #define EXTRACT_OPERAND(FIELD, INSN) \
854 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
855 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
856 EXTRACT_BITS ((INSN).insn_opcode, \
857 MIPS16OP_MASK_##FIELD, \
860 /* Global variables used when generating relaxable macros. See the
861 comment above RELAX_ENCODE for more details about how relaxation
864 /* 0 if we're not emitting a relaxable macro.
865 1 if we're emitting the first of the two relaxation alternatives.
866 2 if we're emitting the second alternative. */
869 /* The first relaxable fixup in the current frag. (In other words,
870 the first fixup that refers to relaxable code.) */
873 /* sizes[0] says how many bytes of the first alternative are stored in
874 the current frag. Likewise sizes[1] for the second alternative. */
875 unsigned int sizes
[2];
877 /* The symbol on which the choice of sequence depends. */
881 /* Global variables used to decide whether a macro needs a warning. */
883 /* True if the macro is in a branch delay slot. */
884 bfd_boolean delay_slot_p
;
886 /* For relaxable macros, sizes[0] is the length of the first alternative
887 in bytes and sizes[1] is the length of the second alternative.
888 For non-relaxable macros, both elements give the length of the
890 unsigned int sizes
[2];
892 /* The first variant frag for this macro. */
894 } mips_macro_warning
;
896 /* Prototypes for static functions. */
898 #define internalError() \
899 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
901 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
903 static void append_insn
904 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
905 static void mips_no_prev_insn (int);
906 static void mips16_macro_build
907 (expressionS
*, const char *, const char *, va_list);
908 static void load_register (int, expressionS
*, int);
909 static void macro_start (void);
910 static void macro_end (void);
911 static void macro (struct mips_cl_insn
* ip
);
912 static void mips16_macro (struct mips_cl_insn
* ip
);
913 #ifdef LOSING_COMPILER
914 static void macro2 (struct mips_cl_insn
* ip
);
916 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
917 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
918 static void mips16_immed
919 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
920 unsigned long *, bfd_boolean
*, unsigned short *);
921 static size_t my_getSmallExpression
922 (expressionS
*, bfd_reloc_code_real_type
*, char *);
923 static void my_getExpression (expressionS
*, char *);
924 static void s_align (int);
925 static void s_change_sec (int);
926 static void s_change_section (int);
927 static void s_cons (int);
928 static void s_float_cons (int);
929 static void s_mips_globl (int);
930 static void s_option (int);
931 static void s_mipsset (int);
932 static void s_abicalls (int);
933 static void s_cpload (int);
934 static void s_cpsetup (int);
935 static void s_cplocal (int);
936 static void s_cprestore (int);
937 static void s_cpreturn (int);
938 static void s_gpvalue (int);
939 static void s_gpword (int);
940 static void s_gpdword (int);
941 static void s_cpadd (int);
942 static void s_insn (int);
943 static void md_obj_begin (void);
944 static void md_obj_end (void);
945 static void s_mips_ent (int);
946 static void s_mips_end (int);
947 static void s_mips_frame (int);
948 static void s_mips_mask (int reg_type
);
949 static void s_mips_stab (int);
950 static void s_mips_weakext (int);
951 static void s_mips_file (int);
952 static void s_mips_loc (int);
953 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
954 static int relaxed_branch_length (fragS
*, asection
*, int);
955 static int validate_mips_insn (const struct mips_opcode
*);
957 /* Table and functions used to map between CPU/ISA names, and
958 ISA levels, and CPU numbers. */
962 const char *name
; /* CPU or ISA name. */
963 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
964 int isa
; /* ISA level. */
965 int cpu
; /* CPU number (default CPU if ISA). */
968 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
969 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
970 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
974 The following pseudo-ops from the Kane and Heinrich MIPS book
975 should be defined here, but are currently unsupported: .alias,
976 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
978 The following pseudo-ops from the Kane and Heinrich MIPS book are
979 specific to the type of debugging information being generated, and
980 should be defined by the object format: .aent, .begin, .bend,
981 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
984 The following pseudo-ops from the Kane and Heinrich MIPS book are
985 not MIPS CPU specific, but are also not specific to the object file
986 format. This file is probably the best place to define them, but
987 they are not currently supported: .asm0, .endr, .lab, .repeat,
990 static const pseudo_typeS mips_pseudo_table
[] =
992 /* MIPS specific pseudo-ops. */
993 {"option", s_option
, 0},
994 {"set", s_mipsset
, 0},
995 {"rdata", s_change_sec
, 'r'},
996 {"sdata", s_change_sec
, 's'},
997 {"livereg", s_ignore
, 0},
998 {"abicalls", s_abicalls
, 0},
999 {"cpload", s_cpload
, 0},
1000 {"cpsetup", s_cpsetup
, 0},
1001 {"cplocal", s_cplocal
, 0},
1002 {"cprestore", s_cprestore
, 0},
1003 {"cpreturn", s_cpreturn
, 0},
1004 {"gpvalue", s_gpvalue
, 0},
1005 {"gpword", s_gpword
, 0},
1006 {"gpdword", s_gpdword
, 0},
1007 {"cpadd", s_cpadd
, 0},
1008 {"insn", s_insn
, 0},
1010 /* Relatively generic pseudo-ops that happen to be used on MIPS
1012 {"asciiz", stringer
, 1},
1013 {"bss", s_change_sec
, 'b'},
1015 {"half", s_cons
, 1},
1016 {"dword", s_cons
, 3},
1017 {"weakext", s_mips_weakext
, 0},
1019 /* These pseudo-ops are defined in read.c, but must be overridden
1020 here for one reason or another. */
1021 {"align", s_align
, 0},
1022 {"byte", s_cons
, 0},
1023 {"data", s_change_sec
, 'd'},
1024 {"double", s_float_cons
, 'd'},
1025 {"float", s_float_cons
, 'f'},
1026 {"globl", s_mips_globl
, 0},
1027 {"global", s_mips_globl
, 0},
1028 {"hword", s_cons
, 1},
1030 {"long", s_cons
, 2},
1031 {"octa", s_cons
, 4},
1032 {"quad", s_cons
, 3},
1033 {"section", s_change_section
, 0},
1034 {"short", s_cons
, 1},
1035 {"single", s_float_cons
, 'f'},
1036 {"stabn", s_mips_stab
, 'n'},
1037 {"text", s_change_sec
, 't'},
1038 {"word", s_cons
, 2},
1040 { "extern", ecoff_directive_extern
, 0},
1045 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1047 /* These pseudo-ops should be defined by the object file format.
1048 However, a.out doesn't support them, so we have versions here. */
1049 {"aent", s_mips_ent
, 1},
1050 {"bgnb", s_ignore
, 0},
1051 {"end", s_mips_end
, 0},
1052 {"endb", s_ignore
, 0},
1053 {"ent", s_mips_ent
, 0},
1054 {"file", s_mips_file
, 0},
1055 {"fmask", s_mips_mask
, 'F'},
1056 {"frame", s_mips_frame
, 0},
1057 {"loc", s_mips_loc
, 0},
1058 {"mask", s_mips_mask
, 'R'},
1059 {"verstamp", s_ignore
, 0},
1063 extern void pop_insert (const pseudo_typeS
*);
1066 mips_pop_insert (void)
1068 pop_insert (mips_pseudo_table
);
1069 if (! ECOFF_DEBUGGING
)
1070 pop_insert (mips_nonecoff_pseudo_table
);
1073 /* Symbols labelling the current insn. */
1075 struct insn_label_list
1077 struct insn_label_list
*next
;
1081 static struct insn_label_list
*insn_labels
;
1082 static struct insn_label_list
*free_insn_labels
;
1084 static void mips_clear_insn_labels (void);
1087 mips_clear_insn_labels (void)
1089 register struct insn_label_list
**pl
;
1091 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1097 static char *expr_end
;
1099 /* Expressions which appear in instructions. These are set by
1102 static expressionS imm_expr
;
1103 static expressionS imm2_expr
;
1104 static expressionS offset_expr
;
1106 /* Relocs associated with imm_expr and offset_expr. */
1108 static bfd_reloc_code_real_type imm_reloc
[3]
1109 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1110 static bfd_reloc_code_real_type offset_reloc
[3]
1111 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1113 /* These are set by mips16_ip if an explicit extension is used. */
1115 static bfd_boolean mips16_small
, mips16_ext
;
1118 /* The pdr segment for per procedure frame/regmask info. Not used for
1121 static segT pdr_seg
;
1124 /* The default target format to use. */
1127 mips_target_format (void)
1129 switch (OUTPUT_FLAVOR
)
1131 case bfd_target_ecoff_flavour
:
1132 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1133 case bfd_target_coff_flavour
:
1135 case bfd_target_elf_flavour
:
1137 /* This is traditional mips. */
1138 return (target_big_endian
1139 ? (HAVE_64BIT_OBJECTS
1140 ? "elf64-tradbigmips"
1142 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1143 : (HAVE_64BIT_OBJECTS
1144 ? "elf64-tradlittlemips"
1146 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1148 return (target_big_endian
1149 ? (HAVE_64BIT_OBJECTS
1152 ? "elf32-nbigmips" : "elf32-bigmips"))
1153 : (HAVE_64BIT_OBJECTS
1154 ? "elf64-littlemips"
1156 ? "elf32-nlittlemips" : "elf32-littlemips")));
1164 /* Return the length of instruction INSN. */
1166 static inline unsigned int
1167 insn_length (const struct mips_cl_insn
*insn
)
1169 if (!mips_opts
.mips16
)
1171 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1174 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1177 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1182 insn
->use_extend
= FALSE
;
1184 insn
->insn_opcode
= mo
->match
;
1187 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1188 insn
->fixp
[i
] = NULL
;
1189 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1190 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1191 insn
->mips16_absolute_jump_p
= 0;
1194 /* Install INSN at the location specified by its "frag" and "where" fields. */
1197 install_insn (const struct mips_cl_insn
*insn
)
1199 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1200 if (!mips_opts
.mips16
)
1201 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1202 else if (insn
->mips16_absolute_jump_p
)
1204 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1205 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1209 if (insn
->use_extend
)
1211 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1214 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1218 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1219 and install the opcode in the new location. */
1222 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1227 insn
->where
= where
;
1228 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1229 if (insn
->fixp
[i
] != NULL
)
1231 insn
->fixp
[i
]->fx_frag
= frag
;
1232 insn
->fixp
[i
]->fx_where
= where
;
1234 install_insn (insn
);
1237 /* Add INSN to the end of the output. */
1240 add_fixed_insn (struct mips_cl_insn
*insn
)
1242 char *f
= frag_more (insn_length (insn
));
1243 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1246 /* Start a variant frag and move INSN to the start of the variant part,
1247 marking it as fixed. The other arguments are as for frag_var. */
1250 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1251 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1253 frag_grow (max_chars
);
1254 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1256 frag_var (rs_machine_dependent
, max_chars
, var
,
1257 subtype
, symbol
, offset
, NULL
);
1260 /* Insert N copies of INSN into the history buffer, starting at
1261 position FIRST. Neither FIRST nor N need to be clipped. */
1264 insert_into_history (unsigned int first
, unsigned int n
,
1265 const struct mips_cl_insn
*insn
)
1267 if (mips_relax
.sequence
!= 2)
1271 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1273 history
[i
] = history
[i
- n
];
1279 /* Emit a nop instruction, recording it in the history buffer. */
1284 add_fixed_insn (NOP_INSN
);
1285 insert_into_history (0, 1, NOP_INSN
);
1288 /* This function is called once, at assembler startup time. It should
1289 set up all the tables, etc. that the MD part of the assembler will need. */
1294 register const char *retval
= NULL
;
1298 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1299 as_warn (_("Could not set architecture and machine"));
1301 op_hash
= hash_new ();
1303 for (i
= 0; i
< NUMOPCODES
;)
1305 const char *name
= mips_opcodes
[i
].name
;
1307 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1310 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1311 mips_opcodes
[i
].name
, retval
);
1312 /* Probably a memory allocation problem? Give up now. */
1313 as_fatal (_("Broken assembler. No assembly attempted."));
1317 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1319 if (!validate_mips_insn (&mips_opcodes
[i
]))
1321 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1323 create_insn (&nop_insn
, mips_opcodes
+ i
);
1324 nop_insn
.fixed_p
= 1;
1329 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1332 mips16_op_hash
= hash_new ();
1335 while (i
< bfd_mips16_num_opcodes
)
1337 const char *name
= mips16_opcodes
[i
].name
;
1339 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1341 as_fatal (_("internal: can't hash `%s': %s"),
1342 mips16_opcodes
[i
].name
, retval
);
1345 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1346 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1347 != mips16_opcodes
[i
].match
))
1349 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1350 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1353 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1355 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1356 mips16_nop_insn
.fixed_p
= 1;
1360 while (i
< bfd_mips16_num_opcodes
1361 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1365 as_fatal (_("Broken assembler. No assembly attempted."));
1367 /* We add all the general register names to the symbol table. This
1368 helps us detect invalid uses of them. */
1369 for (i
= 0; i
< 32; i
++)
1373 sprintf (buf
, "$%d", i
);
1374 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1375 &zero_address_frag
));
1377 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1378 &zero_address_frag
));
1379 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1380 &zero_address_frag
));
1381 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1382 &zero_address_frag
));
1383 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1384 &zero_address_frag
));
1385 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1386 &zero_address_frag
));
1387 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1388 &zero_address_frag
));
1389 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1390 &zero_address_frag
));
1391 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1392 &zero_address_frag
));
1393 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1394 &zero_address_frag
));
1396 /* If we don't add these register names to the symbol table, they
1397 may end up being added as regular symbols by operand(), and then
1398 make it to the object file as undefined in case they're not
1399 regarded as local symbols. They're local in o32, since `$' is a
1400 local symbol prefix, but not in n32 or n64. */
1401 for (i
= 0; i
< 8; i
++)
1405 sprintf (buf
, "$fcc%i", i
);
1406 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1407 &zero_address_frag
));
1410 mips_no_prev_insn (FALSE
);
1413 mips_cprmask
[0] = 0;
1414 mips_cprmask
[1] = 0;
1415 mips_cprmask
[2] = 0;
1416 mips_cprmask
[3] = 0;
1418 /* set the default alignment for the text section (2**2) */
1419 record_alignment (text_section
, 2);
1421 bfd_set_gp_size (stdoutput
, g_switch_value
);
1423 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1425 /* On a native system, sections must be aligned to 16 byte
1426 boundaries. When configured for an embedded ELF target, we
1428 if (strcmp (TARGET_OS
, "elf") != 0)
1430 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1431 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1432 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1435 /* Create a .reginfo section for register masks and a .mdebug
1436 section for debugging information. */
1444 subseg
= now_subseg
;
1446 /* The ABI says this section should be loaded so that the
1447 running program can access it. However, we don't load it
1448 if we are configured for an embedded target */
1449 flags
= SEC_READONLY
| SEC_DATA
;
1450 if (strcmp (TARGET_OS
, "elf") != 0)
1451 flags
|= SEC_ALLOC
| SEC_LOAD
;
1453 if (mips_abi
!= N64_ABI
)
1455 sec
= subseg_new (".reginfo", (subsegT
) 0);
1457 bfd_set_section_flags (stdoutput
, sec
, flags
);
1458 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1461 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1466 /* The 64-bit ABI uses a .MIPS.options section rather than
1467 .reginfo section. */
1468 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1469 bfd_set_section_flags (stdoutput
, sec
, flags
);
1470 bfd_set_section_alignment (stdoutput
, sec
, 3);
1473 /* Set up the option header. */
1475 Elf_Internal_Options opthdr
;
1478 opthdr
.kind
= ODK_REGINFO
;
1479 opthdr
.size
= (sizeof (Elf_External_Options
)
1480 + sizeof (Elf64_External_RegInfo
));
1483 f
= frag_more (sizeof (Elf_External_Options
));
1484 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1485 (Elf_External_Options
*) f
);
1487 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1492 if (ECOFF_DEBUGGING
)
1494 sec
= subseg_new (".mdebug", (subsegT
) 0);
1495 (void) bfd_set_section_flags (stdoutput
, sec
,
1496 SEC_HAS_CONTENTS
| SEC_READONLY
);
1497 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1500 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1502 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1503 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1504 SEC_READONLY
| SEC_RELOC
1506 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1510 subseg_set (seg
, subseg
);
1514 if (! ECOFF_DEBUGGING
)
1521 if (! ECOFF_DEBUGGING
)
1526 md_assemble (char *str
)
1528 struct mips_cl_insn insn
;
1529 bfd_reloc_code_real_type unused_reloc
[3]
1530 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1532 imm_expr
.X_op
= O_absent
;
1533 imm2_expr
.X_op
= O_absent
;
1534 offset_expr
.X_op
= O_absent
;
1535 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1536 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1537 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1538 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1539 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1540 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1542 if (mips_opts
.mips16
)
1543 mips16_ip (str
, &insn
);
1546 mips_ip (str
, &insn
);
1547 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1548 str
, insn
.insn_opcode
));
1553 as_bad ("%s `%s'", insn_error
, str
);
1557 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1560 if (mips_opts
.mips16
)
1561 mips16_macro (&insn
);
1568 if (imm_expr
.X_op
!= O_absent
)
1569 append_insn (&insn
, &imm_expr
, imm_reloc
);
1570 else if (offset_expr
.X_op
!= O_absent
)
1571 append_insn (&insn
, &offset_expr
, offset_reloc
);
1573 append_insn (&insn
, NULL
, unused_reloc
);
1577 /* Return true if the given relocation might need a matching %lo().
1578 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1579 applied to local symbols. */
1581 static inline bfd_boolean
1582 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1584 return (HAVE_IN_PLACE_ADDENDS
1585 && (reloc
== BFD_RELOC_HI16_S
1586 || reloc
== BFD_RELOC_MIPS_GOT16
1587 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1590 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1593 static inline bfd_boolean
1594 fixup_has_matching_lo_p (fixS
*fixp
)
1596 return (fixp
->fx_next
!= NULL
1597 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1598 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1599 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1600 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1603 /* See whether instruction IP reads register REG. CLASS is the type
1607 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1608 enum mips_regclass
class)
1610 if (class == MIPS16_REG
)
1612 assert (mips_opts
.mips16
);
1613 reg
= mips16_to_32_reg_map
[reg
];
1614 class = MIPS_GR_REG
;
1617 /* Don't report on general register ZERO, since it never changes. */
1618 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1621 if (class == MIPS_FP_REG
)
1623 assert (! mips_opts
.mips16
);
1624 /* If we are called with either $f0 or $f1, we must check $f0.
1625 This is not optimal, because it will introduce an unnecessary
1626 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1627 need to distinguish reading both $f0 and $f1 or just one of
1628 them. Note that we don't have to check the other way,
1629 because there is no instruction that sets both $f0 and $f1
1630 and requires a delay. */
1631 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1632 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1633 == (reg
&~ (unsigned) 1)))
1635 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1636 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1637 == (reg
&~ (unsigned) 1)))
1640 else if (! mips_opts
.mips16
)
1642 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1643 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1645 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1646 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1651 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1652 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1654 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1655 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1657 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1658 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1661 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1663 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1665 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1667 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1668 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1675 /* This function returns true if modifying a register requires a
1679 reg_needs_delay (unsigned int reg
)
1681 unsigned long prev_pinfo
;
1683 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1684 if (! mips_opts
.noreorder
1685 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1686 && ! gpr_interlocks
)
1687 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1688 && ! cop_interlocks
)))
1690 /* A load from a coprocessor or from memory. All load delays
1691 delay the use of general register rt for one instruction. */
1692 /* Itbl support may require additional care here. */
1693 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1694 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1701 /* Mark instruction labels in mips16 mode. This permits the linker to
1702 handle them specially, such as generating jalx instructions when
1703 needed. We also make them odd for the duration of the assembly, in
1704 order to generate the right sort of code. We will make them even
1705 in the adjust_symtab routine, while leaving them marked. This is
1706 convenient for the debugger and the disassembler. The linker knows
1707 to make them odd again. */
1710 mips16_mark_labels (void)
1712 if (mips_opts
.mips16
)
1714 struct insn_label_list
*l
;
1717 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1720 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1721 S_SET_OTHER (l
->label
, STO_MIPS16
);
1723 val
= S_GET_VALUE (l
->label
);
1725 S_SET_VALUE (l
->label
, val
+ 1);
1730 /* End the current frag. Make it a variant frag and record the
1734 relax_close_frag (void)
1736 mips_macro_warning
.first_frag
= frag_now
;
1737 frag_var (rs_machine_dependent
, 0, 0,
1738 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1739 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1741 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1742 mips_relax
.first_fixup
= 0;
1745 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1746 See the comment above RELAX_ENCODE for more details. */
1749 relax_start (symbolS
*symbol
)
1751 assert (mips_relax
.sequence
== 0);
1752 mips_relax
.sequence
= 1;
1753 mips_relax
.symbol
= symbol
;
1756 /* Start generating the second version of a relaxable sequence.
1757 See the comment above RELAX_ENCODE for more details. */
1762 assert (mips_relax
.sequence
== 1);
1763 mips_relax
.sequence
= 2;
1766 /* End the current relaxable sequence. */
1771 assert (mips_relax
.sequence
== 2);
1772 relax_close_frag ();
1773 mips_relax
.sequence
= 0;
1776 /* Output an instruction. IP is the instruction information.
1777 ADDRESS_EXPR is an operand of the instruction to be used with
1781 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1782 bfd_reloc_code_real_type
*reloc_type
)
1784 register unsigned long prev_pinfo
, pinfo
;
1786 relax_stateT prev_insn_frag_type
= 0;
1787 bfd_boolean relaxed_branch
= FALSE
;
1789 /* Mark instruction labels in mips16 mode. */
1790 mips16_mark_labels ();
1792 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1793 pinfo
= ip
->insn_mo
->pinfo
;
1795 if (mips_relax
.sequence
!= 2
1796 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1800 /* If the previous insn required any delay slots, see if we need
1801 to insert a NOP or two. There are eight kinds of possible
1802 hazards, of which an instruction can have at most one type.
1803 (1) a load from memory delay
1804 (2) a load from a coprocessor delay
1805 (3) an unconditional branch delay
1806 (4) a conditional branch delay
1807 (5) a move to coprocessor register delay
1808 (6) a load coprocessor register from memory delay
1809 (7) a coprocessor condition code delay
1810 (8) a HI/LO special register delay
1812 There are a lot of optimizations we could do that we don't.
1813 In particular, we do not, in general, reorder instructions.
1814 If you use gcc with optimization, it will reorder
1815 instructions and generally do much more optimization then we
1816 do here; repeating all that work in the assembler would only
1817 benefit hand written assembly code, and does not seem worth
1820 /* The previous insn might require a delay slot, depending upon
1821 the contents of the current insn. */
1822 if (! mips_opts
.mips16
1823 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1824 && ! gpr_interlocks
)
1825 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1826 && ! cop_interlocks
)))
1828 /* A load from a coprocessor or from memory. All load
1829 delays delay the use of general register rt for one
1831 /* Itbl support may require additional care here. */
1832 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1833 if (mips_optimize
== 0
1834 || insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
1838 else if (! mips_opts
.mips16
1839 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1840 && ! cop_interlocks
)
1841 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1842 && ! cop_mem_interlocks
)))
1844 /* A generic coprocessor delay. The previous instruction
1845 modified a coprocessor general or control register. If
1846 it modified a control register, we need to avoid any
1847 coprocessor instruction (this is probably not always
1848 required, but it sometimes is). If it modified a general
1849 register, we avoid using that register.
1851 This case is not handled very well. There is no special
1852 knowledge of CP0 handling, and the coprocessors other
1853 than the floating point unit are not distinguished at
1855 /* Itbl support may require additional care here. FIXME!
1856 Need to modify this to include knowledge about
1857 user specified delays! */
1858 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1860 if (mips_optimize
== 0
1861 || insn_uses_reg (ip
, EXTRACT_OPERAND (FT
, history
[0]),
1865 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1867 if (mips_optimize
== 0
1868 || insn_uses_reg (ip
, EXTRACT_OPERAND (FS
, history
[0]),
1874 /* We don't know exactly what the previous instruction
1875 does. If the current instruction uses a coprocessor
1876 register, we must insert a NOP. If previous
1877 instruction may set the condition codes, and the
1878 current instruction uses them, we must insert two
1880 /* Itbl support may require additional care here. */
1881 if (mips_optimize
== 0
1882 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1883 && (pinfo
& INSN_READ_COND_CODE
)))
1885 else if (pinfo
& INSN_COP
)
1889 else if (! mips_opts
.mips16
1890 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1891 && ! cop_interlocks
)
1893 /* The previous instruction sets the coprocessor condition
1894 codes, but does not require a general coprocessor delay
1895 (this means it is a floating point comparison
1896 instruction). If this instruction uses the condition
1897 codes, we need to insert a single NOP. */
1898 /* Itbl support may require additional care here. */
1899 if (mips_optimize
== 0
1900 || (pinfo
& INSN_READ_COND_CODE
))
1904 /* If we're fixing up mfhi/mflo for the r7000 and the
1905 previous insn was an mfhi/mflo and the current insn
1906 reads the register that the mfhi/mflo wrote to, then
1909 else if (mips_7000_hilo_fix
1910 && MF_HILO_INSN (prev_pinfo
)
1911 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
1917 /* If we're fixing up mfhi/mflo for the r7000 and the
1918 2nd previous insn was an mfhi/mflo and the current insn
1919 reads the register that the mfhi/mflo wrote to, then
1922 else if (mips_7000_hilo_fix
1923 && MF_HILO_INSN (history
[1].insn_opcode
)
1924 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[1]),
1931 else if (prev_pinfo
& INSN_READ_LO
)
1933 /* The previous instruction reads the LO register; if the
1934 current instruction writes to the LO register, we must
1935 insert two NOPS. Some newer processors have interlocks.
1936 Also the tx39's multiply instructions can be executed
1937 immediately after a read from HI/LO (without the delay),
1938 though the tx39's divide insns still do require the
1940 if (! (hilo_interlocks
1941 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1942 && (mips_optimize
== 0
1943 || (pinfo
& INSN_WRITE_LO
)))
1945 /* Most mips16 branch insns don't have a delay slot.
1946 If a read from LO is immediately followed by a branch
1947 to a write to LO we have a read followed by a write
1948 less than 2 insns away. We assume the target of
1949 a branch might be a write to LO, and insert a nop
1950 between a read and an immediately following branch. */
1951 else if (mips_opts
.mips16
1952 && (mips_optimize
== 0
1953 || (pinfo
& MIPS16_INSN_BRANCH
)))
1956 else if (history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
1958 /* The previous instruction reads the HI register; if the
1959 current instruction writes to the HI register, we must
1960 insert a NOP. Some newer processors have interlocks.
1961 Also the note tx39's multiply above. */
1962 if (! (hilo_interlocks
1963 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1964 && (mips_optimize
== 0
1965 || (pinfo
& INSN_WRITE_HI
)))
1967 /* Most mips16 branch insns don't have a delay slot.
1968 If a read from HI is immediately followed by a branch
1969 to a write to HI we have a read followed by a write
1970 less than 2 insns away. We assume the target of
1971 a branch might be a write to HI, and insert a nop
1972 between a read and an immediately following branch. */
1973 else if (mips_opts
.mips16
1974 && (mips_optimize
== 0
1975 || (pinfo
& MIPS16_INSN_BRANCH
)))
1979 /* If the previous instruction was in a noreorder section, then
1980 we don't want to insert the nop after all. */
1981 /* Itbl support may require additional care here. */
1982 if (history
[0].noreorder_p
)
1985 /* There are two cases which require two intervening
1986 instructions: 1) setting the condition codes using a move to
1987 coprocessor instruction which requires a general coprocessor
1988 delay and then reading the condition codes 2) reading the HI
1989 or LO register and then writing to it (except on processors
1990 which have interlocks). If we are not already emitting a NOP
1991 instruction, we must check for these cases compared to the
1992 instruction previous to the previous instruction. */
1993 if ((! mips_opts
.mips16
1994 && (history
[1].insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1995 && (history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1996 && (pinfo
& INSN_READ_COND_CODE
)
1997 && ! cop_interlocks
)
1998 || ((history
[1].insn_mo
->pinfo
& INSN_READ_LO
)
1999 && (pinfo
& INSN_WRITE_LO
)
2000 && ! (hilo_interlocks
2001 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
2002 || ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2003 && (pinfo
& INSN_WRITE_HI
)
2004 && ! (hilo_interlocks
2005 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
2010 if (history
[1].noreorder_p
)
2013 if (prev_prev_nop
&& nops
== 0)
2016 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2018 /* We're out of bits in pinfo, so we must resort to string
2019 ops here. Shortcuts are selected based on opcodes being
2020 limited to the VR4120 instruction set. */
2022 const char *pn
= history
[0].insn_mo
->name
;
2023 const char *tn
= ip
->insn_mo
->name
;
2024 if (strncmp (pn
, "macc", 4) == 0
2025 || strncmp (pn
, "dmacc", 5) == 0)
2027 /* Errata 21 - [D]DIV[U] after [D]MACC */
2028 if (strstr (tn
, "div"))
2031 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2032 instruction is executed immediately after a MACC or
2033 DMACC instruction, the result of [either instruction]
2035 if (strncmp (tn
, "mult", 4) == 0
2036 || strncmp (tn
, "dmult", 5) == 0)
2039 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
2040 Applies on top of VR4181A MD(1) errata. */
2041 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
2044 /* Errata 24 - MT{LO,HI} after [D]MACC */
2045 if (strcmp (tn
, "mtlo") == 0
2046 || strcmp (tn
, "mthi") == 0)
2049 else if (strncmp (pn
, "dmult", 5) == 0
2050 && (strncmp (tn
, "dmult", 5) == 0
2051 || strncmp (tn
, "dmacc", 5) == 0))
2053 /* Here is the rest of errata 23. */
2056 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
2057 && (strncmp (tn
, "macc", 4) == 0
2058 || strncmp (tn
, "dmacc", 5) == 0))
2060 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2061 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2062 DDIV or DDIVU instruction, the result of the MACC or
2063 DMACC instruction is incorrect.". This partly overlaps
2064 the workaround for errata 23. */
2067 if (nops
< min_nops
)
2071 /* If we are being given a nop instruction, don't bother with
2072 one of the nops we would otherwise output. This will only
2073 happen when a nop instruction is used with mips_optimize set
2076 && ! mips_opts
.noreorder
2077 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
2080 /* Now emit the right number of NOP instructions. */
2081 if (nops
> 0 && ! mips_opts
.noreorder
)
2084 unsigned long old_frag_offset
;
2086 struct insn_label_list
*l
;
2088 old_frag
= frag_now
;
2089 old_frag_offset
= frag_now_fix ();
2091 for (i
= 0; i
< nops
; i
++)
2096 listing_prev_line ();
2097 /* We may be at the start of a variant frag. In case we
2098 are, make sure there is enough space for the frag
2099 after the frags created by listing_prev_line. The
2100 argument to frag_grow here must be at least as large
2101 as the argument to all other calls to frag_grow in
2102 this file. We don't have to worry about being in the
2103 middle of a variant frag, because the variants insert
2104 all needed nop instructions themselves. */
2108 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2112 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2113 symbol_set_frag (l
->label
, frag_now
);
2114 val
= (valueT
) frag_now_fix ();
2115 /* mips16 text labels are stored as odd. */
2116 if (mips_opts
.mips16
)
2118 S_SET_VALUE (l
->label
, val
);
2121 #ifndef NO_ECOFF_DEBUGGING
2122 if (ECOFF_DEBUGGING
)
2123 ecoff_fix_loc (old_frag
, old_frag_offset
);
2126 else if (prev_nop_frag
!= NULL
)
2128 /* We have a frag holding nops we may be able to remove. If
2129 we don't need any nops, we can decrease the size of
2130 prev_nop_frag by the size of one instruction. If we do
2131 need some nops, we count them in prev_nops_required. */
2132 if (prev_nop_frag_since
== 0)
2136 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2137 --prev_nop_frag_holds
;
2140 prev_nop_frag_required
+= nops
;
2144 if (prev_prev_nop
== 0)
2146 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2147 --prev_nop_frag_holds
;
2150 ++prev_nop_frag_required
;
2153 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2154 prev_nop_frag
= NULL
;
2156 ++prev_nop_frag_since
;
2158 /* Sanity check: by the time we reach the second instruction
2159 after prev_nop_frag, we should have used up all the nops
2160 one way or another. */
2161 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2166 /* The value passed to dwarf2_emit_insn is the distance between
2167 the beginning of the current instruction and the address that
2168 should be recorded in the debug tables. For MIPS16 debug info
2169 we want to use ISA-encoded addresses, so we pass -1 for an
2170 address higher by one than the current. */
2171 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2174 /* Record the frag type before frag_var. */
2175 if (history
[0].frag
)
2176 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2179 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2180 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2181 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2182 && mips_relax_branch
2183 /* Don't try branch relaxation within .set nomacro, or within
2184 .set noat if we use $at for PIC computations. If it turns
2185 out that the branch was out-of-range, we'll get an error. */
2186 && !mips_opts
.warn_about_macros
2187 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2188 && !mips_opts
.mips16
)
2190 relaxed_branch
= TRUE
;
2191 add_relaxed_insn (ip
, (relaxed_branch_length
2193 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2194 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2197 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2198 pinfo
& INSN_COND_BRANCH_LIKELY
,
2199 pinfo
& INSN_WRITE_GPR_31
,
2201 address_expr
->X_add_symbol
,
2202 address_expr
->X_add_number
);
2203 *reloc_type
= BFD_RELOC_UNUSED
;
2205 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2207 /* We need to set up a variant frag. */
2208 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2209 add_relaxed_insn (ip
, 4, 0,
2211 (*reloc_type
- BFD_RELOC_UNUSED
,
2212 mips16_small
, mips16_ext
,
2213 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2214 history
[0].mips16_absolute_jump_p
),
2215 make_expr_symbol (address_expr
), 0);
2217 else if (mips_opts
.mips16
2219 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2221 /* Make sure there is enough room to swap this instruction with
2222 a following jump instruction. */
2224 add_fixed_insn (ip
);
2228 if (mips_opts
.mips16
2229 && mips_opts
.noreorder
2230 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2231 as_warn (_("extended instruction in delay slot"));
2233 if (mips_relax
.sequence
)
2235 /* If we've reached the end of this frag, turn it into a variant
2236 frag and record the information for the instructions we've
2238 if (frag_room () < 4)
2239 relax_close_frag ();
2240 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2243 if (mips_relax
.sequence
!= 2)
2244 mips_macro_warning
.sizes
[0] += 4;
2245 if (mips_relax
.sequence
!= 1)
2246 mips_macro_warning
.sizes
[1] += 4;
2248 if (mips_opts
.mips16
)
2251 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2253 add_fixed_insn (ip
);
2256 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2258 if (address_expr
->X_op
== O_constant
)
2262 switch (*reloc_type
)
2265 ip
->insn_opcode
|= address_expr
->X_add_number
;
2268 case BFD_RELOC_MIPS_HIGHEST
:
2269 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2270 ip
->insn_opcode
|= tmp
& 0xffff;
2273 case BFD_RELOC_MIPS_HIGHER
:
2274 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2275 ip
->insn_opcode
|= tmp
& 0xffff;
2278 case BFD_RELOC_HI16_S
:
2279 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2280 ip
->insn_opcode
|= tmp
& 0xffff;
2283 case BFD_RELOC_HI16
:
2284 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2287 case BFD_RELOC_UNUSED
:
2288 case BFD_RELOC_LO16
:
2289 case BFD_RELOC_MIPS_GOT_DISP
:
2290 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2293 case BFD_RELOC_MIPS_JMP
:
2294 if ((address_expr
->X_add_number
& 3) != 0)
2295 as_bad (_("jump to misaligned address (0x%lx)"),
2296 (unsigned long) address_expr
->X_add_number
);
2297 if (address_expr
->X_add_number
& ~0xfffffff)
2298 as_bad (_("jump address range overflow (0x%lx)"),
2299 (unsigned long) address_expr
->X_add_number
);
2300 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2303 case BFD_RELOC_MIPS16_JMP
:
2304 if ((address_expr
->X_add_number
& 3) != 0)
2305 as_bad (_("jump to misaligned address (0x%lx)"),
2306 (unsigned long) address_expr
->X_add_number
);
2307 if (address_expr
->X_add_number
& ~0xfffffff)
2308 as_bad (_("jump address range overflow (0x%lx)"),
2309 (unsigned long) address_expr
->X_add_number
);
2311 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2312 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2313 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2316 case BFD_RELOC_16_PCREL_S2
:
2323 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2326 reloc_howto_type
*howto
;
2329 /* In a compound relocation, it is the final (outermost)
2330 operator that determines the relocated field. */
2331 for (i
= 1; i
< 3; i
++)
2332 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2335 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2336 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2337 bfd_get_reloc_size (howto
),
2339 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2342 /* These relocations can have an addend that won't fit in
2343 4 octets for 64bit assembly. */
2345 && ! howto
->partial_inplace
2346 && (reloc_type
[0] == BFD_RELOC_16
2347 || reloc_type
[0] == BFD_RELOC_32
2348 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2349 || reloc_type
[0] == BFD_RELOC_HI16_S
2350 || reloc_type
[0] == BFD_RELOC_LO16
2351 || reloc_type
[0] == BFD_RELOC_GPREL16
2352 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2353 || reloc_type
[0] == BFD_RELOC_GPREL32
2354 || reloc_type
[0] == BFD_RELOC_64
2355 || reloc_type
[0] == BFD_RELOC_CTOR
2356 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2357 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2358 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2359 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2360 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2361 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2362 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2363 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2364 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2365 ip
->fixp
[0]->fx_no_overflow
= 1;
2367 if (mips_relax
.sequence
)
2369 if (mips_relax
.first_fixup
== 0)
2370 mips_relax
.first_fixup
= ip
->fixp
[0];
2372 else if (reloc_needs_lo_p (*reloc_type
))
2374 struct mips_hi_fixup
*hi_fixup
;
2376 /* Reuse the last entry if it already has a matching %lo. */
2377 hi_fixup
= mips_hi_fixup_list
;
2379 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2381 hi_fixup
= ((struct mips_hi_fixup
*)
2382 xmalloc (sizeof (struct mips_hi_fixup
)));
2383 hi_fixup
->next
= mips_hi_fixup_list
;
2384 mips_hi_fixup_list
= hi_fixup
;
2386 hi_fixup
->fixp
= ip
->fixp
[0];
2387 hi_fixup
->seg
= now_seg
;
2390 /* Add fixups for the second and third relocations, if given.
2391 Note that the ABI allows the second relocation to be
2392 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2393 moment we only use RSS_UNDEF, but we could add support
2394 for the others if it ever becomes necessary. */
2395 for (i
= 1; i
< 3; i
++)
2396 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2398 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2399 ip
->fixp
[0]->fx_size
, NULL
, 0,
2400 FALSE
, reloc_type
[i
]);
2402 /* Use fx_tcbit to mark compound relocs. */
2403 ip
->fixp
[0]->fx_tcbit
= 1;
2404 ip
->fixp
[i
]->fx_tcbit
= 1;
2410 /* Update the register mask information. */
2411 if (! mips_opts
.mips16
)
2413 if (pinfo
& INSN_WRITE_GPR_D
)
2414 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2415 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2416 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2417 if (pinfo
& INSN_READ_GPR_S
)
2418 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2419 if (pinfo
& INSN_WRITE_GPR_31
)
2420 mips_gprmask
|= 1 << RA
;
2421 if (pinfo
& INSN_WRITE_FPR_D
)
2422 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2423 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2424 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2425 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2426 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2427 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2428 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2429 if (pinfo
& INSN_COP
)
2431 /* We don't keep enough information to sort these cases out.
2432 The itbl support does keep this information however, although
2433 we currently don't support itbl fprmats as part of the cop
2434 instruction. May want to add this support in the future. */
2436 /* Never set the bit for $0, which is always zero. */
2437 mips_gprmask
&= ~1 << 0;
2441 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2442 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2443 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2444 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2445 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2446 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2447 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2448 mips_gprmask
|= 1 << TREG
;
2449 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2450 mips_gprmask
|= 1 << SP
;
2451 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2452 mips_gprmask
|= 1 << RA
;
2453 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2454 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2455 if (pinfo
& MIPS16_INSN_READ_Z
)
2456 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2457 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2458 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2461 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2463 /* Filling the branch delay slot is more complex. We try to
2464 switch the branch with the previous instruction, which we can
2465 do if the previous instruction does not set up a condition
2466 that the branch tests and if the branch is not itself the
2467 target of any branch. */
2468 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2469 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2471 if (mips_optimize
< 2
2472 /* If we have seen .set volatile or .set nomove, don't
2474 || mips_opts
.nomove
!= 0
2475 /* We can't swap if the previous instruction's position
2477 || history
[0].fixed_p
2478 /* If the previous previous insn was in a .set
2479 noreorder, we can't swap. Actually, the MIPS
2480 assembler will swap in this situation. However, gcc
2481 configured -with-gnu-as will generate code like
2487 in which we can not swap the bne and INSN. If gcc is
2488 not configured -with-gnu-as, it does not output the
2490 || history
[1].noreorder_p
2491 /* If the branch is itself the target of a branch, we
2492 can not swap. We cheat on this; all we check for is
2493 whether there is a label on this instruction. If
2494 there are any branches to anything other than a
2495 label, users must use .set noreorder. */
2496 || insn_labels
!= NULL
2497 /* If the previous instruction is in a variant frag
2498 other than this branch's one, we cannot do the swap.
2499 This does not apply to the mips16, which uses variant
2500 frags for different purposes. */
2501 || (! mips_opts
.mips16
2502 && prev_insn_frag_type
== rs_machine_dependent
)
2503 /* If the branch reads the condition codes, we don't
2504 even try to swap, because in the sequence
2509 we can not swap, and I don't feel like handling that
2511 || (! mips_opts
.mips16
2512 && (pinfo
& INSN_READ_COND_CODE
)
2513 && ! cop_interlocks
)
2514 /* We can not swap with an instruction that requires a
2515 delay slot, because the target of the branch might
2516 interfere with that instruction. */
2517 || (! mips_opts
.mips16
2519 /* Itbl support may require additional care here. */
2520 & (INSN_LOAD_COPROC_DELAY
2521 | INSN_COPROC_MOVE_DELAY
2522 | INSN_WRITE_COND_CODE
))
2523 && ! cop_interlocks
)
2524 || (! (hilo_interlocks
2525 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2529 || (! mips_opts
.mips16
2530 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2531 && ! gpr_interlocks
)
2532 || (! mips_opts
.mips16
2533 /* Itbl support may require additional care here. */
2534 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2535 && ! cop_mem_interlocks
)
2536 /* We do not swap with a trap instruction, since it
2537 complicates trap handlers to have the trap
2538 instruction be in a delay slot. */
2539 || (prev_pinfo
& INSN_TRAP
)
2540 /* If the branch reads a register that the previous
2541 instruction sets, we can not swap. */
2542 || (! mips_opts
.mips16
2543 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2544 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2546 || (! mips_opts
.mips16
2547 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2548 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2550 || (mips_opts
.mips16
2551 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2553 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2555 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2557 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2559 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2561 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2563 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2564 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2565 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2566 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2567 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2568 && insn_uses_reg (ip
,
2569 MIPS16OP_EXTRACT_REG32R
2570 (history
[0].insn_opcode
),
2572 /* If the branch writes a register that the previous
2573 instruction sets, we can not swap (we know that
2574 branches write only to RD or to $31). */
2575 || (! mips_opts
.mips16
2576 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2577 && (((pinfo
& INSN_WRITE_GPR_D
)
2578 && (EXTRACT_OPERAND (RT
, history
[0])
2579 == EXTRACT_OPERAND (RD
, *ip
)))
2580 || ((pinfo
& INSN_WRITE_GPR_31
)
2581 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2582 || (! mips_opts
.mips16
2583 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2584 && (((pinfo
& INSN_WRITE_GPR_D
)
2585 && (EXTRACT_OPERAND (RD
, history
[0])
2586 == EXTRACT_OPERAND (RD
, *ip
)))
2587 || ((pinfo
& INSN_WRITE_GPR_31
)
2588 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2589 || (mips_opts
.mips16
2590 && (pinfo
& MIPS16_INSN_WRITE_31
)
2591 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2592 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2593 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2595 /* If the branch writes a register that the previous
2596 instruction reads, we can not swap (we know that
2597 branches only write to RD or to $31). */
2598 || (! mips_opts
.mips16
2599 && (pinfo
& INSN_WRITE_GPR_D
)
2600 && insn_uses_reg (&history
[0],
2601 EXTRACT_OPERAND (RD
, *ip
),
2603 || (! mips_opts
.mips16
2604 && (pinfo
& INSN_WRITE_GPR_31
)
2605 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2606 || (mips_opts
.mips16
2607 && (pinfo
& MIPS16_INSN_WRITE_31
)
2608 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2609 /* If the previous previous instruction has a load
2610 delay, and sets a register that the branch reads, we
2612 || (! mips_opts
.mips16
2613 /* Itbl support may require additional care here. */
2614 && (((history
[1].insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2615 && ! cop_interlocks
)
2616 || ((history
[1].insn_mo
->pinfo
2617 & INSN_LOAD_MEMORY_DELAY
)
2618 && ! gpr_interlocks
))
2619 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[1]),
2621 /* If one instruction sets a condition code and the
2622 other one uses a condition code, we can not swap. */
2623 || ((pinfo
& INSN_READ_COND_CODE
)
2624 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2625 || ((pinfo
& INSN_WRITE_COND_CODE
)
2626 && (prev_pinfo
& INSN_READ_COND_CODE
))
2627 /* If the previous instruction uses the PC, we can not
2629 || (mips_opts
.mips16
2630 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2631 /* If the previous instruction had a fixup in mips16
2632 mode, we can not swap. This normally means that the
2633 previous instruction was a 4 byte branch anyhow. */
2634 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2635 /* If the previous instruction is a sync, sync.l, or
2636 sync.p, we can not swap. */
2637 || (prev_pinfo
& INSN_SYNC
))
2639 /* We could do even better for unconditional branches to
2640 portions of this object file; we could pick up the
2641 instruction at the destination, put it in the delay
2642 slot, and bump the destination address. */
2643 insert_into_history (0, 1, ip
);
2645 if (mips_relax
.sequence
)
2646 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2650 /* It looks like we can actually do the swap. */
2651 struct mips_cl_insn delay
= history
[0];
2652 if (mips_opts
.mips16
)
2654 know (delay
.frag
== ip
->frag
);
2655 move_insn (ip
, delay
.frag
, delay
.where
);
2656 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2658 else if (relaxed_branch
)
2660 /* Add the delay slot instruction to the end of the
2661 current frag and shrink the fixed part of the
2662 original frag. If the branch occupies the tail of
2663 the latter, move it backwards to cover the gap. */
2664 delay
.frag
->fr_fix
-= 4;
2665 if (delay
.frag
== ip
->frag
)
2666 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2667 add_fixed_insn (&delay
);
2671 move_insn (&delay
, ip
->frag
, ip
->where
);
2672 move_insn (ip
, history
[0].frag
, history
[0].where
);
2676 insert_into_history (0, 1, &delay
);
2679 /* If that was an unconditional branch, forget the previous
2680 insn information. */
2681 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2682 mips_no_prev_insn (FALSE
);
2684 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2686 /* We don't yet optimize a branch likely. What we should do
2687 is look at the target, copy the instruction found there
2688 into the delay slot, and increment the branch to jump to
2689 the next instruction. */
2690 insert_into_history (0, 1, ip
);
2694 insert_into_history (0, 1, ip
);
2697 insert_into_history (0, 1, ip
);
2699 /* We just output an insn, so the next one doesn't have a label. */
2700 mips_clear_insn_labels ();
2703 /* This function forgets that there was any previous instruction or
2704 label. If PRESERVE is non-zero, it remembers enough information to
2705 know whether nops are needed before a noreorder section. */
2708 mips_no_prev_insn (int preserve
)
2714 prev_nop_frag
= NULL
;
2715 prev_nop_frag_holds
= 0;
2716 prev_nop_frag_required
= 0;
2717 prev_nop_frag_since
= 0;
2718 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2719 history
[i
] = (mips_opts
.mips16
? mips16_nop_insn
: nop_insn
);
2722 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2724 history
[i
].fixed_p
= 1;
2725 history
[i
].noreorder_p
= 0;
2726 history
[i
].mips16_absolute_jump_p
= 0;
2728 mips_clear_insn_labels ();
2731 /* This function must be called whenever we turn on noreorder or emit
2732 something other than instructions. It inserts any NOPS which might
2733 be needed by the previous instruction, and clears the information
2734 kept for the previous instructions. The INSNS parameter is true if
2735 instructions are to follow. */
2738 mips_emit_delays (bfd_boolean insns
)
2740 if (! mips_opts
.noreorder
)
2745 if ((! mips_opts
.mips16
2746 && ((history
[0].insn_mo
->pinfo
2747 & (INSN_LOAD_COPROC_DELAY
2748 | INSN_COPROC_MOVE_DELAY
2749 | INSN_WRITE_COND_CODE
))
2750 && ! cop_interlocks
))
2751 || (! hilo_interlocks
2752 && (history
[0].insn_mo
->pinfo
2755 || (! mips_opts
.mips16
2756 && (history
[0].insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2757 && ! gpr_interlocks
)
2758 || (! mips_opts
.mips16
2759 && (history
[0].insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2760 && ! cop_mem_interlocks
))
2762 /* Itbl support may require additional care here. */
2764 if ((! mips_opts
.mips16
2765 && ((history
[0].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2766 && ! cop_interlocks
))
2767 || (! hilo_interlocks
2768 && ((history
[0].insn_mo
->pinfo
& INSN_READ_HI
)
2769 || (history
[0].insn_mo
->pinfo
& INSN_READ_LO
))))
2772 if (history
[0].noreorder_p
)
2775 else if ((! mips_opts
.mips16
2776 && ((history
[1].insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2777 && ! cop_interlocks
))
2778 || (! hilo_interlocks
2779 && ((history
[1].insn_mo
->pinfo
& INSN_READ_HI
)
2780 || (history
[1].insn_mo
->pinfo
& INSN_READ_LO
))))
2782 /* Itbl support may require additional care here. */
2783 if (! history
[1].noreorder_p
)
2787 if (mips_fix_vr4120
&& history
[0].insn_mo
->name
)
2790 const char *pn
= history
[0].insn_mo
->name
;
2791 if (strncmp (pn
, "macc", 4) == 0
2792 || strncmp (pn
, "dmacc", 5) == 0
2793 || strncmp (pn
, "dmult", 5) == 0
2794 || strstr (pn
, "div"))
2796 if (nops
< min_nops
)
2802 struct insn_label_list
*l
;
2806 /* Record the frag which holds the nop instructions, so
2807 that we can remove them if we don't need them. */
2808 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2809 prev_nop_frag
= frag_now
;
2810 prev_nop_frag_holds
= nops
;
2811 prev_nop_frag_required
= 0;
2812 prev_nop_frag_since
= 0;
2815 for (; nops
> 0; --nops
)
2816 add_fixed_insn (NOP_INSN
);
2820 /* Move on to a new frag, so that it is safe to simply
2821 decrease the size of prev_nop_frag. */
2822 frag_wane (frag_now
);
2826 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2830 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2831 symbol_set_frag (l
->label
, frag_now
);
2832 val
= (valueT
) frag_now_fix ();
2833 /* mips16 text labels are stored as odd. */
2834 if (mips_opts
.mips16
)
2836 S_SET_VALUE (l
->label
, val
);
2841 /* Mark instruction labels in mips16 mode. */
2843 mips16_mark_labels ();
2845 mips_no_prev_insn (insns
);
2848 /* Set up global variables for the start of a new macro. */
2853 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2854 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2855 && (history
[0].insn_mo
->pinfo
2856 & (INSN_UNCOND_BRANCH_DELAY
2857 | INSN_COND_BRANCH_DELAY
2858 | INSN_COND_BRANCH_LIKELY
)) != 0);
2861 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2862 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2863 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2866 macro_warning (relax_substateT subtype
)
2868 if (subtype
& RELAX_DELAY_SLOT
)
2869 return _("Macro instruction expanded into multiple instructions"
2870 " in a branch delay slot");
2871 else if (subtype
& RELAX_NOMACRO
)
2872 return _("Macro instruction expanded into multiple instructions");
2877 /* Finish up a macro. Emit warnings as appropriate. */
2882 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2884 relax_substateT subtype
;
2886 /* Set up the relaxation warning flags. */
2888 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2889 subtype
|= RELAX_SECOND_LONGER
;
2890 if (mips_opts
.warn_about_macros
)
2891 subtype
|= RELAX_NOMACRO
;
2892 if (mips_macro_warning
.delay_slot_p
)
2893 subtype
|= RELAX_DELAY_SLOT
;
2895 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2897 /* Either the macro has a single implementation or both
2898 implementations are longer than 4 bytes. Emit the
2900 const char *msg
= macro_warning (subtype
);
2906 /* One implementation might need a warning but the other
2907 definitely doesn't. */
2908 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2913 /* Read a macro's relocation codes from *ARGS and store them in *R.
2914 The first argument in *ARGS will be either the code for a single
2915 relocation or -1 followed by the three codes that make up a
2916 composite relocation. */
2919 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2923 next
= va_arg (*args
, int);
2925 r
[0] = (bfd_reloc_code_real_type
) next
;
2927 for (i
= 0; i
< 3; i
++)
2928 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2931 /* Build an instruction created by a macro expansion. This is passed
2932 a pointer to the count of instructions created so far, an
2933 expression, the name of the instruction to build, an operand format
2934 string, and corresponding arguments. */
2937 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2939 const struct mips_opcode
*mo
;
2940 struct mips_cl_insn insn
;
2941 bfd_reloc_code_real_type r
[3];
2944 va_start (args
, fmt
);
2946 if (mips_opts
.mips16
)
2948 mips16_macro_build (ep
, name
, fmt
, args
);
2953 r
[0] = BFD_RELOC_UNUSED
;
2954 r
[1] = BFD_RELOC_UNUSED
;
2955 r
[2] = BFD_RELOC_UNUSED
;
2956 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2958 assert (strcmp (name
, mo
->name
) == 0);
2960 /* Search until we get a match for NAME. It is assumed here that
2961 macros will never generate MDMX or MIPS-3D instructions. */
2962 while (strcmp (fmt
, mo
->args
) != 0
2963 || mo
->pinfo
== INSN_MACRO
2964 || !OPCODE_IS_MEMBER (mo
,
2966 | (file_ase_mips16
? INSN_MIPS16
: 0)),
2968 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
2972 assert (strcmp (name
, mo
->name
) == 0);
2975 create_insn (&insn
, mo
);
2993 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
2998 /* Note that in the macro case, these arguments are already
2999 in MSB form. (When handling the instruction in the
3000 non-macro case, these arguments are sizes from which
3001 MSB values must be calculated.) */
3002 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3008 /* Note that in the macro case, these arguments are already
3009 in MSBD form. (When handling the instruction in the
3010 non-macro case, these arguments are sizes from which
3011 MSBD values must be calculated.) */
3012 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3023 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3027 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3032 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3038 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3043 int tmp
= va_arg (args
, int);
3045 INSERT_OPERAND (RT
, insn
, tmp
);
3046 INSERT_OPERAND (RD
, insn
, tmp
);
3052 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3059 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3063 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3067 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3071 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3075 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3082 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3088 macro_read_relocs (&args
, r
);
3089 assert (*r
== BFD_RELOC_GPREL16
3090 || *r
== BFD_RELOC_MIPS_LITERAL
3091 || *r
== BFD_RELOC_MIPS_HIGHER
3092 || *r
== BFD_RELOC_HI16_S
3093 || *r
== BFD_RELOC_LO16
3094 || *r
== BFD_RELOC_MIPS_GOT16
3095 || *r
== BFD_RELOC_MIPS_CALL16
3096 || *r
== BFD_RELOC_MIPS_GOT_DISP
3097 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3098 || *r
== BFD_RELOC_MIPS_GOT_OFST
3099 || *r
== BFD_RELOC_MIPS_GOT_LO16
3100 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3104 macro_read_relocs (&args
, r
);
3106 && (ep
->X_op
== O_constant
3107 || (ep
->X_op
== O_symbol
3108 && (*r
== BFD_RELOC_MIPS_HIGHEST
3109 || *r
== BFD_RELOC_HI16_S
3110 || *r
== BFD_RELOC_HI16
3111 || *r
== BFD_RELOC_GPREL16
3112 || *r
== BFD_RELOC_MIPS_GOT_HI16
3113 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3117 assert (ep
!= NULL
);
3119 * This allows macro() to pass an immediate expression for
3120 * creating short branches without creating a symbol.
3121 * Note that the expression still might come from the assembly
3122 * input, in which case the value is not checked for range nor
3123 * is a relocation entry generated (yuck).
3125 if (ep
->X_op
== O_constant
)
3127 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3131 *r
= BFD_RELOC_16_PCREL_S2
;
3135 assert (ep
!= NULL
);
3136 *r
= BFD_RELOC_MIPS_JMP
;
3140 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3149 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3151 append_insn (&insn
, ep
, r
);
3155 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3158 struct mips_opcode
*mo
;
3159 struct mips_cl_insn insn
;
3160 bfd_reloc_code_real_type r
[3]
3161 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3163 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3165 assert (strcmp (name
, mo
->name
) == 0);
3167 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3171 assert (strcmp (name
, mo
->name
) == 0);
3174 create_insn (&insn
, mo
);
3192 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3197 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3201 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3205 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3215 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3222 regno
= va_arg (args
, int);
3223 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3224 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3245 assert (ep
!= NULL
);
3247 if (ep
->X_op
!= O_constant
)
3248 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3251 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3252 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3255 *r
= BFD_RELOC_UNUSED
;
3261 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3268 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3270 append_insn (&insn
, ep
, r
);
3274 * Generate a "jalr" instruction with a relocation hint to the called
3275 * function. This occurs in NewABI PIC code.
3278 macro_build_jalr (expressionS
*ep
)
3287 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3289 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3290 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3294 * Generate a "lui" instruction.
3297 macro_build_lui (expressionS
*ep
, int regnum
)
3299 expressionS high_expr
;
3300 const struct mips_opcode
*mo
;
3301 struct mips_cl_insn insn
;
3302 bfd_reloc_code_real_type r
[3]
3303 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3304 const char *name
= "lui";
3305 const char *fmt
= "t,u";
3307 assert (! mips_opts
.mips16
);
3311 if (high_expr
.X_op
== O_constant
)
3313 /* we can compute the instruction now without a relocation entry */
3314 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3316 *r
= BFD_RELOC_UNUSED
;
3320 assert (ep
->X_op
== O_symbol
);
3321 /* _gp_disp is a special case, used from s_cpload.
3322 __gnu_local_gp is used if mips_no_shared. */
3323 assert (mips_pic
== NO_PIC
3325 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3326 || (! mips_in_shared
3327 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3328 "__gnu_local_gp") == 0));
3329 *r
= BFD_RELOC_HI16_S
;
3332 mo
= hash_find (op_hash
, name
);
3333 assert (strcmp (name
, mo
->name
) == 0);
3334 assert (strcmp (fmt
, mo
->args
) == 0);
3335 create_insn (&insn
, mo
);
3337 insn
.insn_opcode
= insn
.insn_mo
->match
;
3338 INSERT_OPERAND (RT
, insn
, regnum
);
3339 if (*r
== BFD_RELOC_UNUSED
)
3341 insn
.insn_opcode
|= high_expr
.X_add_number
;
3342 append_insn (&insn
, NULL
, r
);
3345 append_insn (&insn
, &high_expr
, r
);
3348 /* Generate a sequence of instructions to do a load or store from a constant
3349 offset off of a base register (breg) into/from a target register (treg),
3350 using AT if necessary. */
3352 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3353 int treg
, int breg
, int dbl
)
3355 assert (ep
->X_op
== O_constant
);
3357 /* Sign-extending 32-bit constants makes their handling easier. */
3358 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3359 == ~((bfd_vma
) 0x7fffffff)))
3361 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3362 as_bad (_("constant too large"));
3364 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3368 /* Right now, this routine can only handle signed 32-bit constants. */
3369 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3370 as_warn (_("operand overflow"));
3372 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3374 /* Signed 16-bit offset will fit in the op. Easy! */
3375 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3379 /* 32-bit offset, need multiple instructions and AT, like:
3380 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3381 addu $tempreg,$tempreg,$breg
3382 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3383 to handle the complete offset. */
3384 macro_build_lui (ep
, AT
);
3385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3386 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3389 as_bad (_("Macro used $at after \".set noat\""));
3394 * Generates code to set the $at register to true (one)
3395 * if reg is less than the immediate expression.
3398 set_at (int reg
, int unsignedp
)
3400 if (imm_expr
.X_op
== O_constant
3401 && imm_expr
.X_add_number
>= -0x8000
3402 && imm_expr
.X_add_number
< 0x8000)
3403 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3404 AT
, reg
, BFD_RELOC_LO16
);
3407 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3408 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3413 normalize_constant_expr (expressionS
*ex
)
3415 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3416 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3420 /* Warn if an expression is not a constant. */
3423 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3425 if (ex
->X_op
== O_big
)
3426 as_bad (_("unsupported large constant"));
3427 else if (ex
->X_op
!= O_constant
)
3428 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3430 normalize_constant_expr (ex
);
3433 /* Count the leading zeroes by performing a binary chop. This is a
3434 bulky bit of source, but performance is a LOT better for the
3435 majority of values than a simple loop to count the bits:
3436 for (lcnt = 0; (lcnt < 32); lcnt++)
3437 if ((v) & (1 << (31 - lcnt)))
3439 However it is not code size friendly, and the gain will drop a bit
3440 on certain cached systems.
3442 #define COUNT_TOP_ZEROES(v) \
3443 (((v) & ~0xffff) == 0 \
3444 ? ((v) & ~0xff) == 0 \
3445 ? ((v) & ~0xf) == 0 \
3446 ? ((v) & ~0x3) == 0 \
3447 ? ((v) & ~0x1) == 0 \
3452 : ((v) & ~0x7) == 0 \
3455 : ((v) & ~0x3f) == 0 \
3456 ? ((v) & ~0x1f) == 0 \
3459 : ((v) & ~0x7f) == 0 \
3462 : ((v) & ~0xfff) == 0 \
3463 ? ((v) & ~0x3ff) == 0 \
3464 ? ((v) & ~0x1ff) == 0 \
3467 : ((v) & ~0x7ff) == 0 \
3470 : ((v) & ~0x3fff) == 0 \
3471 ? ((v) & ~0x1fff) == 0 \
3474 : ((v) & ~0x7fff) == 0 \
3477 : ((v) & ~0xffffff) == 0 \
3478 ? ((v) & ~0xfffff) == 0 \
3479 ? ((v) & ~0x3ffff) == 0 \
3480 ? ((v) & ~0x1ffff) == 0 \
3483 : ((v) & ~0x7ffff) == 0 \
3486 : ((v) & ~0x3fffff) == 0 \
3487 ? ((v) & ~0x1fffff) == 0 \
3490 : ((v) & ~0x7fffff) == 0 \
3493 : ((v) & ~0xfffffff) == 0 \
3494 ? ((v) & ~0x3ffffff) == 0 \
3495 ? ((v) & ~0x1ffffff) == 0 \
3498 : ((v) & ~0x7ffffff) == 0 \
3501 : ((v) & ~0x3fffffff) == 0 \
3502 ? ((v) & ~0x1fffffff) == 0 \
3505 : ((v) & ~0x7fffffff) == 0 \
3510 * This routine generates the least number of instructions necessary to load
3511 * an absolute expression value into a register.
3514 load_register (int reg
, expressionS
*ep
, int dbl
)
3517 expressionS hi32
, lo32
;
3519 if (ep
->X_op
!= O_big
)
3521 assert (ep
->X_op
== O_constant
);
3523 /* Sign-extending 32-bit constants makes their handling easier. */
3524 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3525 == ~((bfd_vma
) 0x7fffffff)))
3527 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3528 as_bad (_("constant too large"));
3530 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3534 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3536 /* We can handle 16 bit signed values with an addiu to
3537 $zero. No need to ever use daddiu here, since $zero and
3538 the result are always correct in 32 bit mode. */
3539 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3542 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3544 /* We can handle 16 bit unsigned values with an ori to
3546 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3549 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3551 /* 32 bit values require an lui. */
3552 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3553 if ((ep
->X_add_number
& 0xffff) != 0)
3554 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3559 /* The value is larger than 32 bits. */
3561 if (HAVE_32BIT_GPRS
)
3563 as_bad (_("Number (0x%lx) larger than 32 bits"),
3564 (unsigned long) ep
->X_add_number
);
3565 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3569 if (ep
->X_op
!= O_big
)
3572 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3573 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3574 hi32
.X_add_number
&= 0xffffffff;
3576 lo32
.X_add_number
&= 0xffffffff;
3580 assert (ep
->X_add_number
> 2);
3581 if (ep
->X_add_number
== 3)
3582 generic_bignum
[3] = 0;
3583 else if (ep
->X_add_number
> 4)
3584 as_bad (_("Number larger than 64 bits"));
3585 lo32
.X_op
= O_constant
;
3586 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3587 hi32
.X_op
= O_constant
;
3588 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3591 if (hi32
.X_add_number
== 0)
3596 unsigned long hi
, lo
;
3598 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3600 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3602 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3605 if (lo32
.X_add_number
& 0x80000000)
3607 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3608 if (lo32
.X_add_number
& 0xffff)
3609 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3614 /* Check for 16bit shifted constant. We know that hi32 is
3615 non-zero, so start the mask on the first bit of the hi32
3620 unsigned long himask
, lomask
;
3624 himask
= 0xffff >> (32 - shift
);
3625 lomask
= (0xffff << shift
) & 0xffffffff;
3629 himask
= 0xffff << (shift
- 32);
3632 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3633 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3637 tmp
.X_op
= O_constant
;
3639 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3640 | (lo32
.X_add_number
>> shift
));
3642 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3643 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3644 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3645 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3650 while (shift
<= (64 - 16));
3652 /* Find the bit number of the lowest one bit, and store the
3653 shifted value in hi/lo. */
3654 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3655 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3659 while ((lo
& 1) == 0)
3664 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3670 while ((hi
& 1) == 0)
3679 /* Optimize if the shifted value is a (power of 2) - 1. */
3680 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3681 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3683 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3688 /* This instruction will set the register to be all
3690 tmp
.X_op
= O_constant
;
3691 tmp
.X_add_number
= (offsetT
) -1;
3692 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3696 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3697 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3699 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3700 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3705 /* Sign extend hi32 before calling load_register, because we can
3706 generally get better code when we load a sign extended value. */
3707 if ((hi32
.X_add_number
& 0x80000000) != 0)
3708 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3709 load_register (reg
, &hi32
, 0);
3712 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3716 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3724 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3726 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3727 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3733 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3737 mid16
.X_add_number
>>= 16;
3738 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3739 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3742 if ((lo32
.X_add_number
& 0xffff) != 0)
3743 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3747 load_delay_nop (void)
3749 if (!gpr_interlocks
)
3750 macro_build (NULL
, "nop", "");
3753 /* Load an address into a register. */
3756 load_address (int reg
, expressionS
*ep
, int *used_at
)
3758 if (ep
->X_op
!= O_constant
3759 && ep
->X_op
!= O_symbol
)
3761 as_bad (_("expression too complex"));
3762 ep
->X_op
= O_constant
;
3765 if (ep
->X_op
== O_constant
)
3767 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3771 if (mips_pic
== NO_PIC
)
3773 /* If this is a reference to a GP relative symbol, we want
3774 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3776 lui $reg,<sym> (BFD_RELOC_HI16_S)
3777 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3778 If we have an addend, we always use the latter form.
3780 With 64bit address space and a usable $at we want
3781 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3782 lui $at,<sym> (BFD_RELOC_HI16_S)
3783 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3784 daddiu $at,<sym> (BFD_RELOC_LO16)
3788 If $at is already in use, we use a path which is suboptimal
3789 on superscalar processors.
3790 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3791 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3793 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3795 daddiu $reg,<sym> (BFD_RELOC_LO16)
3797 For GP relative symbols in 64bit address space we can use
3798 the same sequence as in 32bit address space. */
3799 if (HAVE_64BIT_SYMBOLS
)
3801 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3802 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3804 relax_start (ep
->X_add_symbol
);
3805 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3806 mips_gp_register
, BFD_RELOC_GPREL16
);
3810 if (*used_at
== 0 && !mips_opts
.noat
)
3812 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3813 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3814 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3815 BFD_RELOC_MIPS_HIGHER
);
3816 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3817 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3818 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3823 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3824 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3825 BFD_RELOC_MIPS_HIGHER
);
3826 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3827 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3828 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3829 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3832 if (mips_relax
.sequence
)
3837 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3838 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3840 relax_start (ep
->X_add_symbol
);
3841 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3842 mips_gp_register
, BFD_RELOC_GPREL16
);
3845 macro_build_lui (ep
, reg
);
3846 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3847 reg
, reg
, BFD_RELOC_LO16
);
3848 if (mips_relax
.sequence
)
3852 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3856 /* If this is a reference to an external symbol, we want
3857 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3859 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3861 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3862 If there is a constant, it must be added in after.
3864 If we have NewABI, we want
3865 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3866 unless we're referencing a global symbol with a non-zero
3867 offset, in which case cst must be added separately. */
3870 if (ep
->X_add_number
)
3872 ex
.X_add_number
= ep
->X_add_number
;
3873 ep
->X_add_number
= 0;
3874 relax_start (ep
->X_add_symbol
);
3875 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3876 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3877 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3878 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3879 ex
.X_op
= O_constant
;
3880 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3881 reg
, reg
, BFD_RELOC_LO16
);
3882 ep
->X_add_number
= ex
.X_add_number
;
3885 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3886 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3887 if (mips_relax
.sequence
)
3892 ex
.X_add_number
= ep
->X_add_number
;
3893 ep
->X_add_number
= 0;
3894 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3895 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3897 relax_start (ep
->X_add_symbol
);
3899 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3903 if (ex
.X_add_number
!= 0)
3905 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3906 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3907 ex
.X_op
= O_constant
;
3908 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3909 reg
, reg
, BFD_RELOC_LO16
);
3913 else if (mips_pic
== SVR4_PIC
)
3917 /* This is the large GOT case. If this is a reference to an
3918 external symbol, we want
3919 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3921 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3923 Otherwise, for a reference to a local symbol in old ABI, we want
3924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3926 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3927 If there is a constant, it must be added in after.
3929 In the NewABI, for local symbols, with or without offsets, we want:
3930 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3931 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3935 ex
.X_add_number
= ep
->X_add_number
;
3936 ep
->X_add_number
= 0;
3937 relax_start (ep
->X_add_symbol
);
3938 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3939 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3940 reg
, reg
, mips_gp_register
);
3941 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3942 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3943 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3944 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3945 else if (ex
.X_add_number
)
3947 ex
.X_op
= O_constant
;
3948 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3952 ep
->X_add_number
= ex
.X_add_number
;
3954 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3955 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3956 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3957 BFD_RELOC_MIPS_GOT_OFST
);
3962 ex
.X_add_number
= ep
->X_add_number
;
3963 ep
->X_add_number
= 0;
3964 relax_start (ep
->X_add_symbol
);
3965 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3966 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3967 reg
, reg
, mips_gp_register
);
3968 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3969 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3971 if (reg_needs_delay (mips_gp_register
))
3973 /* We need a nop before loading from $gp. This special
3974 check is required because the lui which starts the main
3975 instruction stream does not refer to $gp, and so will not
3976 insert the nop which may be required. */
3977 macro_build (NULL
, "nop", "");
3979 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3980 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3982 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3986 if (ex
.X_add_number
!= 0)
3988 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3989 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3990 ex
.X_op
= O_constant
;
3991 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3999 if (mips_opts
.noat
&& *used_at
== 1)
4000 as_bad (_("Macro used $at after \".set noat\""));
4003 /* Move the contents of register SOURCE into register DEST. */
4006 move_register (int dest
, int source
)
4008 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4012 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4013 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4014 The two alternatives are:
4016 Global symbol Local sybmol
4017 ------------- ------------
4018 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4020 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4022 load_got_offset emits the first instruction and add_got_offset
4023 emits the second for a 16-bit offset or add_got_offset_hilo emits
4024 a sequence to add a 32-bit offset using a scratch register. */
4027 load_got_offset (int dest
, expressionS
*local
)
4032 global
.X_add_number
= 0;
4034 relax_start (local
->X_add_symbol
);
4035 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4036 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4038 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4039 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4044 add_got_offset (int dest
, expressionS
*local
)
4048 global
.X_op
= O_constant
;
4049 global
.X_op_symbol
= NULL
;
4050 global
.X_add_symbol
= NULL
;
4051 global
.X_add_number
= local
->X_add_number
;
4053 relax_start (local
->X_add_symbol
);
4054 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4055 dest
, dest
, BFD_RELOC_LO16
);
4057 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4062 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4065 int hold_mips_optimize
;
4067 global
.X_op
= O_constant
;
4068 global
.X_op_symbol
= NULL
;
4069 global
.X_add_symbol
= NULL
;
4070 global
.X_add_number
= local
->X_add_number
;
4072 relax_start (local
->X_add_symbol
);
4073 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4075 /* Set mips_optimize around the lui instruction to avoid
4076 inserting an unnecessary nop after the lw. */
4077 hold_mips_optimize
= mips_optimize
;
4079 macro_build_lui (&global
, tmp
);
4080 mips_optimize
= hold_mips_optimize
;
4081 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4084 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4089 * This routine implements the seemingly endless macro or synthesized
4090 * instructions and addressing modes in the mips assembly language. Many
4091 * of these macros are simple and are similar to each other. These could
4092 * probably be handled by some kind of table or grammar approach instead of
4093 * this verbose method. Others are not simple macros but are more like
4094 * optimizing code generation.
4095 * One interesting optimization is when several store macros appear
4096 * consecutively that would load AT with the upper half of the same address.
4097 * The ensuing load upper instructions are ommited. This implies some kind
4098 * of global optimization. We currently only optimize within a single macro.
4099 * For many of the load and store macros if the address is specified as a
4100 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4101 * first load register 'at' with zero and use it as the base register. The
4102 * mips assembler simply uses register $zero. Just one tiny optimization
4106 macro (struct mips_cl_insn
*ip
)
4108 register int treg
, sreg
, dreg
, breg
;
4124 bfd_reloc_code_real_type r
;
4125 int hold_mips_optimize
;
4127 assert (! mips_opts
.mips16
);
4129 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4130 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4131 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4132 mask
= ip
->insn_mo
->mask
;
4134 expr1
.X_op
= O_constant
;
4135 expr1
.X_op_symbol
= NULL
;
4136 expr1
.X_add_symbol
= NULL
;
4137 expr1
.X_add_number
= 1;
4149 mips_emit_delays (TRUE
);
4150 ++mips_opts
.noreorder
;
4151 mips_any_noreorder
= 1;
4153 expr1
.X_add_number
= 8;
4154 macro_build (&expr1
, "bgez", "s,p", sreg
);
4156 macro_build (NULL
, "nop", "", 0);
4158 move_register (dreg
, sreg
);
4159 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4161 --mips_opts
.noreorder
;
4182 if (imm_expr
.X_op
== O_constant
4183 && imm_expr
.X_add_number
>= -0x8000
4184 && imm_expr
.X_add_number
< 0x8000)
4186 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4190 load_register (AT
, &imm_expr
, dbl
);
4191 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4210 if (imm_expr
.X_op
== O_constant
4211 && imm_expr
.X_add_number
>= 0
4212 && imm_expr
.X_add_number
< 0x10000)
4214 if (mask
!= M_NOR_I
)
4215 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4218 macro_build (&imm_expr
, "ori", "t,r,i",
4219 treg
, sreg
, BFD_RELOC_LO16
);
4220 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4226 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4227 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4244 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4246 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4250 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4251 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4259 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4264 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4268 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4269 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4275 /* check for > max integer */
4276 maxnum
= 0x7fffffff;
4277 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4284 if (imm_expr
.X_op
== O_constant
4285 && imm_expr
.X_add_number
>= maxnum
4286 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4289 /* result is always false */
4291 macro_build (NULL
, "nop", "", 0);
4293 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4296 if (imm_expr
.X_op
!= O_constant
)
4297 as_bad (_("Unsupported large constant"));
4298 ++imm_expr
.X_add_number
;
4302 if (mask
== M_BGEL_I
)
4304 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4306 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4309 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4311 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4314 maxnum
= 0x7fffffff;
4315 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4322 maxnum
= - maxnum
- 1;
4323 if (imm_expr
.X_op
== O_constant
4324 && imm_expr
.X_add_number
<= maxnum
4325 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4328 /* result is always true */
4329 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4330 macro_build (&offset_expr
, "b", "p");
4335 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4345 macro_build (&offset_expr
, likely
? "beql" : "beq",
4350 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4351 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4359 && imm_expr
.X_op
== O_constant
4360 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4362 if (imm_expr
.X_op
!= O_constant
)
4363 as_bad (_("Unsupported large constant"));
4364 ++imm_expr
.X_add_number
;
4368 if (mask
== M_BGEUL_I
)
4370 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4372 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4374 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4380 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4388 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4393 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4397 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4398 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4406 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4413 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4414 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4422 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4427 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4431 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4432 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4438 maxnum
= 0x7fffffff;
4439 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4446 if (imm_expr
.X_op
== O_constant
4447 && imm_expr
.X_add_number
>= maxnum
4448 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4450 if (imm_expr
.X_op
!= O_constant
)
4451 as_bad (_("Unsupported large constant"));
4452 ++imm_expr
.X_add_number
;
4456 if (mask
== M_BLTL_I
)
4458 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4460 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4463 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4465 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4470 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4478 macro_build (&offset_expr
, likely
? "beql" : "beq",
4485 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4486 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4494 && imm_expr
.X_op
== O_constant
4495 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4497 if (imm_expr
.X_op
!= O_constant
)
4498 as_bad (_("Unsupported large constant"));
4499 ++imm_expr
.X_add_number
;
4503 if (mask
== M_BLTUL_I
)
4505 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4507 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4509 macro_build (&offset_expr
, likely
? "beql" : "beq",
4515 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4523 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4528 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4532 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4533 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4543 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4548 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4549 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4557 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4559 as_bad (_("Unsupported large constant"));
4564 pos
= (unsigned long) imm_expr
.X_add_number
;
4565 size
= (unsigned long) imm2_expr
.X_add_number
;
4570 as_bad (_("Improper position (%lu)"), pos
);
4573 if (size
== 0 || size
> 64
4574 || (pos
+ size
- 1) > 63)
4576 as_bad (_("Improper extract size (%lu, position %lu)"),
4581 if (size
<= 32 && pos
< 32)
4586 else if (size
<= 32)
4596 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4605 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4607 as_bad (_("Unsupported large constant"));
4612 pos
= (unsigned long) imm_expr
.X_add_number
;
4613 size
= (unsigned long) imm2_expr
.X_add_number
;
4618 as_bad (_("Improper position (%lu)"), pos
);
4621 if (size
== 0 || size
> 64
4622 || (pos
+ size
- 1) > 63)
4624 as_bad (_("Improper insert size (%lu, position %lu)"),
4629 if (pos
< 32 && (pos
+ size
- 1) < 32)
4644 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4661 as_warn (_("Divide by zero."));
4663 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4665 macro_build (NULL
, "break", "c", 7);
4669 mips_emit_delays (TRUE
);
4670 ++mips_opts
.noreorder
;
4671 mips_any_noreorder
= 1;
4674 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4675 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4679 expr1
.X_add_number
= 8;
4680 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4681 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4682 macro_build (NULL
, "break", "c", 7);
4684 expr1
.X_add_number
= -1;
4686 load_register (AT
, &expr1
, dbl
);
4687 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4688 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4691 expr1
.X_add_number
= 1;
4692 load_register (AT
, &expr1
, dbl
);
4693 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4697 expr1
.X_add_number
= 0x80000000;
4698 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4702 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4703 /* We want to close the noreorder block as soon as possible, so
4704 that later insns are available for delay slot filling. */
4705 --mips_opts
.noreorder
;
4709 expr1
.X_add_number
= 8;
4710 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4711 macro_build (NULL
, "nop", "", 0);
4713 /* We want to close the noreorder block as soon as possible, so
4714 that later insns are available for delay slot filling. */
4715 --mips_opts
.noreorder
;
4717 macro_build (NULL
, "break", "c", 6);
4719 macro_build (NULL
, s
, "d", dreg
);
4758 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4760 as_warn (_("Divide by zero."));
4762 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4764 macro_build (NULL
, "break", "c", 7);
4767 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4769 if (strcmp (s2
, "mflo") == 0)
4770 move_register (dreg
, sreg
);
4772 move_register (dreg
, 0);
4775 if (imm_expr
.X_op
== O_constant
4776 && imm_expr
.X_add_number
== -1
4777 && s
[strlen (s
) - 1] != 'u')
4779 if (strcmp (s2
, "mflo") == 0)
4781 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4784 move_register (dreg
, 0);
4789 load_register (AT
, &imm_expr
, dbl
);
4790 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4791 macro_build (NULL
, s2
, "d", dreg
);
4810 mips_emit_delays (TRUE
);
4811 ++mips_opts
.noreorder
;
4812 mips_any_noreorder
= 1;
4815 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4816 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4817 /* We want to close the noreorder block as soon as possible, so
4818 that later insns are available for delay slot filling. */
4819 --mips_opts
.noreorder
;
4823 expr1
.X_add_number
= 8;
4824 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4825 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4827 /* We want to close the noreorder block as soon as possible, so
4828 that later insns are available for delay slot filling. */
4829 --mips_opts
.noreorder
;
4830 macro_build (NULL
, "break", "c", 7);
4832 macro_build (NULL
, s2
, "d", dreg
);
4844 /* Load the address of a symbol into a register. If breg is not
4845 zero, we then add a base register to it. */
4847 if (dbl
&& HAVE_32BIT_GPRS
)
4848 as_warn (_("dla used to load 32-bit register"));
4850 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4851 as_warn (_("la used to load 64-bit address"));
4853 if (offset_expr
.X_op
== O_constant
4854 && offset_expr
.X_add_number
>= -0x8000
4855 && offset_expr
.X_add_number
< 0x8000)
4857 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4858 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4862 if (!mips_opts
.noat
&& (treg
== breg
))
4872 if (offset_expr
.X_op
!= O_symbol
4873 && offset_expr
.X_op
!= O_constant
)
4875 as_bad (_("expression too complex"));
4876 offset_expr
.X_op
= O_constant
;
4879 if (offset_expr
.X_op
== O_constant
)
4880 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4881 else if (mips_pic
== NO_PIC
)
4883 /* If this is a reference to a GP relative symbol, we want
4884 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4886 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4887 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4888 If we have a constant, we need two instructions anyhow,
4889 so we may as well always use the latter form.
4891 With 64bit address space and a usable $at we want
4892 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4893 lui $at,<sym> (BFD_RELOC_HI16_S)
4894 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4895 daddiu $at,<sym> (BFD_RELOC_LO16)
4897 daddu $tempreg,$tempreg,$at
4899 If $at is already in use, we use a path which is suboptimal
4900 on superscalar processors.
4901 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4902 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4904 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4906 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4908 For GP relative symbols in 64bit address space we can use
4909 the same sequence as in 32bit address space. */
4910 if (HAVE_64BIT_SYMBOLS
)
4912 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4913 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4915 relax_start (offset_expr
.X_add_symbol
);
4916 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4917 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4921 if (used_at
== 0 && !mips_opts
.noat
)
4923 macro_build (&offset_expr
, "lui", "t,u",
4924 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4925 macro_build (&offset_expr
, "lui", "t,u",
4926 AT
, BFD_RELOC_HI16_S
);
4927 macro_build (&offset_expr
, "daddiu", "t,r,j",
4928 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4929 macro_build (&offset_expr
, "daddiu", "t,r,j",
4930 AT
, AT
, BFD_RELOC_LO16
);
4931 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4932 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4937 macro_build (&offset_expr
, "lui", "t,u",
4938 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4939 macro_build (&offset_expr
, "daddiu", "t,r,j",
4940 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4941 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4942 macro_build (&offset_expr
, "daddiu", "t,r,j",
4943 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4944 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4945 macro_build (&offset_expr
, "daddiu", "t,r,j",
4946 tempreg
, tempreg
, BFD_RELOC_LO16
);
4949 if (mips_relax
.sequence
)
4954 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4955 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4957 relax_start (offset_expr
.X_add_symbol
);
4958 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4959 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4962 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
4963 as_bad (_("offset too large"));
4964 macro_build_lui (&offset_expr
, tempreg
);
4965 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4966 tempreg
, tempreg
, BFD_RELOC_LO16
);
4967 if (mips_relax
.sequence
)
4971 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
4973 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4975 /* If this is a reference to an external symbol, and there
4976 is no constant, we want
4977 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4978 or for lca or if tempreg is PIC_CALL_REG
4979 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4980 For a local symbol, we want
4981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4983 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4985 If we have a small constant, and this is a reference to
4986 an external symbol, we want
4987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4989 addiu $tempreg,$tempreg,<constant>
4990 For a local symbol, we want the same instruction
4991 sequence, but we output a BFD_RELOC_LO16 reloc on the
4994 If we have a large constant, and this is a reference to
4995 an external symbol, we want
4996 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4997 lui $at,<hiconstant>
4998 addiu $at,$at,<loconstant>
4999 addu $tempreg,$tempreg,$at
5000 For a local symbol, we want the same instruction
5001 sequence, but we output a BFD_RELOC_LO16 reloc on the
5005 if (offset_expr
.X_add_number
== 0)
5007 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5008 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5010 relax_start (offset_expr
.X_add_symbol
);
5011 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5012 lw_reloc_type
, mips_gp_register
);
5015 /* We're going to put in an addu instruction using
5016 tempreg, so we may as well insert the nop right
5021 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5022 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5024 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5025 tempreg
, tempreg
, BFD_RELOC_LO16
);
5027 /* FIXME: If breg == 0, and the next instruction uses
5028 $tempreg, then if this variant case is used an extra
5029 nop will be generated. */
5031 else if (offset_expr
.X_add_number
>= -0x8000
5032 && offset_expr
.X_add_number
< 0x8000)
5034 load_got_offset (tempreg
, &offset_expr
);
5036 add_got_offset (tempreg
, &offset_expr
);
5040 expr1
.X_add_number
= offset_expr
.X_add_number
;
5041 offset_expr
.X_add_number
=
5042 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5043 load_got_offset (tempreg
, &offset_expr
);
5044 offset_expr
.X_add_number
= expr1
.X_add_number
;
5045 /* If we are going to add in a base register, and the
5046 target register and the base register are the same,
5047 then we are using AT as a temporary register. Since
5048 we want to load the constant into AT, we add our
5049 current AT (from the global offset table) and the
5050 register into the register now, and pretend we were
5051 not using a base register. */
5055 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5060 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5064 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5066 int add_breg_early
= 0;
5068 /* If this is a reference to an external, and there is no
5069 constant, or local symbol (*), with or without a
5071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5072 or for lca or if tempreg is PIC_CALL_REG
5073 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5075 If we have a small constant, and this is a reference to
5076 an external symbol, we want
5077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5078 addiu $tempreg,$tempreg,<constant>
5080 If we have a large constant, and this is a reference to
5081 an external symbol, we want
5082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5083 lui $at,<hiconstant>
5084 addiu $at,$at,<loconstant>
5085 addu $tempreg,$tempreg,$at
5087 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5088 local symbols, even though it introduces an additional
5091 if (offset_expr
.X_add_number
)
5093 expr1
.X_add_number
= offset_expr
.X_add_number
;
5094 offset_expr
.X_add_number
= 0;
5096 relax_start (offset_expr
.X_add_symbol
);
5097 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5098 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5100 if (expr1
.X_add_number
>= -0x8000
5101 && expr1
.X_add_number
< 0x8000)
5103 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5104 tempreg
, tempreg
, BFD_RELOC_LO16
);
5106 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5110 /* If we are going to add in a base register, and the
5111 target register and the base register are the same,
5112 then we are using AT as a temporary register. Since
5113 we want to load the constant into AT, we add our
5114 current AT (from the global offset table) and the
5115 register into the register now, and pretend we were
5116 not using a base register. */
5121 assert (tempreg
== AT
);
5122 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5128 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5129 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5135 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5138 offset_expr
.X_add_number
= expr1
.X_add_number
;
5140 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5141 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5144 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5145 treg
, tempreg
, breg
);
5151 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5153 relax_start (offset_expr
.X_add_symbol
);
5154 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5155 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5157 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5158 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5163 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5164 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5167 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5170 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5171 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5172 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5174 /* This is the large GOT case. If this is a reference to an
5175 external symbol, and there is no constant, we want
5176 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5177 addu $tempreg,$tempreg,$gp
5178 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5179 or for lca or if tempreg is PIC_CALL_REG
5180 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5181 addu $tempreg,$tempreg,$gp
5182 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5183 For a local symbol, we want
5184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5186 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5188 If we have a small constant, and this is a reference to
5189 an external symbol, we want
5190 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5191 addu $tempreg,$tempreg,$gp
5192 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5194 addiu $tempreg,$tempreg,<constant>
5195 For a local symbol, we want
5196 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5198 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5200 If we have a large constant, and this is a reference to
5201 an external symbol, we want
5202 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5203 addu $tempreg,$tempreg,$gp
5204 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5205 lui $at,<hiconstant>
5206 addiu $at,$at,<loconstant>
5207 addu $tempreg,$tempreg,$at
5208 For a local symbol, we want
5209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5210 lui $at,<hiconstant>
5211 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5212 addu $tempreg,$tempreg,$at
5215 expr1
.X_add_number
= offset_expr
.X_add_number
;
5216 offset_expr
.X_add_number
= 0;
5217 relax_start (offset_expr
.X_add_symbol
);
5218 gpdelay
= reg_needs_delay (mips_gp_register
);
5219 if (expr1
.X_add_number
== 0 && breg
== 0
5220 && (call
|| tempreg
== PIC_CALL_REG
))
5222 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5223 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5225 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5226 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5227 tempreg
, tempreg
, mips_gp_register
);
5228 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5229 tempreg
, lw_reloc_type
, tempreg
);
5230 if (expr1
.X_add_number
== 0)
5234 /* We're going to put in an addu instruction using
5235 tempreg, so we may as well insert the nop right
5240 else if (expr1
.X_add_number
>= -0x8000
5241 && expr1
.X_add_number
< 0x8000)
5244 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5245 tempreg
, tempreg
, BFD_RELOC_LO16
);
5251 /* If we are going to add in a base register, and the
5252 target register and the base register are the same,
5253 then we are using AT as a temporary register. Since
5254 we want to load the constant into AT, we add our
5255 current AT (from the global offset table) and the
5256 register into the register now, and pretend we were
5257 not using a base register. */
5262 assert (tempreg
== AT
);
5264 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5269 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5270 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5274 offset_expr
.X_add_number
=
5275 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5280 /* This is needed because this instruction uses $gp, but
5281 the first instruction on the main stream does not. */
5282 macro_build (NULL
, "nop", "");
5285 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5286 local_reloc_type
, mips_gp_register
);
5287 if (expr1
.X_add_number
>= -0x8000
5288 && expr1
.X_add_number
< 0x8000)
5291 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5292 tempreg
, tempreg
, BFD_RELOC_LO16
);
5293 /* FIXME: If add_number is 0, and there was no base
5294 register, the external symbol case ended with a load,
5295 so if the symbol turns out to not be external, and
5296 the next instruction uses tempreg, an unnecessary nop
5297 will be inserted. */
5303 /* We must add in the base register now, as in the
5304 external symbol case. */
5305 assert (tempreg
== AT
);
5307 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5310 /* We set breg to 0 because we have arranged to add
5311 it in in both cases. */
5315 macro_build_lui (&expr1
, AT
);
5316 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5317 AT
, AT
, BFD_RELOC_LO16
);
5318 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5319 tempreg
, tempreg
, AT
);
5324 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5326 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5327 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5328 int add_breg_early
= 0;
5330 /* This is the large GOT case. If this is a reference to an
5331 external symbol, and there is no constant, we want
5332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5333 add $tempreg,$tempreg,$gp
5334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5335 or for lca or if tempreg is PIC_CALL_REG
5336 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5337 add $tempreg,$tempreg,$gp
5338 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5340 If we have a small constant, and this is a reference to
5341 an external symbol, we want
5342 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5343 add $tempreg,$tempreg,$gp
5344 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5345 addi $tempreg,$tempreg,<constant>
5347 If we have a large constant, and this is a reference to
5348 an external symbol, we want
5349 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5350 addu $tempreg,$tempreg,$gp
5351 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5352 lui $at,<hiconstant>
5353 addi $at,$at,<loconstant>
5354 add $tempreg,$tempreg,$at
5356 If we have NewABI, and we know it's a local symbol, we want
5357 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5358 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5359 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5361 relax_start (offset_expr
.X_add_symbol
);
5363 expr1
.X_add_number
= offset_expr
.X_add_number
;
5364 offset_expr
.X_add_number
= 0;
5366 if (expr1
.X_add_number
== 0 && breg
== 0
5367 && (call
|| tempreg
== PIC_CALL_REG
))
5369 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5370 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5372 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5373 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5374 tempreg
, tempreg
, mips_gp_register
);
5375 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5376 tempreg
, lw_reloc_type
, tempreg
);
5378 if (expr1
.X_add_number
== 0)
5380 else if (expr1
.X_add_number
>= -0x8000
5381 && expr1
.X_add_number
< 0x8000)
5383 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5384 tempreg
, tempreg
, BFD_RELOC_LO16
);
5386 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5390 /* If we are going to add in a base register, and the
5391 target register and the base register are the same,
5392 then we are using AT as a temporary register. Since
5393 we want to load the constant into AT, we add our
5394 current AT (from the global offset table) and the
5395 register into the register now, and pretend we were
5396 not using a base register. */
5401 assert (tempreg
== AT
);
5402 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5408 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5414 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5417 offset_expr
.X_add_number
= expr1
.X_add_number
;
5418 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5419 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5420 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5421 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5425 treg
, tempreg
, breg
);
5435 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5439 /* The j instruction may not be used in PIC code, since it
5440 requires an absolute address. We convert it to a b
5442 if (mips_pic
== NO_PIC
)
5443 macro_build (&offset_expr
, "j", "a");
5445 macro_build (&offset_expr
, "b", "p");
5448 /* The jal instructions must be handled as macros because when
5449 generating PIC code they expand to multi-instruction
5450 sequences. Normally they are simple instructions. */
5455 if (mips_pic
== NO_PIC
)
5456 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5457 else if (mips_pic
== SVR4_PIC
)
5459 if (sreg
!= PIC_CALL_REG
)
5460 as_warn (_("MIPS PIC call to register other than $25"));
5462 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5465 if (mips_cprestore_offset
< 0)
5466 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5469 if (! mips_frame_reg_valid
)
5471 as_warn (_("No .frame pseudo-op used in PIC code"));
5472 /* Quiet this warning. */
5473 mips_frame_reg_valid
= 1;
5475 if (! mips_cprestore_valid
)
5477 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5478 /* Quiet this warning. */
5479 mips_cprestore_valid
= 1;
5481 expr1
.X_add_number
= mips_cprestore_offset
;
5482 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5485 HAVE_64BIT_ADDRESSES
);
5495 if (mips_pic
== NO_PIC
)
5496 macro_build (&offset_expr
, "jal", "a");
5497 else if (mips_pic
== SVR4_PIC
)
5499 /* If this is a reference to an external symbol, and we are
5500 using a small GOT, we want
5501 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5505 lw $gp,cprestore($sp)
5506 The cprestore value is set using the .cprestore
5507 pseudo-op. If we are using a big GOT, we want
5508 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5510 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5514 lw $gp,cprestore($sp)
5515 If the symbol is not external, we want
5516 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5518 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5521 lw $gp,cprestore($sp)
5523 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5524 sequences above, minus nops, unless the symbol is local,
5525 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5531 relax_start (offset_expr
.X_add_symbol
);
5532 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5533 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5536 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5537 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5543 relax_start (offset_expr
.X_add_symbol
);
5544 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5545 BFD_RELOC_MIPS_CALL_HI16
);
5546 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5547 PIC_CALL_REG
, mips_gp_register
);
5548 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5549 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5552 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5553 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5555 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5556 PIC_CALL_REG
, PIC_CALL_REG
,
5557 BFD_RELOC_MIPS_GOT_OFST
);
5561 macro_build_jalr (&offset_expr
);
5565 relax_start (offset_expr
.X_add_symbol
);
5568 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5569 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5578 gpdelay
= reg_needs_delay (mips_gp_register
);
5579 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5580 BFD_RELOC_MIPS_CALL_HI16
);
5581 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5582 PIC_CALL_REG
, mips_gp_register
);
5583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5584 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5589 macro_build (NULL
, "nop", "");
5591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5592 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5595 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5596 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5598 macro_build_jalr (&offset_expr
);
5600 if (mips_cprestore_offset
< 0)
5601 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5604 if (! mips_frame_reg_valid
)
5606 as_warn (_("No .frame pseudo-op used in PIC code"));
5607 /* Quiet this warning. */
5608 mips_frame_reg_valid
= 1;
5610 if (! mips_cprestore_valid
)
5612 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5613 /* Quiet this warning. */
5614 mips_cprestore_valid
= 1;
5616 if (mips_opts
.noreorder
)
5617 macro_build (NULL
, "nop", "");
5618 expr1
.X_add_number
= mips_cprestore_offset
;
5619 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5622 HAVE_64BIT_ADDRESSES
);
5648 /* Itbl support may require additional care here. */
5653 /* Itbl support may require additional care here. */
5658 /* Itbl support may require additional care here. */
5663 /* Itbl support may require additional care here. */
5675 if (mips_opts
.arch
== CPU_R4650
)
5677 as_bad (_("opcode not supported on this processor"));
5681 /* Itbl support may require additional care here. */
5686 /* Itbl support may require additional care here. */
5691 /* Itbl support may require additional care here. */
5711 if (breg
== treg
|| coproc
|| lr
)
5732 /* Itbl support may require additional care here. */
5737 /* Itbl support may require additional care here. */
5742 /* Itbl support may require additional care here. */
5747 /* Itbl support may require additional care here. */
5763 if (mips_opts
.arch
== CPU_R4650
)
5765 as_bad (_("opcode not supported on this processor"));
5770 /* Itbl support may require additional care here. */
5774 /* Itbl support may require additional care here. */
5779 /* Itbl support may require additional care here. */
5791 /* Itbl support may require additional care here. */
5792 if (mask
== M_LWC1_AB
5793 || mask
== M_SWC1_AB
5794 || mask
== M_LDC1_AB
5795 || mask
== M_SDC1_AB
5804 if (offset_expr
.X_op
!= O_constant
5805 && offset_expr
.X_op
!= O_symbol
)
5807 as_bad (_("expression too complex"));
5808 offset_expr
.X_op
= O_constant
;
5811 /* A constant expression in PIC code can be handled just as it
5812 is in non PIC code. */
5813 if (offset_expr
.X_op
== O_constant
)
5815 if (HAVE_32BIT_ADDRESSES
5816 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5817 as_bad (_("constant too large"));
5819 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5820 & ~(bfd_vma
) 0xffff);
5821 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5823 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5824 tempreg
, tempreg
, breg
);
5825 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5827 else if (mips_pic
== NO_PIC
)
5829 /* If this is a reference to a GP relative symbol, and there
5830 is no base register, we want
5831 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5832 Otherwise, if there is no base register, we want
5833 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5834 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5835 If we have a constant, we need two instructions anyhow,
5836 so we always use the latter form.
5838 If we have a base register, and this is a reference to a
5839 GP relative symbol, we want
5840 addu $tempreg,$breg,$gp
5841 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5843 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5844 addu $tempreg,$tempreg,$breg
5845 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5846 With a constant we always use the latter case.
5848 With 64bit address space and no base register and $at usable,
5850 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5851 lui $at,<sym> (BFD_RELOC_HI16_S)
5852 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5855 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5856 If we have a base register, we want
5857 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5858 lui $at,<sym> (BFD_RELOC_HI16_S)
5859 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5863 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5865 Without $at we can't generate the optimal path for superscalar
5866 processors here since this would require two temporary registers.
5867 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5868 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5870 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5872 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5873 If we have a base register, we want
5874 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5875 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5877 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5879 daddu $tempreg,$tempreg,$breg
5880 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5882 For GP relative symbols in 64bit address space we can use
5883 the same sequence as in 32bit address space. */
5884 if (HAVE_64BIT_SYMBOLS
)
5886 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5887 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5889 relax_start (offset_expr
.X_add_symbol
);
5892 macro_build (&offset_expr
, s
, fmt
, treg
,
5893 BFD_RELOC_GPREL16
, mips_gp_register
);
5897 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5898 tempreg
, breg
, mips_gp_register
);
5899 macro_build (&offset_expr
, s
, fmt
, treg
,
5900 BFD_RELOC_GPREL16
, tempreg
);
5905 if (used_at
== 0 && !mips_opts
.noat
)
5907 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5908 BFD_RELOC_MIPS_HIGHEST
);
5909 macro_build (&offset_expr
, "lui", "t,u", AT
,
5911 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5912 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5914 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5915 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5916 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5917 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5923 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5924 BFD_RELOC_MIPS_HIGHEST
);
5925 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5926 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5927 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5928 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5929 tempreg
, BFD_RELOC_HI16_S
);
5930 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5932 macro_build (NULL
, "daddu", "d,v,t",
5933 tempreg
, tempreg
, breg
);
5934 macro_build (&offset_expr
, s
, fmt
, treg
,
5935 BFD_RELOC_LO16
, tempreg
);
5938 if (mips_relax
.sequence
)
5945 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5946 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5948 relax_start (offset_expr
.X_add_symbol
);
5949 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
5953 macro_build_lui (&offset_expr
, tempreg
);
5954 macro_build (&offset_expr
, s
, fmt
, treg
,
5955 BFD_RELOC_LO16
, tempreg
);
5956 if (mips_relax
.sequence
)
5961 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5962 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5964 relax_start (offset_expr
.X_add_symbol
);
5965 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5966 tempreg
, breg
, mips_gp_register
);
5967 macro_build (&offset_expr
, s
, fmt
, treg
,
5968 BFD_RELOC_GPREL16
, tempreg
);
5971 macro_build_lui (&offset_expr
, tempreg
);
5972 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5973 tempreg
, tempreg
, breg
);
5974 macro_build (&offset_expr
, s
, fmt
, treg
,
5975 BFD_RELOC_LO16
, tempreg
);
5976 if (mips_relax
.sequence
)
5980 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5982 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5984 /* If this is a reference to an external symbol, we want
5985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5987 <op> $treg,0($tempreg)
5989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5991 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5992 <op> $treg,0($tempreg)
5995 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5996 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
5998 If there is a base register, we add it to $tempreg before
5999 the <op>. If there is a constant, we stick it in the
6000 <op> instruction. We don't handle constants larger than
6001 16 bits, because we have no way to load the upper 16 bits
6002 (actually, we could handle them for the subset of cases
6003 in which we are not using $at). */
6004 assert (offset_expr
.X_op
== O_symbol
);
6007 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6008 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6010 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6011 tempreg
, tempreg
, breg
);
6012 macro_build (&offset_expr
, s
, fmt
, treg
,
6013 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6016 expr1
.X_add_number
= offset_expr
.X_add_number
;
6017 offset_expr
.X_add_number
= 0;
6018 if (expr1
.X_add_number
< -0x8000
6019 || expr1
.X_add_number
>= 0x8000)
6020 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6021 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6022 lw_reloc_type
, mips_gp_register
);
6024 relax_start (offset_expr
.X_add_symbol
);
6026 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6027 tempreg
, BFD_RELOC_LO16
);
6030 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6031 tempreg
, tempreg
, breg
);
6032 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6034 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6038 /* If this is a reference to an external symbol, we want
6039 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6040 addu $tempreg,$tempreg,$gp
6041 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6042 <op> $treg,0($tempreg)
6044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6046 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6047 <op> $treg,0($tempreg)
6048 If there is a base register, we add it to $tempreg before
6049 the <op>. If there is a constant, we stick it in the
6050 <op> instruction. We don't handle constants larger than
6051 16 bits, because we have no way to load the upper 16 bits
6052 (actually, we could handle them for the subset of cases
6053 in which we are not using $at). */
6054 assert (offset_expr
.X_op
== O_symbol
);
6055 expr1
.X_add_number
= offset_expr
.X_add_number
;
6056 offset_expr
.X_add_number
= 0;
6057 if (expr1
.X_add_number
< -0x8000
6058 || expr1
.X_add_number
>= 0x8000)
6059 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6060 gpdelay
= reg_needs_delay (mips_gp_register
);
6061 relax_start (offset_expr
.X_add_symbol
);
6062 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6063 BFD_RELOC_MIPS_GOT_HI16
);
6064 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6066 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6067 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6070 macro_build (NULL
, "nop", "");
6071 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6072 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6074 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6075 tempreg
, BFD_RELOC_LO16
);
6079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6080 tempreg
, tempreg
, breg
);
6081 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6083 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6085 /* If this is a reference to an external symbol, we want
6086 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6087 add $tempreg,$tempreg,$gp
6088 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6089 <op> $treg,<ofst>($tempreg)
6090 Otherwise, for local symbols, we want:
6091 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6092 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6093 assert (offset_expr
.X_op
== O_symbol
);
6094 expr1
.X_add_number
= offset_expr
.X_add_number
;
6095 offset_expr
.X_add_number
= 0;
6096 if (expr1
.X_add_number
< -0x8000
6097 || expr1
.X_add_number
>= 0x8000)
6098 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6099 relax_start (offset_expr
.X_add_symbol
);
6100 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6101 BFD_RELOC_MIPS_GOT_HI16
);
6102 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6104 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6105 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6107 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6108 tempreg
, tempreg
, breg
);
6109 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6112 offset_expr
.X_add_number
= expr1
.X_add_number
;
6113 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6114 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6117 tempreg
, tempreg
, breg
);
6118 macro_build (&offset_expr
, s
, fmt
, treg
,
6119 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6129 load_register (treg
, &imm_expr
, 0);
6133 load_register (treg
, &imm_expr
, 1);
6137 if (imm_expr
.X_op
== O_constant
)
6140 load_register (AT
, &imm_expr
, 0);
6141 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6146 assert (offset_expr
.X_op
== O_symbol
6147 && strcmp (segment_name (S_GET_SEGMENT
6148 (offset_expr
.X_add_symbol
)),
6150 && offset_expr
.X_add_number
== 0);
6151 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6152 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6157 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6158 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6159 order 32 bits of the value and the low order 32 bits are either
6160 zero or in OFFSET_EXPR. */
6161 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6163 if (HAVE_64BIT_GPRS
)
6164 load_register (treg
, &imm_expr
, 1);
6169 if (target_big_endian
)
6181 load_register (hreg
, &imm_expr
, 0);
6184 if (offset_expr
.X_op
== O_absent
)
6185 move_register (lreg
, 0);
6188 assert (offset_expr
.X_op
== O_constant
);
6189 load_register (lreg
, &offset_expr
, 0);
6196 /* We know that sym is in the .rdata section. First we get the
6197 upper 16 bits of the address. */
6198 if (mips_pic
== NO_PIC
)
6200 macro_build_lui (&offset_expr
, AT
);
6203 else if (mips_pic
== SVR4_PIC
)
6205 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6206 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6212 /* Now we load the register(s). */
6213 if (HAVE_64BIT_GPRS
)
6216 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6221 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6224 /* FIXME: How in the world do we deal with the possible
6226 offset_expr
.X_add_number
+= 4;
6227 macro_build (&offset_expr
, "lw", "t,o(b)",
6228 treg
+ 1, BFD_RELOC_LO16
, AT
);
6234 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6235 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6236 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6237 the value and the low order 32 bits are either zero or in
6239 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6242 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6243 if (HAVE_64BIT_FPRS
)
6245 assert (HAVE_64BIT_GPRS
);
6246 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6250 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6251 if (offset_expr
.X_op
== O_absent
)
6252 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6255 assert (offset_expr
.X_op
== O_constant
);
6256 load_register (AT
, &offset_expr
, 0);
6257 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6263 assert (offset_expr
.X_op
== O_symbol
6264 && offset_expr
.X_add_number
== 0);
6265 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6266 if (strcmp (s
, ".lit8") == 0)
6268 if (mips_opts
.isa
!= ISA_MIPS1
)
6270 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6271 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6274 breg
= mips_gp_register
;
6275 r
= BFD_RELOC_MIPS_LITERAL
;
6280 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6282 if (mips_pic
== SVR4_PIC
)
6283 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6284 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6287 /* FIXME: This won't work for a 64 bit address. */
6288 macro_build_lui (&offset_expr
, AT
);
6291 if (mips_opts
.isa
!= ISA_MIPS1
)
6293 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6294 treg
, BFD_RELOC_LO16
, AT
);
6303 if (mips_opts
.arch
== CPU_R4650
)
6305 as_bad (_("opcode not supported on this processor"));
6308 /* Even on a big endian machine $fn comes before $fn+1. We have
6309 to adjust when loading from memory. */
6312 assert (mips_opts
.isa
== ISA_MIPS1
);
6313 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6314 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6315 /* FIXME: A possible overflow which I don't know how to deal
6317 offset_expr
.X_add_number
+= 4;
6318 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6319 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6324 * The MIPS assembler seems to check for X_add_number not
6325 * being double aligned and generating:
6328 * addiu at,at,%lo(foo+1)
6331 * But, the resulting address is the same after relocation so why
6332 * generate the extra instruction?
6334 if (mips_opts
.arch
== CPU_R4650
)
6336 as_bad (_("opcode not supported on this processor"));
6339 /* Itbl support may require additional care here. */
6341 if (mips_opts
.isa
!= ISA_MIPS1
)
6352 if (mips_opts
.arch
== CPU_R4650
)
6354 as_bad (_("opcode not supported on this processor"));
6358 if (mips_opts
.isa
!= ISA_MIPS1
)
6366 /* Itbl support may require additional care here. */
6371 if (HAVE_64BIT_GPRS
)
6382 if (HAVE_64BIT_GPRS
)
6392 if (offset_expr
.X_op
!= O_symbol
6393 && offset_expr
.X_op
!= O_constant
)
6395 as_bad (_("expression too complex"));
6396 offset_expr
.X_op
= O_constant
;
6399 /* Even on a big endian machine $fn comes before $fn+1. We have
6400 to adjust when loading from memory. We set coproc if we must
6401 load $fn+1 first. */
6402 /* Itbl support may require additional care here. */
6403 if (! target_big_endian
)
6406 if (mips_pic
== NO_PIC
6407 || offset_expr
.X_op
== O_constant
)
6409 /* If this is a reference to a GP relative symbol, we want
6410 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6411 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6412 If we have a base register, we use this
6414 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6415 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6416 If this is not a GP relative symbol, we want
6417 lui $at,<sym> (BFD_RELOC_HI16_S)
6418 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6419 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6420 If there is a base register, we add it to $at after the
6421 lui instruction. If there is a constant, we always use
6423 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6424 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6426 relax_start (offset_expr
.X_add_symbol
);
6429 tempreg
= mips_gp_register
;
6433 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6434 AT
, breg
, mips_gp_register
);
6439 /* Itbl support may require additional care here. */
6440 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6441 BFD_RELOC_GPREL16
, tempreg
);
6442 offset_expr
.X_add_number
+= 4;
6444 /* Set mips_optimize to 2 to avoid inserting an
6446 hold_mips_optimize
= mips_optimize
;
6448 /* Itbl support may require additional care here. */
6449 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6450 BFD_RELOC_GPREL16
, tempreg
);
6451 mips_optimize
= hold_mips_optimize
;
6455 /* We just generated two relocs. When tc_gen_reloc
6456 handles this case, it will skip the first reloc and
6457 handle the second. The second reloc already has an
6458 extra addend of 4, which we added above. We must
6459 subtract it out, and then subtract another 4 to make
6460 the first reloc come out right. The second reloc
6461 will come out right because we are going to add 4 to
6462 offset_expr when we build its instruction below.
6464 If we have a symbol, then we don't want to include
6465 the offset, because it will wind up being included
6466 when we generate the reloc. */
6468 if (offset_expr
.X_op
== O_constant
)
6469 offset_expr
.X_add_number
-= 8;
6472 offset_expr
.X_add_number
= -4;
6473 offset_expr
.X_op
= O_constant
;
6477 macro_build_lui (&offset_expr
, AT
);
6479 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6480 /* Itbl support may require additional care here. */
6481 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6482 BFD_RELOC_LO16
, AT
);
6483 /* FIXME: How do we handle overflow here? */
6484 offset_expr
.X_add_number
+= 4;
6485 /* Itbl support may require additional care here. */
6486 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6487 BFD_RELOC_LO16
, AT
);
6488 if (mips_relax
.sequence
)
6491 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6493 /* If this is a reference to an external symbol, we want
6494 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6499 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6501 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6502 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6503 If there is a base register we add it to $at before the
6504 lwc1 instructions. If there is a constant we include it
6505 in the lwc1 instructions. */
6507 expr1
.X_add_number
= offset_expr
.X_add_number
;
6508 if (expr1
.X_add_number
< -0x8000
6509 || expr1
.X_add_number
>= 0x8000 - 4)
6510 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6511 load_got_offset (AT
, &offset_expr
);
6514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6516 /* Set mips_optimize to 2 to avoid inserting an undesired
6518 hold_mips_optimize
= mips_optimize
;
6521 /* Itbl support may require additional care here. */
6522 relax_start (offset_expr
.X_add_symbol
);
6523 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6524 BFD_RELOC_LO16
, AT
);
6525 expr1
.X_add_number
+= 4;
6526 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6527 BFD_RELOC_LO16
, AT
);
6529 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6530 BFD_RELOC_LO16
, AT
);
6531 offset_expr
.X_add_number
+= 4;
6532 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6533 BFD_RELOC_LO16
, AT
);
6536 mips_optimize
= hold_mips_optimize
;
6538 else if (mips_pic
== SVR4_PIC
)
6542 /* If this is a reference to an external symbol, we want
6543 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6545 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6550 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6552 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6553 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6554 If there is a base register we add it to $at before the
6555 lwc1 instructions. If there is a constant we include it
6556 in the lwc1 instructions. */
6558 expr1
.X_add_number
= offset_expr
.X_add_number
;
6559 offset_expr
.X_add_number
= 0;
6560 if (expr1
.X_add_number
< -0x8000
6561 || expr1
.X_add_number
>= 0x8000 - 4)
6562 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6563 gpdelay
= reg_needs_delay (mips_gp_register
);
6564 relax_start (offset_expr
.X_add_symbol
);
6565 macro_build (&offset_expr
, "lui", "t,u",
6566 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6567 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6568 AT
, AT
, mips_gp_register
);
6569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6570 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6573 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6574 /* Itbl support may require additional care here. */
6575 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6576 BFD_RELOC_LO16
, AT
);
6577 expr1
.X_add_number
+= 4;
6579 /* Set mips_optimize to 2 to avoid inserting an undesired
6581 hold_mips_optimize
= mips_optimize
;
6583 /* Itbl support may require additional care here. */
6584 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6585 BFD_RELOC_LO16
, AT
);
6586 mips_optimize
= hold_mips_optimize
;
6587 expr1
.X_add_number
-= 4;
6590 offset_expr
.X_add_number
= expr1
.X_add_number
;
6592 macro_build (NULL
, "nop", "");
6593 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6594 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6597 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6598 /* Itbl support may require additional care here. */
6599 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6600 BFD_RELOC_LO16
, AT
);
6601 offset_expr
.X_add_number
+= 4;
6603 /* Set mips_optimize to 2 to avoid inserting an undesired
6605 hold_mips_optimize
= mips_optimize
;
6607 /* Itbl support may require additional care here. */
6608 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6609 BFD_RELOC_LO16
, AT
);
6610 mips_optimize
= hold_mips_optimize
;
6624 assert (HAVE_32BIT_ADDRESSES
);
6625 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6626 offset_expr
.X_add_number
+= 4;
6627 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6630 /* New code added to support COPZ instructions.
6631 This code builds table entries out of the macros in mip_opcodes.
6632 R4000 uses interlocks to handle coproc delays.
6633 Other chips (like the R3000) require nops to be inserted for delays.
6635 FIXME: Currently, we require that the user handle delays.
6636 In order to fill delay slots for non-interlocked chips,
6637 we must have a way to specify delays based on the coprocessor.
6638 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6639 What are the side-effects of the cop instruction?
6640 What cache support might we have and what are its effects?
6641 Both coprocessor & memory require delays. how long???
6642 What registers are read/set/modified?
6644 If an itbl is provided to interpret cop instructions,
6645 this knowledge can be encoded in the itbl spec. */
6659 /* For now we just do C (same as Cz). The parameter will be
6660 stored in insn_opcode by mips_ip. */
6661 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6665 move_register (dreg
, sreg
);
6668 #ifdef LOSING_COMPILER
6670 /* Try and see if this is a new itbl instruction.
6671 This code builds table entries out of the macros in mip_opcodes.
6672 FIXME: For now we just assemble the expression and pass it's
6673 value along as a 32-bit immediate.
6674 We may want to have the assembler assemble this value,
6675 so that we gain the assembler's knowledge of delay slots,
6677 Would it be more efficient to use mask (id) here? */
6678 if (itbl_have_entries
6679 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6681 s
= ip
->insn_mo
->name
;
6683 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6684 macro_build (&immed_expr
, s
, "C");
6690 if (mips_opts
.noat
&& used_at
)
6691 as_bad (_("Macro used $at after \".set noat\""));
6695 macro2 (struct mips_cl_insn
*ip
)
6697 register int treg
, sreg
, dreg
, breg
;
6712 bfd_reloc_code_real_type r
;
6714 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6715 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6716 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6717 mask
= ip
->insn_mo
->mask
;
6719 expr1
.X_op
= O_constant
;
6720 expr1
.X_op_symbol
= NULL
;
6721 expr1
.X_add_symbol
= NULL
;
6722 expr1
.X_add_number
= 1;
6726 #endif /* LOSING_COMPILER */
6731 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6732 macro_build (NULL
, "mflo", "d", dreg
);
6738 /* The MIPS assembler some times generates shifts and adds. I'm
6739 not trying to be that fancy. GCC should do this for us
6742 load_register (AT
, &imm_expr
, dbl
);
6743 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6744 macro_build (NULL
, "mflo", "d", dreg
);
6757 mips_emit_delays (TRUE
);
6758 ++mips_opts
.noreorder
;
6759 mips_any_noreorder
= 1;
6762 load_register (AT
, &imm_expr
, dbl
);
6763 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6764 macro_build (NULL
, "mflo", "d", dreg
);
6765 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6766 macro_build (NULL
, "mfhi", "d", AT
);
6768 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6771 expr1
.X_add_number
= 8;
6772 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6773 macro_build (NULL
, "nop", "", 0);
6774 macro_build (NULL
, "break", "c", 6);
6776 --mips_opts
.noreorder
;
6777 macro_build (NULL
, "mflo", "d", dreg
);
6790 mips_emit_delays (TRUE
);
6791 ++mips_opts
.noreorder
;
6792 mips_any_noreorder
= 1;
6795 load_register (AT
, &imm_expr
, dbl
);
6796 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6797 sreg
, imm
? AT
: treg
);
6798 macro_build (NULL
, "mfhi", "d", AT
);
6799 macro_build (NULL
, "mflo", "d", dreg
);
6801 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6804 expr1
.X_add_number
= 8;
6805 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6806 macro_build (NULL
, "nop", "", 0);
6807 macro_build (NULL
, "break", "c", 6);
6809 --mips_opts
.noreorder
;
6813 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6824 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6825 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6829 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6830 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6831 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6832 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6836 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6847 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6848 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6852 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6853 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6854 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6855 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6863 if (imm_expr
.X_op
!= O_constant
)
6864 as_bad (_("Improper rotate count"));
6865 rot
= imm_expr
.X_add_number
& 0x3f;
6866 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6868 rot
= (64 - rot
) & 0x3f;
6870 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6872 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6877 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6880 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6881 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6884 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6885 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6886 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6894 if (imm_expr
.X_op
!= O_constant
)
6895 as_bad (_("Improper rotate count"));
6896 rot
= imm_expr
.X_add_number
& 0x1f;
6897 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6899 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6904 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6908 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6909 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6910 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6915 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6917 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6921 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6922 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6923 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6924 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6928 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6930 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
6934 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6935 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6936 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
6937 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6945 if (imm_expr
.X_op
!= O_constant
)
6946 as_bad (_("Improper rotate count"));
6947 rot
= imm_expr
.X_add_number
& 0x3f;
6948 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6951 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6953 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6958 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6961 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
6962 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
6965 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
6966 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6967 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6975 if (imm_expr
.X_op
!= O_constant
)
6976 as_bad (_("Improper rotate count"));
6977 rot
= imm_expr
.X_add_number
& 0x1f;
6978 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6980 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
6985 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6989 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
6990 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6991 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6996 if (mips_opts
.arch
== CPU_R4650
)
6998 as_bad (_("opcode not supported on this processor"));
7001 assert (mips_opts
.isa
== ISA_MIPS1
);
7002 /* Even on a big endian machine $fn comes before $fn+1. We have
7003 to adjust when storing to memory. */
7004 macro_build (&offset_expr
, "swc1", "T,o(b)",
7005 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7006 offset_expr
.X_add_number
+= 4;
7007 macro_build (&offset_expr
, "swc1", "T,o(b)",
7008 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7013 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7015 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7018 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7019 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7024 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7026 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7031 as_warn (_("Instruction %s: result is always false"),
7033 move_register (dreg
, 0);
7036 if (imm_expr
.X_op
== O_constant
7037 && imm_expr
.X_add_number
>= 0
7038 && imm_expr
.X_add_number
< 0x10000)
7040 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7042 else if (imm_expr
.X_op
== O_constant
7043 && imm_expr
.X_add_number
> -0x8000
7044 && imm_expr
.X_add_number
< 0)
7046 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7047 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7048 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7052 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7053 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7056 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7059 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7065 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7066 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7069 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7071 if (imm_expr
.X_op
== O_constant
7072 && imm_expr
.X_add_number
>= -0x8000
7073 && imm_expr
.X_add_number
< 0x8000)
7075 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7076 dreg
, sreg
, BFD_RELOC_LO16
);
7080 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7081 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7085 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7088 case M_SGT
: /* sreg > treg <==> treg < sreg */
7094 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7097 case M_SGT_I
: /* sreg > I <==> I < sreg */
7104 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7105 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7108 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7114 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7115 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7118 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7125 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7126 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7127 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7131 if (imm_expr
.X_op
== O_constant
7132 && imm_expr
.X_add_number
>= -0x8000
7133 && imm_expr
.X_add_number
< 0x8000)
7135 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7139 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7140 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7144 if (imm_expr
.X_op
== O_constant
7145 && imm_expr
.X_add_number
>= -0x8000
7146 && imm_expr
.X_add_number
< 0x8000)
7148 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7153 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7154 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7159 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7161 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7164 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7165 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7170 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7172 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7177 as_warn (_("Instruction %s: result is always true"),
7179 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7180 dreg
, 0, BFD_RELOC_LO16
);
7183 if (imm_expr
.X_op
== O_constant
7184 && imm_expr
.X_add_number
>= 0
7185 && imm_expr
.X_add_number
< 0x10000)
7187 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7189 else if (imm_expr
.X_op
== O_constant
7190 && imm_expr
.X_add_number
> -0x8000
7191 && imm_expr
.X_add_number
< 0)
7193 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7194 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7195 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7199 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7200 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7203 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7209 if (imm_expr
.X_op
== O_constant
7210 && imm_expr
.X_add_number
> -0x8000
7211 && imm_expr
.X_add_number
<= 0x8000)
7213 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7214 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7215 dreg
, sreg
, BFD_RELOC_LO16
);
7219 load_register (AT
, &imm_expr
, dbl
);
7220 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7226 if (imm_expr
.X_op
== O_constant
7227 && imm_expr
.X_add_number
> -0x8000
7228 && imm_expr
.X_add_number
<= 0x8000)
7230 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7231 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7232 dreg
, sreg
, BFD_RELOC_LO16
);
7236 load_register (AT
, &imm_expr
, dbl
);
7237 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7259 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7260 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7265 assert (mips_opts
.isa
== ISA_MIPS1
);
7267 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7268 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7271 * Is the double cfc1 instruction a bug in the mips assembler;
7272 * or is there a reason for it?
7274 mips_emit_delays (TRUE
);
7275 ++mips_opts
.noreorder
;
7276 mips_any_noreorder
= 1;
7277 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7278 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7279 macro_build (NULL
, "nop", "");
7280 expr1
.X_add_number
= 3;
7281 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7282 expr1
.X_add_number
= 2;
7283 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7284 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7285 macro_build (NULL
, "nop", "");
7286 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7288 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7289 macro_build (NULL
, "nop", "");
7290 --mips_opts
.noreorder
;
7300 if (offset_expr
.X_add_number
>= 0x7fff)
7301 as_bad (_("operand overflow"));
7302 if (! target_big_endian
)
7303 ++offset_expr
.X_add_number
;
7304 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7305 if (! target_big_endian
)
7306 --offset_expr
.X_add_number
;
7308 ++offset_expr
.X_add_number
;
7309 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7310 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7311 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7324 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7325 as_bad (_("operand overflow"));
7333 if (! target_big_endian
)
7334 offset_expr
.X_add_number
+= off
;
7335 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7336 if (! target_big_endian
)
7337 offset_expr
.X_add_number
-= off
;
7339 offset_expr
.X_add_number
+= off
;
7340 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7342 /* If necessary, move the result in tempreg the final destination. */
7343 if (treg
== tempreg
)
7345 /* Protect second load's delay slot. */
7347 move_register (treg
, tempreg
);
7361 load_address (AT
, &offset_expr
, &used_at
);
7363 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7364 if (! target_big_endian
)
7365 expr1
.X_add_number
= off
;
7367 expr1
.X_add_number
= 0;
7368 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7369 if (! target_big_endian
)
7370 expr1
.X_add_number
= 0;
7372 expr1
.X_add_number
= off
;
7373 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7379 load_address (AT
, &offset_expr
, &used_at
);
7381 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7382 if (target_big_endian
)
7383 expr1
.X_add_number
= 0;
7384 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7385 treg
, BFD_RELOC_LO16
, AT
);
7386 if (target_big_endian
)
7387 expr1
.X_add_number
= 1;
7389 expr1
.X_add_number
= 0;
7390 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7391 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7392 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7397 if (offset_expr
.X_add_number
>= 0x7fff)
7398 as_bad (_("operand overflow"));
7399 if (target_big_endian
)
7400 ++offset_expr
.X_add_number
;
7401 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7402 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7403 if (target_big_endian
)
7404 --offset_expr
.X_add_number
;
7406 ++offset_expr
.X_add_number
;
7407 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7420 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7421 as_bad (_("operand overflow"));
7422 if (! target_big_endian
)
7423 offset_expr
.X_add_number
+= off
;
7424 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7425 if (! target_big_endian
)
7426 offset_expr
.X_add_number
-= off
;
7428 offset_expr
.X_add_number
+= off
;
7429 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7443 load_address (AT
, &offset_expr
, &used_at
);
7445 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7446 if (! target_big_endian
)
7447 expr1
.X_add_number
= off
;
7449 expr1
.X_add_number
= 0;
7450 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7451 if (! target_big_endian
)
7452 expr1
.X_add_number
= 0;
7454 expr1
.X_add_number
= off
;
7455 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7460 load_address (AT
, &offset_expr
, &used_at
);
7462 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7463 if (! target_big_endian
)
7464 expr1
.X_add_number
= 0;
7465 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7466 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7467 if (! target_big_endian
)
7468 expr1
.X_add_number
= 1;
7470 expr1
.X_add_number
= 0;
7471 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7472 if (! target_big_endian
)
7473 expr1
.X_add_number
= 0;
7475 expr1
.X_add_number
= 1;
7476 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7477 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7478 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7482 /* FIXME: Check if this is one of the itbl macros, since they
7483 are added dynamically. */
7484 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7487 if (mips_opts
.noat
&& used_at
)
7488 as_bad (_("Macro used $at after \".set noat\""));
7491 /* Implement macros in mips16 mode. */
7494 mips16_macro (struct mips_cl_insn
*ip
)
7497 int xreg
, yreg
, zreg
, tmp
;
7500 const char *s
, *s2
, *s3
;
7502 mask
= ip
->insn_mo
->mask
;
7504 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7505 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7506 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7508 expr1
.X_op
= O_constant
;
7509 expr1
.X_op_symbol
= NULL
;
7510 expr1
.X_add_symbol
= NULL
;
7511 expr1
.X_add_number
= 1;
7530 mips_emit_delays (TRUE
);
7531 ++mips_opts
.noreorder
;
7532 mips_any_noreorder
= 1;
7533 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7534 expr1
.X_add_number
= 2;
7535 macro_build (&expr1
, "bnez", "x,p", yreg
);
7536 macro_build (NULL
, "break", "6", 7);
7538 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7539 since that causes an overflow. We should do that as well,
7540 but I don't see how to do the comparisons without a temporary
7542 --mips_opts
.noreorder
;
7543 macro_build (NULL
, s
, "x", zreg
);
7562 mips_emit_delays (TRUE
);
7563 ++mips_opts
.noreorder
;
7564 mips_any_noreorder
= 1;
7565 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7566 expr1
.X_add_number
= 2;
7567 macro_build (&expr1
, "bnez", "x,p", yreg
);
7568 macro_build (NULL
, "break", "6", 7);
7569 --mips_opts
.noreorder
;
7570 macro_build (NULL
, s2
, "x", zreg
);
7576 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7577 macro_build (NULL
, "mflo", "x", zreg
);
7585 if (imm_expr
.X_op
!= O_constant
)
7586 as_bad (_("Unsupported large constant"));
7587 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7588 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7592 if (imm_expr
.X_op
!= O_constant
)
7593 as_bad (_("Unsupported large constant"));
7594 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7595 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7599 if (imm_expr
.X_op
!= O_constant
)
7600 as_bad (_("Unsupported large constant"));
7601 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7602 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7624 goto do_reverse_branch
;
7628 goto do_reverse_branch
;
7640 goto do_reverse_branch
;
7651 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7652 macro_build (&offset_expr
, s2
, "p");
7679 goto do_addone_branch_i
;
7684 goto do_addone_branch_i
;
7699 goto do_addone_branch_i
;
7706 if (imm_expr
.X_op
!= O_constant
)
7707 as_bad (_("Unsupported large constant"));
7708 ++imm_expr
.X_add_number
;
7711 macro_build (&imm_expr
, s
, s3
, xreg
);
7712 macro_build (&offset_expr
, s2
, "p");
7716 expr1
.X_add_number
= 0;
7717 macro_build (&expr1
, "slti", "x,8", yreg
);
7719 move_register (xreg
, yreg
);
7720 expr1
.X_add_number
= 2;
7721 macro_build (&expr1
, "bteqz", "p");
7722 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7726 /* For consistency checking, verify that all bits are specified either
7727 by the match/mask part of the instruction definition, or by the
7730 validate_mips_insn (const struct mips_opcode
*opc
)
7732 const char *p
= opc
->args
;
7734 unsigned long used_bits
= opc
->mask
;
7736 if ((used_bits
& opc
->match
) != opc
->match
)
7738 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7739 opc
->name
, opc
->args
);
7742 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7752 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7753 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7754 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7755 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7756 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7757 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7758 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7759 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7760 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7763 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7764 c
, opc
->name
, opc
->args
);
7768 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7769 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7771 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7772 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7773 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7774 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7776 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7777 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7779 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7780 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7782 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7783 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7784 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7785 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7786 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7787 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7788 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7789 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7790 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7791 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7792 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7793 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7794 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7795 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7796 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7797 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7798 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7800 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7801 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7802 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7803 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7805 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7806 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7807 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7808 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7809 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7810 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7811 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7812 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7813 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7816 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7817 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7818 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7819 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7820 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7824 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7825 c
, opc
->name
, opc
->args
);
7829 if (used_bits
!= 0xffffffff)
7831 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7832 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7838 /* This routine assembles an instruction into its binary format. As a
7839 side effect, it sets one of the global variables imm_reloc or
7840 offset_reloc to the type of relocation to do if one of the operands
7841 is an address expression. */
7844 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7849 struct mips_opcode
*insn
;
7852 unsigned int lastregno
= 0;
7853 unsigned int lastpos
= 0;
7854 unsigned int limlo
, limhi
;
7860 /* If the instruction contains a '.', we first try to match an instruction
7861 including the '.'. Then we try again without the '.'. */
7863 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7866 /* If we stopped on whitespace, then replace the whitespace with null for
7867 the call to hash_find. Save the character we replaced just in case we
7868 have to re-parse the instruction. */
7875 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7877 /* If we didn't find the instruction in the opcode table, try again, but
7878 this time with just the instruction up to, but not including the
7882 /* Restore the character we overwrite above (if any). */
7886 /* Scan up to the first '.' or whitespace. */
7888 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7892 /* If we did not find a '.', then we can quit now. */
7895 insn_error
= "unrecognized opcode";
7899 /* Lookup the instruction in the hash table. */
7901 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7903 insn_error
= "unrecognized opcode";
7913 assert (strcmp (insn
->name
, str
) == 0);
7915 if (OPCODE_IS_MEMBER (insn
,
7917 | (file_ase_mips16
? INSN_MIPS16
: 0)
7918 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7919 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7925 if (insn
->pinfo
!= INSN_MACRO
)
7927 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7933 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7934 && strcmp (insn
->name
, insn
[1].name
) == 0)
7943 static char buf
[100];
7945 _("opcode not supported on this processor: %s (%s)"),
7946 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
7947 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
7956 create_insn (ip
, insn
);
7958 for (args
= insn
->args
;; ++args
)
7962 s
+= strspn (s
, " \t");
7966 case '\0': /* end of args */
7979 INSERT_OPERAND (RS
, *ip
, lastregno
);
7983 INSERT_OPERAND (RT
, *ip
, lastregno
);
7987 INSERT_OPERAND (FT
, *ip
, lastregno
);
7991 INSERT_OPERAND (FS
, *ip
, lastregno
);
7997 /* Handle optional base register.
7998 Either the base register is omitted or
7999 we must have a left paren. */
8000 /* This is dependent on the next operand specifier
8001 is a base register specification. */
8002 assert (args
[1] == 'b' || args
[1] == '5'
8003 || args
[1] == '-' || args
[1] == '4');
8007 case ')': /* these must match exactly */
8014 case '+': /* Opcode extension character. */
8017 case 'A': /* ins/ext position, becomes LSB. */
8026 my_getExpression (&imm_expr
, s
);
8027 check_absolute_expr (ip
, &imm_expr
);
8028 if ((unsigned long) imm_expr
.X_add_number
< limlo
8029 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8031 as_bad (_("Improper position (%lu)"),
8032 (unsigned long) imm_expr
.X_add_number
);
8033 imm_expr
.X_add_number
= limlo
;
8035 lastpos
= imm_expr
.X_add_number
;
8036 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8037 imm_expr
.X_op
= O_absent
;
8041 case 'B': /* ins size, becomes MSB. */
8050 my_getExpression (&imm_expr
, s
);
8051 check_absolute_expr (ip
, &imm_expr
);
8052 /* Check for negative input so that small negative numbers
8053 will not succeed incorrectly. The checks against
8054 (pos+size) transitively check "size" itself,
8055 assuming that "pos" is reasonable. */
8056 if ((long) imm_expr
.X_add_number
< 0
8057 || ((unsigned long) imm_expr
.X_add_number
8059 || ((unsigned long) imm_expr
.X_add_number
8062 as_bad (_("Improper insert size (%lu, position %lu)"),
8063 (unsigned long) imm_expr
.X_add_number
,
8064 (unsigned long) lastpos
);
8065 imm_expr
.X_add_number
= limlo
- lastpos
;
8067 INSERT_OPERAND (INSMSB
, *ip
,
8068 lastpos
+ imm_expr
.X_add_number
- 1);
8069 imm_expr
.X_op
= O_absent
;
8073 case 'C': /* ext size, becomes MSBD. */
8086 my_getExpression (&imm_expr
, s
);
8087 check_absolute_expr (ip
, &imm_expr
);
8088 /* Check for negative input so that small negative numbers
8089 will not succeed incorrectly. The checks against
8090 (pos+size) transitively check "size" itself,
8091 assuming that "pos" is reasonable. */
8092 if ((long) imm_expr
.X_add_number
< 0
8093 || ((unsigned long) imm_expr
.X_add_number
8095 || ((unsigned long) imm_expr
.X_add_number
8098 as_bad (_("Improper extract size (%lu, position %lu)"),
8099 (unsigned long) imm_expr
.X_add_number
,
8100 (unsigned long) lastpos
);
8101 imm_expr
.X_add_number
= limlo
- lastpos
;
8103 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8104 imm_expr
.X_op
= O_absent
;
8109 /* +D is for disassembly only; never match. */
8113 /* "+I" is like "I", except that imm2_expr is used. */
8114 my_getExpression (&imm2_expr
, s
);
8115 if (imm2_expr
.X_op
!= O_big
8116 && imm2_expr
.X_op
!= O_constant
)
8117 insn_error
= _("absolute expression required");
8118 normalize_constant_expr (&imm2_expr
);
8123 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8124 *args
, insn
->name
, insn
->args
);
8125 /* Further processing is fruitless. */
8130 case '<': /* must be at least one digit */
8132 * According to the manual, if the shift amount is greater
8133 * than 31 or less than 0, then the shift amount should be
8134 * mod 32. In reality the mips assembler issues an error.
8135 * We issue a warning and mask out all but the low 5 bits.
8137 my_getExpression (&imm_expr
, s
);
8138 check_absolute_expr (ip
, &imm_expr
);
8139 if ((unsigned long) imm_expr
.X_add_number
> 31)
8140 as_warn (_("Improper shift amount (%lu)"),
8141 (unsigned long) imm_expr
.X_add_number
);
8142 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8143 imm_expr
.X_op
= O_absent
;
8147 case '>': /* shift amount minus 32 */
8148 my_getExpression (&imm_expr
, s
);
8149 check_absolute_expr (ip
, &imm_expr
);
8150 if ((unsigned long) imm_expr
.X_add_number
< 32
8151 || (unsigned long) imm_expr
.X_add_number
> 63)
8153 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8154 imm_expr
.X_op
= O_absent
;
8158 case 'k': /* cache code */
8159 case 'h': /* prefx code */
8160 my_getExpression (&imm_expr
, s
);
8161 check_absolute_expr (ip
, &imm_expr
);
8162 if ((unsigned long) imm_expr
.X_add_number
> 31)
8163 as_warn (_("Invalid value for `%s' (%lu)"),
8165 (unsigned long) imm_expr
.X_add_number
);
8167 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8169 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8170 imm_expr
.X_op
= O_absent
;
8174 case 'c': /* break code */
8175 my_getExpression (&imm_expr
, s
);
8176 check_absolute_expr (ip
, &imm_expr
);
8177 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8178 as_warn (_("Illegal break code (%lu)"),
8179 (unsigned long) imm_expr
.X_add_number
);
8180 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8181 imm_expr
.X_op
= O_absent
;
8185 case 'q': /* lower break code */
8186 my_getExpression (&imm_expr
, s
);
8187 check_absolute_expr (ip
, &imm_expr
);
8188 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8189 as_warn (_("Illegal lower break code (%lu)"),
8190 (unsigned long) imm_expr
.X_add_number
);
8191 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8192 imm_expr
.X_op
= O_absent
;
8196 case 'B': /* 20-bit syscall/break code. */
8197 my_getExpression (&imm_expr
, s
);
8198 check_absolute_expr (ip
, &imm_expr
);
8199 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8200 as_warn (_("Illegal 20-bit code (%lu)"),
8201 (unsigned long) imm_expr
.X_add_number
);
8202 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8203 imm_expr
.X_op
= O_absent
;
8207 case 'C': /* Coprocessor code */
8208 my_getExpression (&imm_expr
, s
);
8209 check_absolute_expr (ip
, &imm_expr
);
8210 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8212 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8213 (unsigned long) imm_expr
.X_add_number
);
8214 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8216 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8217 imm_expr
.X_op
= O_absent
;
8221 case 'J': /* 19-bit wait code. */
8222 my_getExpression (&imm_expr
, s
);
8223 check_absolute_expr (ip
, &imm_expr
);
8224 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8225 as_warn (_("Illegal 19-bit code (%lu)"),
8226 (unsigned long) imm_expr
.X_add_number
);
8227 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8228 imm_expr
.X_op
= O_absent
;
8232 case 'P': /* Performance register */
8233 my_getExpression (&imm_expr
, s
);
8234 check_absolute_expr (ip
, &imm_expr
);
8235 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8236 as_warn (_("Invalid performance register (%lu)"),
8237 (unsigned long) imm_expr
.X_add_number
);
8238 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8239 imm_expr
.X_op
= O_absent
;
8243 case 'b': /* base register */
8244 case 'd': /* destination register */
8245 case 's': /* source register */
8246 case 't': /* target register */
8247 case 'r': /* both target and source */
8248 case 'v': /* both dest and source */
8249 case 'w': /* both dest and target */
8250 case 'E': /* coprocessor target register */
8251 case 'G': /* coprocessor destination register */
8252 case 'K': /* 'rdhwr' destination register */
8253 case 'x': /* ignore register name */
8254 case 'z': /* must be zero register */
8255 case 'U': /* destination register (clo/clz). */
8270 while (ISDIGIT (*s
));
8272 as_bad (_("Invalid register number (%d)"), regno
);
8274 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8278 if (s
[1] == 'r' && s
[2] == 'a')
8283 else if (s
[1] == 'f' && s
[2] == 'p')
8288 else if (s
[1] == 's' && s
[2] == 'p')
8293 else if (s
[1] == 'g' && s
[2] == 'p')
8298 else if (s
[1] == 'a' && s
[2] == 't')
8303 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8308 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8313 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8318 else if (itbl_have_entries
)
8323 p
= s
+ 1; /* advance past '$' */
8324 n
= itbl_get_field (&p
); /* n is name */
8326 /* See if this is a register defined in an
8328 if (itbl_get_reg_val (n
, &r
))
8330 /* Get_field advances to the start of
8331 the next field, so we need to back
8332 rack to the end of the last field. */
8336 s
= strchr (s
, '\0');
8350 as_warn (_("Used $at without \".set noat\""));
8356 if (c
== 'r' || c
== 'v' || c
== 'w')
8363 /* 'z' only matches $0. */
8364 if (c
== 'z' && regno
!= 0)
8367 /* Now that we have assembled one operand, we use the args string
8368 * to figure out where it goes in the instruction. */
8375 INSERT_OPERAND (RS
, *ip
, regno
);
8380 INSERT_OPERAND (RD
, *ip
, regno
);
8383 INSERT_OPERAND (RD
, *ip
, regno
);
8384 INSERT_OPERAND (RT
, *ip
, regno
);
8389 INSERT_OPERAND (RT
, *ip
, regno
);
8392 /* This case exists because on the r3000 trunc
8393 expands into a macro which requires a gp
8394 register. On the r6000 or r4000 it is
8395 assembled into a single instruction which
8396 ignores the register. Thus the insn version
8397 is MIPS_ISA2 and uses 'x', and the macro
8398 version is MIPS_ISA1 and uses 't'. */
8401 /* This case is for the div instruction, which
8402 acts differently if the destination argument
8403 is $0. This only matches $0, and is checked
8404 outside the switch. */
8407 /* Itbl operand; not yet implemented. FIXME ?? */
8409 /* What about all other operands like 'i', which
8410 can be specified in the opcode table? */
8420 INSERT_OPERAND (RS
, *ip
, lastregno
);
8423 INSERT_OPERAND (RT
, *ip
, lastregno
);
8428 case 'O': /* MDMX alignment immediate constant. */
8429 my_getExpression (&imm_expr
, s
);
8430 check_absolute_expr (ip
, &imm_expr
);
8431 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8432 as_warn ("Improper align amount (%ld), using low bits",
8433 (long) imm_expr
.X_add_number
);
8434 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8435 imm_expr
.X_op
= O_absent
;
8439 case 'Q': /* MDMX vector, element sel, or const. */
8442 /* MDMX Immediate. */
8443 my_getExpression (&imm_expr
, s
);
8444 check_absolute_expr (ip
, &imm_expr
);
8445 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8446 as_warn (_("Invalid MDMX Immediate (%ld)"),
8447 (long) imm_expr
.X_add_number
);
8448 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8449 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8450 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8452 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8453 imm_expr
.X_op
= O_absent
;
8457 /* Not MDMX Immediate. Fall through. */
8458 case 'X': /* MDMX destination register. */
8459 case 'Y': /* MDMX source register. */
8460 case 'Z': /* MDMX target register. */
8462 case 'D': /* floating point destination register */
8463 case 'S': /* floating point source register */
8464 case 'T': /* floating point target register */
8465 case 'R': /* floating point source register */
8469 /* Accept $fN for FP and MDMX register numbers, and in
8470 addition accept $vN for MDMX register numbers. */
8471 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8472 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8483 while (ISDIGIT (*s
));
8486 as_bad (_("Invalid float register number (%d)"), regno
);
8488 if ((regno
& 1) != 0
8490 && ! (strcmp (str
, "mtc1") == 0
8491 || strcmp (str
, "mfc1") == 0
8492 || strcmp (str
, "lwc1") == 0
8493 || strcmp (str
, "swc1") == 0
8494 || strcmp (str
, "l.s") == 0
8495 || strcmp (str
, "s.s") == 0))
8496 as_warn (_("Float register should be even, was %d"),
8504 if (c
== 'V' || c
== 'W')
8515 INSERT_OPERAND (FD
, *ip
, regno
);
8520 INSERT_OPERAND (FS
, *ip
, regno
);
8523 /* This is like 'Z', but also needs to fix the MDMX
8524 vector/scalar select bits. Note that the
8525 scalar immediate case is handled above. */
8528 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8529 int max_el
= (is_qh
? 3 : 7);
8531 my_getExpression(&imm_expr
, s
);
8532 check_absolute_expr (ip
, &imm_expr
);
8534 if (imm_expr
.X_add_number
> max_el
)
8535 as_bad(_("Bad element selector %ld"),
8536 (long) imm_expr
.X_add_number
);
8537 imm_expr
.X_add_number
&= max_el
;
8538 ip
->insn_opcode
|= (imm_expr
.X_add_number
8541 imm_expr
.X_op
= O_absent
;
8543 as_warn(_("Expecting ']' found '%s'"), s
);
8549 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8550 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8553 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8560 INSERT_OPERAND (FT
, *ip
, regno
);
8563 INSERT_OPERAND (FR
, *ip
, regno
);
8573 INSERT_OPERAND (FS
, *ip
, lastregno
);
8576 INSERT_OPERAND (FT
, *ip
, lastregno
);
8582 my_getExpression (&imm_expr
, s
);
8583 if (imm_expr
.X_op
!= O_big
8584 && imm_expr
.X_op
!= O_constant
)
8585 insn_error
= _("absolute expression required");
8586 normalize_constant_expr (&imm_expr
);
8591 my_getExpression (&offset_expr
, s
);
8592 *imm_reloc
= BFD_RELOC_32
;
8605 unsigned char temp
[8];
8607 unsigned int length
;
8612 /* These only appear as the last operand in an
8613 instruction, and every instruction that accepts
8614 them in any variant accepts them in all variants.
8615 This means we don't have to worry about backing out
8616 any changes if the instruction does not match.
8618 The difference between them is the size of the
8619 floating point constant and where it goes. For 'F'
8620 and 'L' the constant is 64 bits; for 'f' and 'l' it
8621 is 32 bits. Where the constant is placed is based
8622 on how the MIPS assembler does things:
8625 f -- immediate value
8628 The .lit4 and .lit8 sections are only used if
8629 permitted by the -G argument.
8631 The code below needs to know whether the target register
8632 is 32 or 64 bits wide. It relies on the fact 'f' and
8633 'F' are used with GPR-based instructions and 'l' and
8634 'L' are used with FPR-based instructions. */
8636 f64
= *args
== 'F' || *args
== 'L';
8637 using_gprs
= *args
== 'F' || *args
== 'f';
8639 save_in
= input_line_pointer
;
8640 input_line_pointer
= s
;
8641 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8643 s
= input_line_pointer
;
8644 input_line_pointer
= save_in
;
8645 if (err
!= NULL
&& *err
!= '\0')
8647 as_bad (_("Bad floating point constant: %s"), err
);
8648 memset (temp
, '\0', sizeof temp
);
8649 length
= f64
? 8 : 4;
8652 assert (length
== (unsigned) (f64
? 8 : 4));
8656 && (g_switch_value
< 4
8657 || (temp
[0] == 0 && temp
[1] == 0)
8658 || (temp
[2] == 0 && temp
[3] == 0))))
8660 imm_expr
.X_op
= O_constant
;
8661 if (! target_big_endian
)
8662 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8664 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8667 && ! mips_disable_float_construction
8668 /* Constants can only be constructed in GPRs and
8669 copied to FPRs if the GPRs are at least as wide
8670 as the FPRs. Force the constant into memory if
8671 we are using 64-bit FPRs but the GPRs are only
8674 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8675 && ((temp
[0] == 0 && temp
[1] == 0)
8676 || (temp
[2] == 0 && temp
[3] == 0))
8677 && ((temp
[4] == 0 && temp
[5] == 0)
8678 || (temp
[6] == 0 && temp
[7] == 0)))
8680 /* The value is simple enough to load with a couple of
8681 instructions. If using 32-bit registers, set
8682 imm_expr to the high order 32 bits and offset_expr to
8683 the low order 32 bits. Otherwise, set imm_expr to
8684 the entire 64 bit constant. */
8685 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8687 imm_expr
.X_op
= O_constant
;
8688 offset_expr
.X_op
= O_constant
;
8689 if (! target_big_endian
)
8691 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8692 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8696 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8697 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8699 if (offset_expr
.X_add_number
== 0)
8700 offset_expr
.X_op
= O_absent
;
8702 else if (sizeof (imm_expr
.X_add_number
) > 4)
8704 imm_expr
.X_op
= O_constant
;
8705 if (! target_big_endian
)
8706 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8708 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8712 imm_expr
.X_op
= O_big
;
8713 imm_expr
.X_add_number
= 4;
8714 if (! target_big_endian
)
8716 generic_bignum
[0] = bfd_getl16 (temp
);
8717 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8718 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8719 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8723 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8724 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8725 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8726 generic_bignum
[3] = bfd_getb16 (temp
);
8732 const char *newname
;
8735 /* Switch to the right section. */
8737 subseg
= now_subseg
;
8740 default: /* unused default case avoids warnings. */
8742 newname
= RDATA_SECTION_NAME
;
8743 if (g_switch_value
>= 8)
8747 newname
= RDATA_SECTION_NAME
;
8750 assert (g_switch_value
>= 4);
8754 new_seg
= subseg_new (newname
, (subsegT
) 0);
8755 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8756 bfd_set_section_flags (stdoutput
, new_seg
,
8761 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8762 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8763 && strcmp (TARGET_OS
, "elf") != 0)
8764 record_alignment (new_seg
, 4);
8766 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8768 as_bad (_("Can't use floating point insn in this section"));
8770 /* Set the argument to the current address in the
8772 offset_expr
.X_op
= O_symbol
;
8773 offset_expr
.X_add_symbol
=
8774 symbol_new ("L0\001", now_seg
,
8775 (valueT
) frag_now_fix (), frag_now
);
8776 offset_expr
.X_add_number
= 0;
8778 /* Put the floating point number into the section. */
8779 p
= frag_more ((int) length
);
8780 memcpy (p
, temp
, length
);
8782 /* Switch back to the original section. */
8783 subseg_set (seg
, subseg
);
8788 case 'i': /* 16 bit unsigned immediate */
8789 case 'j': /* 16 bit signed immediate */
8790 *imm_reloc
= BFD_RELOC_LO16
;
8791 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8794 offsetT minval
, maxval
;
8796 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8797 && strcmp (insn
->name
, insn
[1].name
) == 0);
8799 /* If the expression was written as an unsigned number,
8800 only treat it as signed if there are no more
8804 && sizeof (imm_expr
.X_add_number
) <= 4
8805 && imm_expr
.X_op
== O_constant
8806 && imm_expr
.X_add_number
< 0
8807 && imm_expr
.X_unsigned
8811 /* For compatibility with older assemblers, we accept
8812 0x8000-0xffff as signed 16-bit numbers when only
8813 signed numbers are allowed. */
8815 minval
= 0, maxval
= 0xffff;
8817 minval
= -0x8000, maxval
= 0x7fff;
8819 minval
= -0x8000, maxval
= 0xffff;
8821 if (imm_expr
.X_op
!= O_constant
8822 || imm_expr
.X_add_number
< minval
8823 || imm_expr
.X_add_number
> maxval
)
8827 if (imm_expr
.X_op
== O_constant
8828 || imm_expr
.X_op
== O_big
)
8829 as_bad (_("expression out of range"));
8835 case 'o': /* 16 bit offset */
8836 /* Check whether there is only a single bracketed expression
8837 left. If so, it must be the base register and the
8838 constant must be zero. */
8839 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8841 offset_expr
.X_op
= O_constant
;
8842 offset_expr
.X_add_number
= 0;
8846 /* If this value won't fit into a 16 bit offset, then go
8847 find a macro that will generate the 32 bit offset
8849 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8850 && (offset_expr
.X_op
!= O_constant
8851 || offset_expr
.X_add_number
>= 0x8000
8852 || offset_expr
.X_add_number
< -0x8000))
8858 case 'p': /* pc relative offset */
8859 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8860 my_getExpression (&offset_expr
, s
);
8864 case 'u': /* upper 16 bits */
8865 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8866 && imm_expr
.X_op
== O_constant
8867 && (imm_expr
.X_add_number
< 0
8868 || imm_expr
.X_add_number
>= 0x10000))
8869 as_bad (_("lui expression not in range 0..65535"));
8873 case 'a': /* 26 bit address */
8874 my_getExpression (&offset_expr
, s
);
8876 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8879 case 'N': /* 3 bit branch condition code */
8880 case 'M': /* 3 bit compare condition code */
8881 if (strncmp (s
, "$fcc", 4) != 0)
8891 while (ISDIGIT (*s
));
8893 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8894 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8895 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8896 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8897 && (regno
& 1) != 0)
8898 as_warn(_("Condition code register should be even for %s, was %d"),
8900 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8901 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8902 && (regno
& 3) != 0)
8903 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8906 INSERT_OPERAND (BCC
, *ip
, regno
);
8908 INSERT_OPERAND (CCC
, *ip
, regno
);
8912 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8923 while (ISDIGIT (*s
));
8926 c
= 8; /* Invalid sel value. */
8929 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8930 ip
->insn_opcode
|= c
;
8934 /* Must be at least one digit. */
8935 my_getExpression (&imm_expr
, s
);
8936 check_absolute_expr (ip
, &imm_expr
);
8938 if ((unsigned long) imm_expr
.X_add_number
8939 > (unsigned long) OP_MASK_VECBYTE
)
8941 as_bad (_("bad byte vector index (%ld)"),
8942 (long) imm_expr
.X_add_number
);
8943 imm_expr
.X_add_number
= 0;
8946 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
8947 imm_expr
.X_op
= O_absent
;
8952 my_getExpression (&imm_expr
, s
);
8953 check_absolute_expr (ip
, &imm_expr
);
8955 if ((unsigned long) imm_expr
.X_add_number
8956 > (unsigned long) OP_MASK_VECALIGN
)
8958 as_bad (_("bad byte vector index (%ld)"),
8959 (long) imm_expr
.X_add_number
);
8960 imm_expr
.X_add_number
= 0;
8963 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
8964 imm_expr
.X_op
= O_absent
;
8969 as_bad (_("bad char = '%c'\n"), *args
);
8974 /* Args don't match. */
8975 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8976 !strcmp (insn
->name
, insn
[1].name
))
8980 insn_error
= _("illegal operands");
8985 insn_error
= _("illegal operands");
8990 /* This routine assembles an instruction into its binary format when
8991 assembling for the mips16. As a side effect, it sets one of the
8992 global variables imm_reloc or offset_reloc to the type of
8993 relocation to do if one of the operands is an address expression.
8994 It also sets mips16_small and mips16_ext if the user explicitly
8995 requested a small or extended instruction. */
8998 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9002 struct mips_opcode
*insn
;
9005 unsigned int lastregno
= 0;
9011 mips16_small
= FALSE
;
9014 for (s
= str
; ISLOWER (*s
); ++s
)
9026 if (s
[1] == 't' && s
[2] == ' ')
9029 mips16_small
= TRUE
;
9033 else if (s
[1] == 'e' && s
[2] == ' ')
9042 insn_error
= _("unknown opcode");
9046 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9047 mips16_small
= TRUE
;
9049 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9051 insn_error
= _("unrecognized opcode");
9058 assert (strcmp (insn
->name
, str
) == 0);
9060 create_insn (ip
, insn
);
9061 imm_expr
.X_op
= O_absent
;
9062 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9063 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9064 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9065 imm2_expr
.X_op
= O_absent
;
9066 offset_expr
.X_op
= O_absent
;
9067 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9068 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9069 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9070 for (args
= insn
->args
; 1; ++args
)
9077 /* In this switch statement we call break if we did not find
9078 a match, continue if we did find a match, or return if we
9087 /* Stuff the immediate value in now, if we can. */
9088 if (imm_expr
.X_op
== O_constant
9089 && *imm_reloc
> BFD_RELOC_UNUSED
9090 && insn
->pinfo
!= INSN_MACRO
)
9094 switch (*offset_reloc
)
9096 case BFD_RELOC_MIPS16_HI16_S
:
9097 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9100 case BFD_RELOC_MIPS16_HI16
:
9101 tmp
= imm_expr
.X_add_number
>> 16;
9104 case BFD_RELOC_MIPS16_LO16
:
9105 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9109 case BFD_RELOC_UNUSED
:
9110 tmp
= imm_expr
.X_add_number
;
9116 *offset_reloc
= BFD_RELOC_UNUSED
;
9118 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9119 tmp
, TRUE
, mips16_small
,
9120 mips16_ext
, &ip
->insn_opcode
,
9121 &ip
->use_extend
, &ip
->extend
);
9122 imm_expr
.X_op
= O_absent
;
9123 *imm_reloc
= BFD_RELOC_UNUSED
;
9137 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9140 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9156 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9158 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9185 while (ISDIGIT (*s
));
9188 as_bad (_("invalid register number (%d)"), regno
);
9194 if (s
[1] == 'r' && s
[2] == 'a')
9199 else if (s
[1] == 'f' && s
[2] == 'p')
9204 else if (s
[1] == 's' && s
[2] == 'p')
9209 else if (s
[1] == 'g' && s
[2] == 'p')
9214 else if (s
[1] == 'a' && s
[2] == 't')
9219 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9224 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9229 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9242 if (c
== 'v' || c
== 'w')
9244 regno
= mips16_to_32_reg_map
[lastregno
];
9258 regno
= mips32_to_16_reg_map
[regno
];
9263 regno
= ILLEGAL_REG
;
9268 regno
= ILLEGAL_REG
;
9273 regno
= ILLEGAL_REG
;
9278 if (regno
== AT
&& ! mips_opts
.noat
)
9279 as_warn (_("used $at without \".set noat\""));
9286 if (regno
== ILLEGAL_REG
)
9293 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9297 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9300 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9303 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9309 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9312 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9313 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9323 if (strncmp (s
, "$pc", 3) == 0)
9340 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9343 if (imm_expr
.X_op
!= O_constant
)
9346 ip
->use_extend
= TRUE
;
9351 /* We need to relax this instruction. */
9352 *offset_reloc
= *imm_reloc
;
9353 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9358 *imm_reloc
= BFD_RELOC_UNUSED
;
9366 my_getExpression (&imm_expr
, s
);
9367 if (imm_expr
.X_op
== O_register
)
9369 /* What we thought was an expression turned out to
9372 if (s
[0] == '(' && args
[1] == '(')
9374 /* It looks like the expression was omitted
9375 before a register indirection, which means
9376 that the expression is implicitly zero. We
9377 still set up imm_expr, so that we handle
9378 explicit extensions correctly. */
9379 imm_expr
.X_op
= O_constant
;
9380 imm_expr
.X_add_number
= 0;
9381 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9388 /* We need to relax this instruction. */
9389 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9398 /* We use offset_reloc rather than imm_reloc for the PC
9399 relative operands. This lets macros with both
9400 immediate and address operands work correctly. */
9401 my_getExpression (&offset_expr
, s
);
9403 if (offset_expr
.X_op
== O_register
)
9406 /* We need to relax this instruction. */
9407 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9411 case '6': /* break code */
9412 my_getExpression (&imm_expr
, s
);
9413 check_absolute_expr (ip
, &imm_expr
);
9414 if ((unsigned long) imm_expr
.X_add_number
> 63)
9415 as_warn (_("Invalid value for `%s' (%lu)"),
9417 (unsigned long) imm_expr
.X_add_number
);
9418 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9419 imm_expr
.X_op
= O_absent
;
9423 case 'a': /* 26 bit address */
9424 my_getExpression (&offset_expr
, s
);
9426 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9427 ip
->insn_opcode
<<= 16;
9430 case 'l': /* register list for entry macro */
9431 case 'L': /* register list for exit macro */
9441 int freg
, reg1
, reg2
;
9443 while (*s
== ' ' || *s
== ',')
9447 as_bad (_("can't parse register list"));
9459 while (ISDIGIT (*s
))
9481 as_bad (_("invalid register list"));
9486 while (ISDIGIT (*s
))
9493 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9498 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9503 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9504 mask
|= (reg2
- 3) << 3;
9505 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9506 mask
|= (reg2
- 15) << 1;
9507 else if (reg1
== RA
&& reg2
== RA
)
9511 as_bad (_("invalid register list"));
9515 /* The mask is filled in in the opcode table for the
9516 benefit of the disassembler. We remove it before
9517 applying the actual mask. */
9518 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9519 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9523 case 'e': /* extend code */
9524 my_getExpression (&imm_expr
, s
);
9525 check_absolute_expr (ip
, &imm_expr
);
9526 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9528 as_warn (_("Invalid value for `%s' (%lu)"),
9530 (unsigned long) imm_expr
.X_add_number
);
9531 imm_expr
.X_add_number
&= 0x7ff;
9533 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9534 imm_expr
.X_op
= O_absent
;
9544 /* Args don't match. */
9545 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9546 strcmp (insn
->name
, insn
[1].name
) == 0)
9553 insn_error
= _("illegal operands");
9559 /* This structure holds information we know about a mips16 immediate
9562 struct mips16_immed_operand
9564 /* The type code used in the argument string in the opcode table. */
9566 /* The number of bits in the short form of the opcode. */
9568 /* The number of bits in the extended form of the opcode. */
9570 /* The amount by which the short form is shifted when it is used;
9571 for example, the sw instruction has a shift count of 2. */
9573 /* The amount by which the short form is shifted when it is stored
9574 into the instruction code. */
9576 /* Non-zero if the short form is unsigned. */
9578 /* Non-zero if the extended form is unsigned. */
9580 /* Non-zero if the value is PC relative. */
9584 /* The mips16 immediate operand types. */
9586 static const struct mips16_immed_operand mips16_immed_operands
[] =
9588 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9589 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9590 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9591 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9592 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9593 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9594 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9595 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9596 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9597 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9598 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9599 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9600 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9601 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9602 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9603 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9604 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9605 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9606 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9607 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9608 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9611 #define MIPS16_NUM_IMMED \
9612 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9614 /* Handle a mips16 instruction with an immediate value. This or's the
9615 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9616 whether an extended value is needed; if one is needed, it sets
9617 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9618 If SMALL is true, an unextended opcode was explicitly requested.
9619 If EXT is true, an extended opcode was explicitly requested. If
9620 WARN is true, warn if EXT does not match reality. */
9623 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9624 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9625 unsigned long *insn
, bfd_boolean
*use_extend
,
9626 unsigned short *extend
)
9628 register const struct mips16_immed_operand
*op
;
9629 int mintiny
, maxtiny
;
9630 bfd_boolean needext
;
9632 op
= mips16_immed_operands
;
9633 while (op
->type
!= type
)
9636 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9641 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9644 maxtiny
= 1 << op
->nbits
;
9649 maxtiny
= (1 << op
->nbits
) - 1;
9654 mintiny
= - (1 << (op
->nbits
- 1));
9655 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9658 /* Branch offsets have an implicit 0 in the lowest bit. */
9659 if (type
== 'p' || type
== 'q')
9662 if ((val
& ((1 << op
->shift
) - 1)) != 0
9663 || val
< (mintiny
<< op
->shift
)
9664 || val
> (maxtiny
<< op
->shift
))
9669 if (warn
&& ext
&& ! needext
)
9670 as_warn_where (file
, line
,
9671 _("extended operand requested but not required"));
9672 if (small
&& needext
)
9673 as_bad_where (file
, line
, _("invalid unextended operand value"));
9675 if (small
|| (! ext
&& ! needext
))
9679 *use_extend
= FALSE
;
9680 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9681 insnval
<<= op
->op_shift
;
9686 long minext
, maxext
;
9692 maxext
= (1 << op
->extbits
) - 1;
9696 minext
= - (1 << (op
->extbits
- 1));
9697 maxext
= (1 << (op
->extbits
- 1)) - 1;
9699 if (val
< minext
|| val
> maxext
)
9700 as_bad_where (file
, line
,
9701 _("operand value out of range for instruction"));
9704 if (op
->extbits
== 16)
9706 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9709 else if (op
->extbits
== 15)
9711 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9716 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9720 *extend
= (unsigned short) extval
;
9725 struct percent_op_match
9728 bfd_reloc_code_real_type reloc
;
9731 static const struct percent_op_match mips_percent_op
[] =
9733 {"%lo", BFD_RELOC_LO16
},
9735 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9736 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9737 {"%call16", BFD_RELOC_MIPS_CALL16
},
9738 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9739 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9740 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9741 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9742 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9743 {"%got", BFD_RELOC_MIPS_GOT16
},
9744 {"%gp_rel", BFD_RELOC_GPREL16
},
9745 {"%half", BFD_RELOC_16
},
9746 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9747 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9748 {"%neg", BFD_RELOC_MIPS_SUB
},
9749 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
9750 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
9751 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
9752 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
9753 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
9754 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
9755 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
9757 {"%hi", BFD_RELOC_HI16_S
}
9760 static const struct percent_op_match mips16_percent_op
[] =
9762 {"%lo", BFD_RELOC_MIPS16_LO16
},
9763 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9764 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9768 /* Return true if *STR points to a relocation operator. When returning true,
9769 move *STR over the operator and store its relocation code in *RELOC.
9770 Leave both *STR and *RELOC alone when returning false. */
9773 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9775 const struct percent_op_match
*percent_op
;
9778 if (mips_opts
.mips16
)
9780 percent_op
= mips16_percent_op
;
9781 limit
= ARRAY_SIZE (mips16_percent_op
);
9785 percent_op
= mips_percent_op
;
9786 limit
= ARRAY_SIZE (mips_percent_op
);
9789 for (i
= 0; i
< limit
; i
++)
9790 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9792 int len
= strlen (percent_op
[i
].str
);
9794 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
9797 *str
+= strlen (percent_op
[i
].str
);
9798 *reloc
= percent_op
[i
].reloc
;
9800 /* Check whether the output BFD supports this relocation.
9801 If not, issue an error and fall back on something safe. */
9802 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9804 as_bad ("relocation %s isn't supported by the current ABI",
9806 *reloc
= BFD_RELOC_UNUSED
;
9814 /* Parse string STR as a 16-bit relocatable operand. Store the
9815 expression in *EP and the relocations in the array starting
9816 at RELOC. Return the number of relocation operators used.
9818 On exit, EXPR_END points to the first character after the expression. */
9821 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9824 bfd_reloc_code_real_type reversed_reloc
[3];
9825 size_t reloc_index
, i
;
9826 int crux_depth
, str_depth
;
9829 /* Search for the start of the main expression, recoding relocations
9830 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9831 of the main expression and with CRUX_DEPTH containing the number
9832 of open brackets at that point. */
9839 crux_depth
= str_depth
;
9841 /* Skip over whitespace and brackets, keeping count of the number
9843 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9848 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9849 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9851 my_getExpression (ep
, crux
);
9854 /* Match every open bracket. */
9855 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9860 as_bad ("unclosed '('");
9864 if (reloc_index
!= 0)
9866 prev_reloc_op_frag
= frag_now
;
9867 for (i
= 0; i
< reloc_index
; i
++)
9868 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9875 my_getExpression (expressionS
*ep
, char *str
)
9880 save_in
= input_line_pointer
;
9881 input_line_pointer
= str
;
9883 expr_end
= input_line_pointer
;
9884 input_line_pointer
= save_in
;
9886 /* If we are in mips16 mode, and this is an expression based on `.',
9887 then we bump the value of the symbol by 1 since that is how other
9888 text symbols are handled. We don't bother to handle complex
9889 expressions, just `.' plus or minus a constant. */
9890 if (mips_opts
.mips16
9891 && ep
->X_op
== O_symbol
9892 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9893 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9894 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9895 && symbol_constant_p (ep
->X_add_symbol
)
9896 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9897 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9900 /* Turn a string in input_line_pointer into a floating point constant
9901 of type TYPE, and store the appropriate bytes in *LITP. The number
9902 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9903 returned, or NULL on OK. */
9906 md_atof (int type
, char *litP
, int *sizeP
)
9909 LITTLENUM_TYPE words
[4];
9925 return _("bad call to md_atof");
9928 t
= atof_ieee (input_line_pointer
, type
, words
);
9930 input_line_pointer
= t
;
9934 if (! target_big_endian
)
9936 for (i
= prec
- 1; i
>= 0; i
--)
9938 md_number_to_chars (litP
, words
[i
], 2);
9944 for (i
= 0; i
< prec
; i
++)
9946 md_number_to_chars (litP
, words
[i
], 2);
9955 md_number_to_chars (char *buf
, valueT val
, int n
)
9957 if (target_big_endian
)
9958 number_to_chars_bigendian (buf
, val
, n
);
9960 number_to_chars_littleendian (buf
, val
, n
);
9964 static int support_64bit_objects(void)
9966 const char **list
, **l
;
9969 list
= bfd_target_list ();
9970 for (l
= list
; *l
!= NULL
; l
++)
9972 /* This is traditional mips */
9973 if (strcmp (*l
, "elf64-tradbigmips") == 0
9974 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9976 if (strcmp (*l
, "elf64-bigmips") == 0
9977 || strcmp (*l
, "elf64-littlemips") == 0)
9984 #endif /* OBJ_ELF */
9986 const char *md_shortopts
= "O::g::G:";
9988 struct option md_longopts
[] =
9990 /* Options which specify architecture. */
9991 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
9992 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
9993 {"march", required_argument
, NULL
, OPTION_MARCH
},
9994 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
9995 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9996 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
9997 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9998 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9999 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10000 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10001 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10002 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10003 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10004 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10005 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10006 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10007 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10008 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10009 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10010 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10011 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10012 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10013 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10014 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10016 /* Options which specify Application Specific Extensions (ASEs). */
10017 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10018 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10019 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10020 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10021 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10022 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10023 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10024 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10025 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10026 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10027 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10028 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10029 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10031 /* Old-style architecture options. Don't add more of these. */
10032 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10033 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10034 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10035 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10036 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10037 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10038 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10039 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10040 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10041 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10042 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10043 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10044 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10045 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10046 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10047 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10048 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10050 /* Options which enable bug fixes. */
10051 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10052 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10053 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10054 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10055 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10056 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10057 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10058 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10059 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10060 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10062 /* Miscellaneous options. */
10063 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10064 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10065 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10066 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10067 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10068 {"break", no_argument
, NULL
, OPTION_BREAK
},
10069 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10070 #define OPTION_EB (OPTION_MISC_BASE + 2)
10071 {"EB", no_argument
, NULL
, OPTION_EB
},
10072 #define OPTION_EL (OPTION_MISC_BASE + 3)
10073 {"EL", no_argument
, NULL
, OPTION_EL
},
10074 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10075 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10076 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10077 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10078 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10079 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10080 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10081 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10082 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10083 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10084 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10085 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10086 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10087 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10088 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10089 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10090 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10091 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10092 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10093 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10094 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10095 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10096 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10097 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10099 /* ELF-specific options. */
10101 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10102 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10103 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10104 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10105 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10106 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10107 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10108 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10109 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10110 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10111 #define OPTION_32 (OPTION_ELF_BASE + 4)
10112 {"32", no_argument
, NULL
, OPTION_32
},
10113 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10114 {"n32", no_argument
, NULL
, OPTION_N32
},
10115 #define OPTION_64 (OPTION_ELF_BASE + 6)
10116 {"64", no_argument
, NULL
, OPTION_64
},
10117 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10118 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10119 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10120 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10121 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10122 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10123 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10124 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10125 #endif /* OBJ_ELF */
10127 {NULL
, no_argument
, NULL
, 0}
10129 size_t md_longopts_size
= sizeof (md_longopts
);
10131 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10132 NEW_VALUE. Warn if another value was already specified. Note:
10133 we have to defer parsing the -march and -mtune arguments in order
10134 to handle 'from-abi' correctly, since the ABI might be specified
10135 in a later argument. */
10138 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10140 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10141 as_warn (_("A different %s was already specified, is now %s"),
10142 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10145 *string_ptr
= new_value
;
10149 md_parse_option (int c
, char *arg
)
10153 case OPTION_CONSTRUCT_FLOATS
:
10154 mips_disable_float_construction
= 0;
10157 case OPTION_NO_CONSTRUCT_FLOATS
:
10158 mips_disable_float_construction
= 1;
10170 target_big_endian
= 1;
10174 target_big_endian
= 0;
10178 if (arg
&& arg
[1] == '0')
10188 mips_debug
= atoi (arg
);
10189 /* When the MIPS assembler sees -g or -g2, it does not do
10190 optimizations which limit full symbolic debugging. We take
10191 that to be equivalent to -O0. */
10192 if (mips_debug
== 2)
10197 file_mips_isa
= ISA_MIPS1
;
10201 file_mips_isa
= ISA_MIPS2
;
10205 file_mips_isa
= ISA_MIPS3
;
10209 file_mips_isa
= ISA_MIPS4
;
10213 file_mips_isa
= ISA_MIPS5
;
10216 case OPTION_MIPS32
:
10217 file_mips_isa
= ISA_MIPS32
;
10220 case OPTION_MIPS32R2
:
10221 file_mips_isa
= ISA_MIPS32R2
;
10224 case OPTION_MIPS64R2
:
10225 file_mips_isa
= ISA_MIPS64R2
;
10228 case OPTION_MIPS64
:
10229 file_mips_isa
= ISA_MIPS64
;
10233 mips_set_option_string (&mips_tune_string
, arg
);
10237 mips_set_option_string (&mips_arch_string
, arg
);
10241 mips_set_option_string (&mips_arch_string
, "4650");
10242 mips_set_option_string (&mips_tune_string
, "4650");
10245 case OPTION_NO_M4650
:
10249 mips_set_option_string (&mips_arch_string
, "4010");
10250 mips_set_option_string (&mips_tune_string
, "4010");
10253 case OPTION_NO_M4010
:
10257 mips_set_option_string (&mips_arch_string
, "4100");
10258 mips_set_option_string (&mips_tune_string
, "4100");
10261 case OPTION_NO_M4100
:
10265 mips_set_option_string (&mips_arch_string
, "3900");
10266 mips_set_option_string (&mips_tune_string
, "3900");
10269 case OPTION_NO_M3900
:
10273 mips_opts
.ase_mdmx
= 1;
10276 case OPTION_NO_MDMX
:
10277 mips_opts
.ase_mdmx
= 0;
10280 case OPTION_MIPS16
:
10281 mips_opts
.mips16
= 1;
10282 mips_no_prev_insn (FALSE
);
10285 case OPTION_NO_MIPS16
:
10286 mips_opts
.mips16
= 0;
10287 mips_no_prev_insn (FALSE
);
10290 case OPTION_MIPS3D
:
10291 mips_opts
.ase_mips3d
= 1;
10294 case OPTION_NO_MIPS3D
:
10295 mips_opts
.ase_mips3d
= 0;
10298 case OPTION_FIX_VR4120
:
10299 mips_fix_vr4120
= 1;
10302 case OPTION_NO_FIX_VR4120
:
10303 mips_fix_vr4120
= 0;
10306 case OPTION_RELAX_BRANCH
:
10307 mips_relax_branch
= 1;
10310 case OPTION_NO_RELAX_BRANCH
:
10311 mips_relax_branch
= 0;
10314 case OPTION_MSHARED
:
10315 mips_in_shared
= TRUE
;
10318 case OPTION_MNO_SHARED
:
10319 mips_in_shared
= FALSE
;
10322 case OPTION_MSYM32
:
10323 mips_opts
.sym32
= TRUE
;
10326 case OPTION_MNO_SYM32
:
10327 mips_opts
.sym32
= FALSE
;
10331 /* When generating ELF code, we permit -KPIC and -call_shared to
10332 select SVR4_PIC, and -non_shared to select no PIC. This is
10333 intended to be compatible with Irix 5. */
10334 case OPTION_CALL_SHARED
:
10335 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10337 as_bad (_("-call_shared is supported only for ELF format"));
10340 mips_pic
= SVR4_PIC
;
10341 mips_abicalls
= TRUE
;
10342 if (g_switch_seen
&& g_switch_value
!= 0)
10344 as_bad (_("-G may not be used with SVR4 PIC code"));
10347 g_switch_value
= 0;
10350 case OPTION_NON_SHARED
:
10351 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10353 as_bad (_("-non_shared is supported only for ELF format"));
10357 mips_abicalls
= FALSE
;
10360 /* The -xgot option tells the assembler to use 32 offsets when
10361 accessing the got in SVR4_PIC mode. It is for Irix
10366 #endif /* OBJ_ELF */
10369 g_switch_value
= atoi (arg
);
10371 if (mips_pic
== SVR4_PIC
&& g_switch_value
!= 0)
10373 as_bad (_("-G may not be used with SVR4 PIC code"));
10379 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10382 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10384 as_bad (_("-32 is supported for ELF format only"));
10387 mips_abi
= O32_ABI
;
10391 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10393 as_bad (_("-n32 is supported for ELF format only"));
10396 mips_abi
= N32_ABI
;
10400 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10402 as_bad (_("-64 is supported for ELF format only"));
10405 mips_abi
= N64_ABI
;
10406 if (! support_64bit_objects())
10407 as_fatal (_("No compiled in support for 64 bit object file format"));
10409 #endif /* OBJ_ELF */
10412 file_mips_gp32
= 1;
10416 file_mips_gp32
= 0;
10420 file_mips_fp32
= 1;
10424 file_mips_fp32
= 0;
10429 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10431 as_bad (_("-mabi is supported for ELF format only"));
10434 if (strcmp (arg
, "32") == 0)
10435 mips_abi
= O32_ABI
;
10436 else if (strcmp (arg
, "o64") == 0)
10437 mips_abi
= O64_ABI
;
10438 else if (strcmp (arg
, "n32") == 0)
10439 mips_abi
= N32_ABI
;
10440 else if (strcmp (arg
, "64") == 0)
10442 mips_abi
= N64_ABI
;
10443 if (! support_64bit_objects())
10444 as_fatal (_("No compiled in support for 64 bit object file "
10447 else if (strcmp (arg
, "eabi") == 0)
10448 mips_abi
= EABI_ABI
;
10451 as_fatal (_("invalid abi -mabi=%s"), arg
);
10455 #endif /* OBJ_ELF */
10457 case OPTION_M7000_HILO_FIX
:
10458 mips_7000_hilo_fix
= TRUE
;
10461 case OPTION_MNO_7000_HILO_FIX
:
10462 mips_7000_hilo_fix
= FALSE
;
10466 case OPTION_MDEBUG
:
10467 mips_flag_mdebug
= TRUE
;
10470 case OPTION_NO_MDEBUG
:
10471 mips_flag_mdebug
= FALSE
;
10475 mips_flag_pdr
= TRUE
;
10478 case OPTION_NO_PDR
:
10479 mips_flag_pdr
= FALSE
;
10481 #endif /* OBJ_ELF */
10490 /* Set up globals to generate code for the ISA or processor
10491 described by INFO. */
10494 mips_set_architecture (const struct mips_cpu_info
*info
)
10498 file_mips_arch
= info
->cpu
;
10499 mips_opts
.arch
= info
->cpu
;
10500 mips_opts
.isa
= info
->isa
;
10505 /* Likewise for tuning. */
10508 mips_set_tune (const struct mips_cpu_info
*info
)
10511 mips_tune
= info
->cpu
;
10516 mips_after_parse_args (void)
10518 const struct mips_cpu_info
*arch_info
= 0;
10519 const struct mips_cpu_info
*tune_info
= 0;
10521 /* GP relative stuff not working for PE */
10522 if (strncmp (TARGET_OS
, "pe", 2) == 0)
10524 if (g_switch_seen
&& g_switch_value
!= 0)
10525 as_bad (_("-G not supported in this configuration."));
10526 g_switch_value
= 0;
10529 if (mips_abi
== NO_ABI
)
10530 mips_abi
= MIPS_DEFAULT_ABI
;
10532 /* The following code determines the architecture and register size.
10533 Similar code was added to GCC 3.3 (see override_options() in
10534 config/mips/mips.c). The GAS and GCC code should be kept in sync
10535 as much as possible. */
10537 if (mips_arch_string
!= 0)
10538 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10540 if (file_mips_isa
!= ISA_UNKNOWN
)
10542 /* Handle -mipsN. At this point, file_mips_isa contains the
10543 ISA level specified by -mipsN, while arch_info->isa contains
10544 the -march selection (if any). */
10545 if (arch_info
!= 0)
10547 /* -march takes precedence over -mipsN, since it is more descriptive.
10548 There's no harm in specifying both as long as the ISA levels
10550 if (file_mips_isa
!= arch_info
->isa
)
10551 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10552 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10553 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10556 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10559 if (arch_info
== 0)
10560 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10562 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10563 as_bad ("-march=%s is not compatible with the selected ABI",
10566 mips_set_architecture (arch_info
);
10568 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10569 if (mips_tune_string
!= 0)
10570 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10572 if (tune_info
== 0)
10573 mips_set_tune (arch_info
);
10575 mips_set_tune (tune_info
);
10577 if (file_mips_gp32
>= 0)
10579 /* The user specified the size of the integer registers. Make sure
10580 it agrees with the ABI and ISA. */
10581 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10582 as_bad (_("-mgp64 used with a 32-bit processor"));
10583 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10584 as_bad (_("-mgp32 used with a 64-bit ABI"));
10585 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10586 as_bad (_("-mgp64 used with a 32-bit ABI"));
10590 /* Infer the integer register size from the ABI and processor.
10591 Restrict ourselves to 32-bit registers if that's all the
10592 processor has, or if the ABI cannot handle 64-bit registers. */
10593 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10594 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10597 /* ??? GAS treats single-float processors as though they had 64-bit
10598 float registers (although it complains when double-precision
10599 instructions are used). As things stand, saying they have 32-bit
10600 registers would lead to spurious "register must be even" messages.
10601 So here we assume float registers are always the same size as
10602 integer ones, unless the user says otherwise. */
10603 if (file_mips_fp32
< 0)
10604 file_mips_fp32
= file_mips_gp32
;
10606 /* End of GCC-shared inference code. */
10608 /* This flag is set when we have a 64-bit capable CPU but use only
10609 32-bit wide registers. Note that EABI does not use it. */
10610 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10611 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10612 || mips_abi
== O32_ABI
))
10613 mips_32bitmode
= 1;
10615 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10616 as_bad (_("trap exception not supported at ISA 1"));
10618 /* If the selected architecture includes support for ASEs, enable
10619 generation of code for them. */
10620 if (mips_opts
.mips16
== -1)
10621 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10622 if (mips_opts
.ase_mips3d
== -1)
10623 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10624 if (mips_opts
.ase_mdmx
== -1)
10625 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10627 file_mips_isa
= mips_opts
.isa
;
10628 file_ase_mips16
= mips_opts
.mips16
;
10629 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10630 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10631 mips_opts
.gp32
= file_mips_gp32
;
10632 mips_opts
.fp32
= file_mips_fp32
;
10634 if (mips_flag_mdebug
< 0)
10636 #ifdef OBJ_MAYBE_ECOFF
10637 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10638 mips_flag_mdebug
= 1;
10640 #endif /* OBJ_MAYBE_ECOFF */
10641 mips_flag_mdebug
= 0;
10646 mips_init_after_args (void)
10648 /* initialize opcodes */
10649 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10650 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10654 md_pcrel_from (fixS
*fixP
)
10656 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10657 switch (fixP
->fx_r_type
)
10659 case BFD_RELOC_16_PCREL_S2
:
10660 case BFD_RELOC_MIPS_JMP
:
10661 /* Return the address of the delay slot. */
10668 /* This is called before the symbol table is processed. In order to
10669 work with gcc when using mips-tfile, we must keep all local labels.
10670 However, in other cases, we want to discard them. If we were
10671 called with -g, but we didn't see any debugging information, it may
10672 mean that gcc is smuggling debugging information through to
10673 mips-tfile, in which case we must generate all local labels. */
10676 mips_frob_file_before_adjust (void)
10678 #ifndef NO_ECOFF_DEBUGGING
10679 if (ECOFF_DEBUGGING
10681 && ! ecoff_debugging_seen
)
10682 flag_keep_locals
= 1;
10686 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10687 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10688 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10689 relocation operators.
10691 For our purposes, a %lo() expression matches a %got() or %hi()
10694 (a) it refers to the same symbol; and
10695 (b) the offset applied in the %lo() expression is no lower than
10696 the offset applied in the %got() or %hi().
10698 (b) allows us to cope with code like:
10701 lh $4,%lo(foo+2)($4)
10703 ...which is legal on RELA targets, and has a well-defined behaviour
10704 if the user knows that adding 2 to "foo" will not induce a carry to
10707 When several %lo()s match a particular %got() or %hi(), we use the
10708 following rules to distinguish them:
10710 (1) %lo()s with smaller offsets are a better match than %lo()s with
10713 (2) %lo()s with no matching %got() or %hi() are better than those
10714 that already have a matching %got() or %hi().
10716 (3) later %lo()s are better than earlier %lo()s.
10718 These rules are applied in order.
10720 (1) means, among other things, that %lo()s with identical offsets are
10721 chosen if they exist.
10723 (2) means that we won't associate several high-part relocations with
10724 the same low-part relocation unless there's no alternative. Having
10725 several high parts for the same low part is a GNU extension; this rule
10726 allows careful users to avoid it.
10728 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10729 with the last high-part relocation being at the front of the list.
10730 It therefore makes sense to choose the last matching low-part
10731 relocation, all other things being equal. It's also easier
10732 to code that way. */
10735 mips_frob_file (void)
10737 struct mips_hi_fixup
*l
;
10739 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10741 segment_info_type
*seginfo
;
10742 bfd_boolean matched_lo_p
;
10743 fixS
**hi_pos
, **lo_pos
, **pos
;
10745 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10747 /* If a GOT16 relocation turns out to be against a global symbol,
10748 there isn't supposed to be a matching LO. */
10749 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10750 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10753 /* Check quickly whether the next fixup happens to be a matching %lo. */
10754 if (fixup_has_matching_lo_p (l
->fixp
))
10757 seginfo
= seg_info (l
->seg
);
10759 /* Set HI_POS to the position of this relocation in the chain.
10760 Set LO_POS to the position of the chosen low-part relocation.
10761 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10762 relocation that matches an immediately-preceding high-part
10766 matched_lo_p
= FALSE
;
10767 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10769 if (*pos
== l
->fixp
)
10772 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10773 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10774 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10776 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10778 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10781 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10782 && fixup_has_matching_lo_p (*pos
));
10785 /* If we found a match, remove the high-part relocation from its
10786 current position and insert it before the low-part relocation.
10787 Make the offsets match so that fixup_has_matching_lo_p()
10790 We don't warn about unmatched high-part relocations since some
10791 versions of gcc have been known to emit dead "lui ...%hi(...)"
10793 if (lo_pos
!= NULL
)
10795 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10796 if (l
->fixp
->fx_next
!= *lo_pos
)
10798 *hi_pos
= l
->fixp
->fx_next
;
10799 l
->fixp
->fx_next
= *lo_pos
;
10806 /* We may have combined relocations without symbols in the N32/N64 ABI.
10807 We have to prevent gas from dropping them. */
10810 mips_force_relocation (fixS
*fixp
)
10812 if (generic_force_reloc (fixp
))
10816 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10817 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10818 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10819 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10825 /* This hook is called before a fix is simplified. We don't really
10826 decide whether to skip a fix here. Rather, we turn global symbols
10827 used as branch targets into local symbols, such that they undergo
10828 simplification. We can only do this if the symbol is defined and
10829 it is in the same section as the branch. If this doesn't hold, we
10830 emit a better error message than just saying the relocation is not
10831 valid for the selected object format.
10833 FIXP is the fix-up we're going to try to simplify, SEG is the
10834 segment in which the fix up occurs. The return value should be
10835 non-zero to indicate the fix-up is valid for further
10836 simplifications. */
10839 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10841 /* There's a lot of discussion on whether it should be possible to
10842 use R_MIPS_PC16 to represent branch relocations. The outcome
10843 seems to be that it can, but gas/bfd are very broken in creating
10844 RELA relocations for this, so for now we only accept branches to
10845 symbols in the same section. Anything else is of dubious value,
10846 since there's no guarantee that at link time the symbol would be
10847 in range. Even for branches to local symbols this is arguably
10848 wrong, since it we assume the symbol is not going to be
10849 overridden, which should be possible per ELF library semantics,
10850 but then, there isn't a dynamic relocation that could be used to
10851 this effect, and the target would likely be out of range as well.
10853 Unfortunately, it seems that there is too much code out there
10854 that relies on branches to symbols that are global to be resolved
10855 as if they were local, like the IRIX tools do, so we do it as
10856 well, but with a warning so that people are reminded to fix their
10857 code. If we ever get back to using R_MIPS_PC16 for branch
10858 targets, this entire block should go away (and probably the
10859 whole function). */
10861 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10862 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10863 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10864 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10867 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10870 _("Cannot branch to undefined symbol."));
10871 /* Avoid any further errors about this fixup. */
10874 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10877 _("Cannot branch to symbol in another section."));
10880 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10882 symbolS
*sym
= fixP
->fx_addsy
;
10884 if (mips_pic
== SVR4_PIC
)
10885 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10886 _("Pretending global symbol used as branch target is local."));
10888 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10889 S_GET_SEGMENT (sym
),
10891 symbol_get_frag (sym
));
10892 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10893 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10894 assert (symbol_resolved_p (sym
));
10895 symbol_mark_resolved (fixP
->fx_addsy
);
10902 /* Apply a fixup to the object file. */
10905 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10909 reloc_howto_type
*howto
;
10911 /* We ignore generic BFD relocations we don't know about. */
10912 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10916 assert (fixP
->fx_size
== 4
10917 || fixP
->fx_r_type
== BFD_RELOC_16
10918 || fixP
->fx_r_type
== BFD_RELOC_64
10919 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10920 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10921 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10922 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10924 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10926 assert (! fixP
->fx_pcrel
);
10928 /* Don't treat parts of a composite relocation as done. There are two
10931 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10932 should nevertheless be emitted if the first part is.
10934 (2) In normal usage, composite relocations are never assembly-time
10935 constants. The easiest way of dealing with the pathological
10936 exceptions is to generate a relocation against STN_UNDEF and
10937 leave everything up to the linker. */
10938 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10941 switch (fixP
->fx_r_type
)
10943 case BFD_RELOC_MIPS_TLS_GD
:
10944 case BFD_RELOC_MIPS_TLS_LDM
:
10945 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
10946 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
10947 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
10948 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
10949 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
10950 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10953 case BFD_RELOC_MIPS_JMP
:
10954 case BFD_RELOC_MIPS_SHIFT5
:
10955 case BFD_RELOC_MIPS_SHIFT6
:
10956 case BFD_RELOC_MIPS_GOT_DISP
:
10957 case BFD_RELOC_MIPS_GOT_PAGE
:
10958 case BFD_RELOC_MIPS_GOT_OFST
:
10959 case BFD_RELOC_MIPS_SUB
:
10960 case BFD_RELOC_MIPS_INSERT_A
:
10961 case BFD_RELOC_MIPS_INSERT_B
:
10962 case BFD_RELOC_MIPS_DELETE
:
10963 case BFD_RELOC_MIPS_HIGHEST
:
10964 case BFD_RELOC_MIPS_HIGHER
:
10965 case BFD_RELOC_MIPS_SCN_DISP
:
10966 case BFD_RELOC_MIPS_REL16
:
10967 case BFD_RELOC_MIPS_RELGOT
:
10968 case BFD_RELOC_MIPS_JALR
:
10969 case BFD_RELOC_HI16
:
10970 case BFD_RELOC_HI16_S
:
10971 case BFD_RELOC_GPREL16
:
10972 case BFD_RELOC_MIPS_LITERAL
:
10973 case BFD_RELOC_MIPS_CALL16
:
10974 case BFD_RELOC_MIPS_GOT16
:
10975 case BFD_RELOC_GPREL32
:
10976 case BFD_RELOC_MIPS_GOT_HI16
:
10977 case BFD_RELOC_MIPS_GOT_LO16
:
10978 case BFD_RELOC_MIPS_CALL_HI16
:
10979 case BFD_RELOC_MIPS_CALL_LO16
:
10980 case BFD_RELOC_MIPS16_GPREL
:
10981 case BFD_RELOC_MIPS16_HI16
:
10982 case BFD_RELOC_MIPS16_HI16_S
:
10983 assert (! fixP
->fx_pcrel
);
10984 /* Nothing needed to do. The value comes from the reloc entry */
10987 case BFD_RELOC_MIPS16_JMP
:
10988 /* We currently always generate a reloc against a symbol, which
10989 means that we don't want an addend even if the symbol is
10995 /* This is handled like BFD_RELOC_32, but we output a sign
10996 extended value if we are only 32 bits. */
10999 if (8 <= sizeof (valueT
))
11000 md_number_to_chars ((char *) buf
, *valP
, 8);
11005 if ((*valP
& 0x80000000) != 0)
11009 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11011 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11017 case BFD_RELOC_RVA
:
11019 /* If we are deleting this reloc entry, we must fill in the
11020 value now. This can happen if we have a .word which is not
11021 resolved when it appears but is later defined. */
11023 md_number_to_chars ((char *) buf
, *valP
, 4);
11027 /* If we are deleting this reloc entry, we must fill in the
11030 md_number_to_chars ((char *) buf
, *valP
, 2);
11033 case BFD_RELOC_LO16
:
11034 case BFD_RELOC_MIPS16_LO16
:
11035 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11036 may be safe to remove, but if so it's not obvious. */
11037 /* When handling an embedded PIC switch statement, we can wind
11038 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11041 if (*valP
+ 0x8000 > 0xffff)
11042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11043 _("relocation overflow"));
11044 if (target_big_endian
)
11046 md_number_to_chars ((char *) buf
, *valP
, 2);
11050 case BFD_RELOC_16_PCREL_S2
:
11051 if ((*valP
& 0x3) != 0)
11052 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11053 _("Branch to odd address (%lx)"), (long) *valP
);
11056 * We need to save the bits in the instruction since fixup_segment()
11057 * might be deleting the relocation entry (i.e., a branch within
11058 * the current segment).
11060 if (! fixP
->fx_done
)
11063 /* update old instruction data */
11064 if (target_big_endian
)
11065 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11067 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11069 if (*valP
+ 0x20000 <= 0x3ffff)
11071 insn
|= (*valP
>> 2) & 0xffff;
11072 md_number_to_chars ((char *) buf
, insn
, 4);
11074 else if (mips_pic
== NO_PIC
11076 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11077 && (fixP
->fx_frag
->fr_address
11078 < text_section
->vma
+ bfd_get_section_size (text_section
))
11079 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11080 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11081 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11083 /* The branch offset is too large. If this is an
11084 unconditional branch, and we are not generating PIC code,
11085 we can convert it to an absolute jump instruction. */
11086 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11087 insn
= 0x0c000000; /* jal */
11089 insn
= 0x08000000; /* j */
11090 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11092 fixP
->fx_addsy
= section_symbol (text_section
);
11093 *valP
+= md_pcrel_from (fixP
);
11094 md_number_to_chars ((char *) buf
, insn
, 4);
11098 /* If we got here, we have branch-relaxation disabled,
11099 and there's nothing we can do to fix this instruction
11100 without turning it into a longer sequence. */
11101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11102 _("Branch out of range"));
11106 case BFD_RELOC_VTABLE_INHERIT
:
11109 && !S_IS_DEFINED (fixP
->fx_addsy
)
11110 && !S_IS_WEAK (fixP
->fx_addsy
))
11111 S_SET_WEAK (fixP
->fx_addsy
);
11114 case BFD_RELOC_VTABLE_ENTRY
:
11122 /* Remember value for tc_gen_reloc. */
11123 fixP
->fx_addnumber
= *valP
;
11133 name
= input_line_pointer
;
11134 c
= get_symbol_end ();
11135 p
= (symbolS
*) symbol_find_or_make (name
);
11136 *input_line_pointer
= c
;
11140 /* Align the current frag to a given power of two. The MIPS assembler
11141 also automatically adjusts any preceding label. */
11144 mips_align (int to
, int fill
, symbolS
*label
)
11146 mips_emit_delays (FALSE
);
11147 frag_align (to
, fill
, 0);
11148 record_alignment (now_seg
, to
);
11151 assert (S_GET_SEGMENT (label
) == now_seg
);
11152 symbol_set_frag (label
, frag_now
);
11153 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11157 /* Align to a given power of two. .align 0 turns off the automatic
11158 alignment used by the data creating pseudo-ops. */
11161 s_align (int x ATTRIBUTE_UNUSED
)
11164 register long temp_fill
;
11165 long max_alignment
= 15;
11169 o Note that the assembler pulls down any immediately preceding label
11170 to the aligned address.
11171 o It's not documented but auto alignment is reinstated by
11172 a .align pseudo instruction.
11173 o Note also that after auto alignment is turned off the mips assembler
11174 issues an error on attempt to assemble an improperly aligned data item.
11179 temp
= get_absolute_expression ();
11180 if (temp
> max_alignment
)
11181 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11184 as_warn (_("Alignment negative: 0 assumed."));
11187 if (*input_line_pointer
== ',')
11189 ++input_line_pointer
;
11190 temp_fill
= get_absolute_expression ();
11197 mips_align (temp
, (int) temp_fill
,
11198 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11205 demand_empty_rest_of_line ();
11209 mips_flush_pending_output (void)
11211 mips_emit_delays (FALSE
);
11212 mips_clear_insn_labels ();
11216 s_change_sec (int sec
)
11221 /* The ELF backend needs to know that we are changing sections, so
11222 that .previous works correctly. We could do something like check
11223 for an obj_section_change_hook macro, but that might be confusing
11224 as it would not be appropriate to use it in the section changing
11225 functions in read.c, since obj-elf.c intercepts those. FIXME:
11226 This should be cleaner, somehow. */
11227 obj_elf_section_change_hook ();
11230 mips_emit_delays (FALSE
);
11240 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11241 demand_empty_rest_of_line ();
11245 seg
= subseg_new (RDATA_SECTION_NAME
,
11246 (subsegT
) get_absolute_expression ());
11247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11249 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11250 | SEC_READONLY
| SEC_RELOC
11252 if (strcmp (TARGET_OS
, "elf") != 0)
11253 record_alignment (seg
, 4);
11255 demand_empty_rest_of_line ();
11259 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11260 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11262 bfd_set_section_flags (stdoutput
, seg
,
11263 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11264 if (strcmp (TARGET_OS
, "elf") != 0)
11265 record_alignment (seg
, 4);
11267 demand_empty_rest_of_line ();
11275 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11278 char *section_name
;
11283 int section_entry_size
;
11284 int section_alignment
;
11286 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11289 section_name
= input_line_pointer
;
11290 c
= get_symbol_end ();
11292 next_c
= *(input_line_pointer
+ 1);
11294 /* Do we have .section Name<,"flags">? */
11295 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11297 /* just after name is now '\0'. */
11298 *input_line_pointer
= c
;
11299 input_line_pointer
= section_name
;
11300 obj_elf_section (ignore
);
11303 input_line_pointer
++;
11305 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11307 section_type
= get_absolute_expression ();
11310 if (*input_line_pointer
++ == ',')
11311 section_flag
= get_absolute_expression ();
11314 if (*input_line_pointer
++ == ',')
11315 section_entry_size
= get_absolute_expression ();
11317 section_entry_size
= 0;
11318 if (*input_line_pointer
++ == ',')
11319 section_alignment
= get_absolute_expression ();
11321 section_alignment
= 0;
11323 section_name
= xstrdup (section_name
);
11325 /* When using the generic form of .section (as implemented by obj-elf.c),
11326 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11327 traditionally had to fall back on the more common @progbits instead.
11329 There's nothing really harmful in this, since bfd will correct
11330 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11331 means that, for backwards compatibiltiy, the special_section entries
11332 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11334 Even so, we shouldn't force users of the MIPS .section syntax to
11335 incorrectly label the sections as SHT_PROGBITS. The best compromise
11336 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11337 generic type-checking code. */
11338 if (section_type
== SHT_MIPS_DWARF
)
11339 section_type
= SHT_PROGBITS
;
11341 obj_elf_change_section (section_name
, section_type
, section_flag
,
11342 section_entry_size
, 0, 0, 0);
11344 if (now_seg
->name
!= section_name
)
11345 free (section_name
);
11346 #endif /* OBJ_ELF */
11350 mips_enable_auto_align (void)
11356 s_cons (int log_size
)
11360 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11361 mips_emit_delays (FALSE
);
11362 if (log_size
> 0 && auto_align
)
11363 mips_align (log_size
, 0, label
);
11364 mips_clear_insn_labels ();
11365 cons (1 << log_size
);
11369 s_float_cons (int type
)
11373 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11375 mips_emit_delays (FALSE
);
11380 mips_align (3, 0, label
);
11382 mips_align (2, 0, label
);
11385 mips_clear_insn_labels ();
11390 /* Handle .globl. We need to override it because on Irix 5 you are
11393 where foo is an undefined symbol, to mean that foo should be
11394 considered to be the address of a function. */
11397 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11404 name
= input_line_pointer
;
11405 c
= get_symbol_end ();
11406 symbolP
= symbol_find_or_make (name
);
11407 *input_line_pointer
= c
;
11408 SKIP_WHITESPACE ();
11410 /* On Irix 5, every global symbol that is not explicitly labelled as
11411 being a function is apparently labelled as being an object. */
11414 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11419 secname
= input_line_pointer
;
11420 c
= get_symbol_end ();
11421 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11423 as_bad (_("%s: no such section"), secname
);
11424 *input_line_pointer
= c
;
11426 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11427 flag
= BSF_FUNCTION
;
11430 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11432 S_SET_EXTERNAL (symbolP
);
11433 demand_empty_rest_of_line ();
11437 s_option (int x ATTRIBUTE_UNUSED
)
11442 opt
= input_line_pointer
;
11443 c
= get_symbol_end ();
11447 /* FIXME: What does this mean? */
11449 else if (strncmp (opt
, "pic", 3) == 0)
11453 i
= atoi (opt
+ 3);
11458 mips_pic
= SVR4_PIC
;
11459 mips_abicalls
= TRUE
;
11462 as_bad (_(".option pic%d not supported"), i
);
11464 if (mips_pic
== SVR4_PIC
)
11466 if (g_switch_seen
&& g_switch_value
!= 0)
11467 as_warn (_("-G may not be used with SVR4 PIC code"));
11468 g_switch_value
= 0;
11469 bfd_set_gp_size (stdoutput
, 0);
11473 as_warn (_("Unrecognized option \"%s\""), opt
);
11475 *input_line_pointer
= c
;
11476 demand_empty_rest_of_line ();
11479 /* This structure is used to hold a stack of .set values. */
11481 struct mips_option_stack
11483 struct mips_option_stack
*next
;
11484 struct mips_set_options options
;
11487 static struct mips_option_stack
*mips_opts_stack
;
11489 /* Handle the .set pseudo-op. */
11492 s_mipsset (int x ATTRIBUTE_UNUSED
)
11494 char *name
= input_line_pointer
, ch
;
11496 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11497 ++input_line_pointer
;
11498 ch
= *input_line_pointer
;
11499 *input_line_pointer
= '\0';
11501 if (strcmp (name
, "reorder") == 0)
11503 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11505 /* If we still have pending nops, we can discard them. The
11506 usual nop handling will insert any that are still
11508 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11509 * (mips_opts
.mips16
? 2 : 4));
11510 prev_nop_frag
= NULL
;
11512 mips_opts
.noreorder
= 0;
11514 else if (strcmp (name
, "noreorder") == 0)
11516 mips_emit_delays (TRUE
);
11517 mips_opts
.noreorder
= 1;
11518 mips_any_noreorder
= 1;
11520 else if (strcmp (name
, "at") == 0)
11522 mips_opts
.noat
= 0;
11524 else if (strcmp (name
, "noat") == 0)
11526 mips_opts
.noat
= 1;
11528 else if (strcmp (name
, "macro") == 0)
11530 mips_opts
.warn_about_macros
= 0;
11532 else if (strcmp (name
, "nomacro") == 0)
11534 if (mips_opts
.noreorder
== 0)
11535 as_bad (_("`noreorder' must be set before `nomacro'"));
11536 mips_opts
.warn_about_macros
= 1;
11538 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11540 mips_opts
.nomove
= 0;
11542 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11544 mips_opts
.nomove
= 1;
11546 else if (strcmp (name
, "bopt") == 0)
11548 mips_opts
.nobopt
= 0;
11550 else if (strcmp (name
, "nobopt") == 0)
11552 mips_opts
.nobopt
= 1;
11554 else if (strcmp (name
, "mips16") == 0
11555 || strcmp (name
, "MIPS-16") == 0)
11556 mips_opts
.mips16
= 1;
11557 else if (strcmp (name
, "nomips16") == 0
11558 || strcmp (name
, "noMIPS-16") == 0)
11559 mips_opts
.mips16
= 0;
11560 else if (strcmp (name
, "mips3d") == 0)
11561 mips_opts
.ase_mips3d
= 1;
11562 else if (strcmp (name
, "nomips3d") == 0)
11563 mips_opts
.ase_mips3d
= 0;
11564 else if (strcmp (name
, "mdmx") == 0)
11565 mips_opts
.ase_mdmx
= 1;
11566 else if (strcmp (name
, "nomdmx") == 0)
11567 mips_opts
.ase_mdmx
= 0;
11568 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11572 /* Permit the user to change the ISA and architecture on the fly.
11573 Needless to say, misuse can cause serious problems. */
11574 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11577 mips_opts
.isa
= file_mips_isa
;
11578 mips_opts
.arch
= file_mips_arch
;
11580 else if (strncmp (name
, "arch=", 5) == 0)
11582 const struct mips_cpu_info
*p
;
11584 p
= mips_parse_cpu("internal use", name
+ 5);
11586 as_bad (_("unknown architecture %s"), name
+ 5);
11589 mips_opts
.arch
= p
->cpu
;
11590 mips_opts
.isa
= p
->isa
;
11593 else if (strncmp (name
, "mips", 4) == 0)
11595 const struct mips_cpu_info
*p
;
11597 p
= mips_parse_cpu("internal use", name
);
11599 as_bad (_("unknown ISA level %s"), name
+ 4);
11602 mips_opts
.arch
= p
->cpu
;
11603 mips_opts
.isa
= p
->isa
;
11607 as_bad (_("unknown ISA or architecture %s"), name
);
11609 switch (mips_opts
.isa
)
11617 mips_opts
.gp32
= 1;
11618 mips_opts
.fp32
= 1;
11625 mips_opts
.gp32
= 0;
11626 mips_opts
.fp32
= 0;
11629 as_bad (_("unknown ISA level %s"), name
+ 4);
11634 mips_opts
.gp32
= file_mips_gp32
;
11635 mips_opts
.fp32
= file_mips_fp32
;
11638 else if (strcmp (name
, "autoextend") == 0)
11639 mips_opts
.noautoextend
= 0;
11640 else if (strcmp (name
, "noautoextend") == 0)
11641 mips_opts
.noautoextend
= 1;
11642 else if (strcmp (name
, "push") == 0)
11644 struct mips_option_stack
*s
;
11646 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11647 s
->next
= mips_opts_stack
;
11648 s
->options
= mips_opts
;
11649 mips_opts_stack
= s
;
11651 else if (strcmp (name
, "pop") == 0)
11653 struct mips_option_stack
*s
;
11655 s
= mips_opts_stack
;
11657 as_bad (_(".set pop with no .set push"));
11660 /* If we're changing the reorder mode we need to handle
11661 delay slots correctly. */
11662 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11663 mips_emit_delays (TRUE
);
11664 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11666 if (prev_nop_frag
!= NULL
)
11668 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11669 * (mips_opts
.mips16
? 2 : 4));
11670 prev_nop_frag
= NULL
;
11674 mips_opts
= s
->options
;
11675 mips_opts_stack
= s
->next
;
11679 else if (strcmp (name
, "sym32") == 0)
11680 mips_opts
.sym32
= TRUE
;
11681 else if (strcmp (name
, "nosym32") == 0)
11682 mips_opts
.sym32
= FALSE
;
11685 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11687 *input_line_pointer
= ch
;
11688 demand_empty_rest_of_line ();
11691 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11692 .option pic2. It means to generate SVR4 PIC calls. */
11695 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11697 mips_pic
= SVR4_PIC
;
11698 mips_abicalls
= TRUE
;
11700 if (g_switch_seen
&& g_switch_value
!= 0)
11701 as_warn (_("-G may not be used with SVR4 PIC code"));
11702 g_switch_value
= 0;
11704 bfd_set_gp_size (stdoutput
, 0);
11705 demand_empty_rest_of_line ();
11708 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11709 PIC code. It sets the $gp register for the function based on the
11710 function address, which is in the register named in the argument.
11711 This uses a relocation against _gp_disp, which is handled specially
11712 by the linker. The result is:
11713 lui $gp,%hi(_gp_disp)
11714 addiu $gp,$gp,%lo(_gp_disp)
11715 addu $gp,$gp,.cpload argument
11716 The .cpload argument is normally $25 == $t9.
11718 The -mno-shared option changes this to:
11719 lui $gp,%hi(__gnu_local_gp)
11720 addiu $gp,$gp,%lo(__gnu_local_gp)
11721 and the argument is ignored. This saves an instruction, but the
11722 resulting code is not position independent; it uses an absolute
11723 address for __gnu_local_gp. Thus code assembled with -mno-shared
11724 can go into an ordinary executable, but not into a shared library. */
11727 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11733 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11734 .cpload is ignored. */
11735 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11741 /* .cpload should be in a .set noreorder section. */
11742 if (mips_opts
.noreorder
== 0)
11743 as_warn (_(".cpload not in noreorder section"));
11745 reg
= tc_get_register (0);
11747 /* If we need to produce a 64-bit address, we are better off using
11748 the default instruction sequence. */
11749 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
11751 ex
.X_op
= O_symbol
;
11752 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
11754 ex
.X_op_symbol
= NULL
;
11755 ex
.X_add_number
= 0;
11757 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11758 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11761 macro_build_lui (&ex
, mips_gp_register
);
11762 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11763 mips_gp_register
, BFD_RELOC_LO16
);
11765 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11766 mips_gp_register
, reg
);
11769 demand_empty_rest_of_line ();
11772 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11773 .cpsetup $reg1, offset|$reg2, label
11775 If offset is given, this results in:
11776 sd $gp, offset($sp)
11777 lui $gp, %hi(%neg(%gp_rel(label)))
11778 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11779 daddu $gp, $gp, $reg1
11781 If $reg2 is given, this results in:
11782 daddu $reg2, $gp, $0
11783 lui $gp, %hi(%neg(%gp_rel(label)))
11784 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11785 daddu $gp, $gp, $reg1
11786 $reg1 is normally $25 == $t9.
11788 The -mno-shared option replaces the last three instructions with
11790 addiu $gp,$gp,%lo(_gp)
11794 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11796 expressionS ex_off
;
11797 expressionS ex_sym
;
11800 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11801 We also need NewABI support. */
11802 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11808 reg1
= tc_get_register (0);
11809 SKIP_WHITESPACE ();
11810 if (*input_line_pointer
!= ',')
11812 as_bad (_("missing argument separator ',' for .cpsetup"));
11816 ++input_line_pointer
;
11817 SKIP_WHITESPACE ();
11818 if (*input_line_pointer
== '$')
11820 mips_cpreturn_register
= tc_get_register (0);
11821 mips_cpreturn_offset
= -1;
11825 mips_cpreturn_offset
= get_absolute_expression ();
11826 mips_cpreturn_register
= -1;
11828 SKIP_WHITESPACE ();
11829 if (*input_line_pointer
!= ',')
11831 as_bad (_("missing argument separator ',' for .cpsetup"));
11835 ++input_line_pointer
;
11836 SKIP_WHITESPACE ();
11837 expression (&ex_sym
);
11840 if (mips_cpreturn_register
== -1)
11842 ex_off
.X_op
= O_constant
;
11843 ex_off
.X_add_symbol
= NULL
;
11844 ex_off
.X_op_symbol
= NULL
;
11845 ex_off
.X_add_number
= mips_cpreturn_offset
;
11847 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11848 BFD_RELOC_LO16
, SP
);
11851 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11852 mips_gp_register
, 0);
11854 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
11856 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11857 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11860 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11861 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11862 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11864 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11865 mips_gp_register
, reg1
);
11871 ex
.X_op
= O_symbol
;
11872 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11873 ex
.X_op_symbol
= NULL
;
11874 ex
.X_add_number
= 0;
11876 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11877 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11879 macro_build_lui (&ex
, mips_gp_register
);
11880 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11881 mips_gp_register
, BFD_RELOC_LO16
);
11886 demand_empty_rest_of_line ();
11890 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11892 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11893 .cplocal is ignored. */
11894 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11900 mips_gp_register
= tc_get_register (0);
11901 demand_empty_rest_of_line ();
11904 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11905 offset from $sp. The offset is remembered, and after making a PIC
11906 call $gp is restored from that location. */
11909 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11913 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11914 .cprestore is ignored. */
11915 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11921 mips_cprestore_offset
= get_absolute_expression ();
11922 mips_cprestore_valid
= 1;
11924 ex
.X_op
= O_constant
;
11925 ex
.X_add_symbol
= NULL
;
11926 ex
.X_op_symbol
= NULL
;
11927 ex
.X_add_number
= mips_cprestore_offset
;
11930 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
11931 SP
, HAVE_64BIT_ADDRESSES
);
11934 demand_empty_rest_of_line ();
11937 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11938 was given in the preceding .cpsetup, it results in:
11939 ld $gp, offset($sp)
11941 If a register $reg2 was given there, it results in:
11942 daddu $gp, $reg2, $0
11945 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
11949 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11950 We also need NewABI support. */
11951 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11958 if (mips_cpreturn_register
== -1)
11960 ex
.X_op
= O_constant
;
11961 ex
.X_add_symbol
= NULL
;
11962 ex
.X_op_symbol
= NULL
;
11963 ex
.X_add_number
= mips_cpreturn_offset
;
11965 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
11968 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
11969 mips_cpreturn_register
, 0);
11972 demand_empty_rest_of_line ();
11975 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11976 code. It sets the offset to use in gp_rel relocations. */
11979 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
11981 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11982 We also need NewABI support. */
11983 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11989 mips_gprel_offset
= get_absolute_expression ();
11991 demand_empty_rest_of_line ();
11994 /* Handle the .gpword pseudo-op. This is used when generating PIC
11995 code. It generates a 32 bit GP relative reloc. */
11998 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12004 /* When not generating PIC code, this is treated as .word. */
12005 if (mips_pic
!= SVR4_PIC
)
12011 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12012 mips_emit_delays (TRUE
);
12014 mips_align (2, 0, label
);
12015 mips_clear_insn_labels ();
12019 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12021 as_bad (_("Unsupported use of .gpword"));
12022 ignore_rest_of_line ();
12026 md_number_to_chars (p
, 0, 4);
12027 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12028 BFD_RELOC_GPREL32
);
12030 demand_empty_rest_of_line ();
12034 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12040 /* When not generating PIC code, this is treated as .dword. */
12041 if (mips_pic
!= SVR4_PIC
)
12047 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12048 mips_emit_delays (TRUE
);
12050 mips_align (3, 0, label
);
12051 mips_clear_insn_labels ();
12055 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12057 as_bad (_("Unsupported use of .gpdword"));
12058 ignore_rest_of_line ();
12062 md_number_to_chars (p
, 0, 8);
12063 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12064 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12066 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12067 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12068 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12070 demand_empty_rest_of_line ();
12073 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12074 tables in SVR4 PIC code. */
12077 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12081 /* This is ignored when not generating SVR4 PIC code. */
12082 if (mips_pic
!= SVR4_PIC
)
12088 /* Add $gp to the register named as an argument. */
12090 reg
= tc_get_register (0);
12091 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12094 demand_empty_rest_of_line ();
12097 /* Handle the .insn pseudo-op. This marks instruction labels in
12098 mips16 mode. This permits the linker to handle them specially,
12099 such as generating jalx instructions when needed. We also make
12100 them odd for the duration of the assembly, in order to generate the
12101 right sort of code. We will make them even in the adjust_symtab
12102 routine, while leaving them marked. This is convenient for the
12103 debugger and the disassembler. The linker knows to make them odd
12107 s_insn (int ignore ATTRIBUTE_UNUSED
)
12109 mips16_mark_labels ();
12111 demand_empty_rest_of_line ();
12114 /* Handle a .stabn directive. We need these in order to mark a label
12115 as being a mips16 text label correctly. Sometimes the compiler
12116 will emit a label, followed by a .stabn, and then switch sections.
12117 If the label and .stabn are in mips16 mode, then the label is
12118 really a mips16 text label. */
12121 s_mips_stab (int type
)
12124 mips16_mark_labels ();
12129 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12133 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12140 name
= input_line_pointer
;
12141 c
= get_symbol_end ();
12142 symbolP
= symbol_find_or_make (name
);
12143 S_SET_WEAK (symbolP
);
12144 *input_line_pointer
= c
;
12146 SKIP_WHITESPACE ();
12148 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12150 if (S_IS_DEFINED (symbolP
))
12152 as_bad ("ignoring attempt to redefine symbol %s",
12153 S_GET_NAME (symbolP
));
12154 ignore_rest_of_line ();
12158 if (*input_line_pointer
== ',')
12160 ++input_line_pointer
;
12161 SKIP_WHITESPACE ();
12165 if (exp
.X_op
!= O_symbol
)
12167 as_bad ("bad .weakext directive");
12168 ignore_rest_of_line ();
12171 symbol_set_value_expression (symbolP
, &exp
);
12174 demand_empty_rest_of_line ();
12177 /* Parse a register string into a number. Called from the ECOFF code
12178 to parse .frame. The argument is non-zero if this is the frame
12179 register, so that we can record it in mips_frame_reg. */
12182 tc_get_register (int frame
)
12186 SKIP_WHITESPACE ();
12187 if (*input_line_pointer
++ != '$')
12189 as_warn (_("expected `$'"));
12192 else if (ISDIGIT (*input_line_pointer
))
12194 reg
= get_absolute_expression ();
12195 if (reg
< 0 || reg
>= 32)
12197 as_warn (_("Bad register number"));
12203 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12206 input_line_pointer
+= 2;
12208 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12211 input_line_pointer
+= 2;
12213 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12216 input_line_pointer
+= 2;
12218 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12221 input_line_pointer
+= 2;
12223 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12226 input_line_pointer
+= 2;
12228 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12231 input_line_pointer
+= 3;
12233 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12236 input_line_pointer
+= 3;
12238 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12241 input_line_pointer
+= 4;
12245 as_warn (_("Unrecognized register name"));
12247 while (ISALNUM(*input_line_pointer
))
12248 input_line_pointer
++;
12253 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12254 mips_frame_reg_valid
= 1;
12255 mips_cprestore_valid
= 0;
12261 md_section_align (asection
*seg
, valueT addr
)
12263 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12266 /* We don't need to align ELF sections to the full alignment.
12267 However, Irix 5 may prefer that we align them at least to a 16
12268 byte boundary. We don't bother to align the sections if we are
12269 targeted for an embedded system. */
12270 if (strcmp (TARGET_OS
, "elf") == 0)
12276 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12279 /* Utility routine, called from above as well. If called while the
12280 input file is still being read, it's only an approximation. (For
12281 example, a symbol may later become defined which appeared to be
12282 undefined earlier.) */
12285 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12290 if (g_switch_value
> 0)
12292 const char *symname
;
12295 /* Find out whether this symbol can be referenced off the $gp
12296 register. It can be if it is smaller than the -G size or if
12297 it is in the .sdata or .sbss section. Certain symbols can
12298 not be referenced off the $gp, although it appears as though
12300 symname
= S_GET_NAME (sym
);
12301 if (symname
!= (const char *) NULL
12302 && (strcmp (symname
, "eprol") == 0
12303 || strcmp (symname
, "etext") == 0
12304 || strcmp (symname
, "_gp") == 0
12305 || strcmp (symname
, "edata") == 0
12306 || strcmp (symname
, "_fbss") == 0
12307 || strcmp (symname
, "_fdata") == 0
12308 || strcmp (symname
, "_ftext") == 0
12309 || strcmp (symname
, "end") == 0
12310 || strcmp (symname
, "_gp_disp") == 0))
12312 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12314 #ifndef NO_ECOFF_DEBUGGING
12315 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12316 && (symbol_get_obj (sym
)->ecoff_extern_size
12317 <= g_switch_value
))
12319 /* We must defer this decision until after the whole
12320 file has been read, since there might be a .extern
12321 after the first use of this symbol. */
12322 || (before_relaxing
12323 #ifndef NO_ECOFF_DEBUGGING
12324 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12326 && S_GET_VALUE (sym
) == 0)
12327 || (S_GET_VALUE (sym
) != 0
12328 && S_GET_VALUE (sym
) <= g_switch_value
)))
12332 const char *segname
;
12334 segname
= segment_name (S_GET_SEGMENT (sym
));
12335 assert (strcmp (segname
, ".lit8") != 0
12336 && strcmp (segname
, ".lit4") != 0);
12337 change
= (strcmp (segname
, ".sdata") != 0
12338 && strcmp (segname
, ".sbss") != 0
12339 && strncmp (segname
, ".sdata.", 7) != 0
12340 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12345 /* We are not optimizing for the $gp register. */
12350 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12353 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12356 bfd_boolean linkonce
;
12358 /* Handle the case of a symbol equated to another symbol. */
12359 while (symbol_equated_reloc_p (sym
))
12363 /* It's possible to get a loop here in a badly written
12365 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12371 symsec
= S_GET_SEGMENT (sym
);
12373 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12375 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12377 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12381 /* The GNU toolchain uses an extension for ELF: a section
12382 beginning with the magic string .gnu.linkonce is a linkonce
12384 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12385 sizeof ".gnu.linkonce" - 1) == 0)
12389 /* This must duplicate the test in adjust_reloc_syms. */
12390 return (symsec
!= &bfd_und_section
12391 && symsec
!= &bfd_abs_section
12392 && ! bfd_is_com_section (symsec
)
12395 /* A global or weak symbol is treated as external. */
12396 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12397 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12403 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12404 extended opcode. SEC is the section the frag is in. */
12407 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12410 register const struct mips16_immed_operand
*op
;
12412 int mintiny
, maxtiny
;
12416 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12418 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12421 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12422 op
= mips16_immed_operands
;
12423 while (op
->type
!= type
)
12426 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12431 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12434 maxtiny
= 1 << op
->nbits
;
12439 maxtiny
= (1 << op
->nbits
) - 1;
12444 mintiny
= - (1 << (op
->nbits
- 1));
12445 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12448 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12449 val
= S_GET_VALUE (fragp
->fr_symbol
);
12450 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12456 /* We won't have the section when we are called from
12457 mips_relax_frag. However, we will always have been called
12458 from md_estimate_size_before_relax first. If this is a
12459 branch to a different section, we mark it as such. If SEC is
12460 NULL, and the frag is not marked, then it must be a branch to
12461 the same section. */
12464 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12469 /* Must have been called from md_estimate_size_before_relax. */
12472 fragp
->fr_subtype
=
12473 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12475 /* FIXME: We should support this, and let the linker
12476 catch branches and loads that are out of range. */
12477 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12478 _("unsupported PC relative reference to different section"));
12482 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12483 /* Assume non-extended on the first relaxation pass.
12484 The address we have calculated will be bogus if this is
12485 a forward branch to another frag, as the forward frag
12486 will have fr_address == 0. */
12490 /* In this case, we know for sure that the symbol fragment is in
12491 the same section. If the relax_marker of the symbol fragment
12492 differs from the relax_marker of this fragment, we have not
12493 yet adjusted the symbol fragment fr_address. We want to add
12494 in STRETCH in order to get a better estimate of the address.
12495 This particularly matters because of the shift bits. */
12497 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12501 /* Adjust stretch for any alignment frag. Note that if have
12502 been expanding the earlier code, the symbol may be
12503 defined in what appears to be an earlier frag. FIXME:
12504 This doesn't handle the fr_subtype field, which specifies
12505 a maximum number of bytes to skip when doing an
12507 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12509 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12512 stretch
= - ((- stretch
)
12513 & ~ ((1 << (int) f
->fr_offset
) - 1));
12515 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12524 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12526 /* The base address rules are complicated. The base address of
12527 a branch is the following instruction. The base address of a
12528 PC relative load or add is the instruction itself, but if it
12529 is in a delay slot (in which case it can not be extended) use
12530 the address of the instruction whose delay slot it is in. */
12531 if (type
== 'p' || type
== 'q')
12535 /* If we are currently assuming that this frag should be
12536 extended, then, the current address is two bytes
12538 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12541 /* Ignore the low bit in the target, since it will be set
12542 for a text label. */
12543 if ((val
& 1) != 0)
12546 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12548 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12551 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12553 /* Branch offsets have an implicit 0 in the lowest bit. */
12554 if (type
== 'p' || type
== 'q')
12557 /* If any of the shifted bits are set, we must use an extended
12558 opcode. If the address depends on the size of this
12559 instruction, this can lead to a loop, so we arrange to always
12560 use an extended opcode. We only check this when we are in
12561 the main relaxation loop, when SEC is NULL. */
12562 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12564 fragp
->fr_subtype
=
12565 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12569 /* If we are about to mark a frag as extended because the value
12570 is precisely maxtiny + 1, then there is a chance of an
12571 infinite loop as in the following code:
12576 In this case when the la is extended, foo is 0x3fc bytes
12577 away, so the la can be shrunk, but then foo is 0x400 away, so
12578 the la must be extended. To avoid this loop, we mark the
12579 frag as extended if it was small, and is about to become
12580 extended with a value of maxtiny + 1. */
12581 if (val
== ((maxtiny
+ 1) << op
->shift
)
12582 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12585 fragp
->fr_subtype
=
12586 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12590 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12591 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12593 if ((val
& ((1 << op
->shift
) - 1)) != 0
12594 || val
< (mintiny
<< op
->shift
)
12595 || val
> (maxtiny
<< op
->shift
))
12601 /* Compute the length of a branch sequence, and adjust the
12602 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12603 worst-case length is computed, with UPDATE being used to indicate
12604 whether an unconditional (-1), branch-likely (+1) or regular (0)
12605 branch is to be computed. */
12607 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12609 bfd_boolean toofar
;
12613 && S_IS_DEFINED (fragp
->fr_symbol
)
12614 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12619 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12621 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12625 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12628 /* If the symbol is not defined or it's in a different segment,
12629 assume the user knows what's going on and emit a short
12635 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12637 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12638 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12639 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12645 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12648 if (mips_pic
!= NO_PIC
)
12650 /* Additional space for PIC loading of target address. */
12652 if (mips_opts
.isa
== ISA_MIPS1
)
12653 /* Additional space for $at-stabilizing nop. */
12657 /* If branch is conditional. */
12658 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12665 /* Estimate the size of a frag before relaxing. Unless this is the
12666 mips16, we are not really relaxing here, and the final size is
12667 encoded in the subtype information. For the mips16, we have to
12668 decide whether we are using an extended opcode or not. */
12671 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12675 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12678 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12680 return fragp
->fr_var
;
12683 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12684 /* We don't want to modify the EXTENDED bit here; it might get us
12685 into infinite loops. We change it only in mips_relax_frag(). */
12686 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12688 if (mips_pic
== NO_PIC
)
12689 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12690 else if (mips_pic
== SVR4_PIC
)
12691 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12697 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12698 return -RELAX_FIRST (fragp
->fr_subtype
);
12701 return -RELAX_SECOND (fragp
->fr_subtype
);
12704 /* This is called to see whether a reloc against a defined symbol
12705 should be converted into a reloc against a section. */
12708 mips_fix_adjustable (fixS
*fixp
)
12710 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12711 about the format of the offset in the .o file. */
12712 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12715 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12716 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12719 if (fixp
->fx_addsy
== NULL
)
12722 /* If symbol SYM is in a mergeable section, relocations of the form
12723 SYM + 0 can usually be made section-relative. The mergeable data
12724 is then identified by the section offset rather than by the symbol.
12726 However, if we're generating REL LO16 relocations, the offset is split
12727 between the LO16 and parterning high part relocation. The linker will
12728 need to recalculate the complete offset in order to correctly identify
12731 The linker has traditionally not looked for the parterning high part
12732 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12733 placed anywhere. Rather than break backwards compatibility by changing
12734 this, it seems better not to force the issue, and instead keep the
12735 original symbol. This will work with either linker behavior. */
12736 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12737 && HAVE_IN_PLACE_ADDENDS
12738 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12742 /* Don't adjust relocations against mips16 symbols, so that the linker
12743 can find them if it needs to set up a stub. */
12744 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12745 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12746 && fixp
->fx_subsy
== NULL
)
12753 /* Translate internal representation of relocation info to BFD target
12757 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12759 static arelent
*retval
[4];
12761 bfd_reloc_code_real_type code
;
12763 memset (retval
, 0, sizeof(retval
));
12764 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12765 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12766 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12767 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12769 assert (! fixp
->fx_pcrel
);
12770 reloc
->addend
= fixp
->fx_addnumber
;
12772 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12773 entry to be used in the relocation's section offset. */
12774 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12776 reloc
->address
= reloc
->addend
;
12780 code
= fixp
->fx_r_type
;
12782 /* To support a PC relative reloc, we used a Cygnus extension.
12783 We check for that here to make sure that we don't let such a
12784 reloc escape normally. (FIXME: This was formerly used by
12785 embedded-PIC support, but is now used by branch handling in
12786 general. That probably should be fixed.) */
12787 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12788 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12789 && code
== BFD_RELOC_16_PCREL_S2
)
12790 reloc
->howto
= NULL
;
12792 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12794 if (reloc
->howto
== NULL
)
12796 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12797 _("Can not represent %s relocation in this object file format"),
12798 bfd_get_reloc_code_name (code
));
12805 /* Relax a machine dependent frag. This returns the amount by which
12806 the current size of the frag should change. */
12809 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12811 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12813 offsetT old_var
= fragp
->fr_var
;
12815 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12817 return fragp
->fr_var
- old_var
;
12820 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12823 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12825 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12827 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12832 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12834 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12841 /* Convert a machine dependent frag. */
12844 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12846 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12849 unsigned long insn
;
12853 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12855 if (target_big_endian
)
12856 insn
= bfd_getb32 (buf
);
12858 insn
= bfd_getl32 (buf
);
12860 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12862 /* We generate a fixup instead of applying it right now
12863 because, if there are linker relaxations, we're going to
12864 need the relocations. */
12865 exp
.X_op
= O_symbol
;
12866 exp
.X_add_symbol
= fragp
->fr_symbol
;
12867 exp
.X_add_number
= fragp
->fr_offset
;
12869 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12871 BFD_RELOC_16_PCREL_S2
);
12872 fixp
->fx_file
= fragp
->fr_file
;
12873 fixp
->fx_line
= fragp
->fr_line
;
12875 md_number_to_chars ((char *) buf
, insn
, 4);
12882 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12883 _("relaxed out-of-range branch into a jump"));
12885 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12888 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12890 /* Reverse the branch. */
12891 switch ((insn
>> 28) & 0xf)
12894 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12895 have the condition reversed by tweaking a single
12896 bit, and their opcodes all have 0x4???????. */
12897 assert ((insn
& 0xf1000000) == 0x41000000);
12898 insn
^= 0x00010000;
12902 /* bltz 0x04000000 bgez 0x04010000
12903 bltzal 0x04100000 bgezal 0x04110000 */
12904 assert ((insn
& 0xfc0e0000) == 0x04000000);
12905 insn
^= 0x00010000;
12909 /* beq 0x10000000 bne 0x14000000
12910 blez 0x18000000 bgtz 0x1c000000 */
12911 insn
^= 0x04000000;
12919 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
12921 /* Clear the and-link bit. */
12922 assert ((insn
& 0xfc1c0000) == 0x04100000);
12924 /* bltzal 0x04100000 bgezal 0x04110000
12925 bltzall 0x04120000 bgezall 0x04130000 */
12926 insn
&= ~0x00100000;
12929 /* Branch over the branch (if the branch was likely) or the
12930 full jump (not likely case). Compute the offset from the
12931 current instruction to branch to. */
12932 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12936 /* How many bytes in instructions we've already emitted? */
12937 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12938 /* How many bytes in instructions from here to the end? */
12939 i
= fragp
->fr_var
- i
;
12941 /* Convert to instruction count. */
12943 /* Branch counts from the next instruction. */
12946 /* Branch over the jump. */
12947 md_number_to_chars ((char *) buf
, insn
, 4);
12951 md_number_to_chars ((char *) buf
, 0, 4);
12954 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12956 /* beql $0, $0, 2f */
12958 /* Compute the PC offset from the current instruction to
12959 the end of the variable frag. */
12960 /* How many bytes in instructions we've already emitted? */
12961 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
12962 /* How many bytes in instructions from here to the end? */
12963 i
= fragp
->fr_var
- i
;
12964 /* Convert to instruction count. */
12966 /* Don't decrement i, because we want to branch over the
12970 md_number_to_chars ((char *) buf
, insn
, 4);
12973 md_number_to_chars ((char *) buf
, 0, 4);
12978 if (mips_pic
== NO_PIC
)
12981 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
12982 ? 0x0c000000 : 0x08000000);
12983 exp
.X_op
= O_symbol
;
12984 exp
.X_add_symbol
= fragp
->fr_symbol
;
12985 exp
.X_add_number
= fragp
->fr_offset
;
12987 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12988 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
12989 fixp
->fx_file
= fragp
->fr_file
;
12990 fixp
->fx_line
= fragp
->fr_line
;
12992 md_number_to_chars ((char *) buf
, insn
, 4);
12997 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
12998 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
12999 exp
.X_op
= O_symbol
;
13000 exp
.X_add_symbol
= fragp
->fr_symbol
;
13001 exp
.X_add_number
= fragp
->fr_offset
;
13003 if (fragp
->fr_offset
)
13005 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13006 exp
.X_add_number
= 0;
13009 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13010 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13011 fixp
->fx_file
= fragp
->fr_file
;
13012 fixp
->fx_line
= fragp
->fr_line
;
13014 md_number_to_chars ((char *) buf
, insn
, 4);
13017 if (mips_opts
.isa
== ISA_MIPS1
)
13020 md_number_to_chars ((char *) buf
, 0, 4);
13024 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13025 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13027 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13028 4, &exp
, 0, BFD_RELOC_LO16
);
13029 fixp
->fx_file
= fragp
->fr_file
;
13030 fixp
->fx_line
= fragp
->fr_line
;
13032 md_number_to_chars ((char *) buf
, insn
, 4);
13036 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13041 md_number_to_chars ((char *) buf
, insn
, 4);
13046 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13047 + fragp
->fr_fix
+ fragp
->fr_var
);
13049 fragp
->fr_fix
+= fragp
->fr_var
;
13054 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13057 register const struct mips16_immed_operand
*op
;
13058 bfd_boolean small
, ext
;
13061 unsigned long insn
;
13062 bfd_boolean use_extend
;
13063 unsigned short extend
;
13065 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13066 op
= mips16_immed_operands
;
13067 while (op
->type
!= type
)
13070 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13081 resolve_symbol_value (fragp
->fr_symbol
);
13082 val
= S_GET_VALUE (fragp
->fr_symbol
);
13087 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13089 /* The rules for the base address of a PC relative reloc are
13090 complicated; see mips16_extended_frag. */
13091 if (type
== 'p' || type
== 'q')
13096 /* Ignore the low bit in the target, since it will be
13097 set for a text label. */
13098 if ((val
& 1) != 0)
13101 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13103 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13106 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13109 /* Make sure the section winds up with the alignment we have
13112 record_alignment (asec
, op
->shift
);
13116 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13117 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13118 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13119 _("extended instruction in delay slot"));
13121 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13123 if (target_big_endian
)
13124 insn
= bfd_getb16 (buf
);
13126 insn
= bfd_getl16 (buf
);
13128 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13129 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13130 small
, ext
, &insn
, &use_extend
, &extend
);
13134 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13135 fragp
->fr_fix
+= 2;
13139 md_number_to_chars ((char *) buf
, insn
, 2);
13140 fragp
->fr_fix
+= 2;
13148 first
= RELAX_FIRST (fragp
->fr_subtype
);
13149 second
= RELAX_SECOND (fragp
->fr_subtype
);
13150 fixp
= (fixS
*) fragp
->fr_opcode
;
13152 /* Possibly emit a warning if we've chosen the longer option. */
13153 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13154 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13156 const char *msg
= macro_warning (fragp
->fr_subtype
);
13158 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13161 /* Go through all the fixups for the first sequence. Disable them
13162 (by marking them as done) if we're going to use the second
13163 sequence instead. */
13165 && fixp
->fx_frag
== fragp
13166 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13168 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13170 fixp
= fixp
->fx_next
;
13173 /* Go through the fixups for the second sequence. Disable them if
13174 we're going to use the first sequence, otherwise adjust their
13175 addresses to account for the relaxation. */
13176 while (fixp
&& fixp
->fx_frag
== fragp
)
13178 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13179 fixp
->fx_where
-= first
;
13182 fixp
= fixp
->fx_next
;
13185 /* Now modify the frag contents. */
13186 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13190 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13191 memmove (start
, start
+ first
, second
);
13192 fragp
->fr_fix
-= first
;
13195 fragp
->fr_fix
-= second
;
13201 /* This function is called after the relocs have been generated.
13202 We've been storing mips16 text labels as odd. Here we convert them
13203 back to even for the convenience of the debugger. */
13206 mips_frob_file_after_relocs (void)
13209 unsigned int count
, i
;
13211 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13214 syms
= bfd_get_outsymbols (stdoutput
);
13215 count
= bfd_get_symcount (stdoutput
);
13216 for (i
= 0; i
< count
; i
++, syms
++)
13218 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13219 && ((*syms
)->value
& 1) != 0)
13221 (*syms
)->value
&= ~1;
13222 /* If the symbol has an odd size, it was probably computed
13223 incorrectly, so adjust that as well. */
13224 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13225 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13232 /* This function is called whenever a label is defined. It is used
13233 when handling branch delays; if a branch has a label, we assume we
13234 can not move it. */
13237 mips_define_label (symbolS
*sym
)
13239 struct insn_label_list
*l
;
13241 if (free_insn_labels
== NULL
)
13242 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13245 l
= free_insn_labels
;
13246 free_insn_labels
= l
->next
;
13250 l
->next
= insn_labels
;
13254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13256 /* Some special processing for a MIPS ELF file. */
13259 mips_elf_final_processing (void)
13261 /* Write out the register information. */
13262 if (mips_abi
!= N64_ABI
)
13266 s
.ri_gprmask
= mips_gprmask
;
13267 s
.ri_cprmask
[0] = mips_cprmask
[0];
13268 s
.ri_cprmask
[1] = mips_cprmask
[1];
13269 s
.ri_cprmask
[2] = mips_cprmask
[2];
13270 s
.ri_cprmask
[3] = mips_cprmask
[3];
13271 /* The gp_value field is set by the MIPS ELF backend. */
13273 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13274 ((Elf32_External_RegInfo
*)
13275 mips_regmask_frag
));
13279 Elf64_Internal_RegInfo s
;
13281 s
.ri_gprmask
= mips_gprmask
;
13283 s
.ri_cprmask
[0] = mips_cprmask
[0];
13284 s
.ri_cprmask
[1] = mips_cprmask
[1];
13285 s
.ri_cprmask
[2] = mips_cprmask
[2];
13286 s
.ri_cprmask
[3] = mips_cprmask
[3];
13287 /* The gp_value field is set by the MIPS ELF backend. */
13289 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13290 ((Elf64_External_RegInfo
*)
13291 mips_regmask_frag
));
13294 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13295 sort of BFD interface for this. */
13296 if (mips_any_noreorder
)
13297 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13298 if (mips_pic
!= NO_PIC
)
13300 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13301 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13304 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13306 /* Set MIPS ELF flags for ASEs. */
13307 if (file_ase_mips16
)
13308 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13309 #if 0 /* XXX FIXME */
13310 if (file_ase_mips3d
)
13311 elf_elfheader (stdoutput
)->e_flags
|= ???;
13314 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13316 /* Set the MIPS ELF ABI flags. */
13317 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13318 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13319 else if (mips_abi
== O64_ABI
)
13320 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13321 else if (mips_abi
== EABI_ABI
)
13323 if (!file_mips_gp32
)
13324 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13326 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13328 else if (mips_abi
== N32_ABI
)
13329 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13331 /* Nothing to do for N64_ABI. */
13333 if (mips_32bitmode
)
13334 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13337 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13339 typedef struct proc
{
13341 symbolS
*func_end_sym
;
13342 unsigned long reg_mask
;
13343 unsigned long reg_offset
;
13344 unsigned long fpreg_mask
;
13345 unsigned long fpreg_offset
;
13346 unsigned long frame_offset
;
13347 unsigned long frame_reg
;
13348 unsigned long pc_reg
;
13351 static procS cur_proc
;
13352 static procS
*cur_proc_ptr
;
13353 static int numprocs
;
13355 /* Fill in an rs_align_code fragment. */
13358 mips_handle_align (fragS
*fragp
)
13360 if (fragp
->fr_type
!= rs_align_code
)
13363 if (mips_opts
.mips16
)
13365 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13366 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13371 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13372 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13380 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13384 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13388 md_obj_begin (void)
13395 /* check for premature end, nesting errors, etc */
13397 as_warn (_("missing .end at end of assembly"));
13406 if (*input_line_pointer
== '-')
13408 ++input_line_pointer
;
13411 if (!ISDIGIT (*input_line_pointer
))
13412 as_bad (_("expected simple number"));
13413 if (input_line_pointer
[0] == '0')
13415 if (input_line_pointer
[1] == 'x')
13417 input_line_pointer
+= 2;
13418 while (ISXDIGIT (*input_line_pointer
))
13421 val
|= hex_value (*input_line_pointer
++);
13423 return negative
? -val
: val
;
13427 ++input_line_pointer
;
13428 while (ISDIGIT (*input_line_pointer
))
13431 val
|= *input_line_pointer
++ - '0';
13433 return negative
? -val
: val
;
13436 if (!ISDIGIT (*input_line_pointer
))
13438 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13439 *input_line_pointer
, *input_line_pointer
);
13440 as_warn (_("invalid number"));
13443 while (ISDIGIT (*input_line_pointer
))
13446 val
+= *input_line_pointer
++ - '0';
13448 return negative
? -val
: val
;
13451 /* The .file directive; just like the usual .file directive, but there
13452 is an initial number which is the ECOFF file index. In the non-ECOFF
13453 case .file implies DWARF-2. */
13456 s_mips_file (int x ATTRIBUTE_UNUSED
)
13458 static int first_file_directive
= 0;
13460 if (ECOFF_DEBUGGING
)
13469 filename
= dwarf2_directive_file (0);
13471 /* Versions of GCC up to 3.1 start files with a ".file"
13472 directive even for stabs output. Make sure that this
13473 ".file" is handled. Note that you need a version of GCC
13474 after 3.1 in order to support DWARF-2 on MIPS. */
13475 if (filename
!= NULL
&& ! first_file_directive
)
13477 (void) new_logical_line (filename
, -1);
13478 s_app_file_string (filename
, 0);
13480 first_file_directive
= 1;
13484 /* The .loc directive, implying DWARF-2. */
13487 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13489 if (!ECOFF_DEBUGGING
)
13490 dwarf2_directive_loc (0);
13493 /* The .end directive. */
13496 s_mips_end (int x ATTRIBUTE_UNUSED
)
13500 /* Following functions need their own .frame and .cprestore directives. */
13501 mips_frame_reg_valid
= 0;
13502 mips_cprestore_valid
= 0;
13504 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13507 demand_empty_rest_of_line ();
13512 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13513 as_warn (_(".end not in text section"));
13517 as_warn (_(".end directive without a preceding .ent directive."));
13518 demand_empty_rest_of_line ();
13524 assert (S_GET_NAME (p
));
13525 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
13526 as_warn (_(".end symbol does not match .ent symbol."));
13528 if (debug_type
== DEBUG_STABS
)
13529 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13533 as_warn (_(".end directive missing or unknown symbol"));
13536 /* Create an expression to calculate the size of the function. */
13537 if (p
&& cur_proc_ptr
)
13539 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
13540 expressionS
*exp
= xmalloc (sizeof (expressionS
));
13543 exp
->X_op
= O_subtract
;
13544 exp
->X_add_symbol
= symbol_temp_new_now ();
13545 exp
->X_op_symbol
= p
;
13546 exp
->X_add_number
= 0;
13548 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
13551 /* Generate a .pdr section. */
13552 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13555 segT saved_seg
= now_seg
;
13556 subsegT saved_subseg
= now_subseg
;
13561 dot
= frag_now_fix ();
13563 #ifdef md_flush_pending_output
13564 md_flush_pending_output ();
13568 subseg_set (pdr_seg
, 0);
13570 /* Write the symbol. */
13571 exp
.X_op
= O_symbol
;
13572 exp
.X_add_symbol
= p
;
13573 exp
.X_add_number
= 0;
13574 emit_expr (&exp
, 4);
13576 fragp
= frag_more (7 * 4);
13578 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13579 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13580 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13581 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13582 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13583 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13584 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13586 subseg_set (saved_seg
, saved_subseg
);
13588 #endif /* OBJ_ELF */
13590 cur_proc_ptr
= NULL
;
13593 /* The .aent and .ent directives. */
13596 s_mips_ent (int aent
)
13600 symbolP
= get_symbol ();
13601 if (*input_line_pointer
== ',')
13602 ++input_line_pointer
;
13603 SKIP_WHITESPACE ();
13604 if (ISDIGIT (*input_line_pointer
)
13605 || *input_line_pointer
== '-')
13608 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13609 as_warn (_(".ent or .aent not in text section."));
13611 if (!aent
&& cur_proc_ptr
)
13612 as_warn (_("missing .end"));
13616 /* This function needs its own .frame and .cprestore directives. */
13617 mips_frame_reg_valid
= 0;
13618 mips_cprestore_valid
= 0;
13620 cur_proc_ptr
= &cur_proc
;
13621 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13623 cur_proc_ptr
->func_sym
= symbolP
;
13625 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13629 if (debug_type
== DEBUG_STABS
)
13630 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13631 S_GET_NAME (symbolP
));
13634 demand_empty_rest_of_line ();
13637 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13638 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13639 s_mips_frame is used so that we can set the PDR information correctly.
13640 We can't use the ecoff routines because they make reference to the ecoff
13641 symbol table (in the mdebug section). */
13644 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13647 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13651 if (cur_proc_ptr
== (procS
*) NULL
)
13653 as_warn (_(".frame outside of .ent"));
13654 demand_empty_rest_of_line ();
13658 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13660 SKIP_WHITESPACE ();
13661 if (*input_line_pointer
++ != ','
13662 || get_absolute_expression_and_terminator (&val
) != ',')
13664 as_warn (_("Bad .frame directive"));
13665 --input_line_pointer
;
13666 demand_empty_rest_of_line ();
13670 cur_proc_ptr
->frame_offset
= val
;
13671 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13673 demand_empty_rest_of_line ();
13676 #endif /* OBJ_ELF */
13680 /* The .fmask and .mask directives. If the mdebug section is present
13681 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13682 embedded targets, s_mips_mask is used so that we can set the PDR
13683 information correctly. We can't use the ecoff routines because they
13684 make reference to the ecoff symbol table (in the mdebug section). */
13687 s_mips_mask (int reg_type
)
13690 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13694 if (cur_proc_ptr
== (procS
*) NULL
)
13696 as_warn (_(".mask/.fmask outside of .ent"));
13697 demand_empty_rest_of_line ();
13701 if (get_absolute_expression_and_terminator (&mask
) != ',')
13703 as_warn (_("Bad .mask/.fmask directive"));
13704 --input_line_pointer
;
13705 demand_empty_rest_of_line ();
13709 off
= get_absolute_expression ();
13711 if (reg_type
== 'F')
13713 cur_proc_ptr
->fpreg_mask
= mask
;
13714 cur_proc_ptr
->fpreg_offset
= off
;
13718 cur_proc_ptr
->reg_mask
= mask
;
13719 cur_proc_ptr
->reg_offset
= off
;
13722 demand_empty_rest_of_line ();
13725 #endif /* OBJ_ELF */
13726 s_ignore (reg_type
);
13729 /* A table describing all the processors gas knows about. Names are
13730 matched in the order listed.
13732 To ease comparison, please keep this table in the same order as
13733 gcc's mips_cpu_info_table[]. */
13734 static const struct mips_cpu_info mips_cpu_info_table
[] =
13736 /* Entries for generic ISAs */
13737 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13738 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13739 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13740 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13741 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13742 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13743 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13744 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13745 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13748 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13749 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13750 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13753 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13756 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13757 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13758 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13759 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13760 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13761 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13762 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13763 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13764 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13765 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13766 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13767 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13770 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13771 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13772 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13773 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13774 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13775 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13776 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13777 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13778 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13779 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13780 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13781 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13782 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13785 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13786 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13787 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13790 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13791 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13793 /* Broadcom SB-1 CPU core */
13794 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13801 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13802 with a final "000" replaced by "k". Ignore case.
13804 Note: this function is shared between GCC and GAS. */
13807 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13809 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13810 given
++, canonical
++;
13812 return ((*given
== 0 && *canonical
== 0)
13813 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13817 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13818 CPU name. We've traditionally allowed a lot of variation here.
13820 Note: this function is shared between GCC and GAS. */
13823 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13825 /* First see if the name matches exactly, or with a final "000"
13826 turned into "k". */
13827 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13830 /* If not, try comparing based on numerical designation alone.
13831 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13832 if (TOLOWER (*given
) == 'r')
13834 if (!ISDIGIT (*given
))
13837 /* Skip over some well-known prefixes in the canonical name,
13838 hoping to find a number there too. */
13839 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13841 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13843 else if (TOLOWER (canonical
[0]) == 'r')
13846 return mips_strict_matching_cpu_name_p (canonical
, given
);
13850 /* Parse an option that takes the name of a processor as its argument.
13851 OPTION is the name of the option and CPU_STRING is the argument.
13852 Return the corresponding processor enumeration if the CPU_STRING is
13853 recognized, otherwise report an error and return null.
13855 A similar function exists in GCC. */
13857 static const struct mips_cpu_info
*
13858 mips_parse_cpu (const char *option
, const char *cpu_string
)
13860 const struct mips_cpu_info
*p
;
13862 /* 'from-abi' selects the most compatible architecture for the given
13863 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13864 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13865 version. Look first at the -mgp options, if given, otherwise base
13866 the choice on MIPS_DEFAULT_64BIT.
13868 Treat NO_ABI like the EABIs. One reason to do this is that the
13869 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13870 architecture. This code picks MIPS I for 'mips' and MIPS III for
13871 'mips64', just as we did in the days before 'from-abi'. */
13872 if (strcasecmp (cpu_string
, "from-abi") == 0)
13874 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13875 return mips_cpu_info_from_isa (ISA_MIPS1
);
13877 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13878 return mips_cpu_info_from_isa (ISA_MIPS3
);
13880 if (file_mips_gp32
>= 0)
13881 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13883 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13888 /* 'default' has traditionally been a no-op. Probably not very useful. */
13889 if (strcasecmp (cpu_string
, "default") == 0)
13892 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13893 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13896 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13900 /* Return the canonical processor information for ISA (a member of the
13901 ISA_MIPS* enumeration). */
13903 static const struct mips_cpu_info
*
13904 mips_cpu_info_from_isa (int isa
)
13908 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13909 if (mips_cpu_info_table
[i
].is_isa
13910 && isa
== mips_cpu_info_table
[i
].isa
)
13911 return (&mips_cpu_info_table
[i
]);
13916 static const struct mips_cpu_info
*
13917 mips_cpu_info_from_arch (int arch
)
13921 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13922 if (arch
== mips_cpu_info_table
[i
].cpu
)
13923 return (&mips_cpu_info_table
[i
]);
13929 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13933 fprintf (stream
, "%24s", "");
13938 fprintf (stream
, ", ");
13942 if (*col_p
+ strlen (string
) > 72)
13944 fprintf (stream
, "\n%24s", "");
13948 fprintf (stream
, "%s", string
);
13949 *col_p
+= strlen (string
);
13955 md_show_usage (FILE *stream
)
13960 fprintf (stream
, _("\
13962 -EB generate big endian output\n\
13963 -EL generate little endian output\n\
13964 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13965 -G NUM allow referencing objects up to NUM bytes\n\
13966 implicitly with the gp register [default 8]\n"));
13967 fprintf (stream
, _("\
13968 -mips1 generate MIPS ISA I instructions\n\
13969 -mips2 generate MIPS ISA II instructions\n\
13970 -mips3 generate MIPS ISA III instructions\n\
13971 -mips4 generate MIPS ISA IV instructions\n\
13972 -mips5 generate MIPS ISA V instructions\n\
13973 -mips32 generate MIPS32 ISA instructions\n\
13974 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
13975 -mips64 generate MIPS64 ISA instructions\n\
13976 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
13977 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13981 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13982 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
13983 show (stream
, "from-abi", &column
, &first
);
13984 fputc ('\n', stream
);
13986 fprintf (stream
, _("\
13987 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13988 -no-mCPU don't generate code specific to CPU.\n\
13989 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13993 show (stream
, "3900", &column
, &first
);
13994 show (stream
, "4010", &column
, &first
);
13995 show (stream
, "4100", &column
, &first
);
13996 show (stream
, "4650", &column
, &first
);
13997 fputc ('\n', stream
);
13999 fprintf (stream
, _("\
14000 -mips16 generate mips16 instructions\n\
14001 -no-mips16 do not generate mips16 instructions\n"));
14002 fprintf (stream
, _("\
14003 -mfix-vr4120 work around certain VR4120 errata\n\
14004 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14005 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14006 -mno-shared optimize output for executables\n\
14007 -msym32 assume all symbols have 32-bit values\n\
14008 -O0 remove unneeded NOPs, do not swap branches\n\
14009 -O remove unneeded NOPs and swap branches\n\
14010 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14011 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14012 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14014 fprintf (stream
, _("\
14015 -KPIC, -call_shared generate SVR4 position independent code\n\
14016 -non_shared do not generate position independent code\n\
14017 -xgot assume a 32 bit GOT\n\
14018 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14019 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14021 -mabi=ABI create ABI conformant object file for:\n"));
14025 show (stream
, "32", &column
, &first
);
14026 show (stream
, "o64", &column
, &first
);
14027 show (stream
, "n32", &column
, &first
);
14028 show (stream
, "64", &column
, &first
);
14029 show (stream
, "eabi", &column
, &first
);
14031 fputc ('\n', stream
);
14033 fprintf (stream
, _("\
14034 -32 create o32 ABI object file (default)\n\
14035 -n32 create n32 ABI object file\n\
14036 -64 create 64 ABI object file\n"));
14041 mips_dwarf2_format (void)
14043 if (mips_abi
== N64_ABI
)
14046 return dwarf2_format_64bit_irix
;
14048 return dwarf2_format_64bit
;
14052 return dwarf2_format_32bit
;
14056 mips_dwarf2_addr_size (void)
14058 if (mips_abi
== N64_ABI
)