1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
36 #include "dw2gencfi.h"
39 #define DBG(x) printf x
45 /* Clean up namespace so we can include obj-elf.h too. */
46 static int mips_output_flavor (void);
47 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
48 #undef OBJ_PROCESS_STAB
55 #undef obj_frob_file_after_relocs
56 #undef obj_frob_symbol
58 #undef obj_sec_sym_ok_for_reloc
59 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
62 /* Fix any of them that we actually care about. */
64 #define OUTPUT_FLAVOR mips_output_flavor()
71 #ifndef ECOFF_DEBUGGING
72 #define NO_ECOFF_DEBUGGING
73 #define ECOFF_DEBUGGING 0
76 int mips_flag_mdebug
= -1;
78 /* Control generation of .pdr sections. Off by default on IRIX: the native
79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
82 int mips_flag_pdr
= FALSE
;
84 int mips_flag_pdr
= TRUE
;
89 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
90 static char *mips_regmask_frag
;
96 #define PIC_CALL_REG 25
104 #define ILLEGAL_REG (32)
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
198 /* Whether we are assembling for the mips16 processor. 0 if we are
199 not, 1 if we are, and -1 if the value has not been initialized.
200 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
201 -nomips16 command line options, and the default CPU. */
203 /* Non-zero if we should not reorder instructions. Changed by `.set
204 reorder' and `.set noreorder'. */
206 /* Non-zero if we should not permit the $at ($1) register to be used
207 in instructions. Changed by `.set at' and `.set noat'. */
209 /* Non-zero if we should warn when a macro instruction expands into
210 more than one machine instruction. Changed by `.set nomacro' and
212 int warn_about_macros
;
213 /* Non-zero if we should not move instructions. Changed by `.set
214 move', `.set volatile', `.set nomove', and `.set novolatile'. */
216 /* Non-zero if we should not optimize branches by moving the target
217 of the branch into the delay slot. Actually, we don't perform
218 this optimization anyhow. Changed by `.set bopt' and `.set
221 /* Non-zero if we should not autoextend mips16 instructions.
222 Changed by `.set autoextend' and `.set noautoextend'. */
224 /* Restrict general purpose registers and floating point registers
225 to 32 bit. This is initially determined when -mgp32 or -mfp32
226 is passed but can changed if the assembler code uses .set mipsN. */
229 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
230 command line option, and the default CPU. */
232 /* True if ".set sym32" is in effect. */
236 /* True if -mgp32 was passed. */
237 static int file_mips_gp32
= -1;
239 /* True if -mfp32 was passed. */
240 static int file_mips_fp32
= -1;
242 /* This is the struct we use to hold the current set of options. Note
243 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
244 -1 to indicate that they have not been initialized. */
246 static struct mips_set_options mips_opts
=
248 ISA_UNKNOWN
, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
251 /* These variables are filled in with the masks of registers used.
252 The object format code reads them and puts them in the appropriate
254 unsigned long mips_gprmask
;
255 unsigned long mips_cprmask
[4];
257 /* MIPS ISA we are using for this output file. */
258 static int file_mips_isa
= ISA_UNKNOWN
;
260 /* True if -mips16 was passed or implied by arguments passed on the
261 command line (e.g., by -march). */
262 static int file_ase_mips16
;
264 /* True if -mips3d was passed or implied by arguments passed on the
265 command line (e.g., by -march). */
266 static int file_ase_mips3d
;
268 /* True if -mdmx was passed or implied by arguments passed on the
269 command line (e.g., by -march). */
270 static int file_ase_mdmx
;
272 /* True if -mdsp was passed or implied by arguments passed on the
273 command line (e.g., by -march). */
274 static int file_ase_dsp
;
276 /* True if -mmt was passed or implied by arguments passed on the
277 command line (e.g., by -march). */
278 static int file_ase_mt
;
280 /* The argument of the -march= flag. The architecture we are assembling. */
281 static int file_mips_arch
= CPU_UNKNOWN
;
282 static const char *mips_arch_string
;
284 /* The argument of the -mtune= flag. The architecture for which we
286 static int mips_tune
= CPU_UNKNOWN
;
287 static const char *mips_tune_string
;
289 /* True when generating 32-bit code for a 64-bit processor. */
290 static int mips_32bitmode
= 0;
292 /* True if the given ABI requires 32-bit registers. */
293 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
295 /* Likewise 64-bit registers. */
296 #define ABI_NEEDS_64BIT_REGS(ABI) \
298 || (ABI) == N64_ABI \
301 /* Return true if ISA supports 64 bit gp register instructions. */
302 #define ISA_HAS_64BIT_REGS(ISA) ( \
304 || (ISA) == ISA_MIPS4 \
305 || (ISA) == ISA_MIPS5 \
306 || (ISA) == ISA_MIPS64 \
307 || (ISA) == ISA_MIPS64R2 \
310 /* Return true if ISA supports 64-bit right rotate (dror et al.)
312 #define ISA_HAS_DROR(ISA) ( \
313 (ISA) == ISA_MIPS64R2 \
316 /* Return true if ISA supports 32-bit right rotate (ror et al.)
318 #define ISA_HAS_ROR(ISA) ( \
319 (ISA) == ISA_MIPS32R2 \
320 || (ISA) == ISA_MIPS64R2 \
323 #define HAVE_32BIT_GPRS \
324 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
326 #define HAVE_32BIT_FPRS \
327 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
329 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
330 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
332 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
334 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
336 /* True if relocations are stored in-place. */
337 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
339 /* The ABI-derived address size. */
340 #define HAVE_64BIT_ADDRESSES \
341 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
342 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
344 /* The size of symbolic constants (i.e., expressions of the form
345 "SYMBOL" or "SYMBOL + OFFSET"). */
346 #define HAVE_32BIT_SYMBOLS \
347 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
348 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
350 /* Addresses are loaded in different ways, depending on the address size
351 in use. The n32 ABI Documentation also mandates the use of additions
352 with overflow checking, but existing implementations don't follow it. */
353 #define ADDRESS_ADD_INSN \
354 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
356 #define ADDRESS_ADDI_INSN \
357 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
359 #define ADDRESS_LOAD_INSN \
360 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
362 #define ADDRESS_STORE_INSN \
363 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
365 /* Return true if the given CPU supports the MIPS16 ASE. */
366 #define CPU_HAS_MIPS16(cpu) \
367 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
368 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
370 /* Return true if the given CPU supports the MIPS3D ASE. */
371 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
374 /* Return true if the given CPU supports the MDMX ASE. */
375 #define CPU_HAS_MDMX(cpu) (FALSE \
378 /* Return true if the given CPU supports the DSP ASE. */
379 #define CPU_HAS_DSP(cpu) (FALSE \
382 /* Return true if the given CPU supports the MT ASE. */
383 #define CPU_HAS_MT(cpu) (FALSE \
386 /* True if CPU has a dror instruction. */
387 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
389 /* True if CPU has a ror instruction. */
390 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
392 /* True if mflo and mfhi can be immediately followed by instructions
393 which write to the HI and LO registers.
395 According to MIPS specifications, MIPS ISAs I, II, and III need
396 (at least) two instructions between the reads of HI/LO and
397 instructions which write them, and later ISAs do not. Contradicting
398 the MIPS specifications, some MIPS IV processor user manuals (e.g.
399 the UM for the NEC Vr5000) document needing the instructions between
400 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
401 MIPS64 and later ISAs to have the interlocks, plus any specific
402 earlier-ISA CPUs for which CPU documentation declares that the
403 instructions are really interlocked. */
404 #define hilo_interlocks \
405 (mips_opts.isa == ISA_MIPS32 \
406 || mips_opts.isa == ISA_MIPS32R2 \
407 || mips_opts.isa == ISA_MIPS64 \
408 || mips_opts.isa == ISA_MIPS64R2 \
409 || mips_opts.arch == CPU_R4010 \
410 || mips_opts.arch == CPU_R10000 \
411 || mips_opts.arch == CPU_R12000 \
412 || mips_opts.arch == CPU_RM7000 \
413 || mips_opts.arch == CPU_VR5500 \
416 /* Whether the processor uses hardware interlocks to protect reads
417 from the GPRs after they are loaded from memory, and thus does not
418 require nops to be inserted. This applies to instructions marked
419 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
421 #define gpr_interlocks \
422 (mips_opts.isa != ISA_MIPS1 \
423 || mips_opts.arch == CPU_R3900)
425 /* Whether the processor uses hardware interlocks to avoid delays
426 required by coprocessor instructions, and thus does not require
427 nops to be inserted. This applies to instructions marked
428 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
429 between instructions marked INSN_WRITE_COND_CODE and ones marked
430 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
431 levels I, II, and III. */
432 /* Itbl support may require additional care here. */
433 #define cop_interlocks \
434 ((mips_opts.isa != ISA_MIPS1 \
435 && mips_opts.isa != ISA_MIPS2 \
436 && mips_opts.isa != ISA_MIPS3) \
437 || mips_opts.arch == CPU_R4300 \
440 /* Whether the processor uses hardware interlocks to protect reads
441 from coprocessor registers after they are loaded from memory, and
442 thus does not require nops to be inserted. This applies to
443 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
444 requires at MIPS ISA level I. */
445 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
447 /* Is this a mfhi or mflo instruction? */
448 #define MF_HILO_INSN(PINFO) \
449 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
451 /* MIPS PIC level. */
453 enum mips_pic_level mips_pic
;
455 /* 1 if we should generate 32 bit offsets from the $gp register in
456 SVR4_PIC mode. Currently has no meaning in other modes. */
457 static int mips_big_got
= 0;
459 /* 1 if trap instructions should used for overflow rather than break
461 static int mips_trap
= 0;
463 /* 1 if double width floating point constants should not be constructed
464 by assembling two single width halves into two single width floating
465 point registers which just happen to alias the double width destination
466 register. On some architectures this aliasing can be disabled by a bit
467 in the status register, and the setting of this bit cannot be determined
468 automatically at assemble time. */
469 static int mips_disable_float_construction
;
471 /* Non-zero if any .set noreorder directives were used. */
473 static int mips_any_noreorder
;
475 /* Non-zero if nops should be inserted when the register referenced in
476 an mfhi/mflo instruction is read in the next two instructions. */
477 static int mips_7000_hilo_fix
;
479 /* The size of the small data section. */
480 static unsigned int g_switch_value
= 8;
481 /* Whether the -G option was used. */
482 static int g_switch_seen
= 0;
487 /* If we can determine in advance that GP optimization won't be
488 possible, we can skip the relaxation stuff that tries to produce
489 GP-relative references. This makes delay slot optimization work
492 This function can only provide a guess, but it seems to work for
493 gcc output. It needs to guess right for gcc, otherwise gcc
494 will put what it thinks is a GP-relative instruction in a branch
497 I don't know if a fix is needed for the SVR4_PIC mode. I've only
498 fixed it for the non-PIC mode. KR 95/04/07 */
499 static int nopic_need_relax (symbolS
*, int);
501 /* handle of the OPCODE hash table */
502 static struct hash_control
*op_hash
= NULL
;
504 /* The opcode hash table we use for the mips16. */
505 static struct hash_control
*mips16_op_hash
= NULL
;
507 /* This array holds the chars that always start a comment. If the
508 pre-processor is disabled, these aren't very useful */
509 const char comment_chars
[] = "#";
511 /* This array holds the chars that only start a comment at the beginning of
512 a line. If the line seems to have the form '# 123 filename'
513 .line and .file directives will appear in the pre-processed output */
514 /* Note that input_file.c hand checks for '#' at the beginning of the
515 first line of the input file. This is because the compiler outputs
516 #NO_APP at the beginning of its output. */
517 /* Also note that C style comments are always supported. */
518 const char line_comment_chars
[] = "#";
520 /* This array holds machine specific line separator characters. */
521 const char line_separator_chars
[] = ";";
523 /* Chars that can be used to separate mant from exp in floating point nums */
524 const char EXP_CHARS
[] = "eE";
526 /* Chars that mean this number is a floating point constant */
529 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
531 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
532 changed in read.c . Ideally it shouldn't have to know about it at all,
533 but nothing is ideal around here.
536 static char *insn_error
;
538 static int auto_align
= 1;
540 /* When outputting SVR4 PIC code, the assembler needs to know the
541 offset in the stack frame from which to restore the $gp register.
542 This is set by the .cprestore pseudo-op, and saved in this
544 static offsetT mips_cprestore_offset
= -1;
546 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
547 more optimizations, it can use a register value instead of a memory-saved
548 offset and even an other register than $gp as global pointer. */
549 static offsetT mips_cpreturn_offset
= -1;
550 static int mips_cpreturn_register
= -1;
551 static int mips_gp_register
= GP
;
552 static int mips_gprel_offset
= 0;
554 /* Whether mips_cprestore_offset has been set in the current function
555 (or whether it has already been warned about, if not). */
556 static int mips_cprestore_valid
= 0;
558 /* This is the register which holds the stack frame, as set by the
559 .frame pseudo-op. This is needed to implement .cprestore. */
560 static int mips_frame_reg
= SP
;
562 /* Whether mips_frame_reg has been set in the current function
563 (or whether it has already been warned about, if not). */
564 static int mips_frame_reg_valid
= 0;
566 /* To output NOP instructions correctly, we need to keep information
567 about the previous two instructions. */
569 /* Whether we are optimizing. The default value of 2 means to remove
570 unneeded NOPs and swap branch instructions when possible. A value
571 of 1 means to not swap branches. A value of 0 means to always
573 static int mips_optimize
= 2;
575 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
576 equivalent to seeing no -g option at all. */
577 static int mips_debug
= 0;
579 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
580 #define MAX_VR4130_NOPS 4
582 /* The maximum number of NOPs needed to fill delay slots. */
583 #define MAX_DELAY_NOPS 2
585 /* The maximum number of NOPs needed for any purpose. */
588 /* A list of previous instructions, with index 0 being the most recent.
589 We need to look back MAX_NOPS instructions when filling delay slots
590 or working around processor errata. We need to look back one
591 instruction further if we're thinking about using history[0] to
592 fill a branch delay slot. */
593 static struct mips_cl_insn history
[1 + MAX_NOPS
];
595 /* Nop instructions used by emit_nop. */
596 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
598 /* The appropriate nop for the current mode. */
599 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
601 /* If this is set, it points to a frag holding nop instructions which
602 were inserted before the start of a noreorder section. If those
603 nops turn out to be unnecessary, the size of the frag can be
605 static fragS
*prev_nop_frag
;
607 /* The number of nop instructions we created in prev_nop_frag. */
608 static int prev_nop_frag_holds
;
610 /* The number of nop instructions that we know we need in
612 static int prev_nop_frag_required
;
614 /* The number of instructions we've seen since prev_nop_frag. */
615 static int prev_nop_frag_since
;
617 /* For ECOFF and ELF, relocations against symbols are done in two
618 parts, with a HI relocation and a LO relocation. Each relocation
619 has only 16 bits of space to store an addend. This means that in
620 order for the linker to handle carries correctly, it must be able
621 to locate both the HI and the LO relocation. This means that the
622 relocations must appear in order in the relocation table.
624 In order to implement this, we keep track of each unmatched HI
625 relocation. We then sort them so that they immediately precede the
626 corresponding LO relocation. */
631 struct mips_hi_fixup
*next
;
634 /* The section this fixup is in. */
638 /* The list of unmatched HI relocs. */
640 static struct mips_hi_fixup
*mips_hi_fixup_list
;
642 /* The frag containing the last explicit relocation operator.
643 Null if explicit relocations have not been used. */
645 static fragS
*prev_reloc_op_frag
;
647 /* Map normal MIPS register numbers to mips16 register numbers. */
649 #define X ILLEGAL_REG
650 static const int mips32_to_16_reg_map
[] =
652 X
, X
, 2, 3, 4, 5, 6, 7,
653 X
, X
, X
, X
, X
, X
, X
, X
,
654 0, 1, X
, X
, X
, X
, X
, X
,
655 X
, X
, X
, X
, X
, X
, X
, X
659 /* Map mips16 register numbers to normal MIPS register numbers. */
661 static const unsigned int mips16_to_32_reg_map
[] =
663 16, 17, 2, 3, 4, 5, 6, 7
666 /* Classifies the kind of instructions we're interested in when
667 implementing -mfix-vr4120. */
668 enum fix_vr4120_class
{
675 NUM_FIX_VR4120_CLASSES
678 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
679 there must be at least one other instruction between an instruction
680 of type X and an instruction of type Y. */
681 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
683 /* True if -mfix-vr4120 is in force. */
684 static int mips_fix_vr4120
;
686 /* ...likewise -mfix-vr4130. */
687 static int mips_fix_vr4130
;
689 /* We don't relax branches by default, since this causes us to expand
690 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
691 fail to compute the offset before expanding the macro to the most
692 efficient expansion. */
694 static int mips_relax_branch
;
696 /* The expansion of many macros depends on the type of symbol that
697 they refer to. For example, when generating position-dependent code,
698 a macro that refers to a symbol may have two different expansions,
699 one which uses GP-relative addresses and one which uses absolute
700 addresses. When generating SVR4-style PIC, a macro may have
701 different expansions for local and global symbols.
703 We handle these situations by generating both sequences and putting
704 them in variant frags. In position-dependent code, the first sequence
705 will be the GP-relative one and the second sequence will be the
706 absolute one. In SVR4 PIC, the first sequence will be for global
707 symbols and the second will be for local symbols.
709 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
710 SECOND are the lengths of the two sequences in bytes. These fields
711 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
712 the subtype has the following flags:
715 Set if it has been decided that we should use the second
716 sequence instead of the first.
719 Set in the first variant frag if the macro's second implementation
720 is longer than its first. This refers to the macro as a whole,
721 not an individual relaxation.
724 Set in the first variant frag if the macro appeared in a .set nomacro
725 block and if one alternative requires a warning but the other does not.
728 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
731 The frag's "opcode" points to the first fixup for relaxable code.
733 Relaxable macros are generated using a sequence such as:
735 relax_start (SYMBOL);
736 ... generate first expansion ...
738 ... generate second expansion ...
741 The code and fixups for the unwanted alternative are discarded
742 by md_convert_frag. */
743 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
745 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
746 #define RELAX_SECOND(X) ((X) & 0xff)
747 #define RELAX_USE_SECOND 0x10000
748 #define RELAX_SECOND_LONGER 0x20000
749 #define RELAX_NOMACRO 0x40000
750 #define RELAX_DELAY_SLOT 0x80000
752 /* Branch without likely bit. If label is out of range, we turn:
754 beq reg1, reg2, label
764 with the following opcode replacements:
771 bltzal <-> bgezal (with jal label instead of j label)
773 Even though keeping the delay slot instruction in the delay slot of
774 the branch would be more efficient, it would be very tricky to do
775 correctly, because we'd have to introduce a variable frag *after*
776 the delay slot instruction, and expand that instead. Let's do it
777 the easy way for now, even if the branch-not-taken case now costs
778 one additional instruction. Out-of-range branches are not supposed
779 to be common, anyway.
781 Branch likely. If label is out of range, we turn:
783 beql reg1, reg2, label
784 delay slot (annulled if branch not taken)
793 delay slot (executed only if branch taken)
796 It would be possible to generate a shorter sequence by losing the
797 likely bit, generating something like:
802 delay slot (executed only if branch taken)
814 bltzall -> bgezal (with jal label instead of j label)
815 bgezall -> bltzal (ditto)
818 but it's not clear that it would actually improve performance. */
819 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
822 | ((toofar) ? 1 : 0) \
824 | ((likely) ? 4 : 0) \
825 | ((uncond) ? 8 : 0)))
826 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
827 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
828 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
829 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
830 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
832 /* For mips16 code, we use an entirely different form of relaxation.
833 mips16 supports two versions of most instructions which take
834 immediate values: a small one which takes some small value, and a
835 larger one which takes a 16 bit value. Since branches also follow
836 this pattern, relaxing these values is required.
838 We can assemble both mips16 and normal MIPS code in a single
839 object. Therefore, we need to support this type of relaxation at
840 the same time that we support the relaxation described above. We
841 use the high bit of the subtype field to distinguish these cases.
843 The information we store for this type of relaxation is the
844 argument code found in the opcode file for this relocation, whether
845 the user explicitly requested a small or extended form, and whether
846 the relocation is in a jump or jal delay slot. That tells us the
847 size of the value, and how it should be stored. We also store
848 whether the fragment is considered to be extended or not. We also
849 store whether this is known to be a branch to a different section,
850 whether we have tried to relax this frag yet, and whether we have
851 ever extended a PC relative fragment because of a shift count. */
852 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
855 | ((small) ? 0x100 : 0) \
856 | ((ext) ? 0x200 : 0) \
857 | ((dslot) ? 0x400 : 0) \
858 | ((jal_dslot) ? 0x800 : 0))
859 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
860 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
861 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
862 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
863 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
864 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
865 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
866 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
867 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
868 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
869 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
870 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
872 /* Is the given value a sign-extended 32-bit value? */
873 #define IS_SEXT_32BIT_NUM(x) \
874 (((x) &~ (offsetT) 0x7fffffff) == 0 \
875 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
877 /* Is the given value a sign-extended 16-bit value? */
878 #define IS_SEXT_16BIT_NUM(x) \
879 (((x) &~ (offsetT) 0x7fff) == 0 \
880 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
882 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
883 #define IS_ZEXT_32BIT_NUM(x) \
884 (((x) &~ (offsetT) 0xffffffff) == 0 \
885 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
887 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
888 VALUE << SHIFT. VALUE is evaluated exactly once. */
889 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
890 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
891 | (((VALUE) & (MASK)) << (SHIFT)))
893 /* Extract bits MASK << SHIFT from STRUCT and shift them right
895 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
896 (((STRUCT) >> (SHIFT)) & (MASK))
898 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
899 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
901 include/opcode/mips.h specifies operand fields using the macros
902 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
903 with "MIPS16OP" instead of "OP". */
904 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
905 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
906 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
907 INSERT_BITS ((INSN).insn_opcode, VALUE, \
908 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
910 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
911 #define EXTRACT_OPERAND(FIELD, INSN) \
912 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
913 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
914 EXTRACT_BITS ((INSN).insn_opcode, \
915 MIPS16OP_MASK_##FIELD, \
918 /* Global variables used when generating relaxable macros. See the
919 comment above RELAX_ENCODE for more details about how relaxation
922 /* 0 if we're not emitting a relaxable macro.
923 1 if we're emitting the first of the two relaxation alternatives.
924 2 if we're emitting the second alternative. */
927 /* The first relaxable fixup in the current frag. (In other words,
928 the first fixup that refers to relaxable code.) */
931 /* sizes[0] says how many bytes of the first alternative are stored in
932 the current frag. Likewise sizes[1] for the second alternative. */
933 unsigned int sizes
[2];
935 /* The symbol on which the choice of sequence depends. */
939 /* Global variables used to decide whether a macro needs a warning. */
941 /* True if the macro is in a branch delay slot. */
942 bfd_boolean delay_slot_p
;
944 /* For relaxable macros, sizes[0] is the length of the first alternative
945 in bytes and sizes[1] is the length of the second alternative.
946 For non-relaxable macros, both elements give the length of the
948 unsigned int sizes
[2];
950 /* The first variant frag for this macro. */
952 } mips_macro_warning
;
954 /* Prototypes for static functions. */
956 #define internalError() \
957 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
959 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
961 static void append_insn
962 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
963 static void mips_no_prev_insn (void);
964 static void mips16_macro_build
965 (expressionS
*, const char *, const char *, va_list);
966 static void load_register (int, expressionS
*, int);
967 static void macro_start (void);
968 static void macro_end (void);
969 static void macro (struct mips_cl_insn
* ip
);
970 static void mips16_macro (struct mips_cl_insn
* ip
);
971 #ifdef LOSING_COMPILER
972 static void macro2 (struct mips_cl_insn
* ip
);
974 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
975 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
976 static void mips16_immed
977 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
978 unsigned long *, bfd_boolean
*, unsigned short *);
979 static size_t my_getSmallExpression
980 (expressionS
*, bfd_reloc_code_real_type
*, char *);
981 static void my_getExpression (expressionS
*, char *);
982 static void s_align (int);
983 static void s_change_sec (int);
984 static void s_change_section (int);
985 static void s_cons (int);
986 static void s_float_cons (int);
987 static void s_mips_globl (int);
988 static void s_option (int);
989 static void s_mipsset (int);
990 static void s_abicalls (int);
991 static void s_cpload (int);
992 static void s_cpsetup (int);
993 static void s_cplocal (int);
994 static void s_cprestore (int);
995 static void s_cpreturn (int);
996 static void s_gpvalue (int);
997 static void s_gpword (int);
998 static void s_gpdword (int);
999 static void s_cpadd (int);
1000 static void s_insn (int);
1001 static void md_obj_begin (void);
1002 static void md_obj_end (void);
1003 static void s_mips_ent (int);
1004 static void s_mips_end (int);
1005 static void s_mips_frame (int);
1006 static void s_mips_mask (int reg_type
);
1007 static void s_mips_stab (int);
1008 static void s_mips_weakext (int);
1009 static void s_mips_file (int);
1010 static void s_mips_loc (int);
1011 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1012 static int relaxed_branch_length (fragS
*, asection
*, int);
1013 static int validate_mips_insn (const struct mips_opcode
*);
1015 /* Table and functions used to map between CPU/ISA names, and
1016 ISA levels, and CPU numbers. */
1018 struct mips_cpu_info
1020 const char *name
; /* CPU or ISA name. */
1021 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
1022 int isa
; /* ISA level. */
1023 int cpu
; /* CPU number (default CPU if ISA). */
1026 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1027 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1028 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1032 The following pseudo-ops from the Kane and Heinrich MIPS book
1033 should be defined here, but are currently unsupported: .alias,
1034 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1036 The following pseudo-ops from the Kane and Heinrich MIPS book are
1037 specific to the type of debugging information being generated, and
1038 should be defined by the object format: .aent, .begin, .bend,
1039 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1042 The following pseudo-ops from the Kane and Heinrich MIPS book are
1043 not MIPS CPU specific, but are also not specific to the object file
1044 format. This file is probably the best place to define them, but
1045 they are not currently supported: .asm0, .endr, .lab, .repeat,
1048 static const pseudo_typeS mips_pseudo_table
[] =
1050 /* MIPS specific pseudo-ops. */
1051 {"option", s_option
, 0},
1052 {"set", s_mipsset
, 0},
1053 {"rdata", s_change_sec
, 'r'},
1054 {"sdata", s_change_sec
, 's'},
1055 {"livereg", s_ignore
, 0},
1056 {"abicalls", s_abicalls
, 0},
1057 {"cpload", s_cpload
, 0},
1058 {"cpsetup", s_cpsetup
, 0},
1059 {"cplocal", s_cplocal
, 0},
1060 {"cprestore", s_cprestore
, 0},
1061 {"cpreturn", s_cpreturn
, 0},
1062 {"gpvalue", s_gpvalue
, 0},
1063 {"gpword", s_gpword
, 0},
1064 {"gpdword", s_gpdword
, 0},
1065 {"cpadd", s_cpadd
, 0},
1066 {"insn", s_insn
, 0},
1068 /* Relatively generic pseudo-ops that happen to be used on MIPS
1070 {"asciiz", stringer
, 1},
1071 {"bss", s_change_sec
, 'b'},
1073 {"half", s_cons
, 1},
1074 {"dword", s_cons
, 3},
1075 {"weakext", s_mips_weakext
, 0},
1077 /* These pseudo-ops are defined in read.c, but must be overridden
1078 here for one reason or another. */
1079 {"align", s_align
, 0},
1080 {"byte", s_cons
, 0},
1081 {"data", s_change_sec
, 'd'},
1082 {"double", s_float_cons
, 'd'},
1083 {"float", s_float_cons
, 'f'},
1084 {"globl", s_mips_globl
, 0},
1085 {"global", s_mips_globl
, 0},
1086 {"hword", s_cons
, 1},
1088 {"long", s_cons
, 2},
1089 {"octa", s_cons
, 4},
1090 {"quad", s_cons
, 3},
1091 {"section", s_change_section
, 0},
1092 {"short", s_cons
, 1},
1093 {"single", s_float_cons
, 'f'},
1094 {"stabn", s_mips_stab
, 'n'},
1095 {"text", s_change_sec
, 't'},
1096 {"word", s_cons
, 2},
1098 { "extern", ecoff_directive_extern
, 0},
1103 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1105 /* These pseudo-ops should be defined by the object file format.
1106 However, a.out doesn't support them, so we have versions here. */
1107 {"aent", s_mips_ent
, 1},
1108 {"bgnb", s_ignore
, 0},
1109 {"end", s_mips_end
, 0},
1110 {"endb", s_ignore
, 0},
1111 {"ent", s_mips_ent
, 0},
1112 {"file", s_mips_file
, 0},
1113 {"fmask", s_mips_mask
, 'F'},
1114 {"frame", s_mips_frame
, 0},
1115 {"loc", s_mips_loc
, 0},
1116 {"mask", s_mips_mask
, 'R'},
1117 {"verstamp", s_ignore
, 0},
1121 extern void pop_insert (const pseudo_typeS
*);
1124 mips_pop_insert (void)
1126 pop_insert (mips_pseudo_table
);
1127 if (! ECOFF_DEBUGGING
)
1128 pop_insert (mips_nonecoff_pseudo_table
);
1131 /* Symbols labelling the current insn. */
1133 struct insn_label_list
1135 struct insn_label_list
*next
;
1139 static struct insn_label_list
*insn_labels
;
1140 static struct insn_label_list
*free_insn_labels
;
1142 static void mips_clear_insn_labels (void);
1145 mips_clear_insn_labels (void)
1147 register struct insn_label_list
**pl
;
1149 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1155 static char *expr_end
;
1157 /* Expressions which appear in instructions. These are set by
1160 static expressionS imm_expr
;
1161 static expressionS imm2_expr
;
1162 static expressionS offset_expr
;
1164 /* Relocs associated with imm_expr and offset_expr. */
1166 static bfd_reloc_code_real_type imm_reloc
[3]
1167 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1168 static bfd_reloc_code_real_type offset_reloc
[3]
1169 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1171 /* These are set by mips16_ip if an explicit extension is used. */
1173 static bfd_boolean mips16_small
, mips16_ext
;
1176 /* The pdr segment for per procedure frame/regmask info. Not used for
1179 static segT pdr_seg
;
1182 /* The default target format to use. */
1185 mips_target_format (void)
1187 switch (OUTPUT_FLAVOR
)
1189 case bfd_target_ecoff_flavour
:
1190 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1191 case bfd_target_coff_flavour
:
1193 case bfd_target_elf_flavour
:
1195 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1196 return (target_big_endian
1197 ? "elf32-bigmips-vxworks"
1198 : "elf32-littlemips-vxworks");
1201 /* This is traditional mips. */
1202 return (target_big_endian
1203 ? (HAVE_64BIT_OBJECTS
1204 ? "elf64-tradbigmips"
1206 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1207 : (HAVE_64BIT_OBJECTS
1208 ? "elf64-tradlittlemips"
1210 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1212 return (target_big_endian
1213 ? (HAVE_64BIT_OBJECTS
1216 ? "elf32-nbigmips" : "elf32-bigmips"))
1217 : (HAVE_64BIT_OBJECTS
1218 ? "elf64-littlemips"
1220 ? "elf32-nlittlemips" : "elf32-littlemips")));
1228 /* Return the length of instruction INSN. */
1230 static inline unsigned int
1231 insn_length (const struct mips_cl_insn
*insn
)
1233 if (!mips_opts
.mips16
)
1235 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1238 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1241 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1246 insn
->use_extend
= FALSE
;
1248 insn
->insn_opcode
= mo
->match
;
1251 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1252 insn
->fixp
[i
] = NULL
;
1253 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1254 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1255 insn
->mips16_absolute_jump_p
= 0;
1258 /* Install INSN at the location specified by its "frag" and "where" fields. */
1261 install_insn (const struct mips_cl_insn
*insn
)
1263 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1264 if (!mips_opts
.mips16
)
1265 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1266 else if (insn
->mips16_absolute_jump_p
)
1268 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1269 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1273 if (insn
->use_extend
)
1275 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1278 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1282 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1283 and install the opcode in the new location. */
1286 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1291 insn
->where
= where
;
1292 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1293 if (insn
->fixp
[i
] != NULL
)
1295 insn
->fixp
[i
]->fx_frag
= frag
;
1296 insn
->fixp
[i
]->fx_where
= where
;
1298 install_insn (insn
);
1301 /* Add INSN to the end of the output. */
1304 add_fixed_insn (struct mips_cl_insn
*insn
)
1306 char *f
= frag_more (insn_length (insn
));
1307 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1310 /* Start a variant frag and move INSN to the start of the variant part,
1311 marking it as fixed. The other arguments are as for frag_var. */
1314 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1315 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1317 frag_grow (max_chars
);
1318 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1320 frag_var (rs_machine_dependent
, max_chars
, var
,
1321 subtype
, symbol
, offset
, NULL
);
1324 /* Insert N copies of INSN into the history buffer, starting at
1325 position FIRST. Neither FIRST nor N need to be clipped. */
1328 insert_into_history (unsigned int first
, unsigned int n
,
1329 const struct mips_cl_insn
*insn
)
1331 if (mips_relax
.sequence
!= 2)
1335 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1337 history
[i
] = history
[i
- n
];
1343 /* Emit a nop instruction, recording it in the history buffer. */
1348 add_fixed_insn (NOP_INSN
);
1349 insert_into_history (0, 1, NOP_INSN
);
1352 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1353 the idea is to make it obvious at a glance that each errata is
1357 init_vr4120_conflicts (void)
1359 #define CONFLICT(FIRST, SECOND) \
1360 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1362 /* Errata 21 - [D]DIV[U] after [D]MACC */
1363 CONFLICT (MACC
, DIV
);
1364 CONFLICT (DMACC
, DIV
);
1366 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1367 CONFLICT (DMULT
, DMULT
);
1368 CONFLICT (DMULT
, DMACC
);
1369 CONFLICT (DMACC
, DMULT
);
1370 CONFLICT (DMACC
, DMACC
);
1372 /* Errata 24 - MT{LO,HI} after [D]MACC */
1373 CONFLICT (MACC
, MTHILO
);
1374 CONFLICT (DMACC
, MTHILO
);
1376 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1377 instruction is executed immediately after a MACC or DMACC
1378 instruction, the result of [either instruction] is incorrect." */
1379 CONFLICT (MACC
, MULT
);
1380 CONFLICT (MACC
, DMULT
);
1381 CONFLICT (DMACC
, MULT
);
1382 CONFLICT (DMACC
, DMULT
);
1384 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1385 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1386 DDIV or DDIVU instruction, the result of the MACC or
1387 DMACC instruction is incorrect.". */
1388 CONFLICT (DMULT
, MACC
);
1389 CONFLICT (DMULT
, DMACC
);
1390 CONFLICT (DIV
, MACC
);
1391 CONFLICT (DIV
, DMACC
);
1396 /* This function is called once, at assembler startup time. It should
1397 set up all the tables, etc. that the MD part of the assembler will need. */
1402 register const char *retval
= NULL
;
1406 if (mips_pic
!= NO_PIC
)
1408 if (g_switch_seen
&& g_switch_value
!= 0)
1409 as_bad (_("-G may not be used in position-independent code"));
1413 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1414 as_warn (_("Could not set architecture and machine"));
1416 op_hash
= hash_new ();
1418 for (i
= 0; i
< NUMOPCODES
;)
1420 const char *name
= mips_opcodes
[i
].name
;
1422 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1425 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1426 mips_opcodes
[i
].name
, retval
);
1427 /* Probably a memory allocation problem? Give up now. */
1428 as_fatal (_("Broken assembler. No assembly attempted."));
1432 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1434 if (!validate_mips_insn (&mips_opcodes
[i
]))
1436 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1438 create_insn (&nop_insn
, mips_opcodes
+ i
);
1439 nop_insn
.fixed_p
= 1;
1444 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1447 mips16_op_hash
= hash_new ();
1450 while (i
< bfd_mips16_num_opcodes
)
1452 const char *name
= mips16_opcodes
[i
].name
;
1454 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1456 as_fatal (_("internal: can't hash `%s': %s"),
1457 mips16_opcodes
[i
].name
, retval
);
1460 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1461 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1462 != mips16_opcodes
[i
].match
))
1464 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1465 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1468 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1470 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1471 mips16_nop_insn
.fixed_p
= 1;
1475 while (i
< bfd_mips16_num_opcodes
1476 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1480 as_fatal (_("Broken assembler. No assembly attempted."));
1482 /* We add all the general register names to the symbol table. This
1483 helps us detect invalid uses of them. */
1484 for (i
= 0; i
< 32; i
++)
1488 sprintf (buf
, "$%d", i
);
1489 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1490 &zero_address_frag
));
1492 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1493 &zero_address_frag
));
1494 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1495 &zero_address_frag
));
1496 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1497 &zero_address_frag
));
1498 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1499 &zero_address_frag
));
1500 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1501 &zero_address_frag
));
1502 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1503 &zero_address_frag
));
1504 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1505 &zero_address_frag
));
1506 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1507 &zero_address_frag
));
1508 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1509 &zero_address_frag
));
1511 /* If we don't add these register names to the symbol table, they
1512 may end up being added as regular symbols by operand(), and then
1513 make it to the object file as undefined in case they're not
1514 regarded as local symbols. They're local in o32, since `$' is a
1515 local symbol prefix, but not in n32 or n64. */
1516 for (i
= 0; i
< 8; i
++)
1520 sprintf (buf
, "$fcc%i", i
);
1521 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1522 &zero_address_frag
));
1525 mips_no_prev_insn ();
1528 mips_cprmask
[0] = 0;
1529 mips_cprmask
[1] = 0;
1530 mips_cprmask
[2] = 0;
1531 mips_cprmask
[3] = 0;
1533 /* set the default alignment for the text section (2**2) */
1534 record_alignment (text_section
, 2);
1536 bfd_set_gp_size (stdoutput
, g_switch_value
);
1538 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1540 /* On a native system other than VxWorks, sections must be aligned
1541 to 16 byte boundaries. When configured for an embedded ELF
1542 target, we don't bother. */
1543 if (strcmp (TARGET_OS
, "elf") != 0
1544 && strcmp (TARGET_OS
, "vxworks") != 0)
1546 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1547 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1548 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1551 /* Create a .reginfo section for register masks and a .mdebug
1552 section for debugging information. */
1560 subseg
= now_subseg
;
1562 /* The ABI says this section should be loaded so that the
1563 running program can access it. However, we don't load it
1564 if we are configured for an embedded target */
1565 flags
= SEC_READONLY
| SEC_DATA
;
1566 if (strcmp (TARGET_OS
, "elf") != 0)
1567 flags
|= SEC_ALLOC
| SEC_LOAD
;
1569 if (mips_abi
!= N64_ABI
)
1571 sec
= subseg_new (".reginfo", (subsegT
) 0);
1573 bfd_set_section_flags (stdoutput
, sec
, flags
);
1574 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1577 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1582 /* The 64-bit ABI uses a .MIPS.options section rather than
1583 .reginfo section. */
1584 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1585 bfd_set_section_flags (stdoutput
, sec
, flags
);
1586 bfd_set_section_alignment (stdoutput
, sec
, 3);
1589 /* Set up the option header. */
1591 Elf_Internal_Options opthdr
;
1594 opthdr
.kind
= ODK_REGINFO
;
1595 opthdr
.size
= (sizeof (Elf_External_Options
)
1596 + sizeof (Elf64_External_RegInfo
));
1599 f
= frag_more (sizeof (Elf_External_Options
));
1600 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1601 (Elf_External_Options
*) f
);
1603 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1608 if (ECOFF_DEBUGGING
)
1610 sec
= subseg_new (".mdebug", (subsegT
) 0);
1611 (void) bfd_set_section_flags (stdoutput
, sec
,
1612 SEC_HAS_CONTENTS
| SEC_READONLY
);
1613 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1616 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1618 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1619 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1620 SEC_READONLY
| SEC_RELOC
1622 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1626 subseg_set (seg
, subseg
);
1630 if (! ECOFF_DEBUGGING
)
1633 if (mips_fix_vr4120
)
1634 init_vr4120_conflicts ();
1640 if (! ECOFF_DEBUGGING
)
1645 md_assemble (char *str
)
1647 struct mips_cl_insn insn
;
1648 bfd_reloc_code_real_type unused_reloc
[3]
1649 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1651 imm_expr
.X_op
= O_absent
;
1652 imm2_expr
.X_op
= O_absent
;
1653 offset_expr
.X_op
= O_absent
;
1654 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1655 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1656 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1657 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1658 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1659 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1661 if (mips_opts
.mips16
)
1662 mips16_ip (str
, &insn
);
1665 mips_ip (str
, &insn
);
1666 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1667 str
, insn
.insn_opcode
));
1672 as_bad ("%s `%s'", insn_error
, str
);
1676 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1679 if (mips_opts
.mips16
)
1680 mips16_macro (&insn
);
1687 if (imm_expr
.X_op
!= O_absent
)
1688 append_insn (&insn
, &imm_expr
, imm_reloc
);
1689 else if (offset_expr
.X_op
!= O_absent
)
1690 append_insn (&insn
, &offset_expr
, offset_reloc
);
1692 append_insn (&insn
, NULL
, unused_reloc
);
1696 /* Return true if the given relocation might need a matching %lo().
1697 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1698 need a matching %lo() when applied to local symbols. */
1700 static inline bfd_boolean
1701 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1703 return (HAVE_IN_PLACE_ADDENDS
1704 && (reloc
== BFD_RELOC_HI16_S
1705 || reloc
== BFD_RELOC_MIPS16_HI16_S
1706 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
1707 all GOT16 relocations evaluate to "G". */
1708 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
1711 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1714 static inline bfd_boolean
1715 fixup_has_matching_lo_p (fixS
*fixp
)
1717 return (fixp
->fx_next
!= NULL
1718 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1719 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1720 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1721 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1724 /* See whether instruction IP reads register REG. CLASS is the type
1728 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
1729 enum mips_regclass
class)
1731 if (class == MIPS16_REG
)
1733 assert (mips_opts
.mips16
);
1734 reg
= mips16_to_32_reg_map
[reg
];
1735 class = MIPS_GR_REG
;
1738 /* Don't report on general register ZERO, since it never changes. */
1739 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1742 if (class == MIPS_FP_REG
)
1744 assert (! mips_opts
.mips16
);
1745 /* If we are called with either $f0 or $f1, we must check $f0.
1746 This is not optimal, because it will introduce an unnecessary
1747 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1748 need to distinguish reading both $f0 and $f1 or just one of
1749 them. Note that we don't have to check the other way,
1750 because there is no instruction that sets both $f0 and $f1
1751 and requires a delay. */
1752 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1753 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
1754 == (reg
&~ (unsigned) 1)))
1756 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1757 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
1758 == (reg
&~ (unsigned) 1)))
1761 else if (! mips_opts
.mips16
)
1763 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1764 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
1766 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1767 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
1772 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1773 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
1775 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1776 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
1778 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1779 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
1782 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1784 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1786 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1788 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1789 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
1796 /* This function returns true if modifying a register requires a
1800 reg_needs_delay (unsigned int reg
)
1802 unsigned long prev_pinfo
;
1804 prev_pinfo
= history
[0].insn_mo
->pinfo
;
1805 if (! mips_opts
.noreorder
1806 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1807 && ! gpr_interlocks
)
1808 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1809 && ! cop_interlocks
)))
1811 /* A load from a coprocessor or from memory. All load delays
1812 delay the use of general register rt for one instruction. */
1813 /* Itbl support may require additional care here. */
1814 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1815 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
1822 /* Move all labels in insn_labels to the current insertion point. */
1825 mips_move_labels (void)
1827 struct insn_label_list
*l
;
1830 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1832 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1833 symbol_set_frag (l
->label
, frag_now
);
1834 val
= (valueT
) frag_now_fix ();
1835 /* mips16 text labels are stored as odd. */
1836 if (mips_opts
.mips16
)
1838 S_SET_VALUE (l
->label
, val
);
1842 /* Mark instruction labels in mips16 mode. This permits the linker to
1843 handle them specially, such as generating jalx instructions when
1844 needed. We also make them odd for the duration of the assembly, in
1845 order to generate the right sort of code. We will make them even
1846 in the adjust_symtab routine, while leaving them marked. This is
1847 convenient for the debugger and the disassembler. The linker knows
1848 to make them odd again. */
1851 mips16_mark_labels (void)
1853 if (mips_opts
.mips16
)
1855 struct insn_label_list
*l
;
1858 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1861 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1862 S_SET_OTHER (l
->label
, STO_MIPS16
);
1864 val
= S_GET_VALUE (l
->label
);
1866 S_SET_VALUE (l
->label
, val
+ 1);
1871 /* End the current frag. Make it a variant frag and record the
1875 relax_close_frag (void)
1877 mips_macro_warning
.first_frag
= frag_now
;
1878 frag_var (rs_machine_dependent
, 0, 0,
1879 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1880 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1882 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1883 mips_relax
.first_fixup
= 0;
1886 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1887 See the comment above RELAX_ENCODE for more details. */
1890 relax_start (symbolS
*symbol
)
1892 assert (mips_relax
.sequence
== 0);
1893 mips_relax
.sequence
= 1;
1894 mips_relax
.symbol
= symbol
;
1897 /* Start generating the second version of a relaxable sequence.
1898 See the comment above RELAX_ENCODE for more details. */
1903 assert (mips_relax
.sequence
== 1);
1904 mips_relax
.sequence
= 2;
1907 /* End the current relaxable sequence. */
1912 assert (mips_relax
.sequence
== 2);
1913 relax_close_frag ();
1914 mips_relax
.sequence
= 0;
1917 /* Classify an instruction according to the FIX_VR4120_* enumeration.
1918 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1919 by VR4120 errata. */
1922 classify_vr4120_insn (const char *name
)
1924 if (strncmp (name
, "macc", 4) == 0)
1925 return FIX_VR4120_MACC
;
1926 if (strncmp (name
, "dmacc", 5) == 0)
1927 return FIX_VR4120_DMACC
;
1928 if (strncmp (name
, "mult", 4) == 0)
1929 return FIX_VR4120_MULT
;
1930 if (strncmp (name
, "dmult", 5) == 0)
1931 return FIX_VR4120_DMULT
;
1932 if (strstr (name
, "div"))
1933 return FIX_VR4120_DIV
;
1934 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
1935 return FIX_VR4120_MTHILO
;
1936 return NUM_FIX_VR4120_CLASSES
;
1939 /* Return the number of instructions that must separate INSN1 and INSN2,
1940 where INSN1 is the earlier instruction. Return the worst-case value
1941 for any INSN2 if INSN2 is null. */
1944 insns_between (const struct mips_cl_insn
*insn1
,
1945 const struct mips_cl_insn
*insn2
)
1947 unsigned long pinfo1
, pinfo2
;
1949 /* This function needs to know which pinfo flags are set for INSN2
1950 and which registers INSN2 uses. The former is stored in PINFO2 and
1951 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1952 will have every flag set and INSN2_USES_REG will always return true. */
1953 pinfo1
= insn1
->insn_mo
->pinfo
;
1954 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
1956 #define INSN2_USES_REG(REG, CLASS) \
1957 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1959 /* For most targets, write-after-read dependencies on the HI and LO
1960 registers must be separated by at least two instructions. */
1961 if (!hilo_interlocks
)
1963 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
1965 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
1969 /* If we're working around r7000 errata, there must be two instructions
1970 between an mfhi or mflo and any instruction that uses the result. */
1971 if (mips_7000_hilo_fix
1972 && MF_HILO_INSN (pinfo1
)
1973 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
1976 /* If working around VR4120 errata, check for combinations that need
1977 a single intervening instruction. */
1978 if (mips_fix_vr4120
)
1980 unsigned int class1
, class2
;
1982 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
1983 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
1987 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
1988 if (vr4120_conflicts
[class1
] & (1 << class2
))
1993 if (!mips_opts
.mips16
)
1995 /* Check for GPR or coprocessor load delays. All such delays
1996 are on the RT register. */
1997 /* Itbl support may require additional care here. */
1998 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
1999 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2001 know (pinfo1
& INSN_WRITE_GPR_T
);
2002 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2006 /* Check for generic coprocessor hazards.
2008 This case is not handled very well. There is no special
2009 knowledge of CP0 handling, and the coprocessors other than
2010 the floating point unit are not distinguished at all. */
2011 /* Itbl support may require additional care here. FIXME!
2012 Need to modify this to include knowledge about
2013 user specified delays! */
2014 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2015 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2017 /* Handle cases where INSN1 writes to a known general coprocessor
2018 register. There must be a one instruction delay before INSN2
2019 if INSN2 reads that register, otherwise no delay is needed. */
2020 if (pinfo1
& INSN_WRITE_FPR_T
)
2022 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2025 else if (pinfo1
& INSN_WRITE_FPR_S
)
2027 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2032 /* Read-after-write dependencies on the control registers
2033 require a two-instruction gap. */
2034 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2035 && (pinfo2
& INSN_READ_COND_CODE
))
2038 /* We don't know exactly what INSN1 does. If INSN2 is
2039 also a coprocessor instruction, assume there must be
2040 a one instruction gap. */
2041 if (pinfo2
& INSN_COP
)
2046 /* Check for read-after-write dependencies on the coprocessor
2047 control registers in cases where INSN1 does not need a general
2048 coprocessor delay. This means that INSN1 is a floating point
2049 comparison instruction. */
2050 /* Itbl support may require additional care here. */
2051 else if (!cop_interlocks
2052 && (pinfo1
& INSN_WRITE_COND_CODE
)
2053 && (pinfo2
& INSN_READ_COND_CODE
))
2057 #undef INSN2_USES_REG
2062 /* Return the number of nops that would be needed to work around the
2063 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2064 the MAX_VR4130_NOPS instructions described by HISTORY. */
2067 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2068 const struct mips_cl_insn
*insn
)
2072 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2073 are not affected by the errata. */
2075 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2076 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2077 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2080 /* Search for the first MFLO or MFHI. */
2081 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2082 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2084 /* Extract the destination register. */
2085 if (mips_opts
.mips16
)
2086 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2088 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2090 /* No nops are needed if INSN reads that register. */
2091 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2094 /* ...or if any of the intervening instructions do. */
2095 for (j
= 0; j
< i
; j
++)
2096 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2099 return MAX_VR4130_NOPS
- i
;
2104 /* Return the number of nops that would be needed if instruction INSN
2105 immediately followed the MAX_NOPS instructions given by HISTORY,
2106 where HISTORY[0] is the most recent instruction. If INSN is null,
2107 return the worse-case number of nops for any instruction. */
2110 nops_for_insn (const struct mips_cl_insn
*history
,
2111 const struct mips_cl_insn
*insn
)
2113 int i
, nops
, tmp_nops
;
2116 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2117 if (!history
[i
].noreorder_p
)
2119 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2120 if (tmp_nops
> nops
)
2124 if (mips_fix_vr4130
)
2126 tmp_nops
= nops_for_vr4130 (history
, insn
);
2127 if (tmp_nops
> nops
)
2134 /* The variable arguments provide NUM_INSNS extra instructions that
2135 might be added to HISTORY. Return the largest number of nops that
2136 would be needed after the extended sequence. */
2139 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2142 struct mips_cl_insn buffer
[MAX_NOPS
];
2143 struct mips_cl_insn
*cursor
;
2146 va_start (args
, history
);
2147 cursor
= buffer
+ num_insns
;
2148 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2149 while (cursor
> buffer
)
2150 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2152 nops
= nops_for_insn (buffer
, NULL
);
2157 /* Like nops_for_insn, but if INSN is a branch, take into account the
2158 worst-case delay for the branch target. */
2161 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2162 const struct mips_cl_insn
*insn
)
2166 nops
= nops_for_insn (history
, insn
);
2167 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2168 | INSN_COND_BRANCH_DELAY
2169 | INSN_COND_BRANCH_LIKELY
))
2171 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2172 if (tmp_nops
> nops
)
2175 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2177 tmp_nops
= nops_for_sequence (1, history
, insn
);
2178 if (tmp_nops
> nops
)
2184 /* Output an instruction. IP is the instruction information.
2185 ADDRESS_EXPR is an operand of the instruction to be used with
2189 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2190 bfd_reloc_code_real_type
*reloc_type
)
2192 register unsigned long prev_pinfo
, pinfo
;
2193 relax_stateT prev_insn_frag_type
= 0;
2194 bfd_boolean relaxed_branch
= FALSE
;
2196 /* Mark instruction labels in mips16 mode. */
2197 mips16_mark_labels ();
2199 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2200 pinfo
= ip
->insn_mo
->pinfo
;
2202 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2204 /* There are a lot of optimizations we could do that we don't.
2205 In particular, we do not, in general, reorder instructions.
2206 If you use gcc with optimization, it will reorder
2207 instructions and generally do much more optimization then we
2208 do here; repeating all that work in the assembler would only
2209 benefit hand written assembly code, and does not seem worth
2211 int nops
= (mips_optimize
== 0
2212 ? nops_for_insn (history
, NULL
)
2213 : nops_for_insn_or_target (history
, ip
));
2217 unsigned long old_frag_offset
;
2220 old_frag
= frag_now
;
2221 old_frag_offset
= frag_now_fix ();
2223 for (i
= 0; i
< nops
; i
++)
2228 listing_prev_line ();
2229 /* We may be at the start of a variant frag. In case we
2230 are, make sure there is enough space for the frag
2231 after the frags created by listing_prev_line. The
2232 argument to frag_grow here must be at least as large
2233 as the argument to all other calls to frag_grow in
2234 this file. We don't have to worry about being in the
2235 middle of a variant frag, because the variants insert
2236 all needed nop instructions themselves. */
2240 mips_move_labels ();
2242 #ifndef NO_ECOFF_DEBUGGING
2243 if (ECOFF_DEBUGGING
)
2244 ecoff_fix_loc (old_frag
, old_frag_offset
);
2248 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2250 /* Work out how many nops in prev_nop_frag are needed by IP. */
2251 int nops
= nops_for_insn_or_target (history
, ip
);
2252 assert (nops
<= prev_nop_frag_holds
);
2254 /* Enforce NOPS as a minimum. */
2255 if (nops
> prev_nop_frag_required
)
2256 prev_nop_frag_required
= nops
;
2258 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2260 /* Settle for the current number of nops. Update the history
2261 accordingly (for the benefit of any future .set reorder code). */
2262 prev_nop_frag
= NULL
;
2263 insert_into_history (prev_nop_frag_since
,
2264 prev_nop_frag_holds
, NOP_INSN
);
2268 /* Allow this instruction to replace one of the nops that was
2269 tentatively added to prev_nop_frag. */
2270 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2271 prev_nop_frag_holds
--;
2272 prev_nop_frag_since
++;
2277 /* The value passed to dwarf2_emit_insn is the distance between
2278 the beginning of the current instruction and the address that
2279 should be recorded in the debug tables. For MIPS16 debug info
2280 we want to use ISA-encoded addresses, so we pass -1 for an
2281 address higher by one than the current. */
2282 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2285 /* Record the frag type before frag_var. */
2286 if (history
[0].frag
)
2287 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2290 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2291 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2292 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2293 && mips_relax_branch
2294 /* Don't try branch relaxation within .set nomacro, or within
2295 .set noat if we use $at for PIC computations. If it turns
2296 out that the branch was out-of-range, we'll get an error. */
2297 && !mips_opts
.warn_about_macros
2298 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2299 && !mips_opts
.mips16
)
2301 relaxed_branch
= TRUE
;
2302 add_relaxed_insn (ip
, (relaxed_branch_length
2304 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2305 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2308 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2309 pinfo
& INSN_COND_BRANCH_LIKELY
,
2310 pinfo
& INSN_WRITE_GPR_31
,
2312 address_expr
->X_add_symbol
,
2313 address_expr
->X_add_number
);
2314 *reloc_type
= BFD_RELOC_UNUSED
;
2316 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2318 /* We need to set up a variant frag. */
2319 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2320 add_relaxed_insn (ip
, 4, 0,
2322 (*reloc_type
- BFD_RELOC_UNUSED
,
2323 mips16_small
, mips16_ext
,
2324 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2325 history
[0].mips16_absolute_jump_p
),
2326 make_expr_symbol (address_expr
), 0);
2328 else if (mips_opts
.mips16
2330 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2332 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2333 /* Make sure there is enough room to swap this instruction with
2334 a following jump instruction. */
2336 add_fixed_insn (ip
);
2340 if (mips_opts
.mips16
2341 && mips_opts
.noreorder
2342 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2343 as_warn (_("extended instruction in delay slot"));
2345 if (mips_relax
.sequence
)
2347 /* If we've reached the end of this frag, turn it into a variant
2348 frag and record the information for the instructions we've
2350 if (frag_room () < 4)
2351 relax_close_frag ();
2352 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2355 if (mips_relax
.sequence
!= 2)
2356 mips_macro_warning
.sizes
[0] += 4;
2357 if (mips_relax
.sequence
!= 1)
2358 mips_macro_warning
.sizes
[1] += 4;
2360 if (mips_opts
.mips16
)
2363 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2365 add_fixed_insn (ip
);
2368 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2370 if (address_expr
->X_op
== O_constant
)
2374 switch (*reloc_type
)
2377 ip
->insn_opcode
|= address_expr
->X_add_number
;
2380 case BFD_RELOC_MIPS_HIGHEST
:
2381 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2382 ip
->insn_opcode
|= tmp
& 0xffff;
2385 case BFD_RELOC_MIPS_HIGHER
:
2386 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2387 ip
->insn_opcode
|= tmp
& 0xffff;
2390 case BFD_RELOC_HI16_S
:
2391 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2392 ip
->insn_opcode
|= tmp
& 0xffff;
2395 case BFD_RELOC_HI16
:
2396 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2399 case BFD_RELOC_UNUSED
:
2400 case BFD_RELOC_LO16
:
2401 case BFD_RELOC_MIPS_GOT_DISP
:
2402 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2405 case BFD_RELOC_MIPS_JMP
:
2406 if ((address_expr
->X_add_number
& 3) != 0)
2407 as_bad (_("jump to misaligned address (0x%lx)"),
2408 (unsigned long) address_expr
->X_add_number
);
2409 if (address_expr
->X_add_number
& ~0xfffffff)
2410 as_bad (_("jump address range overflow (0x%lx)"),
2411 (unsigned long) address_expr
->X_add_number
);
2412 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2415 case BFD_RELOC_MIPS16_JMP
:
2416 if ((address_expr
->X_add_number
& 3) != 0)
2417 as_bad (_("jump to misaligned address (0x%lx)"),
2418 (unsigned long) address_expr
->X_add_number
);
2419 if (address_expr
->X_add_number
& ~0xfffffff)
2420 as_bad (_("jump address range overflow (0x%lx)"),
2421 (unsigned long) address_expr
->X_add_number
);
2423 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2424 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2425 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2428 case BFD_RELOC_16_PCREL_S2
:
2429 if ((address_expr
->X_add_number
& 3) != 0)
2430 as_bad (_("branch to misaligned address (0x%lx)"),
2431 (unsigned long) address_expr
->X_add_number
);
2432 if (mips_relax_branch
)
2434 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2435 as_bad (_("branch address range overflow (0x%lx)"),
2436 (unsigned long) address_expr
->X_add_number
);
2437 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2444 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2447 reloc_howto_type
*howto
;
2450 /* In a compound relocation, it is the final (outermost)
2451 operator that determines the relocated field. */
2452 for (i
= 1; i
< 3; i
++)
2453 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2456 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2457 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2458 bfd_get_reloc_size (howto
),
2460 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2463 /* These relocations can have an addend that won't fit in
2464 4 octets for 64bit assembly. */
2466 && ! howto
->partial_inplace
2467 && (reloc_type
[0] == BFD_RELOC_16
2468 || reloc_type
[0] == BFD_RELOC_32
2469 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2470 || reloc_type
[0] == BFD_RELOC_HI16_S
2471 || reloc_type
[0] == BFD_RELOC_LO16
2472 || reloc_type
[0] == BFD_RELOC_GPREL16
2473 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2474 || reloc_type
[0] == BFD_RELOC_GPREL32
2475 || reloc_type
[0] == BFD_RELOC_64
2476 || reloc_type
[0] == BFD_RELOC_CTOR
2477 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2478 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2479 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2480 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2481 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2482 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2483 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2484 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2485 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2486 ip
->fixp
[0]->fx_no_overflow
= 1;
2488 if (mips_relax
.sequence
)
2490 if (mips_relax
.first_fixup
== 0)
2491 mips_relax
.first_fixup
= ip
->fixp
[0];
2493 else if (reloc_needs_lo_p (*reloc_type
))
2495 struct mips_hi_fixup
*hi_fixup
;
2497 /* Reuse the last entry if it already has a matching %lo. */
2498 hi_fixup
= mips_hi_fixup_list
;
2500 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2502 hi_fixup
= ((struct mips_hi_fixup
*)
2503 xmalloc (sizeof (struct mips_hi_fixup
)));
2504 hi_fixup
->next
= mips_hi_fixup_list
;
2505 mips_hi_fixup_list
= hi_fixup
;
2507 hi_fixup
->fixp
= ip
->fixp
[0];
2508 hi_fixup
->seg
= now_seg
;
2511 /* Add fixups for the second and third relocations, if given.
2512 Note that the ABI allows the second relocation to be
2513 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2514 moment we only use RSS_UNDEF, but we could add support
2515 for the others if it ever becomes necessary. */
2516 for (i
= 1; i
< 3; i
++)
2517 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2519 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2520 ip
->fixp
[0]->fx_size
, NULL
, 0,
2521 FALSE
, reloc_type
[i
]);
2523 /* Use fx_tcbit to mark compound relocs. */
2524 ip
->fixp
[0]->fx_tcbit
= 1;
2525 ip
->fixp
[i
]->fx_tcbit
= 1;
2531 /* Update the register mask information. */
2532 if (! mips_opts
.mips16
)
2534 if (pinfo
& INSN_WRITE_GPR_D
)
2535 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2536 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2537 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2538 if (pinfo
& INSN_READ_GPR_S
)
2539 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2540 if (pinfo
& INSN_WRITE_GPR_31
)
2541 mips_gprmask
|= 1 << RA
;
2542 if (pinfo
& INSN_WRITE_FPR_D
)
2543 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2544 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2545 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2546 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2547 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2548 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2549 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2550 if (pinfo
& INSN_COP
)
2552 /* We don't keep enough information to sort these cases out.
2553 The itbl support does keep this information however, although
2554 we currently don't support itbl fprmats as part of the cop
2555 instruction. May want to add this support in the future. */
2557 /* Never set the bit for $0, which is always zero. */
2558 mips_gprmask
&= ~1 << 0;
2562 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2563 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2564 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2565 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2566 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2567 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2568 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2569 mips_gprmask
|= 1 << TREG
;
2570 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2571 mips_gprmask
|= 1 << SP
;
2572 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2573 mips_gprmask
|= 1 << RA
;
2574 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2575 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2576 if (pinfo
& MIPS16_INSN_READ_Z
)
2577 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2578 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2579 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2582 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2584 /* Filling the branch delay slot is more complex. We try to
2585 switch the branch with the previous instruction, which we can
2586 do if the previous instruction does not set up a condition
2587 that the branch tests and if the branch is not itself the
2588 target of any branch. */
2589 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2590 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2592 if (mips_optimize
< 2
2593 /* If we have seen .set volatile or .set nomove, don't
2595 || mips_opts
.nomove
!= 0
2596 /* We can't swap if the previous instruction's position
2598 || history
[0].fixed_p
2599 /* If the previous previous insn was in a .set
2600 noreorder, we can't swap. Actually, the MIPS
2601 assembler will swap in this situation. However, gcc
2602 configured -with-gnu-as will generate code like
2608 in which we can not swap the bne and INSN. If gcc is
2609 not configured -with-gnu-as, it does not output the
2611 || history
[1].noreorder_p
2612 /* If the branch is itself the target of a branch, we
2613 can not swap. We cheat on this; all we check for is
2614 whether there is a label on this instruction. If
2615 there are any branches to anything other than a
2616 label, users must use .set noreorder. */
2617 || insn_labels
!= NULL
2618 /* If the previous instruction is in a variant frag
2619 other than this branch's one, we cannot do the swap.
2620 This does not apply to the mips16, which uses variant
2621 frags for different purposes. */
2622 || (! mips_opts
.mips16
2623 && prev_insn_frag_type
== rs_machine_dependent
)
2624 /* Check for conflicts between the branch and the instructions
2625 before the candidate delay slot. */
2626 || nops_for_insn (history
+ 1, ip
) > 0
2627 /* Check for conflicts between the swapped sequence and the
2628 target of the branch. */
2629 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2630 /* We do not swap with a trap instruction, since it
2631 complicates trap handlers to have the trap
2632 instruction be in a delay slot. */
2633 || (prev_pinfo
& INSN_TRAP
)
2634 /* If the branch reads a register that the previous
2635 instruction sets, we can not swap. */
2636 || (! mips_opts
.mips16
2637 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2638 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2640 || (! mips_opts
.mips16
2641 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2642 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2644 || (mips_opts
.mips16
2645 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2647 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2649 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2651 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2653 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2655 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2657 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2658 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2659 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2660 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2661 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2662 && insn_uses_reg (ip
,
2663 MIPS16OP_EXTRACT_REG32R
2664 (history
[0].insn_opcode
),
2666 /* If the branch writes a register that the previous
2667 instruction sets, we can not swap (we know that
2668 branches write only to RD or to $31). */
2669 || (! mips_opts
.mips16
2670 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2671 && (((pinfo
& INSN_WRITE_GPR_D
)
2672 && (EXTRACT_OPERAND (RT
, history
[0])
2673 == EXTRACT_OPERAND (RD
, *ip
)))
2674 || ((pinfo
& INSN_WRITE_GPR_31
)
2675 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2676 || (! mips_opts
.mips16
2677 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2678 && (((pinfo
& INSN_WRITE_GPR_D
)
2679 && (EXTRACT_OPERAND (RD
, history
[0])
2680 == EXTRACT_OPERAND (RD
, *ip
)))
2681 || ((pinfo
& INSN_WRITE_GPR_31
)
2682 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2683 || (mips_opts
.mips16
2684 && (pinfo
& MIPS16_INSN_WRITE_31
)
2685 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2686 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2687 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2689 /* If the branch writes a register that the previous
2690 instruction reads, we can not swap (we know that
2691 branches only write to RD or to $31). */
2692 || (! mips_opts
.mips16
2693 && (pinfo
& INSN_WRITE_GPR_D
)
2694 && insn_uses_reg (&history
[0],
2695 EXTRACT_OPERAND (RD
, *ip
),
2697 || (! mips_opts
.mips16
2698 && (pinfo
& INSN_WRITE_GPR_31
)
2699 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2700 || (mips_opts
.mips16
2701 && (pinfo
& MIPS16_INSN_WRITE_31
)
2702 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2703 /* If one instruction sets a condition code and the
2704 other one uses a condition code, we can not swap. */
2705 || ((pinfo
& INSN_READ_COND_CODE
)
2706 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2707 || ((pinfo
& INSN_WRITE_COND_CODE
)
2708 && (prev_pinfo
& INSN_READ_COND_CODE
))
2709 /* If the previous instruction uses the PC, we can not
2711 || (mips_opts
.mips16
2712 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2713 /* If the previous instruction had a fixup in mips16
2714 mode, we can not swap. This normally means that the
2715 previous instruction was a 4 byte branch anyhow. */
2716 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2717 /* If the previous instruction is a sync, sync.l, or
2718 sync.p, we can not swap. */
2719 || (prev_pinfo
& INSN_SYNC
))
2721 if (mips_opts
.mips16
2722 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2723 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
2724 && (mips_opts
.isa
== ISA_MIPS32
2725 || mips_opts
.isa
== ISA_MIPS32R2
2726 || mips_opts
.isa
== ISA_MIPS64
2727 || mips_opts
.isa
== ISA_MIPS64R2
))
2729 /* Convert MIPS16 jr/jalr into a "compact" jump. */
2730 ip
->insn_opcode
|= 0x0080;
2732 insert_into_history (0, 1, ip
);
2736 /* We could do even better for unconditional branches to
2737 portions of this object file; we could pick up the
2738 instruction at the destination, put it in the delay
2739 slot, and bump the destination address. */
2740 insert_into_history (0, 1, ip
);
2744 if (mips_relax
.sequence
)
2745 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2749 /* It looks like we can actually do the swap. */
2750 struct mips_cl_insn delay
= history
[0];
2751 if (mips_opts
.mips16
)
2753 know (delay
.frag
== ip
->frag
);
2754 move_insn (ip
, delay
.frag
, delay
.where
);
2755 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
2757 else if (relaxed_branch
)
2759 /* Add the delay slot instruction to the end of the
2760 current frag and shrink the fixed part of the
2761 original frag. If the branch occupies the tail of
2762 the latter, move it backwards to cover the gap. */
2763 delay
.frag
->fr_fix
-= 4;
2764 if (delay
.frag
== ip
->frag
)
2765 move_insn (ip
, ip
->frag
, ip
->where
- 4);
2766 add_fixed_insn (&delay
);
2770 move_insn (&delay
, ip
->frag
, ip
->where
);
2771 move_insn (ip
, history
[0].frag
, history
[0].where
);
2775 insert_into_history (0, 1, &delay
);
2778 /* If that was an unconditional branch, forget the previous
2779 insn information. */
2780 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2781 mips_no_prev_insn ();
2783 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2785 /* We don't yet optimize a branch likely. What we should do
2786 is look at the target, copy the instruction found there
2787 into the delay slot, and increment the branch to jump to
2788 the next instruction. */
2789 insert_into_history (0, 1, ip
);
2793 insert_into_history (0, 1, ip
);
2796 insert_into_history (0, 1, ip
);
2798 /* We just output an insn, so the next one doesn't have a label. */
2799 mips_clear_insn_labels ();
2802 /* Forget that there was any previous instruction or label. */
2805 mips_no_prev_insn (void)
2807 prev_nop_frag
= NULL
;
2808 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
2809 mips_clear_insn_labels ();
2812 /* This function must be called before we emit something other than
2813 instructions. It is like mips_no_prev_insn except that it inserts
2814 any NOPS that might be needed by previous instructions. */
2817 mips_emit_delays (void)
2819 if (! mips_opts
.noreorder
)
2821 int nops
= nops_for_insn (history
, NULL
);
2825 add_fixed_insn (NOP_INSN
);
2826 mips_move_labels ();
2829 mips_no_prev_insn ();
2832 /* Start a (possibly nested) noreorder block. */
2835 start_noreorder (void)
2837 if (mips_opts
.noreorder
== 0)
2842 /* None of the instructions before the .set noreorder can be moved. */
2843 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
2844 history
[i
].fixed_p
= 1;
2846 /* Insert any nops that might be needed between the .set noreorder
2847 block and the previous instructions. We will later remove any
2848 nops that turn out not to be needed. */
2849 nops
= nops_for_insn (history
, NULL
);
2852 if (mips_optimize
!= 0)
2854 /* Record the frag which holds the nop instructions, so
2855 that we can remove them if we don't need them. */
2856 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2857 prev_nop_frag
= frag_now
;
2858 prev_nop_frag_holds
= nops
;
2859 prev_nop_frag_required
= 0;
2860 prev_nop_frag_since
= 0;
2863 for (; nops
> 0; --nops
)
2864 add_fixed_insn (NOP_INSN
);
2866 /* Move on to a new frag, so that it is safe to simply
2867 decrease the size of prev_nop_frag. */
2868 frag_wane (frag_now
);
2870 mips_move_labels ();
2872 mips16_mark_labels ();
2873 mips_clear_insn_labels ();
2875 mips_opts
.noreorder
++;
2876 mips_any_noreorder
= 1;
2879 /* End a nested noreorder block. */
2882 end_noreorder (void)
2884 mips_opts
.noreorder
--;
2885 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
2887 /* Commit to inserting prev_nop_frag_required nops and go back to
2888 handling nop insertion the .set reorder way. */
2889 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
2890 * (mips_opts
.mips16
? 2 : 4));
2891 insert_into_history (prev_nop_frag_since
,
2892 prev_nop_frag_required
, NOP_INSN
);
2893 prev_nop_frag
= NULL
;
2897 /* Set up global variables for the start of a new macro. */
2902 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2903 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2904 && (history
[0].insn_mo
->pinfo
2905 & (INSN_UNCOND_BRANCH_DELAY
2906 | INSN_COND_BRANCH_DELAY
2907 | INSN_COND_BRANCH_LIKELY
)) != 0);
2910 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2911 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2912 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2915 macro_warning (relax_substateT subtype
)
2917 if (subtype
& RELAX_DELAY_SLOT
)
2918 return _("Macro instruction expanded into multiple instructions"
2919 " in a branch delay slot");
2920 else if (subtype
& RELAX_NOMACRO
)
2921 return _("Macro instruction expanded into multiple instructions");
2926 /* Finish up a macro. Emit warnings as appropriate. */
2931 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2933 relax_substateT subtype
;
2935 /* Set up the relaxation warning flags. */
2937 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2938 subtype
|= RELAX_SECOND_LONGER
;
2939 if (mips_opts
.warn_about_macros
)
2940 subtype
|= RELAX_NOMACRO
;
2941 if (mips_macro_warning
.delay_slot_p
)
2942 subtype
|= RELAX_DELAY_SLOT
;
2944 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2946 /* Either the macro has a single implementation or both
2947 implementations are longer than 4 bytes. Emit the
2949 const char *msg
= macro_warning (subtype
);
2955 /* One implementation might need a warning but the other
2956 definitely doesn't. */
2957 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2962 /* Read a macro's relocation codes from *ARGS and store them in *R.
2963 The first argument in *ARGS will be either the code for a single
2964 relocation or -1 followed by the three codes that make up a
2965 composite relocation. */
2968 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2972 next
= va_arg (*args
, int);
2974 r
[0] = (bfd_reloc_code_real_type
) next
;
2976 for (i
= 0; i
< 3; i
++)
2977 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2980 /* Build an instruction created by a macro expansion. This is passed
2981 a pointer to the count of instructions created so far, an
2982 expression, the name of the instruction to build, an operand format
2983 string, and corresponding arguments. */
2986 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2988 const struct mips_opcode
*mo
;
2989 struct mips_cl_insn insn
;
2990 bfd_reloc_code_real_type r
[3];
2993 va_start (args
, fmt
);
2995 if (mips_opts
.mips16
)
2997 mips16_macro_build (ep
, name
, fmt
, args
);
3002 r
[0] = BFD_RELOC_UNUSED
;
3003 r
[1] = BFD_RELOC_UNUSED
;
3004 r
[2] = BFD_RELOC_UNUSED
;
3005 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3007 assert (strcmp (name
, mo
->name
) == 0);
3009 /* Search until we get a match for NAME. It is assumed here that
3010 macros will never generate MDMX or MIPS-3D instructions. */
3011 while (strcmp (fmt
, mo
->args
) != 0
3012 || mo
->pinfo
== INSN_MACRO
3013 || !OPCODE_IS_MEMBER (mo
,
3015 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3017 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
3021 assert (strcmp (name
, mo
->name
) == 0);
3024 create_insn (&insn
, mo
);
3042 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3047 /* Note that in the macro case, these arguments are already
3048 in MSB form. (When handling the instruction in the
3049 non-macro case, these arguments are sizes from which
3050 MSB values must be calculated.) */
3051 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3057 /* Note that in the macro case, these arguments are already
3058 in MSBD form. (When handling the instruction in the
3059 non-macro case, these arguments are sizes from which
3060 MSBD values must be calculated.) */
3061 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3072 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3076 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3081 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3087 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3092 int tmp
= va_arg (args
, int);
3094 INSERT_OPERAND (RT
, insn
, tmp
);
3095 INSERT_OPERAND (RD
, insn
, tmp
);
3101 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3108 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3112 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3116 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3120 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3124 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3131 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3137 macro_read_relocs (&args
, r
);
3138 assert (*r
== BFD_RELOC_GPREL16
3139 || *r
== BFD_RELOC_MIPS_LITERAL
3140 || *r
== BFD_RELOC_MIPS_HIGHER
3141 || *r
== BFD_RELOC_HI16_S
3142 || *r
== BFD_RELOC_LO16
3143 || *r
== BFD_RELOC_MIPS_GOT16
3144 || *r
== BFD_RELOC_MIPS_CALL16
3145 || *r
== BFD_RELOC_MIPS_GOT_DISP
3146 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3147 || *r
== BFD_RELOC_MIPS_GOT_OFST
3148 || *r
== BFD_RELOC_MIPS_GOT_LO16
3149 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3153 macro_read_relocs (&args
, r
);
3155 && (ep
->X_op
== O_constant
3156 || (ep
->X_op
== O_symbol
3157 && (*r
== BFD_RELOC_MIPS_HIGHEST
3158 || *r
== BFD_RELOC_HI16_S
3159 || *r
== BFD_RELOC_HI16
3160 || *r
== BFD_RELOC_GPREL16
3161 || *r
== BFD_RELOC_MIPS_GOT_HI16
3162 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3166 assert (ep
!= NULL
);
3169 * This allows macro() to pass an immediate expression for
3170 * creating short branches without creating a symbol.
3172 * We don't allow branch relaxation for these branches, as
3173 * they should only appear in ".set nomacro" anyway.
3175 if (ep
->X_op
== O_constant
)
3177 if ((ep
->X_add_number
& 3) != 0)
3178 as_bad (_("branch to misaligned address (0x%lx)"),
3179 (unsigned long) ep
->X_add_number
);
3180 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3181 as_bad (_("branch address range overflow (0x%lx)"),
3182 (unsigned long) ep
->X_add_number
);
3183 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3187 *r
= BFD_RELOC_16_PCREL_S2
;
3191 assert (ep
!= NULL
);
3192 *r
= BFD_RELOC_MIPS_JMP
;
3196 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3205 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3207 append_insn (&insn
, ep
, r
);
3211 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3214 struct mips_opcode
*mo
;
3215 struct mips_cl_insn insn
;
3216 bfd_reloc_code_real_type r
[3]
3217 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3219 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3221 assert (strcmp (name
, mo
->name
) == 0);
3223 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3227 assert (strcmp (name
, mo
->name
) == 0);
3230 create_insn (&insn
, mo
);
3248 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3253 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3257 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3261 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3271 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3278 regno
= va_arg (args
, int);
3279 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3280 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3301 assert (ep
!= NULL
);
3303 if (ep
->X_op
!= O_constant
)
3304 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3307 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3308 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3311 *r
= BFD_RELOC_UNUSED
;
3317 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3324 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3326 append_insn (&insn
, ep
, r
);
3330 * Sign-extend 32-bit mode constants that have bit 31 set and all
3331 * higher bits unset.
3334 normalize_constant_expr (expressionS
*ex
)
3336 if (ex
->X_op
== O_constant
3337 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3338 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3343 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3344 * all higher bits unset.
3347 normalize_address_expr (expressionS
*ex
)
3349 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3350 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3351 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3352 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3357 * Generate a "jalr" instruction with a relocation hint to the called
3358 * function. This occurs in NewABI PIC code.
3361 macro_build_jalr (expressionS
*ep
)
3370 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3372 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3373 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3377 * Generate a "lui" instruction.
3380 macro_build_lui (expressionS
*ep
, int regnum
)
3382 expressionS high_expr
;
3383 const struct mips_opcode
*mo
;
3384 struct mips_cl_insn insn
;
3385 bfd_reloc_code_real_type r
[3]
3386 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3387 const char *name
= "lui";
3388 const char *fmt
= "t,u";
3390 assert (! mips_opts
.mips16
);
3394 if (high_expr
.X_op
== O_constant
)
3396 /* we can compute the instruction now without a relocation entry */
3397 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3399 *r
= BFD_RELOC_UNUSED
;
3403 assert (ep
->X_op
== O_symbol
);
3404 /* _gp_disp is a special case, used from s_cpload.
3405 __gnu_local_gp is used if mips_no_shared. */
3406 assert (mips_pic
== NO_PIC
3408 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3409 || (! mips_in_shared
3410 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3411 "__gnu_local_gp") == 0));
3412 *r
= BFD_RELOC_HI16_S
;
3415 mo
= hash_find (op_hash
, name
);
3416 assert (strcmp (name
, mo
->name
) == 0);
3417 assert (strcmp (fmt
, mo
->args
) == 0);
3418 create_insn (&insn
, mo
);
3420 insn
.insn_opcode
= insn
.insn_mo
->match
;
3421 INSERT_OPERAND (RT
, insn
, regnum
);
3422 if (*r
== BFD_RELOC_UNUSED
)
3424 insn
.insn_opcode
|= high_expr
.X_add_number
;
3425 append_insn (&insn
, NULL
, r
);
3428 append_insn (&insn
, &high_expr
, r
);
3431 /* Generate a sequence of instructions to do a load or store from a constant
3432 offset off of a base register (breg) into/from a target register (treg),
3433 using AT if necessary. */
3435 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3436 int treg
, int breg
, int dbl
)
3438 assert (ep
->X_op
== O_constant
);
3440 /* Sign-extending 32-bit constants makes their handling easier. */
3442 normalize_constant_expr (ep
);
3444 /* Right now, this routine can only handle signed 32-bit constants. */
3445 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3446 as_warn (_("operand overflow"));
3448 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3450 /* Signed 16-bit offset will fit in the op. Easy! */
3451 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3455 /* 32-bit offset, need multiple instructions and AT, like:
3456 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3457 addu $tempreg,$tempreg,$breg
3458 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3459 to handle the complete offset. */
3460 macro_build_lui (ep
, AT
);
3461 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3462 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3465 as_bad (_("Macro used $at after \".set noat\""));
3470 * Generates code to set the $at register to true (one)
3471 * if reg is less than the immediate expression.
3474 set_at (int reg
, int unsignedp
)
3476 if (imm_expr
.X_op
== O_constant
3477 && imm_expr
.X_add_number
>= -0x8000
3478 && imm_expr
.X_add_number
< 0x8000)
3479 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3480 AT
, reg
, BFD_RELOC_LO16
);
3483 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3484 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3488 /* Warn if an expression is not a constant. */
3491 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3493 if (ex
->X_op
== O_big
)
3494 as_bad (_("unsupported large constant"));
3495 else if (ex
->X_op
!= O_constant
)
3496 as_bad (_("Instruction %s requires absolute expression"),
3499 if (HAVE_32BIT_GPRS
)
3500 normalize_constant_expr (ex
);
3503 /* Count the leading zeroes by performing a binary chop. This is a
3504 bulky bit of source, but performance is a LOT better for the
3505 majority of values than a simple loop to count the bits:
3506 for (lcnt = 0; (lcnt < 32); lcnt++)
3507 if ((v) & (1 << (31 - lcnt)))
3509 However it is not code size friendly, and the gain will drop a bit
3510 on certain cached systems.
3512 #define COUNT_TOP_ZEROES(v) \
3513 (((v) & ~0xffff) == 0 \
3514 ? ((v) & ~0xff) == 0 \
3515 ? ((v) & ~0xf) == 0 \
3516 ? ((v) & ~0x3) == 0 \
3517 ? ((v) & ~0x1) == 0 \
3522 : ((v) & ~0x7) == 0 \
3525 : ((v) & ~0x3f) == 0 \
3526 ? ((v) & ~0x1f) == 0 \
3529 : ((v) & ~0x7f) == 0 \
3532 : ((v) & ~0xfff) == 0 \
3533 ? ((v) & ~0x3ff) == 0 \
3534 ? ((v) & ~0x1ff) == 0 \
3537 : ((v) & ~0x7ff) == 0 \
3540 : ((v) & ~0x3fff) == 0 \
3541 ? ((v) & ~0x1fff) == 0 \
3544 : ((v) & ~0x7fff) == 0 \
3547 : ((v) & ~0xffffff) == 0 \
3548 ? ((v) & ~0xfffff) == 0 \
3549 ? ((v) & ~0x3ffff) == 0 \
3550 ? ((v) & ~0x1ffff) == 0 \
3553 : ((v) & ~0x7ffff) == 0 \
3556 : ((v) & ~0x3fffff) == 0 \
3557 ? ((v) & ~0x1fffff) == 0 \
3560 : ((v) & ~0x7fffff) == 0 \
3563 : ((v) & ~0xfffffff) == 0 \
3564 ? ((v) & ~0x3ffffff) == 0 \
3565 ? ((v) & ~0x1ffffff) == 0 \
3568 : ((v) & ~0x7ffffff) == 0 \
3571 : ((v) & ~0x3fffffff) == 0 \
3572 ? ((v) & ~0x1fffffff) == 0 \
3575 : ((v) & ~0x7fffffff) == 0 \
3580 * This routine generates the least number of instructions necessary to load
3581 * an absolute expression value into a register.
3584 load_register (int reg
, expressionS
*ep
, int dbl
)
3587 expressionS hi32
, lo32
;
3589 if (ep
->X_op
!= O_big
)
3591 assert (ep
->X_op
== O_constant
);
3593 /* Sign-extending 32-bit constants makes their handling easier. */
3595 normalize_constant_expr (ep
);
3597 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3599 /* We can handle 16 bit signed values with an addiu to
3600 $zero. No need to ever use daddiu here, since $zero and
3601 the result are always correct in 32 bit mode. */
3602 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3605 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3607 /* We can handle 16 bit unsigned values with an ori to
3609 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3612 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3614 /* 32 bit values require an lui. */
3615 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3616 if ((ep
->X_add_number
& 0xffff) != 0)
3617 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3622 /* The value is larger than 32 bits. */
3624 if (!dbl
|| HAVE_32BIT_GPRS
)
3628 sprintf_vma (value
, ep
->X_add_number
);
3629 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3630 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3634 if (ep
->X_op
!= O_big
)
3637 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3638 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3639 hi32
.X_add_number
&= 0xffffffff;
3641 lo32
.X_add_number
&= 0xffffffff;
3645 assert (ep
->X_add_number
> 2);
3646 if (ep
->X_add_number
== 3)
3647 generic_bignum
[3] = 0;
3648 else if (ep
->X_add_number
> 4)
3649 as_bad (_("Number larger than 64 bits"));
3650 lo32
.X_op
= O_constant
;
3651 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3652 hi32
.X_op
= O_constant
;
3653 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3656 if (hi32
.X_add_number
== 0)
3661 unsigned long hi
, lo
;
3663 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3665 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3667 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3670 if (lo32
.X_add_number
& 0x80000000)
3672 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3673 if (lo32
.X_add_number
& 0xffff)
3674 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3679 /* Check for 16bit shifted constant. We know that hi32 is
3680 non-zero, so start the mask on the first bit of the hi32
3685 unsigned long himask
, lomask
;
3689 himask
= 0xffff >> (32 - shift
);
3690 lomask
= (0xffff << shift
) & 0xffffffff;
3694 himask
= 0xffff << (shift
- 32);
3697 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3698 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3702 tmp
.X_op
= O_constant
;
3704 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3705 | (lo32
.X_add_number
>> shift
));
3707 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3708 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3709 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3710 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3715 while (shift
<= (64 - 16));
3717 /* Find the bit number of the lowest one bit, and store the
3718 shifted value in hi/lo. */
3719 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3720 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3724 while ((lo
& 1) == 0)
3729 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3735 while ((hi
& 1) == 0)
3744 /* Optimize if the shifted value is a (power of 2) - 1. */
3745 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3746 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3748 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3753 /* This instruction will set the register to be all
3755 tmp
.X_op
= O_constant
;
3756 tmp
.X_add_number
= (offsetT
) -1;
3757 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3761 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3762 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3764 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3765 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3770 /* Sign extend hi32 before calling load_register, because we can
3771 generally get better code when we load a sign extended value. */
3772 if ((hi32
.X_add_number
& 0x80000000) != 0)
3773 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3774 load_register (reg
, &hi32
, 0);
3777 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3781 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3789 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3791 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3792 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3798 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3802 mid16
.X_add_number
>>= 16;
3803 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3804 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3807 if ((lo32
.X_add_number
& 0xffff) != 0)
3808 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3812 load_delay_nop (void)
3814 if (!gpr_interlocks
)
3815 macro_build (NULL
, "nop", "");
3818 /* Load an address into a register. */
3821 load_address (int reg
, expressionS
*ep
, int *used_at
)
3823 if (ep
->X_op
!= O_constant
3824 && ep
->X_op
!= O_symbol
)
3826 as_bad (_("expression too complex"));
3827 ep
->X_op
= O_constant
;
3830 if (ep
->X_op
== O_constant
)
3832 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3836 if (mips_pic
== NO_PIC
)
3838 /* If this is a reference to a GP relative symbol, we want
3839 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3841 lui $reg,<sym> (BFD_RELOC_HI16_S)
3842 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3843 If we have an addend, we always use the latter form.
3845 With 64bit address space and a usable $at we want
3846 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3847 lui $at,<sym> (BFD_RELOC_HI16_S)
3848 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3849 daddiu $at,<sym> (BFD_RELOC_LO16)
3853 If $at is already in use, we use a path which is suboptimal
3854 on superscalar processors.
3855 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3856 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3858 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3860 daddiu $reg,<sym> (BFD_RELOC_LO16)
3862 For GP relative symbols in 64bit address space we can use
3863 the same sequence as in 32bit address space. */
3864 if (HAVE_64BIT_SYMBOLS
)
3866 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3867 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3869 relax_start (ep
->X_add_symbol
);
3870 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3871 mips_gp_register
, BFD_RELOC_GPREL16
);
3875 if (*used_at
== 0 && !mips_opts
.noat
)
3877 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3878 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3879 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3880 BFD_RELOC_MIPS_HIGHER
);
3881 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3882 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3883 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3888 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3889 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3890 BFD_RELOC_MIPS_HIGHER
);
3891 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3892 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3893 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3894 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3897 if (mips_relax
.sequence
)
3902 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3903 && !nopic_need_relax (ep
->X_add_symbol
, 1))
3905 relax_start (ep
->X_add_symbol
);
3906 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3907 mips_gp_register
, BFD_RELOC_GPREL16
);
3910 macro_build_lui (ep
, reg
);
3911 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3912 reg
, reg
, BFD_RELOC_LO16
);
3913 if (mips_relax
.sequence
)
3917 else if (!mips_big_got
)
3921 /* If this is a reference to an external symbol, we want
3922 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3926 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3927 If there is a constant, it must be added in after.
3929 If we have NewABI, we want
3930 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3931 unless we're referencing a global symbol with a non-zero
3932 offset, in which case cst must be added separately. */
3935 if (ep
->X_add_number
)
3937 ex
.X_add_number
= ep
->X_add_number
;
3938 ep
->X_add_number
= 0;
3939 relax_start (ep
->X_add_symbol
);
3940 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3941 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3942 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3943 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3944 ex
.X_op
= O_constant
;
3945 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3946 reg
, reg
, BFD_RELOC_LO16
);
3947 ep
->X_add_number
= ex
.X_add_number
;
3950 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3951 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3952 if (mips_relax
.sequence
)
3957 ex
.X_add_number
= ep
->X_add_number
;
3958 ep
->X_add_number
= 0;
3959 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3960 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3962 relax_start (ep
->X_add_symbol
);
3964 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3968 if (ex
.X_add_number
!= 0)
3970 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3971 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3972 ex
.X_op
= O_constant
;
3973 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3974 reg
, reg
, BFD_RELOC_LO16
);
3978 else if (mips_big_got
)
3982 /* This is the large GOT case. If this is a reference to an
3983 external symbol, we want
3984 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3986 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3988 Otherwise, for a reference to a local symbol in old ABI, we want
3989 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3991 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3992 If there is a constant, it must be added in after.
3994 In the NewABI, for local symbols, with or without offsets, we want:
3995 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3996 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4000 ex
.X_add_number
= ep
->X_add_number
;
4001 ep
->X_add_number
= 0;
4002 relax_start (ep
->X_add_symbol
);
4003 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4004 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4005 reg
, reg
, mips_gp_register
);
4006 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4007 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4008 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4009 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4010 else if (ex
.X_add_number
)
4012 ex
.X_op
= O_constant
;
4013 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4017 ep
->X_add_number
= ex
.X_add_number
;
4019 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4020 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4021 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4022 BFD_RELOC_MIPS_GOT_OFST
);
4027 ex
.X_add_number
= ep
->X_add_number
;
4028 ep
->X_add_number
= 0;
4029 relax_start (ep
->X_add_symbol
);
4030 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4032 reg
, reg
, mips_gp_register
);
4033 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4034 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4036 if (reg_needs_delay (mips_gp_register
))
4038 /* We need a nop before loading from $gp. This special
4039 check is required because the lui which starts the main
4040 instruction stream does not refer to $gp, and so will not
4041 insert the nop which may be required. */
4042 macro_build (NULL
, "nop", "");
4044 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4045 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4047 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4051 if (ex
.X_add_number
!= 0)
4053 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4054 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4055 ex
.X_op
= O_constant
;
4056 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4064 if (mips_opts
.noat
&& *used_at
== 1)
4065 as_bad (_("Macro used $at after \".set noat\""));
4068 /* Move the contents of register SOURCE into register DEST. */
4071 move_register (int dest
, int source
)
4073 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4077 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4078 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4079 The two alternatives are:
4081 Global symbol Local sybmol
4082 ------------- ------------
4083 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4085 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4087 load_got_offset emits the first instruction and add_got_offset
4088 emits the second for a 16-bit offset or add_got_offset_hilo emits
4089 a sequence to add a 32-bit offset using a scratch register. */
4092 load_got_offset (int dest
, expressionS
*local
)
4097 global
.X_add_number
= 0;
4099 relax_start (local
->X_add_symbol
);
4100 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4101 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4103 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4104 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4109 add_got_offset (int dest
, expressionS
*local
)
4113 global
.X_op
= O_constant
;
4114 global
.X_op_symbol
= NULL
;
4115 global
.X_add_symbol
= NULL
;
4116 global
.X_add_number
= local
->X_add_number
;
4118 relax_start (local
->X_add_symbol
);
4119 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4120 dest
, dest
, BFD_RELOC_LO16
);
4122 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4127 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4130 int hold_mips_optimize
;
4132 global
.X_op
= O_constant
;
4133 global
.X_op_symbol
= NULL
;
4134 global
.X_add_symbol
= NULL
;
4135 global
.X_add_number
= local
->X_add_number
;
4137 relax_start (local
->X_add_symbol
);
4138 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4140 /* Set mips_optimize around the lui instruction to avoid
4141 inserting an unnecessary nop after the lw. */
4142 hold_mips_optimize
= mips_optimize
;
4144 macro_build_lui (&global
, tmp
);
4145 mips_optimize
= hold_mips_optimize
;
4146 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4149 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4154 * This routine implements the seemingly endless macro or synthesized
4155 * instructions and addressing modes in the mips assembly language. Many
4156 * of these macros are simple and are similar to each other. These could
4157 * probably be handled by some kind of table or grammar approach instead of
4158 * this verbose method. Others are not simple macros but are more like
4159 * optimizing code generation.
4160 * One interesting optimization is when several store macros appear
4161 * consecutively that would load AT with the upper half of the same address.
4162 * The ensuing load upper instructions are ommited. This implies some kind
4163 * of global optimization. We currently only optimize within a single macro.
4164 * For many of the load and store macros if the address is specified as a
4165 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4166 * first load register 'at' with zero and use it as the base register. The
4167 * mips assembler simply uses register $zero. Just one tiny optimization
4171 macro (struct mips_cl_insn
*ip
)
4173 register int treg
, sreg
, dreg
, breg
;
4189 bfd_reloc_code_real_type r
;
4190 int hold_mips_optimize
;
4192 assert (! mips_opts
.mips16
);
4194 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4195 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4196 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4197 mask
= ip
->insn_mo
->mask
;
4199 expr1
.X_op
= O_constant
;
4200 expr1
.X_op_symbol
= NULL
;
4201 expr1
.X_add_symbol
= NULL
;
4202 expr1
.X_add_number
= 1;
4216 expr1
.X_add_number
= 8;
4217 macro_build (&expr1
, "bgez", "s,p", sreg
);
4219 macro_build (NULL
, "nop", "", 0);
4221 move_register (dreg
, sreg
);
4222 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4245 if (imm_expr
.X_op
== O_constant
4246 && imm_expr
.X_add_number
>= -0x8000
4247 && imm_expr
.X_add_number
< 0x8000)
4249 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4253 load_register (AT
, &imm_expr
, dbl
);
4254 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4273 if (imm_expr
.X_op
== O_constant
4274 && imm_expr
.X_add_number
>= 0
4275 && imm_expr
.X_add_number
< 0x10000)
4277 if (mask
!= M_NOR_I
)
4278 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4281 macro_build (&imm_expr
, "ori", "t,r,i",
4282 treg
, sreg
, BFD_RELOC_LO16
);
4283 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4289 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4290 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4307 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4309 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4313 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4314 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4322 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4327 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4331 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4332 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4338 /* check for > max integer */
4339 maxnum
= 0x7fffffff;
4340 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4347 if (imm_expr
.X_op
== O_constant
4348 && imm_expr
.X_add_number
>= maxnum
4349 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4352 /* result is always false */
4354 macro_build (NULL
, "nop", "", 0);
4356 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4359 if (imm_expr
.X_op
!= O_constant
)
4360 as_bad (_("Unsupported large constant"));
4361 ++imm_expr
.X_add_number
;
4365 if (mask
== M_BGEL_I
)
4367 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4369 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4372 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4374 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4377 maxnum
= 0x7fffffff;
4378 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4385 maxnum
= - maxnum
- 1;
4386 if (imm_expr
.X_op
== O_constant
4387 && imm_expr
.X_add_number
<= maxnum
4388 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4391 /* result is always true */
4392 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4393 macro_build (&offset_expr
, "b", "p");
4398 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4408 macro_build (&offset_expr
, likely
? "beql" : "beq",
4413 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4414 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4422 && imm_expr
.X_op
== O_constant
4423 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4425 if (imm_expr
.X_op
!= O_constant
)
4426 as_bad (_("Unsupported large constant"));
4427 ++imm_expr
.X_add_number
;
4431 if (mask
== M_BGEUL_I
)
4433 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4435 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4437 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4443 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4451 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4456 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4460 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4461 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4469 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4476 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4477 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4485 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4490 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4494 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4495 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4501 maxnum
= 0x7fffffff;
4502 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4509 if (imm_expr
.X_op
== O_constant
4510 && imm_expr
.X_add_number
>= maxnum
4511 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4513 if (imm_expr
.X_op
!= O_constant
)
4514 as_bad (_("Unsupported large constant"));
4515 ++imm_expr
.X_add_number
;
4519 if (mask
== M_BLTL_I
)
4521 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4523 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4526 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4528 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4533 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4541 macro_build (&offset_expr
, likely
? "beql" : "beq",
4548 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4549 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4557 && imm_expr
.X_op
== O_constant
4558 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4560 if (imm_expr
.X_op
!= O_constant
)
4561 as_bad (_("Unsupported large constant"));
4562 ++imm_expr
.X_add_number
;
4566 if (mask
== M_BLTUL_I
)
4568 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4570 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4572 macro_build (&offset_expr
, likely
? "beql" : "beq",
4578 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4586 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4591 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4595 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4596 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4606 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4611 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4612 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4620 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4622 as_bad (_("Unsupported large constant"));
4627 pos
= (unsigned long) imm_expr
.X_add_number
;
4628 size
= (unsigned long) imm2_expr
.X_add_number
;
4633 as_bad (_("Improper position (%lu)"), pos
);
4636 if (size
== 0 || size
> 64
4637 || (pos
+ size
- 1) > 63)
4639 as_bad (_("Improper extract size (%lu, position %lu)"),
4644 if (size
<= 32 && pos
< 32)
4649 else if (size
<= 32)
4659 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4668 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4670 as_bad (_("Unsupported large constant"));
4675 pos
= (unsigned long) imm_expr
.X_add_number
;
4676 size
= (unsigned long) imm2_expr
.X_add_number
;
4681 as_bad (_("Improper position (%lu)"), pos
);
4684 if (size
== 0 || size
> 64
4685 || (pos
+ size
- 1) > 63)
4687 as_bad (_("Improper insert size (%lu, position %lu)"),
4692 if (pos
< 32 && (pos
+ size
- 1) < 32)
4707 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4724 as_warn (_("Divide by zero."));
4726 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4728 macro_build (NULL
, "break", "c", 7);
4735 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4736 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4740 expr1
.X_add_number
= 8;
4741 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4742 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4743 macro_build (NULL
, "break", "c", 7);
4745 expr1
.X_add_number
= -1;
4747 load_register (AT
, &expr1
, dbl
);
4748 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4749 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4752 expr1
.X_add_number
= 1;
4753 load_register (AT
, &expr1
, dbl
);
4754 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4758 expr1
.X_add_number
= 0x80000000;
4759 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4763 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4764 /* We want to close the noreorder block as soon as possible, so
4765 that later insns are available for delay slot filling. */
4770 expr1
.X_add_number
= 8;
4771 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4772 macro_build (NULL
, "nop", "", 0);
4774 /* We want to close the noreorder block as soon as possible, so
4775 that later insns are available for delay slot filling. */
4778 macro_build (NULL
, "break", "c", 6);
4780 macro_build (NULL
, s
, "d", dreg
);
4819 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4821 as_warn (_("Divide by zero."));
4823 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4825 macro_build (NULL
, "break", "c", 7);
4828 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4830 if (strcmp (s2
, "mflo") == 0)
4831 move_register (dreg
, sreg
);
4833 move_register (dreg
, 0);
4836 if (imm_expr
.X_op
== O_constant
4837 && imm_expr
.X_add_number
== -1
4838 && s
[strlen (s
) - 1] != 'u')
4840 if (strcmp (s2
, "mflo") == 0)
4842 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4845 move_register (dreg
, 0);
4850 load_register (AT
, &imm_expr
, dbl
);
4851 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4852 macro_build (NULL
, s2
, "d", dreg
);
4874 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4875 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4876 /* We want to close the noreorder block as soon as possible, so
4877 that later insns are available for delay slot filling. */
4882 expr1
.X_add_number
= 8;
4883 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4884 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4886 /* We want to close the noreorder block as soon as possible, so
4887 that later insns are available for delay slot filling. */
4889 macro_build (NULL
, "break", "c", 7);
4891 macro_build (NULL
, s2
, "d", dreg
);
4903 /* Load the address of a symbol into a register. If breg is not
4904 zero, we then add a base register to it. */
4906 if (dbl
&& HAVE_32BIT_GPRS
)
4907 as_warn (_("dla used to load 32-bit register"));
4909 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4910 as_warn (_("la used to load 64-bit address"));
4912 if (offset_expr
.X_op
== O_constant
4913 && offset_expr
.X_add_number
>= -0x8000
4914 && offset_expr
.X_add_number
< 0x8000)
4916 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
4917 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4921 if (!mips_opts
.noat
&& (treg
== breg
))
4931 if (offset_expr
.X_op
!= O_symbol
4932 && offset_expr
.X_op
!= O_constant
)
4934 as_bad (_("expression too complex"));
4935 offset_expr
.X_op
= O_constant
;
4938 if (offset_expr
.X_op
== O_constant
)
4939 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
4940 else if (mips_pic
== NO_PIC
)
4942 /* If this is a reference to a GP relative symbol, we want
4943 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4945 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4946 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4947 If we have a constant, we need two instructions anyhow,
4948 so we may as well always use the latter form.
4950 With 64bit address space and a usable $at we want
4951 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4952 lui $at,<sym> (BFD_RELOC_HI16_S)
4953 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4954 daddiu $at,<sym> (BFD_RELOC_LO16)
4956 daddu $tempreg,$tempreg,$at
4958 If $at is already in use, we use a path which is suboptimal
4959 on superscalar processors.
4960 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4961 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4963 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4965 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4967 For GP relative symbols in 64bit address space we can use
4968 the same sequence as in 32bit address space. */
4969 if (HAVE_64BIT_SYMBOLS
)
4971 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4972 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4974 relax_start (offset_expr
.X_add_symbol
);
4975 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4976 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4980 if (used_at
== 0 && !mips_opts
.noat
)
4982 macro_build (&offset_expr
, "lui", "t,u",
4983 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4984 macro_build (&offset_expr
, "lui", "t,u",
4985 AT
, BFD_RELOC_HI16_S
);
4986 macro_build (&offset_expr
, "daddiu", "t,r,j",
4987 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4988 macro_build (&offset_expr
, "daddiu", "t,r,j",
4989 AT
, AT
, BFD_RELOC_LO16
);
4990 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4991 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4996 macro_build (&offset_expr
, "lui", "t,u",
4997 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4998 macro_build (&offset_expr
, "daddiu", "t,r,j",
4999 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5000 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5001 macro_build (&offset_expr
, "daddiu", "t,r,j",
5002 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5003 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5004 macro_build (&offset_expr
, "daddiu", "t,r,j",
5005 tempreg
, tempreg
, BFD_RELOC_LO16
);
5008 if (mips_relax
.sequence
)
5013 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5014 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5016 relax_start (offset_expr
.X_add_symbol
);
5017 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5018 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5021 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5022 as_bad (_("offset too large"));
5023 macro_build_lui (&offset_expr
, tempreg
);
5024 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5025 tempreg
, tempreg
, BFD_RELOC_LO16
);
5026 if (mips_relax
.sequence
)
5030 else if (!mips_big_got
&& !HAVE_NEWABI
)
5032 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5034 /* If this is a reference to an external symbol, and there
5035 is no constant, we want
5036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5037 or for lca or if tempreg is PIC_CALL_REG
5038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5039 For a local symbol, we want
5040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5042 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5044 If we have a small constant, and this is a reference to
5045 an external symbol, we want
5046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5048 addiu $tempreg,$tempreg,<constant>
5049 For a local symbol, we want the same instruction
5050 sequence, but we output a BFD_RELOC_LO16 reloc on the
5053 If we have a large constant, and this is a reference to
5054 an external symbol, we want
5055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5056 lui $at,<hiconstant>
5057 addiu $at,$at,<loconstant>
5058 addu $tempreg,$tempreg,$at
5059 For a local symbol, we want the same instruction
5060 sequence, but we output a BFD_RELOC_LO16 reloc on the
5064 if (offset_expr
.X_add_number
== 0)
5066 if (mips_pic
== SVR4_PIC
5068 && (call
|| tempreg
== PIC_CALL_REG
))
5069 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5071 relax_start (offset_expr
.X_add_symbol
);
5072 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5073 lw_reloc_type
, mips_gp_register
);
5076 /* We're going to put in an addu instruction using
5077 tempreg, so we may as well insert the nop right
5082 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5083 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5085 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5086 tempreg
, tempreg
, BFD_RELOC_LO16
);
5088 /* FIXME: If breg == 0, and the next instruction uses
5089 $tempreg, then if this variant case is used an extra
5090 nop will be generated. */
5092 else if (offset_expr
.X_add_number
>= -0x8000
5093 && offset_expr
.X_add_number
< 0x8000)
5095 load_got_offset (tempreg
, &offset_expr
);
5097 add_got_offset (tempreg
, &offset_expr
);
5101 expr1
.X_add_number
= offset_expr
.X_add_number
;
5102 offset_expr
.X_add_number
=
5103 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5104 load_got_offset (tempreg
, &offset_expr
);
5105 offset_expr
.X_add_number
= expr1
.X_add_number
;
5106 /* If we are going to add in a base register, and the
5107 target register and the base register are the same,
5108 then we are using AT as a temporary register. Since
5109 we want to load the constant into AT, we add our
5110 current AT (from the global offset table) and the
5111 register into the register now, and pretend we were
5112 not using a base register. */
5116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5121 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5125 else if (!mips_big_got
&& HAVE_NEWABI
)
5127 int add_breg_early
= 0;
5129 /* If this is a reference to an external, and there is no
5130 constant, or local symbol (*), with or without a
5132 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5133 or for lca or if tempreg is PIC_CALL_REG
5134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5136 If we have a small constant, and this is a reference to
5137 an external symbol, we want
5138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5139 addiu $tempreg,$tempreg,<constant>
5141 If we have a large constant, and this is a reference to
5142 an external symbol, we want
5143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5144 lui $at,<hiconstant>
5145 addiu $at,$at,<loconstant>
5146 addu $tempreg,$tempreg,$at
5148 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5149 local symbols, even though it introduces an additional
5152 if (offset_expr
.X_add_number
)
5154 expr1
.X_add_number
= offset_expr
.X_add_number
;
5155 offset_expr
.X_add_number
= 0;
5157 relax_start (offset_expr
.X_add_symbol
);
5158 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5159 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5161 if (expr1
.X_add_number
>= -0x8000
5162 && expr1
.X_add_number
< 0x8000)
5164 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5165 tempreg
, tempreg
, BFD_RELOC_LO16
);
5167 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5171 /* If we are going to add in a base register, and the
5172 target register and the base register are the same,
5173 then we are using AT as a temporary register. Since
5174 we want to load the constant into AT, we add our
5175 current AT (from the global offset table) and the
5176 register into the register now, and pretend we were
5177 not using a base register. */
5182 assert (tempreg
== AT
);
5183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5189 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5190 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5196 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5199 offset_expr
.X_add_number
= expr1
.X_add_number
;
5201 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5202 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5205 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5206 treg
, tempreg
, breg
);
5212 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5214 relax_start (offset_expr
.X_add_symbol
);
5215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5216 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5218 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5219 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5224 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5225 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5228 else if (mips_big_got
&& !HAVE_NEWABI
)
5231 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5232 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5233 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5235 /* This is the large GOT case. If this is a reference to an
5236 external symbol, and there is no constant, we want
5237 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5238 addu $tempreg,$tempreg,$gp
5239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5240 or for lca or if tempreg is PIC_CALL_REG
5241 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5242 addu $tempreg,$tempreg,$gp
5243 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5244 For a local symbol, we want
5245 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5247 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5249 If we have a small constant, and this is a reference to
5250 an external symbol, we want
5251 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5252 addu $tempreg,$tempreg,$gp
5253 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5255 addiu $tempreg,$tempreg,<constant>
5256 For a local symbol, we want
5257 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5259 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5261 If we have a large constant, and this is a reference to
5262 an external symbol, we want
5263 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5264 addu $tempreg,$tempreg,$gp
5265 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5266 lui $at,<hiconstant>
5267 addiu $at,$at,<loconstant>
5268 addu $tempreg,$tempreg,$at
5269 For a local symbol, we want
5270 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5271 lui $at,<hiconstant>
5272 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5273 addu $tempreg,$tempreg,$at
5276 expr1
.X_add_number
= offset_expr
.X_add_number
;
5277 offset_expr
.X_add_number
= 0;
5278 relax_start (offset_expr
.X_add_symbol
);
5279 gpdelay
= reg_needs_delay (mips_gp_register
);
5280 if (expr1
.X_add_number
== 0 && breg
== 0
5281 && (call
|| tempreg
== PIC_CALL_REG
))
5283 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5284 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5286 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5287 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5288 tempreg
, tempreg
, mips_gp_register
);
5289 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5290 tempreg
, lw_reloc_type
, tempreg
);
5291 if (expr1
.X_add_number
== 0)
5295 /* We're going to put in an addu instruction using
5296 tempreg, so we may as well insert the nop right
5301 else if (expr1
.X_add_number
>= -0x8000
5302 && expr1
.X_add_number
< 0x8000)
5305 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5306 tempreg
, tempreg
, BFD_RELOC_LO16
);
5312 /* If we are going to add in a base register, and the
5313 target register and the base register are the same,
5314 then we are using AT as a temporary register. Since
5315 we want to load the constant into AT, we add our
5316 current AT (from the global offset table) and the
5317 register into the register now, and pretend we were
5318 not using a base register. */
5323 assert (tempreg
== AT
);
5325 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5330 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5331 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5335 offset_expr
.X_add_number
=
5336 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5341 /* This is needed because this instruction uses $gp, but
5342 the first instruction on the main stream does not. */
5343 macro_build (NULL
, "nop", "");
5346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5347 local_reloc_type
, mips_gp_register
);
5348 if (expr1
.X_add_number
>= -0x8000
5349 && expr1
.X_add_number
< 0x8000)
5352 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5353 tempreg
, tempreg
, BFD_RELOC_LO16
);
5354 /* FIXME: If add_number is 0, and there was no base
5355 register, the external symbol case ended with a load,
5356 so if the symbol turns out to not be external, and
5357 the next instruction uses tempreg, an unnecessary nop
5358 will be inserted. */
5364 /* We must add in the base register now, as in the
5365 external symbol case. */
5366 assert (tempreg
== AT
);
5368 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5371 /* We set breg to 0 because we have arranged to add
5372 it in in both cases. */
5376 macro_build_lui (&expr1
, AT
);
5377 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5378 AT
, AT
, BFD_RELOC_LO16
);
5379 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5380 tempreg
, tempreg
, AT
);
5385 else if (mips_big_got
&& HAVE_NEWABI
)
5387 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5388 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5389 int add_breg_early
= 0;
5391 /* This is the large GOT case. If this is a reference to an
5392 external symbol, and there is no constant, we want
5393 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5394 add $tempreg,$tempreg,$gp
5395 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5396 or for lca or if tempreg is PIC_CALL_REG
5397 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5398 add $tempreg,$tempreg,$gp
5399 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5401 If we have a small constant, and this is a reference to
5402 an external symbol, we want
5403 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5404 add $tempreg,$tempreg,$gp
5405 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5406 addi $tempreg,$tempreg,<constant>
5408 If we have a large constant, and this is a reference to
5409 an external symbol, we want
5410 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5411 addu $tempreg,$tempreg,$gp
5412 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5413 lui $at,<hiconstant>
5414 addi $at,$at,<loconstant>
5415 add $tempreg,$tempreg,$at
5417 If we have NewABI, and we know it's a local symbol, we want
5418 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5419 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5420 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5422 relax_start (offset_expr
.X_add_symbol
);
5424 expr1
.X_add_number
= offset_expr
.X_add_number
;
5425 offset_expr
.X_add_number
= 0;
5427 if (expr1
.X_add_number
== 0 && breg
== 0
5428 && (call
|| tempreg
== PIC_CALL_REG
))
5430 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5431 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5433 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5435 tempreg
, tempreg
, mips_gp_register
);
5436 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5437 tempreg
, lw_reloc_type
, tempreg
);
5439 if (expr1
.X_add_number
== 0)
5441 else if (expr1
.X_add_number
>= -0x8000
5442 && expr1
.X_add_number
< 0x8000)
5444 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5445 tempreg
, tempreg
, BFD_RELOC_LO16
);
5447 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5451 /* If we are going to add in a base register, and the
5452 target register and the base register are the same,
5453 then we are using AT as a temporary register. Since
5454 we want to load the constant into AT, we add our
5455 current AT (from the global offset table) and the
5456 register into the register now, and pretend we were
5457 not using a base register. */
5462 assert (tempreg
== AT
);
5463 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5469 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5470 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5475 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5478 offset_expr
.X_add_number
= expr1
.X_add_number
;
5479 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5480 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5481 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5482 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5486 treg
, tempreg
, breg
);
5496 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5500 /* The j instruction may not be used in PIC code, since it
5501 requires an absolute address. We convert it to a b
5503 if (mips_pic
== NO_PIC
)
5504 macro_build (&offset_expr
, "j", "a");
5506 macro_build (&offset_expr
, "b", "p");
5509 /* The jal instructions must be handled as macros because when
5510 generating PIC code they expand to multi-instruction
5511 sequences. Normally they are simple instructions. */
5516 if (mips_pic
== NO_PIC
)
5517 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5520 if (sreg
!= PIC_CALL_REG
)
5521 as_warn (_("MIPS PIC call to register other than $25"));
5523 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5524 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5526 if (mips_cprestore_offset
< 0)
5527 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5530 if (! mips_frame_reg_valid
)
5532 as_warn (_("No .frame pseudo-op used in PIC code"));
5533 /* Quiet this warning. */
5534 mips_frame_reg_valid
= 1;
5536 if (! mips_cprestore_valid
)
5538 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5539 /* Quiet this warning. */
5540 mips_cprestore_valid
= 1;
5542 expr1
.X_add_number
= mips_cprestore_offset
;
5543 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5546 HAVE_64BIT_ADDRESSES
);
5554 if (mips_pic
== NO_PIC
)
5555 macro_build (&offset_expr
, "jal", "a");
5556 else if (mips_pic
== SVR4_PIC
)
5558 /* If this is a reference to an external symbol, and we are
5559 using a small GOT, we want
5560 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5564 lw $gp,cprestore($sp)
5565 The cprestore value is set using the .cprestore
5566 pseudo-op. If we are using a big GOT, we want
5567 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5569 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5573 lw $gp,cprestore($sp)
5574 If the symbol is not external, we want
5575 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5577 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5580 lw $gp,cprestore($sp)
5582 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5583 sequences above, minus nops, unless the symbol is local,
5584 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5590 relax_start (offset_expr
.X_add_symbol
);
5591 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5592 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5595 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5596 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5602 relax_start (offset_expr
.X_add_symbol
);
5603 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5604 BFD_RELOC_MIPS_CALL_HI16
);
5605 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5606 PIC_CALL_REG
, mips_gp_register
);
5607 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5608 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5611 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5612 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5614 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5615 PIC_CALL_REG
, PIC_CALL_REG
,
5616 BFD_RELOC_MIPS_GOT_OFST
);
5620 macro_build_jalr (&offset_expr
);
5624 relax_start (offset_expr
.X_add_symbol
);
5627 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5628 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5637 gpdelay
= reg_needs_delay (mips_gp_register
);
5638 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5639 BFD_RELOC_MIPS_CALL_HI16
);
5640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5641 PIC_CALL_REG
, mips_gp_register
);
5642 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5643 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5648 macro_build (NULL
, "nop", "");
5650 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5651 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5654 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5655 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5657 macro_build_jalr (&offset_expr
);
5659 if (mips_cprestore_offset
< 0)
5660 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5663 if (! mips_frame_reg_valid
)
5665 as_warn (_("No .frame pseudo-op used in PIC code"));
5666 /* Quiet this warning. */
5667 mips_frame_reg_valid
= 1;
5669 if (! mips_cprestore_valid
)
5671 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5672 /* Quiet this warning. */
5673 mips_cprestore_valid
= 1;
5675 if (mips_opts
.noreorder
)
5676 macro_build (NULL
, "nop", "");
5677 expr1
.X_add_number
= mips_cprestore_offset
;
5678 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5681 HAVE_64BIT_ADDRESSES
);
5685 else if (mips_pic
== VXWORKS_PIC
)
5686 as_bad (_("Non-PIC jump used in PIC library"));
5709 /* Itbl support may require additional care here. */
5714 /* Itbl support may require additional care here. */
5719 /* Itbl support may require additional care here. */
5724 /* Itbl support may require additional care here. */
5736 if (mips_opts
.arch
== CPU_R4650
)
5738 as_bad (_("opcode not supported on this processor"));
5742 /* Itbl support may require additional care here. */
5747 /* Itbl support may require additional care here. */
5752 /* Itbl support may require additional care here. */
5772 if (breg
== treg
|| coproc
|| lr
)
5793 /* Itbl support may require additional care here. */
5798 /* Itbl support may require additional care here. */
5803 /* Itbl support may require additional care here. */
5808 /* Itbl support may require additional care here. */
5824 if (mips_opts
.arch
== CPU_R4650
)
5826 as_bad (_("opcode not supported on this processor"));
5831 /* Itbl support may require additional care here. */
5835 /* Itbl support may require additional care here. */
5840 /* Itbl support may require additional care here. */
5852 /* Itbl support may require additional care here. */
5853 if (mask
== M_LWC1_AB
5854 || mask
== M_SWC1_AB
5855 || mask
== M_LDC1_AB
5856 || mask
== M_SDC1_AB
5865 if (offset_expr
.X_op
!= O_constant
5866 && offset_expr
.X_op
!= O_symbol
)
5868 as_bad (_("expression too complex"));
5869 offset_expr
.X_op
= O_constant
;
5872 if (HAVE_32BIT_ADDRESSES
5873 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5877 sprintf_vma (value
, offset_expr
.X_add_number
);
5878 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
5881 /* A constant expression in PIC code can be handled just as it
5882 is in non PIC code. */
5883 if (offset_expr
.X_op
== O_constant
)
5885 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
5886 & ~(bfd_vma
) 0xffff);
5887 normalize_address_expr (&expr1
);
5888 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
5890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5891 tempreg
, tempreg
, breg
);
5892 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
5894 else if (mips_pic
== NO_PIC
)
5896 /* If this is a reference to a GP relative symbol, and there
5897 is no base register, we want
5898 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5899 Otherwise, if there is no base register, we want
5900 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5901 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5902 If we have a constant, we need two instructions anyhow,
5903 so we always use the latter form.
5905 If we have a base register, and this is a reference to a
5906 GP relative symbol, we want
5907 addu $tempreg,$breg,$gp
5908 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5910 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5911 addu $tempreg,$tempreg,$breg
5912 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5913 With a constant we always use the latter case.
5915 With 64bit address space and no base register and $at usable,
5917 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5918 lui $at,<sym> (BFD_RELOC_HI16_S)
5919 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5922 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5923 If we have a base register, we want
5924 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5925 lui $at,<sym> (BFD_RELOC_HI16_S)
5926 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5930 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5932 Without $at we can't generate the optimal path for superscalar
5933 processors here since this would require two temporary registers.
5934 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5935 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5937 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5939 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5940 If we have a base register, we want
5941 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5942 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5944 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5946 daddu $tempreg,$tempreg,$breg
5947 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5949 For GP relative symbols in 64bit address space we can use
5950 the same sequence as in 32bit address space. */
5951 if (HAVE_64BIT_SYMBOLS
)
5953 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5954 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5956 relax_start (offset_expr
.X_add_symbol
);
5959 macro_build (&offset_expr
, s
, fmt
, treg
,
5960 BFD_RELOC_GPREL16
, mips_gp_register
);
5964 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5965 tempreg
, breg
, mips_gp_register
);
5966 macro_build (&offset_expr
, s
, fmt
, treg
,
5967 BFD_RELOC_GPREL16
, tempreg
);
5972 if (used_at
== 0 && !mips_opts
.noat
)
5974 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5975 BFD_RELOC_MIPS_HIGHEST
);
5976 macro_build (&offset_expr
, "lui", "t,u", AT
,
5978 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5979 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5981 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5982 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5983 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5984 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5990 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5991 BFD_RELOC_MIPS_HIGHEST
);
5992 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5993 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5994 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5995 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5996 tempreg
, BFD_RELOC_HI16_S
);
5997 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5999 macro_build (NULL
, "daddu", "d,v,t",
6000 tempreg
, tempreg
, breg
);
6001 macro_build (&offset_expr
, s
, fmt
, treg
,
6002 BFD_RELOC_LO16
, tempreg
);
6005 if (mips_relax
.sequence
)
6012 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6013 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6015 relax_start (offset_expr
.X_add_symbol
);
6016 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6020 macro_build_lui (&offset_expr
, tempreg
);
6021 macro_build (&offset_expr
, s
, fmt
, treg
,
6022 BFD_RELOC_LO16
, tempreg
);
6023 if (mips_relax
.sequence
)
6028 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6029 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6031 relax_start (offset_expr
.X_add_symbol
);
6032 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6033 tempreg
, breg
, mips_gp_register
);
6034 macro_build (&offset_expr
, s
, fmt
, treg
,
6035 BFD_RELOC_GPREL16
, tempreg
);
6038 macro_build_lui (&offset_expr
, tempreg
);
6039 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6040 tempreg
, tempreg
, breg
);
6041 macro_build (&offset_expr
, s
, fmt
, treg
,
6042 BFD_RELOC_LO16
, tempreg
);
6043 if (mips_relax
.sequence
)
6047 else if (!mips_big_got
)
6049 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6051 /* If this is a reference to an external symbol, we want
6052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6054 <op> $treg,0($tempreg)
6056 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6058 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6059 <op> $treg,0($tempreg)
6062 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6063 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6065 If there is a base register, we add it to $tempreg before
6066 the <op>. If there is a constant, we stick it in the
6067 <op> instruction. We don't handle constants larger than
6068 16 bits, because we have no way to load the upper 16 bits
6069 (actually, we could handle them for the subset of cases
6070 in which we are not using $at). */
6071 assert (offset_expr
.X_op
== O_symbol
);
6074 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6075 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6077 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6078 tempreg
, tempreg
, breg
);
6079 macro_build (&offset_expr
, s
, fmt
, treg
,
6080 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6083 expr1
.X_add_number
= offset_expr
.X_add_number
;
6084 offset_expr
.X_add_number
= 0;
6085 if (expr1
.X_add_number
< -0x8000
6086 || expr1
.X_add_number
>= 0x8000)
6087 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6088 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6089 lw_reloc_type
, mips_gp_register
);
6091 relax_start (offset_expr
.X_add_symbol
);
6093 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6094 tempreg
, BFD_RELOC_LO16
);
6097 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6098 tempreg
, tempreg
, breg
);
6099 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6101 else if (mips_big_got
&& !HAVE_NEWABI
)
6105 /* If this is a reference to an external symbol, we want
6106 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6107 addu $tempreg,$tempreg,$gp
6108 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6109 <op> $treg,0($tempreg)
6111 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6113 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6114 <op> $treg,0($tempreg)
6115 If there is a base register, we add it to $tempreg before
6116 the <op>. If there is a constant, we stick it in the
6117 <op> instruction. We don't handle constants larger than
6118 16 bits, because we have no way to load the upper 16 bits
6119 (actually, we could handle them for the subset of cases
6120 in which we are not using $at). */
6121 assert (offset_expr
.X_op
== O_symbol
);
6122 expr1
.X_add_number
= offset_expr
.X_add_number
;
6123 offset_expr
.X_add_number
= 0;
6124 if (expr1
.X_add_number
< -0x8000
6125 || expr1
.X_add_number
>= 0x8000)
6126 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6127 gpdelay
= reg_needs_delay (mips_gp_register
);
6128 relax_start (offset_expr
.X_add_symbol
);
6129 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6130 BFD_RELOC_MIPS_GOT_HI16
);
6131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6133 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6134 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6137 macro_build (NULL
, "nop", "");
6138 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6139 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6141 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6142 tempreg
, BFD_RELOC_LO16
);
6146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6147 tempreg
, tempreg
, breg
);
6148 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6150 else if (mips_big_got
&& HAVE_NEWABI
)
6152 /* If this is a reference to an external symbol, we want
6153 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6154 add $tempreg,$tempreg,$gp
6155 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6156 <op> $treg,<ofst>($tempreg)
6157 Otherwise, for local symbols, we want:
6158 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6159 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6160 assert (offset_expr
.X_op
== O_symbol
);
6161 expr1
.X_add_number
= offset_expr
.X_add_number
;
6162 offset_expr
.X_add_number
= 0;
6163 if (expr1
.X_add_number
< -0x8000
6164 || expr1
.X_add_number
>= 0x8000)
6165 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6166 relax_start (offset_expr
.X_add_symbol
);
6167 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6168 BFD_RELOC_MIPS_GOT_HI16
);
6169 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6171 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6172 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6174 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6175 tempreg
, tempreg
, breg
);
6176 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6179 offset_expr
.X_add_number
= expr1
.X_add_number
;
6180 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6181 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6183 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6184 tempreg
, tempreg
, breg
);
6185 macro_build (&offset_expr
, s
, fmt
, treg
,
6186 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6196 load_register (treg
, &imm_expr
, 0);
6200 load_register (treg
, &imm_expr
, 1);
6204 if (imm_expr
.X_op
== O_constant
)
6207 load_register (AT
, &imm_expr
, 0);
6208 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6213 assert (offset_expr
.X_op
== O_symbol
6214 && strcmp (segment_name (S_GET_SEGMENT
6215 (offset_expr
.X_add_symbol
)),
6217 && offset_expr
.X_add_number
== 0);
6218 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6219 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6224 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6225 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6226 order 32 bits of the value and the low order 32 bits are either
6227 zero or in OFFSET_EXPR. */
6228 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6230 if (HAVE_64BIT_GPRS
)
6231 load_register (treg
, &imm_expr
, 1);
6236 if (target_big_endian
)
6248 load_register (hreg
, &imm_expr
, 0);
6251 if (offset_expr
.X_op
== O_absent
)
6252 move_register (lreg
, 0);
6255 assert (offset_expr
.X_op
== O_constant
);
6256 load_register (lreg
, &offset_expr
, 0);
6263 /* We know that sym is in the .rdata section. First we get the
6264 upper 16 bits of the address. */
6265 if (mips_pic
== NO_PIC
)
6267 macro_build_lui (&offset_expr
, AT
);
6272 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6273 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6277 /* Now we load the register(s). */
6278 if (HAVE_64BIT_GPRS
)
6281 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6286 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6289 /* FIXME: How in the world do we deal with the possible
6291 offset_expr
.X_add_number
+= 4;
6292 macro_build (&offset_expr
, "lw", "t,o(b)",
6293 treg
+ 1, BFD_RELOC_LO16
, AT
);
6299 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6300 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6301 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6302 the value and the low order 32 bits are either zero or in
6304 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6307 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6308 if (HAVE_64BIT_FPRS
)
6310 assert (HAVE_64BIT_GPRS
);
6311 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6315 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6316 if (offset_expr
.X_op
== O_absent
)
6317 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6320 assert (offset_expr
.X_op
== O_constant
);
6321 load_register (AT
, &offset_expr
, 0);
6322 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6328 assert (offset_expr
.X_op
== O_symbol
6329 && offset_expr
.X_add_number
== 0);
6330 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6331 if (strcmp (s
, ".lit8") == 0)
6333 if (mips_opts
.isa
!= ISA_MIPS1
)
6335 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6336 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6339 breg
= mips_gp_register
;
6340 r
= BFD_RELOC_MIPS_LITERAL
;
6345 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6347 if (mips_pic
!= NO_PIC
)
6348 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6349 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6352 /* FIXME: This won't work for a 64 bit address. */
6353 macro_build_lui (&offset_expr
, AT
);
6356 if (mips_opts
.isa
!= ISA_MIPS1
)
6358 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6359 treg
, BFD_RELOC_LO16
, AT
);
6368 if (mips_opts
.arch
== CPU_R4650
)
6370 as_bad (_("opcode not supported on this processor"));
6373 /* Even on a big endian machine $fn comes before $fn+1. We have
6374 to adjust when loading from memory. */
6377 assert (mips_opts
.isa
== ISA_MIPS1
);
6378 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6379 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6380 /* FIXME: A possible overflow which I don't know how to deal
6382 offset_expr
.X_add_number
+= 4;
6383 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6384 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6389 * The MIPS assembler seems to check for X_add_number not
6390 * being double aligned and generating:
6393 * addiu at,at,%lo(foo+1)
6396 * But, the resulting address is the same after relocation so why
6397 * generate the extra instruction?
6399 if (mips_opts
.arch
== CPU_R4650
)
6401 as_bad (_("opcode not supported on this processor"));
6404 /* Itbl support may require additional care here. */
6406 if (mips_opts
.isa
!= ISA_MIPS1
)
6417 if (mips_opts
.arch
== CPU_R4650
)
6419 as_bad (_("opcode not supported on this processor"));
6423 if (mips_opts
.isa
!= ISA_MIPS1
)
6431 /* Itbl support may require additional care here. */
6436 if (HAVE_64BIT_GPRS
)
6447 if (HAVE_64BIT_GPRS
)
6457 if (offset_expr
.X_op
!= O_symbol
6458 && offset_expr
.X_op
!= O_constant
)
6460 as_bad (_("expression too complex"));
6461 offset_expr
.X_op
= O_constant
;
6464 if (HAVE_32BIT_ADDRESSES
6465 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6469 sprintf_vma (value
, offset_expr
.X_add_number
);
6470 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6473 /* Even on a big endian machine $fn comes before $fn+1. We have
6474 to adjust when loading from memory. We set coproc if we must
6475 load $fn+1 first. */
6476 /* Itbl support may require additional care here. */
6477 if (! target_big_endian
)
6480 if (mips_pic
== NO_PIC
6481 || offset_expr
.X_op
== O_constant
)
6483 /* If this is a reference to a GP relative symbol, we want
6484 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6485 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6486 If we have a base register, we use this
6488 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6489 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6490 If this is not a GP relative symbol, we want
6491 lui $at,<sym> (BFD_RELOC_HI16_S)
6492 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6493 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6494 If there is a base register, we add it to $at after the
6495 lui instruction. If there is a constant, we always use
6497 if (offset_expr
.X_op
== O_symbol
6498 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6499 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6501 relax_start (offset_expr
.X_add_symbol
);
6504 tempreg
= mips_gp_register
;
6508 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6509 AT
, breg
, mips_gp_register
);
6514 /* Itbl support may require additional care here. */
6515 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6516 BFD_RELOC_GPREL16
, tempreg
);
6517 offset_expr
.X_add_number
+= 4;
6519 /* Set mips_optimize to 2 to avoid inserting an
6521 hold_mips_optimize
= mips_optimize
;
6523 /* Itbl support may require additional care here. */
6524 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6525 BFD_RELOC_GPREL16
, tempreg
);
6526 mips_optimize
= hold_mips_optimize
;
6530 /* We just generated two relocs. When tc_gen_reloc
6531 handles this case, it will skip the first reloc and
6532 handle the second. The second reloc already has an
6533 extra addend of 4, which we added above. We must
6534 subtract it out, and then subtract another 4 to make
6535 the first reloc come out right. The second reloc
6536 will come out right because we are going to add 4 to
6537 offset_expr when we build its instruction below.
6539 If we have a symbol, then we don't want to include
6540 the offset, because it will wind up being included
6541 when we generate the reloc. */
6543 if (offset_expr
.X_op
== O_constant
)
6544 offset_expr
.X_add_number
-= 8;
6547 offset_expr
.X_add_number
= -4;
6548 offset_expr
.X_op
= O_constant
;
6552 macro_build_lui (&offset_expr
, AT
);
6554 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6555 /* Itbl support may require additional care here. */
6556 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6557 BFD_RELOC_LO16
, AT
);
6558 /* FIXME: How do we handle overflow here? */
6559 offset_expr
.X_add_number
+= 4;
6560 /* Itbl support may require additional care here. */
6561 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6562 BFD_RELOC_LO16
, AT
);
6563 if (mips_relax
.sequence
)
6566 else if (!mips_big_got
)
6568 /* If this is a reference to an external symbol, we want
6569 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6574 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6576 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6577 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6578 If there is a base register we add it to $at before the
6579 lwc1 instructions. If there is a constant we include it
6580 in the lwc1 instructions. */
6582 expr1
.X_add_number
= offset_expr
.X_add_number
;
6583 if (expr1
.X_add_number
< -0x8000
6584 || expr1
.X_add_number
>= 0x8000 - 4)
6585 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6586 load_got_offset (AT
, &offset_expr
);
6589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6591 /* Set mips_optimize to 2 to avoid inserting an undesired
6593 hold_mips_optimize
= mips_optimize
;
6596 /* Itbl support may require additional care here. */
6597 relax_start (offset_expr
.X_add_symbol
);
6598 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6599 BFD_RELOC_LO16
, AT
);
6600 expr1
.X_add_number
+= 4;
6601 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6602 BFD_RELOC_LO16
, AT
);
6604 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6605 BFD_RELOC_LO16
, AT
);
6606 offset_expr
.X_add_number
+= 4;
6607 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6608 BFD_RELOC_LO16
, AT
);
6611 mips_optimize
= hold_mips_optimize
;
6613 else if (mips_big_got
)
6617 /* If this is a reference to an external symbol, we want
6618 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6620 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6625 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6627 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6628 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6629 If there is a base register we add it to $at before the
6630 lwc1 instructions. If there is a constant we include it
6631 in the lwc1 instructions. */
6633 expr1
.X_add_number
= offset_expr
.X_add_number
;
6634 offset_expr
.X_add_number
= 0;
6635 if (expr1
.X_add_number
< -0x8000
6636 || expr1
.X_add_number
>= 0x8000 - 4)
6637 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6638 gpdelay
= reg_needs_delay (mips_gp_register
);
6639 relax_start (offset_expr
.X_add_symbol
);
6640 macro_build (&offset_expr
, "lui", "t,u",
6641 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6642 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6643 AT
, AT
, mips_gp_register
);
6644 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6645 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6648 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6649 /* Itbl support may require additional care here. */
6650 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6651 BFD_RELOC_LO16
, AT
);
6652 expr1
.X_add_number
+= 4;
6654 /* Set mips_optimize to 2 to avoid inserting an undesired
6656 hold_mips_optimize
= mips_optimize
;
6658 /* Itbl support may require additional care here. */
6659 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6660 BFD_RELOC_LO16
, AT
);
6661 mips_optimize
= hold_mips_optimize
;
6662 expr1
.X_add_number
-= 4;
6665 offset_expr
.X_add_number
= expr1
.X_add_number
;
6667 macro_build (NULL
, "nop", "");
6668 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6669 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6672 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6673 /* Itbl support may require additional care here. */
6674 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6675 BFD_RELOC_LO16
, AT
);
6676 offset_expr
.X_add_number
+= 4;
6678 /* Set mips_optimize to 2 to avoid inserting an undesired
6680 hold_mips_optimize
= mips_optimize
;
6682 /* Itbl support may require additional care here. */
6683 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6684 BFD_RELOC_LO16
, AT
);
6685 mips_optimize
= hold_mips_optimize
;
6699 assert (HAVE_32BIT_ADDRESSES
);
6700 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6701 offset_expr
.X_add_number
+= 4;
6702 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6705 /* New code added to support COPZ instructions.
6706 This code builds table entries out of the macros in mip_opcodes.
6707 R4000 uses interlocks to handle coproc delays.
6708 Other chips (like the R3000) require nops to be inserted for delays.
6710 FIXME: Currently, we require that the user handle delays.
6711 In order to fill delay slots for non-interlocked chips,
6712 we must have a way to specify delays based on the coprocessor.
6713 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6714 What are the side-effects of the cop instruction?
6715 What cache support might we have and what are its effects?
6716 Both coprocessor & memory require delays. how long???
6717 What registers are read/set/modified?
6719 If an itbl is provided to interpret cop instructions,
6720 this knowledge can be encoded in the itbl spec. */
6734 /* For now we just do C (same as Cz). The parameter will be
6735 stored in insn_opcode by mips_ip. */
6736 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6740 move_register (dreg
, sreg
);
6743 #ifdef LOSING_COMPILER
6745 /* Try and see if this is a new itbl instruction.
6746 This code builds table entries out of the macros in mip_opcodes.
6747 FIXME: For now we just assemble the expression and pass it's
6748 value along as a 32-bit immediate.
6749 We may want to have the assembler assemble this value,
6750 so that we gain the assembler's knowledge of delay slots,
6752 Would it be more efficient to use mask (id) here? */
6753 if (itbl_have_entries
6754 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6756 s
= ip
->insn_mo
->name
;
6758 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6759 macro_build (&immed_expr
, s
, "C");
6765 if (mips_opts
.noat
&& used_at
)
6766 as_bad (_("Macro used $at after \".set noat\""));
6770 macro2 (struct mips_cl_insn
*ip
)
6772 register int treg
, sreg
, dreg
, breg
;
6787 bfd_reloc_code_real_type r
;
6789 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6790 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6791 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6792 mask
= ip
->insn_mo
->mask
;
6794 expr1
.X_op
= O_constant
;
6795 expr1
.X_op_symbol
= NULL
;
6796 expr1
.X_add_symbol
= NULL
;
6797 expr1
.X_add_number
= 1;
6801 #endif /* LOSING_COMPILER */
6806 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6807 macro_build (NULL
, "mflo", "d", dreg
);
6813 /* The MIPS assembler some times generates shifts and adds. I'm
6814 not trying to be that fancy. GCC should do this for us
6817 load_register (AT
, &imm_expr
, dbl
);
6818 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6819 macro_build (NULL
, "mflo", "d", dreg
);
6835 load_register (AT
, &imm_expr
, dbl
);
6836 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6837 macro_build (NULL
, "mflo", "d", dreg
);
6838 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6839 macro_build (NULL
, "mfhi", "d", AT
);
6841 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6844 expr1
.X_add_number
= 8;
6845 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6846 macro_build (NULL
, "nop", "", 0);
6847 macro_build (NULL
, "break", "c", 6);
6850 macro_build (NULL
, "mflo", "d", dreg
);
6866 load_register (AT
, &imm_expr
, dbl
);
6867 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6868 sreg
, imm
? AT
: treg
);
6869 macro_build (NULL
, "mfhi", "d", AT
);
6870 macro_build (NULL
, "mflo", "d", dreg
);
6872 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6875 expr1
.X_add_number
= 8;
6876 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6877 macro_build (NULL
, "nop", "", 0);
6878 macro_build (NULL
, "break", "c", 6);
6884 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6895 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6896 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6900 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6901 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6902 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6903 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6907 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6918 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6919 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6923 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6924 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6925 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6926 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6934 if (imm_expr
.X_op
!= O_constant
)
6935 as_bad (_("Improper rotate count"));
6936 rot
= imm_expr
.X_add_number
& 0x3f;
6937 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6939 rot
= (64 - rot
) & 0x3f;
6941 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6943 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6948 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6951 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6952 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6955 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6956 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6957 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6965 if (imm_expr
.X_op
!= O_constant
)
6966 as_bad (_("Improper rotate count"));
6967 rot
= imm_expr
.X_add_number
& 0x1f;
6968 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6970 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6975 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6979 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6980 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6981 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6986 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6988 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6992 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6993 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6994 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6995 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6999 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7001 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7005 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7006 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7007 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7008 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7016 if (imm_expr
.X_op
!= O_constant
)
7017 as_bad (_("Improper rotate count"));
7018 rot
= imm_expr
.X_add_number
& 0x3f;
7019 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7022 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7024 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7029 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7032 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7033 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7036 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7037 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7038 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7046 if (imm_expr
.X_op
!= O_constant
)
7047 as_bad (_("Improper rotate count"));
7048 rot
= imm_expr
.X_add_number
& 0x1f;
7049 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7051 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7056 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7060 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7061 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7062 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7067 if (mips_opts
.arch
== CPU_R4650
)
7069 as_bad (_("opcode not supported on this processor"));
7072 assert (mips_opts
.isa
== ISA_MIPS1
);
7073 /* Even on a big endian machine $fn comes before $fn+1. We have
7074 to adjust when storing to memory. */
7075 macro_build (&offset_expr
, "swc1", "T,o(b)",
7076 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7077 offset_expr
.X_add_number
+= 4;
7078 macro_build (&offset_expr
, "swc1", "T,o(b)",
7079 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7084 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7086 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7089 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7090 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7095 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7097 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7102 as_warn (_("Instruction %s: result is always false"),
7104 move_register (dreg
, 0);
7107 if (imm_expr
.X_op
== O_constant
7108 && imm_expr
.X_add_number
>= 0
7109 && imm_expr
.X_add_number
< 0x10000)
7111 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7113 else if (imm_expr
.X_op
== O_constant
7114 && imm_expr
.X_add_number
> -0x8000
7115 && imm_expr
.X_add_number
< 0)
7117 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7118 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7119 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7123 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7124 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7127 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7130 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7136 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7137 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7140 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7142 if (imm_expr
.X_op
== O_constant
7143 && imm_expr
.X_add_number
>= -0x8000
7144 && imm_expr
.X_add_number
< 0x8000)
7146 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7147 dreg
, sreg
, BFD_RELOC_LO16
);
7151 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7152 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7156 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7159 case M_SGT
: /* sreg > treg <==> treg < sreg */
7165 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7168 case M_SGT_I
: /* sreg > I <==> I < sreg */
7175 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7176 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7179 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7185 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7186 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7189 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7196 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7197 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7198 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7202 if (imm_expr
.X_op
== O_constant
7203 && imm_expr
.X_add_number
>= -0x8000
7204 && imm_expr
.X_add_number
< 0x8000)
7206 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7210 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7211 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7215 if (imm_expr
.X_op
== O_constant
7216 && imm_expr
.X_add_number
>= -0x8000
7217 && imm_expr
.X_add_number
< 0x8000)
7219 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7224 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7225 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7230 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7232 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7235 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7236 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7241 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7243 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7248 as_warn (_("Instruction %s: result is always true"),
7250 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7251 dreg
, 0, BFD_RELOC_LO16
);
7254 if (imm_expr
.X_op
== O_constant
7255 && imm_expr
.X_add_number
>= 0
7256 && imm_expr
.X_add_number
< 0x10000)
7258 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7260 else if (imm_expr
.X_op
== O_constant
7261 && imm_expr
.X_add_number
> -0x8000
7262 && imm_expr
.X_add_number
< 0)
7264 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7265 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7266 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7270 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7271 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7274 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7280 if (imm_expr
.X_op
== O_constant
7281 && imm_expr
.X_add_number
> -0x8000
7282 && imm_expr
.X_add_number
<= 0x8000)
7284 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7285 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7286 dreg
, sreg
, BFD_RELOC_LO16
);
7290 load_register (AT
, &imm_expr
, dbl
);
7291 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7297 if (imm_expr
.X_op
== O_constant
7298 && imm_expr
.X_add_number
> -0x8000
7299 && imm_expr
.X_add_number
<= 0x8000)
7301 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7302 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7303 dreg
, sreg
, BFD_RELOC_LO16
);
7307 load_register (AT
, &imm_expr
, dbl
);
7308 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7330 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7331 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7336 assert (mips_opts
.isa
== ISA_MIPS1
);
7338 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7339 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7342 * Is the double cfc1 instruction a bug in the mips assembler;
7343 * or is there a reason for it?
7346 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7347 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7348 macro_build (NULL
, "nop", "");
7349 expr1
.X_add_number
= 3;
7350 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7351 expr1
.X_add_number
= 2;
7352 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7353 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7354 macro_build (NULL
, "nop", "");
7355 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7357 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7358 macro_build (NULL
, "nop", "");
7369 if (offset_expr
.X_add_number
>= 0x7fff)
7370 as_bad (_("operand overflow"));
7371 if (! target_big_endian
)
7372 ++offset_expr
.X_add_number
;
7373 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7374 if (! target_big_endian
)
7375 --offset_expr
.X_add_number
;
7377 ++offset_expr
.X_add_number
;
7378 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7379 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7380 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7393 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7394 as_bad (_("operand overflow"));
7402 if (! target_big_endian
)
7403 offset_expr
.X_add_number
+= off
;
7404 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7405 if (! target_big_endian
)
7406 offset_expr
.X_add_number
-= off
;
7408 offset_expr
.X_add_number
+= off
;
7409 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7411 /* If necessary, move the result in tempreg the final destination. */
7412 if (treg
== tempreg
)
7414 /* Protect second load's delay slot. */
7416 move_register (treg
, tempreg
);
7430 load_address (AT
, &offset_expr
, &used_at
);
7432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7433 if (! target_big_endian
)
7434 expr1
.X_add_number
= off
;
7436 expr1
.X_add_number
= 0;
7437 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7438 if (! target_big_endian
)
7439 expr1
.X_add_number
= 0;
7441 expr1
.X_add_number
= off
;
7442 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7448 load_address (AT
, &offset_expr
, &used_at
);
7450 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7451 if (target_big_endian
)
7452 expr1
.X_add_number
= 0;
7453 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7454 treg
, BFD_RELOC_LO16
, AT
);
7455 if (target_big_endian
)
7456 expr1
.X_add_number
= 1;
7458 expr1
.X_add_number
= 0;
7459 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7460 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7461 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7466 if (offset_expr
.X_add_number
>= 0x7fff)
7467 as_bad (_("operand overflow"));
7468 if (target_big_endian
)
7469 ++offset_expr
.X_add_number
;
7470 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7471 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7472 if (target_big_endian
)
7473 --offset_expr
.X_add_number
;
7475 ++offset_expr
.X_add_number
;
7476 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7489 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7490 as_bad (_("operand overflow"));
7491 if (! target_big_endian
)
7492 offset_expr
.X_add_number
+= off
;
7493 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7494 if (! target_big_endian
)
7495 offset_expr
.X_add_number
-= off
;
7497 offset_expr
.X_add_number
+= off
;
7498 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7512 load_address (AT
, &offset_expr
, &used_at
);
7514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7515 if (! target_big_endian
)
7516 expr1
.X_add_number
= off
;
7518 expr1
.X_add_number
= 0;
7519 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7520 if (! target_big_endian
)
7521 expr1
.X_add_number
= 0;
7523 expr1
.X_add_number
= off
;
7524 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7529 load_address (AT
, &offset_expr
, &used_at
);
7531 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7532 if (! target_big_endian
)
7533 expr1
.X_add_number
= 0;
7534 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7535 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7536 if (! target_big_endian
)
7537 expr1
.X_add_number
= 1;
7539 expr1
.X_add_number
= 0;
7540 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7541 if (! target_big_endian
)
7542 expr1
.X_add_number
= 0;
7544 expr1
.X_add_number
= 1;
7545 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7546 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7547 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7551 /* FIXME: Check if this is one of the itbl macros, since they
7552 are added dynamically. */
7553 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7556 if (mips_opts
.noat
&& used_at
)
7557 as_bad (_("Macro used $at after \".set noat\""));
7560 /* Implement macros in mips16 mode. */
7563 mips16_macro (struct mips_cl_insn
*ip
)
7566 int xreg
, yreg
, zreg
, tmp
;
7569 const char *s
, *s2
, *s3
;
7571 mask
= ip
->insn_mo
->mask
;
7573 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7574 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7575 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7577 expr1
.X_op
= O_constant
;
7578 expr1
.X_op_symbol
= NULL
;
7579 expr1
.X_add_symbol
= NULL
;
7580 expr1
.X_add_number
= 1;
7600 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7601 expr1
.X_add_number
= 2;
7602 macro_build (&expr1
, "bnez", "x,p", yreg
);
7603 macro_build (NULL
, "break", "6", 7);
7605 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7606 since that causes an overflow. We should do that as well,
7607 but I don't see how to do the comparisons without a temporary
7610 macro_build (NULL
, s
, "x", zreg
);
7630 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7631 expr1
.X_add_number
= 2;
7632 macro_build (&expr1
, "bnez", "x,p", yreg
);
7633 macro_build (NULL
, "break", "6", 7);
7635 macro_build (NULL
, s2
, "x", zreg
);
7641 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7642 macro_build (NULL
, "mflo", "x", zreg
);
7650 if (imm_expr
.X_op
!= O_constant
)
7651 as_bad (_("Unsupported large constant"));
7652 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7653 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7657 if (imm_expr
.X_op
!= O_constant
)
7658 as_bad (_("Unsupported large constant"));
7659 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7660 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7664 if (imm_expr
.X_op
!= O_constant
)
7665 as_bad (_("Unsupported large constant"));
7666 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7667 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7689 goto do_reverse_branch
;
7693 goto do_reverse_branch
;
7705 goto do_reverse_branch
;
7716 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7717 macro_build (&offset_expr
, s2
, "p");
7744 goto do_addone_branch_i
;
7749 goto do_addone_branch_i
;
7764 goto do_addone_branch_i
;
7771 if (imm_expr
.X_op
!= O_constant
)
7772 as_bad (_("Unsupported large constant"));
7773 ++imm_expr
.X_add_number
;
7776 macro_build (&imm_expr
, s
, s3
, xreg
);
7777 macro_build (&offset_expr
, s2
, "p");
7781 expr1
.X_add_number
= 0;
7782 macro_build (&expr1
, "slti", "x,8", yreg
);
7784 move_register (xreg
, yreg
);
7785 expr1
.X_add_number
= 2;
7786 macro_build (&expr1
, "bteqz", "p");
7787 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7791 /* For consistency checking, verify that all bits are specified either
7792 by the match/mask part of the instruction definition, or by the
7795 validate_mips_insn (const struct mips_opcode
*opc
)
7797 const char *p
= opc
->args
;
7799 unsigned long used_bits
= opc
->mask
;
7801 if ((used_bits
& opc
->match
) != opc
->match
)
7803 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7804 opc
->name
, opc
->args
);
7807 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7817 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
7818 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
7819 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
7820 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
7821 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7822 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7823 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7824 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7825 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7826 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7827 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7828 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7829 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7831 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7832 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
7833 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7835 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7836 c
, opc
->name
, opc
->args
);
7840 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7841 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7843 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7844 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7845 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7846 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7848 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7849 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7851 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7852 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7854 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7855 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7856 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7857 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7858 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7859 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7860 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7861 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7862 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7863 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7864 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7865 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7866 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7867 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7868 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7869 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7870 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7872 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7873 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7874 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7875 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7877 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7878 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7879 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7880 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7881 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7882 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7883 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7884 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7885 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7888 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7889 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7890 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7891 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7892 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7895 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
7896 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
7897 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
7898 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7899 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
7900 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
7901 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
7902 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
7903 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
7904 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
7905 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
7906 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
7907 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
7908 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
7909 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
7910 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7912 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7913 c
, opc
->name
, opc
->args
);
7917 if (used_bits
!= 0xffffffff)
7919 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7920 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7926 /* UDI immediates. */
7934 static const struct mips_immed mips_immed
[] = {
7935 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
7936 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
7937 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
7938 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
7942 /* This routine assembles an instruction into its binary format. As a
7943 side effect, it sets one of the global variables imm_reloc or
7944 offset_reloc to the type of relocation to do if one of the operands
7945 is an address expression. */
7948 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7953 struct mips_opcode
*insn
;
7956 unsigned int lastregno
= 0;
7957 unsigned int lastpos
= 0;
7958 unsigned int limlo
, limhi
;
7961 offsetT min_range
, max_range
;
7965 /* If the instruction contains a '.', we first try to match an instruction
7966 including the '.'. Then we try again without the '.'. */
7968 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7971 /* If we stopped on whitespace, then replace the whitespace with null for
7972 the call to hash_find. Save the character we replaced just in case we
7973 have to re-parse the instruction. */
7980 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7982 /* If we didn't find the instruction in the opcode table, try again, but
7983 this time with just the instruction up to, but not including the
7987 /* Restore the character we overwrite above (if any). */
7991 /* Scan up to the first '.' or whitespace. */
7993 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7997 /* If we did not find a '.', then we can quit now. */
8000 insn_error
= "unrecognized opcode";
8004 /* Lookup the instruction in the hash table. */
8006 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8008 insn_error
= "unrecognized opcode";
8018 assert (strcmp (insn
->name
, str
) == 0);
8020 if (OPCODE_IS_MEMBER (insn
,
8022 | (file_ase_mips16
? INSN_MIPS16
: 0)
8023 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8024 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8025 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8026 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8032 if (insn
->pinfo
!= INSN_MACRO
)
8034 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8040 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8041 && strcmp (insn
->name
, insn
[1].name
) == 0)
8050 static char buf
[100];
8052 _("opcode not supported on this processor: %s (%s)"),
8053 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8054 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8063 create_insn (ip
, insn
);
8065 for (args
= insn
->args
;; ++args
)
8069 s
+= strspn (s
, " \t");
8073 case '\0': /* end of args */
8078 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8079 my_getExpression (&imm_expr
, s
);
8080 check_absolute_expr (ip
, &imm_expr
);
8081 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8083 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8084 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8085 imm_expr
.X_add_number
&= OP_MASK_SA3
;
8087 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA3
;
8088 imm_expr
.X_op
= O_absent
;
8092 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8093 my_getExpression (&imm_expr
, s
);
8094 check_absolute_expr (ip
, &imm_expr
);
8095 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8097 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8098 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8099 imm_expr
.X_add_number
&= OP_MASK_SA4
;
8101 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SA4
;
8102 imm_expr
.X_op
= O_absent
;
8106 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8107 my_getExpression (&imm_expr
, s
);
8108 check_absolute_expr (ip
, &imm_expr
);
8109 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8111 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8112 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8113 imm_expr
.X_add_number
&= OP_MASK_IMM8
;
8115 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_IMM8
;
8116 imm_expr
.X_op
= O_absent
;
8120 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8121 my_getExpression (&imm_expr
, s
);
8122 check_absolute_expr (ip
, &imm_expr
);
8123 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8125 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8126 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8127 imm_expr
.X_add_number
&= OP_MASK_RS
;
8129 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RS
;
8130 imm_expr
.X_op
= O_absent
;
8134 case '7': /* four dsp accumulators in bits 11,12 */
8135 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8136 s
[3] >= '0' && s
[3] <= '3')
8140 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC
;
8144 as_bad (_("Invalid dsp acc register"));
8147 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8148 my_getExpression (&imm_expr
, s
);
8149 check_absolute_expr (ip
, &imm_expr
);
8150 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8152 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8154 (unsigned long) imm_expr
.X_add_number
);
8155 imm_expr
.X_add_number
&= OP_MASK_WRDSP
;
8157 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_WRDSP
;
8158 imm_expr
.X_op
= O_absent
;
8162 case '9': /* four dsp accumulators in bits 21,22 */
8163 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8164 s
[3] >= '0' && s
[3] <= '3')
8168 ip
->insn_opcode
|= regno
<< OP_SH_DSPACC_S
;
8172 as_bad (_("Invalid dsp acc register"));
8175 case '0': /* dsp 6-bit signed immediate in bit 20 */
8176 my_getExpression (&imm_expr
, s
);
8177 check_absolute_expr (ip
, &imm_expr
);
8178 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8179 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8180 if (imm_expr
.X_add_number
< min_range
||
8181 imm_expr
.X_add_number
> max_range
)
8183 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8184 (long) min_range
, (long) max_range
,
8185 (long) imm_expr
.X_add_number
);
8187 imm_expr
.X_add_number
&= OP_MASK_DSPSFT
;
8188 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8190 imm_expr
.X_op
= O_absent
;
8194 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8195 my_getExpression (&imm_expr
, s
);
8196 check_absolute_expr (ip
, &imm_expr
);
8197 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8199 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8201 (unsigned long) imm_expr
.X_add_number
);
8202 imm_expr
.X_add_number
&= OP_MASK_RDDSP
;
8204 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_RDDSP
;
8205 imm_expr
.X_op
= O_absent
;
8209 case ':': /* dsp 7-bit signed immediate in bit 19 */
8210 my_getExpression (&imm_expr
, s
);
8211 check_absolute_expr (ip
, &imm_expr
);
8212 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8213 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8214 if (imm_expr
.X_add_number
< min_range
||
8215 imm_expr
.X_add_number
> max_range
)
8217 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8218 (long) min_range
, (long) max_range
,
8219 (long) imm_expr
.X_add_number
);
8221 imm_expr
.X_add_number
&= OP_MASK_DSPSFT_7
;
8222 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8224 imm_expr
.X_op
= O_absent
;
8228 case '@': /* dsp 10-bit signed immediate in bit 16 */
8229 my_getExpression (&imm_expr
, s
);
8230 check_absolute_expr (ip
, &imm_expr
);
8231 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8232 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8233 if (imm_expr
.X_add_number
< min_range
||
8234 imm_expr
.X_add_number
> max_range
)
8236 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8237 (long) min_range
, (long) max_range
,
8238 (long) imm_expr
.X_add_number
);
8240 imm_expr
.X_add_number
&= OP_MASK_IMM10
;
8241 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8243 imm_expr
.X_op
= O_absent
;
8247 case '!': /* mt 1-bit unsigned immediate in bit 5 */
8248 my_getExpression (&imm_expr
, s
);
8249 check_absolute_expr (ip
, &imm_expr
);
8250 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8252 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8253 OP_MASK_MT_U
, (unsigned long) imm_expr
.X_add_number
);
8254 imm_expr
.X_add_number
&= OP_MASK_MT_U
;
8256 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_U
;
8257 imm_expr
.X_op
= O_absent
;
8261 case '$': /* mt 1-bit unsigned immediate in bit 4 */
8262 my_getExpression (&imm_expr
, s
);
8263 check_absolute_expr (ip
, &imm_expr
);
8264 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8266 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8267 OP_MASK_MT_H
, (unsigned long) imm_expr
.X_add_number
);
8268 imm_expr
.X_add_number
&= OP_MASK_MT_H
;
8270 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_MT_H
;
8271 imm_expr
.X_op
= O_absent
;
8275 case '*': /* four dsp accumulators in bits 18,19 */
8276 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8277 s
[3] >= '0' && s
[3] <= '3')
8281 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_T
;
8285 as_bad (_("Invalid dsp/smartmips acc register"));
8288 case '&': /* four dsp accumulators in bits 13,14 */
8289 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8290 s
[3] >= '0' && s
[3] <= '3')
8294 ip
->insn_opcode
|= regno
<< OP_SH_MTACC_D
;
8298 as_bad (_("Invalid dsp/smartmips acc register"));
8309 INSERT_OPERAND (RS
, *ip
, lastregno
);
8313 INSERT_OPERAND (RT
, *ip
, lastregno
);
8317 INSERT_OPERAND (FT
, *ip
, lastregno
);
8321 INSERT_OPERAND (FS
, *ip
, lastregno
);
8327 /* Handle optional base register.
8328 Either the base register is omitted or
8329 we must have a left paren. */
8330 /* This is dependent on the next operand specifier
8331 is a base register specification. */
8332 assert (args
[1] == 'b' || args
[1] == '5'
8333 || args
[1] == '-' || args
[1] == '4');
8337 case ')': /* these must match exactly */
8344 case '+': /* Opcode extension character. */
8347 case '1': /* UDI immediates. */
8352 const struct mips_immed
*imm
= mips_immed
;
8354 while (imm
->type
&& imm
->type
!= *args
)
8358 my_getExpression (&imm_expr
, s
);
8359 check_absolute_expr (ip
, &imm_expr
);
8360 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8362 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8363 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8364 (unsigned long) imm_expr
.X_add_number
,
8365 (unsigned long) imm_expr
.X_add_number
);
8366 imm_expr
.X_add_number
&= imm
->mask
;
8368 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8370 imm_expr
.X_op
= O_absent
;
8375 case 'A': /* ins/ext position, becomes LSB. */
8384 my_getExpression (&imm_expr
, s
);
8385 check_absolute_expr (ip
, &imm_expr
);
8386 if ((unsigned long) imm_expr
.X_add_number
< limlo
8387 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8389 as_bad (_("Improper position (%lu)"),
8390 (unsigned long) imm_expr
.X_add_number
);
8391 imm_expr
.X_add_number
= limlo
;
8393 lastpos
= imm_expr
.X_add_number
;
8394 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8395 imm_expr
.X_op
= O_absent
;
8399 case 'B': /* ins size, becomes MSB. */
8408 my_getExpression (&imm_expr
, s
);
8409 check_absolute_expr (ip
, &imm_expr
);
8410 /* Check for negative input so that small negative numbers
8411 will not succeed incorrectly. The checks against
8412 (pos+size) transitively check "size" itself,
8413 assuming that "pos" is reasonable. */
8414 if ((long) imm_expr
.X_add_number
< 0
8415 || ((unsigned long) imm_expr
.X_add_number
8417 || ((unsigned long) imm_expr
.X_add_number
8420 as_bad (_("Improper insert size (%lu, position %lu)"),
8421 (unsigned long) imm_expr
.X_add_number
,
8422 (unsigned long) lastpos
);
8423 imm_expr
.X_add_number
= limlo
- lastpos
;
8425 INSERT_OPERAND (INSMSB
, *ip
,
8426 lastpos
+ imm_expr
.X_add_number
- 1);
8427 imm_expr
.X_op
= O_absent
;
8431 case 'C': /* ext size, becomes MSBD. */
8444 my_getExpression (&imm_expr
, s
);
8445 check_absolute_expr (ip
, &imm_expr
);
8446 /* Check for negative input so that small negative numbers
8447 will not succeed incorrectly. The checks against
8448 (pos+size) transitively check "size" itself,
8449 assuming that "pos" is reasonable. */
8450 if ((long) imm_expr
.X_add_number
< 0
8451 || ((unsigned long) imm_expr
.X_add_number
8453 || ((unsigned long) imm_expr
.X_add_number
8456 as_bad (_("Improper extract size (%lu, position %lu)"),
8457 (unsigned long) imm_expr
.X_add_number
,
8458 (unsigned long) lastpos
);
8459 imm_expr
.X_add_number
= limlo
- lastpos
;
8461 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8462 imm_expr
.X_op
= O_absent
;
8467 /* +D is for disassembly only; never match. */
8471 /* "+I" is like "I", except that imm2_expr is used. */
8472 my_getExpression (&imm2_expr
, s
);
8473 if (imm2_expr
.X_op
!= O_big
8474 && imm2_expr
.X_op
!= O_constant
)
8475 insn_error
= _("absolute expression required");
8476 if (HAVE_32BIT_GPRS
)
8477 normalize_constant_expr (&imm2_expr
);
8481 case 'T': /* Coprocessor register */
8482 /* +T is for disassembly only; never match. */
8485 case 't': /* Coprocessor register number */
8486 if (s
[0] == '$' && ISDIGIT (s
[1]))
8496 while (ISDIGIT (*s
));
8498 as_bad (_("Invalid register number (%d)"), regno
);
8501 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8506 as_bad (_("Invalid coprocessor 0 register number"));
8510 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8511 *args
, insn
->name
, insn
->args
);
8512 /* Further processing is fruitless. */
8517 case '<': /* must be at least one digit */
8519 * According to the manual, if the shift amount is greater
8520 * than 31 or less than 0, then the shift amount should be
8521 * mod 32. In reality the mips assembler issues an error.
8522 * We issue a warning and mask out all but the low 5 bits.
8524 my_getExpression (&imm_expr
, s
);
8525 check_absolute_expr (ip
, &imm_expr
);
8526 if ((unsigned long) imm_expr
.X_add_number
> 31)
8527 as_warn (_("Improper shift amount (%lu)"),
8528 (unsigned long) imm_expr
.X_add_number
);
8529 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8530 imm_expr
.X_op
= O_absent
;
8534 case '>': /* shift amount minus 32 */
8535 my_getExpression (&imm_expr
, s
);
8536 check_absolute_expr (ip
, &imm_expr
);
8537 if ((unsigned long) imm_expr
.X_add_number
< 32
8538 || (unsigned long) imm_expr
.X_add_number
> 63)
8540 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8541 imm_expr
.X_op
= O_absent
;
8545 case 'k': /* cache code */
8546 case 'h': /* prefx code */
8547 my_getExpression (&imm_expr
, s
);
8548 check_absolute_expr (ip
, &imm_expr
);
8549 if ((unsigned long) imm_expr
.X_add_number
> 31)
8550 as_warn (_("Invalid value for `%s' (%lu)"),
8552 (unsigned long) imm_expr
.X_add_number
);
8554 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8556 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8557 imm_expr
.X_op
= O_absent
;
8561 case 'c': /* break code */
8562 my_getExpression (&imm_expr
, s
);
8563 check_absolute_expr (ip
, &imm_expr
);
8564 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8565 as_warn (_("Illegal break code (%lu)"),
8566 (unsigned long) imm_expr
.X_add_number
);
8567 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8568 imm_expr
.X_op
= O_absent
;
8572 case 'q': /* lower break code */
8573 my_getExpression (&imm_expr
, s
);
8574 check_absolute_expr (ip
, &imm_expr
);
8575 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8576 as_warn (_("Illegal lower break code (%lu)"),
8577 (unsigned long) imm_expr
.X_add_number
);
8578 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8579 imm_expr
.X_op
= O_absent
;
8583 case 'B': /* 20-bit syscall/break code. */
8584 my_getExpression (&imm_expr
, s
);
8585 check_absolute_expr (ip
, &imm_expr
);
8586 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8587 as_warn (_("Illegal 20-bit code (%lu)"),
8588 (unsigned long) imm_expr
.X_add_number
);
8589 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8590 imm_expr
.X_op
= O_absent
;
8594 case 'C': /* Coprocessor code */
8595 my_getExpression (&imm_expr
, s
);
8596 check_absolute_expr (ip
, &imm_expr
);
8597 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8599 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8600 (unsigned long) imm_expr
.X_add_number
);
8601 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8603 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8604 imm_expr
.X_op
= O_absent
;
8608 case 'J': /* 19-bit wait code. */
8609 my_getExpression (&imm_expr
, s
);
8610 check_absolute_expr (ip
, &imm_expr
);
8611 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8612 as_warn (_("Illegal 19-bit code (%lu)"),
8613 (unsigned long) imm_expr
.X_add_number
);
8614 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8615 imm_expr
.X_op
= O_absent
;
8619 case 'P': /* Performance register */
8620 my_getExpression (&imm_expr
, s
);
8621 check_absolute_expr (ip
, &imm_expr
);
8622 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8623 as_warn (_("Invalid performance register (%lu)"),
8624 (unsigned long) imm_expr
.X_add_number
);
8625 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8626 imm_expr
.X_op
= O_absent
;
8630 case 'b': /* base register */
8631 case 'd': /* destination register */
8632 case 's': /* source register */
8633 case 't': /* target register */
8634 case 'r': /* both target and source */
8635 case 'v': /* both dest and source */
8636 case 'w': /* both dest and target */
8637 case 'E': /* coprocessor target register */
8638 case 'G': /* coprocessor destination register */
8639 case 'K': /* 'rdhwr' destination register */
8640 case 'x': /* ignore register name */
8641 case 'z': /* must be zero register */
8642 case 'U': /* destination register (clo/clz). */
8643 case 'g': /* coprocessor destination register */
8657 while (ISDIGIT (*s
));
8659 as_bad (_("Invalid register number (%d)"), regno
);
8661 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8665 if (s
[1] == 'r' && s
[2] == 'a')
8670 else if (s
[1] == 'f' && s
[2] == 'p')
8675 else if (s
[1] == 's' && s
[2] == 'p')
8680 else if (s
[1] == 'g' && s
[2] == 'p')
8685 else if (s
[1] == 'a' && s
[2] == 't')
8690 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8695 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8700 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8705 else if (itbl_have_entries
)
8710 p
= s
+ 1; /* advance past '$' */
8711 n
= itbl_get_field (&p
); /* n is name */
8713 /* See if this is a register defined in an
8715 if (itbl_get_reg_val (n
, &r
))
8717 /* Get_field advances to the start of
8718 the next field, so we need to back
8719 rack to the end of the last field. */
8723 s
= strchr (s
, '\0');
8737 as_warn (_("Used $at without \".set noat\""));
8743 if (c
== 'r' || c
== 'v' || c
== 'w')
8750 /* 'z' only matches $0. */
8751 if (c
== 'z' && regno
!= 0)
8754 /* Now that we have assembled one operand, we use the args string
8755 * to figure out where it goes in the instruction. */
8762 INSERT_OPERAND (RS
, *ip
, regno
);
8768 INSERT_OPERAND (RD
, *ip
, regno
);
8771 INSERT_OPERAND (RD
, *ip
, regno
);
8772 INSERT_OPERAND (RT
, *ip
, regno
);
8777 INSERT_OPERAND (RT
, *ip
, regno
);
8780 /* This case exists because on the r3000 trunc
8781 expands into a macro which requires a gp
8782 register. On the r6000 or r4000 it is
8783 assembled into a single instruction which
8784 ignores the register. Thus the insn version
8785 is MIPS_ISA2 and uses 'x', and the macro
8786 version is MIPS_ISA1 and uses 't'. */
8789 /* This case is for the div instruction, which
8790 acts differently if the destination argument
8791 is $0. This only matches $0, and is checked
8792 outside the switch. */
8795 /* Itbl operand; not yet implemented. FIXME ?? */
8797 /* What about all other operands like 'i', which
8798 can be specified in the opcode table? */
8808 INSERT_OPERAND (RS
, *ip
, lastregno
);
8811 INSERT_OPERAND (RT
, *ip
, lastregno
);
8816 case 'O': /* MDMX alignment immediate constant. */
8817 my_getExpression (&imm_expr
, s
);
8818 check_absolute_expr (ip
, &imm_expr
);
8819 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8820 as_warn ("Improper align amount (%ld), using low bits",
8821 (long) imm_expr
.X_add_number
);
8822 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
8823 imm_expr
.X_op
= O_absent
;
8827 case 'Q': /* MDMX vector, element sel, or const. */
8830 /* MDMX Immediate. */
8831 my_getExpression (&imm_expr
, s
);
8832 check_absolute_expr (ip
, &imm_expr
);
8833 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8834 as_warn (_("Invalid MDMX Immediate (%ld)"),
8835 (long) imm_expr
.X_add_number
);
8836 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
8837 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8838 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8840 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8841 imm_expr
.X_op
= O_absent
;
8845 /* Not MDMX Immediate. Fall through. */
8846 case 'X': /* MDMX destination register. */
8847 case 'Y': /* MDMX source register. */
8848 case 'Z': /* MDMX target register. */
8850 case 'D': /* floating point destination register */
8851 case 'S': /* floating point source register */
8852 case 'T': /* floating point target register */
8853 case 'R': /* floating point source register */
8857 /* Accept $fN for FP and MDMX register numbers, and in
8858 addition accept $vN for MDMX register numbers. */
8859 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8860 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8871 while (ISDIGIT (*s
));
8874 as_bad (_("Invalid float register number (%d)"), regno
);
8876 if ((regno
& 1) != 0
8878 && ! (strcmp (str
, "mtc1") == 0
8879 || strcmp (str
, "mfc1") == 0
8880 || strcmp (str
, "lwc1") == 0
8881 || strcmp (str
, "swc1") == 0
8882 || strcmp (str
, "l.s") == 0
8883 || strcmp (str
, "s.s") == 0
8884 || strcmp (str
, "mftc1") == 0
8885 || strcmp (str
, "mfthc1") == 0
8886 || strcmp (str
, "cftc1") == 0
8887 || strcmp (str
, "mttc1") == 0
8888 || strcmp (str
, "mtthc1") == 0
8889 || strcmp (str
, "cttc1") == 0))
8890 as_warn (_("Float register should be even, was %d"),
8898 if (c
== 'V' || c
== 'W')
8909 INSERT_OPERAND (FD
, *ip
, regno
);
8914 INSERT_OPERAND (FS
, *ip
, regno
);
8917 /* This is like 'Z', but also needs to fix the MDMX
8918 vector/scalar select bits. Note that the
8919 scalar immediate case is handled above. */
8922 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8923 int max_el
= (is_qh
? 3 : 7);
8925 my_getExpression(&imm_expr
, s
);
8926 check_absolute_expr (ip
, &imm_expr
);
8928 if (imm_expr
.X_add_number
> max_el
)
8929 as_bad(_("Bad element selector %ld"),
8930 (long) imm_expr
.X_add_number
);
8931 imm_expr
.X_add_number
&= max_el
;
8932 ip
->insn_opcode
|= (imm_expr
.X_add_number
8935 imm_expr
.X_op
= O_absent
;
8937 as_warn(_("Expecting ']' found '%s'"), s
);
8943 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8944 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8947 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8954 INSERT_OPERAND (FT
, *ip
, regno
);
8957 INSERT_OPERAND (FR
, *ip
, regno
);
8967 INSERT_OPERAND (FS
, *ip
, lastregno
);
8970 INSERT_OPERAND (FT
, *ip
, lastregno
);
8976 my_getExpression (&imm_expr
, s
);
8977 if (imm_expr
.X_op
!= O_big
8978 && imm_expr
.X_op
!= O_constant
)
8979 insn_error
= _("absolute expression required");
8980 if (HAVE_32BIT_GPRS
)
8981 normalize_constant_expr (&imm_expr
);
8986 my_getExpression (&offset_expr
, s
);
8987 normalize_address_expr (&offset_expr
);
8988 *imm_reloc
= BFD_RELOC_32
;
9001 unsigned char temp
[8];
9003 unsigned int length
;
9008 /* These only appear as the last operand in an
9009 instruction, and every instruction that accepts
9010 them in any variant accepts them in all variants.
9011 This means we don't have to worry about backing out
9012 any changes if the instruction does not match.
9014 The difference between them is the size of the
9015 floating point constant and where it goes. For 'F'
9016 and 'L' the constant is 64 bits; for 'f' and 'l' it
9017 is 32 bits. Where the constant is placed is based
9018 on how the MIPS assembler does things:
9021 f -- immediate value
9024 The .lit4 and .lit8 sections are only used if
9025 permitted by the -G argument.
9027 The code below needs to know whether the target register
9028 is 32 or 64 bits wide. It relies on the fact 'f' and
9029 'F' are used with GPR-based instructions and 'l' and
9030 'L' are used with FPR-based instructions. */
9032 f64
= *args
== 'F' || *args
== 'L';
9033 using_gprs
= *args
== 'F' || *args
== 'f';
9035 save_in
= input_line_pointer
;
9036 input_line_pointer
= s
;
9037 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9039 s
= input_line_pointer
;
9040 input_line_pointer
= save_in
;
9041 if (err
!= NULL
&& *err
!= '\0')
9043 as_bad (_("Bad floating point constant: %s"), err
);
9044 memset (temp
, '\0', sizeof temp
);
9045 length
= f64
? 8 : 4;
9048 assert (length
== (unsigned) (f64
? 8 : 4));
9052 && (g_switch_value
< 4
9053 || (temp
[0] == 0 && temp
[1] == 0)
9054 || (temp
[2] == 0 && temp
[3] == 0))))
9056 imm_expr
.X_op
= O_constant
;
9057 if (! target_big_endian
)
9058 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9060 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9063 && ! mips_disable_float_construction
9064 /* Constants can only be constructed in GPRs and
9065 copied to FPRs if the GPRs are at least as wide
9066 as the FPRs. Force the constant into memory if
9067 we are using 64-bit FPRs but the GPRs are only
9070 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9071 && ((temp
[0] == 0 && temp
[1] == 0)
9072 || (temp
[2] == 0 && temp
[3] == 0))
9073 && ((temp
[4] == 0 && temp
[5] == 0)
9074 || (temp
[6] == 0 && temp
[7] == 0)))
9076 /* The value is simple enough to load with a couple of
9077 instructions. If using 32-bit registers, set
9078 imm_expr to the high order 32 bits and offset_expr to
9079 the low order 32 bits. Otherwise, set imm_expr to
9080 the entire 64 bit constant. */
9081 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9083 imm_expr
.X_op
= O_constant
;
9084 offset_expr
.X_op
= O_constant
;
9085 if (! target_big_endian
)
9087 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9088 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9092 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9093 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9095 if (offset_expr
.X_add_number
== 0)
9096 offset_expr
.X_op
= O_absent
;
9098 else if (sizeof (imm_expr
.X_add_number
) > 4)
9100 imm_expr
.X_op
= O_constant
;
9101 if (! target_big_endian
)
9102 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9104 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9108 imm_expr
.X_op
= O_big
;
9109 imm_expr
.X_add_number
= 4;
9110 if (! target_big_endian
)
9112 generic_bignum
[0] = bfd_getl16 (temp
);
9113 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9114 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9115 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9119 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9120 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9121 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9122 generic_bignum
[3] = bfd_getb16 (temp
);
9128 const char *newname
;
9131 /* Switch to the right section. */
9133 subseg
= now_subseg
;
9136 default: /* unused default case avoids warnings. */
9138 newname
= RDATA_SECTION_NAME
;
9139 if (g_switch_value
>= 8)
9143 newname
= RDATA_SECTION_NAME
;
9146 assert (g_switch_value
>= 4);
9150 new_seg
= subseg_new (newname
, (subsegT
) 0);
9151 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9152 bfd_set_section_flags (stdoutput
, new_seg
,
9157 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9158 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9159 && strcmp (TARGET_OS
, "elf") != 0)
9160 record_alignment (new_seg
, 4);
9162 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9164 as_bad (_("Can't use floating point insn in this section"));
9166 /* Set the argument to the current address in the
9168 offset_expr
.X_op
= O_symbol
;
9169 offset_expr
.X_add_symbol
=
9170 symbol_new ("L0\001", now_seg
,
9171 (valueT
) frag_now_fix (), frag_now
);
9172 offset_expr
.X_add_number
= 0;
9174 /* Put the floating point number into the section. */
9175 p
= frag_more ((int) length
);
9176 memcpy (p
, temp
, length
);
9178 /* Switch back to the original section. */
9179 subseg_set (seg
, subseg
);
9184 case 'i': /* 16 bit unsigned immediate */
9185 case 'j': /* 16 bit signed immediate */
9186 *imm_reloc
= BFD_RELOC_LO16
;
9187 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9190 offsetT minval
, maxval
;
9192 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9193 && strcmp (insn
->name
, insn
[1].name
) == 0);
9195 /* If the expression was written as an unsigned number,
9196 only treat it as signed if there are no more
9200 && sizeof (imm_expr
.X_add_number
) <= 4
9201 && imm_expr
.X_op
== O_constant
9202 && imm_expr
.X_add_number
< 0
9203 && imm_expr
.X_unsigned
9207 /* For compatibility with older assemblers, we accept
9208 0x8000-0xffff as signed 16-bit numbers when only
9209 signed numbers are allowed. */
9211 minval
= 0, maxval
= 0xffff;
9213 minval
= -0x8000, maxval
= 0x7fff;
9215 minval
= -0x8000, maxval
= 0xffff;
9217 if (imm_expr
.X_op
!= O_constant
9218 || imm_expr
.X_add_number
< minval
9219 || imm_expr
.X_add_number
> maxval
)
9223 if (imm_expr
.X_op
== O_constant
9224 || imm_expr
.X_op
== O_big
)
9225 as_bad (_("expression out of range"));
9231 case 'o': /* 16 bit offset */
9232 /* Check whether there is only a single bracketed expression
9233 left. If so, it must be the base register and the
9234 constant must be zero. */
9235 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9237 offset_expr
.X_op
= O_constant
;
9238 offset_expr
.X_add_number
= 0;
9242 /* If this value won't fit into a 16 bit offset, then go
9243 find a macro that will generate the 32 bit offset
9245 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9246 && (offset_expr
.X_op
!= O_constant
9247 || offset_expr
.X_add_number
>= 0x8000
9248 || offset_expr
.X_add_number
< -0x8000))
9254 case 'p': /* pc relative offset */
9255 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9256 my_getExpression (&offset_expr
, s
);
9260 case 'u': /* upper 16 bits */
9261 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9262 && imm_expr
.X_op
== O_constant
9263 && (imm_expr
.X_add_number
< 0
9264 || imm_expr
.X_add_number
>= 0x10000))
9265 as_bad (_("lui expression not in range 0..65535"));
9269 case 'a': /* 26 bit address */
9270 my_getExpression (&offset_expr
, s
);
9272 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9275 case 'N': /* 3 bit branch condition code */
9276 case 'M': /* 3 bit compare condition code */
9277 if (strncmp (s
, "$fcc", 4) != 0)
9287 while (ISDIGIT (*s
));
9289 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9290 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9291 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9292 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9293 && (regno
& 1) != 0)
9294 as_warn(_("Condition code register should be even for %s, was %d"),
9296 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9297 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9298 && (regno
& 3) != 0)
9299 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9302 INSERT_OPERAND (BCC
, *ip
, regno
);
9304 INSERT_OPERAND (CCC
, *ip
, regno
);
9308 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9319 while (ISDIGIT (*s
));
9322 c
= 8; /* Invalid sel value. */
9325 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9326 ip
->insn_opcode
|= c
;
9330 /* Must be at least one digit. */
9331 my_getExpression (&imm_expr
, s
);
9332 check_absolute_expr (ip
, &imm_expr
);
9334 if ((unsigned long) imm_expr
.X_add_number
9335 > (unsigned long) OP_MASK_VECBYTE
)
9337 as_bad (_("bad byte vector index (%ld)"),
9338 (long) imm_expr
.X_add_number
);
9339 imm_expr
.X_add_number
= 0;
9342 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9343 imm_expr
.X_op
= O_absent
;
9348 my_getExpression (&imm_expr
, s
);
9349 check_absolute_expr (ip
, &imm_expr
);
9351 if ((unsigned long) imm_expr
.X_add_number
9352 > (unsigned long) OP_MASK_VECALIGN
)
9354 as_bad (_("bad byte vector index (%ld)"),
9355 (long) imm_expr
.X_add_number
);
9356 imm_expr
.X_add_number
= 0;
9359 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9360 imm_expr
.X_op
= O_absent
;
9365 as_bad (_("bad char = '%c'\n"), *args
);
9370 /* Args don't match. */
9371 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9372 !strcmp (insn
->name
, insn
[1].name
))
9376 insn_error
= _("illegal operands");
9381 insn_error
= _("illegal operands");
9386 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9388 /* This routine assembles an instruction into its binary format when
9389 assembling for the mips16. As a side effect, it sets one of the
9390 global variables imm_reloc or offset_reloc to the type of
9391 relocation to do if one of the operands is an address expression.
9392 It also sets mips16_small and mips16_ext if the user explicitly
9393 requested a small or extended instruction. */
9396 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9400 struct mips_opcode
*insn
;
9403 unsigned int lastregno
= 0;
9409 mips16_small
= FALSE
;
9412 for (s
= str
; ISLOWER (*s
); ++s
)
9424 if (s
[1] == 't' && s
[2] == ' ')
9427 mips16_small
= TRUE
;
9431 else if (s
[1] == 'e' && s
[2] == ' ')
9440 insn_error
= _("unknown opcode");
9444 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9445 mips16_small
= TRUE
;
9447 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9449 insn_error
= _("unrecognized opcode");
9456 assert (strcmp (insn
->name
, str
) == 0);
9458 create_insn (ip
, insn
);
9459 imm_expr
.X_op
= O_absent
;
9460 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9461 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9462 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9463 imm2_expr
.X_op
= O_absent
;
9464 offset_expr
.X_op
= O_absent
;
9465 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9466 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9467 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9468 for (args
= insn
->args
; 1; ++args
)
9475 /* In this switch statement we call break if we did not find
9476 a match, continue if we did find a match, or return if we
9485 /* Stuff the immediate value in now, if we can. */
9486 if (imm_expr
.X_op
== O_constant
9487 && *imm_reloc
> BFD_RELOC_UNUSED
9488 && insn
->pinfo
!= INSN_MACRO
)
9492 switch (*offset_reloc
)
9494 case BFD_RELOC_MIPS16_HI16_S
:
9495 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9498 case BFD_RELOC_MIPS16_HI16
:
9499 tmp
= imm_expr
.X_add_number
>> 16;
9502 case BFD_RELOC_MIPS16_LO16
:
9503 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9507 case BFD_RELOC_UNUSED
:
9508 tmp
= imm_expr
.X_add_number
;
9514 *offset_reloc
= BFD_RELOC_UNUSED
;
9516 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9517 tmp
, TRUE
, mips16_small
,
9518 mips16_ext
, &ip
->insn_opcode
,
9519 &ip
->use_extend
, &ip
->extend
);
9520 imm_expr
.X_op
= O_absent
;
9521 *imm_reloc
= BFD_RELOC_UNUSED
;
9535 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9538 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9554 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9556 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9583 while (ISDIGIT (*s
));
9586 as_bad (_("invalid register number (%d)"), regno
);
9592 if (s
[1] == 'r' && s
[2] == 'a')
9597 else if (s
[1] == 'f' && s
[2] == 'p')
9602 else if (s
[1] == 's' && s
[2] == 'p')
9607 else if (s
[1] == 'g' && s
[2] == 'p')
9612 else if (s
[1] == 'a' && s
[2] == 't')
9617 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9622 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9627 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9640 if (c
== 'v' || c
== 'w')
9642 regno
= mips16_to_32_reg_map
[lastregno
];
9656 regno
= mips32_to_16_reg_map
[regno
];
9661 regno
= ILLEGAL_REG
;
9666 regno
= ILLEGAL_REG
;
9671 regno
= ILLEGAL_REG
;
9676 if (regno
== AT
&& ! mips_opts
.noat
)
9677 as_warn (_("used $at without \".set noat\""));
9684 if (regno
== ILLEGAL_REG
)
9691 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9695 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9698 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9701 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9707 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9710 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9711 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9721 if (strncmp (s
, "$pc", 3) == 0)
9738 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9741 if (imm_expr
.X_op
!= O_constant
)
9744 ip
->use_extend
= TRUE
;
9749 /* We need to relax this instruction. */
9750 *offset_reloc
= *imm_reloc
;
9751 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9756 *imm_reloc
= BFD_RELOC_UNUSED
;
9764 my_getExpression (&imm_expr
, s
);
9765 if (imm_expr
.X_op
== O_register
)
9767 /* What we thought was an expression turned out to
9770 if (s
[0] == '(' && args
[1] == '(')
9772 /* It looks like the expression was omitted
9773 before a register indirection, which means
9774 that the expression is implicitly zero. We
9775 still set up imm_expr, so that we handle
9776 explicit extensions correctly. */
9777 imm_expr
.X_op
= O_constant
;
9778 imm_expr
.X_add_number
= 0;
9779 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9786 /* We need to relax this instruction. */
9787 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9796 /* We use offset_reloc rather than imm_reloc for the PC
9797 relative operands. This lets macros with both
9798 immediate and address operands work correctly. */
9799 my_getExpression (&offset_expr
, s
);
9801 if (offset_expr
.X_op
== O_register
)
9804 /* We need to relax this instruction. */
9805 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9809 case '6': /* break code */
9810 my_getExpression (&imm_expr
, s
);
9811 check_absolute_expr (ip
, &imm_expr
);
9812 if ((unsigned long) imm_expr
.X_add_number
> 63)
9813 as_warn (_("Invalid value for `%s' (%lu)"),
9815 (unsigned long) imm_expr
.X_add_number
);
9816 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
9817 imm_expr
.X_op
= O_absent
;
9821 case 'a': /* 26 bit address */
9822 my_getExpression (&offset_expr
, s
);
9824 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9825 ip
->insn_opcode
<<= 16;
9828 case 'l': /* register list for entry macro */
9829 case 'L': /* register list for exit macro */
9839 int freg
, reg1
, reg2
;
9841 while (*s
== ' ' || *s
== ',')
9845 as_bad (_("can't parse register list"));
9857 while (ISDIGIT (*s
))
9879 as_bad (_("invalid register list"));
9884 while (ISDIGIT (*s
))
9891 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9896 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9901 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9902 mask
|= (reg2
- 3) << 3;
9903 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9904 mask
|= (reg2
- 15) << 1;
9905 else if (reg1
== RA
&& reg2
== RA
)
9909 as_bad (_("invalid register list"));
9913 /* The mask is filled in in the opcode table for the
9914 benefit of the disassembler. We remove it before
9915 applying the actual mask. */
9916 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9917 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9921 case 'm': /* Register list for save insn. */
9922 case 'M': /* Register list for restore insn. */
9925 int framesz
= 0, seen_framesz
= 0;
9926 int args
= 0, statics
= 0, sregs
= 0;
9930 unsigned int reg1
, reg2
;
9932 SKIP_SPACE_TABS (s
);
9935 SKIP_SPACE_TABS (s
);
9937 my_getExpression (&imm_expr
, s
);
9938 if (imm_expr
.X_op
== O_constant
)
9940 /* Handle the frame size. */
9943 as_bad (_("more than one frame size in list"));
9947 framesz
= imm_expr
.X_add_number
;
9948 imm_expr
.X_op
= O_absent
;
9955 as_bad (_("can't parse register list"));
9961 while (ISDIGIT (*s
))
9967 SKIP_SPACE_TABS (s
);
9975 as_bad (_("can't parse register list"));
9980 while (ISDIGIT (*s
))
9988 while (reg1
<= reg2
)
9990 if (reg1
>= 4 && reg1
<= 7)
9992 if (c
== 'm' && !seen_framesz
)
9994 args
|= 1 << (reg1
- 4);
9996 /* statics $a0-$a3 */
9997 statics
|= 1 << (reg1
- 4);
9999 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10002 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10004 else if (reg1
== 31)
10006 /* Add $ra to insn. */
10011 as_bad (_("unexpected register in list"));
10019 /* Encode args/statics combination. */
10020 if (args
& statics
)
10021 as_bad (_("arg/static registers overlap"));
10022 else if (args
== 0xf)
10023 /* All $a0-$a3 are args. */
10024 opcode
|= MIPS16_ALL_ARGS
<< 16;
10025 else if (statics
== 0xf)
10026 /* All $a0-$a3 are statics. */
10027 opcode
|= MIPS16_ALL_STATICS
<< 16;
10030 int narg
= 0, nstat
= 0;
10032 /* Count arg registers. */
10039 as_bad (_("invalid arg register list"));
10041 /* Count static registers. */
10042 while (statics
& 0x8)
10044 statics
= (statics
<< 1) & 0xf;
10048 as_bad (_("invalid static register list"));
10050 /* Encode args/statics. */
10051 opcode
|= ((narg
<< 2) | nstat
) << 16;
10054 /* Encode $s0/$s1. */
10055 if (sregs
& (1 << 0)) /* $s0 */
10057 if (sregs
& (1 << 1)) /* $s1 */
10063 /* Count regs $s2-$s8. */
10071 as_bad (_("invalid static register list"));
10072 /* Encode $s2-$s8. */
10073 opcode
|= nsreg
<< 24;
10076 /* Encode frame size. */
10078 as_bad (_("missing frame size"));
10079 else if ((framesz
& 7) != 0 || framesz
< 0
10080 || framesz
> 0xff * 8)
10081 as_bad (_("invalid frame size"));
10082 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10085 opcode
|= (((framesz
& 0xf0) << 16)
10086 | (framesz
& 0x0f));
10089 /* Finally build the instruction. */
10090 if ((opcode
>> 16) != 0 || framesz
== 0)
10092 ip
->use_extend
= TRUE
;
10093 ip
->extend
= opcode
>> 16;
10095 ip
->insn_opcode
|= opcode
& 0x7f;
10099 case 'e': /* extend code */
10100 my_getExpression (&imm_expr
, s
);
10101 check_absolute_expr (ip
, &imm_expr
);
10102 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10104 as_warn (_("Invalid value for `%s' (%lu)"),
10106 (unsigned long) imm_expr
.X_add_number
);
10107 imm_expr
.X_add_number
&= 0x7ff;
10109 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10110 imm_expr
.X_op
= O_absent
;
10120 /* Args don't match. */
10121 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10122 strcmp (insn
->name
, insn
[1].name
) == 0)
10129 insn_error
= _("illegal operands");
10135 /* This structure holds information we know about a mips16 immediate
10138 struct mips16_immed_operand
10140 /* The type code used in the argument string in the opcode table. */
10142 /* The number of bits in the short form of the opcode. */
10144 /* The number of bits in the extended form of the opcode. */
10146 /* The amount by which the short form is shifted when it is used;
10147 for example, the sw instruction has a shift count of 2. */
10149 /* The amount by which the short form is shifted when it is stored
10150 into the instruction code. */
10152 /* Non-zero if the short form is unsigned. */
10154 /* Non-zero if the extended form is unsigned. */
10156 /* Non-zero if the value is PC relative. */
10160 /* The mips16 immediate operand types. */
10162 static const struct mips16_immed_operand mips16_immed_operands
[] =
10164 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10165 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10166 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10167 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10168 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10169 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10170 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10171 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10172 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10173 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10174 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10175 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10176 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10177 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10178 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10179 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10180 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10181 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10182 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10183 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10184 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10187 #define MIPS16_NUM_IMMED \
10188 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10190 /* Handle a mips16 instruction with an immediate value. This or's the
10191 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10192 whether an extended value is needed; if one is needed, it sets
10193 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10194 If SMALL is true, an unextended opcode was explicitly requested.
10195 If EXT is true, an extended opcode was explicitly requested. If
10196 WARN is true, warn if EXT does not match reality. */
10199 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10200 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10201 unsigned long *insn
, bfd_boolean
*use_extend
,
10202 unsigned short *extend
)
10204 register const struct mips16_immed_operand
*op
;
10205 int mintiny
, maxtiny
;
10206 bfd_boolean needext
;
10208 op
= mips16_immed_operands
;
10209 while (op
->type
!= type
)
10212 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10217 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10220 maxtiny
= 1 << op
->nbits
;
10225 maxtiny
= (1 << op
->nbits
) - 1;
10230 mintiny
= - (1 << (op
->nbits
- 1));
10231 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10234 /* Branch offsets have an implicit 0 in the lowest bit. */
10235 if (type
== 'p' || type
== 'q')
10238 if ((val
& ((1 << op
->shift
) - 1)) != 0
10239 || val
< (mintiny
<< op
->shift
)
10240 || val
> (maxtiny
<< op
->shift
))
10245 if (warn
&& ext
&& ! needext
)
10246 as_warn_where (file
, line
,
10247 _("extended operand requested but not required"));
10248 if (small
&& needext
)
10249 as_bad_where (file
, line
, _("invalid unextended operand value"));
10251 if (small
|| (! ext
&& ! needext
))
10255 *use_extend
= FALSE
;
10256 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10257 insnval
<<= op
->op_shift
;
10262 long minext
, maxext
;
10268 maxext
= (1 << op
->extbits
) - 1;
10272 minext
= - (1 << (op
->extbits
- 1));
10273 maxext
= (1 << (op
->extbits
- 1)) - 1;
10275 if (val
< minext
|| val
> maxext
)
10276 as_bad_where (file
, line
,
10277 _("operand value out of range for instruction"));
10279 *use_extend
= TRUE
;
10280 if (op
->extbits
== 16)
10282 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10285 else if (op
->extbits
== 15)
10287 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10292 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10296 *extend
= (unsigned short) extval
;
10301 struct percent_op_match
10304 bfd_reloc_code_real_type reloc
;
10307 static const struct percent_op_match mips_percent_op
[] =
10309 {"%lo", BFD_RELOC_LO16
},
10311 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10312 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10313 {"%call16", BFD_RELOC_MIPS_CALL16
},
10314 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10315 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10316 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10317 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10318 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10319 {"%got", BFD_RELOC_MIPS_GOT16
},
10320 {"%gp_rel", BFD_RELOC_GPREL16
},
10321 {"%half", BFD_RELOC_16
},
10322 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10323 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10324 {"%neg", BFD_RELOC_MIPS_SUB
},
10325 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10326 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10327 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10328 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10329 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10330 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10331 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10333 {"%hi", BFD_RELOC_HI16_S
}
10336 static const struct percent_op_match mips16_percent_op
[] =
10338 {"%lo", BFD_RELOC_MIPS16_LO16
},
10339 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10340 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10344 /* Return true if *STR points to a relocation operator. When returning true,
10345 move *STR over the operator and store its relocation code in *RELOC.
10346 Leave both *STR and *RELOC alone when returning false. */
10349 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10351 const struct percent_op_match
*percent_op
;
10354 if (mips_opts
.mips16
)
10356 percent_op
= mips16_percent_op
;
10357 limit
= ARRAY_SIZE (mips16_percent_op
);
10361 percent_op
= mips_percent_op
;
10362 limit
= ARRAY_SIZE (mips_percent_op
);
10365 for (i
= 0; i
< limit
; i
++)
10366 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10368 int len
= strlen (percent_op
[i
].str
);
10370 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10373 *str
+= strlen (percent_op
[i
].str
);
10374 *reloc
= percent_op
[i
].reloc
;
10376 /* Check whether the output BFD supports this relocation.
10377 If not, issue an error and fall back on something safe. */
10378 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10380 as_bad ("relocation %s isn't supported by the current ABI",
10381 percent_op
[i
].str
);
10382 *reloc
= BFD_RELOC_UNUSED
;
10390 /* Parse string STR as a 16-bit relocatable operand. Store the
10391 expression in *EP and the relocations in the array starting
10392 at RELOC. Return the number of relocation operators used.
10394 On exit, EXPR_END points to the first character after the expression. */
10397 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10400 bfd_reloc_code_real_type reversed_reloc
[3];
10401 size_t reloc_index
, i
;
10402 int crux_depth
, str_depth
;
10405 /* Search for the start of the main expression, recoding relocations
10406 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10407 of the main expression and with CRUX_DEPTH containing the number
10408 of open brackets at that point. */
10415 crux_depth
= str_depth
;
10417 /* Skip over whitespace and brackets, keeping count of the number
10419 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10424 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10425 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10427 my_getExpression (ep
, crux
);
10430 /* Match every open bracket. */
10431 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10435 if (crux_depth
> 0)
10436 as_bad ("unclosed '('");
10440 if (reloc_index
!= 0)
10442 prev_reloc_op_frag
= frag_now
;
10443 for (i
= 0; i
< reloc_index
; i
++)
10444 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10447 return reloc_index
;
10451 my_getExpression (expressionS
*ep
, char *str
)
10456 save_in
= input_line_pointer
;
10457 input_line_pointer
= str
;
10459 expr_end
= input_line_pointer
;
10460 input_line_pointer
= save_in
;
10462 /* If we are in mips16 mode, and this is an expression based on `.',
10463 then we bump the value of the symbol by 1 since that is how other
10464 text symbols are handled. We don't bother to handle complex
10465 expressions, just `.' plus or minus a constant. */
10466 if (mips_opts
.mips16
10467 && ep
->X_op
== O_symbol
10468 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10469 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10470 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10471 && symbol_constant_p (ep
->X_add_symbol
)
10472 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10473 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10476 /* Turn a string in input_line_pointer into a floating point constant
10477 of type TYPE, and store the appropriate bytes in *LITP. The number
10478 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10479 returned, or NULL on OK. */
10482 md_atof (int type
, char *litP
, int *sizeP
)
10485 LITTLENUM_TYPE words
[4];
10501 return _("bad call to md_atof");
10504 t
= atof_ieee (input_line_pointer
, type
, words
);
10506 input_line_pointer
= t
;
10510 if (! target_big_endian
)
10512 for (i
= prec
- 1; i
>= 0; i
--)
10514 md_number_to_chars (litP
, words
[i
], 2);
10520 for (i
= 0; i
< prec
; i
++)
10522 md_number_to_chars (litP
, words
[i
], 2);
10531 md_number_to_chars (char *buf
, valueT val
, int n
)
10533 if (target_big_endian
)
10534 number_to_chars_bigendian (buf
, val
, n
);
10536 number_to_chars_littleendian (buf
, val
, n
);
10540 static int support_64bit_objects(void)
10542 const char **list
, **l
;
10545 list
= bfd_target_list ();
10546 for (l
= list
; *l
!= NULL
; l
++)
10548 /* This is traditional mips */
10549 if (strcmp (*l
, "elf64-tradbigmips") == 0
10550 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10552 if (strcmp (*l
, "elf64-bigmips") == 0
10553 || strcmp (*l
, "elf64-littlemips") == 0)
10556 yes
= (*l
!= NULL
);
10560 #endif /* OBJ_ELF */
10562 const char *md_shortopts
= "O::g::G:";
10564 struct option md_longopts
[] =
10566 /* Options which specify architecture. */
10567 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10568 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10569 {"march", required_argument
, NULL
, OPTION_MARCH
},
10570 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10571 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10572 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10573 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10574 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10575 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10576 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10577 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10578 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10579 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10580 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10581 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10582 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10583 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10584 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10585 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10586 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10587 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10588 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10589 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10590 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10592 /* Options which specify Application Specific Extensions (ASEs). */
10593 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10594 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10595 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10596 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10597 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10598 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10599 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10600 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10601 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10602 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10603 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10604 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10605 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10606 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10607 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10608 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10609 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10610 #define OPTION_MT (OPTION_ASE_BASE + 8)
10611 {"mmt", no_argument
, NULL
, OPTION_MT
},
10612 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10613 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10615 /* Old-style architecture options. Don't add more of these. */
10616 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
10617 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10618 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10619 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10620 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10621 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10622 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10623 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10624 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10625 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10626 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10627 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10628 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10629 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10630 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10631 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10632 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10634 /* Options which enable bug fixes. */
10635 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10636 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10637 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10638 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10639 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10640 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10641 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10642 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10643 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10644 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10645 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10646 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10647 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10648 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10650 /* Miscellaneous options. */
10651 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10652 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10653 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10654 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10655 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10656 {"break", no_argument
, NULL
, OPTION_BREAK
},
10657 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10658 #define OPTION_EB (OPTION_MISC_BASE + 2)
10659 {"EB", no_argument
, NULL
, OPTION_EB
},
10660 #define OPTION_EL (OPTION_MISC_BASE + 3)
10661 {"EL", no_argument
, NULL
, OPTION_EL
},
10662 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10663 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10664 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10665 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10666 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10667 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10668 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10669 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10670 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10671 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10672 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10673 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10674 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10675 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10676 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10677 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10678 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10679 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10680 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10681 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10682 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10683 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10684 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10685 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10687 /* ELF-specific options. */
10689 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10690 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10691 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10692 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10693 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10694 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10695 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10696 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10697 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10698 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10699 #define OPTION_32 (OPTION_ELF_BASE + 4)
10700 {"32", no_argument
, NULL
, OPTION_32
},
10701 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10702 {"n32", no_argument
, NULL
, OPTION_N32
},
10703 #define OPTION_64 (OPTION_ELF_BASE + 6)
10704 {"64", no_argument
, NULL
, OPTION_64
},
10705 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10706 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10707 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10708 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10709 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10710 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10711 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10712 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10713 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10714 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10715 #endif /* OBJ_ELF */
10717 {NULL
, no_argument
, NULL
, 0}
10719 size_t md_longopts_size
= sizeof (md_longopts
);
10721 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10722 NEW_VALUE. Warn if another value was already specified. Note:
10723 we have to defer parsing the -march and -mtune arguments in order
10724 to handle 'from-abi' correctly, since the ABI might be specified
10725 in a later argument. */
10728 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10730 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10731 as_warn (_("A different %s was already specified, is now %s"),
10732 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10735 *string_ptr
= new_value
;
10739 md_parse_option (int c
, char *arg
)
10743 case OPTION_CONSTRUCT_FLOATS
:
10744 mips_disable_float_construction
= 0;
10747 case OPTION_NO_CONSTRUCT_FLOATS
:
10748 mips_disable_float_construction
= 1;
10760 target_big_endian
= 1;
10764 target_big_endian
= 0;
10768 if (arg
&& arg
[1] == '0')
10778 mips_debug
= atoi (arg
);
10779 /* When the MIPS assembler sees -g or -g2, it does not do
10780 optimizations which limit full symbolic debugging. We take
10781 that to be equivalent to -O0. */
10782 if (mips_debug
== 2)
10787 file_mips_isa
= ISA_MIPS1
;
10791 file_mips_isa
= ISA_MIPS2
;
10795 file_mips_isa
= ISA_MIPS3
;
10799 file_mips_isa
= ISA_MIPS4
;
10803 file_mips_isa
= ISA_MIPS5
;
10806 case OPTION_MIPS32
:
10807 file_mips_isa
= ISA_MIPS32
;
10810 case OPTION_MIPS32R2
:
10811 file_mips_isa
= ISA_MIPS32R2
;
10814 case OPTION_MIPS64R2
:
10815 file_mips_isa
= ISA_MIPS64R2
;
10818 case OPTION_MIPS64
:
10819 file_mips_isa
= ISA_MIPS64
;
10823 mips_set_option_string (&mips_tune_string
, arg
);
10827 mips_set_option_string (&mips_arch_string
, arg
);
10831 mips_set_option_string (&mips_arch_string
, "4650");
10832 mips_set_option_string (&mips_tune_string
, "4650");
10835 case OPTION_NO_M4650
:
10839 mips_set_option_string (&mips_arch_string
, "4010");
10840 mips_set_option_string (&mips_tune_string
, "4010");
10843 case OPTION_NO_M4010
:
10847 mips_set_option_string (&mips_arch_string
, "4100");
10848 mips_set_option_string (&mips_tune_string
, "4100");
10851 case OPTION_NO_M4100
:
10855 mips_set_option_string (&mips_arch_string
, "3900");
10856 mips_set_option_string (&mips_tune_string
, "3900");
10859 case OPTION_NO_M3900
:
10863 mips_opts
.ase_mdmx
= 1;
10866 case OPTION_NO_MDMX
:
10867 mips_opts
.ase_mdmx
= 0;
10871 mips_opts
.ase_dsp
= 1;
10874 case OPTION_NO_DSP
:
10875 mips_opts
.ase_dsp
= 0;
10879 mips_opts
.ase_mt
= 1;
10883 mips_opts
.ase_mt
= 0;
10886 case OPTION_MIPS16
:
10887 mips_opts
.mips16
= 1;
10888 mips_no_prev_insn ();
10891 case OPTION_NO_MIPS16
:
10892 mips_opts
.mips16
= 0;
10893 mips_no_prev_insn ();
10896 case OPTION_MIPS3D
:
10897 mips_opts
.ase_mips3d
= 1;
10900 case OPTION_NO_MIPS3D
:
10901 mips_opts
.ase_mips3d
= 0;
10904 case OPTION_FIX_VR4120
:
10905 mips_fix_vr4120
= 1;
10908 case OPTION_NO_FIX_VR4120
:
10909 mips_fix_vr4120
= 0;
10912 case OPTION_FIX_VR4130
:
10913 mips_fix_vr4130
= 1;
10916 case OPTION_NO_FIX_VR4130
:
10917 mips_fix_vr4130
= 0;
10920 case OPTION_RELAX_BRANCH
:
10921 mips_relax_branch
= 1;
10924 case OPTION_NO_RELAX_BRANCH
:
10925 mips_relax_branch
= 0;
10928 case OPTION_MSHARED
:
10929 mips_in_shared
= TRUE
;
10932 case OPTION_MNO_SHARED
:
10933 mips_in_shared
= FALSE
;
10936 case OPTION_MSYM32
:
10937 mips_opts
.sym32
= TRUE
;
10940 case OPTION_MNO_SYM32
:
10941 mips_opts
.sym32
= FALSE
;
10945 /* When generating ELF code, we permit -KPIC and -call_shared to
10946 select SVR4_PIC, and -non_shared to select no PIC. This is
10947 intended to be compatible with Irix 5. */
10948 case OPTION_CALL_SHARED
:
10949 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10951 as_bad (_("-call_shared is supported only for ELF format"));
10954 mips_pic
= SVR4_PIC
;
10955 mips_abicalls
= TRUE
;
10958 case OPTION_NON_SHARED
:
10959 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10961 as_bad (_("-non_shared is supported only for ELF format"));
10965 mips_abicalls
= FALSE
;
10968 /* The -xgot option tells the assembler to use 32 bit offsets
10969 when accessing the got in SVR4_PIC mode. It is for Irix
10974 #endif /* OBJ_ELF */
10977 g_switch_value
= atoi (arg
);
10982 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10985 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10987 as_bad (_("-32 is supported for ELF format only"));
10990 mips_abi
= O32_ABI
;
10994 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10996 as_bad (_("-n32 is supported for ELF format only"));
10999 mips_abi
= N32_ABI
;
11003 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11005 as_bad (_("-64 is supported for ELF format only"));
11008 mips_abi
= N64_ABI
;
11009 if (! support_64bit_objects())
11010 as_fatal (_("No compiled in support for 64 bit object file format"));
11012 #endif /* OBJ_ELF */
11015 file_mips_gp32
= 1;
11019 file_mips_gp32
= 0;
11023 file_mips_fp32
= 1;
11027 file_mips_fp32
= 0;
11032 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11034 as_bad (_("-mabi is supported for ELF format only"));
11037 if (strcmp (arg
, "32") == 0)
11038 mips_abi
= O32_ABI
;
11039 else if (strcmp (arg
, "o64") == 0)
11040 mips_abi
= O64_ABI
;
11041 else if (strcmp (arg
, "n32") == 0)
11042 mips_abi
= N32_ABI
;
11043 else if (strcmp (arg
, "64") == 0)
11045 mips_abi
= N64_ABI
;
11046 if (! support_64bit_objects())
11047 as_fatal (_("No compiled in support for 64 bit object file "
11050 else if (strcmp (arg
, "eabi") == 0)
11051 mips_abi
= EABI_ABI
;
11054 as_fatal (_("invalid abi -mabi=%s"), arg
);
11058 #endif /* OBJ_ELF */
11060 case OPTION_M7000_HILO_FIX
:
11061 mips_7000_hilo_fix
= TRUE
;
11064 case OPTION_MNO_7000_HILO_FIX
:
11065 mips_7000_hilo_fix
= FALSE
;
11069 case OPTION_MDEBUG
:
11070 mips_flag_mdebug
= TRUE
;
11073 case OPTION_NO_MDEBUG
:
11074 mips_flag_mdebug
= FALSE
;
11078 mips_flag_pdr
= TRUE
;
11081 case OPTION_NO_PDR
:
11082 mips_flag_pdr
= FALSE
;
11085 case OPTION_MVXWORKS_PIC
:
11086 mips_pic
= VXWORKS_PIC
;
11088 #endif /* OBJ_ELF */
11097 /* Set up globals to generate code for the ISA or processor
11098 described by INFO. */
11101 mips_set_architecture (const struct mips_cpu_info
*info
)
11105 file_mips_arch
= info
->cpu
;
11106 mips_opts
.arch
= info
->cpu
;
11107 mips_opts
.isa
= info
->isa
;
11112 /* Likewise for tuning. */
11115 mips_set_tune (const struct mips_cpu_info
*info
)
11118 mips_tune
= info
->cpu
;
11123 mips_after_parse_args (void)
11125 const struct mips_cpu_info
*arch_info
= 0;
11126 const struct mips_cpu_info
*tune_info
= 0;
11128 /* GP relative stuff not working for PE */
11129 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11131 if (g_switch_seen
&& g_switch_value
!= 0)
11132 as_bad (_("-G not supported in this configuration."));
11133 g_switch_value
= 0;
11136 if (mips_abi
== NO_ABI
)
11137 mips_abi
= MIPS_DEFAULT_ABI
;
11139 /* The following code determines the architecture and register size.
11140 Similar code was added to GCC 3.3 (see override_options() in
11141 config/mips/mips.c). The GAS and GCC code should be kept in sync
11142 as much as possible. */
11144 if (mips_arch_string
!= 0)
11145 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11147 if (file_mips_isa
!= ISA_UNKNOWN
)
11149 /* Handle -mipsN. At this point, file_mips_isa contains the
11150 ISA level specified by -mipsN, while arch_info->isa contains
11151 the -march selection (if any). */
11152 if (arch_info
!= 0)
11154 /* -march takes precedence over -mipsN, since it is more descriptive.
11155 There's no harm in specifying both as long as the ISA levels
11157 if (file_mips_isa
!= arch_info
->isa
)
11158 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11159 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11160 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11163 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11166 if (arch_info
== 0)
11167 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11169 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11170 as_bad ("-march=%s is not compatible with the selected ABI",
11173 mips_set_architecture (arch_info
);
11175 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11176 if (mips_tune_string
!= 0)
11177 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11179 if (tune_info
== 0)
11180 mips_set_tune (arch_info
);
11182 mips_set_tune (tune_info
);
11184 if (file_mips_gp32
>= 0)
11186 /* The user specified the size of the integer registers. Make sure
11187 it agrees with the ABI and ISA. */
11188 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11189 as_bad (_("-mgp64 used with a 32-bit processor"));
11190 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11191 as_bad (_("-mgp32 used with a 64-bit ABI"));
11192 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11193 as_bad (_("-mgp64 used with a 32-bit ABI"));
11197 /* Infer the integer register size from the ABI and processor.
11198 Restrict ourselves to 32-bit registers if that's all the
11199 processor has, or if the ABI cannot handle 64-bit registers. */
11200 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11201 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11204 /* ??? GAS treats single-float processors as though they had 64-bit
11205 float registers (although it complains when double-precision
11206 instructions are used). As things stand, saying they have 32-bit
11207 registers would lead to spurious "register must be even" messages.
11208 So here we assume float registers are always the same size as
11209 integer ones, unless the user says otherwise. */
11210 if (file_mips_fp32
< 0)
11211 file_mips_fp32
= file_mips_gp32
;
11213 /* End of GCC-shared inference code. */
11215 /* This flag is set when we have a 64-bit capable CPU but use only
11216 32-bit wide registers. Note that EABI does not use it. */
11217 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11218 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11219 || mips_abi
== O32_ABI
))
11220 mips_32bitmode
= 1;
11222 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11223 as_bad (_("trap exception not supported at ISA 1"));
11225 /* If the selected architecture includes support for ASEs, enable
11226 generation of code for them. */
11227 if (mips_opts
.mips16
== -1)
11228 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11229 if (mips_opts
.ase_mips3d
== -1)
11230 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
11231 if (mips_opts
.ase_mdmx
== -1)
11232 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
11233 if (mips_opts
.ase_dsp
== -1)
11234 mips_opts
.ase_dsp
= (CPU_HAS_DSP (file_mips_arch
)) ? 1 : 0;
11235 if (mips_opts
.ase_mt
== -1)
11236 mips_opts
.ase_mt
= (CPU_HAS_MT (file_mips_arch
)) ? 1 : 0;
11238 file_mips_isa
= mips_opts
.isa
;
11239 file_ase_mips16
= mips_opts
.mips16
;
11240 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11241 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11242 file_ase_dsp
= mips_opts
.ase_dsp
;
11243 file_ase_mt
= mips_opts
.ase_mt
;
11244 mips_opts
.gp32
= file_mips_gp32
;
11245 mips_opts
.fp32
= file_mips_fp32
;
11247 if (mips_flag_mdebug
< 0)
11249 #ifdef OBJ_MAYBE_ECOFF
11250 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11251 mips_flag_mdebug
= 1;
11253 #endif /* OBJ_MAYBE_ECOFF */
11254 mips_flag_mdebug
= 0;
11259 mips_init_after_args (void)
11261 /* initialize opcodes */
11262 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11263 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11267 md_pcrel_from (fixS
*fixP
)
11269 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11270 switch (fixP
->fx_r_type
)
11272 case BFD_RELOC_16_PCREL_S2
:
11273 case BFD_RELOC_MIPS_JMP
:
11274 /* Return the address of the delay slot. */
11281 /* This is called before the symbol table is processed. In order to
11282 work with gcc when using mips-tfile, we must keep all local labels.
11283 However, in other cases, we want to discard them. If we were
11284 called with -g, but we didn't see any debugging information, it may
11285 mean that gcc is smuggling debugging information through to
11286 mips-tfile, in which case we must generate all local labels. */
11289 mips_frob_file_before_adjust (void)
11291 #ifndef NO_ECOFF_DEBUGGING
11292 if (ECOFF_DEBUGGING
11294 && ! ecoff_debugging_seen
)
11295 flag_keep_locals
= 1;
11299 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11300 the corresponding LO16 reloc. This is called before md_apply_fix and
11301 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11302 relocation operators.
11304 For our purposes, a %lo() expression matches a %got() or %hi()
11307 (a) it refers to the same symbol; and
11308 (b) the offset applied in the %lo() expression is no lower than
11309 the offset applied in the %got() or %hi().
11311 (b) allows us to cope with code like:
11314 lh $4,%lo(foo+2)($4)
11316 ...which is legal on RELA targets, and has a well-defined behaviour
11317 if the user knows that adding 2 to "foo" will not induce a carry to
11320 When several %lo()s match a particular %got() or %hi(), we use the
11321 following rules to distinguish them:
11323 (1) %lo()s with smaller offsets are a better match than %lo()s with
11326 (2) %lo()s with no matching %got() or %hi() are better than those
11327 that already have a matching %got() or %hi().
11329 (3) later %lo()s are better than earlier %lo()s.
11331 These rules are applied in order.
11333 (1) means, among other things, that %lo()s with identical offsets are
11334 chosen if they exist.
11336 (2) means that we won't associate several high-part relocations with
11337 the same low-part relocation unless there's no alternative. Having
11338 several high parts for the same low part is a GNU extension; this rule
11339 allows careful users to avoid it.
11341 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11342 with the last high-part relocation being at the front of the list.
11343 It therefore makes sense to choose the last matching low-part
11344 relocation, all other things being equal. It's also easier
11345 to code that way. */
11348 mips_frob_file (void)
11350 struct mips_hi_fixup
*l
;
11352 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11354 segment_info_type
*seginfo
;
11355 bfd_boolean matched_lo_p
;
11356 fixS
**hi_pos
, **lo_pos
, **pos
;
11358 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11360 /* If a GOT16 relocation turns out to be against a global symbol,
11361 there isn't supposed to be a matching LO. */
11362 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11363 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11366 /* Check quickly whether the next fixup happens to be a matching %lo. */
11367 if (fixup_has_matching_lo_p (l
->fixp
))
11370 seginfo
= seg_info (l
->seg
);
11372 /* Set HI_POS to the position of this relocation in the chain.
11373 Set LO_POS to the position of the chosen low-part relocation.
11374 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11375 relocation that matches an immediately-preceding high-part
11379 matched_lo_p
= FALSE
;
11380 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11382 if (*pos
== l
->fixp
)
11385 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11386 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11387 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11388 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11390 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11392 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11395 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11396 && fixup_has_matching_lo_p (*pos
));
11399 /* If we found a match, remove the high-part relocation from its
11400 current position and insert it before the low-part relocation.
11401 Make the offsets match so that fixup_has_matching_lo_p()
11404 We don't warn about unmatched high-part relocations since some
11405 versions of gcc have been known to emit dead "lui ...%hi(...)"
11407 if (lo_pos
!= NULL
)
11409 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11410 if (l
->fixp
->fx_next
!= *lo_pos
)
11412 *hi_pos
= l
->fixp
->fx_next
;
11413 l
->fixp
->fx_next
= *lo_pos
;
11420 /* We may have combined relocations without symbols in the N32/N64 ABI.
11421 We have to prevent gas from dropping them. */
11424 mips_force_relocation (fixS
*fixp
)
11426 if (generic_force_reloc (fixp
))
11430 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11431 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11432 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11433 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11439 /* Apply a fixup to the object file. */
11442 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11446 reloc_howto_type
*howto
;
11448 /* We ignore generic BFD relocations we don't know about. */
11449 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11453 assert (fixP
->fx_size
== 4
11454 || fixP
->fx_r_type
== BFD_RELOC_16
11455 || fixP
->fx_r_type
== BFD_RELOC_64
11456 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11457 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11458 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11459 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11461 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11463 assert (! fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11465 /* Don't treat parts of a composite relocation as done. There are two
11468 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11469 should nevertheless be emitted if the first part is.
11471 (2) In normal usage, composite relocations are never assembly-time
11472 constants. The easiest way of dealing with the pathological
11473 exceptions is to generate a relocation against STN_UNDEF and
11474 leave everything up to the linker. */
11475 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11478 switch (fixP
->fx_r_type
)
11480 case BFD_RELOC_MIPS_TLS_GD
:
11481 case BFD_RELOC_MIPS_TLS_LDM
:
11482 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11483 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11484 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11485 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11486 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11487 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11490 case BFD_RELOC_MIPS_JMP
:
11491 case BFD_RELOC_MIPS_SHIFT5
:
11492 case BFD_RELOC_MIPS_SHIFT6
:
11493 case BFD_RELOC_MIPS_GOT_DISP
:
11494 case BFD_RELOC_MIPS_GOT_PAGE
:
11495 case BFD_RELOC_MIPS_GOT_OFST
:
11496 case BFD_RELOC_MIPS_SUB
:
11497 case BFD_RELOC_MIPS_INSERT_A
:
11498 case BFD_RELOC_MIPS_INSERT_B
:
11499 case BFD_RELOC_MIPS_DELETE
:
11500 case BFD_RELOC_MIPS_HIGHEST
:
11501 case BFD_RELOC_MIPS_HIGHER
:
11502 case BFD_RELOC_MIPS_SCN_DISP
:
11503 case BFD_RELOC_MIPS_REL16
:
11504 case BFD_RELOC_MIPS_RELGOT
:
11505 case BFD_RELOC_MIPS_JALR
:
11506 case BFD_RELOC_HI16
:
11507 case BFD_RELOC_HI16_S
:
11508 case BFD_RELOC_GPREL16
:
11509 case BFD_RELOC_MIPS_LITERAL
:
11510 case BFD_RELOC_MIPS_CALL16
:
11511 case BFD_RELOC_MIPS_GOT16
:
11512 case BFD_RELOC_GPREL32
:
11513 case BFD_RELOC_MIPS_GOT_HI16
:
11514 case BFD_RELOC_MIPS_GOT_LO16
:
11515 case BFD_RELOC_MIPS_CALL_HI16
:
11516 case BFD_RELOC_MIPS_CALL_LO16
:
11517 case BFD_RELOC_MIPS16_GPREL
:
11518 case BFD_RELOC_MIPS16_HI16
:
11519 case BFD_RELOC_MIPS16_HI16_S
:
11520 /* Nothing needed to do. The value comes from the reloc entry */
11523 case BFD_RELOC_MIPS16_JMP
:
11524 /* We currently always generate a reloc against a symbol, which
11525 means that we don't want an addend even if the symbol is
11531 /* This is handled like BFD_RELOC_32, but we output a sign
11532 extended value if we are only 32 bits. */
11535 if (8 <= sizeof (valueT
))
11536 md_number_to_chars ((char *) buf
, *valP
, 8);
11541 if ((*valP
& 0x80000000) != 0)
11545 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11547 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11553 case BFD_RELOC_RVA
:
11555 /* If we are deleting this reloc entry, we must fill in the
11556 value now. This can happen if we have a .word which is not
11557 resolved when it appears but is later defined. */
11559 md_number_to_chars ((char *) buf
, *valP
, 4);
11563 /* If we are deleting this reloc entry, we must fill in the
11566 md_number_to_chars ((char *) buf
, *valP
, 2);
11569 case BFD_RELOC_LO16
:
11570 case BFD_RELOC_MIPS16_LO16
:
11571 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11572 may be safe to remove, but if so it's not obvious. */
11573 /* When handling an embedded PIC switch statement, we can wind
11574 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11577 if (*valP
+ 0x8000 > 0xffff)
11578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11579 _("relocation overflow"));
11580 if (target_big_endian
)
11582 md_number_to_chars ((char *) buf
, *valP
, 2);
11586 case BFD_RELOC_16_PCREL_S2
:
11587 if ((*valP
& 0x3) != 0)
11588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11589 _("Branch to misaligned address (%lx)"), (long) *valP
);
11592 * We need to save the bits in the instruction since fixup_segment()
11593 * might be deleting the relocation entry (i.e., a branch within
11594 * the current segment).
11596 if (! fixP
->fx_done
)
11599 /* update old instruction data */
11600 if (target_big_endian
)
11601 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11603 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11605 if (*valP
+ 0x20000 <= 0x3ffff)
11607 insn
|= (*valP
>> 2) & 0xffff;
11608 md_number_to_chars ((char *) buf
, insn
, 4);
11610 else if (mips_pic
== NO_PIC
11612 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11613 && (fixP
->fx_frag
->fr_address
11614 < text_section
->vma
+ bfd_get_section_size (text_section
))
11615 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11616 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11617 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11619 /* The branch offset is too large. If this is an
11620 unconditional branch, and we are not generating PIC code,
11621 we can convert it to an absolute jump instruction. */
11622 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11623 insn
= 0x0c000000; /* jal */
11625 insn
= 0x08000000; /* j */
11626 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11628 fixP
->fx_addsy
= section_symbol (text_section
);
11629 *valP
+= md_pcrel_from (fixP
);
11630 md_number_to_chars ((char *) buf
, insn
, 4);
11634 /* If we got here, we have branch-relaxation disabled,
11635 and there's nothing we can do to fix this instruction
11636 without turning it into a longer sequence. */
11637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11638 _("Branch out of range"));
11642 case BFD_RELOC_VTABLE_INHERIT
:
11645 && !S_IS_DEFINED (fixP
->fx_addsy
)
11646 && !S_IS_WEAK (fixP
->fx_addsy
))
11647 S_SET_WEAK (fixP
->fx_addsy
);
11650 case BFD_RELOC_VTABLE_ENTRY
:
11658 /* Remember value for tc_gen_reloc. */
11659 fixP
->fx_addnumber
= *valP
;
11669 name
= input_line_pointer
;
11670 c
= get_symbol_end ();
11671 p
= (symbolS
*) symbol_find_or_make (name
);
11672 *input_line_pointer
= c
;
11676 /* Align the current frag to a given power of two. The MIPS assembler
11677 also automatically adjusts any preceding label. */
11680 mips_align (int to
, int fill
, symbolS
*label
)
11682 mips_emit_delays ();
11683 frag_align (to
, fill
, 0);
11684 record_alignment (now_seg
, to
);
11687 assert (S_GET_SEGMENT (label
) == now_seg
);
11688 symbol_set_frag (label
, frag_now
);
11689 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11693 /* Align to a given power of two. .align 0 turns off the automatic
11694 alignment used by the data creating pseudo-ops. */
11697 s_align (int x ATTRIBUTE_UNUSED
)
11700 register long temp_fill
;
11701 long max_alignment
= 15;
11705 o Note that the assembler pulls down any immediately preceding label
11706 to the aligned address.
11707 o It's not documented but auto alignment is reinstated by
11708 a .align pseudo instruction.
11709 o Note also that after auto alignment is turned off the mips assembler
11710 issues an error on attempt to assemble an improperly aligned data item.
11715 temp
= get_absolute_expression ();
11716 if (temp
> max_alignment
)
11717 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11720 as_warn (_("Alignment negative: 0 assumed."));
11723 if (*input_line_pointer
== ',')
11725 ++input_line_pointer
;
11726 temp_fill
= get_absolute_expression ();
11733 mips_align (temp
, (int) temp_fill
,
11734 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11741 demand_empty_rest_of_line ();
11745 s_change_sec (int sec
)
11750 /* The ELF backend needs to know that we are changing sections, so
11751 that .previous works correctly. We could do something like check
11752 for an obj_section_change_hook macro, but that might be confusing
11753 as it would not be appropriate to use it in the section changing
11754 functions in read.c, since obj-elf.c intercepts those. FIXME:
11755 This should be cleaner, somehow. */
11756 obj_elf_section_change_hook ();
11759 mips_emit_delays ();
11769 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11770 demand_empty_rest_of_line ();
11774 seg
= subseg_new (RDATA_SECTION_NAME
,
11775 (subsegT
) get_absolute_expression ());
11776 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11778 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11779 | SEC_READONLY
| SEC_RELOC
11781 if (strcmp (TARGET_OS
, "elf") != 0)
11782 record_alignment (seg
, 4);
11784 demand_empty_rest_of_line ();
11788 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11789 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11791 bfd_set_section_flags (stdoutput
, seg
,
11792 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11793 if (strcmp (TARGET_OS
, "elf") != 0)
11794 record_alignment (seg
, 4);
11796 demand_empty_rest_of_line ();
11804 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11807 char *section_name
;
11812 int section_entry_size
;
11813 int section_alignment
;
11815 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11818 section_name
= input_line_pointer
;
11819 c
= get_symbol_end ();
11821 next_c
= *(input_line_pointer
+ 1);
11823 /* Do we have .section Name<,"flags">? */
11824 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11826 /* just after name is now '\0'. */
11827 *input_line_pointer
= c
;
11828 input_line_pointer
= section_name
;
11829 obj_elf_section (ignore
);
11832 input_line_pointer
++;
11834 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11836 section_type
= get_absolute_expression ();
11839 if (*input_line_pointer
++ == ',')
11840 section_flag
= get_absolute_expression ();
11843 if (*input_line_pointer
++ == ',')
11844 section_entry_size
= get_absolute_expression ();
11846 section_entry_size
= 0;
11847 if (*input_line_pointer
++ == ',')
11848 section_alignment
= get_absolute_expression ();
11850 section_alignment
= 0;
11852 section_name
= xstrdup (section_name
);
11854 /* When using the generic form of .section (as implemented by obj-elf.c),
11855 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11856 traditionally had to fall back on the more common @progbits instead.
11858 There's nothing really harmful in this, since bfd will correct
11859 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11860 means that, for backwards compatibility, the special_section entries
11861 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11863 Even so, we shouldn't force users of the MIPS .section syntax to
11864 incorrectly label the sections as SHT_PROGBITS. The best compromise
11865 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11866 generic type-checking code. */
11867 if (section_type
== SHT_MIPS_DWARF
)
11868 section_type
= SHT_PROGBITS
;
11870 obj_elf_change_section (section_name
, section_type
, section_flag
,
11871 section_entry_size
, 0, 0, 0);
11873 if (now_seg
->name
!= section_name
)
11874 free (section_name
);
11875 #endif /* OBJ_ELF */
11879 mips_enable_auto_align (void)
11885 s_cons (int log_size
)
11889 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11890 mips_emit_delays ();
11891 if (log_size
> 0 && auto_align
)
11892 mips_align (log_size
, 0, label
);
11893 mips_clear_insn_labels ();
11894 cons (1 << log_size
);
11898 s_float_cons (int type
)
11902 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11904 mips_emit_delays ();
11909 mips_align (3, 0, label
);
11911 mips_align (2, 0, label
);
11914 mips_clear_insn_labels ();
11919 /* Handle .globl. We need to override it because on Irix 5 you are
11922 where foo is an undefined symbol, to mean that foo should be
11923 considered to be the address of a function. */
11926 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11935 name
= input_line_pointer
;
11936 c
= get_symbol_end ();
11937 symbolP
= symbol_find_or_make (name
);
11938 S_SET_EXTERNAL (symbolP
);
11940 *input_line_pointer
= c
;
11941 SKIP_WHITESPACE ();
11943 /* On Irix 5, every global symbol that is not explicitly labelled as
11944 being a function is apparently labelled as being an object. */
11947 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
11948 && (*input_line_pointer
!= ','))
11953 secname
= input_line_pointer
;
11954 c
= get_symbol_end ();
11955 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11957 as_bad (_("%s: no such section"), secname
);
11958 *input_line_pointer
= c
;
11960 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11961 flag
= BSF_FUNCTION
;
11964 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11966 c
= *input_line_pointer
;
11969 input_line_pointer
++;
11970 SKIP_WHITESPACE ();
11971 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
11977 demand_empty_rest_of_line ();
11981 s_option (int x ATTRIBUTE_UNUSED
)
11986 opt
= input_line_pointer
;
11987 c
= get_symbol_end ();
11991 /* FIXME: What does this mean? */
11993 else if (strncmp (opt
, "pic", 3) == 0)
11997 i
= atoi (opt
+ 3);
12002 mips_pic
= SVR4_PIC
;
12003 mips_abicalls
= TRUE
;
12006 as_bad (_(".option pic%d not supported"), i
);
12008 if (mips_pic
== SVR4_PIC
)
12010 if (g_switch_seen
&& g_switch_value
!= 0)
12011 as_warn (_("-G may not be used with SVR4 PIC code"));
12012 g_switch_value
= 0;
12013 bfd_set_gp_size (stdoutput
, 0);
12017 as_warn (_("Unrecognized option \"%s\""), opt
);
12019 *input_line_pointer
= c
;
12020 demand_empty_rest_of_line ();
12023 /* This structure is used to hold a stack of .set values. */
12025 struct mips_option_stack
12027 struct mips_option_stack
*next
;
12028 struct mips_set_options options
;
12031 static struct mips_option_stack
*mips_opts_stack
;
12033 /* Handle the .set pseudo-op. */
12036 s_mipsset (int x ATTRIBUTE_UNUSED
)
12038 char *name
= input_line_pointer
, ch
;
12040 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12041 ++input_line_pointer
;
12042 ch
= *input_line_pointer
;
12043 *input_line_pointer
= '\0';
12045 if (strcmp (name
, "reorder") == 0)
12047 if (mips_opts
.noreorder
)
12050 else if (strcmp (name
, "noreorder") == 0)
12052 if (!mips_opts
.noreorder
)
12053 start_noreorder ();
12055 else if (strcmp (name
, "at") == 0)
12057 mips_opts
.noat
= 0;
12059 else if (strcmp (name
, "noat") == 0)
12061 mips_opts
.noat
= 1;
12063 else if (strcmp (name
, "macro") == 0)
12065 mips_opts
.warn_about_macros
= 0;
12067 else if (strcmp (name
, "nomacro") == 0)
12069 if (mips_opts
.noreorder
== 0)
12070 as_bad (_("`noreorder' must be set before `nomacro'"));
12071 mips_opts
.warn_about_macros
= 1;
12073 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12075 mips_opts
.nomove
= 0;
12077 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12079 mips_opts
.nomove
= 1;
12081 else if (strcmp (name
, "bopt") == 0)
12083 mips_opts
.nobopt
= 0;
12085 else if (strcmp (name
, "nobopt") == 0)
12087 mips_opts
.nobopt
= 1;
12089 else if (strcmp (name
, "mips16") == 0
12090 || strcmp (name
, "MIPS-16") == 0)
12091 mips_opts
.mips16
= 1;
12092 else if (strcmp (name
, "nomips16") == 0
12093 || strcmp (name
, "noMIPS-16") == 0)
12094 mips_opts
.mips16
= 0;
12095 else if (strcmp (name
, "mips3d") == 0)
12096 mips_opts
.ase_mips3d
= 1;
12097 else if (strcmp (name
, "nomips3d") == 0)
12098 mips_opts
.ase_mips3d
= 0;
12099 else if (strcmp (name
, "mdmx") == 0)
12100 mips_opts
.ase_mdmx
= 1;
12101 else if (strcmp (name
, "nomdmx") == 0)
12102 mips_opts
.ase_mdmx
= 0;
12103 else if (strcmp (name
, "dsp") == 0)
12104 mips_opts
.ase_dsp
= 1;
12105 else if (strcmp (name
, "nodsp") == 0)
12106 mips_opts
.ase_dsp
= 0;
12107 else if (strcmp (name
, "mt") == 0)
12108 mips_opts
.ase_mt
= 1;
12109 else if (strcmp (name
, "nomt") == 0)
12110 mips_opts
.ase_mt
= 0;
12111 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12115 /* Permit the user to change the ISA and architecture on the fly.
12116 Needless to say, misuse can cause serious problems. */
12117 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12120 mips_opts
.isa
= file_mips_isa
;
12121 mips_opts
.arch
= file_mips_arch
;
12123 else if (strncmp (name
, "arch=", 5) == 0)
12125 const struct mips_cpu_info
*p
;
12127 p
= mips_parse_cpu("internal use", name
+ 5);
12129 as_bad (_("unknown architecture %s"), name
+ 5);
12132 mips_opts
.arch
= p
->cpu
;
12133 mips_opts
.isa
= p
->isa
;
12136 else if (strncmp (name
, "mips", 4) == 0)
12138 const struct mips_cpu_info
*p
;
12140 p
= mips_parse_cpu("internal use", name
);
12142 as_bad (_("unknown ISA level %s"), name
+ 4);
12145 mips_opts
.arch
= p
->cpu
;
12146 mips_opts
.isa
= p
->isa
;
12150 as_bad (_("unknown ISA or architecture %s"), name
);
12152 switch (mips_opts
.isa
)
12160 mips_opts
.gp32
= 1;
12161 mips_opts
.fp32
= 1;
12168 mips_opts
.gp32
= 0;
12169 mips_opts
.fp32
= 0;
12172 as_bad (_("unknown ISA level %s"), name
+ 4);
12177 mips_opts
.gp32
= file_mips_gp32
;
12178 mips_opts
.fp32
= file_mips_fp32
;
12181 else if (strcmp (name
, "autoextend") == 0)
12182 mips_opts
.noautoextend
= 0;
12183 else if (strcmp (name
, "noautoextend") == 0)
12184 mips_opts
.noautoextend
= 1;
12185 else if (strcmp (name
, "push") == 0)
12187 struct mips_option_stack
*s
;
12189 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12190 s
->next
= mips_opts_stack
;
12191 s
->options
= mips_opts
;
12192 mips_opts_stack
= s
;
12194 else if (strcmp (name
, "pop") == 0)
12196 struct mips_option_stack
*s
;
12198 s
= mips_opts_stack
;
12200 as_bad (_(".set pop with no .set push"));
12203 /* If we're changing the reorder mode we need to handle
12204 delay slots correctly. */
12205 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12206 start_noreorder ();
12207 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12210 mips_opts
= s
->options
;
12211 mips_opts_stack
= s
->next
;
12215 else if (strcmp (name
, "sym32") == 0)
12216 mips_opts
.sym32
= TRUE
;
12217 else if (strcmp (name
, "nosym32") == 0)
12218 mips_opts
.sym32
= FALSE
;
12221 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12223 *input_line_pointer
= ch
;
12224 demand_empty_rest_of_line ();
12227 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12228 .option pic2. It means to generate SVR4 PIC calls. */
12231 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12233 mips_pic
= SVR4_PIC
;
12234 mips_abicalls
= TRUE
;
12236 if (g_switch_seen
&& g_switch_value
!= 0)
12237 as_warn (_("-G may not be used with SVR4 PIC code"));
12238 g_switch_value
= 0;
12240 bfd_set_gp_size (stdoutput
, 0);
12241 demand_empty_rest_of_line ();
12244 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12245 PIC code. It sets the $gp register for the function based on the
12246 function address, which is in the register named in the argument.
12247 This uses a relocation against _gp_disp, which is handled specially
12248 by the linker. The result is:
12249 lui $gp,%hi(_gp_disp)
12250 addiu $gp,$gp,%lo(_gp_disp)
12251 addu $gp,$gp,.cpload argument
12252 The .cpload argument is normally $25 == $t9.
12254 The -mno-shared option changes this to:
12255 lui $gp,%hi(__gnu_local_gp)
12256 addiu $gp,$gp,%lo(__gnu_local_gp)
12257 and the argument is ignored. This saves an instruction, but the
12258 resulting code is not position independent; it uses an absolute
12259 address for __gnu_local_gp. Thus code assembled with -mno-shared
12260 can go into an ordinary executable, but not into a shared library. */
12263 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12269 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12270 .cpload is ignored. */
12271 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12277 /* .cpload should be in a .set noreorder section. */
12278 if (mips_opts
.noreorder
== 0)
12279 as_warn (_(".cpload not in noreorder section"));
12281 reg
= tc_get_register (0);
12283 /* If we need to produce a 64-bit address, we are better off using
12284 the default instruction sequence. */
12285 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12287 ex
.X_op
= O_symbol
;
12288 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12290 ex
.X_op_symbol
= NULL
;
12291 ex
.X_add_number
= 0;
12293 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12294 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12297 macro_build_lui (&ex
, mips_gp_register
);
12298 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12299 mips_gp_register
, BFD_RELOC_LO16
);
12301 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12302 mips_gp_register
, reg
);
12305 demand_empty_rest_of_line ();
12308 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12309 .cpsetup $reg1, offset|$reg2, label
12311 If offset is given, this results in:
12312 sd $gp, offset($sp)
12313 lui $gp, %hi(%neg(%gp_rel(label)))
12314 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12315 daddu $gp, $gp, $reg1
12317 If $reg2 is given, this results in:
12318 daddu $reg2, $gp, $0
12319 lui $gp, %hi(%neg(%gp_rel(label)))
12320 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12321 daddu $gp, $gp, $reg1
12322 $reg1 is normally $25 == $t9.
12324 The -mno-shared option replaces the last three instructions with
12326 addiu $gp,$gp,%lo(_gp)
12330 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12332 expressionS ex_off
;
12333 expressionS ex_sym
;
12336 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12337 We also need NewABI support. */
12338 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12344 reg1
= tc_get_register (0);
12345 SKIP_WHITESPACE ();
12346 if (*input_line_pointer
!= ',')
12348 as_bad (_("missing argument separator ',' for .cpsetup"));
12352 ++input_line_pointer
;
12353 SKIP_WHITESPACE ();
12354 if (*input_line_pointer
== '$')
12356 mips_cpreturn_register
= tc_get_register (0);
12357 mips_cpreturn_offset
= -1;
12361 mips_cpreturn_offset
= get_absolute_expression ();
12362 mips_cpreturn_register
= -1;
12364 SKIP_WHITESPACE ();
12365 if (*input_line_pointer
!= ',')
12367 as_bad (_("missing argument separator ',' for .cpsetup"));
12371 ++input_line_pointer
;
12372 SKIP_WHITESPACE ();
12373 expression (&ex_sym
);
12376 if (mips_cpreturn_register
== -1)
12378 ex_off
.X_op
= O_constant
;
12379 ex_off
.X_add_symbol
= NULL
;
12380 ex_off
.X_op_symbol
= NULL
;
12381 ex_off
.X_add_number
= mips_cpreturn_offset
;
12383 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12384 BFD_RELOC_LO16
, SP
);
12387 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12388 mips_gp_register
, 0);
12390 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12392 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12393 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12396 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12397 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12398 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12400 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12401 mips_gp_register
, reg1
);
12407 ex
.X_op
= O_symbol
;
12408 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12409 ex
.X_op_symbol
= NULL
;
12410 ex
.X_add_number
= 0;
12412 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12413 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12415 macro_build_lui (&ex
, mips_gp_register
);
12416 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12417 mips_gp_register
, BFD_RELOC_LO16
);
12422 demand_empty_rest_of_line ();
12426 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12428 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12429 .cplocal is ignored. */
12430 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12436 mips_gp_register
= tc_get_register (0);
12437 demand_empty_rest_of_line ();
12440 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12441 offset from $sp. The offset is remembered, and after making a PIC
12442 call $gp is restored from that location. */
12445 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12449 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12450 .cprestore is ignored. */
12451 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12457 mips_cprestore_offset
= get_absolute_expression ();
12458 mips_cprestore_valid
= 1;
12460 ex
.X_op
= O_constant
;
12461 ex
.X_add_symbol
= NULL
;
12462 ex
.X_op_symbol
= NULL
;
12463 ex
.X_add_number
= mips_cprestore_offset
;
12466 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12467 SP
, HAVE_64BIT_ADDRESSES
);
12470 demand_empty_rest_of_line ();
12473 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12474 was given in the preceding .cpsetup, it results in:
12475 ld $gp, offset($sp)
12477 If a register $reg2 was given there, it results in:
12478 daddu $gp, $reg2, $0
12481 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12485 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12486 We also need NewABI support. */
12487 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12494 if (mips_cpreturn_register
== -1)
12496 ex
.X_op
= O_constant
;
12497 ex
.X_add_symbol
= NULL
;
12498 ex
.X_op_symbol
= NULL
;
12499 ex
.X_add_number
= mips_cpreturn_offset
;
12501 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12504 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12505 mips_cpreturn_register
, 0);
12508 demand_empty_rest_of_line ();
12511 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12512 code. It sets the offset to use in gp_rel relocations. */
12515 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12517 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12518 We also need NewABI support. */
12519 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12525 mips_gprel_offset
= get_absolute_expression ();
12527 demand_empty_rest_of_line ();
12530 /* Handle the .gpword pseudo-op. This is used when generating PIC
12531 code. It generates a 32 bit GP relative reloc. */
12534 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12540 /* When not generating PIC code, this is treated as .word. */
12541 if (mips_pic
!= SVR4_PIC
)
12547 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12548 mips_emit_delays ();
12550 mips_align (2, 0, label
);
12551 mips_clear_insn_labels ();
12555 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12557 as_bad (_("Unsupported use of .gpword"));
12558 ignore_rest_of_line ();
12562 md_number_to_chars (p
, 0, 4);
12563 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12564 BFD_RELOC_GPREL32
);
12566 demand_empty_rest_of_line ();
12570 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12576 /* When not generating PIC code, this is treated as .dword. */
12577 if (mips_pic
!= SVR4_PIC
)
12583 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12584 mips_emit_delays ();
12586 mips_align (3, 0, label
);
12587 mips_clear_insn_labels ();
12591 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12593 as_bad (_("Unsupported use of .gpdword"));
12594 ignore_rest_of_line ();
12598 md_number_to_chars (p
, 0, 8);
12599 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12600 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12602 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12603 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12604 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12606 demand_empty_rest_of_line ();
12609 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12610 tables in SVR4 PIC code. */
12613 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12617 /* This is ignored when not generating SVR4 PIC code. */
12618 if (mips_pic
!= SVR4_PIC
)
12624 /* Add $gp to the register named as an argument. */
12626 reg
= tc_get_register (0);
12627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12630 demand_empty_rest_of_line ();
12633 /* Handle the .insn pseudo-op. This marks instruction labels in
12634 mips16 mode. This permits the linker to handle them specially,
12635 such as generating jalx instructions when needed. We also make
12636 them odd for the duration of the assembly, in order to generate the
12637 right sort of code. We will make them even in the adjust_symtab
12638 routine, while leaving them marked. This is convenient for the
12639 debugger and the disassembler. The linker knows to make them odd
12643 s_insn (int ignore ATTRIBUTE_UNUSED
)
12645 mips16_mark_labels ();
12647 demand_empty_rest_of_line ();
12650 /* Handle a .stabn directive. We need these in order to mark a label
12651 as being a mips16 text label correctly. Sometimes the compiler
12652 will emit a label, followed by a .stabn, and then switch sections.
12653 If the label and .stabn are in mips16 mode, then the label is
12654 really a mips16 text label. */
12657 s_mips_stab (int type
)
12660 mips16_mark_labels ();
12665 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12669 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12676 name
= input_line_pointer
;
12677 c
= get_symbol_end ();
12678 symbolP
= symbol_find_or_make (name
);
12679 S_SET_WEAK (symbolP
);
12680 *input_line_pointer
= c
;
12682 SKIP_WHITESPACE ();
12684 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12686 if (S_IS_DEFINED (symbolP
))
12688 as_bad ("ignoring attempt to redefine symbol %s",
12689 S_GET_NAME (symbolP
));
12690 ignore_rest_of_line ();
12694 if (*input_line_pointer
== ',')
12696 ++input_line_pointer
;
12697 SKIP_WHITESPACE ();
12701 if (exp
.X_op
!= O_symbol
)
12703 as_bad ("bad .weakext directive");
12704 ignore_rest_of_line ();
12707 symbol_set_value_expression (symbolP
, &exp
);
12710 demand_empty_rest_of_line ();
12713 /* Parse a register string into a number. Called from the ECOFF code
12714 to parse .frame. The argument is non-zero if this is the frame
12715 register, so that we can record it in mips_frame_reg. */
12718 tc_get_register (int frame
)
12722 SKIP_WHITESPACE ();
12723 if (*input_line_pointer
++ != '$')
12725 as_warn (_("expected `$'"));
12728 else if (ISDIGIT (*input_line_pointer
))
12730 reg
= get_absolute_expression ();
12731 if (reg
< 0 || reg
>= 32)
12733 as_warn (_("Bad register number"));
12739 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12742 input_line_pointer
+= 2;
12744 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12747 input_line_pointer
+= 2;
12749 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12752 input_line_pointer
+= 2;
12754 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12757 input_line_pointer
+= 2;
12759 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12762 input_line_pointer
+= 2;
12764 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12767 input_line_pointer
+= 3;
12769 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12772 input_line_pointer
+= 3;
12774 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12777 input_line_pointer
+= 4;
12781 as_warn (_("Unrecognized register name"));
12783 while (ISALNUM(*input_line_pointer
))
12784 input_line_pointer
++;
12789 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12790 mips_frame_reg_valid
= 1;
12791 mips_cprestore_valid
= 0;
12797 md_section_align (asection
*seg
, valueT addr
)
12799 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12802 /* We don't need to align ELF sections to the full alignment.
12803 However, Irix 5 may prefer that we align them at least to a 16
12804 byte boundary. We don't bother to align the sections if we are
12805 targeted for an embedded system. */
12806 if (strcmp (TARGET_OS
, "elf") == 0)
12812 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12815 /* Utility routine, called from above as well. If called while the
12816 input file is still being read, it's only an approximation. (For
12817 example, a symbol may later become defined which appeared to be
12818 undefined earlier.) */
12821 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12826 if (g_switch_value
> 0)
12828 const char *symname
;
12831 /* Find out whether this symbol can be referenced off the $gp
12832 register. It can be if it is smaller than the -G size or if
12833 it is in the .sdata or .sbss section. Certain symbols can
12834 not be referenced off the $gp, although it appears as though
12836 symname
= S_GET_NAME (sym
);
12837 if (symname
!= (const char *) NULL
12838 && (strcmp (symname
, "eprol") == 0
12839 || strcmp (symname
, "etext") == 0
12840 || strcmp (symname
, "_gp") == 0
12841 || strcmp (symname
, "edata") == 0
12842 || strcmp (symname
, "_fbss") == 0
12843 || strcmp (symname
, "_fdata") == 0
12844 || strcmp (symname
, "_ftext") == 0
12845 || strcmp (symname
, "end") == 0
12846 || strcmp (symname
, "_gp_disp") == 0))
12848 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12850 #ifndef NO_ECOFF_DEBUGGING
12851 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12852 && (symbol_get_obj (sym
)->ecoff_extern_size
12853 <= g_switch_value
))
12855 /* We must defer this decision until after the whole
12856 file has been read, since there might be a .extern
12857 after the first use of this symbol. */
12858 || (before_relaxing
12859 #ifndef NO_ECOFF_DEBUGGING
12860 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12862 && S_GET_VALUE (sym
) == 0)
12863 || (S_GET_VALUE (sym
) != 0
12864 && S_GET_VALUE (sym
) <= g_switch_value
)))
12868 const char *segname
;
12870 segname
= segment_name (S_GET_SEGMENT (sym
));
12871 assert (strcmp (segname
, ".lit8") != 0
12872 && strcmp (segname
, ".lit4") != 0);
12873 change
= (strcmp (segname
, ".sdata") != 0
12874 && strcmp (segname
, ".sbss") != 0
12875 && strncmp (segname
, ".sdata.", 7) != 0
12876 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12881 /* We are not optimizing for the $gp register. */
12886 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12889 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12892 bfd_boolean linkonce
;
12894 /* Handle the case of a symbol equated to another symbol. */
12895 while (symbol_equated_reloc_p (sym
))
12899 /* It's possible to get a loop here in a badly written
12901 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12907 symsec
= S_GET_SEGMENT (sym
);
12909 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12911 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12913 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12917 /* The GNU toolchain uses an extension for ELF: a section
12918 beginning with the magic string .gnu.linkonce is a linkonce
12920 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12921 sizeof ".gnu.linkonce" - 1) == 0)
12925 /* This must duplicate the test in adjust_reloc_syms. */
12926 return (symsec
!= &bfd_und_section
12927 && symsec
!= &bfd_abs_section
12928 && ! bfd_is_com_section (symsec
)
12931 /* A global or weak symbol is treated as external. */
12932 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12933 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12939 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12940 extended opcode. SEC is the section the frag is in. */
12943 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12946 register const struct mips16_immed_operand
*op
;
12948 int mintiny
, maxtiny
;
12952 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12954 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12957 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12958 op
= mips16_immed_operands
;
12959 while (op
->type
!= type
)
12962 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12967 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12970 maxtiny
= 1 << op
->nbits
;
12975 maxtiny
= (1 << op
->nbits
) - 1;
12980 mintiny
= - (1 << (op
->nbits
- 1));
12981 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12984 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12985 val
= S_GET_VALUE (fragp
->fr_symbol
);
12986 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12992 /* We won't have the section when we are called from
12993 mips_relax_frag. However, we will always have been called
12994 from md_estimate_size_before_relax first. If this is a
12995 branch to a different section, we mark it as such. If SEC is
12996 NULL, and the frag is not marked, then it must be a branch to
12997 the same section. */
13000 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13005 /* Must have been called from md_estimate_size_before_relax. */
13008 fragp
->fr_subtype
=
13009 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13011 /* FIXME: We should support this, and let the linker
13012 catch branches and loads that are out of range. */
13013 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13014 _("unsupported PC relative reference to different section"));
13018 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13019 /* Assume non-extended on the first relaxation pass.
13020 The address we have calculated will be bogus if this is
13021 a forward branch to another frag, as the forward frag
13022 will have fr_address == 0. */
13026 /* In this case, we know for sure that the symbol fragment is in
13027 the same section. If the relax_marker of the symbol fragment
13028 differs from the relax_marker of this fragment, we have not
13029 yet adjusted the symbol fragment fr_address. We want to add
13030 in STRETCH in order to get a better estimate of the address.
13031 This particularly matters because of the shift bits. */
13033 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13037 /* Adjust stretch for any alignment frag. Note that if have
13038 been expanding the earlier code, the symbol may be
13039 defined in what appears to be an earlier frag. FIXME:
13040 This doesn't handle the fr_subtype field, which specifies
13041 a maximum number of bytes to skip when doing an
13043 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13045 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13048 stretch
= - ((- stretch
)
13049 & ~ ((1 << (int) f
->fr_offset
) - 1));
13051 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13060 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13062 /* The base address rules are complicated. The base address of
13063 a branch is the following instruction. The base address of a
13064 PC relative load or add is the instruction itself, but if it
13065 is in a delay slot (in which case it can not be extended) use
13066 the address of the instruction whose delay slot it is in. */
13067 if (type
== 'p' || type
== 'q')
13071 /* If we are currently assuming that this frag should be
13072 extended, then, the current address is two bytes
13074 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13077 /* Ignore the low bit in the target, since it will be set
13078 for a text label. */
13079 if ((val
& 1) != 0)
13082 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13084 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13087 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13089 /* Branch offsets have an implicit 0 in the lowest bit. */
13090 if (type
== 'p' || type
== 'q')
13093 /* If any of the shifted bits are set, we must use an extended
13094 opcode. If the address depends on the size of this
13095 instruction, this can lead to a loop, so we arrange to always
13096 use an extended opcode. We only check this when we are in
13097 the main relaxation loop, when SEC is NULL. */
13098 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13100 fragp
->fr_subtype
=
13101 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13105 /* If we are about to mark a frag as extended because the value
13106 is precisely maxtiny + 1, then there is a chance of an
13107 infinite loop as in the following code:
13112 In this case when the la is extended, foo is 0x3fc bytes
13113 away, so the la can be shrunk, but then foo is 0x400 away, so
13114 the la must be extended. To avoid this loop, we mark the
13115 frag as extended if it was small, and is about to become
13116 extended with a value of maxtiny + 1. */
13117 if (val
== ((maxtiny
+ 1) << op
->shift
)
13118 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13121 fragp
->fr_subtype
=
13122 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13126 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13127 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13129 if ((val
& ((1 << op
->shift
) - 1)) != 0
13130 || val
< (mintiny
<< op
->shift
)
13131 || val
> (maxtiny
<< op
->shift
))
13137 /* Compute the length of a branch sequence, and adjust the
13138 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13139 worst-case length is computed, with UPDATE being used to indicate
13140 whether an unconditional (-1), branch-likely (+1) or regular (0)
13141 branch is to be computed. */
13143 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13145 bfd_boolean toofar
;
13149 && S_IS_DEFINED (fragp
->fr_symbol
)
13150 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13155 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13157 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13161 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13164 /* If the symbol is not defined or it's in a different segment,
13165 assume the user knows what's going on and emit a short
13171 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13173 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13174 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13175 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13181 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13184 if (mips_pic
!= NO_PIC
)
13186 /* Additional space for PIC loading of target address. */
13188 if (mips_opts
.isa
== ISA_MIPS1
)
13189 /* Additional space for $at-stabilizing nop. */
13193 /* If branch is conditional. */
13194 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13201 /* Estimate the size of a frag before relaxing. Unless this is the
13202 mips16, we are not really relaxing here, and the final size is
13203 encoded in the subtype information. For the mips16, we have to
13204 decide whether we are using an extended opcode or not. */
13207 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13211 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13214 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13216 return fragp
->fr_var
;
13219 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13220 /* We don't want to modify the EXTENDED bit here; it might get us
13221 into infinite loops. We change it only in mips_relax_frag(). */
13222 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13224 if (mips_pic
== NO_PIC
)
13225 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13226 else if (mips_pic
== SVR4_PIC
)
13227 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13228 else if (mips_pic
== VXWORKS_PIC
)
13229 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13236 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13237 return -RELAX_FIRST (fragp
->fr_subtype
);
13240 return -RELAX_SECOND (fragp
->fr_subtype
);
13243 /* This is called to see whether a reloc against a defined symbol
13244 should be converted into a reloc against a section. */
13247 mips_fix_adjustable (fixS
*fixp
)
13249 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13250 about the format of the offset in the .o file. */
13251 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13254 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13255 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13258 if (fixp
->fx_addsy
== NULL
)
13261 /* If symbol SYM is in a mergeable section, relocations of the form
13262 SYM + 0 can usually be made section-relative. The mergeable data
13263 is then identified by the section offset rather than by the symbol.
13265 However, if we're generating REL LO16 relocations, the offset is split
13266 between the LO16 and parterning high part relocation. The linker will
13267 need to recalculate the complete offset in order to correctly identify
13270 The linker has traditionally not looked for the parterning high part
13271 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13272 placed anywhere. Rather than break backwards compatibility by changing
13273 this, it seems better not to force the issue, and instead keep the
13274 original symbol. This will work with either linker behavior. */
13275 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13276 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13277 || reloc_needs_lo_p (fixp
->fx_r_type
))
13278 && HAVE_IN_PLACE_ADDENDS
13279 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13283 /* Don't adjust relocations against mips16 symbols, so that the linker
13284 can find them if it needs to set up a stub. */
13285 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13286 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13287 && fixp
->fx_subsy
== NULL
)
13294 /* Translate internal representation of relocation info to BFD target
13298 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13300 static arelent
*retval
[4];
13302 bfd_reloc_code_real_type code
;
13304 memset (retval
, 0, sizeof(retval
));
13305 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13306 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13307 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13308 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13310 if (fixp
->fx_pcrel
)
13312 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13314 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13315 Relocations want only the symbol offset. */
13316 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13317 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13319 /* A gruesome hack which is a result of the gruesome gas
13320 reloc handling. What's worse, for COFF (as opposed to
13321 ECOFF), we might need yet another copy of reloc->address.
13322 See bfd_install_relocation. */
13323 reloc
->addend
+= reloc
->address
;
13327 reloc
->addend
= fixp
->fx_addnumber
;
13329 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13330 entry to be used in the relocation's section offset. */
13331 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13333 reloc
->address
= reloc
->addend
;
13337 code
= fixp
->fx_r_type
;
13339 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13340 if (reloc
->howto
== NULL
)
13342 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13343 _("Can not represent %s relocation in this object file format"),
13344 bfd_get_reloc_code_name (code
));
13351 /* Relax a machine dependent frag. This returns the amount by which
13352 the current size of the frag should change. */
13355 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13357 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13359 offsetT old_var
= fragp
->fr_var
;
13361 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13363 return fragp
->fr_var
- old_var
;
13366 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13369 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13371 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13373 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13378 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13380 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13387 /* Convert a machine dependent frag. */
13390 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13392 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13395 unsigned long insn
;
13399 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13401 if (target_big_endian
)
13402 insn
= bfd_getb32 (buf
);
13404 insn
= bfd_getl32 (buf
);
13406 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13408 /* We generate a fixup instead of applying it right now
13409 because, if there are linker relaxations, we're going to
13410 need the relocations. */
13411 exp
.X_op
= O_symbol
;
13412 exp
.X_add_symbol
= fragp
->fr_symbol
;
13413 exp
.X_add_number
= fragp
->fr_offset
;
13415 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13416 4, &exp
, 1, BFD_RELOC_16_PCREL_S2
);
13417 fixp
->fx_file
= fragp
->fr_file
;
13418 fixp
->fx_line
= fragp
->fr_line
;
13420 md_number_to_chars ((char *) buf
, insn
, 4);
13427 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13428 _("relaxed out-of-range branch into a jump"));
13430 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13433 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13435 /* Reverse the branch. */
13436 switch ((insn
>> 28) & 0xf)
13439 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13440 have the condition reversed by tweaking a single
13441 bit, and their opcodes all have 0x4???????. */
13442 assert ((insn
& 0xf1000000) == 0x41000000);
13443 insn
^= 0x00010000;
13447 /* bltz 0x04000000 bgez 0x04010000
13448 bltzal 0x04100000 bgezal 0x04110000 */
13449 assert ((insn
& 0xfc0e0000) == 0x04000000);
13450 insn
^= 0x00010000;
13454 /* beq 0x10000000 bne 0x14000000
13455 blez 0x18000000 bgtz 0x1c000000 */
13456 insn
^= 0x04000000;
13464 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13466 /* Clear the and-link bit. */
13467 assert ((insn
& 0xfc1c0000) == 0x04100000);
13469 /* bltzal 0x04100000 bgezal 0x04110000
13470 bltzall 0x04120000 bgezall 0x04130000 */
13471 insn
&= ~0x00100000;
13474 /* Branch over the branch (if the branch was likely) or the
13475 full jump (not likely case). Compute the offset from the
13476 current instruction to branch to. */
13477 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13481 /* How many bytes in instructions we've already emitted? */
13482 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13483 /* How many bytes in instructions from here to the end? */
13484 i
= fragp
->fr_var
- i
;
13486 /* Convert to instruction count. */
13488 /* Branch counts from the next instruction. */
13491 /* Branch over the jump. */
13492 md_number_to_chars ((char *) buf
, insn
, 4);
13496 md_number_to_chars ((char *) buf
, 0, 4);
13499 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13501 /* beql $0, $0, 2f */
13503 /* Compute the PC offset from the current instruction to
13504 the end of the variable frag. */
13505 /* How many bytes in instructions we've already emitted? */
13506 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13507 /* How many bytes in instructions from here to the end? */
13508 i
= fragp
->fr_var
- i
;
13509 /* Convert to instruction count. */
13511 /* Don't decrement i, because we want to branch over the
13515 md_number_to_chars ((char *) buf
, insn
, 4);
13518 md_number_to_chars ((char *) buf
, 0, 4);
13523 if (mips_pic
== NO_PIC
)
13526 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13527 ? 0x0c000000 : 0x08000000);
13528 exp
.X_op
= O_symbol
;
13529 exp
.X_add_symbol
= fragp
->fr_symbol
;
13530 exp
.X_add_number
= fragp
->fr_offset
;
13532 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13533 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13534 fixp
->fx_file
= fragp
->fr_file
;
13535 fixp
->fx_line
= fragp
->fr_line
;
13537 md_number_to_chars ((char *) buf
, insn
, 4);
13542 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13543 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13544 exp
.X_op
= O_symbol
;
13545 exp
.X_add_symbol
= fragp
->fr_symbol
;
13546 exp
.X_add_number
= fragp
->fr_offset
;
13548 if (fragp
->fr_offset
)
13550 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13551 exp
.X_add_number
= 0;
13554 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13555 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13556 fixp
->fx_file
= fragp
->fr_file
;
13557 fixp
->fx_line
= fragp
->fr_line
;
13559 md_number_to_chars ((char *) buf
, insn
, 4);
13562 if (mips_opts
.isa
== ISA_MIPS1
)
13565 md_number_to_chars ((char *) buf
, 0, 4);
13569 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13570 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13572 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13573 4, &exp
, 0, BFD_RELOC_LO16
);
13574 fixp
->fx_file
= fragp
->fr_file
;
13575 fixp
->fx_line
= fragp
->fr_line
;
13577 md_number_to_chars ((char *) buf
, insn
, 4);
13581 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13586 md_number_to_chars ((char *) buf
, insn
, 4);
13591 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13592 + fragp
->fr_fix
+ fragp
->fr_var
);
13594 fragp
->fr_fix
+= fragp
->fr_var
;
13599 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13602 register const struct mips16_immed_operand
*op
;
13603 bfd_boolean small
, ext
;
13606 unsigned long insn
;
13607 bfd_boolean use_extend
;
13608 unsigned short extend
;
13610 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13611 op
= mips16_immed_operands
;
13612 while (op
->type
!= type
)
13615 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13626 resolve_symbol_value (fragp
->fr_symbol
);
13627 val
= S_GET_VALUE (fragp
->fr_symbol
);
13632 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13634 /* The rules for the base address of a PC relative reloc are
13635 complicated; see mips16_extended_frag. */
13636 if (type
== 'p' || type
== 'q')
13641 /* Ignore the low bit in the target, since it will be
13642 set for a text label. */
13643 if ((val
& 1) != 0)
13646 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13648 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13651 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13654 /* Make sure the section winds up with the alignment we have
13657 record_alignment (asec
, op
->shift
);
13661 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13662 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13663 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13664 _("extended instruction in delay slot"));
13666 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13668 if (target_big_endian
)
13669 insn
= bfd_getb16 (buf
);
13671 insn
= bfd_getl16 (buf
);
13673 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13674 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13675 small
, ext
, &insn
, &use_extend
, &extend
);
13679 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13680 fragp
->fr_fix
+= 2;
13684 md_number_to_chars ((char *) buf
, insn
, 2);
13685 fragp
->fr_fix
+= 2;
13693 first
= RELAX_FIRST (fragp
->fr_subtype
);
13694 second
= RELAX_SECOND (fragp
->fr_subtype
);
13695 fixp
= (fixS
*) fragp
->fr_opcode
;
13697 /* Possibly emit a warning if we've chosen the longer option. */
13698 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13699 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13701 const char *msg
= macro_warning (fragp
->fr_subtype
);
13703 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13706 /* Go through all the fixups for the first sequence. Disable them
13707 (by marking them as done) if we're going to use the second
13708 sequence instead. */
13710 && fixp
->fx_frag
== fragp
13711 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13713 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13715 fixp
= fixp
->fx_next
;
13718 /* Go through the fixups for the second sequence. Disable them if
13719 we're going to use the first sequence, otherwise adjust their
13720 addresses to account for the relaxation. */
13721 while (fixp
&& fixp
->fx_frag
== fragp
)
13723 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13724 fixp
->fx_where
-= first
;
13727 fixp
= fixp
->fx_next
;
13730 /* Now modify the frag contents. */
13731 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13735 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13736 memmove (start
, start
+ first
, second
);
13737 fragp
->fr_fix
-= first
;
13740 fragp
->fr_fix
-= second
;
13746 /* This function is called after the relocs have been generated.
13747 We've been storing mips16 text labels as odd. Here we convert them
13748 back to even for the convenience of the debugger. */
13751 mips_frob_file_after_relocs (void)
13754 unsigned int count
, i
;
13756 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13759 syms
= bfd_get_outsymbols (stdoutput
);
13760 count
= bfd_get_symcount (stdoutput
);
13761 for (i
= 0; i
< count
; i
++, syms
++)
13763 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13764 && ((*syms
)->value
& 1) != 0)
13766 (*syms
)->value
&= ~1;
13767 /* If the symbol has an odd size, it was probably computed
13768 incorrectly, so adjust that as well. */
13769 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13770 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13777 /* This function is called whenever a label is defined. It is used
13778 when handling branch delays; if a branch has a label, we assume we
13779 can not move it. */
13782 mips_define_label (symbolS
*sym
)
13784 struct insn_label_list
*l
;
13786 if (free_insn_labels
== NULL
)
13787 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13790 l
= free_insn_labels
;
13791 free_insn_labels
= l
->next
;
13795 l
->next
= insn_labels
;
13799 dwarf2_emit_label (sym
);
13803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13805 /* Some special processing for a MIPS ELF file. */
13808 mips_elf_final_processing (void)
13810 /* Write out the register information. */
13811 if (mips_abi
!= N64_ABI
)
13815 s
.ri_gprmask
= mips_gprmask
;
13816 s
.ri_cprmask
[0] = mips_cprmask
[0];
13817 s
.ri_cprmask
[1] = mips_cprmask
[1];
13818 s
.ri_cprmask
[2] = mips_cprmask
[2];
13819 s
.ri_cprmask
[3] = mips_cprmask
[3];
13820 /* The gp_value field is set by the MIPS ELF backend. */
13822 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13823 ((Elf32_External_RegInfo
*)
13824 mips_regmask_frag
));
13828 Elf64_Internal_RegInfo s
;
13830 s
.ri_gprmask
= mips_gprmask
;
13832 s
.ri_cprmask
[0] = mips_cprmask
[0];
13833 s
.ri_cprmask
[1] = mips_cprmask
[1];
13834 s
.ri_cprmask
[2] = mips_cprmask
[2];
13835 s
.ri_cprmask
[3] = mips_cprmask
[3];
13836 /* The gp_value field is set by the MIPS ELF backend. */
13838 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13839 ((Elf64_External_RegInfo
*)
13840 mips_regmask_frag
));
13843 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13844 sort of BFD interface for this. */
13845 if (mips_any_noreorder
)
13846 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13847 if (mips_pic
!= NO_PIC
)
13849 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13850 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13853 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13855 /* Set MIPS ELF flags for ASEs. */
13856 /* We may need to define a new flag for DSP ASE, and set this flag when
13857 file_ase_dsp is true. */
13858 /* We may need to define a new flag for MT ASE, and set this flag when
13859 file_ase_mt is true. */
13860 if (file_ase_mips16
)
13861 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13862 #if 0 /* XXX FIXME */
13863 if (file_ase_mips3d
)
13864 elf_elfheader (stdoutput
)->e_flags
|= ???;
13867 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13869 /* Set the MIPS ELF ABI flags. */
13870 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13871 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13872 else if (mips_abi
== O64_ABI
)
13873 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13874 else if (mips_abi
== EABI_ABI
)
13876 if (!file_mips_gp32
)
13877 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13879 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13881 else if (mips_abi
== N32_ABI
)
13882 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13884 /* Nothing to do for N64_ABI. */
13886 if (mips_32bitmode
)
13887 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13890 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13892 typedef struct proc
{
13894 symbolS
*func_end_sym
;
13895 unsigned long reg_mask
;
13896 unsigned long reg_offset
;
13897 unsigned long fpreg_mask
;
13898 unsigned long fpreg_offset
;
13899 unsigned long frame_offset
;
13900 unsigned long frame_reg
;
13901 unsigned long pc_reg
;
13904 static procS cur_proc
;
13905 static procS
*cur_proc_ptr
;
13906 static int numprocs
;
13908 /* Fill in an rs_align_code fragment. */
13911 mips_handle_align (fragS
*fragp
)
13913 if (fragp
->fr_type
!= rs_align_code
)
13916 if (mips_opts
.mips16
)
13918 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13919 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13924 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13925 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13933 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13937 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13941 md_obj_begin (void)
13948 /* check for premature end, nesting errors, etc */
13950 as_warn (_("missing .end at end of assembly"));
13959 if (*input_line_pointer
== '-')
13961 ++input_line_pointer
;
13964 if (!ISDIGIT (*input_line_pointer
))
13965 as_bad (_("expected simple number"));
13966 if (input_line_pointer
[0] == '0')
13968 if (input_line_pointer
[1] == 'x')
13970 input_line_pointer
+= 2;
13971 while (ISXDIGIT (*input_line_pointer
))
13974 val
|= hex_value (*input_line_pointer
++);
13976 return negative
? -val
: val
;
13980 ++input_line_pointer
;
13981 while (ISDIGIT (*input_line_pointer
))
13984 val
|= *input_line_pointer
++ - '0';
13986 return negative
? -val
: val
;
13989 if (!ISDIGIT (*input_line_pointer
))
13991 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13992 *input_line_pointer
, *input_line_pointer
);
13993 as_warn (_("invalid number"));
13996 while (ISDIGIT (*input_line_pointer
))
13999 val
+= *input_line_pointer
++ - '0';
14001 return negative
? -val
: val
;
14004 /* The .file directive; just like the usual .file directive, but there
14005 is an initial number which is the ECOFF file index. In the non-ECOFF
14006 case .file implies DWARF-2. */
14009 s_mips_file (int x ATTRIBUTE_UNUSED
)
14011 static int first_file_directive
= 0;
14013 if (ECOFF_DEBUGGING
)
14022 filename
= dwarf2_directive_file (0);
14024 /* Versions of GCC up to 3.1 start files with a ".file"
14025 directive even for stabs output. Make sure that this
14026 ".file" is handled. Note that you need a version of GCC
14027 after 3.1 in order to support DWARF-2 on MIPS. */
14028 if (filename
!= NULL
&& ! first_file_directive
)
14030 (void) new_logical_line (filename
, -1);
14031 s_app_file_string (filename
, 0);
14033 first_file_directive
= 1;
14037 /* The .loc directive, implying DWARF-2. */
14040 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14042 if (!ECOFF_DEBUGGING
)
14043 dwarf2_directive_loc (0);
14046 /* The .end directive. */
14049 s_mips_end (int x ATTRIBUTE_UNUSED
)
14053 /* Following functions need their own .frame and .cprestore directives. */
14054 mips_frame_reg_valid
= 0;
14055 mips_cprestore_valid
= 0;
14057 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14060 demand_empty_rest_of_line ();
14065 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14066 as_warn (_(".end not in text section"));
14070 as_warn (_(".end directive without a preceding .ent directive."));
14071 demand_empty_rest_of_line ();
14077 assert (S_GET_NAME (p
));
14078 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14079 as_warn (_(".end symbol does not match .ent symbol."));
14081 if (debug_type
== DEBUG_STABS
)
14082 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14086 as_warn (_(".end directive missing or unknown symbol"));
14089 /* Create an expression to calculate the size of the function. */
14090 if (p
&& cur_proc_ptr
)
14092 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14093 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14096 exp
->X_op
= O_subtract
;
14097 exp
->X_add_symbol
= symbol_temp_new_now ();
14098 exp
->X_op_symbol
= p
;
14099 exp
->X_add_number
= 0;
14101 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14104 /* Generate a .pdr section. */
14105 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14108 segT saved_seg
= now_seg
;
14109 subsegT saved_subseg
= now_subseg
;
14114 dot
= frag_now_fix ();
14116 #ifdef md_flush_pending_output
14117 md_flush_pending_output ();
14121 subseg_set (pdr_seg
, 0);
14123 /* Write the symbol. */
14124 exp
.X_op
= O_symbol
;
14125 exp
.X_add_symbol
= p
;
14126 exp
.X_add_number
= 0;
14127 emit_expr (&exp
, 4);
14129 fragp
= frag_more (7 * 4);
14131 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14132 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14133 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14134 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14135 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14136 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14137 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14139 subseg_set (saved_seg
, saved_subseg
);
14141 #endif /* OBJ_ELF */
14143 cur_proc_ptr
= NULL
;
14146 /* The .aent and .ent directives. */
14149 s_mips_ent (int aent
)
14153 symbolP
= get_symbol ();
14154 if (*input_line_pointer
== ',')
14155 ++input_line_pointer
;
14156 SKIP_WHITESPACE ();
14157 if (ISDIGIT (*input_line_pointer
)
14158 || *input_line_pointer
== '-')
14161 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14162 as_warn (_(".ent or .aent not in text section."));
14164 if (!aent
&& cur_proc_ptr
)
14165 as_warn (_("missing .end"));
14169 /* This function needs its own .frame and .cprestore directives. */
14170 mips_frame_reg_valid
= 0;
14171 mips_cprestore_valid
= 0;
14173 cur_proc_ptr
= &cur_proc
;
14174 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14176 cur_proc_ptr
->func_sym
= symbolP
;
14178 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14182 if (debug_type
== DEBUG_STABS
)
14183 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14184 S_GET_NAME (symbolP
));
14187 demand_empty_rest_of_line ();
14190 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14191 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14192 s_mips_frame is used so that we can set the PDR information correctly.
14193 We can't use the ecoff routines because they make reference to the ecoff
14194 symbol table (in the mdebug section). */
14197 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14200 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14204 if (cur_proc_ptr
== (procS
*) NULL
)
14206 as_warn (_(".frame outside of .ent"));
14207 demand_empty_rest_of_line ();
14211 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14213 SKIP_WHITESPACE ();
14214 if (*input_line_pointer
++ != ','
14215 || get_absolute_expression_and_terminator (&val
) != ',')
14217 as_warn (_("Bad .frame directive"));
14218 --input_line_pointer
;
14219 demand_empty_rest_of_line ();
14223 cur_proc_ptr
->frame_offset
= val
;
14224 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14226 demand_empty_rest_of_line ();
14229 #endif /* OBJ_ELF */
14233 /* The .fmask and .mask directives. If the mdebug section is present
14234 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14235 embedded targets, s_mips_mask is used so that we can set the PDR
14236 information correctly. We can't use the ecoff routines because they
14237 make reference to the ecoff symbol table (in the mdebug section). */
14240 s_mips_mask (int reg_type
)
14243 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14247 if (cur_proc_ptr
== (procS
*) NULL
)
14249 as_warn (_(".mask/.fmask outside of .ent"));
14250 demand_empty_rest_of_line ();
14254 if (get_absolute_expression_and_terminator (&mask
) != ',')
14256 as_warn (_("Bad .mask/.fmask directive"));
14257 --input_line_pointer
;
14258 demand_empty_rest_of_line ();
14262 off
= get_absolute_expression ();
14264 if (reg_type
== 'F')
14266 cur_proc_ptr
->fpreg_mask
= mask
;
14267 cur_proc_ptr
->fpreg_offset
= off
;
14271 cur_proc_ptr
->reg_mask
= mask
;
14272 cur_proc_ptr
->reg_offset
= off
;
14275 demand_empty_rest_of_line ();
14278 #endif /* OBJ_ELF */
14279 s_ignore (reg_type
);
14282 /* A table describing all the processors gas knows about. Names are
14283 matched in the order listed.
14285 To ease comparison, please keep this table in the same order as
14286 gcc's mips_cpu_info_table[]. */
14287 static const struct mips_cpu_info mips_cpu_info_table
[] =
14289 /* Entries for generic ISAs */
14290 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14291 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14292 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14293 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14294 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14295 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14296 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14297 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14298 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14301 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14302 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14303 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14306 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14309 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14310 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14311 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14312 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14313 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14314 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14315 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14316 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14317 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14318 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14319 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14320 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14323 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14324 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14325 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14326 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14327 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14328 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14329 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14330 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14331 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14332 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14333 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14334 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14335 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14338 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14339 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14340 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14342 /* MIPS32 Release 2 */
14343 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14344 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14345 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14346 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14347 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14350 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14351 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14352 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14354 /* Broadcom SB-1 CPU core */
14355 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14362 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14363 with a final "000" replaced by "k". Ignore case.
14365 Note: this function is shared between GCC and GAS. */
14368 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14370 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14371 given
++, canonical
++;
14373 return ((*given
== 0 && *canonical
== 0)
14374 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14378 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14379 CPU name. We've traditionally allowed a lot of variation here.
14381 Note: this function is shared between GCC and GAS. */
14384 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14386 /* First see if the name matches exactly, or with a final "000"
14387 turned into "k". */
14388 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14391 /* If not, try comparing based on numerical designation alone.
14392 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14393 if (TOLOWER (*given
) == 'r')
14395 if (!ISDIGIT (*given
))
14398 /* Skip over some well-known prefixes in the canonical name,
14399 hoping to find a number there too. */
14400 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14402 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14404 else if (TOLOWER (canonical
[0]) == 'r')
14407 return mips_strict_matching_cpu_name_p (canonical
, given
);
14411 /* Parse an option that takes the name of a processor as its argument.
14412 OPTION is the name of the option and CPU_STRING is the argument.
14413 Return the corresponding processor enumeration if the CPU_STRING is
14414 recognized, otherwise report an error and return null.
14416 A similar function exists in GCC. */
14418 static const struct mips_cpu_info
*
14419 mips_parse_cpu (const char *option
, const char *cpu_string
)
14421 const struct mips_cpu_info
*p
;
14423 /* 'from-abi' selects the most compatible architecture for the given
14424 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14425 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14426 version. Look first at the -mgp options, if given, otherwise base
14427 the choice on MIPS_DEFAULT_64BIT.
14429 Treat NO_ABI like the EABIs. One reason to do this is that the
14430 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14431 architecture. This code picks MIPS I for 'mips' and MIPS III for
14432 'mips64', just as we did in the days before 'from-abi'. */
14433 if (strcasecmp (cpu_string
, "from-abi") == 0)
14435 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14436 return mips_cpu_info_from_isa (ISA_MIPS1
);
14438 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14439 return mips_cpu_info_from_isa (ISA_MIPS3
);
14441 if (file_mips_gp32
>= 0)
14442 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14444 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14449 /* 'default' has traditionally been a no-op. Probably not very useful. */
14450 if (strcasecmp (cpu_string
, "default") == 0)
14453 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14454 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14457 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14461 /* Return the canonical processor information for ISA (a member of the
14462 ISA_MIPS* enumeration). */
14464 static const struct mips_cpu_info
*
14465 mips_cpu_info_from_isa (int isa
)
14469 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14470 if (mips_cpu_info_table
[i
].is_isa
14471 && isa
== mips_cpu_info_table
[i
].isa
)
14472 return (&mips_cpu_info_table
[i
]);
14477 static const struct mips_cpu_info
*
14478 mips_cpu_info_from_arch (int arch
)
14482 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14483 if (arch
== mips_cpu_info_table
[i
].cpu
)
14484 return (&mips_cpu_info_table
[i
]);
14490 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14494 fprintf (stream
, "%24s", "");
14499 fprintf (stream
, ", ");
14503 if (*col_p
+ strlen (string
) > 72)
14505 fprintf (stream
, "\n%24s", "");
14509 fprintf (stream
, "%s", string
);
14510 *col_p
+= strlen (string
);
14516 md_show_usage (FILE *stream
)
14521 fprintf (stream
, _("\
14523 -EB generate big endian output\n\
14524 -EL generate little endian output\n\
14525 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14526 -G NUM allow referencing objects up to NUM bytes\n\
14527 implicitly with the gp register [default 8]\n"));
14528 fprintf (stream
, _("\
14529 -mips1 generate MIPS ISA I instructions\n\
14530 -mips2 generate MIPS ISA II instructions\n\
14531 -mips3 generate MIPS ISA III instructions\n\
14532 -mips4 generate MIPS ISA IV instructions\n\
14533 -mips5 generate MIPS ISA V instructions\n\
14534 -mips32 generate MIPS32 ISA instructions\n\
14535 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14536 -mips64 generate MIPS64 ISA instructions\n\
14537 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14538 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14542 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14543 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14544 show (stream
, "from-abi", &column
, &first
);
14545 fputc ('\n', stream
);
14547 fprintf (stream
, _("\
14548 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14549 -no-mCPU don't generate code specific to CPU.\n\
14550 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14554 show (stream
, "3900", &column
, &first
);
14555 show (stream
, "4010", &column
, &first
);
14556 show (stream
, "4100", &column
, &first
);
14557 show (stream
, "4650", &column
, &first
);
14558 fputc ('\n', stream
);
14560 fprintf (stream
, _("\
14561 -mips16 generate mips16 instructions\n\
14562 -no-mips16 do not generate mips16 instructions\n"));
14563 fprintf (stream
, _("\
14564 -mdsp generate DSP instructions\n\
14565 -mno-dsp do not generate DSP instructions\n"));
14566 fprintf (stream
, _("\
14567 -mmt generate MT instructions\n\
14568 -mno-mt do not generate MT instructions\n"));
14569 fprintf (stream
, _("\
14570 -mfix-vr4120 work around certain VR4120 errata\n\
14571 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14572 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14573 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14574 -mno-shared optimize output for executables\n\
14575 -msym32 assume all symbols have 32-bit values\n\
14576 -O0 remove unneeded NOPs, do not swap branches\n\
14577 -O remove unneeded NOPs and swap branches\n\
14578 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14579 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14580 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14582 fprintf (stream
, _("\
14583 -KPIC, -call_shared generate SVR4 position independent code\n\
14584 -non_shared do not generate position independent code\n\
14585 -xgot assume a 32 bit GOT\n\
14586 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14587 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14589 -mabi=ABI create ABI conformant object file for:\n"));
14593 show (stream
, "32", &column
, &first
);
14594 show (stream
, "o64", &column
, &first
);
14595 show (stream
, "n32", &column
, &first
);
14596 show (stream
, "64", &column
, &first
);
14597 show (stream
, "eabi", &column
, &first
);
14599 fputc ('\n', stream
);
14601 fprintf (stream
, _("\
14602 -32 create o32 ABI object file (default)\n\
14603 -n32 create n32 ABI object file\n\
14604 -64 create 64 ABI object file\n"));
14609 mips_dwarf2_format (void)
14611 if (mips_abi
== N64_ABI
)
14614 return dwarf2_format_64bit_irix
;
14616 return dwarf2_format_64bit
;
14620 return dwarf2_format_32bit
;
14624 mips_dwarf2_addr_size (void)
14626 if (mips_abi
== N64_ABI
)
14632 /* Standard calling conventions leave the CFA at SP on entry. */
14634 mips_cfi_frame_initial_instructions (void)
14636 cfi_add_CFA_def_cfa_register (SP
);